[mirror_ubuntu-artful-kernel.git] / drivers / net / fs_enet / fs_enet.h

#ifndef FS_ENET_H
#define FS_ENET_H

#include <linux/mii.h>
#include <linux/netdevice.h>
#include <linux/types.h>
#include <linux/list.h>
#include <linux/phy.h>
#include <linux/dma-mapping.h>

#include <linux/fs_enet_pd.h>
#include <asm/fs_pd.h>

#ifdef CONFIG_CPM1
#include <asm/cpm1.h>
#endif

#if defined(CONFIG_FS_ENET_HAS_FEC)
#include <asm/cpm.h>

#if defined(CONFIG_FS_ENET_MPC5121_FEC)
/* MPC5121 FEC has different register layout */
struct fec {
	u32 fec_reserved0;
	u32 fec_ievent;			/* Interrupt event reg */
	u32 fec_imask;			/* Interrupt mask reg */
	u32 fec_reserved1;
	u32 fec_r_des_active;		/* Receive descriptor reg */
	u32 fec_x_des_active;		/* Transmit descriptor reg */
	u32 fec_reserved2[3];
	u32 fec_ecntrl;			/* Ethernet control reg */
	u32 fec_reserved3[6];
	u32 fec_mii_data;		/* MII manage frame reg */
	u32 fec_mii_speed;		/* MII speed control reg */
	u32 fec_reserved4[7];
	u32 fec_mib_ctrlstat;		/* MIB control/status reg */
	u32 fec_reserved5[7];
	u32 fec_r_cntrl;		/* Receive control reg */
	u32 fec_reserved6[15];
	u32 fec_x_cntrl;		/* Transmit Control reg */
	u32 fec_reserved7[7];
	u32 fec_addr_low;		/* Low 32bits MAC address */
	u32 fec_addr_high;		/* High 16bits MAC address */
	u32 fec_opd;			/* Opcode + Pause duration */
	u32 fec_reserved8[10];
	u32 fec_hash_table_high;	/* High 32bits hash table */
	u32 fec_hash_table_low;		/* Low 32bits hash table */
	u32 fec_grp_hash_table_high;	/* High 32bits hash table */
	u32 fec_grp_hash_table_low;	/* Low 32bits hash table */
	u32 fec_reserved9[7];
	u32 fec_x_wmrk;			/* FIFO transmit water mark */
	u32 fec_reserved10;
	u32 fec_r_bound;		/* FIFO receive bound reg */
	u32 fec_r_fstart;		/* FIFO receive start reg */
	u32 fec_reserved11[11];
	u32 fec_r_des_start;		/* Receive descriptor ring */
	u32 fec_x_des_start;		/* Transmit descriptor ring */
	u32 fec_r_buff_size;		/* Maximum receive buff size */
	u32 fec_reserved12[26];
	u32 fec_dma_control;		/* DMA Endian and other ctrl */
};
#endif

struct fec_info {
	struct fec __iomem *fecp;
	u32 mii_speed;
};
#endif

#ifdef CONFIG_CPM2
#include <asm/cpm2.h>
#endif

/* hw driver ops */
struct fs_ops {
	int (*setup_data)(struct net_device *dev);
	int (*allocate_bd)(struct net_device *dev);
	void (*free_bd)(struct net_device *dev);
	void (*cleanup_data)(struct net_device *dev);
	void (*set_multicast_list)(struct net_device *dev);
	void (*adjust_link)(struct net_device *dev);
	void (*restart)(struct net_device *dev);
	void (*stop)(struct net_device *dev);
	void (*napi_clear_rx_event)(struct net_device *dev);
	void (*napi_enable_rx)(struct net_device *dev);
	void (*napi_disable_rx)(struct net_device *dev);
	void (*rx_bd_done)(struct net_device *dev);
	void (*tx_kickstart)(struct net_device *dev);
	u32 (*get_int_events)(struct net_device *dev);
	void (*clear_int_events)(struct net_device *dev, u32 int_events);
	void (*ev_error)(struct net_device *dev, u32 int_events);
	int (*get_regs)(struct net_device *dev, void *p, int *sizep);
	int (*get_regs_len)(struct net_device *dev);
	void (*tx_restart)(struct net_device *dev);
};

struct phy_info {
	unsigned int id;
	const char *name;
	void (*startup) (struct net_device * dev);
	void (*shutdown) (struct net_device * dev);
	void (*ack_int) (struct net_device * dev);
};

/* The FEC stores dest/src/type, data, and checksum for receive packets.
 */
#define MAX_MTU 1508		/* Allow fullsized pppoe packets over VLAN */
#define MIN_MTU 46		/* this is data size */
#define CRC_LEN 4

#define PKT_MAXBUF_SIZE		(MAX_MTU+ETH_HLEN+CRC_LEN)
#define PKT_MINBUF_SIZE		(MIN_MTU+ETH_HLEN+CRC_LEN)

/* Must be a multiple of 32 (to cover both FEC & FCC) */
#define PKT_MAXBLR_SIZE		((PKT_MAXBUF_SIZE + 31) & ~31)
/* This is needed so that invalidate_xxx wont invalidate too much */
#define ENET_RX_ALIGN  16
#define ENET_RX_FRSIZE L1_CACHE_ALIGN(PKT_MAXBUF_SIZE + ENET_RX_ALIGN - 1)

struct fs_enet_private {
	struct napi_struct napi;
	struct device *dev;	/* pointer back to the device (must be initialized first) */
	struct net_device *ndev;
	spinlock_t lock;	/* during all ops except TX pckt processing */
	spinlock_t tx_lock;	/* during fs_start_xmit and fs_tx         */
	struct fs_platform_info *fpi;
	const struct fs_ops *ops;
	int rx_ring, tx_ring;
	dma_addr_t ring_mem_addr;
	void __iomem *ring_base;
	struct sk_buff **rx_skbuff;
	struct sk_buff **tx_skbuff;
	cbd_t __iomem *rx_bd_base;	/* Address of Rx and Tx buffers.    */
	cbd_t __iomem *tx_bd_base;
	cbd_t __iomem *dirty_tx;	/* ring entries to be free()ed.     */
	cbd_t __iomem *cur_rx;
	cbd_t __iomem *cur_tx;
	int tx_free;
	struct net_device_stats stats;
	struct timer_list phy_timer_list;
	const struct phy_info *phy;
	u32 msg_enable;
	struct mii_if_info mii_if;
	unsigned int last_mii_status;
	int interrupt;

	struct phy_device *phydev;
	int oldduplex, oldspeed, oldlink;	/* current settings */

	/* event masks */
	u32 ev_napi_rx;		/* mask of NAPI rx events */
	u32 ev_rx;		/* rx event mask          */
	u32 ev_tx;		/* tx event mask          */
	u32 ev_err;		/* error event mask       */

	u16 bd_rx_empty;	/* mask of BD rx empty	  */
	u16 bd_rx_err;		/* mask of BD rx errors   */

	union {
		struct {
			int idx;		/* FEC1 = 0, FEC2 = 1  */
			void __iomem *fecp;	/* hw registers        */
			u32 hthi, htlo;		/* state for multicast */
		} fec;

		struct {
			int idx;		/* FCC1-3 = 0-2	       */
			void __iomem *fccp;	/* hw registers	       */
			void __iomem *ep;	/* parameter ram       */
			void __iomem *fcccp;	/* hw registers cont.  */
			void __iomem *mem;	/* FCC DPRAM */
			u32 gaddrh, gaddrl;	/* group address       */
		} fcc;

		struct {
			int idx;		/* FEC1 = 0, FEC2 = 1  */
			void __iomem *sccp;	/* hw registers        */
			void __iomem *ep;	/* parameter ram       */
			u32 hthi, htlo;		/* state for multicast */
		} scc;

	};
};

/***************************************************************************/

void fs_init_bds(struct net_device *dev);
void fs_cleanup_bds(struct net_device *dev);

/***************************************************************************/

#define DRV_MODULE_NAME		"fs_enet"
#define PFX DRV_MODULE_NAME	": "
#define DRV_MODULE_VERSION	"1.0"
#define DRV_MODULE_RELDATE	"Aug 8, 2005"

/***************************************************************************/

int fs_enet_platform_init(void);
void fs_enet_platform_cleanup(void);

/***************************************************************************/
/* buffer descriptor access macros */

/* access macros */
#if defined(CONFIG_CPM1)
/* for a a CPM1 __raw_xxx's are sufficient */
#define __cbd_out32(addr, x)	__raw_writel(x, addr)
#define __cbd_out16(addr, x)	__raw_writew(x, addr)
#define __cbd_in32(addr)	__raw_readl(addr)
#define __cbd_in16(addr)	__raw_readw(addr)
#else
/* for others play it safe */
#define __cbd_out32(addr, x)	out_be32(addr, x)
#define __cbd_out16(addr, x)	out_be16(addr, x)
#define __cbd_in32(addr)	in_be32(addr)
#define __cbd_in16(addr)	in_be16(addr)
#endif

/* write */
#define CBDW_SC(_cbd, _sc) 		__cbd_out16(&(_cbd)->cbd_sc, (_sc))
#define CBDW_DATLEN(_cbd, _datlen)	__cbd_out16(&(_cbd)->cbd_datlen, (_datlen))
#define CBDW_BUFADDR(_cbd, _bufaddr)	__cbd_out32(&(_cbd)->cbd_bufaddr, (_bufaddr))

/* read */
#define CBDR_SC(_cbd) 			__cbd_in16(&(_cbd)->cbd_sc)
#define CBDR_DATLEN(_cbd)		__cbd_in16(&(_cbd)->cbd_datlen)
#define CBDR_BUFADDR(_cbd)		__cbd_in32(&(_cbd)->cbd_bufaddr)

/* set bits */
#define CBDS_SC(_cbd, _sc) 		CBDW_SC(_cbd, CBDR_SC(_cbd) | (_sc))

/* clear bits */
#define CBDC_SC(_cbd, _sc) 		CBDW_SC(_cbd, CBDR_SC(_cbd) & ~(_sc))

/*******************************************************************/

extern const struct fs_ops fs_fec_ops;
extern const struct fs_ops fs_fcc_ops;
extern const struct fs_ops fs_scc_ops;

/*******************************************************************/

#endif
Commit	Line	Data
48257c4f PA	1	#ifndef FS_ENET_H
	2	#define FS_ENET_H
	3
	4	#include <linux/mii.h>
	5	#include <linux/netdevice.h>
	6	#include <linux/types.h>
48257c4f	7	#include <linux/list.h>
5b4b8454	8	#include <linux/phy.h>
d6bd3a39	9	#include <linux/dma-mapping.h>
48257c4f PA	10
48257c4f PA	11	#include <linux/fs_enet_pd.h>
5427828e	12	#include <asm/fs_pd.h>
48257c4f	13
48257c4f	14	#ifdef CONFIG_CPM1
b5677d84	15	#include <asm/cpm1.h>
60ab4361 AG	16	#endif
	17
	18	#if defined(CONFIG_FS_ENET_HAS_FEC)
	19	#include <asm/cpm.h>
	20
	21	#if defined(CONFIG_FS_ENET_MPC5121_FEC)
	22	/* MPC5121 FEC has different register layout */
	23	struct fec {
	24	u32 fec_reserved0;
	25	u32 fec_ievent; /* Interrupt event reg */
	26	u32 fec_imask; /* Interrupt mask reg */
	27	u32 fec_reserved1;
	28	u32 fec_r_des_active; /* Receive descriptor reg */
	29	u32 fec_x_des_active; /* Transmit descriptor reg */
	30	u32 fec_reserved2[3];
	31	u32 fec_ecntrl; /* Ethernet control reg */
	32	u32 fec_reserved3[6];
	33	u32 fec_mii_data; /* MII manage frame reg */
	34	u32 fec_mii_speed; /* MII speed control reg */
	35	u32 fec_reserved4[7];
	36	u32 fec_mib_ctrlstat; /* MIB control/status reg */
	37	u32 fec_reserved5[7];
	38	u32 fec_r_cntrl; /* Receive control reg */
	39	u32 fec_reserved6[15];
	40	u32 fec_x_cntrl; /* Transmit Control reg */
	41	u32 fec_reserved7[7];
	42	u32 fec_addr_low; /* Low 32bits MAC address */
	43	u32 fec_addr_high; /* High 16bits MAC address */
	44	u32 fec_opd; /* Opcode + Pause duration */
	45	u32 fec_reserved8[10];
	46	u32 fec_hash_table_high; /* High 32bits hash table */
	47	u32 fec_hash_table_low; /* Low 32bits hash table */
	48	u32 fec_grp_hash_table_high; /* High 32bits hash table */
	49	u32 fec_grp_hash_table_low; /* Low 32bits hash table */
	50	u32 fec_reserved9[7];
	51	u32 fec_x_wmrk; /* FIFO transmit water mark */
	52	u32 fec_reserved10;
	53	u32 fec_r_bound; /* FIFO receive bound reg */
	54	u32 fec_r_fstart; /* FIFO receive start reg */
	55	u32 fec_reserved11[11];
	56	u32 fec_r_des_start; /* Receive descriptor ring */
	57	u32 fec_x_des_start; /* Transmit descriptor ring */
	58	u32 fec_r_buff_size; /* Maximum receive buff size */
	59	u32 fec_reserved12[26];
	60	u32 fec_dma_control; /* DMA Endian and other ctrl */
	61	};
	62	#endif
5b4b8454 VB	63
5b4b8454 VB	64	struct fec_info {
60ab4361	65	struct fec __iomem *fecp;
0fb300fa	66	u32 mii_speed;
5b4b8454	67	};
48257c4f PA	68	#endif
	69
	70	#ifdef CONFIG_CPM2
	71	#include <asm/cpm2.h>
	72	#endif
	73
	74	/* hw driver ops */
	75	struct fs_ops {
	76	int (setup_data)(struct net_device dev);
	77	int (allocate_bd)(struct net_device dev);
	78	void (free_bd)(struct net_device dev);
	79	void (cleanup_data)(struct net_device dev);
	80	void (set_multicast_list)(struct net_device dev);
5b4b8454	81	void (adjust_link)(struct net_device dev);
48257c4f PA	82	void (restart)(struct net_device dev);
48257c4f PA	83	void (stop)(struct net_device dev);
48257c4f PA	84	void (napi_clear_rx_event)(struct net_device dev);
	85	void (napi_enable_rx)(struct net_device dev);
	86	void (napi_disable_rx)(struct net_device dev);
	87	void (rx_bd_done)(struct net_device dev);
	88	void (tx_kickstart)(struct net_device dev);
	89	u32 (get_int_events)(struct net_device dev);
	90	void (clear_int_events)(struct net_device dev, u32 int_events);
	91	void (ev_error)(struct net_device dev, u32 int_events);
	92	int (get_regs)(struct net_device dev, void p, int sizep);
	93	int (get_regs_len)(struct net_device dev);
	94	void (tx_restart)(struct net_device dev);
	95	};
	96
	97	struct phy_info {
	98	unsigned int id;
	99	const char *name;
	100	void (startup) (struct net_device dev);
	101	void (shutdown) (struct net_device dev);
	102	void (ack_int) (struct net_device dev);
	103	};
	104
	105	/* The FEC stores dest/src/type, data, and checksum for receive packets.
	106	*/
	107	#define MAX_MTU 1508 /* Allow fullsized pppoe packets over VLAN */
	108	#define MIN_MTU 46 /* this is data size */
	109	#define CRC_LEN 4
	110
	111	#define PKT_MAXBUF_SIZE (MAX_MTU+ETH_HLEN+CRC_LEN)
	112	#define PKT_MINBUF_SIZE (MIN_MTU+ETH_HLEN+CRC_LEN)
	113
	114	/* Must be a multiple of 32 (to cover both FEC & FCC) */
	115	#define PKT_MAXBLR_SIZE ((PKT_MAXBUF_SIZE + 31) & ~31)
	116	/* This is needed so that invalidate_xxx wont invalidate too much */
0d0d9c15 SW	117	#define ENET_RX_ALIGN 16
0d0d9c15 SW	118	#define ENET_RX_FRSIZE L1_CACHE_ALIGN(PKT_MAXBUF_SIZE + ENET_RX_ALIGN - 1)
48257c4f	119
48257c4f	120	struct fs_enet_private {
bea3348e	121	struct napi_struct napi;
48257c4f	122	struct device dev; / pointer back to the device (must be initialized first) */
f860f49e	123	struct net_device *ndev;
48257c4f PA	124	spinlock_t lock; /* during all ops except TX pckt processing */
48257c4f PA	125	spinlock_t tx_lock; /* during fs_start_xmit and fs_tx */
976de6a8	126	struct fs_platform_info *fpi;
48257c4f PA	127	const struct fs_ops *ops;
	128	int rx_ring, tx_ring;
	129	dma_addr_t ring_mem_addr;
31a5bb04	130	void __iomem *ring_base;
48257c4f PA	131	struct sk_buff **rx_skbuff;
48257c4f PA	132	struct sk_buff **tx_skbuff;
31a5bb04 SW	133	cbd_t __iomem rx_bd_base; / Address of Rx and Tx buffers. */
	134	cbd_t __iomem *tx_bd_base;
	135	cbd_t __iomem dirty_tx; / ring entries to be free()ed. */
	136	cbd_t __iomem *cur_rx;
	137	cbd_t __iomem *cur_tx;
48257c4f PA	138	int tx_free;
	139	struct net_device_stats stats;
	140	struct timer_list phy_timer_list;
	141	const struct phy_info *phy;
	142	u32 msg_enable;
	143	struct mii_if_info mii_if;
	144	unsigned int last_mii_status;
48257c4f PA	145	int interrupt;
48257c4f PA	146
5b4b8454 VB	147	struct phy_device *phydev;
5b4b8454 VB	148	int oldduplex, oldspeed, oldlink; /* current settings */
48257c4f PA	149
	150	/* event masks */
	151	u32 ev_napi_rx; /* mask of NAPI rx events */
	152	u32 ev_rx; /* rx event mask */
	153	u32 ev_tx; /* tx event mask */
	154	u32 ev_err; /* error event mask */
	155
	156	u16 bd_rx_empty; /* mask of BD rx empty */
	157	u16 bd_rx_err; /* mask of BD rx errors */
	158
	159	union {
	160	struct {
	161	int idx; /* FEC1 = 0, FEC2 = 1 */
31a5bb04	162	void __iomem fecp; / hw registers */
48257c4f PA	163	u32 hthi, htlo; /* state for multicast */
	164	} fec;
	165
	166	struct {
	167	int idx; /* FCC1-3 = 0-2 */
31a5bb04 SW	168	void __iomem fccp; / hw registers */
	169	void __iomem ep; / parameter ram */
	170	void __iomem fcccp; / hw registers cont. */
	171	void __iomem mem; / FCC DPRAM */
48257c4f PA	172	u32 gaddrh, gaddrl; /* group address */
	173	} fcc;
	174
	175	struct {
	176	int idx; /* FEC1 = 0, FEC2 = 1 */
31a5bb04 SW	177	void __iomem sccp; / hw registers */
31a5bb04 SW	178	void __iomem ep; / parameter ram */
48257c4f PA	179	u32 hthi, htlo; /* state for multicast */
	180	} scc;
	181
	182	};
	183	};
	184
	185	/***************************************************************************/
48257c4f PA	186
	187	void fs_init_bds(struct net_device *dev);
	188	void fs_cleanup_bds(struct net_device *dev);
	189
	190	/***************************************************************************/
	191
	192	#define DRV_MODULE_NAME "fs_enet"
	193	#define PFX DRV_MODULE_NAME ": "
	194	#define DRV_MODULE_VERSION "1.0"
	195	#define DRV_MODULE_RELDATE "Aug 8, 2005"
	196
	197	/***************************************************************************/
	198
	199	int fs_enet_platform_init(void);
	200	void fs_enet_platform_cleanup(void);
	201
	202	/***************************************************************************/
48257c4f PA	203	/* buffer descriptor access macros */
	204
	205	/* access macros */
	206	#if defined(CONFIG_CPM1)
	207	/* for a a CPM1 __raw_xxx's are sufficient */
	208	#define __cbd_out32(addr, x) __raw_writel(x, addr)
	209	#define __cbd_out16(addr, x) __raw_writew(x, addr)
	210	#define __cbd_in32(addr) __raw_readl(addr)
	211	#define __cbd_in16(addr) __raw_readw(addr)
	212	#else
	213	/* for others play it safe */
	214	#define __cbd_out32(addr, x) out_be32(addr, x)
	215	#define __cbd_out16(addr, x) out_be16(addr, x)
	216	#define __cbd_in32(addr) in_be32(addr)
	217	#define __cbd_in16(addr) in_be16(addr)
	218	#endif
	219
	220	/* write */
	221	#define CBDW_SC(_cbd, _sc) __cbd_out16(&(_cbd)->cbd_sc, (_sc))
	222	#define CBDW_DATLEN(_cbd, _datlen) __cbd_out16(&(_cbd)->cbd_datlen, (_datlen))
	223	#define CBDW_BUFADDR(_cbd, _bufaddr) __cbd_out32(&(_cbd)->cbd_bufaddr, (_bufaddr))
	224
	225	/* read */
	226	#define CBDR_SC(_cbd) __cbd_in16(&(_cbd)->cbd_sc)
	227	#define CBDR_DATLEN(_cbd) __cbd_in16(&(_cbd)->cbd_datlen)
	228	#define CBDR_BUFADDR(_cbd) __cbd_in32(&(_cbd)->cbd_bufaddr)
	229
	230	/* set bits */
	231	#define CBDS_SC(_cbd, _sc) CBDW_SC(_cbd, CBDR_SC(_cbd) \| (_sc))
	232
	233	/* clear bits */
	234	#define CBDC_SC(_cbd, _sc) CBDW_SC(_cbd, CBDR_SC(_cbd) & ~(_sc))
	235
	236	/*******************************************************************/
	237
	238	extern const struct fs_ops fs_fec_ops;
	239	extern const struct fs_ops fs_fcc_ops;
	240	extern const struct fs_ops fs_scc_ops;
	241
	242	/*******************************************************************/
	243
48257c4f	244	#endif