[mirror_ubuntu-zesty-kernel.git] / drivers / net / fs_enet / mac-fcc.c

/*
 * FCC driver for Motorola MPC82xx (PQ2).
 *
 * Copyright (c) 2003 Intracom S.A.
 *  by Pantelis Antoniou <panto@intracom.gr>
 *
 * 2005 (c) MontaVista Software, Inc.
 * Vitaly Bordug <vbordug@ru.mvista.com>
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2. This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/string.h>
#include <linux/ptrace.h>
#include <linux/errno.h>
#include <linux/ioport.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/spinlock.h>
#include <linux/mii.h>
#include <linux/ethtool.h>
#include <linux/bitops.h>
#include <linux/fs.h>
#include <linux/platform_device.h>
#include <linux/phy.h>

#include <asm/immap_cpm2.h>
#include <asm/mpc8260.h>
#include <asm/cpm2.h>

#include <asm/pgtable.h>
#include <asm/irq.h>
#include <asm/uaccess.h>

#ifdef CONFIG_PPC_CPM_NEW_BINDING
#include <asm/of_device.h>
#endif

#include "fs_enet.h"

/*************************************************/

/* FCC access macros */

/* write, read, set bits, clear bits */
#define W32(_p, _m, _v)	out_be32(&(_p)->_m, (_v))
#define R32(_p, _m)	in_be32(&(_p)->_m)
#define S32(_p, _m, _v)	W32(_p, _m, R32(_p, _m) | (_v))
#define C32(_p, _m, _v)	W32(_p, _m, R32(_p, _m) & ~(_v))

#define W16(_p, _m, _v)	out_be16(&(_p)->_m, (_v))
#define R16(_p, _m)	in_be16(&(_p)->_m)
#define S16(_p, _m, _v)	W16(_p, _m, R16(_p, _m) | (_v))
#define C16(_p, _m, _v)	W16(_p, _m, R16(_p, _m) & ~(_v))

#define W8(_p, _m, _v)	out_8(&(_p)->_m, (_v))
#define R8(_p, _m)	in_8(&(_p)->_m)
#define S8(_p, _m, _v)	W8(_p, _m, R8(_p, _m) | (_v))
#define C8(_p, _m, _v)	W8(_p, _m, R8(_p, _m) & ~(_v))

/*************************************************/

#define FCC_MAX_MULTICAST_ADDRS	64

#define mk_mii_read(REG)	(0x60020000 | ((REG & 0x1f) << 18))
#define mk_mii_write(REG, VAL)	(0x50020000 | ((REG & 0x1f) << 18) | (VAL & 0xffff))
#define mk_mii_end		0

#define MAX_CR_CMD_LOOPS	10000

static inline int fcc_cr_cmd(struct fs_enet_private *fep, u32 op)
{
	const struct fs_platform_info *fpi = fep->fpi;
	cpm2_map_t *immap = fs_enet_immap;
	cpm_cpm2_t *cpmp = &immap->im_cpm;
	int i;

	W32(cpmp, cp_cpcr, fpi->cp_command | op | CPM_CR_FLG);
	for (i = 0; i < MAX_CR_CMD_LOOPS; i++)
		if ((R32(cpmp, cp_cpcr) & CPM_CR_FLG) == 0)
			return 0;

	printk(KERN_ERR "%s(): Not able to issue CPM command\n",
	       __FUNCTION__);
	return 1;
}

static int do_pd_setup(struct fs_enet_private *fep)
{
#ifdef CONFIG_PPC_CPM_NEW_BINDING
	struct of_device *ofdev = to_of_device(fep->dev);
	struct fs_platform_info *fpi = fep->fpi;
	int ret = -EINVAL;

	fep->interrupt = of_irq_to_resource(ofdev->node, 0, NULL);
	if (fep->interrupt == NO_IRQ)
		goto out;

	fep->fcc.fccp = of_iomap(ofdev->node, 0);
	if (!fep->fcc.fccp)
		goto out;

	fep->fcc.ep = of_iomap(ofdev->node, 1);
	if (!fep->fcc.ep)
		goto out_fccp;

	fep->fcc.fcccp = of_iomap(ofdev->node, 2);
	if (!fep->fcc.fcccp)
		goto out_ep;

	fep->fcc.mem = (void *)cpm_dpalloc(128, 8);
	fpi->dpram_offset = (u32)cpm2_immr;
	if (IS_ERR_VALUE(fpi->dpram_offset)) {
		ret = fpi->dpram_offset;
		goto out_fcccp;
	}

	return 0;

out_fcccp:
	iounmap(fep->fcc.fcccp);
out_ep:
	iounmap(fep->fcc.ep);
out_fccp:
	iounmap(fep->fcc.fccp);
out:
	return ret;
#else
	struct platform_device *pdev = to_platform_device(fep->dev);
	struct resource *r;

	/* Fill out IRQ field */
	fep->interrupt = platform_get_irq(pdev, 0);
	if (fep->interrupt < 0)
		return -EINVAL;

	/* Attach the memory for the FCC Parameter RAM */
	r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fcc_pram");
	fep->fcc.ep = (void *)ioremap(r->start, r->end - r->start + 1);
	if (fep->fcc.ep == NULL)
		return -EINVAL;

	r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fcc_regs");
	fep->fcc.fccp = (void *)ioremap(r->start, r->end - r->start + 1);
	if (fep->fcc.fccp == NULL)
		return -EINVAL;

	if (fep->fpi->fcc_regs_c) {

		fep->fcc.fcccp = (void *)fep->fpi->fcc_regs_c;
	} else {
		r = platform_get_resource_byname(pdev, IORESOURCE_MEM,
				"fcc_regs_c");
		fep->fcc.fcccp = (void *)ioremap(r->start,
				r->end - r->start + 1);
	}

	if (fep->fcc.fcccp == NULL)
		return -EINVAL;

	fep->fcc.mem = (void *)fep->fpi->mem_offset;
	if (fep->fcc.mem == NULL)
		return -EINVAL;

	return 0;
#endif
}

#define FCC_NAPI_RX_EVENT_MSK	(FCC_ENET_RXF | FCC_ENET_RXB)
#define FCC_RX_EVENT		(FCC_ENET_RXF)
#define FCC_TX_EVENT		(FCC_ENET_TXB)
#define FCC_ERR_EVENT_MSK	(FCC_ENET_TXE | FCC_ENET_BSY)

static int setup_data(struct net_device *dev)
{
	struct fs_enet_private *fep = netdev_priv(dev);
#ifndef CONFIG_PPC_CPM_NEW_BINDING
	struct fs_platform_info *fpi = fep->fpi;

	fpi->cp_command = (fpi->cp_page << 26) |
	                  (fpi->cp_block << 21) |
	                  (12 << 6);

	fep->fcc.idx = fs_get_fcc_index(fpi->fs_no);
	if ((unsigned int)fep->fcc.idx >= 3)	/* max 3 FCCs */
		return -EINVAL;
#endif

	if (do_pd_setup(fep) != 0)
		return -EINVAL;

	fep->ev_napi_rx = FCC_NAPI_RX_EVENT_MSK;
	fep->ev_rx = FCC_RX_EVENT;
	fep->ev_tx = FCC_TX_EVENT;
	fep->ev_err = FCC_ERR_EVENT_MSK;

	return 0;
}

static int allocate_bd(struct net_device *dev)
{
	struct fs_enet_private *fep = netdev_priv(dev);
	const struct fs_platform_info *fpi = fep->fpi;

	fep->ring_base = dma_alloc_coherent(fep->dev,
					    (fpi->tx_ring + fpi->rx_ring) *
					    sizeof(cbd_t), &fep->ring_mem_addr,
					    GFP_KERNEL);
	if (fep->ring_base == NULL)
		return -ENOMEM;

	return 0;
}

static void free_bd(struct net_device *dev)
{
	struct fs_enet_private *fep = netdev_priv(dev);
	const struct fs_platform_info *fpi = fep->fpi;

	if (fep->ring_base)
		dma_free_coherent(fep->dev,
			(fpi->tx_ring + fpi->rx_ring) * sizeof(cbd_t),
			fep->ring_base, fep->ring_mem_addr);
}

static void cleanup_data(struct net_device *dev)
{
	/* nothing */
}

static void set_promiscuous_mode(struct net_device *dev)
{
	struct fs_enet_private *fep = netdev_priv(dev);
	fcc_t *fccp = fep->fcc.fccp;

	S32(fccp, fcc_fpsmr, FCC_PSMR_PRO);
}

static void set_multicast_start(struct net_device *dev)
{
	struct fs_enet_private *fep = netdev_priv(dev);
	fcc_enet_t *ep = fep->fcc.ep;

	W32(ep, fen_gaddrh, 0);
	W32(ep, fen_gaddrl, 0);
}

static void set_multicast_one(struct net_device *dev, const u8 *mac)
{
	struct fs_enet_private *fep = netdev_priv(dev);
	fcc_enet_t *ep = fep->fcc.ep;
	u16 taddrh, taddrm, taddrl;

	taddrh = ((u16)mac[5] << 8) | mac[4];
	taddrm = ((u16)mac[3] << 8) | mac[2];
	taddrl = ((u16)mac[1] << 8) | mac[0];

	W16(ep, fen_taddrh, taddrh);
	W16(ep, fen_taddrm, taddrm);
	W16(ep, fen_taddrl, taddrl);
	fcc_cr_cmd(fep, CPM_CR_SET_GADDR);
}

static void set_multicast_finish(struct net_device *dev)
{
	struct fs_enet_private *fep = netdev_priv(dev);
	fcc_t *fccp = fep->fcc.fccp;
	fcc_enet_t *ep = fep->fcc.ep;

	/* clear promiscuous always */
	C32(fccp, fcc_fpsmr, FCC_PSMR_PRO);

	/* if all multi or too many multicasts; just enable all */
	if ((dev->flags & IFF_ALLMULTI) != 0 ||
	    dev->mc_count > FCC_MAX_MULTICAST_ADDRS) {

		W32(ep, fen_gaddrh, 0xffffffff);
		W32(ep, fen_gaddrl, 0xffffffff);
	}

	/* read back */
	fep->fcc.gaddrh = R32(ep, fen_gaddrh);
	fep->fcc.gaddrl = R32(ep, fen_gaddrl);
}

static void set_multicast_list(struct net_device *dev)
{
	struct dev_mc_list *pmc;

	if ((dev->flags & IFF_PROMISC) == 0) {
		set_multicast_start(dev);
		for (pmc = dev->mc_list; pmc != NULL; pmc = pmc->next)
			set_multicast_one(dev, pmc->dmi_addr);
		set_multicast_finish(dev);
	} else
		set_promiscuous_mode(dev);
}

static void restart(struct net_device *dev)
{
	struct fs_enet_private *fep = netdev_priv(dev);
	const struct fs_platform_info *fpi = fep->fpi;
	fcc_t *fccp = fep->fcc.fccp;
	fcc_c_t *fcccp = fep->fcc.fcccp;
	fcc_enet_t *ep = fep->fcc.ep;
	dma_addr_t rx_bd_base_phys, tx_bd_base_phys;
	u16 paddrh, paddrm, paddrl;
	u16 mem_addr;
	const unsigned char *mac;
	int i;

	C32(fccp, fcc_gfmr, FCC_GFMR_ENR | FCC_GFMR_ENT);

	/* clear everything (slow & steady does it) */
	for (i = 0; i < sizeof(*ep); i++)
		out_8((u8 __iomem *)ep + i, 0);

	/* get physical address */
	rx_bd_base_phys = fep->ring_mem_addr;
	tx_bd_base_phys = rx_bd_base_phys + sizeof(cbd_t) * fpi->rx_ring;

	/* point to bds */
	W32(ep, fen_genfcc.fcc_rbase, rx_bd_base_phys);
	W32(ep, fen_genfcc.fcc_tbase, tx_bd_base_phys);

	/* Set maximum bytes per receive buffer.
	 * It must be a multiple of 32.
	 */
	W16(ep, fen_genfcc.fcc_mrblr, PKT_MAXBLR_SIZE);

	W32(ep, fen_genfcc.fcc_rstate, (CPMFCR_GBL | CPMFCR_EB) << 24);
	W32(ep, fen_genfcc.fcc_tstate, (CPMFCR_GBL | CPMFCR_EB) << 24);

	/* Allocate space in the reserved FCC area of DPRAM for the
	 * internal buffers.  No one uses this space (yet), so we
	 * can do this.  Later, we will add resource management for
	 * this area.
	 */

	mem_addr = (u32) fep->fcc.mem;	/* de-fixup dpram offset */

	W16(ep, fen_genfcc.fcc_riptr, (mem_addr & 0xffff));
	W16(ep, fen_genfcc.fcc_tiptr, ((mem_addr + 32) & 0xffff));
	W16(ep, fen_padptr, mem_addr + 64);

	/* fill with special symbol...  */
	memset(fep->fcc.mem + fpi->dpram_offset + 64, 0x88, 32);

	W32(ep, fen_genfcc.fcc_rbptr, 0);
	W32(ep, fen_genfcc.fcc_tbptr, 0);
	W32(ep, fen_genfcc.fcc_rcrc, 0);
	W32(ep, fen_genfcc.fcc_tcrc, 0);
	W16(ep, fen_genfcc.fcc_res1, 0);
	W32(ep, fen_genfcc.fcc_res2, 0);

	/* no CAM */
	W32(ep, fen_camptr, 0);

	/* Set CRC preset and mask */
	W32(ep, fen_cmask, 0xdebb20e3);
	W32(ep, fen_cpres, 0xffffffff);

	W32(ep, fen_crcec, 0);		/* CRC Error counter       */
	W32(ep, fen_alec, 0);		/* alignment error counter */
	W32(ep, fen_disfc, 0);		/* discard frame counter   */
	W16(ep, fen_retlim, 15);	/* Retry limit threshold   */
	W16(ep, fen_pper, 0);		/* Normal persistence      */

	/* set group address */
	W32(ep, fen_gaddrh, fep->fcc.gaddrh);
	W32(ep, fen_gaddrl, fep->fcc.gaddrh);

	/* Clear hash filter tables */
	W32(ep, fen_iaddrh, 0);
	W32(ep, fen_iaddrl, 0);

	/* Clear the Out-of-sequence TxBD  */
	W16(ep, fen_tfcstat, 0);
	W16(ep, fen_tfclen, 0);
	W32(ep, fen_tfcptr, 0);

	W16(ep, fen_mflr, PKT_MAXBUF_SIZE);	/* maximum frame length register */
	W16(ep, fen_minflr, PKT_MINBUF_SIZE);	/* minimum frame length register */

	/* set address */
	mac = dev->dev_addr;
	paddrh = ((u16)mac[5] << 8) | mac[4];
	paddrm = ((u16)mac[3] << 8) | mac[2];
	paddrl = ((u16)mac[1] << 8) | mac[0];

	W16(ep, fen_paddrh, paddrh);
	W16(ep, fen_paddrm, paddrm);
	W16(ep, fen_paddrl, paddrl);

	W16(ep, fen_taddrh, 0);
	W16(ep, fen_taddrm, 0);
	W16(ep, fen_taddrl, 0);

	W16(ep, fen_maxd1, 1520);	/* maximum DMA1 length */
	W16(ep, fen_maxd2, 1520);	/* maximum DMA2 length */

	/* Clear stat counters, in case we ever enable RMON */
	W32(ep, fen_octc, 0);
	W32(ep, fen_colc, 0);
	W32(ep, fen_broc, 0);
	W32(ep, fen_mulc, 0);
	W32(ep, fen_uspc, 0);
	W32(ep, fen_frgc, 0);
	W32(ep, fen_ospc, 0);
	W32(ep, fen_jbrc, 0);
	W32(ep, fen_p64c, 0);
	W32(ep, fen_p65c, 0);
	W32(ep, fen_p128c, 0);
	W32(ep, fen_p256c, 0);
	W32(ep, fen_p512c, 0);
	W32(ep, fen_p1024c, 0);

	W16(ep, fen_rfthr, 0);	/* Suggested by manual */
	W16(ep, fen_rfcnt, 0);
	W16(ep, fen_cftype, 0);

	fs_init_bds(dev);

	/* adjust to speed (for RMII mode) */
	if (fpi->use_rmii) {
		if (fep->phydev->speed == 100)
			C8(fcccp, fcc_gfemr, 0x20);
		else
			S8(fcccp, fcc_gfemr, 0x20);
	}

	fcc_cr_cmd(fep, CPM_CR_INIT_TRX);

	/* clear events */
	W16(fccp, fcc_fcce, 0xffff);

	/* Enable interrupts we wish to service */
	W16(fccp, fcc_fccm, FCC_ENET_TXE | FCC_ENET_RXF | FCC_ENET_TXB);

	/* Set GFMR to enable Ethernet operating mode */
	W32(fccp, fcc_gfmr, FCC_GFMR_TCI | FCC_GFMR_MODE_ENET);

	/* set sync/delimiters */
	W16(fccp, fcc_fdsr, 0xd555);

	W32(fccp, fcc_fpsmr, FCC_PSMR_ENCRC);

	if (fpi->use_rmii)
		S32(fccp, fcc_fpsmr, FCC_PSMR_RMII);

	/* adjust to duplex mode */
	if (fep->phydev->duplex)
		S32(fccp, fcc_fpsmr, FCC_PSMR_FDE | FCC_PSMR_LPB);
	else
		C32(fccp, fcc_fpsmr, FCC_PSMR_FDE | FCC_PSMR_LPB);

	S32(fccp, fcc_gfmr, FCC_GFMR_ENR | FCC_GFMR_ENT);
}

static void stop(struct net_device *dev)
{
	struct fs_enet_private *fep = netdev_priv(dev);
	fcc_t *fccp = fep->fcc.fccp;

	/* stop ethernet */
	C32(fccp, fcc_gfmr, FCC_GFMR_ENR | FCC_GFMR_ENT);

	/* clear events */
	W16(fccp, fcc_fcce, 0xffff);

	/* clear interrupt mask */
	W16(fccp, fcc_fccm, 0);

	fs_cleanup_bds(dev);
}

static void pre_request_irq(struct net_device *dev, int irq)
{
	/* nothing */
}

static void post_free_irq(struct net_device *dev, int irq)
{
	/* nothing */
}

static void napi_clear_rx_event(struct net_device *dev)
{
	struct fs_enet_private *fep = netdev_priv(dev);
	fcc_t *fccp = fep->fcc.fccp;

	W16(fccp, fcc_fcce, FCC_NAPI_RX_EVENT_MSK);
}

static void napi_enable_rx(struct net_device *dev)
{
	struct fs_enet_private *fep = netdev_priv(dev);
	fcc_t *fccp = fep->fcc.fccp;

	S16(fccp, fcc_fccm, FCC_NAPI_RX_EVENT_MSK);
}

static void napi_disable_rx(struct net_device *dev)
{
	struct fs_enet_private *fep = netdev_priv(dev);
	fcc_t *fccp = fep->fcc.fccp;

	C16(fccp, fcc_fccm, FCC_NAPI_RX_EVENT_MSK);
}

static void rx_bd_done(struct net_device *dev)
{
	/* nothing */
}

static void tx_kickstart(struct net_device *dev)
{
	struct fs_enet_private *fep = netdev_priv(dev);
	fcc_t *fccp = fep->fcc.fccp;

	S16(fccp, fcc_ftodr, 0x8000);
}

static u32 get_int_events(struct net_device *dev)
{
	struct fs_enet_private *fep = netdev_priv(dev);
	fcc_t *fccp = fep->fcc.fccp;

	return (u32)R16(fccp, fcc_fcce);
}

static void clear_int_events(struct net_device *dev, u32 int_events)
{
	struct fs_enet_private *fep = netdev_priv(dev);
	fcc_t *fccp = fep->fcc.fccp;

	W16(fccp, fcc_fcce, int_events & 0xffff);
}

static void ev_error(struct net_device *dev, u32 int_events)
{
	printk(KERN_WARNING DRV_MODULE_NAME
	       ": %s FS_ENET ERROR(s) 0x%x\n", dev->name, int_events);
}

int get_regs(struct net_device *dev, void *p, int *sizep)
{
	struct fs_enet_private *fep = netdev_priv(dev);

	if (*sizep < sizeof(fcc_t) + sizeof(fcc_enet_t) + 1)
		return -EINVAL;

	memcpy_fromio(p, fep->fcc.fccp, sizeof(fcc_t));
	p = (char *)p + sizeof(fcc_t);

	memcpy_fromio(p, fep->fcc.ep, sizeof(fcc_enet_t));
	p = (char *)p + sizeof(fcc_enet_t);

	memcpy_fromio(p, fep->fcc.fcccp, 1);
	return 0;
}

int get_regs_len(struct net_device *dev)
{
	return sizeof(fcc_t) + sizeof(fcc_enet_t) + 1;
}

/* Some transmit errors cause the transmitter to shut
 * down.  We now issue a restart transmit.  Since the
 * errors close the BD and update the pointers, the restart
 * _should_ pick up without having to reset any of our
 * pointers either.  Also, To workaround 8260 device erratum
 * CPM37, we must disable and then re-enable the transmitter
 * following a Late Collision, Underrun, or Retry Limit error.
 */
void tx_restart(struct net_device *dev)
{
	struct fs_enet_private *fep = netdev_priv(dev);
	fcc_t *fccp = fep->fcc.fccp;

	C32(fccp, fcc_gfmr, FCC_GFMR_ENT);
	udelay(10);
	S32(fccp, fcc_gfmr, FCC_GFMR_ENT);

	fcc_cr_cmd(fep, CPM_CR_RESTART_TX);
}

/*************************************************************************/

const struct fs_ops fs_fcc_ops = {
	.setup_data		= setup_data,
	.cleanup_data		= cleanup_data,
	.set_multicast_list	= set_multicast_list,
	.restart		= restart,
	.stop			= stop,
	.pre_request_irq	= pre_request_irq,
	.post_free_irq		= post_free_irq,
	.napi_clear_rx_event	= napi_clear_rx_event,
	.napi_enable_rx		= napi_enable_rx,
	.napi_disable_rx	= napi_disable_rx,
	.rx_bd_done		= rx_bd_done,
	.tx_kickstart		= tx_kickstart,
	.get_int_events		= get_int_events,
	.clear_int_events	= clear_int_events,
	.ev_error		= ev_error,
	.get_regs		= get_regs,
	.get_regs_len		= get_regs_len,
	.tx_restart		= tx_restart,
	.allocate_bd		= allocate_bd,
	.free_bd		= free_bd,
};
Commit	Line	Data
48257c4f PA	1	/*
	2	* FCC driver for Motorola MPC82xx (PQ2).
	3	*
9b8ee8e7	4	* Copyright (c) 2003 Intracom S.A.
48257c4f PA	5	* by Pantelis Antoniou <panto@intracom.gr>
48257c4f PA	6	*
9b8ee8e7	7	* 2005 (c) MontaVista Software, Inc.
48257c4f PA	8	* Vitaly Bordug <vbordug@ru.mvista.com>
48257c4f PA	9	*
9b8ee8e7 VB	10	* This file is licensed under the terms of the GNU General Public License
9b8ee8e7 VB	11	* version 2. This program is licensed "as is" without any warranty of any
48257c4f PA	12	* kind, whether express or implied.
	13	*/
	14
48257c4f PA	15	#include <linux/module.h>
	16	#include <linux/kernel.h>
	17	#include <linux/types.h>
48257c4f PA	18	#include <linux/string.h>
	19	#include <linux/ptrace.h>
	20	#include <linux/errno.h>
	21	#include <linux/ioport.h>
	22	#include <linux/slab.h>
	23	#include <linux/interrupt.h>
48257c4f PA	24	#include <linux/init.h>
	25	#include <linux/delay.h>
	26	#include <linux/netdevice.h>
	27	#include <linux/etherdevice.h>
	28	#include <linux/skbuff.h>
	29	#include <linux/spinlock.h>
	30	#include <linux/mii.h>
	31	#include <linux/ethtool.h>
	32	#include <linux/bitops.h>
	33	#include <linux/fs.h>
f7b99969	34	#include <linux/platform_device.h>
5b4b8454	35	#include <linux/phy.h>
48257c4f PA	36
	37	#include <asm/immap_cpm2.h>
	38	#include <asm/mpc8260.h>
	39	#include <asm/cpm2.h>
	40
	41	#include <asm/pgtable.h>
	42	#include <asm/irq.h>
	43	#include <asm/uaccess.h>
	44
976de6a8 SW	45	#ifdef CONFIG_PPC_CPM_NEW_BINDING
	46	#include <asm/of_device.h>
	47	#endif
	48
48257c4f PA	49	#include "fs_enet.h"
	50
	51	/*************************************************/
	52
	53	/* FCC access macros */
	54
48257c4f	55	/* write, read, set bits, clear bits */
c6565331 SW	56	#define W32(_p, _m, _v) out_be32(&(_p)->_m, (_v))
c6565331 SW	57	#define R32(_p, _m) in_be32(&(_p)->_m)
48257c4f PA	58	#define S32(_p, _m, _v) W32(_p, _m, R32(_p, _m) \| (_v))
	59	#define C32(_p, _m, _v) W32(_p, _m, R32(_p, _m) & ~(_v))
	60
c6565331 SW	61	#define W16(_p, _m, _v) out_be16(&(_p)->_m, (_v))
c6565331 SW	62	#define R16(_p, _m) in_be16(&(_p)->_m)
48257c4f PA	63	#define S16(_p, _m, _v) W16(_p, _m, R16(_p, _m) \| (_v))
	64	#define C16(_p, _m, _v) W16(_p, _m, R16(_p, _m) & ~(_v))
	65
c6565331 SW	66	#define W8(_p, _m, _v) out_8(&(_p)->_m, (_v))
c6565331 SW	67	#define R8(_p, _m) in_8(&(_p)->_m)
48257c4f PA	68	#define S8(_p, _m, _v) W8(_p, _m, R8(_p, _m) \| (_v))
	69	#define C8(_p, _m, _v) W8(_p, _m, R8(_p, _m) & ~(_v))
	70
	71	/*************************************************/
	72
	73	#define FCC_MAX_MULTICAST_ADDRS 64
	74
	75	#define mk_mii_read(REG) (0x60020000 \| ((REG & 0x1f) << 18))
	76	#define mk_mii_write(REG, VAL) (0x50020000 \| ((REG & 0x1f) << 18) \| (VAL & 0xffff))
	77	#define mk_mii_end 0
	78
	79	#define MAX_CR_CMD_LOOPS 10000
	80
976de6a8	81	static inline int fcc_cr_cmd(struct fs_enet_private *fep, u32 op)
48257c4f PA	82	{
48257c4f PA	83	const struct fs_platform_info *fpi = fep->fpi;
48257c4f PA	84	cpm2_map_t *immap = fs_enet_immap;
48257c4f PA	85	cpm_cpm2_t *cpmp = &immap->im_cpm;
48257c4f PA	86	int i;
48257c4f PA	87
976de6a8	88	W32(cpmp, cp_cpcr, fpi->cp_command \| op \| CPM_CR_FLG);
48257c4f PA	89	for (i = 0; i < MAX_CR_CMD_LOOPS; i++)
48257c4f PA	90	if ((R32(cpmp, cp_cpcr) & CPM_CR_FLG) == 0)
976de6a8	91	return 0;
48257c4f	92
976de6a8 SW	93	printk(KERN_ERR "%s(): Not able to issue CPM command\n",
	94	__FUNCTION__);
	95	return 1;
48257c4f PA	96	}
	97
	98	static int do_pd_setup(struct fs_enet_private *fep)
	99	{
976de6a8 SW	100	#ifdef CONFIG_PPC_CPM_NEW_BINDING
	101	struct of_device *ofdev = to_of_device(fep->dev);
	102	struct fs_platform_info *fpi = fep->fpi;
	103	int ret = -EINVAL;
	104
	105	fep->interrupt = of_irq_to_resource(ofdev->node, 0, NULL);
	106	if (fep->interrupt == NO_IRQ)
	107	goto out;
	108
	109	fep->fcc.fccp = of_iomap(ofdev->node, 0);
	110	if (!fep->fcc.fccp)
	111	goto out;
	112
	113	fep->fcc.ep = of_iomap(ofdev->node, 1);
	114	if (!fep->fcc.ep)
	115	goto out_fccp;
	116
	117	fep->fcc.fcccp = of_iomap(ofdev->node, 2);
	118	if (!fep->fcc.fcccp)
	119	goto out_ep;
	120
	121	fep->fcc.mem = (void *)cpm_dpalloc(128, 8);
	122	fpi->dpram_offset = (u32)cpm2_immr;
	123	if (IS_ERR_VALUE(fpi->dpram_offset)) {
	124	ret = fpi->dpram_offset;
	125	goto out_fcccp;
	126	}
	127
	128	return 0;
	129
	130	out_fcccp:
	131	iounmap(fep->fcc.fcccp);
	132	out_ep:
	133	iounmap(fep->fcc.ep);
	134	out_fccp:
	135	iounmap(fep->fcc.fccp);
	136	out:
	137	return ret;
	138	#else
48257c4f PA	139	struct platform_device *pdev = to_platform_device(fep->dev);
	140	struct resource *r;
	141
	142	/* Fill out IRQ field */
	143	fep->interrupt = platform_get_irq(pdev, 0);
48944738 DV	144	if (fep->interrupt < 0)
48944738 DV	145	return -EINVAL;
48257c4f PA	146
	147	/* Attach the memory for the FCC Parameter RAM */
	148	r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fcc_pram");
5b4b8454	149	fep->fcc.ep = (void *)ioremap(r->start, r->end - r->start + 1);
48257c4f PA	150	if (fep->fcc.ep == NULL)
	151	return -EINVAL;
	152
	153	r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fcc_regs");
5b4b8454	154	fep->fcc.fccp = (void *)ioremap(r->start, r->end - r->start + 1);
48257c4f PA	155	if (fep->fcc.fccp == NULL)
	156	return -EINVAL;
	157
5b4b8454 VB	158	if (fep->fpi->fcc_regs_c) {
	159
	160	fep->fcc.fcccp = (void *)fep->fpi->fcc_regs_c;
	161	} else {
	162	r = platform_get_resource_byname(pdev, IORESOURCE_MEM,
	163	"fcc_regs_c");
	164	fep->fcc.fcccp = (void *)ioremap(r->start,
	165	r->end - r->start + 1);
	166	}
48257c4f PA	167
	168	if (fep->fcc.fcccp == NULL)
	169	return -EINVAL;
	170
5b4b8454 VB	171	fep->fcc.mem = (void *)fep->fpi->mem_offset;
	172	if (fep->fcc.mem == NULL)
	173	return -EINVAL;
	174
48257c4f	175	return 0;
976de6a8	176	#endif
48257c4f PA	177	}
	178
	179	#define FCC_NAPI_RX_EVENT_MSK (FCC_ENET_RXF \| FCC_ENET_RXB)
	180	#define FCC_RX_EVENT (FCC_ENET_RXF)
	181	#define FCC_TX_EVENT (FCC_ENET_TXB)
	182	#define FCC_ERR_EVENT_MSK (FCC_ENET_TXE \| FCC_ENET_BSY)
	183
	184	static int setup_data(struct net_device *dev)
	185	{
	186	struct fs_enet_private *fep = netdev_priv(dev);
976de6a8 SW	187	#ifndef CONFIG_PPC_CPM_NEW_BINDING
	188	struct fs_platform_info *fpi = fep->fpi;
	189
	190	fpi->cp_command = (fpi->cp_page << 26) \|
	191	(fpi->cp_block << 21) \|
	192	(12 << 6);
48257c4f PA	193
	194	fep->fcc.idx = fs_get_fcc_index(fpi->fs_no);
	195	if ((unsigned int)fep->fcc.idx >= 3) /* max 3 FCCs */
	196	return -EINVAL;
976de6a8	197	#endif
48257c4f	198
48257c4f PA	199	if (do_pd_setup(fep) != 0)
	200	return -EINVAL;
	201
	202	fep->ev_napi_rx = FCC_NAPI_RX_EVENT_MSK;
	203	fep->ev_rx = FCC_RX_EVENT;
	204	fep->ev_tx = FCC_TX_EVENT;
	205	fep->ev_err = FCC_ERR_EVENT_MSK;
	206
	207	return 0;
	208	}
	209
	210	static int allocate_bd(struct net_device *dev)
	211	{
	212	struct fs_enet_private *fep = netdev_priv(dev);
	213	const struct fs_platform_info *fpi = fep->fpi;
	214
	215	fep->ring_base = dma_alloc_coherent(fep->dev,
	216	(fpi->tx_ring + fpi->rx_ring) *
	217	sizeof(cbd_t), &fep->ring_mem_addr,
	218	GFP_KERNEL);
	219	if (fep->ring_base == NULL)
	220	return -ENOMEM;
	221
	222	return 0;
	223	}
	224
	225	static void free_bd(struct net_device *dev)
	226	{
	227	struct fs_enet_private *fep = netdev_priv(dev);
	228	const struct fs_platform_info *fpi = fep->fpi;
	229
	230	if (fep->ring_base)
	231	dma_free_coherent(fep->dev,
	232	(fpi->tx_ring + fpi->rx_ring) * sizeof(cbd_t),
	233	fep->ring_base, fep->ring_mem_addr);
	234	}
	235
	236	static void cleanup_data(struct net_device *dev)
	237	{
	238	/* nothing */
	239	}
	240
	241	static void set_promiscuous_mode(struct net_device *dev)
	242	{
	243	struct fs_enet_private *fep = netdev_priv(dev);
	244	fcc_t *fccp = fep->fcc.fccp;
	245
	246	S32(fccp, fcc_fpsmr, FCC_PSMR_PRO);
	247	}
	248
	249	static void set_multicast_start(struct net_device *dev)
	250	{
	251	struct fs_enet_private *fep = netdev_priv(dev);
	252	fcc_enet_t *ep = fep->fcc.ep;
	253
	254	W32(ep, fen_gaddrh, 0);
	255	W32(ep, fen_gaddrl, 0);
	256	}
	257
	258	static void set_multicast_one(struct net_device dev, const u8 mac)
	259	{
	260	struct fs_enet_private *fep = netdev_priv(dev);
	261	fcc_enet_t *ep = fep->fcc.ep;
	262	u16 taddrh, taddrm, taddrl;
263
264	taddrh = ((u16)mac[5] << 8) \| mac[4];
265	taddrm = ((u16)mac[3] << 8) \| mac[2];
266	taddrl = ((u16)mac[1] << 8) \| mac[0];
267
268	W16(ep, fen_taddrh, taddrh);
269	W16(ep, fen_taddrm, taddrm);
270	W16(ep, fen_taddrl, taddrl);
976de6a8	271	fcc_cr_cmd(fep, CPM_CR_SET_GADDR);
48257c4f PA	272	}
	273
	274	static void set_multicast_finish(struct net_device *dev)
	275	{
	276	struct fs_enet_private *fep = netdev_priv(dev);
	277	fcc_t *fccp = fep->fcc.fccp;
	278	fcc_enet_t *ep = fep->fcc.ep;
	279
	280	/* clear promiscuous always */
	281	C32(fccp, fcc_fpsmr, FCC_PSMR_PRO);
	282
	283	/* if all multi or too many multicasts; just enable all */
	284	if ((dev->flags & IFF_ALLMULTI) != 0 \|\|
	285	dev->mc_count > FCC_MAX_MULTICAST_ADDRS) {
	286
	287	W32(ep, fen_gaddrh, 0xffffffff);
	288	W32(ep, fen_gaddrl, 0xffffffff);
	289	}
	290
	291	/* read back */
	292	fep->fcc.gaddrh = R32(ep, fen_gaddrh);
	293	fep->fcc.gaddrl = R32(ep, fen_gaddrl);
	294	}
	295
	296	static void set_multicast_list(struct net_device *dev)
	297	{
	298	struct dev_mc_list *pmc;
	299
	300	if ((dev->flags & IFF_PROMISC) == 0) {
	301	set_multicast_start(dev);
	302	for (pmc = dev->mc_list; pmc != NULL; pmc = pmc->next)
	303	set_multicast_one(dev, pmc->dmi_addr);
	304	set_multicast_finish(dev);
	305	} else
	306	set_promiscuous_mode(dev);
	307	}
	308
	309	static void restart(struct net_device *dev)
	310	{
	311	struct fs_enet_private *fep = netdev_priv(dev);
	312	const struct fs_platform_info *fpi = fep->fpi;
	313	fcc_t *fccp = fep->fcc.fccp;
	314	fcc_c_t *fcccp = fep->fcc.fcccp;
	315	fcc_enet_t *ep = fep->fcc.ep;
	316	dma_addr_t rx_bd_base_phys, tx_bd_base_phys;
	317	u16 paddrh, paddrm, paddrl;
	318	u16 mem_addr;
	319	const unsigned char *mac;
	320	int i;
	321
	322	C32(fccp, fcc_gfmr, FCC_GFMR_ENR \| FCC_GFMR_ENT);
	323
	324	/* clear everything (slow & steady does it) */
	325	for (i = 0; i < sizeof(*ep); i++)
976de6a8	326	out_8((u8 __iomem *)ep + i, 0);
48257c4f PA	327
	328	/* get physical address */
	329	rx_bd_base_phys = fep->ring_mem_addr;
	330	tx_bd_base_phys = rx_bd_base_phys + sizeof(cbd_t) * fpi->rx_ring;
	331
	332	/* point to bds */
	333	W32(ep, fen_genfcc.fcc_rbase, rx_bd_base_phys);
	334	W32(ep, fen_genfcc.fcc_tbase, tx_bd_base_phys);
	335
	336	/* Set maximum bytes per receive buffer.
	337	* It must be a multiple of 32.
	338	*/
	339	W16(ep, fen_genfcc.fcc_mrblr, PKT_MAXBLR_SIZE);
	340
	341	W32(ep, fen_genfcc.fcc_rstate, (CPMFCR_GBL \| CPMFCR_EB) << 24);
	342	W32(ep, fen_genfcc.fcc_tstate, (CPMFCR_GBL \| CPMFCR_EB) << 24);
	343
	344	/* Allocate space in the reserved FCC area of DPRAM for the
	345	* internal buffers. No one uses this space (yet), so we
	346	* can do this. Later, we will add resource management for
	347	* this area.
	348	*/
	349
	350	mem_addr = (u32) fep->fcc.mem; /* de-fixup dpram offset */
	351
	352	W16(ep, fen_genfcc.fcc_riptr, (mem_addr & 0xffff));
	353	W16(ep, fen_genfcc.fcc_tiptr, ((mem_addr + 32) & 0xffff));
	354	W16(ep, fen_padptr, mem_addr + 64);
	355
	356	/* fill with special symbol... */
	357	memset(fep->fcc.mem + fpi->dpram_offset + 64, 0x88, 32);
	358
	359	W32(ep, fen_genfcc.fcc_rbptr, 0);
	360	W32(ep, fen_genfcc.fcc_tbptr, 0);
	361	W32(ep, fen_genfcc.fcc_rcrc, 0);
	362	W32(ep, fen_genfcc.fcc_tcrc, 0);
	363	W16(ep, fen_genfcc.fcc_res1, 0);
	364	W32(ep, fen_genfcc.fcc_res2, 0);
	365
	366	/* no CAM */
	367	W32(ep, fen_camptr, 0);
	368
	369	/* Set CRC preset and mask */
	370	W32(ep, fen_cmask, 0xdebb20e3);
	371	W32(ep, fen_cpres, 0xffffffff);
	372
	373	W32(ep, fen_crcec, 0); /* CRC Error counter */
	374	W32(ep, fen_alec, 0); /* alignment error counter */
	375	W32(ep, fen_disfc, 0); /* discard frame counter */
	376	W16(ep, fen_retlim, 15); /* Retry limit threshold */
	377	W16(ep, fen_pper, 0); /* Normal persistence */
	378
	379	/* set group address */
	380	W32(ep, fen_gaddrh, fep->fcc.gaddrh);
	381	W32(ep, fen_gaddrl, fep->fcc.gaddrh);
	382
	383	/* Clear hash filter tables */
	384	W32(ep, fen_iaddrh, 0);
	385	W32(ep, fen_iaddrl, 0);
	386
	387	/* Clear the Out-of-sequence TxBD */
	388	W16(ep, fen_tfcstat, 0);
	389	W16(ep, fen_tfclen, 0);
	390	W32(ep, fen_tfcptr, 0);
391
392	W16(ep, fen_mflr, PKT_MAXBUF_SIZE); /* maximum frame length register */
393	W16(ep, fen_minflr, PKT_MINBUF_SIZE); /* minimum frame length register */
394
395	/* set address */
396	mac = dev->dev_addr;
397	paddrh = ((u16)mac[5] << 8) \| mac[4];
398	paddrm = ((u16)mac[3] << 8) \| mac[2];
399	paddrl = ((u16)mac[1] << 8) \| mac[0];
400
401	W16(ep, fen_paddrh, paddrh);
402	W16(ep, fen_paddrm, paddrm);
403	W16(ep, fen_paddrl, paddrl);
404
405	W16(ep, fen_taddrh, 0);
406	W16(ep, fen_taddrm, 0);
407	W16(ep, fen_taddrl, 0);
408
409	W16(ep, fen_maxd1, 1520); /* maximum DMA1 length */
410	W16(ep, fen_maxd2, 1520); /* maximum DMA2 length */
411
412	/* Clear stat counters, in case we ever enable RMON */
413	W32(ep, fen_octc, 0);
414	W32(ep, fen_colc, 0);
415	W32(ep, fen_broc, 0);
416	W32(ep, fen_mulc, 0);
417	W32(ep, fen_uspc, 0);
418	W32(ep, fen_frgc, 0);
419	W32(ep, fen_ospc, 0);
420	W32(ep, fen_jbrc, 0);
421	W32(ep, fen_p64c, 0);
422	W32(ep, fen_p65c, 0);
423	W32(ep, fen_p128c, 0);
424	W32(ep, fen_p256c, 0);
425	W32(ep, fen_p512c, 0);
426	W32(ep, fen_p1024c, 0);
427
428	W16(ep, fen_rfthr, 0); /* Suggested by manual */
429	W16(ep, fen_rfcnt, 0);
430	W16(ep, fen_cftype, 0);
431
432	fs_init_bds(dev);
433
434	/* adjust to speed (for RMII mode) */
435	if (fpi->use_rmii) {
5b4b8454	436	if (fep->phydev->speed == 100)
48257c4f PA	437	C8(fcccp, fcc_gfemr, 0x20);
	438	else
	439	S8(fcccp, fcc_gfemr, 0x20);
	440	}
	441
976de6a8	442	fcc_cr_cmd(fep, CPM_CR_INIT_TRX);
48257c4f PA	443
	444	/* clear events */
	445	W16(fccp, fcc_fcce, 0xffff);
	446
	447	/* Enable interrupts we wish to service */
	448	W16(fccp, fcc_fccm, FCC_ENET_TXE \| FCC_ENET_RXF \| FCC_ENET_TXB);
	449
	450	/* Set GFMR to enable Ethernet operating mode */
	451	W32(fccp, fcc_gfmr, FCC_GFMR_TCI \| FCC_GFMR_MODE_ENET);
	452
	453	/* set sync/delimiters */
	454	W16(fccp, fcc_fdsr, 0xd555);
	455
	456	W32(fccp, fcc_fpsmr, FCC_PSMR_ENCRC);
	457
	458	if (fpi->use_rmii)
	459	S32(fccp, fcc_fpsmr, FCC_PSMR_RMII);
	460
	461	/* adjust to duplex mode */
5b4b8454	462	if (fep->phydev->duplex)
48257c4f PA	463	S32(fccp, fcc_fpsmr, FCC_PSMR_FDE \| FCC_PSMR_LPB);
	464	else
	465	C32(fccp, fcc_fpsmr, FCC_PSMR_FDE \| FCC_PSMR_LPB);
	466
	467	S32(fccp, fcc_gfmr, FCC_GFMR_ENR \| FCC_GFMR_ENT);
	468	}
	469
	470	static void stop(struct net_device *dev)
	471	{
	472	struct fs_enet_private *fep = netdev_priv(dev);
	473	fcc_t *fccp = fep->fcc.fccp;
	474
	475	/* stop ethernet */
	476	C32(fccp, fcc_gfmr, FCC_GFMR_ENR \| FCC_GFMR_ENT);
	477
	478	/* clear events */
	479	W16(fccp, fcc_fcce, 0xffff);
	480
	481	/* clear interrupt mask */
	482	W16(fccp, fcc_fccm, 0);
	483
	484	fs_cleanup_bds(dev);
	485	}
	486
	487	static void pre_request_irq(struct net_device *dev, int irq)
	488	{
	489	/* nothing */
	490	}
	491
	492	static void post_free_irq(struct net_device *dev, int irq)
	493	{
	494	/* nothing */
	495	}
	496
	497	static void napi_clear_rx_event(struct net_device *dev)
	498	{
	499	struct fs_enet_private *fep = netdev_priv(dev);
	500	fcc_t *fccp = fep->fcc.fccp;
	501
	502	W16(fccp, fcc_fcce, FCC_NAPI_RX_EVENT_MSK);
	503	}
	504
	505	static void napi_enable_rx(struct net_device *dev)
	506	{
	507	struct fs_enet_private *fep = netdev_priv(dev);
	508	fcc_t *fccp = fep->fcc.fccp;
	509
	510	S16(fccp, fcc_fccm, FCC_NAPI_RX_EVENT_MSK);
	511	}
	512
	513	static void napi_disable_rx(struct net_device *dev)
	514	{
	515	struct fs_enet_private *fep = netdev_priv(dev);
	516	fcc_t *fccp = fep->fcc.fccp;
	517
	518	C16(fccp, fcc_fccm, FCC_NAPI_RX_EVENT_MSK);
	519	}
	520
	521	static void rx_bd_done(struct net_device *dev)
	522	{
	523	/* nothing */
	524	}
	525
	526	static void tx_kickstart(struct net_device *dev)
527	{
5b4b8454 VB	528	struct fs_enet_private *fep = netdev_priv(dev);
	529	fcc_t *fccp = fep->fcc.fccp;
	530
c6565331	531	S16(fccp, fcc_ftodr, 0x8000);
48257c4f PA	532	}
	533
	534	static u32 get_int_events(struct net_device *dev)
	535	{
	536	struct fs_enet_private *fep = netdev_priv(dev);
	537	fcc_t *fccp = fep->fcc.fccp;
	538
	539	return (u32)R16(fccp, fcc_fcce);
	540	}
	541
	542	static void clear_int_events(struct net_device *dev, u32 int_events)
	543	{
	544	struct fs_enet_private *fep = netdev_priv(dev);
	545	fcc_t *fccp = fep->fcc.fccp;
	546
	547	W16(fccp, fcc_fcce, int_events & 0xffff);
	548	}
	549
	550	static void ev_error(struct net_device *dev, u32 int_events)
	551	{
	552	printk(KERN_WARNING DRV_MODULE_NAME
	553	": %s FS_ENET ERROR(s) 0x%x\n", dev->name, int_events);
	554	}
	555
	556	int get_regs(struct net_device dev, void p, int *sizep)
	557	{
	558	struct fs_enet_private *fep = netdev_priv(dev);
	559
976de6a8	560	if (*sizep < sizeof(fcc_t) + sizeof(fcc_enet_t) + 1)
48257c4f PA	561	return -EINVAL;
	562
	563	memcpy_fromio(p, fep->fcc.fccp, sizeof(fcc_t));
	564	p = (char *)p + sizeof(fcc_t);
	565
48257c4f	566	memcpy_fromio(p, fep->fcc.ep, sizeof(fcc_enet_t));
976de6a8	567	p = (char *)p + sizeof(fcc_enet_t);
48257c4f	568
976de6a8	569	memcpy_fromio(p, fep->fcc.fcccp, 1);
48257c4f PA	570	return 0;
	571	}
	572
	573	int get_regs_len(struct net_device *dev)
	574	{
976de6a8	575	return sizeof(fcc_t) + sizeof(fcc_enet_t) + 1;
48257c4f PA	576	}
	577
	578	/* Some transmit errors cause the transmitter to shut
	579	* down. We now issue a restart transmit. Since the
	580	* errors close the BD and update the pointers, the restart
	581	* _should_ pick up without having to reset any of our
9b8ee8e7	582	* pointers either. Also, To workaround 8260 device erratum
48257c4f PA	583	* CPM37, we must disable and then re-enable the transmitter
	584	* following a Late Collision, Underrun, or Retry Limit error.
	585	*/
	586	void tx_restart(struct net_device *dev)
	587	{
	588	struct fs_enet_private *fep = netdev_priv(dev);
	589	fcc_t *fccp = fep->fcc.fccp;
	590
	591	C32(fccp, fcc_gfmr, FCC_GFMR_ENT);
	592	udelay(10);
	593	S32(fccp, fcc_gfmr, FCC_GFMR_ENT);
	594
976de6a8	595	fcc_cr_cmd(fep, CPM_CR_RESTART_TX);
48257c4f PA	596	}
	597
	598	/*************************************************************************/
	599
	600	const struct fs_ops fs_fcc_ops = {
	601	.setup_data = setup_data,
	602	.cleanup_data = cleanup_data,
	603	.set_multicast_list = set_multicast_list,
	604	.restart = restart,
	605	.stop = stop,
	606	.pre_request_irq = pre_request_irq,
	607	.post_free_irq = post_free_irq,
	608	.napi_clear_rx_event = napi_clear_rx_event,
	609	.napi_enable_rx = napi_enable_rx,
	610	.napi_disable_rx = napi_disable_rx,
	611	.rx_bd_done = rx_bd_done,
	612	.tx_kickstart = tx_kickstart,
	613	.get_int_events = get_int_events,
	614	.clear_int_events = clear_int_events,
	615	.ev_error = ev_error,
	616	.get_regs = get_regs,
	617	.get_regs_len = get_regs_len,
	618	.tx_restart = tx_restart,
	619	.allocate_bd = allocate_bd,
	620	.free_bd = free_bd,
	621	};