]>
Commit | Line | Data |
---|---|---|
48257c4f PA |
1 | /* |
2 | * Freescale Ethernet controllers | |
3 | * | |
9b8ee8e7 | 4 | * Copyright (c) 2005 Intracom S.A. |
48257c4f PA |
5 | * by Pantelis Antoniou <panto@intracom.gr> |
6 | * | |
9b8ee8e7 | 7 | * 2005 (c) MontaVista Software, Inc. |
48257c4f PA |
8 | * Vitaly Bordug <vbordug@ru.mvista.com> |
9 | * | |
9b8ee8e7 VB |
10 | * This file is licensed under the terms of the GNU General Public License |
11 | * version 2. This program is licensed "as is" without any warranty of any | |
48257c4f PA |
12 | * kind, whether express or implied. |
13 | */ | |
14 | ||
48257c4f PA |
15 | #include <linux/module.h> |
16 | #include <linux/kernel.h> | |
17 | #include <linux/types.h> | |
48257c4f PA |
18 | #include <linux/string.h> |
19 | #include <linux/ptrace.h> | |
20 | #include <linux/errno.h> | |
21 | #include <linux/ioport.h> | |
48257c4f | 22 | #include <linux/interrupt.h> |
48257c4f PA |
23 | #include <linux/init.h> |
24 | #include <linux/delay.h> | |
25 | #include <linux/netdevice.h> | |
26 | #include <linux/etherdevice.h> | |
27 | #include <linux/skbuff.h> | |
28 | #include <linux/spinlock.h> | |
29 | #include <linux/mii.h> | |
30 | #include <linux/ethtool.h> | |
31 | #include <linux/bitops.h> | |
32 | #include <linux/fs.h> | |
f7b99969 | 33 | #include <linux/platform_device.h> |
b219108c | 34 | #include <linux/of_device.h> |
5a0e3ad6 | 35 | #include <linux/gfp.h> |
48257c4f PA |
36 | |
37 | #include <asm/irq.h> | |
38 | #include <asm/uaccess.h> | |
39 | ||
40 | #ifdef CONFIG_8xx | |
41 | #include <asm/8xx_immap.h> | |
42 | #include <asm/pgtable.h> | |
43 | #include <asm/mpc8xx.h> | |
b5677d84 | 44 | #include <asm/cpm1.h> |
48257c4f PA |
45 | #endif |
46 | ||
47 | #include "fs_enet.h" | |
5b4b8454 | 48 | #include "fec.h" |
48257c4f PA |
49 | |
50 | /*************************************************/ | |
51 | ||
52 | #if defined(CONFIG_CPM1) | |
53 | /* for a CPM1 __raw_xxx's are sufficient */ | |
54 | #define __fs_out32(addr, x) __raw_writel(x, addr) | |
55 | #define __fs_out16(addr, x) __raw_writew(x, addr) | |
56 | #define __fs_in32(addr) __raw_readl(addr) | |
57 | #define __fs_in16(addr) __raw_readw(addr) | |
58 | #else | |
59 | /* for others play it safe */ | |
60 | #define __fs_out32(addr, x) out_be32(addr, x) | |
61 | #define __fs_out16(addr, x) out_be16(addr, x) | |
62 | #define __fs_in32(addr) in_be32(addr) | |
63 | #define __fs_in16(addr) in_be16(addr) | |
64 | #endif | |
65 | ||
66 | /* write */ | |
67 | #define FW(_fecp, _reg, _v) __fs_out32(&(_fecp)->fec_ ## _reg, (_v)) | |
68 | ||
69 | /* read */ | |
70 | #define FR(_fecp, _reg) __fs_in32(&(_fecp)->fec_ ## _reg) | |
71 | ||
72 | /* set bits */ | |
73 | #define FS(_fecp, _reg, _v) FW(_fecp, _reg, FR(_fecp, _reg) | (_v)) | |
74 | ||
75 | /* clear bits */ | |
76 | #define FC(_fecp, _reg, _v) FW(_fecp, _reg, FR(_fecp, _reg) & ~(_v)) | |
77 | ||
48257c4f | 78 | /* |
5b4b8454 | 79 | * Delay to wait for FEC reset command to complete (in us) |
48257c4f PA |
80 | */ |
81 | #define FEC_RESET_DELAY 50 | |
82 | ||
60ab4361 | 83 | static int whack_reset(struct fec __iomem *fecp) |
48257c4f PA |
84 | { |
85 | int i; | |
86 | ||
87 | FW(fecp, ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET); | |
88 | for (i = 0; i < FEC_RESET_DELAY; i++) { | |
89 | if ((FR(fecp, ecntrl) & FEC_ECNTRL_RESET) == 0) | |
90 | return 0; /* OK */ | |
91 | udelay(1); | |
92 | } | |
93 | ||
94 | return -1; | |
95 | } | |
96 | ||
97 | static int do_pd_setup(struct fs_enet_private *fep) | |
98 | { | |
976de6a8 SW |
99 | struct of_device *ofdev = to_of_device(fep->dev); |
100 | ||
61c7a080 | 101 | fep->interrupt = of_irq_to_resource(ofdev->dev.of_node, 0, NULL); |
976de6a8 SW |
102 | if (fep->interrupt == NO_IRQ) |
103 | return -EINVAL; | |
104 | ||
61c7a080 | 105 | fep->fec.fecp = of_iomap(ofdev->dev.of_node, 0); |
976de6a8 SW |
106 | if (!fep->fcc.fccp) |
107 | return -EINVAL; | |
108 | ||
109 | return 0; | |
48257c4f PA |
110 | } |
111 | ||
112 | #define FEC_NAPI_RX_EVENT_MSK (FEC_ENET_RXF | FEC_ENET_RXB) | |
113 | #define FEC_RX_EVENT (FEC_ENET_RXF) | |
114 | #define FEC_TX_EVENT (FEC_ENET_TXF) | |
115 | #define FEC_ERR_EVENT_MSK (FEC_ENET_HBERR | FEC_ENET_BABR | \ | |
116 | FEC_ENET_BABT | FEC_ENET_EBERR) | |
117 | ||
118 | static int setup_data(struct net_device *dev) | |
119 | { | |
120 | struct fs_enet_private *fep = netdev_priv(dev); | |
121 | ||
122 | if (do_pd_setup(fep) != 0) | |
123 | return -EINVAL; | |
124 | ||
125 | fep->fec.hthi = 0; | |
126 | fep->fec.htlo = 0; | |
127 | ||
128 | fep->ev_napi_rx = FEC_NAPI_RX_EVENT_MSK; | |
129 | fep->ev_rx = FEC_RX_EVENT; | |
130 | fep->ev_tx = FEC_TX_EVENT; | |
131 | fep->ev_err = FEC_ERR_EVENT_MSK; | |
132 | ||
133 | return 0; | |
134 | } | |
135 | ||
136 | static int allocate_bd(struct net_device *dev) | |
137 | { | |
138 | struct fs_enet_private *fep = netdev_priv(dev); | |
139 | const struct fs_platform_info *fpi = fep->fpi; | |
9b8ee8e7 | 140 | |
31a5bb04 | 141 | fep->ring_base = (void __force __iomem *)dma_alloc_coherent(fep->dev, |
48257c4f PA |
142 | (fpi->tx_ring + fpi->rx_ring) * |
143 | sizeof(cbd_t), &fep->ring_mem_addr, | |
144 | GFP_KERNEL); | |
145 | if (fep->ring_base == NULL) | |
146 | return -ENOMEM; | |
147 | ||
148 | return 0; | |
149 | } | |
150 | ||
151 | static void free_bd(struct net_device *dev) | |
152 | { | |
153 | struct fs_enet_private *fep = netdev_priv(dev); | |
154 | const struct fs_platform_info *fpi = fep->fpi; | |
155 | ||
156 | if(fep->ring_base) | |
157 | dma_free_coherent(fep->dev, (fpi->tx_ring + fpi->rx_ring) | |
158 | * sizeof(cbd_t), | |
31a5bb04 | 159 | (void __force *)fep->ring_base, |
48257c4f PA |
160 | fep->ring_mem_addr); |
161 | } | |
162 | ||
163 | static void cleanup_data(struct net_device *dev) | |
164 | { | |
165 | /* nothing */ | |
166 | } | |
167 | ||
168 | static void set_promiscuous_mode(struct net_device *dev) | |
169 | { | |
170 | struct fs_enet_private *fep = netdev_priv(dev); | |
60ab4361 | 171 | struct fec __iomem *fecp = fep->fec.fecp; |
48257c4f PA |
172 | |
173 | FS(fecp, r_cntrl, FEC_RCNTRL_PROM); | |
174 | } | |
175 | ||
176 | static void set_multicast_start(struct net_device *dev) | |
177 | { | |
178 | struct fs_enet_private *fep = netdev_priv(dev); | |
179 | ||
180 | fep->fec.hthi = 0; | |
181 | fep->fec.htlo = 0; | |
182 | } | |
183 | ||
184 | static void set_multicast_one(struct net_device *dev, const u8 *mac) | |
185 | { | |
186 | struct fs_enet_private *fep = netdev_priv(dev); | |
187 | int temp, hash_index, i, j; | |
188 | u32 crc, csrVal; | |
189 | u8 byte, msb; | |
190 | ||
191 | crc = 0xffffffff; | |
192 | for (i = 0; i < 6; i++) { | |
193 | byte = mac[i]; | |
194 | for (j = 0; j < 8; j++) { | |
195 | msb = crc >> 31; | |
196 | crc <<= 1; | |
197 | if (msb ^ (byte & 0x1)) | |
198 | crc ^= FEC_CRC_POLY; | |
199 | byte >>= 1; | |
200 | } | |
201 | } | |
202 | ||
203 | temp = (crc & 0x3f) >> 1; | |
204 | hash_index = ((temp & 0x01) << 4) | | |
205 | ((temp & 0x02) << 2) | | |
206 | ((temp & 0x04)) | | |
207 | ((temp & 0x08) >> 2) | | |
208 | ((temp & 0x10) >> 4); | |
209 | csrVal = 1 << hash_index; | |
210 | if (crc & 1) | |
211 | fep->fec.hthi |= csrVal; | |
212 | else | |
213 | fep->fec.htlo |= csrVal; | |
214 | } | |
215 | ||
216 | static void set_multicast_finish(struct net_device *dev) | |
217 | { | |
218 | struct fs_enet_private *fep = netdev_priv(dev); | |
60ab4361 | 219 | struct fec __iomem *fecp = fep->fec.fecp; |
48257c4f PA |
220 | |
221 | /* if all multi or too many multicasts; just enable all */ | |
222 | if ((dev->flags & IFF_ALLMULTI) != 0 || | |
4cd24eaf | 223 | netdev_mc_count(dev) > FEC_MAX_MULTICAST_ADDRS) { |
48257c4f PA |
224 | fep->fec.hthi = 0xffffffffU; |
225 | fep->fec.htlo = 0xffffffffU; | |
226 | } | |
227 | ||
228 | FC(fecp, r_cntrl, FEC_RCNTRL_PROM); | |
229 | FW(fecp, hash_table_high, fep->fec.hthi); | |
230 | FW(fecp, hash_table_low, fep->fec.htlo); | |
231 | } | |
232 | ||
233 | static void set_multicast_list(struct net_device *dev) | |
234 | { | |
235 | struct dev_mc_list *pmc; | |
236 | ||
237 | if ((dev->flags & IFF_PROMISC) == 0) { | |
238 | set_multicast_start(dev); | |
48e2f183 | 239 | netdev_for_each_mc_addr(pmc, dev) |
48257c4f PA |
240 | set_multicast_one(dev, pmc->dmi_addr); |
241 | set_multicast_finish(dev); | |
242 | } else | |
243 | set_promiscuous_mode(dev); | |
244 | } | |
245 | ||
246 | static void restart(struct net_device *dev) | |
247 | { | |
48257c4f | 248 | struct fs_enet_private *fep = netdev_priv(dev); |
60ab4361 | 249 | struct fec __iomem *fecp = fep->fec.fecp; |
48257c4f PA |
250 | const struct fs_platform_info *fpi = fep->fpi; |
251 | dma_addr_t rx_bd_base_phys, tx_bd_base_phys; | |
252 | int r; | |
253 | u32 addrhi, addrlo; | |
254 | ||
5b4b8454 VB |
255 | struct mii_bus* mii = fep->phydev->bus; |
256 | struct fec_info* fec_inf = mii->priv; | |
257 | ||
48257c4f PA |
258 | r = whack_reset(fep->fec.fecp); |
259 | if (r != 0) | |
fcb6a1c8 | 260 | dev_err(fep->dev, "FEC Reset FAILED!\n"); |
48257c4f | 261 | /* |
5b4b8454 | 262 | * Set station address. |
48257c4f PA |
263 | */ |
264 | addrhi = ((u32) dev->dev_addr[0] << 24) | | |
265 | ((u32) dev->dev_addr[1] << 16) | | |
266 | ((u32) dev->dev_addr[2] << 8) | | |
267 | (u32) dev->dev_addr[3]; | |
268 | addrlo = ((u32) dev->dev_addr[4] << 24) | | |
269 | ((u32) dev->dev_addr[5] << 16); | |
270 | FW(fecp, addr_low, addrhi); | |
271 | FW(fecp, addr_high, addrlo); | |
272 | ||
273 | /* | |
9b8ee8e7 | 274 | * Reset all multicast. |
48257c4f PA |
275 | */ |
276 | FW(fecp, hash_table_high, fep->fec.hthi); | |
277 | FW(fecp, hash_table_low, fep->fec.htlo); | |
278 | ||
279 | /* | |
9b8ee8e7 | 280 | * Set maximum receive buffer size. |
48257c4f PA |
281 | */ |
282 | FW(fecp, r_buff_size, PKT_MAXBLR_SIZE); | |
60ab4361 AG |
283 | #ifdef CONFIG_FS_ENET_MPC5121_FEC |
284 | FW(fecp, r_cntrl, PKT_MAXBUF_SIZE << 16); | |
285 | #else | |
48257c4f | 286 | FW(fecp, r_hash, PKT_MAXBUF_SIZE); |
60ab4361 | 287 | #endif |
48257c4f PA |
288 | |
289 | /* get physical address */ | |
290 | rx_bd_base_phys = fep->ring_mem_addr; | |
291 | tx_bd_base_phys = rx_bd_base_phys + sizeof(cbd_t) * fpi->rx_ring; | |
292 | ||
293 | /* | |
9b8ee8e7 | 294 | * Set receive and transmit descriptor base. |
48257c4f PA |
295 | */ |
296 | FW(fecp, r_des_start, rx_bd_base_phys); | |
297 | FW(fecp, x_des_start, tx_bd_base_phys); | |
298 | ||
299 | fs_init_bds(dev); | |
300 | ||
301 | /* | |
9b8ee8e7 | 302 | * Enable big endian and don't care about SDMA FC. |
48257c4f | 303 | */ |
60ab4361 AG |
304 | #ifdef CONFIG_FS_ENET_MPC5121_FEC |
305 | FS(fecp, dma_control, 0xC0000000); | |
306 | #else | |
48257c4f | 307 | FW(fecp, fun_code, 0x78000000); |
60ab4361 | 308 | #endif |
48257c4f PA |
309 | |
310 | /* | |
5b4b8454 | 311 | * Set MII speed. |
48257c4f | 312 | */ |
5b4b8454 | 313 | FW(fecp, mii_speed, fec_inf->mii_speed); |
48257c4f PA |
314 | |
315 | /* | |
5b4b8454 | 316 | * Clear any outstanding interrupt. |
48257c4f PA |
317 | */ |
318 | FW(fecp, ievent, 0xffc0); | |
60ab4361 | 319 | #ifndef CONFIG_FS_ENET_MPC5121_FEC |
b1f54ba3 | 320 | FW(fecp, ivec, (virq_to_hw(fep->interrupt) / 2) << 29); |
48257c4f | 321 | |
48257c4f | 322 | FW(fecp, r_cntrl, FEC_RCNTRL_MII_MODE); /* MII enable */ |
60ab4361 AG |
323 | #else |
324 | /* | |
325 | * Only set MII mode - do not touch maximum frame length | |
326 | * configured before. | |
327 | */ | |
328 | FS(fecp, r_cntrl, FEC_RCNTRL_MII_MODE); | |
329 | #endif | |
48257c4f | 330 | /* |
5b4b8454 | 331 | * adjust to duplex mode |
48257c4f | 332 | */ |
5b4b8454 | 333 | if (fep->phydev->duplex) { |
48257c4f PA |
334 | FC(fecp, r_cntrl, FEC_RCNTRL_DRT); |
335 | FS(fecp, x_cntrl, FEC_TCNTRL_FDEN); /* FD enable */ | |
336 | } else { | |
337 | FS(fecp, r_cntrl, FEC_RCNTRL_DRT); | |
338 | FC(fecp, x_cntrl, FEC_TCNTRL_FDEN); /* FD disable */ | |
339 | } | |
340 | ||
341 | /* | |
9b8ee8e7 | 342 | * Enable interrupts we wish to service. |
48257c4f PA |
343 | */ |
344 | FW(fecp, imask, FEC_ENET_TXF | FEC_ENET_TXB | | |
345 | FEC_ENET_RXF | FEC_ENET_RXB); | |
346 | ||
347 | /* | |
9b8ee8e7 | 348 | * And last, enable the transmit and receive processing. |
48257c4f PA |
349 | */ |
350 | FW(fecp, ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN); | |
351 | FW(fecp, r_des_active, 0x01000000); | |
352 | } | |
353 | ||
354 | static void stop(struct net_device *dev) | |
355 | { | |
356 | struct fs_enet_private *fep = netdev_priv(dev); | |
5b4b8454 | 357 | const struct fs_platform_info *fpi = fep->fpi; |
60ab4361 | 358 | struct fec __iomem *fecp = fep->fec.fecp; |
5b4b8454 VB |
359 | |
360 | struct fec_info* feci= fep->phydev->bus->priv; | |
361 | ||
48257c4f PA |
362 | int i; |
363 | ||
364 | if ((FR(fecp, ecntrl) & FEC_ECNTRL_ETHER_EN) == 0) | |
365 | return; /* already down */ | |
366 | ||
367 | FW(fecp, x_cntrl, 0x01); /* Graceful transmit stop */ | |
368 | for (i = 0; ((FR(fecp, ievent) & 0x10000000) == 0) && | |
369 | i < FEC_RESET_DELAY; i++) | |
370 | udelay(1); | |
371 | ||
372 | if (i == FEC_RESET_DELAY) | |
fcb6a1c8 | 373 | dev_warn(fep->dev, "FEC timeout on graceful transmit stop\n"); |
48257c4f | 374 | /* |
9b8ee8e7 | 375 | * Disable FEC. Let only MII interrupts. |
48257c4f PA |
376 | */ |
377 | FW(fecp, imask, 0); | |
378 | FC(fecp, ecntrl, FEC_ECNTRL_ETHER_EN); | |
379 | ||
380 | fs_cleanup_bds(dev); | |
381 | ||
382 | /* shut down FEC1? that's where the mii bus is */ | |
5b4b8454 | 383 | if (fpi->has_phy) { |
48257c4f PA |
384 | FS(fecp, r_cntrl, FEC_RCNTRL_MII_MODE); /* MII enable */ |
385 | FS(fecp, ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN); | |
386 | FW(fecp, ievent, FEC_ENET_MII); | |
5b4b8454 | 387 | FW(fecp, mii_speed, feci->mii_speed); |
48257c4f PA |
388 | } |
389 | } | |
390 | ||
48257c4f PA |
391 | static void napi_clear_rx_event(struct net_device *dev) |
392 | { | |
393 | struct fs_enet_private *fep = netdev_priv(dev); | |
60ab4361 | 394 | struct fec __iomem *fecp = fep->fec.fecp; |
48257c4f PA |
395 | |
396 | FW(fecp, ievent, FEC_NAPI_RX_EVENT_MSK); | |
397 | } | |
398 | ||
399 | static void napi_enable_rx(struct net_device *dev) | |
400 | { | |
401 | struct fs_enet_private *fep = netdev_priv(dev); | |
60ab4361 | 402 | struct fec __iomem *fecp = fep->fec.fecp; |
48257c4f PA |
403 | |
404 | FS(fecp, imask, FEC_NAPI_RX_EVENT_MSK); | |
405 | } | |
406 | ||
407 | static void napi_disable_rx(struct net_device *dev) | |
408 | { | |
409 | struct fs_enet_private *fep = netdev_priv(dev); | |
60ab4361 | 410 | struct fec __iomem *fecp = fep->fec.fecp; |
48257c4f PA |
411 | |
412 | FC(fecp, imask, FEC_NAPI_RX_EVENT_MSK); | |
413 | } | |
414 | ||
415 | static void rx_bd_done(struct net_device *dev) | |
416 | { | |
417 | struct fs_enet_private *fep = netdev_priv(dev); | |
60ab4361 | 418 | struct fec __iomem *fecp = fep->fec.fecp; |
48257c4f PA |
419 | |
420 | FW(fecp, r_des_active, 0x01000000); | |
421 | } | |
422 | ||
423 | static void tx_kickstart(struct net_device *dev) | |
424 | { | |
425 | struct fs_enet_private *fep = netdev_priv(dev); | |
60ab4361 | 426 | struct fec __iomem *fecp = fep->fec.fecp; |
48257c4f PA |
427 | |
428 | FW(fecp, x_des_active, 0x01000000); | |
429 | } | |
430 | ||
431 | static u32 get_int_events(struct net_device *dev) | |
432 | { | |
433 | struct fs_enet_private *fep = netdev_priv(dev); | |
60ab4361 | 434 | struct fec __iomem *fecp = fep->fec.fecp; |
48257c4f PA |
435 | |
436 | return FR(fecp, ievent) & FR(fecp, imask); | |
437 | } | |
438 | ||
439 | static void clear_int_events(struct net_device *dev, u32 int_events) | |
440 | { | |
441 | struct fs_enet_private *fep = netdev_priv(dev); | |
60ab4361 | 442 | struct fec __iomem *fecp = fep->fec.fecp; |
48257c4f PA |
443 | |
444 | FW(fecp, ievent, int_events); | |
445 | } | |
446 | ||
447 | static void ev_error(struct net_device *dev, u32 int_events) | |
448 | { | |
fcb6a1c8 AG |
449 | struct fs_enet_private *fep = netdev_priv(dev); |
450 | ||
451 | dev_warn(fep->dev, "FEC ERROR(s) 0x%x\n", int_events); | |
48257c4f PA |
452 | } |
453 | ||
31a5bb04 | 454 | static int get_regs(struct net_device *dev, void *p, int *sizep) |
48257c4f PA |
455 | { |
456 | struct fs_enet_private *fep = netdev_priv(dev); | |
457 | ||
60ab4361 | 458 | if (*sizep < sizeof(struct fec)) |
48257c4f PA |
459 | return -EINVAL; |
460 | ||
60ab4361 | 461 | memcpy_fromio(p, fep->fec.fecp, sizeof(struct fec)); |
48257c4f PA |
462 | |
463 | return 0; | |
464 | } | |
465 | ||
31a5bb04 | 466 | static int get_regs_len(struct net_device *dev) |
48257c4f | 467 | { |
60ab4361 | 468 | return sizeof(struct fec); |
48257c4f PA |
469 | } |
470 | ||
31a5bb04 | 471 | static void tx_restart(struct net_device *dev) |
48257c4f PA |
472 | { |
473 | /* nothing */ | |
474 | } | |
475 | ||
476 | /*************************************************************************/ | |
477 | ||
478 | const struct fs_ops fs_fec_ops = { | |
479 | .setup_data = setup_data, | |
480 | .cleanup_data = cleanup_data, | |
481 | .set_multicast_list = set_multicast_list, | |
482 | .restart = restart, | |
483 | .stop = stop, | |
48257c4f PA |
484 | .napi_clear_rx_event = napi_clear_rx_event, |
485 | .napi_enable_rx = napi_enable_rx, | |
486 | .napi_disable_rx = napi_disable_rx, | |
487 | .rx_bd_done = rx_bd_done, | |
488 | .tx_kickstart = tx_kickstart, | |
489 | .get_int_events = get_int_events, | |
490 | .clear_int_events = clear_int_events, | |
491 | .ev_error = ev_error, | |
492 | .get_regs = get_regs, | |
493 | .get_regs_len = get_regs_len, | |
494 | .tx_restart = tx_restart, | |
495 | .allocate_bd = allocate_bd, | |
496 | .free_bd = free_bd, | |
497 | }; | |
498 |