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Commit | Line | Data |
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48257c4f PA |
1 | /* |
2 | * Ethernet on Serial Communications Controller (SCC) driver for Motorola MPC8xx and MPC82xx. | |
3 | * | |
9b8ee8e7 | 4 | * Copyright (c) 2003 Intracom S.A. |
48257c4f | 5 | * by Pantelis Antoniou <panto@intracom.gr> |
9b8ee8e7 VB |
6 | * |
7 | * 2005 (c) MontaVista Software, Inc. | |
48257c4f PA |
8 | * Vitaly Bordug <vbordug@ru.mvista.com> |
9 | * | |
9b8ee8e7 VB |
10 | * This file is licensed under the terms of the GNU General Public License |
11 | * version 2. This program is licensed "as is" without any warranty of any | |
48257c4f PA |
12 | * kind, whether express or implied. |
13 | */ | |
14 | ||
48257c4f PA |
15 | #include <linux/module.h> |
16 | #include <linux/kernel.h> | |
17 | #include <linux/types.h> | |
48257c4f PA |
18 | #include <linux/string.h> |
19 | #include <linux/ptrace.h> | |
20 | #include <linux/errno.h> | |
21 | #include <linux/ioport.h> | |
22 | #include <linux/slab.h> | |
23 | #include <linux/interrupt.h> | |
48257c4f PA |
24 | #include <linux/init.h> |
25 | #include <linux/delay.h> | |
26 | #include <linux/netdevice.h> | |
27 | #include <linux/etherdevice.h> | |
28 | #include <linux/skbuff.h> | |
29 | #include <linux/spinlock.h> | |
30 | #include <linux/mii.h> | |
31 | #include <linux/ethtool.h> | |
32 | #include <linux/bitops.h> | |
33 | #include <linux/fs.h> | |
f7b99969 | 34 | #include <linux/platform_device.h> |
48257c4f PA |
35 | |
36 | #include <asm/irq.h> | |
37 | #include <asm/uaccess.h> | |
38 | ||
39 | #ifdef CONFIG_8xx | |
40 | #include <asm/8xx_immap.h> | |
41 | #include <asm/pgtable.h> | |
42 | #include <asm/mpc8xx.h> | |
43 | #include <asm/commproc.h> | |
44 | #endif | |
45 | ||
976de6a8 SW |
46 | #ifdef CONFIG_PPC_CPM_NEW_BINDING |
47 | #include <asm/of_platform.h> | |
48 | #endif | |
49 | ||
48257c4f PA |
50 | #include "fs_enet.h" |
51 | ||
52 | /*************************************************/ | |
53 | ||
54 | #if defined(CONFIG_CPM1) | |
55 | /* for a 8xx __raw_xxx's are sufficient */ | |
56 | #define __fs_out32(addr, x) __raw_writel(x, addr) | |
57 | #define __fs_out16(addr, x) __raw_writew(x, addr) | |
58 | #define __fs_out8(addr, x) __raw_writeb(x, addr) | |
59 | #define __fs_in32(addr) __raw_readl(addr) | |
60 | #define __fs_in16(addr) __raw_readw(addr) | |
61 | #define __fs_in8(addr) __raw_readb(addr) | |
62 | #else | |
63 | /* for others play it safe */ | |
64 | #define __fs_out32(addr, x) out_be32(addr, x) | |
65 | #define __fs_out16(addr, x) out_be16(addr, x) | |
66 | #define __fs_in32(addr) in_be32(addr) | |
67 | #define __fs_in16(addr) in_be16(addr) | |
68 | #endif | |
69 | ||
70 | /* write, read, set bits, clear bits */ | |
71 | #define W32(_p, _m, _v) __fs_out32(&(_p)->_m, (_v)) | |
72 | #define R32(_p, _m) __fs_in32(&(_p)->_m) | |
73 | #define S32(_p, _m, _v) W32(_p, _m, R32(_p, _m) | (_v)) | |
74 | #define C32(_p, _m, _v) W32(_p, _m, R32(_p, _m) & ~(_v)) | |
75 | ||
76 | #define W16(_p, _m, _v) __fs_out16(&(_p)->_m, (_v)) | |
77 | #define R16(_p, _m) __fs_in16(&(_p)->_m) | |
78 | #define S16(_p, _m, _v) W16(_p, _m, R16(_p, _m) | (_v)) | |
79 | #define C16(_p, _m, _v) W16(_p, _m, R16(_p, _m) & ~(_v)) | |
80 | ||
81 | #define W8(_p, _m, _v) __fs_out8(&(_p)->_m, (_v)) | |
82 | #define R8(_p, _m) __fs_in8(&(_p)->_m) | |
83 | #define S8(_p, _m, _v) W8(_p, _m, R8(_p, _m) | (_v)) | |
84 | #define C8(_p, _m, _v) W8(_p, _m, R8(_p, _m) & ~(_v)) | |
85 | ||
86 | #define SCC_MAX_MULTICAST_ADDRS 64 | |
87 | ||
88 | /* | |
9b8ee8e7 | 89 | * Delay to wait for SCC reset command to complete (in us) |
48257c4f PA |
90 | */ |
91 | #define SCC_RESET_DELAY 50 | |
48257c4f PA |
92 | |
93 | static inline int scc_cr_cmd(struct fs_enet_private *fep, u32 op) | |
94 | { | |
976de6a8 | 95 | const struct fs_platform_info *fpi = fep->fpi; |
48257c4f | 96 | |
362f9b6f | 97 | return cpm_command(fpi->cp_command, op); |
48257c4f PA |
98 | } |
99 | ||
100 | static int do_pd_setup(struct fs_enet_private *fep) | |
101 | { | |
976de6a8 SW |
102 | #ifdef CONFIG_PPC_CPM_NEW_BINDING |
103 | struct of_device *ofdev = to_of_device(fep->dev); | |
104 | ||
105 | fep->interrupt = of_irq_to_resource(ofdev->node, 0, NULL); | |
106 | if (fep->interrupt == NO_IRQ) | |
107 | return -EINVAL; | |
108 | ||
109 | fep->scc.sccp = of_iomap(ofdev->node, 0); | |
110 | if (!fep->scc.sccp) | |
111 | return -EINVAL; | |
112 | ||
113 | fep->scc.ep = of_iomap(ofdev->node, 1); | |
114 | if (!fep->scc.ep) { | |
115 | iounmap(fep->scc.sccp); | |
116 | return -EINVAL; | |
117 | } | |
118 | #else | |
48257c4f PA |
119 | struct platform_device *pdev = to_platform_device(fep->dev); |
120 | struct resource *r; | |
121 | ||
122 | /* Fill out IRQ field */ | |
123 | fep->interrupt = platform_get_irq_byname(pdev, "interrupt"); | |
48944738 DV |
124 | if (fep->interrupt < 0) |
125 | return -EINVAL; | |
48257c4f PA |
126 | |
127 | r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"); | |
b1f54ba3 | 128 | fep->scc.sccp = ioremap(r->start, r->end - r->start + 1); |
48257c4f PA |
129 | |
130 | if (fep->scc.sccp == NULL) | |
131 | return -EINVAL; | |
132 | ||
133 | r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pram"); | |
b1f54ba3 | 134 | fep->scc.ep = ioremap(r->start, r->end - r->start + 1); |
48257c4f PA |
135 | |
136 | if (fep->scc.ep == NULL) | |
137 | return -EINVAL; | |
976de6a8 | 138 | #endif |
48257c4f PA |
139 | |
140 | return 0; | |
141 | } | |
142 | ||
143 | #define SCC_NAPI_RX_EVENT_MSK (SCCE_ENET_RXF | SCCE_ENET_RXB) | |
144 | #define SCC_RX_EVENT (SCCE_ENET_RXF) | |
145 | #define SCC_TX_EVENT (SCCE_ENET_TXB) | |
146 | #define SCC_ERR_EVENT_MSK (SCCE_ENET_TXE | SCCE_ENET_BSY) | |
147 | ||
148 | static int setup_data(struct net_device *dev) | |
149 | { | |
150 | struct fs_enet_private *fep = netdev_priv(dev); | |
976de6a8 SW |
151 | |
152 | #ifdef CONFIG_PPC_CPM_NEW_BINDING | |
153 | struct fs_platform_info *fpi = fep->fpi; | |
48257c4f PA |
154 | |
155 | fep->scc.idx = fs_get_scc_index(fpi->fs_no); | |
976de6a8 | 156 | if ((unsigned int)fep->fcc.idx >= 4) /* max 4 SCCs */ |
48257c4f PA |
157 | return -EINVAL; |
158 | ||
976de6a8 SW |
159 | fpi->cp_command = fep->fcc.idx << 6; |
160 | #endif | |
161 | ||
48257c4f PA |
162 | do_pd_setup(fep); |
163 | ||
164 | fep->scc.hthi = 0; | |
165 | fep->scc.htlo = 0; | |
166 | ||
167 | fep->ev_napi_rx = SCC_NAPI_RX_EVENT_MSK; | |
168 | fep->ev_rx = SCC_RX_EVENT; | |
976de6a8 | 169 | fep->ev_tx = SCC_TX_EVENT | SCCE_ENET_TXE; |
48257c4f PA |
170 | fep->ev_err = SCC_ERR_EVENT_MSK; |
171 | ||
172 | return 0; | |
173 | } | |
174 | ||
175 | static int allocate_bd(struct net_device *dev) | |
176 | { | |
177 | struct fs_enet_private *fep = netdev_priv(dev); | |
178 | const struct fs_platform_info *fpi = fep->fpi; | |
179 | ||
180 | fep->ring_mem_addr = cpm_dpalloc((fpi->tx_ring + fpi->rx_ring) * | |
181 | sizeof(cbd_t), 8); | |
4c35630c | 182 | if (IS_ERR_VALUE(fep->ring_mem_addr)) |
48257c4f PA |
183 | return -ENOMEM; |
184 | ||
31a5bb04 SW |
185 | fep->ring_base = (void __iomem __force*) |
186 | cpm_dpram_addr(fep->ring_mem_addr); | |
48257c4f PA |
187 | |
188 | return 0; | |
189 | } | |
190 | ||
191 | static void free_bd(struct net_device *dev) | |
192 | { | |
193 | struct fs_enet_private *fep = netdev_priv(dev); | |
194 | ||
195 | if (fep->ring_base) | |
196 | cpm_dpfree(fep->ring_mem_addr); | |
197 | } | |
198 | ||
199 | static void cleanup_data(struct net_device *dev) | |
200 | { | |
201 | /* nothing */ | |
202 | } | |
203 | ||
204 | static void set_promiscuous_mode(struct net_device *dev) | |
9b8ee8e7 | 205 | { |
48257c4f | 206 | struct fs_enet_private *fep = netdev_priv(dev); |
31a5bb04 | 207 | scc_t __iomem *sccp = fep->scc.sccp; |
48257c4f PA |
208 | |
209 | S16(sccp, scc_psmr, SCC_PSMR_PRO); | |
210 | } | |
211 | ||
212 | static void set_multicast_start(struct net_device *dev) | |
213 | { | |
214 | struct fs_enet_private *fep = netdev_priv(dev); | |
31a5bb04 | 215 | scc_enet_t __iomem *ep = fep->scc.ep; |
48257c4f PA |
216 | |
217 | W16(ep, sen_gaddr1, 0); | |
218 | W16(ep, sen_gaddr2, 0); | |
219 | W16(ep, sen_gaddr3, 0); | |
220 | W16(ep, sen_gaddr4, 0); | |
221 | } | |
222 | ||
223 | static void set_multicast_one(struct net_device *dev, const u8 * mac) | |
224 | { | |
225 | struct fs_enet_private *fep = netdev_priv(dev); | |
31a5bb04 | 226 | scc_enet_t __iomem *ep = fep->scc.ep; |
48257c4f PA |
227 | u16 taddrh, taddrm, taddrl; |
228 | ||
229 | taddrh = ((u16) mac[5] << 8) | mac[4]; | |
230 | taddrm = ((u16) mac[3] << 8) | mac[2]; | |
231 | taddrl = ((u16) mac[1] << 8) | mac[0]; | |
232 | ||
233 | W16(ep, sen_taddrh, taddrh); | |
234 | W16(ep, sen_taddrm, taddrm); | |
235 | W16(ep, sen_taddrl, taddrl); | |
236 | scc_cr_cmd(fep, CPM_CR_SET_GADDR); | |
237 | } | |
238 | ||
239 | static void set_multicast_finish(struct net_device *dev) | |
240 | { | |
241 | struct fs_enet_private *fep = netdev_priv(dev); | |
31a5bb04 SW |
242 | scc_t __iomem *sccp = fep->scc.sccp; |
243 | scc_enet_t __iomem *ep = fep->scc.ep; | |
48257c4f PA |
244 | |
245 | /* clear promiscuous always */ | |
246 | C16(sccp, scc_psmr, SCC_PSMR_PRO); | |
247 | ||
248 | /* if all multi or too many multicasts; just enable all */ | |
249 | if ((dev->flags & IFF_ALLMULTI) != 0 || | |
250 | dev->mc_count > SCC_MAX_MULTICAST_ADDRS) { | |
251 | ||
252 | W16(ep, sen_gaddr1, 0xffff); | |
253 | W16(ep, sen_gaddr2, 0xffff); | |
254 | W16(ep, sen_gaddr3, 0xffff); | |
255 | W16(ep, sen_gaddr4, 0xffff); | |
256 | } | |
257 | } | |
258 | ||
259 | static void set_multicast_list(struct net_device *dev) | |
260 | { | |
261 | struct dev_mc_list *pmc; | |
262 | ||
263 | if ((dev->flags & IFF_PROMISC) == 0) { | |
264 | set_multicast_start(dev); | |
265 | for (pmc = dev->mc_list; pmc != NULL; pmc = pmc->next) | |
266 | set_multicast_one(dev, pmc->dmi_addr); | |
267 | set_multicast_finish(dev); | |
268 | } else | |
269 | set_promiscuous_mode(dev); | |
270 | } | |
271 | ||
272 | /* | |
273 | * This function is called to start or restart the FEC during a link | |
274 | * change. This only happens when switching between half and full | |
275 | * duplex. | |
276 | */ | |
277 | static void restart(struct net_device *dev) | |
278 | { | |
279 | struct fs_enet_private *fep = netdev_priv(dev); | |
31a5bb04 SW |
280 | scc_t __iomem *sccp = fep->scc.sccp; |
281 | scc_enet_t __iomem *ep = fep->scc.ep; | |
48257c4f PA |
282 | const struct fs_platform_info *fpi = fep->fpi; |
283 | u16 paddrh, paddrm, paddrl; | |
284 | const unsigned char *mac; | |
285 | int i; | |
286 | ||
287 | C32(sccp, scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT); | |
288 | ||
289 | /* clear everything (slow & steady does it) */ | |
290 | for (i = 0; i < sizeof(*ep); i++) | |
31a5bb04 | 291 | __fs_out8((u8 __iomem *)ep + i, 0); |
48257c4f PA |
292 | |
293 | /* point to bds */ | |
294 | W16(ep, sen_genscc.scc_rbase, fep->ring_mem_addr); | |
295 | W16(ep, sen_genscc.scc_tbase, | |
296 | fep->ring_mem_addr + sizeof(cbd_t) * fpi->rx_ring); | |
297 | ||
298 | /* Initialize function code registers for big-endian. | |
299 | */ | |
300 | W8(ep, sen_genscc.scc_rfcr, SCC_EB); | |
301 | W8(ep, sen_genscc.scc_tfcr, SCC_EB); | |
302 | ||
303 | /* Set maximum bytes per receive buffer. | |
304 | * This appears to be an Ethernet frame size, not the buffer | |
305 | * fragment size. It must be a multiple of four. | |
306 | */ | |
307 | W16(ep, sen_genscc.scc_mrblr, 0x5f0); | |
308 | ||
309 | /* Set CRC preset and mask. | |
310 | */ | |
311 | W32(ep, sen_cpres, 0xffffffff); | |
312 | W32(ep, sen_cmask, 0xdebb20e3); | |
313 | ||
314 | W32(ep, sen_crcec, 0); /* CRC Error counter */ | |
315 | W32(ep, sen_alec, 0); /* alignment error counter */ | |
316 | W32(ep, sen_disfc, 0); /* discard frame counter */ | |
317 | ||
318 | W16(ep, sen_pads, 0x8888); /* Tx short frame pad character */ | |
319 | W16(ep, sen_retlim, 15); /* Retry limit threshold */ | |
320 | ||
321 | W16(ep, sen_maxflr, 0x5ee); /* maximum frame length register */ | |
322 | ||
323 | W16(ep, sen_minflr, PKT_MINBUF_SIZE); /* minimum frame length register */ | |
324 | ||
325 | W16(ep, sen_maxd1, 0x000005f0); /* maximum DMA1 length */ | |
326 | W16(ep, sen_maxd2, 0x000005f0); /* maximum DMA2 length */ | |
327 | ||
328 | /* Clear hash tables. | |
329 | */ | |
330 | W16(ep, sen_gaddr1, 0); | |
331 | W16(ep, sen_gaddr2, 0); | |
332 | W16(ep, sen_gaddr3, 0); | |
333 | W16(ep, sen_gaddr4, 0); | |
334 | W16(ep, sen_iaddr1, 0); | |
335 | W16(ep, sen_iaddr2, 0); | |
336 | W16(ep, sen_iaddr3, 0); | |
337 | W16(ep, sen_iaddr4, 0); | |
338 | ||
9b8ee8e7 | 339 | /* set address |
48257c4f PA |
340 | */ |
341 | mac = dev->dev_addr; | |
342 | paddrh = ((u16) mac[5] << 8) | mac[4]; | |
343 | paddrm = ((u16) mac[3] << 8) | mac[2]; | |
344 | paddrl = ((u16) mac[1] << 8) | mac[0]; | |
345 | ||
346 | W16(ep, sen_paddrh, paddrh); | |
347 | W16(ep, sen_paddrm, paddrm); | |
348 | W16(ep, sen_paddrl, paddrl); | |
349 | ||
350 | W16(ep, sen_pper, 0); | |
351 | W16(ep, sen_taddrl, 0); | |
352 | W16(ep, sen_taddrm, 0); | |
353 | W16(ep, sen_taddrh, 0); | |
354 | ||
355 | fs_init_bds(dev); | |
356 | ||
357 | scc_cr_cmd(fep, CPM_CR_INIT_TRX); | |
358 | ||
359 | W16(sccp, scc_scce, 0xffff); | |
360 | ||
9b8ee8e7 | 361 | /* Enable interrupts we wish to service. |
48257c4f PA |
362 | */ |
363 | W16(sccp, scc_sccm, SCCE_ENET_TXE | SCCE_ENET_RXF | SCCE_ENET_TXB); | |
364 | ||
365 | /* Set GSMR_H to enable all normal operating modes. | |
366 | * Set GSMR_L to enable Ethernet to MC68160. | |
367 | */ | |
368 | W32(sccp, scc_gsmrh, 0); | |
369 | W32(sccp, scc_gsmrl, | |
370 | SCC_GSMRL_TCI | SCC_GSMRL_TPL_48 | SCC_GSMRL_TPP_10 | | |
371 | SCC_GSMRL_MODE_ENET); | |
372 | ||
373 | /* Set sync/delimiters. | |
374 | */ | |
375 | W16(sccp, scc_dsr, 0xd555); | |
376 | ||
377 | /* Set processing mode. Use Ethernet CRC, catch broadcast, and | |
378 | * start frame search 22 bit times after RENA. | |
379 | */ | |
380 | W16(sccp, scc_psmr, SCC_PSMR_ENCRC | SCC_PSMR_NIB22); | |
381 | ||
382 | /* Set full duplex mode if needed */ | |
5b4b8454 | 383 | if (fep->phydev->duplex) |
48257c4f PA |
384 | S16(sccp, scc_psmr, SCC_PSMR_LPB | SCC_PSMR_FDE); |
385 | ||
386 | S32(sccp, scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT); | |
387 | } | |
388 | ||
9b8ee8e7 | 389 | static void stop(struct net_device *dev) |
48257c4f PA |
390 | { |
391 | struct fs_enet_private *fep = netdev_priv(dev); | |
31a5bb04 | 392 | scc_t __iomem *sccp = fep->scc.sccp; |
48257c4f PA |
393 | int i; |
394 | ||
395 | for (i = 0; (R16(sccp, scc_sccm) == 0) && i < SCC_RESET_DELAY; i++) | |
396 | udelay(1); | |
397 | ||
398 | if (i == SCC_RESET_DELAY) | |
399 | printk(KERN_WARNING DRV_MODULE_NAME | |
400 | ": %s SCC timeout on graceful transmit stop\n", | |
401 | dev->name); | |
402 | ||
403 | W16(sccp, scc_sccm, 0); | |
404 | C32(sccp, scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT); | |
405 | ||
406 | fs_cleanup_bds(dev); | |
407 | } | |
408 | ||
409 | static void pre_request_irq(struct net_device *dev, int irq) | |
410 | { | |
b1f54ba3 | 411 | #ifndef CONFIG_PPC_MERGE |
48257c4f PA |
412 | immap_t *immap = fs_enet_immap; |
413 | u32 siel; | |
414 | ||
415 | /* SIU interrupt */ | |
416 | if (irq >= SIU_IRQ0 && irq < SIU_LEVEL7) { | |
417 | ||
418 | siel = in_be32(&immap->im_siu_conf.sc_siel); | |
419 | if ((irq & 1) == 0) | |
420 | siel |= (0x80000000 >> irq); | |
421 | else | |
422 | siel &= ~(0x80000000 >> (irq & ~1)); | |
423 | out_be32(&immap->im_siu_conf.sc_siel, siel); | |
424 | } | |
b1f54ba3 | 425 | #endif |
48257c4f PA |
426 | } |
427 | ||
428 | static void post_free_irq(struct net_device *dev, int irq) | |
429 | { | |
430 | /* nothing */ | |
431 | } | |
432 | ||
433 | static void napi_clear_rx_event(struct net_device *dev) | |
434 | { | |
435 | struct fs_enet_private *fep = netdev_priv(dev); | |
31a5bb04 | 436 | scc_t __iomem *sccp = fep->scc.sccp; |
48257c4f PA |
437 | |
438 | W16(sccp, scc_scce, SCC_NAPI_RX_EVENT_MSK); | |
439 | } | |
440 | ||
441 | static void napi_enable_rx(struct net_device *dev) | |
442 | { | |
443 | struct fs_enet_private *fep = netdev_priv(dev); | |
31a5bb04 | 444 | scc_t __iomem *sccp = fep->scc.sccp; |
48257c4f PA |
445 | |
446 | S16(sccp, scc_sccm, SCC_NAPI_RX_EVENT_MSK); | |
447 | } | |
448 | ||
449 | static void napi_disable_rx(struct net_device *dev) | |
450 | { | |
451 | struct fs_enet_private *fep = netdev_priv(dev); | |
31a5bb04 | 452 | scc_t __iomem *sccp = fep->scc.sccp; |
48257c4f PA |
453 | |
454 | C16(sccp, scc_sccm, SCC_NAPI_RX_EVENT_MSK); | |
455 | } | |
456 | ||
457 | static void rx_bd_done(struct net_device *dev) | |
458 | { | |
459 | /* nothing */ | |
460 | } | |
461 | ||
462 | static void tx_kickstart(struct net_device *dev) | |
463 | { | |
464 | /* nothing */ | |
465 | } | |
466 | ||
467 | static u32 get_int_events(struct net_device *dev) | |
468 | { | |
469 | struct fs_enet_private *fep = netdev_priv(dev); | |
31a5bb04 | 470 | scc_t __iomem *sccp = fep->scc.sccp; |
48257c4f PA |
471 | |
472 | return (u32) R16(sccp, scc_scce); | |
473 | } | |
474 | ||
475 | static void clear_int_events(struct net_device *dev, u32 int_events) | |
476 | { | |
477 | struct fs_enet_private *fep = netdev_priv(dev); | |
31a5bb04 | 478 | scc_t __iomem *sccp = fep->scc.sccp; |
48257c4f PA |
479 | |
480 | W16(sccp, scc_scce, int_events & 0xffff); | |
481 | } | |
482 | ||
483 | static void ev_error(struct net_device *dev, u32 int_events) | |
484 | { | |
485 | printk(KERN_WARNING DRV_MODULE_NAME | |
486 | ": %s SCC ERROR(s) 0x%x\n", dev->name, int_events); | |
487 | } | |
488 | ||
489 | static int get_regs(struct net_device *dev, void *p, int *sizep) | |
490 | { | |
491 | struct fs_enet_private *fep = netdev_priv(dev); | |
492 | ||
31a5bb04 | 493 | if (*sizep < sizeof(scc_t) + sizeof(scc_enet_t __iomem *)) |
48257c4f PA |
494 | return -EINVAL; |
495 | ||
496 | memcpy_fromio(p, fep->scc.sccp, sizeof(scc_t)); | |
497 | p = (char *)p + sizeof(scc_t); | |
498 | ||
31a5bb04 | 499 | memcpy_fromio(p, fep->scc.ep, sizeof(scc_enet_t __iomem *)); |
48257c4f PA |
500 | |
501 | return 0; | |
502 | } | |
503 | ||
504 | static int get_regs_len(struct net_device *dev) | |
505 | { | |
31a5bb04 | 506 | return sizeof(scc_t) + sizeof(scc_enet_t __iomem *); |
48257c4f PA |
507 | } |
508 | ||
509 | static void tx_restart(struct net_device *dev) | |
510 | { | |
511 | struct fs_enet_private *fep = netdev_priv(dev); | |
512 | ||
513 | scc_cr_cmd(fep, CPM_CR_RESTART_TX); | |
514 | } | |
515 | ||
5b4b8454 VB |
516 | |
517 | ||
48257c4f PA |
518 | /*************************************************************************/ |
519 | ||
520 | const struct fs_ops fs_scc_ops = { | |
521 | .setup_data = setup_data, | |
522 | .cleanup_data = cleanup_data, | |
523 | .set_multicast_list = set_multicast_list, | |
524 | .restart = restart, | |
525 | .stop = stop, | |
526 | .pre_request_irq = pre_request_irq, | |
527 | .post_free_irq = post_free_irq, | |
528 | .napi_clear_rx_event = napi_clear_rx_event, | |
529 | .napi_enable_rx = napi_enable_rx, | |
530 | .napi_disable_rx = napi_disable_rx, | |
531 | .rx_bd_done = rx_bd_done, | |
532 | .tx_kickstart = tx_kickstart, | |
533 | .get_int_events = get_int_events, | |
534 | .clear_int_events = clear_int_events, | |
535 | .ev_error = ev_error, | |
536 | .get_regs = get_regs, | |
537 | .get_regs_len = get_regs_len, | |
538 | .tx_restart = tx_restart, | |
539 | .allocate_bd = allocate_bd, | |
540 | .free_bd = free_bd, | |
541 | }; |