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Commit | Line | Data |
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0bbaf069 | 1 | /* |
1da177e4 LT |
2 | * drivers/net/gianfar.c |
3 | * | |
4 | * Gianfar Ethernet Driver | |
7f7f5316 AF |
5 | * This driver is designed for the non-CPM ethernet controllers |
6 | * on the 85xx and 83xx family of integrated processors | |
1da177e4 LT |
7 | * Based on 8260_io/fcc_enet.c |
8 | * | |
9 | * Author: Andy Fleming | |
4c8d3d99 | 10 | * Maintainer: Kumar Gala |
1da177e4 | 11 | * |
e8a2b6a4 | 12 | * Copyright (c) 2002-2006 Freescale Semiconductor, Inc. |
538cc7ee | 13 | * Copyright (c) 2007 MontaVista Software, Inc. |
1da177e4 LT |
14 | * |
15 | * This program is free software; you can redistribute it and/or modify it | |
16 | * under the terms of the GNU General Public License as published by the | |
17 | * Free Software Foundation; either version 2 of the License, or (at your | |
18 | * option) any later version. | |
19 | * | |
20 | * Gianfar: AKA Lambda Draconis, "Dragon" | |
21 | * RA 11 31 24.2 | |
22 | * Dec +69 19 52 | |
23 | * V 3.84 | |
24 | * B-V +1.62 | |
25 | * | |
26 | * Theory of operation | |
0bbaf069 | 27 | * |
b31a1d8b AF |
28 | * The driver is initialized through of_device. Configuration information |
29 | * is therefore conveyed through an OF-style device tree. | |
1da177e4 LT |
30 | * |
31 | * The Gianfar Ethernet Controller uses a ring of buffer | |
32 | * descriptors. The beginning is indicated by a register | |
0bbaf069 KG |
33 | * pointing to the physical address of the start of the ring. |
34 | * The end is determined by a "wrap" bit being set in the | |
1da177e4 LT |
35 | * last descriptor of the ring. |
36 | * | |
37 | * When a packet is received, the RXF bit in the | |
0bbaf069 | 38 | * IEVENT register is set, triggering an interrupt when the |
1da177e4 LT |
39 | * corresponding bit in the IMASK register is also set (if |
40 | * interrupt coalescing is active, then the interrupt may not | |
41 | * happen immediately, but will wait until either a set number | |
bb40dcbb | 42 | * of frames or amount of time have passed). In NAPI, the |
1da177e4 | 43 | * interrupt handler will signal there is work to be done, and |
0aa1538f | 44 | * exit. This method will start at the last known empty |
0bbaf069 | 45 | * descriptor, and process every subsequent descriptor until there |
1da177e4 LT |
46 | * are none left with data (NAPI will stop after a set number of |
47 | * packets to give time to other tasks, but will eventually | |
48 | * process all the packets). The data arrives inside a | |
49 | * pre-allocated skb, and so after the skb is passed up to the | |
50 | * stack, a new skb must be allocated, and the address field in | |
51 | * the buffer descriptor must be updated to indicate this new | |
52 | * skb. | |
53 | * | |
54 | * When the kernel requests that a packet be transmitted, the | |
55 | * driver starts where it left off last time, and points the | |
56 | * descriptor at the buffer which was passed in. The driver | |
57 | * then informs the DMA engine that there are packets ready to | |
58 | * be transmitted. Once the controller is finished transmitting | |
59 | * the packet, an interrupt may be triggered (under the same | |
60 | * conditions as for reception, but depending on the TXF bit). | |
61 | * The driver then cleans up the buffer. | |
62 | */ | |
63 | ||
1da177e4 | 64 | #include <linux/kernel.h> |
1da177e4 LT |
65 | #include <linux/string.h> |
66 | #include <linux/errno.h> | |
bb40dcbb | 67 | #include <linux/unistd.h> |
1da177e4 LT |
68 | #include <linux/slab.h> |
69 | #include <linux/interrupt.h> | |
70 | #include <linux/init.h> | |
71 | #include <linux/delay.h> | |
72 | #include <linux/netdevice.h> | |
73 | #include <linux/etherdevice.h> | |
74 | #include <linux/skbuff.h> | |
0bbaf069 | 75 | #include <linux/if_vlan.h> |
1da177e4 LT |
76 | #include <linux/spinlock.h> |
77 | #include <linux/mm.h> | |
b31a1d8b | 78 | #include <linux/of_platform.h> |
0bbaf069 KG |
79 | #include <linux/ip.h> |
80 | #include <linux/tcp.h> | |
81 | #include <linux/udp.h> | |
9c07b884 | 82 | #include <linux/in.h> |
1da177e4 LT |
83 | |
84 | #include <asm/io.h> | |
85 | #include <asm/irq.h> | |
86 | #include <asm/uaccess.h> | |
87 | #include <linux/module.h> | |
1da177e4 LT |
88 | #include <linux/dma-mapping.h> |
89 | #include <linux/crc32.h> | |
bb40dcbb AF |
90 | #include <linux/mii.h> |
91 | #include <linux/phy.h> | |
b31a1d8b AF |
92 | #include <linux/phy_fixed.h> |
93 | #include <linux/of.h> | |
1da177e4 LT |
94 | |
95 | #include "gianfar.h" | |
bb40dcbb | 96 | #include "gianfar_mii.h" |
1da177e4 LT |
97 | |
98 | #define TX_TIMEOUT (1*HZ) | |
1da177e4 LT |
99 | #undef BRIEF_GFAR_ERRORS |
100 | #undef VERBOSE_GFAR_ERRORS | |
101 | ||
1da177e4 | 102 | const char gfar_driver_name[] = "Gianfar Ethernet"; |
7f7f5316 | 103 | const char gfar_driver_version[] = "1.3"; |
1da177e4 | 104 | |
1da177e4 LT |
105 | static int gfar_enet_open(struct net_device *dev); |
106 | static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev); | |
ab939905 | 107 | static void gfar_reset_task(struct work_struct *work); |
1da177e4 LT |
108 | static void gfar_timeout(struct net_device *dev); |
109 | static int gfar_close(struct net_device *dev); | |
815b97c6 AF |
110 | struct sk_buff *gfar_new_skb(struct net_device *dev); |
111 | static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp, | |
112 | struct sk_buff *skb); | |
1da177e4 LT |
113 | static int gfar_set_mac_address(struct net_device *dev); |
114 | static int gfar_change_mtu(struct net_device *dev, int new_mtu); | |
7d12e780 DH |
115 | static irqreturn_t gfar_error(int irq, void *dev_id); |
116 | static irqreturn_t gfar_transmit(int irq, void *dev_id); | |
117 | static irqreturn_t gfar_interrupt(int irq, void *dev_id); | |
1da177e4 LT |
118 | static void adjust_link(struct net_device *dev); |
119 | static void init_registers(struct net_device *dev); | |
120 | static int init_phy(struct net_device *dev); | |
b31a1d8b AF |
121 | static int gfar_probe(struct of_device *ofdev, |
122 | const struct of_device_id *match); | |
123 | static int gfar_remove(struct of_device *ofdev); | |
bb40dcbb | 124 | static void free_skb_resources(struct gfar_private *priv); |
1da177e4 LT |
125 | static void gfar_set_multi(struct net_device *dev); |
126 | static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr); | |
d3c12873 | 127 | static void gfar_configure_serdes(struct net_device *dev); |
bea3348e | 128 | static int gfar_poll(struct napi_struct *napi, int budget); |
f2d71c2d VW |
129 | #ifdef CONFIG_NET_POLL_CONTROLLER |
130 | static void gfar_netpoll(struct net_device *dev); | |
131 | #endif | |
0bbaf069 | 132 | int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit); |
f162b9d5 | 133 | static int gfar_clean_tx_ring(struct net_device *dev); |
2c2db48a DH |
134 | static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb, |
135 | int amount_pull); | |
0bbaf069 KG |
136 | static void gfar_vlan_rx_register(struct net_device *netdev, |
137 | struct vlan_group *grp); | |
7f7f5316 | 138 | void gfar_halt(struct net_device *dev); |
d87eb127 | 139 | static void gfar_halt_nodisable(struct net_device *dev); |
7f7f5316 AF |
140 | void gfar_start(struct net_device *dev); |
141 | static void gfar_clear_exact_match(struct net_device *dev); | |
142 | static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr); | |
1da177e4 | 143 | |
7282d491 | 144 | extern const struct ethtool_ops gfar_ethtool_ops; |
1da177e4 LT |
145 | |
146 | MODULE_AUTHOR("Freescale Semiconductor, Inc"); | |
147 | MODULE_DESCRIPTION("Gianfar Ethernet Driver"); | |
148 | MODULE_LICENSE("GPL"); | |
149 | ||
7f7f5316 AF |
150 | /* Returns 1 if incoming frames use an FCB */ |
151 | static inline int gfar_uses_fcb(struct gfar_private *priv) | |
0bbaf069 | 152 | { |
77ecaf2d | 153 | return priv->vlgrp || priv->rx_csum_enable; |
0bbaf069 | 154 | } |
bb40dcbb | 155 | |
b31a1d8b AF |
156 | static int gfar_of_init(struct net_device *dev) |
157 | { | |
158 | struct device_node *phy, *mdio; | |
159 | const unsigned int *id; | |
160 | const char *model; | |
161 | const char *ctype; | |
162 | const void *mac_addr; | |
163 | const phandle *ph; | |
164 | u64 addr, size; | |
165 | int err = 0; | |
166 | struct gfar_private *priv = netdev_priv(dev); | |
167 | struct device_node *np = priv->node; | |
168 | char bus_name[MII_BUS_ID_SIZE]; | |
169 | ||
170 | if (!np || !of_device_is_available(np)) | |
171 | return -ENODEV; | |
172 | ||
173 | /* get a pointer to the register memory */ | |
174 | addr = of_translate_address(np, of_get_address(np, 0, &size, NULL)); | |
175 | priv->regs = ioremap(addr, size); | |
176 | ||
177 | if (priv->regs == NULL) | |
178 | return -ENOMEM; | |
179 | ||
180 | priv->interruptTransmit = irq_of_parse_and_map(np, 0); | |
181 | ||
182 | model = of_get_property(np, "model", NULL); | |
183 | ||
184 | /* If we aren't the FEC we have multiple interrupts */ | |
185 | if (model && strcasecmp(model, "FEC")) { | |
186 | priv->interruptReceive = irq_of_parse_and_map(np, 1); | |
187 | ||
188 | priv->interruptError = irq_of_parse_and_map(np, 2); | |
189 | ||
190 | if (priv->interruptTransmit < 0 || | |
191 | priv->interruptReceive < 0 || | |
192 | priv->interruptError < 0) { | |
193 | err = -EINVAL; | |
194 | goto err_out; | |
195 | } | |
196 | } | |
197 | ||
198 | mac_addr = of_get_mac_address(np); | |
199 | if (mac_addr) | |
200 | memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN); | |
201 | ||
202 | if (model && !strcasecmp(model, "TSEC")) | |
203 | priv->device_flags = | |
204 | FSL_GIANFAR_DEV_HAS_GIGABIT | | |
205 | FSL_GIANFAR_DEV_HAS_COALESCE | | |
206 | FSL_GIANFAR_DEV_HAS_RMON | | |
207 | FSL_GIANFAR_DEV_HAS_MULTI_INTR; | |
208 | if (model && !strcasecmp(model, "eTSEC")) | |
209 | priv->device_flags = | |
210 | FSL_GIANFAR_DEV_HAS_GIGABIT | | |
211 | FSL_GIANFAR_DEV_HAS_COALESCE | | |
212 | FSL_GIANFAR_DEV_HAS_RMON | | |
213 | FSL_GIANFAR_DEV_HAS_MULTI_INTR | | |
2c2db48a | 214 | FSL_GIANFAR_DEV_HAS_PADDING | |
b31a1d8b AF |
215 | FSL_GIANFAR_DEV_HAS_CSUM | |
216 | FSL_GIANFAR_DEV_HAS_VLAN | | |
217 | FSL_GIANFAR_DEV_HAS_MAGIC_PACKET | | |
218 | FSL_GIANFAR_DEV_HAS_EXTENDED_HASH; | |
219 | ||
220 | ctype = of_get_property(np, "phy-connection-type", NULL); | |
221 | ||
222 | /* We only care about rgmii-id. The rest are autodetected */ | |
223 | if (ctype && !strcmp(ctype, "rgmii-id")) | |
224 | priv->interface = PHY_INTERFACE_MODE_RGMII_ID; | |
225 | else | |
226 | priv->interface = PHY_INTERFACE_MODE_MII; | |
227 | ||
228 | if (of_get_property(np, "fsl,magic-packet", NULL)) | |
229 | priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET; | |
230 | ||
231 | ph = of_get_property(np, "phy-handle", NULL); | |
232 | if (ph == NULL) { | |
233 | u32 *fixed_link; | |
234 | ||
235 | fixed_link = (u32 *)of_get_property(np, "fixed-link", NULL); | |
236 | if (!fixed_link) { | |
237 | err = -ENODEV; | |
238 | goto err_out; | |
239 | } | |
240 | ||
241 | snprintf(priv->phy_bus_id, BUS_ID_SIZE, PHY_ID_FMT, "0", | |
242 | fixed_link[0]); | |
243 | } else { | |
244 | phy = of_find_node_by_phandle(*ph); | |
245 | ||
246 | if (phy == NULL) { | |
247 | err = -ENODEV; | |
248 | goto err_out; | |
249 | } | |
250 | ||
251 | mdio = of_get_parent(phy); | |
252 | ||
253 | id = of_get_property(phy, "reg", NULL); | |
254 | ||
255 | of_node_put(phy); | |
256 | of_node_put(mdio); | |
257 | ||
258 | gfar_mdio_bus_name(bus_name, mdio); | |
259 | snprintf(priv->phy_bus_id, BUS_ID_SIZE, "%s:%02x", | |
260 | bus_name, *id); | |
261 | } | |
262 | ||
263 | /* Find the TBI PHY. If it's not there, we don't support SGMII */ | |
264 | ph = of_get_property(np, "tbi-handle", NULL); | |
265 | if (ph) { | |
266 | struct device_node *tbi = of_find_node_by_phandle(*ph); | |
267 | struct of_device *ofdev; | |
268 | struct mii_bus *bus; | |
269 | ||
270 | if (!tbi) | |
271 | return 0; | |
272 | ||
273 | mdio = of_get_parent(tbi); | |
274 | if (!mdio) | |
275 | return 0; | |
276 | ||
277 | ofdev = of_find_device_by_node(mdio); | |
278 | ||
279 | of_node_put(mdio); | |
280 | ||
281 | id = of_get_property(tbi, "reg", NULL); | |
282 | if (!id) | |
283 | return 0; | |
284 | ||
285 | of_node_put(tbi); | |
286 | ||
287 | bus = dev_get_drvdata(&ofdev->dev); | |
288 | ||
289 | priv->tbiphy = bus->phy_map[*id]; | |
290 | } | |
291 | ||
292 | return 0; | |
293 | ||
294 | err_out: | |
295 | iounmap(priv->regs); | |
296 | return err; | |
297 | } | |
298 | ||
bb40dcbb AF |
299 | /* Set up the ethernet device structure, private data, |
300 | * and anything else we need before we start */ | |
b31a1d8b AF |
301 | static int gfar_probe(struct of_device *ofdev, |
302 | const struct of_device_id *match) | |
1da177e4 LT |
303 | { |
304 | u32 tempval; | |
305 | struct net_device *dev = NULL; | |
306 | struct gfar_private *priv = NULL; | |
b31a1d8b AF |
307 | int err = 0; |
308 | DECLARE_MAC_BUF(mac); | |
1da177e4 LT |
309 | |
310 | /* Create an ethernet device instance */ | |
311 | dev = alloc_etherdev(sizeof (*priv)); | |
312 | ||
bb40dcbb | 313 | if (NULL == dev) |
1da177e4 LT |
314 | return -ENOMEM; |
315 | ||
316 | priv = netdev_priv(dev); | |
bea3348e | 317 | priv->dev = dev; |
b31a1d8b | 318 | priv->node = ofdev->node; |
1da177e4 | 319 | |
b31a1d8b | 320 | err = gfar_of_init(dev); |
1da177e4 | 321 | |
b31a1d8b | 322 | if (err) |
1da177e4 | 323 | goto regs_fail; |
1da177e4 | 324 | |
fef6108d AF |
325 | spin_lock_init(&priv->txlock); |
326 | spin_lock_init(&priv->rxlock); | |
d87eb127 | 327 | spin_lock_init(&priv->bflock); |
ab939905 | 328 | INIT_WORK(&priv->reset_task, gfar_reset_task); |
1da177e4 | 329 | |
b31a1d8b | 330 | dev_set_drvdata(&ofdev->dev, priv); |
1da177e4 LT |
331 | |
332 | /* Stop the DMA engine now, in case it was running before */ | |
333 | /* (The firmware could have used it, and left it running). */ | |
257d938a | 334 | gfar_halt(dev); |
1da177e4 LT |
335 | |
336 | /* Reset MAC layer */ | |
337 | gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET); | |
338 | ||
339 | tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW); | |
340 | gfar_write(&priv->regs->maccfg1, tempval); | |
341 | ||
342 | /* Initialize MACCFG2. */ | |
343 | gfar_write(&priv->regs->maccfg2, MACCFG2_INIT_SETTINGS); | |
344 | ||
345 | /* Initialize ECNTRL */ | |
346 | gfar_write(&priv->regs->ecntrl, ECNTRL_INIT_SETTINGS); | |
347 | ||
1da177e4 LT |
348 | /* Set the dev->base_addr to the gfar reg region */ |
349 | dev->base_addr = (unsigned long) (priv->regs); | |
350 | ||
b31a1d8b | 351 | SET_NETDEV_DEV(dev, &ofdev->dev); |
1da177e4 LT |
352 | |
353 | /* Fill in the dev structure */ | |
354 | dev->open = gfar_enet_open; | |
355 | dev->hard_start_xmit = gfar_start_xmit; | |
356 | dev->tx_timeout = gfar_timeout; | |
357 | dev->watchdog_timeo = TX_TIMEOUT; | |
bea3348e | 358 | netif_napi_add(dev, &priv->napi, gfar_poll, GFAR_DEV_WEIGHT); |
f2d71c2d VW |
359 | #ifdef CONFIG_NET_POLL_CONTROLLER |
360 | dev->poll_controller = gfar_netpoll; | |
1da177e4 LT |
361 | #endif |
362 | dev->stop = gfar_close; | |
1da177e4 LT |
363 | dev->change_mtu = gfar_change_mtu; |
364 | dev->mtu = 1500; | |
365 | dev->set_multicast_list = gfar_set_multi; | |
366 | ||
0bbaf069 KG |
367 | dev->ethtool_ops = &gfar_ethtool_ops; |
368 | ||
b31a1d8b | 369 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) { |
0bbaf069 KG |
370 | priv->rx_csum_enable = 1; |
371 | dev->features |= NETIF_F_IP_CSUM; | |
372 | } else | |
373 | priv->rx_csum_enable = 0; | |
374 | ||
375 | priv->vlgrp = NULL; | |
1da177e4 | 376 | |
b31a1d8b | 377 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) { |
0bbaf069 | 378 | dev->vlan_rx_register = gfar_vlan_rx_register; |
1da177e4 | 379 | |
0bbaf069 | 380 | dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; |
0bbaf069 KG |
381 | } |
382 | ||
b31a1d8b | 383 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) { |
0bbaf069 KG |
384 | priv->extended_hash = 1; |
385 | priv->hash_width = 9; | |
386 | ||
387 | priv->hash_regs[0] = &priv->regs->igaddr0; | |
388 | priv->hash_regs[1] = &priv->regs->igaddr1; | |
389 | priv->hash_regs[2] = &priv->regs->igaddr2; | |
390 | priv->hash_regs[3] = &priv->regs->igaddr3; | |
391 | priv->hash_regs[4] = &priv->regs->igaddr4; | |
392 | priv->hash_regs[5] = &priv->regs->igaddr5; | |
393 | priv->hash_regs[6] = &priv->regs->igaddr6; | |
394 | priv->hash_regs[7] = &priv->regs->igaddr7; | |
395 | priv->hash_regs[8] = &priv->regs->gaddr0; | |
396 | priv->hash_regs[9] = &priv->regs->gaddr1; | |
397 | priv->hash_regs[10] = &priv->regs->gaddr2; | |
398 | priv->hash_regs[11] = &priv->regs->gaddr3; | |
399 | priv->hash_regs[12] = &priv->regs->gaddr4; | |
400 | priv->hash_regs[13] = &priv->regs->gaddr5; | |
401 | priv->hash_regs[14] = &priv->regs->gaddr6; | |
402 | priv->hash_regs[15] = &priv->regs->gaddr7; | |
403 | ||
404 | } else { | |
405 | priv->extended_hash = 0; | |
406 | priv->hash_width = 8; | |
407 | ||
408 | priv->hash_regs[0] = &priv->regs->gaddr0; | |
409 | priv->hash_regs[1] = &priv->regs->gaddr1; | |
410 | priv->hash_regs[2] = &priv->regs->gaddr2; | |
411 | priv->hash_regs[3] = &priv->regs->gaddr3; | |
412 | priv->hash_regs[4] = &priv->regs->gaddr4; | |
413 | priv->hash_regs[5] = &priv->regs->gaddr5; | |
414 | priv->hash_regs[6] = &priv->regs->gaddr6; | |
415 | priv->hash_regs[7] = &priv->regs->gaddr7; | |
416 | } | |
417 | ||
b31a1d8b | 418 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING) |
0bbaf069 KG |
419 | priv->padding = DEFAULT_PADDING; |
420 | else | |
421 | priv->padding = 0; | |
422 | ||
0bbaf069 KG |
423 | if (dev->features & NETIF_F_IP_CSUM) |
424 | dev->hard_header_len += GMAC_FCB_LEN; | |
1da177e4 LT |
425 | |
426 | priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE; | |
1da177e4 LT |
427 | priv->tx_ring_size = DEFAULT_TX_RING_SIZE; |
428 | priv->rx_ring_size = DEFAULT_RX_RING_SIZE; | |
429 | ||
430 | priv->txcoalescing = DEFAULT_TX_COALESCE; | |
b46a8454 | 431 | priv->txic = DEFAULT_TXIC; |
1da177e4 | 432 | priv->rxcoalescing = DEFAULT_RX_COALESCE; |
b46a8454 | 433 | priv->rxic = DEFAULT_RXIC; |
1da177e4 | 434 | |
0bbaf069 KG |
435 | /* Enable most messages by default */ |
436 | priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1; | |
437 | ||
d3eab82b TP |
438 | /* Carrier starts down, phylib will bring it up */ |
439 | netif_carrier_off(dev); | |
440 | ||
1da177e4 LT |
441 | err = register_netdev(dev); |
442 | ||
443 | if (err) { | |
444 | printk(KERN_ERR "%s: Cannot register net device, aborting.\n", | |
445 | dev->name); | |
446 | goto register_fail; | |
447 | } | |
448 | ||
7f7f5316 AF |
449 | /* Create all the sysfs files */ |
450 | gfar_init_sysfs(dev); | |
451 | ||
1da177e4 | 452 | /* Print out the device info */ |
e174961c | 453 | printk(KERN_INFO DEVICE_NAME "%pM\n", dev->name, dev->dev_addr); |
1da177e4 LT |
454 | |
455 | /* Even more device info helps when determining which kernel */ | |
7f7f5316 | 456 | /* provided which set of benchmarks. */ |
1da177e4 | 457 | printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name); |
1da177e4 LT |
458 | printk(KERN_INFO "%s: %d/%d RX/TX BD ring size\n", |
459 | dev->name, priv->rx_ring_size, priv->tx_ring_size); | |
460 | ||
461 | return 0; | |
462 | ||
463 | register_fail: | |
cc8c6e37 | 464 | iounmap(priv->regs); |
1da177e4 LT |
465 | regs_fail: |
466 | free_netdev(dev); | |
bb40dcbb | 467 | return err; |
1da177e4 LT |
468 | } |
469 | ||
b31a1d8b | 470 | static int gfar_remove(struct of_device *ofdev) |
1da177e4 | 471 | { |
b31a1d8b | 472 | struct gfar_private *priv = dev_get_drvdata(&ofdev->dev); |
1da177e4 | 473 | |
b31a1d8b | 474 | dev_set_drvdata(&ofdev->dev, NULL); |
1da177e4 | 475 | |
cc8c6e37 | 476 | iounmap(priv->regs); |
b31a1d8b | 477 | free_netdev(priv->dev); |
1da177e4 LT |
478 | |
479 | return 0; | |
480 | } | |
481 | ||
d87eb127 | 482 | #ifdef CONFIG_PM |
b31a1d8b | 483 | static int gfar_suspend(struct of_device *ofdev, pm_message_t state) |
d87eb127 | 484 | { |
b31a1d8b AF |
485 | struct gfar_private *priv = dev_get_drvdata(&ofdev->dev); |
486 | struct net_device *dev = priv->dev; | |
d87eb127 SW |
487 | unsigned long flags; |
488 | u32 tempval; | |
489 | ||
490 | int magic_packet = priv->wol_en && | |
b31a1d8b | 491 | (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); |
d87eb127 SW |
492 | |
493 | netif_device_detach(dev); | |
494 | ||
495 | if (netif_running(dev)) { | |
496 | spin_lock_irqsave(&priv->txlock, flags); | |
497 | spin_lock(&priv->rxlock); | |
498 | ||
499 | gfar_halt_nodisable(dev); | |
500 | ||
501 | /* Disable Tx, and Rx if wake-on-LAN is disabled. */ | |
502 | tempval = gfar_read(&priv->regs->maccfg1); | |
503 | ||
504 | tempval &= ~MACCFG1_TX_EN; | |
505 | ||
506 | if (!magic_packet) | |
507 | tempval &= ~MACCFG1_RX_EN; | |
508 | ||
509 | gfar_write(&priv->regs->maccfg1, tempval); | |
510 | ||
511 | spin_unlock(&priv->rxlock); | |
512 | spin_unlock_irqrestore(&priv->txlock, flags); | |
513 | ||
d87eb127 | 514 | napi_disable(&priv->napi); |
d87eb127 SW |
515 | |
516 | if (magic_packet) { | |
517 | /* Enable interrupt on Magic Packet */ | |
518 | gfar_write(&priv->regs->imask, IMASK_MAG); | |
519 | ||
520 | /* Enable Magic Packet mode */ | |
521 | tempval = gfar_read(&priv->regs->maccfg2); | |
522 | tempval |= MACCFG2_MPEN; | |
523 | gfar_write(&priv->regs->maccfg2, tempval); | |
524 | } else { | |
525 | phy_stop(priv->phydev); | |
526 | } | |
527 | } | |
528 | ||
529 | return 0; | |
530 | } | |
531 | ||
b31a1d8b | 532 | static int gfar_resume(struct of_device *ofdev) |
d87eb127 | 533 | { |
b31a1d8b AF |
534 | struct gfar_private *priv = dev_get_drvdata(&ofdev->dev); |
535 | struct net_device *dev = priv->dev; | |
d87eb127 SW |
536 | unsigned long flags; |
537 | u32 tempval; | |
538 | int magic_packet = priv->wol_en && | |
b31a1d8b | 539 | (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); |
d87eb127 SW |
540 | |
541 | if (!netif_running(dev)) { | |
542 | netif_device_attach(dev); | |
543 | return 0; | |
544 | } | |
545 | ||
546 | if (!magic_packet && priv->phydev) | |
547 | phy_start(priv->phydev); | |
548 | ||
549 | /* Disable Magic Packet mode, in case something | |
550 | * else woke us up. | |
551 | */ | |
552 | ||
553 | spin_lock_irqsave(&priv->txlock, flags); | |
554 | spin_lock(&priv->rxlock); | |
555 | ||
556 | tempval = gfar_read(&priv->regs->maccfg2); | |
557 | tempval &= ~MACCFG2_MPEN; | |
558 | gfar_write(&priv->regs->maccfg2, tempval); | |
559 | ||
560 | gfar_start(dev); | |
561 | ||
562 | spin_unlock(&priv->rxlock); | |
563 | spin_unlock_irqrestore(&priv->txlock, flags); | |
564 | ||
565 | netif_device_attach(dev); | |
566 | ||
d87eb127 | 567 | napi_enable(&priv->napi); |
d87eb127 SW |
568 | |
569 | return 0; | |
570 | } | |
571 | #else | |
572 | #define gfar_suspend NULL | |
573 | #define gfar_resume NULL | |
574 | #endif | |
1da177e4 | 575 | |
e8a2b6a4 AF |
576 | /* Reads the controller's registers to determine what interface |
577 | * connects it to the PHY. | |
578 | */ | |
579 | static phy_interface_t gfar_get_interface(struct net_device *dev) | |
580 | { | |
581 | struct gfar_private *priv = netdev_priv(dev); | |
582 | u32 ecntrl = gfar_read(&priv->regs->ecntrl); | |
583 | ||
584 | if (ecntrl & ECNTRL_SGMII_MODE) | |
585 | return PHY_INTERFACE_MODE_SGMII; | |
586 | ||
587 | if (ecntrl & ECNTRL_TBI_MODE) { | |
588 | if (ecntrl & ECNTRL_REDUCED_MODE) | |
589 | return PHY_INTERFACE_MODE_RTBI; | |
590 | else | |
591 | return PHY_INTERFACE_MODE_TBI; | |
592 | } | |
593 | ||
594 | if (ecntrl & ECNTRL_REDUCED_MODE) { | |
595 | if (ecntrl & ECNTRL_REDUCED_MII_MODE) | |
596 | return PHY_INTERFACE_MODE_RMII; | |
7132ab7f | 597 | else { |
b31a1d8b | 598 | phy_interface_t interface = priv->interface; |
7132ab7f AF |
599 | |
600 | /* | |
601 | * This isn't autodetected right now, so it must | |
602 | * be set by the device tree or platform code. | |
603 | */ | |
604 | if (interface == PHY_INTERFACE_MODE_RGMII_ID) | |
605 | return PHY_INTERFACE_MODE_RGMII_ID; | |
606 | ||
e8a2b6a4 | 607 | return PHY_INTERFACE_MODE_RGMII; |
7132ab7f | 608 | } |
e8a2b6a4 AF |
609 | } |
610 | ||
b31a1d8b | 611 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT) |
e8a2b6a4 AF |
612 | return PHY_INTERFACE_MODE_GMII; |
613 | ||
614 | return PHY_INTERFACE_MODE_MII; | |
615 | } | |
616 | ||
617 | ||
bb40dcbb AF |
618 | /* Initializes driver's PHY state, and attaches to the PHY. |
619 | * Returns 0 on success. | |
1da177e4 LT |
620 | */ |
621 | static int init_phy(struct net_device *dev) | |
622 | { | |
623 | struct gfar_private *priv = netdev_priv(dev); | |
bb40dcbb | 624 | uint gigabit_support = |
b31a1d8b | 625 | priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ? |
bb40dcbb AF |
626 | SUPPORTED_1000baseT_Full : 0; |
627 | struct phy_device *phydev; | |
e8a2b6a4 | 628 | phy_interface_t interface; |
1da177e4 LT |
629 | |
630 | priv->oldlink = 0; | |
631 | priv->oldspeed = 0; | |
632 | priv->oldduplex = -1; | |
633 | ||
e8a2b6a4 AF |
634 | interface = gfar_get_interface(dev); |
635 | ||
b31a1d8b | 636 | phydev = phy_connect(dev, priv->phy_bus_id, &adjust_link, 0, interface); |
1da177e4 | 637 | |
d3c12873 KJ |
638 | if (interface == PHY_INTERFACE_MODE_SGMII) |
639 | gfar_configure_serdes(dev); | |
640 | ||
bb40dcbb AF |
641 | if (IS_ERR(phydev)) { |
642 | printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name); | |
643 | return PTR_ERR(phydev); | |
1da177e4 LT |
644 | } |
645 | ||
bb40dcbb AF |
646 | /* Remove any features not supported by the controller */ |
647 | phydev->supported &= (GFAR_SUPPORTED | gigabit_support); | |
648 | phydev->advertising = phydev->supported; | |
1da177e4 | 649 | |
bb40dcbb | 650 | priv->phydev = phydev; |
1da177e4 LT |
651 | |
652 | return 0; | |
1da177e4 LT |
653 | } |
654 | ||
d0313587 PG |
655 | /* |
656 | * Initialize TBI PHY interface for communicating with the | |
657 | * SERDES lynx PHY on the chip. We communicate with this PHY | |
658 | * through the MDIO bus on each controller, treating it as a | |
659 | * "normal" PHY at the address found in the TBIPA register. We assume | |
660 | * that the TBIPA register is valid. Either the MDIO bus code will set | |
661 | * it to a value that doesn't conflict with other PHYs on the bus, or the | |
662 | * value doesn't matter, as there are no other PHYs on the bus. | |
663 | */ | |
d3c12873 KJ |
664 | static void gfar_configure_serdes(struct net_device *dev) |
665 | { | |
666 | struct gfar_private *priv = netdev_priv(dev); | |
c132419e | 667 | |
b31a1d8b AF |
668 | if (!priv->tbiphy) { |
669 | printk(KERN_WARNING "SGMII mode requires that the device " | |
670 | "tree specify a tbi-handle\n"); | |
671 | return; | |
672 | } | |
d3c12873 | 673 | |
b31a1d8b AF |
674 | /* |
675 | * If the link is already up, we must already be ok, and don't need to | |
bdb59f94 TP |
676 | * configure and reset the TBI<->SerDes link. Maybe U-Boot configured |
677 | * everything for us? Resetting it takes the link down and requires | |
678 | * several seconds for it to come back. | |
679 | */ | |
b31a1d8b AF |
680 | if (phy_read(priv->tbiphy, MII_BMSR) & BMSR_LSTATUS) |
681 | return; | |
d3c12873 | 682 | |
d0313587 | 683 | /* Single clk mode, mii mode off(for serdes communication) */ |
b31a1d8b | 684 | phy_write(priv->tbiphy, MII_TBICON, TBICON_CLK_SELECT); |
d3c12873 | 685 | |
b31a1d8b | 686 | phy_write(priv->tbiphy, MII_ADVERTISE, |
d3c12873 KJ |
687 | ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE | |
688 | ADVERTISE_1000XPSE_ASYM); | |
689 | ||
b31a1d8b | 690 | phy_write(priv->tbiphy, MII_BMCR, BMCR_ANENABLE | |
d3c12873 KJ |
691 | BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000); |
692 | } | |
693 | ||
1da177e4 LT |
694 | static void init_registers(struct net_device *dev) |
695 | { | |
696 | struct gfar_private *priv = netdev_priv(dev); | |
697 | ||
698 | /* Clear IEVENT */ | |
699 | gfar_write(&priv->regs->ievent, IEVENT_INIT_CLEAR); | |
700 | ||
701 | /* Initialize IMASK */ | |
702 | gfar_write(&priv->regs->imask, IMASK_INIT_CLEAR); | |
703 | ||
704 | /* Init hash registers to zero */ | |
0bbaf069 KG |
705 | gfar_write(&priv->regs->igaddr0, 0); |
706 | gfar_write(&priv->regs->igaddr1, 0); | |
707 | gfar_write(&priv->regs->igaddr2, 0); | |
708 | gfar_write(&priv->regs->igaddr3, 0); | |
709 | gfar_write(&priv->regs->igaddr4, 0); | |
710 | gfar_write(&priv->regs->igaddr5, 0); | |
711 | gfar_write(&priv->regs->igaddr6, 0); | |
712 | gfar_write(&priv->regs->igaddr7, 0); | |
1da177e4 LT |
713 | |
714 | gfar_write(&priv->regs->gaddr0, 0); | |
715 | gfar_write(&priv->regs->gaddr1, 0); | |
716 | gfar_write(&priv->regs->gaddr2, 0); | |
717 | gfar_write(&priv->regs->gaddr3, 0); | |
718 | gfar_write(&priv->regs->gaddr4, 0); | |
719 | gfar_write(&priv->regs->gaddr5, 0); | |
720 | gfar_write(&priv->regs->gaddr6, 0); | |
721 | gfar_write(&priv->regs->gaddr7, 0); | |
722 | ||
1da177e4 | 723 | /* Zero out the rmon mib registers if it has them */ |
b31a1d8b | 724 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) { |
cc8c6e37 | 725 | memset_io(&(priv->regs->rmon), 0, sizeof (struct rmon_mib)); |
1da177e4 LT |
726 | |
727 | /* Mask off the CAM interrupts */ | |
728 | gfar_write(&priv->regs->rmon.cam1, 0xffffffff); | |
729 | gfar_write(&priv->regs->rmon.cam2, 0xffffffff); | |
730 | } | |
731 | ||
732 | /* Initialize the max receive buffer length */ | |
733 | gfar_write(&priv->regs->mrblr, priv->rx_buffer_size); | |
734 | ||
1da177e4 LT |
735 | /* Initialize the Minimum Frame Length Register */ |
736 | gfar_write(&priv->regs->minflr, MINFLR_INIT_SETTINGS); | |
1da177e4 LT |
737 | } |
738 | ||
0bbaf069 KG |
739 | |
740 | /* Halt the receive and transmit queues */ | |
d87eb127 | 741 | static void gfar_halt_nodisable(struct net_device *dev) |
1da177e4 LT |
742 | { |
743 | struct gfar_private *priv = netdev_priv(dev); | |
cc8c6e37 | 744 | struct gfar __iomem *regs = priv->regs; |
1da177e4 LT |
745 | u32 tempval; |
746 | ||
1da177e4 LT |
747 | /* Mask all interrupts */ |
748 | gfar_write(®s->imask, IMASK_INIT_CLEAR); | |
749 | ||
750 | /* Clear all interrupts */ | |
751 | gfar_write(®s->ievent, IEVENT_INIT_CLEAR); | |
752 | ||
753 | /* Stop the DMA, and wait for it to stop */ | |
754 | tempval = gfar_read(&priv->regs->dmactrl); | |
755 | if ((tempval & (DMACTRL_GRS | DMACTRL_GTS)) | |
756 | != (DMACTRL_GRS | DMACTRL_GTS)) { | |
757 | tempval |= (DMACTRL_GRS | DMACTRL_GTS); | |
758 | gfar_write(&priv->regs->dmactrl, tempval); | |
759 | ||
760 | while (!(gfar_read(&priv->regs->ievent) & | |
761 | (IEVENT_GRSC | IEVENT_GTSC))) | |
762 | cpu_relax(); | |
763 | } | |
d87eb127 | 764 | } |
d87eb127 SW |
765 | |
766 | /* Halt the receive and transmit queues */ | |
767 | void gfar_halt(struct net_device *dev) | |
768 | { | |
769 | struct gfar_private *priv = netdev_priv(dev); | |
770 | struct gfar __iomem *regs = priv->regs; | |
771 | u32 tempval; | |
1da177e4 | 772 | |
2a54adc3 SW |
773 | gfar_halt_nodisable(dev); |
774 | ||
1da177e4 LT |
775 | /* Disable Rx and Tx */ |
776 | tempval = gfar_read(®s->maccfg1); | |
777 | tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN); | |
778 | gfar_write(®s->maccfg1, tempval); | |
0bbaf069 KG |
779 | } |
780 | ||
781 | void stop_gfar(struct net_device *dev) | |
782 | { | |
783 | struct gfar_private *priv = netdev_priv(dev); | |
cc8c6e37 | 784 | struct gfar __iomem *regs = priv->regs; |
0bbaf069 KG |
785 | unsigned long flags; |
786 | ||
bb40dcbb AF |
787 | phy_stop(priv->phydev); |
788 | ||
0bbaf069 | 789 | /* Lock it down */ |
fef6108d AF |
790 | spin_lock_irqsave(&priv->txlock, flags); |
791 | spin_lock(&priv->rxlock); | |
0bbaf069 | 792 | |
0bbaf069 | 793 | gfar_halt(dev); |
1da177e4 | 794 | |
fef6108d AF |
795 | spin_unlock(&priv->rxlock); |
796 | spin_unlock_irqrestore(&priv->txlock, flags); | |
1da177e4 LT |
797 | |
798 | /* Free the IRQs */ | |
b31a1d8b | 799 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
1da177e4 LT |
800 | free_irq(priv->interruptError, dev); |
801 | free_irq(priv->interruptTransmit, dev); | |
802 | free_irq(priv->interruptReceive, dev); | |
803 | } else { | |
bb40dcbb | 804 | free_irq(priv->interruptTransmit, dev); |
1da177e4 LT |
805 | } |
806 | ||
807 | free_skb_resources(priv); | |
808 | ||
cf782298 | 809 | dma_free_coherent(&dev->dev, |
1da177e4 LT |
810 | sizeof(struct txbd8)*priv->tx_ring_size |
811 | + sizeof(struct rxbd8)*priv->rx_ring_size, | |
812 | priv->tx_bd_base, | |
0bbaf069 | 813 | gfar_read(®s->tbase0)); |
1da177e4 LT |
814 | } |
815 | ||
816 | /* If there are any tx skbs or rx skbs still around, free them. | |
817 | * Then free tx_skbuff and rx_skbuff */ | |
bb40dcbb | 818 | static void free_skb_resources(struct gfar_private *priv) |
1da177e4 LT |
819 | { |
820 | struct rxbd8 *rxbdp; | |
821 | struct txbd8 *txbdp; | |
822 | int i; | |
823 | ||
824 | /* Go through all the buffer descriptors and free their data buffers */ | |
825 | txbdp = priv->tx_bd_base; | |
826 | ||
827 | for (i = 0; i < priv->tx_ring_size; i++) { | |
828 | ||
829 | if (priv->tx_skbuff[i]) { | |
cf782298 | 830 | dma_unmap_single(&priv->dev->dev, txbdp->bufPtr, |
1da177e4 LT |
831 | txbdp->length, |
832 | DMA_TO_DEVICE); | |
833 | dev_kfree_skb_any(priv->tx_skbuff[i]); | |
834 | priv->tx_skbuff[i] = NULL; | |
835 | } | |
ad5da7ab AF |
836 | |
837 | txbdp++; | |
1da177e4 LT |
838 | } |
839 | ||
840 | kfree(priv->tx_skbuff); | |
841 | ||
842 | rxbdp = priv->rx_bd_base; | |
843 | ||
844 | /* rx_skbuff is not guaranteed to be allocated, so only | |
845 | * free it and its contents if it is allocated */ | |
846 | if(priv->rx_skbuff != NULL) { | |
847 | for (i = 0; i < priv->rx_ring_size; i++) { | |
848 | if (priv->rx_skbuff[i]) { | |
cf782298 | 849 | dma_unmap_single(&priv->dev->dev, rxbdp->bufPtr, |
7f7f5316 | 850 | priv->rx_buffer_size, |
1da177e4 LT |
851 | DMA_FROM_DEVICE); |
852 | ||
853 | dev_kfree_skb_any(priv->rx_skbuff[i]); | |
854 | priv->rx_skbuff[i] = NULL; | |
855 | } | |
856 | ||
857 | rxbdp->status = 0; | |
858 | rxbdp->length = 0; | |
859 | rxbdp->bufPtr = 0; | |
860 | ||
861 | rxbdp++; | |
862 | } | |
863 | ||
864 | kfree(priv->rx_skbuff); | |
865 | } | |
866 | } | |
867 | ||
0bbaf069 KG |
868 | void gfar_start(struct net_device *dev) |
869 | { | |
870 | struct gfar_private *priv = netdev_priv(dev); | |
cc8c6e37 | 871 | struct gfar __iomem *regs = priv->regs; |
0bbaf069 KG |
872 | u32 tempval; |
873 | ||
874 | /* Enable Rx and Tx in MACCFG1 */ | |
875 | tempval = gfar_read(®s->maccfg1); | |
876 | tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN); | |
877 | gfar_write(®s->maccfg1, tempval); | |
878 | ||
879 | /* Initialize DMACTRL to have WWR and WOP */ | |
880 | tempval = gfar_read(&priv->regs->dmactrl); | |
881 | tempval |= DMACTRL_INIT_SETTINGS; | |
882 | gfar_write(&priv->regs->dmactrl, tempval); | |
883 | ||
0bbaf069 KG |
884 | /* Make sure we aren't stopped */ |
885 | tempval = gfar_read(&priv->regs->dmactrl); | |
886 | tempval &= ~(DMACTRL_GRS | DMACTRL_GTS); | |
887 | gfar_write(&priv->regs->dmactrl, tempval); | |
888 | ||
fef6108d AF |
889 | /* Clear THLT/RHLT, so that the DMA starts polling now */ |
890 | gfar_write(®s->tstat, TSTAT_CLEAR_THALT); | |
891 | gfar_write(®s->rstat, RSTAT_CLEAR_RHALT); | |
892 | ||
0bbaf069 KG |
893 | /* Unmask the interrupts we look for */ |
894 | gfar_write(®s->imask, IMASK_DEFAULT); | |
12dea57b DH |
895 | |
896 | dev->trans_start = jiffies; | |
0bbaf069 KG |
897 | } |
898 | ||
1da177e4 LT |
899 | /* Bring the controller up and running */ |
900 | int startup_gfar(struct net_device *dev) | |
901 | { | |
902 | struct txbd8 *txbdp; | |
903 | struct rxbd8 *rxbdp; | |
f9663aea | 904 | dma_addr_t addr = 0; |
1da177e4 LT |
905 | unsigned long vaddr; |
906 | int i; | |
907 | struct gfar_private *priv = netdev_priv(dev); | |
cc8c6e37 | 908 | struct gfar __iomem *regs = priv->regs; |
1da177e4 | 909 | int err = 0; |
0bbaf069 | 910 | u32 rctrl = 0; |
7f7f5316 | 911 | u32 attrs = 0; |
1da177e4 LT |
912 | |
913 | gfar_write(®s->imask, IMASK_INIT_CLEAR); | |
914 | ||
915 | /* Allocate memory for the buffer descriptors */ | |
cf782298 | 916 | vaddr = (unsigned long) dma_alloc_coherent(&dev->dev, |
1da177e4 LT |
917 | sizeof (struct txbd8) * priv->tx_ring_size + |
918 | sizeof (struct rxbd8) * priv->rx_ring_size, | |
919 | &addr, GFP_KERNEL); | |
920 | ||
921 | if (vaddr == 0) { | |
0bbaf069 KG |
922 | if (netif_msg_ifup(priv)) |
923 | printk(KERN_ERR "%s: Could not allocate buffer descriptors!\n", | |
924 | dev->name); | |
1da177e4 LT |
925 | return -ENOMEM; |
926 | } | |
927 | ||
928 | priv->tx_bd_base = (struct txbd8 *) vaddr; | |
929 | ||
930 | /* enet DMA only understands physical addresses */ | |
0bbaf069 | 931 | gfar_write(®s->tbase0, addr); |
1da177e4 LT |
932 | |
933 | /* Start the rx descriptor ring where the tx ring leaves off */ | |
934 | addr = addr + sizeof (struct txbd8) * priv->tx_ring_size; | |
935 | vaddr = vaddr + sizeof (struct txbd8) * priv->tx_ring_size; | |
936 | priv->rx_bd_base = (struct rxbd8 *) vaddr; | |
0bbaf069 | 937 | gfar_write(®s->rbase0, addr); |
1da177e4 LT |
938 | |
939 | /* Setup the skbuff rings */ | |
940 | priv->tx_skbuff = | |
941 | (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) * | |
942 | priv->tx_ring_size, GFP_KERNEL); | |
943 | ||
bb40dcbb | 944 | if (NULL == priv->tx_skbuff) { |
0bbaf069 KG |
945 | if (netif_msg_ifup(priv)) |
946 | printk(KERN_ERR "%s: Could not allocate tx_skbuff\n", | |
947 | dev->name); | |
1da177e4 LT |
948 | err = -ENOMEM; |
949 | goto tx_skb_fail; | |
950 | } | |
951 | ||
952 | for (i = 0; i < priv->tx_ring_size; i++) | |
953 | priv->tx_skbuff[i] = NULL; | |
954 | ||
955 | priv->rx_skbuff = | |
956 | (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) * | |
957 | priv->rx_ring_size, GFP_KERNEL); | |
958 | ||
bb40dcbb | 959 | if (NULL == priv->rx_skbuff) { |
0bbaf069 KG |
960 | if (netif_msg_ifup(priv)) |
961 | printk(KERN_ERR "%s: Could not allocate rx_skbuff\n", | |
962 | dev->name); | |
1da177e4 LT |
963 | err = -ENOMEM; |
964 | goto rx_skb_fail; | |
965 | } | |
966 | ||
967 | for (i = 0; i < priv->rx_ring_size; i++) | |
968 | priv->rx_skbuff[i] = NULL; | |
969 | ||
970 | /* Initialize some variables in our dev structure */ | |
971 | priv->dirty_tx = priv->cur_tx = priv->tx_bd_base; | |
972 | priv->cur_rx = priv->rx_bd_base; | |
973 | priv->skb_curtx = priv->skb_dirtytx = 0; | |
974 | priv->skb_currx = 0; | |
975 | ||
976 | /* Initialize Transmit Descriptor Ring */ | |
977 | txbdp = priv->tx_bd_base; | |
978 | for (i = 0; i < priv->tx_ring_size; i++) { | |
979 | txbdp->status = 0; | |
980 | txbdp->length = 0; | |
981 | txbdp->bufPtr = 0; | |
982 | txbdp++; | |
983 | } | |
984 | ||
985 | /* Set the last descriptor in the ring to indicate wrap */ | |
986 | txbdp--; | |
987 | txbdp->status |= TXBD_WRAP; | |
988 | ||
989 | rxbdp = priv->rx_bd_base; | |
990 | for (i = 0; i < priv->rx_ring_size; i++) { | |
815b97c6 | 991 | struct sk_buff *skb; |
1da177e4 | 992 | |
815b97c6 | 993 | skb = gfar_new_skb(dev); |
1da177e4 | 994 | |
815b97c6 AF |
995 | if (!skb) { |
996 | printk(KERN_ERR "%s: Can't allocate RX buffers\n", | |
997 | dev->name); | |
998 | ||
999 | goto err_rxalloc_fail; | |
1000 | } | |
1da177e4 LT |
1001 | |
1002 | priv->rx_skbuff[i] = skb; | |
1003 | ||
815b97c6 AF |
1004 | gfar_new_rxbdp(dev, rxbdp, skb); |
1005 | ||
1da177e4 LT |
1006 | rxbdp++; |
1007 | } | |
1008 | ||
1009 | /* Set the last descriptor in the ring to wrap */ | |
1010 | rxbdp--; | |
1011 | rxbdp->status |= RXBD_WRAP; | |
1012 | ||
1013 | /* If the device has multiple interrupts, register for | |
1014 | * them. Otherwise, only register for the one */ | |
b31a1d8b | 1015 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
0bbaf069 | 1016 | /* Install our interrupt handlers for Error, |
1da177e4 LT |
1017 | * Transmit, and Receive */ |
1018 | if (request_irq(priv->interruptError, gfar_error, | |
1019 | 0, "enet_error", dev) < 0) { | |
0bbaf069 KG |
1020 | if (netif_msg_intr(priv)) |
1021 | printk(KERN_ERR "%s: Can't get IRQ %d\n", | |
1022 | dev->name, priv->interruptError); | |
1da177e4 LT |
1023 | |
1024 | err = -1; | |
1025 | goto err_irq_fail; | |
1026 | } | |
1027 | ||
1028 | if (request_irq(priv->interruptTransmit, gfar_transmit, | |
1029 | 0, "enet_tx", dev) < 0) { | |
0bbaf069 KG |
1030 | if (netif_msg_intr(priv)) |
1031 | printk(KERN_ERR "%s: Can't get IRQ %d\n", | |
1032 | dev->name, priv->interruptTransmit); | |
1da177e4 LT |
1033 | |
1034 | err = -1; | |
1035 | ||
1036 | goto tx_irq_fail; | |
1037 | } | |
1038 | ||
1039 | if (request_irq(priv->interruptReceive, gfar_receive, | |
1040 | 0, "enet_rx", dev) < 0) { | |
0bbaf069 KG |
1041 | if (netif_msg_intr(priv)) |
1042 | printk(KERN_ERR "%s: Can't get IRQ %d (receive0)\n", | |
1043 | dev->name, priv->interruptReceive); | |
1da177e4 LT |
1044 | |
1045 | err = -1; | |
1046 | goto rx_irq_fail; | |
1047 | } | |
1048 | } else { | |
1049 | if (request_irq(priv->interruptTransmit, gfar_interrupt, | |
1050 | 0, "gfar_interrupt", dev) < 0) { | |
0bbaf069 KG |
1051 | if (netif_msg_intr(priv)) |
1052 | printk(KERN_ERR "%s: Can't get IRQ %d\n", | |
1053 | dev->name, priv->interruptError); | |
1da177e4 LT |
1054 | |
1055 | err = -1; | |
1056 | goto err_irq_fail; | |
1057 | } | |
1058 | } | |
1059 | ||
bb40dcbb | 1060 | phy_start(priv->phydev); |
1da177e4 LT |
1061 | |
1062 | /* Configure the coalescing support */ | |
b46a8454 | 1063 | gfar_write(®s->txic, 0); |
1da177e4 | 1064 | if (priv->txcoalescing) |
b46a8454 | 1065 | gfar_write(®s->txic, priv->txic); |
1da177e4 | 1066 | |
b46a8454 | 1067 | gfar_write(®s->rxic, 0); |
1da177e4 | 1068 | if (priv->rxcoalescing) |
b46a8454 | 1069 | gfar_write(®s->rxic, priv->rxic); |
1da177e4 | 1070 | |
0bbaf069 KG |
1071 | if (priv->rx_csum_enable) |
1072 | rctrl |= RCTRL_CHECKSUMMING; | |
1da177e4 | 1073 | |
7f7f5316 | 1074 | if (priv->extended_hash) { |
0bbaf069 | 1075 | rctrl |= RCTRL_EXTHASH; |
1da177e4 | 1076 | |
7f7f5316 AF |
1077 | gfar_clear_exact_match(dev); |
1078 | rctrl |= RCTRL_EMEN; | |
1079 | } | |
1080 | ||
7f7f5316 AF |
1081 | if (priv->padding) { |
1082 | rctrl &= ~RCTRL_PAL_MASK; | |
1083 | rctrl |= RCTRL_PADDING(priv->padding); | |
1084 | } | |
1085 | ||
0bbaf069 KG |
1086 | /* Init rctrl based on our settings */ |
1087 | gfar_write(&priv->regs->rctrl, rctrl); | |
1da177e4 | 1088 | |
0bbaf069 KG |
1089 | if (dev->features & NETIF_F_IP_CSUM) |
1090 | gfar_write(&priv->regs->tctrl, TCTRL_INIT_CSUM); | |
1da177e4 | 1091 | |
7f7f5316 AF |
1092 | /* Set the extraction length and index */ |
1093 | attrs = ATTRELI_EL(priv->rx_stash_size) | | |
1094 | ATTRELI_EI(priv->rx_stash_index); | |
1095 | ||
1096 | gfar_write(&priv->regs->attreli, attrs); | |
1097 | ||
1098 | /* Start with defaults, and add stashing or locking | |
1099 | * depending on the approprate variables */ | |
1100 | attrs = ATTR_INIT_SETTINGS; | |
1101 | ||
1102 | if (priv->bd_stash_en) | |
1103 | attrs |= ATTR_BDSTASH; | |
1104 | ||
1105 | if (priv->rx_stash_size != 0) | |
1106 | attrs |= ATTR_BUFSTASH; | |
1107 | ||
1108 | gfar_write(&priv->regs->attr, attrs); | |
1109 | ||
1110 | gfar_write(&priv->regs->fifo_tx_thr, priv->fifo_threshold); | |
1111 | gfar_write(&priv->regs->fifo_tx_starve, priv->fifo_starve); | |
1112 | gfar_write(&priv->regs->fifo_tx_starve_shutoff, priv->fifo_starve_off); | |
1113 | ||
1114 | /* Start the controller */ | |
0bbaf069 | 1115 | gfar_start(dev); |
1da177e4 LT |
1116 | |
1117 | return 0; | |
1118 | ||
1119 | rx_irq_fail: | |
1120 | free_irq(priv->interruptTransmit, dev); | |
1121 | tx_irq_fail: | |
1122 | free_irq(priv->interruptError, dev); | |
1123 | err_irq_fail: | |
7d2e3cb7 | 1124 | err_rxalloc_fail: |
1da177e4 LT |
1125 | rx_skb_fail: |
1126 | free_skb_resources(priv); | |
1127 | tx_skb_fail: | |
cf782298 | 1128 | dma_free_coherent(&dev->dev, |
1da177e4 LT |
1129 | sizeof(struct txbd8)*priv->tx_ring_size |
1130 | + sizeof(struct rxbd8)*priv->rx_ring_size, | |
1131 | priv->tx_bd_base, | |
0bbaf069 | 1132 | gfar_read(®s->tbase0)); |
1da177e4 | 1133 | |
1da177e4 LT |
1134 | return err; |
1135 | } | |
1136 | ||
1137 | /* Called when something needs to use the ethernet device */ | |
1138 | /* Returns 0 for success. */ | |
1139 | static int gfar_enet_open(struct net_device *dev) | |
1140 | { | |
94e8cc35 | 1141 | struct gfar_private *priv = netdev_priv(dev); |
1da177e4 LT |
1142 | int err; |
1143 | ||
bea3348e SH |
1144 | napi_enable(&priv->napi); |
1145 | ||
1da177e4 LT |
1146 | /* Initialize a bunch of registers */ |
1147 | init_registers(dev); | |
1148 | ||
1149 | gfar_set_mac_address(dev); | |
1150 | ||
1151 | err = init_phy(dev); | |
1152 | ||
bea3348e SH |
1153 | if(err) { |
1154 | napi_disable(&priv->napi); | |
1da177e4 | 1155 | return err; |
bea3348e | 1156 | } |
1da177e4 LT |
1157 | |
1158 | err = startup_gfar(dev); | |
db0e8e3f | 1159 | if (err) { |
bea3348e | 1160 | napi_disable(&priv->napi); |
db0e8e3f AV |
1161 | return err; |
1162 | } | |
1da177e4 LT |
1163 | |
1164 | netif_start_queue(dev); | |
1165 | ||
1166 | return err; | |
1167 | } | |
1168 | ||
a22823e7 | 1169 | static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb) |
0bbaf069 KG |
1170 | { |
1171 | struct txfcb *fcb = (struct txfcb *)skb_push (skb, GMAC_FCB_LEN); | |
1172 | ||
a22823e7 | 1173 | cacheable_memzero(fcb, GMAC_FCB_LEN); |
0bbaf069 | 1174 | |
0bbaf069 KG |
1175 | return fcb; |
1176 | } | |
1177 | ||
1178 | static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb) | |
1179 | { | |
7f7f5316 | 1180 | u8 flags = 0; |
0bbaf069 KG |
1181 | |
1182 | /* If we're here, it's a IP packet with a TCP or UDP | |
1183 | * payload. We set it to checksum, using a pseudo-header | |
1184 | * we provide | |
1185 | */ | |
7f7f5316 | 1186 | flags = TXFCB_DEFAULT; |
0bbaf069 | 1187 | |
7f7f5316 AF |
1188 | /* Tell the controller what the protocol is */ |
1189 | /* And provide the already calculated phcs */ | |
eddc9ec5 | 1190 | if (ip_hdr(skb)->protocol == IPPROTO_UDP) { |
7f7f5316 | 1191 | flags |= TXFCB_UDP; |
4bedb452 | 1192 | fcb->phcs = udp_hdr(skb)->check; |
7f7f5316 | 1193 | } else |
8da32de5 | 1194 | fcb->phcs = tcp_hdr(skb)->check; |
0bbaf069 KG |
1195 | |
1196 | /* l3os is the distance between the start of the | |
1197 | * frame (skb->data) and the start of the IP hdr. | |
1198 | * l4os is the distance between the start of the | |
1199 | * l3 hdr and the l4 hdr */ | |
bbe735e4 | 1200 | fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN); |
cfe1fc77 | 1201 | fcb->l4os = skb_network_header_len(skb); |
0bbaf069 | 1202 | |
7f7f5316 | 1203 | fcb->flags = flags; |
0bbaf069 KG |
1204 | } |
1205 | ||
7f7f5316 | 1206 | void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb) |
0bbaf069 | 1207 | { |
7f7f5316 | 1208 | fcb->flags |= TXFCB_VLN; |
0bbaf069 KG |
1209 | fcb->vlctl = vlan_tx_tag_get(skb); |
1210 | } | |
1211 | ||
1da177e4 LT |
1212 | /* This is called by the kernel when a frame is ready for transmission. */ |
1213 | /* It is pointed to by the dev->hard_start_xmit function pointer */ | |
1214 | static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
1215 | { | |
1216 | struct gfar_private *priv = netdev_priv(dev); | |
0bbaf069 | 1217 | struct txfcb *fcb = NULL; |
1da177e4 | 1218 | struct txbd8 *txbdp; |
7f7f5316 | 1219 | u16 status; |
fef6108d | 1220 | unsigned long flags; |
1da177e4 LT |
1221 | |
1222 | /* Update transmit stats */ | |
09f75cd7 | 1223 | dev->stats.tx_bytes += skb->len; |
1da177e4 LT |
1224 | |
1225 | /* Lock priv now */ | |
fef6108d | 1226 | spin_lock_irqsave(&priv->txlock, flags); |
1da177e4 LT |
1227 | |
1228 | /* Point at the first free tx descriptor */ | |
1229 | txbdp = priv->cur_tx; | |
1230 | ||
1231 | /* Clear all but the WRAP status flags */ | |
7f7f5316 | 1232 | status = txbdp->status & TXBD_WRAP; |
1da177e4 | 1233 | |
0bbaf069 | 1234 | /* Set up checksumming */ |
12dea57b | 1235 | if (CHECKSUM_PARTIAL == skb->ip_summed) { |
a22823e7 | 1236 | fcb = gfar_add_fcb(skb); |
7f7f5316 | 1237 | status |= TXBD_TOE; |
0bbaf069 KG |
1238 | gfar_tx_checksum(skb, fcb); |
1239 | } | |
1240 | ||
77ecaf2d | 1241 | if (priv->vlgrp && vlan_tx_tag_present(skb)) { |
7f7f5316 | 1242 | if (unlikely(NULL == fcb)) { |
a22823e7 | 1243 | fcb = gfar_add_fcb(skb); |
7f7f5316 AF |
1244 | status |= TXBD_TOE; |
1245 | } | |
0bbaf069 KG |
1246 | |
1247 | gfar_tx_vlan(skb, fcb); | |
1248 | } | |
1249 | ||
1da177e4 LT |
1250 | /* Set buffer length and pointer */ |
1251 | txbdp->length = skb->len; | |
cf782298 | 1252 | txbdp->bufPtr = dma_map_single(&dev->dev, skb->data, |
1da177e4 LT |
1253 | skb->len, DMA_TO_DEVICE); |
1254 | ||
1255 | /* Save the skb pointer so we can free it later */ | |
1256 | priv->tx_skbuff[priv->skb_curtx] = skb; | |
1257 | ||
1258 | /* Update the current skb pointer (wrapping if this was the last) */ | |
1259 | priv->skb_curtx = | |
1260 | (priv->skb_curtx + 1) & TX_RING_MOD_MASK(priv->tx_ring_size); | |
1261 | ||
1262 | /* Flag the BD as interrupt-causing */ | |
7f7f5316 | 1263 | status |= TXBD_INTERRUPT; |
1da177e4 LT |
1264 | |
1265 | /* Flag the BD as ready to go, last in frame, and */ | |
1266 | /* in need of CRC */ | |
7f7f5316 | 1267 | status |= (TXBD_READY | TXBD_LAST | TXBD_CRC); |
1da177e4 LT |
1268 | |
1269 | dev->trans_start = jiffies; | |
1270 | ||
3b6330ce SW |
1271 | /* The powerpc-specific eieio() is used, as wmb() has too strong |
1272 | * semantics (it requires synchronization between cacheable and | |
1273 | * uncacheable mappings, which eieio doesn't provide and which we | |
1274 | * don't need), thus requiring a more expensive sync instruction. At | |
1275 | * some point, the set of architecture-independent barrier functions | |
1276 | * should be expanded to include weaker barriers. | |
1277 | */ | |
1278 | ||
1279 | eieio(); | |
7f7f5316 AF |
1280 | txbdp->status = status; |
1281 | ||
1da177e4 LT |
1282 | /* If this was the last BD in the ring, the next one */ |
1283 | /* is at the beginning of the ring */ | |
1284 | if (txbdp->status & TXBD_WRAP) | |
1285 | txbdp = priv->tx_bd_base; | |
1286 | else | |
1287 | txbdp++; | |
1288 | ||
1289 | /* If the next BD still needs to be cleaned up, then the bds | |
1290 | are full. We need to tell the kernel to stop sending us stuff. */ | |
1291 | if (txbdp == priv->dirty_tx) { | |
1292 | netif_stop_queue(dev); | |
1293 | ||
09f75cd7 | 1294 | dev->stats.tx_fifo_errors++; |
1da177e4 LT |
1295 | } |
1296 | ||
1297 | /* Update the current txbd to the next one */ | |
1298 | priv->cur_tx = txbdp; | |
1299 | ||
1300 | /* Tell the DMA to go go go */ | |
1301 | gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT); | |
1302 | ||
1303 | /* Unlock priv */ | |
fef6108d | 1304 | spin_unlock_irqrestore(&priv->txlock, flags); |
1da177e4 LT |
1305 | |
1306 | return 0; | |
1307 | } | |
1308 | ||
1309 | /* Stops the kernel queue, and halts the controller */ | |
1310 | static int gfar_close(struct net_device *dev) | |
1311 | { | |
1312 | struct gfar_private *priv = netdev_priv(dev); | |
bea3348e SH |
1313 | |
1314 | napi_disable(&priv->napi); | |
1315 | ||
ab939905 | 1316 | cancel_work_sync(&priv->reset_task); |
1da177e4 LT |
1317 | stop_gfar(dev); |
1318 | ||
bb40dcbb AF |
1319 | /* Disconnect from the PHY */ |
1320 | phy_disconnect(priv->phydev); | |
1321 | priv->phydev = NULL; | |
1da177e4 LT |
1322 | |
1323 | netif_stop_queue(dev); | |
1324 | ||
1325 | return 0; | |
1326 | } | |
1327 | ||
1da177e4 | 1328 | /* Changes the mac address if the controller is not running. */ |
f162b9d5 | 1329 | static int gfar_set_mac_address(struct net_device *dev) |
1da177e4 | 1330 | { |
7f7f5316 | 1331 | gfar_set_mac_for_addr(dev, 0, dev->dev_addr); |
1da177e4 LT |
1332 | |
1333 | return 0; | |
1334 | } | |
1335 | ||
1336 | ||
0bbaf069 KG |
1337 | /* Enables and disables VLAN insertion/extraction */ |
1338 | static void gfar_vlan_rx_register(struct net_device *dev, | |
1339 | struct vlan_group *grp) | |
1340 | { | |
1341 | struct gfar_private *priv = netdev_priv(dev); | |
1342 | unsigned long flags; | |
77ecaf2d | 1343 | struct vlan_group *old_grp; |
0bbaf069 KG |
1344 | u32 tempval; |
1345 | ||
fef6108d | 1346 | spin_lock_irqsave(&priv->rxlock, flags); |
0bbaf069 | 1347 | |
77ecaf2d DH |
1348 | old_grp = priv->vlgrp; |
1349 | ||
1350 | if (old_grp == grp) | |
1351 | return; | |
0bbaf069 KG |
1352 | |
1353 | if (grp) { | |
1354 | /* Enable VLAN tag insertion */ | |
1355 | tempval = gfar_read(&priv->regs->tctrl); | |
1356 | tempval |= TCTRL_VLINS; | |
1357 | ||
1358 | gfar_write(&priv->regs->tctrl, tempval); | |
6aa20a22 | 1359 | |
0bbaf069 KG |
1360 | /* Enable VLAN tag extraction */ |
1361 | tempval = gfar_read(&priv->regs->rctrl); | |
1362 | tempval |= RCTRL_VLEX; | |
77ecaf2d | 1363 | tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT); |
0bbaf069 KG |
1364 | gfar_write(&priv->regs->rctrl, tempval); |
1365 | } else { | |
1366 | /* Disable VLAN tag insertion */ | |
1367 | tempval = gfar_read(&priv->regs->tctrl); | |
1368 | tempval &= ~TCTRL_VLINS; | |
1369 | gfar_write(&priv->regs->tctrl, tempval); | |
1370 | ||
1371 | /* Disable VLAN tag extraction */ | |
1372 | tempval = gfar_read(&priv->regs->rctrl); | |
1373 | tempval &= ~RCTRL_VLEX; | |
77ecaf2d DH |
1374 | /* If parse is no longer required, then disable parser */ |
1375 | if (tempval & RCTRL_REQ_PARSER) | |
1376 | tempval |= RCTRL_PRSDEP_INIT; | |
1377 | else | |
1378 | tempval &= ~RCTRL_PRSDEP_INIT; | |
0bbaf069 KG |
1379 | gfar_write(&priv->regs->rctrl, tempval); |
1380 | } | |
1381 | ||
77ecaf2d DH |
1382 | gfar_change_mtu(dev, dev->mtu); |
1383 | ||
fef6108d | 1384 | spin_unlock_irqrestore(&priv->rxlock, flags); |
0bbaf069 KG |
1385 | } |
1386 | ||
1da177e4 LT |
1387 | static int gfar_change_mtu(struct net_device *dev, int new_mtu) |
1388 | { | |
1389 | int tempsize, tempval; | |
1390 | struct gfar_private *priv = netdev_priv(dev); | |
1391 | int oldsize = priv->rx_buffer_size; | |
0bbaf069 KG |
1392 | int frame_size = new_mtu + ETH_HLEN; |
1393 | ||
77ecaf2d | 1394 | if (priv->vlgrp) |
faa89577 | 1395 | frame_size += VLAN_HLEN; |
0bbaf069 | 1396 | |
1da177e4 | 1397 | if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) { |
0bbaf069 KG |
1398 | if (netif_msg_drv(priv)) |
1399 | printk(KERN_ERR "%s: Invalid MTU setting\n", | |
1400 | dev->name); | |
1da177e4 LT |
1401 | return -EINVAL; |
1402 | } | |
1403 | ||
77ecaf2d DH |
1404 | if (gfar_uses_fcb(priv)) |
1405 | frame_size += GMAC_FCB_LEN; | |
1406 | ||
1407 | frame_size += priv->padding; | |
1408 | ||
1da177e4 LT |
1409 | tempsize = |
1410 | (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) + | |
1411 | INCREMENTAL_BUFFER_SIZE; | |
1412 | ||
1413 | /* Only stop and start the controller if it isn't already | |
7f7f5316 | 1414 | * stopped, and we changed something */ |
1da177e4 LT |
1415 | if ((oldsize != tempsize) && (dev->flags & IFF_UP)) |
1416 | stop_gfar(dev); | |
1417 | ||
1418 | priv->rx_buffer_size = tempsize; | |
1419 | ||
1420 | dev->mtu = new_mtu; | |
1421 | ||
1422 | gfar_write(&priv->regs->mrblr, priv->rx_buffer_size); | |
1423 | gfar_write(&priv->regs->maxfrm, priv->rx_buffer_size); | |
1424 | ||
1425 | /* If the mtu is larger than the max size for standard | |
1426 | * ethernet frames (ie, a jumbo frame), then set maccfg2 | |
1427 | * to allow huge frames, and to check the length */ | |
1428 | tempval = gfar_read(&priv->regs->maccfg2); | |
1429 | ||
1430 | if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE) | |
1431 | tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK); | |
1432 | else | |
1433 | tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK); | |
1434 | ||
1435 | gfar_write(&priv->regs->maccfg2, tempval); | |
1436 | ||
1437 | if ((oldsize != tempsize) && (dev->flags & IFF_UP)) | |
1438 | startup_gfar(dev); | |
1439 | ||
1440 | return 0; | |
1441 | } | |
1442 | ||
ab939905 | 1443 | /* gfar_reset_task gets scheduled when a packet has not been |
1da177e4 LT |
1444 | * transmitted after a set amount of time. |
1445 | * For now, assume that clearing out all the structures, and | |
ab939905 SS |
1446 | * starting over will fix the problem. |
1447 | */ | |
1448 | static void gfar_reset_task(struct work_struct *work) | |
1da177e4 | 1449 | { |
ab939905 SS |
1450 | struct gfar_private *priv = container_of(work, struct gfar_private, |
1451 | reset_task); | |
1452 | struct net_device *dev = priv->dev; | |
1da177e4 LT |
1453 | |
1454 | if (dev->flags & IFF_UP) { | |
1455 | stop_gfar(dev); | |
1456 | startup_gfar(dev); | |
1457 | } | |
1458 | ||
263ba320 | 1459 | netif_tx_schedule_all(dev); |
1da177e4 LT |
1460 | } |
1461 | ||
ab939905 SS |
1462 | static void gfar_timeout(struct net_device *dev) |
1463 | { | |
1464 | struct gfar_private *priv = netdev_priv(dev); | |
1465 | ||
1466 | dev->stats.tx_errors++; | |
1467 | schedule_work(&priv->reset_task); | |
1468 | } | |
1469 | ||
1da177e4 | 1470 | /* Interrupt Handler for Transmit complete */ |
f162b9d5 | 1471 | static int gfar_clean_tx_ring(struct net_device *dev) |
1da177e4 | 1472 | { |
1da177e4 | 1473 | struct txbd8 *bdp; |
d080cd63 DH |
1474 | struct gfar_private *priv = netdev_priv(dev); |
1475 | int howmany = 0; | |
1da177e4 | 1476 | |
1da177e4 LT |
1477 | bdp = priv->dirty_tx; |
1478 | while ((bdp->status & TXBD_READY) == 0) { | |
1479 | /* If dirty_tx and cur_tx are the same, then either the */ | |
1480 | /* ring is empty or full now (it could only be full in the beginning, */ | |
1481 | /* obviously). If it is empty, we are done. */ | |
1482 | if ((bdp == priv->cur_tx) && (netif_queue_stopped(dev) == 0)) | |
1483 | break; | |
1484 | ||
d080cd63 | 1485 | howmany++; |
1da177e4 LT |
1486 | |
1487 | /* Deferred means some collisions occurred during transmit, */ | |
1488 | /* but we eventually sent the packet. */ | |
1489 | if (bdp->status & TXBD_DEF) | |
09f75cd7 | 1490 | dev->stats.collisions++; |
1da177e4 | 1491 | |
81183059 AF |
1492 | /* Unmap the DMA memory */ |
1493 | dma_unmap_single(&priv->dev->dev, bdp->bufPtr, | |
1494 | bdp->length, DMA_TO_DEVICE); | |
1495 | ||
1da177e4 LT |
1496 | /* Free the sk buffer associated with this TxBD */ |
1497 | dev_kfree_skb_irq(priv->tx_skbuff[priv->skb_dirtytx]); | |
d080cd63 | 1498 | |
1da177e4 LT |
1499 | priv->tx_skbuff[priv->skb_dirtytx] = NULL; |
1500 | priv->skb_dirtytx = | |
1501 | (priv->skb_dirtytx + | |
1502 | 1) & TX_RING_MOD_MASK(priv->tx_ring_size); | |
1503 | ||
d080cd63 DH |
1504 | /* Clean BD length for empty detection */ |
1505 | bdp->length = 0; | |
1506 | ||
1da177e4 LT |
1507 | /* update bdp to point at next bd in the ring (wrapping if necessary) */ |
1508 | if (bdp->status & TXBD_WRAP) | |
1509 | bdp = priv->tx_bd_base; | |
1510 | else | |
1511 | bdp++; | |
1512 | ||
1513 | /* Move dirty_tx to be the next bd */ | |
1514 | priv->dirty_tx = bdp; | |
1515 | ||
1516 | /* We freed a buffer, so now we can restart transmission */ | |
1517 | if (netif_queue_stopped(dev)) | |
1518 | netif_wake_queue(dev); | |
1519 | } /* while ((bdp->status & TXBD_READY) == 0) */ | |
1520 | ||
d080cd63 DH |
1521 | dev->stats.tx_packets += howmany; |
1522 | ||
1523 | return howmany; | |
1524 | } | |
1525 | ||
1526 | /* Interrupt Handler for Transmit complete */ | |
1527 | static irqreturn_t gfar_transmit(int irq, void *dev_id) | |
1528 | { | |
1529 | struct net_device *dev = (struct net_device *) dev_id; | |
1530 | struct gfar_private *priv = netdev_priv(dev); | |
1531 | ||
1532 | /* Clear IEVENT */ | |
1533 | gfar_write(&priv->regs->ievent, IEVENT_TX_MASK); | |
1534 | ||
1535 | /* Lock priv */ | |
1536 | spin_lock(&priv->txlock); | |
1537 | ||
1538 | gfar_clean_tx_ring(dev); | |
1539 | ||
1da177e4 LT |
1540 | /* If we are coalescing the interrupts, reset the timer */ |
1541 | /* Otherwise, clear it */ | |
2f448911 AF |
1542 | if (likely(priv->txcoalescing)) { |
1543 | gfar_write(&priv->regs->txic, 0); | |
b46a8454 | 1544 | gfar_write(&priv->regs->txic, priv->txic); |
2f448911 | 1545 | } |
1da177e4 | 1546 | |
fef6108d | 1547 | spin_unlock(&priv->txlock); |
1da177e4 LT |
1548 | |
1549 | return IRQ_HANDLED; | |
1550 | } | |
1551 | ||
815b97c6 AF |
1552 | static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp, |
1553 | struct sk_buff *skb) | |
1554 | { | |
1555 | struct gfar_private *priv = netdev_priv(dev); | |
1556 | u32 * status_len = (u32 *)bdp; | |
1557 | u16 flags; | |
1558 | ||
1559 | bdp->bufPtr = dma_map_single(&dev->dev, skb->data, | |
1560 | priv->rx_buffer_size, DMA_FROM_DEVICE); | |
1561 | ||
1562 | flags = RXBD_EMPTY | RXBD_INTERRUPT; | |
1563 | ||
1564 | if (bdp == priv->rx_bd_base + priv->rx_ring_size - 1) | |
1565 | flags |= RXBD_WRAP; | |
1566 | ||
1567 | eieio(); | |
1568 | ||
1569 | *status_len = (u32)flags << 16; | |
1570 | } | |
1571 | ||
1572 | ||
1573 | struct sk_buff * gfar_new_skb(struct net_device *dev) | |
1da177e4 | 1574 | { |
7f7f5316 | 1575 | unsigned int alignamount; |
1da177e4 LT |
1576 | struct gfar_private *priv = netdev_priv(dev); |
1577 | struct sk_buff *skb = NULL; | |
1da177e4 LT |
1578 | |
1579 | /* We have to allocate the skb, so keep trying till we succeed */ | |
815b97c6 | 1580 | skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT); |
1da177e4 | 1581 | |
815b97c6 | 1582 | if (!skb) |
1da177e4 LT |
1583 | return NULL; |
1584 | ||
7f7f5316 | 1585 | alignamount = RXBUF_ALIGNMENT - |
bea3348e | 1586 | (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1)); |
7f7f5316 | 1587 | |
1da177e4 LT |
1588 | /* We need the data buffer to be aligned properly. We will reserve |
1589 | * as many bytes as needed to align the data properly | |
1590 | */ | |
7f7f5316 | 1591 | skb_reserve(skb, alignamount); |
1da177e4 | 1592 | |
1da177e4 LT |
1593 | return skb; |
1594 | } | |
1595 | ||
298e1a9e | 1596 | static inline void count_errors(unsigned short status, struct net_device *dev) |
1da177e4 | 1597 | { |
298e1a9e | 1598 | struct gfar_private *priv = netdev_priv(dev); |
09f75cd7 | 1599 | struct net_device_stats *stats = &dev->stats; |
1da177e4 LT |
1600 | struct gfar_extra_stats *estats = &priv->extra_stats; |
1601 | ||
1602 | /* If the packet was truncated, none of the other errors | |
1603 | * matter */ | |
1604 | if (status & RXBD_TRUNCATED) { | |
1605 | stats->rx_length_errors++; | |
1606 | ||
1607 | estats->rx_trunc++; | |
1608 | ||
1609 | return; | |
1610 | } | |
1611 | /* Count the errors, if there were any */ | |
1612 | if (status & (RXBD_LARGE | RXBD_SHORT)) { | |
1613 | stats->rx_length_errors++; | |
1614 | ||
1615 | if (status & RXBD_LARGE) | |
1616 | estats->rx_large++; | |
1617 | else | |
1618 | estats->rx_short++; | |
1619 | } | |
1620 | if (status & RXBD_NONOCTET) { | |
1621 | stats->rx_frame_errors++; | |
1622 | estats->rx_nonoctet++; | |
1623 | } | |
1624 | if (status & RXBD_CRCERR) { | |
1625 | estats->rx_crcerr++; | |
1626 | stats->rx_crc_errors++; | |
1627 | } | |
1628 | if (status & RXBD_OVERRUN) { | |
1629 | estats->rx_overrun++; | |
1630 | stats->rx_crc_errors++; | |
1631 | } | |
1632 | } | |
1633 | ||
7d12e780 | 1634 | irqreturn_t gfar_receive(int irq, void *dev_id) |
1da177e4 LT |
1635 | { |
1636 | struct net_device *dev = (struct net_device *) dev_id; | |
1637 | struct gfar_private *priv = netdev_priv(dev); | |
1da177e4 | 1638 | u32 tempval; |
1da177e4 | 1639 | |
1da177e4 | 1640 | /* support NAPI */ |
d080cd63 DH |
1641 | /* Clear IEVENT, so interrupts aren't called again |
1642 | * because of the packets that have already arrived */ | |
1643 | gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK); | |
1644 | ||
bea3348e | 1645 | if (netif_rx_schedule_prep(dev, &priv->napi)) { |
1da177e4 | 1646 | tempval = gfar_read(&priv->regs->imask); |
d080cd63 | 1647 | tempval &= IMASK_RTX_DISABLED; |
1da177e4 LT |
1648 | gfar_write(&priv->regs->imask, tempval); |
1649 | ||
bea3348e | 1650 | __netif_rx_schedule(dev, &priv->napi); |
1da177e4 | 1651 | } else { |
0bbaf069 KG |
1652 | if (netif_msg_rx_err(priv)) |
1653 | printk(KERN_DEBUG "%s: receive called twice (%x)[%x]\n", | |
1654 | dev->name, gfar_read(&priv->regs->ievent), | |
1655 | gfar_read(&priv->regs->imask)); | |
1da177e4 | 1656 | } |
1da177e4 LT |
1657 | |
1658 | return IRQ_HANDLED; | |
1659 | } | |
1660 | ||
0bbaf069 KG |
1661 | static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb) |
1662 | { | |
1663 | /* If valid headers were found, and valid sums | |
1664 | * were verified, then we tell the kernel that no | |
1665 | * checksumming is necessary. Otherwise, it is */ | |
7f7f5316 | 1666 | if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU)) |
0bbaf069 KG |
1667 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
1668 | else | |
1669 | skb->ip_summed = CHECKSUM_NONE; | |
1670 | } | |
1671 | ||
1672 | ||
1da177e4 LT |
1673 | /* gfar_process_frame() -- handle one incoming packet if skb |
1674 | * isn't NULL. */ | |
1675 | static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb, | |
2c2db48a | 1676 | int amount_pull) |
1da177e4 LT |
1677 | { |
1678 | struct gfar_private *priv = netdev_priv(dev); | |
0bbaf069 | 1679 | struct rxfcb *fcb = NULL; |
1da177e4 | 1680 | |
2c2db48a | 1681 | int ret; |
1da177e4 | 1682 | |
2c2db48a DH |
1683 | /* fcb is at the beginning if exists */ |
1684 | fcb = (struct rxfcb *)skb->data; | |
0bbaf069 | 1685 | |
2c2db48a DH |
1686 | /* Remove the FCB from the skb */ |
1687 | /* Remove the padded bytes, if there are any */ | |
1688 | if (amount_pull) | |
1689 | skb_pull(skb, amount_pull); | |
0bbaf069 | 1690 | |
2c2db48a DH |
1691 | if (priv->rx_csum_enable) |
1692 | gfar_rx_checksum(skb, fcb); | |
0bbaf069 | 1693 | |
2c2db48a DH |
1694 | /* Tell the skb what kind of packet this is */ |
1695 | skb->protocol = eth_type_trans(skb, dev); | |
1da177e4 | 1696 | |
2c2db48a DH |
1697 | /* Send the packet up the stack */ |
1698 | if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN))) | |
1699 | ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp, fcb->vlctl); | |
1700 | else | |
1701 | ret = netif_receive_skb(skb); | |
0bbaf069 | 1702 | |
2c2db48a DH |
1703 | if (NET_RX_DROP == ret) |
1704 | priv->extra_stats.kernel_dropped++; | |
1da177e4 LT |
1705 | |
1706 | return 0; | |
1707 | } | |
1708 | ||
1709 | /* gfar_clean_rx_ring() -- Processes each frame in the rx ring | |
0bbaf069 | 1710 | * until the budget/quota has been reached. Returns the number |
1da177e4 LT |
1711 | * of frames handled |
1712 | */ | |
0bbaf069 | 1713 | int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit) |
1da177e4 LT |
1714 | { |
1715 | struct rxbd8 *bdp; | |
1716 | struct sk_buff *skb; | |
2c2db48a DH |
1717 | int pkt_len; |
1718 | int amount_pull; | |
1da177e4 LT |
1719 | int howmany = 0; |
1720 | struct gfar_private *priv = netdev_priv(dev); | |
1721 | ||
1722 | /* Get the first full descriptor */ | |
1723 | bdp = priv->cur_rx; | |
1724 | ||
2c2db48a DH |
1725 | amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0) + |
1726 | priv->padding; | |
1727 | ||
1da177e4 | 1728 | while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) { |
815b97c6 | 1729 | struct sk_buff *newskb; |
3b6330ce | 1730 | rmb(); |
815b97c6 AF |
1731 | |
1732 | /* Add another skb for the future */ | |
1733 | newskb = gfar_new_skb(dev); | |
1734 | ||
1da177e4 LT |
1735 | skb = priv->rx_skbuff[priv->skb_currx]; |
1736 | ||
81183059 AF |
1737 | dma_unmap_single(&priv->dev->dev, bdp->bufPtr, |
1738 | priv->rx_buffer_size, DMA_FROM_DEVICE); | |
1739 | ||
815b97c6 AF |
1740 | /* We drop the frame if we failed to allocate a new buffer */ |
1741 | if (unlikely(!newskb || !(bdp->status & RXBD_LAST) || | |
1742 | bdp->status & RXBD_ERR)) { | |
1743 | count_errors(bdp->status, dev); | |
1744 | ||
1745 | if (unlikely(!newskb)) | |
1746 | newskb = skb; | |
1747 | ||
81183059 | 1748 | if (skb) |
815b97c6 | 1749 | dev_kfree_skb_any(skb); |
815b97c6 | 1750 | } else { |
1da177e4 | 1751 | /* Increment the number of packets */ |
09f75cd7 | 1752 | dev->stats.rx_packets++; |
1da177e4 LT |
1753 | howmany++; |
1754 | ||
2c2db48a DH |
1755 | if (likely(skb)) { |
1756 | pkt_len = bdp->length - ETH_FCS_LEN; | |
1757 | /* Remove the FCS from the packet length */ | |
1758 | skb_put(skb, pkt_len); | |
1759 | dev->stats.rx_bytes += pkt_len; | |
1da177e4 | 1760 | |
2c2db48a DH |
1761 | gfar_process_frame(dev, skb, amount_pull); |
1762 | ||
1763 | } else { | |
1764 | if (netif_msg_rx_err(priv)) | |
1765 | printk(KERN_WARNING | |
1766 | "%s: Missing skb!\n", dev->name); | |
1767 | dev->stats.rx_dropped++; | |
1768 | priv->extra_stats.rx_skbmissing++; | |
1769 | } | |
1da177e4 | 1770 | |
1da177e4 LT |
1771 | } |
1772 | ||
815b97c6 | 1773 | priv->rx_skbuff[priv->skb_currx] = newskb; |
1da177e4 | 1774 | |
815b97c6 AF |
1775 | /* Setup the new bdp */ |
1776 | gfar_new_rxbdp(dev, bdp, newskb); | |
1da177e4 LT |
1777 | |
1778 | /* Update to the next pointer */ | |
1779 | if (bdp->status & RXBD_WRAP) | |
1780 | bdp = priv->rx_bd_base; | |
1781 | else | |
1782 | bdp++; | |
1783 | ||
1784 | /* update to point at the next skb */ | |
1785 | priv->skb_currx = | |
815b97c6 AF |
1786 | (priv->skb_currx + 1) & |
1787 | RX_RING_MOD_MASK(priv->rx_ring_size); | |
1da177e4 LT |
1788 | } |
1789 | ||
1790 | /* Update the current rxbd pointer to be the next one */ | |
1791 | priv->cur_rx = bdp; | |
1792 | ||
1da177e4 LT |
1793 | return howmany; |
1794 | } | |
1795 | ||
bea3348e | 1796 | static int gfar_poll(struct napi_struct *napi, int budget) |
1da177e4 | 1797 | { |
bea3348e SH |
1798 | struct gfar_private *priv = container_of(napi, struct gfar_private, napi); |
1799 | struct net_device *dev = priv->dev; | |
1da177e4 | 1800 | int howmany; |
d080cd63 DH |
1801 | unsigned long flags; |
1802 | ||
1803 | /* If we fail to get the lock, don't bother with the TX BDs */ | |
1804 | if (spin_trylock_irqsave(&priv->txlock, flags)) { | |
1805 | gfar_clean_tx_ring(dev); | |
1806 | spin_unlock_irqrestore(&priv->txlock, flags); | |
1807 | } | |
1da177e4 | 1808 | |
bea3348e | 1809 | howmany = gfar_clean_rx_ring(dev, budget); |
1da177e4 | 1810 | |
bea3348e SH |
1811 | if (howmany < budget) { |
1812 | netif_rx_complete(dev, napi); | |
1da177e4 LT |
1813 | |
1814 | /* Clear the halt bit in RSTAT */ | |
1815 | gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT); | |
1816 | ||
1817 | gfar_write(&priv->regs->imask, IMASK_DEFAULT); | |
1818 | ||
1819 | /* If we are coalescing interrupts, update the timer */ | |
1820 | /* Otherwise, clear it */ | |
2f448911 AF |
1821 | if (likely(priv->rxcoalescing)) { |
1822 | gfar_write(&priv->regs->rxic, 0); | |
b46a8454 | 1823 | gfar_write(&priv->regs->rxic, priv->rxic); |
2f448911 | 1824 | } |
1da177e4 LT |
1825 | } |
1826 | ||
bea3348e | 1827 | return howmany; |
1da177e4 | 1828 | } |
1da177e4 | 1829 | |
f2d71c2d VW |
1830 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1831 | /* | |
1832 | * Polling 'interrupt' - used by things like netconsole to send skbs | |
1833 | * without having to re-enable interrupts. It's not called while | |
1834 | * the interrupt routine is executing. | |
1835 | */ | |
1836 | static void gfar_netpoll(struct net_device *dev) | |
1837 | { | |
1838 | struct gfar_private *priv = netdev_priv(dev); | |
1839 | ||
1840 | /* If the device has multiple interrupts, run tx/rx */ | |
b31a1d8b | 1841 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
f2d71c2d VW |
1842 | disable_irq(priv->interruptTransmit); |
1843 | disable_irq(priv->interruptReceive); | |
1844 | disable_irq(priv->interruptError); | |
1845 | gfar_interrupt(priv->interruptTransmit, dev); | |
1846 | enable_irq(priv->interruptError); | |
1847 | enable_irq(priv->interruptReceive); | |
1848 | enable_irq(priv->interruptTransmit); | |
1849 | } else { | |
1850 | disable_irq(priv->interruptTransmit); | |
1851 | gfar_interrupt(priv->interruptTransmit, dev); | |
1852 | enable_irq(priv->interruptTransmit); | |
1853 | } | |
1854 | } | |
1855 | #endif | |
1856 | ||
1da177e4 | 1857 | /* The interrupt handler for devices with one interrupt */ |
7d12e780 | 1858 | static irqreturn_t gfar_interrupt(int irq, void *dev_id) |
1da177e4 LT |
1859 | { |
1860 | struct net_device *dev = dev_id; | |
1861 | struct gfar_private *priv = netdev_priv(dev); | |
1862 | ||
1863 | /* Save ievent for future reference */ | |
1864 | u32 events = gfar_read(&priv->regs->ievent); | |
1865 | ||
1da177e4 | 1866 | /* Check for reception */ |
538cc7ee | 1867 | if (events & IEVENT_RX_MASK) |
7d12e780 | 1868 | gfar_receive(irq, dev_id); |
1da177e4 LT |
1869 | |
1870 | /* Check for transmit completion */ | |
538cc7ee | 1871 | if (events & IEVENT_TX_MASK) |
7d12e780 | 1872 | gfar_transmit(irq, dev_id); |
1da177e4 | 1873 | |
538cc7ee SS |
1874 | /* Check for errors */ |
1875 | if (events & IEVENT_ERR_MASK) | |
1876 | gfar_error(irq, dev_id); | |
1da177e4 LT |
1877 | |
1878 | return IRQ_HANDLED; | |
1879 | } | |
1880 | ||
1da177e4 LT |
1881 | /* Called every time the controller might need to be made |
1882 | * aware of new link state. The PHY code conveys this | |
bb40dcbb | 1883 | * information through variables in the phydev structure, and this |
1da177e4 LT |
1884 | * function converts those variables into the appropriate |
1885 | * register values, and can bring down the device if needed. | |
1886 | */ | |
1887 | static void adjust_link(struct net_device *dev) | |
1888 | { | |
1889 | struct gfar_private *priv = netdev_priv(dev); | |
cc8c6e37 | 1890 | struct gfar __iomem *regs = priv->regs; |
bb40dcbb AF |
1891 | unsigned long flags; |
1892 | struct phy_device *phydev = priv->phydev; | |
1893 | int new_state = 0; | |
1894 | ||
fef6108d | 1895 | spin_lock_irqsave(&priv->txlock, flags); |
bb40dcbb AF |
1896 | if (phydev->link) { |
1897 | u32 tempval = gfar_read(®s->maccfg2); | |
7f7f5316 | 1898 | u32 ecntrl = gfar_read(®s->ecntrl); |
1da177e4 | 1899 | |
1da177e4 LT |
1900 | /* Now we make sure that we can be in full duplex mode. |
1901 | * If not, we operate in half-duplex mode. */ | |
bb40dcbb AF |
1902 | if (phydev->duplex != priv->oldduplex) { |
1903 | new_state = 1; | |
1904 | if (!(phydev->duplex)) | |
1da177e4 | 1905 | tempval &= ~(MACCFG2_FULL_DUPLEX); |
bb40dcbb | 1906 | else |
1da177e4 | 1907 | tempval |= MACCFG2_FULL_DUPLEX; |
1da177e4 | 1908 | |
bb40dcbb | 1909 | priv->oldduplex = phydev->duplex; |
1da177e4 LT |
1910 | } |
1911 | ||
bb40dcbb AF |
1912 | if (phydev->speed != priv->oldspeed) { |
1913 | new_state = 1; | |
1914 | switch (phydev->speed) { | |
1da177e4 | 1915 | case 1000: |
1da177e4 LT |
1916 | tempval = |
1917 | ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII); | |
1da177e4 LT |
1918 | break; |
1919 | case 100: | |
1920 | case 10: | |
1da177e4 LT |
1921 | tempval = |
1922 | ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII); | |
7f7f5316 AF |
1923 | |
1924 | /* Reduced mode distinguishes | |
1925 | * between 10 and 100 */ | |
1926 | if (phydev->speed == SPEED_100) | |
1927 | ecntrl |= ECNTRL_R100; | |
1928 | else | |
1929 | ecntrl &= ~(ECNTRL_R100); | |
1da177e4 LT |
1930 | break; |
1931 | default: | |
0bbaf069 KG |
1932 | if (netif_msg_link(priv)) |
1933 | printk(KERN_WARNING | |
bb40dcbb AF |
1934 | "%s: Ack! Speed (%d) is not 10/100/1000!\n", |
1935 | dev->name, phydev->speed); | |
1da177e4 LT |
1936 | break; |
1937 | } | |
1938 | ||
bb40dcbb | 1939 | priv->oldspeed = phydev->speed; |
1da177e4 LT |
1940 | } |
1941 | ||
bb40dcbb | 1942 | gfar_write(®s->maccfg2, tempval); |
7f7f5316 | 1943 | gfar_write(®s->ecntrl, ecntrl); |
bb40dcbb | 1944 | |
1da177e4 | 1945 | if (!priv->oldlink) { |
bb40dcbb | 1946 | new_state = 1; |
1da177e4 | 1947 | priv->oldlink = 1; |
1da177e4 | 1948 | } |
bb40dcbb AF |
1949 | } else if (priv->oldlink) { |
1950 | new_state = 1; | |
1951 | priv->oldlink = 0; | |
1952 | priv->oldspeed = 0; | |
1953 | priv->oldduplex = -1; | |
1da177e4 | 1954 | } |
1da177e4 | 1955 | |
bb40dcbb AF |
1956 | if (new_state && netif_msg_link(priv)) |
1957 | phy_print_status(phydev); | |
1958 | ||
fef6108d | 1959 | spin_unlock_irqrestore(&priv->txlock, flags); |
bb40dcbb | 1960 | } |
1da177e4 LT |
1961 | |
1962 | /* Update the hash table based on the current list of multicast | |
1963 | * addresses we subscribe to. Also, change the promiscuity of | |
1964 | * the device based on the flags (this function is called | |
1965 | * whenever dev->flags is changed */ | |
1966 | static void gfar_set_multi(struct net_device *dev) | |
1967 | { | |
1968 | struct dev_mc_list *mc_ptr; | |
1969 | struct gfar_private *priv = netdev_priv(dev); | |
cc8c6e37 | 1970 | struct gfar __iomem *regs = priv->regs; |
1da177e4 LT |
1971 | u32 tempval; |
1972 | ||
1973 | if(dev->flags & IFF_PROMISC) { | |
1da177e4 LT |
1974 | /* Set RCTRL to PROM */ |
1975 | tempval = gfar_read(®s->rctrl); | |
1976 | tempval |= RCTRL_PROM; | |
1977 | gfar_write(®s->rctrl, tempval); | |
1978 | } else { | |
1979 | /* Set RCTRL to not PROM */ | |
1980 | tempval = gfar_read(®s->rctrl); | |
1981 | tempval &= ~(RCTRL_PROM); | |
1982 | gfar_write(®s->rctrl, tempval); | |
1983 | } | |
6aa20a22 | 1984 | |
1da177e4 LT |
1985 | if(dev->flags & IFF_ALLMULTI) { |
1986 | /* Set the hash to rx all multicast frames */ | |
0bbaf069 KG |
1987 | gfar_write(®s->igaddr0, 0xffffffff); |
1988 | gfar_write(®s->igaddr1, 0xffffffff); | |
1989 | gfar_write(®s->igaddr2, 0xffffffff); | |
1990 | gfar_write(®s->igaddr3, 0xffffffff); | |
1991 | gfar_write(®s->igaddr4, 0xffffffff); | |
1992 | gfar_write(®s->igaddr5, 0xffffffff); | |
1993 | gfar_write(®s->igaddr6, 0xffffffff); | |
1994 | gfar_write(®s->igaddr7, 0xffffffff); | |
1da177e4 LT |
1995 | gfar_write(®s->gaddr0, 0xffffffff); |
1996 | gfar_write(®s->gaddr1, 0xffffffff); | |
1997 | gfar_write(®s->gaddr2, 0xffffffff); | |
1998 | gfar_write(®s->gaddr3, 0xffffffff); | |
1999 | gfar_write(®s->gaddr4, 0xffffffff); | |
2000 | gfar_write(®s->gaddr5, 0xffffffff); | |
2001 | gfar_write(®s->gaddr6, 0xffffffff); | |
2002 | gfar_write(®s->gaddr7, 0xffffffff); | |
2003 | } else { | |
7f7f5316 AF |
2004 | int em_num; |
2005 | int idx; | |
2006 | ||
1da177e4 | 2007 | /* zero out the hash */ |
0bbaf069 KG |
2008 | gfar_write(®s->igaddr0, 0x0); |
2009 | gfar_write(®s->igaddr1, 0x0); | |
2010 | gfar_write(®s->igaddr2, 0x0); | |
2011 | gfar_write(®s->igaddr3, 0x0); | |
2012 | gfar_write(®s->igaddr4, 0x0); | |
2013 | gfar_write(®s->igaddr5, 0x0); | |
2014 | gfar_write(®s->igaddr6, 0x0); | |
2015 | gfar_write(®s->igaddr7, 0x0); | |
1da177e4 LT |
2016 | gfar_write(®s->gaddr0, 0x0); |
2017 | gfar_write(®s->gaddr1, 0x0); | |
2018 | gfar_write(®s->gaddr2, 0x0); | |
2019 | gfar_write(®s->gaddr3, 0x0); | |
2020 | gfar_write(®s->gaddr4, 0x0); | |
2021 | gfar_write(®s->gaddr5, 0x0); | |
2022 | gfar_write(®s->gaddr6, 0x0); | |
2023 | gfar_write(®s->gaddr7, 0x0); | |
2024 | ||
7f7f5316 AF |
2025 | /* If we have extended hash tables, we need to |
2026 | * clear the exact match registers to prepare for | |
2027 | * setting them */ | |
2028 | if (priv->extended_hash) { | |
2029 | em_num = GFAR_EM_NUM + 1; | |
2030 | gfar_clear_exact_match(dev); | |
2031 | idx = 1; | |
2032 | } else { | |
2033 | idx = 0; | |
2034 | em_num = 0; | |
2035 | } | |
2036 | ||
1da177e4 LT |
2037 | if(dev->mc_count == 0) |
2038 | return; | |
2039 | ||
2040 | /* Parse the list, and set the appropriate bits */ | |
2041 | for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) { | |
7f7f5316 AF |
2042 | if (idx < em_num) { |
2043 | gfar_set_mac_for_addr(dev, idx, | |
2044 | mc_ptr->dmi_addr); | |
2045 | idx++; | |
2046 | } else | |
2047 | gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr); | |
1da177e4 LT |
2048 | } |
2049 | } | |
2050 | ||
2051 | return; | |
2052 | } | |
2053 | ||
7f7f5316 AF |
2054 | |
2055 | /* Clears each of the exact match registers to zero, so they | |
2056 | * don't interfere with normal reception */ | |
2057 | static void gfar_clear_exact_match(struct net_device *dev) | |
2058 | { | |
2059 | int idx; | |
2060 | u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0}; | |
2061 | ||
2062 | for(idx = 1;idx < GFAR_EM_NUM + 1;idx++) | |
2063 | gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr); | |
2064 | } | |
2065 | ||
1da177e4 LT |
2066 | /* Set the appropriate hash bit for the given addr */ |
2067 | /* The algorithm works like so: | |
2068 | * 1) Take the Destination Address (ie the multicast address), and | |
2069 | * do a CRC on it (little endian), and reverse the bits of the | |
2070 | * result. | |
2071 | * 2) Use the 8 most significant bits as a hash into a 256-entry | |
2072 | * table. The table is controlled through 8 32-bit registers: | |
2073 | * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is | |
2074 | * gaddr7. This means that the 3 most significant bits in the | |
2075 | * hash index which gaddr register to use, and the 5 other bits | |
2076 | * indicate which bit (assuming an IBM numbering scheme, which | |
2077 | * for PowerPC (tm) is usually the case) in the register holds | |
2078 | * the entry. */ | |
2079 | static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr) | |
2080 | { | |
2081 | u32 tempval; | |
2082 | struct gfar_private *priv = netdev_priv(dev); | |
1da177e4 | 2083 | u32 result = ether_crc(MAC_ADDR_LEN, addr); |
0bbaf069 KG |
2084 | int width = priv->hash_width; |
2085 | u8 whichbit = (result >> (32 - width)) & 0x1f; | |
2086 | u8 whichreg = result >> (32 - width + 5); | |
1da177e4 LT |
2087 | u32 value = (1 << (31-whichbit)); |
2088 | ||
0bbaf069 | 2089 | tempval = gfar_read(priv->hash_regs[whichreg]); |
1da177e4 | 2090 | tempval |= value; |
0bbaf069 | 2091 | gfar_write(priv->hash_regs[whichreg], tempval); |
1da177e4 LT |
2092 | |
2093 | return; | |
2094 | } | |
2095 | ||
7f7f5316 AF |
2096 | |
2097 | /* There are multiple MAC Address register pairs on some controllers | |
2098 | * This function sets the numth pair to a given address | |
2099 | */ | |
2100 | static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr) | |
2101 | { | |
2102 | struct gfar_private *priv = netdev_priv(dev); | |
2103 | int idx; | |
2104 | char tmpbuf[MAC_ADDR_LEN]; | |
2105 | u32 tempval; | |
cc8c6e37 | 2106 | u32 __iomem *macptr = &priv->regs->macstnaddr1; |
7f7f5316 AF |
2107 | |
2108 | macptr += num*2; | |
2109 | ||
2110 | /* Now copy it into the mac registers backwards, cuz */ | |
2111 | /* little endian is silly */ | |
2112 | for (idx = 0; idx < MAC_ADDR_LEN; idx++) | |
2113 | tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx]; | |
2114 | ||
2115 | gfar_write(macptr, *((u32 *) (tmpbuf))); | |
2116 | ||
2117 | tempval = *((u32 *) (tmpbuf + 4)); | |
2118 | ||
2119 | gfar_write(macptr+1, tempval); | |
2120 | } | |
2121 | ||
1da177e4 | 2122 | /* GFAR error interrupt handler */ |
7d12e780 | 2123 | static irqreturn_t gfar_error(int irq, void *dev_id) |
1da177e4 LT |
2124 | { |
2125 | struct net_device *dev = dev_id; | |
2126 | struct gfar_private *priv = netdev_priv(dev); | |
2127 | ||
2128 | /* Save ievent for future reference */ | |
2129 | u32 events = gfar_read(&priv->regs->ievent); | |
2130 | ||
2131 | /* Clear IEVENT */ | |
d87eb127 SW |
2132 | gfar_write(&priv->regs->ievent, events & IEVENT_ERR_MASK); |
2133 | ||
2134 | /* Magic Packet is not an error. */ | |
b31a1d8b | 2135 | if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) && |
d87eb127 SW |
2136 | (events & IEVENT_MAG)) |
2137 | events &= ~IEVENT_MAG; | |
1da177e4 LT |
2138 | |
2139 | /* Hmm... */ | |
0bbaf069 KG |
2140 | if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv)) |
2141 | printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n", | |
538cc7ee | 2142 | dev->name, events, gfar_read(&priv->regs->imask)); |
1da177e4 LT |
2143 | |
2144 | /* Update the error counters */ | |
2145 | if (events & IEVENT_TXE) { | |
09f75cd7 | 2146 | dev->stats.tx_errors++; |
1da177e4 LT |
2147 | |
2148 | if (events & IEVENT_LC) | |
09f75cd7 | 2149 | dev->stats.tx_window_errors++; |
1da177e4 | 2150 | if (events & IEVENT_CRL) |
09f75cd7 | 2151 | dev->stats.tx_aborted_errors++; |
1da177e4 | 2152 | if (events & IEVENT_XFUN) { |
0bbaf069 | 2153 | if (netif_msg_tx_err(priv)) |
538cc7ee SS |
2154 | printk(KERN_DEBUG "%s: TX FIFO underrun, " |
2155 | "packet dropped.\n", dev->name); | |
09f75cd7 | 2156 | dev->stats.tx_dropped++; |
1da177e4 LT |
2157 | priv->extra_stats.tx_underrun++; |
2158 | ||
2159 | /* Reactivate the Tx Queues */ | |
2160 | gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT); | |
2161 | } | |
0bbaf069 KG |
2162 | if (netif_msg_tx_err(priv)) |
2163 | printk(KERN_DEBUG "%s: Transmit Error\n", dev->name); | |
1da177e4 LT |
2164 | } |
2165 | if (events & IEVENT_BSY) { | |
09f75cd7 | 2166 | dev->stats.rx_errors++; |
1da177e4 LT |
2167 | priv->extra_stats.rx_bsy++; |
2168 | ||
7d12e780 | 2169 | gfar_receive(irq, dev_id); |
1da177e4 | 2170 | |
0bbaf069 | 2171 | if (netif_msg_rx_err(priv)) |
538cc7ee SS |
2172 | printk(KERN_DEBUG "%s: busy error (rstat: %x)\n", |
2173 | dev->name, gfar_read(&priv->regs->rstat)); | |
1da177e4 LT |
2174 | } |
2175 | if (events & IEVENT_BABR) { | |
09f75cd7 | 2176 | dev->stats.rx_errors++; |
1da177e4 LT |
2177 | priv->extra_stats.rx_babr++; |
2178 | ||
0bbaf069 | 2179 | if (netif_msg_rx_err(priv)) |
538cc7ee | 2180 | printk(KERN_DEBUG "%s: babbling RX error\n", dev->name); |
1da177e4 LT |
2181 | } |
2182 | if (events & IEVENT_EBERR) { | |
2183 | priv->extra_stats.eberr++; | |
0bbaf069 | 2184 | if (netif_msg_rx_err(priv)) |
538cc7ee | 2185 | printk(KERN_DEBUG "%s: bus error\n", dev->name); |
1da177e4 | 2186 | } |
0bbaf069 | 2187 | if ((events & IEVENT_RXC) && netif_msg_rx_status(priv)) |
538cc7ee | 2188 | printk(KERN_DEBUG "%s: control frame\n", dev->name); |
1da177e4 LT |
2189 | |
2190 | if (events & IEVENT_BABT) { | |
2191 | priv->extra_stats.tx_babt++; | |
0bbaf069 | 2192 | if (netif_msg_tx_err(priv)) |
538cc7ee | 2193 | printk(KERN_DEBUG "%s: babbling TX error\n", dev->name); |
1da177e4 LT |
2194 | } |
2195 | return IRQ_HANDLED; | |
2196 | } | |
2197 | ||
72abb461 KS |
2198 | /* work with hotplug and coldplug */ |
2199 | MODULE_ALIAS("platform:fsl-gianfar"); | |
2200 | ||
b31a1d8b AF |
2201 | static struct of_device_id gfar_match[] = |
2202 | { | |
2203 | { | |
2204 | .type = "network", | |
2205 | .compatible = "gianfar", | |
2206 | }, | |
2207 | {}, | |
2208 | }; | |
2209 | ||
1da177e4 | 2210 | /* Structure for a device driver */ |
b31a1d8b AF |
2211 | static struct of_platform_driver gfar_driver = { |
2212 | .name = "fsl-gianfar", | |
2213 | .match_table = gfar_match, | |
2214 | ||
1da177e4 LT |
2215 | .probe = gfar_probe, |
2216 | .remove = gfar_remove, | |
d87eb127 SW |
2217 | .suspend = gfar_suspend, |
2218 | .resume = gfar_resume, | |
1da177e4 LT |
2219 | }; |
2220 | ||
2221 | static int __init gfar_init(void) | |
2222 | { | |
bb40dcbb AF |
2223 | int err = gfar_mdio_init(); |
2224 | ||
2225 | if (err) | |
2226 | return err; | |
2227 | ||
b31a1d8b | 2228 | err = of_register_platform_driver(&gfar_driver); |
bb40dcbb AF |
2229 | |
2230 | if (err) | |
2231 | gfar_mdio_exit(); | |
6aa20a22 | 2232 | |
bb40dcbb | 2233 | return err; |
1da177e4 LT |
2234 | } |
2235 | ||
2236 | static void __exit gfar_exit(void) | |
2237 | { | |
b31a1d8b | 2238 | of_unregister_platform_driver(&gfar_driver); |
bb40dcbb | 2239 | gfar_mdio_exit(); |
1da177e4 LT |
2240 | } |
2241 | ||
2242 | module_init(gfar_init); | |
2243 | module_exit(gfar_exit); | |
2244 |