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1da177e4 LT |
1 | /* |
2 | * drivers/net/gianfar.h | |
3 | * | |
4 | * Gianfar Ethernet Driver | |
5 | * Driver for FEC on MPC8540 and TSEC on MPC8540/MPC8560 | |
6 | * Based on 8260_io/fcc_enet.c | |
7 | * | |
8 | * Author: Andy Fleming | |
9 | * Maintainer: Kumar Gala (kumar.gala@freescale.com) | |
10 | * | |
11 | * Copyright (c) 2002-2004 Freescale Semiconductor, Inc. | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify it | |
14 | * under the terms of the GNU General Public License as published by the | |
15 | * Free Software Foundation; either version 2 of the License, or (at your | |
16 | * option) any later version. | |
17 | * | |
18 | * Still left to do: | |
19 | * -Add support for module parameters | |
20 | * -Add support for ethtool -s | |
21 | * -Add patch for ethtool phys id | |
22 | */ | |
23 | #ifndef __GIANFAR_H | |
24 | #define __GIANFAR_H | |
25 | ||
26 | #include <linux/config.h> | |
27 | #include <linux/kernel.h> | |
28 | #include <linux/sched.h> | |
29 | #include <linux/string.h> | |
30 | #include <linux/errno.h> | |
31 | #include <linux/slab.h> | |
32 | #include <linux/interrupt.h> | |
33 | #include <linux/init.h> | |
34 | #include <linux/delay.h> | |
35 | #include <linux/netdevice.h> | |
36 | #include <linux/etherdevice.h> | |
37 | #include <linux/skbuff.h> | |
38 | #include <linux/spinlock.h> | |
39 | #include <linux/mm.h> | |
40 | #include <linux/fsl_devices.h> | |
41 | ||
42 | #include <asm/io.h> | |
43 | #include <asm/irq.h> | |
44 | #include <asm/uaccess.h> | |
45 | #include <linux/module.h> | |
46 | #include <linux/version.h> | |
47 | #include <linux/crc32.h> | |
48 | #include <linux/workqueue.h> | |
49 | #include <linux/ethtool.h> | |
50 | #include <linux/netdevice.h> | |
51 | #include "gianfar_phy.h" | |
52 | ||
53 | /* The maximum number of packets to be handled in one call of gfar_poll */ | |
54 | #define GFAR_DEV_WEIGHT 64 | |
55 | ||
56 | /* Number of bytes to align the rx bufs to */ | |
57 | #define RXBUF_ALIGNMENT 64 | |
58 | ||
59 | /* The number of bytes which composes a unit for the purpose of | |
60 | * allocating data buffers. ie-for any given MTU, the data buffer | |
61 | * will be the next highest multiple of 512 bytes. */ | |
62 | #define INCREMENTAL_BUFFER_SIZE 512 | |
63 | ||
64 | ||
65 | #define MAC_ADDR_LEN 6 | |
66 | ||
67 | #define PHY_INIT_TIMEOUT 100000 | |
68 | #define GFAR_PHY_CHANGE_TIME 2 | |
69 | ||
70 | #define DEVICE_NAME "%s: Gianfar Ethernet Controller Version 1.1, " | |
71 | #define DRV_NAME "gfar-enet" | |
72 | extern const char gfar_driver_name[]; | |
73 | extern const char gfar_driver_version[]; | |
74 | ||
75 | /* These need to be powers of 2 for this driver */ | |
76 | #ifdef CONFIG_GFAR_NAPI | |
77 | #define DEFAULT_TX_RING_SIZE 256 | |
78 | #define DEFAULT_RX_RING_SIZE 256 | |
79 | #else | |
80 | #define DEFAULT_TX_RING_SIZE 64 | |
81 | #define DEFAULT_RX_RING_SIZE 64 | |
82 | #endif | |
83 | ||
84 | #define GFAR_RX_MAX_RING_SIZE 256 | |
85 | #define GFAR_TX_MAX_RING_SIZE 256 | |
86 | ||
87 | #define DEFAULT_RX_BUFFER_SIZE 1536 | |
88 | #define TX_RING_MOD_MASK(size) (size-1) | |
89 | #define RX_RING_MOD_MASK(size) (size-1) | |
90 | #define JUMBO_BUFFER_SIZE 9728 | |
91 | #define JUMBO_FRAME_SIZE 9600 | |
92 | ||
93 | /* Latency of interface clock in nanoseconds */ | |
94 | /* Interface clock latency , in this case, means the | |
95 | * time described by a value of 1 in the interrupt | |
96 | * coalescing registers' time fields. Since those fields | |
97 | * refer to the time it takes for 64 clocks to pass, the | |
98 | * latencies are as such: | |
99 | * GBIT = 125MHz => 8ns/clock => 8*64 ns / tick | |
100 | * 100 = 25 MHz => 40ns/clock => 40*64 ns / tick | |
101 | * 10 = 2.5 MHz => 400ns/clock => 400*64 ns / tick | |
102 | */ | |
103 | #define GFAR_GBIT_TIME 512 | |
104 | #define GFAR_100_TIME 2560 | |
105 | #define GFAR_10_TIME 25600 | |
106 | ||
107 | #define DEFAULT_TX_COALESCE 1 | |
108 | #define DEFAULT_TXCOUNT 16 | |
109 | #define DEFAULT_TXTIME 400 | |
110 | ||
111 | #define DEFAULT_RX_COALESCE 1 | |
112 | #define DEFAULT_RXCOUNT 16 | |
113 | #define DEFAULT_RXTIME 400 | |
114 | ||
115 | #define TBIPA_VALUE 0x1f | |
116 | #define MIIMCFG_INIT_VALUE 0x00000007 | |
117 | #define MIIMCFG_RESET 0x80000000 | |
118 | #define MIIMIND_BUSY 0x00000001 | |
119 | ||
120 | /* MAC register bits */ | |
121 | #define MACCFG1_SOFT_RESET 0x80000000 | |
122 | #define MACCFG1_RESET_RX_MC 0x00080000 | |
123 | #define MACCFG1_RESET_TX_MC 0x00040000 | |
124 | #define MACCFG1_RESET_RX_FUN 0x00020000 | |
125 | #define MACCFG1_RESET_TX_FUN 0x00010000 | |
126 | #define MACCFG1_LOOPBACK 0x00000100 | |
127 | #define MACCFG1_RX_FLOW 0x00000020 | |
128 | #define MACCFG1_TX_FLOW 0x00000010 | |
129 | #define MACCFG1_SYNCD_RX_EN 0x00000008 | |
130 | #define MACCFG1_RX_EN 0x00000004 | |
131 | #define MACCFG1_SYNCD_TX_EN 0x00000002 | |
132 | #define MACCFG1_TX_EN 0x00000001 | |
133 | ||
134 | #define MACCFG2_INIT_SETTINGS 0x00007205 | |
135 | #define MACCFG2_FULL_DUPLEX 0x00000001 | |
136 | #define MACCFG2_IF 0x00000300 | |
137 | #define MACCFG2_MII 0x00000100 | |
138 | #define MACCFG2_GMII 0x00000200 | |
139 | #define MACCFG2_HUGEFRAME 0x00000020 | |
140 | #define MACCFG2_LENGTHCHECK 0x00000010 | |
141 | ||
142 | #define ECNTRL_INIT_SETTINGS 0x00001000 | |
143 | #define ECNTRL_TBI_MODE 0x00000020 | |
144 | ||
145 | #define MRBLR_INIT_SETTINGS DEFAULT_RX_BUFFER_SIZE | |
146 | ||
147 | #define MINFLR_INIT_SETTINGS 0x00000040 | |
148 | ||
149 | /* Init to do tx snooping for buffers and descriptors */ | |
150 | #define DMACTRL_INIT_SETTINGS 0x000000c3 | |
151 | #define DMACTRL_GRS 0x00000010 | |
152 | #define DMACTRL_GTS 0x00000008 | |
153 | ||
154 | #define TSTAT_CLEAR_THALT 0x80000000 | |
155 | ||
156 | /* Interrupt coalescing macros */ | |
157 | #define IC_ICEN 0x80000000 | |
158 | #define IC_ICFT_MASK 0x1fe00000 | |
159 | #define IC_ICFT_SHIFT 21 | |
160 | #define mk_ic_icft(x) \ | |
161 | (((unsigned int)x << IC_ICFT_SHIFT)&IC_ICFT_MASK) | |
162 | #define IC_ICTT_MASK 0x0000ffff | |
163 | #define mk_ic_ictt(x) (x&IC_ICTT_MASK) | |
164 | ||
165 | #define mk_ic_value(count, time) (IC_ICEN | \ | |
166 | mk_ic_icft(count) | \ | |
167 | mk_ic_ictt(time)) | |
168 | ||
169 | #define RCTRL_PROM 0x00000008 | |
170 | #define RSTAT_CLEAR_RHALT 0x00800000 | |
171 | ||
172 | #define IEVENT_INIT_CLEAR 0xffffffff | |
173 | #define IEVENT_BABR 0x80000000 | |
174 | #define IEVENT_RXC 0x40000000 | |
175 | #define IEVENT_BSY 0x20000000 | |
176 | #define IEVENT_EBERR 0x10000000 | |
177 | #define IEVENT_MSRO 0x04000000 | |
178 | #define IEVENT_GTSC 0x02000000 | |
179 | #define IEVENT_BABT 0x01000000 | |
180 | #define IEVENT_TXC 0x00800000 | |
181 | #define IEVENT_TXE 0x00400000 | |
182 | #define IEVENT_TXB 0x00200000 | |
183 | #define IEVENT_TXF 0x00100000 | |
184 | #define IEVENT_LC 0x00040000 | |
185 | #define IEVENT_CRL 0x00020000 | |
186 | #define IEVENT_XFUN 0x00010000 | |
187 | #define IEVENT_RXB0 0x00008000 | |
188 | #define IEVENT_GRSC 0x00000100 | |
189 | #define IEVENT_RXF0 0x00000080 | |
190 | #define IEVENT_RX_MASK (IEVENT_RXB0 | IEVENT_RXF0) | |
191 | #define IEVENT_TX_MASK (IEVENT_TXB | IEVENT_TXF) | |
192 | #define IEVENT_ERR_MASK \ | |
193 | (IEVENT_RXC | IEVENT_BSY | IEVENT_EBERR | IEVENT_MSRO | \ | |
194 | IEVENT_BABT | IEVENT_TXC | IEVENT_TXE | IEVENT_LC \ | |
195 | | IEVENT_CRL | IEVENT_XFUN) | |
196 | ||
197 | #define IMASK_INIT_CLEAR 0x00000000 | |
198 | #define IMASK_BABR 0x80000000 | |
199 | #define IMASK_RXC 0x40000000 | |
200 | #define IMASK_BSY 0x20000000 | |
201 | #define IMASK_EBERR 0x10000000 | |
202 | #define IMASK_MSRO 0x04000000 | |
203 | #define IMASK_GRSC 0x02000000 | |
204 | #define IMASK_BABT 0x01000000 | |
205 | #define IMASK_TXC 0x00800000 | |
206 | #define IMASK_TXEEN 0x00400000 | |
207 | #define IMASK_TXBEN 0x00200000 | |
208 | #define IMASK_TXFEN 0x00100000 | |
209 | #define IMASK_LC 0x00040000 | |
210 | #define IMASK_CRL 0x00020000 | |
211 | #define IMASK_XFUN 0x00010000 | |
212 | #define IMASK_RXB0 0x00008000 | |
213 | #define IMASK_GTSC 0x00000100 | |
214 | #define IMASK_RXFEN0 0x00000080 | |
215 | #define IMASK_RX_DISABLED ~(IMASK_RXFEN0 | IMASK_BSY) | |
216 | #define IMASK_DEFAULT (IMASK_TXEEN | IMASK_TXFEN | IMASK_TXBEN | \ | |
217 | IMASK_RXFEN0 | IMASK_BSY | IMASK_EBERR | IMASK_BABR | \ | |
218 | IMASK_XFUN | IMASK_RXC | IMASK_BABT) | |
219 | ||
220 | ||
221 | /* Attribute fields */ | |
222 | ||
223 | /* This enables rx snooping for buffers and descriptors */ | |
224 | #ifdef CONFIG_GFAR_BDSTASH | |
225 | #define ATTR_BDSTASH 0x00000800 | |
226 | #else | |
227 | #define ATTR_BDSTASH 0x00000000 | |
228 | #endif | |
229 | ||
230 | #ifdef CONFIG_GFAR_BUFSTASH | |
231 | #define ATTR_BUFSTASH 0x00004000 | |
232 | #define STASH_LENGTH 64 | |
233 | #else | |
234 | #define ATTR_BUFSTASH 0x00000000 | |
235 | #endif | |
236 | ||
237 | #define ATTR_SNOOPING 0x000000c0 | |
238 | #define ATTR_INIT_SETTINGS (ATTR_SNOOPING \ | |
239 | | ATTR_BDSTASH | ATTR_BUFSTASH) | |
240 | ||
241 | #define ATTRELI_INIT_SETTINGS 0x0 | |
242 | ||
243 | ||
244 | /* TxBD status field bits */ | |
245 | #define TXBD_READY 0x8000 | |
246 | #define TXBD_PADCRC 0x4000 | |
247 | #define TXBD_WRAP 0x2000 | |
248 | #define TXBD_INTERRUPT 0x1000 | |
249 | #define TXBD_LAST 0x0800 | |
250 | #define TXBD_CRC 0x0400 | |
251 | #define TXBD_DEF 0x0200 | |
252 | #define TXBD_HUGEFRAME 0x0080 | |
253 | #define TXBD_LATECOLLISION 0x0080 | |
254 | #define TXBD_RETRYLIMIT 0x0040 | |
255 | #define TXBD_RETRYCOUNTMASK 0x003c | |
256 | #define TXBD_UNDERRUN 0x0002 | |
257 | ||
258 | /* RxBD status field bits */ | |
259 | #define RXBD_EMPTY 0x8000 | |
260 | #define RXBD_RO1 0x4000 | |
261 | #define RXBD_WRAP 0x2000 | |
262 | #define RXBD_INTERRUPT 0x1000 | |
263 | #define RXBD_LAST 0x0800 | |
264 | #define RXBD_FIRST 0x0400 | |
265 | #define RXBD_MISS 0x0100 | |
266 | #define RXBD_BROADCAST 0x0080 | |
267 | #define RXBD_MULTICAST 0x0040 | |
268 | #define RXBD_LARGE 0x0020 | |
269 | #define RXBD_NONOCTET 0x0010 | |
270 | #define RXBD_SHORT 0x0008 | |
271 | #define RXBD_CRCERR 0x0004 | |
272 | #define RXBD_OVERRUN 0x0002 | |
273 | #define RXBD_TRUNCATED 0x0001 | |
274 | #define RXBD_STATS 0x01ff | |
275 | ||
276 | struct txbd8 | |
277 | { | |
278 | u16 status; /* Status Fields */ | |
279 | u16 length; /* Buffer length */ | |
280 | u32 bufPtr; /* Buffer Pointer */ | |
281 | }; | |
282 | ||
283 | struct rxbd8 | |
284 | { | |
285 | u16 status; /* Status Fields */ | |
286 | u16 length; /* Buffer Length */ | |
287 | u32 bufPtr; /* Buffer Pointer */ | |
288 | }; | |
289 | ||
290 | struct rmon_mib | |
291 | { | |
292 | u32 tr64; /* 0x.680 - Transmit and Receive 64-byte Frame Counter */ | |
293 | u32 tr127; /* 0x.684 - Transmit and Receive 65-127 byte Frame Counter */ | |
294 | u32 tr255; /* 0x.688 - Transmit and Receive 128-255 byte Frame Counter */ | |
295 | u32 tr511; /* 0x.68c - Transmit and Receive 256-511 byte Frame Counter */ | |
296 | u32 tr1k; /* 0x.690 - Transmit and Receive 512-1023 byte Frame Counter */ | |
297 | u32 trmax; /* 0x.694 - Transmit and Receive 1024-1518 byte Frame Counter */ | |
298 | u32 trmgv; /* 0x.698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */ | |
299 | u32 rbyt; /* 0x.69c - Receive Byte Counter */ | |
300 | u32 rpkt; /* 0x.6a0 - Receive Packet Counter */ | |
301 | u32 rfcs; /* 0x.6a4 - Receive FCS Error Counter */ | |
302 | u32 rmca; /* 0x.6a8 - Receive Multicast Packet Counter */ | |
303 | u32 rbca; /* 0x.6ac - Receive Broadcast Packet Counter */ | |
304 | u32 rxcf; /* 0x.6b0 - Receive Control Frame Packet Counter */ | |
305 | u32 rxpf; /* 0x.6b4 - Receive Pause Frame Packet Counter */ | |
306 | u32 rxuo; /* 0x.6b8 - Receive Unknown OP Code Counter */ | |
307 | u32 raln; /* 0x.6bc - Receive Alignment Error Counter */ | |
308 | u32 rflr; /* 0x.6c0 - Receive Frame Length Error Counter */ | |
309 | u32 rcde; /* 0x.6c4 - Receive Code Error Counter */ | |
310 | u32 rcse; /* 0x.6c8 - Receive Carrier Sense Error Counter */ | |
311 | u32 rund; /* 0x.6cc - Receive Undersize Packet Counter */ | |
312 | u32 rovr; /* 0x.6d0 - Receive Oversize Packet Counter */ | |
313 | u32 rfrg; /* 0x.6d4 - Receive Fragments Counter */ | |
314 | u32 rjbr; /* 0x.6d8 - Receive Jabber Counter */ | |
315 | u32 rdrp; /* 0x.6dc - Receive Drop Counter */ | |
316 | u32 tbyt; /* 0x.6e0 - Transmit Byte Counter Counter */ | |
317 | u32 tpkt; /* 0x.6e4 - Transmit Packet Counter */ | |
318 | u32 tmca; /* 0x.6e8 - Transmit Multicast Packet Counter */ | |
319 | u32 tbca; /* 0x.6ec - Transmit Broadcast Packet Counter */ | |
320 | u32 txpf; /* 0x.6f0 - Transmit Pause Control Frame Counter */ | |
321 | u32 tdfr; /* 0x.6f4 - Transmit Deferral Packet Counter */ | |
322 | u32 tedf; /* 0x.6f8 - Transmit Excessive Deferral Packet Counter */ | |
323 | u32 tscl; /* 0x.6fc - Transmit Single Collision Packet Counter */ | |
324 | u32 tmcl; /* 0x.700 - Transmit Multiple Collision Packet Counter */ | |
325 | u32 tlcl; /* 0x.704 - Transmit Late Collision Packet Counter */ | |
326 | u32 txcl; /* 0x.708 - Transmit Excessive Collision Packet Counter */ | |
327 | u32 tncl; /* 0x.70c - Transmit Total Collision Counter */ | |
328 | u8 res1[4]; | |
329 | u32 tdrp; /* 0x.714 - Transmit Drop Frame Counter */ | |
330 | u32 tjbr; /* 0x.718 - Transmit Jabber Frame Counter */ | |
331 | u32 tfcs; /* 0x.71c - Transmit FCS Error Counter */ | |
332 | u32 txcf; /* 0x.720 - Transmit Control Frame Counter */ | |
333 | u32 tovr; /* 0x.724 - Transmit Oversize Frame Counter */ | |
334 | u32 tund; /* 0x.728 - Transmit Undersize Frame Counter */ | |
335 | u32 tfrg; /* 0x.72c - Transmit Fragments Frame Counter */ | |
336 | u32 car1; /* 0x.730 - Carry Register One */ | |
337 | u32 car2; /* 0x.734 - Carry Register Two */ | |
338 | u32 cam1; /* 0x.738 - Carry Mask Register One */ | |
339 | u32 cam2; /* 0x.73c - Carry Mask Register Two */ | |
340 | }; | |
341 | ||
342 | struct gfar_extra_stats { | |
343 | u64 kernel_dropped; | |
344 | u64 rx_large; | |
345 | u64 rx_short; | |
346 | u64 rx_nonoctet; | |
347 | u64 rx_crcerr; | |
348 | u64 rx_overrun; | |
349 | u64 rx_bsy; | |
350 | u64 rx_babr; | |
351 | u64 rx_trunc; | |
352 | u64 eberr; | |
353 | u64 tx_babt; | |
354 | u64 tx_underrun; | |
355 | u64 rx_skbmissing; | |
356 | u64 tx_timeout; | |
357 | }; | |
358 | ||
359 | #define GFAR_RMON_LEN ((sizeof(struct rmon_mib) - 16)/sizeof(u32)) | |
360 | #define GFAR_EXTRA_STATS_LEN (sizeof(struct gfar_extra_stats)/sizeof(u64)) | |
361 | ||
362 | /* Number of stats in the stats structure (ignore car and cam regs)*/ | |
363 | #define GFAR_STATS_LEN (GFAR_RMON_LEN + GFAR_EXTRA_STATS_LEN) | |
364 | ||
365 | #define GFAR_INFOSTR_LEN 32 | |
366 | ||
367 | struct gfar_stats { | |
368 | u64 extra[GFAR_EXTRA_STATS_LEN]; | |
369 | u64 rmon[GFAR_RMON_LEN]; | |
370 | }; | |
371 | ||
372 | ||
373 | struct gfar { | |
374 | u8 res1[16]; | |
375 | u32 ievent; /* 0x.010 - Interrupt Event Register */ | |
376 | u32 imask; /* 0x.014 - Interrupt Mask Register */ | |
377 | u32 edis; /* 0x.018 - Error Disabled Register */ | |
378 | u8 res2[4]; | |
379 | u32 ecntrl; /* 0x.020 - Ethernet Control Register */ | |
380 | u32 minflr; /* 0x.024 - Minimum Frame Length Register */ | |
381 | u32 ptv; /* 0x.028 - Pause Time Value Register */ | |
382 | u32 dmactrl; /* 0x.02c - DMA Control Register */ | |
383 | u32 tbipa; /* 0x.030 - TBI PHY Address Register */ | |
384 | u8 res3[88]; | |
385 | u32 fifo_tx_thr; /* 0x.08c - FIFO transmit threshold register */ | |
386 | u8 res4[8]; | |
387 | u32 fifo_tx_starve; /* 0x.098 - FIFO transmit starve register */ | |
388 | u32 fifo_tx_starve_shutoff; /* 0x.09c - FIFO transmit starve shutoff register */ | |
389 | u8 res5[96]; | |
390 | u32 tctrl; /* 0x.100 - Transmit Control Register */ | |
391 | u32 tstat; /* 0x.104 - Transmit Status Register */ | |
392 | u8 res6[4]; | |
393 | u32 tbdlen; /* 0x.10c - Transmit Buffer Descriptor Data Length Register */ | |
394 | u32 txic; /* 0x.110 - Transmit Interrupt Coalescing Configuration Register */ | |
395 | u8 res7[16]; | |
396 | u32 ctbptr; /* 0x.124 - Current Transmit Buffer Descriptor Pointer Register */ | |
397 | u8 res8[92]; | |
398 | u32 tbptr; /* 0x.184 - Transmit Buffer Descriptor Pointer Low Register */ | |
399 | u8 res9[124]; | |
400 | u32 tbase; /* 0x.204 - Transmit Descriptor Base Address Register */ | |
401 | u8 res10[168]; | |
402 | u32 ostbd; /* 0x.2b0 - Out-of-Sequence Transmit Buffer Descriptor Register */ | |
403 | u32 ostbdp; /* 0x.2b4 - Out-of-Sequence Transmit Data Buffer Pointer Register */ | |
404 | u8 res11[72]; | |
405 | u32 rctrl; /* 0x.300 - Receive Control Register */ | |
406 | u32 rstat; /* 0x.304 - Receive Status Register */ | |
407 | u8 res12[4]; | |
408 | u32 rbdlen; /* 0x.30c - RxBD Data Length Register */ | |
409 | u32 rxic; /* 0x.310 - Receive Interrupt Coalescing Configuration Register */ | |
410 | u8 res13[16]; | |
411 | u32 crbptr; /* 0x.324 - Current Receive Buffer Descriptor Pointer */ | |
412 | u8 res14[24]; | |
413 | u32 mrblr; /* 0x.340 - Maximum Receive Buffer Length Register */ | |
414 | u8 res15[64]; | |
415 | u32 rbptr; /* 0x.384 - Receive Buffer Descriptor Pointer */ | |
416 | u8 res16[124]; | |
417 | u32 rbase; /* 0x.404 - Receive Descriptor Base Address */ | |
418 | u8 res17[248]; | |
419 | u32 maccfg1; /* 0x.500 - MAC Configuration 1 Register */ | |
420 | u32 maccfg2; /* 0x.504 - MAC Configuration 2 Register */ | |
421 | u32 ipgifg; /* 0x.508 - Inter Packet Gap/Inter Frame Gap Register */ | |
422 | u32 hafdup; /* 0x.50c - Half Duplex Register */ | |
423 | u32 maxfrm; /* 0x.510 - Maximum Frame Length Register */ | |
424 | u8 res18[12]; | |
425 | u32 miimcfg; /* 0x.520 - MII Management Configuration Register */ | |
426 | u32 miimcom; /* 0x.524 - MII Management Command Register */ | |
427 | u32 miimadd; /* 0x.528 - MII Management Address Register */ | |
428 | u32 miimcon; /* 0x.52c - MII Management Control Register */ | |
429 | u32 miimstat; /* 0x.530 - MII Management Status Register */ | |
430 | u32 miimind; /* 0x.534 - MII Management Indicator Register */ | |
431 | u8 res19[4]; | |
432 | u32 ifstat; /* 0x.53c - Interface Status Register */ | |
433 | u32 macstnaddr1; /* 0x.540 - Station Address Part 1 Register */ | |
434 | u32 macstnaddr2; /* 0x.544 - Station Address Part 2 Register */ | |
435 | u8 res20[312]; | |
436 | struct rmon_mib rmon; | |
437 | u8 res21[192]; | |
438 | u32 iaddr0; /* 0x.800 - Indivdual address register 0 */ | |
439 | u32 iaddr1; /* 0x.804 - Indivdual address register 1 */ | |
440 | u32 iaddr2; /* 0x.808 - Indivdual address register 2 */ | |
441 | u32 iaddr3; /* 0x.80c - Indivdual address register 3 */ | |
442 | u32 iaddr4; /* 0x.810 - Indivdual address register 4 */ | |
443 | u32 iaddr5; /* 0x.814 - Indivdual address register 5 */ | |
444 | u32 iaddr6; /* 0x.818 - Indivdual address register 6 */ | |
445 | u32 iaddr7; /* 0x.81c - Indivdual address register 7 */ | |
446 | u8 res22[96]; | |
447 | u32 gaddr0; /* 0x.880 - Global address register 0 */ | |
448 | u32 gaddr1; /* 0x.884 - Global address register 1 */ | |
449 | u32 gaddr2; /* 0x.888 - Global address register 2 */ | |
450 | u32 gaddr3; /* 0x.88c - Global address register 3 */ | |
451 | u32 gaddr4; /* 0x.890 - Global address register 4 */ | |
452 | u32 gaddr5; /* 0x.894 - Global address register 5 */ | |
453 | u32 gaddr6; /* 0x.898 - Global address register 6 */ | |
454 | u32 gaddr7; /* 0x.89c - Global address register 7 */ | |
455 | u8 res23[856]; | |
456 | u32 attr; /* 0x.bf8 - Attributes Register */ | |
457 | u32 attreli; /* 0x.bfc - Attributes Extract Length and Extract Index Register */ | |
458 | u8 res24[1024]; | |
459 | ||
460 | }; | |
461 | ||
462 | /* Struct stolen almost completely (and shamelessly) from the FCC enet source | |
463 | * (Ok, that's not so true anymore, but there is a family resemblence) | |
464 | * The GFAR buffer descriptors track the ring buffers. The rx_bd_base | |
465 | * and tx_bd_base always point to the currently available buffer. | |
466 | * The dirty_tx tracks the current buffer that is being sent by the | |
467 | * controller. The cur_tx and dirty_tx are equal under both completely | |
468 | * empty and completely full conditions. The empty/ready indicator in | |
469 | * the buffer descriptor determines the actual condition. | |
470 | */ | |
471 | struct gfar_private { | |
472 | /* pointers to arrays of skbuffs for tx and rx */ | |
473 | struct sk_buff ** tx_skbuff; | |
474 | struct sk_buff ** rx_skbuff; | |
475 | ||
476 | /* indices pointing to the next free sbk in skb arrays */ | |
477 | u16 skb_curtx; | |
478 | u16 skb_currx; | |
479 | ||
480 | /* index of the first skb which hasn't been transmitted | |
481 | * yet. */ | |
482 | u16 skb_dirtytx; | |
483 | ||
484 | /* Configuration info for the coalescing features */ | |
485 | unsigned char txcoalescing; | |
486 | unsigned short txcount; | |
487 | unsigned short txtime; | |
488 | unsigned char rxcoalescing; | |
489 | unsigned short rxcount; | |
490 | unsigned short rxtime; | |
491 | ||
492 | /* GFAR addresses */ | |
493 | struct rxbd8 *rx_bd_base; /* Base addresses of Rx and Tx Buffers */ | |
494 | struct txbd8 *tx_bd_base; | |
495 | struct rxbd8 *cur_rx; /* Next free rx ring entry */ | |
496 | struct txbd8 *cur_tx; /* Next free ring entry */ | |
497 | struct txbd8 *dirty_tx; /* The Ring entry to be freed. */ | |
498 | struct gfar *regs; /* Pointer to the GFAR memory mapped Registers */ | |
499 | struct gfar *phyregs; | |
500 | struct work_struct tq; | |
501 | struct timer_list phy_info_timer; | |
502 | struct net_device_stats stats; /* linux network statistics */ | |
503 | struct gfar_extra_stats extra_stats; | |
504 | spinlock_t lock; | |
505 | unsigned int rx_buffer_size; | |
506 | unsigned int rx_stash_size; | |
507 | unsigned int tx_ring_size; | |
508 | unsigned int rx_ring_size; | |
509 | wait_queue_head_t rxcleanupq; | |
510 | unsigned int rxclean; | |
511 | ||
512 | /* Info structure initialized by board setup code */ | |
513 | unsigned int interruptTransmit; | |
514 | unsigned int interruptReceive; | |
515 | unsigned int interruptError; | |
516 | struct gianfar_platform_data *einfo; | |
517 | ||
518 | struct gfar_mii_info *mii_info; | |
519 | int oldspeed; | |
520 | int oldduplex; | |
521 | int oldlink; | |
522 | }; | |
523 | ||
524 | extern inline u32 gfar_read(volatile unsigned *addr) | |
525 | { | |
526 | u32 val; | |
527 | val = in_be32(addr); | |
528 | return val; | |
529 | } | |
530 | ||
531 | extern inline void gfar_write(volatile unsigned *addr, u32 val) | |
532 | { | |
533 | out_be32(addr, val); | |
534 | } | |
535 | ||
536 | extern struct ethtool_ops *gfar_op_array[]; | |
537 | ||
538 | #endif /* __GIANFAR_H */ |