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hamachi: Delete TX checksumming code commented out since 1999
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1/* hamachi.c: A Packet Engines GNIC-II Gigabit Ethernet driver for Linux. */
2/*
3 Written 1998-2000 by Donald Becker.
4 Updates 2000 by Keith Underwood.
5
6aa20a22 6 This software may be used and distributed according to the terms of
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7 the GNU General Public License (GPL), incorporated herein by reference.
8 Drivers based on or derived from this code fall under the GPL and must
9 retain the authorship, copyright and license notice. This file is not
10 a complete program and may only be used when the entire operating
11 system is licensed under the GPL.
12
13 The author may be reached as becker@scyld.com, or C/O
14 Scyld Computing Corporation
15 410 Severn Ave., Suite 210
16 Annapolis MD 21403
17
18 This driver is for the Packet Engines GNIC-II PCI Gigabit Ethernet
19 adapter.
20
21 Support and updates available at
22 http://www.scyld.com/network/hamachi.html
03a8c661 23 [link no longer provides useful info -jgarzik]
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24 or
25 http://www.parl.clemson.edu/~keithu/hamachi.html
26
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27*/
28
29#define DRV_NAME "hamachi"
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30#define DRV_VERSION "2.1"
31#define DRV_RELDATE "Sept 11, 2006"
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32
33
34/* A few user-configurable values. */
35
36static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
37#define final_version
38#define hamachi_debug debug
39/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
40static int max_interrupt_work = 40;
41static int mtu;
42/* Default values selected by testing on a dual processor PIII-450 */
43/* These six interrupt control parameters may be set directly when loading the
44 * module, or through the rx_params and tx_params variables
45 */
46static int max_rx_latency = 0x11;
47static int max_rx_gap = 0x05;
48static int min_rx_pkt = 0x18;
6aa20a22 49static int max_tx_latency = 0x00;
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50static int max_tx_gap = 0x00;
51static int min_tx_pkt = 0x30;
52
53/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
54 -Setting to > 1518 causes all frames to be copied
55 -Setting to 0 disables copies
56*/
57static int rx_copybreak;
58
59/* An override for the hardware detection of bus width.
60 Set to 1 to force 32 bit PCI bus detection. Set to 4 to force 64 bit.
61 Add 2 to disable parity detection.
62*/
63static int force32;
64
65
66/* Used to pass the media type, etc.
67 These exist for driver interoperability.
68 No media types are currently defined.
69 - The lower 4 bits are reserved for the media type.
70 - The next three bits may be set to one of the following:
71 0x00000000 : Autodetect PCI bus
72 0x00000010 : Force 32 bit PCI bus
73 0x00000020 : Disable parity detection
74 0x00000040 : Force 64 bit PCI bus
75 Default is autodetect
76 - The next bit can be used to force half-duplex. This is a bad
77 idea since no known implementations implement half-duplex, and,
78 in general, half-duplex for gigabit ethernet is a bad idea.
6aa20a22 79 0x00000080 : Force half-duplex
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80 Default is full-duplex.
81 - In the original driver, the ninth bit could be used to force
82 full-duplex. Maintain that for compatibility
83 0x00000200 : Force full-duplex
84*/
85#define MAX_UNITS 8 /* More are supported, limit only on options */
86static int options[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
87static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
88/* The Hamachi chipset supports 3 parameters each for Rx and Tx
89 * interruput management. Parameters will be loaded as specified into
6aa20a22 90 * the TxIntControl and RxIntControl registers.
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91 *
92 * The registers are arranged as follows:
93 * 23 - 16 15 - 8 7 - 0
94 * _________________________________
95 * | min_pkt | max_gap | max_latency |
96 * ---------------------------------
97 * min_pkt : The minimum number of packets processed between
6aa20a22 98 * interrupts.
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99 * max_gap : The maximum inter-packet gap in units of 8.192 us
100 * max_latency : The absolute time between interrupts in units of 8.192 us
6aa20a22 101 *
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102 */
103static int rx_params[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
104static int tx_params[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
105
106/* Operational parameters that are set at compile time. */
107
108/* Keep the ring sizes a power of two for compile efficiency.
109 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
110 Making the Tx ring too large decreases the effectiveness of channel
111 bonding and packet priority.
112 There are no ill effects from too-large receive rings, except for
113 excessive memory usage */
114/* Empirically it appears that the Tx ring needs to be a little bigger
115 for these Gbit adapters or you get into an overrun condition really
116 easily. Also, things appear to work a bit better in back-to-back
117 configurations if the Rx ring is 8 times the size of the Tx ring
118*/
119#define TX_RING_SIZE 64
120#define RX_RING_SIZE 512
121#define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct hamachi_desc)
122#define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct hamachi_desc)
123
124/*
125 * Enable netdev_ioctl. Added interrupt coalescing parameter adjustment.
126 * 2/19/99 Pete Wyckoff <wyckoff@ca.sandia.gov>
127 */
128
129/* play with 64-bit addrlen; seems to be a teensy bit slower --pw */
130/* #define ADDRLEN 64 */
131
132/*
133 * RX_CHECKSUM turns on card-generated receive checksum generation for
134 * TCP and UDP packets. Otherwise the upper layers do the calculation.
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135 * 3/10/1999 Pete Wyckoff <wyckoff@ca.sandia.gov>
136 */
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137
138/* Operational parameters that usually are not changed. */
139/* Time in jiffies before concluding the transmitter is hung. */
140#define TX_TIMEOUT (5*HZ)
141
d43c36dc 142#include <linux/capability.h>
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143#include <linux/module.h>
144#include <linux/kernel.h>
145#include <linux/string.h>
146#include <linux/timer.h>
147#include <linux/time.h>
148#include <linux/errno.h>
149#include <linux/ioport.h>
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150#include <linux/interrupt.h>
151#include <linux/pci.h>
152#include <linux/init.h>
153#include <linux/ethtool.h>
154#include <linux/mii.h>
155#include <linux/netdevice.h>
156#include <linux/etherdevice.h>
157#include <linux/skbuff.h>
158#include <linux/ip.h>
159#include <linux/delay.h>
160#include <linux/bitops.h>
161
162#include <asm/uaccess.h>
163#include <asm/processor.h> /* Processor type for cache alignment. */
164#include <asm/io.h>
165#include <asm/unaligned.h>
166#include <asm/cache.h>
167
98683956 168static const char version[] __devinitconst =
1da177e4 169KERN_INFO DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " Written by Donald Becker\n"
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170" Some modifications by Eric kasten <kasten@nscl.msu.edu>\n"
171" Further modifications by Keith Underwood <keithu@parl.clemson.edu>\n";
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172
173
174/* IP_MF appears to be only defined in <netinet/ip.h>, however,
175 we need it for hardware checksumming support. FYI... some of
176 the definitions in <netinet/ip.h> conflict/duplicate those in
177 other linux headers causing many compiler warnings.
178*/
179#ifndef IP_MF
6aa20a22 180 #define IP_MF 0x2000 /* IP more frags from <netinet/ip.h> */
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181#endif
182
183/* Define IP_OFFSET to be IPOPT_OFFSET */
184#ifndef IP_OFFSET
185 #ifdef IPOPT_OFFSET
186 #define IP_OFFSET IPOPT_OFFSET
187 #else
188 #define IP_OFFSET 2
189 #endif
190#endif
191
192#define RUN_AT(x) (jiffies + (x))
193
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194#ifndef ADDRLEN
195#define ADDRLEN 32
196#endif
197
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198/* Condensed bus+endian portability operations. */
199#if ADDRLEN == 64
200#define cpu_to_leXX(addr) cpu_to_le64(addr)
8e985918 201#define leXX_to_cpu(addr) le64_to_cpu(addr)
6aa20a22 202#else
1da177e4 203#define cpu_to_leXX(addr) cpu_to_le32(addr)
8e985918 204#define leXX_to_cpu(addr) le32_to_cpu(addr)
6aa20a22 205#endif
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206
207
208/*
209 Theory of Operation
210
211I. Board Compatibility
212
213This device driver is designed for the Packet Engines "Hamachi"
214Gigabit Ethernet chip. The only PCA currently supported is the GNIC-II 64-bit
21566Mhz PCI card.
216
217II. Board-specific settings
218
219No jumpers exist on the board. The chip supports software correction of
220various motherboard wiring errors, however this driver does not support
221that feature.
222
223III. Driver operation
224
225IIIa. Ring buffers
226
227The Hamachi uses a typical descriptor based bus-master architecture.
228The descriptor list is similar to that used by the Digital Tulip.
229This driver uses two statically allocated fixed-size descriptor lists
230formed into rings by a branch from the final descriptor to the beginning of
231the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
232
233This driver uses a zero-copy receive and transmit scheme similar my other
234network drivers.
235The driver allocates full frame size skbuffs for the Rx ring buffers at
236open() time and passes the skb->data field to the Hamachi as receive data
237buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
238a fresh skbuff is allocated and the frame is copied to the new skbuff.
239When the incoming frame is larger, the skbuff is passed directly up the
240protocol stack and replaced by a newly allocated skbuff.
241
242The RX_COPYBREAK value is chosen to trade-off the memory wasted by
243using a full-sized skbuff for small frames vs. the copying costs of larger
244frames. Gigabit cards are typically used on generously configured machines
245and the underfilled buffers have negligible impact compared to the benefit of
246a single allocation size, so the default value of zero results in never
247copying packets.
248
249IIIb/c. Transmit/Receive Structure
250
251The Rx and Tx descriptor structure are straight-forward, with no historical
252baggage that must be explained. Unlike the awkward DBDMA structure, there
253are no unused fields or option bits that had only one allowable setting.
254
255Two details should be noted about the descriptors: The chip supports both 32
256bit and 64 bit address structures, and the length field is overwritten on
257the receive descriptors. The descriptor length is set in the control word
258for each channel. The development driver uses 32 bit addresses only, however
25964 bit addresses may be enabled for 64 bit architectures e.g. the Alpha.
260
261IIId. Synchronization
262
263This driver is very similar to my other network drivers.
264The driver runs as two independent, single-threaded flows of control. One
265is the send-packet routine, which enforces single-threaded use by the
266dev->tbusy flag. The other thread is the interrupt handler, which is single
267threaded by the hardware and other software.
268
269The send packet thread has partial control over the Tx ring and 'dev->tbusy'
270flag. It sets the tbusy flag whenever it's queuing a Tx packet. If the next
271queue slot is empty, it clears the tbusy flag when finished otherwise it sets
272the 'hmp->tx_full' flag.
273
274The interrupt handler has exclusive control over the Rx ring and records stats
275from the Tx ring. After reaping the stats, it marks the Tx queue entry as
276empty by incrementing the dirty_tx mark. Iff the 'hmp->tx_full' flag is set, it
277clears both the tx_full and tbusy flags.
278
279IV. Notes
280
281Thanks to Kim Stearns of Packet Engines for providing a pair of GNIC-II boards.
282
283IVb. References
284
285Hamachi Engineering Design Specification, 5/15/97
286(Note: This version was marked "Confidential".)
287
288IVc. Errata
289
6aa20a22 290None noted.
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291
292V. Recent Changes
293
6aa20a22 29401/15/1999 EPK Enlargement of the TX and RX ring sizes. This appears
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295 to help avoid some stall conditions -- this needs further research.
296
6aa20a22 29701/15/1999 EPK Creation of the hamachi_tx function. This function cleans
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298 the Tx ring and is called from hamachi_start_xmit (this used to be
299 called from hamachi_interrupt but it tends to delay execution of the
300 interrupt handler and thus reduce bandwidth by reducing the latency
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301 between hamachi_rx()'s). Notably, some modification has been made so
302 that the cleaning loop checks only to make sure that the DescOwn bit
303 isn't set in the status flag since the card is not required
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304 to set the entire flag to zero after processing.
305
6aa20a22 30601/15/1999 EPK In the hamachi_start_tx function, the Tx ring full flag is
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307 checked before attempting to add a buffer to the ring. If the ring is full
308 an attempt is made to free any dirty buffers and thus find space for
309 the new buffer or the function returns non-zero which should case the
310 scheduler to reschedule the buffer later.
311
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31201/15/1999 EPK Some adjustments were made to the chip initialization.
313 End-to-end flow control should now be fully active and the interrupt
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314 algorithm vars have been changed. These could probably use further tuning.
315
31601/15/1999 EPK Added the max_{rx,tx}_latency options. These are used to
317 set the rx and tx latencies for the Hamachi interrupts. If you're having
318 problems with network stalls, try setting these to higher values.
319 Valid values are 0x00 through 0xff.
320
6aa20a22 32101/15/1999 EPK In general, the overall bandwidth has increased and
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322 latencies are better (sometimes by a factor of 2). Stalls are rare at
323 this point, however there still appears to be a bug somewhere between the
324 hardware and driver. TCP checksum errors under load also appear to be
325 eliminated at this point.
326
32701/18/1999 EPK Ensured that the DescEndRing bit was being set on both the
328 Rx and Tx rings. This appears to have been affecting whether a particular
329 peer-to-peer connection would hang under high load. I believe the Rx
330 rings was typically getting set correctly, but the Tx ring wasn't getting
331 the DescEndRing bit set during initialization. ??? Does this mean the
332 hamachi card is using the DescEndRing in processing even if a particular
6aa20a22 333 slot isn't in use -- hypothetically, the card might be searching the
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334 entire Tx ring for slots with the DescOwn bit set and then processing
335 them. If the DescEndRing bit isn't set, then it might just wander off
336 through memory until it hits a chunk of data with that bit set
337 and then looping back.
338
6aa20a22 33902/09/1999 EPK Added Michel Mueller's TxDMA Interrupt and Tx-timeout
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340 problem (TxCmd and RxCmd need only to be set when idle or stopped.
341
34202/09/1999 EPK Added code to check/reset dev->tbusy in hamachi_interrupt.
6aa20a22 343 (Michel Mueller pointed out the ``permanently busy'' potential
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344 problem here).
345
6aa20a22 34602/22/1999 EPK Added Pete Wyckoff's ioctl to control the Tx/Rx latencies.
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347
34802/23/1999 EPK Verified that the interrupt status field bits for Tx were
349 incorrectly defined and corrected (as per Michel Mueller).
350
35102/23/1999 EPK Corrected the Tx full check to check that at least 4 slots
352 were available before reseting the tbusy and tx_full flags
353 (as per Michel Mueller).
354
35503/11/1999 EPK Added Pete Wyckoff's hardware checksumming support.
356
35712/31/1999 KDU Cleaned up assorted things and added Don's code to force
35832 bit.
359
36002/20/2000 KDU Some of the control was just plain odd. Cleaned up the
361hamachi_start_xmit() and hamachi_interrupt() code. There is still some
6aa20a22 362re-structuring I would like to do.
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363
36403/01/2000 KDU Experimenting with a WIDE range of interrupt mitigation
365parameters on a dual P3-450 setup yielded the new default interrupt
366mitigation parameters. Tx should interrupt VERY infrequently due to
367Eric's scheme. Rx should be more often...
368
36903/13/2000 KDU Added a patch to make the Rx Checksum code interact
6aa20a22 370nicely with non-linux machines.
1da177e4 371
6aa20a22 37203/13/2000 KDU Experimented with some of the configuration values:
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373
374 -It seems that enabling PCI performance commands for descriptors
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375 (changing RxDMACtrl and TxDMACtrl lower nibble from 5 to D) has minimal
376 performance impact for any of my tests. (ttcp, netpipe, netperf) I will
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377 leave them that way until I hear further feedback.
378
6aa20a22 379 -Increasing the PCI_LATENCY_TIMER to 130
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380 (2 + (burst size of 128 * (0 wait states + 1))) seems to slightly
381 degrade performance. Leaving default at 64 pending further information.
382
6aa20a22 38303/14/2000 KDU Further tuning:
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384
385 -adjusted boguscnt in hamachi_rx() to depend on interrupt
386 mitigation parameters chosen.
387
6aa20a22 388 -Selected a set of interrupt parameters based on some extensive testing.
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389 These may change with more testing.
390
391TO DO:
392
393-Consider borrowing from the acenic driver code to check PCI_COMMAND for
394PCI_COMMAND_INVALIDATE. Set maximum burst size to cache line size in
395that case.
396
6aa20a22 397-fix the reset procedure. It doesn't quite work.
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398*/
399
400/* A few values that may be tweaked. */
401/* Size of each temporary Rx buffer, calculated as:
402 * 1518 bytes (ethernet packet) + 2 bytes (to get 8 byte alignment for
89d71a66 403 * the card) + 8 bytes of status info + 8 bytes for the Rx Checksum
1da177e4 404 */
89d71a66 405#define PKT_BUF_SZ 1536
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406
407/* For now, this is going to be set to the maximum size of an ethernet
408 * packet. Eventually, we may want to make it a variable that is
409 * related to the MTU
410 */
411#define MAX_FRAME_SIZE 1518
412
413/* The rest of these values should never change. */
414
415static void hamachi_timer(unsigned long data);
416
417enum capability_flags {CanHaveMII=1, };
f71e1309 418static const struct chip_info {
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419 u16 vendor_id, device_id, device_id_mask, pad;
420 const char *name;
421 void (*media_timer)(unsigned long data);
422 int flags;
423} chip_tbl[] = {
424 {0x1318, 0x0911, 0xffff, 0, "Hamachi GNIC-II", hamachi_timer, 0},
425 {0,},
426};
427
428/* Offsets to the Hamachi registers. Various sizes. */
429enum hamachi_offsets {
430 TxDMACtrl=0x00, TxCmd=0x04, TxStatus=0x06, TxPtr=0x08, TxCurPtr=0x10,
431 RxDMACtrl=0x20, RxCmd=0x24, RxStatus=0x26, RxPtr=0x28, RxCurPtr=0x30,
432 PCIClkMeas=0x060, MiscStatus=0x066, ChipRev=0x68, ChipReset=0x06B,
433 LEDCtrl=0x06C, VirtualJumpers=0x06D, GPIO=0x6E,
434 TxChecksum=0x074, RxChecksum=0x076,
435 TxIntrCtrl=0x078, RxIntrCtrl=0x07C,
436 InterruptEnable=0x080, InterruptClear=0x084, IntrStatus=0x088,
437 EventStatus=0x08C,
438 MACCnfg=0x0A0, FrameGap0=0x0A2, FrameGap1=0x0A4,
439 /* See enum MII_offsets below. */
440 MACCnfg2=0x0B0, RxDepth=0x0B8, FlowCtrl=0x0BC, MaxFrameSize=0x0CE,
441 AddrMode=0x0D0, StationAddr=0x0D2,
442 /* Gigabit AutoNegotiation. */
443 ANCtrl=0x0E0, ANStatus=0x0E2, ANXchngCtrl=0x0E4, ANAdvertise=0x0E8,
444 ANLinkPartnerAbility=0x0EA,
445 EECmdStatus=0x0F0, EEData=0x0F1, EEAddr=0x0F2,
446 FIFOcfg=0x0F8,
447};
448
449/* Offsets to the MII-mode registers. */
450enum MII_offsets {
451 MII_Cmd=0xA6, MII_Addr=0xA8, MII_Wr_Data=0xAA, MII_Rd_Data=0xAC,
452 MII_Status=0xAE,
453};
454
455/* Bits in the interrupt status/mask registers. */
456enum intr_status_bits {
457 IntrRxDone=0x01, IntrRxPCIFault=0x02, IntrRxPCIErr=0x04,
458 IntrTxDone=0x100, IntrTxPCIFault=0x200, IntrTxPCIErr=0x400,
459 LinkChange=0x10000, NegotiationChange=0x20000, StatsMax=0x40000, };
460
461/* The Hamachi Rx and Tx buffer descriptors. */
462struct hamachi_desc {
8e985918 463 __le32 status_n_length;
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464#if ADDRLEN == 64
465 u32 pad;
8e985918 466 __le64 addr;
1da177e4 467#else
8e985918 468 __le32 addr;
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469#endif
470};
471
472/* Bits in hamachi_desc.status_n_length */
473enum desc_status_bits {
6aa20a22 474 DescOwn=0x80000000, DescEndPacket=0x40000000, DescEndRing=0x20000000,
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475 DescIntr=0x10000000,
476};
477
478#define PRIV_ALIGN 15 /* Required alignment mask */
479#define MII_CNT 4
480struct hamachi_private {
481 /* Descriptor rings first for alignment. Tx requires a second descriptor
482 for status. */
483 struct hamachi_desc *rx_ring;
484 struct hamachi_desc *tx_ring;
485 struct sk_buff* rx_skbuff[RX_RING_SIZE];
486 struct sk_buff* tx_skbuff[TX_RING_SIZE];
487 dma_addr_t tx_ring_dma;
488 dma_addr_t rx_ring_dma;
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489 struct timer_list timer; /* Media selection timer. */
490 /* Frequently used and paired value: keep adjacent for cache effect. */
491 spinlock_t lock;
492 int chip_id;
493 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
494 unsigned int cur_tx, dirty_tx;
495 unsigned int rx_buf_sz; /* Based on MTU+slack. */
496 unsigned int tx_full:1; /* The Tx queue is full. */
497 unsigned int duplex_lock:1;
498 unsigned int default_port:4; /* Last dev->if_port value. */
499 /* MII transceiver section. */
500 int mii_cnt; /* MII device addresses. */
501 struct mii_if_info mii_if; /* MII lib hooks/info */
502 unsigned char phys[MII_CNT]; /* MII device addresses, only first one used. */
503 u32 rx_int_var, tx_int_var; /* interrupt control variables */
504 u32 option; /* Hold on to a copy of the options */
505 struct pci_dev *pci_dev;
506 void __iomem *base;
507};
508
509MODULE_AUTHOR("Donald Becker <becker@scyld.com>, Eric Kasten <kasten@nscl.msu.edu>, Keith Underwood <keithu@parl.clemson.edu>");
510MODULE_DESCRIPTION("Packet Engines 'Hamachi' GNIC-II Gigabit Ethernet driver");
511MODULE_LICENSE("GPL");
512
513module_param(max_interrupt_work, int, 0);
514module_param(mtu, int, 0);
515module_param(debug, int, 0);
516module_param(min_rx_pkt, int, 0);
517module_param(max_rx_gap, int, 0);
518module_param(max_rx_latency, int, 0);
519module_param(min_tx_pkt, int, 0);
520module_param(max_tx_gap, int, 0);
521module_param(max_tx_latency, int, 0);
522module_param(rx_copybreak, int, 0);
523module_param_array(rx_params, int, NULL, 0);
524module_param_array(tx_params, int, NULL, 0);
525module_param_array(options, int, NULL, 0);
526module_param_array(full_duplex, int, NULL, 0);
527module_param(force32, int, 0);
528MODULE_PARM_DESC(max_interrupt_work, "GNIC-II maximum events handled per interrupt");
529MODULE_PARM_DESC(mtu, "GNIC-II MTU (all boards)");
530MODULE_PARM_DESC(debug, "GNIC-II debug level (0-7)");
531MODULE_PARM_DESC(min_rx_pkt, "GNIC-II minimum Rx packets processed between interrupts");
532MODULE_PARM_DESC(max_rx_gap, "GNIC-II maximum Rx inter-packet gap in 8.192 microsecond units");
533MODULE_PARM_DESC(max_rx_latency, "GNIC-II time between Rx interrupts in 8.192 microsecond units");
534MODULE_PARM_DESC(min_tx_pkt, "GNIC-II minimum Tx packets processed between interrupts");
535MODULE_PARM_DESC(max_tx_gap, "GNIC-II maximum Tx inter-packet gap in 8.192 microsecond units");
536MODULE_PARM_DESC(max_tx_latency, "GNIC-II time between Tx interrupts in 8.192 microsecond units");
537MODULE_PARM_DESC(rx_copybreak, "GNIC-II copy breakpoint for copy-only-tiny-frames");
538MODULE_PARM_DESC(rx_params, "GNIC-II min_rx_pkt+max_rx_gap+max_rx_latency");
539MODULE_PARM_DESC(tx_params, "GNIC-II min_tx_pkt+max_tx_gap+max_tx_latency");
540MODULE_PARM_DESC(options, "GNIC-II Bits 0-3: media type, bits 4-6: as force32, bit 7: half duplex, bit 9 full duplex");
541MODULE_PARM_DESC(full_duplex, "GNIC-II full duplex setting(s) (1)");
542MODULE_PARM_DESC(force32, "GNIC-II: Bit 0: 32 bit PCI, bit 1: disable parity, bit 2: 64 bit PCI (all boards)");
6aa20a22 543
1da177e4
LT
544static int read_eeprom(void __iomem *ioaddr, int location);
545static int mdio_read(struct net_device *dev, int phy_id, int location);
546static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
547static int hamachi_open(struct net_device *dev);
548static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
549static void hamachi_timer(unsigned long data);
550static void hamachi_tx_timeout(struct net_device *dev);
551static void hamachi_init_ring(struct net_device *dev);
61357325
SH
552static netdev_tx_t hamachi_start_xmit(struct sk_buff *skb,
553 struct net_device *dev);
7d12e780 554static irqreturn_t hamachi_interrupt(int irq, void *dev_instance);
1da177e4
LT
555static int hamachi_rx(struct net_device *dev);
556static inline int hamachi_tx(struct net_device *dev);
557static void hamachi_error(struct net_device *dev, int intr_status);
558static int hamachi_close(struct net_device *dev);
559static struct net_device_stats *hamachi_get_stats(struct net_device *dev);
560static void set_rx_mode(struct net_device *dev);
7282d491
JG
561static const struct ethtool_ops ethtool_ops;
562static const struct ethtool_ops ethtool_ops_no_mii;
1da177e4 563
a8652d23
SH
564static const struct net_device_ops hamachi_netdev_ops = {
565 .ndo_open = hamachi_open,
566 .ndo_stop = hamachi_close,
567 .ndo_start_xmit = hamachi_start_xmit,
568 .ndo_get_stats = hamachi_get_stats,
569 .ndo_set_multicast_list = set_rx_mode,
570 .ndo_change_mtu = eth_change_mtu,
571 .ndo_validate_addr = eth_validate_addr,
fe96aaa1 572 .ndo_set_mac_address = eth_mac_addr,
a8652d23
SH
573 .ndo_tx_timeout = hamachi_tx_timeout,
574 .ndo_do_ioctl = netdev_ioctl,
575};
576
577
1da177e4
LT
578static int __devinit hamachi_init_one (struct pci_dev *pdev,
579 const struct pci_device_id *ent)
580{
581 struct hamachi_private *hmp;
582 int option, i, rx_int_var, tx_int_var, boguscnt;
583 int chip_id = ent->driver_data;
584 int irq;
585 void __iomem *ioaddr;
586 unsigned long base;
587 static int card_idx;
588 struct net_device *dev;
589 void *ring_space;
590 dma_addr_t ring_dma;
591 int ret = -ENOMEM;
592
593/* when built into the kernel, we only print version if device is found */
594#ifndef MODULE
595 static int printed_version;
596 if (!printed_version++)
597 printk(version);
598#endif
599
600 if (pci_enable_device(pdev)) {
601 ret = -EIO;
602 goto err_out;
603 }
604
605 base = pci_resource_start(pdev, 0);
606#ifdef __alpha__ /* Really "64 bit addrs" */
607 base |= (pci_resource_start(pdev, 1) << 32);
608#endif
609
610 pci_set_master(pdev);
611
612 i = pci_request_regions(pdev, DRV_NAME);
2e8a538d
JG
613 if (i)
614 return i;
1da177e4
LT
615
616 irq = pdev->irq;
617 ioaddr = ioremap(base, 0x400);
618 if (!ioaddr)
619 goto err_out_release;
620
621 dev = alloc_etherdev(sizeof(struct hamachi_private));
622 if (!dev)
623 goto err_out_iounmap;
624
1da177e4
LT
625 SET_NETDEV_DEV(dev, &pdev->dev);
626
1da177e4
LT
627 for (i = 0; i < 6; i++)
628 dev->dev_addr[i] = 1 ? read_eeprom(ioaddr, 4 + i)
629 : readb(ioaddr + StationAddr + i);
630
631#if ! defined(final_version)
632 if (hamachi_debug > 4)
633 for (i = 0; i < 0x10; i++)
634 printk("%2.2x%s",
635 read_eeprom(ioaddr, i), i % 16 != 15 ? " " : "\n");
636#endif
637
638 hmp = netdev_priv(dev);
639 spin_lock_init(&hmp->lock);
640
641 hmp->mii_if.dev = dev;
642 hmp->mii_if.mdio_read = mdio_read;
643 hmp->mii_if.mdio_write = mdio_write;
644 hmp->mii_if.phy_id_mask = 0x1f;
645 hmp->mii_if.reg_num_mask = 0x1f;
646
647 ring_space = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &ring_dma);
648 if (!ring_space)
649 goto err_out_cleardev;
650 hmp->tx_ring = (struct hamachi_desc *)ring_space;
651 hmp->tx_ring_dma = ring_dma;
652
653 ring_space = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &ring_dma);
654 if (!ring_space)
655 goto err_out_unmap_tx;
656 hmp->rx_ring = (struct hamachi_desc *)ring_space;
657 hmp->rx_ring_dma = ring_dma;
658
659 /* Check for options being passed in */
660 option = card_idx < MAX_UNITS ? options[card_idx] : 0;
661 if (dev->mem_start)
662 option = dev->mem_start;
663
664 /* If the bus size is misidentified, do the following. */
6aa20a22 665 force32 = force32 ? force32 :
1da177e4
LT
666 ((option >= 0) ? ((option & 0x00000070) >> 4) : 0 );
667 if (force32)
668 writeb(force32, ioaddr + VirtualJumpers);
669
670 /* Hmmm, do we really need to reset the chip???. */
671 writeb(0x01, ioaddr + ChipReset);
672
673 /* After a reset, the clock speed measurement of the PCI bus will not
674 * be valid for a moment. Wait for a little while until it is. If
675 * it takes more than 10ms, forget it.
676 */
6aa20a22 677 udelay(10);
1da177e4
LT
678 i = readb(ioaddr + PCIClkMeas);
679 for (boguscnt = 0; (!(i & 0x080)) && boguscnt < 1000; boguscnt++){
6aa20a22
JG
680 udelay(10);
681 i = readb(ioaddr + PCIClkMeas);
1da177e4
LT
682 }
683
684 hmp->base = ioaddr;
685 dev->base_addr = (unsigned long)ioaddr;
686 dev->irq = irq;
687 pci_set_drvdata(pdev, dev);
688
689 hmp->chip_id = chip_id;
690 hmp->pci_dev = pdev;
691
692 /* The lower four bits are the media type. */
693 if (option > 0) {
694 hmp->option = option;
695 if (option & 0x200)
696 hmp->mii_if.full_duplex = 1;
697 else if (option & 0x080)
698 hmp->mii_if.full_duplex = 0;
699 hmp->default_port = option & 15;
700 if (hmp->default_port)
701 hmp->mii_if.force_media = 1;
702 }
703 if (card_idx < MAX_UNITS && full_duplex[card_idx] > 0)
704 hmp->mii_if.full_duplex = 1;
705
706 /* lock the duplex mode if someone specified a value */
707 if (hmp->mii_if.full_duplex || (option & 0x080))
708 hmp->duplex_lock = 1;
709
710 /* Set interrupt tuning parameters */
711 max_rx_latency = max_rx_latency & 0x00ff;
712 max_rx_gap = max_rx_gap & 0x00ff;
713 min_rx_pkt = min_rx_pkt & 0x00ff;
714 max_tx_latency = max_tx_latency & 0x00ff;
715 max_tx_gap = max_tx_gap & 0x00ff;
716 min_tx_pkt = min_tx_pkt & 0x00ff;
717
718 rx_int_var = card_idx < MAX_UNITS ? rx_params[card_idx] : -1;
719 tx_int_var = card_idx < MAX_UNITS ? tx_params[card_idx] : -1;
6aa20a22 720 hmp->rx_int_var = rx_int_var >= 0 ? rx_int_var :
1da177e4 721 (min_rx_pkt << 16 | max_rx_gap << 8 | max_rx_latency);
6aa20a22 722 hmp->tx_int_var = tx_int_var >= 0 ? tx_int_var :
1da177e4
LT
723 (min_tx_pkt << 16 | max_tx_gap << 8 | max_tx_latency);
724
725
726 /* The Hamachi-specific entries in the device structure. */
a8652d23 727 dev->netdev_ops = &hamachi_netdev_ops;
1da177e4
LT
728 if (chip_tbl[hmp->chip_id].flags & CanHaveMII)
729 SET_ETHTOOL_OPS(dev, &ethtool_ops);
730 else
731 SET_ETHTOOL_OPS(dev, &ethtool_ops_no_mii);
1da177e4
LT
732 dev->watchdog_timeo = TX_TIMEOUT;
733 if (mtu)
734 dev->mtu = mtu;
735
736 i = register_netdev(dev);
737 if (i) {
738 ret = i;
739 goto err_out_unmap_rx;
740 }
741
e174961c 742 printk(KERN_INFO "%s: %s type %x at %p, %pM, IRQ %d.\n",
1da177e4 743 dev->name, chip_tbl[chip_id].name, readl(ioaddr + ChipRev),
e174961c 744 ioaddr, dev->dev_addr, irq);
1da177e4
LT
745 i = readb(ioaddr + PCIClkMeas);
746 printk(KERN_INFO "%s: %d-bit %d Mhz PCI bus (%d), Virtual Jumpers "
747 "%2.2x, LPA %4.4x.\n",
748 dev->name, readw(ioaddr + MiscStatus) & 1 ? 64 : 32,
749 i ? 2000/(i&0x7f) : 0, i&0x7f, (int)readb(ioaddr + VirtualJumpers),
750 readw(ioaddr + ANLinkPartnerAbility));
751
752 if (chip_tbl[hmp->chip_id].flags & CanHaveMII) {
753 int phy, phy_idx = 0;
754 for (phy = 0; phy < 32 && phy_idx < MII_CNT; phy++) {
755 int mii_status = mdio_read(dev, phy, MII_BMSR);
756 if (mii_status != 0xffff &&
757 mii_status != 0x0000) {
758 hmp->phys[phy_idx++] = phy;
759 hmp->mii_if.advertising = mdio_read(dev, phy, MII_ADVERTISE);
760 printk(KERN_INFO "%s: MII PHY found at address %d, status "
761 "0x%4.4x advertising %4.4x.\n",
762 dev->name, phy, mii_status, hmp->mii_if.advertising);
763 }
764 }
765 hmp->mii_cnt = phy_idx;
766 if (hmp->mii_cnt > 0)
767 hmp->mii_if.phy_id = hmp->phys[0];
768 else
769 memset(&hmp->mii_if, 0, sizeof(hmp->mii_if));
770 }
771 /* Configure gigabit autonegotiation. */
772 writew(0x0400, ioaddr + ANXchngCtrl); /* Enable legacy links. */
773 writew(0x08e0, ioaddr + ANAdvertise); /* Set our advertise word. */
774 writew(0x1000, ioaddr + ANCtrl); /* Enable negotiation */
775
776 card_idx++;
777 return 0;
778
779err_out_unmap_rx:
6aa20a22 780 pci_free_consistent(pdev, RX_TOTAL_SIZE, hmp->rx_ring,
1da177e4
LT
781 hmp->rx_ring_dma);
782err_out_unmap_tx:
6aa20a22 783 pci_free_consistent(pdev, TX_TOTAL_SIZE, hmp->tx_ring,
1da177e4
LT
784 hmp->tx_ring_dma);
785err_out_cleardev:
786 free_netdev (dev);
787err_out_iounmap:
788 iounmap(ioaddr);
789err_out_release:
790 pci_release_regions(pdev);
791err_out:
792 return ret;
793}
794
795static int __devinit read_eeprom(void __iomem *ioaddr, int location)
796{
797 int bogus_cnt = 1000;
798
799 /* We should check busy first - per docs -KDU */
800 while ((readb(ioaddr + EECmdStatus) & 0x40) && --bogus_cnt > 0);
801 writew(location, ioaddr + EEAddr);
802 writeb(0x02, ioaddr + EECmdStatus);
803 bogus_cnt = 1000;
804 while ((readb(ioaddr + EECmdStatus) & 0x40) && --bogus_cnt > 0);
805 if (hamachi_debug > 5)
806 printk(" EEPROM status is %2.2x after %d ticks.\n",
807 (int)readb(ioaddr + EECmdStatus), 1000- bogus_cnt);
808 return readb(ioaddr + EEData);
809}
810
811/* MII Managemen Data I/O accesses.
812 These routines assume the MDIO controller is idle, and do not exit until
813 the command is finished. */
814
815static int mdio_read(struct net_device *dev, int phy_id, int location)
816{
817 struct hamachi_private *hmp = netdev_priv(dev);
818 void __iomem *ioaddr = hmp->base;
819 int i;
820
821 /* We should check busy first - per docs -KDU */
822 for (i = 10000; i >= 0; i--)
823 if ((readw(ioaddr + MII_Status) & 1) == 0)
824 break;
825 writew((phy_id<<8) + location, ioaddr + MII_Addr);
826 writew(0x0001, ioaddr + MII_Cmd);
827 for (i = 10000; i >= 0; i--)
828 if ((readw(ioaddr + MII_Status) & 1) == 0)
829 break;
830 return readw(ioaddr + MII_Rd_Data);
831}
832
833static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
834{
835 struct hamachi_private *hmp = netdev_priv(dev);
836 void __iomem *ioaddr = hmp->base;
837 int i;
838
839 /* We should check busy first - per docs -KDU */
840 for (i = 10000; i >= 0; i--)
841 if ((readw(ioaddr + MII_Status) & 1) == 0)
842 break;
843 writew((phy_id<<8) + location, ioaddr + MII_Addr);
844 writew(value, ioaddr + MII_Wr_Data);
845
846 /* Wait for the command to finish. */
847 for (i = 10000; i >= 0; i--)
848 if ((readw(ioaddr + MII_Status) & 1) == 0)
849 break;
1da177e4
LT
850}
851
6aa20a22 852
1da177e4
LT
853static int hamachi_open(struct net_device *dev)
854{
855 struct hamachi_private *hmp = netdev_priv(dev);
856 void __iomem *ioaddr = hmp->base;
857 int i;
858 u32 rx_int_var, tx_int_var;
859 u16 fifo_info;
860
a0607fd3 861 i = request_irq(dev->irq, hamachi_interrupt, IRQF_SHARED, dev->name, dev);
1da177e4
LT
862 if (i)
863 return i;
864
865 if (hamachi_debug > 1)
866 printk(KERN_DEBUG "%s: hamachi_open() irq %d.\n",
867 dev->name, dev->irq);
868
869 hamachi_init_ring(dev);
870
871#if ADDRLEN == 64
872 /* writellll anyone ? */
8e985918
AV
873 writel(hmp->rx_ring_dma, ioaddr + RxPtr);
874 writel(hmp->rx_ring_dma >> 32, ioaddr + RxPtr + 4);
875 writel(hmp->tx_ring_dma, ioaddr + TxPtr);
876 writel(hmp->tx_ring_dma >> 32, ioaddr + TxPtr + 4);
1da177e4 877#else
8e985918
AV
878 writel(hmp->rx_ring_dma, ioaddr + RxPtr);
879 writel(hmp->tx_ring_dma, ioaddr + TxPtr);
1da177e4
LT
880#endif
881
6aa20a22 882 /* TODO: It would make sense to organize this as words since the card
1da177e4
LT
883 * documentation does. -KDU
884 */
885 for (i = 0; i < 6; i++)
886 writeb(dev->dev_addr[i], ioaddr + StationAddr + i);
887
888 /* Initialize other registers: with so many this eventually this will
889 converted to an offset/value list. */
890
891 /* Configure the FIFO */
892 fifo_info = (readw(ioaddr + GPIO) & 0x00C0) >> 6;
893 switch (fifo_info){
6aa20a22 894 case 0 :
1da177e4
LT
895 /* No FIFO */
896 writew(0x0000, ioaddr + FIFOcfg);
897 break;
6aa20a22 898 case 1 :
1da177e4
LT
899 /* Configure the FIFO for 512K external, 16K used for Tx. */
900 writew(0x0028, ioaddr + FIFOcfg);
901 break;
6aa20a22 902 case 2 :
1da177e4
LT
903 /* Configure the FIFO for 1024 external, 32K used for Tx. */
904 writew(0x004C, ioaddr + FIFOcfg);
905 break;
6aa20a22 906 case 3 :
1da177e4
LT
907 /* Configure the FIFO for 2048 external, 32K used for Tx. */
908 writew(0x006C, ioaddr + FIFOcfg);
909 break;
6aa20a22 910 default :
1da177e4
LT
911 printk(KERN_WARNING "%s: Unsupported external memory config!\n",
912 dev->name);
913 /* Default to no FIFO */
914 writew(0x0000, ioaddr + FIFOcfg);
915 break;
916 }
6aa20a22 917
1da177e4
LT
918 if (dev->if_port == 0)
919 dev->if_port = hmp->default_port;
920
921
922 /* Setting the Rx mode will start the Rx process. */
6aa20a22 923 /* If someone didn't choose a duplex, default to full-duplex */
1da177e4
LT
924 if (hmp->duplex_lock != 1)
925 hmp->mii_if.full_duplex = 1;
926
927 /* always 1, takes no more time to do it */
928 writew(0x0001, ioaddr + RxChecksum);
1da177e4 929 writew(0x0000, ioaddr + TxChecksum);
1da177e4
LT
930 writew(0x8000, ioaddr + MACCnfg); /* Soft reset the MAC */
931 writew(0x215F, ioaddr + MACCnfg);
6aa20a22 932 writew(0x000C, ioaddr + FrameGap0);
1da177e4
LT
933 /* WHAT?!?!? Why isn't this documented somewhere? -KDU */
934 writew(0x1018, ioaddr + FrameGap1);
935 /* Why do we enable receives/transmits here? -KDU */
936 writew(0x0780, ioaddr + MACCnfg2); /* Upper 16 bits control LEDs. */
937 /* Enable automatic generation of flow control frames, period 0xffff. */
938 writel(0x0030FFFF, ioaddr + FlowCtrl);
939 writew(MAX_FRAME_SIZE, ioaddr + MaxFrameSize); /* dev->mtu+14 ??? */
940
941 /* Enable legacy links. */
942 writew(0x0400, ioaddr + ANXchngCtrl); /* Enable legacy links. */
943 /* Initial Link LED to blinking red. */
944 writeb(0x03, ioaddr + LEDCtrl);
945
946 /* Configure interrupt mitigation. This has a great effect on
947 performance, so systems tuning should start here!. */
948
949 rx_int_var = hmp->rx_int_var;
950 tx_int_var = hmp->tx_int_var;
951
952 if (hamachi_debug > 1) {
953 printk("max_tx_latency: %d, max_tx_gap: %d, min_tx_pkt: %d\n",
6aa20a22 954 tx_int_var & 0x00ff, (tx_int_var & 0x00ff00) >> 8,
1da177e4
LT
955 (tx_int_var & 0x00ff0000) >> 16);
956 printk("max_rx_latency: %d, max_rx_gap: %d, min_rx_pkt: %d\n",
6aa20a22 957 rx_int_var & 0x00ff, (rx_int_var & 0x00ff00) >> 8,
1da177e4
LT
958 (rx_int_var & 0x00ff0000) >> 16);
959 printk("rx_int_var: %x, tx_int_var: %x\n", rx_int_var, tx_int_var);
960 }
961
6aa20a22
JG
962 writel(tx_int_var, ioaddr + TxIntrCtrl);
963 writel(rx_int_var, ioaddr + RxIntrCtrl);
1da177e4
LT
964
965 set_rx_mode(dev);
966
967 netif_start_queue(dev);
968
969 /* Enable interrupts by setting the interrupt mask. */
970 writel(0x80878787, ioaddr + InterruptEnable);
971 writew(0x0000, ioaddr + EventStatus); /* Clear non-interrupting events */
972
973 /* Configure and start the DMA channels. */
974 /* Burst sizes are in the low three bits: size = 4<<(val&7) */
975#if ADDRLEN == 64
976 writew(0x005D, ioaddr + RxDMACtrl); /* 128 dword bursts */
977 writew(0x005D, ioaddr + TxDMACtrl);
978#else
979 writew(0x001D, ioaddr + RxDMACtrl);
980 writew(0x001D, ioaddr + TxDMACtrl);
981#endif
982 writew(0x0001, ioaddr + RxCmd);
983
984 if (hamachi_debug > 2) {
985 printk(KERN_DEBUG "%s: Done hamachi_open(), status: Rx %x Tx %x.\n",
986 dev->name, readw(ioaddr + RxStatus), readw(ioaddr + TxStatus));
987 }
988 /* Set the timer to check for link beat. */
989 init_timer(&hmp->timer);
990 hmp->timer.expires = RUN_AT((24*HZ)/10); /* 2.4 sec. */
991 hmp->timer.data = (unsigned long)dev;
c061b18d 992 hmp->timer.function = hamachi_timer; /* timer handler */
1da177e4
LT
993 add_timer(&hmp->timer);
994
995 return 0;
996}
997
998static inline int hamachi_tx(struct net_device *dev)
999{
1000 struct hamachi_private *hmp = netdev_priv(dev);
1001
1002 /* Update the dirty pointer until we find an entry that is
1003 still owned by the card */
1004 for (; hmp->cur_tx - hmp->dirty_tx > 0; hmp->dirty_tx++) {
1005 int entry = hmp->dirty_tx % TX_RING_SIZE;
1006 struct sk_buff *skb;
1007
6aa20a22 1008 if (hmp->tx_ring[entry].status_n_length & cpu_to_le32(DescOwn))
1da177e4
LT
1009 break;
1010 /* Free the original skb. */
1011 skb = hmp->tx_skbuff[entry];
ddfce6bb 1012 if (skb) {
6aa20a22 1013 pci_unmap_single(hmp->pci_dev,
8e985918
AV
1014 leXX_to_cpu(hmp->tx_ring[entry].addr),
1015 skb->len, PCI_DMA_TODEVICE);
1da177e4
LT
1016 dev_kfree_skb(skb);
1017 hmp->tx_skbuff[entry] = NULL;
1018 }
1019 hmp->tx_ring[entry].status_n_length = 0;
6aa20a22 1020 if (entry >= TX_RING_SIZE-1)
1da177e4 1021 hmp->tx_ring[TX_RING_SIZE-1].status_n_length |=
6aa20a22 1022 cpu_to_le32(DescEndRing);
0b9be50b 1023 dev->stats.tx_packets++;
1da177e4
LT
1024 }
1025
1026 return 0;
1027}
1028
1029static void hamachi_timer(unsigned long data)
1030{
1031 struct net_device *dev = (struct net_device *)data;
1032 struct hamachi_private *hmp = netdev_priv(dev);
1033 void __iomem *ioaddr = hmp->base;
1034 int next_tick = 10*HZ;
1035
1036 if (hamachi_debug > 2) {
1037 printk(KERN_INFO "%s: Hamachi Autonegotiation status %4.4x, LPA "
1038 "%4.4x.\n", dev->name, readw(ioaddr + ANStatus),
1039 readw(ioaddr + ANLinkPartnerAbility));
1040 printk(KERN_INFO "%s: Autonegotiation regs %4.4x %4.4x %4.4x "
1041 "%4.4x %4.4x %4.4x.\n", dev->name,
1042 readw(ioaddr + 0x0e0),
1043 readw(ioaddr + 0x0e2),
1044 readw(ioaddr + 0x0e4),
1045 readw(ioaddr + 0x0e6),
1046 readw(ioaddr + 0x0e8),
1047 readw(ioaddr + 0x0eA));
1048 }
1049 /* We could do something here... nah. */
1050 hmp->timer.expires = RUN_AT(next_tick);
1051 add_timer(&hmp->timer);
1052}
1053
1054static void hamachi_tx_timeout(struct net_device *dev)
1055{
1056 int i;
1057 struct hamachi_private *hmp = netdev_priv(dev);
1058 void __iomem *ioaddr = hmp->base;
1059
1060 printk(KERN_WARNING "%s: Hamachi transmit timed out, status %8.8x,"
1061 " resetting...\n", dev->name, (int)readw(ioaddr + TxStatus));
1062
1063 {
1da177e4
LT
1064 printk(KERN_DEBUG " Rx ring %p: ", hmp->rx_ring);
1065 for (i = 0; i < RX_RING_SIZE; i++)
ad361c98
JP
1066 printk(KERN_CONT " %8.8x",
1067 le32_to_cpu(hmp->rx_ring[i].status_n_length));
1068 printk(KERN_CONT "\n");
1069 printk(KERN_DEBUG" Tx ring %p: ", hmp->tx_ring);
1da177e4 1070 for (i = 0; i < TX_RING_SIZE; i++)
ad361c98
JP
1071 printk(KERN_CONT " %4.4x",
1072 le32_to_cpu(hmp->tx_ring[i].status_n_length));
1073 printk(KERN_CONT "\n");
1da177e4
LT
1074 }
1075
6aa20a22 1076 /* Reinit the hardware and make sure the Rx and Tx processes
1da177e4
LT
1077 are up and running.
1078 */
1079 dev->if_port = 0;
1080 /* The right way to do Reset. -KDU
1081 * -Clear OWN bit in all Rx/Tx descriptors
1082 * -Wait 50 uS for channels to go idle
1083 * -Turn off MAC receiver
1084 * -Issue Reset
1085 */
6aa20a22 1086
1da177e4
LT
1087 for (i = 0; i < RX_RING_SIZE; i++)
1088 hmp->rx_ring[i].status_n_length &= cpu_to_le32(~DescOwn);
1089
1090 /* Presume that all packets in the Tx queue are gone if we have to
1091 * re-init the hardware.
1092 */
1093 for (i = 0; i < TX_RING_SIZE; i++){
1094 struct sk_buff *skb;
1095
1096 if (i >= TX_RING_SIZE - 1)
8e985918
AV
1097 hmp->tx_ring[i].status_n_length =
1098 cpu_to_le32(DescEndRing) |
1099 (hmp->tx_ring[i].status_n_length &
1100 cpu_to_le32(0x0000ffff));
6aa20a22 1101 else
8e985918 1102 hmp->tx_ring[i].status_n_length &= cpu_to_le32(0x0000ffff);
1da177e4
LT
1103 skb = hmp->tx_skbuff[i];
1104 if (skb){
8e985918 1105 pci_unmap_single(hmp->pci_dev, leXX_to_cpu(hmp->tx_ring[i].addr),
1da177e4
LT
1106 skb->len, PCI_DMA_TODEVICE);
1107 dev_kfree_skb(skb);
1108 hmp->tx_skbuff[i] = NULL;
1109 }
1110 }
1111
1112 udelay(60); /* Sleep 60 us just for safety sake */
1113 writew(0x0002, ioaddr + RxCmd); /* STOP Rx */
6aa20a22
JG
1114
1115 writeb(0x01, ioaddr + ChipReset); /* Reinit the hardware */
1da177e4
LT
1116
1117 hmp->tx_full = 0;
1118 hmp->cur_rx = hmp->cur_tx = 0;
1119 hmp->dirty_rx = hmp->dirty_tx = 0;
1120 /* Rx packets are also presumed lost; however, we need to make sure a
1121 * ring of buffers is in tact. -KDU
6aa20a22 1122 */
1da177e4
LT
1123 for (i = 0; i < RX_RING_SIZE; i++){
1124 struct sk_buff *skb = hmp->rx_skbuff[i];
1125
1126 if (skb){
8e985918
AV
1127 pci_unmap_single(hmp->pci_dev,
1128 leXX_to_cpu(hmp->rx_ring[i].addr),
1da177e4
LT
1129 hmp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1130 dev_kfree_skb(skb);
1131 hmp->rx_skbuff[i] = NULL;
1132 }
1133 }
1134 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
1135 for (i = 0; i < RX_RING_SIZE; i++) {
89d71a66
ED
1136 struct sk_buff *skb;
1137
1138 skb = netdev_alloc_skb_ip_align(dev, hmp->rx_buf_sz);
1da177e4
LT
1139 hmp->rx_skbuff[i] = skb;
1140 if (skb == NULL)
1141 break;
8eb60131 1142
6aa20a22 1143 hmp->rx_ring[i].addr = cpu_to_leXX(pci_map_single(hmp->pci_dev,
689be439 1144 skb->data, hmp->rx_buf_sz, PCI_DMA_FROMDEVICE));
6aa20a22 1145 hmp->rx_ring[i].status_n_length = cpu_to_le32(DescOwn |
1da177e4
LT
1146 DescEndPacket | DescIntr | (hmp->rx_buf_sz - 2));
1147 }
1148 hmp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
1149 /* Mark the last entry as wrapping the ring. */
1150 hmp->rx_ring[RX_RING_SIZE-1].status_n_length |= cpu_to_le32(DescEndRing);
1151
1152 /* Trigger an immediate transmit demand. */
cdd0db05 1153 dev->trans_start = jiffies; /* prevent tx timeout */
0b9be50b 1154 dev->stats.tx_errors++;
1da177e4
LT
1155
1156 /* Restart the chip's Tx/Rx processes . */
1157 writew(0x0002, ioaddr + TxCmd); /* STOP Tx */
1158 writew(0x0001, ioaddr + TxCmd); /* START Tx */
1159 writew(0x0001, ioaddr + RxCmd); /* START Rx */
1160
1161 netif_wake_queue(dev);
1162}
1163
1164
1165/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1166static void hamachi_init_ring(struct net_device *dev)
1167{
1168 struct hamachi_private *hmp = netdev_priv(dev);
1169 int i;
1170
1171 hmp->tx_full = 0;
1172 hmp->cur_rx = hmp->cur_tx = 0;
1173 hmp->dirty_rx = hmp->dirty_tx = 0;
1174
1da177e4 1175 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
6aa20a22
JG
1176 * card needs room to do 8 byte alignment, +2 so we can reserve
1177 * the first 2 bytes, and +16 gets room for the status word from the
1da177e4
LT
1178 * card. -KDU
1179 */
6aa20a22 1180 hmp->rx_buf_sz = (dev->mtu <= 1492 ? PKT_BUF_SZ :
89d71a66 1181 (((dev->mtu+26+7) & ~7) + 16));
1da177e4
LT
1182
1183 /* Initialize all Rx descriptors. */
1184 for (i = 0; i < RX_RING_SIZE; i++) {
1185 hmp->rx_ring[i].status_n_length = 0;
1186 hmp->rx_skbuff[i] = NULL;
1187 }
1188 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
1189 for (i = 0; i < RX_RING_SIZE; i++) {
7a36df8a 1190 struct sk_buff *skb = dev_alloc_skb(hmp->rx_buf_sz + 2);
1da177e4
LT
1191 hmp->rx_skbuff[i] = skb;
1192 if (skb == NULL)
1193 break;
1194 skb->dev = dev; /* Mark as being used by this device. */
1195 skb_reserve(skb, 2); /* 16 byte align the IP header. */
6aa20a22 1196 hmp->rx_ring[i].addr = cpu_to_leXX(pci_map_single(hmp->pci_dev,
689be439 1197 skb->data, hmp->rx_buf_sz, PCI_DMA_FROMDEVICE));
1da177e4 1198 /* -2 because it doesn't REALLY have that first 2 bytes -KDU */
6aa20a22 1199 hmp->rx_ring[i].status_n_length = cpu_to_le32(DescOwn |
1da177e4
LT
1200 DescEndPacket | DescIntr | (hmp->rx_buf_sz -2));
1201 }
1202 hmp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
1203 hmp->rx_ring[RX_RING_SIZE-1].status_n_length |= cpu_to_le32(DescEndRing);
1204
1205 for (i = 0; i < TX_RING_SIZE; i++) {
1206 hmp->tx_skbuff[i] = NULL;
1207 hmp->tx_ring[i].status_n_length = 0;
1208 }
1209 /* Mark the last entry of the ring */
1210 hmp->tx_ring[TX_RING_SIZE-1].status_n_length |= cpu_to_le32(DescEndRing);
1da177e4
LT
1211}
1212
1213
61357325
SH
1214static netdev_tx_t hamachi_start_xmit(struct sk_buff *skb,
1215 struct net_device *dev)
1da177e4
LT
1216{
1217 struct hamachi_private *hmp = netdev_priv(dev);
1218 unsigned entry;
1219 u16 status;
1220
6aa20a22 1221 /* Ok, now make sure that the queue has space before trying to
1da177e4
LT
1222 add another skbuff. if we return non-zero the scheduler
1223 should interpret this as a queue full and requeue the buffer
1224 for later.
1225 */
1226 if (hmp->tx_full) {
1227 /* We should NEVER reach this point -KDU */
1228 printk(KERN_WARNING "%s: Hamachi transmit queue full at slot %d.\n",dev->name, hmp->cur_tx);
1229
1230 /* Wake the potentially-idle transmit channel. */
1231 /* If we don't need to read status, DON'T -KDU */
1232 status=readw(hmp->base + TxStatus);
1233 if( !(status & 0x0001) || (status & 0x0002))
1234 writew(0x0001, hmp->base + TxCmd);
5b548140 1235 return NETDEV_TX_BUSY;
6aa20a22 1236 }
1da177e4
LT
1237
1238 /* Caution: the write order is important here, set the field
1239 with the "ownership" bits last. */
1240
1241 /* Calculate the next Tx descriptor entry. */
1242 entry = hmp->cur_tx % TX_RING_SIZE;
1243
1244 hmp->tx_skbuff[entry] = skb;
1245
6aa20a22 1246 hmp->tx_ring[entry].addr = cpu_to_leXX(pci_map_single(hmp->pci_dev,
1da177e4 1247 skb->data, skb->len, PCI_DMA_TODEVICE));
6aa20a22 1248
1da177e4
LT
1249 /* Hmmmm, could probably put a DescIntr on these, but the way
1250 the driver is currently coded makes Tx interrupts unnecessary
1251 since the clearing of the Tx ring is handled by the start_xmit
1252 routine. This organization helps mitigate the interrupts a
1253 bit and probably renders the max_tx_latency param useless.
6aa20a22 1254
1da177e4
LT
1255 Update: Putting a DescIntr bit on all of the descriptors and
1256 mitigating interrupt frequency with the tx_min_pkt parameter. -KDU
1257 */
1258 if (entry >= TX_RING_SIZE-1) /* Wrap ring */
1259 hmp->tx_ring[entry].status_n_length = cpu_to_le32(DescOwn |
1260 DescEndPacket | DescEndRing | DescIntr | skb->len);
1261 else
1262 hmp->tx_ring[entry].status_n_length = cpu_to_le32(DescOwn |
1263 DescEndPacket | DescIntr | skb->len);
1264 hmp->cur_tx++;
1265
1266 /* Non-x86 Todo: explicitly flush cache lines here. */
1267
1268 /* Wake the potentially-idle transmit channel. */
1269 /* If we don't need to read status, DON'T -KDU */
1270 status=readw(hmp->base + TxStatus);
1271 if( !(status & 0x0001) || (status & 0x0002))
1272 writew(0x0001, hmp->base + TxCmd);
1273
1274 /* Immediately before returning, let's clear as many entries as we can. */
1275 hamachi_tx(dev);
1276
1277 /* We should kick the bottom half here, since we are not accepting
1278 * interrupts with every packet. i.e. realize that Gigabit ethernet
1279 * can transmit faster than ordinary machines can load packets;
1280 * hence, any packet that got put off because we were in the transmit
1281 * routine should IMMEDIATELY get a chance to be re-queued. -KDU
1282 */
6aa20a22 1283 if ((hmp->cur_tx - hmp->dirty_tx) < (TX_RING_SIZE - 4))
1da177e4
LT
1284 netif_wake_queue(dev); /* Typical path */
1285 else {
1286 hmp->tx_full = 1;
1287 netif_stop_queue(dev);
1288 }
1da177e4
LT
1289
1290 if (hamachi_debug > 4) {
1291 printk(KERN_DEBUG "%s: Hamachi transmit frame #%d queued in slot %d.\n",
1292 dev->name, hmp->cur_tx, entry);
1293 }
6ed10654 1294 return NETDEV_TX_OK;
1da177e4
LT
1295}
1296
1297/* The interrupt handler does all of the Rx thread work and cleans up
1298 after the Tx thread. */
7d12e780 1299static irqreturn_t hamachi_interrupt(int irq, void *dev_instance)
1da177e4
LT
1300{
1301 struct net_device *dev = dev_instance;
1302 struct hamachi_private *hmp = netdev_priv(dev);
1303 void __iomem *ioaddr = hmp->base;
1304 long boguscnt = max_interrupt_work;
1305 int handled = 0;
1306
1307#ifndef final_version /* Can never occur. */
1308 if (dev == NULL) {
1309 printk (KERN_ERR "hamachi_interrupt(): irq %d for unknown device.\n", irq);
1310 return IRQ_NONE;
1311 }
1312#endif
1313
1314 spin_lock(&hmp->lock);
1315
1316 do {
1317 u32 intr_status = readl(ioaddr + InterruptClear);
1318
1319 if (hamachi_debug > 4)
1320 printk(KERN_DEBUG "%s: Hamachi interrupt, status %4.4x.\n",
1321 dev->name, intr_status);
1322
1323 if (intr_status == 0)
1324 break;
1325
1326 handled = 1;
1327
1328 if (intr_status & IntrRxDone)
1329 hamachi_rx(dev);
1330
1331 if (intr_status & IntrTxDone){
1332 /* This code should RARELY need to execute. After all, this is
1333 * a gigabit link, it should consume packets as fast as we put
1334 * them in AND we clear the Tx ring in hamachi_start_xmit().
6aa20a22 1335 */
1da177e4
LT
1336 if (hmp->tx_full){
1337 for (; hmp->cur_tx - hmp->dirty_tx > 0; hmp->dirty_tx++){
1338 int entry = hmp->dirty_tx % TX_RING_SIZE;
1339 struct sk_buff *skb;
1340
6aa20a22 1341 if (hmp->tx_ring[entry].status_n_length & cpu_to_le32(DescOwn))
1da177e4
LT
1342 break;
1343 skb = hmp->tx_skbuff[entry];
1344 /* Free the original skb. */
1345 if (skb){
6aa20a22 1346 pci_unmap_single(hmp->pci_dev,
8e985918 1347 leXX_to_cpu(hmp->tx_ring[entry].addr),
1da177e4
LT
1348 skb->len,
1349 PCI_DMA_TODEVICE);
1350 dev_kfree_skb_irq(skb);
1351 hmp->tx_skbuff[entry] = NULL;
1352 }
1353 hmp->tx_ring[entry].status_n_length = 0;
6aa20a22
JG
1354 if (entry >= TX_RING_SIZE-1)
1355 hmp->tx_ring[TX_RING_SIZE-1].status_n_length |=
1da177e4 1356 cpu_to_le32(DescEndRing);
0b9be50b 1357 dev->stats.tx_packets++;
1da177e4
LT
1358 }
1359 if (hmp->cur_tx - hmp->dirty_tx < TX_RING_SIZE - 4){
1360 /* The ring is no longer full */
1361 hmp->tx_full = 0;
1362 netif_wake_queue(dev);
1363 }
1364 } else {
1365 netif_wake_queue(dev);
1366 }
1367 }
1368
1369
1370 /* Abnormal error summary/uncommon events handlers. */
1371 if (intr_status &
1372 (IntrTxPCIFault | IntrTxPCIErr | IntrRxPCIFault | IntrRxPCIErr |
1373 LinkChange | NegotiationChange | StatsMax))
1374 hamachi_error(dev, intr_status);
1375
1376 if (--boguscnt < 0) {
1377 printk(KERN_WARNING "%s: Too much work at interrupt, status=0x%4.4x.\n",
1378 dev->name, intr_status);
1379 break;
1380 }
1381 } while (1);
1382
1383 if (hamachi_debug > 3)
1384 printk(KERN_DEBUG "%s: exiting interrupt, status=%#4.4x.\n",
1385 dev->name, readl(ioaddr + IntrStatus));
1386
1387#ifndef final_version
1388 /* Code that should never be run! Perhaps remove after testing.. */
1389 {
1390 static int stopit = 10;
1391 if (dev->start == 0 && --stopit < 0) {
1392 printk(KERN_ERR "%s: Emergency stop, looping startup interrupt.\n",
1393 dev->name);
1394 free_irq(irq, dev);
1395 }
1396 }
1397#endif
1398
1399 spin_unlock(&hmp->lock);
1400 return IRQ_RETVAL(handled);
1401}
1402
1403/* This routine is logically part of the interrupt handler, but separated
1404 for clarity and better register allocation. */
1405static int hamachi_rx(struct net_device *dev)
1406{
1407 struct hamachi_private *hmp = netdev_priv(dev);
1408 int entry = hmp->cur_rx % RX_RING_SIZE;
1409 int boguscnt = (hmp->dirty_rx + RX_RING_SIZE) - hmp->cur_rx;
1410
1411 if (hamachi_debug > 4) {
1412 printk(KERN_DEBUG " In hamachi_rx(), entry %d status %4.4x.\n",
1413 entry, hmp->rx_ring[entry].status_n_length);
1414 }
1415
1416 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1417 while (1) {
1418 struct hamachi_desc *desc = &(hmp->rx_ring[entry]);
1419 u32 desc_status = le32_to_cpu(desc->status_n_length);
1420 u16 data_size = desc_status; /* Implicit truncate */
6aa20a22 1421 u8 *buf_addr;
1da177e4 1422 s32 frame_status;
6aa20a22 1423
1da177e4
LT
1424 if (desc_status & DescOwn)
1425 break;
1426 pci_dma_sync_single_for_cpu(hmp->pci_dev,
8e985918 1427 leXX_to_cpu(desc->addr),
1da177e4
LT
1428 hmp->rx_buf_sz,
1429 PCI_DMA_FROMDEVICE);
689be439 1430 buf_addr = (u8 *) hmp->rx_skbuff[entry]->data;
6caf52a4 1431 frame_status = get_unaligned_le32(&(buf_addr[data_size - 12]));
1da177e4
LT
1432 if (hamachi_debug > 4)
1433 printk(KERN_DEBUG " hamachi_rx() status was %8.8x.\n",
1434 frame_status);
1435 if (--boguscnt < 0)
1436 break;
1437 if ( ! (desc_status & DescEndPacket)) {
1438 printk(KERN_WARNING "%s: Oversized Ethernet frame spanned "
1439 "multiple buffers, entry %#x length %d status %4.4x!\n",
1440 dev->name, hmp->cur_rx, data_size, desc_status);
1441 printk(KERN_WARNING "%s: Oversized Ethernet frame %p vs %p.\n",
1442 dev->name, desc, &hmp->rx_ring[hmp->cur_rx % RX_RING_SIZE]);
1443 printk(KERN_WARNING "%s: Oversized Ethernet frame -- next status %x/%x last status %x.\n",
1444 dev->name,
8e985918
AV
1445 le32_to_cpu(hmp->rx_ring[(hmp->cur_rx+1) % RX_RING_SIZE].status_n_length) & 0xffff0000,
1446 le32_to_cpu(hmp->rx_ring[(hmp->cur_rx+1) % RX_RING_SIZE].status_n_length) & 0x0000ffff,
1447 le32_to_cpu(hmp->rx_ring[(hmp->cur_rx-1) % RX_RING_SIZE].status_n_length));
0b9be50b 1448 dev->stats.rx_length_errors++;
1da177e4
LT
1449 } /* else Omit for prototype errata??? */
1450 if (frame_status & 0x00380000) {
1451 /* There was an error. */
1452 if (hamachi_debug > 2)
1453 printk(KERN_DEBUG " hamachi_rx() Rx error was %8.8x.\n",
1454 frame_status);
0b9be50b
KV
1455 dev->stats.rx_errors++;
1456 if (frame_status & 0x00600000)
1457 dev->stats.rx_length_errors++;
1458 if (frame_status & 0x00080000)
1459 dev->stats.rx_frame_errors++;
1460 if (frame_status & 0x00100000)
1461 dev->stats.rx_crc_errors++;
1462 if (frame_status < 0)
1463 dev->stats.rx_dropped++;
1da177e4
LT
1464 } else {
1465 struct sk_buff *skb;
1466 /* Omit CRC */
6aa20a22 1467 u16 pkt_len = (frame_status & 0x07ff) - 4;
1da177e4
LT
1468#ifdef RX_CHECKSUM
1469 u32 pfck = *(u32 *) &buf_addr[data_size - 8];
1470#endif
1471
1472
1473#ifndef final_version
1474 if (hamachi_debug > 4)
1475 printk(KERN_DEBUG " hamachi_rx() normal Rx pkt length %d"
1476 " of %d, bogus_cnt %d.\n",
1477 pkt_len, data_size, boguscnt);
1478 if (hamachi_debug > 5)
1479 printk(KERN_DEBUG"%s: rx status %8.8x %8.8x %8.8x %8.8x %8.8x.\n",
1480 dev->name,
1481 *(s32*)&(buf_addr[data_size - 20]),
1482 *(s32*)&(buf_addr[data_size - 16]),
1483 *(s32*)&(buf_addr[data_size - 12]),
1484 *(s32*)&(buf_addr[data_size - 8]),
1485 *(s32*)&(buf_addr[data_size - 4]));
1486#endif
1487 /* Check if the packet is long enough to accept without copying
1488 to a minimally-sized skbuff. */
8e95a202
JP
1489 if (pkt_len < rx_copybreak &&
1490 (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1da177e4
LT
1491#ifdef RX_CHECKSUM
1492 printk(KERN_ERR "%s: rx_copybreak non-zero "
1493 "not good with RX_CHECKSUM\n", dev->name);
1494#endif
1da177e4
LT
1495 skb_reserve(skb, 2); /* 16 byte align the IP header */
1496 pci_dma_sync_single_for_cpu(hmp->pci_dev,
8e985918 1497 leXX_to_cpu(hmp->rx_ring[entry].addr),
1da177e4
LT
1498 hmp->rx_buf_sz,
1499 PCI_DMA_FROMDEVICE);
1500 /* Call copy + cksum if available. */
1501#if 1 || USE_IP_COPYSUM
8c7b7faa
DM
1502 skb_copy_to_linear_data(skb,
1503 hmp->rx_skbuff[entry]->data, pkt_len);
1da177e4
LT
1504 skb_put(skb, pkt_len);
1505#else
1506 memcpy(skb_put(skb, pkt_len), hmp->rx_ring_dma
1507 + entry*sizeof(*desc), pkt_len);
1508#endif
1509 pci_dma_sync_single_for_device(hmp->pci_dev,
8e985918 1510 leXX_to_cpu(hmp->rx_ring[entry].addr),
1da177e4
LT
1511 hmp->rx_buf_sz,
1512 PCI_DMA_FROMDEVICE);
1513 } else {
6aa20a22 1514 pci_unmap_single(hmp->pci_dev,
8e985918 1515 leXX_to_cpu(hmp->rx_ring[entry].addr),
1da177e4
LT
1516 hmp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1517 skb_put(skb = hmp->rx_skbuff[entry], pkt_len);
1518 hmp->rx_skbuff[entry] = NULL;
1519 }
1520 skb->protocol = eth_type_trans(skb, dev);
1521
1522
1523#ifdef RX_CHECKSUM
1524 /* TCP or UDP on ipv4, DIX encoding */
1525 if (pfck>>24 == 0x91 || pfck>>24 == 0x51) {
1526 struct iphdr *ih = (struct iphdr *) skb->data;
1527 /* Check that IP packet is at least 46 bytes, otherwise,
1528 * there may be pad bytes included in the hardware checksum.
1529 * This wouldn't happen if everyone padded with 0.
1530 */
1531 if (ntohs(ih->tot_len) >= 46){
1532 /* don't worry about frags */
09640e63 1533 if (!(ih->frag_off & cpu_to_be16(IP_MF|IP_OFFSET))) {
1da177e4
LT
1534 u32 inv = *(u32 *) &buf_addr[data_size - 16];
1535 u32 *p = (u32 *) &buf_addr[data_size - 20];
1536 register u32 crc, p_r, p_r1;
1537
1538 if (inv & 4) {
1539 inv &= ~4;
1540 --p;
1541 }
1542 p_r = *p;
1543 p_r1 = *(p-1);
1544 switch (inv) {
6aa20a22 1545 case 0:
1da177e4
LT
1546 crc = (p_r & 0xffff) + (p_r >> 16);
1547 break;
6aa20a22 1548 case 1:
1da177e4 1549 crc = (p_r >> 16) + (p_r & 0xffff)
6aa20a22 1550 + (p_r1 >> 16 & 0xff00);
1da177e4 1551 break;
6aa20a22
JG
1552 case 2:
1553 crc = p_r + (p_r1 >> 16);
1da177e4 1554 break;
6aa20a22
JG
1555 case 3:
1556 crc = p_r + (p_r1 & 0xff00) + (p_r1 >> 16);
1da177e4
LT
1557 break;
1558 default: /*NOTREACHED*/ crc = 0;
1559 }
1560 if (crc & 0xffff0000) {
1561 crc &= 0xffff;
1562 ++crc;
1563 }
1564 /* tcp/udp will add in pseudo */
1565 skb->csum = ntohs(pfck & 0xffff);
1566 if (skb->csum > crc)
1567 skb->csum -= crc;
1568 else
1569 skb->csum += (~crc & 0xffff);
1570 /*
1571 * could do the pseudo myself and return
1572 * CHECKSUM_UNNECESSARY
1573 */
84fa7933 1574 skb->ip_summed = CHECKSUM_COMPLETE;
1da177e4 1575 }
6aa20a22 1576 }
1da177e4
LT
1577 }
1578#endif /* RX_CHECKSUM */
1579
1580 netif_rx(skb);
0b9be50b 1581 dev->stats.rx_packets++;
1da177e4
LT
1582 }
1583 entry = (++hmp->cur_rx) % RX_RING_SIZE;
1584 }
1585
1586 /* Refill the Rx ring buffers. */
1587 for (; hmp->cur_rx - hmp->dirty_rx > 0; hmp->dirty_rx++) {
1588 struct hamachi_desc *desc;
1589
1590 entry = hmp->dirty_rx % RX_RING_SIZE;
1591 desc = &(hmp->rx_ring[entry]);
1592 if (hmp->rx_skbuff[entry] == NULL) {
7a36df8a 1593 struct sk_buff *skb = dev_alloc_skb(hmp->rx_buf_sz + 2);
1da177e4
LT
1594
1595 hmp->rx_skbuff[entry] = skb;
1596 if (skb == NULL)
1597 break; /* Better luck next round. */
1598 skb->dev = dev; /* Mark as being used by this device. */
1599 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
6aa20a22 1600 desc->addr = cpu_to_leXX(pci_map_single(hmp->pci_dev,
689be439 1601 skb->data, hmp->rx_buf_sz, PCI_DMA_FROMDEVICE));
1da177e4
LT
1602 }
1603 desc->status_n_length = cpu_to_le32(hmp->rx_buf_sz);
1604 if (entry >= RX_RING_SIZE-1)
6aa20a22 1605 desc->status_n_length |= cpu_to_le32(DescOwn |
1da177e4
LT
1606 DescEndPacket | DescEndRing | DescIntr);
1607 else
6aa20a22 1608 desc->status_n_length |= cpu_to_le32(DescOwn |
1da177e4
LT
1609 DescEndPacket | DescIntr);
1610 }
1611
1612 /* Restart Rx engine if stopped. */
1613 /* If we don't need to check status, don't. -KDU */
1614 if (readw(hmp->base + RxStatus) & 0x0002)
1615 writew(0x0001, hmp->base + RxCmd);
1616
1617 return 0;
1618}
1619
1620/* This is more properly named "uncommon interrupt events", as it covers more
1621 than just errors. */
1622static void hamachi_error(struct net_device *dev, int intr_status)
1623{
1624 struct hamachi_private *hmp = netdev_priv(dev);
1625 void __iomem *ioaddr = hmp->base;
1626
1627 if (intr_status & (LinkChange|NegotiationChange)) {
1628 if (hamachi_debug > 1)
1629 printk(KERN_INFO "%s: Link changed: AutoNegotiation Ctrl"
1630 " %4.4x, Status %4.4x %4.4x Intr status %4.4x.\n",
1631 dev->name, readw(ioaddr + 0x0E0), readw(ioaddr + 0x0E2),
1632 readw(ioaddr + ANLinkPartnerAbility),
1633 readl(ioaddr + IntrStatus));
1634 if (readw(ioaddr + ANStatus) & 0x20)
1635 writeb(0x01, ioaddr + LEDCtrl);
1636 else
1637 writeb(0x03, ioaddr + LEDCtrl);
1638 }
1639 if (intr_status & StatsMax) {
1640 hamachi_get_stats(dev);
1641 /* Read the overflow bits to clear. */
1642 readl(ioaddr + 0x370);
1643 readl(ioaddr + 0x3F0);
1644 }
8e95a202
JP
1645 if ((intr_status & ~(LinkChange|StatsMax|NegotiationChange|IntrRxDone|IntrTxDone)) &&
1646 hamachi_debug)
1da177e4 1647 printk(KERN_ERR "%s: Something Wicked happened! %4.4x.\n",
8e95a202 1648 dev->name, intr_status);
1da177e4
LT
1649 /* Hmmmmm, it's not clear how to recover from PCI faults. */
1650 if (intr_status & (IntrTxPCIErr | IntrTxPCIFault))
0b9be50b 1651 dev->stats.tx_fifo_errors++;
1da177e4 1652 if (intr_status & (IntrRxPCIErr | IntrRxPCIFault))
0b9be50b 1653 dev->stats.rx_fifo_errors++;
1da177e4
LT
1654}
1655
1656static int hamachi_close(struct net_device *dev)
1657{
1658 struct hamachi_private *hmp = netdev_priv(dev);
1659 void __iomem *ioaddr = hmp->base;
1660 struct sk_buff *skb;
1661 int i;
1662
1663 netif_stop_queue(dev);
1664
1665 if (hamachi_debug > 1) {
1666 printk(KERN_DEBUG "%s: Shutting down ethercard, status was Tx %4.4x Rx %4.4x Int %2.2x.\n",
1667 dev->name, readw(ioaddr + TxStatus),
1668 readw(ioaddr + RxStatus), readl(ioaddr + IntrStatus));
1669 printk(KERN_DEBUG "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
1670 dev->name, hmp->cur_tx, hmp->dirty_tx, hmp->cur_rx, hmp->dirty_rx);
1671 }
1672
1673 /* Disable interrupts by clearing the interrupt mask. */
1674 writel(0x0000, ioaddr + InterruptEnable);
1675
1676 /* Stop the chip's Tx and Rx processes. */
1677 writel(2, ioaddr + RxCmd);
1678 writew(2, ioaddr + TxCmd);
1679
1680#ifdef __i386__
1681 if (hamachi_debug > 2) {
ad361c98 1682 printk(KERN_DEBUG " Tx ring at %8.8x:\n",
1da177e4
LT
1683 (int)hmp->tx_ring_dma);
1684 for (i = 0; i < TX_RING_SIZE; i++)
ad361c98 1685 printk(KERN_DEBUG " %c #%d desc. %8.8x %8.8x.\n",
1da177e4
LT
1686 readl(ioaddr + TxCurPtr) == (long)&hmp->tx_ring[i] ? '>' : ' ',
1687 i, hmp->tx_ring[i].status_n_length, hmp->tx_ring[i].addr);
ad361c98 1688 printk(KERN_DEBUG " Rx ring %8.8x:\n",
1da177e4
LT
1689 (int)hmp->rx_ring_dma);
1690 for (i = 0; i < RX_RING_SIZE; i++) {
1691 printk(KERN_DEBUG " %c #%d desc. %4.4x %8.8x\n",
1692 readl(ioaddr + RxCurPtr) == (long)&hmp->rx_ring[i] ? '>' : ' ',
1693 i, hmp->rx_ring[i].status_n_length, hmp->rx_ring[i].addr);
1694 if (hamachi_debug > 6) {
689be439 1695 if (*(u8*)hmp->rx_skbuff[i]->data != 0x69) {
1da177e4 1696 u16 *addr = (u16 *)
689be439 1697 hmp->rx_skbuff[i]->data;
1da177e4 1698 int j;
ad361c98 1699 printk(KERN_DEBUG "Addr: ");
1da177e4
LT
1700 for (j = 0; j < 0x50; j++)
1701 printk(" %4.4x", addr[j]);
1702 printk("\n");
1703 }
1704 }
1705 }
1706 }
1707#endif /* __i386__ debugging only */
1708
1709 free_irq(dev->irq, dev);
1710
1711 del_timer_sync(&hmp->timer);
1712
1713 /* Free all the skbuffs in the Rx queue. */
1714 for (i = 0; i < RX_RING_SIZE; i++) {
1715 skb = hmp->rx_skbuff[i];
1716 hmp->rx_ring[i].status_n_length = 0;
1da177e4 1717 if (skb) {
6aa20a22 1718 pci_unmap_single(hmp->pci_dev,
8e985918
AV
1719 leXX_to_cpu(hmp->rx_ring[i].addr),
1720 hmp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1da177e4
LT
1721 dev_kfree_skb(skb);
1722 hmp->rx_skbuff[i] = NULL;
1723 }
8e985918 1724 hmp->rx_ring[i].addr = cpu_to_leXX(0xBADF00D0); /* An invalid address. */
1da177e4
LT
1725 }
1726 for (i = 0; i < TX_RING_SIZE; i++) {
1727 skb = hmp->tx_skbuff[i];
1728 if (skb) {
6aa20a22 1729 pci_unmap_single(hmp->pci_dev,
8e985918
AV
1730 leXX_to_cpu(hmp->tx_ring[i].addr),
1731 skb->len, PCI_DMA_TODEVICE);
1da177e4
LT
1732 dev_kfree_skb(skb);
1733 hmp->tx_skbuff[i] = NULL;
1734 }
1735 }
1736
1737 writeb(0x00, ioaddr + LEDCtrl);
1738
1739 return 0;
1740}
1741
1742static struct net_device_stats *hamachi_get_stats(struct net_device *dev)
1743{
1744 struct hamachi_private *hmp = netdev_priv(dev);
1745 void __iomem *ioaddr = hmp->base;
1746
1747 /* We should lock this segment of code for SMP eventually, although
1748 the vulnerability window is very small and statistics are
1749 non-critical. */
1750 /* Ok, what goes here? This appears to be stuck at 21 packets
1751 according to ifconfig. It does get incremented in hamachi_tx(),
1752 so I think I'll comment it out here and see if better things
1753 happen.
6aa20a22 1754 */
0b9be50b
KV
1755 /* dev->stats.tx_packets = readl(ioaddr + 0x000); */
1756
1757 /* Total Uni+Brd+Multi */
1758 dev->stats.rx_bytes = readl(ioaddr + 0x330);
1759 /* Total Uni+Brd+Multi */
1760 dev->stats.tx_bytes = readl(ioaddr + 0x3B0);
1761 /* Multicast Rx */
1762 dev->stats.multicast = readl(ioaddr + 0x320);
1763
1764 /* Over+Undersized */
1765 dev->stats.rx_length_errors = readl(ioaddr + 0x368);
1766 /* Jabber */
1767 dev->stats.rx_over_errors = readl(ioaddr + 0x35C);
1768 /* Jabber */
1769 dev->stats.rx_crc_errors = readl(ioaddr + 0x360);
1770 /* Symbol Errs */
1771 dev->stats.rx_frame_errors = readl(ioaddr + 0x364);
1772 /* Dropped */
1773 dev->stats.rx_missed_errors = readl(ioaddr + 0x36C);
1774
1775 return &dev->stats;
1da177e4
LT
1776}
1777
1778static void set_rx_mode(struct net_device *dev)
1779{
1780 struct hamachi_private *hmp = netdev_priv(dev);
1781 void __iomem *ioaddr = hmp->base;
1782
1783 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1da177e4 1784 writew(0x000F, ioaddr + AddrMode);
4cd24eaf 1785 } else if ((netdev_mc_count(dev) > 63) || (dev->flags & IFF_ALLMULTI)) {
1da177e4
LT
1786 /* Too many to match, or accept all multicasts. */
1787 writew(0x000B, ioaddr + AddrMode);
4cd24eaf 1788 } else if (!netdev_mc_empty(dev)) { /* Must use the CAM filter. */
22bedad3 1789 struct netdev_hw_addr *ha;
48e2f183
JP
1790 int i = 0;
1791
22bedad3
JP
1792 netdev_for_each_mc_addr(ha, dev) {
1793 writel(*(u32 *)(ha->addr), ioaddr + 0x100 + i*8);
1794 writel(0x20000 | (*(u16 *)&ha->addr[4]),
1da177e4 1795 ioaddr + 0x104 + i*8);
48e2f183 1796 i++;
1da177e4
LT
1797 }
1798 /* Clear remaining entries. */
1799 for (; i < 64; i++)
1800 writel(0, ioaddr + 0x104 + i*8);
1801 writew(0x0003, ioaddr + AddrMode);
1802 } else { /* Normal, unicast/broadcast-only mode. */
1803 writew(0x0001, ioaddr + AddrMode);
1804 }
1805}
1806
1807static int check_if_running(struct net_device *dev)
1808{
1809 if (!netif_running(dev))
1810 return -EINVAL;
1811 return 0;
1812}
1813
1814static void hamachi_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1815{
1816 struct hamachi_private *np = netdev_priv(dev);
1817 strcpy(info->driver, DRV_NAME);
1818 strcpy(info->version, DRV_VERSION);
1819 strcpy(info->bus_info, pci_name(np->pci_dev));
1820}
1821
1822static int hamachi_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1823{
1824 struct hamachi_private *np = netdev_priv(dev);
1825 spin_lock_irq(&np->lock);
1826 mii_ethtool_gset(&np->mii_if, ecmd);
1827 spin_unlock_irq(&np->lock);
1828 return 0;
1829}
1830
1831static int hamachi_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1832{
1833 struct hamachi_private *np = netdev_priv(dev);
1834 int res;
1835 spin_lock_irq(&np->lock);
1836 res = mii_ethtool_sset(&np->mii_if, ecmd);
1837 spin_unlock_irq(&np->lock);
1838 return res;
1839}
1840
1841static int hamachi_nway_reset(struct net_device *dev)
1842{
1843 struct hamachi_private *np = netdev_priv(dev);
1844 return mii_nway_restart(&np->mii_if);
1845}
1846
1847static u32 hamachi_get_link(struct net_device *dev)
1848{
1849 struct hamachi_private *np = netdev_priv(dev);
1850 return mii_link_ok(&np->mii_if);
1851}
1852
7282d491 1853static const struct ethtool_ops ethtool_ops = {
1da177e4
LT
1854 .begin = check_if_running,
1855 .get_drvinfo = hamachi_get_drvinfo,
1856 .get_settings = hamachi_get_settings,
1857 .set_settings = hamachi_set_settings,
1858 .nway_reset = hamachi_nway_reset,
1859 .get_link = hamachi_get_link,
1860};
1861
7282d491 1862static const struct ethtool_ops ethtool_ops_no_mii = {
1da177e4
LT
1863 .begin = check_if_running,
1864 .get_drvinfo = hamachi_get_drvinfo,
1865};
1866
1867static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1868{
1869 struct hamachi_private *np = netdev_priv(dev);
1870 struct mii_ioctl_data *data = if_mii(rq);
1871 int rc;
1872
1873 if (!netif_running(dev))
1874 return -EINVAL;
1875
1876 if (cmd == (SIOCDEVPRIVATE+3)) { /* set rx,tx intr params */
1877 u32 *d = (u32 *)&rq->ifr_ifru;
1878 /* Should add this check here or an ordinary user can do nasty
1879 * things. -KDU
1880 *
1881 * TODO: Shut down the Rx and Tx engines while doing this.
1882 */
1883 if (!capable(CAP_NET_ADMIN))
1884 return -EPERM;
1885 writel(d[0], np->base + TxIntrCtrl);
1886 writel(d[1], np->base + RxIntrCtrl);
1887 printk(KERN_NOTICE "%s: tx %08x, rx %08x intr\n", dev->name,
1888 (u32) readl(np->base + TxIntrCtrl),
1889 (u32) readl(np->base + RxIntrCtrl));
1890 rc = 0;
1891 }
1892
1893 else {
1894 spin_lock_irq(&np->lock);
1895 rc = generic_mii_ioctl(&np->mii_if, data, cmd, NULL);
1896 spin_unlock_irq(&np->lock);
1897 }
1898
1899 return rc;
1900}
1901
1902
1903static void __devexit hamachi_remove_one (struct pci_dev *pdev)
1904{
1905 struct net_device *dev = pci_get_drvdata(pdev);
1906
1907 if (dev) {
1908 struct hamachi_private *hmp = netdev_priv(dev);
1909
6aa20a22 1910 pci_free_consistent(pdev, RX_TOTAL_SIZE, hmp->rx_ring,
1da177e4 1911 hmp->rx_ring_dma);
6aa20a22 1912 pci_free_consistent(pdev, TX_TOTAL_SIZE, hmp->tx_ring,
1da177e4
LT
1913 hmp->tx_ring_dma);
1914 unregister_netdev(dev);
1915 iounmap(hmp->base);
1916 free_netdev(dev);
1917 pci_release_regions(pdev);
1918 pci_set_drvdata(pdev, NULL);
1919 }
1920}
1921
a3aa1884 1922static DEFINE_PCI_DEVICE_TABLE(hamachi_pci_tbl) = {
1da177e4
LT
1923 { 0x1318, 0x0911, PCI_ANY_ID, PCI_ANY_ID, },
1924 { 0, }
1925};
1926MODULE_DEVICE_TABLE(pci, hamachi_pci_tbl);
1927
1928static struct pci_driver hamachi_driver = {
1929 .name = DRV_NAME,
1930 .id_table = hamachi_pci_tbl,
1931 .probe = hamachi_init_one,
1932 .remove = __devexit_p(hamachi_remove_one),
1933};
1934
1935static int __init hamachi_init (void)
1936{
1937/* when a module, this is printed whether or not devices are found in probe */
1938#ifdef MODULE
1939 printk(version);
1940#endif
1941 return pci_register_driver(&hamachi_driver);
1942}
1943
1944static void __exit hamachi_exit (void)
1945{
1946 pci_unregister_driver(&hamachi_driver);
1947}
1948
1949
1950module_init(hamachi_init);
1951module_exit(hamachi_exit);