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9d5c8243 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel(R) Gigabit Ethernet Linux driver | |
4 | Copyright(c) 2007 Intel Corporation. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #include <linux/module.h> | |
29 | #include <linux/types.h> | |
30 | #include <linux/init.h> | |
31 | #include <linux/vmalloc.h> | |
32 | #include <linux/pagemap.h> | |
33 | #include <linux/netdevice.h> | |
9d5c8243 AK |
34 | #include <linux/ipv6.h> |
35 | #include <net/checksum.h> | |
36 | #include <net/ip6_checksum.h> | |
37 | #include <linux/mii.h> | |
38 | #include <linux/ethtool.h> | |
39 | #include <linux/if_vlan.h> | |
40 | #include <linux/pci.h> | |
41 | #include <linux/delay.h> | |
42 | #include <linux/interrupt.h> | |
43 | #include <linux/if_ether.h> | |
fe4506b6 JC |
44 | #ifdef CONFIG_DCA |
45 | #include <linux/dca.h> | |
46 | #endif | |
9d5c8243 AK |
47 | #include "igb.h" |
48 | ||
0024fd00 | 49 | #define DRV_VERSION "1.2.45-k2" |
9d5c8243 AK |
50 | char igb_driver_name[] = "igb"; |
51 | char igb_driver_version[] = DRV_VERSION; | |
52 | static const char igb_driver_string[] = | |
53 | "Intel(R) Gigabit Ethernet Network Driver"; | |
2d064c06 | 54 | static const char igb_copyright[] = "Copyright (c) 2008 Intel Corporation."; |
9d5c8243 | 55 | |
9d5c8243 AK |
56 | static const struct e1000_info *igb_info_tbl[] = { |
57 | [board_82575] = &e1000_82575_info, | |
58 | }; | |
59 | ||
60 | static struct pci_device_id igb_pci_tbl[] = { | |
2d064c06 AD |
61 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, |
62 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, | |
63 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, | |
9d5c8243 AK |
64 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, |
65 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, | |
66 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, | |
67 | /* required last entry */ | |
68 | {0, } | |
69 | }; | |
70 | ||
71 | MODULE_DEVICE_TABLE(pci, igb_pci_tbl); | |
72 | ||
73 | void igb_reset(struct igb_adapter *); | |
74 | static int igb_setup_all_tx_resources(struct igb_adapter *); | |
75 | static int igb_setup_all_rx_resources(struct igb_adapter *); | |
76 | static void igb_free_all_tx_resources(struct igb_adapter *); | |
77 | static void igb_free_all_rx_resources(struct igb_adapter *); | |
3b644cf6 MW |
78 | static void igb_free_tx_resources(struct igb_ring *); |
79 | static void igb_free_rx_resources(struct igb_ring *); | |
9d5c8243 AK |
80 | void igb_update_stats(struct igb_adapter *); |
81 | static int igb_probe(struct pci_dev *, const struct pci_device_id *); | |
82 | static void __devexit igb_remove(struct pci_dev *pdev); | |
83 | static int igb_sw_init(struct igb_adapter *); | |
84 | static int igb_open(struct net_device *); | |
85 | static int igb_close(struct net_device *); | |
86 | static void igb_configure_tx(struct igb_adapter *); | |
87 | static void igb_configure_rx(struct igb_adapter *); | |
88 | static void igb_setup_rctl(struct igb_adapter *); | |
89 | static void igb_clean_all_tx_rings(struct igb_adapter *); | |
90 | static void igb_clean_all_rx_rings(struct igb_adapter *); | |
3b644cf6 MW |
91 | static void igb_clean_tx_ring(struct igb_ring *); |
92 | static void igb_clean_rx_ring(struct igb_ring *); | |
9d5c8243 AK |
93 | static void igb_set_multi(struct net_device *); |
94 | static void igb_update_phy_info(unsigned long); | |
95 | static void igb_watchdog(unsigned long); | |
96 | static void igb_watchdog_task(struct work_struct *); | |
97 | static int igb_xmit_frame_ring_adv(struct sk_buff *, struct net_device *, | |
98 | struct igb_ring *); | |
99 | static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *); | |
100 | static struct net_device_stats *igb_get_stats(struct net_device *); | |
101 | static int igb_change_mtu(struct net_device *, int); | |
102 | static int igb_set_mac(struct net_device *, void *); | |
103 | static irqreturn_t igb_intr(int irq, void *); | |
104 | static irqreturn_t igb_intr_msi(int irq, void *); | |
105 | static irqreturn_t igb_msix_other(int irq, void *); | |
106 | static irqreturn_t igb_msix_rx(int irq, void *); | |
107 | static irqreturn_t igb_msix_tx(int irq, void *); | |
108 | static int igb_clean_rx_ring_msix(struct napi_struct *, int); | |
fe4506b6 JC |
109 | #ifdef CONFIG_DCA |
110 | static void igb_update_rx_dca(struct igb_ring *); | |
111 | static void igb_update_tx_dca(struct igb_ring *); | |
112 | static void igb_setup_dca(struct igb_adapter *); | |
113 | #endif /* CONFIG_DCA */ | |
3b644cf6 | 114 | static bool igb_clean_tx_irq(struct igb_ring *); |
661086df | 115 | static int igb_poll(struct napi_struct *, int); |
3b644cf6 MW |
116 | static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int); |
117 | static void igb_alloc_rx_buffers_adv(struct igb_ring *, int); | |
d3352520 AD |
118 | #ifdef CONFIG_IGB_LRO |
119 | static int igb_get_skb_hdr(struct sk_buff *skb, void **, void **, u64 *, void *); | |
120 | #endif | |
9d5c8243 AK |
121 | static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); |
122 | static void igb_tx_timeout(struct net_device *); | |
123 | static void igb_reset_task(struct work_struct *); | |
124 | static void igb_vlan_rx_register(struct net_device *, struct vlan_group *); | |
125 | static void igb_vlan_rx_add_vid(struct net_device *, u16); | |
126 | static void igb_vlan_rx_kill_vid(struct net_device *, u16); | |
127 | static void igb_restore_vlan(struct igb_adapter *); | |
128 | ||
129 | static int igb_suspend(struct pci_dev *, pm_message_t); | |
130 | #ifdef CONFIG_PM | |
131 | static int igb_resume(struct pci_dev *); | |
132 | #endif | |
133 | static void igb_shutdown(struct pci_dev *); | |
fe4506b6 JC |
134 | #ifdef CONFIG_DCA |
135 | static int igb_notify_dca(struct notifier_block *, unsigned long, void *); | |
136 | static struct notifier_block dca_notifier = { | |
137 | .notifier_call = igb_notify_dca, | |
138 | .next = NULL, | |
139 | .priority = 0 | |
140 | }; | |
141 | #endif | |
9d5c8243 AK |
142 | |
143 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
144 | /* for netdump / net console */ | |
145 | static void igb_netpoll(struct net_device *); | |
146 | #endif | |
147 | ||
148 | static pci_ers_result_t igb_io_error_detected(struct pci_dev *, | |
149 | pci_channel_state_t); | |
150 | static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); | |
151 | static void igb_io_resume(struct pci_dev *); | |
152 | ||
153 | static struct pci_error_handlers igb_err_handler = { | |
154 | .error_detected = igb_io_error_detected, | |
155 | .slot_reset = igb_io_slot_reset, | |
156 | .resume = igb_io_resume, | |
157 | }; | |
158 | ||
159 | ||
160 | static struct pci_driver igb_driver = { | |
161 | .name = igb_driver_name, | |
162 | .id_table = igb_pci_tbl, | |
163 | .probe = igb_probe, | |
164 | .remove = __devexit_p(igb_remove), | |
165 | #ifdef CONFIG_PM | |
166 | /* Power Managment Hooks */ | |
167 | .suspend = igb_suspend, | |
168 | .resume = igb_resume, | |
169 | #endif | |
170 | .shutdown = igb_shutdown, | |
171 | .err_handler = &igb_err_handler | |
172 | }; | |
173 | ||
7dfc16fa AD |
174 | static int global_quad_port_a; /* global quad port a indication */ |
175 | ||
9d5c8243 AK |
176 | MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); |
177 | MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); | |
178 | MODULE_LICENSE("GPL"); | |
179 | MODULE_VERSION(DRV_VERSION); | |
180 | ||
181 | #ifdef DEBUG | |
182 | /** | |
183 | * igb_get_hw_dev_name - return device name string | |
184 | * used by hardware layer to print debugging information | |
185 | **/ | |
186 | char *igb_get_hw_dev_name(struct e1000_hw *hw) | |
187 | { | |
188 | struct igb_adapter *adapter = hw->back; | |
189 | return adapter->netdev->name; | |
190 | } | |
191 | #endif | |
192 | ||
193 | /** | |
194 | * igb_init_module - Driver Registration Routine | |
195 | * | |
196 | * igb_init_module is the first routine called when the driver is | |
197 | * loaded. All it does is register with the PCI subsystem. | |
198 | **/ | |
199 | static int __init igb_init_module(void) | |
200 | { | |
201 | int ret; | |
202 | printk(KERN_INFO "%s - version %s\n", | |
203 | igb_driver_string, igb_driver_version); | |
204 | ||
205 | printk(KERN_INFO "%s\n", igb_copyright); | |
206 | ||
7dfc16fa AD |
207 | global_quad_port_a = 0; |
208 | ||
9d5c8243 | 209 | ret = pci_register_driver(&igb_driver); |
fe4506b6 JC |
210 | #ifdef CONFIG_DCA |
211 | dca_register_notify(&dca_notifier); | |
212 | #endif | |
9d5c8243 AK |
213 | return ret; |
214 | } | |
215 | ||
216 | module_init(igb_init_module); | |
217 | ||
218 | /** | |
219 | * igb_exit_module - Driver Exit Cleanup Routine | |
220 | * | |
221 | * igb_exit_module is called just before the driver is removed | |
222 | * from memory. | |
223 | **/ | |
224 | static void __exit igb_exit_module(void) | |
225 | { | |
fe4506b6 JC |
226 | #ifdef CONFIG_DCA |
227 | dca_unregister_notify(&dca_notifier); | |
228 | #endif | |
9d5c8243 AK |
229 | pci_unregister_driver(&igb_driver); |
230 | } | |
231 | ||
232 | module_exit(igb_exit_module); | |
233 | ||
234 | /** | |
235 | * igb_alloc_queues - Allocate memory for all rings | |
236 | * @adapter: board private structure to initialize | |
237 | * | |
238 | * We allocate one ring per queue at run-time since we don't know the | |
239 | * number of queues at compile-time. | |
240 | **/ | |
241 | static int igb_alloc_queues(struct igb_adapter *adapter) | |
242 | { | |
243 | int i; | |
244 | ||
245 | adapter->tx_ring = kcalloc(adapter->num_tx_queues, | |
246 | sizeof(struct igb_ring), GFP_KERNEL); | |
247 | if (!adapter->tx_ring) | |
248 | return -ENOMEM; | |
249 | ||
250 | adapter->rx_ring = kcalloc(adapter->num_rx_queues, | |
251 | sizeof(struct igb_ring), GFP_KERNEL); | |
252 | if (!adapter->rx_ring) { | |
253 | kfree(adapter->tx_ring); | |
254 | return -ENOMEM; | |
255 | } | |
256 | ||
6eb5a7f1 AD |
257 | adapter->rx_ring->buddy = adapter->tx_ring; |
258 | ||
661086df PWJ |
259 | for (i = 0; i < adapter->num_tx_queues; i++) { |
260 | struct igb_ring *ring = &(adapter->tx_ring[i]); | |
261 | ring->adapter = adapter; | |
262 | ring->queue_index = i; | |
263 | } | |
9d5c8243 AK |
264 | for (i = 0; i < adapter->num_rx_queues; i++) { |
265 | struct igb_ring *ring = &(adapter->rx_ring[i]); | |
266 | ring->adapter = adapter; | |
844290e5 | 267 | ring->queue_index = i; |
9d5c8243 AK |
268 | ring->itr_register = E1000_ITR; |
269 | ||
844290e5 | 270 | /* set a default napi handler for each rx_ring */ |
661086df | 271 | netif_napi_add(adapter->netdev, &ring->napi, igb_poll, 64); |
9d5c8243 AK |
272 | } |
273 | return 0; | |
274 | } | |
275 | ||
a88f10ec AD |
276 | static void igb_free_queues(struct igb_adapter *adapter) |
277 | { | |
278 | int i; | |
279 | ||
280 | for (i = 0; i < adapter->num_rx_queues; i++) | |
281 | netif_napi_del(&adapter->rx_ring[i].napi); | |
282 | ||
283 | kfree(adapter->tx_ring); | |
284 | kfree(adapter->rx_ring); | |
285 | } | |
286 | ||
9d5c8243 AK |
287 | #define IGB_N0_QUEUE -1 |
288 | static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue, | |
289 | int tx_queue, int msix_vector) | |
290 | { | |
291 | u32 msixbm = 0; | |
292 | struct e1000_hw *hw = &adapter->hw; | |
2d064c06 AD |
293 | u32 ivar, index; |
294 | ||
295 | switch (hw->mac.type) { | |
296 | case e1000_82575: | |
9d5c8243 AK |
297 | /* The 82575 assigns vectors using a bitmask, which matches the |
298 | bitmask for the EICR/EIMS/EIMC registers. To assign one | |
299 | or more queues to a vector, we write the appropriate bits | |
300 | into the MSIXBM register for that vector. */ | |
301 | if (rx_queue > IGB_N0_QUEUE) { | |
302 | msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; | |
303 | adapter->rx_ring[rx_queue].eims_value = msixbm; | |
304 | } | |
305 | if (tx_queue > IGB_N0_QUEUE) { | |
306 | msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; | |
307 | adapter->tx_ring[tx_queue].eims_value = | |
308 | E1000_EICR_TX_QUEUE0 << tx_queue; | |
309 | } | |
310 | array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); | |
2d064c06 AD |
311 | break; |
312 | case e1000_82576: | |
106ef2fe | 313 | /* The 82576 uses a table-based method for assigning vectors. |
2d064c06 AD |
314 | Each queue has a single entry in the table to which we write |
315 | a vector number along with a "valid" bit. Sadly, the layout | |
316 | of the table is somewhat counterintuitive. */ | |
317 | if (rx_queue > IGB_N0_QUEUE) { | |
318 | index = (rx_queue & 0x7); | |
319 | ivar = array_rd32(E1000_IVAR0, index); | |
320 | if (rx_queue < 8) { | |
321 | /* vector goes into low byte of register */ | |
322 | ivar = ivar & 0xFFFFFF00; | |
323 | ivar |= msix_vector | E1000_IVAR_VALID; | |
324 | } else { | |
325 | /* vector goes into third byte of register */ | |
326 | ivar = ivar & 0xFF00FFFF; | |
327 | ivar |= (msix_vector | E1000_IVAR_VALID) << 16; | |
328 | } | |
329 | adapter->rx_ring[rx_queue].eims_value= 1 << msix_vector; | |
330 | array_wr32(E1000_IVAR0, index, ivar); | |
331 | } | |
332 | if (tx_queue > IGB_N0_QUEUE) { | |
333 | index = (tx_queue & 0x7); | |
334 | ivar = array_rd32(E1000_IVAR0, index); | |
335 | if (tx_queue < 8) { | |
336 | /* vector goes into second byte of register */ | |
337 | ivar = ivar & 0xFFFF00FF; | |
338 | ivar |= (msix_vector | E1000_IVAR_VALID) << 8; | |
339 | } else { | |
340 | /* vector goes into high byte of register */ | |
341 | ivar = ivar & 0x00FFFFFF; | |
342 | ivar |= (msix_vector | E1000_IVAR_VALID) << 24; | |
343 | } | |
344 | adapter->tx_ring[tx_queue].eims_value= 1 << msix_vector; | |
345 | array_wr32(E1000_IVAR0, index, ivar); | |
346 | } | |
347 | break; | |
348 | default: | |
349 | BUG(); | |
350 | break; | |
351 | } | |
9d5c8243 AK |
352 | } |
353 | ||
354 | /** | |
355 | * igb_configure_msix - Configure MSI-X hardware | |
356 | * | |
357 | * igb_configure_msix sets up the hardware to properly | |
358 | * generate MSI-X interrupts. | |
359 | **/ | |
360 | static void igb_configure_msix(struct igb_adapter *adapter) | |
361 | { | |
362 | u32 tmp; | |
363 | int i, vector = 0; | |
364 | struct e1000_hw *hw = &adapter->hw; | |
365 | ||
366 | adapter->eims_enable_mask = 0; | |
2d064c06 AD |
367 | if (hw->mac.type == e1000_82576) |
368 | /* Turn on MSI-X capability first, or our settings | |
369 | * won't stick. And it will take days to debug. */ | |
370 | wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | | |
371 | E1000_GPIE_PBA | E1000_GPIE_EIAME | | |
372 | E1000_GPIE_NSICR); | |
9d5c8243 AK |
373 | |
374 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
375 | struct igb_ring *tx_ring = &adapter->tx_ring[i]; | |
376 | igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++); | |
377 | adapter->eims_enable_mask |= tx_ring->eims_value; | |
378 | if (tx_ring->itr_val) | |
6eb5a7f1 | 379 | writel(tx_ring->itr_val, |
9d5c8243 AK |
380 | hw->hw_addr + tx_ring->itr_register); |
381 | else | |
382 | writel(1, hw->hw_addr + tx_ring->itr_register); | |
383 | } | |
384 | ||
385 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
386 | struct igb_ring *rx_ring = &adapter->rx_ring[i]; | |
25ac3c24 | 387 | rx_ring->buddy = NULL; |
9d5c8243 AK |
388 | igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++); |
389 | adapter->eims_enable_mask |= rx_ring->eims_value; | |
390 | if (rx_ring->itr_val) | |
6eb5a7f1 | 391 | writel(rx_ring->itr_val, |
9d5c8243 AK |
392 | hw->hw_addr + rx_ring->itr_register); |
393 | else | |
394 | writel(1, hw->hw_addr + rx_ring->itr_register); | |
395 | } | |
396 | ||
397 | ||
398 | /* set vector for other causes, i.e. link changes */ | |
2d064c06 AD |
399 | switch (hw->mac.type) { |
400 | case e1000_82575: | |
9d5c8243 AK |
401 | array_wr32(E1000_MSIXBM(0), vector++, |
402 | E1000_EIMS_OTHER); | |
403 | ||
9d5c8243 AK |
404 | tmp = rd32(E1000_CTRL_EXT); |
405 | /* enable MSI-X PBA support*/ | |
406 | tmp |= E1000_CTRL_EXT_PBA_CLR; | |
407 | ||
408 | /* Auto-Mask interrupts upon ICR read. */ | |
409 | tmp |= E1000_CTRL_EXT_EIAME; | |
410 | tmp |= E1000_CTRL_EXT_IRCA; | |
411 | ||
412 | wr32(E1000_CTRL_EXT, tmp); | |
413 | adapter->eims_enable_mask |= E1000_EIMS_OTHER; | |
844290e5 | 414 | adapter->eims_other = E1000_EIMS_OTHER; |
9d5c8243 | 415 | |
2d064c06 AD |
416 | break; |
417 | ||
418 | case e1000_82576: | |
419 | tmp = (vector++ | E1000_IVAR_VALID) << 8; | |
420 | wr32(E1000_IVAR_MISC, tmp); | |
421 | ||
422 | adapter->eims_enable_mask = (1 << (vector)) - 1; | |
423 | adapter->eims_other = 1 << (vector - 1); | |
424 | break; | |
425 | default: | |
426 | /* do nothing, since nothing else supports MSI-X */ | |
427 | break; | |
428 | } /* switch (hw->mac.type) */ | |
9d5c8243 AK |
429 | wrfl(); |
430 | } | |
431 | ||
432 | /** | |
433 | * igb_request_msix - Initialize MSI-X interrupts | |
434 | * | |
435 | * igb_request_msix allocates MSI-X vectors and requests interrupts from the | |
436 | * kernel. | |
437 | **/ | |
438 | static int igb_request_msix(struct igb_adapter *adapter) | |
439 | { | |
440 | struct net_device *netdev = adapter->netdev; | |
441 | int i, err = 0, vector = 0; | |
442 | ||
443 | vector = 0; | |
444 | ||
445 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
446 | struct igb_ring *ring = &(adapter->tx_ring[i]); | |
447 | sprintf(ring->name, "%s-tx%d", netdev->name, i); | |
448 | err = request_irq(adapter->msix_entries[vector].vector, | |
449 | &igb_msix_tx, 0, ring->name, | |
450 | &(adapter->tx_ring[i])); | |
451 | if (err) | |
452 | goto out; | |
453 | ring->itr_register = E1000_EITR(0) + (vector << 2); | |
6eb5a7f1 | 454 | ring->itr_val = 976; /* ~4000 ints/sec */ |
9d5c8243 AK |
455 | vector++; |
456 | } | |
457 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
458 | struct igb_ring *ring = &(adapter->rx_ring[i]); | |
459 | if (strlen(netdev->name) < (IFNAMSIZ - 5)) | |
460 | sprintf(ring->name, "%s-rx%d", netdev->name, i); | |
461 | else | |
462 | memcpy(ring->name, netdev->name, IFNAMSIZ); | |
463 | err = request_irq(adapter->msix_entries[vector].vector, | |
464 | &igb_msix_rx, 0, ring->name, | |
465 | &(adapter->rx_ring[i])); | |
466 | if (err) | |
467 | goto out; | |
468 | ring->itr_register = E1000_EITR(0) + (vector << 2); | |
469 | ring->itr_val = adapter->itr; | |
844290e5 PW |
470 | /* overwrite the poll routine for MSIX, we've already done |
471 | * netif_napi_add */ | |
472 | ring->napi.poll = &igb_clean_rx_ring_msix; | |
9d5c8243 AK |
473 | vector++; |
474 | } | |
475 | ||
476 | err = request_irq(adapter->msix_entries[vector].vector, | |
477 | &igb_msix_other, 0, netdev->name, netdev); | |
478 | if (err) | |
479 | goto out; | |
480 | ||
9d5c8243 AK |
481 | igb_configure_msix(adapter); |
482 | return 0; | |
483 | out: | |
484 | return err; | |
485 | } | |
486 | ||
487 | static void igb_reset_interrupt_capability(struct igb_adapter *adapter) | |
488 | { | |
489 | if (adapter->msix_entries) { | |
490 | pci_disable_msix(adapter->pdev); | |
491 | kfree(adapter->msix_entries); | |
492 | adapter->msix_entries = NULL; | |
7dfc16fa | 493 | } else if (adapter->flags & IGB_FLAG_HAS_MSI) |
9d5c8243 AK |
494 | pci_disable_msi(adapter->pdev); |
495 | return; | |
496 | } | |
497 | ||
498 | ||
499 | /** | |
500 | * igb_set_interrupt_capability - set MSI or MSI-X if supported | |
501 | * | |
502 | * Attempt to configure interrupts using the best available | |
503 | * capabilities of the hardware and kernel. | |
504 | **/ | |
505 | static void igb_set_interrupt_capability(struct igb_adapter *adapter) | |
506 | { | |
507 | int err; | |
508 | int numvecs, i; | |
509 | ||
510 | numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1; | |
511 | adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry), | |
512 | GFP_KERNEL); | |
513 | if (!adapter->msix_entries) | |
514 | goto msi_only; | |
515 | ||
516 | for (i = 0; i < numvecs; i++) | |
517 | adapter->msix_entries[i].entry = i; | |
518 | ||
519 | err = pci_enable_msix(adapter->pdev, | |
520 | adapter->msix_entries, | |
521 | numvecs); | |
522 | if (err == 0) | |
34a20e89 | 523 | goto out; |
9d5c8243 AK |
524 | |
525 | igb_reset_interrupt_capability(adapter); | |
526 | ||
527 | /* If we can't do MSI-X, try MSI */ | |
528 | msi_only: | |
529 | adapter->num_rx_queues = 1; | |
661086df | 530 | adapter->num_tx_queues = 1; |
9d5c8243 | 531 | if (!pci_enable_msi(adapter->pdev)) |
7dfc16fa | 532 | adapter->flags |= IGB_FLAG_HAS_MSI; |
34a20e89 | 533 | out: |
661086df | 534 | /* Notify the stack of the (possibly) reduced Tx Queue count. */ |
fd2ea0a7 | 535 | adapter->netdev->real_num_tx_queues = adapter->num_tx_queues; |
9d5c8243 AK |
536 | return; |
537 | } | |
538 | ||
539 | /** | |
540 | * igb_request_irq - initialize interrupts | |
541 | * | |
542 | * Attempts to configure interrupts using the best available | |
543 | * capabilities of the hardware and kernel. | |
544 | **/ | |
545 | static int igb_request_irq(struct igb_adapter *adapter) | |
546 | { | |
547 | struct net_device *netdev = adapter->netdev; | |
548 | struct e1000_hw *hw = &adapter->hw; | |
549 | int err = 0; | |
550 | ||
551 | if (adapter->msix_entries) { | |
552 | err = igb_request_msix(adapter); | |
844290e5 | 553 | if (!err) |
9d5c8243 | 554 | goto request_done; |
9d5c8243 AK |
555 | /* fall back to MSI */ |
556 | igb_reset_interrupt_capability(adapter); | |
557 | if (!pci_enable_msi(adapter->pdev)) | |
7dfc16fa | 558 | adapter->flags |= IGB_FLAG_HAS_MSI; |
9d5c8243 AK |
559 | igb_free_all_tx_resources(adapter); |
560 | igb_free_all_rx_resources(adapter); | |
561 | adapter->num_rx_queues = 1; | |
562 | igb_alloc_queues(adapter); | |
844290e5 | 563 | } else { |
2d064c06 AD |
564 | switch (hw->mac.type) { |
565 | case e1000_82575: | |
566 | wr32(E1000_MSIXBM(0), | |
567 | (E1000_EICR_RX_QUEUE0 | E1000_EIMS_OTHER)); | |
568 | break; | |
569 | case e1000_82576: | |
570 | wr32(E1000_IVAR0, E1000_IVAR_VALID); | |
571 | break; | |
572 | default: | |
573 | break; | |
574 | } | |
9d5c8243 | 575 | } |
844290e5 | 576 | |
7dfc16fa | 577 | if (adapter->flags & IGB_FLAG_HAS_MSI) { |
9d5c8243 AK |
578 | err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0, |
579 | netdev->name, netdev); | |
580 | if (!err) | |
581 | goto request_done; | |
582 | /* fall back to legacy interrupts */ | |
583 | igb_reset_interrupt_capability(adapter); | |
7dfc16fa | 584 | adapter->flags &= ~IGB_FLAG_HAS_MSI; |
9d5c8243 AK |
585 | } |
586 | ||
587 | err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED, | |
588 | netdev->name, netdev); | |
589 | ||
6cb5e577 | 590 | if (err) |
9d5c8243 AK |
591 | dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n", |
592 | err); | |
9d5c8243 AK |
593 | |
594 | request_done: | |
595 | return err; | |
596 | } | |
597 | ||
598 | static void igb_free_irq(struct igb_adapter *adapter) | |
599 | { | |
600 | struct net_device *netdev = adapter->netdev; | |
601 | ||
602 | if (adapter->msix_entries) { | |
603 | int vector = 0, i; | |
604 | ||
605 | for (i = 0; i < adapter->num_tx_queues; i++) | |
606 | free_irq(adapter->msix_entries[vector++].vector, | |
607 | &(adapter->tx_ring[i])); | |
608 | for (i = 0; i < adapter->num_rx_queues; i++) | |
609 | free_irq(adapter->msix_entries[vector++].vector, | |
610 | &(adapter->rx_ring[i])); | |
611 | ||
612 | free_irq(adapter->msix_entries[vector++].vector, netdev); | |
613 | return; | |
614 | } | |
615 | ||
616 | free_irq(adapter->pdev->irq, netdev); | |
617 | } | |
618 | ||
619 | /** | |
620 | * igb_irq_disable - Mask off interrupt generation on the NIC | |
621 | * @adapter: board private structure | |
622 | **/ | |
623 | static void igb_irq_disable(struct igb_adapter *adapter) | |
624 | { | |
625 | struct e1000_hw *hw = &adapter->hw; | |
626 | ||
627 | if (adapter->msix_entries) { | |
844290e5 | 628 | wr32(E1000_EIAM, 0); |
9d5c8243 AK |
629 | wr32(E1000_EIMC, ~0); |
630 | wr32(E1000_EIAC, 0); | |
631 | } | |
844290e5 PW |
632 | |
633 | wr32(E1000_IAM, 0); | |
9d5c8243 AK |
634 | wr32(E1000_IMC, ~0); |
635 | wrfl(); | |
636 | synchronize_irq(adapter->pdev->irq); | |
637 | } | |
638 | ||
639 | /** | |
640 | * igb_irq_enable - Enable default interrupt generation settings | |
641 | * @adapter: board private structure | |
642 | **/ | |
643 | static void igb_irq_enable(struct igb_adapter *adapter) | |
644 | { | |
645 | struct e1000_hw *hw = &adapter->hw; | |
646 | ||
647 | if (adapter->msix_entries) { | |
844290e5 PW |
648 | wr32(E1000_EIAC, adapter->eims_enable_mask); |
649 | wr32(E1000_EIAM, adapter->eims_enable_mask); | |
650 | wr32(E1000_EIMS, adapter->eims_enable_mask); | |
9d5c8243 | 651 | wr32(E1000_IMS, E1000_IMS_LSC); |
844290e5 PW |
652 | } else { |
653 | wr32(E1000_IMS, IMS_ENABLE_MASK); | |
654 | wr32(E1000_IAM, IMS_ENABLE_MASK); | |
655 | } | |
9d5c8243 AK |
656 | } |
657 | ||
658 | static void igb_update_mng_vlan(struct igb_adapter *adapter) | |
659 | { | |
660 | struct net_device *netdev = adapter->netdev; | |
661 | u16 vid = adapter->hw.mng_cookie.vlan_id; | |
662 | u16 old_vid = adapter->mng_vlan_id; | |
663 | if (adapter->vlgrp) { | |
664 | if (!vlan_group_get_device(adapter->vlgrp, vid)) { | |
665 | if (adapter->hw.mng_cookie.status & | |
666 | E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { | |
667 | igb_vlan_rx_add_vid(netdev, vid); | |
668 | adapter->mng_vlan_id = vid; | |
669 | } else | |
670 | adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; | |
671 | ||
672 | if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && | |
673 | (vid != old_vid) && | |
674 | !vlan_group_get_device(adapter->vlgrp, old_vid)) | |
675 | igb_vlan_rx_kill_vid(netdev, old_vid); | |
676 | } else | |
677 | adapter->mng_vlan_id = vid; | |
678 | } | |
679 | } | |
680 | ||
681 | /** | |
682 | * igb_release_hw_control - release control of the h/w to f/w | |
683 | * @adapter: address of board private structure | |
684 | * | |
685 | * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. | |
686 | * For ASF and Pass Through versions of f/w this means that the | |
687 | * driver is no longer loaded. | |
688 | * | |
689 | **/ | |
690 | static void igb_release_hw_control(struct igb_adapter *adapter) | |
691 | { | |
692 | struct e1000_hw *hw = &adapter->hw; | |
693 | u32 ctrl_ext; | |
694 | ||
695 | /* Let firmware take over control of h/w */ | |
696 | ctrl_ext = rd32(E1000_CTRL_EXT); | |
697 | wr32(E1000_CTRL_EXT, | |
698 | ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); | |
699 | } | |
700 | ||
701 | ||
702 | /** | |
703 | * igb_get_hw_control - get control of the h/w from f/w | |
704 | * @adapter: address of board private structure | |
705 | * | |
706 | * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. | |
707 | * For ASF and Pass Through versions of f/w this means that | |
708 | * the driver is loaded. | |
709 | * | |
710 | **/ | |
711 | static void igb_get_hw_control(struct igb_adapter *adapter) | |
712 | { | |
713 | struct e1000_hw *hw = &adapter->hw; | |
714 | u32 ctrl_ext; | |
715 | ||
716 | /* Let firmware know the driver has taken over */ | |
717 | ctrl_ext = rd32(E1000_CTRL_EXT); | |
718 | wr32(E1000_CTRL_EXT, | |
719 | ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); | |
720 | } | |
721 | ||
9d5c8243 AK |
722 | /** |
723 | * igb_configure - configure the hardware for RX and TX | |
724 | * @adapter: private board structure | |
725 | **/ | |
726 | static void igb_configure(struct igb_adapter *adapter) | |
727 | { | |
728 | struct net_device *netdev = adapter->netdev; | |
729 | int i; | |
730 | ||
731 | igb_get_hw_control(adapter); | |
732 | igb_set_multi(netdev); | |
733 | ||
734 | igb_restore_vlan(adapter); | |
9d5c8243 AK |
735 | |
736 | igb_configure_tx(adapter); | |
737 | igb_setup_rctl(adapter); | |
738 | igb_configure_rx(adapter); | |
662d7205 AD |
739 | |
740 | igb_rx_fifo_flush_82575(&adapter->hw); | |
741 | ||
9d5c8243 AK |
742 | /* call IGB_DESC_UNUSED which always leaves |
743 | * at least 1 descriptor unused to make sure | |
744 | * next_to_use != next_to_clean */ | |
745 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
746 | struct igb_ring *ring = &adapter->rx_ring[i]; | |
3b644cf6 | 747 | igb_alloc_rx_buffers_adv(ring, IGB_DESC_UNUSED(ring)); |
9d5c8243 AK |
748 | } |
749 | ||
750 | ||
751 | adapter->tx_queue_len = netdev->tx_queue_len; | |
752 | } | |
753 | ||
754 | ||
755 | /** | |
756 | * igb_up - Open the interface and prepare it to handle traffic | |
757 | * @adapter: board private structure | |
758 | **/ | |
759 | ||
760 | int igb_up(struct igb_adapter *adapter) | |
761 | { | |
762 | struct e1000_hw *hw = &adapter->hw; | |
763 | int i; | |
764 | ||
765 | /* hardware has been reset, we need to reload some things */ | |
766 | igb_configure(adapter); | |
767 | ||
768 | clear_bit(__IGB_DOWN, &adapter->state); | |
769 | ||
844290e5 PW |
770 | for (i = 0; i < adapter->num_rx_queues; i++) |
771 | napi_enable(&adapter->rx_ring[i].napi); | |
772 | if (adapter->msix_entries) | |
9d5c8243 | 773 | igb_configure_msix(adapter); |
9d5c8243 AK |
774 | |
775 | /* Clear any pending interrupts. */ | |
776 | rd32(E1000_ICR); | |
777 | igb_irq_enable(adapter); | |
778 | ||
779 | /* Fire a link change interrupt to start the watchdog. */ | |
780 | wr32(E1000_ICS, E1000_ICS_LSC); | |
781 | return 0; | |
782 | } | |
783 | ||
784 | void igb_down(struct igb_adapter *adapter) | |
785 | { | |
786 | struct e1000_hw *hw = &adapter->hw; | |
787 | struct net_device *netdev = adapter->netdev; | |
788 | u32 tctl, rctl; | |
789 | int i; | |
790 | ||
791 | /* signal that we're down so the interrupt handler does not | |
792 | * reschedule our watchdog timer */ | |
793 | set_bit(__IGB_DOWN, &adapter->state); | |
794 | ||
795 | /* disable receives in the hardware */ | |
796 | rctl = rd32(E1000_RCTL); | |
797 | wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); | |
798 | /* flush and sleep below */ | |
799 | ||
fd2ea0a7 | 800 | netif_tx_stop_all_queues(netdev); |
9d5c8243 AK |
801 | |
802 | /* disable transmits in the hardware */ | |
803 | tctl = rd32(E1000_TCTL); | |
804 | tctl &= ~E1000_TCTL_EN; | |
805 | wr32(E1000_TCTL, tctl); | |
806 | /* flush both disables and wait for them to finish */ | |
807 | wrfl(); | |
808 | msleep(10); | |
809 | ||
844290e5 PW |
810 | for (i = 0; i < adapter->num_rx_queues; i++) |
811 | napi_disable(&adapter->rx_ring[i].napi); | |
9d5c8243 | 812 | |
9d5c8243 AK |
813 | igb_irq_disable(adapter); |
814 | ||
815 | del_timer_sync(&adapter->watchdog_timer); | |
816 | del_timer_sync(&adapter->phy_info_timer); | |
817 | ||
818 | netdev->tx_queue_len = adapter->tx_queue_len; | |
819 | netif_carrier_off(netdev); | |
820 | adapter->link_speed = 0; | |
821 | adapter->link_duplex = 0; | |
822 | ||
3023682e JK |
823 | if (!pci_channel_offline(adapter->pdev)) |
824 | igb_reset(adapter); | |
9d5c8243 AK |
825 | igb_clean_all_tx_rings(adapter); |
826 | igb_clean_all_rx_rings(adapter); | |
827 | } | |
828 | ||
829 | void igb_reinit_locked(struct igb_adapter *adapter) | |
830 | { | |
831 | WARN_ON(in_interrupt()); | |
832 | while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) | |
833 | msleep(1); | |
834 | igb_down(adapter); | |
835 | igb_up(adapter); | |
836 | clear_bit(__IGB_RESETTING, &adapter->state); | |
837 | } | |
838 | ||
839 | void igb_reset(struct igb_adapter *adapter) | |
840 | { | |
841 | struct e1000_hw *hw = &adapter->hw; | |
2d064c06 AD |
842 | struct e1000_mac_info *mac = &hw->mac; |
843 | struct e1000_fc_info *fc = &hw->fc; | |
9d5c8243 AK |
844 | u32 pba = 0, tx_space, min_tx_space, min_rx_space; |
845 | u16 hwm; | |
846 | ||
847 | /* Repartition Pba for greater than 9k mtu | |
848 | * To take effect CTRL.RST is required. | |
849 | */ | |
2d064c06 | 850 | if (mac->type != e1000_82576) { |
9d5c8243 | 851 | pba = E1000_PBA_34K; |
2d064c06 AD |
852 | } |
853 | else { | |
854 | pba = E1000_PBA_64K; | |
855 | } | |
9d5c8243 | 856 | |
2d064c06 AD |
857 | if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) && |
858 | (mac->type < e1000_82576)) { | |
9d5c8243 AK |
859 | /* adjust PBA for jumbo frames */ |
860 | wr32(E1000_PBA, pba); | |
861 | ||
862 | /* To maintain wire speed transmits, the Tx FIFO should be | |
863 | * large enough to accommodate two full transmit packets, | |
864 | * rounded up to the next 1KB and expressed in KB. Likewise, | |
865 | * the Rx FIFO should be large enough to accommodate at least | |
866 | * one full receive packet and is similarly rounded up and | |
867 | * expressed in KB. */ | |
868 | pba = rd32(E1000_PBA); | |
869 | /* upper 16 bits has Tx packet buffer allocation size in KB */ | |
870 | tx_space = pba >> 16; | |
871 | /* lower 16 bits has Rx packet buffer allocation size in KB */ | |
872 | pba &= 0xffff; | |
873 | /* the tx fifo also stores 16 bytes of information about the tx | |
874 | * but don't include ethernet FCS because hardware appends it */ | |
875 | min_tx_space = (adapter->max_frame_size + | |
876 | sizeof(struct e1000_tx_desc) - | |
877 | ETH_FCS_LEN) * 2; | |
878 | min_tx_space = ALIGN(min_tx_space, 1024); | |
879 | min_tx_space >>= 10; | |
880 | /* software strips receive CRC, so leave room for it */ | |
881 | min_rx_space = adapter->max_frame_size; | |
882 | min_rx_space = ALIGN(min_rx_space, 1024); | |
883 | min_rx_space >>= 10; | |
884 | ||
885 | /* If current Tx allocation is less than the min Tx FIFO size, | |
886 | * and the min Tx FIFO size is less than the current Rx FIFO | |
887 | * allocation, take space away from current Rx allocation */ | |
888 | if (tx_space < min_tx_space && | |
889 | ((min_tx_space - tx_space) < pba)) { | |
890 | pba = pba - (min_tx_space - tx_space); | |
891 | ||
892 | /* if short on rx space, rx wins and must trump tx | |
893 | * adjustment */ | |
894 | if (pba < min_rx_space) | |
895 | pba = min_rx_space; | |
896 | } | |
2d064c06 | 897 | wr32(E1000_PBA, pba); |
9d5c8243 | 898 | } |
9d5c8243 AK |
899 | |
900 | /* flow control settings */ | |
901 | /* The high water mark must be low enough to fit one full frame | |
902 | * (or the size used for early receive) above it in the Rx FIFO. | |
903 | * Set it to the lower of: | |
904 | * - 90% of the Rx FIFO size, or | |
905 | * - the full Rx FIFO size minus one full frame */ | |
906 | hwm = min(((pba << 10) * 9 / 10), | |
2d064c06 | 907 | ((pba << 10) - 2 * adapter->max_frame_size)); |
9d5c8243 | 908 | |
2d064c06 AD |
909 | if (mac->type < e1000_82576) { |
910 | fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */ | |
911 | fc->low_water = fc->high_water - 8; | |
912 | } else { | |
913 | fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */ | |
914 | fc->low_water = fc->high_water - 16; | |
915 | } | |
9d5c8243 AK |
916 | fc->pause_time = 0xFFFF; |
917 | fc->send_xon = 1; | |
918 | fc->type = fc->original_type; | |
919 | ||
920 | /* Allow time for pending master requests to run */ | |
921 | adapter->hw.mac.ops.reset_hw(&adapter->hw); | |
922 | wr32(E1000_WUC, 0); | |
923 | ||
924 | if (adapter->hw.mac.ops.init_hw(&adapter->hw)) | |
925 | dev_err(&adapter->pdev->dev, "Hardware Error\n"); | |
926 | ||
927 | igb_update_mng_vlan(adapter); | |
928 | ||
929 | /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ | |
930 | wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); | |
931 | ||
932 | igb_reset_adaptive(&adapter->hw); | |
68707acb BH |
933 | if (adapter->hw.phy.ops.get_phy_info) |
934 | adapter->hw.phy.ops.get_phy_info(&adapter->hw); | |
9d5c8243 AK |
935 | } |
936 | ||
42bfd33a TI |
937 | /** |
938 | * igb_is_need_ioport - determine if an adapter needs ioport resources or not | |
939 | * @pdev: PCI device information struct | |
940 | * | |
941 | * Returns true if an adapter needs ioport resources | |
942 | **/ | |
943 | static int igb_is_need_ioport(struct pci_dev *pdev) | |
944 | { | |
945 | switch (pdev->device) { | |
946 | /* Currently there are no adapters that need ioport resources */ | |
947 | default: | |
948 | return false; | |
949 | } | |
950 | } | |
951 | ||
9d5c8243 AK |
952 | /** |
953 | * igb_probe - Device Initialization Routine | |
954 | * @pdev: PCI device information struct | |
955 | * @ent: entry in igb_pci_tbl | |
956 | * | |
957 | * Returns 0 on success, negative on failure | |
958 | * | |
959 | * igb_probe initializes an adapter identified by a pci_dev structure. | |
960 | * The OS initialization, configuring of the adapter private structure, | |
961 | * and a hardware reset occur. | |
962 | **/ | |
963 | static int __devinit igb_probe(struct pci_dev *pdev, | |
964 | const struct pci_device_id *ent) | |
965 | { | |
966 | struct net_device *netdev; | |
967 | struct igb_adapter *adapter; | |
968 | struct e1000_hw *hw; | |
969 | const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; | |
970 | unsigned long mmio_start, mmio_len; | |
9d5c8243 AK |
971 | int i, err, pci_using_dac; |
972 | u16 eeprom_data = 0; | |
973 | u16 eeprom_apme_mask = IGB_EEPROM_APME; | |
974 | u32 part_num; | |
42bfd33a | 975 | int bars, need_ioport; |
9d5c8243 | 976 | |
42bfd33a TI |
977 | /* do not allocate ioport bars when not needed */ |
978 | need_ioport = igb_is_need_ioport(pdev); | |
979 | if (need_ioport) { | |
980 | bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO); | |
981 | err = pci_enable_device(pdev); | |
982 | } else { | |
983 | bars = pci_select_bars(pdev, IORESOURCE_MEM); | |
984 | err = pci_enable_device_mem(pdev); | |
985 | } | |
9d5c8243 AK |
986 | if (err) |
987 | return err; | |
988 | ||
989 | pci_using_dac = 0; | |
990 | err = pci_set_dma_mask(pdev, DMA_64BIT_MASK); | |
991 | if (!err) { | |
992 | err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); | |
993 | if (!err) | |
994 | pci_using_dac = 1; | |
995 | } else { | |
996 | err = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
997 | if (err) { | |
998 | err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
999 | if (err) { | |
1000 | dev_err(&pdev->dev, "No usable DMA " | |
1001 | "configuration, aborting\n"); | |
1002 | goto err_dma; | |
1003 | } | |
1004 | } | |
1005 | } | |
1006 | ||
42bfd33a | 1007 | err = pci_request_selected_regions(pdev, bars, igb_driver_name); |
9d5c8243 AK |
1008 | if (err) |
1009 | goto err_pci_reg; | |
1010 | ||
1011 | pci_set_master(pdev); | |
c682fc23 | 1012 | pci_save_state(pdev); |
9d5c8243 AK |
1013 | |
1014 | err = -ENOMEM; | |
661086df | 1015 | netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), IGB_MAX_TX_QUEUES); |
9d5c8243 AK |
1016 | if (!netdev) |
1017 | goto err_alloc_etherdev; | |
1018 | ||
1019 | SET_NETDEV_DEV(netdev, &pdev->dev); | |
1020 | ||
1021 | pci_set_drvdata(pdev, netdev); | |
1022 | adapter = netdev_priv(netdev); | |
1023 | adapter->netdev = netdev; | |
1024 | adapter->pdev = pdev; | |
1025 | hw = &adapter->hw; | |
1026 | hw->back = adapter; | |
1027 | adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE; | |
42bfd33a TI |
1028 | adapter->bars = bars; |
1029 | adapter->need_ioport = need_ioport; | |
9d5c8243 AK |
1030 | |
1031 | mmio_start = pci_resource_start(pdev, 0); | |
1032 | mmio_len = pci_resource_len(pdev, 0); | |
1033 | ||
1034 | err = -EIO; | |
1035 | adapter->hw.hw_addr = ioremap(mmio_start, mmio_len); | |
1036 | if (!adapter->hw.hw_addr) | |
1037 | goto err_ioremap; | |
1038 | ||
1039 | netdev->open = &igb_open; | |
1040 | netdev->stop = &igb_close; | |
1041 | netdev->get_stats = &igb_get_stats; | |
1042 | netdev->set_multicast_list = &igb_set_multi; | |
1043 | netdev->set_mac_address = &igb_set_mac; | |
1044 | netdev->change_mtu = &igb_change_mtu; | |
1045 | netdev->do_ioctl = &igb_ioctl; | |
1046 | igb_set_ethtool_ops(netdev); | |
1047 | netdev->tx_timeout = &igb_tx_timeout; | |
1048 | netdev->watchdog_timeo = 5 * HZ; | |
9d5c8243 AK |
1049 | netdev->vlan_rx_register = igb_vlan_rx_register; |
1050 | netdev->vlan_rx_add_vid = igb_vlan_rx_add_vid; | |
1051 | netdev->vlan_rx_kill_vid = igb_vlan_rx_kill_vid; | |
1052 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1053 | netdev->poll_controller = igb_netpoll; | |
1054 | #endif | |
1055 | netdev->hard_start_xmit = &igb_xmit_frame_adv; | |
1056 | ||
1057 | strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); | |
1058 | ||
1059 | netdev->mem_start = mmio_start; | |
1060 | netdev->mem_end = mmio_start + mmio_len; | |
1061 | ||
9d5c8243 AK |
1062 | /* PCI config space info */ |
1063 | hw->vendor_id = pdev->vendor; | |
1064 | hw->device_id = pdev->device; | |
1065 | hw->revision_id = pdev->revision; | |
1066 | hw->subsystem_vendor_id = pdev->subsystem_vendor; | |
1067 | hw->subsystem_device_id = pdev->subsystem_device; | |
1068 | ||
1069 | /* setup the private structure */ | |
1070 | hw->back = adapter; | |
1071 | /* Copy the default MAC, PHY and NVM function pointers */ | |
1072 | memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); | |
1073 | memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); | |
1074 | memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); | |
1075 | /* Initialize skew-specific constants */ | |
1076 | err = ei->get_invariants(hw); | |
1077 | if (err) | |
1078 | goto err_hw_init; | |
1079 | ||
1080 | err = igb_sw_init(adapter); | |
1081 | if (err) | |
1082 | goto err_sw_init; | |
1083 | ||
1084 | igb_get_bus_info_pcie(hw); | |
1085 | ||
7dfc16fa AD |
1086 | /* set flags */ |
1087 | switch (hw->mac.type) { | |
1088 | case e1000_82576: | |
1089 | case e1000_82575: | |
1090 | adapter->flags |= IGB_FLAG_HAS_DCA; | |
1091 | adapter->flags |= IGB_FLAG_NEED_CTX_IDX; | |
1092 | break; | |
1093 | default: | |
1094 | break; | |
1095 | } | |
1096 | ||
9d5c8243 AK |
1097 | hw->phy.autoneg_wait_to_complete = false; |
1098 | hw->mac.adaptive_ifs = true; | |
1099 | ||
1100 | /* Copper options */ | |
1101 | if (hw->phy.media_type == e1000_media_type_copper) { | |
1102 | hw->phy.mdix = AUTO_ALL_MODES; | |
1103 | hw->phy.disable_polarity_correction = false; | |
1104 | hw->phy.ms_type = e1000_ms_hw_default; | |
1105 | } | |
1106 | ||
1107 | if (igb_check_reset_block(hw)) | |
1108 | dev_info(&pdev->dev, | |
1109 | "PHY reset is blocked due to SOL/IDER session.\n"); | |
1110 | ||
1111 | netdev->features = NETIF_F_SG | | |
1112 | NETIF_F_HW_CSUM | | |
1113 | NETIF_F_HW_VLAN_TX | | |
1114 | NETIF_F_HW_VLAN_RX | | |
1115 | NETIF_F_HW_VLAN_FILTER; | |
1116 | ||
1117 | netdev->features |= NETIF_F_TSO; | |
9d5c8243 | 1118 | netdev->features |= NETIF_F_TSO6; |
48f29ffc | 1119 | |
d3352520 AD |
1120 | #ifdef CONFIG_IGB_LRO |
1121 | netdev->features |= NETIF_F_LRO; | |
1122 | #endif | |
1123 | ||
48f29ffc JK |
1124 | netdev->vlan_features |= NETIF_F_TSO; |
1125 | netdev->vlan_features |= NETIF_F_TSO6; | |
1126 | netdev->vlan_features |= NETIF_F_HW_CSUM; | |
1127 | netdev->vlan_features |= NETIF_F_SG; | |
1128 | ||
9d5c8243 AK |
1129 | if (pci_using_dac) |
1130 | netdev->features |= NETIF_F_HIGHDMA; | |
1131 | ||
1132 | netdev->features |= NETIF_F_LLTX; | |
1133 | adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw); | |
1134 | ||
1135 | /* before reading the NVM, reset the controller to put the device in a | |
1136 | * known good starting state */ | |
1137 | hw->mac.ops.reset_hw(hw); | |
1138 | ||
1139 | /* make sure the NVM is good */ | |
1140 | if (igb_validate_nvm_checksum(hw) < 0) { | |
1141 | dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); | |
1142 | err = -EIO; | |
1143 | goto err_eeprom; | |
1144 | } | |
1145 | ||
1146 | /* copy the MAC address out of the NVM */ | |
1147 | if (hw->mac.ops.read_mac_addr(hw)) | |
1148 | dev_err(&pdev->dev, "NVM Read Error\n"); | |
1149 | ||
1150 | memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len); | |
1151 | memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len); | |
1152 | ||
1153 | if (!is_valid_ether_addr(netdev->perm_addr)) { | |
1154 | dev_err(&pdev->dev, "Invalid MAC Address\n"); | |
1155 | err = -EIO; | |
1156 | goto err_eeprom; | |
1157 | } | |
1158 | ||
1159 | init_timer(&adapter->watchdog_timer); | |
1160 | adapter->watchdog_timer.function = &igb_watchdog; | |
1161 | adapter->watchdog_timer.data = (unsigned long) adapter; | |
1162 | ||
1163 | init_timer(&adapter->phy_info_timer); | |
1164 | adapter->phy_info_timer.function = &igb_update_phy_info; | |
1165 | adapter->phy_info_timer.data = (unsigned long) adapter; | |
1166 | ||
1167 | INIT_WORK(&adapter->reset_task, igb_reset_task); | |
1168 | INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); | |
1169 | ||
1170 | /* Initialize link & ring properties that are user-changeable */ | |
1171 | adapter->tx_ring->count = 256; | |
1172 | for (i = 0; i < adapter->num_tx_queues; i++) | |
1173 | adapter->tx_ring[i].count = adapter->tx_ring->count; | |
1174 | adapter->rx_ring->count = 256; | |
1175 | for (i = 0; i < adapter->num_rx_queues; i++) | |
1176 | adapter->rx_ring[i].count = adapter->rx_ring->count; | |
1177 | ||
1178 | adapter->fc_autoneg = true; | |
1179 | hw->mac.autoneg = true; | |
1180 | hw->phy.autoneg_advertised = 0x2f; | |
1181 | ||
1182 | hw->fc.original_type = e1000_fc_default; | |
1183 | hw->fc.type = e1000_fc_default; | |
1184 | ||
1185 | adapter->itr_setting = 3; | |
1186 | adapter->itr = IGB_START_ITR; | |
1187 | ||
1188 | igb_validate_mdi_setting(hw); | |
1189 | ||
1190 | adapter->rx_csum = 1; | |
1191 | ||
1192 | /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM, | |
1193 | * enable the ACPI Magic Packet filter | |
1194 | */ | |
1195 | ||
1196 | if (hw->bus.func == 0 || | |
1197 | hw->device_id == E1000_DEV_ID_82575EB_COPPER) | |
1198 | hw->nvm.ops.read_nvm(hw, NVM_INIT_CONTROL3_PORT_A, 1, | |
1199 | &eeprom_data); | |
1200 | ||
1201 | if (eeprom_data & eeprom_apme_mask) | |
1202 | adapter->eeprom_wol |= E1000_WUFC_MAG; | |
1203 | ||
1204 | /* now that we have the eeprom settings, apply the special cases where | |
1205 | * the eeprom may be wrong or the board simply won't support wake on | |
1206 | * lan on a particular port */ | |
1207 | switch (pdev->device) { | |
1208 | case E1000_DEV_ID_82575GB_QUAD_COPPER: | |
1209 | adapter->eeprom_wol = 0; | |
1210 | break; | |
1211 | case E1000_DEV_ID_82575EB_FIBER_SERDES: | |
2d064c06 AD |
1212 | case E1000_DEV_ID_82576_FIBER: |
1213 | case E1000_DEV_ID_82576_SERDES: | |
9d5c8243 AK |
1214 | /* Wake events only supported on port A for dual fiber |
1215 | * regardless of eeprom setting */ | |
1216 | if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) | |
1217 | adapter->eeprom_wol = 0; | |
1218 | break; | |
1219 | } | |
1220 | ||
1221 | /* initialize the wol settings based on the eeprom settings */ | |
1222 | adapter->wol = adapter->eeprom_wol; | |
1223 | ||
1224 | /* reset the hardware with the new settings */ | |
1225 | igb_reset(adapter); | |
1226 | ||
1227 | /* let the f/w know that the h/w is now under the control of the | |
1228 | * driver. */ | |
1229 | igb_get_hw_control(adapter); | |
1230 | ||
1231 | /* tell the stack to leave us alone until igb_open() is called */ | |
1232 | netif_carrier_off(netdev); | |
fd2ea0a7 | 1233 | netif_tx_stop_all_queues(netdev); |
9d5c8243 AK |
1234 | |
1235 | strcpy(netdev->name, "eth%d"); | |
1236 | err = register_netdev(netdev); | |
1237 | if (err) | |
1238 | goto err_register; | |
1239 | ||
fe4506b6 | 1240 | #ifdef CONFIG_DCA |
7dfc16fa AD |
1241 | if ((adapter->flags & IGB_FLAG_HAS_DCA) && |
1242 | (dca_add_requester(&pdev->dev) == 0)) { | |
1243 | adapter->flags |= IGB_FLAG_DCA_ENABLED; | |
fe4506b6 JC |
1244 | dev_info(&pdev->dev, "DCA enabled\n"); |
1245 | /* Always use CB2 mode, difference is masked | |
1246 | * in the CB driver. */ | |
1247 | wr32(E1000_DCA_CTRL, 2); | |
1248 | igb_setup_dca(adapter); | |
1249 | } | |
1250 | #endif | |
1251 | ||
9d5c8243 AK |
1252 | dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); |
1253 | /* print bus type/speed/width info */ | |
1254 | dev_info(&pdev->dev, | |
1255 | "%s: (PCIe:%s:%s) %02x:%02x:%02x:%02x:%02x:%02x\n", | |
1256 | netdev->name, | |
1257 | ((hw->bus.speed == e1000_bus_speed_2500) | |
1258 | ? "2.5Gb/s" : "unknown"), | |
1259 | ((hw->bus.width == e1000_bus_width_pcie_x4) | |
1260 | ? "Width x4" : (hw->bus.width == e1000_bus_width_pcie_x1) | |
1261 | ? "Width x1" : "unknown"), | |
1262 | netdev->dev_addr[0], netdev->dev_addr[1], netdev->dev_addr[2], | |
1263 | netdev->dev_addr[3], netdev->dev_addr[4], netdev->dev_addr[5]); | |
1264 | ||
1265 | igb_read_part_num(hw, &part_num); | |
1266 | dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name, | |
1267 | (part_num >> 8), (part_num & 0xff)); | |
1268 | ||
1269 | dev_info(&pdev->dev, | |
1270 | "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", | |
1271 | adapter->msix_entries ? "MSI-X" : | |
7dfc16fa | 1272 | (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", |
9d5c8243 AK |
1273 | adapter->num_rx_queues, adapter->num_tx_queues); |
1274 | ||
9d5c8243 AK |
1275 | return 0; |
1276 | ||
1277 | err_register: | |
1278 | igb_release_hw_control(adapter); | |
1279 | err_eeprom: | |
1280 | if (!igb_check_reset_block(hw)) | |
1281 | hw->phy.ops.reset_phy(hw); | |
1282 | ||
1283 | if (hw->flash_address) | |
1284 | iounmap(hw->flash_address); | |
1285 | ||
1286 | igb_remove_device(hw); | |
a88f10ec | 1287 | igb_free_queues(adapter); |
9d5c8243 AK |
1288 | err_sw_init: |
1289 | err_hw_init: | |
1290 | iounmap(hw->hw_addr); | |
1291 | err_ioremap: | |
1292 | free_netdev(netdev); | |
1293 | err_alloc_etherdev: | |
42bfd33a | 1294 | pci_release_selected_regions(pdev, bars); |
9d5c8243 AK |
1295 | err_pci_reg: |
1296 | err_dma: | |
1297 | pci_disable_device(pdev); | |
1298 | return err; | |
1299 | } | |
1300 | ||
1301 | /** | |
1302 | * igb_remove - Device Removal Routine | |
1303 | * @pdev: PCI device information struct | |
1304 | * | |
1305 | * igb_remove is called by the PCI subsystem to alert the driver | |
1306 | * that it should release a PCI device. The could be caused by a | |
1307 | * Hot-Plug event, or because the driver is going to be removed from | |
1308 | * memory. | |
1309 | **/ | |
1310 | static void __devexit igb_remove(struct pci_dev *pdev) | |
1311 | { | |
1312 | struct net_device *netdev = pci_get_drvdata(pdev); | |
1313 | struct igb_adapter *adapter = netdev_priv(netdev); | |
9280fa52 | 1314 | #ifdef CONFIG_DCA |
fe4506b6 | 1315 | struct e1000_hw *hw = &adapter->hw; |
9280fa52 | 1316 | #endif |
9d5c8243 AK |
1317 | |
1318 | /* flush_scheduled work may reschedule our watchdog task, so | |
1319 | * explicitly disable watchdog tasks from being rescheduled */ | |
1320 | set_bit(__IGB_DOWN, &adapter->state); | |
1321 | del_timer_sync(&adapter->watchdog_timer); | |
1322 | del_timer_sync(&adapter->phy_info_timer); | |
1323 | ||
1324 | flush_scheduled_work(); | |
1325 | ||
fe4506b6 | 1326 | #ifdef CONFIG_DCA |
7dfc16fa | 1327 | if (adapter->flags & IGB_FLAG_DCA_ENABLED) { |
fe4506b6 JC |
1328 | dev_info(&pdev->dev, "DCA disabled\n"); |
1329 | dca_remove_requester(&pdev->dev); | |
7dfc16fa | 1330 | adapter->flags &= ~IGB_FLAG_DCA_ENABLED; |
fe4506b6 JC |
1331 | wr32(E1000_DCA_CTRL, 1); |
1332 | } | |
1333 | #endif | |
1334 | ||
9d5c8243 AK |
1335 | /* Release control of h/w to f/w. If f/w is AMT enabled, this |
1336 | * would have already happened in close and is redundant. */ | |
1337 | igb_release_hw_control(adapter); | |
1338 | ||
1339 | unregister_netdev(netdev); | |
1340 | ||
c743a87e AD |
1341 | if (adapter->hw.phy.ops.reset_phy && |
1342 | !igb_check_reset_block(&adapter->hw)) | |
9d5c8243 AK |
1343 | adapter->hw.phy.ops.reset_phy(&adapter->hw); |
1344 | ||
1345 | igb_remove_device(&adapter->hw); | |
1346 | igb_reset_interrupt_capability(adapter); | |
1347 | ||
a88f10ec | 1348 | igb_free_queues(adapter); |
9d5c8243 AK |
1349 | |
1350 | iounmap(adapter->hw.hw_addr); | |
1351 | if (adapter->hw.flash_address) | |
1352 | iounmap(adapter->hw.flash_address); | |
42bfd33a | 1353 | pci_release_selected_regions(pdev, adapter->bars); |
9d5c8243 AK |
1354 | |
1355 | free_netdev(netdev); | |
1356 | ||
1357 | pci_disable_device(pdev); | |
1358 | } | |
1359 | ||
1360 | /** | |
1361 | * igb_sw_init - Initialize general software structures (struct igb_adapter) | |
1362 | * @adapter: board private structure to initialize | |
1363 | * | |
1364 | * igb_sw_init initializes the Adapter private data structure. | |
1365 | * Fields are initialized based on PCI device information and | |
1366 | * OS network device settings (MTU size). | |
1367 | **/ | |
1368 | static int __devinit igb_sw_init(struct igb_adapter *adapter) | |
1369 | { | |
1370 | struct e1000_hw *hw = &adapter->hw; | |
1371 | struct net_device *netdev = adapter->netdev; | |
1372 | struct pci_dev *pdev = adapter->pdev; | |
1373 | ||
1374 | pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); | |
1375 | ||
1376 | adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE; | |
1377 | adapter->rx_ps_hdr_size = 0; /* disable packet split */ | |
1378 | adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; | |
1379 | adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; | |
1380 | ||
1381 | /* Number of supported queues. */ | |
1382 | /* Having more queues than CPUs doesn't make sense. */ | |
661086df | 1383 | adapter->num_rx_queues = min((u32)IGB_MAX_RX_QUEUES, (u32)num_online_cpus()); |
661086df | 1384 | adapter->num_tx_queues = min(IGB_MAX_TX_QUEUES, num_online_cpus()); |
9d5c8243 | 1385 | |
661086df PWJ |
1386 | /* This call may decrease the number of queues depending on |
1387 | * interrupt mode. */ | |
9d5c8243 AK |
1388 | igb_set_interrupt_capability(adapter); |
1389 | ||
1390 | if (igb_alloc_queues(adapter)) { | |
1391 | dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); | |
1392 | return -ENOMEM; | |
1393 | } | |
1394 | ||
1395 | /* Explicitly disable IRQ since the NIC can be in any state. */ | |
1396 | igb_irq_disable(adapter); | |
1397 | ||
1398 | set_bit(__IGB_DOWN, &adapter->state); | |
1399 | return 0; | |
1400 | } | |
1401 | ||
1402 | /** | |
1403 | * igb_open - Called when a network interface is made active | |
1404 | * @netdev: network interface device structure | |
1405 | * | |
1406 | * Returns 0 on success, negative value on failure | |
1407 | * | |
1408 | * The open entry point is called when a network interface is made | |
1409 | * active by the system (IFF_UP). At this point all resources needed | |
1410 | * for transmit and receive operations are allocated, the interrupt | |
1411 | * handler is registered with the OS, the watchdog timer is started, | |
1412 | * and the stack is notified that the interface is ready. | |
1413 | **/ | |
1414 | static int igb_open(struct net_device *netdev) | |
1415 | { | |
1416 | struct igb_adapter *adapter = netdev_priv(netdev); | |
1417 | struct e1000_hw *hw = &adapter->hw; | |
1418 | int err; | |
1419 | int i; | |
1420 | ||
1421 | /* disallow open during test */ | |
1422 | if (test_bit(__IGB_TESTING, &adapter->state)) | |
1423 | return -EBUSY; | |
1424 | ||
1425 | /* allocate transmit descriptors */ | |
1426 | err = igb_setup_all_tx_resources(adapter); | |
1427 | if (err) | |
1428 | goto err_setup_tx; | |
1429 | ||
1430 | /* allocate receive descriptors */ | |
1431 | err = igb_setup_all_rx_resources(adapter); | |
1432 | if (err) | |
1433 | goto err_setup_rx; | |
1434 | ||
1435 | /* e1000_power_up_phy(adapter); */ | |
1436 | ||
1437 | adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; | |
1438 | if ((adapter->hw.mng_cookie.status & | |
1439 | E1000_MNG_DHCP_COOKIE_STATUS_VLAN)) | |
1440 | igb_update_mng_vlan(adapter); | |
1441 | ||
1442 | /* before we allocate an interrupt, we must be ready to handle it. | |
1443 | * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt | |
1444 | * as soon as we call pci_request_irq, so we have to setup our | |
1445 | * clean_rx handler before we do so. */ | |
1446 | igb_configure(adapter); | |
1447 | ||
1448 | err = igb_request_irq(adapter); | |
1449 | if (err) | |
1450 | goto err_req_irq; | |
1451 | ||
1452 | /* From here on the code is the same as igb_up() */ | |
1453 | clear_bit(__IGB_DOWN, &adapter->state); | |
1454 | ||
844290e5 PW |
1455 | for (i = 0; i < adapter->num_rx_queues; i++) |
1456 | napi_enable(&adapter->rx_ring[i].napi); | |
9d5c8243 AK |
1457 | |
1458 | /* Clear any pending interrupts. */ | |
1459 | rd32(E1000_ICR); | |
844290e5 PW |
1460 | |
1461 | igb_irq_enable(adapter); | |
1462 | ||
d55b53ff JK |
1463 | netif_tx_start_all_queues(netdev); |
1464 | ||
9d5c8243 AK |
1465 | /* Fire a link status change interrupt to start the watchdog. */ |
1466 | wr32(E1000_ICS, E1000_ICS_LSC); | |
1467 | ||
1468 | return 0; | |
1469 | ||
1470 | err_req_irq: | |
1471 | igb_release_hw_control(adapter); | |
1472 | /* e1000_power_down_phy(adapter); */ | |
1473 | igb_free_all_rx_resources(adapter); | |
1474 | err_setup_rx: | |
1475 | igb_free_all_tx_resources(adapter); | |
1476 | err_setup_tx: | |
1477 | igb_reset(adapter); | |
1478 | ||
1479 | return err; | |
1480 | } | |
1481 | ||
1482 | /** | |
1483 | * igb_close - Disables a network interface | |
1484 | * @netdev: network interface device structure | |
1485 | * | |
1486 | * Returns 0, this is not allowed to fail | |
1487 | * | |
1488 | * The close entry point is called when an interface is de-activated | |
1489 | * by the OS. The hardware is still under the driver's control, but | |
1490 | * needs to be disabled. A global MAC reset is issued to stop the | |
1491 | * hardware, and all transmit and receive resources are freed. | |
1492 | **/ | |
1493 | static int igb_close(struct net_device *netdev) | |
1494 | { | |
1495 | struct igb_adapter *adapter = netdev_priv(netdev); | |
1496 | ||
1497 | WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); | |
1498 | igb_down(adapter); | |
1499 | ||
1500 | igb_free_irq(adapter); | |
1501 | ||
1502 | igb_free_all_tx_resources(adapter); | |
1503 | igb_free_all_rx_resources(adapter); | |
1504 | ||
1505 | /* kill manageability vlan ID if supported, but not if a vlan with | |
1506 | * the same ID is registered on the host OS (let 8021q kill it) */ | |
1507 | if ((adapter->hw.mng_cookie.status & | |
1508 | E1000_MNG_DHCP_COOKIE_STATUS_VLAN) && | |
1509 | !(adapter->vlgrp && | |
1510 | vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id))) | |
1511 | igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id); | |
1512 | ||
1513 | return 0; | |
1514 | } | |
1515 | ||
1516 | /** | |
1517 | * igb_setup_tx_resources - allocate Tx resources (Descriptors) | |
1518 | * @adapter: board private structure | |
1519 | * @tx_ring: tx descriptor ring (for a specific queue) to setup | |
1520 | * | |
1521 | * Return 0 on success, negative on failure | |
1522 | **/ | |
1523 | ||
1524 | int igb_setup_tx_resources(struct igb_adapter *adapter, | |
1525 | struct igb_ring *tx_ring) | |
1526 | { | |
1527 | struct pci_dev *pdev = adapter->pdev; | |
1528 | int size; | |
1529 | ||
1530 | size = sizeof(struct igb_buffer) * tx_ring->count; | |
1531 | tx_ring->buffer_info = vmalloc(size); | |
1532 | if (!tx_ring->buffer_info) | |
1533 | goto err; | |
1534 | memset(tx_ring->buffer_info, 0, size); | |
1535 | ||
1536 | /* round up to nearest 4K */ | |
1537 | tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc) | |
1538 | + sizeof(u32); | |
1539 | tx_ring->size = ALIGN(tx_ring->size, 4096); | |
1540 | ||
1541 | tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size, | |
1542 | &tx_ring->dma); | |
1543 | ||
1544 | if (!tx_ring->desc) | |
1545 | goto err; | |
1546 | ||
1547 | tx_ring->adapter = adapter; | |
1548 | tx_ring->next_to_use = 0; | |
1549 | tx_ring->next_to_clean = 0; | |
9d5c8243 AK |
1550 | return 0; |
1551 | ||
1552 | err: | |
1553 | vfree(tx_ring->buffer_info); | |
1554 | dev_err(&adapter->pdev->dev, | |
1555 | "Unable to allocate memory for the transmit descriptor ring\n"); | |
1556 | return -ENOMEM; | |
1557 | } | |
1558 | ||
1559 | /** | |
1560 | * igb_setup_all_tx_resources - wrapper to allocate Tx resources | |
1561 | * (Descriptors) for all queues | |
1562 | * @adapter: board private structure | |
1563 | * | |
1564 | * Return 0 on success, negative on failure | |
1565 | **/ | |
1566 | static int igb_setup_all_tx_resources(struct igb_adapter *adapter) | |
1567 | { | |
1568 | int i, err = 0; | |
661086df | 1569 | int r_idx; |
9d5c8243 AK |
1570 | |
1571 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
1572 | err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]); | |
1573 | if (err) { | |
1574 | dev_err(&adapter->pdev->dev, | |
1575 | "Allocation for Tx Queue %u failed\n", i); | |
1576 | for (i--; i >= 0; i--) | |
3b644cf6 | 1577 | igb_free_tx_resources(&adapter->tx_ring[i]); |
9d5c8243 AK |
1578 | break; |
1579 | } | |
1580 | } | |
1581 | ||
661086df PWJ |
1582 | for (i = 0; i < IGB_MAX_TX_QUEUES; i++) { |
1583 | r_idx = i % adapter->num_tx_queues; | |
1584 | adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx]; | |
1585 | } | |
9d5c8243 AK |
1586 | return err; |
1587 | } | |
1588 | ||
1589 | /** | |
1590 | * igb_configure_tx - Configure transmit Unit after Reset | |
1591 | * @adapter: board private structure | |
1592 | * | |
1593 | * Configure the Tx unit of the MAC after a reset. | |
1594 | **/ | |
1595 | static void igb_configure_tx(struct igb_adapter *adapter) | |
1596 | { | |
1597 | u64 tdba, tdwba; | |
1598 | struct e1000_hw *hw = &adapter->hw; | |
1599 | u32 tctl; | |
1600 | u32 txdctl, txctrl; | |
1601 | int i; | |
1602 | ||
1603 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
1604 | struct igb_ring *ring = &(adapter->tx_ring[i]); | |
1605 | ||
1606 | wr32(E1000_TDLEN(i), | |
1607 | ring->count * sizeof(struct e1000_tx_desc)); | |
1608 | tdba = ring->dma; | |
1609 | wr32(E1000_TDBAL(i), | |
1610 | tdba & 0x00000000ffffffffULL); | |
1611 | wr32(E1000_TDBAH(i), tdba >> 32); | |
1612 | ||
1613 | tdwba = ring->dma + ring->count * sizeof(struct e1000_tx_desc); | |
1614 | tdwba |= 1; /* enable head wb */ | |
1615 | wr32(E1000_TDWBAL(i), | |
1616 | tdwba & 0x00000000ffffffffULL); | |
1617 | wr32(E1000_TDWBAH(i), tdwba >> 32); | |
1618 | ||
1619 | ring->head = E1000_TDH(i); | |
1620 | ring->tail = E1000_TDT(i); | |
1621 | writel(0, hw->hw_addr + ring->tail); | |
1622 | writel(0, hw->hw_addr + ring->head); | |
1623 | txdctl = rd32(E1000_TXDCTL(i)); | |
1624 | txdctl |= E1000_TXDCTL_QUEUE_ENABLE; | |
1625 | wr32(E1000_TXDCTL(i), txdctl); | |
1626 | ||
1627 | /* Turn off Relaxed Ordering on head write-backs. The | |
1628 | * writebacks MUST be delivered in order or it will | |
1629 | * completely screw up our bookeeping. | |
1630 | */ | |
1631 | txctrl = rd32(E1000_DCA_TXCTRL(i)); | |
1632 | txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN; | |
1633 | wr32(E1000_DCA_TXCTRL(i), txctrl); | |
1634 | } | |
1635 | ||
1636 | ||
1637 | ||
1638 | /* Use the default values for the Tx Inter Packet Gap (IPG) timer */ | |
1639 | ||
1640 | /* Program the Transmit Control Register */ | |
1641 | ||
1642 | tctl = rd32(E1000_TCTL); | |
1643 | tctl &= ~E1000_TCTL_CT; | |
1644 | tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | | |
1645 | (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); | |
1646 | ||
1647 | igb_config_collision_dist(hw); | |
1648 | ||
1649 | /* Setup Transmit Descriptor Settings for eop descriptor */ | |
1650 | adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS; | |
1651 | ||
1652 | /* Enable transmits */ | |
1653 | tctl |= E1000_TCTL_EN; | |
1654 | ||
1655 | wr32(E1000_TCTL, tctl); | |
1656 | } | |
1657 | ||
1658 | /** | |
1659 | * igb_setup_rx_resources - allocate Rx resources (Descriptors) | |
1660 | * @adapter: board private structure | |
1661 | * @rx_ring: rx descriptor ring (for a specific queue) to setup | |
1662 | * | |
1663 | * Returns 0 on success, negative on failure | |
1664 | **/ | |
1665 | ||
1666 | int igb_setup_rx_resources(struct igb_adapter *adapter, | |
1667 | struct igb_ring *rx_ring) | |
1668 | { | |
1669 | struct pci_dev *pdev = adapter->pdev; | |
1670 | int size, desc_len; | |
1671 | ||
d3352520 AD |
1672 | #ifdef CONFIG_IGB_LRO |
1673 | size = sizeof(struct net_lro_desc) * MAX_LRO_DESCRIPTORS; | |
1674 | rx_ring->lro_mgr.lro_arr = vmalloc(size); | |
1675 | if (!rx_ring->lro_mgr.lro_arr) | |
1676 | goto err; | |
1677 | memset(rx_ring->lro_mgr.lro_arr, 0, size); | |
1678 | #endif | |
1679 | ||
9d5c8243 AK |
1680 | size = sizeof(struct igb_buffer) * rx_ring->count; |
1681 | rx_ring->buffer_info = vmalloc(size); | |
1682 | if (!rx_ring->buffer_info) | |
1683 | goto err; | |
1684 | memset(rx_ring->buffer_info, 0, size); | |
1685 | ||
1686 | desc_len = sizeof(union e1000_adv_rx_desc); | |
1687 | ||
1688 | /* Round up to nearest 4K */ | |
1689 | rx_ring->size = rx_ring->count * desc_len; | |
1690 | rx_ring->size = ALIGN(rx_ring->size, 4096); | |
1691 | ||
1692 | rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, | |
1693 | &rx_ring->dma); | |
1694 | ||
1695 | if (!rx_ring->desc) | |
1696 | goto err; | |
1697 | ||
1698 | rx_ring->next_to_clean = 0; | |
1699 | rx_ring->next_to_use = 0; | |
9d5c8243 AK |
1700 | |
1701 | rx_ring->adapter = adapter; | |
9d5c8243 AK |
1702 | |
1703 | return 0; | |
1704 | ||
1705 | err: | |
d3352520 AD |
1706 | #ifdef CONFIG_IGB_LRO |
1707 | vfree(rx_ring->lro_mgr.lro_arr); | |
1708 | rx_ring->lro_mgr.lro_arr = NULL; | |
1709 | #endif | |
9d5c8243 AK |
1710 | vfree(rx_ring->buffer_info); |
1711 | dev_err(&adapter->pdev->dev, "Unable to allocate memory for " | |
1712 | "the receive descriptor ring\n"); | |
1713 | return -ENOMEM; | |
1714 | } | |
1715 | ||
1716 | /** | |
1717 | * igb_setup_all_rx_resources - wrapper to allocate Rx resources | |
1718 | * (Descriptors) for all queues | |
1719 | * @adapter: board private structure | |
1720 | * | |
1721 | * Return 0 on success, negative on failure | |
1722 | **/ | |
1723 | static int igb_setup_all_rx_resources(struct igb_adapter *adapter) | |
1724 | { | |
1725 | int i, err = 0; | |
1726 | ||
1727 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
1728 | err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]); | |
1729 | if (err) { | |
1730 | dev_err(&adapter->pdev->dev, | |
1731 | "Allocation for Rx Queue %u failed\n", i); | |
1732 | for (i--; i >= 0; i--) | |
3b644cf6 | 1733 | igb_free_rx_resources(&adapter->rx_ring[i]); |
9d5c8243 AK |
1734 | break; |
1735 | } | |
1736 | } | |
1737 | ||
1738 | return err; | |
1739 | } | |
1740 | ||
1741 | /** | |
1742 | * igb_setup_rctl - configure the receive control registers | |
1743 | * @adapter: Board private structure | |
1744 | **/ | |
1745 | static void igb_setup_rctl(struct igb_adapter *adapter) | |
1746 | { | |
1747 | struct e1000_hw *hw = &adapter->hw; | |
1748 | u32 rctl; | |
1749 | u32 srrctl = 0; | |
1750 | int i; | |
1751 | ||
1752 | rctl = rd32(E1000_RCTL); | |
1753 | ||
1754 | rctl &= ~(3 << E1000_RCTL_MO_SHIFT); | |
1755 | ||
1756 | rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | | |
1757 | E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | | |
1758 | (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT); | |
1759 | ||
87cb7e8c AK |
1760 | /* |
1761 | * enable stripping of CRC. It's unlikely this will break BMC | |
1762 | * redirection as it did with e1000. Newer features require | |
1763 | * that the HW strips the CRC. | |
9d5c8243 | 1764 | */ |
87cb7e8c | 1765 | rctl |= E1000_RCTL_SECRC; |
9d5c8243 AK |
1766 | |
1767 | rctl &= ~E1000_RCTL_SBP; | |
1768 | ||
1769 | if (adapter->netdev->mtu <= ETH_DATA_LEN) | |
1770 | rctl &= ~E1000_RCTL_LPE; | |
1771 | else | |
1772 | rctl |= E1000_RCTL_LPE; | |
1773 | if (adapter->rx_buffer_len <= IGB_RXBUFFER_2048) { | |
1774 | /* Setup buffer sizes */ | |
1775 | rctl &= ~E1000_RCTL_SZ_4096; | |
1776 | rctl |= E1000_RCTL_BSEX; | |
1777 | switch (adapter->rx_buffer_len) { | |
1778 | case IGB_RXBUFFER_256: | |
1779 | rctl |= E1000_RCTL_SZ_256; | |
1780 | rctl &= ~E1000_RCTL_BSEX; | |
1781 | break; | |
1782 | case IGB_RXBUFFER_512: | |
1783 | rctl |= E1000_RCTL_SZ_512; | |
1784 | rctl &= ~E1000_RCTL_BSEX; | |
1785 | break; | |
1786 | case IGB_RXBUFFER_1024: | |
1787 | rctl |= E1000_RCTL_SZ_1024; | |
1788 | rctl &= ~E1000_RCTL_BSEX; | |
1789 | break; | |
1790 | case IGB_RXBUFFER_2048: | |
1791 | default: | |
1792 | rctl |= E1000_RCTL_SZ_2048; | |
1793 | rctl &= ~E1000_RCTL_BSEX; | |
1794 | break; | |
9d5c8243 AK |
1795 | } |
1796 | } else { | |
1797 | rctl &= ~E1000_RCTL_BSEX; | |
1798 | srrctl = adapter->rx_buffer_len >> E1000_SRRCTL_BSIZEPKT_SHIFT; | |
1799 | } | |
1800 | ||
1801 | /* 82575 and greater support packet-split where the protocol | |
1802 | * header is placed in skb->data and the packet data is | |
1803 | * placed in pages hanging off of skb_shinfo(skb)->nr_frags. | |
1804 | * In the case of a non-split, skb->data is linearly filled, | |
1805 | * followed by the page buffers. Therefore, skb->data is | |
1806 | * sized to hold the largest protocol header. | |
1807 | */ | |
1808 | /* allocations using alloc_page take too long for regular MTU | |
1809 | * so only enable packet split for jumbo frames */ | |
1810 | if (rctl & E1000_RCTL_LPE) { | |
1811 | adapter->rx_ps_hdr_size = IGB_RXBUFFER_128; | |
bf36c1a0 | 1812 | srrctl |= adapter->rx_ps_hdr_size << |
9d5c8243 | 1813 | E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; |
9d5c8243 AK |
1814 | srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS; |
1815 | } else { | |
1816 | adapter->rx_ps_hdr_size = 0; | |
1817 | srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; | |
1818 | } | |
1819 | ||
1820 | for (i = 0; i < adapter->num_rx_queues; i++) | |
1821 | wr32(E1000_SRRCTL(i), srrctl); | |
1822 | ||
1823 | wr32(E1000_RCTL, rctl); | |
1824 | } | |
1825 | ||
1826 | /** | |
1827 | * igb_configure_rx - Configure receive Unit after Reset | |
1828 | * @adapter: board private structure | |
1829 | * | |
1830 | * Configure the Rx unit of the MAC after a reset. | |
1831 | **/ | |
1832 | static void igb_configure_rx(struct igb_adapter *adapter) | |
1833 | { | |
1834 | u64 rdba; | |
1835 | struct e1000_hw *hw = &adapter->hw; | |
1836 | u32 rctl, rxcsum; | |
1837 | u32 rxdctl; | |
1838 | int i; | |
1839 | ||
1840 | /* disable receives while setting up the descriptors */ | |
1841 | rctl = rd32(E1000_RCTL); | |
1842 | wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); | |
1843 | wrfl(); | |
1844 | mdelay(10); | |
1845 | ||
1846 | if (adapter->itr_setting > 3) | |
6eb5a7f1 | 1847 | wr32(E1000_ITR, adapter->itr); |
9d5c8243 AK |
1848 | |
1849 | /* Setup the HW Rx Head and Tail Descriptor Pointers and | |
1850 | * the Base and Length of the Rx Descriptor Ring */ | |
1851 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
1852 | struct igb_ring *ring = &(adapter->rx_ring[i]); | |
1853 | rdba = ring->dma; | |
1854 | wr32(E1000_RDBAL(i), | |
1855 | rdba & 0x00000000ffffffffULL); | |
1856 | wr32(E1000_RDBAH(i), rdba >> 32); | |
1857 | wr32(E1000_RDLEN(i), | |
1858 | ring->count * sizeof(union e1000_adv_rx_desc)); | |
1859 | ||
1860 | ring->head = E1000_RDH(i); | |
1861 | ring->tail = E1000_RDT(i); | |
1862 | writel(0, hw->hw_addr + ring->tail); | |
1863 | writel(0, hw->hw_addr + ring->head); | |
1864 | ||
1865 | rxdctl = rd32(E1000_RXDCTL(i)); | |
1866 | rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; | |
1867 | rxdctl &= 0xFFF00000; | |
1868 | rxdctl |= IGB_RX_PTHRESH; | |
1869 | rxdctl |= IGB_RX_HTHRESH << 8; | |
1870 | rxdctl |= IGB_RX_WTHRESH << 16; | |
1871 | wr32(E1000_RXDCTL(i), rxdctl); | |
d3352520 AD |
1872 | #ifdef CONFIG_IGB_LRO |
1873 | /* Intitial LRO Settings */ | |
1874 | ring->lro_mgr.max_aggr = MAX_LRO_AGGR; | |
1875 | ring->lro_mgr.max_desc = MAX_LRO_DESCRIPTORS; | |
1876 | ring->lro_mgr.get_skb_header = igb_get_skb_hdr; | |
1877 | ring->lro_mgr.features = LRO_F_NAPI | LRO_F_EXTRACT_VLAN_ID; | |
1878 | ring->lro_mgr.dev = adapter->netdev; | |
1879 | ring->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY; | |
1880 | ring->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY; | |
1881 | #endif | |
9d5c8243 AK |
1882 | } |
1883 | ||
1884 | if (adapter->num_rx_queues > 1) { | |
1885 | u32 random[10]; | |
1886 | u32 mrqc; | |
1887 | u32 j, shift; | |
1888 | union e1000_reta { | |
1889 | u32 dword; | |
1890 | u8 bytes[4]; | |
1891 | } reta; | |
1892 | ||
1893 | get_random_bytes(&random[0], 40); | |
1894 | ||
2d064c06 AD |
1895 | if (hw->mac.type >= e1000_82576) |
1896 | shift = 0; | |
1897 | else | |
1898 | shift = 6; | |
9d5c8243 AK |
1899 | for (j = 0; j < (32 * 4); j++) { |
1900 | reta.bytes[j & 3] = | |
1901 | (j % adapter->num_rx_queues) << shift; | |
1902 | if ((j & 3) == 3) | |
1903 | writel(reta.dword, | |
1904 | hw->hw_addr + E1000_RETA(0) + (j & ~3)); | |
1905 | } | |
1906 | mrqc = E1000_MRQC_ENABLE_RSS_4Q; | |
1907 | ||
1908 | /* Fill out hash function seeds */ | |
1909 | for (j = 0; j < 10; j++) | |
1910 | array_wr32(E1000_RSSRK(0), j, random[j]); | |
1911 | ||
1912 | mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | | |
1913 | E1000_MRQC_RSS_FIELD_IPV4_TCP); | |
1914 | mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 | | |
1915 | E1000_MRQC_RSS_FIELD_IPV6_TCP); | |
1916 | mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP | | |
1917 | E1000_MRQC_RSS_FIELD_IPV6_UDP); | |
1918 | mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | | |
1919 | E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); | |
1920 | ||
1921 | ||
1922 | wr32(E1000_MRQC, mrqc); | |
1923 | ||
1924 | /* Multiqueue and raw packet checksumming are mutually | |
1925 | * exclusive. Note that this not the same as TCP/IP | |
1926 | * checksumming, which works fine. */ | |
1927 | rxcsum = rd32(E1000_RXCSUM); | |
1928 | rxcsum |= E1000_RXCSUM_PCSD; | |
1929 | wr32(E1000_RXCSUM, rxcsum); | |
1930 | } else { | |
1931 | /* Enable Receive Checksum Offload for TCP and UDP */ | |
1932 | rxcsum = rd32(E1000_RXCSUM); | |
1933 | if (adapter->rx_csum) { | |
1934 | rxcsum |= E1000_RXCSUM_TUOFL; | |
1935 | ||
1936 | /* Enable IPv4 payload checksum for UDP fragments | |
1937 | * Must be used in conjunction with packet-split. */ | |
1938 | if (adapter->rx_ps_hdr_size) | |
1939 | rxcsum |= E1000_RXCSUM_IPPCSE; | |
1940 | } else { | |
1941 | rxcsum &= ~E1000_RXCSUM_TUOFL; | |
1942 | /* don't need to clear IPPCSE as it defaults to 0 */ | |
1943 | } | |
1944 | wr32(E1000_RXCSUM, rxcsum); | |
1945 | } | |
1946 | ||
1947 | if (adapter->vlgrp) | |
1948 | wr32(E1000_RLPML, | |
1949 | adapter->max_frame_size + VLAN_TAG_SIZE); | |
1950 | else | |
1951 | wr32(E1000_RLPML, adapter->max_frame_size); | |
1952 | ||
1953 | /* Enable Receives */ | |
1954 | wr32(E1000_RCTL, rctl); | |
1955 | } | |
1956 | ||
1957 | /** | |
1958 | * igb_free_tx_resources - Free Tx Resources per Queue | |
1959 | * @adapter: board private structure | |
1960 | * @tx_ring: Tx descriptor ring for a specific queue | |
1961 | * | |
1962 | * Free all transmit software resources | |
1963 | **/ | |
3b644cf6 | 1964 | static void igb_free_tx_resources(struct igb_ring *tx_ring) |
9d5c8243 | 1965 | { |
3b644cf6 | 1966 | struct pci_dev *pdev = tx_ring->adapter->pdev; |
9d5c8243 | 1967 | |
3b644cf6 | 1968 | igb_clean_tx_ring(tx_ring); |
9d5c8243 AK |
1969 | |
1970 | vfree(tx_ring->buffer_info); | |
1971 | tx_ring->buffer_info = NULL; | |
1972 | ||
1973 | pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma); | |
1974 | ||
1975 | tx_ring->desc = NULL; | |
1976 | } | |
1977 | ||
1978 | /** | |
1979 | * igb_free_all_tx_resources - Free Tx Resources for All Queues | |
1980 | * @adapter: board private structure | |
1981 | * | |
1982 | * Free all transmit software resources | |
1983 | **/ | |
1984 | static void igb_free_all_tx_resources(struct igb_adapter *adapter) | |
1985 | { | |
1986 | int i; | |
1987 | ||
1988 | for (i = 0; i < adapter->num_tx_queues; i++) | |
3b644cf6 | 1989 | igb_free_tx_resources(&adapter->tx_ring[i]); |
9d5c8243 AK |
1990 | } |
1991 | ||
1992 | static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter, | |
1993 | struct igb_buffer *buffer_info) | |
1994 | { | |
1995 | if (buffer_info->dma) { | |
1996 | pci_unmap_page(adapter->pdev, | |
1997 | buffer_info->dma, | |
1998 | buffer_info->length, | |
1999 | PCI_DMA_TODEVICE); | |
2000 | buffer_info->dma = 0; | |
2001 | } | |
2002 | if (buffer_info->skb) { | |
2003 | dev_kfree_skb_any(buffer_info->skb); | |
2004 | buffer_info->skb = NULL; | |
2005 | } | |
2006 | buffer_info->time_stamp = 0; | |
2007 | /* buffer_info must be completely set up in the transmit path */ | |
2008 | } | |
2009 | ||
2010 | /** | |
2011 | * igb_clean_tx_ring - Free Tx Buffers | |
2012 | * @adapter: board private structure | |
2013 | * @tx_ring: ring to be cleaned | |
2014 | **/ | |
3b644cf6 | 2015 | static void igb_clean_tx_ring(struct igb_ring *tx_ring) |
9d5c8243 | 2016 | { |
3b644cf6 | 2017 | struct igb_adapter *adapter = tx_ring->adapter; |
9d5c8243 AK |
2018 | struct igb_buffer *buffer_info; |
2019 | unsigned long size; | |
2020 | unsigned int i; | |
2021 | ||
2022 | if (!tx_ring->buffer_info) | |
2023 | return; | |
2024 | /* Free all the Tx ring sk_buffs */ | |
2025 | ||
2026 | for (i = 0; i < tx_ring->count; i++) { | |
2027 | buffer_info = &tx_ring->buffer_info[i]; | |
2028 | igb_unmap_and_free_tx_resource(adapter, buffer_info); | |
2029 | } | |
2030 | ||
2031 | size = sizeof(struct igb_buffer) * tx_ring->count; | |
2032 | memset(tx_ring->buffer_info, 0, size); | |
2033 | ||
2034 | /* Zero out the descriptor ring */ | |
2035 | ||
2036 | memset(tx_ring->desc, 0, tx_ring->size); | |
2037 | ||
2038 | tx_ring->next_to_use = 0; | |
2039 | tx_ring->next_to_clean = 0; | |
2040 | ||
2041 | writel(0, adapter->hw.hw_addr + tx_ring->head); | |
2042 | writel(0, adapter->hw.hw_addr + tx_ring->tail); | |
2043 | } | |
2044 | ||
2045 | /** | |
2046 | * igb_clean_all_tx_rings - Free Tx Buffers for all queues | |
2047 | * @adapter: board private structure | |
2048 | **/ | |
2049 | static void igb_clean_all_tx_rings(struct igb_adapter *adapter) | |
2050 | { | |
2051 | int i; | |
2052 | ||
2053 | for (i = 0; i < adapter->num_tx_queues; i++) | |
3b644cf6 | 2054 | igb_clean_tx_ring(&adapter->tx_ring[i]); |
9d5c8243 AK |
2055 | } |
2056 | ||
2057 | /** | |
2058 | * igb_free_rx_resources - Free Rx Resources | |
2059 | * @adapter: board private structure | |
2060 | * @rx_ring: ring to clean the resources from | |
2061 | * | |
2062 | * Free all receive software resources | |
2063 | **/ | |
3b644cf6 | 2064 | static void igb_free_rx_resources(struct igb_ring *rx_ring) |
9d5c8243 | 2065 | { |
3b644cf6 | 2066 | struct pci_dev *pdev = rx_ring->adapter->pdev; |
9d5c8243 | 2067 | |
3b644cf6 | 2068 | igb_clean_rx_ring(rx_ring); |
9d5c8243 AK |
2069 | |
2070 | vfree(rx_ring->buffer_info); | |
2071 | rx_ring->buffer_info = NULL; | |
2072 | ||
d3352520 AD |
2073 | #ifdef CONFIG_IGB_LRO |
2074 | vfree(rx_ring->lro_mgr.lro_arr); | |
2075 | rx_ring->lro_mgr.lro_arr = NULL; | |
2076 | #endif | |
2077 | ||
9d5c8243 AK |
2078 | pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma); |
2079 | ||
2080 | rx_ring->desc = NULL; | |
2081 | } | |
2082 | ||
2083 | /** | |
2084 | * igb_free_all_rx_resources - Free Rx Resources for All Queues | |
2085 | * @adapter: board private structure | |
2086 | * | |
2087 | * Free all receive software resources | |
2088 | **/ | |
2089 | static void igb_free_all_rx_resources(struct igb_adapter *adapter) | |
2090 | { | |
2091 | int i; | |
2092 | ||
2093 | for (i = 0; i < adapter->num_rx_queues; i++) | |
3b644cf6 | 2094 | igb_free_rx_resources(&adapter->rx_ring[i]); |
9d5c8243 AK |
2095 | } |
2096 | ||
2097 | /** | |
2098 | * igb_clean_rx_ring - Free Rx Buffers per Queue | |
2099 | * @adapter: board private structure | |
2100 | * @rx_ring: ring to free buffers from | |
2101 | **/ | |
3b644cf6 | 2102 | static void igb_clean_rx_ring(struct igb_ring *rx_ring) |
9d5c8243 | 2103 | { |
3b644cf6 | 2104 | struct igb_adapter *adapter = rx_ring->adapter; |
9d5c8243 AK |
2105 | struct igb_buffer *buffer_info; |
2106 | struct pci_dev *pdev = adapter->pdev; | |
2107 | unsigned long size; | |
2108 | unsigned int i; | |
2109 | ||
2110 | if (!rx_ring->buffer_info) | |
2111 | return; | |
2112 | /* Free all the Rx ring sk_buffs */ | |
2113 | for (i = 0; i < rx_ring->count; i++) { | |
2114 | buffer_info = &rx_ring->buffer_info[i]; | |
2115 | if (buffer_info->dma) { | |
2116 | if (adapter->rx_ps_hdr_size) | |
2117 | pci_unmap_single(pdev, buffer_info->dma, | |
2118 | adapter->rx_ps_hdr_size, | |
2119 | PCI_DMA_FROMDEVICE); | |
2120 | else | |
2121 | pci_unmap_single(pdev, buffer_info->dma, | |
2122 | adapter->rx_buffer_len, | |
2123 | PCI_DMA_FROMDEVICE); | |
2124 | buffer_info->dma = 0; | |
2125 | } | |
2126 | ||
2127 | if (buffer_info->skb) { | |
2128 | dev_kfree_skb(buffer_info->skb); | |
2129 | buffer_info->skb = NULL; | |
2130 | } | |
2131 | if (buffer_info->page) { | |
bf36c1a0 AD |
2132 | if (buffer_info->page_dma) |
2133 | pci_unmap_page(pdev, buffer_info->page_dma, | |
2134 | PAGE_SIZE / 2, | |
2135 | PCI_DMA_FROMDEVICE); | |
9d5c8243 AK |
2136 | put_page(buffer_info->page); |
2137 | buffer_info->page = NULL; | |
2138 | buffer_info->page_dma = 0; | |
bf36c1a0 | 2139 | buffer_info->page_offset = 0; |
9d5c8243 AK |
2140 | } |
2141 | } | |
2142 | ||
9d5c8243 AK |
2143 | size = sizeof(struct igb_buffer) * rx_ring->count; |
2144 | memset(rx_ring->buffer_info, 0, size); | |
2145 | ||
2146 | /* Zero out the descriptor ring */ | |
2147 | memset(rx_ring->desc, 0, rx_ring->size); | |
2148 | ||
2149 | rx_ring->next_to_clean = 0; | |
2150 | rx_ring->next_to_use = 0; | |
2151 | ||
2152 | writel(0, adapter->hw.hw_addr + rx_ring->head); | |
2153 | writel(0, adapter->hw.hw_addr + rx_ring->tail); | |
2154 | } | |
2155 | ||
2156 | /** | |
2157 | * igb_clean_all_rx_rings - Free Rx Buffers for all queues | |
2158 | * @adapter: board private structure | |
2159 | **/ | |
2160 | static void igb_clean_all_rx_rings(struct igb_adapter *adapter) | |
2161 | { | |
2162 | int i; | |
2163 | ||
2164 | for (i = 0; i < adapter->num_rx_queues; i++) | |
3b644cf6 | 2165 | igb_clean_rx_ring(&adapter->rx_ring[i]); |
9d5c8243 AK |
2166 | } |
2167 | ||
2168 | /** | |
2169 | * igb_set_mac - Change the Ethernet Address of the NIC | |
2170 | * @netdev: network interface device structure | |
2171 | * @p: pointer to an address structure | |
2172 | * | |
2173 | * Returns 0 on success, negative on failure | |
2174 | **/ | |
2175 | static int igb_set_mac(struct net_device *netdev, void *p) | |
2176 | { | |
2177 | struct igb_adapter *adapter = netdev_priv(netdev); | |
2178 | struct sockaddr *addr = p; | |
2179 | ||
2180 | if (!is_valid_ether_addr(addr->sa_data)) | |
2181 | return -EADDRNOTAVAIL; | |
2182 | ||
2183 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | |
2184 | memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len); | |
2185 | ||
2186 | adapter->hw.mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0); | |
2187 | ||
2188 | return 0; | |
2189 | } | |
2190 | ||
2191 | /** | |
2192 | * igb_set_multi - Multicast and Promiscuous mode set | |
2193 | * @netdev: network interface device structure | |
2194 | * | |
2195 | * The set_multi entry point is called whenever the multicast address | |
2196 | * list or the network interface flags are updated. This routine is | |
2197 | * responsible for configuring the hardware for proper multicast, | |
2198 | * promiscuous mode, and all-multi behavior. | |
2199 | **/ | |
2200 | static void igb_set_multi(struct net_device *netdev) | |
2201 | { | |
2202 | struct igb_adapter *adapter = netdev_priv(netdev); | |
2203 | struct e1000_hw *hw = &adapter->hw; | |
2204 | struct e1000_mac_info *mac = &hw->mac; | |
2205 | struct dev_mc_list *mc_ptr; | |
2206 | u8 *mta_list; | |
2207 | u32 rctl; | |
2208 | int i; | |
2209 | ||
2210 | /* Check for Promiscuous and All Multicast modes */ | |
2211 | ||
2212 | rctl = rd32(E1000_RCTL); | |
2213 | ||
746b9f02 | 2214 | if (netdev->flags & IFF_PROMISC) { |
9d5c8243 | 2215 | rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); |
746b9f02 PM |
2216 | rctl &= ~E1000_RCTL_VFE; |
2217 | } else { | |
2218 | if (netdev->flags & IFF_ALLMULTI) { | |
2219 | rctl |= E1000_RCTL_MPE; | |
2220 | rctl &= ~E1000_RCTL_UPE; | |
2221 | } else | |
2222 | rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE); | |
78ed11a5 | 2223 | rctl |= E1000_RCTL_VFE; |
746b9f02 | 2224 | } |
9d5c8243 AK |
2225 | wr32(E1000_RCTL, rctl); |
2226 | ||
2227 | if (!netdev->mc_count) { | |
2228 | /* nothing to program, so clear mc list */ | |
2d064c06 | 2229 | igb_update_mc_addr_list_82575(hw, NULL, 0, 1, |
9d5c8243 AK |
2230 | mac->rar_entry_count); |
2231 | return; | |
2232 | } | |
2233 | ||
2234 | mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC); | |
2235 | if (!mta_list) | |
2236 | return; | |
2237 | ||
2238 | /* The shared function expects a packed array of only addresses. */ | |
2239 | mc_ptr = netdev->mc_list; | |
2240 | ||
2241 | for (i = 0; i < netdev->mc_count; i++) { | |
2242 | if (!mc_ptr) | |
2243 | break; | |
2244 | memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN); | |
2245 | mc_ptr = mc_ptr->next; | |
2246 | } | |
2d064c06 AD |
2247 | igb_update_mc_addr_list_82575(hw, mta_list, i, 1, |
2248 | mac->rar_entry_count); | |
9d5c8243 AK |
2249 | kfree(mta_list); |
2250 | } | |
2251 | ||
2252 | /* Need to wait a few seconds after link up to get diagnostic information from | |
2253 | * the phy */ | |
2254 | static void igb_update_phy_info(unsigned long data) | |
2255 | { | |
2256 | struct igb_adapter *adapter = (struct igb_adapter *) data; | |
68707acb BH |
2257 | if (adapter->hw.phy.ops.get_phy_info) |
2258 | adapter->hw.phy.ops.get_phy_info(&adapter->hw); | |
9d5c8243 AK |
2259 | } |
2260 | ||
2261 | /** | |
2262 | * igb_watchdog - Timer Call-back | |
2263 | * @data: pointer to adapter cast into an unsigned long | |
2264 | **/ | |
2265 | static void igb_watchdog(unsigned long data) | |
2266 | { | |
2267 | struct igb_adapter *adapter = (struct igb_adapter *)data; | |
2268 | /* Do the rest outside of interrupt context */ | |
2269 | schedule_work(&adapter->watchdog_task); | |
2270 | } | |
2271 | ||
2272 | static void igb_watchdog_task(struct work_struct *work) | |
2273 | { | |
2274 | struct igb_adapter *adapter = container_of(work, | |
2275 | struct igb_adapter, watchdog_task); | |
2276 | struct e1000_hw *hw = &adapter->hw; | |
2277 | ||
2278 | struct net_device *netdev = adapter->netdev; | |
2279 | struct igb_ring *tx_ring = adapter->tx_ring; | |
2280 | struct e1000_mac_info *mac = &adapter->hw.mac; | |
2281 | u32 link; | |
7a6ea550 | 2282 | u32 eics = 0; |
9d5c8243 | 2283 | s32 ret_val; |
7a6ea550 | 2284 | int i; |
9d5c8243 AK |
2285 | |
2286 | if ((netif_carrier_ok(netdev)) && | |
2287 | (rd32(E1000_STATUS) & E1000_STATUS_LU)) | |
2288 | goto link_up; | |
2289 | ||
2290 | ret_val = hw->mac.ops.check_for_link(&adapter->hw); | |
2291 | if ((ret_val == E1000_ERR_PHY) && | |
2292 | (hw->phy.type == e1000_phy_igp_3) && | |
2293 | (rd32(E1000_CTRL) & | |
2294 | E1000_PHY_CTRL_GBE_DISABLE)) | |
2295 | dev_info(&adapter->pdev->dev, | |
2296 | "Gigabit has been disabled, downgrading speed\n"); | |
2297 | ||
2298 | if ((hw->phy.media_type == e1000_media_type_internal_serdes) && | |
2299 | !(rd32(E1000_TXCW) & E1000_TXCW_ANE)) | |
2300 | link = mac->serdes_has_link; | |
2301 | else | |
2302 | link = rd32(E1000_STATUS) & | |
2303 | E1000_STATUS_LU; | |
2304 | ||
2305 | if (link) { | |
2306 | if (!netif_carrier_ok(netdev)) { | |
2307 | u32 ctrl; | |
2308 | hw->mac.ops.get_speed_and_duplex(&adapter->hw, | |
2309 | &adapter->link_speed, | |
2310 | &adapter->link_duplex); | |
2311 | ||
2312 | ctrl = rd32(E1000_CTRL); | |
2313 | dev_info(&adapter->pdev->dev, | |
2314 | "NIC Link is Up %d Mbps %s, " | |
2315 | "Flow Control: %s\n", | |
2316 | adapter->link_speed, | |
2317 | adapter->link_duplex == FULL_DUPLEX ? | |
2318 | "Full Duplex" : "Half Duplex", | |
2319 | ((ctrl & E1000_CTRL_TFCE) && (ctrl & | |
2320 | E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl & | |
2321 | E1000_CTRL_RFCE) ? "RX" : ((ctrl & | |
2322 | E1000_CTRL_TFCE) ? "TX" : "None"))); | |
2323 | ||
2324 | /* tweak tx_queue_len according to speed/duplex and | |
2325 | * adjust the timeout factor */ | |
2326 | netdev->tx_queue_len = adapter->tx_queue_len; | |
2327 | adapter->tx_timeout_factor = 1; | |
2328 | switch (adapter->link_speed) { | |
2329 | case SPEED_10: | |
2330 | netdev->tx_queue_len = 10; | |
2331 | adapter->tx_timeout_factor = 14; | |
2332 | break; | |
2333 | case SPEED_100: | |
2334 | netdev->tx_queue_len = 100; | |
2335 | /* maybe add some timeout factor ? */ | |
2336 | break; | |
2337 | } | |
2338 | ||
2339 | netif_carrier_on(netdev); | |
fd2ea0a7 | 2340 | netif_tx_wake_all_queues(netdev); |
9d5c8243 AK |
2341 | |
2342 | if (!test_bit(__IGB_DOWN, &adapter->state)) | |
2343 | mod_timer(&adapter->phy_info_timer, | |
2344 | round_jiffies(jiffies + 2 * HZ)); | |
2345 | } | |
2346 | } else { | |
2347 | if (netif_carrier_ok(netdev)) { | |
2348 | adapter->link_speed = 0; | |
2349 | adapter->link_duplex = 0; | |
2350 | dev_info(&adapter->pdev->dev, "NIC Link is Down\n"); | |
2351 | netif_carrier_off(netdev); | |
fd2ea0a7 | 2352 | netif_tx_stop_all_queues(netdev); |
9d5c8243 AK |
2353 | if (!test_bit(__IGB_DOWN, &adapter->state)) |
2354 | mod_timer(&adapter->phy_info_timer, | |
2355 | round_jiffies(jiffies + 2 * HZ)); | |
2356 | } | |
2357 | } | |
2358 | ||
2359 | link_up: | |
2360 | igb_update_stats(adapter); | |
2361 | ||
2362 | mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old; | |
2363 | adapter->tpt_old = adapter->stats.tpt; | |
2364 | mac->collision_delta = adapter->stats.colc - adapter->colc_old; | |
2365 | adapter->colc_old = adapter->stats.colc; | |
2366 | ||
2367 | adapter->gorc = adapter->stats.gorc - adapter->gorc_old; | |
2368 | adapter->gorc_old = adapter->stats.gorc; | |
2369 | adapter->gotc = adapter->stats.gotc - adapter->gotc_old; | |
2370 | adapter->gotc_old = adapter->stats.gotc; | |
2371 | ||
2372 | igb_update_adaptive(&adapter->hw); | |
2373 | ||
2374 | if (!netif_carrier_ok(netdev)) { | |
2375 | if (IGB_DESC_UNUSED(tx_ring) + 1 < tx_ring->count) { | |
2376 | /* We've lost link, so the controller stops DMA, | |
2377 | * but we've got queued Tx work that's never going | |
2378 | * to get done, so reset controller to flush Tx. | |
2379 | * (Do the reset outside of interrupt context). */ | |
2380 | adapter->tx_timeout_count++; | |
2381 | schedule_work(&adapter->reset_task); | |
2382 | } | |
2383 | } | |
2384 | ||
2385 | /* Cause software interrupt to ensure rx ring is cleaned */ | |
7a6ea550 AD |
2386 | if (adapter->msix_entries) { |
2387 | for (i = 0; i < adapter->num_rx_queues; i++) | |
2388 | eics |= adapter->rx_ring[i].eims_value; | |
2389 | wr32(E1000_EICS, eics); | |
2390 | } else { | |
2391 | wr32(E1000_ICS, E1000_ICS_RXDMT0); | |
2392 | } | |
9d5c8243 AK |
2393 | |
2394 | /* Force detection of hung controller every watchdog period */ | |
2395 | tx_ring->detect_tx_hung = true; | |
2396 | ||
2397 | /* Reset the timer */ | |
2398 | if (!test_bit(__IGB_DOWN, &adapter->state)) | |
2399 | mod_timer(&adapter->watchdog_timer, | |
2400 | round_jiffies(jiffies + 2 * HZ)); | |
2401 | } | |
2402 | ||
2403 | enum latency_range { | |
2404 | lowest_latency = 0, | |
2405 | low_latency = 1, | |
2406 | bulk_latency = 2, | |
2407 | latency_invalid = 255 | |
2408 | }; | |
2409 | ||
2410 | ||
6eb5a7f1 AD |
2411 | /** |
2412 | * igb_update_ring_itr - update the dynamic ITR value based on packet size | |
2413 | * | |
2414 | * Stores a new ITR value based on strictly on packet size. This | |
2415 | * algorithm is less sophisticated than that used in igb_update_itr, | |
2416 | * due to the difficulty of synchronizing statistics across multiple | |
2417 | * receive rings. The divisors and thresholds used by this fuction | |
2418 | * were determined based on theoretical maximum wire speed and testing | |
2419 | * data, in order to minimize response time while increasing bulk | |
2420 | * throughput. | |
2421 | * This functionality is controlled by the InterruptThrottleRate module | |
2422 | * parameter (see igb_param.c) | |
2423 | * NOTE: This function is called only when operating in a multiqueue | |
2424 | * receive environment. | |
2425 | * @rx_ring: pointer to ring | |
2426 | **/ | |
2427 | static void igb_update_ring_itr(struct igb_ring *rx_ring) | |
9d5c8243 | 2428 | { |
6eb5a7f1 AD |
2429 | int new_val = rx_ring->itr_val; |
2430 | int avg_wire_size = 0; | |
2431 | struct igb_adapter *adapter = rx_ring->adapter; | |
9d5c8243 | 2432 | |
6eb5a7f1 AD |
2433 | if (!rx_ring->total_packets) |
2434 | goto clear_counts; /* no packets, so don't do anything */ | |
9d5c8243 | 2435 | |
6eb5a7f1 AD |
2436 | /* For non-gigabit speeds, just fix the interrupt rate at 4000 |
2437 | * ints/sec - ITR timer value of 120 ticks. | |
2438 | */ | |
2439 | if (adapter->link_speed != SPEED_1000) { | |
2440 | new_val = 120; | |
2441 | goto set_itr_val; | |
9d5c8243 | 2442 | } |
6eb5a7f1 | 2443 | avg_wire_size = rx_ring->total_bytes / rx_ring->total_packets; |
9d5c8243 | 2444 | |
6eb5a7f1 AD |
2445 | /* Add 24 bytes to size to account for CRC, preamble, and gap */ |
2446 | avg_wire_size += 24; | |
2447 | ||
2448 | /* Don't starve jumbo frames */ | |
2449 | avg_wire_size = min(avg_wire_size, 3000); | |
9d5c8243 | 2450 | |
6eb5a7f1 AD |
2451 | /* Give a little boost to mid-size frames */ |
2452 | if ((avg_wire_size > 300) && (avg_wire_size < 1200)) | |
2453 | new_val = avg_wire_size / 3; | |
2454 | else | |
2455 | new_val = avg_wire_size / 2; | |
9d5c8243 | 2456 | |
6eb5a7f1 | 2457 | set_itr_val: |
9d5c8243 AK |
2458 | if (new_val != rx_ring->itr_val) { |
2459 | rx_ring->itr_val = new_val; | |
6eb5a7f1 | 2460 | rx_ring->set_itr = 1; |
9d5c8243 | 2461 | } |
6eb5a7f1 AD |
2462 | clear_counts: |
2463 | rx_ring->total_bytes = 0; | |
2464 | rx_ring->total_packets = 0; | |
9d5c8243 AK |
2465 | } |
2466 | ||
2467 | /** | |
2468 | * igb_update_itr - update the dynamic ITR value based on statistics | |
2469 | * Stores a new ITR value based on packets and byte | |
2470 | * counts during the last interrupt. The advantage of per interrupt | |
2471 | * computation is faster updates and more accurate ITR for the current | |
2472 | * traffic pattern. Constants in this function were computed | |
2473 | * based on theoretical maximum wire speed and thresholds were set based | |
2474 | * on testing data as well as attempting to minimize response time | |
2475 | * while increasing bulk throughput. | |
2476 | * this functionality is controlled by the InterruptThrottleRate module | |
2477 | * parameter (see igb_param.c) | |
2478 | * NOTE: These calculations are only valid when operating in a single- | |
2479 | * queue environment. | |
2480 | * @adapter: pointer to adapter | |
2481 | * @itr_setting: current adapter->itr | |
2482 | * @packets: the number of packets during this measurement interval | |
2483 | * @bytes: the number of bytes during this measurement interval | |
2484 | **/ | |
2485 | static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting, | |
2486 | int packets, int bytes) | |
2487 | { | |
2488 | unsigned int retval = itr_setting; | |
2489 | ||
2490 | if (packets == 0) | |
2491 | goto update_itr_done; | |
2492 | ||
2493 | switch (itr_setting) { | |
2494 | case lowest_latency: | |
2495 | /* handle TSO and jumbo frames */ | |
2496 | if (bytes/packets > 8000) | |
2497 | retval = bulk_latency; | |
2498 | else if ((packets < 5) && (bytes > 512)) | |
2499 | retval = low_latency; | |
2500 | break; | |
2501 | case low_latency: /* 50 usec aka 20000 ints/s */ | |
2502 | if (bytes > 10000) { | |
2503 | /* this if handles the TSO accounting */ | |
2504 | if (bytes/packets > 8000) { | |
2505 | retval = bulk_latency; | |
2506 | } else if ((packets < 10) || ((bytes/packets) > 1200)) { | |
2507 | retval = bulk_latency; | |
2508 | } else if ((packets > 35)) { | |
2509 | retval = lowest_latency; | |
2510 | } | |
2511 | } else if (bytes/packets > 2000) { | |
2512 | retval = bulk_latency; | |
2513 | } else if (packets <= 2 && bytes < 512) { | |
2514 | retval = lowest_latency; | |
2515 | } | |
2516 | break; | |
2517 | case bulk_latency: /* 250 usec aka 4000 ints/s */ | |
2518 | if (bytes > 25000) { | |
2519 | if (packets > 35) | |
2520 | retval = low_latency; | |
2521 | } else if (bytes < 6000) { | |
2522 | retval = low_latency; | |
2523 | } | |
2524 | break; | |
2525 | } | |
2526 | ||
2527 | update_itr_done: | |
2528 | return retval; | |
2529 | } | |
2530 | ||
6eb5a7f1 | 2531 | static void igb_set_itr(struct igb_adapter *adapter) |
9d5c8243 AK |
2532 | { |
2533 | u16 current_itr; | |
2534 | u32 new_itr = adapter->itr; | |
2535 | ||
2536 | /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ | |
2537 | if (adapter->link_speed != SPEED_1000) { | |
2538 | current_itr = 0; | |
2539 | new_itr = 4000; | |
2540 | goto set_itr_now; | |
2541 | } | |
2542 | ||
2543 | adapter->rx_itr = igb_update_itr(adapter, | |
2544 | adapter->rx_itr, | |
2545 | adapter->rx_ring->total_packets, | |
2546 | adapter->rx_ring->total_bytes); | |
9d5c8243 | 2547 | |
6eb5a7f1 | 2548 | if (adapter->rx_ring->buddy) { |
9d5c8243 AK |
2549 | adapter->tx_itr = igb_update_itr(adapter, |
2550 | adapter->tx_itr, | |
2551 | adapter->tx_ring->total_packets, | |
2552 | adapter->tx_ring->total_bytes); | |
9d5c8243 AK |
2553 | |
2554 | current_itr = max(adapter->rx_itr, adapter->tx_itr); | |
2555 | } else { | |
2556 | current_itr = adapter->rx_itr; | |
2557 | } | |
2558 | ||
6eb5a7f1 AD |
2559 | /* conservative mode (itr 3) eliminates the lowest_latency setting */ |
2560 | if (adapter->itr_setting == 3 && | |
2561 | current_itr == lowest_latency) | |
2562 | current_itr = low_latency; | |
2563 | ||
9d5c8243 AK |
2564 | switch (current_itr) { |
2565 | /* counts and packets in update_itr are dependent on these numbers */ | |
2566 | case lowest_latency: | |
2567 | new_itr = 70000; | |
2568 | break; | |
2569 | case low_latency: | |
2570 | new_itr = 20000; /* aka hwitr = ~200 */ | |
2571 | break; | |
2572 | case bulk_latency: | |
2573 | new_itr = 4000; | |
2574 | break; | |
2575 | default: | |
2576 | break; | |
2577 | } | |
2578 | ||
2579 | set_itr_now: | |
6eb5a7f1 AD |
2580 | adapter->rx_ring->total_bytes = 0; |
2581 | adapter->rx_ring->total_packets = 0; | |
2582 | if (adapter->rx_ring->buddy) { | |
2583 | adapter->rx_ring->buddy->total_bytes = 0; | |
2584 | adapter->rx_ring->buddy->total_packets = 0; | |
2585 | } | |
2586 | ||
9d5c8243 AK |
2587 | if (new_itr != adapter->itr) { |
2588 | /* this attempts to bias the interrupt rate towards Bulk | |
2589 | * by adding intermediate steps when interrupt rate is | |
2590 | * increasing */ | |
2591 | new_itr = new_itr > adapter->itr ? | |
2592 | min(adapter->itr + (new_itr >> 2), new_itr) : | |
2593 | new_itr; | |
2594 | /* Don't write the value here; it resets the adapter's | |
2595 | * internal timer, and causes us to delay far longer than | |
2596 | * we should between interrupts. Instead, we write the ITR | |
2597 | * value at the beginning of the next interrupt so the timing | |
2598 | * ends up being correct. | |
2599 | */ | |
2600 | adapter->itr = new_itr; | |
6eb5a7f1 AD |
2601 | adapter->rx_ring->itr_val = 1000000000 / (new_itr * 256); |
2602 | adapter->rx_ring->set_itr = 1; | |
9d5c8243 AK |
2603 | } |
2604 | ||
2605 | return; | |
2606 | } | |
2607 | ||
2608 | ||
2609 | #define IGB_TX_FLAGS_CSUM 0x00000001 | |
2610 | #define IGB_TX_FLAGS_VLAN 0x00000002 | |
2611 | #define IGB_TX_FLAGS_TSO 0x00000004 | |
2612 | #define IGB_TX_FLAGS_IPV4 0x00000008 | |
2613 | #define IGB_TX_FLAGS_VLAN_MASK 0xffff0000 | |
2614 | #define IGB_TX_FLAGS_VLAN_SHIFT 16 | |
2615 | ||
2616 | static inline int igb_tso_adv(struct igb_adapter *adapter, | |
2617 | struct igb_ring *tx_ring, | |
2618 | struct sk_buff *skb, u32 tx_flags, u8 *hdr_len) | |
2619 | { | |
2620 | struct e1000_adv_tx_context_desc *context_desc; | |
2621 | unsigned int i; | |
2622 | int err; | |
2623 | struct igb_buffer *buffer_info; | |
2624 | u32 info = 0, tu_cmd = 0; | |
2625 | u32 mss_l4len_idx, l4len; | |
2626 | *hdr_len = 0; | |
2627 | ||
2628 | if (skb_header_cloned(skb)) { | |
2629 | err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); | |
2630 | if (err) | |
2631 | return err; | |
2632 | } | |
2633 | ||
2634 | l4len = tcp_hdrlen(skb); | |
2635 | *hdr_len += l4len; | |
2636 | ||
2637 | if (skb->protocol == htons(ETH_P_IP)) { | |
2638 | struct iphdr *iph = ip_hdr(skb); | |
2639 | iph->tot_len = 0; | |
2640 | iph->check = 0; | |
2641 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, | |
2642 | iph->daddr, 0, | |
2643 | IPPROTO_TCP, | |
2644 | 0); | |
2645 | } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) { | |
2646 | ipv6_hdr(skb)->payload_len = 0; | |
2647 | tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, | |
2648 | &ipv6_hdr(skb)->daddr, | |
2649 | 0, IPPROTO_TCP, 0); | |
2650 | } | |
2651 | ||
2652 | i = tx_ring->next_to_use; | |
2653 | ||
2654 | buffer_info = &tx_ring->buffer_info[i]; | |
2655 | context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i); | |
2656 | /* VLAN MACLEN IPLEN */ | |
2657 | if (tx_flags & IGB_TX_FLAGS_VLAN) | |
2658 | info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK); | |
2659 | info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT); | |
2660 | *hdr_len += skb_network_offset(skb); | |
2661 | info |= skb_network_header_len(skb); | |
2662 | *hdr_len += skb_network_header_len(skb); | |
2663 | context_desc->vlan_macip_lens = cpu_to_le32(info); | |
2664 | ||
2665 | /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ | |
2666 | tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT); | |
2667 | ||
2668 | if (skb->protocol == htons(ETH_P_IP)) | |
2669 | tu_cmd |= E1000_ADVTXD_TUCMD_IPV4; | |
2670 | tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP; | |
2671 | ||
2672 | context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd); | |
2673 | ||
2674 | /* MSS L4LEN IDX */ | |
2675 | mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT); | |
2676 | mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT); | |
2677 | ||
7dfc16fa AD |
2678 | /* Context index must be unique per ring. */ |
2679 | if (adapter->flags & IGB_FLAG_NEED_CTX_IDX) | |
2680 | mss_l4len_idx |= tx_ring->queue_index << 4; | |
9d5c8243 AK |
2681 | |
2682 | context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); | |
2683 | context_desc->seqnum_seed = 0; | |
2684 | ||
2685 | buffer_info->time_stamp = jiffies; | |
2686 | buffer_info->dma = 0; | |
2687 | i++; | |
2688 | if (i == tx_ring->count) | |
2689 | i = 0; | |
2690 | ||
2691 | tx_ring->next_to_use = i; | |
2692 | ||
2693 | return true; | |
2694 | } | |
2695 | ||
2696 | static inline bool igb_tx_csum_adv(struct igb_adapter *adapter, | |
2697 | struct igb_ring *tx_ring, | |
2698 | struct sk_buff *skb, u32 tx_flags) | |
2699 | { | |
2700 | struct e1000_adv_tx_context_desc *context_desc; | |
2701 | unsigned int i; | |
2702 | struct igb_buffer *buffer_info; | |
2703 | u32 info = 0, tu_cmd = 0; | |
2704 | ||
2705 | if ((skb->ip_summed == CHECKSUM_PARTIAL) || | |
2706 | (tx_flags & IGB_TX_FLAGS_VLAN)) { | |
2707 | i = tx_ring->next_to_use; | |
2708 | buffer_info = &tx_ring->buffer_info[i]; | |
2709 | context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i); | |
2710 | ||
2711 | if (tx_flags & IGB_TX_FLAGS_VLAN) | |
2712 | info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK); | |
2713 | info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT); | |
2714 | if (skb->ip_summed == CHECKSUM_PARTIAL) | |
2715 | info |= skb_network_header_len(skb); | |
2716 | ||
2717 | context_desc->vlan_macip_lens = cpu_to_le32(info); | |
2718 | ||
2719 | tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT); | |
2720 | ||
2721 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
44b0cda3 MW |
2722 | switch (skb->protocol) { |
2723 | case __constant_htons(ETH_P_IP): | |
9d5c8243 | 2724 | tu_cmd |= E1000_ADVTXD_TUCMD_IPV4; |
44b0cda3 MW |
2725 | if (ip_hdr(skb)->protocol == IPPROTO_TCP) |
2726 | tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP; | |
2727 | break; | |
2728 | case __constant_htons(ETH_P_IPV6): | |
2729 | /* XXX what about other V6 headers?? */ | |
2730 | if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP) | |
2731 | tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP; | |
2732 | break; | |
2733 | default: | |
2734 | if (unlikely(net_ratelimit())) | |
2735 | dev_warn(&adapter->pdev->dev, | |
2736 | "partial checksum but proto=%x!\n", | |
2737 | skb->protocol); | |
2738 | break; | |
2739 | } | |
9d5c8243 AK |
2740 | } |
2741 | ||
2742 | context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd); | |
2743 | context_desc->seqnum_seed = 0; | |
7dfc16fa AD |
2744 | if (adapter->flags & IGB_FLAG_NEED_CTX_IDX) |
2745 | context_desc->mss_l4len_idx = | |
2746 | cpu_to_le32(tx_ring->queue_index << 4); | |
9d5c8243 AK |
2747 | |
2748 | buffer_info->time_stamp = jiffies; | |
2749 | buffer_info->dma = 0; | |
2750 | ||
2751 | i++; | |
2752 | if (i == tx_ring->count) | |
2753 | i = 0; | |
2754 | tx_ring->next_to_use = i; | |
2755 | ||
2756 | return true; | |
2757 | } | |
2758 | ||
2759 | ||
2760 | return false; | |
2761 | } | |
2762 | ||
2763 | #define IGB_MAX_TXD_PWR 16 | |
2764 | #define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR) | |
2765 | ||
2766 | static inline int igb_tx_map_adv(struct igb_adapter *adapter, | |
2767 | struct igb_ring *tx_ring, | |
2768 | struct sk_buff *skb) | |
2769 | { | |
2770 | struct igb_buffer *buffer_info; | |
2771 | unsigned int len = skb_headlen(skb); | |
2772 | unsigned int count = 0, i; | |
2773 | unsigned int f; | |
2774 | ||
2775 | i = tx_ring->next_to_use; | |
2776 | ||
2777 | buffer_info = &tx_ring->buffer_info[i]; | |
2778 | BUG_ON(len >= IGB_MAX_DATA_PER_TXD); | |
2779 | buffer_info->length = len; | |
2780 | /* set time_stamp *before* dma to help avoid a possible race */ | |
2781 | buffer_info->time_stamp = jiffies; | |
2782 | buffer_info->dma = pci_map_single(adapter->pdev, skb->data, len, | |
2783 | PCI_DMA_TODEVICE); | |
2784 | count++; | |
2785 | i++; | |
2786 | if (i == tx_ring->count) | |
2787 | i = 0; | |
2788 | ||
2789 | for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) { | |
2790 | struct skb_frag_struct *frag; | |
2791 | ||
2792 | frag = &skb_shinfo(skb)->frags[f]; | |
2793 | len = frag->size; | |
2794 | ||
2795 | buffer_info = &tx_ring->buffer_info[i]; | |
2796 | BUG_ON(len >= IGB_MAX_DATA_PER_TXD); | |
2797 | buffer_info->length = len; | |
2798 | buffer_info->time_stamp = jiffies; | |
2799 | buffer_info->dma = pci_map_page(adapter->pdev, | |
2800 | frag->page, | |
2801 | frag->page_offset, | |
2802 | len, | |
2803 | PCI_DMA_TODEVICE); | |
2804 | ||
2805 | count++; | |
2806 | i++; | |
2807 | if (i == tx_ring->count) | |
2808 | i = 0; | |
2809 | } | |
2810 | ||
2811 | i = (i == 0) ? tx_ring->count - 1 : i - 1; | |
2812 | tx_ring->buffer_info[i].skb = skb; | |
2813 | ||
2814 | return count; | |
2815 | } | |
2816 | ||
2817 | static inline void igb_tx_queue_adv(struct igb_adapter *adapter, | |
2818 | struct igb_ring *tx_ring, | |
2819 | int tx_flags, int count, u32 paylen, | |
2820 | u8 hdr_len) | |
2821 | { | |
2822 | union e1000_adv_tx_desc *tx_desc = NULL; | |
2823 | struct igb_buffer *buffer_info; | |
2824 | u32 olinfo_status = 0, cmd_type_len; | |
2825 | unsigned int i; | |
2826 | ||
2827 | cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS | | |
2828 | E1000_ADVTXD_DCMD_DEXT); | |
2829 | ||
2830 | if (tx_flags & IGB_TX_FLAGS_VLAN) | |
2831 | cmd_type_len |= E1000_ADVTXD_DCMD_VLE; | |
2832 | ||
2833 | if (tx_flags & IGB_TX_FLAGS_TSO) { | |
2834 | cmd_type_len |= E1000_ADVTXD_DCMD_TSE; | |
2835 | ||
2836 | /* insert tcp checksum */ | |
2837 | olinfo_status |= E1000_TXD_POPTS_TXSM << 8; | |
2838 | ||
2839 | /* insert ip checksum */ | |
2840 | if (tx_flags & IGB_TX_FLAGS_IPV4) | |
2841 | olinfo_status |= E1000_TXD_POPTS_IXSM << 8; | |
2842 | ||
2843 | } else if (tx_flags & IGB_TX_FLAGS_CSUM) { | |
2844 | olinfo_status |= E1000_TXD_POPTS_TXSM << 8; | |
2845 | } | |
2846 | ||
7dfc16fa AD |
2847 | if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) && |
2848 | (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO | | |
2849 | IGB_TX_FLAGS_VLAN))) | |
661086df | 2850 | olinfo_status |= tx_ring->queue_index << 4; |
9d5c8243 AK |
2851 | |
2852 | olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT); | |
2853 | ||
2854 | i = tx_ring->next_to_use; | |
2855 | while (count--) { | |
2856 | buffer_info = &tx_ring->buffer_info[i]; | |
2857 | tx_desc = E1000_TX_DESC_ADV(*tx_ring, i); | |
2858 | tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma); | |
2859 | tx_desc->read.cmd_type_len = | |
2860 | cpu_to_le32(cmd_type_len | buffer_info->length); | |
2861 | tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); | |
2862 | i++; | |
2863 | if (i == tx_ring->count) | |
2864 | i = 0; | |
2865 | } | |
2866 | ||
2867 | tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd); | |
2868 | /* Force memory writes to complete before letting h/w | |
2869 | * know there are new descriptors to fetch. (Only | |
2870 | * applicable for weak-ordered memory model archs, | |
2871 | * such as IA-64). */ | |
2872 | wmb(); | |
2873 | ||
2874 | tx_ring->next_to_use = i; | |
2875 | writel(i, adapter->hw.hw_addr + tx_ring->tail); | |
2876 | /* we need this if more than one processor can write to our tail | |
2877 | * at a time, it syncronizes IO on IA64/Altix systems */ | |
2878 | mmiowb(); | |
2879 | } | |
2880 | ||
2881 | static int __igb_maybe_stop_tx(struct net_device *netdev, | |
2882 | struct igb_ring *tx_ring, int size) | |
2883 | { | |
2884 | struct igb_adapter *adapter = netdev_priv(netdev); | |
2885 | ||
661086df | 2886 | netif_stop_subqueue(netdev, tx_ring->queue_index); |
661086df | 2887 | |
9d5c8243 AK |
2888 | /* Herbert's original patch had: |
2889 | * smp_mb__after_netif_stop_queue(); | |
2890 | * but since that doesn't exist yet, just open code it. */ | |
2891 | smp_mb(); | |
2892 | ||
2893 | /* We need to check again in a case another CPU has just | |
2894 | * made room available. */ | |
2895 | if (IGB_DESC_UNUSED(tx_ring) < size) | |
2896 | return -EBUSY; | |
2897 | ||
2898 | /* A reprieve! */ | |
661086df | 2899 | netif_wake_subqueue(netdev, tx_ring->queue_index); |
9d5c8243 AK |
2900 | ++adapter->restart_queue; |
2901 | return 0; | |
2902 | } | |
2903 | ||
2904 | static int igb_maybe_stop_tx(struct net_device *netdev, | |
2905 | struct igb_ring *tx_ring, int size) | |
2906 | { | |
2907 | if (IGB_DESC_UNUSED(tx_ring) >= size) | |
2908 | return 0; | |
2909 | return __igb_maybe_stop_tx(netdev, tx_ring, size); | |
2910 | } | |
2911 | ||
2912 | #define TXD_USE_COUNT(S) (((S) >> (IGB_MAX_TXD_PWR)) + 1) | |
2913 | ||
2914 | static int igb_xmit_frame_ring_adv(struct sk_buff *skb, | |
2915 | struct net_device *netdev, | |
2916 | struct igb_ring *tx_ring) | |
2917 | { | |
2918 | struct igb_adapter *adapter = netdev_priv(netdev); | |
2919 | unsigned int tx_flags = 0; | |
2920 | unsigned int len; | |
9d5c8243 AK |
2921 | u8 hdr_len = 0; |
2922 | int tso = 0; | |
2923 | ||
2924 | len = skb_headlen(skb); | |
2925 | ||
2926 | if (test_bit(__IGB_DOWN, &adapter->state)) { | |
2927 | dev_kfree_skb_any(skb); | |
2928 | return NETDEV_TX_OK; | |
2929 | } | |
2930 | ||
2931 | if (skb->len <= 0) { | |
2932 | dev_kfree_skb_any(skb); | |
2933 | return NETDEV_TX_OK; | |
2934 | } | |
2935 | ||
9d5c8243 AK |
2936 | /* need: 1 descriptor per page, |
2937 | * + 2 desc gap to keep tail from touching head, | |
2938 | * + 1 desc for skb->data, | |
2939 | * + 1 desc for context descriptor, | |
2940 | * otherwise try next time */ | |
2941 | if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) { | |
2942 | /* this is a hard error */ | |
9d5c8243 AK |
2943 | return NETDEV_TX_BUSY; |
2944 | } | |
6eb5a7f1 | 2945 | skb_orphan(skb); |
9d5c8243 AK |
2946 | |
2947 | if (adapter->vlgrp && vlan_tx_tag_present(skb)) { | |
2948 | tx_flags |= IGB_TX_FLAGS_VLAN; | |
2949 | tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); | |
2950 | } | |
2951 | ||
661086df PWJ |
2952 | if (skb->protocol == htons(ETH_P_IP)) |
2953 | tx_flags |= IGB_TX_FLAGS_IPV4; | |
2954 | ||
9d5c8243 AK |
2955 | tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags, |
2956 | &hdr_len) : 0; | |
2957 | ||
2958 | if (tso < 0) { | |
2959 | dev_kfree_skb_any(skb); | |
9d5c8243 AK |
2960 | return NETDEV_TX_OK; |
2961 | } | |
2962 | ||
2963 | if (tso) | |
2964 | tx_flags |= IGB_TX_FLAGS_TSO; | |
2965 | else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags)) | |
2966 | if (skb->ip_summed == CHECKSUM_PARTIAL) | |
2967 | tx_flags |= IGB_TX_FLAGS_CSUM; | |
2968 | ||
9d5c8243 AK |
2969 | igb_tx_queue_adv(adapter, tx_ring, tx_flags, |
2970 | igb_tx_map_adv(adapter, tx_ring, skb), | |
2971 | skb->len, hdr_len); | |
2972 | ||
2973 | netdev->trans_start = jiffies; | |
2974 | ||
2975 | /* Make sure there is space in the ring for the next send. */ | |
2976 | igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4); | |
2977 | ||
9d5c8243 AK |
2978 | return NETDEV_TX_OK; |
2979 | } | |
2980 | ||
2981 | static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *netdev) | |
2982 | { | |
2983 | struct igb_adapter *adapter = netdev_priv(netdev); | |
661086df PWJ |
2984 | struct igb_ring *tx_ring; |
2985 | ||
661086df PWJ |
2986 | int r_idx = 0; |
2987 | r_idx = skb->queue_mapping & (IGB_MAX_TX_QUEUES - 1); | |
2988 | tx_ring = adapter->multi_tx_table[r_idx]; | |
9d5c8243 AK |
2989 | |
2990 | /* This goes back to the question of how to logically map a tx queue | |
2991 | * to a flow. Right now, performance is impacted slightly negatively | |
2992 | * if using multiple tx queues. If the stack breaks away from a | |
2993 | * single qdisc implementation, we can look at this again. */ | |
2994 | return (igb_xmit_frame_ring_adv(skb, netdev, tx_ring)); | |
2995 | } | |
2996 | ||
2997 | /** | |
2998 | * igb_tx_timeout - Respond to a Tx Hang | |
2999 | * @netdev: network interface device structure | |
3000 | **/ | |
3001 | static void igb_tx_timeout(struct net_device *netdev) | |
3002 | { | |
3003 | struct igb_adapter *adapter = netdev_priv(netdev); | |
3004 | struct e1000_hw *hw = &adapter->hw; | |
3005 | ||
3006 | /* Do the reset outside of interrupt context */ | |
3007 | adapter->tx_timeout_count++; | |
3008 | schedule_work(&adapter->reset_task); | |
3009 | wr32(E1000_EICS, adapter->eims_enable_mask & | |
3010 | ~(E1000_EIMS_TCP_TIMER | E1000_EIMS_OTHER)); | |
3011 | } | |
3012 | ||
3013 | static void igb_reset_task(struct work_struct *work) | |
3014 | { | |
3015 | struct igb_adapter *adapter; | |
3016 | adapter = container_of(work, struct igb_adapter, reset_task); | |
3017 | ||
3018 | igb_reinit_locked(adapter); | |
3019 | } | |
3020 | ||
3021 | /** | |
3022 | * igb_get_stats - Get System Network Statistics | |
3023 | * @netdev: network interface device structure | |
3024 | * | |
3025 | * Returns the address of the device statistics structure. | |
3026 | * The statistics are actually updated from the timer callback. | |
3027 | **/ | |
3028 | static struct net_device_stats * | |
3029 | igb_get_stats(struct net_device *netdev) | |
3030 | { | |
3031 | struct igb_adapter *adapter = netdev_priv(netdev); | |
3032 | ||
3033 | /* only return the current stats */ | |
3034 | return &adapter->net_stats; | |
3035 | } | |
3036 | ||
3037 | /** | |
3038 | * igb_change_mtu - Change the Maximum Transfer Unit | |
3039 | * @netdev: network interface device structure | |
3040 | * @new_mtu: new value for maximum frame size | |
3041 | * | |
3042 | * Returns 0 on success, negative on failure | |
3043 | **/ | |
3044 | static int igb_change_mtu(struct net_device *netdev, int new_mtu) | |
3045 | { | |
3046 | struct igb_adapter *adapter = netdev_priv(netdev); | |
3047 | int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; | |
3048 | ||
3049 | if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) || | |
3050 | (max_frame > MAX_JUMBO_FRAME_SIZE)) { | |
3051 | dev_err(&adapter->pdev->dev, "Invalid MTU setting\n"); | |
3052 | return -EINVAL; | |
3053 | } | |
3054 | ||
3055 | #define MAX_STD_JUMBO_FRAME_SIZE 9234 | |
3056 | if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) { | |
3057 | dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n"); | |
3058 | return -EINVAL; | |
3059 | } | |
3060 | ||
3061 | while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) | |
3062 | msleep(1); | |
3063 | /* igb_down has a dependency on max_frame_size */ | |
3064 | adapter->max_frame_size = max_frame; | |
3065 | if (netif_running(netdev)) | |
3066 | igb_down(adapter); | |
3067 | ||
3068 | /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN | |
3069 | * means we reserve 2 more, this pushes us to allocate from the next | |
3070 | * larger slab size. | |
3071 | * i.e. RXBUFFER_2048 --> size-4096 slab | |
3072 | */ | |
3073 | ||
3074 | if (max_frame <= IGB_RXBUFFER_256) | |
3075 | adapter->rx_buffer_len = IGB_RXBUFFER_256; | |
3076 | else if (max_frame <= IGB_RXBUFFER_512) | |
3077 | adapter->rx_buffer_len = IGB_RXBUFFER_512; | |
3078 | else if (max_frame <= IGB_RXBUFFER_1024) | |
3079 | adapter->rx_buffer_len = IGB_RXBUFFER_1024; | |
3080 | else if (max_frame <= IGB_RXBUFFER_2048) | |
3081 | adapter->rx_buffer_len = IGB_RXBUFFER_2048; | |
3082 | else | |
bf36c1a0 AD |
3083 | #if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384 |
3084 | adapter->rx_buffer_len = IGB_RXBUFFER_16384; | |
3085 | #else | |
3086 | adapter->rx_buffer_len = PAGE_SIZE / 2; | |
3087 | #endif | |
9d5c8243 AK |
3088 | /* adjust allocation if LPE protects us, and we aren't using SBP */ |
3089 | if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) || | |
3090 | (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE)) | |
3091 | adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE; | |
3092 | ||
3093 | dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n", | |
3094 | netdev->mtu, new_mtu); | |
3095 | netdev->mtu = new_mtu; | |
3096 | ||
3097 | if (netif_running(netdev)) | |
3098 | igb_up(adapter); | |
3099 | else | |
3100 | igb_reset(adapter); | |
3101 | ||
3102 | clear_bit(__IGB_RESETTING, &adapter->state); | |
3103 | ||
3104 | return 0; | |
3105 | } | |
3106 | ||
3107 | /** | |
3108 | * igb_update_stats - Update the board statistics counters | |
3109 | * @adapter: board private structure | |
3110 | **/ | |
3111 | ||
3112 | void igb_update_stats(struct igb_adapter *adapter) | |
3113 | { | |
3114 | struct e1000_hw *hw = &adapter->hw; | |
3115 | struct pci_dev *pdev = adapter->pdev; | |
3116 | u16 phy_tmp; | |
3117 | ||
3118 | #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF | |
3119 | ||
3120 | /* | |
3121 | * Prevent stats update while adapter is being reset, or if the pci | |
3122 | * connection is down. | |
3123 | */ | |
3124 | if (adapter->link_speed == 0) | |
3125 | return; | |
3126 | if (pci_channel_offline(pdev)) | |
3127 | return; | |
3128 | ||
3129 | adapter->stats.crcerrs += rd32(E1000_CRCERRS); | |
3130 | adapter->stats.gprc += rd32(E1000_GPRC); | |
3131 | adapter->stats.gorc += rd32(E1000_GORCL); | |
3132 | rd32(E1000_GORCH); /* clear GORCL */ | |
3133 | adapter->stats.bprc += rd32(E1000_BPRC); | |
3134 | adapter->stats.mprc += rd32(E1000_MPRC); | |
3135 | adapter->stats.roc += rd32(E1000_ROC); | |
3136 | ||
3137 | adapter->stats.prc64 += rd32(E1000_PRC64); | |
3138 | adapter->stats.prc127 += rd32(E1000_PRC127); | |
3139 | adapter->stats.prc255 += rd32(E1000_PRC255); | |
3140 | adapter->stats.prc511 += rd32(E1000_PRC511); | |
3141 | adapter->stats.prc1023 += rd32(E1000_PRC1023); | |
3142 | adapter->stats.prc1522 += rd32(E1000_PRC1522); | |
3143 | adapter->stats.symerrs += rd32(E1000_SYMERRS); | |
3144 | adapter->stats.sec += rd32(E1000_SEC); | |
3145 | ||
3146 | adapter->stats.mpc += rd32(E1000_MPC); | |
3147 | adapter->stats.scc += rd32(E1000_SCC); | |
3148 | adapter->stats.ecol += rd32(E1000_ECOL); | |
3149 | adapter->stats.mcc += rd32(E1000_MCC); | |
3150 | adapter->stats.latecol += rd32(E1000_LATECOL); | |
3151 | adapter->stats.dc += rd32(E1000_DC); | |
3152 | adapter->stats.rlec += rd32(E1000_RLEC); | |
3153 | adapter->stats.xonrxc += rd32(E1000_XONRXC); | |
3154 | adapter->stats.xontxc += rd32(E1000_XONTXC); | |
3155 | adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); | |
3156 | adapter->stats.xofftxc += rd32(E1000_XOFFTXC); | |
3157 | adapter->stats.fcruc += rd32(E1000_FCRUC); | |
3158 | adapter->stats.gptc += rd32(E1000_GPTC); | |
3159 | adapter->stats.gotc += rd32(E1000_GOTCL); | |
3160 | rd32(E1000_GOTCH); /* clear GOTCL */ | |
3161 | adapter->stats.rnbc += rd32(E1000_RNBC); | |
3162 | adapter->stats.ruc += rd32(E1000_RUC); | |
3163 | adapter->stats.rfc += rd32(E1000_RFC); | |
3164 | adapter->stats.rjc += rd32(E1000_RJC); | |
3165 | adapter->stats.tor += rd32(E1000_TORH); | |
3166 | adapter->stats.tot += rd32(E1000_TOTH); | |
3167 | adapter->stats.tpr += rd32(E1000_TPR); | |
3168 | ||
3169 | adapter->stats.ptc64 += rd32(E1000_PTC64); | |
3170 | adapter->stats.ptc127 += rd32(E1000_PTC127); | |
3171 | adapter->stats.ptc255 += rd32(E1000_PTC255); | |
3172 | adapter->stats.ptc511 += rd32(E1000_PTC511); | |
3173 | adapter->stats.ptc1023 += rd32(E1000_PTC1023); | |
3174 | adapter->stats.ptc1522 += rd32(E1000_PTC1522); | |
3175 | ||
3176 | adapter->stats.mptc += rd32(E1000_MPTC); | |
3177 | adapter->stats.bptc += rd32(E1000_BPTC); | |
3178 | ||
3179 | /* used for adaptive IFS */ | |
3180 | ||
3181 | hw->mac.tx_packet_delta = rd32(E1000_TPT); | |
3182 | adapter->stats.tpt += hw->mac.tx_packet_delta; | |
3183 | hw->mac.collision_delta = rd32(E1000_COLC); | |
3184 | adapter->stats.colc += hw->mac.collision_delta; | |
3185 | ||
3186 | adapter->stats.algnerrc += rd32(E1000_ALGNERRC); | |
3187 | adapter->stats.rxerrc += rd32(E1000_RXERRC); | |
3188 | adapter->stats.tncrs += rd32(E1000_TNCRS); | |
3189 | adapter->stats.tsctc += rd32(E1000_TSCTC); | |
3190 | adapter->stats.tsctfc += rd32(E1000_TSCTFC); | |
3191 | ||
3192 | adapter->stats.iac += rd32(E1000_IAC); | |
3193 | adapter->stats.icrxoc += rd32(E1000_ICRXOC); | |
3194 | adapter->stats.icrxptc += rd32(E1000_ICRXPTC); | |
3195 | adapter->stats.icrxatc += rd32(E1000_ICRXATC); | |
3196 | adapter->stats.ictxptc += rd32(E1000_ICTXPTC); | |
3197 | adapter->stats.ictxatc += rd32(E1000_ICTXATC); | |
3198 | adapter->stats.ictxqec += rd32(E1000_ICTXQEC); | |
3199 | adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); | |
3200 | adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); | |
3201 | ||
3202 | /* Fill out the OS statistics structure */ | |
3203 | adapter->net_stats.multicast = adapter->stats.mprc; | |
3204 | adapter->net_stats.collisions = adapter->stats.colc; | |
3205 | ||
3206 | /* Rx Errors */ | |
3207 | ||
3208 | /* RLEC on some newer hardware can be incorrect so build | |
3209 | * our own version based on RUC and ROC */ | |
3210 | adapter->net_stats.rx_errors = adapter->stats.rxerrc + | |
3211 | adapter->stats.crcerrs + adapter->stats.algnerrc + | |
3212 | adapter->stats.ruc + adapter->stats.roc + | |
3213 | adapter->stats.cexterr; | |
3214 | adapter->net_stats.rx_length_errors = adapter->stats.ruc + | |
3215 | adapter->stats.roc; | |
3216 | adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs; | |
3217 | adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc; | |
3218 | adapter->net_stats.rx_missed_errors = adapter->stats.mpc; | |
3219 | ||
3220 | /* Tx Errors */ | |
3221 | adapter->net_stats.tx_errors = adapter->stats.ecol + | |
3222 | adapter->stats.latecol; | |
3223 | adapter->net_stats.tx_aborted_errors = adapter->stats.ecol; | |
3224 | adapter->net_stats.tx_window_errors = adapter->stats.latecol; | |
3225 | adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs; | |
3226 | ||
3227 | /* Tx Dropped needs to be maintained elsewhere */ | |
3228 | ||
3229 | /* Phy Stats */ | |
3230 | if (hw->phy.media_type == e1000_media_type_copper) { | |
3231 | if ((adapter->link_speed == SPEED_1000) && | |
3232 | (!hw->phy.ops.read_phy_reg(hw, PHY_1000T_STATUS, | |
3233 | &phy_tmp))) { | |
3234 | phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK; | |
3235 | adapter->phy_stats.idle_errors += phy_tmp; | |
3236 | } | |
3237 | } | |
3238 | ||
3239 | /* Management Stats */ | |
3240 | adapter->stats.mgptc += rd32(E1000_MGTPTC); | |
3241 | adapter->stats.mgprc += rd32(E1000_MGTPRC); | |
3242 | adapter->stats.mgpdc += rd32(E1000_MGTPDC); | |
3243 | } | |
3244 | ||
3245 | ||
3246 | static irqreturn_t igb_msix_other(int irq, void *data) | |
3247 | { | |
3248 | struct net_device *netdev = data; | |
3249 | struct igb_adapter *adapter = netdev_priv(netdev); | |
3250 | struct e1000_hw *hw = &adapter->hw; | |
844290e5 | 3251 | u32 icr = rd32(E1000_ICR); |
9d5c8243 | 3252 | |
844290e5 PW |
3253 | /* reading ICR causes bit 31 of EICR to be cleared */ |
3254 | if (!(icr & E1000_ICR_LSC)) | |
3255 | goto no_link_interrupt; | |
3256 | hw->mac.get_link_status = 1; | |
3257 | /* guard against interrupt when we're going down */ | |
3258 | if (!test_bit(__IGB_DOWN, &adapter->state)) | |
3259 | mod_timer(&adapter->watchdog_timer, jiffies + 1); | |
661086df | 3260 | |
9d5c8243 AK |
3261 | no_link_interrupt: |
3262 | wr32(E1000_IMS, E1000_IMS_LSC); | |
844290e5 | 3263 | wr32(E1000_EIMS, adapter->eims_other); |
9d5c8243 AK |
3264 | |
3265 | return IRQ_HANDLED; | |
3266 | } | |
3267 | ||
3268 | static irqreturn_t igb_msix_tx(int irq, void *data) | |
3269 | { | |
3270 | struct igb_ring *tx_ring = data; | |
3271 | struct igb_adapter *adapter = tx_ring->adapter; | |
3272 | struct e1000_hw *hw = &adapter->hw; | |
3273 | ||
fe4506b6 | 3274 | #ifdef CONFIG_DCA |
7dfc16fa | 3275 | if (adapter->flags & IGB_FLAG_DCA_ENABLED) |
fe4506b6 JC |
3276 | igb_update_tx_dca(tx_ring); |
3277 | #endif | |
9d5c8243 AK |
3278 | tx_ring->total_bytes = 0; |
3279 | tx_ring->total_packets = 0; | |
661086df PWJ |
3280 | |
3281 | /* auto mask will automatically reenable the interrupt when we write | |
3282 | * EICS */ | |
3b644cf6 | 3283 | if (!igb_clean_tx_irq(tx_ring)) |
9d5c8243 AK |
3284 | /* Ring was not completely cleaned, so fire another interrupt */ |
3285 | wr32(E1000_EICS, tx_ring->eims_value); | |
661086df | 3286 | else |
9d5c8243 | 3287 | wr32(E1000_EIMS, tx_ring->eims_value); |
661086df | 3288 | |
9d5c8243 AK |
3289 | return IRQ_HANDLED; |
3290 | } | |
3291 | ||
6eb5a7f1 AD |
3292 | static void igb_write_itr(struct igb_ring *ring) |
3293 | { | |
3294 | struct e1000_hw *hw = &ring->adapter->hw; | |
3295 | if ((ring->adapter->itr_setting & 3) && ring->set_itr) { | |
3296 | switch (hw->mac.type) { | |
3297 | case e1000_82576: | |
3298 | wr32(ring->itr_register, | |
3299 | ring->itr_val | | |
3300 | 0x80000000); | |
3301 | break; | |
3302 | default: | |
3303 | wr32(ring->itr_register, | |
3304 | ring->itr_val | | |
3305 | (ring->itr_val << 16)); | |
3306 | break; | |
3307 | } | |
3308 | ring->set_itr = 0; | |
3309 | } | |
3310 | } | |
3311 | ||
9d5c8243 AK |
3312 | static irqreturn_t igb_msix_rx(int irq, void *data) |
3313 | { | |
3314 | struct igb_ring *rx_ring = data; | |
3315 | struct igb_adapter *adapter = rx_ring->adapter; | |
9d5c8243 | 3316 | |
844290e5 PW |
3317 | /* Write the ITR value calculated at the end of the |
3318 | * previous interrupt. | |
3319 | */ | |
9d5c8243 | 3320 | |
6eb5a7f1 | 3321 | igb_write_itr(rx_ring); |
9d5c8243 | 3322 | |
844290e5 PW |
3323 | if (netif_rx_schedule_prep(adapter->netdev, &rx_ring->napi)) |
3324 | __netif_rx_schedule(adapter->netdev, &rx_ring->napi); | |
3325 | ||
fe4506b6 | 3326 | #ifdef CONFIG_DCA |
7dfc16fa | 3327 | if (adapter->flags & IGB_FLAG_DCA_ENABLED) |
fe4506b6 JC |
3328 | igb_update_rx_dca(rx_ring); |
3329 | #endif | |
3330 | return IRQ_HANDLED; | |
3331 | } | |
3332 | ||
3333 | #ifdef CONFIG_DCA | |
3334 | static void igb_update_rx_dca(struct igb_ring *rx_ring) | |
3335 | { | |
3336 | u32 dca_rxctrl; | |
3337 | struct igb_adapter *adapter = rx_ring->adapter; | |
3338 | struct e1000_hw *hw = &adapter->hw; | |
3339 | int cpu = get_cpu(); | |
3340 | int q = rx_ring - adapter->rx_ring; | |
3341 | ||
3342 | if (rx_ring->cpu != cpu) { | |
3343 | dca_rxctrl = rd32(E1000_DCA_RXCTRL(q)); | |
2d064c06 AD |
3344 | if (hw->mac.type == e1000_82576) { |
3345 | dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576; | |
3346 | dca_rxctrl |= dca_get_tag(cpu) << | |
3347 | E1000_DCA_RXCTRL_CPUID_SHIFT; | |
3348 | } else { | |
3349 | dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK; | |
3350 | dca_rxctrl |= dca_get_tag(cpu); | |
3351 | } | |
fe4506b6 JC |
3352 | dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN; |
3353 | dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN; | |
3354 | dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN; | |
3355 | wr32(E1000_DCA_RXCTRL(q), dca_rxctrl); | |
3356 | rx_ring->cpu = cpu; | |
3357 | } | |
3358 | put_cpu(); | |
3359 | } | |
3360 | ||
3361 | static void igb_update_tx_dca(struct igb_ring *tx_ring) | |
3362 | { | |
3363 | u32 dca_txctrl; | |
3364 | struct igb_adapter *adapter = tx_ring->adapter; | |
3365 | struct e1000_hw *hw = &adapter->hw; | |
3366 | int cpu = get_cpu(); | |
3367 | int q = tx_ring - adapter->tx_ring; | |
3368 | ||
3369 | if (tx_ring->cpu != cpu) { | |
3370 | dca_txctrl = rd32(E1000_DCA_TXCTRL(q)); | |
2d064c06 AD |
3371 | if (hw->mac.type == e1000_82576) { |
3372 | dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576; | |
3373 | dca_txctrl |= dca_get_tag(cpu) << | |
3374 | E1000_DCA_TXCTRL_CPUID_SHIFT; | |
3375 | } else { | |
3376 | dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK; | |
3377 | dca_txctrl |= dca_get_tag(cpu); | |
3378 | } | |
fe4506b6 JC |
3379 | dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN; |
3380 | wr32(E1000_DCA_TXCTRL(q), dca_txctrl); | |
3381 | tx_ring->cpu = cpu; | |
3382 | } | |
3383 | put_cpu(); | |
3384 | } | |
3385 | ||
3386 | static void igb_setup_dca(struct igb_adapter *adapter) | |
3387 | { | |
3388 | int i; | |
3389 | ||
7dfc16fa | 3390 | if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) |
fe4506b6 JC |
3391 | return; |
3392 | ||
3393 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
3394 | adapter->tx_ring[i].cpu = -1; | |
3395 | igb_update_tx_dca(&adapter->tx_ring[i]); | |
3396 | } | |
3397 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
3398 | adapter->rx_ring[i].cpu = -1; | |
3399 | igb_update_rx_dca(&adapter->rx_ring[i]); | |
3400 | } | |
3401 | } | |
3402 | ||
3403 | static int __igb_notify_dca(struct device *dev, void *data) | |
3404 | { | |
3405 | struct net_device *netdev = dev_get_drvdata(dev); | |
3406 | struct igb_adapter *adapter = netdev_priv(netdev); | |
3407 | struct e1000_hw *hw = &adapter->hw; | |
3408 | unsigned long event = *(unsigned long *)data; | |
3409 | ||
7dfc16fa AD |
3410 | if (!(adapter->flags & IGB_FLAG_HAS_DCA)) |
3411 | goto out; | |
3412 | ||
fe4506b6 JC |
3413 | switch (event) { |
3414 | case DCA_PROVIDER_ADD: | |
3415 | /* if already enabled, don't do it again */ | |
7dfc16fa | 3416 | if (adapter->flags & IGB_FLAG_DCA_ENABLED) |
fe4506b6 | 3417 | break; |
7dfc16fa | 3418 | adapter->flags |= IGB_FLAG_DCA_ENABLED; |
fe4506b6 JC |
3419 | /* Always use CB2 mode, difference is masked |
3420 | * in the CB driver. */ | |
3421 | wr32(E1000_DCA_CTRL, 2); | |
3422 | if (dca_add_requester(dev) == 0) { | |
3423 | dev_info(&adapter->pdev->dev, "DCA enabled\n"); | |
3424 | igb_setup_dca(adapter); | |
3425 | break; | |
3426 | } | |
3427 | /* Fall Through since DCA is disabled. */ | |
3428 | case DCA_PROVIDER_REMOVE: | |
7dfc16fa | 3429 | if (adapter->flags & IGB_FLAG_DCA_ENABLED) { |
fe4506b6 JC |
3430 | /* without this a class_device is left |
3431 | * hanging around in the sysfs model */ | |
3432 | dca_remove_requester(dev); | |
3433 | dev_info(&adapter->pdev->dev, "DCA disabled\n"); | |
7dfc16fa | 3434 | adapter->flags &= ~IGB_FLAG_DCA_ENABLED; |
fe4506b6 JC |
3435 | wr32(E1000_DCA_CTRL, 1); |
3436 | } | |
3437 | break; | |
3438 | } | |
7dfc16fa | 3439 | out: |
fe4506b6 | 3440 | return 0; |
9d5c8243 AK |
3441 | } |
3442 | ||
fe4506b6 JC |
3443 | static int igb_notify_dca(struct notifier_block *nb, unsigned long event, |
3444 | void *p) | |
3445 | { | |
3446 | int ret_val; | |
3447 | ||
3448 | ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, | |
3449 | __igb_notify_dca); | |
3450 | ||
3451 | return ret_val ? NOTIFY_BAD : NOTIFY_DONE; | |
3452 | } | |
3453 | #endif /* CONFIG_DCA */ | |
9d5c8243 AK |
3454 | |
3455 | /** | |
3456 | * igb_intr_msi - Interrupt Handler | |
3457 | * @irq: interrupt number | |
3458 | * @data: pointer to a network interface device structure | |
3459 | **/ | |
3460 | static irqreturn_t igb_intr_msi(int irq, void *data) | |
3461 | { | |
3462 | struct net_device *netdev = data; | |
3463 | struct igb_adapter *adapter = netdev_priv(netdev); | |
9d5c8243 AK |
3464 | struct e1000_hw *hw = &adapter->hw; |
3465 | /* read ICR disables interrupts using IAM */ | |
3466 | u32 icr = rd32(E1000_ICR); | |
3467 | ||
6eb5a7f1 | 3468 | igb_write_itr(adapter->rx_ring); |
9d5c8243 | 3469 | |
9d5c8243 AK |
3470 | if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { |
3471 | hw->mac.get_link_status = 1; | |
3472 | if (!test_bit(__IGB_DOWN, &adapter->state)) | |
3473 | mod_timer(&adapter->watchdog_timer, jiffies + 1); | |
3474 | } | |
3475 | ||
844290e5 | 3476 | netif_rx_schedule(netdev, &adapter->rx_ring[0].napi); |
9d5c8243 AK |
3477 | |
3478 | return IRQ_HANDLED; | |
3479 | } | |
3480 | ||
3481 | /** | |
3482 | * igb_intr - Interrupt Handler | |
3483 | * @irq: interrupt number | |
3484 | * @data: pointer to a network interface device structure | |
3485 | **/ | |
3486 | static irqreturn_t igb_intr(int irq, void *data) | |
3487 | { | |
3488 | struct net_device *netdev = data; | |
3489 | struct igb_adapter *adapter = netdev_priv(netdev); | |
9d5c8243 AK |
3490 | struct e1000_hw *hw = &adapter->hw; |
3491 | /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No | |
3492 | * need for the IMC write */ | |
3493 | u32 icr = rd32(E1000_ICR); | |
3494 | u32 eicr = 0; | |
3495 | if (!icr) | |
3496 | return IRQ_NONE; /* Not our interrupt */ | |
3497 | ||
6eb5a7f1 | 3498 | igb_write_itr(adapter->rx_ring); |
9d5c8243 AK |
3499 | |
3500 | /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is | |
3501 | * not set, then the adapter didn't send an interrupt */ | |
3502 | if (!(icr & E1000_ICR_INT_ASSERTED)) | |
3503 | return IRQ_NONE; | |
3504 | ||
3505 | eicr = rd32(E1000_EICR); | |
3506 | ||
3507 | if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { | |
3508 | hw->mac.get_link_status = 1; | |
3509 | /* guard against interrupt when we're going down */ | |
3510 | if (!test_bit(__IGB_DOWN, &adapter->state)) | |
3511 | mod_timer(&adapter->watchdog_timer, jiffies + 1); | |
3512 | } | |
3513 | ||
844290e5 | 3514 | netif_rx_schedule(netdev, &adapter->rx_ring[0].napi); |
9d5c8243 AK |
3515 | |
3516 | return IRQ_HANDLED; | |
3517 | } | |
3518 | ||
3519 | /** | |
661086df PWJ |
3520 | * igb_poll - NAPI Rx polling callback |
3521 | * @napi: napi polling structure | |
3522 | * @budget: count of how many packets we should handle | |
9d5c8243 | 3523 | **/ |
661086df | 3524 | static int igb_poll(struct napi_struct *napi, int budget) |
9d5c8243 | 3525 | { |
661086df PWJ |
3526 | struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi); |
3527 | struct igb_adapter *adapter = rx_ring->adapter; | |
9d5c8243 | 3528 | struct net_device *netdev = adapter->netdev; |
661086df | 3529 | int tx_clean_complete, work_done = 0; |
9d5c8243 | 3530 | |
661086df | 3531 | /* this poll routine only supports one tx and one rx queue */ |
fe4506b6 | 3532 | #ifdef CONFIG_DCA |
7dfc16fa | 3533 | if (adapter->flags & IGB_FLAG_DCA_ENABLED) |
fe4506b6 JC |
3534 | igb_update_tx_dca(&adapter->tx_ring[0]); |
3535 | #endif | |
661086df | 3536 | tx_clean_complete = igb_clean_tx_irq(&adapter->tx_ring[0]); |
fe4506b6 JC |
3537 | |
3538 | #ifdef CONFIG_DCA | |
7dfc16fa | 3539 | if (adapter->flags & IGB_FLAG_DCA_ENABLED) |
fe4506b6 JC |
3540 | igb_update_rx_dca(&adapter->rx_ring[0]); |
3541 | #endif | |
661086df | 3542 | igb_clean_rx_irq_adv(&adapter->rx_ring[0], &work_done, budget); |
9d5c8243 AK |
3543 | |
3544 | /* If no Tx and not enough Rx work done, exit the polling mode */ | |
3545 | if ((tx_clean_complete && (work_done < budget)) || | |
3546 | !netif_running(netdev)) { | |
9d5c8243 | 3547 | if (adapter->itr_setting & 3) |
6eb5a7f1 | 3548 | igb_set_itr(adapter); |
9d5c8243 AK |
3549 | netif_rx_complete(netdev, napi); |
3550 | if (!test_bit(__IGB_DOWN, &adapter->state)) | |
3551 | igb_irq_enable(adapter); | |
3552 | return 0; | |
3553 | } | |
3554 | ||
3555 | return 1; | |
3556 | } | |
3557 | ||
3558 | static int igb_clean_rx_ring_msix(struct napi_struct *napi, int budget) | |
3559 | { | |
3560 | struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi); | |
3561 | struct igb_adapter *adapter = rx_ring->adapter; | |
3562 | struct e1000_hw *hw = &adapter->hw; | |
3563 | struct net_device *netdev = adapter->netdev; | |
3564 | int work_done = 0; | |
3565 | ||
fe4506b6 | 3566 | #ifdef CONFIG_DCA |
7dfc16fa | 3567 | if (adapter->flags & IGB_FLAG_DCA_ENABLED) |
fe4506b6 JC |
3568 | igb_update_rx_dca(rx_ring); |
3569 | #endif | |
3b644cf6 | 3570 | igb_clean_rx_irq_adv(rx_ring, &work_done, budget); |
9d5c8243 AK |
3571 | |
3572 | ||
3573 | /* If not enough Rx work done, exit the polling mode */ | |
3574 | if ((work_done == 0) || !netif_running(netdev)) { | |
9d5c8243 AK |
3575 | netif_rx_complete(netdev, napi); |
3576 | ||
6eb5a7f1 AD |
3577 | if (adapter->itr_setting & 3) { |
3578 | if (adapter->num_rx_queues == 1) | |
3579 | igb_set_itr(adapter); | |
3580 | else | |
3581 | igb_update_ring_itr(rx_ring); | |
9d5c8243 | 3582 | } |
844290e5 PW |
3583 | |
3584 | if (!test_bit(__IGB_DOWN, &adapter->state)) | |
3585 | wr32(E1000_EIMS, rx_ring->eims_value); | |
3586 | ||
9d5c8243 AK |
3587 | return 0; |
3588 | } | |
3589 | ||
3590 | return 1; | |
3591 | } | |
6d8126f9 AV |
3592 | |
3593 | static inline u32 get_head(struct igb_ring *tx_ring) | |
3594 | { | |
3595 | void *end = (struct e1000_tx_desc *)tx_ring->desc + tx_ring->count; | |
3596 | return le32_to_cpu(*(volatile __le32 *)end); | |
3597 | } | |
3598 | ||
9d5c8243 AK |
3599 | /** |
3600 | * igb_clean_tx_irq - Reclaim resources after transmit completes | |
3601 | * @adapter: board private structure | |
3602 | * returns true if ring is completely cleaned | |
3603 | **/ | |
3b644cf6 | 3604 | static bool igb_clean_tx_irq(struct igb_ring *tx_ring) |
9d5c8243 | 3605 | { |
3b644cf6 | 3606 | struct igb_adapter *adapter = tx_ring->adapter; |
9d5c8243 | 3607 | struct e1000_hw *hw = &adapter->hw; |
3b644cf6 | 3608 | struct net_device *netdev = adapter->netdev; |
9d5c8243 AK |
3609 | struct e1000_tx_desc *tx_desc; |
3610 | struct igb_buffer *buffer_info; | |
3611 | struct sk_buff *skb; | |
3612 | unsigned int i; | |
3613 | u32 head, oldhead; | |
3614 | unsigned int count = 0; | |
9d5c8243 | 3615 | unsigned int total_bytes = 0, total_packets = 0; |
fc7d345d | 3616 | bool retval = true; |
9d5c8243 AK |
3617 | |
3618 | rmb(); | |
6d8126f9 | 3619 | head = get_head(tx_ring); |
9d5c8243 AK |
3620 | i = tx_ring->next_to_clean; |
3621 | while (1) { | |
3622 | while (i != head) { | |
9d5c8243 AK |
3623 | tx_desc = E1000_TX_DESC(*tx_ring, i); |
3624 | buffer_info = &tx_ring->buffer_info[i]; | |
3625 | skb = buffer_info->skb; | |
3626 | ||
3627 | if (skb) { | |
3628 | unsigned int segs, bytecount; | |
3629 | /* gso_segs is currently only valid for tcp */ | |
3630 | segs = skb_shinfo(skb)->gso_segs ?: 1; | |
3631 | /* multiply data chunks by size of headers */ | |
3632 | bytecount = ((segs - 1) * skb_headlen(skb)) + | |
3633 | skb->len; | |
3634 | total_packets += segs; | |
3635 | total_bytes += bytecount; | |
3636 | } | |
3637 | ||
3638 | igb_unmap_and_free_tx_resource(adapter, buffer_info); | |
9d5c8243 AK |
3639 | |
3640 | i++; | |
3641 | if (i == tx_ring->count) | |
3642 | i = 0; | |
3643 | ||
3644 | count++; | |
3645 | if (count == IGB_MAX_TX_CLEAN) { | |
3646 | retval = false; | |
3647 | goto done_cleaning; | |
3648 | } | |
3649 | } | |
3650 | oldhead = head; | |
3651 | rmb(); | |
6d8126f9 | 3652 | head = get_head(tx_ring); |
9d5c8243 AK |
3653 | if (head == oldhead) |
3654 | goto done_cleaning; | |
3655 | } /* while (1) */ | |
3656 | ||
3657 | done_cleaning: | |
3658 | tx_ring->next_to_clean = i; | |
3659 | ||
fc7d345d | 3660 | if (unlikely(count && |
9d5c8243 AK |
3661 | netif_carrier_ok(netdev) && |
3662 | IGB_DESC_UNUSED(tx_ring) >= IGB_TX_QUEUE_WAKE)) { | |
3663 | /* Make sure that anybody stopping the queue after this | |
3664 | * sees the new next_to_clean. | |
3665 | */ | |
3666 | smp_mb(); | |
661086df PWJ |
3667 | if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) && |
3668 | !(test_bit(__IGB_DOWN, &adapter->state))) { | |
3669 | netif_wake_subqueue(netdev, tx_ring->queue_index); | |
3670 | ++adapter->restart_queue; | |
3671 | } | |
9d5c8243 AK |
3672 | } |
3673 | ||
3674 | if (tx_ring->detect_tx_hung) { | |
3675 | /* Detect a transmit hang in hardware, this serializes the | |
3676 | * check with the clearing of time_stamp and movement of i */ | |
3677 | tx_ring->detect_tx_hung = false; | |
3678 | if (tx_ring->buffer_info[i].time_stamp && | |
3679 | time_after(jiffies, tx_ring->buffer_info[i].time_stamp + | |
3680 | (adapter->tx_timeout_factor * HZ)) | |
3681 | && !(rd32(E1000_STATUS) & | |
3682 | E1000_STATUS_TXOFF)) { | |
3683 | ||
3684 | tx_desc = E1000_TX_DESC(*tx_ring, i); | |
3685 | /* detected Tx unit hang */ | |
3686 | dev_err(&adapter->pdev->dev, | |
3687 | "Detected Tx Unit Hang\n" | |
2d064c06 | 3688 | " Tx Queue <%d>\n" |
9d5c8243 AK |
3689 | " TDH <%x>\n" |
3690 | " TDT <%x>\n" | |
3691 | " next_to_use <%x>\n" | |
3692 | " next_to_clean <%x>\n" | |
3693 | " head (WB) <%x>\n" | |
3694 | "buffer_info[next_to_clean]\n" | |
3695 | " time_stamp <%lx>\n" | |
3696 | " jiffies <%lx>\n" | |
3697 | " desc.status <%x>\n", | |
2d064c06 | 3698 | tx_ring->queue_index, |
9d5c8243 AK |
3699 | readl(adapter->hw.hw_addr + tx_ring->head), |
3700 | readl(adapter->hw.hw_addr + tx_ring->tail), | |
3701 | tx_ring->next_to_use, | |
3702 | tx_ring->next_to_clean, | |
3703 | head, | |
3704 | tx_ring->buffer_info[i].time_stamp, | |
3705 | jiffies, | |
3706 | tx_desc->upper.fields.status); | |
661086df | 3707 | netif_stop_subqueue(netdev, tx_ring->queue_index); |
9d5c8243 AK |
3708 | } |
3709 | } | |
3710 | tx_ring->total_bytes += total_bytes; | |
3711 | tx_ring->total_packets += total_packets; | |
e21ed353 AD |
3712 | tx_ring->tx_stats.bytes += total_bytes; |
3713 | tx_ring->tx_stats.packets += total_packets; | |
9d5c8243 AK |
3714 | adapter->net_stats.tx_bytes += total_bytes; |
3715 | adapter->net_stats.tx_packets += total_packets; | |
3716 | return retval; | |
3717 | } | |
3718 | ||
d3352520 AD |
3719 | #ifdef CONFIG_IGB_LRO |
3720 | /** | |
3721 | * igb_get_skb_hdr - helper function for LRO header processing | |
3722 | * @skb: pointer to sk_buff to be added to LRO packet | |
3723 | * @iphdr: pointer to ip header structure | |
3724 | * @tcph: pointer to tcp header structure | |
3725 | * @hdr_flags: pointer to header flags | |
3726 | * @priv: pointer to the receive descriptor for the current sk_buff | |
3727 | **/ | |
3728 | static int igb_get_skb_hdr(struct sk_buff *skb, void **iphdr, void **tcph, | |
3729 | u64 *hdr_flags, void *priv) | |
3730 | { | |
3731 | union e1000_adv_rx_desc *rx_desc = priv; | |
3732 | u16 pkt_type = rx_desc->wb.lower.lo_dword.pkt_info & | |
3733 | (E1000_RXDADV_PKTTYPE_IPV4 | E1000_RXDADV_PKTTYPE_TCP); | |
3734 | ||
3735 | /* Verify that this is a valid IPv4 TCP packet */ | |
3736 | if (pkt_type != (E1000_RXDADV_PKTTYPE_IPV4 | | |
3737 | E1000_RXDADV_PKTTYPE_TCP)) | |
3738 | return -1; | |
3739 | ||
3740 | /* Set network headers */ | |
3741 | skb_reset_network_header(skb); | |
3742 | skb_set_transport_header(skb, ip_hdrlen(skb)); | |
3743 | *iphdr = ip_hdr(skb); | |
3744 | *tcph = tcp_hdr(skb); | |
3745 | *hdr_flags = LRO_IPV4 | LRO_TCP; | |
3746 | ||
3747 | return 0; | |
3748 | ||
3749 | } | |
3750 | #endif /* CONFIG_IGB_LRO */ | |
9d5c8243 AK |
3751 | |
3752 | /** | |
3753 | * igb_receive_skb - helper function to handle rx indications | |
d3352520 | 3754 | * @ring: pointer to receive ring receving this packet |
9d5c8243 AK |
3755 | * @status: descriptor status field as written by hardware |
3756 | * @vlan: descriptor vlan field as written by hardware (no le/be conversion) | |
3757 | * @skb: pointer to sk_buff to be indicated to stack | |
3758 | **/ | |
d3352520 AD |
3759 | static void igb_receive_skb(struct igb_ring *ring, u8 status, |
3760 | union e1000_adv_rx_desc * rx_desc, | |
3761 | struct sk_buff *skb) | |
3762 | { | |
3763 | struct igb_adapter * adapter = ring->adapter; | |
3764 | bool vlan_extracted = (adapter->vlgrp && (status & E1000_RXD_STAT_VP)); | |
3765 | ||
3766 | #ifdef CONFIG_IGB_LRO | |
3767 | if (adapter->netdev->features & NETIF_F_LRO && | |
3768 | skb->ip_summed == CHECKSUM_UNNECESSARY) { | |
3769 | if (vlan_extracted) | |
3770 | lro_vlan_hwaccel_receive_skb(&ring->lro_mgr, skb, | |
3771 | adapter->vlgrp, | |
3772 | le16_to_cpu(rx_desc->wb.upper.vlan), | |
3773 | rx_desc); | |
3774 | else | |
3775 | lro_receive_skb(&ring->lro_mgr,skb, rx_desc); | |
3776 | ring->lro_used = 1; | |
3777 | } else { | |
3778 | #endif | |
3779 | if (vlan_extracted) | |
3780 | vlan_hwaccel_receive_skb(skb, adapter->vlgrp, | |
3781 | le16_to_cpu(rx_desc->wb.upper.vlan)); | |
3782 | else | |
3783 | ||
3784 | netif_receive_skb(skb); | |
3785 | #ifdef CONFIG_IGB_LRO | |
3786 | } | |
3787 | #endif | |
9d5c8243 AK |
3788 | } |
3789 | ||
3790 | ||
3791 | static inline void igb_rx_checksum_adv(struct igb_adapter *adapter, | |
3792 | u32 status_err, struct sk_buff *skb) | |
3793 | { | |
3794 | skb->ip_summed = CHECKSUM_NONE; | |
3795 | ||
3796 | /* Ignore Checksum bit is set or checksum is disabled through ethtool */ | |
3797 | if ((status_err & E1000_RXD_STAT_IXSM) || !adapter->rx_csum) | |
3798 | return; | |
3799 | /* TCP/UDP checksum error bit is set */ | |
3800 | if (status_err & | |
3801 | (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) { | |
3802 | /* let the stack verify checksum errors */ | |
3803 | adapter->hw_csum_err++; | |
3804 | return; | |
3805 | } | |
3806 | /* It must be a TCP or UDP packet with a valid checksum */ | |
3807 | if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)) | |
3808 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
3809 | ||
3810 | adapter->hw_csum_good++; | |
3811 | } | |
3812 | ||
3b644cf6 MW |
3813 | static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring, |
3814 | int *work_done, int budget) | |
9d5c8243 | 3815 | { |
3b644cf6 | 3816 | struct igb_adapter *adapter = rx_ring->adapter; |
9d5c8243 AK |
3817 | struct net_device *netdev = adapter->netdev; |
3818 | struct pci_dev *pdev = adapter->pdev; | |
3819 | union e1000_adv_rx_desc *rx_desc , *next_rxd; | |
3820 | struct igb_buffer *buffer_info , *next_buffer; | |
3821 | struct sk_buff *skb; | |
bf36c1a0 | 3822 | unsigned int i; |
9d5c8243 AK |
3823 | u32 length, hlen, staterr; |
3824 | bool cleaned = false; | |
3825 | int cleaned_count = 0; | |
3826 | unsigned int total_bytes = 0, total_packets = 0; | |
3827 | ||
3828 | i = rx_ring->next_to_clean; | |
3829 | rx_desc = E1000_RX_DESC_ADV(*rx_ring, i); | |
3830 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
3831 | ||
3832 | while (staterr & E1000_RXD_STAT_DD) { | |
3833 | if (*work_done >= budget) | |
3834 | break; | |
3835 | (*work_done)++; | |
3836 | buffer_info = &rx_ring->buffer_info[i]; | |
3837 | ||
3838 | /* HW will not DMA in data larger than the given buffer, even | |
3839 | * if it parses the (NFS, of course) header to be larger. In | |
3840 | * that case, it fills the header buffer and spills the rest | |
3841 | * into the page. | |
3842 | */ | |
7deb07b1 AV |
3843 | hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) & |
3844 | E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT; | |
9d5c8243 AK |
3845 | if (hlen > adapter->rx_ps_hdr_size) |
3846 | hlen = adapter->rx_ps_hdr_size; | |
3847 | ||
3848 | length = le16_to_cpu(rx_desc->wb.upper.length); | |
3849 | cleaned = true; | |
3850 | cleaned_count++; | |
3851 | ||
bf36c1a0 AD |
3852 | skb = buffer_info->skb; |
3853 | prefetch(skb->data - NET_IP_ALIGN); | |
3854 | buffer_info->skb = NULL; | |
3855 | if (!adapter->rx_ps_hdr_size) { | |
3856 | pci_unmap_single(pdev, buffer_info->dma, | |
3857 | adapter->rx_buffer_len + | |
3858 | NET_IP_ALIGN, | |
3859 | PCI_DMA_FROMDEVICE); | |
3860 | skb_put(skb, length); | |
3861 | goto send_up; | |
9d5c8243 AK |
3862 | } |
3863 | ||
bf36c1a0 AD |
3864 | if (!skb_shinfo(skb)->nr_frags) { |
3865 | pci_unmap_single(pdev, buffer_info->dma, | |
3866 | adapter->rx_ps_hdr_size + | |
3867 | NET_IP_ALIGN, | |
3868 | PCI_DMA_FROMDEVICE); | |
3869 | skb_put(skb, hlen); | |
3870 | } | |
3871 | ||
3872 | if (length) { | |
9d5c8243 | 3873 | pci_unmap_page(pdev, buffer_info->page_dma, |
bf36c1a0 | 3874 | PAGE_SIZE / 2, PCI_DMA_FROMDEVICE); |
9d5c8243 | 3875 | buffer_info->page_dma = 0; |
bf36c1a0 AD |
3876 | |
3877 | skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++, | |
3878 | buffer_info->page, | |
3879 | buffer_info->page_offset, | |
3880 | length); | |
3881 | ||
3882 | if ((adapter->rx_buffer_len > (PAGE_SIZE / 2)) || | |
3883 | (page_count(buffer_info->page) != 1)) | |
3884 | buffer_info->page = NULL; | |
3885 | else | |
3886 | get_page(buffer_info->page); | |
9d5c8243 AK |
3887 | |
3888 | skb->len += length; | |
3889 | skb->data_len += length; | |
9d5c8243 | 3890 | |
bf36c1a0 | 3891 | skb->truesize += length; |
9d5c8243 AK |
3892 | } |
3893 | send_up: | |
9d5c8243 AK |
3894 | i++; |
3895 | if (i == rx_ring->count) | |
3896 | i = 0; | |
3897 | next_rxd = E1000_RX_DESC_ADV(*rx_ring, i); | |
3898 | prefetch(next_rxd); | |
3899 | next_buffer = &rx_ring->buffer_info[i]; | |
3900 | ||
bf36c1a0 AD |
3901 | if (!(staterr & E1000_RXD_STAT_EOP)) { |
3902 | buffer_info->skb = xchg(&next_buffer->skb, skb); | |
3903 | buffer_info->dma = xchg(&next_buffer->dma, 0); | |
3904 | goto next_desc; | |
3905 | } | |
3906 | ||
9d5c8243 AK |
3907 | if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) { |
3908 | dev_kfree_skb_irq(skb); | |
3909 | goto next_desc; | |
3910 | } | |
9d5c8243 AK |
3911 | |
3912 | total_bytes += skb->len; | |
3913 | total_packets++; | |
3914 | ||
3915 | igb_rx_checksum_adv(adapter, staterr, skb); | |
3916 | ||
3917 | skb->protocol = eth_type_trans(skb, netdev); | |
3918 | ||
d3352520 | 3919 | igb_receive_skb(rx_ring, staterr, rx_desc, skb); |
9d5c8243 AK |
3920 | |
3921 | netdev->last_rx = jiffies; | |
3922 | ||
3923 | next_desc: | |
3924 | rx_desc->wb.upper.status_error = 0; | |
3925 | ||
3926 | /* return some buffers to hardware, one at a time is too slow */ | |
3927 | if (cleaned_count >= IGB_RX_BUFFER_WRITE) { | |
3b644cf6 | 3928 | igb_alloc_rx_buffers_adv(rx_ring, cleaned_count); |
9d5c8243 AK |
3929 | cleaned_count = 0; |
3930 | } | |
3931 | ||
3932 | /* use prefetched values */ | |
3933 | rx_desc = next_rxd; | |
3934 | buffer_info = next_buffer; | |
3935 | ||
3936 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
3937 | } | |
bf36c1a0 | 3938 | |
9d5c8243 AK |
3939 | rx_ring->next_to_clean = i; |
3940 | cleaned_count = IGB_DESC_UNUSED(rx_ring); | |
3941 | ||
d3352520 AD |
3942 | #ifdef CONFIG_IGB_LRO |
3943 | if (rx_ring->lro_used) { | |
3944 | lro_flush_all(&rx_ring->lro_mgr); | |
3945 | rx_ring->lro_used = 0; | |
3946 | } | |
3947 | #endif | |
3948 | ||
9d5c8243 | 3949 | if (cleaned_count) |
3b644cf6 | 3950 | igb_alloc_rx_buffers_adv(rx_ring, cleaned_count); |
9d5c8243 AK |
3951 | |
3952 | rx_ring->total_packets += total_packets; | |
3953 | rx_ring->total_bytes += total_bytes; | |
3954 | rx_ring->rx_stats.packets += total_packets; | |
3955 | rx_ring->rx_stats.bytes += total_bytes; | |
3956 | adapter->net_stats.rx_bytes += total_bytes; | |
3957 | adapter->net_stats.rx_packets += total_packets; | |
3958 | return cleaned; | |
3959 | } | |
3960 | ||
3961 | ||
3962 | /** | |
3963 | * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split | |
3964 | * @adapter: address of board private structure | |
3965 | **/ | |
3b644cf6 | 3966 | static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring, |
9d5c8243 AK |
3967 | int cleaned_count) |
3968 | { | |
3b644cf6 | 3969 | struct igb_adapter *adapter = rx_ring->adapter; |
9d5c8243 AK |
3970 | struct net_device *netdev = adapter->netdev; |
3971 | struct pci_dev *pdev = adapter->pdev; | |
3972 | union e1000_adv_rx_desc *rx_desc; | |
3973 | struct igb_buffer *buffer_info; | |
3974 | struct sk_buff *skb; | |
3975 | unsigned int i; | |
3976 | ||
3977 | i = rx_ring->next_to_use; | |
3978 | buffer_info = &rx_ring->buffer_info[i]; | |
3979 | ||
3980 | while (cleaned_count--) { | |
3981 | rx_desc = E1000_RX_DESC_ADV(*rx_ring, i); | |
3982 | ||
bf36c1a0 | 3983 | if (adapter->rx_ps_hdr_size && !buffer_info->page_dma) { |
9d5c8243 | 3984 | if (!buffer_info->page) { |
bf36c1a0 AD |
3985 | buffer_info->page = alloc_page(GFP_ATOMIC); |
3986 | if (!buffer_info->page) { | |
3987 | adapter->alloc_rx_buff_failed++; | |
3988 | goto no_buffers; | |
3989 | } | |
3990 | buffer_info->page_offset = 0; | |
3991 | } else { | |
3992 | buffer_info->page_offset ^= PAGE_SIZE / 2; | |
9d5c8243 AK |
3993 | } |
3994 | buffer_info->page_dma = | |
3995 | pci_map_page(pdev, | |
3996 | buffer_info->page, | |
bf36c1a0 AD |
3997 | buffer_info->page_offset, |
3998 | PAGE_SIZE / 2, | |
9d5c8243 AK |
3999 | PCI_DMA_FROMDEVICE); |
4000 | } | |
4001 | ||
4002 | if (!buffer_info->skb) { | |
4003 | int bufsz; | |
4004 | ||
4005 | if (adapter->rx_ps_hdr_size) | |
4006 | bufsz = adapter->rx_ps_hdr_size; | |
4007 | else | |
4008 | bufsz = adapter->rx_buffer_len; | |
4009 | bufsz += NET_IP_ALIGN; | |
4010 | skb = netdev_alloc_skb(netdev, bufsz); | |
4011 | ||
4012 | if (!skb) { | |
4013 | adapter->alloc_rx_buff_failed++; | |
4014 | goto no_buffers; | |
4015 | } | |
4016 | ||
4017 | /* Make buffer alignment 2 beyond a 16 byte boundary | |
4018 | * this will result in a 16 byte aligned IP header after | |
4019 | * the 14 byte MAC header is removed | |
4020 | */ | |
4021 | skb_reserve(skb, NET_IP_ALIGN); | |
4022 | ||
4023 | buffer_info->skb = skb; | |
4024 | buffer_info->dma = pci_map_single(pdev, skb->data, | |
4025 | bufsz, | |
4026 | PCI_DMA_FROMDEVICE); | |
4027 | ||
4028 | } | |
4029 | /* Refresh the desc even if buffer_addrs didn't change because | |
4030 | * each write-back erases this info. */ | |
4031 | if (adapter->rx_ps_hdr_size) { | |
4032 | rx_desc->read.pkt_addr = | |
4033 | cpu_to_le64(buffer_info->page_dma); | |
4034 | rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma); | |
4035 | } else { | |
4036 | rx_desc->read.pkt_addr = | |
4037 | cpu_to_le64(buffer_info->dma); | |
4038 | rx_desc->read.hdr_addr = 0; | |
4039 | } | |
4040 | ||
4041 | i++; | |
4042 | if (i == rx_ring->count) | |
4043 | i = 0; | |
4044 | buffer_info = &rx_ring->buffer_info[i]; | |
4045 | } | |
4046 | ||
4047 | no_buffers: | |
4048 | if (rx_ring->next_to_use != i) { | |
4049 | rx_ring->next_to_use = i; | |
4050 | if (i == 0) | |
4051 | i = (rx_ring->count - 1); | |
4052 | else | |
4053 | i--; | |
4054 | ||
4055 | /* Force memory writes to complete before letting h/w | |
4056 | * know there are new descriptors to fetch. (Only | |
4057 | * applicable for weak-ordered memory model archs, | |
4058 | * such as IA-64). */ | |
4059 | wmb(); | |
4060 | writel(i, adapter->hw.hw_addr + rx_ring->tail); | |
4061 | } | |
4062 | } | |
4063 | ||
4064 | /** | |
4065 | * igb_mii_ioctl - | |
4066 | * @netdev: | |
4067 | * @ifreq: | |
4068 | * @cmd: | |
4069 | **/ | |
4070 | static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) | |
4071 | { | |
4072 | struct igb_adapter *adapter = netdev_priv(netdev); | |
4073 | struct mii_ioctl_data *data = if_mii(ifr); | |
4074 | ||
4075 | if (adapter->hw.phy.media_type != e1000_media_type_copper) | |
4076 | return -EOPNOTSUPP; | |
4077 | ||
4078 | switch (cmd) { | |
4079 | case SIOCGMIIPHY: | |
4080 | data->phy_id = adapter->hw.phy.addr; | |
4081 | break; | |
4082 | case SIOCGMIIREG: | |
4083 | if (!capable(CAP_NET_ADMIN)) | |
4084 | return -EPERM; | |
4085 | if (adapter->hw.phy.ops.read_phy_reg(&adapter->hw, | |
4086 | data->reg_num | |
4087 | & 0x1F, &data->val_out)) | |
4088 | return -EIO; | |
4089 | break; | |
4090 | case SIOCSMIIREG: | |
4091 | default: | |
4092 | return -EOPNOTSUPP; | |
4093 | } | |
4094 | return 0; | |
4095 | } | |
4096 | ||
4097 | /** | |
4098 | * igb_ioctl - | |
4099 | * @netdev: | |
4100 | * @ifreq: | |
4101 | * @cmd: | |
4102 | **/ | |
4103 | static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) | |
4104 | { | |
4105 | switch (cmd) { | |
4106 | case SIOCGMIIPHY: | |
4107 | case SIOCGMIIREG: | |
4108 | case SIOCSMIIREG: | |
4109 | return igb_mii_ioctl(netdev, ifr, cmd); | |
4110 | default: | |
4111 | return -EOPNOTSUPP; | |
4112 | } | |
4113 | } | |
4114 | ||
4115 | static void igb_vlan_rx_register(struct net_device *netdev, | |
4116 | struct vlan_group *grp) | |
4117 | { | |
4118 | struct igb_adapter *adapter = netdev_priv(netdev); | |
4119 | struct e1000_hw *hw = &adapter->hw; | |
4120 | u32 ctrl, rctl; | |
4121 | ||
4122 | igb_irq_disable(adapter); | |
4123 | adapter->vlgrp = grp; | |
4124 | ||
4125 | if (grp) { | |
4126 | /* enable VLAN tag insert/strip */ | |
4127 | ctrl = rd32(E1000_CTRL); | |
4128 | ctrl |= E1000_CTRL_VME; | |
4129 | wr32(E1000_CTRL, ctrl); | |
4130 | ||
4131 | /* enable VLAN receive filtering */ | |
4132 | rctl = rd32(E1000_RCTL); | |
9d5c8243 AK |
4133 | rctl &= ~E1000_RCTL_CFIEN; |
4134 | wr32(E1000_RCTL, rctl); | |
4135 | igb_update_mng_vlan(adapter); | |
4136 | wr32(E1000_RLPML, | |
4137 | adapter->max_frame_size + VLAN_TAG_SIZE); | |
4138 | } else { | |
4139 | /* disable VLAN tag insert/strip */ | |
4140 | ctrl = rd32(E1000_CTRL); | |
4141 | ctrl &= ~E1000_CTRL_VME; | |
4142 | wr32(E1000_CTRL, ctrl); | |
4143 | ||
9d5c8243 AK |
4144 | if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) { |
4145 | igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id); | |
4146 | adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; | |
4147 | } | |
4148 | wr32(E1000_RLPML, | |
4149 | adapter->max_frame_size); | |
4150 | } | |
4151 | ||
4152 | if (!test_bit(__IGB_DOWN, &adapter->state)) | |
4153 | igb_irq_enable(adapter); | |
4154 | } | |
4155 | ||
4156 | static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid) | |
4157 | { | |
4158 | struct igb_adapter *adapter = netdev_priv(netdev); | |
4159 | struct e1000_hw *hw = &adapter->hw; | |
4160 | u32 vfta, index; | |
4161 | ||
4162 | if ((adapter->hw.mng_cookie.status & | |
4163 | E1000_MNG_DHCP_COOKIE_STATUS_VLAN) && | |
4164 | (vid == adapter->mng_vlan_id)) | |
4165 | return; | |
4166 | /* add VID to filter table */ | |
4167 | index = (vid >> 5) & 0x7F; | |
4168 | vfta = array_rd32(E1000_VFTA, index); | |
4169 | vfta |= (1 << (vid & 0x1F)); | |
4170 | igb_write_vfta(&adapter->hw, index, vfta); | |
4171 | } | |
4172 | ||
4173 | static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) | |
4174 | { | |
4175 | struct igb_adapter *adapter = netdev_priv(netdev); | |
4176 | struct e1000_hw *hw = &adapter->hw; | |
4177 | u32 vfta, index; | |
4178 | ||
4179 | igb_irq_disable(adapter); | |
4180 | vlan_group_set_device(adapter->vlgrp, vid, NULL); | |
4181 | ||
4182 | if (!test_bit(__IGB_DOWN, &adapter->state)) | |
4183 | igb_irq_enable(adapter); | |
4184 | ||
4185 | if ((adapter->hw.mng_cookie.status & | |
4186 | E1000_MNG_DHCP_COOKIE_STATUS_VLAN) && | |
4187 | (vid == adapter->mng_vlan_id)) { | |
4188 | /* release control to f/w */ | |
4189 | igb_release_hw_control(adapter); | |
4190 | return; | |
4191 | } | |
4192 | ||
4193 | /* remove VID from filter table */ | |
4194 | index = (vid >> 5) & 0x7F; | |
4195 | vfta = array_rd32(E1000_VFTA, index); | |
4196 | vfta &= ~(1 << (vid & 0x1F)); | |
4197 | igb_write_vfta(&adapter->hw, index, vfta); | |
4198 | } | |
4199 | ||
4200 | static void igb_restore_vlan(struct igb_adapter *adapter) | |
4201 | { | |
4202 | igb_vlan_rx_register(adapter->netdev, adapter->vlgrp); | |
4203 | ||
4204 | if (adapter->vlgrp) { | |
4205 | u16 vid; | |
4206 | for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) { | |
4207 | if (!vlan_group_get_device(adapter->vlgrp, vid)) | |
4208 | continue; | |
4209 | igb_vlan_rx_add_vid(adapter->netdev, vid); | |
4210 | } | |
4211 | } | |
4212 | } | |
4213 | ||
4214 | int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx) | |
4215 | { | |
4216 | struct e1000_mac_info *mac = &adapter->hw.mac; | |
4217 | ||
4218 | mac->autoneg = 0; | |
4219 | ||
4220 | /* Fiber NICs only allow 1000 gbps Full duplex */ | |
4221 | if ((adapter->hw.phy.media_type == e1000_media_type_fiber) && | |
4222 | spddplx != (SPEED_1000 + DUPLEX_FULL)) { | |
4223 | dev_err(&adapter->pdev->dev, | |
4224 | "Unsupported Speed/Duplex configuration\n"); | |
4225 | return -EINVAL; | |
4226 | } | |
4227 | ||
4228 | switch (spddplx) { | |
4229 | case SPEED_10 + DUPLEX_HALF: | |
4230 | mac->forced_speed_duplex = ADVERTISE_10_HALF; | |
4231 | break; | |
4232 | case SPEED_10 + DUPLEX_FULL: | |
4233 | mac->forced_speed_duplex = ADVERTISE_10_FULL; | |
4234 | break; | |
4235 | case SPEED_100 + DUPLEX_HALF: | |
4236 | mac->forced_speed_duplex = ADVERTISE_100_HALF; | |
4237 | break; | |
4238 | case SPEED_100 + DUPLEX_FULL: | |
4239 | mac->forced_speed_duplex = ADVERTISE_100_FULL; | |
4240 | break; | |
4241 | case SPEED_1000 + DUPLEX_FULL: | |
4242 | mac->autoneg = 1; | |
4243 | adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; | |
4244 | break; | |
4245 | case SPEED_1000 + DUPLEX_HALF: /* not supported */ | |
4246 | default: | |
4247 | dev_err(&adapter->pdev->dev, | |
4248 | "Unsupported Speed/Duplex configuration\n"); | |
4249 | return -EINVAL; | |
4250 | } | |
4251 | return 0; | |
4252 | } | |
4253 | ||
4254 | ||
4255 | static int igb_suspend(struct pci_dev *pdev, pm_message_t state) | |
4256 | { | |
4257 | struct net_device *netdev = pci_get_drvdata(pdev); | |
4258 | struct igb_adapter *adapter = netdev_priv(netdev); | |
4259 | struct e1000_hw *hw = &adapter->hw; | |
2d064c06 | 4260 | u32 ctrl, rctl, status; |
9d5c8243 AK |
4261 | u32 wufc = adapter->wol; |
4262 | #ifdef CONFIG_PM | |
4263 | int retval = 0; | |
4264 | #endif | |
4265 | ||
4266 | netif_device_detach(netdev); | |
4267 | ||
a88f10ec AD |
4268 | if (netif_running(netdev)) |
4269 | igb_close(netdev); | |
4270 | ||
4271 | igb_reset_interrupt_capability(adapter); | |
4272 | ||
4273 | igb_free_queues(adapter); | |
9d5c8243 AK |
4274 | |
4275 | #ifdef CONFIG_PM | |
4276 | retval = pci_save_state(pdev); | |
4277 | if (retval) | |
4278 | return retval; | |
4279 | #endif | |
4280 | ||
4281 | status = rd32(E1000_STATUS); | |
4282 | if (status & E1000_STATUS_LU) | |
4283 | wufc &= ~E1000_WUFC_LNKC; | |
4284 | ||
4285 | if (wufc) { | |
4286 | igb_setup_rctl(adapter); | |
4287 | igb_set_multi(netdev); | |
4288 | ||
4289 | /* turn on all-multi mode if wake on multicast is enabled */ | |
4290 | if (wufc & E1000_WUFC_MC) { | |
4291 | rctl = rd32(E1000_RCTL); | |
4292 | rctl |= E1000_RCTL_MPE; | |
4293 | wr32(E1000_RCTL, rctl); | |
4294 | } | |
4295 | ||
4296 | ctrl = rd32(E1000_CTRL); | |
4297 | /* advertise wake from D3Cold */ | |
4298 | #define E1000_CTRL_ADVD3WUC 0x00100000 | |
4299 | /* phy power management enable */ | |
4300 | #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 | |
4301 | ctrl |= E1000_CTRL_ADVD3WUC; | |
4302 | wr32(E1000_CTRL, ctrl); | |
4303 | ||
9d5c8243 AK |
4304 | /* Allow time for pending master requests to run */ |
4305 | igb_disable_pcie_master(&adapter->hw); | |
4306 | ||
4307 | wr32(E1000_WUC, E1000_WUC_PME_EN); | |
4308 | wr32(E1000_WUFC, wufc); | |
9d5c8243 AK |
4309 | } else { |
4310 | wr32(E1000_WUC, 0); | |
4311 | wr32(E1000_WUFC, 0); | |
9d5c8243 AK |
4312 | } |
4313 | ||
2d064c06 AD |
4314 | /* make sure adapter isn't asleep if manageability/wol is enabled */ |
4315 | if (wufc || adapter->en_mng_pt) { | |
9d5c8243 AK |
4316 | pci_enable_wake(pdev, PCI_D3hot, 1); |
4317 | pci_enable_wake(pdev, PCI_D3cold, 1); | |
2d064c06 AD |
4318 | } else { |
4319 | igb_shutdown_fiber_serdes_link_82575(hw); | |
4320 | pci_enable_wake(pdev, PCI_D3hot, 0); | |
4321 | pci_enable_wake(pdev, PCI_D3cold, 0); | |
9d5c8243 AK |
4322 | } |
4323 | ||
4324 | /* Release control of h/w to f/w. If f/w is AMT enabled, this | |
4325 | * would have already happened in close and is redundant. */ | |
4326 | igb_release_hw_control(adapter); | |
4327 | ||
4328 | pci_disable_device(pdev); | |
4329 | ||
4330 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); | |
4331 | ||
4332 | return 0; | |
4333 | } | |
4334 | ||
4335 | #ifdef CONFIG_PM | |
4336 | static int igb_resume(struct pci_dev *pdev) | |
4337 | { | |
4338 | struct net_device *netdev = pci_get_drvdata(pdev); | |
4339 | struct igb_adapter *adapter = netdev_priv(netdev); | |
4340 | struct e1000_hw *hw = &adapter->hw; | |
4341 | u32 err; | |
4342 | ||
4343 | pci_set_power_state(pdev, PCI_D0); | |
4344 | pci_restore_state(pdev); | |
42bfd33a TI |
4345 | |
4346 | if (adapter->need_ioport) | |
4347 | err = pci_enable_device(pdev); | |
4348 | else | |
4349 | err = pci_enable_device_mem(pdev); | |
9d5c8243 AK |
4350 | if (err) { |
4351 | dev_err(&pdev->dev, | |
4352 | "igb: Cannot enable PCI device from suspend\n"); | |
4353 | return err; | |
4354 | } | |
4355 | pci_set_master(pdev); | |
4356 | ||
4357 | pci_enable_wake(pdev, PCI_D3hot, 0); | |
4358 | pci_enable_wake(pdev, PCI_D3cold, 0); | |
4359 | ||
a88f10ec AD |
4360 | igb_set_interrupt_capability(adapter); |
4361 | ||
4362 | if (igb_alloc_queues(adapter)) { | |
4363 | dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); | |
4364 | return -ENOMEM; | |
9d5c8243 AK |
4365 | } |
4366 | ||
4367 | /* e1000_power_up_phy(adapter); */ | |
4368 | ||
4369 | igb_reset(adapter); | |
4370 | wr32(E1000_WUS, ~0); | |
4371 | ||
a88f10ec AD |
4372 | if (netif_running(netdev)) { |
4373 | err = igb_open(netdev); | |
4374 | if (err) | |
4375 | return err; | |
4376 | } | |
9d5c8243 AK |
4377 | |
4378 | netif_device_attach(netdev); | |
4379 | ||
4380 | /* let the f/w know that the h/w is now under the control of the | |
4381 | * driver. */ | |
4382 | igb_get_hw_control(adapter); | |
4383 | ||
4384 | return 0; | |
4385 | } | |
4386 | #endif | |
4387 | ||
4388 | static void igb_shutdown(struct pci_dev *pdev) | |
4389 | { | |
4390 | igb_suspend(pdev, PMSG_SUSPEND); | |
4391 | } | |
4392 | ||
4393 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
4394 | /* | |
4395 | * Polling 'interrupt' - used by things like netconsole to send skbs | |
4396 | * without having to re-enable interrupts. It's not called while | |
4397 | * the interrupt routine is executing. | |
4398 | */ | |
4399 | static void igb_netpoll(struct net_device *netdev) | |
4400 | { | |
4401 | struct igb_adapter *adapter = netdev_priv(netdev); | |
4402 | int i; | |
4403 | int work_done = 0; | |
4404 | ||
4405 | igb_irq_disable(adapter); | |
7dfc16fa AD |
4406 | adapter->flags |= IGB_FLAG_IN_NETPOLL; |
4407 | ||
9d5c8243 | 4408 | for (i = 0; i < adapter->num_tx_queues; i++) |
3b644cf6 | 4409 | igb_clean_tx_irq(&adapter->tx_ring[i]); |
9d5c8243 AK |
4410 | |
4411 | for (i = 0; i < adapter->num_rx_queues; i++) | |
3b644cf6 | 4412 | igb_clean_rx_irq_adv(&adapter->rx_ring[i], |
9d5c8243 AK |
4413 | &work_done, |
4414 | adapter->rx_ring[i].napi.weight); | |
4415 | ||
7dfc16fa | 4416 | adapter->flags &= ~IGB_FLAG_IN_NETPOLL; |
9d5c8243 AK |
4417 | igb_irq_enable(adapter); |
4418 | } | |
4419 | #endif /* CONFIG_NET_POLL_CONTROLLER */ | |
4420 | ||
4421 | /** | |
4422 | * igb_io_error_detected - called when PCI error is detected | |
4423 | * @pdev: Pointer to PCI device | |
4424 | * @state: The current pci connection state | |
4425 | * | |
4426 | * This function is called after a PCI bus error affecting | |
4427 | * this device has been detected. | |
4428 | */ | |
4429 | static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, | |
4430 | pci_channel_state_t state) | |
4431 | { | |
4432 | struct net_device *netdev = pci_get_drvdata(pdev); | |
4433 | struct igb_adapter *adapter = netdev_priv(netdev); | |
4434 | ||
4435 | netif_device_detach(netdev); | |
4436 | ||
4437 | if (netif_running(netdev)) | |
4438 | igb_down(adapter); | |
4439 | pci_disable_device(pdev); | |
4440 | ||
4441 | /* Request a slot slot reset. */ | |
4442 | return PCI_ERS_RESULT_NEED_RESET; | |
4443 | } | |
4444 | ||
4445 | /** | |
4446 | * igb_io_slot_reset - called after the pci bus has been reset. | |
4447 | * @pdev: Pointer to PCI device | |
4448 | * | |
4449 | * Restart the card from scratch, as if from a cold-boot. Implementation | |
4450 | * resembles the first-half of the igb_resume routine. | |
4451 | */ | |
4452 | static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) | |
4453 | { | |
4454 | struct net_device *netdev = pci_get_drvdata(pdev); | |
4455 | struct igb_adapter *adapter = netdev_priv(netdev); | |
4456 | struct e1000_hw *hw = &adapter->hw; | |
42bfd33a | 4457 | int err; |
9d5c8243 | 4458 | |
42bfd33a TI |
4459 | if (adapter->need_ioport) |
4460 | err = pci_enable_device(pdev); | |
4461 | else | |
4462 | err = pci_enable_device_mem(pdev); | |
4463 | if (err) { | |
9d5c8243 AK |
4464 | dev_err(&pdev->dev, |
4465 | "Cannot re-enable PCI device after reset.\n"); | |
4466 | return PCI_ERS_RESULT_DISCONNECT; | |
4467 | } | |
4468 | pci_set_master(pdev); | |
c682fc23 | 4469 | pci_restore_state(pdev); |
9d5c8243 AK |
4470 | |
4471 | pci_enable_wake(pdev, PCI_D3hot, 0); | |
4472 | pci_enable_wake(pdev, PCI_D3cold, 0); | |
4473 | ||
4474 | igb_reset(adapter); | |
4475 | wr32(E1000_WUS, ~0); | |
4476 | ||
4477 | return PCI_ERS_RESULT_RECOVERED; | |
4478 | } | |
4479 | ||
4480 | /** | |
4481 | * igb_io_resume - called when traffic can start flowing again. | |
4482 | * @pdev: Pointer to PCI device | |
4483 | * | |
4484 | * This callback is called when the error recovery driver tells us that | |
4485 | * its OK to resume normal operation. Implementation resembles the | |
4486 | * second-half of the igb_resume routine. | |
4487 | */ | |
4488 | static void igb_io_resume(struct pci_dev *pdev) | |
4489 | { | |
4490 | struct net_device *netdev = pci_get_drvdata(pdev); | |
4491 | struct igb_adapter *adapter = netdev_priv(netdev); | |
4492 | ||
9d5c8243 AK |
4493 | if (netif_running(netdev)) { |
4494 | if (igb_up(adapter)) { | |
4495 | dev_err(&pdev->dev, "igb_up failed after reset\n"); | |
4496 | return; | |
4497 | } | |
4498 | } | |
4499 | ||
4500 | netif_device_attach(netdev); | |
4501 | ||
4502 | /* let the f/w know that the h/w is now under the control of the | |
4503 | * driver. */ | |
4504 | igb_get_hw_control(adapter); | |
4505 | ||
4506 | } | |
4507 | ||
4508 | /* igb_main.c */ |