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igb: only disable/enable interrupt bits for igb physical function
[mirror_ubuntu-artful-kernel.git] / drivers / net / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
86d5d38f 4 Copyright(c) 2007-2009 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/module.h>
29#include <linux/types.h>
30#include <linux/init.h>
31#include <linux/vmalloc.h>
32#include <linux/pagemap.h>
33#include <linux/netdevice.h>
9d5c8243
AK		 34#include <linux/ipv6.h>
35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
c6cb090b 37#include <linux/net_tstamp.h>
9d5c8243
AK		 38#include <linux/mii.h>
39#include <linux/ethtool.h>
40#include <linux/if_vlan.h>
41#include <linux/pci.h>
c54106bb 42#include <linux/pci-aspm.h>
9d5c8243
AK		 43#include <linux/delay.h>
44#include <linux/interrupt.h>
45#include <linux/if_ether.h>
40a914fa 46#include <linux/aer.h>
421e02f0 47#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 48#include <linux/dca.h>
49#endif
9d5c8243
AK		 50#include "igb.h"
51
86d5d38f 52#define DRV_VERSION "1.3.16-k2"
9d5c8243
AK		 53char igb_driver_name[] = "igb";
54char igb_driver_version[] = DRV_VERSION;
55static const char igb_driver_string[] =
56 "Intel(R) Gigabit Ethernet Network Driver";
86d5d38f 57static const char igb_copyright[] = "Copyright (c) 2007-2009 Intel Corporation.";
9d5c8243 58
9d5c8243
AK		 59static const struct e1000_info *igb_info_tbl[] = {
60 [board_82575] = &e1000_82575_info,
61};
62
63static struct pci_device_id igb_pci_tbl[] = {
2d064c06 64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
2d064c06
AD		 66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
c8ea5ea9 69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 70 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
71 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
72 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
73 /* required last entry */
74 {0, }
75};
76
77MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
78
79void igb_reset(struct igb_adapter *);
80static int igb_setup_all_tx_resources(struct igb_adapter *);
81static int igb_setup_all_rx_resources(struct igb_adapter *);
82static void igb_free_all_tx_resources(struct igb_adapter *);
83static void igb_free_all_rx_resources(struct igb_adapter *);
9d5c8243
AK		 84void igb_update_stats(struct igb_adapter *);
85static int igb_probe(struct pci_dev *, const struct pci_device_id *);
86static void __devexit igb_remove(struct pci_dev *pdev);
87static int igb_sw_init(struct igb_adapter *);
88static int igb_open(struct net_device *);
89static int igb_close(struct net_device *);
90static void igb_configure_tx(struct igb_adapter *);
91static void igb_configure_rx(struct igb_adapter *);
92static void igb_setup_rctl(struct igb_adapter *);
93static void igb_clean_all_tx_rings(struct igb_adapter *);
94static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 95static void igb_clean_tx_ring(struct igb_ring *);
96static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 97static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 98static void igb_update_phy_info(unsigned long);
99static void igb_watchdog(unsigned long);
100static void igb_watchdog_task(struct work_struct *);
3b29a56d
SH		 101static netdev_tx_t igb_xmit_frame_ring_adv(struct sk_buff *,
102 struct net_device *,
103 struct igb_ring *);
104static netdev_tx_t igb_xmit_frame_adv(struct sk_buff *skb,
105 struct net_device *);
9d5c8243
AK		 106static struct net_device_stats *igb_get_stats(struct net_device *);
107static int igb_change_mtu(struct net_device *, int);
108static int igb_set_mac(struct net_device *, void *);
109static irqreturn_t igb_intr(int irq, void *);
110static irqreturn_t igb_intr_msi(int irq, void *);
111static irqreturn_t igb_msix_other(int irq, void *);
112static irqreturn_t igb_msix_rx(int irq, void *);
113static irqreturn_t igb_msix_tx(int irq, void *);
421e02f0 114#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 115static void igb_update_rx_dca(struct igb_ring *);
116static void igb_update_tx_dca(struct igb_ring *);
117static void igb_setup_dca(struct igb_adapter *);
421e02f0 118#endif /* CONFIG_IGB_DCA */
3b644cf6 119static bool igb_clean_tx_irq(struct igb_ring *);
661086df 120static int igb_poll(struct napi_struct *, int);
3b644cf6
MW		 121static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int);
122static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
9d5c8243
AK		 123static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
124static void igb_tx_timeout(struct net_device *);
125static void igb_reset_task(struct work_struct *);
126static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
127static void igb_vlan_rx_add_vid(struct net_device *, u16);
128static void igb_vlan_rx_kill_vid(struct net_device *, u16);
129static void igb_restore_vlan(struct igb_adapter *);
4ae196df
AD		 130static void igb_ping_all_vfs(struct igb_adapter *);
131static void igb_msg_task(struct igb_adapter *);
132static int igb_rcv_msg_from_vf(struct igb_adapter *, u32);
28fc06f5 133static inline void igb_set_rah_pool(struct e1000_hw *, int , int);
4ae196df 134static void igb_vmm_control(struct igb_adapter *);
4ae196df
AD		 135static int igb_set_vf_mac(struct igb_adapter *adapter, int, unsigned char *);
136static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
9d5c8243 137
c8159b2d
ED		 138static inline void igb_set_vmolr(struct e1000_hw *hw, int vfn)
139{
140 u32 reg_data;
141
142 reg_data = rd32(E1000_VMOLR(vfn));
143 reg_data |= E1000_VMOLR_BAM | /* Accept broadcast */
144 E1000_VMOLR_ROPE | /* Accept packets matched in UTA */
145 E1000_VMOLR_ROMPE | /* Accept packets matched in MTA */
146 E1000_VMOLR_AUPE | /* Accept untagged packets */
147 E1000_VMOLR_STRVLAN; /* Strip vlan tags */
148 wr32(E1000_VMOLR(vfn), reg_data);
149}
150
151static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
152 int vfn)
153{
154 struct e1000_hw *hw = &adapter->hw;
155 u32 vmolr;
156
157 vmolr = rd32(E1000_VMOLR(vfn));
158 vmolr &= ~E1000_VMOLR_RLPML_MASK;
159 vmolr |= size | E1000_VMOLR_LPE;
160 wr32(E1000_VMOLR(vfn), vmolr);
161
162 return 0;
163}
164
165static inline void igb_set_rah_pool(struct e1000_hw *hw, int pool, int entry)
166{
167 u32 reg_data;
168
169 reg_data = rd32(E1000_RAH(entry));
170 reg_data &= ~E1000_RAH_POOL_MASK;
171 reg_data |= E1000_RAH_POOL_1 << pool;;
172 wr32(E1000_RAH(entry), reg_data);
173}
174
9d5c8243 175#ifdef CONFIG_PM
3fe7c4c9 176static int igb_suspend(struct pci_dev *, pm_message_t);
9d5c8243
AK		 177static int igb_resume(struct pci_dev *);
178#endif
179static void igb_shutdown(struct pci_dev *);
421e02f0 180#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 181static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
182static struct notifier_block dca_notifier = {
183 .notifier_call = igb_notify_dca,
184 .next = NULL,
185 .priority = 0
186};
187#endif
9d5c8243
AK		 188#ifdef CONFIG_NET_POLL_CONTROLLER
189/* for netdump / net console */
190static void igb_netpoll(struct net_device *);
191#endif
37680117 192#ifdef CONFIG_PCI_IOV
2a3abf6d
AD		 193static unsigned int max_vfs = 0;
194module_param(max_vfs, uint, 0);
195MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
196 "per physical function");
197#endif /* CONFIG_PCI_IOV */
198
9d5c8243
AK		 199static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
200 pci_channel_state_t);
201static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
202static void igb_io_resume(struct pci_dev *);
203
204static struct pci_error_handlers igb_err_handler = {
205 .error_detected = igb_io_error_detected,
206 .slot_reset = igb_io_slot_reset,
207 .resume = igb_io_resume,
208};
209
210
211static struct pci_driver igb_driver = {
212 .name = igb_driver_name,
213 .id_table = igb_pci_tbl,
214 .probe = igb_probe,
215 .remove = __devexit_p(igb_remove),
216#ifdef CONFIG_PM
217 /* Power Managment Hooks */
218 .suspend = igb_suspend,
219 .resume = igb_resume,
220#endif
221 .shutdown = igb_shutdown,
222 .err_handler = &igb_err_handler
223};
224
7dfc16fa
AD		 225static int global_quad_port_a; /* global quad port a indication */
226
9d5c8243
AK		 227MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
228MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
229MODULE_LICENSE("GPL");
230MODULE_VERSION(DRV_VERSION);
231
38c845c7
PO		 232/**
233 * Scale the NIC clock cycle by a large factor so that
234 * relatively small clock corrections can be added or
235 * substracted at each clock tick. The drawbacks of a
236 * large factor are a) that the clock register overflows
237 * more quickly (not such a big deal) and b) that the
238 * increment per tick has to fit into 24 bits.
239 *
240 * Note that
241 * TIMINCA = IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS *
242 * IGB_TSYNC_SCALE
243 * TIMINCA += TIMINCA * adjustment [ppm] / 1e9
244 *
245 * The base scale factor is intentionally a power of two
246 * so that the division in %struct timecounter can be done with
247 * a shift.
248 */
249#define IGB_TSYNC_SHIFT (19)
250#define IGB_TSYNC_SCALE (1<<IGB_TSYNC_SHIFT)
251
252/**
253 * The duration of one clock cycle of the NIC.
254 *
255 * @todo This hard-coded value is part of the specification and might change
256 * in future hardware revisions. Add revision check.
257 */
258#define IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS 16
259
260#if (IGB_TSYNC_SCALE * IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS) >= (1<<24)
261# error IGB_TSYNC_SCALE and/or IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS are too large to fit into TIMINCA
262#endif
263
264/**
265 * igb_read_clock - read raw cycle counter (to be used by time counter)
266 */
267static cycle_t igb_read_clock(const struct cyclecounter *tc)
268{
269 struct igb_adapter *adapter =
270 container_of(tc, struct igb_adapter, cycles);
271 struct e1000_hw *hw = &adapter->hw;
272 u64 stamp;
273
274 stamp = rd32(E1000_SYSTIML);
275 stamp |= (u64)rd32(E1000_SYSTIMH) << 32ULL;
276
277 return stamp;
278}
279
9d5c8243
AK		 280#ifdef DEBUG
281/**
282 * igb_get_hw_dev_name - return device name string
283 * used by hardware layer to print debugging information
284 **/
285char *igb_get_hw_dev_name(struct e1000_hw *hw)
286{
287 struct igb_adapter *adapter = hw->back;
288 return adapter->netdev->name;
289}
38c845c7
PO		 290
291/**
292 * igb_get_time_str - format current NIC and system time as string
293 */
294static char *igb_get_time_str(struct igb_adapter *adapter,
295 char buffer[160])
296{
297 cycle_t hw = adapter->cycles.read(&adapter->cycles);
298 struct timespec nic = ns_to_timespec(timecounter_read(&adapter->clock));
299 struct timespec sys;
300 struct timespec delta;
301 getnstimeofday(&sys);
302
303 delta = timespec_sub(nic, sys);
304
305 sprintf(buffer,
33af6bcc
PO		 306 "HW %llu, NIC %ld.%09lus, SYS %ld.%09lus, NIC-SYS %lds + %09luns",
307 hw,
38c845c7
PO		 308 (long)nic.tv_sec, nic.tv_nsec,
309 (long)sys.tv_sec, sys.tv_nsec,
310 (long)delta.tv_sec, delta.tv_nsec);
311
312 return buffer;
313}
9d5c8243
AK		 314#endif
315
c493ea45
AD		 316/**
317 * igb_desc_unused - calculate if we have unused descriptors
318 **/
319static int igb_desc_unused(struct igb_ring *ring)
320{
321 if (ring->next_to_clean > ring->next_to_use)
322 return ring->next_to_clean - ring->next_to_use - 1;
323
324 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
325}
326
9d5c8243
AK		 327/**
328 * igb_init_module - Driver Registration Routine
329 *
330 * igb_init_module is the first routine called when the driver is
331 * loaded. All it does is register with the PCI subsystem.
332 **/
333static int __init igb_init_module(void)
334{
335 int ret;
336 printk(KERN_INFO "%s - version %s\n",
337 igb_driver_string, igb_driver_version);
338
339 printk(KERN_INFO "%s\n", igb_copyright);
340
7dfc16fa
AD		 341 global_quad_port_a = 0;
342
421e02f0 343#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 344 dca_register_notify(&dca_notifier);
345#endif
bbd98fe4
AD		 346
347 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 348 return ret;
349}
350
351module_init(igb_init_module);
352
353/**
354 * igb_exit_module - Driver Exit Cleanup Routine
355 *
356 * igb_exit_module is called just before the driver is removed
357 * from memory.
358 **/
359static void __exit igb_exit_module(void)
360{
421e02f0 361#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 362 dca_unregister_notify(&dca_notifier);
363#endif
9d5c8243
AK		 364 pci_unregister_driver(&igb_driver);
365}
366
367module_exit(igb_exit_module);
368
26bc19ec
AD		 369#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
370/**
371 * igb_cache_ring_register - Descriptor ring to register mapping
372 * @adapter: board private structure to initialize
373 *
374 * Once we know the feature-set enabled for the device, we'll cache
375 * the register offset the descriptor ring is assigned to.
376 **/
377static void igb_cache_ring_register(struct igb_adapter *adapter)
378{
379 int i;
1bfaf07b 380 unsigned int rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 381
382 switch (adapter->hw.mac.type) {
383 case e1000_82576:
384 /* The queues are allocated for virtualization such that VF 0
385 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
386 * In order to avoid collision we start at the first free queue
387 * and continue consuming queues in the same sequence
388 */
389 for (i = 0; i < adapter->num_rx_queues; i++)
1bfaf07b
AD		 390 adapter->rx_ring[i].reg_idx = rbase_offset +
391 Q_IDX_82576(i);
26bc19ec 392 for (i = 0; i < adapter->num_tx_queues; i++)
1bfaf07b
AD		 393 adapter->tx_ring[i].reg_idx = rbase_offset +
394 Q_IDX_82576(i);
26bc19ec
AD		 395 break;
396 case e1000_82575:
397 default:
398 for (i = 0; i < adapter->num_rx_queues; i++)
399 adapter->rx_ring[i].reg_idx = i;
400 for (i = 0; i < adapter->num_tx_queues; i++)
401 adapter->tx_ring[i].reg_idx = i;
402 break;
403 }
404}
405
9d5c8243
AK		 406/**
407 * igb_alloc_queues - Allocate memory for all rings
408 * @adapter: board private structure to initialize
409 *
410 * We allocate one ring per queue at run-time since we don't know the
411 * number of queues at compile-time.
412 **/
413static int igb_alloc_queues(struct igb_adapter *adapter)
414{
415 int i;
416
417 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
418 sizeof(struct igb_ring), GFP_KERNEL);
419 if (!adapter->tx_ring)
420 return -ENOMEM;
421
422 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
423 sizeof(struct igb_ring), GFP_KERNEL);
424 if (!adapter->rx_ring) {
425 kfree(adapter->tx_ring);
426 return -ENOMEM;
427 }
428
6eb5a7f1
AD		 429 adapter->rx_ring->buddy = adapter->tx_ring;
430
661086df
PWJ		 431 for (i = 0; i < adapter->num_tx_queues; i++) {
432 struct igb_ring *ring = &(adapter->tx_ring[i]);
68fd9910 433 ring->count = adapter->tx_ring_count;
661086df
PWJ		 434 ring->adapter = adapter;
435 ring->queue_index = i;
436 }
9d5c8243
AK		 437 for (i = 0; i < adapter->num_rx_queues; i++) {
438 struct igb_ring *ring = &(adapter->rx_ring[i]);
68fd9910 439 ring->count = adapter->rx_ring_count;
9d5c8243 440 ring->adapter = adapter;
844290e5 441 ring->queue_index = i;
9d5c8243
AK		 442 ring->itr_register = E1000_ITR;
443
844290e5 444 /* set a default napi handler for each rx_ring */
661086df 445 netif_napi_add(adapter->netdev, &ring->napi, igb_poll, 64);
9d5c8243 446 }
26bc19ec
AD		 447
448 igb_cache_ring_register(adapter);
9d5c8243
AK		 449 return 0;
450}
451
a88f10ec
AD		 452static void igb_free_queues(struct igb_adapter *adapter)
453{
454 int i;
455
456 for (i = 0; i < adapter->num_rx_queues; i++)
457 netif_napi_del(&adapter->rx_ring[i].napi);
458
d1a8c9e1
AD		 459 adapter->num_rx_queues = 0;
460 adapter->num_tx_queues = 0;
461
a88f10ec
AD		 462 kfree(adapter->tx_ring);
463 kfree(adapter->rx_ring);
464}
465
9d5c8243
AK		 466#define IGB_N0_QUEUE -1
467static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
468 int tx_queue, int msix_vector)
469{
470 u32 msixbm = 0;
471 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 472 u32 ivar, index;
473
474 switch (hw->mac.type) {
475 case e1000_82575:
9d5c8243
AK		 476 /* The 82575 assigns vectors using a bitmask, which matches the
477 bitmask for the EICR/EIMS/EIMC registers. To assign one
478 or more queues to a vector, we write the appropriate bits
479 into the MSIXBM register for that vector. */
480 if (rx_queue > IGB_N0_QUEUE) {
481 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
482 adapter->rx_ring[rx_queue].eims_value = msixbm;
483 }
484 if (tx_queue > IGB_N0_QUEUE) {
485 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
486 adapter->tx_ring[tx_queue].eims_value =
487 E1000_EICR_TX_QUEUE0 << tx_queue;
488 }
489 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
2d064c06
AD		 490 break;
491 case e1000_82576:
26bc19ec 492 /* 82576 uses a table-based method for assigning vectors.
2d064c06
AD		 493 Each queue has a single entry in the table to which we write
494 a vector number along with a "valid" bit. Sadly, the layout
495 of the table is somewhat counterintuitive. */
496 if (rx_queue > IGB_N0_QUEUE) {
1bfaf07b 497 index = (rx_queue >> 1) + adapter->vfs_allocated_count;
2d064c06 498 ivar = array_rd32(E1000_IVAR0, index);
26bc19ec 499 if (rx_queue & 0x1) {
2d064c06
AD		 500 /* vector goes into third byte of register */
501 ivar = ivar & 0xFF00FFFF;
502 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
26bc19ec
AD		 503 } else {
504 /* vector goes into low byte of register */
505 ivar = ivar & 0xFFFFFF00;
506 ivar |= msix_vector | E1000_IVAR_VALID;
2d064c06
AD		 507 }
508 adapter->rx_ring[rx_queue].eims_value= 1 << msix_vector;
509 array_wr32(E1000_IVAR0, index, ivar);
510 }
511 if (tx_queue > IGB_N0_QUEUE) {
1bfaf07b 512 index = (tx_queue >> 1) + adapter->vfs_allocated_count;
2d064c06 513 ivar = array_rd32(E1000_IVAR0, index);
26bc19ec 514 if (tx_queue & 0x1) {
2d064c06
AD		 515 /* vector goes into high byte of register */
516 ivar = ivar & 0x00FFFFFF;
517 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
26bc19ec
AD		 518 } else {
519 /* vector goes into second byte of register */
520 ivar = ivar & 0xFFFF00FF;
521 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
2d064c06
AD		 522 }
523 adapter->tx_ring[tx_queue].eims_value= 1 << msix_vector;
524 array_wr32(E1000_IVAR0, index, ivar);
525 }
526 break;
527 default:
528 BUG();
529 break;
530 }
9d5c8243
AK		 531}
532
533/**
534 * igb_configure_msix - Configure MSI-X hardware
535 *
536 * igb_configure_msix sets up the hardware to properly
537 * generate MSI-X interrupts.
538 **/
539static void igb_configure_msix(struct igb_adapter *adapter)
540{
541 u32 tmp;
542 int i, vector = 0;
543 struct e1000_hw *hw = &adapter->hw;
544
545 adapter->eims_enable_mask = 0;
2d064c06
AD		 546 if (hw->mac.type == e1000_82576)
547 /* Turn on MSI-X capability first, or our settings
548 * won't stick. And it will take days to debug. */
549 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
eebbbdba 550 E1000_GPIE_PBA | E1000_GPIE_EIAME |
2d064c06 551 E1000_GPIE_NSICR);
9d5c8243
AK		 552
553 for (i = 0; i < adapter->num_tx_queues; i++) {
554 struct igb_ring *tx_ring = &adapter->tx_ring[i];
555 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
556 adapter->eims_enable_mask |= tx_ring->eims_value;
557 if (tx_ring->itr_val)
6eb5a7f1 558 writel(tx_ring->itr_val,
9d5c8243
AK		 559 hw->hw_addr + tx_ring->itr_register);
560 else
561 writel(1, hw->hw_addr + tx_ring->itr_register);
562 }
563
564 for (i = 0; i < adapter->num_rx_queues; i++) {
565 struct igb_ring *rx_ring = &adapter->rx_ring[i];
25ac3c24 566 rx_ring->buddy = NULL;
9d5c8243
AK		 567 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
568 adapter->eims_enable_mask |= rx_ring->eims_value;
569 if (rx_ring->itr_val)
6eb5a7f1 570 writel(rx_ring->itr_val,
9d5c8243
AK		 571 hw->hw_addr + rx_ring->itr_register);
572 else
573 writel(1, hw->hw_addr + rx_ring->itr_register);
574 }
575
576
577 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 578 switch (hw->mac.type) {
579 case e1000_82575:
9d5c8243
AK		 580 array_wr32(E1000_MSIXBM(0), vector++,
581 E1000_EIMS_OTHER);
582
9d5c8243
AK		 583 tmp = rd32(E1000_CTRL_EXT);
584 /* enable MSI-X PBA support*/
585 tmp |= E1000_CTRL_EXT_PBA_CLR;
586
587 /* Auto-Mask interrupts upon ICR read. */
588 tmp |= E1000_CTRL_EXT_EIAME;
589 tmp |= E1000_CTRL_EXT_IRCA;
590
591 wr32(E1000_CTRL_EXT, tmp);
592 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
844290e5 593 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 594
2d064c06
AD		 595 break;
596
597 case e1000_82576:
598 tmp = (vector++ | E1000_IVAR_VALID) << 8;
599 wr32(E1000_IVAR_MISC, tmp);
600
601 adapter->eims_enable_mask = (1 << (vector)) - 1;
602 adapter->eims_other = 1 << (vector - 1);
603 break;
604 default:
605 /* do nothing, since nothing else supports MSI-X */
606 break;
607 } /* switch (hw->mac.type) */
9d5c8243
AK		 608 wrfl();
609}
610
611/**
612 * igb_request_msix - Initialize MSI-X interrupts
613 *
614 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
615 * kernel.
616 **/
617static int igb_request_msix(struct igb_adapter *adapter)
618{
619 struct net_device *netdev = adapter->netdev;
620 int i, err = 0, vector = 0;
621
622 vector = 0;
623
624 for (i = 0; i < adapter->num_tx_queues; i++) {
625 struct igb_ring *ring = &(adapter->tx_ring[i]);
cb7b48f6 626 sprintf(ring->name, "%s-tx-%d", netdev->name, i);
9d5c8243
AK		 627 err = request_irq(adapter->msix_entries[vector].vector,
628 &igb_msix_tx, 0, ring->name,
629 &(adapter->tx_ring[i]));
630 if (err)
631 goto out;
632 ring->itr_register = E1000_EITR(0) + (vector << 2);
6eb5a7f1 633 ring->itr_val = 976; /* ~4000 ints/sec */
9d5c8243
AK		 634 vector++;
635 }
636 for (i = 0; i < adapter->num_rx_queues; i++) {
637 struct igb_ring *ring = &(adapter->rx_ring[i]);
638 if (strlen(netdev->name) < (IFNAMSIZ - 5))
cb7b48f6 639 sprintf(ring->name, "%s-rx-%d", netdev->name, i);
9d5c8243
AK		 640 else
641 memcpy(ring->name, netdev->name, IFNAMSIZ);
642 err = request_irq(adapter->msix_entries[vector].vector,
643 &igb_msix_rx, 0, ring->name,
644 &(adapter->rx_ring[i]));
645 if (err)
646 goto out;
647 ring->itr_register = E1000_EITR(0) + (vector << 2);
648 ring->itr_val = adapter->itr;
649 vector++;
650 }
651
652 err = request_irq(adapter->msix_entries[vector].vector,
653 &igb_msix_other, 0, netdev->name, netdev);
654 if (err)
655 goto out;
656
9d5c8243
AK		 657 igb_configure_msix(adapter);
658 return 0;
659out:
660 return err;
661}
662
663static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
664{
665 if (adapter->msix_entries) {
666 pci_disable_msix(adapter->pdev);
667 kfree(adapter->msix_entries);
668 adapter->msix_entries = NULL;
7dfc16fa 669 } else if (adapter->flags & IGB_FLAG_HAS_MSI)
9d5c8243
AK		 670 pci_disable_msi(adapter->pdev);
671 return;
672}
673
674
675/**
676 * igb_set_interrupt_capability - set MSI or MSI-X if supported
677 *
678 * Attempt to configure interrupts using the best available
679 * capabilities of the hardware and kernel.
680 **/
681static void igb_set_interrupt_capability(struct igb_adapter *adapter)
682{
683 int err;
684 int numvecs, i;
685
83b7180d
AD		 686 /* Number of supported queues. */
687 /* Having more queues than CPUs doesn't make sense. */
688 adapter->num_rx_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
689 adapter->num_tx_queues = min_t(u32, IGB_MAX_TX_QUEUES, num_online_cpus());
690
9d5c8243
AK		 691 numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1;
692 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
693 GFP_KERNEL);
694 if (!adapter->msix_entries)
695 goto msi_only;
696
697 for (i = 0; i < numvecs; i++)
698 adapter->msix_entries[i].entry = i;
699
700 err = pci_enable_msix(adapter->pdev,
701 adapter->msix_entries,
702 numvecs);
703 if (err == 0)
34a20e89 704 goto out;
9d5c8243
AK		 705
706 igb_reset_interrupt_capability(adapter);
707
708 /* If we can't do MSI-X, try MSI */
709msi_only:
2a3abf6d
AD		 710#ifdef CONFIG_PCI_IOV
711 /* disable SR-IOV for non MSI-X configurations */
712 if (adapter->vf_data) {
713 struct e1000_hw *hw = &adapter->hw;
714 /* disable iov and allow time for transactions to clear */
715 pci_disable_sriov(adapter->pdev);
716 msleep(500);
717
718 kfree(adapter->vf_data);
719 adapter->vf_data = NULL;
720 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
721 msleep(100);
722 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
723 }
724#endif
9d5c8243 725 adapter->num_rx_queues = 1;
661086df 726 adapter->num_tx_queues = 1;
9d5c8243 727 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 728 adapter->flags |= IGB_FLAG_HAS_MSI;
34a20e89 729out:
661086df 730 /* Notify the stack of the (possibly) reduced Tx Queue count. */
fd2ea0a7 731 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
9d5c8243
AK		 732 return;
733}
734
735/**
736 * igb_request_irq - initialize interrupts
737 *
738 * Attempts to configure interrupts using the best available
739 * capabilities of the hardware and kernel.
740 **/
741static int igb_request_irq(struct igb_adapter *adapter)
742{
743 struct net_device *netdev = adapter->netdev;
744 struct e1000_hw *hw = &adapter->hw;
745 int err = 0;
746
747 if (adapter->msix_entries) {
748 err = igb_request_msix(adapter);
844290e5 749 if (!err)
9d5c8243 750 goto request_done;
9d5c8243
AK		 751 /* fall back to MSI */
752 igb_reset_interrupt_capability(adapter);
753 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 754 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 755 igb_free_all_tx_resources(adapter);
756 igb_free_all_rx_resources(adapter);
757 adapter->num_rx_queues = 1;
758 igb_alloc_queues(adapter);
844290e5 759 } else {
2d064c06
AD		 760 switch (hw->mac.type) {
761 case e1000_82575:
762 wr32(E1000_MSIXBM(0),
763 (E1000_EICR_RX_QUEUE0 | E1000_EIMS_OTHER));
764 break;
765 case e1000_82576:
766 wr32(E1000_IVAR0, E1000_IVAR_VALID);
767 break;
768 default:
769 break;
770 }
9d5c8243 771 }
844290e5 772
7dfc16fa 773 if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243
AK		 774 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
775 netdev->name, netdev);
776 if (!err)
777 goto request_done;
778 /* fall back to legacy interrupts */
779 igb_reset_interrupt_capability(adapter);
7dfc16fa 780 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 781 }
782
783 err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
784 netdev->name, netdev);
785
6cb5e577 786 if (err)
9d5c8243
AK		 787 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
788 err);
9d5c8243
AK		 789
790request_done:
791 return err;
792}
793
794static void igb_free_irq(struct igb_adapter *adapter)
795{
796 struct net_device *netdev = adapter->netdev;
797
798 if (adapter->msix_entries) {
799 int vector = 0, i;
800
801 for (i = 0; i < adapter->num_tx_queues; i++)
802 free_irq(adapter->msix_entries[vector++].vector,
803 &(adapter->tx_ring[i]));
804 for (i = 0; i < adapter->num_rx_queues; i++)
805 free_irq(adapter->msix_entries[vector++].vector,
806 &(adapter->rx_ring[i]));
807
808 free_irq(adapter->msix_entries[vector++].vector, netdev);
809 return;
810 }
811
812 free_irq(adapter->pdev->irq, netdev);
813}
814
815/**
816 * igb_irq_disable - Mask off interrupt generation on the NIC
817 * @adapter: board private structure
818 **/
819static void igb_irq_disable(struct igb_adapter *adapter)
820{
821 struct e1000_hw *hw = &adapter->hw;
822
823 if (adapter->msix_entries) {
2dfd1212
AD		 824 u32 regval = rd32(E1000_EIAM);
825 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
826 wr32(E1000_EIMC, adapter->eims_enable_mask);
827 regval = rd32(E1000_EIAC);
828 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 829 }
844290e5
PW		 830
831 wr32(E1000_IAM, 0);
9d5c8243
AK		 832 wr32(E1000_IMC, ~0);
833 wrfl();
834 synchronize_irq(adapter->pdev->irq);
835}
836
837/**
838 * igb_irq_enable - Enable default interrupt generation settings
839 * @adapter: board private structure
840 **/
841static void igb_irq_enable(struct igb_adapter *adapter)
842{
843 struct e1000_hw *hw = &adapter->hw;
844
845 if (adapter->msix_entries) {
2dfd1212
AD		 846 u32 regval = rd32(E1000_EIAC);
847 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
848 regval = rd32(E1000_EIAM);
849 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 850 wr32(E1000_EIMS, adapter->eims_enable_mask);
4ae196df
AD		 851 if (adapter->vfs_allocated_count)
852 wr32(E1000_MBVFIMR, 0xFF);
853 wr32(E1000_IMS, (E1000_IMS_LSC | E1000_IMS_VMMB |
854 E1000_IMS_DOUTSYNC));
844290e5
PW		 855 } else {
856 wr32(E1000_IMS, IMS_ENABLE_MASK);
857 wr32(E1000_IAM, IMS_ENABLE_MASK);
858 }
9d5c8243
AK		 859}
860
861static void igb_update_mng_vlan(struct igb_adapter *adapter)
862{
863 struct net_device *netdev = adapter->netdev;
864 u16 vid = adapter->hw.mng_cookie.vlan_id;
865 u16 old_vid = adapter->mng_vlan_id;
866 if (adapter->vlgrp) {
867 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
868 if (adapter->hw.mng_cookie.status &
869 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
870 igb_vlan_rx_add_vid(netdev, vid);
871 adapter->mng_vlan_id = vid;
872 } else
873 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
874
875 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
876 (vid != old_vid) &&
877 !vlan_group_get_device(adapter->vlgrp, old_vid))
878 igb_vlan_rx_kill_vid(netdev, old_vid);
879 } else
880 adapter->mng_vlan_id = vid;
881 }
882}
883
884/**
885 * igb_release_hw_control - release control of the h/w to f/w
886 * @adapter: address of board private structure
887 *
888 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
889 * For ASF and Pass Through versions of f/w this means that the
890 * driver is no longer loaded.
891 *
892 **/
893static void igb_release_hw_control(struct igb_adapter *adapter)
894{
895 struct e1000_hw *hw = &adapter->hw;
896 u32 ctrl_ext;
897
898 /* Let firmware take over control of h/w */
899 ctrl_ext = rd32(E1000_CTRL_EXT);
900 wr32(E1000_CTRL_EXT,
901 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
902}
903
904
905/**
906 * igb_get_hw_control - get control of the h/w from f/w
907 * @adapter: address of board private structure
908 *
909 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
910 * For ASF and Pass Through versions of f/w this means that
911 * the driver is loaded.
912 *
913 **/
914static void igb_get_hw_control(struct igb_adapter *adapter)
915{
916 struct e1000_hw *hw = &adapter->hw;
917 u32 ctrl_ext;
918
919 /* Let firmware know the driver has taken over */
920 ctrl_ext = rd32(E1000_CTRL_EXT);
921 wr32(E1000_CTRL_EXT,
922 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
923}
924
9d5c8243
AK		 925/**
926 * igb_configure - configure the hardware for RX and TX
927 * @adapter: private board structure
928 **/
929static void igb_configure(struct igb_adapter *adapter)
930{
931 struct net_device *netdev = adapter->netdev;
932 int i;
933
934 igb_get_hw_control(adapter);
ff41f8dc 935 igb_set_rx_mode(netdev);
9d5c8243
AK		 936
937 igb_restore_vlan(adapter);
9d5c8243
AK		 938
939 igb_configure_tx(adapter);
940 igb_setup_rctl(adapter);
941 igb_configure_rx(adapter);
662d7205
AD		 942
943 igb_rx_fifo_flush_82575(&adapter->hw);
944
c493ea45 945 /* call igb_desc_unused which always leaves
9d5c8243
AK		 946 * at least 1 descriptor unused to make sure
947 * next_to_use != next_to_clean */
948 for (i = 0; i < adapter->num_rx_queues; i++) {
949 struct igb_ring *ring = &adapter->rx_ring[i];
c493ea45 950 igb_alloc_rx_buffers_adv(ring, igb_desc_unused(ring));
9d5c8243
AK		 951 }
952
953
954 adapter->tx_queue_len = netdev->tx_queue_len;
955}
956
957
958/**
959 * igb_up - Open the interface and prepare it to handle traffic
960 * @adapter: board private structure
961 **/
962
963int igb_up(struct igb_adapter *adapter)
964{
965 struct e1000_hw *hw = &adapter->hw;
966 int i;
967
968 /* hardware has been reset, we need to reload some things */
969 igb_configure(adapter);
970
971 clear_bit(__IGB_DOWN, &adapter->state);
972
844290e5
PW		 973 for (i = 0; i < adapter->num_rx_queues; i++)
974 napi_enable(&adapter->rx_ring[i].napi);
975 if (adapter->msix_entries)
9d5c8243 976 igb_configure_msix(adapter);
9d5c8243 977
4ae196df 978 igb_vmm_control(adapter);
e1739522
AD		 979 igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
980 igb_set_vmolr(hw, adapter->vfs_allocated_count);
981
9d5c8243
AK		 982 /* Clear any pending interrupts. */
983 rd32(E1000_ICR);
984 igb_irq_enable(adapter);
985
4cb9be7a
JB		 986 netif_tx_start_all_queues(adapter->netdev);
987
9d5c8243
AK		 988 /* Fire a link change interrupt to start the watchdog. */
989 wr32(E1000_ICS, E1000_ICS_LSC);
990 return 0;
991}
992
993void igb_down(struct igb_adapter *adapter)
994{
995 struct e1000_hw *hw = &adapter->hw;
996 struct net_device *netdev = adapter->netdev;
997 u32 tctl, rctl;
998 int i;
999
1000 /* signal that we're down so the interrupt handler does not
1001 * reschedule our watchdog timer */
1002 set_bit(__IGB_DOWN, &adapter->state);
1003
1004 /* disable receives in the hardware */
1005 rctl = rd32(E1000_RCTL);
1006 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1007 /* flush and sleep below */
1008
fd2ea0a7 1009 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1010
1011 /* disable transmits in the hardware */
1012 tctl = rd32(E1000_TCTL);
1013 tctl &= ~E1000_TCTL_EN;
1014 wr32(E1000_TCTL, tctl);
1015 /* flush both disables and wait for them to finish */
1016 wrfl();
1017 msleep(10);
1018
844290e5
PW		 1019 for (i = 0; i < adapter->num_rx_queues; i++)
1020 napi_disable(&adapter->rx_ring[i].napi);
9d5c8243 1021
9d5c8243
AK		 1022 igb_irq_disable(adapter);
1023
1024 del_timer_sync(&adapter->watchdog_timer);
1025 del_timer_sync(&adapter->phy_info_timer);
1026
1027 netdev->tx_queue_len = adapter->tx_queue_len;
1028 netif_carrier_off(netdev);
04fe6358
AD		 1029
1030 /* record the stats before reset*/
1031 igb_update_stats(adapter);
1032
9d5c8243
AK		 1033 adapter->link_speed = 0;
1034 adapter->link_duplex = 0;
1035
3023682e
JK		 1036 if (!pci_channel_offline(adapter->pdev))
1037 igb_reset(adapter);
9d5c8243
AK		 1038 igb_clean_all_tx_rings(adapter);
1039 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1040#ifdef CONFIG_IGB_DCA
1041
1042 /* since we reset the hardware DCA settings were cleared */
1043 igb_setup_dca(adapter);
1044#endif
9d5c8243
AK		 1045}
1046
1047void igb_reinit_locked(struct igb_adapter *adapter)
1048{
1049 WARN_ON(in_interrupt());
1050 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1051 msleep(1);
1052 igb_down(adapter);
1053 igb_up(adapter);
1054 clear_bit(__IGB_RESETTING, &adapter->state);
1055}
1056
1057void igb_reset(struct igb_adapter *adapter)
1058{
1059 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1060 struct e1000_mac_info *mac = &hw->mac;
1061 struct e1000_fc_info *fc = &hw->fc;
9d5c8243
AK		 1062 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
1063 u16 hwm;
1064
1065 /* Repartition Pba for greater than 9k mtu
1066 * To take effect CTRL.RST is required.
1067 */
fa4dfae0
AD		 1068 switch (mac->type) {
1069 case e1000_82576:
2d064c06 1070 pba = E1000_PBA_64K;
fa4dfae0
AD		 1071 break;
1072 case e1000_82575:
1073 default:
1074 pba = E1000_PBA_34K;
1075 break;
2d064c06 1076 }
9d5c8243 1077
2d064c06
AD		 1078 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1079 (mac->type < e1000_82576)) {
9d5c8243
AK		 1080 /* adjust PBA for jumbo frames */
1081 wr32(E1000_PBA, pba);
1082
1083 /* To maintain wire speed transmits, the Tx FIFO should be
1084 * large enough to accommodate two full transmit packets,
1085 * rounded up to the next 1KB and expressed in KB. Likewise,
1086 * the Rx FIFO should be large enough to accommodate at least
1087 * one full receive packet and is similarly rounded up and
1088 * expressed in KB. */
1089 pba = rd32(E1000_PBA);
1090 /* upper 16 bits has Tx packet buffer allocation size in KB */
1091 tx_space = pba >> 16;
1092 /* lower 16 bits has Rx packet buffer allocation size in KB */
1093 pba &= 0xffff;
1094 /* the tx fifo also stores 16 bytes of information about the tx
1095 * but don't include ethernet FCS because hardware appends it */
1096 min_tx_space = (adapter->max_frame_size +
85e8d004 1097 sizeof(union e1000_adv_tx_desc) -
9d5c8243
AK		 1098 ETH_FCS_LEN) * 2;
1099 min_tx_space = ALIGN(min_tx_space, 1024);
1100 min_tx_space >>= 10;
1101 /* software strips receive CRC, so leave room for it */
1102 min_rx_space = adapter->max_frame_size;
1103 min_rx_space = ALIGN(min_rx_space, 1024);
1104 min_rx_space >>= 10;
1105
1106 /* If current Tx allocation is less than the min Tx FIFO size,
1107 * and the min Tx FIFO size is less than the current Rx FIFO
1108 * allocation, take space away from current Rx allocation */
1109 if (tx_space < min_tx_space &&
1110 ((min_tx_space - tx_space) < pba)) {
1111 pba = pba - (min_tx_space - tx_space);
1112
1113 /* if short on rx space, rx wins and must trump tx
1114 * adjustment */
1115 if (pba < min_rx_space)
1116 pba = min_rx_space;
1117 }
2d064c06 1118 wr32(E1000_PBA, pba);
9d5c8243 1119 }
9d5c8243
AK		 1120
1121 /* flow control settings */
1122 /* The high water mark must be low enough to fit one full frame
1123 * (or the size used for early receive) above it in the Rx FIFO.
1124 * Set it to the lower of:
1125 * - 90% of the Rx FIFO size, or
1126 * - the full Rx FIFO size minus one full frame */
1127 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1128 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1129
2d064c06
AD		 1130 if (mac->type < e1000_82576) {
1131 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
1132 fc->low_water = fc->high_water - 8;
1133 } else {
1134 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1135 fc->low_water = fc->high_water - 16;
1136 }
9d5c8243
AK		 1137 fc->pause_time = 0xFFFF;
1138 fc->send_xon = 1;
0cce119a 1139 fc->current_mode = fc->requested_mode;
9d5c8243 1140
4ae196df
AD		 1141 /* disable receive for all VFs and wait one second */
1142 if (adapter->vfs_allocated_count) {
1143 int i;
1144 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
1145 adapter->vf_data[i].clear_to_send = false;
1146
1147 /* ping all the active vfs to let them know we are going down */
1148 igb_ping_all_vfs(adapter);
1149
1150 /* disable transmits and receives */
1151 wr32(E1000_VFRE, 0);
1152 wr32(E1000_VFTE, 0);
1153 }
1154
9d5c8243
AK		 1155 /* Allow time for pending master requests to run */
1156 adapter->hw.mac.ops.reset_hw(&adapter->hw);
1157 wr32(E1000_WUC, 0);
1158
1159 if (adapter->hw.mac.ops.init_hw(&adapter->hw))
1160 dev_err(&adapter->pdev->dev, "Hardware Error\n");
1161
1162 igb_update_mng_vlan(adapter);
1163
1164 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1165 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1166
1167 igb_reset_adaptive(&adapter->hw);
f5f4cf08 1168 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 1169}
1170
2e5c6922
SH		 1171static const struct net_device_ops igb_netdev_ops = {
1172 .ndo_open = igb_open,
1173 .ndo_stop = igb_close,
00829823 1174 .ndo_start_xmit = igb_xmit_frame_adv,
2e5c6922 1175 .ndo_get_stats = igb_get_stats,
ff41f8dc
AD		 1176 .ndo_set_rx_mode = igb_set_rx_mode,
1177 .ndo_set_multicast_list = igb_set_rx_mode,
2e5c6922
SH		 1178 .ndo_set_mac_address = igb_set_mac,
1179 .ndo_change_mtu = igb_change_mtu,
1180 .ndo_do_ioctl = igb_ioctl,
1181 .ndo_tx_timeout = igb_tx_timeout,
1182 .ndo_validate_addr = eth_validate_addr,
1183 .ndo_vlan_rx_register = igb_vlan_rx_register,
1184 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1185 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
1186#ifdef CONFIG_NET_POLL_CONTROLLER
1187 .ndo_poll_controller = igb_netpoll,
1188#endif
1189};
1190
9d5c8243
AK		 1191/**
1192 * igb_probe - Device Initialization Routine
1193 * @pdev: PCI device information struct
1194 * @ent: entry in igb_pci_tbl
1195 *
1196 * Returns 0 on success, negative on failure
1197 *
1198 * igb_probe initializes an adapter identified by a pci_dev structure.
1199 * The OS initialization, configuring of the adapter private structure,
1200 * and a hardware reset occur.
1201 **/
1202static int __devinit igb_probe(struct pci_dev *pdev,
1203 const struct pci_device_id *ent)
1204{
1205 struct net_device *netdev;
1206 struct igb_adapter *adapter;
1207 struct e1000_hw *hw;
1208 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1209 unsigned long mmio_start, mmio_len;
2d6a5e95 1210 int err, pci_using_dac;
682337fe 1211 u16 eeprom_data = 0;
9d5c8243
AK		 1212 u16 eeprom_apme_mask = IGB_EEPROM_APME;
1213 u32 part_num;
1214
aed5dec3 1215 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 1216 if (err)
1217 return err;
1218
1219 pci_using_dac = 0;
6a35528a 1220 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
9d5c8243 1221 if (!err) {
6a35528a 1222 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
9d5c8243
AK		 1223 if (!err)
1224 pci_using_dac = 1;
1225 } else {
284901a9 1226 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
9d5c8243 1227 if (err) {
284901a9 1228 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
9d5c8243
AK		 1229 if (err) {
1230 dev_err(&pdev->dev, "No usable DMA "
1231 "configuration, aborting\n");
1232 goto err_dma;
1233 }
1234 }
1235 }
1236
aed5dec3
AD		 1237 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1238 IORESOURCE_MEM),
1239 igb_driver_name);
9d5c8243
AK		 1240 if (err)
1241 goto err_pci_reg;
1242
ea943d41
JK		 1243 err = pci_enable_pcie_error_reporting(pdev);
1244 if (err) {
1245 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
1246 "0x%x\n", err);
1247 /* non-fatal, continue */
1248 }
40a914fa 1249
9d5c8243 1250 pci_set_master(pdev);
c682fc23 1251 pci_save_state(pdev);
9d5c8243
AK		 1252
1253 err = -ENOMEM;
1bfaf07b
AD		 1254 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1255 IGB_ABS_MAX_TX_QUEUES);
9d5c8243
AK		 1256 if (!netdev)
1257 goto err_alloc_etherdev;
1258
1259 SET_NETDEV_DEV(netdev, &pdev->dev);
1260
1261 pci_set_drvdata(pdev, netdev);
1262 adapter = netdev_priv(netdev);
1263 adapter->netdev = netdev;
1264 adapter->pdev = pdev;
1265 hw = &adapter->hw;
1266 hw->back = adapter;
1267 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
1268
1269 mmio_start = pci_resource_start(pdev, 0);
1270 mmio_len = pci_resource_len(pdev, 0);
1271
1272 err = -EIO;
28b0759c
AD		 1273 hw->hw_addr = ioremap(mmio_start, mmio_len);
1274 if (!hw->hw_addr)
9d5c8243
AK		 1275 goto err_ioremap;
1276
2e5c6922 1277 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 1278 igb_set_ethtool_ops(netdev);
9d5c8243 1279 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 1280
1281 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1282
1283 netdev->mem_start = mmio_start;
1284 netdev->mem_end = mmio_start + mmio_len;
1285
9d5c8243
AK		 1286 /* PCI config space info */
1287 hw->vendor_id = pdev->vendor;
1288 hw->device_id = pdev->device;
1289 hw->revision_id = pdev->revision;
1290 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1291 hw->subsystem_device_id = pdev->subsystem_device;
1292
1293 /* setup the private structure */
1294 hw->back = adapter;
1295 /* Copy the default MAC, PHY and NVM function pointers */
1296 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1297 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1298 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1299 /* Initialize skew-specific constants */
1300 err = ei->get_invariants(hw);
1301 if (err)
450c87c8 1302 goto err_sw_init;
9d5c8243 1303
2a3abf6d
AD		 1304#ifdef CONFIG_PCI_IOV
1305 /* since iov functionality isn't critical to base device function we
1306 * can accept failure. If it fails we don't allow iov to be enabled */
1307 if (hw->mac.type == e1000_82576) {
1308 /* 82576 supports a maximum of 7 VFs in addition to the PF */
1309 unsigned int num_vfs = (max_vfs > 7) ? 7 : max_vfs;
1310 int i;
1311 unsigned char mac_addr[ETH_ALEN];
1312
9ca046d5 1313 if (num_vfs) {
2a3abf6d
AD		 1314 adapter->vf_data = kcalloc(num_vfs,
1315 sizeof(struct vf_data_storage),
1316 GFP_KERNEL);
9ca046d5
AD		 1317 if (!adapter->vf_data) {
1318 dev_err(&pdev->dev,
1319 "Could not allocate VF private data - "
1320 "IOV enable failed\n");
2a3abf6d 1321 } else {
9ca046d5
AD		 1322 err = pci_enable_sriov(pdev, num_vfs);
1323 if (!err) {
1324 adapter->vfs_allocated_count = num_vfs;
1325 dev_info(&pdev->dev,
1326 "%d vfs allocated\n",
1327 num_vfs);
1328 for (i = 0;
1329 i < adapter->vfs_allocated_count;
1330 i++) {
1331 random_ether_addr(mac_addr);
1332 igb_set_vf_mac(adapter, i,
1333 mac_addr);
1334 }
1335 } else {
1336 kfree(adapter->vf_data);
1337 adapter->vf_data = NULL;
1338 }
2a3abf6d
AD		 1339 }
1340 }
1341 }
1342
1343#endif
450c87c8 1344 /* setup the private structure */
9d5c8243
AK		 1345 err = igb_sw_init(adapter);
1346 if (err)
1347 goto err_sw_init;
1348
1349 igb_get_bus_info_pcie(hw);
1350
7dfc16fa
AD		 1351 /* set flags */
1352 switch (hw->mac.type) {
7dfc16fa 1353 case e1000_82575:
7dfc16fa
AD		 1354 adapter->flags |= IGB_FLAG_NEED_CTX_IDX;
1355 break;
bbd98fe4 1356 case e1000_82576:
7dfc16fa
AD		 1357 default:
1358 break;
1359 }
1360
9d5c8243
AK		 1361 hw->phy.autoneg_wait_to_complete = false;
1362 hw->mac.adaptive_ifs = true;
1363
1364 /* Copper options */
1365 if (hw->phy.media_type == e1000_media_type_copper) {
1366 hw->phy.mdix = AUTO_ALL_MODES;
1367 hw->phy.disable_polarity_correction = false;
1368 hw->phy.ms_type = e1000_ms_hw_default;
1369 }
1370
1371 if (igb_check_reset_block(hw))
1372 dev_info(&pdev->dev,
1373 "PHY reset is blocked due to SOL/IDER session.\n");
1374
1375 netdev->features = NETIF_F_SG |
7d8eb29e 1376 NETIF_F_IP_CSUM |
9d5c8243
AK		 1377 NETIF_F_HW_VLAN_TX |
1378 NETIF_F_HW_VLAN_RX |
1379 NETIF_F_HW_VLAN_FILTER;
1380
7d8eb29e 1381 netdev->features |= NETIF_F_IPV6_CSUM;
9d5c8243 1382 netdev->features |= NETIF_F_TSO;
9d5c8243 1383 netdev->features |= NETIF_F_TSO6;
48f29ffc 1384
5c0999b7 1385 netdev->features |= NETIF_F_GRO;
d3352520 1386
48f29ffc
JK		 1387 netdev->vlan_features |= NETIF_F_TSO;
1388 netdev->vlan_features |= NETIF_F_TSO6;
7d8eb29e 1389 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 1390 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
48f29ffc
JK		 1391 netdev->vlan_features |= NETIF_F_SG;
1392
9d5c8243
AK		 1393 if (pci_using_dac)
1394 netdev->features |= NETIF_F_HIGHDMA;
1395
b9473560
JB		 1396 if (adapter->hw.mac.type == e1000_82576)
1397 netdev->features |= NETIF_F_SCTP_CSUM;
1398
9d5c8243
AK		 1399 adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1400
1401 /* before reading the NVM, reset the controller to put the device in a
1402 * known good starting state */
1403 hw->mac.ops.reset_hw(hw);
1404
1405 /* make sure the NVM is good */
1406 if (igb_validate_nvm_checksum(hw) < 0) {
1407 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1408 err = -EIO;
1409 goto err_eeprom;
1410 }
1411
1412 /* copy the MAC address out of the NVM */
1413 if (hw->mac.ops.read_mac_addr(hw))
1414 dev_err(&pdev->dev, "NVM Read Error\n");
1415
1416 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1417 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1418
1419 if (!is_valid_ether_addr(netdev->perm_addr)) {
1420 dev_err(&pdev->dev, "Invalid MAC Address\n");
1421 err = -EIO;
1422 goto err_eeprom;
1423 }
1424
0e340485
AD		 1425 setup_timer(&adapter->watchdog_timer, &igb_watchdog,
1426 (unsigned long) adapter);
1427 setup_timer(&adapter->phy_info_timer, &igb_update_phy_info,
1428 (unsigned long) adapter);
9d5c8243
AK		 1429
1430 INIT_WORK(&adapter->reset_task, igb_reset_task);
1431 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1432
450c87c8 1433 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 1434 adapter->fc_autoneg = true;
1435 hw->mac.autoneg = true;
1436 hw->phy.autoneg_advertised = 0x2f;
1437
0cce119a
AD		 1438 hw->fc.requested_mode = e1000_fc_default;
1439 hw->fc.current_mode = e1000_fc_default;
9d5c8243 1440
cbd347ad 1441 adapter->itr_setting = IGB_DEFAULT_ITR;
9d5c8243
AK		 1442 adapter->itr = IGB_START_ITR;
1443
1444 igb_validate_mdi_setting(hw);
1445
9d5c8243
AK		 1446 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1447 * enable the ACPI Magic Packet filter
1448 */
1449
a2cf8b6c 1450 if (hw->bus.func == 0)
312c75ae 1451 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
a2cf8b6c
AD		 1452 else if (hw->bus.func == 1)
1453 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243
AK		 1454
1455 if (eeprom_data & eeprom_apme_mask)
1456 adapter->eeprom_wol |= E1000_WUFC_MAG;
1457
1458 /* now that we have the eeprom settings, apply the special cases where
1459 * the eeprom may be wrong or the board simply won't support wake on
1460 * lan on a particular port */
1461 switch (pdev->device) {
1462 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1463 adapter->eeprom_wol = 0;
1464 break;
1465 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 1466 case E1000_DEV_ID_82576_FIBER:
1467 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 1468 /* Wake events only supported on port A for dual fiber
1469 * regardless of eeprom setting */
1470 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1471 adapter->eeprom_wol = 0;
1472 break;
c8ea5ea9
AD		 1473 case E1000_DEV_ID_82576_QUAD_COPPER:
1474 /* if quad port adapter, disable WoL on all but port A */
1475 if (global_quad_port_a != 0)
1476 adapter->eeprom_wol = 0;
1477 else
1478 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
1479 /* Reset for multiple quad port adapters */
1480 if (++global_quad_port_a == 4)
1481 global_quad_port_a = 0;
1482 break;
9d5c8243
AK		 1483 }
1484
1485 /* initialize the wol settings based on the eeprom settings */
1486 adapter->wol = adapter->eeprom_wol;
e1b86d84 1487 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
9d5c8243
AK		 1488
1489 /* reset the hardware with the new settings */
1490 igb_reset(adapter);
1491
1492 /* let the f/w know that the h/w is now under the control of the
1493 * driver. */
1494 igb_get_hw_control(adapter);
1495
9d5c8243
AK		 1496 strcpy(netdev->name, "eth%d");
1497 err = register_netdev(netdev);
1498 if (err)
1499 goto err_register;
1500
b168dfc5
JB		 1501 /* carrier off reporting is important to ethtool even BEFORE open */
1502 netif_carrier_off(netdev);
1503
421e02f0 1504#ifdef CONFIG_IGB_DCA
bbd98fe4 1505 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 1506 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 1507 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 1508 igb_setup_dca(adapter);
1509 }
1510#endif
1511
38c845c7
PO		 1512 /*
1513 * Initialize hardware timer: we keep it running just in case
1514 * that some program needs it later on.
1515 */
1516 memset(&adapter->cycles, 0, sizeof(adapter->cycles));
1517 adapter->cycles.read = igb_read_clock;
1518 adapter->cycles.mask = CLOCKSOURCE_MASK(64);
1519 adapter->cycles.mult = 1;
1520 adapter->cycles.shift = IGB_TSYNC_SHIFT;
1521 wr32(E1000_TIMINCA,
1522 (1<<24) |
1523 IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS * IGB_TSYNC_SCALE);
1524#if 0
1525 /*
1526 * Avoid rollover while we initialize by resetting the time counter.
1527 */
1528 wr32(E1000_SYSTIML, 0x00000000);
1529 wr32(E1000_SYSTIMH, 0x00000000);
1530#else
1531 /*
1532 * Set registers so that rollover occurs soon to test this.
1533 */
1534 wr32(E1000_SYSTIML, 0x00000000);
1535 wr32(E1000_SYSTIMH, 0xFF800000);
1536#endif
1537 wrfl();
1538 timecounter_init(&adapter->clock,
1539 &adapter->cycles,
1540 ktime_to_ns(ktime_get_real()));
1541
33af6bcc
PO		 1542 /*
1543 * Synchronize our NIC clock against system wall clock. NIC
1544 * time stamp reading requires ~3us per sample, each sample
1545 * was pretty stable even under load => only require 10
1546 * samples for each offset comparison.
1547 */
1548 memset(&adapter->compare, 0, sizeof(adapter->compare));
1549 adapter->compare.source = &adapter->clock;
1550 adapter->compare.target = ktime_get_real;
1551 adapter->compare.num_samples = 10;
1552 timecompare_update(&adapter->compare, 0);
1553
38c845c7
PO		 1554#ifdef DEBUG
1555 {
1556 char buffer[160];
1557 printk(KERN_DEBUG
1558 "igb: %s: hw %p initialized timer\n",
1559 igb_get_time_str(adapter, buffer),
1560 &adapter->hw);
1561 }
1562#endif
1563
9d5c8243
AK		 1564 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1565 /* print bus type/speed/width info */
7c510e4b 1566 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
9d5c8243
AK		 1567 netdev->name,
1568 ((hw->bus.speed == e1000_bus_speed_2500)
1569 ? "2.5Gb/s" : "unknown"),
59c3de89
AD		 1570 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
1571 (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :
1572 (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" :
1573 "unknown"),
7c510e4b 1574 netdev->dev_addr);
9d5c8243
AK		 1575
1576 igb_read_part_num(hw, &part_num);
1577 dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1578 (part_num >> 8), (part_num & 0xff));
1579
1580 dev_info(&pdev->dev,
1581 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1582 adapter->msix_entries ? "MSI-X" :
7dfc16fa 1583 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243
AK		 1584 adapter->num_rx_queues, adapter->num_tx_queues);
1585
9d5c8243
AK		 1586 return 0;
1587
1588err_register:
1589 igb_release_hw_control(adapter);
1590err_eeprom:
1591 if (!igb_check_reset_block(hw))
f5f4cf08 1592 igb_reset_phy(hw);
9d5c8243
AK		 1593
1594 if (hw->flash_address)
1595 iounmap(hw->flash_address);
1596
a88f10ec 1597 igb_free_queues(adapter);
9d5c8243 1598err_sw_init:
9d5c8243
AK		 1599 iounmap(hw->hw_addr);
1600err_ioremap:
1601 free_netdev(netdev);
1602err_alloc_etherdev:
aed5dec3
AD		 1603 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1604 IORESOURCE_MEM));
9d5c8243
AK		 1605err_pci_reg:
1606err_dma:
1607 pci_disable_device(pdev);
1608 return err;
1609}
1610
1611/**
1612 * igb_remove - Device Removal Routine
1613 * @pdev: PCI device information struct
1614 *
1615 * igb_remove is called by the PCI subsystem to alert the driver
1616 * that it should release a PCI device. The could be caused by a
1617 * Hot-Plug event, or because the driver is going to be removed from
1618 * memory.
1619 **/
1620static void __devexit igb_remove(struct pci_dev *pdev)
1621{
1622 struct net_device *netdev = pci_get_drvdata(pdev);
1623 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 1624 struct e1000_hw *hw = &adapter->hw;
ea943d41 1625 int err;
9d5c8243
AK		 1626
1627 /* flush_scheduled work may reschedule our watchdog task, so
1628 * explicitly disable watchdog tasks from being rescheduled */
1629 set_bit(__IGB_DOWN, &adapter->state);
1630 del_timer_sync(&adapter->watchdog_timer);
1631 del_timer_sync(&adapter->phy_info_timer);
1632
1633 flush_scheduled_work();
1634
421e02f0 1635#ifdef CONFIG_IGB_DCA
7dfc16fa 1636 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 1637 dev_info(&pdev->dev, "DCA disabled\n");
1638 dca_remove_requester(&pdev->dev);
7dfc16fa 1639 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 1640 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 1641 }
1642#endif
1643
9d5c8243
AK		 1644 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1645 * would have already happened in close and is redundant. */
1646 igb_release_hw_control(adapter);
1647
1648 unregister_netdev(netdev);
1649
f5f4cf08
AD		 1650 if (!igb_check_reset_block(&adapter->hw))
1651 igb_reset_phy(&adapter->hw);
9d5c8243 1652
9d5c8243
AK		 1653 igb_reset_interrupt_capability(adapter);
1654
a88f10ec 1655 igb_free_queues(adapter);
9d5c8243 1656
37680117
AD		 1657#ifdef CONFIG_PCI_IOV
1658 /* reclaim resources allocated to VFs */
1659 if (adapter->vf_data) {
1660 /* disable iov and allow time for transactions to clear */
1661 pci_disable_sriov(pdev);
1662 msleep(500);
1663
1664 kfree(adapter->vf_data);
1665 adapter->vf_data = NULL;
1666 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1667 msleep(100);
1668 dev_info(&pdev->dev, "IOV Disabled\n");
1669 }
1670#endif
28b0759c
AD		 1671 iounmap(hw->hw_addr);
1672 if (hw->flash_address)
1673 iounmap(hw->flash_address);
aed5dec3
AD		 1674 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1675 IORESOURCE_MEM));
9d5c8243
AK		 1676
1677 free_netdev(netdev);
1678
ea943d41
JK		 1679 err = pci_disable_pcie_error_reporting(pdev);
1680 if (err)
1681 dev_err(&pdev->dev,
1682 "pci_disable_pcie_error_reporting failed 0x%x\n", err);
40a914fa 1683
9d5c8243
AK		 1684 pci_disable_device(pdev);
1685}
1686
1687/**
1688 * igb_sw_init - Initialize general software structures (struct igb_adapter)
1689 * @adapter: board private structure to initialize
1690 *
1691 * igb_sw_init initializes the Adapter private data structure.
1692 * Fields are initialized based on PCI device information and
1693 * OS network device settings (MTU size).
1694 **/
1695static int __devinit igb_sw_init(struct igb_adapter *adapter)
1696{
1697 struct e1000_hw *hw = &adapter->hw;
1698 struct net_device *netdev = adapter->netdev;
1699 struct pci_dev *pdev = adapter->pdev;
1700
1701 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1702
68fd9910
AD		 1703 adapter->tx_ring_count = IGB_DEFAULT_TXD;
1704 adapter->rx_ring_count = IGB_DEFAULT_RXD;
9d5c8243
AK		 1705 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1706 adapter->rx_ps_hdr_size = 0; /* disable packet split */
1707 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1708 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1709
661086df
PWJ		 1710 /* This call may decrease the number of queues depending on
1711 * interrupt mode. */
9d5c8243
AK		 1712 igb_set_interrupt_capability(adapter);
1713
1714 if (igb_alloc_queues(adapter)) {
1715 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1716 return -ENOMEM;
1717 }
1718
1719 /* Explicitly disable IRQ since the NIC can be in any state. */
1720 igb_irq_disable(adapter);
1721
1722 set_bit(__IGB_DOWN, &adapter->state);
1723 return 0;
1724}
1725
1726/**
1727 * igb_open - Called when a network interface is made active
1728 * @netdev: network interface device structure
1729 *
1730 * Returns 0 on success, negative value on failure
1731 *
1732 * The open entry point is called when a network interface is made
1733 * active by the system (IFF_UP). At this point all resources needed
1734 * for transmit and receive operations are allocated, the interrupt
1735 * handler is registered with the OS, the watchdog timer is started,
1736 * and the stack is notified that the interface is ready.
1737 **/
1738static int igb_open(struct net_device *netdev)
1739{
1740 struct igb_adapter *adapter = netdev_priv(netdev);
1741 struct e1000_hw *hw = &adapter->hw;
1742 int err;
1743 int i;
1744
1745 /* disallow open during test */
1746 if (test_bit(__IGB_TESTING, &adapter->state))
1747 return -EBUSY;
1748
b168dfc5
JB		 1749 netif_carrier_off(netdev);
1750
9d5c8243
AK		 1751 /* allocate transmit descriptors */
1752 err = igb_setup_all_tx_resources(adapter);
1753 if (err)
1754 goto err_setup_tx;
1755
1756 /* allocate receive descriptors */
1757 err = igb_setup_all_rx_resources(adapter);
1758 if (err)
1759 goto err_setup_rx;
1760
1761 /* e1000_power_up_phy(adapter); */
1762
1763 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1764 if ((adapter->hw.mng_cookie.status &
1765 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1766 igb_update_mng_vlan(adapter);
1767
1768 /* before we allocate an interrupt, we must be ready to handle it.
1769 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1770 * as soon as we call pci_request_irq, so we have to setup our
1771 * clean_rx handler before we do so. */
1772 igb_configure(adapter);
1773
4ae196df 1774 igb_vmm_control(adapter);
e1739522
AD		 1775 igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
1776 igb_set_vmolr(hw, adapter->vfs_allocated_count);
1777
9d5c8243
AK		 1778 err = igb_request_irq(adapter);
1779 if (err)
1780 goto err_req_irq;
1781
1782 /* From here on the code is the same as igb_up() */
1783 clear_bit(__IGB_DOWN, &adapter->state);
1784
844290e5
PW		 1785 for (i = 0; i < adapter->num_rx_queues; i++)
1786 napi_enable(&adapter->rx_ring[i].napi);
9d5c8243
AK		 1787
1788 /* Clear any pending interrupts. */
1789 rd32(E1000_ICR);
844290e5
PW		 1790
1791 igb_irq_enable(adapter);
1792
d55b53ff
JK		 1793 netif_tx_start_all_queues(netdev);
1794
9d5c8243
AK		 1795 /* Fire a link status change interrupt to start the watchdog. */
1796 wr32(E1000_ICS, E1000_ICS_LSC);
1797
1798 return 0;
1799
1800err_req_irq:
1801 igb_release_hw_control(adapter);
1802 /* e1000_power_down_phy(adapter); */
1803 igb_free_all_rx_resources(adapter);
1804err_setup_rx:
1805 igb_free_all_tx_resources(adapter);
1806err_setup_tx:
1807 igb_reset(adapter);
1808
1809 return err;
1810}
1811
1812/**
1813 * igb_close - Disables a network interface
1814 * @netdev: network interface device structure
1815 *
1816 * Returns 0, this is not allowed to fail
1817 *
1818 * The close entry point is called when an interface is de-activated
1819 * by the OS. The hardware is still under the driver's control, but
1820 * needs to be disabled. A global MAC reset is issued to stop the
1821 * hardware, and all transmit and receive resources are freed.
1822 **/
1823static int igb_close(struct net_device *netdev)
1824{
1825 struct igb_adapter *adapter = netdev_priv(netdev);
1826
1827 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1828 igb_down(adapter);
1829
1830 igb_free_irq(adapter);
1831
1832 igb_free_all_tx_resources(adapter);
1833 igb_free_all_rx_resources(adapter);
1834
1835 /* kill manageability vlan ID if supported, but not if a vlan with
1836 * the same ID is registered on the host OS (let 8021q kill it) */
1837 if ((adapter->hw.mng_cookie.status &
1838 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1839 !(adapter->vlgrp &&
1840 vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1841 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1842
1843 return 0;
1844}
1845
1846/**
1847 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
1848 * @adapter: board private structure
1849 * @tx_ring: tx descriptor ring (for a specific queue) to setup
1850 *
1851 * Return 0 on success, negative on failure
1852 **/
9d5c8243
AK		 1853int igb_setup_tx_resources(struct igb_adapter *adapter,
1854 struct igb_ring *tx_ring)
1855{
1856 struct pci_dev *pdev = adapter->pdev;
1857 int size;
1858
1859 size = sizeof(struct igb_buffer) * tx_ring->count;
1860 tx_ring->buffer_info = vmalloc(size);
1861 if (!tx_ring->buffer_info)
1862 goto err;
1863 memset(tx_ring->buffer_info, 0, size);
1864
1865 /* round up to nearest 4K */
85e8d004 1866 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 1867 tx_ring->size = ALIGN(tx_ring->size, 4096);
1868
1869 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1870 &tx_ring->dma);
1871
1872 if (!tx_ring->desc)
1873 goto err;
1874
1875 tx_ring->adapter = adapter;
1876 tx_ring->next_to_use = 0;
1877 tx_ring->next_to_clean = 0;
9d5c8243
AK		 1878 return 0;
1879
1880err:
1881 vfree(tx_ring->buffer_info);
1882 dev_err(&adapter->pdev->dev,
1883 "Unable to allocate memory for the transmit descriptor ring\n");
1884 return -ENOMEM;
1885}
1886
1887/**
1888 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1889 * (Descriptors) for all queues
1890 * @adapter: board private structure
1891 *
1892 * Return 0 on success, negative on failure
1893 **/
1894static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1895{
1896 int i, err = 0;
661086df 1897 int r_idx;
9d5c8243
AK		 1898
1899 for (i = 0; i < adapter->num_tx_queues; i++) {
1900 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1901 if (err) {
1902 dev_err(&adapter->pdev->dev,
1903 "Allocation for Tx Queue %u failed\n", i);
1904 for (i--; i >= 0; i--)
3b644cf6 1905 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 1906 break;
1907 }
1908 }
1909
661086df
PWJ		 1910 for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
1911 r_idx = i % adapter->num_tx_queues;
1912 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
eebbbdba 1913 }
9d5c8243
AK		 1914 return err;
1915}
1916
1917/**
1918 * igb_configure_tx - Configure transmit Unit after Reset
1919 * @adapter: board private structure
1920 *
1921 * Configure the Tx unit of the MAC after a reset.
1922 **/
1923static void igb_configure_tx(struct igb_adapter *adapter)
1924{
0e014cb1 1925 u64 tdba;
9d5c8243
AK		 1926 struct e1000_hw *hw = &adapter->hw;
1927 u32 tctl;
1928 u32 txdctl, txctrl;
26bc19ec 1929 int i, j;
9d5c8243
AK		 1930
1931 for (i = 0; i < adapter->num_tx_queues; i++) {
73cd78f1 1932 struct igb_ring *ring = &adapter->tx_ring[i];
26bc19ec
AD		 1933 j = ring->reg_idx;
1934 wr32(E1000_TDLEN(j),
85e8d004 1935 ring->count * sizeof(union e1000_adv_tx_desc));
9d5c8243 1936 tdba = ring->dma;
26bc19ec 1937 wr32(E1000_TDBAL(j),
73cd78f1 1938 tdba & 0x00000000ffffffffULL);
26bc19ec 1939 wr32(E1000_TDBAH(j), tdba >> 32);
9d5c8243 1940
26bc19ec
AD		 1941 ring->head = E1000_TDH(j);
1942 ring->tail = E1000_TDT(j);
9d5c8243
AK		 1943 writel(0, hw->hw_addr + ring->tail);
1944 writel(0, hw->hw_addr + ring->head);
26bc19ec 1945 txdctl = rd32(E1000_TXDCTL(j));
9d5c8243 1946 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
26bc19ec 1947 wr32(E1000_TXDCTL(j), txdctl);
9d5c8243
AK		 1948
1949 /* Turn off Relaxed Ordering on head write-backs. The
1950 * writebacks MUST be delivered in order or it will
1951 * completely screw up our bookeeping.
1952 */
26bc19ec 1953 txctrl = rd32(E1000_DCA_TXCTRL(j));
9d5c8243 1954 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
26bc19ec 1955 wr32(E1000_DCA_TXCTRL(j), txctrl);
9d5c8243
AK		 1956 }
1957
e1739522
AD		 1958 /* disable queue 0 to prevent tail bump w/o re-configuration */
1959 if (adapter->vfs_allocated_count)
1960 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 1961
1962 /* Program the Transmit Control Register */
9d5c8243
AK		 1963 tctl = rd32(E1000_TCTL);
1964 tctl &= ~E1000_TCTL_CT;
1965 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1966 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1967
1968 igb_config_collision_dist(hw);
1969
1970 /* Setup Transmit Descriptor Settings for eop descriptor */
1971 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
1972
1973 /* Enable transmits */
1974 tctl |= E1000_TCTL_EN;
1975
1976 wr32(E1000_TCTL, tctl);
1977}
1978
1979/**
1980 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
1981 * @adapter: board private structure
1982 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1983 *
1984 * Returns 0 on success, negative on failure
1985 **/
9d5c8243
AK		 1986int igb_setup_rx_resources(struct igb_adapter *adapter,
1987 struct igb_ring *rx_ring)
1988{
1989 struct pci_dev *pdev = adapter->pdev;
1990 int size, desc_len;
1991
1992 size = sizeof(struct igb_buffer) * rx_ring->count;
1993 rx_ring->buffer_info = vmalloc(size);
1994 if (!rx_ring->buffer_info)
1995 goto err;
1996 memset(rx_ring->buffer_info, 0, size);
1997
1998 desc_len = sizeof(union e1000_adv_rx_desc);
1999
2000 /* Round up to nearest 4K */
2001 rx_ring->size = rx_ring->count * desc_len;
2002 rx_ring->size = ALIGN(rx_ring->size, 4096);
2003
2004 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
2005 &rx_ring->dma);
2006
2007 if (!rx_ring->desc)
2008 goto err;
2009
2010 rx_ring->next_to_clean = 0;
2011 rx_ring->next_to_use = 0;
9d5c8243
AK		 2012
2013 rx_ring->adapter = adapter;
9d5c8243
AK		 2014
2015 return 0;
2016
2017err:
2018 vfree(rx_ring->buffer_info);
2019 dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
2020 "the receive descriptor ring\n");
2021 return -ENOMEM;
2022}
2023
2024/**
2025 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
2026 * (Descriptors) for all queues
2027 * @adapter: board private structure
2028 *
2029 * Return 0 on success, negative on failure
2030 **/
2031static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
2032{
2033 int i, err = 0;
2034
2035 for (i = 0; i < adapter->num_rx_queues; i++) {
2036 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
2037 if (err) {
2038 dev_err(&adapter->pdev->dev,
2039 "Allocation for Rx Queue %u failed\n", i);
2040 for (i--; i >= 0; i--)
3b644cf6 2041 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 2042 break;
2043 }
2044 }
2045
2046 return err;
2047}
2048
2049/**
2050 * igb_setup_rctl - configure the receive control registers
2051 * @adapter: Board private structure
2052 **/
2053static void igb_setup_rctl(struct igb_adapter *adapter)
2054{
2055 struct e1000_hw *hw = &adapter->hw;
2056 u32 rctl;
2057 u32 srrctl = 0;
77a22941 2058 int i;
9d5c8243
AK		 2059
2060 rctl = rd32(E1000_RCTL);
2061
2062 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 2063 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 2064
69d728ba 2065 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 2066 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 2067
87cb7e8c
AK		 2068 /*
2069 * enable stripping of CRC. It's unlikely this will break BMC
2070 * redirection as it did with e1000. Newer features require
2071 * that the HW strips the CRC.
73cd78f1 2072 */
87cb7e8c 2073 rctl |= E1000_RCTL_SECRC;
9d5c8243 2074
9b07f3d3 2075 /*
ec54d7d6 2076 * disable store bad packets and clear size bits.
9b07f3d3 2077 */
ec54d7d6 2078 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 2079
ec54d7d6 2080 /* enable LPE when to prevent packets larger than max_frame_size */
9b07f3d3 2081 rctl |= E1000_RCTL_LPE;
b4557be2
AD		 2082
2083 /* Setup buffer sizes */
2084 switch (adapter->rx_buffer_len) {
2085 case IGB_RXBUFFER_256:
2086 rctl |= E1000_RCTL_SZ_256;
2087 break;
2088 case IGB_RXBUFFER_512:
2089 rctl |= E1000_RCTL_SZ_512;
2090 break;
2091 default:
2092 srrctl = ALIGN(adapter->rx_buffer_len, 1024)
2093 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2094 break;
9d5c8243
AK		 2095 }
2096
2097 /* 82575 and greater support packet-split where the protocol
2098 * header is placed in skb->data and the packet data is
2099 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
2100 * In the case of a non-split, skb->data is linearly filled,
2101 * followed by the page buffers. Therefore, skb->data is
2102 * sized to hold the largest protocol header.
2103 */
2104 /* allocations using alloc_page take too long for regular MTU
2105 * so only enable packet split for jumbo frames */
ec54d7d6 2106 if (adapter->netdev->mtu > ETH_DATA_LEN) {
9d5c8243 2107 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
bf36c1a0 2108 srrctl |= adapter->rx_ps_hdr_size <<
9d5c8243 2109 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
9d5c8243
AK		 2110 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2111 } else {
2112 adapter->rx_ps_hdr_size = 0;
2113 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2114 }
2115
e1739522
AD		 2116 /* Attention!!! For SR-IOV PF driver operations you must enable
2117 * queue drop for all VF and PF queues to prevent head of line blocking
2118 * if an un-trusted VF does not provide descriptors to hardware.
2119 */
2120 if (adapter->vfs_allocated_count) {
2121 u32 vmolr;
2122
e1739522
AD		 2123 /* set all queue drop enable bits */
2124 wr32(E1000_QDE, ALL_QUEUES);
2125 srrctl |= E1000_SRRCTL_DROP_EN;
2126
2127 /* disable queue 0 to prevent tail write w/o re-config */
2128 wr32(E1000_RXDCTL(0), 0);
2129
77a22941 2130 vmolr = rd32(E1000_VMOLR(adapter->vfs_allocated_count));
e1739522
AD		 2131 if (rctl & E1000_RCTL_LPE)
2132 vmolr |= E1000_VMOLR_LPE;
77a22941 2133 if (adapter->num_rx_queues > 1)
e1739522 2134 vmolr |= E1000_VMOLR_RSSE;
77a22941 2135 wr32(E1000_VMOLR(adapter->vfs_allocated_count), vmolr);
e1739522
AD		 2136 }
2137
26bc19ec 2138 for (i = 0; i < adapter->num_rx_queues; i++) {
77a22941 2139 int j = adapter->rx_ring[i].reg_idx;
26bc19ec
AD		 2140 wr32(E1000_SRRCTL(j), srrctl);
2141 }
9d5c8243
AK		 2142
2143 wr32(E1000_RCTL, rctl);
2144}
2145
e1739522
AD		 2146/**
2147 * igb_rlpml_set - set maximum receive packet size
2148 * @adapter: board private structure
2149 *
2150 * Configure maximum receivable packet size.
2151 **/
2152static void igb_rlpml_set(struct igb_adapter *adapter)
2153{
2154 u32 max_frame_size = adapter->max_frame_size;
2155 struct e1000_hw *hw = &adapter->hw;
2156 u16 pf_id = adapter->vfs_allocated_count;
2157
2158 if (adapter->vlgrp)
2159 max_frame_size += VLAN_TAG_SIZE;
2160
2161 /* if vfs are enabled we set RLPML to the largest possible request
2162 * size and set the VMOLR RLPML to the size we need */
2163 if (pf_id) {
2164 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
2165 max_frame_size = MAX_STD_JUMBO_FRAME_SIZE + VLAN_TAG_SIZE;
2166 }
2167
2168 wr32(E1000_RLPML, max_frame_size);
2169}
2170
2171/**
2172 * igb_configure_vt_default_pool - Configure VT default pool
2173 * @adapter: board private structure
2174 *
2175 * Configure the default pool
2176 **/
2177static void igb_configure_vt_default_pool(struct igb_adapter *adapter)
2178{
2179 struct e1000_hw *hw = &adapter->hw;
2180 u16 pf_id = adapter->vfs_allocated_count;
2181 u32 vtctl;
2182
2183 /* not in sr-iov mode - do nothing */
2184 if (!pf_id)
2185 return;
2186
2187 vtctl = rd32(E1000_VT_CTL);
2188 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
2189 E1000_VT_CTL_DISABLE_DEF_POOL);
2190 vtctl |= pf_id << E1000_VT_CTL_DEFAULT_POOL_SHIFT;
2191 wr32(E1000_VT_CTL, vtctl);
2192}
2193
9d5c8243
AK		 2194/**
2195 * igb_configure_rx - Configure receive Unit after Reset
2196 * @adapter: board private structure
2197 *
2198 * Configure the Rx unit of the MAC after a reset.
2199 **/
2200static void igb_configure_rx(struct igb_adapter *adapter)
2201{
2202 u64 rdba;
2203 struct e1000_hw *hw = &adapter->hw;
2204 u32 rctl, rxcsum;
2205 u32 rxdctl;
9107584e 2206 int i;
9d5c8243
AK		 2207
2208 /* disable receives while setting up the descriptors */
2209 rctl = rd32(E1000_RCTL);
2210 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
2211 wrfl();
2212 mdelay(10);
2213
2214 if (adapter->itr_setting > 3)
6eb5a7f1 2215 wr32(E1000_ITR, adapter->itr);
9d5c8243
AK		 2216
2217 /* Setup the HW Rx Head and Tail Descriptor Pointers and
2218 * the Base and Length of the Rx Descriptor Ring */
2219 for (i = 0; i < adapter->num_rx_queues; i++) {
73cd78f1 2220 struct igb_ring *ring = &adapter->rx_ring[i];
9107584e 2221 int j = ring->reg_idx;
9d5c8243 2222 rdba = ring->dma;
26bc19ec 2223 wr32(E1000_RDBAL(j),
73cd78f1 2224 rdba & 0x00000000ffffffffULL);
26bc19ec
AD		 2225 wr32(E1000_RDBAH(j), rdba >> 32);
2226 wr32(E1000_RDLEN(j),
73cd78f1 2227 ring->count * sizeof(union e1000_adv_rx_desc));
9d5c8243 2228
26bc19ec
AD		 2229 ring->head = E1000_RDH(j);
2230 ring->tail = E1000_RDT(j);
9d5c8243
AK		 2231 writel(0, hw->hw_addr + ring->tail);
2232 writel(0, hw->hw_addr + ring->head);
2233
26bc19ec 2234 rxdctl = rd32(E1000_RXDCTL(j));
9d5c8243
AK		 2235 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2236 rxdctl &= 0xFFF00000;
2237 rxdctl |= IGB_RX_PTHRESH;
2238 rxdctl |= IGB_RX_HTHRESH << 8;
2239 rxdctl |= IGB_RX_WTHRESH << 16;
26bc19ec 2240 wr32(E1000_RXDCTL(j), rxdctl);
9d5c8243
AK		 2241 }
2242
2243 if (adapter->num_rx_queues > 1) {
2244 u32 random[10];
2245 u32 mrqc;
2246 u32 j, shift;
2247 union e1000_reta {
2248 u32 dword;
2249 u8 bytes[4];
2250 } reta;
2251
2252 get_random_bytes(&random[0], 40);
2253
2d064c06
AD		 2254 if (hw->mac.type >= e1000_82576)
2255 shift = 0;
2256 else
2257 shift = 6;
9d5c8243
AK		 2258 for (j = 0; j < (32 * 4); j++) {
2259 reta.bytes[j & 3] =
26bc19ec 2260 adapter->rx_ring[(j % adapter->num_rx_queues)].reg_idx << shift;
9d5c8243
AK		 2261 if ((j & 3) == 3)
2262 writel(reta.dword,
2263 hw->hw_addr + E1000_RETA(0) + (j & ~3));
2264 }
e1739522
AD		 2265 if (adapter->vfs_allocated_count)
2266 mrqc = E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
2267 else
2268 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
9d5c8243
AK		 2269
2270 /* Fill out hash function seeds */
2271 for (j = 0; j < 10; j++)
2272 array_wr32(E1000_RSSRK(0), j, random[j]);
2273
2274 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2275 E1000_MRQC_RSS_FIELD_IPV4_TCP);
2276 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2277 E1000_MRQC_RSS_FIELD_IPV6_TCP);
2278 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
2279 E1000_MRQC_RSS_FIELD_IPV6_UDP);
2280 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2281 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2282
9d5c8243 2283 wr32(E1000_MRQC, mrqc);
2844f797 2284 } else if (adapter->vfs_allocated_count) {
e1739522 2285 /* Enable multi-queue for sr-iov */
2844f797 2286 wr32(E1000_MRQC, E1000_MRQC_ENABLE_VMDQ);
9d5c8243
AK		 2287 }
2288
2844f797
AD		 2289 /* Enable Receive Checksum Offload for TCP and UDP */
2290 rxcsum = rd32(E1000_RXCSUM);
2291 /* Disable raw packet checksumming */
2292 rxcsum |= E1000_RXCSUM_PCSD;
7beb0146
AD		 2293
2294 if (adapter->hw.mac.type == e1000_82576)
b9473560
JB		 2295 /* Enable Receive Checksum Offload for SCTP */
2296 rxcsum |= E1000_RXCSUM_CRCOFL;
2297
7beb0146 2298 /* Don't need to set TUOFL or IPOFL, they default to 1 */
2844f797
AD		 2299 wr32(E1000_RXCSUM, rxcsum);
2300
e1739522
AD		 2301 /* Set the default pool for the PF's first queue */
2302 igb_configure_vt_default_pool(adapter);
2303
2304 igb_rlpml_set(adapter);
9d5c8243
AK		 2305
2306 /* Enable Receives */
2307 wr32(E1000_RCTL, rctl);
2308}
2309
2310/**
2311 * igb_free_tx_resources - Free Tx Resources per Queue
9d5c8243
AK		 2312 * @tx_ring: Tx descriptor ring for a specific queue
2313 *
2314 * Free all transmit software resources
2315 **/
68fd9910 2316void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 2317{
3b644cf6 2318 struct pci_dev *pdev = tx_ring->adapter->pdev;
9d5c8243 2319
3b644cf6 2320 igb_clean_tx_ring(tx_ring);
9d5c8243
AK		 2321
2322 vfree(tx_ring->buffer_info);
2323 tx_ring->buffer_info = NULL;
2324
2325 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
2326
2327 tx_ring->desc = NULL;
2328}
2329
2330/**
2331 * igb_free_all_tx_resources - Free Tx Resources for All Queues
2332 * @adapter: board private structure
2333 *
2334 * Free all transmit software resources
2335 **/
2336static void igb_free_all_tx_resources(struct igb_adapter *adapter)
2337{
2338 int i;
2339
2340 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2341 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 2342}
2343
2344static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
2345 struct igb_buffer *buffer_info)
2346{
65689fef 2347 buffer_info->dma = 0;
9d5c8243 2348 if (buffer_info->skb) {
65689fef
AD		 2349 skb_dma_unmap(&adapter->pdev->dev, buffer_info->skb,
2350 DMA_TO_DEVICE);
9d5c8243
AK		 2351 dev_kfree_skb_any(buffer_info->skb);
2352 buffer_info->skb = NULL;
2353 }
2354 buffer_info->time_stamp = 0;
2355 /* buffer_info must be completely set up in the transmit path */
2356}
2357
2358/**
2359 * igb_clean_tx_ring - Free Tx Buffers
9d5c8243
AK		 2360 * @tx_ring: ring to be cleaned
2361 **/
3b644cf6 2362static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 2363{
3b644cf6 2364 struct igb_adapter *adapter = tx_ring->adapter;
9d5c8243
AK		 2365 struct igb_buffer *buffer_info;
2366 unsigned long size;
2367 unsigned int i;
2368
2369 if (!tx_ring->buffer_info)
2370 return;
2371 /* Free all the Tx ring sk_buffs */
2372
2373 for (i = 0; i < tx_ring->count; i++) {
2374 buffer_info = &tx_ring->buffer_info[i];
2375 igb_unmap_and_free_tx_resource(adapter, buffer_info);
2376 }
2377
2378 size = sizeof(struct igb_buffer) * tx_ring->count;
2379 memset(tx_ring->buffer_info, 0, size);
2380
2381 /* Zero out the descriptor ring */
2382
2383 memset(tx_ring->desc, 0, tx_ring->size);
2384
2385 tx_ring->next_to_use = 0;
2386 tx_ring->next_to_clean = 0;
2387
2388 writel(0, adapter->hw.hw_addr + tx_ring->head);
2389 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2390}
2391
2392/**
2393 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2394 * @adapter: board private structure
2395 **/
2396static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2397{
2398 int i;
2399
2400 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2401 igb_clean_tx_ring(&adapter->tx_ring[i]);
9d5c8243
AK		 2402}
2403
2404/**
2405 * igb_free_rx_resources - Free Rx Resources
9d5c8243
AK		 2406 * @rx_ring: ring to clean the resources from
2407 *
2408 * Free all receive software resources
2409 **/
68fd9910 2410void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2411{
3b644cf6 2412 struct pci_dev *pdev = rx_ring->adapter->pdev;
9d5c8243 2413
3b644cf6 2414 igb_clean_rx_ring(rx_ring);
9d5c8243
AK		 2415
2416 vfree(rx_ring->buffer_info);
2417 rx_ring->buffer_info = NULL;
2418
2419 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2420
2421 rx_ring->desc = NULL;
2422}
2423
2424/**
2425 * igb_free_all_rx_resources - Free Rx Resources for All Queues
2426 * @adapter: board private structure
2427 *
2428 * Free all receive software resources
2429 **/
2430static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2431{
2432 int i;
2433
2434 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2435 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 2436}
2437
2438/**
2439 * igb_clean_rx_ring - Free Rx Buffers per Queue
9d5c8243
AK		 2440 * @rx_ring: ring to free buffers from
2441 **/
3b644cf6 2442static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 2443{
3b644cf6 2444 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 2445 struct igb_buffer *buffer_info;
2446 struct pci_dev *pdev = adapter->pdev;
2447 unsigned long size;
2448 unsigned int i;
2449
2450 if (!rx_ring->buffer_info)
2451 return;
2452 /* Free all the Rx ring sk_buffs */
2453 for (i = 0; i < rx_ring->count; i++) {
2454 buffer_info = &rx_ring->buffer_info[i];
2455 if (buffer_info->dma) {
2456 if (adapter->rx_ps_hdr_size)
2457 pci_unmap_single(pdev, buffer_info->dma,
2458 adapter->rx_ps_hdr_size,
2459 PCI_DMA_FROMDEVICE);
2460 else
2461 pci_unmap_single(pdev, buffer_info->dma,
2462 adapter->rx_buffer_len,
2463 PCI_DMA_FROMDEVICE);
2464 buffer_info->dma = 0;
2465 }
2466
2467 if (buffer_info->skb) {
2468 dev_kfree_skb(buffer_info->skb);
2469 buffer_info->skb = NULL;
2470 }
2471 if (buffer_info->page) {
bf36c1a0
AD		 2472 if (buffer_info->page_dma)
2473 pci_unmap_page(pdev, buffer_info->page_dma,
2474 PAGE_SIZE / 2,
2475 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 2476 put_page(buffer_info->page);
2477 buffer_info->page = NULL;
2478 buffer_info->page_dma = 0;
bf36c1a0 2479 buffer_info->page_offset = 0;
9d5c8243
AK		 2480 }
2481 }
2482
9d5c8243
AK		 2483 size = sizeof(struct igb_buffer) * rx_ring->count;
2484 memset(rx_ring->buffer_info, 0, size);
2485
2486 /* Zero out the descriptor ring */
2487 memset(rx_ring->desc, 0, rx_ring->size);
2488
2489 rx_ring->next_to_clean = 0;
2490 rx_ring->next_to_use = 0;
2491
2492 writel(0, adapter->hw.hw_addr + rx_ring->head);
2493 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2494}
2495
2496/**
2497 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2498 * @adapter: board private structure
2499 **/
2500static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2501{
2502 int i;
2503
2504 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2505 igb_clean_rx_ring(&adapter->rx_ring[i]);
9d5c8243
AK		 2506}
2507
2508/**
2509 * igb_set_mac - Change the Ethernet Address of the NIC
2510 * @netdev: network interface device structure
2511 * @p: pointer to an address structure
2512 *
2513 * Returns 0 on success, negative on failure
2514 **/
2515static int igb_set_mac(struct net_device *netdev, void *p)
2516{
2517 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 2518 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 2519 struct sockaddr *addr = p;
2520
2521 if (!is_valid_ether_addr(addr->sa_data))
2522 return -EADDRNOTAVAIL;
2523
2524 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 2525 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 2526
ff41f8dc 2527 igb_rar_set(hw, hw->mac.addr, 0);
e1739522
AD		 2528 igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
2529
9d5c8243
AK		 2530 return 0;
2531}
2532
2533/**
ff41f8dc 2534 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
9d5c8243
AK		 2535 * @netdev: network interface device structure
2536 *
ff41f8dc
AD		 2537 * The set_rx_mode entry point is called whenever the unicast or multicast
2538 * address lists or the network interface flags are updated. This routine is
2539 * responsible for configuring the hardware for proper unicast, multicast,
9d5c8243
AK		 2540 * promiscuous mode, and all-multi behavior.
2541 **/
ff41f8dc 2542static void igb_set_rx_mode(struct net_device *netdev)
9d5c8243
AK		 2543{
2544 struct igb_adapter *adapter = netdev_priv(netdev);
2545 struct e1000_hw *hw = &adapter->hw;
ff41f8dc
AD		 2546 unsigned int rar_entries = hw->mac.rar_entry_count -
2547 (adapter->vfs_allocated_count + 1);
2548 struct dev_mc_list *mc_ptr = netdev->mc_list;
c5cd11e3 2549 u8 *mta_list = NULL;
9d5c8243
AK		 2550 u32 rctl;
2551 int i;
2552
2553 /* Check for Promiscuous and All Multicast modes */
9d5c8243
AK		 2554 rctl = rd32(E1000_RCTL);
2555
746b9f02 2556 if (netdev->flags & IFF_PROMISC) {
9d5c8243 2557 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
746b9f02
PM		 2558 rctl &= ~E1000_RCTL_VFE;
2559 } else {
ff41f8dc 2560 if (netdev->flags & IFF_ALLMULTI)
746b9f02 2561 rctl |= E1000_RCTL_MPE;
ff41f8dc
AD		 2562 else
2563 rctl &= ~E1000_RCTL_MPE;
2564
2565 if (netdev->uc.count > rar_entries)
2566 rctl |= E1000_RCTL_UPE;
2567 else
746b9f02 2568 rctl &= ~E1000_RCTL_UPE;
78ed11a5 2569 rctl |= E1000_RCTL_VFE;
746b9f02 2570 }
9d5c8243
AK		 2571 wr32(E1000_RCTL, rctl);
2572
ff41f8dc
AD		 2573 if (netdev->uc.count && rar_entries) {
2574 struct netdev_hw_addr *ha;
2575 list_for_each_entry(ha, &netdev->uc.list, list) {
2576 if (!rar_entries)
2577 break;
2578 igb_rar_set(hw, ha->addr, rar_entries);
2579 igb_set_rah_pool(hw, adapter->vfs_allocated_count,
2580 rar_entries);
2581 rar_entries--;
2582 }
2583 }
2584 /* write the addresses in reverse order to avoid write combining */
2585 for (; rar_entries > 0 ; rar_entries--) {
2586 wr32(E1000_RAH(rar_entries), 0);
2587 wr32(E1000_RAL(rar_entries), 0);
2588 }
2589 wrfl();
2590
28fc06f5
AD		 2591 if (!netdev->mc_count) {
2592 /* nothing to program, so clear mc list */
2593 igb_update_mc_addr_list(hw, NULL, 0);
2594 igb_restore_vf_multicasts(adapter);
2595 return;
2596 }
2597
2598 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2599 if (!mta_list) {
2600 dev_err(&adapter->pdev->dev,
2601 "failed to allocate multicast filter list\n");
2602 return;
9d5c8243
AK		 2603 }
2604
9d5c8243 2605 /* The shared function expects a packed array of only addresses. */
9d5c8243
AK		 2606 for (i = 0; i < netdev->mc_count; i++) {
2607 if (!mc_ptr)
2608 break;
2609 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2610 mc_ptr = mc_ptr->next;
2611 }
28fc06f5 2612 igb_update_mc_addr_list(hw, mta_list, i);
9d5c8243 2613 kfree(mta_list);
28fc06f5 2614 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 2615}
2616
2617/* Need to wait a few seconds after link up to get diagnostic information from
2618 * the phy */
2619static void igb_update_phy_info(unsigned long data)
2620{
2621 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 2622 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 2623}
2624
4d6b725e
AD		 2625/**
2626 * igb_has_link - check shared code for link and determine up/down
2627 * @adapter: pointer to driver private info
2628 **/
2629static bool igb_has_link(struct igb_adapter *adapter)
2630{
2631 struct e1000_hw *hw = &adapter->hw;
2632 bool link_active = false;
2633 s32 ret_val = 0;
2634
2635 /* get_link_status is set on LSC (link status) interrupt or
2636 * rx sequence error interrupt. get_link_status will stay
2637 * false until the e1000_check_for_link establishes link
2638 * for copper adapters ONLY
2639 */
2640 switch (hw->phy.media_type) {
2641 case e1000_media_type_copper:
2642 if (hw->mac.get_link_status) {
2643 ret_val = hw->mac.ops.check_for_link(hw);
2644 link_active = !hw->mac.get_link_status;
2645 } else {
2646 link_active = true;
2647 }
2648 break;
4d6b725e
AD		 2649 case e1000_media_type_internal_serdes:
2650 ret_val = hw->mac.ops.check_for_link(hw);
2651 link_active = hw->mac.serdes_has_link;
2652 break;
2653 default:
2654 case e1000_media_type_unknown:
2655 break;
2656 }
2657
2658 return link_active;
2659}
2660
9d5c8243
AK		 2661/**
2662 * igb_watchdog - Timer Call-back
2663 * @data: pointer to adapter cast into an unsigned long
2664 **/
2665static void igb_watchdog(unsigned long data)
2666{
2667 struct igb_adapter *adapter = (struct igb_adapter *)data;
2668 /* Do the rest outside of interrupt context */
2669 schedule_work(&adapter->watchdog_task);
2670}
2671
2672static void igb_watchdog_task(struct work_struct *work)
2673{
2674 struct igb_adapter *adapter = container_of(work,
2675 struct igb_adapter, watchdog_task);
2676 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 2677 struct net_device *netdev = adapter->netdev;
2678 struct igb_ring *tx_ring = adapter->tx_ring;
9d5c8243 2679 u32 link;
7a6ea550 2680 u32 eics = 0;
7a6ea550 2681 int i;
9d5c8243 2682
4d6b725e
AD		 2683 link = igb_has_link(adapter);
2684 if ((netif_carrier_ok(netdev)) && link)
9d5c8243
AK		 2685 goto link_up;
2686
9d5c8243
AK		 2687 if (link) {
2688 if (!netif_carrier_ok(netdev)) {
2689 u32 ctrl;
2690 hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2691 &adapter->link_speed,
2692 &adapter->link_duplex);
2693
2694 ctrl = rd32(E1000_CTRL);
527d47c1
AD		 2695 /* Links status message must follow this format */
2696 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
9d5c8243 2697 "Flow Control: %s\n",
527d47c1 2698 netdev->name,
9d5c8243
AK		 2699 adapter->link_speed,
2700 adapter->link_duplex == FULL_DUPLEX ?
2701 "Full Duplex" : "Half Duplex",
2702 ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2703 E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2704 E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2705 E1000_CTRL_TFCE) ? "TX" : "None")));
2706
2707 /* tweak tx_queue_len according to speed/duplex and
2708 * adjust the timeout factor */
2709 netdev->tx_queue_len = adapter->tx_queue_len;
2710 adapter->tx_timeout_factor = 1;
2711 switch (adapter->link_speed) {
2712 case SPEED_10:
2713 netdev->tx_queue_len = 10;
2714 adapter->tx_timeout_factor = 14;
2715 break;
2716 case SPEED_100:
2717 netdev->tx_queue_len = 100;
2718 /* maybe add some timeout factor ? */
2719 break;
2720 }
2721
2722 netif_carrier_on(netdev);
9d5c8243 2723
4ae196df
AD		 2724 igb_ping_all_vfs(adapter);
2725
4b1a9877 2726 /* link state has changed, schedule phy info update */
9d5c8243
AK		 2727 if (!test_bit(__IGB_DOWN, &adapter->state))
2728 mod_timer(&adapter->phy_info_timer,
2729 round_jiffies(jiffies + 2 * HZ));
2730 }
2731 } else {
2732 if (netif_carrier_ok(netdev)) {
2733 adapter->link_speed = 0;
2734 adapter->link_duplex = 0;
527d47c1
AD		 2735 /* Links status message must follow this format */
2736 printk(KERN_INFO "igb: %s NIC Link is Down\n",
2737 netdev->name);
9d5c8243 2738 netif_carrier_off(netdev);
4b1a9877 2739
4ae196df
AD		 2740 igb_ping_all_vfs(adapter);
2741
4b1a9877 2742 /* link state has changed, schedule phy info update */
9d5c8243
AK		 2743 if (!test_bit(__IGB_DOWN, &adapter->state))
2744 mod_timer(&adapter->phy_info_timer,
2745 round_jiffies(jiffies + 2 * HZ));
2746 }
2747 }
2748
2749link_up:
2750 igb_update_stats(adapter);
2751
4b1a9877 2752 hw->mac.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
9d5c8243 2753 adapter->tpt_old = adapter->stats.tpt;
4b1a9877 2754 hw->mac.collision_delta = adapter->stats.colc - adapter->colc_old;
9d5c8243
AK		 2755 adapter->colc_old = adapter->stats.colc;
2756
2757 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2758 adapter->gorc_old = adapter->stats.gorc;
2759 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2760 adapter->gotc_old = adapter->stats.gotc;
2761
2762 igb_update_adaptive(&adapter->hw);
2763
2764 if (!netif_carrier_ok(netdev)) {
c493ea45 2765 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
9d5c8243
AK		 2766 /* We've lost link, so the controller stops DMA,
2767 * but we've got queued Tx work that's never going
2768 * to get done, so reset controller to flush Tx.
2769 * (Do the reset outside of interrupt context). */
2770 adapter->tx_timeout_count++;
2771 schedule_work(&adapter->reset_task);
c2d5ab49
JB		 2772 /* return immediately since reset is imminent */
2773 return;
9d5c8243
AK		 2774 }
2775 }
2776
2777 /* Cause software interrupt to ensure rx ring is cleaned */
7a6ea550
AD		 2778 if (adapter->msix_entries) {
2779 for (i = 0; i < adapter->num_rx_queues; i++)
2780 eics |= adapter->rx_ring[i].eims_value;
2781 wr32(E1000_EICS, eics);
2782 } else {
2783 wr32(E1000_ICS, E1000_ICS_RXDMT0);
2784 }
9d5c8243
AK		 2785
2786 /* Force detection of hung controller every watchdog period */
2787 tx_ring->detect_tx_hung = true;
2788
2789 /* Reset the timer */
2790 if (!test_bit(__IGB_DOWN, &adapter->state))
2791 mod_timer(&adapter->watchdog_timer,
2792 round_jiffies(jiffies + 2 * HZ));
2793}
2794
2795enum latency_range {
2796 lowest_latency = 0,
2797 low_latency = 1,
2798 bulk_latency = 2,
2799 latency_invalid = 255
2800};
2801
2802
6eb5a7f1
AD		 2803/**
2804 * igb_update_ring_itr - update the dynamic ITR value based on packet size
2805 *
2806 * Stores a new ITR value based on strictly on packet size. This
2807 * algorithm is less sophisticated than that used in igb_update_itr,
2808 * due to the difficulty of synchronizing statistics across multiple
2809 * receive rings. The divisors and thresholds used by this fuction
2810 * were determined based on theoretical maximum wire speed and testing
2811 * data, in order to minimize response time while increasing bulk
2812 * throughput.
2813 * This functionality is controlled by the InterruptThrottleRate module
2814 * parameter (see igb_param.c)
2815 * NOTE: This function is called only when operating in a multiqueue
2816 * receive environment.
2817 * @rx_ring: pointer to ring
2818 **/
2819static void igb_update_ring_itr(struct igb_ring *rx_ring)
9d5c8243 2820{
6eb5a7f1
AD		 2821 int new_val = rx_ring->itr_val;
2822 int avg_wire_size = 0;
2823 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 2824
6eb5a7f1
AD		 2825 if (!rx_ring->total_packets)
2826 goto clear_counts; /* no packets, so don't do anything */
9d5c8243 2827
6eb5a7f1
AD		 2828 /* For non-gigabit speeds, just fix the interrupt rate at 4000
2829 * ints/sec - ITR timer value of 120 ticks.
2830 */
2831 if (adapter->link_speed != SPEED_1000) {
2832 new_val = 120;
2833 goto set_itr_val;
9d5c8243 2834 }
6eb5a7f1 2835 avg_wire_size = rx_ring->total_bytes / rx_ring->total_packets;
9d5c8243 2836
6eb5a7f1
AD		 2837 /* Add 24 bytes to size to account for CRC, preamble, and gap */
2838 avg_wire_size += 24;
2839
2840 /* Don't starve jumbo frames */
2841 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 2842
6eb5a7f1
AD		 2843 /* Give a little boost to mid-size frames */
2844 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
2845 new_val = avg_wire_size / 3;
2846 else
2847 new_val = avg_wire_size / 2;
9d5c8243 2848
6eb5a7f1 2849set_itr_val:
9d5c8243
AK		 2850 if (new_val != rx_ring->itr_val) {
2851 rx_ring->itr_val = new_val;
6eb5a7f1 2852 rx_ring->set_itr = 1;
9d5c8243 2853 }
6eb5a7f1
AD		 2854clear_counts:
2855 rx_ring->total_bytes = 0;
2856 rx_ring->total_packets = 0;
9d5c8243
AK		 2857}
2858
2859/**
2860 * igb_update_itr - update the dynamic ITR value based on statistics
2861 * Stores a new ITR value based on packets and byte
2862 * counts during the last interrupt. The advantage of per interrupt
2863 * computation is faster updates and more accurate ITR for the current
2864 * traffic pattern. Constants in this function were computed
2865 * based on theoretical maximum wire speed and thresholds were set based
2866 * on testing data as well as attempting to minimize response time
2867 * while increasing bulk throughput.
2868 * this functionality is controlled by the InterruptThrottleRate module
2869 * parameter (see igb_param.c)
2870 * NOTE: These calculations are only valid when operating in a single-
2871 * queue environment.
2872 * @adapter: pointer to adapter
2873 * @itr_setting: current adapter->itr
2874 * @packets: the number of packets during this measurement interval
2875 * @bytes: the number of bytes during this measurement interval
2876 **/
2877static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
2878 int packets, int bytes)
2879{
2880 unsigned int retval = itr_setting;
2881
2882 if (packets == 0)
2883 goto update_itr_done;
2884
2885 switch (itr_setting) {
2886 case lowest_latency:
2887 /* handle TSO and jumbo frames */
2888 if (bytes/packets > 8000)
2889 retval = bulk_latency;
2890 else if ((packets < 5) && (bytes > 512))
2891 retval = low_latency;
2892 break;
2893 case low_latency: /* 50 usec aka 20000 ints/s */
2894 if (bytes > 10000) {
2895 /* this if handles the TSO accounting */
2896 if (bytes/packets > 8000) {
2897 retval = bulk_latency;
2898 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
2899 retval = bulk_latency;
2900 } else if ((packets > 35)) {
2901 retval = lowest_latency;
2902 }
2903 } else if (bytes/packets > 2000) {
2904 retval = bulk_latency;
2905 } else if (packets <= 2 && bytes < 512) {
2906 retval = lowest_latency;
2907 }
2908 break;
2909 case bulk_latency: /* 250 usec aka 4000 ints/s */
2910 if (bytes > 25000) {
2911 if (packets > 35)
2912 retval = low_latency;
1e5c3d21 2913 } else if (bytes < 1500) {
9d5c8243
AK		 2914 retval = low_latency;
2915 }
2916 break;
2917 }
2918
2919update_itr_done:
2920 return retval;
2921}
2922
6eb5a7f1 2923static void igb_set_itr(struct igb_adapter *adapter)
9d5c8243
AK		 2924{
2925 u16 current_itr;
2926 u32 new_itr = adapter->itr;
2927
2928 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2929 if (adapter->link_speed != SPEED_1000) {
2930 current_itr = 0;
2931 new_itr = 4000;
2932 goto set_itr_now;
2933 }
2934
2935 adapter->rx_itr = igb_update_itr(adapter,
2936 adapter->rx_itr,
2937 adapter->rx_ring->total_packets,
2938 adapter->rx_ring->total_bytes);
9d5c8243 2939
6eb5a7f1 2940 if (adapter->rx_ring->buddy) {
9d5c8243
AK		 2941 adapter->tx_itr = igb_update_itr(adapter,
2942 adapter->tx_itr,
2943 adapter->tx_ring->total_packets,
2944 adapter->tx_ring->total_bytes);
9d5c8243
AK		 2945 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2946 } else {
2947 current_itr = adapter->rx_itr;
2948 }
2949
6eb5a7f1 2950 /* conservative mode (itr 3) eliminates the lowest_latency setting */
73cd78f1 2951 if (adapter->itr_setting == 3 && current_itr == lowest_latency)
6eb5a7f1
AD		 2952 current_itr = low_latency;
2953
9d5c8243
AK		 2954 switch (current_itr) {
2955 /* counts and packets in update_itr are dependent on these numbers */
2956 case lowest_latency:
78b1f607 2957 new_itr = 56; /* aka 70,000 ints/sec */
9d5c8243
AK		 2958 break;
2959 case low_latency:
78b1f607 2960 new_itr = 196; /* aka 20,000 ints/sec */
9d5c8243
AK		 2961 break;
2962 case bulk_latency:
78b1f607 2963 new_itr = 980; /* aka 4,000 ints/sec */
9d5c8243
AK		 2964 break;
2965 default:
2966 break;
2967 }
2968
2969set_itr_now:
6eb5a7f1
AD		 2970 adapter->rx_ring->total_bytes = 0;
2971 adapter->rx_ring->total_packets = 0;
2972 if (adapter->rx_ring->buddy) {
2973 adapter->rx_ring->buddy->total_bytes = 0;
2974 adapter->rx_ring->buddy->total_packets = 0;
2975 }
2976
9d5c8243
AK		 2977 if (new_itr != adapter->itr) {
2978 /* this attempts to bias the interrupt rate towards Bulk
2979 * by adding intermediate steps when interrupt rate is
2980 * increasing */
2981 new_itr = new_itr > adapter->itr ?
78b1f607
AD		 2982 max((new_itr * adapter->itr) /
2983 (new_itr + (adapter->itr >> 2)), new_itr) :
9d5c8243
AK		 2984 new_itr;
2985 /* Don't write the value here; it resets the adapter's
2986 * internal timer, and causes us to delay far longer than
2987 * we should between interrupts. Instead, we write the ITR
2988 * value at the beginning of the next interrupt so the timing
2989 * ends up being correct.
2990 */
2991 adapter->itr = new_itr;
78b1f607 2992 adapter->rx_ring->itr_val = new_itr;
6eb5a7f1 2993 adapter->rx_ring->set_itr = 1;
9d5c8243
AK		 2994 }
2995
2996 return;
2997}
2998
2999
3000#define IGB_TX_FLAGS_CSUM 0x00000001
3001#define IGB_TX_FLAGS_VLAN 0x00000002
3002#define IGB_TX_FLAGS_TSO 0x00000004
3003#define IGB_TX_FLAGS_IPV4 0x00000008
33af6bcc 3004#define IGB_TX_FLAGS_TSTAMP 0x00000010
9d5c8243
AK		 3005#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
3006#define IGB_TX_FLAGS_VLAN_SHIFT 16
3007
3008static inline int igb_tso_adv(struct igb_adapter *adapter,
3009 struct igb_ring *tx_ring,
3010 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
3011{
3012 struct e1000_adv_tx_context_desc *context_desc;
3013 unsigned int i;
3014 int err;
3015 struct igb_buffer *buffer_info;
3016 u32 info = 0, tu_cmd = 0;
3017 u32 mss_l4len_idx, l4len;
3018 *hdr_len = 0;
3019
3020 if (skb_header_cloned(skb)) {
3021 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
3022 if (err)
3023 return err;
3024 }
3025
3026 l4len = tcp_hdrlen(skb);
3027 *hdr_len += l4len;
3028
3029 if (skb->protocol == htons(ETH_P_IP)) {
3030 struct iphdr *iph = ip_hdr(skb);
3031 iph->tot_len = 0;
3032 iph->check = 0;
3033 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
3034 iph->daddr, 0,
3035 IPPROTO_TCP,
3036 0);
3037 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
3038 ipv6_hdr(skb)->payload_len = 0;
3039 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
3040 &ipv6_hdr(skb)->daddr,
3041 0, IPPROTO_TCP, 0);
3042 }
3043
3044 i = tx_ring->next_to_use;
3045
3046 buffer_info = &tx_ring->buffer_info[i];
3047 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3048 /* VLAN MACLEN IPLEN */
3049 if (tx_flags & IGB_TX_FLAGS_VLAN)
3050 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
3051 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3052 *hdr_len += skb_network_offset(skb);
3053 info |= skb_network_header_len(skb);
3054 *hdr_len += skb_network_header_len(skb);
3055 context_desc->vlan_macip_lens = cpu_to_le32(info);
3056
3057 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
3058 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3059
3060 if (skb->protocol == htons(ETH_P_IP))
3061 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
3062 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3063
3064 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3065
3066 /* MSS L4LEN IDX */
3067 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
3068 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
3069
73cd78f1 3070 /* For 82575, context index must be unique per ring. */
7dfc16fa
AD		 3071 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
3072 mss_l4len_idx |= tx_ring->queue_index << 4;
9d5c8243
AK		 3073
3074 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
3075 context_desc->seqnum_seed = 0;
3076
3077 buffer_info->time_stamp = jiffies;
0e014cb1 3078 buffer_info->next_to_watch = i;
9d5c8243
AK		 3079 buffer_info->dma = 0;
3080 i++;
3081 if (i == tx_ring->count)
3082 i = 0;
3083
3084 tx_ring->next_to_use = i;
3085
3086 return true;
3087}
3088
3089static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
3090 struct igb_ring *tx_ring,
3091 struct sk_buff *skb, u32 tx_flags)
3092{
3093 struct e1000_adv_tx_context_desc *context_desc;
3094 unsigned int i;
3095 struct igb_buffer *buffer_info;
3096 u32 info = 0, tu_cmd = 0;
3097
3098 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
3099 (tx_flags & IGB_TX_FLAGS_VLAN)) {
3100 i = tx_ring->next_to_use;
3101 buffer_info = &tx_ring->buffer_info[i];
3102 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3103
3104 if (tx_flags & IGB_TX_FLAGS_VLAN)
3105 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
3106 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3107 if (skb->ip_summed == CHECKSUM_PARTIAL)
3108 info |= skb_network_header_len(skb);
3109
3110 context_desc->vlan_macip_lens = cpu_to_le32(info);
3111
3112 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3113
3114 if (skb->ip_summed == CHECKSUM_PARTIAL) {
fa4a7ef3
AJ		 3115 __be16 protocol;
3116
3117 if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
3118 const struct vlan_ethhdr *vhdr =
3119 (const struct vlan_ethhdr*)skb->data;
3120
3121 protocol = vhdr->h_vlan_encapsulated_proto;
3122 } else {
3123 protocol = skb->protocol;
3124 }
3125
3126 switch (protocol) {
09640e63 3127 case cpu_to_be16(ETH_P_IP):
9d5c8243 3128 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
44b0cda3
MW		 3129 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
3130 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
b9473560
JB		 3131 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
3132 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
44b0cda3 3133 break;
09640e63 3134 case cpu_to_be16(ETH_P_IPV6):
44b0cda3
MW		 3135 /* XXX what about other V6 headers?? */
3136 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
3137 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
b9473560
JB		 3138 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
3139 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
44b0cda3
MW		 3140 break;
3141 default:
3142 if (unlikely(net_ratelimit()))
3143 dev_warn(&adapter->pdev->dev,
3144 "partial checksum but proto=%x!\n",
3145 skb->protocol);
3146 break;
3147 }
9d5c8243
AK		 3148 }
3149
3150 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3151 context_desc->seqnum_seed = 0;
7dfc16fa
AD		 3152 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
3153 context_desc->mss_l4len_idx =
3154 cpu_to_le32(tx_ring->queue_index << 4);
265de409
AD		 3155 else
3156 context_desc->mss_l4len_idx = 0;
9d5c8243
AK		 3157
3158 buffer_info->time_stamp = jiffies;
0e014cb1 3159 buffer_info->next_to_watch = i;
9d5c8243
AK		 3160 buffer_info->dma = 0;
3161
3162 i++;
3163 if (i == tx_ring->count)
3164 i = 0;
3165 tx_ring->next_to_use = i;
3166
3167 return true;
3168 }
9d5c8243
AK		 3169 return false;
3170}
3171
3172#define IGB_MAX_TXD_PWR 16
3173#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
3174
3175static inline int igb_tx_map_adv(struct igb_adapter *adapter,
0e014cb1
AD		 3176 struct igb_ring *tx_ring, struct sk_buff *skb,
3177 unsigned int first)
9d5c8243
AK		 3178{
3179 struct igb_buffer *buffer_info;
3180 unsigned int len = skb_headlen(skb);
3181 unsigned int count = 0, i;
3182 unsigned int f;
65689fef 3183 dma_addr_t *map;
9d5c8243
AK		 3184
3185 i = tx_ring->next_to_use;
3186
65689fef
AD		 3187 if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
3188 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
3189 return 0;
3190 }
3191
3192 map = skb_shinfo(skb)->dma_maps;
3193
9d5c8243
AK		 3194 buffer_info = &tx_ring->buffer_info[i];
3195 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3196 buffer_info->length = len;
3197 /* set time_stamp *before* dma to help avoid a possible race */
3198 buffer_info->time_stamp = jiffies;
0e014cb1 3199 buffer_info->next_to_watch = i;
042a53a9 3200 buffer_info->dma = skb_shinfo(skb)->dma_head;
9d5c8243
AK		 3201
3202 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
3203 struct skb_frag_struct *frag;
3204
65689fef
AD		 3205 i++;
3206 if (i == tx_ring->count)
3207 i = 0;
3208
9d5c8243
AK		 3209 frag = &skb_shinfo(skb)->frags[f];
3210 len = frag->size;
3211
3212 buffer_info = &tx_ring->buffer_info[i];
3213 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3214 buffer_info->length = len;
3215 buffer_info->time_stamp = jiffies;
0e014cb1 3216 buffer_info->next_to_watch = i;
65689fef 3217 buffer_info->dma = map[count];
9d5c8243 3218 count++;
9d5c8243
AK		 3219 }
3220
9d5c8243 3221 tx_ring->buffer_info[i].skb = skb;
0e014cb1 3222 tx_ring->buffer_info[first].next_to_watch = i;
9d5c8243 3223
042a53a9 3224 return count + 1;
9d5c8243
AK		 3225}
3226
3227static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
3228 struct igb_ring *tx_ring,
3229 int tx_flags, int count, u32 paylen,
3230 u8 hdr_len)
3231{
3232 union e1000_adv_tx_desc *tx_desc = NULL;
3233 struct igb_buffer *buffer_info;
3234 u32 olinfo_status = 0, cmd_type_len;
3235 unsigned int i;
3236
3237 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
3238 E1000_ADVTXD_DCMD_DEXT);
3239
3240 if (tx_flags & IGB_TX_FLAGS_VLAN)
3241 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3242
33af6bcc
PO		 3243 if (tx_flags & IGB_TX_FLAGS_TSTAMP)
3244 cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP;
3245
9d5c8243
AK		 3246 if (tx_flags & IGB_TX_FLAGS_TSO) {
3247 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3248
3249 /* insert tcp checksum */
3250 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3251
3252 /* insert ip checksum */
3253 if (tx_flags & IGB_TX_FLAGS_IPV4)
3254 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3255
3256 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
3257 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3258 }
3259
7dfc16fa
AD		 3260 if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) &&
3261 (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
3262 IGB_TX_FLAGS_VLAN)))
661086df 3263 olinfo_status |= tx_ring->queue_index << 4;
9d5c8243
AK		 3264
3265 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
3266
3267 i = tx_ring->next_to_use;
3268 while (count--) {
3269 buffer_info = &tx_ring->buffer_info[i];
3270 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
3271 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
3272 tx_desc->read.cmd_type_len =
3273 cpu_to_le32(cmd_type_len | buffer_info->length);
3274 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
3275 i++;
3276 if (i == tx_ring->count)
3277 i = 0;
3278 }
3279
3280 tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
3281 /* Force memory writes to complete before letting h/w
3282 * know there are new descriptors to fetch. (Only
3283 * applicable for weak-ordered memory model archs,
3284 * such as IA-64). */
3285 wmb();
3286
3287 tx_ring->next_to_use = i;
3288 writel(i, adapter->hw.hw_addr + tx_ring->tail);
3289 /* we need this if more than one processor can write to our tail
3290 * at a time, it syncronizes IO on IA64/Altix systems */
3291 mmiowb();
3292}
3293
3294static int __igb_maybe_stop_tx(struct net_device *netdev,
3295 struct igb_ring *tx_ring, int size)
3296{
3297 struct igb_adapter *adapter = netdev_priv(netdev);
3298
661086df 3299 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 3300
9d5c8243
AK		 3301 /* Herbert's original patch had:
3302 * smp_mb__after_netif_stop_queue();
3303 * but since that doesn't exist yet, just open code it. */
3304 smp_mb();
3305
3306 /* We need to check again in a case another CPU has just
3307 * made room available. */
c493ea45 3308 if (igb_desc_unused(tx_ring) < size)
9d5c8243
AK		 3309 return -EBUSY;
3310
3311 /* A reprieve! */
661086df 3312 netif_wake_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 3313 ++adapter->restart_queue;
3314 return 0;
3315}
3316
3317static int igb_maybe_stop_tx(struct net_device *netdev,
3318 struct igb_ring *tx_ring, int size)
3319{
c493ea45 3320 if (igb_desc_unused(tx_ring) >= size)
9d5c8243
AK		 3321 return 0;
3322 return __igb_maybe_stop_tx(netdev, tx_ring, size);
3323}
3324
3b29a56d
SH		 3325static netdev_tx_t igb_xmit_frame_ring_adv(struct sk_buff *skb,
3326 struct net_device *netdev,
3327 struct igb_ring *tx_ring)
9d5c8243
AK		 3328{
3329 struct igb_adapter *adapter = netdev_priv(netdev);
0e014cb1 3330 unsigned int first;
9d5c8243 3331 unsigned int tx_flags = 0;
9d5c8243 3332 u8 hdr_len = 0;
65689fef 3333 int count = 0;
9d5c8243 3334 int tso = 0;
33af6bcc 3335 union skb_shared_tx *shtx;
9d5c8243 3336
9d5c8243
AK		 3337 if (test_bit(__IGB_DOWN, &adapter->state)) {
3338 dev_kfree_skb_any(skb);
3339 return NETDEV_TX_OK;
3340 }
3341
3342 if (skb->len <= 0) {
3343 dev_kfree_skb_any(skb);
3344 return NETDEV_TX_OK;
3345 }
3346
9d5c8243
AK		 3347 /* need: 1 descriptor per page,
3348 * + 2 desc gap to keep tail from touching head,
3349 * + 1 desc for skb->data,
3350 * + 1 desc for context descriptor,
3351 * otherwise try next time */
3352 if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
3353 /* this is a hard error */
9d5c8243
AK		 3354 return NETDEV_TX_BUSY;
3355 }
33af6bcc
PO		 3356
3357 /*
3358 * TODO: check that there currently is no other packet with
3359 * time stamping in the queue
3360 *
3361 * When doing time stamping, keep the connection to the socket
3362 * a while longer: it is still needed by skb_hwtstamp_tx(),
3363 * called either in igb_tx_hwtstamp() or by our caller when
3364 * doing software time stamping.
3365 */
3366 shtx = skb_tx(skb);
3367 if (unlikely(shtx->hardware)) {
3368 shtx->in_progress = 1;
3369 tx_flags |= IGB_TX_FLAGS_TSTAMP;
33af6bcc 3370 }
9d5c8243
AK		 3371
3372 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
3373 tx_flags |= IGB_TX_FLAGS_VLAN;
3374 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
3375 }
3376
661086df
PWJ		 3377 if (skb->protocol == htons(ETH_P_IP))
3378 tx_flags |= IGB_TX_FLAGS_IPV4;
3379
0e014cb1 3380 first = tx_ring->next_to_use;
9d5c8243
AK		 3381 tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
3382 &hdr_len) : 0;
3383
3384 if (tso < 0) {
3385 dev_kfree_skb_any(skb);
9d5c8243
AK		 3386 return NETDEV_TX_OK;
3387 }
3388
3389 if (tso)
3390 tx_flags |= IGB_TX_FLAGS_TSO;
bc1cbd34
AD		 3391 else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags) &&
3392 (skb->ip_summed == CHECKSUM_PARTIAL))
3393 tx_flags |= IGB_TX_FLAGS_CSUM;
9d5c8243 3394
65689fef
AD		 3395 /*
3396 * count reflects descriptors mapped, if 0 then mapping error
3397 * has occured and we need to rewind the descriptor queue
3398 */
3399 count = igb_tx_map_adv(adapter, tx_ring, skb, first);
3400
3401 if (count) {
3402 igb_tx_queue_adv(adapter, tx_ring, tx_flags, count,
3403 skb->len, hdr_len);
65689fef
AD		 3404 /* Make sure there is space in the ring for the next send. */
3405 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
3406 } else {
3407 dev_kfree_skb_any(skb);
3408 tx_ring->buffer_info[first].time_stamp = 0;
3409 tx_ring->next_to_use = first;
3410 }
9d5c8243 3411
9d5c8243
AK		 3412 return NETDEV_TX_OK;
3413}
3414
3b29a56d
SH		 3415static netdev_tx_t igb_xmit_frame_adv(struct sk_buff *skb,
3416 struct net_device *netdev)
9d5c8243
AK		 3417{
3418 struct igb_adapter *adapter = netdev_priv(netdev);
661086df
PWJ		 3419 struct igb_ring *tx_ring;
3420
661086df 3421 int r_idx = 0;
1bfaf07b 3422 r_idx = skb->queue_mapping & (IGB_ABS_MAX_TX_QUEUES - 1);
661086df 3423 tx_ring = adapter->multi_tx_table[r_idx];
9d5c8243
AK		 3424
3425 /* This goes back to the question of how to logically map a tx queue
3426 * to a flow. Right now, performance is impacted slightly negatively
3427 * if using multiple tx queues. If the stack breaks away from a
3428 * single qdisc implementation, we can look at this again. */
3b29a56d 3429 return igb_xmit_frame_ring_adv(skb, netdev, tx_ring);
9d5c8243
AK		 3430}
3431
3432/**
3433 * igb_tx_timeout - Respond to a Tx Hang
3434 * @netdev: network interface device structure
3435 **/
3436static void igb_tx_timeout(struct net_device *netdev)
3437{
3438 struct igb_adapter *adapter = netdev_priv(netdev);
3439 struct e1000_hw *hw = &adapter->hw;
3440
3441 /* Do the reset outside of interrupt context */
3442 adapter->tx_timeout_count++;
3443 schedule_work(&adapter->reset_task);
265de409
AD		 3444 wr32(E1000_EICS,
3445 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 3446}
3447
3448static void igb_reset_task(struct work_struct *work)
3449{
3450 struct igb_adapter *adapter;
3451 adapter = container_of(work, struct igb_adapter, reset_task);
3452
3453 igb_reinit_locked(adapter);
3454}
3455
3456/**
3457 * igb_get_stats - Get System Network Statistics
3458 * @netdev: network interface device structure
3459 *
3460 * Returns the address of the device statistics structure.
3461 * The statistics are actually updated from the timer callback.
3462 **/
73cd78f1 3463static struct net_device_stats *igb_get_stats(struct net_device *netdev)
9d5c8243
AK		 3464{
3465 struct igb_adapter *adapter = netdev_priv(netdev);
3466
3467 /* only return the current stats */
3468 return &adapter->net_stats;
3469}
3470
3471/**
3472 * igb_change_mtu - Change the Maximum Transfer Unit
3473 * @netdev: network interface device structure
3474 * @new_mtu: new value for maximum frame size
3475 *
3476 * Returns 0 on success, negative on failure
3477 **/
3478static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3479{
3480 struct igb_adapter *adapter = netdev_priv(netdev);
3481 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3482
3483 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
3484 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3485 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
3486 return -EINVAL;
3487 }
3488
9d5c8243
AK		 3489 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3490 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
3491 return -EINVAL;
3492 }
3493
3494 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3495 msleep(1);
73cd78f1 3496
9d5c8243
AK		 3497 /* igb_down has a dependency on max_frame_size */
3498 adapter->max_frame_size = max_frame;
3499 if (netif_running(netdev))
3500 igb_down(adapter);
3501
3502 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3503 * means we reserve 2 more, this pushes us to allocate from the next
3504 * larger slab size.
3505 * i.e. RXBUFFER_2048 --> size-4096 slab
3506 */
3507
3508 if (max_frame <= IGB_RXBUFFER_256)
3509 adapter->rx_buffer_len = IGB_RXBUFFER_256;
3510 else if (max_frame <= IGB_RXBUFFER_512)
3511 adapter->rx_buffer_len = IGB_RXBUFFER_512;
3512 else if (max_frame <= IGB_RXBUFFER_1024)
3513 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3514 else if (max_frame <= IGB_RXBUFFER_2048)
3515 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
3516 else
bf36c1a0
AD		 3517#if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
3518 adapter->rx_buffer_len = IGB_RXBUFFER_16384;
3519#else
3520 adapter->rx_buffer_len = PAGE_SIZE / 2;
3521#endif
e1739522
AD		 3522
3523 /* if sr-iov is enabled we need to force buffer size to 1K or larger */
3524 if (adapter->vfs_allocated_count &&
3525 (adapter->rx_buffer_len < IGB_RXBUFFER_1024))
3526 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3527
9d5c8243
AK		 3528 /* adjust allocation if LPE protects us, and we aren't using SBP */
3529 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
3530 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
3531 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3532
3533 dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
3534 netdev->mtu, new_mtu);
3535 netdev->mtu = new_mtu;
3536
3537 if (netif_running(netdev))
3538 igb_up(adapter);
3539 else
3540 igb_reset(adapter);
3541
3542 clear_bit(__IGB_RESETTING, &adapter->state);
3543
3544 return 0;
3545}
3546
3547/**
3548 * igb_update_stats - Update the board statistics counters
3549 * @adapter: board private structure
3550 **/
3551
3552void igb_update_stats(struct igb_adapter *adapter)
3553{
3554 struct e1000_hw *hw = &adapter->hw;
3555 struct pci_dev *pdev = adapter->pdev;
3556 u16 phy_tmp;
3557
3558#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3559
3560 /*
3561 * Prevent stats update while adapter is being reset, or if the pci
3562 * connection is down.
3563 */
3564 if (adapter->link_speed == 0)
3565 return;
3566 if (pci_channel_offline(pdev))
3567 return;
3568
3569 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3570 adapter->stats.gprc += rd32(E1000_GPRC);
3571 adapter->stats.gorc += rd32(E1000_GORCL);
3572 rd32(E1000_GORCH); /* clear GORCL */
3573 adapter->stats.bprc += rd32(E1000_BPRC);
3574 adapter->stats.mprc += rd32(E1000_MPRC);
3575 adapter->stats.roc += rd32(E1000_ROC);
3576
3577 adapter->stats.prc64 += rd32(E1000_PRC64);
3578 adapter->stats.prc127 += rd32(E1000_PRC127);
3579 adapter->stats.prc255 += rd32(E1000_PRC255);
3580 adapter->stats.prc511 += rd32(E1000_PRC511);
3581 adapter->stats.prc1023 += rd32(E1000_PRC1023);
3582 adapter->stats.prc1522 += rd32(E1000_PRC1522);
3583 adapter->stats.symerrs += rd32(E1000_SYMERRS);
3584 adapter->stats.sec += rd32(E1000_SEC);
3585
3586 adapter->stats.mpc += rd32(E1000_MPC);
3587 adapter->stats.scc += rd32(E1000_SCC);
3588 adapter->stats.ecol += rd32(E1000_ECOL);
3589 adapter->stats.mcc += rd32(E1000_MCC);
3590 adapter->stats.latecol += rd32(E1000_LATECOL);
3591 adapter->stats.dc += rd32(E1000_DC);
3592 adapter->stats.rlec += rd32(E1000_RLEC);
3593 adapter->stats.xonrxc += rd32(E1000_XONRXC);
3594 adapter->stats.xontxc += rd32(E1000_XONTXC);
3595 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
3596 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
3597 adapter->stats.fcruc += rd32(E1000_FCRUC);
3598 adapter->stats.gptc += rd32(E1000_GPTC);
3599 adapter->stats.gotc += rd32(E1000_GOTCL);
3600 rd32(E1000_GOTCH); /* clear GOTCL */
3601 adapter->stats.rnbc += rd32(E1000_RNBC);
3602 adapter->stats.ruc += rd32(E1000_RUC);
3603 adapter->stats.rfc += rd32(E1000_RFC);
3604 adapter->stats.rjc += rd32(E1000_RJC);
3605 adapter->stats.tor += rd32(E1000_TORH);
3606 adapter->stats.tot += rd32(E1000_TOTH);
3607 adapter->stats.tpr += rd32(E1000_TPR);
3608
3609 adapter->stats.ptc64 += rd32(E1000_PTC64);
3610 adapter->stats.ptc127 += rd32(E1000_PTC127);
3611 adapter->stats.ptc255 += rd32(E1000_PTC255);
3612 adapter->stats.ptc511 += rd32(E1000_PTC511);
3613 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
3614 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
3615
3616 adapter->stats.mptc += rd32(E1000_MPTC);
3617 adapter->stats.bptc += rd32(E1000_BPTC);
3618
3619 /* used for adaptive IFS */
3620
3621 hw->mac.tx_packet_delta = rd32(E1000_TPT);
3622 adapter->stats.tpt += hw->mac.tx_packet_delta;
3623 hw->mac.collision_delta = rd32(E1000_COLC);
3624 adapter->stats.colc += hw->mac.collision_delta;
3625
3626 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
3627 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3628 adapter->stats.tncrs += rd32(E1000_TNCRS);
3629 adapter->stats.tsctc += rd32(E1000_TSCTC);
3630 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
3631
3632 adapter->stats.iac += rd32(E1000_IAC);
3633 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
3634 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
3635 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
3636 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
3637 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
3638 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
3639 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
3640 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
3641
3642 /* Fill out the OS statistics structure */
3643 adapter->net_stats.multicast = adapter->stats.mprc;
3644 adapter->net_stats.collisions = adapter->stats.colc;
3645
3646 /* Rx Errors */
3647
8c0ab70a
JDB		 3648 if (hw->mac.type != e1000_82575) {
3649 u32 rqdpc_tmp;
3ea73afa 3650 u64 rqdpc_total = 0;
8c0ab70a
JDB		 3651 int i;
3652 /* Read out drops stats per RX queue. Notice RQDPC (Receive
3653 * Queue Drop Packet Count) stats only gets incremented, if
3654 * the DROP_EN but it set (in the SRRCTL register for that
3655 * queue). If DROP_EN bit is NOT set, then the some what
3656 * equivalent count is stored in RNBC (not per queue basis).
3657 * Also note the drop count is due to lack of available
3658 * descriptors.
3659 */
3660 for (i = 0; i < adapter->num_rx_queues; i++) {
3661 rqdpc_tmp = rd32(E1000_RQDPC(i)) & 0xFFF;
3662 adapter->rx_ring[i].rx_stats.drops += rqdpc_tmp;
3ea73afa 3663 rqdpc_total += adapter->rx_ring[i].rx_stats.drops;
8c0ab70a 3664 }
3ea73afa 3665 adapter->net_stats.rx_fifo_errors = rqdpc_total;
8c0ab70a
JDB		 3666 }
3667
3ea73afa
JDB		 3668 /* Note RNBC (Receive No Buffers Count) is an not an exact
3669 * drop count as the hardware FIFO might save the day. Thats
3670 * one of the reason for saving it in rx_fifo_errors, as its
3671 * potentially not a true drop.
3672 */
3673 adapter->net_stats.rx_fifo_errors += adapter->stats.rnbc;
3674
9d5c8243 3675 /* RLEC on some newer hardware can be incorrect so build
8c0ab70a 3676 * our own version based on RUC and ROC */
9d5c8243
AK		 3677 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3678 adapter->stats.crcerrs + adapter->stats.algnerrc +
3679 adapter->stats.ruc + adapter->stats.roc +
3680 adapter->stats.cexterr;
3681 adapter->net_stats.rx_length_errors = adapter->stats.ruc +
3682 adapter->stats.roc;
3683 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3684 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
3685 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3686
3687 /* Tx Errors */
3688 adapter->net_stats.tx_errors = adapter->stats.ecol +
3689 adapter->stats.latecol;
3690 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3691 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3692 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3693
3694 /* Tx Dropped needs to be maintained elsewhere */
3695
3696 /* Phy Stats */
3697 if (hw->phy.media_type == e1000_media_type_copper) {
3698 if ((adapter->link_speed == SPEED_1000) &&
73cd78f1 3699 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
9d5c8243
AK		 3700 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3701 adapter->phy_stats.idle_errors += phy_tmp;
3702 }
3703 }
3704
3705 /* Management Stats */
3706 adapter->stats.mgptc += rd32(E1000_MGTPTC);
3707 adapter->stats.mgprc += rd32(E1000_MGTPRC);
3708 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3709}
3710
9d5c8243
AK		 3711static irqreturn_t igb_msix_other(int irq, void *data)
3712{
3713 struct net_device *netdev = data;
3714 struct igb_adapter *adapter = netdev_priv(netdev);
3715 struct e1000_hw *hw = &adapter->hw;
844290e5 3716 u32 icr = rd32(E1000_ICR);
9d5c8243 3717
844290e5 3718 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083
AD		 3719
3720 if(icr & E1000_ICR_DOUTSYNC) {
3721 /* HW is reporting DMA is out of sync */
3722 adapter->stats.doosync++;
3723 }
eebbbdba 3724
4ae196df
AD		 3725 /* Check for a mailbox event */
3726 if (icr & E1000_ICR_VMMB)
3727 igb_msg_task(adapter);
3728
3729 if (icr & E1000_ICR_LSC) {
3730 hw->mac.get_link_status = 1;
3731 /* guard against interrupt when we're going down */
3732 if (!test_bit(__IGB_DOWN, &adapter->state))
3733 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3734 }
3735
3736 wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_VMMB);
844290e5 3737 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 3738
3739 return IRQ_HANDLED;
3740}
3741
3742static irqreturn_t igb_msix_tx(int irq, void *data)
3743{
3744 struct igb_ring *tx_ring = data;
3745 struct igb_adapter *adapter = tx_ring->adapter;
3746 struct e1000_hw *hw = &adapter->hw;
3747
421e02f0 3748#ifdef CONFIG_IGB_DCA
7dfc16fa 3749 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3750 igb_update_tx_dca(tx_ring);
3751#endif
73cd78f1 3752
9d5c8243
AK		 3753 tx_ring->total_bytes = 0;
3754 tx_ring->total_packets = 0;
661086df
PWJ		 3755
3756 /* auto mask will automatically reenable the interrupt when we write
3757 * EICS */
3b644cf6 3758 if (!igb_clean_tx_irq(tx_ring))
9d5c8243
AK		 3759 /* Ring was not completely cleaned, so fire another interrupt */
3760 wr32(E1000_EICS, tx_ring->eims_value);
661086df 3761 else
9d5c8243 3762 wr32(E1000_EIMS, tx_ring->eims_value);
661086df 3763
9d5c8243
AK		 3764 return IRQ_HANDLED;
3765}
3766
6eb5a7f1
AD		 3767static void igb_write_itr(struct igb_ring *ring)
3768{
3769 struct e1000_hw *hw = &ring->adapter->hw;
3770 if ((ring->adapter->itr_setting & 3) && ring->set_itr) {
3771 switch (hw->mac.type) {
3772 case e1000_82576:
73cd78f1 3773 wr32(ring->itr_register, ring->itr_val |
6eb5a7f1
AD		 3774 0x80000000);
3775 break;
3776 default:
73cd78f1 3777 wr32(ring->itr_register, ring->itr_val |
6eb5a7f1
AD		 3778 (ring->itr_val << 16));
3779 break;
3780 }
3781 ring->set_itr = 0;
3782 }
3783}
3784
9d5c8243
AK		 3785static irqreturn_t igb_msix_rx(int irq, void *data)
3786{
3787 struct igb_ring *rx_ring = data;
9d5c8243 3788
844290e5
PW		 3789 /* Write the ITR value calculated at the end of the
3790 * previous interrupt.
3791 */
9d5c8243 3792
6eb5a7f1 3793 igb_write_itr(rx_ring);
9d5c8243 3794
288379f0
BH		 3795 if (napi_schedule_prep(&rx_ring->napi))
3796 __napi_schedule(&rx_ring->napi);
844290e5 3797
421e02f0 3798#ifdef CONFIG_IGB_DCA
8d253320 3799 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3800 igb_update_rx_dca(rx_ring);
3801#endif
3802 return IRQ_HANDLED;
3803}
3804
421e02f0 3805#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 3806static void igb_update_rx_dca(struct igb_ring *rx_ring)
3807{
3808 u32 dca_rxctrl;
3809 struct igb_adapter *adapter = rx_ring->adapter;
3810 struct e1000_hw *hw = &adapter->hw;
3811 int cpu = get_cpu();
26bc19ec 3812 int q = rx_ring->reg_idx;
fe4506b6
JC		 3813
3814 if (rx_ring->cpu != cpu) {
3815 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
2d064c06
AD		 3816 if (hw->mac.type == e1000_82576) {
3817 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
92be7917 3818 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
2d064c06
AD		 3819 E1000_DCA_RXCTRL_CPUID_SHIFT;
3820 } else {
3821 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
92be7917 3822 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
2d064c06 3823 }
fe4506b6
JC		 3824 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
3825 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
3826 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
3827 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
3828 rx_ring->cpu = cpu;
3829 }
3830 put_cpu();
3831}
3832
3833static void igb_update_tx_dca(struct igb_ring *tx_ring)
3834{
3835 u32 dca_txctrl;
3836 struct igb_adapter *adapter = tx_ring->adapter;
3837 struct e1000_hw *hw = &adapter->hw;
3838 int cpu = get_cpu();
26bc19ec 3839 int q = tx_ring->reg_idx;
fe4506b6
JC		 3840
3841 if (tx_ring->cpu != cpu) {
3842 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
2d064c06
AD		 3843 if (hw->mac.type == e1000_82576) {
3844 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
92be7917 3845 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
2d064c06
AD		 3846 E1000_DCA_TXCTRL_CPUID_SHIFT;
3847 } else {
3848 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
92be7917 3849 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
2d064c06 3850 }
fe4506b6
JC		 3851 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
3852 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
3853 tx_ring->cpu = cpu;
3854 }
3855 put_cpu();
3856}
3857
3858static void igb_setup_dca(struct igb_adapter *adapter)
3859{
7e0e99ef 3860 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 3861 int i;
3862
7dfc16fa 3863 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 3864 return;
3865
7e0e99ef
AD		 3866 /* Always use CB2 mode, difference is masked in the CB driver. */
3867 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
3868
fe4506b6
JC		 3869 for (i = 0; i < adapter->num_tx_queues; i++) {
3870 adapter->tx_ring[i].cpu = -1;
3871 igb_update_tx_dca(&adapter->tx_ring[i]);
3872 }
3873 for (i = 0; i < adapter->num_rx_queues; i++) {
3874 adapter->rx_ring[i].cpu = -1;
3875 igb_update_rx_dca(&adapter->rx_ring[i]);
3876 }
3877}
3878
3879static int __igb_notify_dca(struct device *dev, void *data)
3880{
3881 struct net_device *netdev = dev_get_drvdata(dev);
3882 struct igb_adapter *adapter = netdev_priv(netdev);
3883 struct e1000_hw *hw = &adapter->hw;
3884 unsigned long event = *(unsigned long *)data;
3885
3886 switch (event) {
3887 case DCA_PROVIDER_ADD:
3888 /* if already enabled, don't do it again */
7dfc16fa 3889 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 3890 break;
fe4506b6
JC		 3891 /* Always use CB2 mode, difference is masked
3892 * in the CB driver. */
cbd347ad 3893 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
fe4506b6 3894 if (dca_add_requester(dev) == 0) {
bbd98fe4 3895 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 3896 dev_info(&adapter->pdev->dev, "DCA enabled\n");
3897 igb_setup_dca(adapter);
3898 break;
3899 }
3900 /* Fall Through since DCA is disabled. */
3901 case DCA_PROVIDER_REMOVE:
7dfc16fa 3902 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 3903 /* without this a class_device is left
3904 * hanging around in the sysfs model */
3905 dca_remove_requester(dev);
3906 dev_info(&adapter->pdev->dev, "DCA disabled\n");
7dfc16fa 3907 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 3908 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 3909 }
3910 break;
3911 }
bbd98fe4 3912
fe4506b6 3913 return 0;
9d5c8243
AK		 3914}
3915
fe4506b6
JC		 3916static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
3917 void *p)
3918{
3919 int ret_val;
3920
3921 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
3922 __igb_notify_dca);
3923
3924 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
3925}
421e02f0 3926#endif /* CONFIG_IGB_DCA */
9d5c8243 3927
4ae196df
AD		 3928static void igb_ping_all_vfs(struct igb_adapter *adapter)
3929{
3930 struct e1000_hw *hw = &adapter->hw;
3931 u32 ping;
3932 int i;
3933
3934 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
3935 ping = E1000_PF_CONTROL_MSG;
3936 if (adapter->vf_data[i].clear_to_send)
3937 ping |= E1000_VT_MSGTYPE_CTS;
3938 igb_write_mbx(hw, &ping, 1, i);
3939 }
3940}
3941
3942static int igb_set_vf_multicasts(struct igb_adapter *adapter,
3943 u32 *msgbuf, u32 vf)
3944{
3945 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
3946 u16 *hash_list = (u16 *)&msgbuf[1];
3947 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
3948 int i;
3949
3950 /* only up to 30 hash values supported */
3951 if (n > 30)
3952 n = 30;
3953
3954 /* salt away the number of multi cast addresses assigned
3955 * to this VF for later use to restore when the PF multi cast
3956 * list changes
3957 */
3958 vf_data->num_vf_mc_hashes = n;
3959
3960 /* VFs are limited to using the MTA hash table for their multicast
3961 * addresses */
3962 for (i = 0; i < n; i++)
3963 vf_data->vf_mc_hashes[i] = hash_list[i];;
3964
3965 /* Flush and reset the mta with the new values */
ff41f8dc 3966 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 3967
3968 return 0;
3969}
3970
3971static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
3972{
3973 struct e1000_hw *hw = &adapter->hw;
3974 struct vf_data_storage *vf_data;
3975 int i, j;
3976
3977 for (i = 0; i < adapter->vfs_allocated_count; i++) {
3978 vf_data = &adapter->vf_data[i];
75f4f382 3979 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
4ae196df
AD		 3980 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
3981 }
3982}
3983
3984static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
3985{
3986 struct e1000_hw *hw = &adapter->hw;
3987 u32 pool_mask, reg, vid;
3988 int i;
3989
3990 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
3991
3992 /* Find the vlan filter for this id */
3993 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
3994 reg = rd32(E1000_VLVF(i));
3995
3996 /* remove the vf from the pool */
3997 reg &= ~pool_mask;
3998
3999 /* if pool is empty then remove entry from vfta */
4000 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
4001 (reg & E1000_VLVF_VLANID_ENABLE)) {
4002 reg = 0;
4003 vid = reg & E1000_VLVF_VLANID_MASK;
4004 igb_vfta_set(hw, vid, false);
4005 }
4006
4007 wr32(E1000_VLVF(i), reg);
4008 }
4009}
4010
4011static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
4012{
4013 struct e1000_hw *hw = &adapter->hw;
4014 u32 reg, i;
4015
4016 /* It is an error to call this function when VFs are not enabled */
4017 if (!adapter->vfs_allocated_count)
4018 return -1;
4019
4020 /* Find the vlan filter for this id */
4021 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4022 reg = rd32(E1000_VLVF(i));
4023 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
4024 vid == (reg & E1000_VLVF_VLANID_MASK))
4025 break;
4026 }
4027
4028 if (add) {
4029 if (i == E1000_VLVF_ARRAY_SIZE) {
4030 /* Did not find a matching VLAN ID entry that was
4031 * enabled. Search for a free filter entry, i.e.
4032 * one without the enable bit set
4033 */
4034 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4035 reg = rd32(E1000_VLVF(i));
4036 if (!(reg & E1000_VLVF_VLANID_ENABLE))
4037 break;
4038 }
4039 }
4040 if (i < E1000_VLVF_ARRAY_SIZE) {
4041 /* Found an enabled/available entry */
4042 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
4043
4044 /* if !enabled we need to set this up in vfta */
4045 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
cad6d05f
AD		 4046 /* add VID to filter table, if bit already set
4047 * PF must have added it outside of table */
4048 if (igb_vfta_set(hw, vid, true))
4049 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT +
4050 adapter->vfs_allocated_count);
4ae196df
AD		 4051 reg |= E1000_VLVF_VLANID_ENABLE;
4052 }
cad6d05f
AD		 4053 reg &= ~E1000_VLVF_VLANID_MASK;
4054 reg |= vid;
4ae196df
AD		 4055
4056 wr32(E1000_VLVF(i), reg);
4057 return 0;
4058 }
4059 } else {
4060 if (i < E1000_VLVF_ARRAY_SIZE) {
4061 /* remove vf from the pool */
4062 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
4063 /* if pool is empty then remove entry from vfta */
4064 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
4065 reg = 0;
4066 igb_vfta_set(hw, vid, false);
4067 }
4068 wr32(E1000_VLVF(i), reg);
4069 return 0;
4070 }
4071 }
4072 return -1;
4073}
4074
4075static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
4076{
4077 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
4078 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
4079
4080 return igb_vlvf_set(adapter, vid, add, vf);
4081}
4082
4083static inline void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
4084{
4085 struct e1000_hw *hw = &adapter->hw;
4086
4087 /* disable mailbox functionality for vf */
4088 adapter->vf_data[vf].clear_to_send = false;
4089
4090 /* reset offloads to defaults */
4091 igb_set_vmolr(hw, vf);
4092
4093 /* reset vlans for device */
4094 igb_clear_vf_vfta(adapter, vf);
4095
4096 /* reset multicast table array for vf */
4097 adapter->vf_data[vf].num_vf_mc_hashes = 0;
4098
4099 /* Flush and reset the mta with the new values */
ff41f8dc 4100 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 4101}
4102
4103static inline void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4104{
4105 struct e1000_hw *hw = &adapter->hw;
4106 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 4107 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 4108 u32 reg, msgbuf[3];
4109 u8 *addr = (u8 *)(&msgbuf[1]);
4110
4111 /* process all the same items cleared in a function level reset */
4112 igb_vf_reset_event(adapter, vf);
4113
4114 /* set vf mac address */
ff41f8dc
AD		 4115 igb_rar_set(hw, vf_mac, rar_entry);
4116 igb_set_rah_pool(hw, vf, rar_entry);
4ae196df
AD		 4117
4118 /* enable transmit and receive for vf */
4119 reg = rd32(E1000_VFTE);
4120 wr32(E1000_VFTE, reg | (1 << vf));
4121 reg = rd32(E1000_VFRE);
4122 wr32(E1000_VFRE, reg | (1 << vf));
4123
4124 /* enable mailbox functionality for vf */
4125 adapter->vf_data[vf].clear_to_send = true;
4126
4127 /* reply to reset with ack and vf mac address */
4128 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
4129 memcpy(addr, vf_mac, 6);
4130 igb_write_mbx(hw, msgbuf, 3, vf);
4131}
4132
4133static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
4134{
4135 unsigned char *addr = (char *)&msg[1];
4136 int err = -1;
4137
4138 if (is_valid_ether_addr(addr))
4139 err = igb_set_vf_mac(adapter, vf, addr);
4140
4141 return err;
4142
4143}
4144
4145static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
4146{
4147 struct e1000_hw *hw = &adapter->hw;
4148 u32 msg = E1000_VT_MSGTYPE_NACK;
4149
4150 /* if device isn't clear to send it shouldn't be reading either */
4151 if (!adapter->vf_data[vf].clear_to_send)
4152 igb_write_mbx(hw, &msg, 1, vf);
4153}
4154
4155
4156static void igb_msg_task(struct igb_adapter *adapter)
4157{
4158 struct e1000_hw *hw = &adapter->hw;
4159 u32 vf;
4160
4161 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
4162 /* process any reset requests */
4163 if (!igb_check_for_rst(hw, vf)) {
4164 adapter->vf_data[vf].clear_to_send = false;
4165 igb_vf_reset_event(adapter, vf);
4166 }
4167
4168 /* process any messages pending */
4169 if (!igb_check_for_msg(hw, vf))
4170 igb_rcv_msg_from_vf(adapter, vf);
4171
4172 /* process any acks */
4173 if (!igb_check_for_ack(hw, vf))
4174 igb_rcv_ack_from_vf(adapter, vf);
4175
4176 }
4177}
4178
4179static int igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4180{
4181 u32 mbx_size = E1000_VFMAILBOX_SIZE;
4182 u32 msgbuf[mbx_size];
4183 struct e1000_hw *hw = &adapter->hw;
4184 s32 retval;
4185
4186 retval = igb_read_mbx(hw, msgbuf, mbx_size, vf);
4187
4188 if (retval)
4189 dev_err(&adapter->pdev->dev,
4190 "Error receiving message from VF\n");
4191
4192 /* this is a message we already processed, do nothing */
4193 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
4194 return retval;
4195
4196 /*
4197 * until the vf completes a reset it should not be
4198 * allowed to start any configuration.
4199 */
4200
4201 if (msgbuf[0] == E1000_VF_RESET) {
4202 igb_vf_reset_msg(adapter, vf);
4203
4204 return retval;
4205 }
4206
4207 if (!adapter->vf_data[vf].clear_to_send) {
4208 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4209 igb_write_mbx(hw, msgbuf, 1, vf);
4210 return retval;
4211 }
4212
4213 switch ((msgbuf[0] & 0xFFFF)) {
4214 case E1000_VF_SET_MAC_ADDR:
4215 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
4216 break;
4217 case E1000_VF_SET_MULTICAST:
4218 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
4219 break;
4220 case E1000_VF_SET_LPE:
4221 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
4222 break;
4223 case E1000_VF_SET_VLAN:
4224 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4225 break;
4226 default:
4227 dev_err(&adapter->pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4228 retval = -1;
4229 break;
4230 }
4231
4232 /* notify the VF of the results of what it sent us */
4233 if (retval)
4234 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4235 else
4236 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
4237
4238 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
4239
4240 igb_write_mbx(hw, msgbuf, 1, vf);
4241
4242 return retval;
4243}
4244
9d5c8243
AK		 4245/**
4246 * igb_intr_msi - Interrupt Handler
4247 * @irq: interrupt number
4248 * @data: pointer to a network interface device structure
4249 **/
4250static irqreturn_t igb_intr_msi(int irq, void *data)
4251{
4252 struct net_device *netdev = data;
4253 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 4254 struct e1000_hw *hw = &adapter->hw;
4255 /* read ICR disables interrupts using IAM */
4256 u32 icr = rd32(E1000_ICR);
4257
6eb5a7f1 4258 igb_write_itr(adapter->rx_ring);
9d5c8243 4259
dda0e083
AD		 4260 if(icr & E1000_ICR_DOUTSYNC) {
4261 /* HW is reporting DMA is out of sync */
4262 adapter->stats.doosync++;
4263 }
4264
9d5c8243
AK		 4265 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4266 hw->mac.get_link_status = 1;
4267 if (!test_bit(__IGB_DOWN, &adapter->state))
4268 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4269 }
4270
288379f0 4271 napi_schedule(&adapter->rx_ring[0].napi);
9d5c8243
AK		 4272
4273 return IRQ_HANDLED;
4274}
4275
4276/**
4a3c6433 4277 * igb_intr - Legacy Interrupt Handler
9d5c8243
AK		 4278 * @irq: interrupt number
4279 * @data: pointer to a network interface device structure
4280 **/
4281static irqreturn_t igb_intr(int irq, void *data)
4282{
4283 struct net_device *netdev = data;
4284 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 4285 struct e1000_hw *hw = &adapter->hw;
4286 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
4287 * need for the IMC write */
4288 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 4289 if (!icr)
4290 return IRQ_NONE; /* Not our interrupt */
4291
6eb5a7f1 4292 igb_write_itr(adapter->rx_ring);
9d5c8243
AK		 4293
4294 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
4295 * not set, then the adapter didn't send an interrupt */
4296 if (!(icr & E1000_ICR_INT_ASSERTED))
4297 return IRQ_NONE;
4298
dda0e083
AD		 4299 if(icr & E1000_ICR_DOUTSYNC) {
4300 /* HW is reporting DMA is out of sync */
4301 adapter->stats.doosync++;
4302 }
4303
9d5c8243
AK		 4304 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4305 hw->mac.get_link_status = 1;
4306 /* guard against interrupt when we're going down */
4307 if (!test_bit(__IGB_DOWN, &adapter->state))
4308 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4309 }
4310
288379f0 4311 napi_schedule(&adapter->rx_ring[0].napi);
9d5c8243
AK		 4312
4313 return IRQ_HANDLED;
4314}
4315
46544258 4316static inline void igb_rx_irq_enable(struct igb_ring *rx_ring)
9d5c8243 4317{
661086df 4318 struct igb_adapter *adapter = rx_ring->adapter;
46544258 4319 struct e1000_hw *hw = &adapter->hw;
9d5c8243 4320
46544258
AD		 4321 if (adapter->itr_setting & 3) {
4322 if (adapter->num_rx_queues == 1)
6eb5a7f1 4323 igb_set_itr(adapter);
46544258
AD		 4324 else
4325 igb_update_ring_itr(rx_ring);
9d5c8243
AK		 4326 }
4327
46544258
AD		 4328 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4329 if (adapter->msix_entries)
4330 wr32(E1000_EIMS, rx_ring->eims_value);
4331 else
4332 igb_irq_enable(adapter);
4333 }
9d5c8243
AK		 4334}
4335
46544258
AD		 4336/**
4337 * igb_poll - NAPI Rx polling callback
4338 * @napi: napi polling structure
4339 * @budget: count of how many packets we should handle
4340 **/
4341static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243
AK		 4342{
4343 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
9d5c8243
AK		 4344 int work_done = 0;
4345
421e02f0 4346#ifdef CONFIG_IGB_DCA
bd38e5d1 4347 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 4348 igb_update_rx_dca(rx_ring);
4349#endif
3b644cf6 4350 igb_clean_rx_irq_adv(rx_ring, &work_done, budget);
9d5c8243 4351
46544258
AD		 4352 if (rx_ring->buddy) {
4353#ifdef CONFIG_IGB_DCA
bd38e5d1 4354 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
46544258
AD		 4355 igb_update_tx_dca(rx_ring->buddy);
4356#endif
4357 if (!igb_clean_tx_irq(rx_ring->buddy))
4358 work_done = budget;
4359 }
4360
9d5c8243 4361 /* If not enough Rx work done, exit the polling mode */
5e6d5b17 4362 if (work_done < budget) {
288379f0 4363 napi_complete(napi);
46544258 4364 igb_rx_irq_enable(rx_ring);
9d5c8243
AK		 4365 }
4366
46544258 4367 return work_done;
9d5c8243 4368}
6d8126f9 4369
33af6bcc
PO		 4370/**
4371 * igb_hwtstamp - utility function which checks for TX time stamp
4372 * @adapter: board private structure
4373 * @skb: packet that was just sent
4374 *
4375 * If we were asked to do hardware stamping and such a time stamp is
4376 * available, then it must have been for this skb here because we only
4377 * allow only one such packet into the queue.
4378 */
4379static void igb_tx_hwtstamp(struct igb_adapter *adapter, struct sk_buff *skb)
4380{
4381 union skb_shared_tx *shtx = skb_tx(skb);
4382 struct e1000_hw *hw = &adapter->hw;
4383
4384 if (unlikely(shtx->hardware)) {
4385 u32 valid = rd32(E1000_TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID;
4386 if (valid) {
4387 u64 regval = rd32(E1000_TXSTMPL);
4388 u64 ns;
4389 struct skb_shared_hwtstamps shhwtstamps;
4390
4391 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
4392 regval |= (u64)rd32(E1000_TXSTMPH) << 32;
4393 ns = timecounter_cyc2time(&adapter->clock,
4394 regval);
4395 timecompare_update(&adapter->compare, ns);
4396 shhwtstamps.hwtstamp = ns_to_ktime(ns);
4397 shhwtstamps.syststamp =
4398 timecompare_transform(&adapter->compare, ns);
4399 skb_tstamp_tx(skb, &shhwtstamps);
4400 }
33af6bcc
PO		 4401 }
4402}
4403
9d5c8243
AK		 4404/**
4405 * igb_clean_tx_irq - Reclaim resources after transmit completes
4406 * @adapter: board private structure
4407 * returns true if ring is completely cleaned
4408 **/
3b644cf6 4409static bool igb_clean_tx_irq(struct igb_ring *tx_ring)
9d5c8243 4410{
3b644cf6 4411 struct igb_adapter *adapter = tx_ring->adapter;
3b644cf6 4412 struct net_device *netdev = adapter->netdev;
0e014cb1 4413 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 4414 struct igb_buffer *buffer_info;
4415 struct sk_buff *skb;
0e014cb1 4416 union e1000_adv_tx_desc *tx_desc, *eop_desc;
9d5c8243 4417 unsigned int total_bytes = 0, total_packets = 0;
0e014cb1
AD		 4418 unsigned int i, eop, count = 0;
4419 bool cleaned = false;
9d5c8243 4420
9d5c8243 4421 i = tx_ring->next_to_clean;
0e014cb1
AD		 4422 eop = tx_ring->buffer_info[i].next_to_watch;
4423 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4424
4425 while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) &&
4426 (count < tx_ring->count)) {
4427 for (cleaned = false; !cleaned; count++) {
4428 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
9d5c8243 4429 buffer_info = &tx_ring->buffer_info[i];
0e014cb1 4430 cleaned = (i == eop);
9d5c8243
AK		 4431 skb = buffer_info->skb;
4432
4433 if (skb) {
4434 unsigned int segs, bytecount;
4435 /* gso_segs is currently only valid for tcp */
4436 segs = skb_shinfo(skb)->gso_segs ?: 1;
4437 /* multiply data chunks by size of headers */
4438 bytecount = ((segs - 1) * skb_headlen(skb)) +
4439 skb->len;
4440 total_packets += segs;
4441 total_bytes += bytecount;
33af6bcc
PO		 4442
4443 igb_tx_hwtstamp(adapter, skb);
9d5c8243
AK		 4444 }
4445
4446 igb_unmap_and_free_tx_resource(adapter, buffer_info);
0e014cb1 4447 tx_desc->wb.status = 0;
9d5c8243
AK		 4448
4449 i++;
4450 if (i == tx_ring->count)
4451 i = 0;
9d5c8243 4452 }
0e014cb1
AD		 4453 eop = tx_ring->buffer_info[i].next_to_watch;
4454 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4455 }
4456
9d5c8243
AK		 4457 tx_ring->next_to_clean = i;
4458
fc7d345d 4459 if (unlikely(count &&
9d5c8243 4460 netif_carrier_ok(netdev) &&
c493ea45 4461 igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
9d5c8243
AK		 4462 /* Make sure that anybody stopping the queue after this
4463 * sees the new next_to_clean.
4464 */
4465 smp_mb();
661086df
PWJ		 4466 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
4467 !(test_bit(__IGB_DOWN, &adapter->state))) {
4468 netif_wake_subqueue(netdev, tx_ring->queue_index);
4469 ++adapter->restart_queue;
4470 }
9d5c8243
AK		 4471 }
4472
4473 if (tx_ring->detect_tx_hung) {
4474 /* Detect a transmit hang in hardware, this serializes the
4475 * check with the clearing of time_stamp and movement of i */
4476 tx_ring->detect_tx_hung = false;
4477 if (tx_ring->buffer_info[i].time_stamp &&
4478 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
4479 (adapter->tx_timeout_factor * HZ))
4480 && !(rd32(E1000_STATUS) &
4481 E1000_STATUS_TXOFF)) {
4482
9d5c8243
AK		 4483 /* detected Tx unit hang */
4484 dev_err(&adapter->pdev->dev,
4485 "Detected Tx Unit Hang\n"
2d064c06 4486 " Tx Queue <%d>\n"
9d5c8243
AK		 4487 " TDH <%x>\n"
4488 " TDT <%x>\n"
4489 " next_to_use <%x>\n"
4490 " next_to_clean <%x>\n"
9d5c8243
AK		 4491 "buffer_info[next_to_clean]\n"
4492 " time_stamp <%lx>\n"
0e014cb1 4493 " next_to_watch <%x>\n"
9d5c8243
AK		 4494 " jiffies <%lx>\n"
4495 " desc.status <%x>\n",
2d064c06 4496 tx_ring->queue_index,
9d5c8243
AK		 4497 readl(adapter->hw.hw_addr + tx_ring->head),
4498 readl(adapter->hw.hw_addr + tx_ring->tail),
4499 tx_ring->next_to_use,
4500 tx_ring->next_to_clean,
9d5c8243 4501 tx_ring->buffer_info[i].time_stamp,
0e014cb1 4502 eop,
9d5c8243 4503 jiffies,
0e014cb1 4504 eop_desc->wb.status);
661086df 4505 netif_stop_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 4506 }
4507 }
4508 tx_ring->total_bytes += total_bytes;
4509 tx_ring->total_packets += total_packets;
e21ed353
AD		 4510 tx_ring->tx_stats.bytes += total_bytes;
4511 tx_ring->tx_stats.packets += total_packets;
9d5c8243
AK		 4512 adapter->net_stats.tx_bytes += total_bytes;
4513 adapter->net_stats.tx_packets += total_packets;
0e014cb1 4514 return (count < tx_ring->count);
9d5c8243
AK		 4515}
4516
9d5c8243
AK		 4517/**
4518 * igb_receive_skb - helper function to handle rx indications
eebbbdba 4519 * @ring: pointer to receive ring receving this packet
9d5c8243 4520 * @status: descriptor status field as written by hardware
73cd78f1 4521 * @rx_desc: receive descriptor containing vlan and type information.
9d5c8243
AK		 4522 * @skb: pointer to sk_buff to be indicated to stack
4523 **/
d3352520
AD		 4524static void igb_receive_skb(struct igb_ring *ring, u8 status,
4525 union e1000_adv_rx_desc * rx_desc,
4526 struct sk_buff *skb)
4527{
4528 struct igb_adapter * adapter = ring->adapter;
4529 bool vlan_extracted = (adapter->vlgrp && (status & E1000_RXD_STAT_VP));
4530
0c8dfc83 4531 skb_record_rx_queue(skb, ring->queue_index);
182ff8df
AD		 4532 if (vlan_extracted)
4533 vlan_gro_receive(&ring->napi, adapter->vlgrp,
4534 le16_to_cpu(rx_desc->wb.upper.vlan),
4535 skb);
4536 else
4537 napi_gro_receive(&ring->napi, skb);
9d5c8243
AK		 4538}
4539
9d5c8243
AK		 4540static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
4541 u32 status_err, struct sk_buff *skb)
4542{
4543 skb->ip_summed = CHECKSUM_NONE;
4544
4545 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
7beb0146
AD		 4546 if ((status_err & E1000_RXD_STAT_IXSM) ||
4547 (adapter->flags & IGB_FLAG_RX_CSUM_DISABLED))
9d5c8243
AK		 4548 return;
4549 /* TCP/UDP checksum error bit is set */
4550 if (status_err &
4551 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
b9473560
JB		 4552 /*
4553 * work around errata with sctp packets where the TCPE aka
4554 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
4555 * packets, (aka let the stack check the crc32c)
4556 */
4557 if (!((adapter->hw.mac.type == e1000_82576) &&
4558 (skb->len == 60)))
4559 adapter->hw_csum_err++;
9d5c8243 4560 /* let the stack verify checksum errors */
9d5c8243
AK		 4561 return;
4562 }
4563 /* It must be a TCP or UDP packet with a valid checksum */
4564 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
4565 skb->ip_summed = CHECKSUM_UNNECESSARY;
4566
b9473560 4567 dev_dbg(&adapter->pdev->dev, "cksum success: bits %08X\n", status_err);
9d5c8243
AK		 4568 adapter->hw_csum_good++;
4569}
4570
2d94d8ab
AD		 4571static inline u16 igb_get_hlen(struct igb_adapter *adapter,
4572 union e1000_adv_rx_desc *rx_desc)
4573{
4574 /* HW will not DMA in data larger than the given buffer, even if it
4575 * parses the (NFS, of course) header to be larger. In that case, it
4576 * fills the header buffer and spills the rest into the page.
4577 */
4578 u16 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
4579 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
4580 if (hlen > adapter->rx_ps_hdr_size)
4581 hlen = adapter->rx_ps_hdr_size;
4582 return hlen;
4583}
4584
3b644cf6
MW		 4585static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring,
4586 int *work_done, int budget)
9d5c8243 4587{
3b644cf6 4588 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 4589 struct net_device *netdev = adapter->netdev;
33af6bcc 4590 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 4591 struct pci_dev *pdev = adapter->pdev;
4592 union e1000_adv_rx_desc *rx_desc , *next_rxd;
4593 struct igb_buffer *buffer_info , *next_buffer;
4594 struct sk_buff *skb;
9d5c8243
AK		 4595 bool cleaned = false;
4596 int cleaned_count = 0;
4597 unsigned int total_bytes = 0, total_packets = 0;
73cd78f1 4598 unsigned int i;
2d94d8ab
AD		 4599 u32 staterr;
4600 u16 length;
9d5c8243
AK		 4601
4602 i = rx_ring->next_to_clean;
69d3ca53 4603 buffer_info = &rx_ring->buffer_info[i];
9d5c8243
AK		 4604 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4605 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4606
4607 while (staterr & E1000_RXD_STAT_DD) {
4608 if (*work_done >= budget)
4609 break;
4610 (*work_done)++;
9d5c8243 4611
69d3ca53
AD		 4612 skb = buffer_info->skb;
4613 prefetch(skb->data - NET_IP_ALIGN);
4614 buffer_info->skb = NULL;
4615
4616 i++;
4617 if (i == rx_ring->count)
4618 i = 0;
4619 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
4620 prefetch(next_rxd);
4621 next_buffer = &rx_ring->buffer_info[i];
9d5c8243
AK		 4622
4623 length = le16_to_cpu(rx_desc->wb.upper.length);
4624 cleaned = true;
4625 cleaned_count++;
4626
91615f76 4627 /* this is the fast path for the non-packet split case */
bf36c1a0
AD		 4628 if (!adapter->rx_ps_hdr_size) {
4629 pci_unmap_single(pdev, buffer_info->dma,
91615f76 4630 adapter->rx_buffer_len,
bf36c1a0 4631 PCI_DMA_FROMDEVICE);
91615f76 4632 buffer_info->dma = 0;
bf36c1a0
AD		 4633 skb_put(skb, length);
4634 goto send_up;
9d5c8243
AK		 4635 }
4636
2d94d8ab
AD		 4637 if (buffer_info->dma) {
4638 u16 hlen = igb_get_hlen(adapter, rx_desc);
bf36c1a0 4639 pci_unmap_single(pdev, buffer_info->dma,
91615f76 4640 adapter->rx_ps_hdr_size,
bf36c1a0 4641 PCI_DMA_FROMDEVICE);
91615f76 4642 buffer_info->dma = 0;
bf36c1a0
AD		 4643 skb_put(skb, hlen);
4644 }
4645
4646 if (length) {
9d5c8243 4647 pci_unmap_page(pdev, buffer_info->page_dma,
bf36c1a0 4648 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9d5c8243 4649 buffer_info->page_dma = 0;
bf36c1a0
AD		 4650
4651 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
4652 buffer_info->page,
4653 buffer_info->page_offset,
4654 length);
4655
4656 if ((adapter->rx_buffer_len > (PAGE_SIZE / 2)) ||
4657 (page_count(buffer_info->page) != 1))
4658 buffer_info->page = NULL;
4659 else
4660 get_page(buffer_info->page);
9d5c8243
AK		 4661
4662 skb->len += length;
4663 skb->data_len += length;
9d5c8243 4664
bf36c1a0 4665 skb->truesize += length;
9d5c8243 4666 }
9d5c8243 4667
bf36c1a0 4668 if (!(staterr & E1000_RXD_STAT_EOP)) {
b2d56536
AD		 4669 buffer_info->skb = next_buffer->skb;
4670 buffer_info->dma = next_buffer->dma;
4671 next_buffer->skb = skb;
4672 next_buffer->dma = 0;
bf36c1a0
AD		 4673 goto next_desc;
4674 }
69d3ca53 4675send_up:
33af6bcc
PO		 4676 /*
4677 * If this bit is set, then the RX registers contain
4678 * the time stamp. No other packet will be time
4679 * stamped until we read these registers, so read the
4680 * registers to make them available again. Because
4681 * only one packet can be time stamped at a time, we
4682 * know that the register values must belong to this
4683 * one here and therefore we don't need to compare
4684 * any of the additional attributes stored for it.
4685 *
4686 * If nothing went wrong, then it should have a
4687 * skb_shared_tx that we can turn into a
4688 * skb_shared_hwtstamps.
4689 *
4690 * TODO: can time stamping be triggered (thus locking
4691 * the registers) without the packet reaching this point
4692 * here? In that case RX time stamping would get stuck.
4693 *
4694 * TODO: in "time stamp all packets" mode this bit is
4695 * not set. Need a global flag for this mode and then
4696 * always read the registers. Cannot be done without
4697 * a race condition.
4698 */
4699 if (unlikely(staterr & E1000_RXD_STAT_TS)) {
4700 u64 regval;
4701 u64 ns;
4702 struct skb_shared_hwtstamps *shhwtstamps =
4703 skb_hwtstamps(skb);
4704
4705 WARN(!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID),
4706 "igb: no RX time stamp available for time stamped packet");
4707 regval = rd32(E1000_RXSTMPL);
4708 regval |= (u64)rd32(E1000_RXSTMPH) << 32;
4709 ns = timecounter_cyc2time(&adapter->clock, regval);
4710 timecompare_update(&adapter->compare, ns);
4711 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
4712 shhwtstamps->hwtstamp = ns_to_ktime(ns);
4713 shhwtstamps->syststamp =
4714 timecompare_transform(&adapter->compare, ns);
4715 }
4716
9d5c8243
AK		 4717 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
4718 dev_kfree_skb_irq(skb);
4719 goto next_desc;
4720 }
9d5c8243
AK		 4721
4722 total_bytes += skb->len;
4723 total_packets++;
4724
4725 igb_rx_checksum_adv(adapter, staterr, skb);
4726
4727 skb->protocol = eth_type_trans(skb, netdev);
4728
d3352520 4729 igb_receive_skb(rx_ring, staterr, rx_desc, skb);
9d5c8243 4730
9d5c8243
AK		 4731next_desc:
4732 rx_desc->wb.upper.status_error = 0;
4733
4734 /* return some buffers to hardware, one at a time is too slow */
4735 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
3b644cf6 4736 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 4737 cleaned_count = 0;
4738 }
4739
4740 /* use prefetched values */
4741 rx_desc = next_rxd;
4742 buffer_info = next_buffer;
9d5c8243
AK		 4743 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4744 }
bf36c1a0 4745
9d5c8243 4746 rx_ring->next_to_clean = i;
c493ea45 4747 cleaned_count = igb_desc_unused(rx_ring);
9d5c8243
AK		 4748
4749 if (cleaned_count)
3b644cf6 4750 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 4751
4752 rx_ring->total_packets += total_packets;
4753 rx_ring->total_bytes += total_bytes;
4754 rx_ring->rx_stats.packets += total_packets;
4755 rx_ring->rx_stats.bytes += total_bytes;
4756 adapter->net_stats.rx_bytes += total_bytes;
4757 adapter->net_stats.rx_packets += total_packets;
4758 return cleaned;
4759}
4760
9d5c8243
AK		 4761/**
4762 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
4763 * @adapter: address of board private structure
4764 **/
3b644cf6 4765static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
9d5c8243
AK		 4766 int cleaned_count)
4767{
3b644cf6 4768 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 4769 struct net_device *netdev = adapter->netdev;
4770 struct pci_dev *pdev = adapter->pdev;
4771 union e1000_adv_rx_desc *rx_desc;
4772 struct igb_buffer *buffer_info;
4773 struct sk_buff *skb;
4774 unsigned int i;
db761762 4775 int bufsz;
9d5c8243
AK		 4776
4777 i = rx_ring->next_to_use;
4778 buffer_info = &rx_ring->buffer_info[i];
4779
db761762
AD		 4780 if (adapter->rx_ps_hdr_size)
4781 bufsz = adapter->rx_ps_hdr_size;
4782 else
4783 bufsz = adapter->rx_buffer_len;
db761762 4784
9d5c8243
AK		 4785 while (cleaned_count--) {
4786 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4787
bf36c1a0 4788 if (adapter->rx_ps_hdr_size && !buffer_info->page_dma) {
9d5c8243 4789 if (!buffer_info->page) {
bf36c1a0
AD		 4790 buffer_info->page = alloc_page(GFP_ATOMIC);
4791 if (!buffer_info->page) {
4792 adapter->alloc_rx_buff_failed++;
4793 goto no_buffers;
4794 }
4795 buffer_info->page_offset = 0;
4796 } else {
4797 buffer_info->page_offset ^= PAGE_SIZE / 2;
9d5c8243
AK		 4798 }
4799 buffer_info->page_dma =
db761762 4800 pci_map_page(pdev, buffer_info->page,
bf36c1a0
AD		 4801 buffer_info->page_offset,
4802 PAGE_SIZE / 2,
9d5c8243
AK		 4803 PCI_DMA_FROMDEVICE);
4804 }
4805
4806 if (!buffer_info->skb) {
91615f76 4807 skb = netdev_alloc_skb(netdev, bufsz + NET_IP_ALIGN);
9d5c8243
AK		 4808 if (!skb) {
4809 adapter->alloc_rx_buff_failed++;
4810 goto no_buffers;
4811 }
4812
4813 /* Make buffer alignment 2 beyond a 16 byte boundary
4814 * this will result in a 16 byte aligned IP header after
4815 * the 14 byte MAC header is removed
4816 */
4817 skb_reserve(skb, NET_IP_ALIGN);
4818
4819 buffer_info->skb = skb;
4820 buffer_info->dma = pci_map_single(pdev, skb->data,
4821 bufsz,
4822 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 4823 }
4824 /* Refresh the desc even if buffer_addrs didn't change because
4825 * each write-back erases this info. */
4826 if (adapter->rx_ps_hdr_size) {
4827 rx_desc->read.pkt_addr =
4828 cpu_to_le64(buffer_info->page_dma);
4829 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
4830 } else {
4831 rx_desc->read.pkt_addr =
4832 cpu_to_le64(buffer_info->dma);
4833 rx_desc->read.hdr_addr = 0;
4834 }
4835
4836 i++;
4837 if (i == rx_ring->count)
4838 i = 0;
4839 buffer_info = &rx_ring->buffer_info[i];
4840 }
4841
4842no_buffers:
4843 if (rx_ring->next_to_use != i) {
4844 rx_ring->next_to_use = i;
4845 if (i == 0)
4846 i = (rx_ring->count - 1);
4847 else
4848 i--;
4849
4850 /* Force memory writes to complete before letting h/w
4851 * know there are new descriptors to fetch. (Only
4852 * applicable for weak-ordered memory model archs,
4853 * such as IA-64). */
4854 wmb();
4855 writel(i, adapter->hw.hw_addr + rx_ring->tail);
4856 }
4857}
4858
4859/**
4860 * igb_mii_ioctl -
4861 * @netdev:
4862 * @ifreq:
4863 * @cmd:
4864 **/
4865static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4866{
4867 struct igb_adapter *adapter = netdev_priv(netdev);
4868 struct mii_ioctl_data *data = if_mii(ifr);
4869
4870 if (adapter->hw.phy.media_type != e1000_media_type_copper)
4871 return -EOPNOTSUPP;
4872
4873 switch (cmd) {
4874 case SIOCGMIIPHY:
4875 data->phy_id = adapter->hw.phy.addr;
4876 break;
4877 case SIOCGMIIREG:
4878 if (!capable(CAP_NET_ADMIN))
4879 return -EPERM;
f5f4cf08
AD		 4880 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
4881 &data->val_out))
9d5c8243
AK		 4882 return -EIO;
4883 break;
4884 case SIOCSMIIREG:
4885 default:
4886 return -EOPNOTSUPP;
4887 }
4888 return 0;
4889}
4890
c6cb090b
PO		 4891/**
4892 * igb_hwtstamp_ioctl - control hardware time stamping
4893 * @netdev:
4894 * @ifreq:
4895 * @cmd:
4896 *
33af6bcc
PO		 4897 * Outgoing time stamping can be enabled and disabled. Play nice and
4898 * disable it when requested, although it shouldn't case any overhead
4899 * when no packet needs it. At most one packet in the queue may be
4900 * marked for time stamping, otherwise it would be impossible to tell
4901 * for sure to which packet the hardware time stamp belongs.
4902 *
4903 * Incoming time stamping has to be configured via the hardware
4904 * filters. Not all combinations are supported, in particular event
4905 * type has to be specified. Matching the kind of event packet is
4906 * not supported, with the exception of "all V2 events regardless of
4907 * level 2 or 4".
4908 *
c6cb090b
PO		 4909 **/
4910static int igb_hwtstamp_ioctl(struct net_device *netdev,
4911 struct ifreq *ifr, int cmd)
4912{
33af6bcc
PO		 4913 struct igb_adapter *adapter = netdev_priv(netdev);
4914 struct e1000_hw *hw = &adapter->hw;
c6cb090b 4915 struct hwtstamp_config config;
33af6bcc
PO		 4916 u32 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
4917 u32 tsync_rx_ctl_bit = E1000_TSYNCRXCTL_ENABLED;
4918 u32 tsync_rx_ctl_type = 0;
4919 u32 tsync_rx_cfg = 0;
4920 int is_l4 = 0;
4921 int is_l2 = 0;
4922 short port = 319; /* PTP */
4923 u32 regval;
c6cb090b
PO		 4924
4925 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
4926 return -EFAULT;
4927
4928 /* reserved for future extensions */
4929 if (config.flags)
4930 return -EINVAL;
4931
33af6bcc
PO		 4932 switch (config.tx_type) {
4933 case HWTSTAMP_TX_OFF:
4934 tsync_tx_ctl_bit = 0;
4935 break;
4936 case HWTSTAMP_TX_ON:
4937 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
4938 break;
4939 default:
4940 return -ERANGE;
4941 }
4942
4943 switch (config.rx_filter) {
4944 case HWTSTAMP_FILTER_NONE:
4945 tsync_rx_ctl_bit = 0;
4946 break;
4947 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4948 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4949 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4950 case HWTSTAMP_FILTER_ALL:
4951 /*
4952 * register TSYNCRXCFG must be set, therefore it is not
4953 * possible to time stamp both Sync and Delay_Req messages
4954 * => fall back to time stamping all packets
4955 */
4956 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_ALL;
4957 config.rx_filter = HWTSTAMP_FILTER_ALL;
4958 break;
4959 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4960 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
4961 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
4962 is_l4 = 1;
4963 break;
4964 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4965 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
4966 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
4967 is_l4 = 1;
4968 break;
4969 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4970 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4971 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
4972 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE;
4973 is_l2 = 1;
4974 is_l4 = 1;
4975 config.rx_filter = HWTSTAMP_FILTER_SOME;
4976 break;
4977 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4978 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4979 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
4980 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE;
4981 is_l2 = 1;
4982 is_l4 = 1;
4983 config.rx_filter = HWTSTAMP_FILTER_SOME;
4984 break;
4985 case HWTSTAMP_FILTER_PTP_V2_EVENT:
4986 case HWTSTAMP_FILTER_PTP_V2_SYNC:
4987 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4988 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_EVENT_V2;
4989 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
4990 is_l2 = 1;
4991 break;
4992 default:
4993 return -ERANGE;
4994 }
4995
4996 /* enable/disable TX */
4997 regval = rd32(E1000_TSYNCTXCTL);
4998 regval = (regval & ~E1000_TSYNCTXCTL_ENABLED) | tsync_tx_ctl_bit;
4999 wr32(E1000_TSYNCTXCTL, regval);
5000
5001 /* enable/disable RX, define which PTP packets are time stamped */
5002 regval = rd32(E1000_TSYNCRXCTL);
5003 regval = (regval & ~E1000_TSYNCRXCTL_ENABLED) | tsync_rx_ctl_bit;
5004 regval = (regval & ~0xE) | tsync_rx_ctl_type;
5005 wr32(E1000_TSYNCRXCTL, regval);
5006 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
5007
5008 /*
5009 * Ethertype Filter Queue Filter[0][15:0] = 0x88F7
5010 * (Ethertype to filter on)
5011 * Ethertype Filter Queue Filter[0][26] = 0x1 (Enable filter)
5012 * Ethertype Filter Queue Filter[0][30] = 0x1 (Enable Timestamping)
5013 */
5014 wr32(E1000_ETQF0, is_l2 ? 0x440088f7 : 0);
5015
5016 /* L4 Queue Filter[0]: only filter by source and destination port */
5017 wr32(E1000_SPQF0, htons(port));
5018 wr32(E1000_IMIREXT(0), is_l4 ?
5019 ((1<<12) | (1<<19) /* bypass size and control flags */) : 0);
5020 wr32(E1000_IMIR(0), is_l4 ?
5021 (htons(port)
5022 | (0<<16) /* immediate interrupt disabled */
5023 | 0 /* (1<<17) bit cleared: do not bypass
5024 destination port check */)
5025 : 0);
5026 wr32(E1000_FTQF0, is_l4 ?
5027 (0x11 /* UDP */
5028 | (1<<15) /* VF not compared */
5029 | (1<<27) /* Enable Timestamping */
5030 | (7<<28) /* only source port filter enabled,
5031 source/target address and protocol
5032 masked */)
5033 : ((1<<15) | (15<<28) /* all mask bits set = filter not
5034 enabled */));
5035
5036 wrfl();
5037
5038 adapter->hwtstamp_config = config;
5039
5040 /* clear TX/RX time stamp registers, just to be sure */
5041 regval = rd32(E1000_TXSTMPH);
5042 regval = rd32(E1000_RXSTMPH);
c6cb090b 5043
33af6bcc
PO		 5044 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
5045 -EFAULT : 0;
c6cb090b
PO		 5046}
5047
9d5c8243
AK		 5048/**
5049 * igb_ioctl -
5050 * @netdev:
5051 * @ifreq:
5052 * @cmd:
5053 **/
5054static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5055{
5056 switch (cmd) {
5057 case SIOCGMIIPHY:
5058 case SIOCGMIIREG:
5059 case SIOCSMIIREG:
5060 return igb_mii_ioctl(netdev, ifr, cmd);
c6cb090b
PO		 5061 case SIOCSHWTSTAMP:
5062 return igb_hwtstamp_ioctl(netdev, ifr, cmd);
9d5c8243
AK		 5063 default:
5064 return -EOPNOTSUPP;
5065 }
5066}
5067
009bc06e
AD		 5068s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
5069{
5070 struct igb_adapter *adapter = hw->back;
5071 u16 cap_offset;
5072
5073 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
5074 if (!cap_offset)
5075 return -E1000_ERR_CONFIG;
5076
5077 pci_read_config_word(adapter->pdev, cap_offset + reg, value);
5078
5079 return 0;
5080}
5081
5082s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
5083{
5084 struct igb_adapter *adapter = hw->back;
5085 u16 cap_offset;
5086
5087 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
5088 if (!cap_offset)
5089 return -E1000_ERR_CONFIG;
5090
5091 pci_write_config_word(adapter->pdev, cap_offset + reg, *value);
5092
5093 return 0;
5094}
5095
9d5c8243
AK		 5096static void igb_vlan_rx_register(struct net_device *netdev,
5097 struct vlan_group *grp)
5098{
5099 struct igb_adapter *adapter = netdev_priv(netdev);
5100 struct e1000_hw *hw = &adapter->hw;
5101 u32 ctrl, rctl;
5102
5103 igb_irq_disable(adapter);
5104 adapter->vlgrp = grp;
5105
5106 if (grp) {
5107 /* enable VLAN tag insert/strip */
5108 ctrl = rd32(E1000_CTRL);
5109 ctrl |= E1000_CTRL_VME;
5110 wr32(E1000_CTRL, ctrl);
5111
5112 /* enable VLAN receive filtering */
5113 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 5114 rctl &= ~E1000_RCTL_CFIEN;
5115 wr32(E1000_RCTL, rctl);
5116 igb_update_mng_vlan(adapter);
9d5c8243
AK		 5117 } else {
5118 /* disable VLAN tag insert/strip */
5119 ctrl = rd32(E1000_CTRL);
5120 ctrl &= ~E1000_CTRL_VME;
5121 wr32(E1000_CTRL, ctrl);
5122
9d5c8243
AK		 5123 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
5124 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
5125 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
5126 }
9d5c8243
AK		 5127 }
5128
e1739522
AD		 5129 igb_rlpml_set(adapter);
5130
9d5c8243
AK		 5131 if (!test_bit(__IGB_DOWN, &adapter->state))
5132 igb_irq_enable(adapter);
5133}
5134
5135static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
5136{
5137 struct igb_adapter *adapter = netdev_priv(netdev);
5138 struct e1000_hw *hw = &adapter->hw;
4ae196df 5139 int pf_id = adapter->vfs_allocated_count;
9d5c8243 5140
28b0759c 5141 if ((hw->mng_cookie.status &
9d5c8243
AK		 5142 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
5143 (vid == adapter->mng_vlan_id))
5144 return;
4ae196df
AD		 5145
5146 /* add vid to vlvf if sr-iov is enabled,
5147 * if that fails add directly to filter table */
5148 if (igb_vlvf_set(adapter, vid, true, pf_id))
5149 igb_vfta_set(hw, vid, true);
5150
9d5c8243
AK		 5151}
5152
5153static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
5154{
5155 struct igb_adapter *adapter = netdev_priv(netdev);
5156 struct e1000_hw *hw = &adapter->hw;
4ae196df 5157 int pf_id = adapter->vfs_allocated_count;
9d5c8243
AK		 5158
5159 igb_irq_disable(adapter);
5160 vlan_group_set_device(adapter->vlgrp, vid, NULL);
5161
5162 if (!test_bit(__IGB_DOWN, &adapter->state))
5163 igb_irq_enable(adapter);
5164
5165 if ((adapter->hw.mng_cookie.status &
5166 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
5167 (vid == adapter->mng_vlan_id)) {
5168 /* release control to f/w */
5169 igb_release_hw_control(adapter);
5170 return;
5171 }
5172
4ae196df
AD		 5173 /* remove vid from vlvf if sr-iov is enabled,
5174 * if not in vlvf remove from vfta */
5175 if (igb_vlvf_set(adapter, vid, false, pf_id))
5176 igb_vfta_set(hw, vid, false);
9d5c8243
AK		 5177}
5178
5179static void igb_restore_vlan(struct igb_adapter *adapter)
5180{
5181 igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
5182
5183 if (adapter->vlgrp) {
5184 u16 vid;
5185 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
5186 if (!vlan_group_get_device(adapter->vlgrp, vid))
5187 continue;
5188 igb_vlan_rx_add_vid(adapter->netdev, vid);
5189 }
5190 }
5191}
5192
5193int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
5194{
5195 struct e1000_mac_info *mac = &adapter->hw.mac;
5196
5197 mac->autoneg = 0;
5198
9d5c8243
AK		 5199 switch (spddplx) {
5200 case SPEED_10 + DUPLEX_HALF:
5201 mac->forced_speed_duplex = ADVERTISE_10_HALF;
5202 break;
5203 case SPEED_10 + DUPLEX_FULL:
5204 mac->forced_speed_duplex = ADVERTISE_10_FULL;
5205 break;
5206 case SPEED_100 + DUPLEX_HALF:
5207 mac->forced_speed_duplex = ADVERTISE_100_HALF;
5208 break;
5209 case SPEED_100 + DUPLEX_FULL:
5210 mac->forced_speed_duplex = ADVERTISE_100_FULL;
5211 break;
5212 case SPEED_1000 + DUPLEX_FULL:
5213 mac->autoneg = 1;
5214 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
5215 break;
5216 case SPEED_1000 + DUPLEX_HALF: /* not supported */
5217 default:
5218 dev_err(&adapter->pdev->dev,
5219 "Unsupported Speed/Duplex configuration\n");
5220 return -EINVAL;
5221 }
5222 return 0;
5223}
5224
3fe7c4c9 5225static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake)
9d5c8243
AK		 5226{
5227 struct net_device *netdev = pci_get_drvdata(pdev);
5228 struct igb_adapter *adapter = netdev_priv(netdev);
5229 struct e1000_hw *hw = &adapter->hw;
2d064c06 5230 u32 ctrl, rctl, status;
9d5c8243
AK		 5231 u32 wufc = adapter->wol;
5232#ifdef CONFIG_PM
5233 int retval = 0;
5234#endif
5235
5236 netif_device_detach(netdev);
5237
a88f10ec
AD		 5238 if (netif_running(netdev))
5239 igb_close(netdev);
5240
5241 igb_reset_interrupt_capability(adapter);
5242
5243 igb_free_queues(adapter);
9d5c8243
AK		 5244
5245#ifdef CONFIG_PM
5246 retval = pci_save_state(pdev);
5247 if (retval)
5248 return retval;
5249#endif
5250
5251 status = rd32(E1000_STATUS);
5252 if (status & E1000_STATUS_LU)
5253 wufc &= ~E1000_WUFC_LNKC;
5254
5255 if (wufc) {
5256 igb_setup_rctl(adapter);
ff41f8dc 5257 igb_set_rx_mode(netdev);
9d5c8243
AK		 5258
5259 /* turn on all-multi mode if wake on multicast is enabled */
5260 if (wufc & E1000_WUFC_MC) {
5261 rctl = rd32(E1000_RCTL);
5262 rctl |= E1000_RCTL_MPE;
5263 wr32(E1000_RCTL, rctl);
5264 }
5265
5266 ctrl = rd32(E1000_CTRL);
5267 /* advertise wake from D3Cold */
5268 #define E1000_CTRL_ADVD3WUC 0x00100000
5269 /* phy power management enable */
5270 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
5271 ctrl |= E1000_CTRL_ADVD3WUC;
5272 wr32(E1000_CTRL, ctrl);
5273
9d5c8243
AK		 5274 /* Allow time for pending master requests to run */
5275 igb_disable_pcie_master(&adapter->hw);
5276
5277 wr32(E1000_WUC, E1000_WUC_PME_EN);
5278 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 5279 } else {
5280 wr32(E1000_WUC, 0);
5281 wr32(E1000_WUFC, 0);
9d5c8243
AK		 5282 }
5283
3fe7c4c9
RW		 5284 *enable_wake = wufc || adapter->en_mng_pt;
5285 if (!*enable_wake)
2d064c06 5286 igb_shutdown_fiber_serdes_link_82575(hw);
9d5c8243
AK		 5287
5288 /* Release control of h/w to f/w. If f/w is AMT enabled, this
5289 * would have already happened in close and is redundant. */
5290 igb_release_hw_control(adapter);
5291
5292 pci_disable_device(pdev);
5293
9d5c8243
AK		 5294 return 0;
5295}
5296
5297#ifdef CONFIG_PM
3fe7c4c9
RW		 5298static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
5299{
5300 int retval;
5301 bool wake;
5302
5303 retval = __igb_shutdown(pdev, &wake);
5304 if (retval)
5305 return retval;
5306
5307 if (wake) {
5308 pci_prepare_to_sleep(pdev);
5309 } else {
5310 pci_wake_from_d3(pdev, false);
5311 pci_set_power_state(pdev, PCI_D3hot);
5312 }
5313
5314 return 0;
5315}
5316
9d5c8243
AK		 5317static int igb_resume(struct pci_dev *pdev)
5318{
5319 struct net_device *netdev = pci_get_drvdata(pdev);
5320 struct igb_adapter *adapter = netdev_priv(netdev);
5321 struct e1000_hw *hw = &adapter->hw;
5322 u32 err;
5323
5324 pci_set_power_state(pdev, PCI_D0);
5325 pci_restore_state(pdev);
42bfd33a 5326
aed5dec3 5327 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 5328 if (err) {
5329 dev_err(&pdev->dev,
5330 "igb: Cannot enable PCI device from suspend\n");
5331 return err;
5332 }
5333 pci_set_master(pdev);
5334
5335 pci_enable_wake(pdev, PCI_D3hot, 0);
5336 pci_enable_wake(pdev, PCI_D3cold, 0);
5337
a88f10ec
AD		 5338 igb_set_interrupt_capability(adapter);
5339
5340 if (igb_alloc_queues(adapter)) {
5341 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
5342 return -ENOMEM;
9d5c8243
AK		 5343 }
5344
5345 /* e1000_power_up_phy(adapter); */
5346
5347 igb_reset(adapter);
a8564f03
AD		 5348
5349 /* let the f/w know that the h/w is now under the control of the
5350 * driver. */
5351 igb_get_hw_control(adapter);
5352
9d5c8243
AK		 5353 wr32(E1000_WUS, ~0);
5354
a88f10ec
AD		 5355 if (netif_running(netdev)) {
5356 err = igb_open(netdev);
5357 if (err)
5358 return err;
5359 }
9d5c8243
AK		 5360
5361 netif_device_attach(netdev);
5362
9d5c8243
AK		 5363 return 0;
5364}
5365#endif
5366
5367static void igb_shutdown(struct pci_dev *pdev)
5368{
3fe7c4c9
RW		 5369 bool wake;
5370
5371 __igb_shutdown(pdev, &wake);
5372
5373 if (system_state == SYSTEM_POWER_OFF) {
5374 pci_wake_from_d3(pdev, wake);
5375 pci_set_power_state(pdev, PCI_D3hot);
5376 }
9d5c8243
AK		 5377}
5378
5379#ifdef CONFIG_NET_POLL_CONTROLLER
5380/*
5381 * Polling 'interrupt' - used by things like netconsole to send skbs
5382 * without having to re-enable interrupts. It's not called while
5383 * the interrupt routine is executing.
5384 */
5385static void igb_netpoll(struct net_device *netdev)
5386{
5387 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 5388 struct e1000_hw *hw = &adapter->hw;
9d5c8243 5389 int i;
9d5c8243 5390
eebbbdba
AD		 5391 if (!adapter->msix_entries) {
5392 igb_irq_disable(adapter);
5393 napi_schedule(&adapter->rx_ring[0].napi);
5394 return;
5395 }
9d5c8243 5396
eebbbdba
AD		 5397 for (i = 0; i < adapter->num_tx_queues; i++) {
5398 struct igb_ring *tx_ring = &adapter->tx_ring[i];
5399 wr32(E1000_EIMC, tx_ring->eims_value);
5400 igb_clean_tx_irq(tx_ring);
5401 wr32(E1000_EIMS, tx_ring->eims_value);
5402 }
9d5c8243 5403
eebbbdba
AD		 5404 for (i = 0; i < adapter->num_rx_queues; i++) {
5405 struct igb_ring *rx_ring = &adapter->rx_ring[i];
5406 wr32(E1000_EIMC, rx_ring->eims_value);
5407 napi_schedule(&rx_ring->napi);
5408 }
9d5c8243
AK		 5409}
5410#endif /* CONFIG_NET_POLL_CONTROLLER */
5411
5412/**
5413 * igb_io_error_detected - called when PCI error is detected
5414 * @pdev: Pointer to PCI device
5415 * @state: The current pci connection state
5416 *
5417 * This function is called after a PCI bus error affecting
5418 * this device has been detected.
5419 */
5420static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
5421 pci_channel_state_t state)
5422{
5423 struct net_device *netdev = pci_get_drvdata(pdev);
5424 struct igb_adapter *adapter = netdev_priv(netdev);
5425
5426 netif_device_detach(netdev);
5427
59ed6eec
AD		 5428 if (state == pci_channel_io_perm_failure)
5429 return PCI_ERS_RESULT_DISCONNECT;
5430
9d5c8243
AK		 5431 if (netif_running(netdev))
5432 igb_down(adapter);
5433 pci_disable_device(pdev);
5434
5435 /* Request a slot slot reset. */
5436 return PCI_ERS_RESULT_NEED_RESET;
5437}
5438
5439/**
5440 * igb_io_slot_reset - called after the pci bus has been reset.
5441 * @pdev: Pointer to PCI device
5442 *
5443 * Restart the card from scratch, as if from a cold-boot. Implementation
5444 * resembles the first-half of the igb_resume routine.
5445 */
5446static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
5447{
5448 struct net_device *netdev = pci_get_drvdata(pdev);
5449 struct igb_adapter *adapter = netdev_priv(netdev);
5450 struct e1000_hw *hw = &adapter->hw;
40a914fa 5451 pci_ers_result_t result;
42bfd33a 5452 int err;
9d5c8243 5453
aed5dec3 5454 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 5455 dev_err(&pdev->dev,
5456 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 5457 result = PCI_ERS_RESULT_DISCONNECT;
5458 } else {
5459 pci_set_master(pdev);
5460 pci_restore_state(pdev);
9d5c8243 5461
40a914fa
AD		 5462 pci_enable_wake(pdev, PCI_D3hot, 0);
5463 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 5464
40a914fa
AD		 5465 igb_reset(adapter);
5466 wr32(E1000_WUS, ~0);
5467 result = PCI_ERS_RESULT_RECOVERED;
5468 }
9d5c8243 5469
ea943d41
JK		 5470 err = pci_cleanup_aer_uncorrect_error_status(pdev);
5471 if (err) {
5472 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
5473 "failed 0x%0x\n", err);
5474 /* non-fatal, continue */
5475 }
40a914fa
AD		 5476
5477 return result;
9d5c8243
AK		 5478}
5479
5480/**
5481 * igb_io_resume - called when traffic can start flowing again.
5482 * @pdev: Pointer to PCI device
5483 *
5484 * This callback is called when the error recovery driver tells us that
5485 * its OK to resume normal operation. Implementation resembles the
5486 * second-half of the igb_resume routine.
5487 */
5488static void igb_io_resume(struct pci_dev *pdev)
5489{
5490 struct net_device *netdev = pci_get_drvdata(pdev);
5491 struct igb_adapter *adapter = netdev_priv(netdev);
5492
9d5c8243
AK		 5493 if (netif_running(netdev)) {
5494 if (igb_up(adapter)) {
5495 dev_err(&pdev->dev, "igb_up failed after reset\n");
5496 return;
5497 }
5498 }
5499
5500 netif_device_attach(netdev);
5501
5502 /* let the f/w know that the h/w is now under the control of the
5503 * driver. */
5504 igb_get_hw_control(adapter);
9d5c8243
AK		 5505}
5506
4ae196df
AD		 5507static int igb_set_vf_mac(struct igb_adapter *adapter,
5508 int vf, unsigned char *mac_addr)
5509{
5510 struct e1000_hw *hw = &adapter->hw;
ff41f8dc
AD		 5511 /* VF MAC addresses start at end of receive addresses and moves
5512 * torwards the first, as a result a collision should not be possible */
5513 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 5514
37680117 5515 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 5516
ff41f8dc 5517 igb_rar_set(hw, mac_addr, rar_entry);
4ae196df
AD		 5518 igb_set_rah_pool(hw, vf, rar_entry);
5519
5520 return 0;
5521}
5522
5523static void igb_vmm_control(struct igb_adapter *adapter)
5524{
5525 struct e1000_hw *hw = &adapter->hw;
5526 u32 reg_data;
5527
5528 if (!adapter->vfs_allocated_count)
5529 return;
5530
5531 /* VF's need PF reset indication before they
5532 * can send/receive mail */
5533 reg_data = rd32(E1000_CTRL_EXT);
5534 reg_data |= E1000_CTRL_EXT_PFRSTD;
5535 wr32(E1000_CTRL_EXT, reg_data);
5536
5537 igb_vmdq_set_loopback_pf(hw, true);
5538 igb_vmdq_set_replication_pf(hw, true);
5539}
5540
9d5c8243 5541/* igb_main.c */
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