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igb: Add support for DH89xxCC
[mirror_ubuntu-artful-kernel.git] / drivers / net / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
86d5d38f 4 Copyright(c) 2007-2009 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/module.h>
29#include <linux/types.h>
30#include <linux/init.h>
31#include <linux/vmalloc.h>
32#include <linux/pagemap.h>
33#include <linux/netdevice.h>
9d5c8243 34#include <linux/ipv6.h>
5a0e3ad6 35#include <linux/slab.h>
9d5c8243
AK		 36#include <net/checksum.h>
37#include <net/ip6_checksum.h>
c6cb090b 38#include <linux/net_tstamp.h>
9d5c8243
AK		 39#include <linux/mii.h>
40#include <linux/ethtool.h>
41#include <linux/if_vlan.h>
42#include <linux/pci.h>
c54106bb 43#include <linux/pci-aspm.h>
9d5c8243
AK		 44#include <linux/delay.h>
45#include <linux/interrupt.h>
46#include <linux/if_ether.h>
40a914fa 47#include <linux/aer.h>
421e02f0 48#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 49#include <linux/dca.h>
50#endif
9d5c8243
AK		 51#include "igb.h"
52
55cac248 53#define DRV_VERSION "2.1.0-k2"
9d5c8243
AK		 54char igb_driver_name[] = "igb";
55char igb_driver_version[] = DRV_VERSION;
56static const char igb_driver_string[] =
57 "Intel(R) Gigabit Ethernet Network Driver";
86d5d38f 58static const char igb_copyright[] = "Copyright (c) 2007-2009 Intel Corporation.";
9d5c8243 59
9d5c8243
AK		 60static const struct e1000_info *igb_info_tbl[] = {
61 [board_82575] = &e1000_82575_info,
62};
63
a3aa1884 64static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = {
d2ba2ed8
AD		 65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
55cac248
AD		 69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
70 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
71 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
72 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
73 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
308fb39a
JG		 74 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
75 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
2d064c06 76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
747d49ba 78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
2d064c06
AD		 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
b894fa26 82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
c8ea5ea9 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
87 /* required last entry */
88 {0, }
89};
90
91MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
92
93void igb_reset(struct igb_adapter *);
94static int igb_setup_all_tx_resources(struct igb_adapter *);
95static int igb_setup_all_rx_resources(struct igb_adapter *);
96static void igb_free_all_tx_resources(struct igb_adapter *);
97static void igb_free_all_rx_resources(struct igb_adapter *);
06cf2666 98static void igb_setup_mrqc(struct igb_adapter *);
9d5c8243
AK		 99void igb_update_stats(struct igb_adapter *);
100static int igb_probe(struct pci_dev *, const struct pci_device_id *);
101static void __devexit igb_remove(struct pci_dev *pdev);
102static int igb_sw_init(struct igb_adapter *);
103static int igb_open(struct net_device *);
104static int igb_close(struct net_device *);
105static void igb_configure_tx(struct igb_adapter *);
106static void igb_configure_rx(struct igb_adapter *);
9d5c8243
AK		 107static void igb_clean_all_tx_rings(struct igb_adapter *);
108static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 109static void igb_clean_tx_ring(struct igb_ring *);
110static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 111static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 112static void igb_update_phy_info(unsigned long);
113static void igb_watchdog(unsigned long);
114static void igb_watchdog_task(struct work_struct *);
b1a436c3 115static netdev_tx_t igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
9d5c8243
AK		 116static struct net_device_stats *igb_get_stats(struct net_device *);
117static int igb_change_mtu(struct net_device *, int);
118static int igb_set_mac(struct net_device *, void *);
68d480c4 119static void igb_set_uta(struct igb_adapter *adapter);
9d5c8243
AK		 120static irqreturn_t igb_intr(int irq, void *);
121static irqreturn_t igb_intr_msi(int irq, void *);
122static irqreturn_t igb_msix_other(int irq, void *);
047e0030 123static irqreturn_t igb_msix_ring(int irq, void *);
421e02f0 124#ifdef CONFIG_IGB_DCA
047e0030 125static void igb_update_dca(struct igb_q_vector *);
fe4506b6 126static void igb_setup_dca(struct igb_adapter *);
421e02f0 127#endif /* CONFIG_IGB_DCA */
047e0030 128static bool igb_clean_tx_irq(struct igb_q_vector *);
661086df 129static int igb_poll(struct napi_struct *, int);
047e0030 130static bool igb_clean_rx_irq_adv(struct igb_q_vector *, int *, int);
9d5c8243
AK		 131static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
132static void igb_tx_timeout(struct net_device *);
133static void igb_reset_task(struct work_struct *);
134static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
135static void igb_vlan_rx_add_vid(struct net_device *, u16);
136static void igb_vlan_rx_kill_vid(struct net_device *, u16);
137static void igb_restore_vlan(struct igb_adapter *);
26ad9178 138static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
4ae196df
AD		 139static void igb_ping_all_vfs(struct igb_adapter *);
140static void igb_msg_task(struct igb_adapter *);
4ae196df 141static void igb_vmm_control(struct igb_adapter *);
f2ca0dbe 142static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
4ae196df 143static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
8151d294
WM		 144static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
145static int igb_ndo_set_vf_vlan(struct net_device *netdev,
146 int vf, u16 vlan, u8 qos);
147static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate);
148static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
149 struct ifla_vf_info *ivi);
9d5c8243 150
9d5c8243 151#ifdef CONFIG_PM
3fe7c4c9 152static int igb_suspend(struct pci_dev *, pm_message_t);
9d5c8243
AK		 153static int igb_resume(struct pci_dev *);
154#endif
155static void igb_shutdown(struct pci_dev *);
421e02f0 156#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 157static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
158static struct notifier_block dca_notifier = {
159 .notifier_call = igb_notify_dca,
160 .next = NULL,
161 .priority = 0
162};
163#endif
9d5c8243
AK		 164#ifdef CONFIG_NET_POLL_CONTROLLER
165/* for netdump / net console */
166static void igb_netpoll(struct net_device *);
167#endif
37680117 168#ifdef CONFIG_PCI_IOV
2a3abf6d
AD		 169static unsigned int max_vfs = 0;
170module_param(max_vfs, uint, 0);
171MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
172 "per physical function");
173#endif /* CONFIG_PCI_IOV */
174
9d5c8243
AK		 175static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
176 pci_channel_state_t);
177static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
178static void igb_io_resume(struct pci_dev *);
179
180static struct pci_error_handlers igb_err_handler = {
181 .error_detected = igb_io_error_detected,
182 .slot_reset = igb_io_slot_reset,
183 .resume = igb_io_resume,
184};
185
186
187static struct pci_driver igb_driver = {
188 .name = igb_driver_name,
189 .id_table = igb_pci_tbl,
190 .probe = igb_probe,
191 .remove = __devexit_p(igb_remove),
192#ifdef CONFIG_PM
193 /* Power Managment Hooks */
194 .suspend = igb_suspend,
195 .resume = igb_resume,
196#endif
197 .shutdown = igb_shutdown,
198 .err_handler = &igb_err_handler
199};
200
201MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
202MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
203MODULE_LICENSE("GPL");
204MODULE_VERSION(DRV_VERSION);
205
c97ec42a
TI		 206struct igb_reg_info {
207 u32 ofs;
208 char *name;
209};
210
211static const struct igb_reg_info igb_reg_info_tbl[] = {
212
213 /* General Registers */
214 {E1000_CTRL, "CTRL"},
215 {E1000_STATUS, "STATUS"},
216 {E1000_CTRL_EXT, "CTRL_EXT"},
217
218 /* Interrupt Registers */
219 {E1000_ICR, "ICR"},
220
221 /* RX Registers */
222 {E1000_RCTL, "RCTL"},
223 {E1000_RDLEN(0), "RDLEN"},
224 {E1000_RDH(0), "RDH"},
225 {E1000_RDT(0), "RDT"},
226 {E1000_RXDCTL(0), "RXDCTL"},
227 {E1000_RDBAL(0), "RDBAL"},
228 {E1000_RDBAH(0), "RDBAH"},
229
230 /* TX Registers */
231 {E1000_TCTL, "TCTL"},
232 {E1000_TDBAL(0), "TDBAL"},
233 {E1000_TDBAH(0), "TDBAH"},
234 {E1000_TDLEN(0), "TDLEN"},
235 {E1000_TDH(0), "TDH"},
236 {E1000_TDT(0), "TDT"},
237 {E1000_TXDCTL(0), "TXDCTL"},
238 {E1000_TDFH, "TDFH"},
239 {E1000_TDFT, "TDFT"},
240 {E1000_TDFHS, "TDFHS"},
241 {E1000_TDFPC, "TDFPC"},
242
243 /* List Terminator */
244 {}
245};
246
247/*
248 * igb_regdump - register printout routine
249 */
250static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
251{
252 int n = 0;
253 char rname[16];
254 u32 regs[8];
255
256 switch (reginfo->ofs) {
257 case E1000_RDLEN(0):
258 for (n = 0; n < 4; n++)
259 regs[n] = rd32(E1000_RDLEN(n));
260 break;
261 case E1000_RDH(0):
262 for (n = 0; n < 4; n++)
263 regs[n] = rd32(E1000_RDH(n));
264 break;
265 case E1000_RDT(0):
266 for (n = 0; n < 4; n++)
267 regs[n] = rd32(E1000_RDT(n));
268 break;
269 case E1000_RXDCTL(0):
270 for (n = 0; n < 4; n++)
271 regs[n] = rd32(E1000_RXDCTL(n));
272 break;
273 case E1000_RDBAL(0):
274 for (n = 0; n < 4; n++)
275 regs[n] = rd32(E1000_RDBAL(n));
276 break;
277 case E1000_RDBAH(0):
278 for (n = 0; n < 4; n++)
279 regs[n] = rd32(E1000_RDBAH(n));
280 break;
281 case E1000_TDBAL(0):
282 for (n = 0; n < 4; n++)
283 regs[n] = rd32(E1000_RDBAL(n));
284 break;
285 case E1000_TDBAH(0):
286 for (n = 0; n < 4; n++)
287 regs[n] = rd32(E1000_TDBAH(n));
288 break;
289 case E1000_TDLEN(0):
290 for (n = 0; n < 4; n++)
291 regs[n] = rd32(E1000_TDLEN(n));
292 break;
293 case E1000_TDH(0):
294 for (n = 0; n < 4; n++)
295 regs[n] = rd32(E1000_TDH(n));
296 break;
297 case E1000_TDT(0):
298 for (n = 0; n < 4; n++)
299 regs[n] = rd32(E1000_TDT(n));
300 break;
301 case E1000_TXDCTL(0):
302 for (n = 0; n < 4; n++)
303 regs[n] = rd32(E1000_TXDCTL(n));
304 break;
305 default:
306 printk(KERN_INFO "%-15s %08x\n",
307 reginfo->name, rd32(reginfo->ofs));
308 return;
309 }
310
311 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
312 printk(KERN_INFO "%-15s ", rname);
313 for (n = 0; n < 4; n++)
314 printk(KERN_CONT "%08x ", regs[n]);
315 printk(KERN_CONT "\n");
316}
317
318/*
319 * igb_dump - Print registers, tx-rings and rx-rings
320 */
321static void igb_dump(struct igb_adapter *adapter)
322{
323 struct net_device *netdev = adapter->netdev;
324 struct e1000_hw *hw = &adapter->hw;
325 struct igb_reg_info *reginfo;
326 int n = 0;
327 struct igb_ring *tx_ring;
328 union e1000_adv_tx_desc *tx_desc;
329 struct my_u0 { u64 a; u64 b; } *u0;
330 struct igb_buffer *buffer_info;
331 struct igb_ring *rx_ring;
332 union e1000_adv_rx_desc *rx_desc;
333 u32 staterr;
334 int i = 0;
335
336 if (!netif_msg_hw(adapter))
337 return;
338
339 /* Print netdevice Info */
340 if (netdev) {
341 dev_info(&adapter->pdev->dev, "Net device Info\n");
342 printk(KERN_INFO "Device Name state "
343 "trans_start last_rx\n");
344 printk(KERN_INFO "%-15s %016lX %016lX %016lX\n",
345 netdev->name,
346 netdev->state,
347 netdev->trans_start,
348 netdev->last_rx);
349 }
350
351 /* Print Registers */
352 dev_info(&adapter->pdev->dev, "Register Dump\n");
353 printk(KERN_INFO " Register Name Value\n");
354 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
355 reginfo->name; reginfo++) {
356 igb_regdump(hw, reginfo);
357 }
358
359 /* Print TX Ring Summary */
360 if (!netdev || !netif_running(netdev))
361 goto exit;
362
363 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
364 printk(KERN_INFO "Queue [NTU] [NTC] [bi(ntc)->dma ]"
365 " leng ntw timestamp\n");
366 for (n = 0; n < adapter->num_tx_queues; n++) {
367 tx_ring = adapter->tx_ring[n];
368 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean];
369 printk(KERN_INFO " %5d %5X %5X %016llX %04X %3X %016llX\n",
370 n, tx_ring->next_to_use, tx_ring->next_to_clean,
371 (u64)buffer_info->dma,
372 buffer_info->length,
373 buffer_info->next_to_watch,
374 (u64)buffer_info->time_stamp);
375 }
376
377 /* Print TX Rings */
378 if (!netif_msg_tx_done(adapter))
379 goto rx_ring_summary;
380
381 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
382
383 /* Transmit Descriptor Formats
384 *
385 * Advanced Transmit Descriptor
386 * +--------------------------------------------------------------+
387 * 0 | Buffer Address [63:0] |
388 * +--------------------------------------------------------------+
389 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
390 * +--------------------------------------------------------------+
391 * 63 46 45 40 39 38 36 35 32 31 24 15 0
392 */
393
394 for (n = 0; n < adapter->num_tx_queues; n++) {
395 tx_ring = adapter->tx_ring[n];
396 printk(KERN_INFO "------------------------------------\n");
397 printk(KERN_INFO "TX QUEUE INDEX = %d\n", tx_ring->queue_index);
398 printk(KERN_INFO "------------------------------------\n");
399 printk(KERN_INFO "T [desc] [address 63:0 ] "
400 "[PlPOCIStDDM Ln] [bi->dma ] "
401 "leng ntw timestamp bi->skb\n");
402
403 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
404 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
405 buffer_info = &tx_ring->buffer_info[i];
406 u0 = (struct my_u0 *)tx_desc;
407 printk(KERN_INFO "T [0x%03X] %016llX %016llX %016llX"
408 " %04X %3X %016llX %p", i,
409 le64_to_cpu(u0->a),
410 le64_to_cpu(u0->b),
411 (u64)buffer_info->dma,
412 buffer_info->length,
413 buffer_info->next_to_watch,
414 (u64)buffer_info->time_stamp,
415 buffer_info->skb);
416 if (i == tx_ring->next_to_use &&
417 i == tx_ring->next_to_clean)
418 printk(KERN_CONT " NTC/U\n");
419 else if (i == tx_ring->next_to_use)
420 printk(KERN_CONT " NTU\n");
421 else if (i == tx_ring->next_to_clean)
422 printk(KERN_CONT " NTC\n");
423 else
424 printk(KERN_CONT "\n");
425
426 if (netif_msg_pktdata(adapter) && buffer_info->dma != 0)
427 print_hex_dump(KERN_INFO, "",
428 DUMP_PREFIX_ADDRESS,
429 16, 1, phys_to_virt(buffer_info->dma),
430 buffer_info->length, true);
431 }
432 }
433
434 /* Print RX Rings Summary */
435rx_ring_summary:
436 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
437 printk(KERN_INFO "Queue [NTU] [NTC]\n");
438 for (n = 0; n < adapter->num_rx_queues; n++) {
439 rx_ring = adapter->rx_ring[n];
440 printk(KERN_INFO " %5d %5X %5X\n", n,
441 rx_ring->next_to_use, rx_ring->next_to_clean);
442 }
443
444 /* Print RX Rings */
445 if (!netif_msg_rx_status(adapter))
446 goto exit;
447
448 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
449
450 /* Advanced Receive Descriptor (Read) Format
451 * 63 1 0
452 * +-----------------------------------------------------+
453 * 0 | Packet Buffer Address [63:1] |A0/NSE|
454 * +----------------------------------------------+------+
455 * 8 | Header Buffer Address [63:1] | DD |
456 * +-----------------------------------------------------+
457 *
458 *
459 * Advanced Receive Descriptor (Write-Back) Format
460 *
461 * 63 48 47 32 31 30 21 20 17 16 4 3 0
462 * +------------------------------------------------------+
463 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
464 * | Checksum Ident | | | | Type | Type |
465 * +------------------------------------------------------+
466 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
467 * +------------------------------------------------------+
468 * 63 48 47 32 31 20 19 0
469 */
470
471 for (n = 0; n < adapter->num_rx_queues; n++) {
472 rx_ring = adapter->rx_ring[n];
473 printk(KERN_INFO "------------------------------------\n");
474 printk(KERN_INFO "RX QUEUE INDEX = %d\n", rx_ring->queue_index);
475 printk(KERN_INFO "------------------------------------\n");
476 printk(KERN_INFO "R [desc] [ PktBuf A0] "
477 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
478 "<-- Adv Rx Read format\n");
479 printk(KERN_INFO "RWB[desc] [PcsmIpSHl PtRs] "
480 "[vl er S cks ln] ---------------- [bi->skb] "
481 "<-- Adv Rx Write-Back format\n");
482
483 for (i = 0; i < rx_ring->count; i++) {
484 buffer_info = &rx_ring->buffer_info[i];
485 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
486 u0 = (struct my_u0 *)rx_desc;
487 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
488 if (staterr & E1000_RXD_STAT_DD) {
489 /* Descriptor Done */
490 printk(KERN_INFO "RWB[0x%03X] %016llX "
491 "%016llX ---------------- %p", i,
492 le64_to_cpu(u0->a),
493 le64_to_cpu(u0->b),
494 buffer_info->skb);
495 } else {
496 printk(KERN_INFO "R [0x%03X] %016llX "
497 "%016llX %016llX %p", i,
498 le64_to_cpu(u0->a),
499 le64_to_cpu(u0->b),
500 (u64)buffer_info->dma,
501 buffer_info->skb);
502
503 if (netif_msg_pktdata(adapter)) {
504 print_hex_dump(KERN_INFO, "",
505 DUMP_PREFIX_ADDRESS,
506 16, 1,
507 phys_to_virt(buffer_info->dma),
508 rx_ring->rx_buffer_len, true);
509 if (rx_ring->rx_buffer_len
510 < IGB_RXBUFFER_1024)
511 print_hex_dump(KERN_INFO, "",
512 DUMP_PREFIX_ADDRESS,
513 16, 1,
514 phys_to_virt(
515 buffer_info->page_dma +
516 buffer_info->page_offset),
517 PAGE_SIZE/2, true);
518 }
519 }
520
521 if (i == rx_ring->next_to_use)
522 printk(KERN_CONT " NTU\n");
523 else if (i == rx_ring->next_to_clean)
524 printk(KERN_CONT " NTC\n");
525 else
526 printk(KERN_CONT "\n");
527
528 }
529 }
530
531exit:
532 return;
533}
534
535
38c845c7
PO		 536/**
537 * igb_read_clock - read raw cycle counter (to be used by time counter)
538 */
539static cycle_t igb_read_clock(const struct cyclecounter *tc)
540{
541 struct igb_adapter *adapter =
542 container_of(tc, struct igb_adapter, cycles);
543 struct e1000_hw *hw = &adapter->hw;
c5b9bd5e
AD		 544 u64 stamp = 0;
545 int shift = 0;
38c845c7 546
55cac248
AD		 547 /*
548 * The timestamp latches on lowest register read. For the 82580
549 * the lowest register is SYSTIMR instead of SYSTIML. However we never
550 * adjusted TIMINCA so SYSTIMR will just read as all 0s so ignore it.
551 */
552 if (hw->mac.type == e1000_82580) {
553 stamp = rd32(E1000_SYSTIMR) >> 8;
554 shift = IGB_82580_TSYNC_SHIFT;
555 }
556
c5b9bd5e
AD		 557 stamp |= (u64)rd32(E1000_SYSTIML) << shift;
558 stamp |= (u64)rd32(E1000_SYSTIMH) << (shift + 32);
38c845c7
PO		 559 return stamp;
560}
561
9d5c8243 562/**
c041076a 563 * igb_get_hw_dev - return device
9d5c8243
AK		 564 * used by hardware layer to print debugging information
565 **/
c041076a 566struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
9d5c8243
AK		 567{
568 struct igb_adapter *adapter = hw->back;
c041076a 569 return adapter->netdev;
9d5c8243 570}
38c845c7 571
9d5c8243
AK		 572/**
573 * igb_init_module - Driver Registration Routine
574 *
575 * igb_init_module is the first routine called when the driver is
576 * loaded. All it does is register with the PCI subsystem.
577 **/
578static int __init igb_init_module(void)
579{
580 int ret;
581 printk(KERN_INFO "%s - version %s\n",
582 igb_driver_string, igb_driver_version);
583
584 printk(KERN_INFO "%s\n", igb_copyright);
585
421e02f0 586#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 587 dca_register_notify(&dca_notifier);
588#endif
bbd98fe4 589 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 590 return ret;
591}
592
593module_init(igb_init_module);
594
595/**
596 * igb_exit_module - Driver Exit Cleanup Routine
597 *
598 * igb_exit_module is called just before the driver is removed
599 * from memory.
600 **/
601static void __exit igb_exit_module(void)
602{
421e02f0 603#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 604 dca_unregister_notify(&dca_notifier);
605#endif
9d5c8243
AK		 606 pci_unregister_driver(&igb_driver);
607}
608
609module_exit(igb_exit_module);
610
26bc19ec
AD		 611#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
612/**
613 * igb_cache_ring_register - Descriptor ring to register mapping
614 * @adapter: board private structure to initialize
615 *
616 * Once we know the feature-set enabled for the device, we'll cache
617 * the register offset the descriptor ring is assigned to.
618 **/
619static void igb_cache_ring_register(struct igb_adapter *adapter)
620{
ee1b9f06 621 int i = 0, j = 0;
047e0030 622 u32 rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 623
624 switch (adapter->hw.mac.type) {
625 case e1000_82576:
626 /* The queues are allocated for virtualization such that VF 0
627 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
628 * In order to avoid collision we start at the first free queue
629 * and continue consuming queues in the same sequence
630 */
ee1b9f06 631 if (adapter->vfs_allocated_count) {
a99955fc 632 for (; i < adapter->rss_queues; i++)
3025a446
AD		 633 adapter->rx_ring[i]->reg_idx = rbase_offset +
634 Q_IDX_82576(i);
ee1b9f06 635 }
26bc19ec 636 case e1000_82575:
55cac248 637 case e1000_82580:
d2ba2ed8 638 case e1000_i350:
26bc19ec 639 default:
ee1b9f06 640 for (; i < adapter->num_rx_queues; i++)
3025a446 641 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
ee1b9f06 642 for (; j < adapter->num_tx_queues; j++)
3025a446 643 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
26bc19ec
AD		 644 break;
645 }
646}
647
047e0030
AD		 648static void igb_free_queues(struct igb_adapter *adapter)
649{
3025a446 650 int i;
047e0030 651
3025a446
AD		 652 for (i = 0; i < adapter->num_tx_queues; i++) {
653 kfree(adapter->tx_ring[i]);
654 adapter->tx_ring[i] = NULL;
655 }
656 for (i = 0; i < adapter->num_rx_queues; i++) {
657 kfree(adapter->rx_ring[i]);
658 adapter->rx_ring[i] = NULL;
659 }
047e0030
AD		 660 adapter->num_rx_queues = 0;
661 adapter->num_tx_queues = 0;
662}
663
9d5c8243
AK		 664/**
665 * igb_alloc_queues - Allocate memory for all rings
666 * @adapter: board private structure to initialize
667 *
668 * We allocate one ring per queue at run-time since we don't know the
669 * number of queues at compile-time.
670 **/
671static int igb_alloc_queues(struct igb_adapter *adapter)
672{
3025a446 673 struct igb_ring *ring;
9d5c8243
AK		 674 int i;
675
661086df 676 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446
AD		 677 ring = kzalloc(sizeof(struct igb_ring), GFP_KERNEL);
678 if (!ring)
679 goto err;
68fd9910 680 ring->count = adapter->tx_ring_count;
661086df 681 ring->queue_index = i;
59d71989 682 ring->dev = &adapter->pdev->dev;
e694e964 683 ring->netdev = adapter->netdev;
85ad76b2
AD		 684 /* For 82575, context index must be unique per ring. */
685 if (adapter->hw.mac.type == e1000_82575)
686 ring->flags = IGB_RING_FLAG_TX_CTX_IDX;
3025a446 687 adapter->tx_ring[i] = ring;
661086df 688 }
85ad76b2 689
9d5c8243 690 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446
AD		 691 ring = kzalloc(sizeof(struct igb_ring), GFP_KERNEL);
692 if (!ring)
693 goto err;
68fd9910 694 ring->count = adapter->rx_ring_count;
844290e5 695 ring->queue_index = i;
59d71989 696 ring->dev = &adapter->pdev->dev;
e694e964 697 ring->netdev = adapter->netdev;
4c844851 698 ring->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
85ad76b2
AD		 699 ring->flags = IGB_RING_FLAG_RX_CSUM; /* enable rx checksum */
700 /* set flag indicating ring supports SCTP checksum offload */
701 if (adapter->hw.mac.type >= e1000_82576)
702 ring->flags |= IGB_RING_FLAG_RX_SCTP_CSUM;
3025a446 703 adapter->rx_ring[i] = ring;
9d5c8243 704 }
26bc19ec
AD		 705
706 igb_cache_ring_register(adapter);
9d5c8243 707
047e0030 708 return 0;
a88f10ec 709
047e0030
AD		 710err:
711 igb_free_queues(adapter);
d1a8c9e1 712
047e0030 713 return -ENOMEM;
a88f10ec
AD		 714}
715
9d5c8243 716#define IGB_N0_QUEUE -1
047e0030 717static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
9d5c8243
AK		 718{
719 u32 msixbm = 0;
047e0030 720 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 721 struct e1000_hw *hw = &adapter->hw;
2d064c06 722 u32 ivar, index;
047e0030
AD		 723 int rx_queue = IGB_N0_QUEUE;
724 int tx_queue = IGB_N0_QUEUE;
725
726 if (q_vector->rx_ring)
727 rx_queue = q_vector->rx_ring->reg_idx;
728 if (q_vector->tx_ring)
729 tx_queue = q_vector->tx_ring->reg_idx;
2d064c06
AD		 730
731 switch (hw->mac.type) {
732 case e1000_82575:
9d5c8243
AK		 733 /* The 82575 assigns vectors using a bitmask, which matches the
734 bitmask for the EICR/EIMS/EIMC registers. To assign one
735 or more queues to a vector, we write the appropriate bits
736 into the MSIXBM register for that vector. */
047e0030 737 if (rx_queue > IGB_N0_QUEUE)
9d5c8243 738 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
047e0030 739 if (tx_queue > IGB_N0_QUEUE)
9d5c8243 740 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
feeb2721
AD		 741 if (!adapter->msix_entries && msix_vector == 0)
742 msixbm |= E1000_EIMS_OTHER;
9d5c8243 743 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
047e0030 744 q_vector->eims_value = msixbm;
2d064c06
AD		 745 break;
746 case e1000_82576:
26bc19ec 747 /* 82576 uses a table-based method for assigning vectors.
2d064c06
AD		 748 Each queue has a single entry in the table to which we write
749 a vector number along with a "valid" bit. Sadly, the layout
750 of the table is somewhat counterintuitive. */
751 if (rx_queue > IGB_N0_QUEUE) {
047e0030 752 index = (rx_queue & 0x7);
2d064c06 753 ivar = array_rd32(E1000_IVAR0, index);
047e0030 754 if (rx_queue < 8) {
26bc19ec
AD		 755 /* vector goes into low byte of register */
756 ivar = ivar & 0xFFFFFF00;
757 ivar |= msix_vector | E1000_IVAR_VALID;
047e0030
AD		 758 } else {
759 /* vector goes into third byte of register */
760 ivar = ivar & 0xFF00FFFF;
761 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
2d064c06 762 }
2d064c06
AD		 763 array_wr32(E1000_IVAR0, index, ivar);
764 }
765 if (tx_queue > IGB_N0_QUEUE) {
047e0030 766 index = (tx_queue & 0x7);
2d064c06 767 ivar = array_rd32(E1000_IVAR0, index);
047e0030 768 if (tx_queue < 8) {
26bc19ec
AD		 769 /* vector goes into second byte of register */
770 ivar = ivar & 0xFFFF00FF;
771 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
047e0030
AD		 772 } else {
773 /* vector goes into high byte of register */
774 ivar = ivar & 0x00FFFFFF;
775 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
2d064c06 776 }
2d064c06
AD		 777 array_wr32(E1000_IVAR0, index, ivar);
778 }
047e0030 779 q_vector->eims_value = 1 << msix_vector;
2d064c06 780 break;
55cac248 781 case e1000_82580:
d2ba2ed8 782 case e1000_i350:
55cac248
AD		 783 /* 82580 uses the same table-based approach as 82576 but has fewer
784 entries as a result we carry over for queues greater than 4. */
785 if (rx_queue > IGB_N0_QUEUE) {
786 index = (rx_queue >> 1);
787 ivar = array_rd32(E1000_IVAR0, index);
788 if (rx_queue & 0x1) {
789 /* vector goes into third byte of register */
790 ivar = ivar & 0xFF00FFFF;
791 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
792 } else {
793 /* vector goes into low byte of register */
794 ivar = ivar & 0xFFFFFF00;
795 ivar |= msix_vector | E1000_IVAR_VALID;
796 }
797 array_wr32(E1000_IVAR0, index, ivar);
798 }
799 if (tx_queue > IGB_N0_QUEUE) {
800 index = (tx_queue >> 1);
801 ivar = array_rd32(E1000_IVAR0, index);
802 if (tx_queue & 0x1) {
803 /* vector goes into high byte of register */
804 ivar = ivar & 0x00FFFFFF;
805 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
806 } else {
807 /* vector goes into second byte of register */
808 ivar = ivar & 0xFFFF00FF;
809 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
810 }
811 array_wr32(E1000_IVAR0, index, ivar);
812 }
813 q_vector->eims_value = 1 << msix_vector;
814 break;
2d064c06
AD		 815 default:
816 BUG();
817 break;
818 }
26b39276
AD		 819
820 /* add q_vector eims value to global eims_enable_mask */
821 adapter->eims_enable_mask |= q_vector->eims_value;
822
823 /* configure q_vector to set itr on first interrupt */
824 q_vector->set_itr = 1;
9d5c8243
AK		 825}
826
827/**
828 * igb_configure_msix - Configure MSI-X hardware
829 *
830 * igb_configure_msix sets up the hardware to properly
831 * generate MSI-X interrupts.
832 **/
833static void igb_configure_msix(struct igb_adapter *adapter)
834{
835 u32 tmp;
836 int i, vector = 0;
837 struct e1000_hw *hw = &adapter->hw;
838
839 adapter->eims_enable_mask = 0;
9d5c8243
AK		 840
841 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 842 switch (hw->mac.type) {
843 case e1000_82575:
9d5c8243
AK		 844 tmp = rd32(E1000_CTRL_EXT);
845 /* enable MSI-X PBA support*/
846 tmp |= E1000_CTRL_EXT_PBA_CLR;
847
848 /* Auto-Mask interrupts upon ICR read. */
849 tmp |= E1000_CTRL_EXT_EIAME;
850 tmp |= E1000_CTRL_EXT_IRCA;
851
852 wr32(E1000_CTRL_EXT, tmp);
047e0030
AD		 853
854 /* enable msix_other interrupt */
855 array_wr32(E1000_MSIXBM(0), vector++,
856 E1000_EIMS_OTHER);
844290e5 857 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 858
2d064c06
AD		 859 break;
860
861 case e1000_82576:
55cac248 862 case e1000_82580:
d2ba2ed8 863 case e1000_i350:
047e0030
AD		 864 /* Turn on MSI-X capability first, or our settings
865 * won't stick. And it will take days to debug. */
866 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
867 E1000_GPIE_PBA | E1000_GPIE_EIAME |
868 E1000_GPIE_NSICR);
869
870 /* enable msix_other interrupt */
871 adapter->eims_other = 1 << vector;
2d064c06 872 tmp = (vector++ | E1000_IVAR_VALID) << 8;
2d064c06 873
047e0030 874 wr32(E1000_IVAR_MISC, tmp);
2d064c06
AD		 875 break;
876 default:
877 /* do nothing, since nothing else supports MSI-X */
878 break;
879 } /* switch (hw->mac.type) */
047e0030
AD		 880
881 adapter->eims_enable_mask |= adapter->eims_other;
882
26b39276
AD		 883 for (i = 0; i < adapter->num_q_vectors; i++)
884 igb_assign_vector(adapter->q_vector[i], vector++);
047e0030 885
9d5c8243
AK		 886 wrfl();
887}
888
889/**
890 * igb_request_msix - Initialize MSI-X interrupts
891 *
892 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
893 * kernel.
894 **/
895static int igb_request_msix(struct igb_adapter *adapter)
896{
897 struct net_device *netdev = adapter->netdev;
047e0030 898 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 899 int i, err = 0, vector = 0;
900
047e0030 901 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 902 igb_msix_other, 0, netdev->name, adapter);
047e0030
AD		 903 if (err)
904 goto out;
905 vector++;
906
907 for (i = 0; i < adapter->num_q_vectors; i++) {
908 struct igb_q_vector *q_vector = adapter->q_vector[i];
909
910 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
911
912 if (q_vector->rx_ring && q_vector->tx_ring)
913 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
914 q_vector->rx_ring->queue_index);
915 else if (q_vector->tx_ring)
916 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
917 q_vector->tx_ring->queue_index);
918 else if (q_vector->rx_ring)
919 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
920 q_vector->rx_ring->queue_index);
9d5c8243 921 else
047e0030
AD		 922 sprintf(q_vector->name, "%s-unused", netdev->name);
923
9d5c8243 924 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 925 igb_msix_ring, 0, q_vector->name,
047e0030 926 q_vector);
9d5c8243
AK		 927 if (err)
928 goto out;
9d5c8243
AK		 929 vector++;
930 }
931
9d5c8243
AK		 932 igb_configure_msix(adapter);
933 return 0;
934out:
935 return err;
936}
937
938static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
939{
940 if (adapter->msix_entries) {
941 pci_disable_msix(adapter->pdev);
942 kfree(adapter->msix_entries);
943 adapter->msix_entries = NULL;
047e0030 944 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243 945 pci_disable_msi(adapter->pdev);
047e0030 946 }
9d5c8243
AK		 947}
948
047e0030
AD		 949/**
950 * igb_free_q_vectors - Free memory allocated for interrupt vectors
951 * @adapter: board private structure to initialize
952 *
953 * This function frees the memory allocated to the q_vectors. In addition if
954 * NAPI is enabled it will delete any references to the NAPI struct prior
955 * to freeing the q_vector.
956 **/
957static void igb_free_q_vectors(struct igb_adapter *adapter)
958{
959 int v_idx;
960
961 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
962 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
963 adapter->q_vector[v_idx] = NULL;
fe0592b4
NN		 964 if (!q_vector)
965 continue;
047e0030
AD		 966 netif_napi_del(&q_vector->napi);
967 kfree(q_vector);
968 }
969 adapter->num_q_vectors = 0;
970}
971
972/**
973 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
974 *
975 * This function resets the device so that it has 0 rx queues, tx queues, and
976 * MSI-X interrupts allocated.
977 */
978static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
979{
980 igb_free_queues(adapter);
981 igb_free_q_vectors(adapter);
982 igb_reset_interrupt_capability(adapter);
983}
9d5c8243
AK		 984
985/**
986 * igb_set_interrupt_capability - set MSI or MSI-X if supported
987 *
988 * Attempt to configure interrupts using the best available
989 * capabilities of the hardware and kernel.
990 **/
991static void igb_set_interrupt_capability(struct igb_adapter *adapter)
992{
993 int err;
994 int numvecs, i;
995
83b7180d 996 /* Number of supported queues. */
a99955fc 997 adapter->num_rx_queues = adapter->rss_queues;
5fa8517f
GR		 998 if (adapter->vfs_allocated_count)
999 adapter->num_tx_queues = 1;
1000 else
1001 adapter->num_tx_queues = adapter->rss_queues;
83b7180d 1002
047e0030
AD		 1003 /* start with one vector for every rx queue */
1004 numvecs = adapter->num_rx_queues;
1005
3ad2f3fb 1006 /* if tx handler is separate add 1 for every tx queue */
a99955fc
AD		 1007 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1008 numvecs += adapter->num_tx_queues;
047e0030
AD		 1009
1010 /* store the number of vectors reserved for queues */
1011 adapter->num_q_vectors = numvecs;
1012
1013 /* add 1 vector for link status interrupts */
1014 numvecs++;
9d5c8243
AK		 1015 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
1016 GFP_KERNEL);
1017 if (!adapter->msix_entries)
1018 goto msi_only;
1019
1020 for (i = 0; i < numvecs; i++)
1021 adapter->msix_entries[i].entry = i;
1022
1023 err = pci_enable_msix(adapter->pdev,
1024 adapter->msix_entries,
1025 numvecs);
1026 if (err == 0)
34a20e89 1027 goto out;
9d5c8243
AK		 1028
1029 igb_reset_interrupt_capability(adapter);
1030
1031 /* If we can't do MSI-X, try MSI */
1032msi_only:
2a3abf6d
AD		 1033#ifdef CONFIG_PCI_IOV
1034 /* disable SR-IOV for non MSI-X configurations */
1035 if (adapter->vf_data) {
1036 struct e1000_hw *hw = &adapter->hw;
1037 /* disable iov and allow time for transactions to clear */
1038 pci_disable_sriov(adapter->pdev);
1039 msleep(500);
1040
1041 kfree(adapter->vf_data);
1042 adapter->vf_data = NULL;
1043 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1044 msleep(100);
1045 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1046 }
1047#endif
4fc82adf 1048 adapter->vfs_allocated_count = 0;
a99955fc 1049 adapter->rss_queues = 1;
4fc82adf 1050 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
9d5c8243 1051 adapter->num_rx_queues = 1;
661086df 1052 adapter->num_tx_queues = 1;
047e0030 1053 adapter->num_q_vectors = 1;
9d5c8243 1054 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 1055 adapter->flags |= IGB_FLAG_HAS_MSI;
34a20e89 1056out:
661086df 1057 /* Notify the stack of the (possibly) reduced Tx Queue count. */
fd2ea0a7 1058 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
9d5c8243
AK		 1059}
1060
047e0030
AD		 1061/**
1062 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1063 * @adapter: board private structure to initialize
1064 *
1065 * We allocate one q_vector per queue interrupt. If allocation fails we
1066 * return -ENOMEM.
1067 **/
1068static int igb_alloc_q_vectors(struct igb_adapter *adapter)
1069{
1070 struct igb_q_vector *q_vector;
1071 struct e1000_hw *hw = &adapter->hw;
1072 int v_idx;
1073
1074 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
1075 q_vector = kzalloc(sizeof(struct igb_q_vector), GFP_KERNEL);
1076 if (!q_vector)
1077 goto err_out;
1078 q_vector->adapter = adapter;
047e0030
AD		 1079 q_vector->itr_register = hw->hw_addr + E1000_EITR(0);
1080 q_vector->itr_val = IGB_START_ITR;
047e0030
AD		 1081 netif_napi_add(adapter->netdev, &q_vector->napi, igb_poll, 64);
1082 adapter->q_vector[v_idx] = q_vector;
1083 }
1084 return 0;
1085
1086err_out:
fe0592b4 1087 igb_free_q_vectors(adapter);
047e0030
AD		 1088 return -ENOMEM;
1089}
1090
1091static void igb_map_rx_ring_to_vector(struct igb_adapter *adapter,
1092 int ring_idx, int v_idx)
1093{
3025a446 1094 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
047e0030 1095
3025a446 1096 q_vector->rx_ring = adapter->rx_ring[ring_idx];
047e0030 1097 q_vector->rx_ring->q_vector = q_vector;
4fc82adf
AD		 1098 q_vector->itr_val = adapter->rx_itr_setting;
1099 if (q_vector->itr_val && q_vector->itr_val <= 3)
1100 q_vector->itr_val = IGB_START_ITR;
047e0030
AD		 1101}
1102
1103static void igb_map_tx_ring_to_vector(struct igb_adapter *adapter,
1104 int ring_idx, int v_idx)
1105{
3025a446 1106 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
047e0030 1107
3025a446 1108 q_vector->tx_ring = adapter->tx_ring[ring_idx];
047e0030 1109 q_vector->tx_ring->q_vector = q_vector;
4fc82adf
AD		 1110 q_vector->itr_val = adapter->tx_itr_setting;
1111 if (q_vector->itr_val && q_vector->itr_val <= 3)
1112 q_vector->itr_val = IGB_START_ITR;
047e0030
AD		 1113}
1114
1115/**
1116 * igb_map_ring_to_vector - maps allocated queues to vectors
1117 *
1118 * This function maps the recently allocated queues to vectors.
1119 **/
1120static int igb_map_ring_to_vector(struct igb_adapter *adapter)
1121{
1122 int i;
1123 int v_idx = 0;
1124
1125 if ((adapter->num_q_vectors < adapter->num_rx_queues) ||
1126 (adapter->num_q_vectors < adapter->num_tx_queues))
1127 return -ENOMEM;
1128
1129 if (adapter->num_q_vectors >=
1130 (adapter->num_rx_queues + adapter->num_tx_queues)) {
1131 for (i = 0; i < adapter->num_rx_queues; i++)
1132 igb_map_rx_ring_to_vector(adapter, i, v_idx++);
1133 for (i = 0; i < adapter->num_tx_queues; i++)
1134 igb_map_tx_ring_to_vector(adapter, i, v_idx++);
1135 } else {
1136 for (i = 0; i < adapter->num_rx_queues; i++) {
1137 if (i < adapter->num_tx_queues)
1138 igb_map_tx_ring_to_vector(adapter, i, v_idx);
1139 igb_map_rx_ring_to_vector(adapter, i, v_idx++);
1140 }
1141 for (; i < adapter->num_tx_queues; i++)
1142 igb_map_tx_ring_to_vector(adapter, i, v_idx++);
1143 }
1144 return 0;
1145}
1146
1147/**
1148 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1149 *
1150 * This function initializes the interrupts and allocates all of the queues.
1151 **/
1152static int igb_init_interrupt_scheme(struct igb_adapter *adapter)
1153{
1154 struct pci_dev *pdev = adapter->pdev;
1155 int err;
1156
1157 igb_set_interrupt_capability(adapter);
1158
1159 err = igb_alloc_q_vectors(adapter);
1160 if (err) {
1161 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1162 goto err_alloc_q_vectors;
1163 }
1164
1165 err = igb_alloc_queues(adapter);
1166 if (err) {
1167 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1168 goto err_alloc_queues;
1169 }
1170
1171 err = igb_map_ring_to_vector(adapter);
1172 if (err) {
1173 dev_err(&pdev->dev, "Invalid q_vector to ring mapping\n");
1174 goto err_map_queues;
1175 }
1176
1177
1178 return 0;
1179err_map_queues:
1180 igb_free_queues(adapter);
1181err_alloc_queues:
1182 igb_free_q_vectors(adapter);
1183err_alloc_q_vectors:
1184 igb_reset_interrupt_capability(adapter);
1185 return err;
1186}
1187
9d5c8243
AK		 1188/**
1189 * igb_request_irq - initialize interrupts
1190 *
1191 * Attempts to configure interrupts using the best available
1192 * capabilities of the hardware and kernel.
1193 **/
1194static int igb_request_irq(struct igb_adapter *adapter)
1195{
1196 struct net_device *netdev = adapter->netdev;
047e0030 1197 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 1198 int err = 0;
1199
1200 if (adapter->msix_entries) {
1201 err = igb_request_msix(adapter);
844290e5 1202 if (!err)
9d5c8243 1203 goto request_done;
9d5c8243 1204 /* fall back to MSI */
047e0030 1205 igb_clear_interrupt_scheme(adapter);
9d5c8243 1206 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 1207 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1208 igb_free_all_tx_resources(adapter);
1209 igb_free_all_rx_resources(adapter);
047e0030 1210 adapter->num_tx_queues = 1;
9d5c8243 1211 adapter->num_rx_queues = 1;
047e0030
AD		 1212 adapter->num_q_vectors = 1;
1213 err = igb_alloc_q_vectors(adapter);
1214 if (err) {
1215 dev_err(&pdev->dev,
1216 "Unable to allocate memory for vectors\n");
1217 goto request_done;
1218 }
1219 err = igb_alloc_queues(adapter);
1220 if (err) {
1221 dev_err(&pdev->dev,
1222 "Unable to allocate memory for queues\n");
1223 igb_free_q_vectors(adapter);
1224 goto request_done;
1225 }
1226 igb_setup_all_tx_resources(adapter);
1227 igb_setup_all_rx_resources(adapter);
844290e5 1228 } else {
feeb2721 1229 igb_assign_vector(adapter->q_vector[0], 0);
9d5c8243 1230 }
844290e5 1231
7dfc16fa 1232 if (adapter->flags & IGB_FLAG_HAS_MSI) {
a0607fd3 1233 err = request_irq(adapter->pdev->irq, igb_intr_msi, 0,
047e0030 1234 netdev->name, adapter);
9d5c8243
AK		 1235 if (!err)
1236 goto request_done;
047e0030 1237
9d5c8243
AK		 1238 /* fall back to legacy interrupts */
1239 igb_reset_interrupt_capability(adapter);
7dfc16fa 1240 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1241 }
1242
a0607fd3 1243 err = request_irq(adapter->pdev->irq, igb_intr, IRQF_SHARED,
047e0030 1244 netdev->name, adapter);
9d5c8243 1245
6cb5e577 1246 if (err)
9d5c8243
AK		 1247 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
1248 err);
9d5c8243
AK		 1249
1250request_done:
1251 return err;
1252}
1253
1254static void igb_free_irq(struct igb_adapter *adapter)
1255{
9d5c8243
AK		 1256 if (adapter->msix_entries) {
1257 int vector = 0, i;
1258
047e0030 1259 free_irq(adapter->msix_entries[vector++].vector, adapter);
9d5c8243 1260
047e0030
AD		 1261 for (i = 0; i < adapter->num_q_vectors; i++) {
1262 struct igb_q_vector *q_vector = adapter->q_vector[i];
1263 free_irq(adapter->msix_entries[vector++].vector,
1264 q_vector);
1265 }
1266 } else {
1267 free_irq(adapter->pdev->irq, adapter);
9d5c8243 1268 }
9d5c8243
AK		 1269}
1270
1271/**
1272 * igb_irq_disable - Mask off interrupt generation on the NIC
1273 * @adapter: board private structure
1274 **/
1275static void igb_irq_disable(struct igb_adapter *adapter)
1276{
1277 struct e1000_hw *hw = &adapter->hw;
1278
25568a53
AD		 1279 /*
1280 * we need to be careful when disabling interrupts. The VFs are also
1281 * mapped into these registers and so clearing the bits can cause
1282 * issues on the VF drivers so we only need to clear what we set
1283 */
9d5c8243 1284 if (adapter->msix_entries) {
2dfd1212
AD		 1285 u32 regval = rd32(E1000_EIAM);
1286 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1287 wr32(E1000_EIMC, adapter->eims_enable_mask);
1288 regval = rd32(E1000_EIAC);
1289 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 1290 }
844290e5
PW		 1291
1292 wr32(E1000_IAM, 0);
9d5c8243
AK		 1293 wr32(E1000_IMC, ~0);
1294 wrfl();
81a61859
ET		 1295 if (adapter->msix_entries) {
1296 int i;
1297 for (i = 0; i < adapter->num_q_vectors; i++)
1298 synchronize_irq(adapter->msix_entries[i].vector);
1299 } else {
1300 synchronize_irq(adapter->pdev->irq);
1301 }
9d5c8243
AK		 1302}
1303
1304/**
1305 * igb_irq_enable - Enable default interrupt generation settings
1306 * @adapter: board private structure
1307 **/
1308static void igb_irq_enable(struct igb_adapter *adapter)
1309{
1310 struct e1000_hw *hw = &adapter->hw;
1311
1312 if (adapter->msix_entries) {
25568a53 1313 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC;
2dfd1212
AD		 1314 u32 regval = rd32(E1000_EIAC);
1315 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1316 regval = rd32(E1000_EIAM);
1317 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 1318 wr32(E1000_EIMS, adapter->eims_enable_mask);
25568a53 1319 if (adapter->vfs_allocated_count) {
4ae196df 1320 wr32(E1000_MBVFIMR, 0xFF);
25568a53
AD		 1321 ims |= E1000_IMS_VMMB;
1322 }
55cac248
AD		 1323 if (adapter->hw.mac.type == e1000_82580)
1324 ims |= E1000_IMS_DRSTA;
1325
25568a53 1326 wr32(E1000_IMS, ims);
844290e5 1327 } else {
55cac248
AD		 1328 wr32(E1000_IMS, IMS_ENABLE_MASK |
1329 E1000_IMS_DRSTA);
1330 wr32(E1000_IAM, IMS_ENABLE_MASK |
1331 E1000_IMS_DRSTA);
844290e5 1332 }
9d5c8243
AK		 1333}
1334
1335static void igb_update_mng_vlan(struct igb_adapter *adapter)
1336{
51466239 1337 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1338 u16 vid = adapter->hw.mng_cookie.vlan_id;
1339 u16 old_vid = adapter->mng_vlan_id;
51466239
AD		 1340
1341 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1342 /* add VID to filter table */
1343 igb_vfta_set(hw, vid, true);
1344 adapter->mng_vlan_id = vid;
1345 } else {
1346 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1347 }
1348
1349 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1350 (vid != old_vid) &&
1351 !vlan_group_get_device(adapter->vlgrp, old_vid)) {
1352 /* remove VID from filter table */
1353 igb_vfta_set(hw, old_vid, false);
9d5c8243
AK		 1354 }
1355}
1356
1357/**
1358 * igb_release_hw_control - release control of the h/w to f/w
1359 * @adapter: address of board private structure
1360 *
1361 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1362 * For ASF and Pass Through versions of f/w this means that the
1363 * driver is no longer loaded.
1364 *
1365 **/
1366static void igb_release_hw_control(struct igb_adapter *adapter)
1367{
1368 struct e1000_hw *hw = &adapter->hw;
1369 u32 ctrl_ext;
1370
1371 /* Let firmware take over control of h/w */
1372 ctrl_ext = rd32(E1000_CTRL_EXT);
1373 wr32(E1000_CTRL_EXT,
1374 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1375}
1376
9d5c8243
AK		 1377/**
1378 * igb_get_hw_control - get control of the h/w from f/w
1379 * @adapter: address of board private structure
1380 *
1381 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1382 * For ASF and Pass Through versions of f/w this means that
1383 * the driver is loaded.
1384 *
1385 **/
1386static void igb_get_hw_control(struct igb_adapter *adapter)
1387{
1388 struct e1000_hw *hw = &adapter->hw;
1389 u32 ctrl_ext;
1390
1391 /* Let firmware know the driver has taken over */
1392 ctrl_ext = rd32(E1000_CTRL_EXT);
1393 wr32(E1000_CTRL_EXT,
1394 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1395}
1396
9d5c8243
AK		 1397/**
1398 * igb_configure - configure the hardware for RX and TX
1399 * @adapter: private board structure
1400 **/
1401static void igb_configure(struct igb_adapter *adapter)
1402{
1403 struct net_device *netdev = adapter->netdev;
1404 int i;
1405
1406 igb_get_hw_control(adapter);
ff41f8dc 1407 igb_set_rx_mode(netdev);
9d5c8243
AK		 1408
1409 igb_restore_vlan(adapter);
9d5c8243 1410
85b430b4 1411 igb_setup_tctl(adapter);
06cf2666 1412 igb_setup_mrqc(adapter);
9d5c8243 1413 igb_setup_rctl(adapter);
85b430b4
AD		 1414
1415 igb_configure_tx(adapter);
9d5c8243 1416 igb_configure_rx(adapter);
662d7205
AD		 1417
1418 igb_rx_fifo_flush_82575(&adapter->hw);
1419
c493ea45 1420 /* call igb_desc_unused which always leaves
9d5c8243
AK		 1421 * at least 1 descriptor unused to make sure
1422 * next_to_use != next_to_clean */
1423 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 1424 struct igb_ring *ring = adapter->rx_ring[i];
c493ea45 1425 igb_alloc_rx_buffers_adv(ring, igb_desc_unused(ring));
9d5c8243 1426 }
9d5c8243
AK		 1427}
1428
88a268c1
NN		 1429/**
1430 * igb_power_up_link - Power up the phy/serdes link
1431 * @adapter: address of board private structure
1432 **/
1433void igb_power_up_link(struct igb_adapter *adapter)
1434{
1435 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1436 igb_power_up_phy_copper(&adapter->hw);
1437 else
1438 igb_power_up_serdes_link_82575(&adapter->hw);
1439}
1440
1441/**
1442 * igb_power_down_link - Power down the phy/serdes link
1443 * @adapter: address of board private structure
1444 */
1445static void igb_power_down_link(struct igb_adapter *adapter)
1446{
1447 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1448 igb_power_down_phy_copper_82575(&adapter->hw);
1449 else
1450 igb_shutdown_serdes_link_82575(&adapter->hw);
1451}
9d5c8243
AK		 1452
1453/**
1454 * igb_up - Open the interface and prepare it to handle traffic
1455 * @adapter: board private structure
1456 **/
9d5c8243
AK		 1457int igb_up(struct igb_adapter *adapter)
1458{
1459 struct e1000_hw *hw = &adapter->hw;
1460 int i;
1461
1462 /* hardware has been reset, we need to reload some things */
1463 igb_configure(adapter);
1464
1465 clear_bit(__IGB_DOWN, &adapter->state);
1466
047e0030
AD		 1467 for (i = 0; i < adapter->num_q_vectors; i++) {
1468 struct igb_q_vector *q_vector = adapter->q_vector[i];
1469 napi_enable(&q_vector->napi);
1470 }
844290e5 1471 if (adapter->msix_entries)
9d5c8243 1472 igb_configure_msix(adapter);
feeb2721
AD		 1473 else
1474 igb_assign_vector(adapter->q_vector[0], 0);
9d5c8243
AK		 1475
1476 /* Clear any pending interrupts. */
1477 rd32(E1000_ICR);
1478 igb_irq_enable(adapter);
1479
d4960307
AD		 1480 /* notify VFs that reset has been completed */
1481 if (adapter->vfs_allocated_count) {
1482 u32 reg_data = rd32(E1000_CTRL_EXT);
1483 reg_data |= E1000_CTRL_EXT_PFRSTD;
1484 wr32(E1000_CTRL_EXT, reg_data);
1485 }
1486
4cb9be7a
JB		 1487 netif_tx_start_all_queues(adapter->netdev);
1488
25568a53
AD		 1489 /* start the watchdog. */
1490 hw->mac.get_link_status = 1;
1491 schedule_work(&adapter->watchdog_task);
1492
9d5c8243
AK		 1493 return 0;
1494}
1495
1496void igb_down(struct igb_adapter *adapter)
1497{
9d5c8243 1498 struct net_device *netdev = adapter->netdev;
330a6d6a 1499 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1500 u32 tctl, rctl;
1501 int i;
1502
1503 /* signal that we're down so the interrupt handler does not
1504 * reschedule our watchdog timer */
1505 set_bit(__IGB_DOWN, &adapter->state);
1506
1507 /* disable receives in the hardware */
1508 rctl = rd32(E1000_RCTL);
1509 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1510 /* flush and sleep below */
1511
fd2ea0a7 1512 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1513
1514 /* disable transmits in the hardware */
1515 tctl = rd32(E1000_TCTL);
1516 tctl &= ~E1000_TCTL_EN;
1517 wr32(E1000_TCTL, tctl);
1518 /* flush both disables and wait for them to finish */
1519 wrfl();
1520 msleep(10);
1521
047e0030
AD		 1522 for (i = 0; i < adapter->num_q_vectors; i++) {
1523 struct igb_q_vector *q_vector = adapter->q_vector[i];
1524 napi_disable(&q_vector->napi);
1525 }
9d5c8243 1526
9d5c8243
AK		 1527 igb_irq_disable(adapter);
1528
1529 del_timer_sync(&adapter->watchdog_timer);
1530 del_timer_sync(&adapter->phy_info_timer);
1531
9d5c8243 1532 netif_carrier_off(netdev);
04fe6358
AD		 1533
1534 /* record the stats before reset*/
1535 igb_update_stats(adapter);
1536
9d5c8243
AK		 1537 adapter->link_speed = 0;
1538 adapter->link_duplex = 0;
1539
3023682e
JK		 1540 if (!pci_channel_offline(adapter->pdev))
1541 igb_reset(adapter);
9d5c8243
AK		 1542 igb_clean_all_tx_rings(adapter);
1543 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1544#ifdef CONFIG_IGB_DCA
1545
1546 /* since we reset the hardware DCA settings were cleared */
1547 igb_setup_dca(adapter);
1548#endif
9d5c8243
AK		 1549}
1550
1551void igb_reinit_locked(struct igb_adapter *adapter)
1552{
1553 WARN_ON(in_interrupt());
1554 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1555 msleep(1);
1556 igb_down(adapter);
1557 igb_up(adapter);
1558 clear_bit(__IGB_RESETTING, &adapter->state);
1559}
1560
1561void igb_reset(struct igb_adapter *adapter)
1562{
090b1795 1563 struct pci_dev *pdev = adapter->pdev;
9d5c8243 1564 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1565 struct e1000_mac_info *mac = &hw->mac;
1566 struct e1000_fc_info *fc = &hw->fc;
9d5c8243
AK		 1567 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
1568 u16 hwm;
1569
1570 /* Repartition Pba for greater than 9k mtu
1571 * To take effect CTRL.RST is required.
1572 */
fa4dfae0 1573 switch (mac->type) {
d2ba2ed8 1574 case e1000_i350:
55cac248
AD		 1575 case e1000_82580:
1576 pba = rd32(E1000_RXPBS);
1577 pba = igb_rxpbs_adjust_82580(pba);
1578 break;
fa4dfae0 1579 case e1000_82576:
d249be54
AD		 1580 pba = rd32(E1000_RXPBS);
1581 pba &= E1000_RXPBS_SIZE_MASK_82576;
fa4dfae0
AD		 1582 break;
1583 case e1000_82575:
1584 default:
1585 pba = E1000_PBA_34K;
1586 break;
2d064c06 1587 }
9d5c8243 1588
2d064c06
AD		 1589 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1590 (mac->type < e1000_82576)) {
9d5c8243
AK		 1591 /* adjust PBA for jumbo frames */
1592 wr32(E1000_PBA, pba);
1593
1594 /* To maintain wire speed transmits, the Tx FIFO should be
1595 * large enough to accommodate two full transmit packets,
1596 * rounded up to the next 1KB and expressed in KB. Likewise,
1597 * the Rx FIFO should be large enough to accommodate at least
1598 * one full receive packet and is similarly rounded up and
1599 * expressed in KB. */
1600 pba = rd32(E1000_PBA);
1601 /* upper 16 bits has Tx packet buffer allocation size in KB */
1602 tx_space = pba >> 16;
1603 /* lower 16 bits has Rx packet buffer allocation size in KB */
1604 pba &= 0xffff;
1605 /* the tx fifo also stores 16 bytes of information about the tx
1606 * but don't include ethernet FCS because hardware appends it */
1607 min_tx_space = (adapter->max_frame_size +
85e8d004 1608 sizeof(union e1000_adv_tx_desc) -
9d5c8243
AK		 1609 ETH_FCS_LEN) * 2;
1610 min_tx_space = ALIGN(min_tx_space, 1024);
1611 min_tx_space >>= 10;
1612 /* software strips receive CRC, so leave room for it */
1613 min_rx_space = adapter->max_frame_size;
1614 min_rx_space = ALIGN(min_rx_space, 1024);
1615 min_rx_space >>= 10;
1616
1617 /* If current Tx allocation is less than the min Tx FIFO size,
1618 * and the min Tx FIFO size is less than the current Rx FIFO
1619 * allocation, take space away from current Rx allocation */
1620 if (tx_space < min_tx_space &&
1621 ((min_tx_space - tx_space) < pba)) {
1622 pba = pba - (min_tx_space - tx_space);
1623
1624 /* if short on rx space, rx wins and must trump tx
1625 * adjustment */
1626 if (pba < min_rx_space)
1627 pba = min_rx_space;
1628 }
2d064c06 1629 wr32(E1000_PBA, pba);
9d5c8243 1630 }
9d5c8243
AK		 1631
1632 /* flow control settings */
1633 /* The high water mark must be low enough to fit one full frame
1634 * (or the size used for early receive) above it in the Rx FIFO.
1635 * Set it to the lower of:
1636 * - 90% of the Rx FIFO size, or
1637 * - the full Rx FIFO size minus one full frame */
1638 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1639 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1640
d405ea3e
AD		 1641 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1642 fc->low_water = fc->high_water - 16;
9d5c8243
AK		 1643 fc->pause_time = 0xFFFF;
1644 fc->send_xon = 1;
0cce119a 1645 fc->current_mode = fc->requested_mode;
9d5c8243 1646
4ae196df
AD		 1647 /* disable receive for all VFs and wait one second */
1648 if (adapter->vfs_allocated_count) {
1649 int i;
1650 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
f2ca0dbe 1651 adapter->vf_data[i].flags = 0;
4ae196df
AD		 1652
1653 /* ping all the active vfs to let them know we are going down */
f2ca0dbe 1654 igb_ping_all_vfs(adapter);
4ae196df
AD		 1655
1656 /* disable transmits and receives */
1657 wr32(E1000_VFRE, 0);
1658 wr32(E1000_VFTE, 0);
1659 }
1660
9d5c8243 1661 /* Allow time for pending master requests to run */
330a6d6a 1662 hw->mac.ops.reset_hw(hw);
9d5c8243
AK		 1663 wr32(E1000_WUC, 0);
1664
330a6d6a 1665 if (hw->mac.ops.init_hw(hw))
090b1795 1666 dev_err(&pdev->dev, "Hardware Error\n");
9d5c8243 1667
55cac248
AD		 1668 if (hw->mac.type == e1000_82580) {
1669 u32 reg = rd32(E1000_PCIEMISC);
1670 wr32(E1000_PCIEMISC,
1671 reg & ~E1000_PCIEMISC_LX_DECISION);
1672 }
88a268c1
NN		 1673 if (!netif_running(adapter->netdev))
1674 igb_power_down_link(adapter);
1675
9d5c8243
AK		 1676 igb_update_mng_vlan(adapter);
1677
1678 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1679 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1680
330a6d6a 1681 igb_get_phy_info(hw);
9d5c8243
AK		 1682}
1683
2e5c6922 1684static const struct net_device_ops igb_netdev_ops = {
559e9c49 1685 .ndo_open = igb_open,
2e5c6922 1686 .ndo_stop = igb_close,
00829823 1687 .ndo_start_xmit = igb_xmit_frame_adv,
2e5c6922 1688 .ndo_get_stats = igb_get_stats,
ff41f8dc
AD		 1689 .ndo_set_rx_mode = igb_set_rx_mode,
1690 .ndo_set_multicast_list = igb_set_rx_mode,
2e5c6922
SH		 1691 .ndo_set_mac_address = igb_set_mac,
1692 .ndo_change_mtu = igb_change_mtu,
1693 .ndo_do_ioctl = igb_ioctl,
1694 .ndo_tx_timeout = igb_tx_timeout,
1695 .ndo_validate_addr = eth_validate_addr,
1696 .ndo_vlan_rx_register = igb_vlan_rx_register,
1697 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1698 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
8151d294
WM		 1699 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
1700 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
1701 .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw,
1702 .ndo_get_vf_config = igb_ndo_get_vf_config,
2e5c6922
SH		 1703#ifdef CONFIG_NET_POLL_CONTROLLER
1704 .ndo_poll_controller = igb_netpoll,
1705#endif
1706};
1707
9d5c8243
AK		 1708/**
1709 * igb_probe - Device Initialization Routine
1710 * @pdev: PCI device information struct
1711 * @ent: entry in igb_pci_tbl
1712 *
1713 * Returns 0 on success, negative on failure
1714 *
1715 * igb_probe initializes an adapter identified by a pci_dev structure.
1716 * The OS initialization, configuring of the adapter private structure,
1717 * and a hardware reset occur.
1718 **/
1719static int __devinit igb_probe(struct pci_dev *pdev,
1720 const struct pci_device_id *ent)
1721{
1722 struct net_device *netdev;
1723 struct igb_adapter *adapter;
1724 struct e1000_hw *hw;
4337e993
AD		 1725 u16 eeprom_data = 0;
1726 static int global_quad_port_a; /* global quad port a indication */
9d5c8243
AK		 1727 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1728 unsigned long mmio_start, mmio_len;
2d6a5e95 1729 int err, pci_using_dac;
9d5c8243
AK		 1730 u16 eeprom_apme_mask = IGB_EEPROM_APME;
1731 u32 part_num;
1732
bded64a7
AG		 1733 /* Catch broken hardware that put the wrong VF device ID in
1734 * the PCIe SR-IOV capability.
1735 */
1736 if (pdev->is_virtfn) {
1737 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
1738 pci_name(pdev), pdev->vendor, pdev->device);
1739 return -EINVAL;
1740 }
1741
aed5dec3 1742 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 1743 if (err)
1744 return err;
1745
1746 pci_using_dac = 0;
59d71989 1747 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243 1748 if (!err) {
59d71989 1749 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243
AK		 1750 if (!err)
1751 pci_using_dac = 1;
1752 } else {
59d71989 1753 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243 1754 if (err) {
59d71989 1755 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243
AK		 1756 if (err) {
1757 dev_err(&pdev->dev, "No usable DMA "
1758 "configuration, aborting\n");
1759 goto err_dma;
1760 }
1761 }
1762 }
1763
aed5dec3
AD		 1764 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1765 IORESOURCE_MEM),
1766 igb_driver_name);
9d5c8243
AK		 1767 if (err)
1768 goto err_pci_reg;
1769
19d5afd4 1770 pci_enable_pcie_error_reporting(pdev);
40a914fa 1771
9d5c8243 1772 pci_set_master(pdev);
c682fc23 1773 pci_save_state(pdev);
9d5c8243
AK		 1774
1775 err = -ENOMEM;
1bfaf07b
AD		 1776 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1777 IGB_ABS_MAX_TX_QUEUES);
9d5c8243
AK		 1778 if (!netdev)
1779 goto err_alloc_etherdev;
1780
1781 SET_NETDEV_DEV(netdev, &pdev->dev);
1782
1783 pci_set_drvdata(pdev, netdev);
1784 adapter = netdev_priv(netdev);
1785 adapter->netdev = netdev;
1786 adapter->pdev = pdev;
1787 hw = &adapter->hw;
1788 hw->back = adapter;
1789 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
1790
1791 mmio_start = pci_resource_start(pdev, 0);
1792 mmio_len = pci_resource_len(pdev, 0);
1793
1794 err = -EIO;
28b0759c
AD		 1795 hw->hw_addr = ioremap(mmio_start, mmio_len);
1796 if (!hw->hw_addr)
9d5c8243
AK		 1797 goto err_ioremap;
1798
2e5c6922 1799 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 1800 igb_set_ethtool_ops(netdev);
9d5c8243 1801 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 1802
1803 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1804
1805 netdev->mem_start = mmio_start;
1806 netdev->mem_end = mmio_start + mmio_len;
1807
9d5c8243
AK		 1808 /* PCI config space info */
1809 hw->vendor_id = pdev->vendor;
1810 hw->device_id = pdev->device;
1811 hw->revision_id = pdev->revision;
1812 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1813 hw->subsystem_device_id = pdev->subsystem_device;
1814
9d5c8243
AK		 1815 /* Copy the default MAC, PHY and NVM function pointers */
1816 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1817 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1818 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1819 /* Initialize skew-specific constants */
1820 err = ei->get_invariants(hw);
1821 if (err)
450c87c8 1822 goto err_sw_init;
9d5c8243 1823
450c87c8 1824 /* setup the private structure */
9d5c8243
AK		 1825 err = igb_sw_init(adapter);
1826 if (err)
1827 goto err_sw_init;
1828
1829 igb_get_bus_info_pcie(hw);
1830
1831 hw->phy.autoneg_wait_to_complete = false;
9d5c8243
AK		 1832
1833 /* Copper options */
1834 if (hw->phy.media_type == e1000_media_type_copper) {
1835 hw->phy.mdix = AUTO_ALL_MODES;
1836 hw->phy.disable_polarity_correction = false;
1837 hw->phy.ms_type = e1000_ms_hw_default;
1838 }
1839
1840 if (igb_check_reset_block(hw))
1841 dev_info(&pdev->dev,
1842 "PHY reset is blocked due to SOL/IDER session.\n");
1843
1844 netdev->features = NETIF_F_SG |
7d8eb29e 1845 NETIF_F_IP_CSUM |
9d5c8243
AK		 1846 NETIF_F_HW_VLAN_TX |
1847 NETIF_F_HW_VLAN_RX |
1848 NETIF_F_HW_VLAN_FILTER;
1849
7d8eb29e 1850 netdev->features |= NETIF_F_IPV6_CSUM;
9d5c8243 1851 netdev->features |= NETIF_F_TSO;
9d5c8243 1852 netdev->features |= NETIF_F_TSO6;
5c0999b7 1853 netdev->features |= NETIF_F_GRO;
d3352520 1854
48f29ffc
JK		 1855 netdev->vlan_features |= NETIF_F_TSO;
1856 netdev->vlan_features |= NETIF_F_TSO6;
7d8eb29e 1857 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 1858 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
48f29ffc
JK		 1859 netdev->vlan_features |= NETIF_F_SG;
1860
9d5c8243
AK		 1861 if (pci_using_dac)
1862 netdev->features |= NETIF_F_HIGHDMA;
1863
5b043fb0 1864 if (hw->mac.type >= e1000_82576)
b9473560
JB		 1865 netdev->features |= NETIF_F_SCTP_CSUM;
1866
330a6d6a 1867 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
9d5c8243
AK		 1868
1869 /* before reading the NVM, reset the controller to put the device in a
1870 * known good starting state */
1871 hw->mac.ops.reset_hw(hw);
1872
1873 /* make sure the NVM is good */
1874 if (igb_validate_nvm_checksum(hw) < 0) {
1875 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1876 err = -EIO;
1877 goto err_eeprom;
1878 }
1879
1880 /* copy the MAC address out of the NVM */
1881 if (hw->mac.ops.read_mac_addr(hw))
1882 dev_err(&pdev->dev, "NVM Read Error\n");
1883
1884 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1885 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1886
1887 if (!is_valid_ether_addr(netdev->perm_addr)) {
1888 dev_err(&pdev->dev, "Invalid MAC Address\n");
1889 err = -EIO;
1890 goto err_eeprom;
1891 }
1892
c061b18d 1893 setup_timer(&adapter->watchdog_timer, igb_watchdog,
0e340485 1894 (unsigned long) adapter);
c061b18d 1895 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
0e340485 1896 (unsigned long) adapter);
9d5c8243
AK		 1897
1898 INIT_WORK(&adapter->reset_task, igb_reset_task);
1899 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1900
450c87c8 1901 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 1902 adapter->fc_autoneg = true;
1903 hw->mac.autoneg = true;
1904 hw->phy.autoneg_advertised = 0x2f;
1905
0cce119a
AD		 1906 hw->fc.requested_mode = e1000_fc_default;
1907 hw->fc.current_mode = e1000_fc_default;
9d5c8243 1908
9d5c8243
AK		 1909 igb_validate_mdi_setting(hw);
1910
9d5c8243
AK		 1911 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1912 * enable the ACPI Magic Packet filter
1913 */
1914
a2cf8b6c 1915 if (hw->bus.func == 0)
312c75ae 1916 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
55cac248
AD		 1917 else if (hw->mac.type == e1000_82580)
1918 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
1919 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
1920 &eeprom_data);
a2cf8b6c
AD		 1921 else if (hw->bus.func == 1)
1922 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243
AK		 1923
1924 if (eeprom_data & eeprom_apme_mask)
1925 adapter->eeprom_wol |= E1000_WUFC_MAG;
1926
1927 /* now that we have the eeprom settings, apply the special cases where
1928 * the eeprom may be wrong or the board simply won't support wake on
1929 * lan on a particular port */
1930 switch (pdev->device) {
1931 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1932 adapter->eeprom_wol = 0;
1933 break;
1934 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 1935 case E1000_DEV_ID_82576_FIBER:
1936 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 1937 /* Wake events only supported on port A for dual fiber
1938 * regardless of eeprom setting */
1939 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1940 adapter->eeprom_wol = 0;
1941 break;
c8ea5ea9 1942 case E1000_DEV_ID_82576_QUAD_COPPER:
d5aa2252 1943 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
c8ea5ea9
AD		 1944 /* if quad port adapter, disable WoL on all but port A */
1945 if (global_quad_port_a != 0)
1946 adapter->eeprom_wol = 0;
1947 else
1948 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
1949 /* Reset for multiple quad port adapters */
1950 if (++global_quad_port_a == 4)
1951 global_quad_port_a = 0;
1952 break;
9d5c8243
AK		 1953 }
1954
1955 /* initialize the wol settings based on the eeprom settings */
1956 adapter->wol = adapter->eeprom_wol;
e1b86d84 1957 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
9d5c8243
AK		 1958
1959 /* reset the hardware with the new settings */
1960 igb_reset(adapter);
1961
1962 /* let the f/w know that the h/w is now under the control of the
1963 * driver. */
1964 igb_get_hw_control(adapter);
1965
9d5c8243
AK		 1966 strcpy(netdev->name, "eth%d");
1967 err = register_netdev(netdev);
1968 if (err)
1969 goto err_register;
1970
b168dfc5
JB		 1971 /* carrier off reporting is important to ethtool even BEFORE open */
1972 netif_carrier_off(netdev);
1973
421e02f0 1974#ifdef CONFIG_IGB_DCA
bbd98fe4 1975 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 1976 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 1977 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 1978 igb_setup_dca(adapter);
1979 }
fe4506b6 1980
38c845c7 1981#endif
9d5c8243
AK		 1982 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1983 /* print bus type/speed/width info */
7c510e4b 1984 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
9d5c8243 1985 netdev->name,
559e9c49 1986 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
ff846f52 1987 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
559e9c49 1988 "unknown"),
59c3de89
AD		 1989 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
1990 (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :
1991 (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" :
1992 "unknown"),
7c510e4b 1993 netdev->dev_addr);
9d5c8243
AK		 1994
1995 igb_read_part_num(hw, &part_num);
1996 dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1997 (part_num >> 8), (part_num & 0xff));
1998
1999 dev_info(&pdev->dev,
2000 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
2001 adapter->msix_entries ? "MSI-X" :
7dfc16fa 2002 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243
AK		 2003 adapter->num_rx_queues, adapter->num_tx_queues);
2004
9d5c8243
AK		 2005 return 0;
2006
2007err_register:
2008 igb_release_hw_control(adapter);
2009err_eeprom:
2010 if (!igb_check_reset_block(hw))
f5f4cf08 2011 igb_reset_phy(hw);
9d5c8243
AK		 2012
2013 if (hw->flash_address)
2014 iounmap(hw->flash_address);
9d5c8243 2015err_sw_init:
047e0030 2016 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 2017 iounmap(hw->hw_addr);
2018err_ioremap:
2019 free_netdev(netdev);
2020err_alloc_etherdev:
559e9c49
AD		 2021 pci_release_selected_regions(pdev,
2022 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243
AK		 2023err_pci_reg:
2024err_dma:
2025 pci_disable_device(pdev);
2026 return err;
2027}
2028
2029/**
2030 * igb_remove - Device Removal Routine
2031 * @pdev: PCI device information struct
2032 *
2033 * igb_remove is called by the PCI subsystem to alert the driver
2034 * that it should release a PCI device. The could be caused by a
2035 * Hot-Plug event, or because the driver is going to be removed from
2036 * memory.
2037 **/
2038static void __devexit igb_remove(struct pci_dev *pdev)
2039{
2040 struct net_device *netdev = pci_get_drvdata(pdev);
2041 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 2042 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 2043
2044 /* flush_scheduled work may reschedule our watchdog task, so
2045 * explicitly disable watchdog tasks from being rescheduled */
2046 set_bit(__IGB_DOWN, &adapter->state);
2047 del_timer_sync(&adapter->watchdog_timer);
2048 del_timer_sync(&adapter->phy_info_timer);
2049
2050 flush_scheduled_work();
2051
421e02f0 2052#ifdef CONFIG_IGB_DCA
7dfc16fa 2053 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 2054 dev_info(&pdev->dev, "DCA disabled\n");
2055 dca_remove_requester(&pdev->dev);
7dfc16fa 2056 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 2057 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 2058 }
2059#endif
2060
9d5c8243
AK		 2061 /* Release control of h/w to f/w. If f/w is AMT enabled, this
2062 * would have already happened in close and is redundant. */
2063 igb_release_hw_control(adapter);
2064
2065 unregister_netdev(netdev);
2066
047e0030 2067 igb_clear_interrupt_scheme(adapter);
9d5c8243 2068
37680117
AD		 2069#ifdef CONFIG_PCI_IOV
2070 /* reclaim resources allocated to VFs */
2071 if (adapter->vf_data) {
2072 /* disable iov and allow time for transactions to clear */
2073 pci_disable_sriov(pdev);
2074 msleep(500);
2075
2076 kfree(adapter->vf_data);
2077 adapter->vf_data = NULL;
2078 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2079 msleep(100);
2080 dev_info(&pdev->dev, "IOV Disabled\n");
2081 }
2082#endif
559e9c49 2083
28b0759c
AD		 2084 iounmap(hw->hw_addr);
2085 if (hw->flash_address)
2086 iounmap(hw->flash_address);
559e9c49
AD		 2087 pci_release_selected_regions(pdev,
2088 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243
AK		 2089
2090 free_netdev(netdev);
2091
19d5afd4 2092 pci_disable_pcie_error_reporting(pdev);
40a914fa 2093
9d5c8243
AK		 2094 pci_disable_device(pdev);
2095}
2096
a6b623e0
AD		 2097/**
2098 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2099 * @adapter: board private structure to initialize
2100 *
2101 * This function initializes the vf specific data storage and then attempts to
2102 * allocate the VFs. The reason for ordering it this way is because it is much
2103 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2104 * the memory for the VFs.
2105 **/
2106static void __devinit igb_probe_vfs(struct igb_adapter * adapter)
2107{
2108#ifdef CONFIG_PCI_IOV
2109 struct pci_dev *pdev = adapter->pdev;
2110
a6b623e0
AD		 2111 if (adapter->vfs_allocated_count) {
2112 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2113 sizeof(struct vf_data_storage),
2114 GFP_KERNEL);
2115 /* if allocation failed then we do not support SR-IOV */
2116 if (!adapter->vf_data) {
2117 adapter->vfs_allocated_count = 0;
2118 dev_err(&pdev->dev, "Unable to allocate memory for VF "
2119 "Data Storage\n");
2120 }
2121 }
2122
2123 if (pci_enable_sriov(pdev, adapter->vfs_allocated_count)) {
2124 kfree(adapter->vf_data);
2125 adapter->vf_data = NULL;
2126#endif /* CONFIG_PCI_IOV */
2127 adapter->vfs_allocated_count = 0;
2128#ifdef CONFIG_PCI_IOV
2129 } else {
2130 unsigned char mac_addr[ETH_ALEN];
2131 int i;
2132 dev_info(&pdev->dev, "%d vfs allocated\n",
2133 adapter->vfs_allocated_count);
2134 for (i = 0; i < adapter->vfs_allocated_count; i++) {
2135 random_ether_addr(mac_addr);
2136 igb_set_vf_mac(adapter, i, mac_addr);
2137 }
2138 }
2139#endif /* CONFIG_PCI_IOV */
2140}
2141
115f459a
AD		 2142
2143/**
2144 * igb_init_hw_timer - Initialize hardware timer used with IEEE 1588 timestamp
2145 * @adapter: board private structure to initialize
2146 *
2147 * igb_init_hw_timer initializes the function pointer and values for the hw
2148 * timer found in hardware.
2149 **/
2150static void igb_init_hw_timer(struct igb_adapter *adapter)
2151{
2152 struct e1000_hw *hw = &adapter->hw;
2153
2154 switch (hw->mac.type) {
d2ba2ed8 2155 case e1000_i350:
55cac248
AD		 2156 case e1000_82580:
2157 memset(&adapter->cycles, 0, sizeof(adapter->cycles));
2158 adapter->cycles.read = igb_read_clock;
2159 adapter->cycles.mask = CLOCKSOURCE_MASK(64);
2160 adapter->cycles.mult = 1;
2161 /*
2162 * The 82580 timesync updates the system timer every 8ns by 8ns
2163 * and the value cannot be shifted. Instead we need to shift
2164 * the registers to generate a 64bit timer value. As a result
2165 * SYSTIMR/L/H, TXSTMPL/H, RXSTMPL/H all have to be shifted by
2166 * 24 in order to generate a larger value for synchronization.
2167 */
2168 adapter->cycles.shift = IGB_82580_TSYNC_SHIFT;
2169 /* disable system timer temporarily by setting bit 31 */
2170 wr32(E1000_TSAUXC, 0x80000000);
2171 wrfl();
2172
2173 /* Set registers so that rollover occurs soon to test this. */
2174 wr32(E1000_SYSTIMR, 0x00000000);
2175 wr32(E1000_SYSTIML, 0x80000000);
2176 wr32(E1000_SYSTIMH, 0x000000FF);
2177 wrfl();
2178
2179 /* enable system timer by clearing bit 31 */
2180 wr32(E1000_TSAUXC, 0x0);
2181 wrfl();
2182
2183 timecounter_init(&adapter->clock,
2184 &adapter->cycles,
2185 ktime_to_ns(ktime_get_real()));
2186 /*
2187 * Synchronize our NIC clock against system wall clock. NIC
2188 * time stamp reading requires ~3us per sample, each sample
2189 * was pretty stable even under load => only require 10
2190 * samples for each offset comparison.
2191 */
2192 memset(&adapter->compare, 0, sizeof(adapter->compare));
2193 adapter->compare.source = &adapter->clock;
2194 adapter->compare.target = ktime_get_real;
2195 adapter->compare.num_samples = 10;
2196 timecompare_update(&adapter->compare, 0);
2197 break;
115f459a
AD		 2198 case e1000_82576:
2199 /*
2200 * Initialize hardware timer: we keep it running just in case
2201 * that some program needs it later on.
2202 */
2203 memset(&adapter->cycles, 0, sizeof(adapter->cycles));
2204 adapter->cycles.read = igb_read_clock;
2205 adapter->cycles.mask = CLOCKSOURCE_MASK(64);
2206 adapter->cycles.mult = 1;
2207 /**
2208 * Scale the NIC clock cycle by a large factor so that
2209 * relatively small clock corrections can be added or
2210 * substracted at each clock tick. The drawbacks of a large
2211 * factor are a) that the clock register overflows more quickly
2212 * (not such a big deal) and b) that the increment per tick has
2213 * to fit into 24 bits. As a result we need to use a shift of
2214 * 19 so we can fit a value of 16 into the TIMINCA register.
2215 */
2216 adapter->cycles.shift = IGB_82576_TSYNC_SHIFT;
2217 wr32(E1000_TIMINCA,
2218 (1 << E1000_TIMINCA_16NS_SHIFT) |
2219 (16 << IGB_82576_TSYNC_SHIFT));
2220
2221 /* Set registers so that rollover occurs soon to test this. */
2222 wr32(E1000_SYSTIML, 0x00000000);
2223 wr32(E1000_SYSTIMH, 0xFF800000);
2224 wrfl();
2225
2226 timecounter_init(&adapter->clock,
2227 &adapter->cycles,
2228 ktime_to_ns(ktime_get_real()));
2229 /*
2230 * Synchronize our NIC clock against system wall clock. NIC
2231 * time stamp reading requires ~3us per sample, each sample
2232 * was pretty stable even under load => only require 10
2233 * samples for each offset comparison.
2234 */
2235 memset(&adapter->compare, 0, sizeof(adapter->compare));
2236 adapter->compare.source = &adapter->clock;
2237 adapter->compare.target = ktime_get_real;
2238 adapter->compare.num_samples = 10;
2239 timecompare_update(&adapter->compare, 0);
2240 break;
2241 case e1000_82575:
2242 /* 82575 does not support timesync */
2243 default:
2244 break;
2245 }
2246
2247}
2248
9d5c8243
AK		 2249/**
2250 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2251 * @adapter: board private structure to initialize
2252 *
2253 * igb_sw_init initializes the Adapter private data structure.
2254 * Fields are initialized based on PCI device information and
2255 * OS network device settings (MTU size).
2256 **/
2257static int __devinit igb_sw_init(struct igb_adapter *adapter)
2258{
2259 struct e1000_hw *hw = &adapter->hw;
2260 struct net_device *netdev = adapter->netdev;
2261 struct pci_dev *pdev = adapter->pdev;
2262
2263 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2264
68fd9910
AD		 2265 adapter->tx_ring_count = IGB_DEFAULT_TXD;
2266 adapter->rx_ring_count = IGB_DEFAULT_RXD;
4fc82adf
AD		 2267 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2268 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2269
9d5c8243
AK		 2270 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2271 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2272
a6b623e0
AD		 2273#ifdef CONFIG_PCI_IOV
2274 if (hw->mac.type == e1000_82576)
c0f2276f 2275 adapter->vfs_allocated_count = (max_vfs > 7) ? 7 : max_vfs;
a6b623e0
AD		 2276
2277#endif /* CONFIG_PCI_IOV */
a99955fc
AD		 2278 adapter->rss_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
2279
2280 /*
2281 * if rss_queues > 4 or vfs are going to be allocated with rss_queues
2282 * then we should combine the queues into a queue pair in order to
2283 * conserve interrupts due to limited supply
2284 */
2285 if ((adapter->rss_queues > 4) ||
2286 ((adapter->rss_queues > 1) && (adapter->vfs_allocated_count > 6)))
2287 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2288
a6b623e0 2289 /* This call may decrease the number of queues */
047e0030 2290 if (igb_init_interrupt_scheme(adapter)) {
9d5c8243
AK		 2291 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
2292 return -ENOMEM;
2293 }
2294
115f459a 2295 igb_init_hw_timer(adapter);
a6b623e0
AD		 2296 igb_probe_vfs(adapter);
2297
9d5c8243
AK		 2298 /* Explicitly disable IRQ since the NIC can be in any state. */
2299 igb_irq_disable(adapter);
2300
2301 set_bit(__IGB_DOWN, &adapter->state);
2302 return 0;
2303}
2304
2305/**
2306 * igb_open - Called when a network interface is made active
2307 * @netdev: network interface device structure
2308 *
2309 * Returns 0 on success, negative value on failure
2310 *
2311 * The open entry point is called when a network interface is made
2312 * active by the system (IFF_UP). At this point all resources needed
2313 * for transmit and receive operations are allocated, the interrupt
2314 * handler is registered with the OS, the watchdog timer is started,
2315 * and the stack is notified that the interface is ready.
2316 **/
2317static int igb_open(struct net_device *netdev)
2318{
2319 struct igb_adapter *adapter = netdev_priv(netdev);
2320 struct e1000_hw *hw = &adapter->hw;
2321 int err;
2322 int i;
2323
2324 /* disallow open during test */
2325 if (test_bit(__IGB_TESTING, &adapter->state))
2326 return -EBUSY;
2327
b168dfc5
JB		 2328 netif_carrier_off(netdev);
2329
9d5c8243
AK		 2330 /* allocate transmit descriptors */
2331 err = igb_setup_all_tx_resources(adapter);
2332 if (err)
2333 goto err_setup_tx;
2334
2335 /* allocate receive descriptors */
2336 err = igb_setup_all_rx_resources(adapter);
2337 if (err)
2338 goto err_setup_rx;
2339
88a268c1 2340 igb_power_up_link(adapter);
9d5c8243 2341
9d5c8243
AK		 2342 /* before we allocate an interrupt, we must be ready to handle it.
2343 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
2344 * as soon as we call pci_request_irq, so we have to setup our
2345 * clean_rx handler before we do so. */
2346 igb_configure(adapter);
2347
2348 err = igb_request_irq(adapter);
2349 if (err)
2350 goto err_req_irq;
2351
2352 /* From here on the code is the same as igb_up() */
2353 clear_bit(__IGB_DOWN, &adapter->state);
2354
047e0030
AD		 2355 for (i = 0; i < adapter->num_q_vectors; i++) {
2356 struct igb_q_vector *q_vector = adapter->q_vector[i];
2357 napi_enable(&q_vector->napi);
2358 }
9d5c8243
AK		 2359
2360 /* Clear any pending interrupts. */
2361 rd32(E1000_ICR);
844290e5
PW		 2362
2363 igb_irq_enable(adapter);
2364
d4960307
AD		 2365 /* notify VFs that reset has been completed */
2366 if (adapter->vfs_allocated_count) {
2367 u32 reg_data = rd32(E1000_CTRL_EXT);
2368 reg_data |= E1000_CTRL_EXT_PFRSTD;
2369 wr32(E1000_CTRL_EXT, reg_data);
2370 }
2371
d55b53ff
JK		 2372 netif_tx_start_all_queues(netdev);
2373
25568a53
AD		 2374 /* start the watchdog. */
2375 hw->mac.get_link_status = 1;
2376 schedule_work(&adapter->watchdog_task);
9d5c8243
AK		 2377
2378 return 0;
2379
2380err_req_irq:
2381 igb_release_hw_control(adapter);
88a268c1 2382 igb_power_down_link(adapter);
9d5c8243
AK		 2383 igb_free_all_rx_resources(adapter);
2384err_setup_rx:
2385 igb_free_all_tx_resources(adapter);
2386err_setup_tx:
2387 igb_reset(adapter);
2388
2389 return err;
2390}
2391
2392/**
2393 * igb_close - Disables a network interface
2394 * @netdev: network interface device structure
2395 *
2396 * Returns 0, this is not allowed to fail
2397 *
2398 * The close entry point is called when an interface is de-activated
2399 * by the OS. The hardware is still under the driver's control, but
2400 * needs to be disabled. A global MAC reset is issued to stop the
2401 * hardware, and all transmit and receive resources are freed.
2402 **/
2403static int igb_close(struct net_device *netdev)
2404{
2405 struct igb_adapter *adapter = netdev_priv(netdev);
2406
2407 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
2408 igb_down(adapter);
2409
2410 igb_free_irq(adapter);
2411
2412 igb_free_all_tx_resources(adapter);
2413 igb_free_all_rx_resources(adapter);
2414
9d5c8243
AK		 2415 return 0;
2416}
2417
2418/**
2419 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
9d5c8243
AK		 2420 * @tx_ring: tx descriptor ring (for a specific queue) to setup
2421 *
2422 * Return 0 on success, negative on failure
2423 **/
80785298 2424int igb_setup_tx_resources(struct igb_ring *tx_ring)
9d5c8243 2425{
59d71989 2426 struct device *dev = tx_ring->dev;
9d5c8243
AK		 2427 int size;
2428
2429 size = sizeof(struct igb_buffer) * tx_ring->count;
2430 tx_ring->buffer_info = vmalloc(size);
2431 if (!tx_ring->buffer_info)
2432 goto err;
2433 memset(tx_ring->buffer_info, 0, size);
2434
2435 /* round up to nearest 4K */
85e8d004 2436 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 2437 tx_ring->size = ALIGN(tx_ring->size, 4096);
2438
59d71989
AD		 2439 tx_ring->desc = dma_alloc_coherent(dev,
2440 tx_ring->size,
2441 &tx_ring->dma,
2442 GFP_KERNEL);
9d5c8243
AK		 2443
2444 if (!tx_ring->desc)
2445 goto err;
2446
9d5c8243
AK		 2447 tx_ring->next_to_use = 0;
2448 tx_ring->next_to_clean = 0;
9d5c8243
AK		 2449 return 0;
2450
2451err:
2452 vfree(tx_ring->buffer_info);
59d71989 2453 dev_err(dev,
9d5c8243
AK		 2454 "Unable to allocate memory for the transmit descriptor ring\n");
2455 return -ENOMEM;
2456}
2457
2458/**
2459 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
2460 * (Descriptors) for all queues
2461 * @adapter: board private structure
2462 *
2463 * Return 0 on success, negative on failure
2464 **/
2465static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
2466{
439705e1 2467 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2468 int i, err = 0;
2469
2470 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 2471 err = igb_setup_tx_resources(adapter->tx_ring[i]);
9d5c8243 2472 if (err) {
439705e1 2473 dev_err(&pdev->dev,
9d5c8243
AK		 2474 "Allocation for Tx Queue %u failed\n", i);
2475 for (i--; i >= 0; i--)
3025a446 2476 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 2477 break;
2478 }
2479 }
2480
a99955fc 2481 for (i = 0; i < IGB_ABS_MAX_TX_QUEUES; i++) {
439705e1 2482 int r_idx = i % adapter->num_tx_queues;
3025a446 2483 adapter->multi_tx_table[i] = adapter->tx_ring[r_idx];
eebbbdba 2484 }
9d5c8243
AK		 2485 return err;
2486}
2487
2488/**
85b430b4
AD		 2489 * igb_setup_tctl - configure the transmit control registers
2490 * @adapter: Board private structure
9d5c8243 2491 **/
d7ee5b3a 2492void igb_setup_tctl(struct igb_adapter *adapter)
9d5c8243 2493{
9d5c8243
AK		 2494 struct e1000_hw *hw = &adapter->hw;
2495 u32 tctl;
9d5c8243 2496
85b430b4
AD		 2497 /* disable queue 0 which is enabled by default on 82575 and 82576 */
2498 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 2499
2500 /* Program the Transmit Control Register */
9d5c8243
AK		 2501 tctl = rd32(E1000_TCTL);
2502 tctl &= ~E1000_TCTL_CT;
2503 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2504 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2505
2506 igb_config_collision_dist(hw);
2507
9d5c8243
AK		 2508 /* Enable transmits */
2509 tctl |= E1000_TCTL_EN;
2510
2511 wr32(E1000_TCTL, tctl);
2512}
2513
85b430b4
AD		 2514/**
2515 * igb_configure_tx_ring - Configure transmit ring after Reset
2516 * @adapter: board private structure
2517 * @ring: tx ring to configure
2518 *
2519 * Configure a transmit ring after a reset.
2520 **/
d7ee5b3a
AD		 2521void igb_configure_tx_ring(struct igb_adapter *adapter,
2522 struct igb_ring *ring)
85b430b4
AD		 2523{
2524 struct e1000_hw *hw = &adapter->hw;
2525 u32 txdctl;
2526 u64 tdba = ring->dma;
2527 int reg_idx = ring->reg_idx;
2528
2529 /* disable the queue */
2530 txdctl = rd32(E1000_TXDCTL(reg_idx));
2531 wr32(E1000_TXDCTL(reg_idx),
2532 txdctl & ~E1000_TXDCTL_QUEUE_ENABLE);
2533 wrfl();
2534 mdelay(10);
2535
2536 wr32(E1000_TDLEN(reg_idx),
2537 ring->count * sizeof(union e1000_adv_tx_desc));
2538 wr32(E1000_TDBAL(reg_idx),
2539 tdba & 0x00000000ffffffffULL);
2540 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
2541
fce99e34
AD		 2542 ring->head = hw->hw_addr + E1000_TDH(reg_idx);
2543 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
2544 writel(0, ring->head);
2545 writel(0, ring->tail);
85b430b4
AD		 2546
2547 txdctl |= IGB_TX_PTHRESH;
2548 txdctl |= IGB_TX_HTHRESH << 8;
2549 txdctl |= IGB_TX_WTHRESH << 16;
2550
2551 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
2552 wr32(E1000_TXDCTL(reg_idx), txdctl);
2553}
2554
2555/**
2556 * igb_configure_tx - Configure transmit Unit after Reset
2557 * @adapter: board private structure
2558 *
2559 * Configure the Tx unit of the MAC after a reset.
2560 **/
2561static void igb_configure_tx(struct igb_adapter *adapter)
2562{
2563 int i;
2564
2565 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 2566 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
85b430b4
AD		 2567}
2568
9d5c8243
AK		 2569/**
2570 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
9d5c8243
AK		 2571 * @rx_ring: rx descriptor ring (for a specific queue) to setup
2572 *
2573 * Returns 0 on success, negative on failure
2574 **/
80785298 2575int igb_setup_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2576{
59d71989 2577 struct device *dev = rx_ring->dev;
9d5c8243
AK		 2578 int size, desc_len;
2579
2580 size = sizeof(struct igb_buffer) * rx_ring->count;
2581 rx_ring->buffer_info = vmalloc(size);
2582 if (!rx_ring->buffer_info)
2583 goto err;
2584 memset(rx_ring->buffer_info, 0, size);
2585
2586 desc_len = sizeof(union e1000_adv_rx_desc);
2587
2588 /* Round up to nearest 4K */
2589 rx_ring->size = rx_ring->count * desc_len;
2590 rx_ring->size = ALIGN(rx_ring->size, 4096);
2591
59d71989
AD		 2592 rx_ring->desc = dma_alloc_coherent(dev,
2593 rx_ring->size,
2594 &rx_ring->dma,
2595 GFP_KERNEL);
9d5c8243
AK		 2596
2597 if (!rx_ring->desc)
2598 goto err;
2599
2600 rx_ring->next_to_clean = 0;
2601 rx_ring->next_to_use = 0;
9d5c8243 2602
9d5c8243
AK		 2603 return 0;
2604
2605err:
2606 vfree(rx_ring->buffer_info);
439705e1 2607 rx_ring->buffer_info = NULL;
59d71989
AD		 2608 dev_err(dev, "Unable to allocate memory for the receive descriptor"
2609 " ring\n");
9d5c8243
AK		 2610 return -ENOMEM;
2611}
2612
2613/**
2614 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
2615 * (Descriptors) for all queues
2616 * @adapter: board private structure
2617 *
2618 * Return 0 on success, negative on failure
2619 **/
2620static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
2621{
439705e1 2622 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2623 int i, err = 0;
2624
2625 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 2626 err = igb_setup_rx_resources(adapter->rx_ring[i]);
9d5c8243 2627 if (err) {
439705e1 2628 dev_err(&pdev->dev,
9d5c8243
AK		 2629 "Allocation for Rx Queue %u failed\n", i);
2630 for (i--; i >= 0; i--)
3025a446 2631 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 2632 break;
2633 }
2634 }
2635
2636 return err;
2637}
2638
06cf2666
AD		 2639/**
2640 * igb_setup_mrqc - configure the multiple receive queue control registers
2641 * @adapter: Board private structure
2642 **/
2643static void igb_setup_mrqc(struct igb_adapter *adapter)
2644{
2645 struct e1000_hw *hw = &adapter->hw;
2646 u32 mrqc, rxcsum;
2647 u32 j, num_rx_queues, shift = 0, shift2 = 0;
2648 union e1000_reta {
2649 u32 dword;
2650 u8 bytes[4];
2651 } reta;
2652 static const u8 rsshash[40] = {
2653 0x6d, 0x5a, 0x56, 0xda, 0x25, 0x5b, 0x0e, 0xc2, 0x41, 0x67,
2654 0x25, 0x3d, 0x43, 0xa3, 0x8f, 0xb0, 0xd0, 0xca, 0x2b, 0xcb,
2655 0xae, 0x7b, 0x30, 0xb4, 0x77, 0xcb, 0x2d, 0xa3, 0x80, 0x30,
2656 0xf2, 0x0c, 0x6a, 0x42, 0xb7, 0x3b, 0xbe, 0xac, 0x01, 0xfa };
2657
2658 /* Fill out hash function seeds */
2659 for (j = 0; j < 10; j++) {
2660 u32 rsskey = rsshash[(j * 4)];
2661 rsskey |= rsshash[(j * 4) + 1] << 8;
2662 rsskey |= rsshash[(j * 4) + 2] << 16;
2663 rsskey |= rsshash[(j * 4) + 3] << 24;
2664 array_wr32(E1000_RSSRK(0), j, rsskey);
2665 }
2666
a99955fc 2667 num_rx_queues = adapter->rss_queues;
06cf2666
AD		 2668
2669 if (adapter->vfs_allocated_count) {
2670 /* 82575 and 82576 supports 2 RSS queues for VMDq */
2671 switch (hw->mac.type) {
d2ba2ed8 2672 case e1000_i350:
55cac248
AD		 2673 case e1000_82580:
2674 num_rx_queues = 1;
2675 shift = 0;
2676 break;
06cf2666
AD		 2677 case e1000_82576:
2678 shift = 3;
2679 num_rx_queues = 2;
2680 break;
2681 case e1000_82575:
2682 shift = 2;
2683 shift2 = 6;
2684 default:
2685 break;
2686 }
2687 } else {
2688 if (hw->mac.type == e1000_82575)
2689 shift = 6;
2690 }
2691
2692 for (j = 0; j < (32 * 4); j++) {
2693 reta.bytes[j & 3] = (j % num_rx_queues) << shift;
2694 if (shift2)
2695 reta.bytes[j & 3] |= num_rx_queues << shift2;
2696 if ((j & 3) == 3)
2697 wr32(E1000_RETA(j >> 2), reta.dword);
2698 }
2699
2700 /*
2701 * Disable raw packet checksumming so that RSS hash is placed in
2702 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
2703 * offloads as they are enabled by default
2704 */
2705 rxcsum = rd32(E1000_RXCSUM);
2706 rxcsum |= E1000_RXCSUM_PCSD;
2707
2708 if (adapter->hw.mac.type >= e1000_82576)
2709 /* Enable Receive Checksum Offload for SCTP */
2710 rxcsum |= E1000_RXCSUM_CRCOFL;
2711
2712 /* Don't need to set TUOFL or IPOFL, they default to 1 */
2713 wr32(E1000_RXCSUM, rxcsum);
2714
2715 /* If VMDq is enabled then we set the appropriate mode for that, else
2716 * we default to RSS so that an RSS hash is calculated per packet even
2717 * if we are only using one queue */
2718 if (adapter->vfs_allocated_count) {
2719 if (hw->mac.type > e1000_82575) {
2720 /* Set the default pool for the PF's first queue */
2721 u32 vtctl = rd32(E1000_VT_CTL);
2722 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
2723 E1000_VT_CTL_DISABLE_DEF_POOL);
2724 vtctl |= adapter->vfs_allocated_count <<
2725 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
2726 wr32(E1000_VT_CTL, vtctl);
2727 }
a99955fc 2728 if (adapter->rss_queues > 1)
06cf2666
AD		 2729 mrqc = E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
2730 else
2731 mrqc = E1000_MRQC_ENABLE_VMDQ;
2732 } else {
2733 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
2734 }
2735 igb_vmm_control(adapter);
2736
4478a9cd
AD		 2737 /*
2738 * Generate RSS hash based on TCP port numbers and/or
2739 * IPv4/v6 src and dst addresses since UDP cannot be
2740 * hashed reliably due to IP fragmentation
2741 */
2742 mrqc |= E1000_MRQC_RSS_FIELD_IPV4 |
2743 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2744 E1000_MRQC_RSS_FIELD_IPV6 |
2745 E1000_MRQC_RSS_FIELD_IPV6_TCP |
2746 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
06cf2666
AD		 2747
2748 wr32(E1000_MRQC, mrqc);
2749}
2750
9d5c8243
AK		 2751/**
2752 * igb_setup_rctl - configure the receive control registers
2753 * @adapter: Board private structure
2754 **/
d7ee5b3a 2755void igb_setup_rctl(struct igb_adapter *adapter)
9d5c8243
AK		 2756{
2757 struct e1000_hw *hw = &adapter->hw;
2758 u32 rctl;
9d5c8243
AK		 2759
2760 rctl = rd32(E1000_RCTL);
2761
2762 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 2763 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 2764
69d728ba 2765 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 2766 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 2767
87cb7e8c
AK		 2768 /*
2769 * enable stripping of CRC. It's unlikely this will break BMC
2770 * redirection as it did with e1000. Newer features require
2771 * that the HW strips the CRC.
73cd78f1 2772 */
87cb7e8c 2773 rctl |= E1000_RCTL_SECRC;
9d5c8243 2774
559e9c49 2775 /* disable store bad packets and clear size bits. */
ec54d7d6 2776 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 2777
6ec43fe6
AD		 2778 /* enable LPE to prevent packets larger than max_frame_size */
2779 rctl |= E1000_RCTL_LPE;
9d5c8243 2780
952f72a8
AD		 2781 /* disable queue 0 to prevent tail write w/o re-config */
2782 wr32(E1000_RXDCTL(0), 0);
9d5c8243 2783
e1739522
AD		 2784 /* Attention!!! For SR-IOV PF driver operations you must enable
2785 * queue drop for all VF and PF queues to prevent head of line blocking
2786 * if an un-trusted VF does not provide descriptors to hardware.
2787 */
2788 if (adapter->vfs_allocated_count) {
e1739522
AD		 2789 /* set all queue drop enable bits */
2790 wr32(E1000_QDE, ALL_QUEUES);
e1739522
AD		 2791 }
2792
9d5c8243
AK		 2793 wr32(E1000_RCTL, rctl);
2794}
2795
7d5753f0
AD		 2796static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
2797 int vfn)
2798{
2799 struct e1000_hw *hw = &adapter->hw;
2800 u32 vmolr;
2801
2802 /* if it isn't the PF check to see if VFs are enabled and
2803 * increase the size to support vlan tags */
2804 if (vfn < adapter->vfs_allocated_count &&
2805 adapter->vf_data[vfn].vlans_enabled)
2806 size += VLAN_TAG_SIZE;
2807
2808 vmolr = rd32(E1000_VMOLR(vfn));
2809 vmolr &= ~E1000_VMOLR_RLPML_MASK;
2810 vmolr |= size | E1000_VMOLR_LPE;
2811 wr32(E1000_VMOLR(vfn), vmolr);
2812
2813 return 0;
2814}
2815
e1739522
AD		 2816/**
2817 * igb_rlpml_set - set maximum receive packet size
2818 * @adapter: board private structure
2819 *
2820 * Configure maximum receivable packet size.
2821 **/
2822static void igb_rlpml_set(struct igb_adapter *adapter)
2823{
2824 u32 max_frame_size = adapter->max_frame_size;
2825 struct e1000_hw *hw = &adapter->hw;
2826 u16 pf_id = adapter->vfs_allocated_count;
2827
2828 if (adapter->vlgrp)
2829 max_frame_size += VLAN_TAG_SIZE;
2830
2831 /* if vfs are enabled we set RLPML to the largest possible request
2832 * size and set the VMOLR RLPML to the size we need */
2833 if (pf_id) {
2834 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
7d5753f0 2835 max_frame_size = MAX_JUMBO_FRAME_SIZE;
e1739522
AD		 2836 }
2837
2838 wr32(E1000_RLPML, max_frame_size);
2839}
2840
8151d294
WM		 2841static inline void igb_set_vmolr(struct igb_adapter *adapter,
2842 int vfn, bool aupe)
7d5753f0
AD		 2843{
2844 struct e1000_hw *hw = &adapter->hw;
2845 u32 vmolr;
2846
2847 /*
2848 * This register exists only on 82576 and newer so if we are older then
2849 * we should exit and do nothing
2850 */
2851 if (hw->mac.type < e1000_82576)
2852 return;
2853
2854 vmolr = rd32(E1000_VMOLR(vfn));
8151d294
WM		 2855 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
2856 if (aupe)
2857 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
2858 else
2859 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
7d5753f0
AD		 2860
2861 /* clear all bits that might not be set */
2862 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
2863
a99955fc 2864 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
7d5753f0
AD		 2865 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
2866 /*
2867 * for VMDq only allow the VFs and pool 0 to accept broadcast and
2868 * multicast packets
2869 */
2870 if (vfn <= adapter->vfs_allocated_count)
2871 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
2872
2873 wr32(E1000_VMOLR(vfn), vmolr);
2874}
2875
85b430b4
AD		 2876/**
2877 * igb_configure_rx_ring - Configure a receive ring after Reset
2878 * @adapter: board private structure
2879 * @ring: receive ring to be configured
2880 *
2881 * Configure the Rx unit of the MAC after a reset.
2882 **/
d7ee5b3a
AD		 2883void igb_configure_rx_ring(struct igb_adapter *adapter,
2884 struct igb_ring *ring)
85b430b4
AD		 2885{
2886 struct e1000_hw *hw = &adapter->hw;
2887 u64 rdba = ring->dma;
2888 int reg_idx = ring->reg_idx;
952f72a8 2889 u32 srrctl, rxdctl;
85b430b4
AD		 2890
2891 /* disable the queue */
2892 rxdctl = rd32(E1000_RXDCTL(reg_idx));
2893 wr32(E1000_RXDCTL(reg_idx),
2894 rxdctl & ~E1000_RXDCTL_QUEUE_ENABLE);
2895
2896 /* Set DMA base address registers */
2897 wr32(E1000_RDBAL(reg_idx),
2898 rdba & 0x00000000ffffffffULL);
2899 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
2900 wr32(E1000_RDLEN(reg_idx),
2901 ring->count * sizeof(union e1000_adv_rx_desc));
2902
2903 /* initialize head and tail */
fce99e34
AD		 2904 ring->head = hw->hw_addr + E1000_RDH(reg_idx);
2905 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
2906 writel(0, ring->head);
2907 writel(0, ring->tail);
85b430b4 2908
952f72a8 2909 /* set descriptor configuration */
4c844851
AD		 2910 if (ring->rx_buffer_len < IGB_RXBUFFER_1024) {
2911 srrctl = ALIGN(ring->rx_buffer_len, 64) <<
952f72a8
AD		 2912 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2913#if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
2914 srrctl |= IGB_RXBUFFER_16384 >>
2915 E1000_SRRCTL_BSIZEPKT_SHIFT;
2916#else
2917 srrctl |= (PAGE_SIZE / 2) >>
2918 E1000_SRRCTL_BSIZEPKT_SHIFT;
2919#endif
2920 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2921 } else {
4c844851 2922 srrctl = ALIGN(ring->rx_buffer_len, 1024) >>
952f72a8
AD		 2923 E1000_SRRCTL_BSIZEPKT_SHIFT;
2924 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2925 }
757b77e2
NN		 2926 if (hw->mac.type == e1000_82580)
2927 srrctl |= E1000_SRRCTL_TIMESTAMP;
e6bdb6fe
NN		 2928 /* Only set Drop Enable if we are supporting multiple queues */
2929 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
2930 srrctl |= E1000_SRRCTL_DROP_EN;
952f72a8
AD		 2931
2932 wr32(E1000_SRRCTL(reg_idx), srrctl);
2933
7d5753f0 2934 /* set filtering for VMDQ pools */
8151d294 2935 igb_set_vmolr(adapter, reg_idx & 0x7, true);
7d5753f0 2936
85b430b4
AD		 2937 /* enable receive descriptor fetching */
2938 rxdctl = rd32(E1000_RXDCTL(reg_idx));
2939 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2940 rxdctl &= 0xFFF00000;
2941 rxdctl |= IGB_RX_PTHRESH;
2942 rxdctl |= IGB_RX_HTHRESH << 8;
2943 rxdctl |= IGB_RX_WTHRESH << 16;
2944 wr32(E1000_RXDCTL(reg_idx), rxdctl);
2945}
2946
9d5c8243
AK		 2947/**
2948 * igb_configure_rx - Configure receive Unit after Reset
2949 * @adapter: board private structure
2950 *
2951 * Configure the Rx unit of the MAC after a reset.
2952 **/
2953static void igb_configure_rx(struct igb_adapter *adapter)
2954{
9107584e 2955 int i;
9d5c8243 2956
68d480c4
AD		 2957 /* set UTA to appropriate mode */
2958 igb_set_uta(adapter);
2959
26ad9178
AD		 2960 /* set the correct pool for the PF default MAC address in entry 0 */
2961 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
2962 adapter->vfs_allocated_count);
2963
06cf2666
AD		 2964 /* Setup the HW Rx Head and Tail Descriptor Pointers and
2965 * the Base and Length of the Rx Descriptor Ring */
2966 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 2967 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
9d5c8243
AK		 2968}
2969
2970/**
2971 * igb_free_tx_resources - Free Tx Resources per Queue
9d5c8243
AK		 2972 * @tx_ring: Tx descriptor ring for a specific queue
2973 *
2974 * Free all transmit software resources
2975 **/
68fd9910 2976void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 2977{
3b644cf6 2978 igb_clean_tx_ring(tx_ring);
9d5c8243
AK		 2979
2980 vfree(tx_ring->buffer_info);
2981 tx_ring->buffer_info = NULL;
2982
439705e1
AD		 2983 /* if not set, then don't free */
2984 if (!tx_ring->desc)
2985 return;
2986
59d71989
AD		 2987 dma_free_coherent(tx_ring->dev, tx_ring->size,
2988 tx_ring->desc, tx_ring->dma);
9d5c8243
AK		 2989
2990 tx_ring->desc = NULL;
2991}
2992
2993/**
2994 * igb_free_all_tx_resources - Free Tx Resources for All Queues
2995 * @adapter: board private structure
2996 *
2997 * Free all transmit software resources
2998 **/
2999static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3000{
3001 int i;
3002
3003 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3004 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3005}
3006
b1a436c3
AD		 3007void igb_unmap_and_free_tx_resource(struct igb_ring *tx_ring,
3008 struct igb_buffer *buffer_info)
9d5c8243 3009{
6366ad33
AD		 3010 if (buffer_info->dma) {
3011 if (buffer_info->mapped_as_page)
59d71989 3012 dma_unmap_page(tx_ring->dev,
6366ad33
AD		 3013 buffer_info->dma,
3014 buffer_info->length,
59d71989 3015 DMA_TO_DEVICE);
6366ad33 3016 else
59d71989 3017 dma_unmap_single(tx_ring->dev,
6366ad33
AD		 3018 buffer_info->dma,
3019 buffer_info->length,
59d71989 3020 DMA_TO_DEVICE);
6366ad33
AD		 3021 buffer_info->dma = 0;
3022 }
9d5c8243
AK		 3023 if (buffer_info->skb) {
3024 dev_kfree_skb_any(buffer_info->skb);
3025 buffer_info->skb = NULL;
3026 }
3027 buffer_info->time_stamp = 0;
6366ad33
AD		 3028 buffer_info->length = 0;
3029 buffer_info->next_to_watch = 0;
3030 buffer_info->mapped_as_page = false;
9d5c8243
AK		 3031}
3032
3033/**
3034 * igb_clean_tx_ring - Free Tx Buffers
9d5c8243
AK		 3035 * @tx_ring: ring to be cleaned
3036 **/
3b644cf6 3037static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243
AK		 3038{
3039 struct igb_buffer *buffer_info;
3040 unsigned long size;
3041 unsigned int i;
3042
3043 if (!tx_ring->buffer_info)
3044 return;
3045 /* Free all the Tx ring sk_buffs */
3046
3047 for (i = 0; i < tx_ring->count; i++) {
3048 buffer_info = &tx_ring->buffer_info[i];
80785298 3049 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
9d5c8243
AK		 3050 }
3051
3052 size = sizeof(struct igb_buffer) * tx_ring->count;
3053 memset(tx_ring->buffer_info, 0, size);
3054
3055 /* Zero out the descriptor ring */
9d5c8243
AK		 3056 memset(tx_ring->desc, 0, tx_ring->size);
3057
3058 tx_ring->next_to_use = 0;
3059 tx_ring->next_to_clean = 0;
9d5c8243
AK		 3060}
3061
3062/**
3063 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3064 * @adapter: board private structure
3065 **/
3066static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3067{
3068 int i;
3069
3070 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3071 igb_clean_tx_ring(adapter->tx_ring[i]);
9d5c8243
AK		 3072}
3073
3074/**
3075 * igb_free_rx_resources - Free Rx Resources
9d5c8243
AK		 3076 * @rx_ring: ring to clean the resources from
3077 *
3078 * Free all receive software resources
3079 **/
68fd9910 3080void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3081{
3b644cf6 3082 igb_clean_rx_ring(rx_ring);
9d5c8243
AK		 3083
3084 vfree(rx_ring->buffer_info);
3085 rx_ring->buffer_info = NULL;
3086
439705e1
AD		 3087 /* if not set, then don't free */
3088 if (!rx_ring->desc)
3089 return;
3090
59d71989
AD		 3091 dma_free_coherent(rx_ring->dev, rx_ring->size,
3092 rx_ring->desc, rx_ring->dma);
9d5c8243
AK		 3093
3094 rx_ring->desc = NULL;
3095}
3096
3097/**
3098 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3099 * @adapter: board private structure
3100 *
3101 * Free all receive software resources
3102 **/
3103static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3104{
3105 int i;
3106
3107 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3108 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3109}
3110
3111/**
3112 * igb_clean_rx_ring - Free Rx Buffers per Queue
9d5c8243
AK		 3113 * @rx_ring: ring to free buffers from
3114 **/
3b644cf6 3115static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243
AK		 3116{
3117 struct igb_buffer *buffer_info;
9d5c8243
AK		 3118 unsigned long size;
3119 unsigned int i;
3120
3121 if (!rx_ring->buffer_info)
3122 return;
439705e1 3123
9d5c8243
AK		 3124 /* Free all the Rx ring sk_buffs */
3125 for (i = 0; i < rx_ring->count; i++) {
3126 buffer_info = &rx_ring->buffer_info[i];
3127 if (buffer_info->dma) {
59d71989 3128 dma_unmap_single(rx_ring->dev,
80785298 3129 buffer_info->dma,
4c844851 3130 rx_ring->rx_buffer_len,
59d71989 3131 DMA_FROM_DEVICE);
9d5c8243
AK		 3132 buffer_info->dma = 0;
3133 }
3134
3135 if (buffer_info->skb) {
3136 dev_kfree_skb(buffer_info->skb);
3137 buffer_info->skb = NULL;
3138 }
6ec43fe6 3139 if (buffer_info->page_dma) {
59d71989 3140 dma_unmap_page(rx_ring->dev,
80785298 3141 buffer_info->page_dma,
6ec43fe6 3142 PAGE_SIZE / 2,
59d71989 3143 DMA_FROM_DEVICE);
6ec43fe6
AD		 3144 buffer_info->page_dma = 0;
3145 }
9d5c8243 3146 if (buffer_info->page) {
9d5c8243
AK		 3147 put_page(buffer_info->page);
3148 buffer_info->page = NULL;
bf36c1a0 3149 buffer_info->page_offset = 0;
9d5c8243
AK		 3150 }
3151 }
3152
9d5c8243
AK		 3153 size = sizeof(struct igb_buffer) * rx_ring->count;
3154 memset(rx_ring->buffer_info, 0, size);
3155
3156 /* Zero out the descriptor ring */
3157 memset(rx_ring->desc, 0, rx_ring->size);
3158
3159 rx_ring->next_to_clean = 0;
3160 rx_ring->next_to_use = 0;
9d5c8243
AK		 3161}
3162
3163/**
3164 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3165 * @adapter: board private structure
3166 **/
3167static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3168{
3169 int i;
3170
3171 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3172 igb_clean_rx_ring(adapter->rx_ring[i]);
9d5c8243
AK		 3173}
3174
3175/**
3176 * igb_set_mac - Change the Ethernet Address of the NIC
3177 * @netdev: network interface device structure
3178 * @p: pointer to an address structure
3179 *
3180 * Returns 0 on success, negative on failure
3181 **/
3182static int igb_set_mac(struct net_device *netdev, void *p)
3183{
3184 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 3185 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 3186 struct sockaddr *addr = p;
3187
3188 if (!is_valid_ether_addr(addr->sa_data))
3189 return -EADDRNOTAVAIL;
3190
3191 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 3192 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 3193
26ad9178
AD		 3194 /* set the correct pool for the new PF MAC address in entry 0 */
3195 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
3196 adapter->vfs_allocated_count);
e1739522 3197
9d5c8243
AK		 3198 return 0;
3199}
3200
3201/**
68d480c4 3202 * igb_write_mc_addr_list - write multicast addresses to MTA
9d5c8243
AK		 3203 * @netdev: network interface device structure
3204 *
68d480c4
AD		 3205 * Writes multicast address list to the MTA hash table.
3206 * Returns: -ENOMEM on failure
3207 * 0 on no addresses written
3208 * X on writing X addresses to MTA
9d5c8243 3209 **/
68d480c4 3210static int igb_write_mc_addr_list(struct net_device *netdev)
9d5c8243
AK		 3211{
3212 struct igb_adapter *adapter = netdev_priv(netdev);
3213 struct e1000_hw *hw = &adapter->hw;
22bedad3 3214 struct netdev_hw_addr *ha;
68d480c4 3215 u8 *mta_list;
9d5c8243
AK		 3216 int i;
3217
4cd24eaf 3218 if (netdev_mc_empty(netdev)) {
68d480c4
AD		 3219 /* nothing to program, so clear mc list */
3220 igb_update_mc_addr_list(hw, NULL, 0);
3221 igb_restore_vf_multicasts(adapter);
3222 return 0;
3223 }
9d5c8243 3224
4cd24eaf 3225 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
68d480c4
AD		 3226 if (!mta_list)
3227 return -ENOMEM;
ff41f8dc 3228
68d480c4 3229 /* The shared function expects a packed array of only addresses. */
48e2f183 3230 i = 0;
22bedad3
JP		 3231 netdev_for_each_mc_addr(ha, netdev)
3232 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
68d480c4 3233
68d480c4
AD		 3234 igb_update_mc_addr_list(hw, mta_list, i);
3235 kfree(mta_list);
3236
4cd24eaf 3237 return netdev_mc_count(netdev);
68d480c4
AD		 3238}
3239
3240/**
3241 * igb_write_uc_addr_list - write unicast addresses to RAR table
3242 * @netdev: network interface device structure
3243 *
3244 * Writes unicast address list to the RAR table.
3245 * Returns: -ENOMEM on failure/insufficient address space
3246 * 0 on no addresses written
3247 * X on writing X addresses to the RAR table
3248 **/
3249static int igb_write_uc_addr_list(struct net_device *netdev)
3250{
3251 struct igb_adapter *adapter = netdev_priv(netdev);
3252 struct e1000_hw *hw = &adapter->hw;
3253 unsigned int vfn = adapter->vfs_allocated_count;
3254 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3255 int count = 0;
3256
3257 /* return ENOMEM indicating insufficient memory for addresses */
32e7bfc4 3258 if (netdev_uc_count(netdev) > rar_entries)
68d480c4 3259 return -ENOMEM;
9d5c8243 3260
32e7bfc4 3261 if (!netdev_uc_empty(netdev) && rar_entries) {
ff41f8dc 3262 struct netdev_hw_addr *ha;
32e7bfc4
JP		 3263
3264 netdev_for_each_uc_addr(ha, netdev) {
ff41f8dc
AD		 3265 if (!rar_entries)
3266 break;
26ad9178
AD		 3267 igb_rar_set_qsel(adapter, ha->addr,
3268 rar_entries--,
68d480c4
AD		 3269 vfn);
3270 count++;
ff41f8dc
AD		 3271 }
3272 }
3273 /* write the addresses in reverse order to avoid write combining */
3274 for (; rar_entries > 0 ; rar_entries--) {
3275 wr32(E1000_RAH(rar_entries), 0);
3276 wr32(E1000_RAL(rar_entries), 0);
3277 }
3278 wrfl();
3279
68d480c4
AD		 3280 return count;
3281}
3282
3283/**
3284 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3285 * @netdev: network interface device structure
3286 *
3287 * The set_rx_mode entry point is called whenever the unicast or multicast
3288 * address lists or the network interface flags are updated. This routine is
3289 * responsible for configuring the hardware for proper unicast, multicast,
3290 * promiscuous mode, and all-multi behavior.
3291 **/
3292static void igb_set_rx_mode(struct net_device *netdev)
3293{
3294 struct igb_adapter *adapter = netdev_priv(netdev);
3295 struct e1000_hw *hw = &adapter->hw;
3296 unsigned int vfn = adapter->vfs_allocated_count;
3297 u32 rctl, vmolr = 0;
3298 int count;
3299
3300 /* Check for Promiscuous and All Multicast modes */
3301 rctl = rd32(E1000_RCTL);
3302
3303 /* clear the effected bits */
3304 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
3305
3306 if (netdev->flags & IFF_PROMISC) {
3307 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3308 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
3309 } else {
3310 if (netdev->flags & IFF_ALLMULTI) {
3311 rctl |= E1000_RCTL_MPE;
3312 vmolr |= E1000_VMOLR_MPME;
3313 } else {
3314 /*
3315 * Write addresses to the MTA, if the attempt fails
3316 * then we should just turn on promiscous mode so
3317 * that we can at least receive multicast traffic
3318 */
3319 count = igb_write_mc_addr_list(netdev);
3320 if (count < 0) {
3321 rctl |= E1000_RCTL_MPE;
3322 vmolr |= E1000_VMOLR_MPME;
3323 } else if (count) {
3324 vmolr |= E1000_VMOLR_ROMPE;
3325 }
3326 }
3327 /*
3328 * Write addresses to available RAR registers, if there is not
3329 * sufficient space to store all the addresses then enable
3330 * unicast promiscous mode
3331 */
3332 count = igb_write_uc_addr_list(netdev);
3333 if (count < 0) {
3334 rctl |= E1000_RCTL_UPE;
3335 vmolr |= E1000_VMOLR_ROPE;
3336 }
3337 rctl |= E1000_RCTL_VFE;
28fc06f5 3338 }
68d480c4 3339 wr32(E1000_RCTL, rctl);
28fc06f5 3340
68d480c4
AD		 3341 /*
3342 * In order to support SR-IOV and eventually VMDq it is necessary to set
3343 * the VMOLR to enable the appropriate modes. Without this workaround
3344 * we will have issues with VLAN tag stripping not being done for frames
3345 * that are only arriving because we are the default pool
3346 */
3347 if (hw->mac.type < e1000_82576)
28fc06f5 3348 return;
9d5c8243 3349
68d480c4
AD		 3350 vmolr |= rd32(E1000_VMOLR(vfn)) &
3351 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
3352 wr32(E1000_VMOLR(vfn), vmolr);
28fc06f5 3353 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 3354}
3355
3356/* Need to wait a few seconds after link up to get diagnostic information from
3357 * the phy */
3358static void igb_update_phy_info(unsigned long data)
3359{
3360 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 3361 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 3362}
3363
4d6b725e
AD		 3364/**
3365 * igb_has_link - check shared code for link and determine up/down
3366 * @adapter: pointer to driver private info
3367 **/
3145535a 3368bool igb_has_link(struct igb_adapter *adapter)
4d6b725e
AD		 3369{
3370 struct e1000_hw *hw = &adapter->hw;
3371 bool link_active = false;
3372 s32 ret_val = 0;
3373
3374 /* get_link_status is set on LSC (link status) interrupt or
3375 * rx sequence error interrupt. get_link_status will stay
3376 * false until the e1000_check_for_link establishes link
3377 * for copper adapters ONLY
3378 */
3379 switch (hw->phy.media_type) {
3380 case e1000_media_type_copper:
3381 if (hw->mac.get_link_status) {
3382 ret_val = hw->mac.ops.check_for_link(hw);
3383 link_active = !hw->mac.get_link_status;
3384 } else {
3385 link_active = true;
3386 }
3387 break;
4d6b725e
AD		 3388 case e1000_media_type_internal_serdes:
3389 ret_val = hw->mac.ops.check_for_link(hw);
3390 link_active = hw->mac.serdes_has_link;
3391 break;
3392 default:
3393 case e1000_media_type_unknown:
3394 break;
3395 }
3396
3397 return link_active;
3398}
3399
9d5c8243
AK		 3400/**
3401 * igb_watchdog - Timer Call-back
3402 * @data: pointer to adapter cast into an unsigned long
3403 **/
3404static void igb_watchdog(unsigned long data)
3405{
3406 struct igb_adapter *adapter = (struct igb_adapter *)data;
3407 /* Do the rest outside of interrupt context */
3408 schedule_work(&adapter->watchdog_task);
3409}
3410
3411static void igb_watchdog_task(struct work_struct *work)
3412{
3413 struct igb_adapter *adapter = container_of(work,
559e9c49
AD		 3414 struct igb_adapter,
3415 watchdog_task);
9d5c8243 3416 struct e1000_hw *hw = &adapter->hw;
9d5c8243 3417 struct net_device *netdev = adapter->netdev;
9d5c8243 3418 u32 link;
7a6ea550 3419 int i;
9d5c8243 3420
4d6b725e 3421 link = igb_has_link(adapter);
9d5c8243
AK		 3422 if (link) {
3423 if (!netif_carrier_ok(netdev)) {
3424 u32 ctrl;
330a6d6a
AD		 3425 hw->mac.ops.get_speed_and_duplex(hw,
3426 &adapter->link_speed,
3427 &adapter->link_duplex);
9d5c8243
AK		 3428
3429 ctrl = rd32(E1000_CTRL);
527d47c1
AD		 3430 /* Links status message must follow this format */
3431 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
9d5c8243 3432 "Flow Control: %s\n",
559e9c49
AD		 3433 netdev->name,
3434 adapter->link_speed,
3435 adapter->link_duplex == FULL_DUPLEX ?
9d5c8243 3436 "Full Duplex" : "Half Duplex",
559e9c49
AD		 3437 ((ctrl & E1000_CTRL_TFCE) &&
3438 (ctrl & E1000_CTRL_RFCE)) ? "RX/TX" :
3439 ((ctrl & E1000_CTRL_RFCE) ? "RX" :
3440 ((ctrl & E1000_CTRL_TFCE) ? "TX" : "None")));
9d5c8243 3441
d07f3e37 3442 /* adjust timeout factor according to speed/duplex */
9d5c8243
AK		 3443 adapter->tx_timeout_factor = 1;
3444 switch (adapter->link_speed) {
3445 case SPEED_10:
9d5c8243
AK		 3446 adapter->tx_timeout_factor = 14;
3447 break;
3448 case SPEED_100:
9d5c8243
AK		 3449 /* maybe add some timeout factor ? */
3450 break;
3451 }
3452
3453 netif_carrier_on(netdev);
9d5c8243 3454
4ae196df
AD		 3455 igb_ping_all_vfs(adapter);
3456
4b1a9877 3457 /* link state has changed, schedule phy info update */
9d5c8243
AK		 3458 if (!test_bit(__IGB_DOWN, &adapter->state))
3459 mod_timer(&adapter->phy_info_timer,
3460 round_jiffies(jiffies + 2 * HZ));
3461 }
3462 } else {
3463 if (netif_carrier_ok(netdev)) {
3464 adapter->link_speed = 0;
3465 adapter->link_duplex = 0;
527d47c1
AD		 3466 /* Links status message must follow this format */
3467 printk(KERN_INFO "igb: %s NIC Link is Down\n",
3468 netdev->name);
9d5c8243 3469 netif_carrier_off(netdev);
4b1a9877 3470
4ae196df
AD		 3471 igb_ping_all_vfs(adapter);
3472
4b1a9877 3473 /* link state has changed, schedule phy info update */
9d5c8243
AK		 3474 if (!test_bit(__IGB_DOWN, &adapter->state))
3475 mod_timer(&adapter->phy_info_timer,
3476 round_jiffies(jiffies + 2 * HZ));
3477 }
3478 }
3479
9d5c8243 3480 igb_update_stats(adapter);
9d5c8243 3481
dbabb065 3482 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 3483 struct igb_ring *tx_ring = adapter->tx_ring[i];
dbabb065 3484 if (!netif_carrier_ok(netdev)) {
9d5c8243
AK		 3485 /* We've lost link, so the controller stops DMA,
3486 * but we've got queued Tx work that's never going
3487 * to get done, so reset controller to flush Tx.
3488 * (Do the reset outside of interrupt context). */
dbabb065
AD		 3489 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
3490 adapter->tx_timeout_count++;
3491 schedule_work(&adapter->reset_task);
3492 /* return immediately since reset is imminent */
3493 return;
3494 }
9d5c8243 3495 }
9d5c8243 3496
dbabb065
AD		 3497 /* Force detection of hung controller every watchdog period */
3498 tx_ring->detect_tx_hung = true;
3499 }
f7ba205e 3500
9d5c8243 3501 /* Cause software interrupt to ensure rx ring is cleaned */
7a6ea550 3502 if (adapter->msix_entries) {
047e0030
AD		 3503 u32 eics = 0;
3504 for (i = 0; i < adapter->num_q_vectors; i++) {
3505 struct igb_q_vector *q_vector = adapter->q_vector[i];
3506 eics |= q_vector->eims_value;
3507 }
7a6ea550
AD		 3508 wr32(E1000_EICS, eics);
3509 } else {
3510 wr32(E1000_ICS, E1000_ICS_RXDMT0);
3511 }
9d5c8243 3512
9d5c8243
AK		 3513 /* Reset the timer */
3514 if (!test_bit(__IGB_DOWN, &adapter->state))
3515 mod_timer(&adapter->watchdog_timer,
3516 round_jiffies(jiffies + 2 * HZ));
3517}
3518
3519enum latency_range {
3520 lowest_latency = 0,
3521 low_latency = 1,
3522 bulk_latency = 2,
3523 latency_invalid = 255
3524};
3525
6eb5a7f1
AD		 3526/**
3527 * igb_update_ring_itr - update the dynamic ITR value based on packet size
3528 *
3529 * Stores a new ITR value based on strictly on packet size. This
3530 * algorithm is less sophisticated than that used in igb_update_itr,
3531 * due to the difficulty of synchronizing statistics across multiple
3532 * receive rings. The divisors and thresholds used by this fuction
3533 * were determined based on theoretical maximum wire speed and testing
3534 * data, in order to minimize response time while increasing bulk
3535 * throughput.
3536 * This functionality is controlled by the InterruptThrottleRate module
3537 * parameter (see igb_param.c)
3538 * NOTE: This function is called only when operating in a multiqueue
3539 * receive environment.
047e0030 3540 * @q_vector: pointer to q_vector
6eb5a7f1 3541 **/
047e0030 3542static void igb_update_ring_itr(struct igb_q_vector *q_vector)
9d5c8243 3543{
047e0030 3544 int new_val = q_vector->itr_val;
6eb5a7f1 3545 int avg_wire_size = 0;
047e0030 3546 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 3547
6eb5a7f1
AD		 3548 /* For non-gigabit speeds, just fix the interrupt rate at 4000
3549 * ints/sec - ITR timer value of 120 ticks.
3550 */
3551 if (adapter->link_speed != SPEED_1000) {
047e0030 3552 new_val = 976;
6eb5a7f1 3553 goto set_itr_val;
9d5c8243 3554 }
047e0030
AD		 3555
3556 if (q_vector->rx_ring && q_vector->rx_ring->total_packets) {
3557 struct igb_ring *ring = q_vector->rx_ring;
3558 avg_wire_size = ring->total_bytes / ring->total_packets;
3559 }
3560
3561 if (q_vector->tx_ring && q_vector->tx_ring->total_packets) {
3562 struct igb_ring *ring = q_vector->tx_ring;
3563 avg_wire_size = max_t(u32, avg_wire_size,
3564 (ring->total_bytes /
3565 ring->total_packets));
3566 }
3567
3568 /* if avg_wire_size isn't set no work was done */
3569 if (!avg_wire_size)
3570 goto clear_counts;
9d5c8243 3571
6eb5a7f1
AD		 3572 /* Add 24 bytes to size to account for CRC, preamble, and gap */
3573 avg_wire_size += 24;
3574
3575 /* Don't starve jumbo frames */
3576 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 3577
6eb5a7f1
AD		 3578 /* Give a little boost to mid-size frames */
3579 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
3580 new_val = avg_wire_size / 3;
3581 else
3582 new_val = avg_wire_size / 2;
9d5c8243 3583
abe1c363
NN		 3584 /* when in itr mode 3 do not exceed 20K ints/sec */
3585 if (adapter->rx_itr_setting == 3 && new_val < 196)
3586 new_val = 196;
3587
6eb5a7f1 3588set_itr_val:
047e0030
AD		 3589 if (new_val != q_vector->itr_val) {
3590 q_vector->itr_val = new_val;
3591 q_vector->set_itr = 1;
9d5c8243 3592 }
6eb5a7f1 3593clear_counts:
047e0030
AD		 3594 if (q_vector->rx_ring) {
3595 q_vector->rx_ring->total_bytes = 0;
3596 q_vector->rx_ring->total_packets = 0;
3597 }
3598 if (q_vector->tx_ring) {
3599 q_vector->tx_ring->total_bytes = 0;
3600 q_vector->tx_ring->total_packets = 0;
3601 }
9d5c8243
AK		 3602}
3603
3604/**
3605 * igb_update_itr - update the dynamic ITR value based on statistics
3606 * Stores a new ITR value based on packets and byte
3607 * counts during the last interrupt. The advantage of per interrupt
3608 * computation is faster updates and more accurate ITR for the current
3609 * traffic pattern. Constants in this function were computed
3610 * based on theoretical maximum wire speed and thresholds were set based
3611 * on testing data as well as attempting to minimize response time
3612 * while increasing bulk throughput.
3613 * this functionality is controlled by the InterruptThrottleRate module
3614 * parameter (see igb_param.c)
3615 * NOTE: These calculations are only valid when operating in a single-
3616 * queue environment.
3617 * @adapter: pointer to adapter
047e0030 3618 * @itr_setting: current q_vector->itr_val
9d5c8243
AK		 3619 * @packets: the number of packets during this measurement interval
3620 * @bytes: the number of bytes during this measurement interval
3621 **/
3622static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
3623 int packets, int bytes)
3624{
3625 unsigned int retval = itr_setting;
3626
3627 if (packets == 0)
3628 goto update_itr_done;
3629
3630 switch (itr_setting) {
3631 case lowest_latency:
3632 /* handle TSO and jumbo frames */
3633 if (bytes/packets > 8000)
3634 retval = bulk_latency;
3635 else if ((packets < 5) && (bytes > 512))
3636 retval = low_latency;
3637 break;
3638 case low_latency: /* 50 usec aka 20000 ints/s */
3639 if (bytes > 10000) {
3640 /* this if handles the TSO accounting */
3641 if (bytes/packets > 8000) {
3642 retval = bulk_latency;
3643 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
3644 retval = bulk_latency;
3645 } else if ((packets > 35)) {
3646 retval = lowest_latency;
3647 }
3648 } else if (bytes/packets > 2000) {
3649 retval = bulk_latency;
3650 } else if (packets <= 2 && bytes < 512) {
3651 retval = lowest_latency;
3652 }
3653 break;
3654 case bulk_latency: /* 250 usec aka 4000 ints/s */
3655 if (bytes > 25000) {
3656 if (packets > 35)
3657 retval = low_latency;
1e5c3d21 3658 } else if (bytes < 1500) {
9d5c8243
AK		 3659 retval = low_latency;
3660 }
3661 break;
3662 }
3663
3664update_itr_done:
3665 return retval;
3666}
3667
6eb5a7f1 3668static void igb_set_itr(struct igb_adapter *adapter)
9d5c8243 3669{
047e0030 3670 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243 3671 u16 current_itr;
047e0030 3672 u32 new_itr = q_vector->itr_val;
9d5c8243
AK		 3673
3674 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
3675 if (adapter->link_speed != SPEED_1000) {
3676 current_itr = 0;
3677 new_itr = 4000;
3678 goto set_itr_now;
3679 }
3680
3681 adapter->rx_itr = igb_update_itr(adapter,
3682 adapter->rx_itr,
3025a446
AD		 3683 q_vector->rx_ring->total_packets,
3684 q_vector->rx_ring->total_bytes);
9d5c8243 3685
047e0030
AD		 3686 adapter->tx_itr = igb_update_itr(adapter,
3687 adapter->tx_itr,
3025a446
AD		 3688 q_vector->tx_ring->total_packets,
3689 q_vector->tx_ring->total_bytes);
047e0030 3690 current_itr = max(adapter->rx_itr, adapter->tx_itr);
9d5c8243 3691
6eb5a7f1 3692 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4fc82adf 3693 if (adapter->rx_itr_setting == 3 && current_itr == lowest_latency)
6eb5a7f1
AD		 3694 current_itr = low_latency;
3695
9d5c8243
AK		 3696 switch (current_itr) {
3697 /* counts and packets in update_itr are dependent on these numbers */
3698 case lowest_latency:
78b1f607 3699 new_itr = 56; /* aka 70,000 ints/sec */
9d5c8243
AK		 3700 break;
3701 case low_latency:
78b1f607 3702 new_itr = 196; /* aka 20,000 ints/sec */
9d5c8243
AK		 3703 break;
3704 case bulk_latency:
78b1f607 3705 new_itr = 980; /* aka 4,000 ints/sec */
9d5c8243
AK		 3706 break;
3707 default:
3708 break;
3709 }
3710
3711set_itr_now:
3025a446
AD		 3712 q_vector->rx_ring->total_bytes = 0;
3713 q_vector->rx_ring->total_packets = 0;
3714 q_vector->tx_ring->total_bytes = 0;
3715 q_vector->tx_ring->total_packets = 0;
6eb5a7f1 3716
047e0030 3717 if (new_itr != q_vector->itr_val) {
9d5c8243
AK		 3718 /* this attempts to bias the interrupt rate towards Bulk
3719 * by adding intermediate steps when interrupt rate is
3720 * increasing */
047e0030
AD		 3721 new_itr = new_itr > q_vector->itr_val ?
3722 max((new_itr * q_vector->itr_val) /
3723 (new_itr + (q_vector->itr_val >> 2)),
3724 new_itr) :
9d5c8243
AK		 3725 new_itr;
3726 /* Don't write the value here; it resets the adapter's
3727 * internal timer, and causes us to delay far longer than
3728 * we should between interrupts. Instead, we write the ITR
3729 * value at the beginning of the next interrupt so the timing
3730 * ends up being correct.
3731 */
047e0030
AD		 3732 q_vector->itr_val = new_itr;
3733 q_vector->set_itr = 1;
9d5c8243 3734 }
9d5c8243
AK		 3735}
3736
9d5c8243
AK		 3737#define IGB_TX_FLAGS_CSUM 0x00000001
3738#define IGB_TX_FLAGS_VLAN 0x00000002
3739#define IGB_TX_FLAGS_TSO 0x00000004
3740#define IGB_TX_FLAGS_IPV4 0x00000008
cdfd01fc
AD		 3741#define IGB_TX_FLAGS_TSTAMP 0x00000010
3742#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
3743#define IGB_TX_FLAGS_VLAN_SHIFT 16
9d5c8243 3744
85ad76b2 3745static inline int igb_tso_adv(struct igb_ring *tx_ring,
9d5c8243
AK		 3746 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
3747{
3748 struct e1000_adv_tx_context_desc *context_desc;
3749 unsigned int i;
3750 int err;
3751 struct igb_buffer *buffer_info;
3752 u32 info = 0, tu_cmd = 0;
91d4ee33
NN		 3753 u32 mss_l4len_idx;
3754 u8 l4len;
9d5c8243
AK		 3755
3756 if (skb_header_cloned(skb)) {
3757 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
3758 if (err)
3759 return err;
3760 }
3761
3762 l4len = tcp_hdrlen(skb);
3763 *hdr_len += l4len;
3764
3765 if (skb->protocol == htons(ETH_P_IP)) {
3766 struct iphdr *iph = ip_hdr(skb);
3767 iph->tot_len = 0;
3768 iph->check = 0;
3769 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
3770 iph->daddr, 0,
3771 IPPROTO_TCP,
3772 0);
8e1e8a47 3773 } else if (skb_is_gso_v6(skb)) {
9d5c8243
AK		 3774 ipv6_hdr(skb)->payload_len = 0;
3775 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
3776 &ipv6_hdr(skb)->daddr,
3777 0, IPPROTO_TCP, 0);
3778 }
3779
3780 i = tx_ring->next_to_use;
3781
3782 buffer_info = &tx_ring->buffer_info[i];
3783 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3784 /* VLAN MACLEN IPLEN */
3785 if (tx_flags & IGB_TX_FLAGS_VLAN)
3786 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
3787 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3788 *hdr_len += skb_network_offset(skb);
3789 info |= skb_network_header_len(skb);
3790 *hdr_len += skb_network_header_len(skb);
3791 context_desc->vlan_macip_lens = cpu_to_le32(info);
3792
3793 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
3794 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3795
3796 if (skb->protocol == htons(ETH_P_IP))
3797 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
3798 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3799
3800 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3801
3802 /* MSS L4LEN IDX */
3803 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
3804 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
3805
73cd78f1 3806 /* For 82575, context index must be unique per ring. */
85ad76b2
AD		 3807 if (tx_ring->flags & IGB_RING_FLAG_TX_CTX_IDX)
3808 mss_l4len_idx |= tx_ring->reg_idx << 4;
9d5c8243
AK		 3809
3810 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
3811 context_desc->seqnum_seed = 0;
3812
3813 buffer_info->time_stamp = jiffies;
0e014cb1 3814 buffer_info->next_to_watch = i;
9d5c8243
AK		 3815 buffer_info->dma = 0;
3816 i++;
3817 if (i == tx_ring->count)
3818 i = 0;
3819
3820 tx_ring->next_to_use = i;
3821
3822 return true;
3823}
3824
85ad76b2
AD		 3825static inline bool igb_tx_csum_adv(struct igb_ring *tx_ring,
3826 struct sk_buff *skb, u32 tx_flags)
9d5c8243
AK		 3827{
3828 struct e1000_adv_tx_context_desc *context_desc;
59d71989 3829 struct device *dev = tx_ring->dev;
9d5c8243
AK		 3830 struct igb_buffer *buffer_info;
3831 u32 info = 0, tu_cmd = 0;
80785298 3832 unsigned int i;
9d5c8243
AK		 3833
3834 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
3835 (tx_flags & IGB_TX_FLAGS_VLAN)) {
3836 i = tx_ring->next_to_use;
3837 buffer_info = &tx_ring->buffer_info[i];
3838 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3839
3840 if (tx_flags & IGB_TX_FLAGS_VLAN)
3841 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
cdfd01fc 3842
9d5c8243
AK		 3843 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3844 if (skb->ip_summed == CHECKSUM_PARTIAL)
3845 info |= skb_network_header_len(skb);
3846
3847 context_desc->vlan_macip_lens = cpu_to_le32(info);
3848
3849 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3850
3851 if (skb->ip_summed == CHECKSUM_PARTIAL) {
fa4a7ef3
AJ		 3852 __be16 protocol;
3853
3854 if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
3855 const struct vlan_ethhdr *vhdr =
3856 (const struct vlan_ethhdr*)skb->data;
3857
3858 protocol = vhdr->h_vlan_encapsulated_proto;
3859 } else {
3860 protocol = skb->protocol;
3861 }
3862
3863 switch (protocol) {
09640e63 3864 case cpu_to_be16(ETH_P_IP):
9d5c8243 3865 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
44b0cda3
MW		 3866 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
3867 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
b9473560
JB		 3868 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
3869 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
44b0cda3 3870 break;
09640e63 3871 case cpu_to_be16(ETH_P_IPV6):
44b0cda3
MW		 3872 /* XXX what about other V6 headers?? */
3873 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
3874 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
b9473560
JB		 3875 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
3876 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
44b0cda3
MW		 3877 break;
3878 default:
3879 if (unlikely(net_ratelimit()))
59d71989 3880 dev_warn(dev,
44b0cda3
MW		 3881 "partial checksum but proto=%x!\n",
3882 skb->protocol);
3883 break;
3884 }
9d5c8243
AK		 3885 }
3886
3887 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3888 context_desc->seqnum_seed = 0;
85ad76b2 3889 if (tx_ring->flags & IGB_RING_FLAG_TX_CTX_IDX)
7dfc16fa 3890 context_desc->mss_l4len_idx =
85ad76b2 3891 cpu_to_le32(tx_ring->reg_idx << 4);
9d5c8243
AK		 3892
3893 buffer_info->time_stamp = jiffies;
0e014cb1 3894 buffer_info->next_to_watch = i;
9d5c8243
AK		 3895 buffer_info->dma = 0;
3896
3897 i++;
3898 if (i == tx_ring->count)
3899 i = 0;
3900 tx_ring->next_to_use = i;
3901
3902 return true;
3903 }
9d5c8243
AK		 3904 return false;
3905}
3906
3907#define IGB_MAX_TXD_PWR 16
3908#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
3909
80785298 3910static inline int igb_tx_map_adv(struct igb_ring *tx_ring, struct sk_buff *skb,
0e014cb1 3911 unsigned int first)
9d5c8243
AK		 3912{
3913 struct igb_buffer *buffer_info;
59d71989 3914 struct device *dev = tx_ring->dev;
2873957d 3915 unsigned int hlen = skb_headlen(skb);
9d5c8243
AK		 3916 unsigned int count = 0, i;
3917 unsigned int f;
2873957d 3918 u16 gso_segs = skb_shinfo(skb)->gso_segs ?: 1;
9d5c8243
AK		 3919
3920 i = tx_ring->next_to_use;
3921
3922 buffer_info = &tx_ring->buffer_info[i];
2873957d
NN		 3923 BUG_ON(hlen >= IGB_MAX_DATA_PER_TXD);
3924 buffer_info->length = hlen;
9d5c8243
AK		 3925 /* set time_stamp *before* dma to help avoid a possible race */
3926 buffer_info->time_stamp = jiffies;
0e014cb1 3927 buffer_info->next_to_watch = i;
2873957d 3928 buffer_info->dma = dma_map_single(dev, skb->data, hlen,
59d71989
AD		 3929 DMA_TO_DEVICE);
3930 if (dma_mapping_error(dev, buffer_info->dma))
6366ad33 3931 goto dma_error;
9d5c8243
AK		 3932
3933 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
2873957d
NN		 3934 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[f];
3935 unsigned int len = frag->size;
9d5c8243 3936
8581145f 3937 count++;
65689fef
AD		 3938 i++;
3939 if (i == tx_ring->count)
3940 i = 0;
3941
9d5c8243
AK		 3942 buffer_info = &tx_ring->buffer_info[i];
3943 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3944 buffer_info->length = len;
3945 buffer_info->time_stamp = jiffies;
0e014cb1 3946 buffer_info->next_to_watch = i;
6366ad33 3947 buffer_info->mapped_as_page = true;
59d71989 3948 buffer_info->dma = dma_map_page(dev,
6366ad33
AD		 3949 frag->page,
3950 frag->page_offset,
3951 len,
59d71989
AD		 3952 DMA_TO_DEVICE);
3953 if (dma_mapping_error(dev, buffer_info->dma))
6366ad33
AD		 3954 goto dma_error;
3955
9d5c8243
AK		 3956 }
3957
9d5c8243 3958 tx_ring->buffer_info[i].skb = skb;
2244d07b 3959 tx_ring->buffer_info[i].tx_flags = skb_shinfo(skb)->tx_flags;
2873957d
NN		 3960 /* multiply data chunks by size of headers */
3961 tx_ring->buffer_info[i].bytecount = ((gso_segs - 1) * hlen) + skb->len;
3962 tx_ring->buffer_info[i].gso_segs = gso_segs;
0e014cb1 3963 tx_ring->buffer_info[first].next_to_watch = i;
9d5c8243 3964
cdfd01fc 3965 return ++count;
6366ad33
AD		 3966
3967dma_error:
59d71989 3968 dev_err(dev, "TX DMA map failed\n");
6366ad33
AD		 3969
3970 /* clear timestamp and dma mappings for failed buffer_info mapping */
3971 buffer_info->dma = 0;
3972 buffer_info->time_stamp = 0;
3973 buffer_info->length = 0;
3974 buffer_info->next_to_watch = 0;
3975 buffer_info->mapped_as_page = false;
6366ad33
AD		 3976
3977 /* clear timestamp and dma mappings for remaining portion of packet */
a77ff709
NN		 3978 while (count--) {
3979 if (i == 0)
3980 i = tx_ring->count;
6366ad33 3981 i--;
6366ad33
AD		 3982 buffer_info = &tx_ring->buffer_info[i];
3983 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
3984 }
3985
3986 return 0;
9d5c8243
AK		 3987}
3988
85ad76b2 3989static inline void igb_tx_queue_adv(struct igb_ring *tx_ring,
91d4ee33 3990 u32 tx_flags, int count, u32 paylen,
9d5c8243
AK		 3991 u8 hdr_len)
3992{
cdfd01fc 3993 union e1000_adv_tx_desc *tx_desc;
9d5c8243
AK		 3994 struct igb_buffer *buffer_info;
3995 u32 olinfo_status = 0, cmd_type_len;
cdfd01fc 3996 unsigned int i = tx_ring->next_to_use;
9d5c8243
AK		 3997
3998 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
3999 E1000_ADVTXD_DCMD_DEXT);
4000
4001 if (tx_flags & IGB_TX_FLAGS_VLAN)
4002 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
4003
33af6bcc
PO		 4004 if (tx_flags & IGB_TX_FLAGS_TSTAMP)
4005 cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP;
4006
9d5c8243
AK		 4007 if (tx_flags & IGB_TX_FLAGS_TSO) {
4008 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
4009
4010 /* insert tcp checksum */
4011 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
4012
4013 /* insert ip checksum */
4014 if (tx_flags & IGB_TX_FLAGS_IPV4)
4015 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
4016
4017 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
4018 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
4019 }
4020
85ad76b2
AD		 4021 if ((tx_ring->flags & IGB_RING_FLAG_TX_CTX_IDX) &&
4022 (tx_flags & (IGB_TX_FLAGS_CSUM |
4023 IGB_TX_FLAGS_TSO |
7dfc16fa 4024 IGB_TX_FLAGS_VLAN)))
85ad76b2 4025 olinfo_status |= tx_ring->reg_idx << 4;
9d5c8243
AK		 4026
4027 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
4028
cdfd01fc 4029 do {
9d5c8243
AK		 4030 buffer_info = &tx_ring->buffer_info[i];
4031 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
4032 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
4033 tx_desc->read.cmd_type_len =
4034 cpu_to_le32(cmd_type_len | buffer_info->length);
4035 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
cdfd01fc 4036 count--;
9d5c8243
AK		 4037 i++;
4038 if (i == tx_ring->count)
4039 i = 0;
cdfd01fc 4040 } while (count > 0);
9d5c8243 4041
85ad76b2 4042 tx_desc->read.cmd_type_len |= cpu_to_le32(IGB_ADVTXD_DCMD);
9d5c8243
AK		 4043 /* Force memory writes to complete before letting h/w
4044 * know there are new descriptors to fetch. (Only
4045 * applicable for weak-ordered memory model archs,
4046 * such as IA-64). */
4047 wmb();
4048
4049 tx_ring->next_to_use = i;
fce99e34 4050 writel(i, tx_ring->tail);
9d5c8243
AK		 4051 /* we need this if more than one processor can write to our tail
4052 * at a time, it syncronizes IO on IA64/Altix systems */
4053 mmiowb();
4054}
4055
e694e964 4056static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, int size)
9d5c8243 4057{
e694e964
AD		 4058 struct net_device *netdev = tx_ring->netdev;
4059
661086df 4060 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 4061
9d5c8243
AK		 4062 /* Herbert's original patch had:
4063 * smp_mb__after_netif_stop_queue();
4064 * but since that doesn't exist yet, just open code it. */
4065 smp_mb();
4066
4067 /* We need to check again in a case another CPU has just
4068 * made room available. */
c493ea45 4069 if (igb_desc_unused(tx_ring) < size)
9d5c8243
AK		 4070 return -EBUSY;
4071
4072 /* A reprieve! */
661086df 4073 netif_wake_subqueue(netdev, tx_ring->queue_index);
04a5fcaa 4074 tx_ring->tx_stats.restart_queue++;
9d5c8243
AK		 4075 return 0;
4076}
4077
717ba089 4078static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, int size)
9d5c8243 4079{
c493ea45 4080 if (igb_desc_unused(tx_ring) >= size)
9d5c8243 4081 return 0;
e694e964 4082 return __igb_maybe_stop_tx(tx_ring, size);
9d5c8243
AK		 4083}
4084
b1a436c3
AD		 4085netdev_tx_t igb_xmit_frame_ring_adv(struct sk_buff *skb,
4086 struct igb_ring *tx_ring)
9d5c8243 4087{
e694e964 4088 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
cdfd01fc 4089 int tso = 0, count;
91d4ee33
NN		 4090 u32 tx_flags = 0;
4091 u16 first;
4092 u8 hdr_len = 0;
9d5c8243 4093
9d5c8243
AK		 4094 /* need: 1 descriptor per page,
4095 * + 2 desc gap to keep tail from touching head,
4096 * + 1 desc for skb->data,
4097 * + 1 desc for context descriptor,
4098 * otherwise try next time */
e694e964 4099 if (igb_maybe_stop_tx(tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
9d5c8243 4100 /* this is a hard error */
9d5c8243
AK		 4101 return NETDEV_TX_BUSY;
4102 }
33af6bcc 4103
2244d07b
OH		 4104 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
4105 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
33af6bcc 4106 tx_flags |= IGB_TX_FLAGS_TSTAMP;
33af6bcc 4107 }
9d5c8243 4108
cdfd01fc 4109 if (vlan_tx_tag_present(skb) && adapter->vlgrp) {
9d5c8243
AK		 4110 tx_flags |= IGB_TX_FLAGS_VLAN;
4111 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
4112 }
4113
661086df
PWJ		 4114 if (skb->protocol == htons(ETH_P_IP))
4115 tx_flags |= IGB_TX_FLAGS_IPV4;
4116
0e014cb1 4117 first = tx_ring->next_to_use;
85ad76b2
AD		 4118 if (skb_is_gso(skb)) {
4119 tso = igb_tso_adv(tx_ring, skb, tx_flags, &hdr_len);
cdfd01fc 4120
85ad76b2
AD		 4121 if (tso < 0) {
4122 dev_kfree_skb_any(skb);
4123 return NETDEV_TX_OK;
4124 }
9d5c8243
AK		 4125 }
4126
4127 if (tso)
4128 tx_flags |= IGB_TX_FLAGS_TSO;
85ad76b2 4129 else if (igb_tx_csum_adv(tx_ring, skb, tx_flags) &&
bc1cbd34
AD		 4130 (skb->ip_summed == CHECKSUM_PARTIAL))
4131 tx_flags |= IGB_TX_FLAGS_CSUM;
9d5c8243 4132
65689fef 4133 /*
cdfd01fc 4134 * count reflects descriptors mapped, if 0 or less then mapping error
65689fef
AD		 4135 * has occured and we need to rewind the descriptor queue
4136 */
80785298 4137 count = igb_tx_map_adv(tx_ring, skb, first);
6366ad33 4138 if (!count) {
65689fef
AD		 4139 dev_kfree_skb_any(skb);
4140 tx_ring->buffer_info[first].time_stamp = 0;
4141 tx_ring->next_to_use = first;
85ad76b2 4142 return NETDEV_TX_OK;
65689fef 4143 }
9d5c8243 4144
85ad76b2
AD		 4145 igb_tx_queue_adv(tx_ring, tx_flags, count, skb->len, hdr_len);
4146
4147 /* Make sure there is space in the ring for the next send. */
e694e964 4148 igb_maybe_stop_tx(tx_ring, MAX_SKB_FRAGS + 4);
85ad76b2 4149
9d5c8243
AK		 4150 return NETDEV_TX_OK;
4151}
4152
3b29a56d
SH		 4153static netdev_tx_t igb_xmit_frame_adv(struct sk_buff *skb,
4154 struct net_device *netdev)
9d5c8243
AK		 4155{
4156 struct igb_adapter *adapter = netdev_priv(netdev);
661086df 4157 struct igb_ring *tx_ring;
661086df 4158 int r_idx = 0;
b1a436c3
AD		 4159
4160 if (test_bit(__IGB_DOWN, &adapter->state)) {
4161 dev_kfree_skb_any(skb);
4162 return NETDEV_TX_OK;
4163 }
4164
4165 if (skb->len <= 0) {
4166 dev_kfree_skb_any(skb);
4167 return NETDEV_TX_OK;
4168 }
4169
1bfaf07b 4170 r_idx = skb->queue_mapping & (IGB_ABS_MAX_TX_QUEUES - 1);
661086df 4171 tx_ring = adapter->multi_tx_table[r_idx];
9d5c8243
AK		 4172
4173 /* This goes back to the question of how to logically map a tx queue
4174 * to a flow. Right now, performance is impacted slightly negatively
4175 * if using multiple tx queues. If the stack breaks away from a
4176 * single qdisc implementation, we can look at this again. */
e694e964 4177 return igb_xmit_frame_ring_adv(skb, tx_ring);
9d5c8243
AK		 4178}
4179
4180/**
4181 * igb_tx_timeout - Respond to a Tx Hang
4182 * @netdev: network interface device structure
4183 **/
4184static void igb_tx_timeout(struct net_device *netdev)
4185{
4186 struct igb_adapter *adapter = netdev_priv(netdev);
4187 struct e1000_hw *hw = &adapter->hw;
4188
4189 /* Do the reset outside of interrupt context */
4190 adapter->tx_timeout_count++;
f7ba205e 4191
55cac248
AD		 4192 if (hw->mac.type == e1000_82580)
4193 hw->dev_spec._82575.global_device_reset = true;
4194
9d5c8243 4195 schedule_work(&adapter->reset_task);
265de409
AD		 4196 wr32(E1000_EICS,
4197 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 4198}
4199
4200static void igb_reset_task(struct work_struct *work)
4201{
4202 struct igb_adapter *adapter;
4203 adapter = container_of(work, struct igb_adapter, reset_task);
4204
c97ec42a
TI		 4205 igb_dump(adapter);
4206 netdev_err(adapter->netdev, "Reset adapter\n");
9d5c8243
AK		 4207 igb_reinit_locked(adapter);
4208}
4209
4210/**
4211 * igb_get_stats - Get System Network Statistics
4212 * @netdev: network interface device structure
4213 *
4214 * Returns the address of the device statistics structure.
4215 * The statistics are actually updated from the timer callback.
4216 **/
73cd78f1 4217static struct net_device_stats *igb_get_stats(struct net_device *netdev)
9d5c8243 4218{
9d5c8243 4219 /* only return the current stats */
8d24e933 4220 return &netdev->stats;
9d5c8243
AK		 4221}
4222
4223/**
4224 * igb_change_mtu - Change the Maximum Transfer Unit
4225 * @netdev: network interface device structure
4226 * @new_mtu: new value for maximum frame size
4227 *
4228 * Returns 0 on success, negative on failure
4229 **/
4230static int igb_change_mtu(struct net_device *netdev, int new_mtu)
4231{
4232 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 4233 struct pci_dev *pdev = adapter->pdev;
9d5c8243 4234 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4c844851 4235 u32 rx_buffer_len, i;
9d5c8243 4236
c809d227 4237 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
090b1795 4238 dev_err(&pdev->dev, "Invalid MTU setting\n");
9d5c8243
AK		 4239 return -EINVAL;
4240 }
4241
9d5c8243 4242 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
090b1795 4243 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
9d5c8243
AK		 4244 return -EINVAL;
4245 }
4246
4247 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
4248 msleep(1);
73cd78f1 4249
9d5c8243
AK		 4250 /* igb_down has a dependency on max_frame_size */
4251 adapter->max_frame_size = max_frame;
559e9c49 4252
9d5c8243
AK		 4253 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
4254 * means we reserve 2 more, this pushes us to allocate from the next
4255 * larger slab size.
4256 * i.e. RXBUFFER_2048 --> size-4096 slab
4257 */
4258
757b77e2
NN		 4259 if (adapter->hw.mac.type == e1000_82580)
4260 max_frame += IGB_TS_HDR_LEN;
4261
7d95b717 4262 if (max_frame <= IGB_RXBUFFER_1024)
4c844851 4263 rx_buffer_len = IGB_RXBUFFER_1024;
6ec43fe6 4264 else if (max_frame <= MAXIMUM_ETHERNET_VLAN_SIZE)
4c844851 4265 rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
6ec43fe6 4266 else
4c844851
AD		 4267 rx_buffer_len = IGB_RXBUFFER_128;
4268
757b77e2
NN		 4269 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN + IGB_TS_HDR_LEN) ||
4270 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE + IGB_TS_HDR_LEN))
4271 rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE + IGB_TS_HDR_LEN;
4272
4273 if ((adapter->hw.mac.type == e1000_82580) &&
4274 (rx_buffer_len == IGB_RXBUFFER_128))
4275 rx_buffer_len += IGB_RXBUFFER_64;
4276
4c844851
AD		 4277 if (netif_running(netdev))
4278 igb_down(adapter);
9d5c8243 4279
090b1795 4280 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
9d5c8243
AK		 4281 netdev->mtu, new_mtu);
4282 netdev->mtu = new_mtu;
4283
4c844851 4284 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 4285 adapter->rx_ring[i]->rx_buffer_len = rx_buffer_len;
4c844851 4286
9d5c8243
AK		 4287 if (netif_running(netdev))
4288 igb_up(adapter);
4289 else
4290 igb_reset(adapter);
4291
4292 clear_bit(__IGB_RESETTING, &adapter->state);
4293
4294 return 0;
4295}
4296
4297/**
4298 * igb_update_stats - Update the board statistics counters
4299 * @adapter: board private structure
4300 **/
4301
4302void igb_update_stats(struct igb_adapter *adapter)
4303{
128e45eb 4304 struct net_device_stats *net_stats = igb_get_stats(adapter->netdev);
9d5c8243
AK		 4305 struct e1000_hw *hw = &adapter->hw;
4306 struct pci_dev *pdev = adapter->pdev;
fa3d9a6d 4307 u32 reg, mpc;
9d5c8243 4308 u16 phy_tmp;
3f9c0164
AD		 4309 int i;
4310 u64 bytes, packets;
9d5c8243
AK		 4311
4312#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
4313
4314 /*
4315 * Prevent stats update while adapter is being reset, or if the pci
4316 * connection is down.
4317 */
4318 if (adapter->link_speed == 0)
4319 return;
4320 if (pci_channel_offline(pdev))
4321 return;
4322
3f9c0164
AD		 4323 bytes = 0;
4324 packets = 0;
4325 for (i = 0; i < adapter->num_rx_queues; i++) {
4326 u32 rqdpc_tmp = rd32(E1000_RQDPC(i)) & 0x0FFF;
3025a446
AD		 4327 struct igb_ring *ring = adapter->rx_ring[i];
4328 ring->rx_stats.drops += rqdpc_tmp;
128e45eb 4329 net_stats->rx_fifo_errors += rqdpc_tmp;
3025a446
AD		 4330 bytes += ring->rx_stats.bytes;
4331 packets += ring->rx_stats.packets;
3f9c0164
AD		 4332 }
4333
128e45eb
AD		 4334 net_stats->rx_bytes = bytes;
4335 net_stats->rx_packets = packets;
3f9c0164
AD		 4336
4337 bytes = 0;
4338 packets = 0;
4339 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446
AD		 4340 struct igb_ring *ring = adapter->tx_ring[i];
4341 bytes += ring->tx_stats.bytes;
4342 packets += ring->tx_stats.packets;
3f9c0164 4343 }
128e45eb
AD		 4344 net_stats->tx_bytes = bytes;
4345 net_stats->tx_packets = packets;
3f9c0164
AD		 4346
4347 /* read stats registers */
9d5c8243
AK		 4348 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
4349 adapter->stats.gprc += rd32(E1000_GPRC);
4350 adapter->stats.gorc += rd32(E1000_GORCL);
4351 rd32(E1000_GORCH); /* clear GORCL */
4352 adapter->stats.bprc += rd32(E1000_BPRC);
4353 adapter->stats.mprc += rd32(E1000_MPRC);
4354 adapter->stats.roc += rd32(E1000_ROC);
4355
4356 adapter->stats.prc64 += rd32(E1000_PRC64);
4357 adapter->stats.prc127 += rd32(E1000_PRC127);
4358 adapter->stats.prc255 += rd32(E1000_PRC255);
4359 adapter->stats.prc511 += rd32(E1000_PRC511);
4360 adapter->stats.prc1023 += rd32(E1000_PRC1023);
4361 adapter->stats.prc1522 += rd32(E1000_PRC1522);
4362 adapter->stats.symerrs += rd32(E1000_SYMERRS);
4363 adapter->stats.sec += rd32(E1000_SEC);
4364
fa3d9a6d
MW		 4365 mpc = rd32(E1000_MPC);
4366 adapter->stats.mpc += mpc;
4367 net_stats->rx_fifo_errors += mpc;
9d5c8243
AK		 4368 adapter->stats.scc += rd32(E1000_SCC);
4369 adapter->stats.ecol += rd32(E1000_ECOL);
4370 adapter->stats.mcc += rd32(E1000_MCC);
4371 adapter->stats.latecol += rd32(E1000_LATECOL);
4372 adapter->stats.dc += rd32(E1000_DC);
4373 adapter->stats.rlec += rd32(E1000_RLEC);
4374 adapter->stats.xonrxc += rd32(E1000_XONRXC);
4375 adapter->stats.xontxc += rd32(E1000_XONTXC);
4376 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
4377 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
4378 adapter->stats.fcruc += rd32(E1000_FCRUC);
4379 adapter->stats.gptc += rd32(E1000_GPTC);
4380 adapter->stats.gotc += rd32(E1000_GOTCL);
4381 rd32(E1000_GOTCH); /* clear GOTCL */
fa3d9a6d 4382 adapter->stats.rnbc += rd32(E1000_RNBC);
9d5c8243
AK		 4383 adapter->stats.ruc += rd32(E1000_RUC);
4384 adapter->stats.rfc += rd32(E1000_RFC);
4385 adapter->stats.rjc += rd32(E1000_RJC);
4386 adapter->stats.tor += rd32(E1000_TORH);
4387 adapter->stats.tot += rd32(E1000_TOTH);
4388 adapter->stats.tpr += rd32(E1000_TPR);
4389
4390 adapter->stats.ptc64 += rd32(E1000_PTC64);
4391 adapter->stats.ptc127 += rd32(E1000_PTC127);
4392 adapter->stats.ptc255 += rd32(E1000_PTC255);
4393 adapter->stats.ptc511 += rd32(E1000_PTC511);
4394 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
4395 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
4396
4397 adapter->stats.mptc += rd32(E1000_MPTC);
4398 adapter->stats.bptc += rd32(E1000_BPTC);
4399
2d0b0f69
NN		 4400 adapter->stats.tpt += rd32(E1000_TPT);
4401 adapter->stats.colc += rd32(E1000_COLC);
9d5c8243
AK		 4402
4403 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
43915c7c
NN		 4404 /* read internal phy specific stats */
4405 reg = rd32(E1000_CTRL_EXT);
4406 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
4407 adapter->stats.rxerrc += rd32(E1000_RXERRC);
4408 adapter->stats.tncrs += rd32(E1000_TNCRS);
4409 }
4410
9d5c8243
AK		 4411 adapter->stats.tsctc += rd32(E1000_TSCTC);
4412 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
4413
4414 adapter->stats.iac += rd32(E1000_IAC);
4415 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
4416 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
4417 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
4418 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
4419 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
4420 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
4421 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
4422 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
4423
4424 /* Fill out the OS statistics structure */
128e45eb
AD		 4425 net_stats->multicast = adapter->stats.mprc;
4426 net_stats->collisions = adapter->stats.colc;
9d5c8243
AK		 4427
4428 /* Rx Errors */
4429
4430 /* RLEC on some newer hardware can be incorrect so build
8c0ab70a 4431 * our own version based on RUC and ROC */
128e45eb 4432 net_stats->rx_errors = adapter->stats.rxerrc +
9d5c8243
AK		 4433 adapter->stats.crcerrs + adapter->stats.algnerrc +
4434 adapter->stats.ruc + adapter->stats.roc +
4435 adapter->stats.cexterr;
128e45eb
AD		 4436 net_stats->rx_length_errors = adapter->stats.ruc +
4437 adapter->stats.roc;
4438 net_stats->rx_crc_errors = adapter->stats.crcerrs;
4439 net_stats->rx_frame_errors = adapter->stats.algnerrc;
4440 net_stats->rx_missed_errors = adapter->stats.mpc;
9d5c8243
AK		 4441
4442 /* Tx Errors */
128e45eb
AD		 4443 net_stats->tx_errors = adapter->stats.ecol +
4444 adapter->stats.latecol;
4445 net_stats->tx_aborted_errors = adapter->stats.ecol;
4446 net_stats->tx_window_errors = adapter->stats.latecol;
4447 net_stats->tx_carrier_errors = adapter->stats.tncrs;
9d5c8243
AK		 4448
4449 /* Tx Dropped needs to be maintained elsewhere */
4450
4451 /* Phy Stats */
4452 if (hw->phy.media_type == e1000_media_type_copper) {
4453 if ((adapter->link_speed == SPEED_1000) &&
73cd78f1 4454 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
9d5c8243
AK		 4455 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
4456 adapter->phy_stats.idle_errors += phy_tmp;
4457 }
4458 }
4459
4460 /* Management Stats */
4461 adapter->stats.mgptc += rd32(E1000_MGTPTC);
4462 adapter->stats.mgprc += rd32(E1000_MGTPRC);
4463 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
4464}
4465
9d5c8243
AK		 4466static irqreturn_t igb_msix_other(int irq, void *data)
4467{
047e0030 4468 struct igb_adapter *adapter = data;
9d5c8243 4469 struct e1000_hw *hw = &adapter->hw;
844290e5 4470 u32 icr = rd32(E1000_ICR);
844290e5 4471 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083 4472
7f081d40
AD		 4473 if (icr & E1000_ICR_DRSTA)
4474 schedule_work(&adapter->reset_task);
4475
047e0030 4476 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 4477 /* HW is reporting DMA is out of sync */
4478 adapter->stats.doosync++;
4479 }
eebbbdba 4480
4ae196df
AD		 4481 /* Check for a mailbox event */
4482 if (icr & E1000_ICR_VMMB)
4483 igb_msg_task(adapter);
4484
4485 if (icr & E1000_ICR_LSC) {
4486 hw->mac.get_link_status = 1;
4487 /* guard against interrupt when we're going down */
4488 if (!test_bit(__IGB_DOWN, &adapter->state))
4489 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4490 }
4491
25568a53
AD		 4492 if (adapter->vfs_allocated_count)
4493 wr32(E1000_IMS, E1000_IMS_LSC |
4494 E1000_IMS_VMMB |
4495 E1000_IMS_DOUTSYNC);
4496 else
4497 wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC);
844290e5 4498 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 4499
4500 return IRQ_HANDLED;
4501}
4502
047e0030 4503static void igb_write_itr(struct igb_q_vector *q_vector)
9d5c8243 4504{
26b39276 4505 struct igb_adapter *adapter = q_vector->adapter;
047e0030 4506 u32 itr_val = q_vector->itr_val & 0x7FFC;
9d5c8243 4507
047e0030
AD		 4508 if (!q_vector->set_itr)
4509 return;
73cd78f1 4510
047e0030
AD		 4511 if (!itr_val)
4512 itr_val = 0x4;
661086df 4513
26b39276
AD		 4514 if (adapter->hw.mac.type == e1000_82575)
4515 itr_val |= itr_val << 16;
661086df 4516 else
047e0030 4517 itr_val |= 0x8000000;
661086df 4518
047e0030
AD		 4519 writel(itr_val, q_vector->itr_register);
4520 q_vector->set_itr = 0;
6eb5a7f1
AD		 4521}
4522
047e0030 4523static irqreturn_t igb_msix_ring(int irq, void *data)
9d5c8243 4524{
047e0030 4525 struct igb_q_vector *q_vector = data;
9d5c8243 4526
047e0030
AD		 4527 /* Write the ITR value calculated from the previous interrupt. */
4528 igb_write_itr(q_vector);
9d5c8243 4529
047e0030 4530 napi_schedule(&q_vector->napi);
844290e5 4531
047e0030 4532 return IRQ_HANDLED;
fe4506b6
JC		 4533}
4534
421e02f0 4535#ifdef CONFIG_IGB_DCA
047e0030 4536static void igb_update_dca(struct igb_q_vector *q_vector)
fe4506b6 4537{
047e0030 4538 struct igb_adapter *adapter = q_vector->adapter;
fe4506b6
JC		 4539 struct e1000_hw *hw = &adapter->hw;
4540 int cpu = get_cpu();
fe4506b6 4541
047e0030
AD		 4542 if (q_vector->cpu == cpu)
4543 goto out_no_update;
4544
4545 if (q_vector->tx_ring) {
4546 int q = q_vector->tx_ring->reg_idx;
4547 u32 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
4548 if (hw->mac.type == e1000_82575) {
4549 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
4550 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
2d064c06 4551 } else {
047e0030
AD		 4552 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
4553 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
4554 E1000_DCA_TXCTRL_CPUID_SHIFT;
4555 }
4556 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
4557 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
4558 }
4559 if (q_vector->rx_ring) {
4560 int q = q_vector->rx_ring->reg_idx;
4561 u32 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
4562 if (hw->mac.type == e1000_82575) {
2d064c06 4563 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
92be7917 4564 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
047e0030
AD		 4565 } else {
4566 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
4567 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
4568 E1000_DCA_RXCTRL_CPUID_SHIFT;
2d064c06 4569 }
fe4506b6
JC		 4570 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
4571 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
4572 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
4573 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
fe4506b6 4574 }
047e0030
AD		 4575 q_vector->cpu = cpu;
4576out_no_update:
fe4506b6
JC		 4577 put_cpu();
4578}
4579
4580static void igb_setup_dca(struct igb_adapter *adapter)
4581{
7e0e99ef 4582 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 4583 int i;
4584
7dfc16fa 4585 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 4586 return;
4587
7e0e99ef
AD		 4588 /* Always use CB2 mode, difference is masked in the CB driver. */
4589 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
4590
047e0030 4591 for (i = 0; i < adapter->num_q_vectors; i++) {
26b39276
AD		 4592 adapter->q_vector[i]->cpu = -1;
4593 igb_update_dca(adapter->q_vector[i]);
fe4506b6
JC		 4594 }
4595}
4596
4597static int __igb_notify_dca(struct device *dev, void *data)
4598{
4599 struct net_device *netdev = dev_get_drvdata(dev);
4600 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 4601 struct pci_dev *pdev = adapter->pdev;
fe4506b6
JC		 4602 struct e1000_hw *hw = &adapter->hw;
4603 unsigned long event = *(unsigned long *)data;
4604
4605 switch (event) {
4606 case DCA_PROVIDER_ADD:
4607 /* if already enabled, don't do it again */
7dfc16fa 4608 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 4609 break;
fe4506b6 4610 if (dca_add_requester(dev) == 0) {
bbd98fe4 4611 adapter->flags |= IGB_FLAG_DCA_ENABLED;
090b1795 4612 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 4613 igb_setup_dca(adapter);
4614 break;
4615 }
4616 /* Fall Through since DCA is disabled. */
4617 case DCA_PROVIDER_REMOVE:
7dfc16fa 4618 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6 4619 /* without this a class_device is left
047e0030 4620 * hanging around in the sysfs model */
fe4506b6 4621 dca_remove_requester(dev);
090b1795 4622 dev_info(&pdev->dev, "DCA disabled\n");
7dfc16fa 4623 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 4624 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 4625 }
4626 break;
4627 }
bbd98fe4 4628
fe4506b6 4629 return 0;
9d5c8243
AK		 4630}
4631
fe4506b6
JC		 4632static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
4633 void *p)
4634{
4635 int ret_val;
4636
4637 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
4638 __igb_notify_dca);
4639
4640 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
4641}
421e02f0 4642#endif /* CONFIG_IGB_DCA */
9d5c8243 4643
4ae196df
AD		 4644static void igb_ping_all_vfs(struct igb_adapter *adapter)
4645{
4646 struct e1000_hw *hw = &adapter->hw;
4647 u32 ping;
4648 int i;
4649
4650 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
4651 ping = E1000_PF_CONTROL_MSG;
f2ca0dbe 4652 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
4ae196df
AD		 4653 ping |= E1000_VT_MSGTYPE_CTS;
4654 igb_write_mbx(hw, &ping, 1, i);
4655 }
4656}
4657
7d5753f0
AD		 4658static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
4659{
4660 struct e1000_hw *hw = &adapter->hw;
4661 u32 vmolr = rd32(E1000_VMOLR(vf));
4662 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4663
d85b9004 4664 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
7d5753f0
AD		 4665 IGB_VF_FLAG_MULTI_PROMISC);
4666 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
4667
4668 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
4669 vmolr |= E1000_VMOLR_MPME;
d85b9004 4670 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
7d5753f0
AD		 4671 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
4672 } else {
4673 /*
4674 * if we have hashes and we are clearing a multicast promisc
4675 * flag we need to write the hashes to the MTA as this step
4676 * was previously skipped
4677 */
4678 if (vf_data->num_vf_mc_hashes > 30) {
4679 vmolr |= E1000_VMOLR_MPME;
4680 } else if (vf_data->num_vf_mc_hashes) {
4681 int j;
4682 vmolr |= E1000_VMOLR_ROMPE;
4683 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
4684 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
4685 }
4686 }
4687
4688 wr32(E1000_VMOLR(vf), vmolr);
4689
4690 /* there are flags left unprocessed, likely not supported */
4691 if (*msgbuf & E1000_VT_MSGINFO_MASK)
4692 return -EINVAL;
4693
4694 return 0;
4695
4696}
4697
4ae196df
AD		 4698static int igb_set_vf_multicasts(struct igb_adapter *adapter,
4699 u32 *msgbuf, u32 vf)
4700{
4701 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
4702 u16 *hash_list = (u16 *)&msgbuf[1];
4703 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4704 int i;
4705
7d5753f0 4706 /* salt away the number of multicast addresses assigned
4ae196df
AD		 4707 * to this VF for later use to restore when the PF multi cast
4708 * list changes
4709 */
4710 vf_data->num_vf_mc_hashes = n;
4711
7d5753f0
AD		 4712 /* only up to 30 hash values supported */
4713 if (n > 30)
4714 n = 30;
4715
4716 /* store the hashes for later use */
4ae196df 4717 for (i = 0; i < n; i++)
a419aef8 4718 vf_data->vf_mc_hashes[i] = hash_list[i];
4ae196df
AD		 4719
4720 /* Flush and reset the mta with the new values */
ff41f8dc 4721 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 4722
4723 return 0;
4724}
4725
4726static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
4727{
4728 struct e1000_hw *hw = &adapter->hw;
4729 struct vf_data_storage *vf_data;
4730 int i, j;
4731
4732 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7d5753f0
AD		 4733 u32 vmolr = rd32(E1000_VMOLR(i));
4734 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
4735
4ae196df 4736 vf_data = &adapter->vf_data[i];
7d5753f0
AD		 4737
4738 if ((vf_data->num_vf_mc_hashes > 30) ||
4739 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
4740 vmolr |= E1000_VMOLR_MPME;
4741 } else if (vf_data->num_vf_mc_hashes) {
4742 vmolr |= E1000_VMOLR_ROMPE;
4743 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
4744 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
4745 }
4746 wr32(E1000_VMOLR(i), vmolr);
4ae196df
AD		 4747 }
4748}
4749
4750static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
4751{
4752 struct e1000_hw *hw = &adapter->hw;
4753 u32 pool_mask, reg, vid;
4754 int i;
4755
4756 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
4757
4758 /* Find the vlan filter for this id */
4759 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4760 reg = rd32(E1000_VLVF(i));
4761
4762 /* remove the vf from the pool */
4763 reg &= ~pool_mask;
4764
4765 /* if pool is empty then remove entry from vfta */
4766 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
4767 (reg & E1000_VLVF_VLANID_ENABLE)) {
4768 reg = 0;
4769 vid = reg & E1000_VLVF_VLANID_MASK;
4770 igb_vfta_set(hw, vid, false);
4771 }
4772
4773 wr32(E1000_VLVF(i), reg);
4774 }
ae641bdc
AD		 4775
4776 adapter->vf_data[vf].vlans_enabled = 0;
4ae196df
AD		 4777}
4778
4779static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
4780{
4781 struct e1000_hw *hw = &adapter->hw;
4782 u32 reg, i;
4783
51466239
AD		 4784 /* The vlvf table only exists on 82576 hardware and newer */
4785 if (hw->mac.type < e1000_82576)
4786 return -1;
4787
4788 /* we only need to do this if VMDq is enabled */
4ae196df
AD		 4789 if (!adapter->vfs_allocated_count)
4790 return -1;
4791
4792 /* Find the vlan filter for this id */
4793 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4794 reg = rd32(E1000_VLVF(i));
4795 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
4796 vid == (reg & E1000_VLVF_VLANID_MASK))
4797 break;
4798 }
4799
4800 if (add) {
4801 if (i == E1000_VLVF_ARRAY_SIZE) {
4802 /* Did not find a matching VLAN ID entry that was
4803 * enabled. Search for a free filter entry, i.e.
4804 * one without the enable bit set
4805 */
4806 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4807 reg = rd32(E1000_VLVF(i));
4808 if (!(reg & E1000_VLVF_VLANID_ENABLE))
4809 break;
4810 }
4811 }
4812 if (i < E1000_VLVF_ARRAY_SIZE) {
4813 /* Found an enabled/available entry */
4814 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
4815
4816 /* if !enabled we need to set this up in vfta */
4817 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
51466239
AD		 4818 /* add VID to filter table */
4819 igb_vfta_set(hw, vid, true);
4ae196df
AD		 4820 reg |= E1000_VLVF_VLANID_ENABLE;
4821 }
cad6d05f
AD		 4822 reg &= ~E1000_VLVF_VLANID_MASK;
4823 reg |= vid;
4ae196df 4824 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 4825
4826 /* do not modify RLPML for PF devices */
4827 if (vf >= adapter->vfs_allocated_count)
4828 return 0;
4829
4830 if (!adapter->vf_data[vf].vlans_enabled) {
4831 u32 size;
4832 reg = rd32(E1000_VMOLR(vf));
4833 size = reg & E1000_VMOLR_RLPML_MASK;
4834 size += 4;
4835 reg &= ~E1000_VMOLR_RLPML_MASK;
4836 reg |= size;
4837 wr32(E1000_VMOLR(vf), reg);
4838 }
ae641bdc 4839
51466239 4840 adapter->vf_data[vf].vlans_enabled++;
4ae196df
AD		 4841 return 0;
4842 }
4843 } else {
4844 if (i < E1000_VLVF_ARRAY_SIZE) {
4845 /* remove vf from the pool */
4846 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
4847 /* if pool is empty then remove entry from vfta */
4848 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
4849 reg = 0;
4850 igb_vfta_set(hw, vid, false);
4851 }
4852 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 4853
4854 /* do not modify RLPML for PF devices */
4855 if (vf >= adapter->vfs_allocated_count)
4856 return 0;
4857
4858 adapter->vf_data[vf].vlans_enabled--;
4859 if (!adapter->vf_data[vf].vlans_enabled) {
4860 u32 size;
4861 reg = rd32(E1000_VMOLR(vf));
4862 size = reg & E1000_VMOLR_RLPML_MASK;
4863 size -= 4;
4864 reg &= ~E1000_VMOLR_RLPML_MASK;
4865 reg |= size;
4866 wr32(E1000_VMOLR(vf), reg);
4867 }
4ae196df
AD		 4868 }
4869 }
8151d294
WM		 4870 return 0;
4871}
4872
4873static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
4874{
4875 struct e1000_hw *hw = &adapter->hw;
4876
4877 if (vid)
4878 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
4879 else
4880 wr32(E1000_VMVIR(vf), 0);
4881}
4882
4883static int igb_ndo_set_vf_vlan(struct net_device *netdev,
4884 int vf, u16 vlan, u8 qos)
4885{
4886 int err = 0;
4887 struct igb_adapter *adapter = netdev_priv(netdev);
4888
4889 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
4890 return -EINVAL;
4891 if (vlan || qos) {
4892 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
4893 if (err)
4894 goto out;
4895 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
4896 igb_set_vmolr(adapter, vf, !vlan);
4897 adapter->vf_data[vf].pf_vlan = vlan;
4898 adapter->vf_data[vf].pf_qos = qos;
4899 dev_info(&adapter->pdev->dev,
4900 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
4901 if (test_bit(__IGB_DOWN, &adapter->state)) {
4902 dev_warn(&adapter->pdev->dev,
4903 "The VF VLAN has been set,"
4904 " but the PF device is not up.\n");
4905 dev_warn(&adapter->pdev->dev,
4906 "Bring the PF device up before"
4907 " attempting to use the VF device.\n");
4908 }
4909 } else {
4910 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
4911 false, vf);
4912 igb_set_vmvir(adapter, vlan, vf);
4913 igb_set_vmolr(adapter, vf, true);
4914 adapter->vf_data[vf].pf_vlan = 0;
4915 adapter->vf_data[vf].pf_qos = 0;
4916 }
4917out:
4918 return err;
4ae196df
AD		 4919}
4920
4921static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
4922{
4923 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
4924 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
4925
4926 return igb_vlvf_set(adapter, vid, add, vf);
4927}
4928
f2ca0dbe 4929static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
4ae196df 4930{
8151d294
WM		 4931 /* clear flags */
4932 adapter->vf_data[vf].flags &= ~(IGB_VF_FLAG_PF_SET_MAC);
f2ca0dbe 4933 adapter->vf_data[vf].last_nack = jiffies;
4ae196df
AD		 4934
4935 /* reset offloads to defaults */
8151d294 4936 igb_set_vmolr(adapter, vf, true);
4ae196df
AD		 4937
4938 /* reset vlans for device */
4939 igb_clear_vf_vfta(adapter, vf);
8151d294
WM		 4940 if (adapter->vf_data[vf].pf_vlan)
4941 igb_ndo_set_vf_vlan(adapter->netdev, vf,
4942 adapter->vf_data[vf].pf_vlan,
4943 adapter->vf_data[vf].pf_qos);
4944 else
4945 igb_clear_vf_vfta(adapter, vf);
4ae196df
AD		 4946
4947 /* reset multicast table array for vf */
4948 adapter->vf_data[vf].num_vf_mc_hashes = 0;
4949
4950 /* Flush and reset the mta with the new values */
ff41f8dc 4951 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 4952}
4953
f2ca0dbe
AD		 4954static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
4955{
4956 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
4957
4958 /* generate a new mac address as we were hotplug removed/added */
8151d294
WM		 4959 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
4960 random_ether_addr(vf_mac);
f2ca0dbe
AD		 4961
4962 /* process remaining reset events */
4963 igb_vf_reset(adapter, vf);
4964}
4965
4966static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4ae196df
AD		 4967{
4968 struct e1000_hw *hw = &adapter->hw;
4969 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 4970 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 4971 u32 reg, msgbuf[3];
4972 u8 *addr = (u8 *)(&msgbuf[1]);
4973
4974 /* process all the same items cleared in a function level reset */
f2ca0dbe 4975 igb_vf_reset(adapter, vf);
4ae196df
AD		 4976
4977 /* set vf mac address */
26ad9178 4978 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4ae196df
AD		 4979
4980 /* enable transmit and receive for vf */
4981 reg = rd32(E1000_VFTE);
4982 wr32(E1000_VFTE, reg | (1 << vf));
4983 reg = rd32(E1000_VFRE);
4984 wr32(E1000_VFRE, reg | (1 << vf));
4985
f2ca0dbe 4986 adapter->vf_data[vf].flags = IGB_VF_FLAG_CTS;
4ae196df
AD		 4987
4988 /* reply to reset with ack and vf mac address */
4989 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
4990 memcpy(addr, vf_mac, 6);
4991 igb_write_mbx(hw, msgbuf, 3, vf);
4992}
4993
4994static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
4995{
de42edde
GR		 4996 /*
4997 * The VF MAC Address is stored in a packed array of bytes
4998 * starting at the second 32 bit word of the msg array
4999 */
f2ca0dbe
AD		 5000 unsigned char *addr = (char *)&msg[1];
5001 int err = -1;
4ae196df 5002
f2ca0dbe
AD		 5003 if (is_valid_ether_addr(addr))
5004 err = igb_set_vf_mac(adapter, vf, addr);
4ae196df 5005
f2ca0dbe 5006 return err;
4ae196df
AD		 5007}
5008
5009static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
5010{
5011 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 5012 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 5013 u32 msg = E1000_VT_MSGTYPE_NACK;
5014
5015 /* if device isn't clear to send it shouldn't be reading either */
f2ca0dbe
AD		 5016 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
5017 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
4ae196df 5018 igb_write_mbx(hw, &msg, 1, vf);
f2ca0dbe 5019 vf_data->last_nack = jiffies;
4ae196df
AD		 5020 }
5021}
5022
f2ca0dbe 5023static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4ae196df 5024{
f2ca0dbe
AD		 5025 struct pci_dev *pdev = adapter->pdev;
5026 u32 msgbuf[E1000_VFMAILBOX_SIZE];
4ae196df 5027 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 5028 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 5029 s32 retval;
5030
f2ca0dbe 5031 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
4ae196df 5032
fef45f4c
AD		 5033 if (retval) {
5034 /* if receive failed revoke VF CTS stats and restart init */
f2ca0dbe 5035 dev_err(&pdev->dev, "Error receiving message from VF\n");
fef45f4c
AD		 5036 vf_data->flags &= ~IGB_VF_FLAG_CTS;
5037 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5038 return;
5039 goto out;
5040 }
4ae196df
AD		 5041
5042 /* this is a message we already processed, do nothing */
5043 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
f2ca0dbe 5044 return;
4ae196df
AD		 5045
5046 /*
5047 * until the vf completes a reset it should not be
5048 * allowed to start any configuration.
5049 */
5050
5051 if (msgbuf[0] == E1000_VF_RESET) {
5052 igb_vf_reset_msg(adapter, vf);
f2ca0dbe 5053 return;
4ae196df
AD		 5054 }
5055
f2ca0dbe 5056 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
fef45f4c
AD		 5057 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5058 return;
5059 retval = -1;
5060 goto out;
4ae196df
AD		 5061 }
5062
5063 switch ((msgbuf[0] & 0xFFFF)) {
5064 case E1000_VF_SET_MAC_ADDR:
5065 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
5066 break;
7d5753f0
AD		 5067 case E1000_VF_SET_PROMISC:
5068 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
5069 break;
4ae196df
AD		 5070 case E1000_VF_SET_MULTICAST:
5071 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
5072 break;
5073 case E1000_VF_SET_LPE:
5074 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
5075 break;
5076 case E1000_VF_SET_VLAN:
8151d294
WM		 5077 if (adapter->vf_data[vf].pf_vlan)
5078 retval = -1;
5079 else
5080 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4ae196df
AD		 5081 break;
5082 default:
090b1795 5083 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4ae196df
AD		 5084 retval = -1;
5085 break;
5086 }
5087
fef45f4c
AD		 5088 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
5089out:
4ae196df
AD		 5090 /* notify the VF of the results of what it sent us */
5091 if (retval)
5092 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
5093 else
5094 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
5095
4ae196df 5096 igb_write_mbx(hw, msgbuf, 1, vf);
f2ca0dbe 5097}
4ae196df 5098
f2ca0dbe
AD		 5099static void igb_msg_task(struct igb_adapter *adapter)
5100{
5101 struct e1000_hw *hw = &adapter->hw;
5102 u32 vf;
5103
5104 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
5105 /* process any reset requests */
5106 if (!igb_check_for_rst(hw, vf))
5107 igb_vf_reset_event(adapter, vf);
5108
5109 /* process any messages pending */
5110 if (!igb_check_for_msg(hw, vf))
5111 igb_rcv_msg_from_vf(adapter, vf);
5112
5113 /* process any acks */
5114 if (!igb_check_for_ack(hw, vf))
5115 igb_rcv_ack_from_vf(adapter, vf);
5116 }
4ae196df
AD		 5117}
5118
68d480c4
AD		 5119/**
5120 * igb_set_uta - Set unicast filter table address
5121 * @adapter: board private structure
5122 *
5123 * The unicast table address is a register array of 32-bit registers.
5124 * The table is meant to be used in a way similar to how the MTA is used
5125 * however due to certain limitations in the hardware it is necessary to
5126 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscous
5127 * enable bit to allow vlan tag stripping when promiscous mode is enabled
5128 **/
5129static void igb_set_uta(struct igb_adapter *adapter)
5130{
5131 struct e1000_hw *hw = &adapter->hw;
5132 int i;
5133
5134 /* The UTA table only exists on 82576 hardware and newer */
5135 if (hw->mac.type < e1000_82576)
5136 return;
5137
5138 /* we only need to do this if VMDq is enabled */
5139 if (!adapter->vfs_allocated_count)
5140 return;
5141
5142 for (i = 0; i < hw->mac.uta_reg_count; i++)
5143 array_wr32(E1000_UTA, i, ~0);
5144}
5145
9d5c8243
AK		 5146/**
5147 * igb_intr_msi - Interrupt Handler
5148 * @irq: interrupt number
5149 * @data: pointer to a network interface device structure
5150 **/
5151static irqreturn_t igb_intr_msi(int irq, void *data)
5152{
047e0030
AD		 5153 struct igb_adapter *adapter = data;
5154 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 5155 struct e1000_hw *hw = &adapter->hw;
5156 /* read ICR disables interrupts using IAM */
5157 u32 icr = rd32(E1000_ICR);
5158
047e0030 5159 igb_write_itr(q_vector);
9d5c8243 5160
7f081d40
AD		 5161 if (icr & E1000_ICR_DRSTA)
5162 schedule_work(&adapter->reset_task);
5163
047e0030 5164 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5165 /* HW is reporting DMA is out of sync */
5166 adapter->stats.doosync++;
5167 }
5168
9d5c8243
AK		 5169 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5170 hw->mac.get_link_status = 1;
5171 if (!test_bit(__IGB_DOWN, &adapter->state))
5172 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5173 }
5174
047e0030 5175 napi_schedule(&q_vector->napi);
9d5c8243
AK		 5176
5177 return IRQ_HANDLED;
5178}
5179
5180/**
4a3c6433 5181 * igb_intr - Legacy Interrupt Handler
9d5c8243
AK		 5182 * @irq: interrupt number
5183 * @data: pointer to a network interface device structure
5184 **/
5185static irqreturn_t igb_intr(int irq, void *data)
5186{
047e0030
AD		 5187 struct igb_adapter *adapter = data;
5188 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 5189 struct e1000_hw *hw = &adapter->hw;
5190 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
5191 * need for the IMC write */
5192 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 5193 if (!icr)
5194 return IRQ_NONE; /* Not our interrupt */
5195
047e0030 5196 igb_write_itr(q_vector);
9d5c8243
AK		 5197
5198 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
5199 * not set, then the adapter didn't send an interrupt */
5200 if (!(icr & E1000_ICR_INT_ASSERTED))
5201 return IRQ_NONE;
5202
7f081d40
AD		 5203 if (icr & E1000_ICR_DRSTA)
5204 schedule_work(&adapter->reset_task);
5205
047e0030 5206 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5207 /* HW is reporting DMA is out of sync */
5208 adapter->stats.doosync++;
5209 }
5210
9d5c8243
AK		 5211 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5212 hw->mac.get_link_status = 1;
5213 /* guard against interrupt when we're going down */
5214 if (!test_bit(__IGB_DOWN, &adapter->state))
5215 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5216 }
5217
047e0030 5218 napi_schedule(&q_vector->napi);
9d5c8243
AK		 5219
5220 return IRQ_HANDLED;
5221}
5222
047e0030 5223static inline void igb_ring_irq_enable(struct igb_q_vector *q_vector)
9d5c8243 5224{
047e0030 5225 struct igb_adapter *adapter = q_vector->adapter;
46544258 5226 struct e1000_hw *hw = &adapter->hw;
9d5c8243 5227
4fc82adf
AD		 5228 if ((q_vector->rx_ring && (adapter->rx_itr_setting & 3)) ||
5229 (!q_vector->rx_ring && (adapter->tx_itr_setting & 3))) {
047e0030 5230 if (!adapter->msix_entries)
6eb5a7f1 5231 igb_set_itr(adapter);
46544258 5232 else
047e0030 5233 igb_update_ring_itr(q_vector);
9d5c8243
AK		 5234 }
5235
46544258
AD		 5236 if (!test_bit(__IGB_DOWN, &adapter->state)) {
5237 if (adapter->msix_entries)
047e0030 5238 wr32(E1000_EIMS, q_vector->eims_value);
46544258
AD		 5239 else
5240 igb_irq_enable(adapter);
5241 }
9d5c8243
AK		 5242}
5243
46544258
AD		 5244/**
5245 * igb_poll - NAPI Rx polling callback
5246 * @napi: napi polling structure
5247 * @budget: count of how many packets we should handle
5248 **/
5249static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 5250{
047e0030
AD		 5251 struct igb_q_vector *q_vector = container_of(napi,
5252 struct igb_q_vector,
5253 napi);
5254 int tx_clean_complete = 1, work_done = 0;
9d5c8243 5255
421e02f0 5256#ifdef CONFIG_IGB_DCA
047e0030
AD		 5257 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
5258 igb_update_dca(q_vector);
fe4506b6 5259#endif
047e0030
AD		 5260 if (q_vector->tx_ring)
5261 tx_clean_complete = igb_clean_tx_irq(q_vector);
9d5c8243 5262
047e0030
AD		 5263 if (q_vector->rx_ring)
5264 igb_clean_rx_irq_adv(q_vector, &work_done, budget);
5265
5266 if (!tx_clean_complete)
5267 work_done = budget;
46544258 5268
9d5c8243 5269 /* If not enough Rx work done, exit the polling mode */
5e6d5b17 5270 if (work_done < budget) {
288379f0 5271 napi_complete(napi);
047e0030 5272 igb_ring_irq_enable(q_vector);
9d5c8243
AK		 5273 }
5274
46544258 5275 return work_done;
9d5c8243 5276}
6d8126f9 5277
33af6bcc 5278/**
c5b9bd5e 5279 * igb_systim_to_hwtstamp - convert system time value to hw timestamp
33af6bcc 5280 * @adapter: board private structure
c5b9bd5e
AD		 5281 * @shhwtstamps: timestamp structure to update
5282 * @regval: unsigned 64bit system time value.
5283 *
5284 * We need to convert the system time value stored in the RX/TXSTMP registers
5285 * into a hwtstamp which can be used by the upper level timestamping functions
5286 */
5287static void igb_systim_to_hwtstamp(struct igb_adapter *adapter,
5288 struct skb_shared_hwtstamps *shhwtstamps,
5289 u64 regval)
5290{
5291 u64 ns;
5292
55cac248
AD		 5293 /*
5294 * The 82580 starts with 1ns at bit 0 in RX/TXSTMPL, shift this up to
5295 * 24 to match clock shift we setup earlier.
5296 */
5297 if (adapter->hw.mac.type == e1000_82580)
5298 regval <<= IGB_82580_TSYNC_SHIFT;
5299
c5b9bd5e
AD		 5300 ns = timecounter_cyc2time(&adapter->clock, regval);
5301 timecompare_update(&adapter->compare, ns);
5302 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps));
5303 shhwtstamps->hwtstamp = ns_to_ktime(ns);
5304 shhwtstamps->syststamp = timecompare_transform(&adapter->compare, ns);
5305}
5306
5307/**
5308 * igb_tx_hwtstamp - utility function which checks for TX time stamp
5309 * @q_vector: pointer to q_vector containing needed info
2873957d 5310 * @buffer: pointer to igb_buffer structure
33af6bcc
PO		 5311 *
5312 * If we were asked to do hardware stamping and such a time stamp is
5313 * available, then it must have been for this skb here because we only
5314 * allow only one such packet into the queue.
5315 */
2873957d 5316static void igb_tx_hwtstamp(struct igb_q_vector *q_vector, struct igb_buffer *buffer_info)
33af6bcc 5317{
c5b9bd5e 5318 struct igb_adapter *adapter = q_vector->adapter;
33af6bcc 5319 struct e1000_hw *hw = &adapter->hw;
c5b9bd5e
AD		 5320 struct skb_shared_hwtstamps shhwtstamps;
5321 u64 regval;
33af6bcc 5322
c5b9bd5e 5323 /* if skb does not support hw timestamp or TX stamp not valid exit */
2244d07b 5324 if (likely(!(buffer_info->tx_flags & SKBTX_HW_TSTAMP)) ||
c5b9bd5e
AD		 5325 !(rd32(E1000_TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID))
5326 return;
5327
5328 regval = rd32(E1000_TXSTMPL);
5329 regval |= (u64)rd32(E1000_TXSTMPH) << 32;
5330
5331 igb_systim_to_hwtstamp(adapter, &shhwtstamps, regval);
2873957d 5332 skb_tstamp_tx(buffer_info->skb, &shhwtstamps);
33af6bcc
PO		 5333}
5334
9d5c8243
AK		 5335/**
5336 * igb_clean_tx_irq - Reclaim resources after transmit completes
047e0030 5337 * @q_vector: pointer to q_vector containing needed info
9d5c8243
AK		 5338 * returns true if ring is completely cleaned
5339 **/
047e0030 5340static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
9d5c8243 5341{
047e0030
AD		 5342 struct igb_adapter *adapter = q_vector->adapter;
5343 struct igb_ring *tx_ring = q_vector->tx_ring;
e694e964 5344 struct net_device *netdev = tx_ring->netdev;
0e014cb1 5345 struct e1000_hw *hw = &adapter->hw;
9d5c8243 5346 struct igb_buffer *buffer_info;
0e014cb1 5347 union e1000_adv_tx_desc *tx_desc, *eop_desc;
9d5c8243 5348 unsigned int total_bytes = 0, total_packets = 0;
0e014cb1
AD		 5349 unsigned int i, eop, count = 0;
5350 bool cleaned = false;
9d5c8243 5351
9d5c8243 5352 i = tx_ring->next_to_clean;
0e014cb1
AD		 5353 eop = tx_ring->buffer_info[i].next_to_watch;
5354 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
5355
5356 while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) &&
5357 (count < tx_ring->count)) {
2d0bb1c1 5358 rmb(); /* read buffer_info after eop_desc status */
0e014cb1
AD		 5359 for (cleaned = false; !cleaned; count++) {
5360 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
9d5c8243 5361 buffer_info = &tx_ring->buffer_info[i];
0e014cb1 5362 cleaned = (i == eop);
9d5c8243 5363
2873957d
NN		 5364 if (buffer_info->skb) {
5365 total_bytes += buffer_info->bytecount;
9d5c8243 5366 /* gso_segs is currently only valid for tcp */
2873957d
NN		 5367 total_packets += buffer_info->gso_segs;
5368 igb_tx_hwtstamp(q_vector, buffer_info);
9d5c8243
AK		 5369 }
5370
80785298 5371 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
0e014cb1 5372 tx_desc->wb.status = 0;
9d5c8243
AK		 5373
5374 i++;
5375 if (i == tx_ring->count)
5376 i = 0;
9d5c8243 5377 }
0e014cb1
AD		 5378 eop = tx_ring->buffer_info[i].next_to_watch;
5379 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
5380 }
5381
9d5c8243
AK		 5382 tx_ring->next_to_clean = i;
5383
fc7d345d 5384 if (unlikely(count &&
9d5c8243 5385 netif_carrier_ok(netdev) &&
c493ea45 5386 igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
9d5c8243
AK		 5387 /* Make sure that anybody stopping the queue after this
5388 * sees the new next_to_clean.
5389 */
5390 smp_mb();
661086df
PWJ		 5391 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
5392 !(test_bit(__IGB_DOWN, &adapter->state))) {
5393 netif_wake_subqueue(netdev, tx_ring->queue_index);
04a5fcaa 5394 tx_ring->tx_stats.restart_queue++;
661086df 5395 }
9d5c8243
AK		 5396 }
5397
5398 if (tx_ring->detect_tx_hung) {
5399 /* Detect a transmit hang in hardware, this serializes the
5400 * check with the clearing of time_stamp and movement of i */
5401 tx_ring->detect_tx_hung = false;
5402 if (tx_ring->buffer_info[i].time_stamp &&
5403 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
8e95a202
JP		 5404 (adapter->tx_timeout_factor * HZ)) &&
5405 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
9d5c8243 5406
9d5c8243 5407 /* detected Tx unit hang */
59d71989 5408 dev_err(tx_ring->dev,
9d5c8243 5409 "Detected Tx Unit Hang\n"
2d064c06 5410 " Tx Queue <%d>\n"
9d5c8243
AK		 5411 " TDH <%x>\n"
5412 " TDT <%x>\n"
5413 " next_to_use <%x>\n"
5414 " next_to_clean <%x>\n"
9d5c8243
AK		 5415 "buffer_info[next_to_clean]\n"
5416 " time_stamp <%lx>\n"
0e014cb1 5417 " next_to_watch <%x>\n"
9d5c8243
AK		 5418 " jiffies <%lx>\n"
5419 " desc.status <%x>\n",
2d064c06 5420 tx_ring->queue_index,
fce99e34
AD		 5421 readl(tx_ring->head),
5422 readl(tx_ring->tail),
9d5c8243
AK		 5423 tx_ring->next_to_use,
5424 tx_ring->next_to_clean,
f7ba205e 5425 tx_ring->buffer_info[eop].time_stamp,
0e014cb1 5426 eop,
9d5c8243 5427 jiffies,
0e014cb1 5428 eop_desc->wb.status);
661086df 5429 netif_stop_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 5430 }
5431 }
5432 tx_ring->total_bytes += total_bytes;
5433 tx_ring->total_packets += total_packets;
e21ed353
AD		 5434 tx_ring->tx_stats.bytes += total_bytes;
5435 tx_ring->tx_stats.packets += total_packets;
0e014cb1 5436 return (count < tx_ring->count);
9d5c8243
AK		 5437}
5438
9d5c8243
AK		 5439/**
5440 * igb_receive_skb - helper function to handle rx indications
047e0030
AD		 5441 * @q_vector: structure containing interrupt and ring information
5442 * @skb: packet to send up
5443 * @vlan_tag: vlan tag for packet
9d5c8243 5444 **/
047e0030
AD		 5445static void igb_receive_skb(struct igb_q_vector *q_vector,
5446 struct sk_buff *skb,
5447 u16 vlan_tag)
5448{
5449 struct igb_adapter *adapter = q_vector->adapter;
5450
31b24b95 5451 if (vlan_tag && adapter->vlgrp)
047e0030
AD		 5452 vlan_gro_receive(&q_vector->napi, adapter->vlgrp,
5453 vlan_tag, skb);
182ff8df 5454 else
047e0030 5455 napi_gro_receive(&q_vector->napi, skb);
9d5c8243
AK		 5456}
5457
04a5fcaa 5458static inline void igb_rx_checksum_adv(struct igb_ring *ring,
9d5c8243
AK		 5459 u32 status_err, struct sk_buff *skb)
5460{
bc8acf2c 5461 skb_checksum_none_assert(skb);
9d5c8243
AK		 5462
5463 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
85ad76b2
AD		 5464 if (!(ring->flags & IGB_RING_FLAG_RX_CSUM) ||
5465 (status_err & E1000_RXD_STAT_IXSM))
9d5c8243 5466 return;
85ad76b2 5467
9d5c8243
AK		 5468 /* TCP/UDP checksum error bit is set */
5469 if (status_err &
5470 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
b9473560
JB		 5471 /*
5472 * work around errata with sctp packets where the TCPE aka
5473 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
5474 * packets, (aka let the stack check the crc32c)
5475 */
85ad76b2
AD		 5476 if ((skb->len == 60) &&
5477 (ring->flags & IGB_RING_FLAG_RX_SCTP_CSUM))
04a5fcaa 5478 ring->rx_stats.csum_err++;
85ad76b2 5479
9d5c8243 5480 /* let the stack verify checksum errors */
9d5c8243
AK		 5481 return;
5482 }
5483 /* It must be a TCP or UDP packet with a valid checksum */
5484 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
5485 skb->ip_summed = CHECKSUM_UNNECESSARY;
5486
59d71989 5487 dev_dbg(ring->dev, "cksum success: bits %08X\n", status_err);
9d5c8243
AK		 5488}
5489
757b77e2 5490static void igb_rx_hwtstamp(struct igb_q_vector *q_vector, u32 staterr,
c5b9bd5e
AD		 5491 struct sk_buff *skb)
5492{
5493 struct igb_adapter *adapter = q_vector->adapter;
5494 struct e1000_hw *hw = &adapter->hw;
5495 u64 regval;
5496
5497 /*
5498 * If this bit is set, then the RX registers contain the time stamp. No
5499 * other packet will be time stamped until we read these registers, so
5500 * read the registers to make them available again. Because only one
5501 * packet can be time stamped at a time, we know that the register
5502 * values must belong to this one here and therefore we don't need to
5503 * compare any of the additional attributes stored for it.
5504 *
2244d07b 5505 * If nothing went wrong, then it should have a shared tx_flags that we
c5b9bd5e
AD		 5506 * can turn into a skb_shared_hwtstamps.
5507 */
757b77e2
NN		 5508 if (staterr & E1000_RXDADV_STAT_TSIP) {
5509 u32 *stamp = (u32 *)skb->data;
5510 regval = le32_to_cpu(*(stamp + 2));
5511 regval |= (u64)le32_to_cpu(*(stamp + 3)) << 32;
5512 skb_pull(skb, IGB_TS_HDR_LEN);
5513 } else {
5514 if(!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
5515 return;
c5b9bd5e 5516
757b77e2
NN		 5517 regval = rd32(E1000_RXSTMPL);
5518 regval |= (u64)rd32(E1000_RXSTMPH) << 32;
5519 }
c5b9bd5e
AD		 5520
5521 igb_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval);
5522}
4c844851 5523static inline u16 igb_get_hlen(struct igb_ring *rx_ring,
2d94d8ab
AD		 5524 union e1000_adv_rx_desc *rx_desc)
5525{
5526 /* HW will not DMA in data larger than the given buffer, even if it
5527 * parses the (NFS, of course) header to be larger. In that case, it
5528 * fills the header buffer and spills the rest into the page.
5529 */
5530 u16 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
5531 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
4c844851
AD		 5532 if (hlen > rx_ring->rx_buffer_len)
5533 hlen = rx_ring->rx_buffer_len;
2d94d8ab
AD		 5534 return hlen;
5535}
5536
047e0030
AD		 5537static bool igb_clean_rx_irq_adv(struct igb_q_vector *q_vector,
5538 int *work_done, int budget)
9d5c8243 5539{
047e0030 5540 struct igb_ring *rx_ring = q_vector->rx_ring;
e694e964 5541 struct net_device *netdev = rx_ring->netdev;
59d71989 5542 struct device *dev = rx_ring->dev;
9d5c8243
AK		 5543 union e1000_adv_rx_desc *rx_desc , *next_rxd;
5544 struct igb_buffer *buffer_info , *next_buffer;
5545 struct sk_buff *skb;
9d5c8243
AK		 5546 bool cleaned = false;
5547 int cleaned_count = 0;
d1eff350 5548 int current_node = numa_node_id();
9d5c8243 5549 unsigned int total_bytes = 0, total_packets = 0;
73cd78f1 5550 unsigned int i;
2d94d8ab
AD		 5551 u32 staterr;
5552 u16 length;
047e0030 5553 u16 vlan_tag;
9d5c8243
AK		 5554
5555 i = rx_ring->next_to_clean;
69d3ca53 5556 buffer_info = &rx_ring->buffer_info[i];
9d5c8243
AK		 5557 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
5558 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
5559
5560 while (staterr & E1000_RXD_STAT_DD) {
5561 if (*work_done >= budget)
5562 break;
5563 (*work_done)++;
2d0bb1c1 5564 rmb(); /* read descriptor and rx_buffer_info after status DD */
9d5c8243 5565
69d3ca53
AD		 5566 skb = buffer_info->skb;
5567 prefetch(skb->data - NET_IP_ALIGN);
5568 buffer_info->skb = NULL;
5569
5570 i++;
5571 if (i == rx_ring->count)
5572 i = 0;
42d0781a 5573
69d3ca53
AD		 5574 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
5575 prefetch(next_rxd);
5576 next_buffer = &rx_ring->buffer_info[i];
9d5c8243
AK		 5577
5578 length = le16_to_cpu(rx_desc->wb.upper.length);
5579 cleaned = true;
5580 cleaned_count++;
5581
2d94d8ab 5582 if (buffer_info->dma) {
59d71989 5583 dma_unmap_single(dev, buffer_info->dma,
4c844851 5584 rx_ring->rx_buffer_len,
59d71989 5585 DMA_FROM_DEVICE);
91615f76 5586 buffer_info->dma = 0;
4c844851 5587 if (rx_ring->rx_buffer_len >= IGB_RXBUFFER_1024) {
6ec43fe6
AD		 5588 skb_put(skb, length);
5589 goto send_up;
5590 }
4c844851 5591 skb_put(skb, igb_get_hlen(rx_ring, rx_desc));
bf36c1a0
AD		 5592 }
5593
5594 if (length) {
59d71989
AD		 5595 dma_unmap_page(dev, buffer_info->page_dma,
5596 PAGE_SIZE / 2, DMA_FROM_DEVICE);
9d5c8243 5597 buffer_info->page_dma = 0;
bf36c1a0 5598
aa913403 5599 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
bf36c1a0
AD		 5600 buffer_info->page,
5601 buffer_info->page_offset,
5602 length);
5603
d1eff350
AD		 5604 if ((page_count(buffer_info->page) != 1) ||
5605 (page_to_nid(buffer_info->page) != current_node))
bf36c1a0
AD		 5606 buffer_info->page = NULL;
5607 else
5608 get_page(buffer_info->page);
9d5c8243
AK		 5609
5610 skb->len += length;
5611 skb->data_len += length;
bf36c1a0 5612 skb->truesize += length;
9d5c8243 5613 }
9d5c8243 5614
bf36c1a0 5615 if (!(staterr & E1000_RXD_STAT_EOP)) {
b2d56536
AD		 5616 buffer_info->skb = next_buffer->skb;
5617 buffer_info->dma = next_buffer->dma;
5618 next_buffer->skb = skb;
5619 next_buffer->dma = 0;
bf36c1a0
AD		 5620 goto next_desc;
5621 }
69d3ca53 5622send_up:
9d5c8243
AK		 5623 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
5624 dev_kfree_skb_irq(skb);
5625 goto next_desc;
5626 }
9d5c8243 5627
757b77e2
NN		 5628 if (staterr & (E1000_RXDADV_STAT_TSIP | E1000_RXDADV_STAT_TS))
5629 igb_rx_hwtstamp(q_vector, staterr, skb);
9d5c8243
AK		 5630 total_bytes += skb->len;
5631 total_packets++;
5632
85ad76b2 5633 igb_rx_checksum_adv(rx_ring, staterr, skb);
9d5c8243
AK		 5634
5635 skb->protocol = eth_type_trans(skb, netdev);
047e0030
AD		 5636 skb_record_rx_queue(skb, rx_ring->queue_index);
5637
5638 vlan_tag = ((staterr & E1000_RXD_STAT_VP) ?
5639 le16_to_cpu(rx_desc->wb.upper.vlan) : 0);
9d5c8243 5640
047e0030 5641 igb_receive_skb(q_vector, skb, vlan_tag);
9d5c8243 5642
9d5c8243
AK		 5643next_desc:
5644 rx_desc->wb.upper.status_error = 0;
5645
5646 /* return some buffers to hardware, one at a time is too slow */
5647 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
3b644cf6 5648 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 5649 cleaned_count = 0;
5650 }
5651
5652 /* use prefetched values */
5653 rx_desc = next_rxd;
5654 buffer_info = next_buffer;
9d5c8243
AK		 5655 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
5656 }
bf36c1a0 5657
9d5c8243 5658 rx_ring->next_to_clean = i;
c493ea45 5659 cleaned_count = igb_desc_unused(rx_ring);
9d5c8243
AK		 5660
5661 if (cleaned_count)
3b644cf6 5662 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 5663
5664 rx_ring->total_packets += total_packets;
5665 rx_ring->total_bytes += total_bytes;
5666 rx_ring->rx_stats.packets += total_packets;
5667 rx_ring->rx_stats.bytes += total_bytes;
9d5c8243
AK		 5668 return cleaned;
5669}
5670
9d5c8243
AK		 5671/**
5672 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
5673 * @adapter: address of board private structure
5674 **/
d7ee5b3a 5675void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring, int cleaned_count)
9d5c8243 5676{
e694e964 5677 struct net_device *netdev = rx_ring->netdev;
9d5c8243
AK		 5678 union e1000_adv_rx_desc *rx_desc;
5679 struct igb_buffer *buffer_info;
5680 struct sk_buff *skb;
5681 unsigned int i;
db761762 5682 int bufsz;
9d5c8243
AK		 5683
5684 i = rx_ring->next_to_use;
5685 buffer_info = &rx_ring->buffer_info[i];
5686
4c844851 5687 bufsz = rx_ring->rx_buffer_len;
db761762 5688
9d5c8243
AK		 5689 while (cleaned_count--) {
5690 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
5691
6ec43fe6 5692 if ((bufsz < IGB_RXBUFFER_1024) && !buffer_info->page_dma) {
9d5c8243 5693 if (!buffer_info->page) {
42d0781a 5694 buffer_info->page = netdev_alloc_page(netdev);
bf36c1a0 5695 if (!buffer_info->page) {
04a5fcaa 5696 rx_ring->rx_stats.alloc_failed++;
bf36c1a0
AD		 5697 goto no_buffers;
5698 }
5699 buffer_info->page_offset = 0;
5700 } else {
5701 buffer_info->page_offset ^= PAGE_SIZE / 2;
9d5c8243
AK		 5702 }
5703 buffer_info->page_dma =
59d71989 5704 dma_map_page(rx_ring->dev, buffer_info->page,
bf36c1a0
AD		 5705 buffer_info->page_offset,
5706 PAGE_SIZE / 2,
59d71989
AD		 5707 DMA_FROM_DEVICE);
5708 if (dma_mapping_error(rx_ring->dev,
5709 buffer_info->page_dma)) {
42d0781a
AD		 5710 buffer_info->page_dma = 0;
5711 rx_ring->rx_stats.alloc_failed++;
5712 goto no_buffers;
5713 }
9d5c8243
AK		 5714 }
5715
42d0781a
AD		 5716 skb = buffer_info->skb;
5717 if (!skb) {
89d71a66 5718 skb = netdev_alloc_skb_ip_align(netdev, bufsz);
9d5c8243 5719 if (!skb) {
04a5fcaa 5720 rx_ring->rx_stats.alloc_failed++;
9d5c8243
AK		 5721 goto no_buffers;
5722 }
5723
9d5c8243 5724 buffer_info->skb = skb;
42d0781a
AD		 5725 }
5726 if (!buffer_info->dma) {
59d71989 5727 buffer_info->dma = dma_map_single(rx_ring->dev,
80785298 5728 skb->data,
9d5c8243 5729 bufsz,
59d71989
AD		 5730 DMA_FROM_DEVICE);
5731 if (dma_mapping_error(rx_ring->dev,
5732 buffer_info->dma)) {
42d0781a
AD		 5733 buffer_info->dma = 0;
5734 rx_ring->rx_stats.alloc_failed++;
5735 goto no_buffers;
5736 }
9d5c8243
AK		 5737 }
5738 /* Refresh the desc even if buffer_addrs didn't change because
5739 * each write-back erases this info. */
6ec43fe6 5740 if (bufsz < IGB_RXBUFFER_1024) {
9d5c8243
AK		 5741 rx_desc->read.pkt_addr =
5742 cpu_to_le64(buffer_info->page_dma);
5743 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
5744 } else {
42d0781a 5745 rx_desc->read.pkt_addr = cpu_to_le64(buffer_info->dma);
9d5c8243
AK		 5746 rx_desc->read.hdr_addr = 0;
5747 }
5748
5749 i++;
5750 if (i == rx_ring->count)
5751 i = 0;
5752 buffer_info = &rx_ring->buffer_info[i];
5753 }
5754
5755no_buffers:
5756 if (rx_ring->next_to_use != i) {
5757 rx_ring->next_to_use = i;
5758 if (i == 0)
5759 i = (rx_ring->count - 1);
5760 else
5761 i--;
5762
5763 /* Force memory writes to complete before letting h/w
5764 * know there are new descriptors to fetch. (Only
5765 * applicable for weak-ordered memory model archs,
5766 * such as IA-64). */
5767 wmb();
fce99e34 5768 writel(i, rx_ring->tail);
9d5c8243
AK		 5769 }
5770}
5771
5772/**
5773 * igb_mii_ioctl -
5774 * @netdev:
5775 * @ifreq:
5776 * @cmd:
5777 **/
5778static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5779{
5780 struct igb_adapter *adapter = netdev_priv(netdev);
5781 struct mii_ioctl_data *data = if_mii(ifr);
5782
5783 if (adapter->hw.phy.media_type != e1000_media_type_copper)
5784 return -EOPNOTSUPP;
5785
5786 switch (cmd) {
5787 case SIOCGMIIPHY:
5788 data->phy_id = adapter->hw.phy.addr;
5789 break;
5790 case SIOCGMIIREG:
f5f4cf08
AD		 5791 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
5792 &data->val_out))
9d5c8243
AK		 5793 return -EIO;
5794 break;
5795 case SIOCSMIIREG:
5796 default:
5797 return -EOPNOTSUPP;
5798 }
5799 return 0;
5800}
5801
c6cb090b
PO		 5802/**
5803 * igb_hwtstamp_ioctl - control hardware time stamping
5804 * @netdev:
5805 * @ifreq:
5806 * @cmd:
5807 *
33af6bcc
PO		 5808 * Outgoing time stamping can be enabled and disabled. Play nice and
5809 * disable it when requested, although it shouldn't case any overhead
5810 * when no packet needs it. At most one packet in the queue may be
5811 * marked for time stamping, otherwise it would be impossible to tell
5812 * for sure to which packet the hardware time stamp belongs.
5813 *
5814 * Incoming time stamping has to be configured via the hardware
5815 * filters. Not all combinations are supported, in particular event
5816 * type has to be specified. Matching the kind of event packet is
5817 * not supported, with the exception of "all V2 events regardless of
5818 * level 2 or 4".
5819 *
c6cb090b
PO		 5820 **/
5821static int igb_hwtstamp_ioctl(struct net_device *netdev,
5822 struct ifreq *ifr, int cmd)
5823{
33af6bcc
PO		 5824 struct igb_adapter *adapter = netdev_priv(netdev);
5825 struct e1000_hw *hw = &adapter->hw;
c6cb090b 5826 struct hwtstamp_config config;
c5b9bd5e
AD		 5827 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
5828 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
33af6bcc 5829 u32 tsync_rx_cfg = 0;
c5b9bd5e
AD		 5830 bool is_l4 = false;
5831 bool is_l2 = false;
33af6bcc 5832 u32 regval;
c6cb090b
PO		 5833
5834 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
5835 return -EFAULT;
5836
5837 /* reserved for future extensions */
5838 if (config.flags)
5839 return -EINVAL;
5840
33af6bcc
PO		 5841 switch (config.tx_type) {
5842 case HWTSTAMP_TX_OFF:
c5b9bd5e 5843 tsync_tx_ctl = 0;
33af6bcc 5844 case HWTSTAMP_TX_ON:
33af6bcc
PO		 5845 break;
5846 default:
5847 return -ERANGE;
5848 }
5849
5850 switch (config.rx_filter) {
5851 case HWTSTAMP_FILTER_NONE:
c5b9bd5e 5852 tsync_rx_ctl = 0;
33af6bcc
PO		 5853 break;
5854 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
5855 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
5856 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
5857 case HWTSTAMP_FILTER_ALL:
5858 /*
5859 * register TSYNCRXCFG must be set, therefore it is not
5860 * possible to time stamp both Sync and Delay_Req messages
5861 * => fall back to time stamping all packets
5862 */
c5b9bd5e 5863 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
33af6bcc
PO		 5864 config.rx_filter = HWTSTAMP_FILTER_ALL;
5865 break;
5866 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
c5b9bd5e 5867 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
33af6bcc 5868 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
c5b9bd5e 5869 is_l4 = true;
33af6bcc
PO		 5870 break;
5871 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
c5b9bd5e 5872 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
33af6bcc 5873 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
c5b9bd5e 5874 is_l4 = true;
33af6bcc
PO		 5875 break;
5876 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
5877 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
c5b9bd5e 5878 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
33af6bcc 5879 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE;
c5b9bd5e
AD		 5880 is_l2 = true;
5881 is_l4 = true;
33af6bcc
PO		 5882 config.rx_filter = HWTSTAMP_FILTER_SOME;
5883 break;
5884 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
5885 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
c5b9bd5e 5886 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
33af6bcc 5887 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE;
c5b9bd5e
AD		 5888 is_l2 = true;
5889 is_l4 = true;
33af6bcc
PO		 5890 config.rx_filter = HWTSTAMP_FILTER_SOME;
5891 break;
5892 case HWTSTAMP_FILTER_PTP_V2_EVENT:
5893 case HWTSTAMP_FILTER_PTP_V2_SYNC:
5894 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
c5b9bd5e 5895 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
33af6bcc 5896 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
c5b9bd5e 5897 is_l2 = true;
33af6bcc
PO		 5898 break;
5899 default:
5900 return -ERANGE;
5901 }
5902
c5b9bd5e
AD		 5903 if (hw->mac.type == e1000_82575) {
5904 if (tsync_rx_ctl | tsync_tx_ctl)
5905 return -EINVAL;
5906 return 0;
5907 }
5908
757b77e2
NN		 5909 /*
5910 * Per-packet timestamping only works if all packets are
5911 * timestamped, so enable timestamping in all packets as
5912 * long as one rx filter was configured.
5913 */
5914 if ((hw->mac.type == e1000_82580) && tsync_rx_ctl) {
5915 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
5916 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
5917 }
5918
33af6bcc
PO		 5919 /* enable/disable TX */
5920 regval = rd32(E1000_TSYNCTXCTL);
c5b9bd5e
AD		 5921 regval &= ~E1000_TSYNCTXCTL_ENABLED;
5922 regval |= tsync_tx_ctl;
33af6bcc
PO		 5923 wr32(E1000_TSYNCTXCTL, regval);
5924
c5b9bd5e 5925 /* enable/disable RX */
33af6bcc 5926 regval = rd32(E1000_TSYNCRXCTL);
c5b9bd5e
AD		 5927 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
5928 regval |= tsync_rx_ctl;
33af6bcc 5929 wr32(E1000_TSYNCRXCTL, regval);
33af6bcc 5930
c5b9bd5e
AD		 5931 /* define which PTP packets are time stamped */
5932 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
33af6bcc 5933
c5b9bd5e
AD		 5934 /* define ethertype filter for timestamped packets */
5935 if (is_l2)
5936 wr32(E1000_ETQF(3),
5937 (E1000_ETQF_FILTER_ENABLE | /* enable filter */
5938 E1000_ETQF_1588 | /* enable timestamping */
5939 ETH_P_1588)); /* 1588 eth protocol type */
5940 else
5941 wr32(E1000_ETQF(3), 0);
5942
5943#define PTP_PORT 319
5944 /* L4 Queue Filter[3]: filter by destination port and protocol */
5945 if (is_l4) {
5946 u32 ftqf = (IPPROTO_UDP /* UDP */
5947 | E1000_FTQF_VF_BP /* VF not compared */
5948 | E1000_FTQF_1588_TIME_STAMP /* Enable Timestamping */
5949 | E1000_FTQF_MASK); /* mask all inputs */
5950 ftqf &= ~E1000_FTQF_MASK_PROTO_BP; /* enable protocol check */
5951
5952 wr32(E1000_IMIR(3), htons(PTP_PORT));
5953 wr32(E1000_IMIREXT(3),
5954 (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP));
5955 if (hw->mac.type == e1000_82576) {
5956 /* enable source port check */
5957 wr32(E1000_SPQF(3), htons(PTP_PORT));
5958 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
5959 }
5960 wr32(E1000_FTQF(3), ftqf);
5961 } else {
5962 wr32(E1000_FTQF(3), E1000_FTQF_MASK);
5963 }
33af6bcc
PO		 5964 wrfl();
5965
5966 adapter->hwtstamp_config = config;
5967
5968 /* clear TX/RX time stamp registers, just to be sure */
5969 regval = rd32(E1000_TXSTMPH);
5970 regval = rd32(E1000_RXSTMPH);
c6cb090b 5971
33af6bcc
PO		 5972 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
5973 -EFAULT : 0;
c6cb090b
PO		 5974}
5975
9d5c8243
AK		 5976/**
5977 * igb_ioctl -
5978 * @netdev:
5979 * @ifreq:
5980 * @cmd:
5981 **/
5982static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5983{
5984 switch (cmd) {
5985 case SIOCGMIIPHY:
5986 case SIOCGMIIREG:
5987 case SIOCSMIIREG:
5988 return igb_mii_ioctl(netdev, ifr, cmd);
c6cb090b
PO		 5989 case SIOCSHWTSTAMP:
5990 return igb_hwtstamp_ioctl(netdev, ifr, cmd);
9d5c8243
AK		 5991 default:
5992 return -EOPNOTSUPP;
5993 }
5994}
5995
009bc06e
AD		 5996s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
5997{
5998 struct igb_adapter *adapter = hw->back;
5999 u16 cap_offset;
6000
6001 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
6002 if (!cap_offset)
6003 return -E1000_ERR_CONFIG;
6004
6005 pci_read_config_word(adapter->pdev, cap_offset + reg, value);
6006
6007 return 0;
6008}
6009
6010s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6011{
6012 struct igb_adapter *adapter = hw->back;
6013 u16 cap_offset;
6014
6015 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
6016 if (!cap_offset)
6017 return -E1000_ERR_CONFIG;
6018
6019 pci_write_config_word(adapter->pdev, cap_offset + reg, *value);
6020
6021 return 0;
6022}
6023
9d5c8243
AK		 6024static void igb_vlan_rx_register(struct net_device *netdev,
6025 struct vlan_group *grp)
6026{
6027 struct igb_adapter *adapter = netdev_priv(netdev);
6028 struct e1000_hw *hw = &adapter->hw;
6029 u32 ctrl, rctl;
6030
6031 igb_irq_disable(adapter);
6032 adapter->vlgrp = grp;
6033
6034 if (grp) {
6035 /* enable VLAN tag insert/strip */
6036 ctrl = rd32(E1000_CTRL);
6037 ctrl |= E1000_CTRL_VME;
6038 wr32(E1000_CTRL, ctrl);
6039
51466239 6040 /* Disable CFI check */
9d5c8243 6041 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 6042 rctl &= ~E1000_RCTL_CFIEN;
6043 wr32(E1000_RCTL, rctl);
9d5c8243
AK		 6044 } else {
6045 /* disable VLAN tag insert/strip */
6046 ctrl = rd32(E1000_CTRL);
6047 ctrl &= ~E1000_CTRL_VME;
6048 wr32(E1000_CTRL, ctrl);
9d5c8243
AK		 6049 }
6050
e1739522
AD		 6051 igb_rlpml_set(adapter);
6052
9d5c8243
AK		 6053 if (!test_bit(__IGB_DOWN, &adapter->state))
6054 igb_irq_enable(adapter);
6055}
6056
6057static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
6058{
6059 struct igb_adapter *adapter = netdev_priv(netdev);
6060 struct e1000_hw *hw = &adapter->hw;
4ae196df 6061 int pf_id = adapter->vfs_allocated_count;
9d5c8243 6062
51466239
AD		 6063 /* attempt to add filter to vlvf array */
6064 igb_vlvf_set(adapter, vid, true, pf_id);
4ae196df 6065
51466239
AD		 6066 /* add the filter since PF can receive vlans w/o entry in vlvf */
6067 igb_vfta_set(hw, vid, true);
9d5c8243
AK		 6068}
6069
6070static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
6071{
6072 struct igb_adapter *adapter = netdev_priv(netdev);
6073 struct e1000_hw *hw = &adapter->hw;
4ae196df 6074 int pf_id = adapter->vfs_allocated_count;
51466239 6075 s32 err;
9d5c8243
AK		 6076
6077 igb_irq_disable(adapter);
6078 vlan_group_set_device(adapter->vlgrp, vid, NULL);
6079
6080 if (!test_bit(__IGB_DOWN, &adapter->state))
6081 igb_irq_enable(adapter);
6082
51466239
AD		 6083 /* remove vlan from VLVF table array */
6084 err = igb_vlvf_set(adapter, vid, false, pf_id);
9d5c8243 6085
51466239
AD		 6086 /* if vid was not present in VLVF just remove it from table */
6087 if (err)
4ae196df 6088 igb_vfta_set(hw, vid, false);
9d5c8243
AK		 6089}
6090
6091static void igb_restore_vlan(struct igb_adapter *adapter)
6092{
6093 igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
6094
6095 if (adapter->vlgrp) {
6096 u16 vid;
6097 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
6098 if (!vlan_group_get_device(adapter->vlgrp, vid))
6099 continue;
6100 igb_vlan_rx_add_vid(adapter->netdev, vid);
6101 }
6102 }
6103}
6104
6105int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
6106{
090b1795 6107 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 6108 struct e1000_mac_info *mac = &adapter->hw.mac;
6109
6110 mac->autoneg = 0;
6111
9d5c8243
AK		 6112 switch (spddplx) {
6113 case SPEED_10 + DUPLEX_HALF:
6114 mac->forced_speed_duplex = ADVERTISE_10_HALF;
6115 break;
6116 case SPEED_10 + DUPLEX_FULL:
6117 mac->forced_speed_duplex = ADVERTISE_10_FULL;
6118 break;
6119 case SPEED_100 + DUPLEX_HALF:
6120 mac->forced_speed_duplex = ADVERTISE_100_HALF;
6121 break;
6122 case SPEED_100 + DUPLEX_FULL:
6123 mac->forced_speed_duplex = ADVERTISE_100_FULL;
6124 break;
6125 case SPEED_1000 + DUPLEX_FULL:
6126 mac->autoneg = 1;
6127 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
6128 break;
6129 case SPEED_1000 + DUPLEX_HALF: /* not supported */
6130 default:
090b1795 6131 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
9d5c8243
AK		 6132 return -EINVAL;
6133 }
6134 return 0;
6135}
6136
3fe7c4c9 6137static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake)
9d5c8243
AK		 6138{
6139 struct net_device *netdev = pci_get_drvdata(pdev);
6140 struct igb_adapter *adapter = netdev_priv(netdev);
6141 struct e1000_hw *hw = &adapter->hw;
2d064c06 6142 u32 ctrl, rctl, status;
9d5c8243
AK		 6143 u32 wufc = adapter->wol;
6144#ifdef CONFIG_PM
6145 int retval = 0;
6146#endif
6147
6148 netif_device_detach(netdev);
6149
a88f10ec
AD		 6150 if (netif_running(netdev))
6151 igb_close(netdev);
6152
047e0030 6153 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 6154
6155#ifdef CONFIG_PM
6156 retval = pci_save_state(pdev);
6157 if (retval)
6158 return retval;
6159#endif
6160
6161 status = rd32(E1000_STATUS);
6162 if (status & E1000_STATUS_LU)
6163 wufc &= ~E1000_WUFC_LNKC;
6164
6165 if (wufc) {
6166 igb_setup_rctl(adapter);
ff41f8dc 6167 igb_set_rx_mode(netdev);
9d5c8243
AK		 6168
6169 /* turn on all-multi mode if wake on multicast is enabled */
6170 if (wufc & E1000_WUFC_MC) {
6171 rctl = rd32(E1000_RCTL);
6172 rctl |= E1000_RCTL_MPE;
6173 wr32(E1000_RCTL, rctl);
6174 }
6175
6176 ctrl = rd32(E1000_CTRL);
6177 /* advertise wake from D3Cold */
6178 #define E1000_CTRL_ADVD3WUC 0x00100000
6179 /* phy power management enable */
6180 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
6181 ctrl |= E1000_CTRL_ADVD3WUC;
6182 wr32(E1000_CTRL, ctrl);
6183
9d5c8243 6184 /* Allow time for pending master requests to run */
330a6d6a 6185 igb_disable_pcie_master(hw);
9d5c8243
AK		 6186
6187 wr32(E1000_WUC, E1000_WUC_PME_EN);
6188 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 6189 } else {
6190 wr32(E1000_WUC, 0);
6191 wr32(E1000_WUFC, 0);
9d5c8243
AK		 6192 }
6193
3fe7c4c9
RW		 6194 *enable_wake = wufc || adapter->en_mng_pt;
6195 if (!*enable_wake)
88a268c1
NN		 6196 igb_power_down_link(adapter);
6197 else
6198 igb_power_up_link(adapter);
9d5c8243
AK		 6199
6200 /* Release control of h/w to f/w. If f/w is AMT enabled, this
6201 * would have already happened in close and is redundant. */
6202 igb_release_hw_control(adapter);
6203
6204 pci_disable_device(pdev);
6205
9d5c8243
AK		 6206 return 0;
6207}
6208
6209#ifdef CONFIG_PM
3fe7c4c9
RW		 6210static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
6211{
6212 int retval;
6213 bool wake;
6214
6215 retval = __igb_shutdown(pdev, &wake);
6216 if (retval)
6217 return retval;
6218
6219 if (wake) {
6220 pci_prepare_to_sleep(pdev);
6221 } else {
6222 pci_wake_from_d3(pdev, false);
6223 pci_set_power_state(pdev, PCI_D3hot);
6224 }
6225
6226 return 0;
6227}
6228
9d5c8243
AK		 6229static int igb_resume(struct pci_dev *pdev)
6230{
6231 struct net_device *netdev = pci_get_drvdata(pdev);
6232 struct igb_adapter *adapter = netdev_priv(netdev);
6233 struct e1000_hw *hw = &adapter->hw;
6234 u32 err;
6235
6236 pci_set_power_state(pdev, PCI_D0);
6237 pci_restore_state(pdev);
b94f2d77 6238 pci_save_state(pdev);
42bfd33a 6239
aed5dec3 6240 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 6241 if (err) {
6242 dev_err(&pdev->dev,
6243 "igb: Cannot enable PCI device from suspend\n");
6244 return err;
6245 }
6246 pci_set_master(pdev);
6247
6248 pci_enable_wake(pdev, PCI_D3hot, 0);
6249 pci_enable_wake(pdev, PCI_D3cold, 0);
6250
047e0030 6251 if (igb_init_interrupt_scheme(adapter)) {
a88f10ec
AD		 6252 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
6253 return -ENOMEM;
9d5c8243
AK		 6254 }
6255
9d5c8243 6256 igb_reset(adapter);
a8564f03
AD		 6257
6258 /* let the f/w know that the h/w is now under the control of the
6259 * driver. */
6260 igb_get_hw_control(adapter);
6261
9d5c8243
AK		 6262 wr32(E1000_WUS, ~0);
6263
a88f10ec
AD		 6264 if (netif_running(netdev)) {
6265 err = igb_open(netdev);
6266 if (err)
6267 return err;
6268 }
9d5c8243
AK		 6269
6270 netif_device_attach(netdev);
6271
9d5c8243
AK		 6272 return 0;
6273}
6274#endif
6275
6276static void igb_shutdown(struct pci_dev *pdev)
6277{
3fe7c4c9
RW		 6278 bool wake;
6279
6280 __igb_shutdown(pdev, &wake);
6281
6282 if (system_state == SYSTEM_POWER_OFF) {
6283 pci_wake_from_d3(pdev, wake);
6284 pci_set_power_state(pdev, PCI_D3hot);
6285 }
9d5c8243
AK		 6286}
6287
6288#ifdef CONFIG_NET_POLL_CONTROLLER
6289/*
6290 * Polling 'interrupt' - used by things like netconsole to send skbs
6291 * without having to re-enable interrupts. It's not called while
6292 * the interrupt routine is executing.
6293 */
6294static void igb_netpoll(struct net_device *netdev)
6295{
6296 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 6297 struct e1000_hw *hw = &adapter->hw;
9d5c8243 6298 int i;
9d5c8243 6299
eebbbdba 6300 if (!adapter->msix_entries) {
047e0030 6301 struct igb_q_vector *q_vector = adapter->q_vector[0];
eebbbdba 6302 igb_irq_disable(adapter);
047e0030 6303 napi_schedule(&q_vector->napi);
eebbbdba
AD		 6304 return;
6305 }
9d5c8243 6306
047e0030
AD		 6307 for (i = 0; i < adapter->num_q_vectors; i++) {
6308 struct igb_q_vector *q_vector = adapter->q_vector[i];
6309 wr32(E1000_EIMC, q_vector->eims_value);
6310 napi_schedule(&q_vector->napi);
eebbbdba 6311 }
9d5c8243
AK		 6312}
6313#endif /* CONFIG_NET_POLL_CONTROLLER */
6314
6315/**
6316 * igb_io_error_detected - called when PCI error is detected
6317 * @pdev: Pointer to PCI device
6318 * @state: The current pci connection state
6319 *
6320 * This function is called after a PCI bus error affecting
6321 * this device has been detected.
6322 */
6323static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
6324 pci_channel_state_t state)
6325{
6326 struct net_device *netdev = pci_get_drvdata(pdev);
6327 struct igb_adapter *adapter = netdev_priv(netdev);
6328
6329 netif_device_detach(netdev);
6330
59ed6eec
AD		 6331 if (state == pci_channel_io_perm_failure)
6332 return PCI_ERS_RESULT_DISCONNECT;
6333
9d5c8243
AK		 6334 if (netif_running(netdev))
6335 igb_down(adapter);
6336 pci_disable_device(pdev);
6337
6338 /* Request a slot slot reset. */
6339 return PCI_ERS_RESULT_NEED_RESET;
6340}
6341
6342/**
6343 * igb_io_slot_reset - called after the pci bus has been reset.
6344 * @pdev: Pointer to PCI device
6345 *
6346 * Restart the card from scratch, as if from a cold-boot. Implementation
6347 * resembles the first-half of the igb_resume routine.
6348 */
6349static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
6350{
6351 struct net_device *netdev = pci_get_drvdata(pdev);
6352 struct igb_adapter *adapter = netdev_priv(netdev);
6353 struct e1000_hw *hw = &adapter->hw;
40a914fa 6354 pci_ers_result_t result;
42bfd33a 6355 int err;
9d5c8243 6356
aed5dec3 6357 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 6358 dev_err(&pdev->dev,
6359 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 6360 result = PCI_ERS_RESULT_DISCONNECT;
6361 } else {
6362 pci_set_master(pdev);
6363 pci_restore_state(pdev);
b94f2d77 6364 pci_save_state(pdev);
9d5c8243 6365
40a914fa
AD		 6366 pci_enable_wake(pdev, PCI_D3hot, 0);
6367 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 6368
40a914fa
AD		 6369 igb_reset(adapter);
6370 wr32(E1000_WUS, ~0);
6371 result = PCI_ERS_RESULT_RECOVERED;
6372 }
9d5c8243 6373
ea943d41
JK		 6374 err = pci_cleanup_aer_uncorrect_error_status(pdev);
6375 if (err) {
6376 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
6377 "failed 0x%0x\n", err);
6378 /* non-fatal, continue */
6379 }
40a914fa
AD		 6380
6381 return result;
9d5c8243
AK		 6382}
6383
6384/**
6385 * igb_io_resume - called when traffic can start flowing again.
6386 * @pdev: Pointer to PCI device
6387 *
6388 * This callback is called when the error recovery driver tells us that
6389 * its OK to resume normal operation. Implementation resembles the
6390 * second-half of the igb_resume routine.
6391 */
6392static void igb_io_resume(struct pci_dev *pdev)
6393{
6394 struct net_device *netdev = pci_get_drvdata(pdev);
6395 struct igb_adapter *adapter = netdev_priv(netdev);
6396
9d5c8243
AK		 6397 if (netif_running(netdev)) {
6398 if (igb_up(adapter)) {
6399 dev_err(&pdev->dev, "igb_up failed after reset\n");
6400 return;
6401 }
6402 }
6403
6404 netif_device_attach(netdev);
6405
6406 /* let the f/w know that the h/w is now under the control of the
6407 * driver. */
6408 igb_get_hw_control(adapter);
9d5c8243
AK		 6409}
6410
26ad9178
AD		 6411static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
6412 u8 qsel)
6413{
6414 u32 rar_low, rar_high;
6415 struct e1000_hw *hw = &adapter->hw;
6416
6417 /* HW expects these in little endian so we reverse the byte order
6418 * from network order (big endian) to little endian
6419 */
6420 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
6421 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
6422 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
6423
6424 /* Indicate to hardware the Address is Valid. */
6425 rar_high |= E1000_RAH_AV;
6426
6427 if (hw->mac.type == e1000_82575)
6428 rar_high |= E1000_RAH_POOL_1 * qsel;
6429 else
6430 rar_high |= E1000_RAH_POOL_1 << qsel;
6431
6432 wr32(E1000_RAL(index), rar_low);
6433 wrfl();
6434 wr32(E1000_RAH(index), rar_high);
6435 wrfl();
6436}
6437
4ae196df
AD		 6438static int igb_set_vf_mac(struct igb_adapter *adapter,
6439 int vf, unsigned char *mac_addr)
6440{
6441 struct e1000_hw *hw = &adapter->hw;
ff41f8dc
AD		 6442 /* VF MAC addresses start at end of receive addresses and moves
6443 * torwards the first, as a result a collision should not be possible */
6444 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 6445
37680117 6446 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 6447
26ad9178 6448 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
4ae196df
AD		 6449
6450 return 0;
6451}
6452
8151d294
WM		 6453static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
6454{
6455 struct igb_adapter *adapter = netdev_priv(netdev);
6456 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
6457 return -EINVAL;
6458 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
6459 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
6460 dev_info(&adapter->pdev->dev, "Reload the VF driver to make this"
6461 " change effective.");
6462 if (test_bit(__IGB_DOWN, &adapter->state)) {
6463 dev_warn(&adapter->pdev->dev, "The VF MAC address has been set,"
6464 " but the PF device is not up.\n");
6465 dev_warn(&adapter->pdev->dev, "Bring the PF device up before"
6466 " attempting to use the VF device.\n");
6467 }
6468 return igb_set_vf_mac(adapter, vf, mac);
6469}
6470
6471static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate)
6472{
6473 return -EOPNOTSUPP;
6474}
6475
6476static int igb_ndo_get_vf_config(struct net_device *netdev,
6477 int vf, struct ifla_vf_info *ivi)
6478{
6479 struct igb_adapter *adapter = netdev_priv(netdev);
6480 if (vf >= adapter->vfs_allocated_count)
6481 return -EINVAL;
6482 ivi->vf = vf;
6483 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
6484 ivi->tx_rate = 0;
6485 ivi->vlan = adapter->vf_data[vf].pf_vlan;
6486 ivi->qos = adapter->vf_data[vf].pf_qos;
6487 return 0;
6488}
6489
4ae196df
AD		 6490static void igb_vmm_control(struct igb_adapter *adapter)
6491{
6492 struct e1000_hw *hw = &adapter->hw;
10d8e907 6493 u32 reg;
4ae196df 6494
52a1dd4d
AD		 6495 switch (hw->mac.type) {
6496 case e1000_82575:
6497 default:
6498 /* replication is not supported for 82575 */
4ae196df 6499 return;
52a1dd4d
AD		 6500 case e1000_82576:
6501 /* notify HW that the MAC is adding vlan tags */
6502 reg = rd32(E1000_DTXCTL);
6503 reg |= E1000_DTXCTL_VLAN_ADDED;
6504 wr32(E1000_DTXCTL, reg);
6505 case e1000_82580:
6506 /* enable replication vlan tag stripping */
6507 reg = rd32(E1000_RPLOLR);
6508 reg |= E1000_RPLOLR_STRVLAN;
6509 wr32(E1000_RPLOLR, reg);
d2ba2ed8
AD		 6510 case e1000_i350:
6511 /* none of the above registers are supported by i350 */
52a1dd4d
AD		 6512 break;
6513 }
10d8e907 6514
d4960307
AD		 6515 if (adapter->vfs_allocated_count) {
6516 igb_vmdq_set_loopback_pf(hw, true);
6517 igb_vmdq_set_replication_pf(hw, true);
6518 } else {
6519 igb_vmdq_set_loopback_pf(hw, false);
6520 igb_vmdq_set_replication_pf(hw, false);
6521 }
4ae196df
AD		 6522}
6523
9d5c8243 6524/* igb_main.c */
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