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igb: access to NIC time
[mirror_ubuntu-zesty-kernel.git] / drivers / net / igb / igb_main.c
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9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
86d5d38f 4 Copyright(c) 2007-2009 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/module.h>
29#include <linux/types.h>
30#include <linux/init.h>
31#include <linux/vmalloc.h>
32#include <linux/pagemap.h>
33#include <linux/netdevice.h>
9d5c8243
AK		 34#include <linux/ipv6.h>
35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
37#include <linux/mii.h>
38#include <linux/ethtool.h>
39#include <linux/if_vlan.h>
40#include <linux/pci.h>
c54106bb 41#include <linux/pci-aspm.h>
9d5c8243
AK		 42#include <linux/delay.h>
43#include <linux/interrupt.h>
44#include <linux/if_ether.h>
40a914fa 45#include <linux/aer.h>
421e02f0 46#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 47#include <linux/dca.h>
48#endif
9d5c8243
AK		 49#include "igb.h"
50
86d5d38f 51#define DRV_VERSION "1.3.16-k2"
9d5c8243
AK		 52char igb_driver_name[] = "igb";
53char igb_driver_version[] = DRV_VERSION;
54static const char igb_driver_string[] =
55 "Intel(R) Gigabit Ethernet Network Driver";
86d5d38f 56static const char igb_copyright[] = "Copyright (c) 2007-2009 Intel Corporation.";
9d5c8243 57
9d5c8243
AK		 58static const struct e1000_info *igb_info_tbl[] = {
59 [board_82575] = &e1000_82575_info,
60};
61
62static struct pci_device_id igb_pci_tbl[] = {
2d064c06
AD		 63 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
9d5c8243
AK		 66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
69 /* required last entry */
70 {0, }
71};
72
73MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
74
75void igb_reset(struct igb_adapter *);
76static int igb_setup_all_tx_resources(struct igb_adapter *);
77static int igb_setup_all_rx_resources(struct igb_adapter *);
78static void igb_free_all_tx_resources(struct igb_adapter *);
79static void igb_free_all_rx_resources(struct igb_adapter *);
9d5c8243
AK		 80void igb_update_stats(struct igb_adapter *);
81static int igb_probe(struct pci_dev *, const struct pci_device_id *);
82static void __devexit igb_remove(struct pci_dev *pdev);
83static int igb_sw_init(struct igb_adapter *);
84static int igb_open(struct net_device *);
85static int igb_close(struct net_device *);
86static void igb_configure_tx(struct igb_adapter *);
87static void igb_configure_rx(struct igb_adapter *);
88static void igb_setup_rctl(struct igb_adapter *);
89static void igb_clean_all_tx_rings(struct igb_adapter *);
90static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 91static void igb_clean_tx_ring(struct igb_ring *);
92static void igb_clean_rx_ring(struct igb_ring *);
9d5c8243
AK		 93static void igb_set_multi(struct net_device *);
94static void igb_update_phy_info(unsigned long);
95static void igb_watchdog(unsigned long);
96static void igb_watchdog_task(struct work_struct *);
97static int igb_xmit_frame_ring_adv(struct sk_buff *, struct net_device *,
98 struct igb_ring *);
99static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
100static struct net_device_stats *igb_get_stats(struct net_device *);
101static int igb_change_mtu(struct net_device *, int);
102static int igb_set_mac(struct net_device *, void *);
103static irqreturn_t igb_intr(int irq, void *);
104static irqreturn_t igb_intr_msi(int irq, void *);
105static irqreturn_t igb_msix_other(int irq, void *);
106static irqreturn_t igb_msix_rx(int irq, void *);
107static irqreturn_t igb_msix_tx(int irq, void *);
108static int igb_clean_rx_ring_msix(struct napi_struct *, int);
421e02f0 109#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 110static void igb_update_rx_dca(struct igb_ring *);
111static void igb_update_tx_dca(struct igb_ring *);
112static void igb_setup_dca(struct igb_adapter *);
421e02f0 113#endif /* CONFIG_IGB_DCA */
3b644cf6 114static bool igb_clean_tx_irq(struct igb_ring *);
661086df 115static int igb_poll(struct napi_struct *, int);
3b644cf6
MW		 116static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int);
117static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
9d5c8243
AK		 118static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
119static void igb_tx_timeout(struct net_device *);
120static void igb_reset_task(struct work_struct *);
121static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
122static void igb_vlan_rx_add_vid(struct net_device *, u16);
123static void igb_vlan_rx_kill_vid(struct net_device *, u16);
124static void igb_restore_vlan(struct igb_adapter *);
125
126static int igb_suspend(struct pci_dev *, pm_message_t);
127#ifdef CONFIG_PM
128static int igb_resume(struct pci_dev *);
129#endif
130static void igb_shutdown(struct pci_dev *);
421e02f0 131#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 132static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
133static struct notifier_block dca_notifier = {
134 .notifier_call = igb_notify_dca,
135 .next = NULL,
136 .priority = 0
137};
138#endif
9d5c8243
AK		 139
140#ifdef CONFIG_NET_POLL_CONTROLLER
141/* for netdump / net console */
142static void igb_netpoll(struct net_device *);
143#endif
144
145static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
146 pci_channel_state_t);
147static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
148static void igb_io_resume(struct pci_dev *);
149
150static struct pci_error_handlers igb_err_handler = {
151 .error_detected = igb_io_error_detected,
152 .slot_reset = igb_io_slot_reset,
153 .resume = igb_io_resume,
154};
155
156
157static struct pci_driver igb_driver = {
158 .name = igb_driver_name,
159 .id_table = igb_pci_tbl,
160 .probe = igb_probe,
161 .remove = __devexit_p(igb_remove),
162#ifdef CONFIG_PM
163 /* Power Managment Hooks */
164 .suspend = igb_suspend,
165 .resume = igb_resume,
166#endif
167 .shutdown = igb_shutdown,
168 .err_handler = &igb_err_handler
169};
170
7dfc16fa
AD		 171static int global_quad_port_a; /* global quad port a indication */
172
9d5c8243
AK		 173MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
174MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
175MODULE_LICENSE("GPL");
176MODULE_VERSION(DRV_VERSION);
177
38c845c7
PO		 178/**
179 * Scale the NIC clock cycle by a large factor so that
180 * relatively small clock corrections can be added or
181 * substracted at each clock tick. The drawbacks of a
182 * large factor are a) that the clock register overflows
183 * more quickly (not such a big deal) and b) that the
184 * increment per tick has to fit into 24 bits.
185 *
186 * Note that
187 * TIMINCA = IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS *
188 * IGB_TSYNC_SCALE
189 * TIMINCA += TIMINCA * adjustment [ppm] / 1e9
190 *
191 * The base scale factor is intentionally a power of two
192 * so that the division in %struct timecounter can be done with
193 * a shift.
194 */
195#define IGB_TSYNC_SHIFT (19)
196#define IGB_TSYNC_SCALE (1<<IGB_TSYNC_SHIFT)
197
198/**
199 * The duration of one clock cycle of the NIC.
200 *
201 * @todo This hard-coded value is part of the specification and might change
202 * in future hardware revisions. Add revision check.
203 */
204#define IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS 16
205
206#if (IGB_TSYNC_SCALE * IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS) >= (1<<24)
207# error IGB_TSYNC_SCALE and/or IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS are too large to fit into TIMINCA
208#endif
209
210/**
211 * igb_read_clock - read raw cycle counter (to be used by time counter)
212 */
213static cycle_t igb_read_clock(const struct cyclecounter *tc)
214{
215 struct igb_adapter *adapter =
216 container_of(tc, struct igb_adapter, cycles);
217 struct e1000_hw *hw = &adapter->hw;
218 u64 stamp;
219
220 stamp = rd32(E1000_SYSTIML);
221 stamp |= (u64)rd32(E1000_SYSTIMH) << 32ULL;
222
223 return stamp;
224}
225
9d5c8243
AK		 226#ifdef DEBUG
227/**
228 * igb_get_hw_dev_name - return device name string
229 * used by hardware layer to print debugging information
230 **/
231char *igb_get_hw_dev_name(struct e1000_hw *hw)
232{
233 struct igb_adapter *adapter = hw->back;
234 return adapter->netdev->name;
235}
38c845c7
PO		 236
237/**
238 * igb_get_time_str - format current NIC and system time as string
239 */
240static char *igb_get_time_str(struct igb_adapter *adapter,
241 char buffer[160])
242{
243 cycle_t hw = adapter->cycles.read(&adapter->cycles);
244 struct timespec nic = ns_to_timespec(timecounter_read(&adapter->clock));
245 struct timespec sys;
246 struct timespec delta;
247 getnstimeofday(&sys);
248
249 delta = timespec_sub(nic, sys);
250
251 sprintf(buffer,
252 "NIC %ld.%09lus, SYS %ld.%09lus, NIC-SYS %lds + %09luns",
253 (long)nic.tv_sec, nic.tv_nsec,
254 (long)sys.tv_sec, sys.tv_nsec,
255 (long)delta.tv_sec, delta.tv_nsec);
256
257 return buffer;
258}
9d5c8243
AK		 259#endif
260
261/**
262 * igb_init_module - Driver Registration Routine
263 *
264 * igb_init_module is the first routine called when the driver is
265 * loaded. All it does is register with the PCI subsystem.
266 **/
267static int __init igb_init_module(void)
268{
269 int ret;
270 printk(KERN_INFO "%s - version %s\n",
271 igb_driver_string, igb_driver_version);
272
273 printk(KERN_INFO "%s\n", igb_copyright);
274
7dfc16fa
AD		 275 global_quad_port_a = 0;
276
421e02f0 277#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 278 dca_register_notify(&dca_notifier);
279#endif
bbd98fe4
AD		 280
281 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 282 return ret;
283}
284
285module_init(igb_init_module);
286
287/**
288 * igb_exit_module - Driver Exit Cleanup Routine
289 *
290 * igb_exit_module is called just before the driver is removed
291 * from memory.
292 **/
293static void __exit igb_exit_module(void)
294{
421e02f0 295#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 296 dca_unregister_notify(&dca_notifier);
297#endif
9d5c8243
AK		 298 pci_unregister_driver(&igb_driver);
299}
300
301module_exit(igb_exit_module);
302
26bc19ec
AD		 303#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
304/**
305 * igb_cache_ring_register - Descriptor ring to register mapping
306 * @adapter: board private structure to initialize
307 *
308 * Once we know the feature-set enabled for the device, we'll cache
309 * the register offset the descriptor ring is assigned to.
310 **/
311static void igb_cache_ring_register(struct igb_adapter *adapter)
312{
313 int i;
314
315 switch (adapter->hw.mac.type) {
316 case e1000_82576:
317 /* The queues are allocated for virtualization such that VF 0
318 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
319 * In order to avoid collision we start at the first free queue
320 * and continue consuming queues in the same sequence
321 */
322 for (i = 0; i < adapter->num_rx_queues; i++)
323 adapter->rx_ring[i].reg_idx = Q_IDX_82576(i);
324 for (i = 0; i < adapter->num_tx_queues; i++)
325 adapter->tx_ring[i].reg_idx = Q_IDX_82576(i);
326 break;
327 case e1000_82575:
328 default:
329 for (i = 0; i < adapter->num_rx_queues; i++)
330 adapter->rx_ring[i].reg_idx = i;
331 for (i = 0; i < adapter->num_tx_queues; i++)
332 adapter->tx_ring[i].reg_idx = i;
333 break;
334 }
335}
336
9d5c8243
AK		 337/**
338 * igb_alloc_queues - Allocate memory for all rings
339 * @adapter: board private structure to initialize
340 *
341 * We allocate one ring per queue at run-time since we don't know the
342 * number of queues at compile-time.
343 **/
344static int igb_alloc_queues(struct igb_adapter *adapter)
345{
346 int i;
347
348 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
349 sizeof(struct igb_ring), GFP_KERNEL);
350 if (!adapter->tx_ring)
351 return -ENOMEM;
352
353 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
354 sizeof(struct igb_ring), GFP_KERNEL);
355 if (!adapter->rx_ring) {
356 kfree(adapter->tx_ring);
357 return -ENOMEM;
358 }
359
6eb5a7f1
AD		 360 adapter->rx_ring->buddy = adapter->tx_ring;
361
661086df
PWJ		 362 for (i = 0; i < adapter->num_tx_queues; i++) {
363 struct igb_ring *ring = &(adapter->tx_ring[i]);
68fd9910 364 ring->count = adapter->tx_ring_count;
661086df
PWJ		 365 ring->adapter = adapter;
366 ring->queue_index = i;
367 }
9d5c8243
AK		 368 for (i = 0; i < adapter->num_rx_queues; i++) {
369 struct igb_ring *ring = &(adapter->rx_ring[i]);
68fd9910 370 ring->count = adapter->rx_ring_count;
9d5c8243 371 ring->adapter = adapter;
844290e5 372 ring->queue_index = i;
9d5c8243
AK		 373 ring->itr_register = E1000_ITR;
374
844290e5 375 /* set a default napi handler for each rx_ring */
661086df 376 netif_napi_add(adapter->netdev, &ring->napi, igb_poll, 64);
9d5c8243 377 }
26bc19ec
AD		 378
379 igb_cache_ring_register(adapter);
9d5c8243
AK		 380 return 0;
381}
382
a88f10ec
AD		 383static void igb_free_queues(struct igb_adapter *adapter)
384{
385 int i;
386
387 for (i = 0; i < adapter->num_rx_queues; i++)
388 netif_napi_del(&adapter->rx_ring[i].napi);
389
390 kfree(adapter->tx_ring);
391 kfree(adapter->rx_ring);
392}
393
9d5c8243
AK		 394#define IGB_N0_QUEUE -1
395static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
396 int tx_queue, int msix_vector)
397{
398 u32 msixbm = 0;
399 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 400 u32 ivar, index;
401
402 switch (hw->mac.type) {
403 case e1000_82575:
9d5c8243
AK		 404 /* The 82575 assigns vectors using a bitmask, which matches the
405 bitmask for the EICR/EIMS/EIMC registers. To assign one
406 or more queues to a vector, we write the appropriate bits
407 into the MSIXBM register for that vector. */
408 if (rx_queue > IGB_N0_QUEUE) {
409 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
410 adapter->rx_ring[rx_queue].eims_value = msixbm;
411 }
412 if (tx_queue > IGB_N0_QUEUE) {
413 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
414 adapter->tx_ring[tx_queue].eims_value =
415 E1000_EICR_TX_QUEUE0 << tx_queue;
416 }
417 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
2d064c06
AD		 418 break;
419 case e1000_82576:
26bc19ec 420 /* 82576 uses a table-based method for assigning vectors.
2d064c06
AD		 421 Each queue has a single entry in the table to which we write
422 a vector number along with a "valid" bit. Sadly, the layout
423 of the table is somewhat counterintuitive. */
424 if (rx_queue > IGB_N0_QUEUE) {
26bc19ec 425 index = (rx_queue >> 1);
2d064c06 426 ivar = array_rd32(E1000_IVAR0, index);
26bc19ec 427 if (rx_queue & 0x1) {
2d064c06
AD		 428 /* vector goes into third byte of register */
429 ivar = ivar & 0xFF00FFFF;
430 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
26bc19ec
AD		 431 } else {
432 /* vector goes into low byte of register */
433 ivar = ivar & 0xFFFFFF00;
434 ivar |= msix_vector | E1000_IVAR_VALID;
2d064c06
AD		 435 }
436 adapter->rx_ring[rx_queue].eims_value= 1 << msix_vector;
437 array_wr32(E1000_IVAR0, index, ivar);
438 }
439 if (tx_queue > IGB_N0_QUEUE) {
26bc19ec 440 index = (tx_queue >> 1);
2d064c06 441 ivar = array_rd32(E1000_IVAR0, index);
26bc19ec 442 if (tx_queue & 0x1) {
2d064c06
AD		 443 /* vector goes into high byte of register */
444 ivar = ivar & 0x00FFFFFF;
445 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
26bc19ec
AD		 446 } else {
447 /* vector goes into second byte of register */
448 ivar = ivar & 0xFFFF00FF;
449 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
2d064c06
AD		 450 }
451 adapter->tx_ring[tx_queue].eims_value= 1 << msix_vector;
452 array_wr32(E1000_IVAR0, index, ivar);
453 }
454 break;
455 default:
456 BUG();
457 break;
458 }
9d5c8243
AK		 459}
460
461/**
462 * igb_configure_msix - Configure MSI-X hardware
463 *
464 * igb_configure_msix sets up the hardware to properly
465 * generate MSI-X interrupts.
466 **/
467static void igb_configure_msix(struct igb_adapter *adapter)
468{
469 u32 tmp;
470 int i, vector = 0;
471 struct e1000_hw *hw = &adapter->hw;
472
473 adapter->eims_enable_mask = 0;
2d064c06
AD		 474 if (hw->mac.type == e1000_82576)
475 /* Turn on MSI-X capability first, or our settings
476 * won't stick. And it will take days to debug. */
477 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
eebbbdba 478 E1000_GPIE_PBA | E1000_GPIE_EIAME |
2d064c06 479 E1000_GPIE_NSICR);
9d5c8243
AK		 480
481 for (i = 0; i < adapter->num_tx_queues; i++) {
482 struct igb_ring *tx_ring = &adapter->tx_ring[i];
483 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
484 adapter->eims_enable_mask |= tx_ring->eims_value;
485 if (tx_ring->itr_val)
6eb5a7f1 486 writel(tx_ring->itr_val,
9d5c8243
AK		 487 hw->hw_addr + tx_ring->itr_register);
488 else
489 writel(1, hw->hw_addr + tx_ring->itr_register);
490 }
491
492 for (i = 0; i < adapter->num_rx_queues; i++) {
493 struct igb_ring *rx_ring = &adapter->rx_ring[i];
25ac3c24 494 rx_ring->buddy = NULL;
9d5c8243
AK		 495 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
496 adapter->eims_enable_mask |= rx_ring->eims_value;
497 if (rx_ring->itr_val)
6eb5a7f1 498 writel(rx_ring->itr_val,
9d5c8243
AK		 499 hw->hw_addr + rx_ring->itr_register);
500 else
501 writel(1, hw->hw_addr + rx_ring->itr_register);
502 }
503
504
505 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 506 switch (hw->mac.type) {
507 case e1000_82575:
9d5c8243
AK		 508 array_wr32(E1000_MSIXBM(0), vector++,
509 E1000_EIMS_OTHER);
510
9d5c8243
AK		 511 tmp = rd32(E1000_CTRL_EXT);
512 /* enable MSI-X PBA support*/
513 tmp |= E1000_CTRL_EXT_PBA_CLR;
514
515 /* Auto-Mask interrupts upon ICR read. */
516 tmp |= E1000_CTRL_EXT_EIAME;
517 tmp |= E1000_CTRL_EXT_IRCA;
518
519 wr32(E1000_CTRL_EXT, tmp);
520 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
844290e5 521 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 522
2d064c06
AD		 523 break;
524
525 case e1000_82576:
526 tmp = (vector++ | E1000_IVAR_VALID) << 8;
527 wr32(E1000_IVAR_MISC, tmp);
528
529 adapter->eims_enable_mask = (1 << (vector)) - 1;
530 adapter->eims_other = 1 << (vector - 1);
531 break;
532 default:
533 /* do nothing, since nothing else supports MSI-X */
534 break;
535 } /* switch (hw->mac.type) */
9d5c8243
AK		 536 wrfl();
537}
538
539/**
540 * igb_request_msix - Initialize MSI-X interrupts
541 *
542 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
543 * kernel.
544 **/
545static int igb_request_msix(struct igb_adapter *adapter)
546{
547 struct net_device *netdev = adapter->netdev;
548 int i, err = 0, vector = 0;
549
550 vector = 0;
551
552 for (i = 0; i < adapter->num_tx_queues; i++) {
553 struct igb_ring *ring = &(adapter->tx_ring[i]);
cb7b48f6 554 sprintf(ring->name, "%s-tx-%d", netdev->name, i);
9d5c8243
AK		 555 err = request_irq(adapter->msix_entries[vector].vector,
556 &igb_msix_tx, 0, ring->name,
557 &(adapter->tx_ring[i]));
558 if (err)
559 goto out;
560 ring->itr_register = E1000_EITR(0) + (vector << 2);
6eb5a7f1 561 ring->itr_val = 976; /* ~4000 ints/sec */
9d5c8243
AK		 562 vector++;
563 }
564 for (i = 0; i < adapter->num_rx_queues; i++) {
565 struct igb_ring *ring = &(adapter->rx_ring[i]);
566 if (strlen(netdev->name) < (IFNAMSIZ - 5))
cb7b48f6 567 sprintf(ring->name, "%s-rx-%d", netdev->name, i);
9d5c8243
AK		 568 else
569 memcpy(ring->name, netdev->name, IFNAMSIZ);
570 err = request_irq(adapter->msix_entries[vector].vector,
571 &igb_msix_rx, 0, ring->name,
572 &(adapter->rx_ring[i]));
573 if (err)
574 goto out;
575 ring->itr_register = E1000_EITR(0) + (vector << 2);
576 ring->itr_val = adapter->itr;
844290e5
PW		 577 /* overwrite the poll routine for MSIX, we've already done
578 * netif_napi_add */
579 ring->napi.poll = &igb_clean_rx_ring_msix;
9d5c8243
AK		 580 vector++;
581 }
582
583 err = request_irq(adapter->msix_entries[vector].vector,
584 &igb_msix_other, 0, netdev->name, netdev);
585 if (err)
586 goto out;
587
9d5c8243
AK		 588 igb_configure_msix(adapter);
589 return 0;
590out:
591 return err;
592}
593
594static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
595{
596 if (adapter->msix_entries) {
597 pci_disable_msix(adapter->pdev);
598 kfree(adapter->msix_entries);
599 adapter->msix_entries = NULL;
7dfc16fa 600 } else if (adapter->flags & IGB_FLAG_HAS_MSI)
9d5c8243
AK		 601 pci_disable_msi(adapter->pdev);
602 return;
603}
604
605
606/**
607 * igb_set_interrupt_capability - set MSI or MSI-X if supported
608 *
609 * Attempt to configure interrupts using the best available
610 * capabilities of the hardware and kernel.
611 **/
612static void igb_set_interrupt_capability(struct igb_adapter *adapter)
613{
614 int err;
615 int numvecs, i;
616
83b7180d
AD		 617 /* Number of supported queues. */
618 /* Having more queues than CPUs doesn't make sense. */
619 adapter->num_rx_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
620 adapter->num_tx_queues = min_t(u32, IGB_MAX_TX_QUEUES, num_online_cpus());
621
9d5c8243
AK		 622 numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1;
623 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
624 GFP_KERNEL);
625 if (!adapter->msix_entries)
626 goto msi_only;
627
628 for (i = 0; i < numvecs; i++)
629 adapter->msix_entries[i].entry = i;
630
631 err = pci_enable_msix(adapter->pdev,
632 adapter->msix_entries,
633 numvecs);
634 if (err == 0)
34a20e89 635 goto out;
9d5c8243
AK		 636
637 igb_reset_interrupt_capability(adapter);
638
639 /* If we can't do MSI-X, try MSI */
640msi_only:
641 adapter->num_rx_queues = 1;
661086df 642 adapter->num_tx_queues = 1;
9d5c8243 643 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 644 adapter->flags |= IGB_FLAG_HAS_MSI;
34a20e89 645out:
661086df 646 /* Notify the stack of the (possibly) reduced Tx Queue count. */
fd2ea0a7 647 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
9d5c8243
AK		 648 return;
649}
650
651/**
652 * igb_request_irq - initialize interrupts
653 *
654 * Attempts to configure interrupts using the best available
655 * capabilities of the hardware and kernel.
656 **/
657static int igb_request_irq(struct igb_adapter *adapter)
658{
659 struct net_device *netdev = adapter->netdev;
660 struct e1000_hw *hw = &adapter->hw;
661 int err = 0;
662
663 if (adapter->msix_entries) {
664 err = igb_request_msix(adapter);
844290e5 665 if (!err)
9d5c8243 666 goto request_done;
9d5c8243
AK		 667 /* fall back to MSI */
668 igb_reset_interrupt_capability(adapter);
669 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 670 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 671 igb_free_all_tx_resources(adapter);
672 igb_free_all_rx_resources(adapter);
673 adapter->num_rx_queues = 1;
674 igb_alloc_queues(adapter);
844290e5 675 } else {
2d064c06
AD		 676 switch (hw->mac.type) {
677 case e1000_82575:
678 wr32(E1000_MSIXBM(0),
679 (E1000_EICR_RX_QUEUE0 | E1000_EIMS_OTHER));
680 break;
681 case e1000_82576:
682 wr32(E1000_IVAR0, E1000_IVAR_VALID);
683 break;
684 default:
685 break;
686 }
9d5c8243 687 }
844290e5 688
7dfc16fa 689 if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243
AK		 690 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
691 netdev->name, netdev);
692 if (!err)
693 goto request_done;
694 /* fall back to legacy interrupts */
695 igb_reset_interrupt_capability(adapter);
7dfc16fa 696 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 697 }
698
699 err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
700 netdev->name, netdev);
701
6cb5e577 702 if (err)
9d5c8243
AK		 703 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
704 err);
9d5c8243
AK		 705
706request_done:
707 return err;
708}
709
710static void igb_free_irq(struct igb_adapter *adapter)
711{
712 struct net_device *netdev = adapter->netdev;
713
714 if (adapter->msix_entries) {
715 int vector = 0, i;
716
717 for (i = 0; i < adapter->num_tx_queues; i++)
718 free_irq(adapter->msix_entries[vector++].vector,
719 &(adapter->tx_ring[i]));
720 for (i = 0; i < adapter->num_rx_queues; i++)
721 free_irq(adapter->msix_entries[vector++].vector,
722 &(adapter->rx_ring[i]));
723
724 free_irq(adapter->msix_entries[vector++].vector, netdev);
725 return;
726 }
727
728 free_irq(adapter->pdev->irq, netdev);
729}
730
731/**
732 * igb_irq_disable - Mask off interrupt generation on the NIC
733 * @adapter: board private structure
734 **/
735static void igb_irq_disable(struct igb_adapter *adapter)
736{
737 struct e1000_hw *hw = &adapter->hw;
738
739 if (adapter->msix_entries) {
844290e5 740 wr32(E1000_EIAM, 0);
9d5c8243
AK		 741 wr32(E1000_EIMC, ~0);
742 wr32(E1000_EIAC, 0);
743 }
844290e5
PW		 744
745 wr32(E1000_IAM, 0);
9d5c8243
AK		 746 wr32(E1000_IMC, ~0);
747 wrfl();
748 synchronize_irq(adapter->pdev->irq);
749}
750
751/**
752 * igb_irq_enable - Enable default interrupt generation settings
753 * @adapter: board private structure
754 **/
755static void igb_irq_enable(struct igb_adapter *adapter)
756{
757 struct e1000_hw *hw = &adapter->hw;
758
759 if (adapter->msix_entries) {
844290e5
PW		 760 wr32(E1000_EIAC, adapter->eims_enable_mask);
761 wr32(E1000_EIAM, adapter->eims_enable_mask);
762 wr32(E1000_EIMS, adapter->eims_enable_mask);
dda0e083 763 wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC);
844290e5
PW		 764 } else {
765 wr32(E1000_IMS, IMS_ENABLE_MASK);
766 wr32(E1000_IAM, IMS_ENABLE_MASK);
767 }
9d5c8243
AK		 768}
769
770static void igb_update_mng_vlan(struct igb_adapter *adapter)
771{
772 struct net_device *netdev = adapter->netdev;
773 u16 vid = adapter->hw.mng_cookie.vlan_id;
774 u16 old_vid = adapter->mng_vlan_id;
775 if (adapter->vlgrp) {
776 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
777 if (adapter->hw.mng_cookie.status &
778 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
779 igb_vlan_rx_add_vid(netdev, vid);
780 adapter->mng_vlan_id = vid;
781 } else
782 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
783
784 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
785 (vid != old_vid) &&
786 !vlan_group_get_device(adapter->vlgrp, old_vid))
787 igb_vlan_rx_kill_vid(netdev, old_vid);
788 } else
789 adapter->mng_vlan_id = vid;
790 }
791}
792
793/**
794 * igb_release_hw_control - release control of the h/w to f/w
795 * @adapter: address of board private structure
796 *
797 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
798 * For ASF and Pass Through versions of f/w this means that the
799 * driver is no longer loaded.
800 *
801 **/
802static void igb_release_hw_control(struct igb_adapter *adapter)
803{
804 struct e1000_hw *hw = &adapter->hw;
805 u32 ctrl_ext;
806
807 /* Let firmware take over control of h/w */
808 ctrl_ext = rd32(E1000_CTRL_EXT);
809 wr32(E1000_CTRL_EXT,
810 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
811}
812
813
814/**
815 * igb_get_hw_control - get control of the h/w from f/w
816 * @adapter: address of board private structure
817 *
818 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
819 * For ASF and Pass Through versions of f/w this means that
820 * the driver is loaded.
821 *
822 **/
823static void igb_get_hw_control(struct igb_adapter *adapter)
824{
825 struct e1000_hw *hw = &adapter->hw;
826 u32 ctrl_ext;
827
828 /* Let firmware know the driver has taken over */
829 ctrl_ext = rd32(E1000_CTRL_EXT);
830 wr32(E1000_CTRL_EXT,
831 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
832}
833
9d5c8243
AK		 834/**
835 * igb_configure - configure the hardware for RX and TX
836 * @adapter: private board structure
837 **/
838static void igb_configure(struct igb_adapter *adapter)
839{
840 struct net_device *netdev = adapter->netdev;
841 int i;
842
843 igb_get_hw_control(adapter);
844 igb_set_multi(netdev);
845
846 igb_restore_vlan(adapter);
9d5c8243
AK		 847
848 igb_configure_tx(adapter);
849 igb_setup_rctl(adapter);
850 igb_configure_rx(adapter);
662d7205
AD		 851
852 igb_rx_fifo_flush_82575(&adapter->hw);
853
9d5c8243
AK		 854 /* call IGB_DESC_UNUSED which always leaves
855 * at least 1 descriptor unused to make sure
856 * next_to_use != next_to_clean */
857 for (i = 0; i < adapter->num_rx_queues; i++) {
858 struct igb_ring *ring = &adapter->rx_ring[i];
3b644cf6 859 igb_alloc_rx_buffers_adv(ring, IGB_DESC_UNUSED(ring));
9d5c8243
AK		 860 }
861
862
863 adapter->tx_queue_len = netdev->tx_queue_len;
864}
865
866
867/**
868 * igb_up - Open the interface and prepare it to handle traffic
869 * @adapter: board private structure
870 **/
871
872int igb_up(struct igb_adapter *adapter)
873{
874 struct e1000_hw *hw = &adapter->hw;
875 int i;
876
877 /* hardware has been reset, we need to reload some things */
878 igb_configure(adapter);
879
880 clear_bit(__IGB_DOWN, &adapter->state);
881
844290e5
PW		 882 for (i = 0; i < adapter->num_rx_queues; i++)
883 napi_enable(&adapter->rx_ring[i].napi);
884 if (adapter->msix_entries)
9d5c8243 885 igb_configure_msix(adapter);
9d5c8243
AK		 886
887 /* Clear any pending interrupts. */
888 rd32(E1000_ICR);
889 igb_irq_enable(adapter);
890
891 /* Fire a link change interrupt to start the watchdog. */
892 wr32(E1000_ICS, E1000_ICS_LSC);
893 return 0;
894}
895
896void igb_down(struct igb_adapter *adapter)
897{
898 struct e1000_hw *hw = &adapter->hw;
899 struct net_device *netdev = adapter->netdev;
900 u32 tctl, rctl;
901 int i;
902
903 /* signal that we're down so the interrupt handler does not
904 * reschedule our watchdog timer */
905 set_bit(__IGB_DOWN, &adapter->state);
906
907 /* disable receives in the hardware */
908 rctl = rd32(E1000_RCTL);
909 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
910 /* flush and sleep below */
911
fd2ea0a7 912 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 913
914 /* disable transmits in the hardware */
915 tctl = rd32(E1000_TCTL);
916 tctl &= ~E1000_TCTL_EN;
917 wr32(E1000_TCTL, tctl);
918 /* flush both disables and wait for them to finish */
919 wrfl();
920 msleep(10);
921
844290e5
PW		 922 for (i = 0; i < adapter->num_rx_queues; i++)
923 napi_disable(&adapter->rx_ring[i].napi);
9d5c8243 924
9d5c8243
AK		 925 igb_irq_disable(adapter);
926
927 del_timer_sync(&adapter->watchdog_timer);
928 del_timer_sync(&adapter->phy_info_timer);
929
930 netdev->tx_queue_len = adapter->tx_queue_len;
931 netif_carrier_off(netdev);
04fe6358
AD		 932
933 /* record the stats before reset*/
934 igb_update_stats(adapter);
935
9d5c8243
AK		 936 adapter->link_speed = 0;
937 adapter->link_duplex = 0;
938
3023682e
JK		 939 if (!pci_channel_offline(adapter->pdev))
940 igb_reset(adapter);
9d5c8243
AK		 941 igb_clean_all_tx_rings(adapter);
942 igb_clean_all_rx_rings(adapter);
943}
944
945void igb_reinit_locked(struct igb_adapter *adapter)
946{
947 WARN_ON(in_interrupt());
948 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
949 msleep(1);
950 igb_down(adapter);
951 igb_up(adapter);
952 clear_bit(__IGB_RESETTING, &adapter->state);
953}
954
955void igb_reset(struct igb_adapter *adapter)
956{
957 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 958 struct e1000_mac_info *mac = &hw->mac;
959 struct e1000_fc_info *fc = &hw->fc;
9d5c8243
AK		 960 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
961 u16 hwm;
962
963 /* Repartition Pba for greater than 9k mtu
964 * To take effect CTRL.RST is required.
965 */
fa4dfae0
AD		 966 switch (mac->type) {
967 case e1000_82576:
2d064c06 968 pba = E1000_PBA_64K;
fa4dfae0
AD		 969 break;
970 case e1000_82575:
971 default:
972 pba = E1000_PBA_34K;
973 break;
2d064c06 974 }
9d5c8243 975
2d064c06
AD		 976 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
977 (mac->type < e1000_82576)) {
9d5c8243
AK		 978 /* adjust PBA for jumbo frames */
979 wr32(E1000_PBA, pba);
980
981 /* To maintain wire speed transmits, the Tx FIFO should be
982 * large enough to accommodate two full transmit packets,
983 * rounded up to the next 1KB and expressed in KB. Likewise,
984 * the Rx FIFO should be large enough to accommodate at least
985 * one full receive packet and is similarly rounded up and
986 * expressed in KB. */
987 pba = rd32(E1000_PBA);
988 /* upper 16 bits has Tx packet buffer allocation size in KB */
989 tx_space = pba >> 16;
990 /* lower 16 bits has Rx packet buffer allocation size in KB */
991 pba &= 0xffff;
992 /* the tx fifo also stores 16 bytes of information about the tx
993 * but don't include ethernet FCS because hardware appends it */
994 min_tx_space = (adapter->max_frame_size +
995 sizeof(struct e1000_tx_desc) -
996 ETH_FCS_LEN) * 2;
997 min_tx_space = ALIGN(min_tx_space, 1024);
998 min_tx_space >>= 10;
999 /* software strips receive CRC, so leave room for it */
1000 min_rx_space = adapter->max_frame_size;
1001 min_rx_space = ALIGN(min_rx_space, 1024);
1002 min_rx_space >>= 10;
1003
1004 /* If current Tx allocation is less than the min Tx FIFO size,
1005 * and the min Tx FIFO size is less than the current Rx FIFO
1006 * allocation, take space away from current Rx allocation */
1007 if (tx_space < min_tx_space &&
1008 ((min_tx_space - tx_space) < pba)) {
1009 pba = pba - (min_tx_space - tx_space);
1010
1011 /* if short on rx space, rx wins and must trump tx
1012 * adjustment */
1013 if (pba < min_rx_space)
1014 pba = min_rx_space;
1015 }
2d064c06 1016 wr32(E1000_PBA, pba);
9d5c8243 1017 }
9d5c8243
AK		 1018
1019 /* flow control settings */
1020 /* The high water mark must be low enough to fit one full frame
1021 * (or the size used for early receive) above it in the Rx FIFO.
1022 * Set it to the lower of:
1023 * - 90% of the Rx FIFO size, or
1024 * - the full Rx FIFO size minus one full frame */
1025 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1026 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1027
2d064c06
AD		 1028 if (mac->type < e1000_82576) {
1029 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
1030 fc->low_water = fc->high_water - 8;
1031 } else {
1032 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1033 fc->low_water = fc->high_water - 16;
1034 }
9d5c8243
AK		 1035 fc->pause_time = 0xFFFF;
1036 fc->send_xon = 1;
1037 fc->type = fc->original_type;
1038
1039 /* Allow time for pending master requests to run */
1040 adapter->hw.mac.ops.reset_hw(&adapter->hw);
1041 wr32(E1000_WUC, 0);
1042
1043 if (adapter->hw.mac.ops.init_hw(&adapter->hw))
1044 dev_err(&adapter->pdev->dev, "Hardware Error\n");
1045
1046 igb_update_mng_vlan(adapter);
1047
1048 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1049 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1050
1051 igb_reset_adaptive(&adapter->hw);
f5f4cf08 1052 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 1053}
1054
2e5c6922
SH		 1055static const struct net_device_ops igb_netdev_ops = {
1056 .ndo_open = igb_open,
1057 .ndo_stop = igb_close,
00829823 1058 .ndo_start_xmit = igb_xmit_frame_adv,
2e5c6922
SH		 1059 .ndo_get_stats = igb_get_stats,
1060 .ndo_set_multicast_list = igb_set_multi,
1061 .ndo_set_mac_address = igb_set_mac,
1062 .ndo_change_mtu = igb_change_mtu,
1063 .ndo_do_ioctl = igb_ioctl,
1064 .ndo_tx_timeout = igb_tx_timeout,
1065 .ndo_validate_addr = eth_validate_addr,
1066 .ndo_vlan_rx_register = igb_vlan_rx_register,
1067 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1068 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
1069#ifdef CONFIG_NET_POLL_CONTROLLER
1070 .ndo_poll_controller = igb_netpoll,
1071#endif
1072};
1073
9d5c8243
AK		 1074/**
1075 * igb_probe - Device Initialization Routine
1076 * @pdev: PCI device information struct
1077 * @ent: entry in igb_pci_tbl
1078 *
1079 * Returns 0 on success, negative on failure
1080 *
1081 * igb_probe initializes an adapter identified by a pci_dev structure.
1082 * The OS initialization, configuring of the adapter private structure,
1083 * and a hardware reset occur.
1084 **/
1085static int __devinit igb_probe(struct pci_dev *pdev,
1086 const struct pci_device_id *ent)
1087{
1088 struct net_device *netdev;
1089 struct igb_adapter *adapter;
1090 struct e1000_hw *hw;
c54106bb 1091 struct pci_dev *us_dev;
9d5c8243
AK		 1092 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1093 unsigned long mmio_start, mmio_len;
450c87c8 1094 int err, pci_using_dac, pos;
c54106bb 1095 u16 eeprom_data = 0, state = 0;
9d5c8243
AK		 1096 u16 eeprom_apme_mask = IGB_EEPROM_APME;
1097 u32 part_num;
1098
aed5dec3 1099 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 1100 if (err)
1101 return err;
1102
1103 pci_using_dac = 0;
1104 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
1105 if (!err) {
1106 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1107 if (!err)
1108 pci_using_dac = 1;
1109 } else {
1110 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1111 if (err) {
1112 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1113 if (err) {
1114 dev_err(&pdev->dev, "No usable DMA "
1115 "configuration, aborting\n");
1116 goto err_dma;
1117 }
1118 }
1119 }
1120
c54106bb
AD		 1121 /* 82575 requires that the pci-e link partner disable the L0s state */
1122 switch (pdev->device) {
1123 case E1000_DEV_ID_82575EB_COPPER:
1124 case E1000_DEV_ID_82575EB_FIBER_SERDES:
1125 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1126 us_dev = pdev->bus->self;
1127 pos = pci_find_capability(us_dev, PCI_CAP_ID_EXP);
1128 if (pos) {
1129 pci_read_config_word(us_dev, pos + PCI_EXP_LNKCTL,
1130 &state);
1131 state &= ~PCIE_LINK_STATE_L0S;
1132 pci_write_config_word(us_dev, pos + PCI_EXP_LNKCTL,
1133 state);
ac450208
BH		 1134 dev_info(&pdev->dev,
1135 "Disabling ASPM L0s upstream switch port %s\n",
1136 pci_name(us_dev));
c54106bb
AD		 1137 }
1138 default:
1139 break;
1140 }
1141
aed5dec3
AD		 1142 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1143 IORESOURCE_MEM),
1144 igb_driver_name);
9d5c8243
AK		 1145 if (err)
1146 goto err_pci_reg;
1147
ea943d41
JK		 1148 err = pci_enable_pcie_error_reporting(pdev);
1149 if (err) {
1150 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
1151 "0x%x\n", err);
1152 /* non-fatal, continue */
1153 }
40a914fa 1154
9d5c8243 1155 pci_set_master(pdev);
c682fc23 1156 pci_save_state(pdev);
9d5c8243
AK		 1157
1158 err = -ENOMEM;
661086df 1159 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), IGB_MAX_TX_QUEUES);
9d5c8243
AK		 1160 if (!netdev)
1161 goto err_alloc_etherdev;
1162
1163 SET_NETDEV_DEV(netdev, &pdev->dev);
1164
1165 pci_set_drvdata(pdev, netdev);
1166 adapter = netdev_priv(netdev);
1167 adapter->netdev = netdev;
1168 adapter->pdev = pdev;
1169 hw = &adapter->hw;
1170 hw->back = adapter;
1171 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
1172
1173 mmio_start = pci_resource_start(pdev, 0);
1174 mmio_len = pci_resource_len(pdev, 0);
1175
1176 err = -EIO;
28b0759c
AD		 1177 hw->hw_addr = ioremap(mmio_start, mmio_len);
1178 if (!hw->hw_addr)
9d5c8243
AK		 1179 goto err_ioremap;
1180
2e5c6922 1181 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 1182 igb_set_ethtool_ops(netdev);
9d5c8243 1183 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 1184
1185 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1186
1187 netdev->mem_start = mmio_start;
1188 netdev->mem_end = mmio_start + mmio_len;
1189
9d5c8243
AK		 1190 /* PCI config space info */
1191 hw->vendor_id = pdev->vendor;
1192 hw->device_id = pdev->device;
1193 hw->revision_id = pdev->revision;
1194 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1195 hw->subsystem_device_id = pdev->subsystem_device;
1196
1197 /* setup the private structure */
1198 hw->back = adapter;
1199 /* Copy the default MAC, PHY and NVM function pointers */
1200 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1201 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1202 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1203 /* Initialize skew-specific constants */
1204 err = ei->get_invariants(hw);
1205 if (err)
450c87c8 1206 goto err_sw_init;
9d5c8243 1207
450c87c8 1208 /* setup the private structure */
9d5c8243
AK		 1209 err = igb_sw_init(adapter);
1210 if (err)
1211 goto err_sw_init;
1212
1213 igb_get_bus_info_pcie(hw);
1214
7dfc16fa
AD		 1215 /* set flags */
1216 switch (hw->mac.type) {
7dfc16fa 1217 case e1000_82575:
7dfc16fa
AD		 1218 adapter->flags |= IGB_FLAG_NEED_CTX_IDX;
1219 break;
bbd98fe4 1220 case e1000_82576:
7dfc16fa
AD		 1221 default:
1222 break;
1223 }
1224
9d5c8243
AK		 1225 hw->phy.autoneg_wait_to_complete = false;
1226 hw->mac.adaptive_ifs = true;
1227
1228 /* Copper options */
1229 if (hw->phy.media_type == e1000_media_type_copper) {
1230 hw->phy.mdix = AUTO_ALL_MODES;
1231 hw->phy.disable_polarity_correction = false;
1232 hw->phy.ms_type = e1000_ms_hw_default;
1233 }
1234
1235 if (igb_check_reset_block(hw))
1236 dev_info(&pdev->dev,
1237 "PHY reset is blocked due to SOL/IDER session.\n");
1238
1239 netdev->features = NETIF_F_SG |
7d8eb29e 1240 NETIF_F_IP_CSUM |
9d5c8243
AK		 1241 NETIF_F_HW_VLAN_TX |
1242 NETIF_F_HW_VLAN_RX |
1243 NETIF_F_HW_VLAN_FILTER;
1244
7d8eb29e 1245 netdev->features |= NETIF_F_IPV6_CSUM;
9d5c8243 1246 netdev->features |= NETIF_F_TSO;
9d5c8243 1247 netdev->features |= NETIF_F_TSO6;
48f29ffc 1248
d3352520 1249#ifdef CONFIG_IGB_LRO
5c0999b7 1250 netdev->features |= NETIF_F_GRO;
d3352520
AD		 1251#endif
1252
48f29ffc
JK		 1253 netdev->vlan_features |= NETIF_F_TSO;
1254 netdev->vlan_features |= NETIF_F_TSO6;
7d8eb29e 1255 netdev->vlan_features |= NETIF_F_IP_CSUM;
48f29ffc
JK		 1256 netdev->vlan_features |= NETIF_F_SG;
1257
9d5c8243
AK		 1258 if (pci_using_dac)
1259 netdev->features |= NETIF_F_HIGHDMA;
1260
9d5c8243
AK		 1261 adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1262
1263 /* before reading the NVM, reset the controller to put the device in a
1264 * known good starting state */
1265 hw->mac.ops.reset_hw(hw);
1266
1267 /* make sure the NVM is good */
1268 if (igb_validate_nvm_checksum(hw) < 0) {
1269 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1270 err = -EIO;
1271 goto err_eeprom;
1272 }
1273
1274 /* copy the MAC address out of the NVM */
1275 if (hw->mac.ops.read_mac_addr(hw))
1276 dev_err(&pdev->dev, "NVM Read Error\n");
1277
1278 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1279 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1280
1281 if (!is_valid_ether_addr(netdev->perm_addr)) {
1282 dev_err(&pdev->dev, "Invalid MAC Address\n");
1283 err = -EIO;
1284 goto err_eeprom;
1285 }
1286
1287 init_timer(&adapter->watchdog_timer);
1288 adapter->watchdog_timer.function = &igb_watchdog;
1289 adapter->watchdog_timer.data = (unsigned long) adapter;
1290
1291 init_timer(&adapter->phy_info_timer);
1292 adapter->phy_info_timer.function = &igb_update_phy_info;
1293 adapter->phy_info_timer.data = (unsigned long) adapter;
1294
1295 INIT_WORK(&adapter->reset_task, igb_reset_task);
1296 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1297
450c87c8 1298 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 1299 adapter->fc_autoneg = true;
1300 hw->mac.autoneg = true;
1301 hw->phy.autoneg_advertised = 0x2f;
1302
1303 hw->fc.original_type = e1000_fc_default;
1304 hw->fc.type = e1000_fc_default;
1305
1306 adapter->itr_setting = 3;
1307 adapter->itr = IGB_START_ITR;
1308
1309 igb_validate_mdi_setting(hw);
1310
1311 adapter->rx_csum = 1;
1312
1313 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1314 * enable the ACPI Magic Packet filter
1315 */
1316
1317 if (hw->bus.func == 0 ||
1318 hw->device_id == E1000_DEV_ID_82575EB_COPPER)
312c75ae 1319 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
9d5c8243
AK		 1320
1321 if (eeprom_data & eeprom_apme_mask)
1322 adapter->eeprom_wol |= E1000_WUFC_MAG;
1323
1324 /* now that we have the eeprom settings, apply the special cases where
1325 * the eeprom may be wrong or the board simply won't support wake on
1326 * lan on a particular port */
1327 switch (pdev->device) {
1328 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1329 adapter->eeprom_wol = 0;
1330 break;
1331 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 1332 case E1000_DEV_ID_82576_FIBER:
1333 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 1334 /* Wake events only supported on port A for dual fiber
1335 * regardless of eeprom setting */
1336 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1337 adapter->eeprom_wol = 0;
1338 break;
1339 }
1340
1341 /* initialize the wol settings based on the eeprom settings */
1342 adapter->wol = adapter->eeprom_wol;
e1b86d84 1343 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
9d5c8243
AK		 1344
1345 /* reset the hardware with the new settings */
1346 igb_reset(adapter);
1347
1348 /* let the f/w know that the h/w is now under the control of the
1349 * driver. */
1350 igb_get_hw_control(adapter);
1351
1352 /* tell the stack to leave us alone until igb_open() is called */
1353 netif_carrier_off(netdev);
fd2ea0a7 1354 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1355
1356 strcpy(netdev->name, "eth%d");
1357 err = register_netdev(netdev);
1358 if (err)
1359 goto err_register;
1360
421e02f0 1361#ifdef CONFIG_IGB_DCA
bbd98fe4 1362 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 1363 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 1364 dev_info(&pdev->dev, "DCA enabled\n");
1365 /* Always use CB2 mode, difference is masked
1366 * in the CB driver. */
1367 wr32(E1000_DCA_CTRL, 2);
1368 igb_setup_dca(adapter);
1369 }
1370#endif
1371
38c845c7
PO		 1372 /*
1373 * Initialize hardware timer: we keep it running just in case
1374 * that some program needs it later on.
1375 */
1376 memset(&adapter->cycles, 0, sizeof(adapter->cycles));
1377 adapter->cycles.read = igb_read_clock;
1378 adapter->cycles.mask = CLOCKSOURCE_MASK(64);
1379 adapter->cycles.mult = 1;
1380 adapter->cycles.shift = IGB_TSYNC_SHIFT;
1381 wr32(E1000_TIMINCA,
1382 (1<<24) |
1383 IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS * IGB_TSYNC_SCALE);
1384#if 0
1385 /*
1386 * Avoid rollover while we initialize by resetting the time counter.
1387 */
1388 wr32(E1000_SYSTIML, 0x00000000);
1389 wr32(E1000_SYSTIMH, 0x00000000);
1390#else
1391 /*
1392 * Set registers so that rollover occurs soon to test this.
1393 */
1394 wr32(E1000_SYSTIML, 0x00000000);
1395 wr32(E1000_SYSTIMH, 0xFF800000);
1396#endif
1397 wrfl();
1398 timecounter_init(&adapter->clock,
1399 &adapter->cycles,
1400 ktime_to_ns(ktime_get_real()));
1401
1402#ifdef DEBUG
1403 {
1404 char buffer[160];
1405 printk(KERN_DEBUG
1406 "igb: %s: hw %p initialized timer\n",
1407 igb_get_time_str(adapter, buffer),
1408 &adapter->hw);
1409 }
1410#endif
1411
9d5c8243
AK		 1412 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1413 /* print bus type/speed/width info */
7c510e4b 1414 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
9d5c8243
AK		 1415 netdev->name,
1416 ((hw->bus.speed == e1000_bus_speed_2500)
1417 ? "2.5Gb/s" : "unknown"),
1418 ((hw->bus.width == e1000_bus_width_pcie_x4)
1419 ? "Width x4" : (hw->bus.width == e1000_bus_width_pcie_x1)
1420 ? "Width x1" : "unknown"),
7c510e4b 1421 netdev->dev_addr);
9d5c8243
AK		 1422
1423 igb_read_part_num(hw, &part_num);
1424 dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1425 (part_num >> 8), (part_num & 0xff));
1426
1427 dev_info(&pdev->dev,
1428 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1429 adapter->msix_entries ? "MSI-X" :
7dfc16fa 1430 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243
AK		 1431 adapter->num_rx_queues, adapter->num_tx_queues);
1432
9d5c8243
AK		 1433 return 0;
1434
1435err_register:
1436 igb_release_hw_control(adapter);
1437err_eeprom:
1438 if (!igb_check_reset_block(hw))
f5f4cf08 1439 igb_reset_phy(hw);
9d5c8243
AK		 1440
1441 if (hw->flash_address)
1442 iounmap(hw->flash_address);
1443
a88f10ec 1444 igb_free_queues(adapter);
9d5c8243 1445err_sw_init:
9d5c8243
AK		 1446 iounmap(hw->hw_addr);
1447err_ioremap:
1448 free_netdev(netdev);
1449err_alloc_etherdev:
aed5dec3
AD		 1450 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1451 IORESOURCE_MEM));
9d5c8243
AK		 1452err_pci_reg:
1453err_dma:
1454 pci_disable_device(pdev);
1455 return err;
1456}
1457
1458/**
1459 * igb_remove - Device Removal Routine
1460 * @pdev: PCI device information struct
1461 *
1462 * igb_remove is called by the PCI subsystem to alert the driver
1463 * that it should release a PCI device. The could be caused by a
1464 * Hot-Plug event, or because the driver is going to be removed from
1465 * memory.
1466 **/
1467static void __devexit igb_remove(struct pci_dev *pdev)
1468{
1469 struct net_device *netdev = pci_get_drvdata(pdev);
1470 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 1471 struct e1000_hw *hw = &adapter->hw;
ea943d41 1472 int err;
9d5c8243
AK		 1473
1474 /* flush_scheduled work may reschedule our watchdog task, so
1475 * explicitly disable watchdog tasks from being rescheduled */
1476 set_bit(__IGB_DOWN, &adapter->state);
1477 del_timer_sync(&adapter->watchdog_timer);
1478 del_timer_sync(&adapter->phy_info_timer);
1479
1480 flush_scheduled_work();
1481
421e02f0 1482#ifdef CONFIG_IGB_DCA
7dfc16fa 1483 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 1484 dev_info(&pdev->dev, "DCA disabled\n");
1485 dca_remove_requester(&pdev->dev);
7dfc16fa 1486 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 1487 wr32(E1000_DCA_CTRL, 1);
1488 }
1489#endif
1490
9d5c8243
AK		 1491 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1492 * would have already happened in close and is redundant. */
1493 igb_release_hw_control(adapter);
1494
1495 unregister_netdev(netdev);
1496
f5f4cf08
AD		 1497 if (!igb_check_reset_block(&adapter->hw))
1498 igb_reset_phy(&adapter->hw);
9d5c8243 1499
9d5c8243
AK		 1500 igb_reset_interrupt_capability(adapter);
1501
a88f10ec 1502 igb_free_queues(adapter);
9d5c8243 1503
28b0759c
AD		 1504 iounmap(hw->hw_addr);
1505 if (hw->flash_address)
1506 iounmap(hw->flash_address);
aed5dec3
AD		 1507 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1508 IORESOURCE_MEM));
9d5c8243
AK		 1509
1510 free_netdev(netdev);
1511
ea943d41
JK		 1512 err = pci_disable_pcie_error_reporting(pdev);
1513 if (err)
1514 dev_err(&pdev->dev,
1515 "pci_disable_pcie_error_reporting failed 0x%x\n", err);
40a914fa 1516
9d5c8243
AK		 1517 pci_disable_device(pdev);
1518}
1519
1520/**
1521 * igb_sw_init - Initialize general software structures (struct igb_adapter)
1522 * @adapter: board private structure to initialize
1523 *
1524 * igb_sw_init initializes the Adapter private data structure.
1525 * Fields are initialized based on PCI device information and
1526 * OS network device settings (MTU size).
1527 **/
1528static int __devinit igb_sw_init(struct igb_adapter *adapter)
1529{
1530 struct e1000_hw *hw = &adapter->hw;
1531 struct net_device *netdev = adapter->netdev;
1532 struct pci_dev *pdev = adapter->pdev;
1533
1534 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1535
68fd9910
AD		 1536 adapter->tx_ring_count = IGB_DEFAULT_TXD;
1537 adapter->rx_ring_count = IGB_DEFAULT_RXD;
9d5c8243
AK		 1538 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1539 adapter->rx_ps_hdr_size = 0; /* disable packet split */
1540 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1541 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1542
661086df
PWJ		 1543 /* This call may decrease the number of queues depending on
1544 * interrupt mode. */
9d5c8243
AK		 1545 igb_set_interrupt_capability(adapter);
1546
1547 if (igb_alloc_queues(adapter)) {
1548 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1549 return -ENOMEM;
1550 }
1551
1552 /* Explicitly disable IRQ since the NIC can be in any state. */
1553 igb_irq_disable(adapter);
1554
1555 set_bit(__IGB_DOWN, &adapter->state);
1556 return 0;
1557}
1558
1559/**
1560 * igb_open - Called when a network interface is made active
1561 * @netdev: network interface device structure
1562 *
1563 * Returns 0 on success, negative value on failure
1564 *
1565 * The open entry point is called when a network interface is made
1566 * active by the system (IFF_UP). At this point all resources needed
1567 * for transmit and receive operations are allocated, the interrupt
1568 * handler is registered with the OS, the watchdog timer is started,
1569 * and the stack is notified that the interface is ready.
1570 **/
1571static int igb_open(struct net_device *netdev)
1572{
1573 struct igb_adapter *adapter = netdev_priv(netdev);
1574 struct e1000_hw *hw = &adapter->hw;
1575 int err;
1576 int i;
1577
1578 /* disallow open during test */
1579 if (test_bit(__IGB_TESTING, &adapter->state))
1580 return -EBUSY;
1581
1582 /* allocate transmit descriptors */
1583 err = igb_setup_all_tx_resources(adapter);
1584 if (err)
1585 goto err_setup_tx;
1586
1587 /* allocate receive descriptors */
1588 err = igb_setup_all_rx_resources(adapter);
1589 if (err)
1590 goto err_setup_rx;
1591
1592 /* e1000_power_up_phy(adapter); */
1593
1594 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1595 if ((adapter->hw.mng_cookie.status &
1596 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1597 igb_update_mng_vlan(adapter);
1598
1599 /* before we allocate an interrupt, we must be ready to handle it.
1600 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1601 * as soon as we call pci_request_irq, so we have to setup our
1602 * clean_rx handler before we do so. */
1603 igb_configure(adapter);
1604
1605 err = igb_request_irq(adapter);
1606 if (err)
1607 goto err_req_irq;
1608
1609 /* From here on the code is the same as igb_up() */
1610 clear_bit(__IGB_DOWN, &adapter->state);
1611
844290e5
PW		 1612 for (i = 0; i < adapter->num_rx_queues; i++)
1613 napi_enable(&adapter->rx_ring[i].napi);
9d5c8243
AK		 1614
1615 /* Clear any pending interrupts. */
1616 rd32(E1000_ICR);
844290e5
PW		 1617
1618 igb_irq_enable(adapter);
1619
d55b53ff
JK		 1620 netif_tx_start_all_queues(netdev);
1621
9d5c8243
AK		 1622 /* Fire a link status change interrupt to start the watchdog. */
1623 wr32(E1000_ICS, E1000_ICS_LSC);
1624
1625 return 0;
1626
1627err_req_irq:
1628 igb_release_hw_control(adapter);
1629 /* e1000_power_down_phy(adapter); */
1630 igb_free_all_rx_resources(adapter);
1631err_setup_rx:
1632 igb_free_all_tx_resources(adapter);
1633err_setup_tx:
1634 igb_reset(adapter);
1635
1636 return err;
1637}
1638
1639/**
1640 * igb_close - Disables a network interface
1641 * @netdev: network interface device structure
1642 *
1643 * Returns 0, this is not allowed to fail
1644 *
1645 * The close entry point is called when an interface is de-activated
1646 * by the OS. The hardware is still under the driver's control, but
1647 * needs to be disabled. A global MAC reset is issued to stop the
1648 * hardware, and all transmit and receive resources are freed.
1649 **/
1650static int igb_close(struct net_device *netdev)
1651{
1652 struct igb_adapter *adapter = netdev_priv(netdev);
1653
1654 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1655 igb_down(adapter);
1656
1657 igb_free_irq(adapter);
1658
1659 igb_free_all_tx_resources(adapter);
1660 igb_free_all_rx_resources(adapter);
1661
1662 /* kill manageability vlan ID if supported, but not if a vlan with
1663 * the same ID is registered on the host OS (let 8021q kill it) */
1664 if ((adapter->hw.mng_cookie.status &
1665 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1666 !(adapter->vlgrp &&
1667 vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1668 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1669
1670 return 0;
1671}
1672
1673/**
1674 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
1675 * @adapter: board private structure
1676 * @tx_ring: tx descriptor ring (for a specific queue) to setup
1677 *
1678 * Return 0 on success, negative on failure
1679 **/
1680
1681int igb_setup_tx_resources(struct igb_adapter *adapter,
1682 struct igb_ring *tx_ring)
1683{
1684 struct pci_dev *pdev = adapter->pdev;
1685 int size;
1686
1687 size = sizeof(struct igb_buffer) * tx_ring->count;
1688 tx_ring->buffer_info = vmalloc(size);
1689 if (!tx_ring->buffer_info)
1690 goto err;
1691 memset(tx_ring->buffer_info, 0, size);
1692
1693 /* round up to nearest 4K */
0e014cb1 1694 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
9d5c8243
AK		 1695 tx_ring->size = ALIGN(tx_ring->size, 4096);
1696
1697 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1698 &tx_ring->dma);
1699
1700 if (!tx_ring->desc)
1701 goto err;
1702
1703 tx_ring->adapter = adapter;
1704 tx_ring->next_to_use = 0;
1705 tx_ring->next_to_clean = 0;
9d5c8243
AK		 1706 return 0;
1707
1708err:
1709 vfree(tx_ring->buffer_info);
1710 dev_err(&adapter->pdev->dev,
1711 "Unable to allocate memory for the transmit descriptor ring\n");
1712 return -ENOMEM;
1713}
1714
1715/**
1716 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1717 * (Descriptors) for all queues
1718 * @adapter: board private structure
1719 *
1720 * Return 0 on success, negative on failure
1721 **/
1722static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1723{
1724 int i, err = 0;
661086df 1725 int r_idx;
9d5c8243
AK		 1726
1727 for (i = 0; i < adapter->num_tx_queues; i++) {
1728 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1729 if (err) {
1730 dev_err(&adapter->pdev->dev,
1731 "Allocation for Tx Queue %u failed\n", i);
1732 for (i--; i >= 0; i--)
3b644cf6 1733 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 1734 break;
1735 }
1736 }
1737
661086df
PWJ		 1738 for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
1739 r_idx = i % adapter->num_tx_queues;
1740 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
eebbbdba 1741 }
9d5c8243
AK		 1742 return err;
1743}
1744
1745/**
1746 * igb_configure_tx - Configure transmit Unit after Reset
1747 * @adapter: board private structure
1748 *
1749 * Configure the Tx unit of the MAC after a reset.
1750 **/
1751static void igb_configure_tx(struct igb_adapter *adapter)
1752{
0e014cb1 1753 u64 tdba;
9d5c8243
AK		 1754 struct e1000_hw *hw = &adapter->hw;
1755 u32 tctl;
1756 u32 txdctl, txctrl;
26bc19ec 1757 int i, j;
9d5c8243
AK		 1758
1759 for (i = 0; i < adapter->num_tx_queues; i++) {
1760 struct igb_ring *ring = &(adapter->tx_ring[i]);
26bc19ec
AD		 1761 j = ring->reg_idx;
1762 wr32(E1000_TDLEN(j),
9d5c8243
AK		 1763 ring->count * sizeof(struct e1000_tx_desc));
1764 tdba = ring->dma;
26bc19ec 1765 wr32(E1000_TDBAL(j),
9d5c8243 1766 tdba & 0x00000000ffffffffULL);
26bc19ec 1767 wr32(E1000_TDBAH(j), tdba >> 32);
9d5c8243 1768
26bc19ec
AD		 1769 ring->head = E1000_TDH(j);
1770 ring->tail = E1000_TDT(j);
9d5c8243
AK		 1771 writel(0, hw->hw_addr + ring->tail);
1772 writel(0, hw->hw_addr + ring->head);
26bc19ec 1773 txdctl = rd32(E1000_TXDCTL(j));
9d5c8243 1774 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
26bc19ec 1775 wr32(E1000_TXDCTL(j), txdctl);
9d5c8243
AK		 1776
1777 /* Turn off Relaxed Ordering on head write-backs. The
1778 * writebacks MUST be delivered in order or it will
1779 * completely screw up our bookeeping.
1780 */
26bc19ec 1781 txctrl = rd32(E1000_DCA_TXCTRL(j));
9d5c8243 1782 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
26bc19ec 1783 wr32(E1000_DCA_TXCTRL(j), txctrl);
9d5c8243
AK		 1784 }
1785
1786
1787
1788 /* Use the default values for the Tx Inter Packet Gap (IPG) timer */
1789
1790 /* Program the Transmit Control Register */
1791
1792 tctl = rd32(E1000_TCTL);
1793 tctl &= ~E1000_TCTL_CT;
1794 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1795 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1796
1797 igb_config_collision_dist(hw);
1798
1799 /* Setup Transmit Descriptor Settings for eop descriptor */
1800 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
1801
1802 /* Enable transmits */
1803 tctl |= E1000_TCTL_EN;
1804
1805 wr32(E1000_TCTL, tctl);
1806}
1807
1808/**
1809 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
1810 * @adapter: board private structure
1811 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1812 *
1813 * Returns 0 on success, negative on failure
1814 **/
1815
1816int igb_setup_rx_resources(struct igb_adapter *adapter,
1817 struct igb_ring *rx_ring)
1818{
1819 struct pci_dev *pdev = adapter->pdev;
1820 int size, desc_len;
1821
1822 size = sizeof(struct igb_buffer) * rx_ring->count;
1823 rx_ring->buffer_info = vmalloc(size);
1824 if (!rx_ring->buffer_info)
1825 goto err;
1826 memset(rx_ring->buffer_info, 0, size);
1827
1828 desc_len = sizeof(union e1000_adv_rx_desc);
1829
1830 /* Round up to nearest 4K */
1831 rx_ring->size = rx_ring->count * desc_len;
1832 rx_ring->size = ALIGN(rx_ring->size, 4096);
1833
1834 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1835 &rx_ring->dma);
1836
1837 if (!rx_ring->desc)
1838 goto err;
1839
1840 rx_ring->next_to_clean = 0;
1841 rx_ring->next_to_use = 0;
9d5c8243
AK		 1842
1843 rx_ring->adapter = adapter;
9d5c8243
AK		 1844
1845 return 0;
1846
1847err:
1848 vfree(rx_ring->buffer_info);
1849 dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
1850 "the receive descriptor ring\n");
1851 return -ENOMEM;
1852}
1853
1854/**
1855 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
1856 * (Descriptors) for all queues
1857 * @adapter: board private structure
1858 *
1859 * Return 0 on success, negative on failure
1860 **/
1861static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
1862{
1863 int i, err = 0;
1864
1865 for (i = 0; i < adapter->num_rx_queues; i++) {
1866 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1867 if (err) {
1868 dev_err(&adapter->pdev->dev,
1869 "Allocation for Rx Queue %u failed\n", i);
1870 for (i--; i >= 0; i--)
3b644cf6 1871 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 1872 break;
1873 }
1874 }
1875
1876 return err;
1877}
1878
1879/**
1880 * igb_setup_rctl - configure the receive control registers
1881 * @adapter: Board private structure
1882 **/
1883static void igb_setup_rctl(struct igb_adapter *adapter)
1884{
1885 struct e1000_hw *hw = &adapter->hw;
1886 u32 rctl;
1887 u32 srrctl = 0;
26bc19ec 1888 int i, j;
9d5c8243
AK		 1889
1890 rctl = rd32(E1000_RCTL);
1891
1892 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 1893 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 1894
69d728ba 1895 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 1896 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 1897
87cb7e8c
AK		 1898 /*
1899 * enable stripping of CRC. It's unlikely this will break BMC
1900 * redirection as it did with e1000. Newer features require
1901 * that the HW strips the CRC.
9d5c8243 1902 */
87cb7e8c 1903 rctl |= E1000_RCTL_SECRC;
9d5c8243 1904
9b07f3d3 1905 /*
ec54d7d6 1906 * disable store bad packets and clear size bits.
9b07f3d3 1907 */
ec54d7d6 1908 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 1909
ec54d7d6 1910 /* enable LPE when to prevent packets larger than max_frame_size */
9b07f3d3 1911 rctl |= E1000_RCTL_LPE;
b4557be2
AD		 1912
1913 /* Setup buffer sizes */
1914 switch (adapter->rx_buffer_len) {
1915 case IGB_RXBUFFER_256:
1916 rctl |= E1000_RCTL_SZ_256;
1917 break;
1918 case IGB_RXBUFFER_512:
1919 rctl |= E1000_RCTL_SZ_512;
1920 break;
1921 default:
1922 srrctl = ALIGN(adapter->rx_buffer_len, 1024)
1923 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1924 break;
9d5c8243
AK		 1925 }
1926
1927 /* 82575 and greater support packet-split where the protocol
1928 * header is placed in skb->data and the packet data is
1929 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
1930 * In the case of a non-split, skb->data is linearly filled,
1931 * followed by the page buffers. Therefore, skb->data is
1932 * sized to hold the largest protocol header.
1933 */
1934 /* allocations using alloc_page take too long for regular MTU
1935 * so only enable packet split for jumbo frames */
ec54d7d6 1936 if (adapter->netdev->mtu > ETH_DATA_LEN) {
9d5c8243 1937 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
bf36c1a0 1938 srrctl |= adapter->rx_ps_hdr_size <<
9d5c8243 1939 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
9d5c8243
AK		 1940 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1941 } else {
1942 adapter->rx_ps_hdr_size = 0;
1943 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
1944 }
1945
26bc19ec
AD		 1946 for (i = 0; i < adapter->num_rx_queues; i++) {
1947 j = adapter->rx_ring[i].reg_idx;
1948 wr32(E1000_SRRCTL(j), srrctl);
1949 }
9d5c8243
AK		 1950
1951 wr32(E1000_RCTL, rctl);
1952}
1953
1954/**
1955 * igb_configure_rx - Configure receive Unit after Reset
1956 * @adapter: board private structure
1957 *
1958 * Configure the Rx unit of the MAC after a reset.
1959 **/
1960static void igb_configure_rx(struct igb_adapter *adapter)
1961{
1962 u64 rdba;
1963 struct e1000_hw *hw = &adapter->hw;
1964 u32 rctl, rxcsum;
1965 u32 rxdctl;
26bc19ec 1966 int i, j;
9d5c8243
AK		 1967
1968 /* disable receives while setting up the descriptors */
1969 rctl = rd32(E1000_RCTL);
1970 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1971 wrfl();
1972 mdelay(10);
1973
1974 if (adapter->itr_setting > 3)
6eb5a7f1 1975 wr32(E1000_ITR, adapter->itr);
9d5c8243
AK		 1976
1977 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1978 * the Base and Length of the Rx Descriptor Ring */
1979 for (i = 0; i < adapter->num_rx_queues; i++) {
1980 struct igb_ring *ring = &(adapter->rx_ring[i]);
26bc19ec 1981 j = ring->reg_idx;
9d5c8243 1982 rdba = ring->dma;
26bc19ec 1983 wr32(E1000_RDBAL(j),
9d5c8243 1984 rdba & 0x00000000ffffffffULL);
26bc19ec
AD		 1985 wr32(E1000_RDBAH(j), rdba >> 32);
1986 wr32(E1000_RDLEN(j),
9d5c8243
AK		 1987 ring->count * sizeof(union e1000_adv_rx_desc));
1988
26bc19ec
AD		 1989 ring->head = E1000_RDH(j);
1990 ring->tail = E1000_RDT(j);
9d5c8243
AK		 1991 writel(0, hw->hw_addr + ring->tail);
1992 writel(0, hw->hw_addr + ring->head);
1993
26bc19ec 1994 rxdctl = rd32(E1000_RXDCTL(j));
9d5c8243
AK		 1995 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
1996 rxdctl &= 0xFFF00000;
1997 rxdctl |= IGB_RX_PTHRESH;
1998 rxdctl |= IGB_RX_HTHRESH << 8;
1999 rxdctl |= IGB_RX_WTHRESH << 16;
26bc19ec 2000 wr32(E1000_RXDCTL(j), rxdctl);
9d5c8243
AK		 2001 }
2002
2003 if (adapter->num_rx_queues > 1) {
2004 u32 random[10];
2005 u32 mrqc;
2006 u32 j, shift;
2007 union e1000_reta {
2008 u32 dword;
2009 u8 bytes[4];
2010 } reta;
2011
2012 get_random_bytes(&random[0], 40);
2013
2d064c06
AD		 2014 if (hw->mac.type >= e1000_82576)
2015 shift = 0;
2016 else
2017 shift = 6;
9d5c8243
AK		 2018 for (j = 0; j < (32 * 4); j++) {
2019 reta.bytes[j & 3] =
26bc19ec 2020 adapter->rx_ring[(j % adapter->num_rx_queues)].reg_idx << shift;
9d5c8243
AK		 2021 if ((j & 3) == 3)
2022 writel(reta.dword,
2023 hw->hw_addr + E1000_RETA(0) + (j & ~3));
2024 }
2025 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
2026
2027 /* Fill out hash function seeds */
2028 for (j = 0; j < 10; j++)
2029 array_wr32(E1000_RSSRK(0), j, random[j]);
2030
2031 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2032 E1000_MRQC_RSS_FIELD_IPV4_TCP);
2033 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2034 E1000_MRQC_RSS_FIELD_IPV6_TCP);
2035 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
2036 E1000_MRQC_RSS_FIELD_IPV6_UDP);
2037 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2038 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2039
2040
2041 wr32(E1000_MRQC, mrqc);
2042
2043 /* Multiqueue and raw packet checksumming are mutually
2044 * exclusive. Note that this not the same as TCP/IP
2045 * checksumming, which works fine. */
2046 rxcsum = rd32(E1000_RXCSUM);
2047 rxcsum |= E1000_RXCSUM_PCSD;
2048 wr32(E1000_RXCSUM, rxcsum);
2049 } else {
2050 /* Enable Receive Checksum Offload for TCP and UDP */
2051 rxcsum = rd32(E1000_RXCSUM);
2052 if (adapter->rx_csum) {
2053 rxcsum |= E1000_RXCSUM_TUOFL;
2054
2055 /* Enable IPv4 payload checksum for UDP fragments
2056 * Must be used in conjunction with packet-split. */
2057 if (adapter->rx_ps_hdr_size)
2058 rxcsum |= E1000_RXCSUM_IPPCSE;
2059 } else {
2060 rxcsum &= ~E1000_RXCSUM_TUOFL;
2061 /* don't need to clear IPPCSE as it defaults to 0 */
2062 }
2063 wr32(E1000_RXCSUM, rxcsum);
2064 }
2065
2066 if (adapter->vlgrp)
2067 wr32(E1000_RLPML,
2068 adapter->max_frame_size + VLAN_TAG_SIZE);
2069 else
2070 wr32(E1000_RLPML, adapter->max_frame_size);
2071
2072 /* Enable Receives */
2073 wr32(E1000_RCTL, rctl);
2074}
2075
2076/**
2077 * igb_free_tx_resources - Free Tx Resources per Queue
9d5c8243
AK		 2078 * @tx_ring: Tx descriptor ring for a specific queue
2079 *
2080 * Free all transmit software resources
2081 **/
68fd9910 2082void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 2083{
3b644cf6 2084 struct pci_dev *pdev = tx_ring->adapter->pdev;
9d5c8243 2085
3b644cf6 2086 igb_clean_tx_ring(tx_ring);
9d5c8243
AK		 2087
2088 vfree(tx_ring->buffer_info);
2089 tx_ring->buffer_info = NULL;
2090
2091 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
2092
2093 tx_ring->desc = NULL;
2094}
2095
2096/**
2097 * igb_free_all_tx_resources - Free Tx Resources for All Queues
2098 * @adapter: board private structure
2099 *
2100 * Free all transmit software resources
2101 **/
2102static void igb_free_all_tx_resources(struct igb_adapter *adapter)
2103{
2104 int i;
2105
2106 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2107 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 2108}
2109
2110static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
2111 struct igb_buffer *buffer_info)
2112{
2113 if (buffer_info->dma) {
2114 pci_unmap_page(adapter->pdev,
2115 buffer_info->dma,
2116 buffer_info->length,
2117 PCI_DMA_TODEVICE);
2118 buffer_info->dma = 0;
2119 }
2120 if (buffer_info->skb) {
2121 dev_kfree_skb_any(buffer_info->skb);
2122 buffer_info->skb = NULL;
2123 }
2124 buffer_info->time_stamp = 0;
2125 /* buffer_info must be completely set up in the transmit path */
2126}
2127
2128/**
2129 * igb_clean_tx_ring - Free Tx Buffers
9d5c8243
AK		 2130 * @tx_ring: ring to be cleaned
2131 **/
3b644cf6 2132static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 2133{
3b644cf6 2134 struct igb_adapter *adapter = tx_ring->adapter;
9d5c8243
AK		 2135 struct igb_buffer *buffer_info;
2136 unsigned long size;
2137 unsigned int i;
2138
2139 if (!tx_ring->buffer_info)
2140 return;
2141 /* Free all the Tx ring sk_buffs */
2142
2143 for (i = 0; i < tx_ring->count; i++) {
2144 buffer_info = &tx_ring->buffer_info[i];
2145 igb_unmap_and_free_tx_resource(adapter, buffer_info);
2146 }
2147
2148 size = sizeof(struct igb_buffer) * tx_ring->count;
2149 memset(tx_ring->buffer_info, 0, size);
2150
2151 /* Zero out the descriptor ring */
2152
2153 memset(tx_ring->desc, 0, tx_ring->size);
2154
2155 tx_ring->next_to_use = 0;
2156 tx_ring->next_to_clean = 0;
2157
2158 writel(0, adapter->hw.hw_addr + tx_ring->head);
2159 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2160}
2161
2162/**
2163 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2164 * @adapter: board private structure
2165 **/
2166static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2167{
2168 int i;
2169
2170 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2171 igb_clean_tx_ring(&adapter->tx_ring[i]);
9d5c8243
AK		 2172}
2173
2174/**
2175 * igb_free_rx_resources - Free Rx Resources
9d5c8243
AK		 2176 * @rx_ring: ring to clean the resources from
2177 *
2178 * Free all receive software resources
2179 **/
68fd9910 2180void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2181{
3b644cf6 2182 struct pci_dev *pdev = rx_ring->adapter->pdev;
9d5c8243 2183
3b644cf6 2184 igb_clean_rx_ring(rx_ring);
9d5c8243
AK		 2185
2186 vfree(rx_ring->buffer_info);
2187 rx_ring->buffer_info = NULL;
2188
2189 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2190
2191 rx_ring->desc = NULL;
2192}
2193
2194/**
2195 * igb_free_all_rx_resources - Free Rx Resources for All Queues
2196 * @adapter: board private structure
2197 *
2198 * Free all receive software resources
2199 **/
2200static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2201{
2202 int i;
2203
2204 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2205 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 2206}
2207
2208/**
2209 * igb_clean_rx_ring - Free Rx Buffers per Queue
9d5c8243
AK		 2210 * @rx_ring: ring to free buffers from
2211 **/
3b644cf6 2212static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 2213{
3b644cf6 2214 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 2215 struct igb_buffer *buffer_info;
2216 struct pci_dev *pdev = adapter->pdev;
2217 unsigned long size;
2218 unsigned int i;
2219
2220 if (!rx_ring->buffer_info)
2221 return;
2222 /* Free all the Rx ring sk_buffs */
2223 for (i = 0; i < rx_ring->count; i++) {
2224 buffer_info = &rx_ring->buffer_info[i];
2225 if (buffer_info->dma) {
2226 if (adapter->rx_ps_hdr_size)
2227 pci_unmap_single(pdev, buffer_info->dma,
2228 adapter->rx_ps_hdr_size,
2229 PCI_DMA_FROMDEVICE);
2230 else
2231 pci_unmap_single(pdev, buffer_info->dma,
2232 adapter->rx_buffer_len,
2233 PCI_DMA_FROMDEVICE);
2234 buffer_info->dma = 0;
2235 }
2236
2237 if (buffer_info->skb) {
2238 dev_kfree_skb(buffer_info->skb);
2239 buffer_info->skb = NULL;
2240 }
2241 if (buffer_info->page) {
bf36c1a0
AD		 2242 if (buffer_info->page_dma)
2243 pci_unmap_page(pdev, buffer_info->page_dma,
2244 PAGE_SIZE / 2,
2245 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 2246 put_page(buffer_info->page);
2247 buffer_info->page = NULL;
2248 buffer_info->page_dma = 0;
bf36c1a0 2249 buffer_info->page_offset = 0;
9d5c8243
AK		 2250 }
2251 }
2252
9d5c8243
AK		 2253 size = sizeof(struct igb_buffer) * rx_ring->count;
2254 memset(rx_ring->buffer_info, 0, size);
2255
2256 /* Zero out the descriptor ring */
2257 memset(rx_ring->desc, 0, rx_ring->size);
2258
2259 rx_ring->next_to_clean = 0;
2260 rx_ring->next_to_use = 0;
2261
2262 writel(0, adapter->hw.hw_addr + rx_ring->head);
2263 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2264}
2265
2266/**
2267 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2268 * @adapter: board private structure
2269 **/
2270static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2271{
2272 int i;
2273
2274 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2275 igb_clean_rx_ring(&adapter->rx_ring[i]);
9d5c8243
AK		 2276}
2277
2278/**
2279 * igb_set_mac - Change the Ethernet Address of the NIC
2280 * @netdev: network interface device structure
2281 * @p: pointer to an address structure
2282 *
2283 * Returns 0 on success, negative on failure
2284 **/
2285static int igb_set_mac(struct net_device *netdev, void *p)
2286{
2287 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 2288 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 2289 struct sockaddr *addr = p;
2290
2291 if (!is_valid_ether_addr(addr->sa_data))
2292 return -EADDRNOTAVAIL;
2293
2294 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 2295 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 2296
28b0759c 2297 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
9d5c8243
AK		 2298
2299 return 0;
2300}
2301
2302/**
2303 * igb_set_multi - Multicast and Promiscuous mode set
2304 * @netdev: network interface device structure
2305 *
2306 * The set_multi entry point is called whenever the multicast address
2307 * list or the network interface flags are updated. This routine is
2308 * responsible for configuring the hardware for proper multicast,
2309 * promiscuous mode, and all-multi behavior.
2310 **/
2311static void igb_set_multi(struct net_device *netdev)
2312{
2313 struct igb_adapter *adapter = netdev_priv(netdev);
2314 struct e1000_hw *hw = &adapter->hw;
2315 struct e1000_mac_info *mac = &hw->mac;
2316 struct dev_mc_list *mc_ptr;
2317 u8 *mta_list;
2318 u32 rctl;
2319 int i;
2320
2321 /* Check for Promiscuous and All Multicast modes */
2322
2323 rctl = rd32(E1000_RCTL);
2324
746b9f02 2325 if (netdev->flags & IFF_PROMISC) {
9d5c8243 2326 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
746b9f02
PM		 2327 rctl &= ~E1000_RCTL_VFE;
2328 } else {
2329 if (netdev->flags & IFF_ALLMULTI) {
2330 rctl |= E1000_RCTL_MPE;
2331 rctl &= ~E1000_RCTL_UPE;
2332 } else
2333 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
78ed11a5 2334 rctl |= E1000_RCTL_VFE;
746b9f02 2335 }
9d5c8243
AK		 2336 wr32(E1000_RCTL, rctl);
2337
2338 if (!netdev->mc_count) {
2339 /* nothing to program, so clear mc list */
8a900862
AD		 2340 igb_update_mc_addr_list(hw, NULL, 0, 1,
2341 mac->rar_entry_count);
9d5c8243
AK		 2342 return;
2343 }
2344
2345 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2346 if (!mta_list)
2347 return;
2348
2349 /* The shared function expects a packed array of only addresses. */
2350 mc_ptr = netdev->mc_list;
2351
2352 for (i = 0; i < netdev->mc_count; i++) {
2353 if (!mc_ptr)
2354 break;
2355 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2356 mc_ptr = mc_ptr->next;
2357 }
8a900862 2358 igb_update_mc_addr_list(hw, mta_list, i, 1, mac->rar_entry_count);
9d5c8243
AK		 2359 kfree(mta_list);
2360}
2361
2362/* Need to wait a few seconds after link up to get diagnostic information from
2363 * the phy */
2364static void igb_update_phy_info(unsigned long data)
2365{
2366 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 2367 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 2368}
2369
4d6b725e
AD		 2370/**
2371 * igb_has_link - check shared code for link and determine up/down
2372 * @adapter: pointer to driver private info
2373 **/
2374static bool igb_has_link(struct igb_adapter *adapter)
2375{
2376 struct e1000_hw *hw = &adapter->hw;
2377 bool link_active = false;
2378 s32 ret_val = 0;
2379
2380 /* get_link_status is set on LSC (link status) interrupt or
2381 * rx sequence error interrupt. get_link_status will stay
2382 * false until the e1000_check_for_link establishes link
2383 * for copper adapters ONLY
2384 */
2385 switch (hw->phy.media_type) {
2386 case e1000_media_type_copper:
2387 if (hw->mac.get_link_status) {
2388 ret_val = hw->mac.ops.check_for_link(hw);
2389 link_active = !hw->mac.get_link_status;
2390 } else {
2391 link_active = true;
2392 }
2393 break;
2394 case e1000_media_type_fiber:
2395 ret_val = hw->mac.ops.check_for_link(hw);
2396 link_active = !!(rd32(E1000_STATUS) & E1000_STATUS_LU);
2397 break;
2398 case e1000_media_type_internal_serdes:
2399 ret_val = hw->mac.ops.check_for_link(hw);
2400 link_active = hw->mac.serdes_has_link;
2401 break;
2402 default:
2403 case e1000_media_type_unknown:
2404 break;
2405 }
2406
2407 return link_active;
2408}
2409
9d5c8243
AK		 2410/**
2411 * igb_watchdog - Timer Call-back
2412 * @data: pointer to adapter cast into an unsigned long
2413 **/
2414static void igb_watchdog(unsigned long data)
2415{
2416 struct igb_adapter *adapter = (struct igb_adapter *)data;
2417 /* Do the rest outside of interrupt context */
2418 schedule_work(&adapter->watchdog_task);
2419}
2420
2421static void igb_watchdog_task(struct work_struct *work)
2422{
2423 struct igb_adapter *adapter = container_of(work,
2424 struct igb_adapter, watchdog_task);
2425 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 2426 struct net_device *netdev = adapter->netdev;
2427 struct igb_ring *tx_ring = adapter->tx_ring;
9d5c8243 2428 u32 link;
7a6ea550 2429 u32 eics = 0;
7a6ea550 2430 int i;
9d5c8243 2431
4d6b725e
AD		 2432 link = igb_has_link(adapter);
2433 if ((netif_carrier_ok(netdev)) && link)
9d5c8243
AK		 2434 goto link_up;
2435
9d5c8243
AK		 2436 if (link) {
2437 if (!netif_carrier_ok(netdev)) {
2438 u32 ctrl;
2439 hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2440 &adapter->link_speed,
2441 &adapter->link_duplex);
2442
2443 ctrl = rd32(E1000_CTRL);
527d47c1
AD		 2444 /* Links status message must follow this format */
2445 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
9d5c8243 2446 "Flow Control: %s\n",
527d47c1 2447 netdev->name,
9d5c8243
AK		 2448 adapter->link_speed,
2449 adapter->link_duplex == FULL_DUPLEX ?
2450 "Full Duplex" : "Half Duplex",
2451 ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2452 E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2453 E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2454 E1000_CTRL_TFCE) ? "TX" : "None")));
2455
2456 /* tweak tx_queue_len according to speed/duplex and
2457 * adjust the timeout factor */
2458 netdev->tx_queue_len = adapter->tx_queue_len;
2459 adapter->tx_timeout_factor = 1;
2460 switch (adapter->link_speed) {
2461 case SPEED_10:
2462 netdev->tx_queue_len = 10;
2463 adapter->tx_timeout_factor = 14;
2464 break;
2465 case SPEED_100:
2466 netdev->tx_queue_len = 100;
2467 /* maybe add some timeout factor ? */
2468 break;
2469 }
2470
2471 netif_carrier_on(netdev);
fd2ea0a7 2472 netif_tx_wake_all_queues(netdev);
9d5c8243 2473
4b1a9877 2474 /* link state has changed, schedule phy info update */
9d5c8243
AK		 2475 if (!test_bit(__IGB_DOWN, &adapter->state))
2476 mod_timer(&adapter->phy_info_timer,
2477 round_jiffies(jiffies + 2 * HZ));
2478 }
2479 } else {
2480 if (netif_carrier_ok(netdev)) {
2481 adapter->link_speed = 0;
2482 adapter->link_duplex = 0;
527d47c1
AD		 2483 /* Links status message must follow this format */
2484 printk(KERN_INFO "igb: %s NIC Link is Down\n",
2485 netdev->name);
9d5c8243 2486 netif_carrier_off(netdev);
fd2ea0a7 2487 netif_tx_stop_all_queues(netdev);
4b1a9877
AD		 2488
2489 /* link state has changed, schedule phy info update */
9d5c8243
AK		 2490 if (!test_bit(__IGB_DOWN, &adapter->state))
2491 mod_timer(&adapter->phy_info_timer,
2492 round_jiffies(jiffies + 2 * HZ));
2493 }
2494 }
2495
2496link_up:
2497 igb_update_stats(adapter);
2498
4b1a9877 2499 hw->mac.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
9d5c8243 2500 adapter->tpt_old = adapter->stats.tpt;
4b1a9877 2501 hw->mac.collision_delta = adapter->stats.colc - adapter->colc_old;
9d5c8243
AK		 2502 adapter->colc_old = adapter->stats.colc;
2503
2504 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2505 adapter->gorc_old = adapter->stats.gorc;
2506 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2507 adapter->gotc_old = adapter->stats.gotc;
2508
2509 igb_update_adaptive(&adapter->hw);
2510
2511 if (!netif_carrier_ok(netdev)) {
2512 if (IGB_DESC_UNUSED(tx_ring) + 1 < tx_ring->count) {
2513 /* We've lost link, so the controller stops DMA,
2514 * but we've got queued Tx work that's never going
2515 * to get done, so reset controller to flush Tx.
2516 * (Do the reset outside of interrupt context). */
2517 adapter->tx_timeout_count++;
2518 schedule_work(&adapter->reset_task);
2519 }
2520 }
2521
2522 /* Cause software interrupt to ensure rx ring is cleaned */
7a6ea550
AD		 2523 if (adapter->msix_entries) {
2524 for (i = 0; i < adapter->num_rx_queues; i++)
2525 eics |= adapter->rx_ring[i].eims_value;
2526 wr32(E1000_EICS, eics);
2527 } else {
2528 wr32(E1000_ICS, E1000_ICS_RXDMT0);
2529 }
9d5c8243
AK		 2530
2531 /* Force detection of hung controller every watchdog period */
2532 tx_ring->detect_tx_hung = true;
2533
2534 /* Reset the timer */
2535 if (!test_bit(__IGB_DOWN, &adapter->state))
2536 mod_timer(&adapter->watchdog_timer,
2537 round_jiffies(jiffies + 2 * HZ));
2538}
2539
2540enum latency_range {
2541 lowest_latency = 0,
2542 low_latency = 1,
2543 bulk_latency = 2,
2544 latency_invalid = 255
2545};
2546
2547
6eb5a7f1
AD		 2548/**
2549 * igb_update_ring_itr - update the dynamic ITR value based on packet size
2550 *
2551 * Stores a new ITR value based on strictly on packet size. This
2552 * algorithm is less sophisticated than that used in igb_update_itr,
2553 * due to the difficulty of synchronizing statistics across multiple
2554 * receive rings. The divisors and thresholds used by this fuction
2555 * were determined based on theoretical maximum wire speed and testing
2556 * data, in order to minimize response time while increasing bulk
2557 * throughput.
2558 * This functionality is controlled by the InterruptThrottleRate module
2559 * parameter (see igb_param.c)
2560 * NOTE: This function is called only when operating in a multiqueue
2561 * receive environment.
2562 * @rx_ring: pointer to ring
2563 **/
2564static void igb_update_ring_itr(struct igb_ring *rx_ring)
9d5c8243 2565{
6eb5a7f1
AD		 2566 int new_val = rx_ring->itr_val;
2567 int avg_wire_size = 0;
2568 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 2569
6eb5a7f1
AD		 2570 if (!rx_ring->total_packets)
2571 goto clear_counts; /* no packets, so don't do anything */
9d5c8243 2572
6eb5a7f1
AD		 2573 /* For non-gigabit speeds, just fix the interrupt rate at 4000
2574 * ints/sec - ITR timer value of 120 ticks.
2575 */
2576 if (adapter->link_speed != SPEED_1000) {
2577 new_val = 120;
2578 goto set_itr_val;
9d5c8243 2579 }
6eb5a7f1 2580 avg_wire_size = rx_ring->total_bytes / rx_ring->total_packets;
9d5c8243 2581
6eb5a7f1
AD		 2582 /* Add 24 bytes to size to account for CRC, preamble, and gap */
2583 avg_wire_size += 24;
2584
2585 /* Don't starve jumbo frames */
2586 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 2587
6eb5a7f1
AD		 2588 /* Give a little boost to mid-size frames */
2589 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
2590 new_val = avg_wire_size / 3;
2591 else
2592 new_val = avg_wire_size / 2;
9d5c8243 2593
6eb5a7f1 2594set_itr_val:
9d5c8243
AK		 2595 if (new_val != rx_ring->itr_val) {
2596 rx_ring->itr_val = new_val;
6eb5a7f1 2597 rx_ring->set_itr = 1;
9d5c8243 2598 }
6eb5a7f1
AD		 2599clear_counts:
2600 rx_ring->total_bytes = 0;
2601 rx_ring->total_packets = 0;
9d5c8243
AK		 2602}
2603
2604/**
2605 * igb_update_itr - update the dynamic ITR value based on statistics
2606 * Stores a new ITR value based on packets and byte
2607 * counts during the last interrupt. The advantage of per interrupt
2608 * computation is faster updates and more accurate ITR for the current
2609 * traffic pattern. Constants in this function were computed
2610 * based on theoretical maximum wire speed and thresholds were set based
2611 * on testing data as well as attempting to minimize response time
2612 * while increasing bulk throughput.
2613 * this functionality is controlled by the InterruptThrottleRate module
2614 * parameter (see igb_param.c)
2615 * NOTE: These calculations are only valid when operating in a single-
2616 * queue environment.
2617 * @adapter: pointer to adapter
2618 * @itr_setting: current adapter->itr
2619 * @packets: the number of packets during this measurement interval
2620 * @bytes: the number of bytes during this measurement interval
2621 **/
2622static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
2623 int packets, int bytes)
2624{
2625 unsigned int retval = itr_setting;
2626
2627 if (packets == 0)
2628 goto update_itr_done;
2629
2630 switch (itr_setting) {
2631 case lowest_latency:
2632 /* handle TSO and jumbo frames */
2633 if (bytes/packets > 8000)
2634 retval = bulk_latency;
2635 else if ((packets < 5) && (bytes > 512))
2636 retval = low_latency;
2637 break;
2638 case low_latency: /* 50 usec aka 20000 ints/s */
2639 if (bytes > 10000) {
2640 /* this if handles the TSO accounting */
2641 if (bytes/packets > 8000) {
2642 retval = bulk_latency;
2643 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
2644 retval = bulk_latency;
2645 } else if ((packets > 35)) {
2646 retval = lowest_latency;
2647 }
2648 } else if (bytes/packets > 2000) {
2649 retval = bulk_latency;
2650 } else if (packets <= 2 && bytes < 512) {
2651 retval = lowest_latency;
2652 }
2653 break;
2654 case bulk_latency: /* 250 usec aka 4000 ints/s */
2655 if (bytes > 25000) {
2656 if (packets > 35)
2657 retval = low_latency;
2658 } else if (bytes < 6000) {
2659 retval = low_latency;
2660 }
2661 break;
2662 }
2663
2664update_itr_done:
2665 return retval;
2666}
2667
6eb5a7f1 2668static void igb_set_itr(struct igb_adapter *adapter)
9d5c8243
AK		 2669{
2670 u16 current_itr;
2671 u32 new_itr = adapter->itr;
2672
2673 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2674 if (adapter->link_speed != SPEED_1000) {
2675 current_itr = 0;
2676 new_itr = 4000;
2677 goto set_itr_now;
2678 }
2679
2680 adapter->rx_itr = igb_update_itr(adapter,
2681 adapter->rx_itr,
2682 adapter->rx_ring->total_packets,
2683 adapter->rx_ring->total_bytes);
9d5c8243 2684
6eb5a7f1 2685 if (adapter->rx_ring->buddy) {
9d5c8243
AK		 2686 adapter->tx_itr = igb_update_itr(adapter,
2687 adapter->tx_itr,
2688 adapter->tx_ring->total_packets,
2689 adapter->tx_ring->total_bytes);
9d5c8243
AK		 2690
2691 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2692 } else {
2693 current_itr = adapter->rx_itr;
2694 }
2695
6eb5a7f1
AD		 2696 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2697 if (adapter->itr_setting == 3 &&
2698 current_itr == lowest_latency)
2699 current_itr = low_latency;
2700
9d5c8243
AK		 2701 switch (current_itr) {
2702 /* counts and packets in update_itr are dependent on these numbers */
2703 case lowest_latency:
2704 new_itr = 70000;
2705 break;
2706 case low_latency:
2707 new_itr = 20000; /* aka hwitr = ~200 */
2708 break;
2709 case bulk_latency:
2710 new_itr = 4000;
2711 break;
2712 default:
2713 break;
2714 }
2715
2716set_itr_now:
6eb5a7f1
AD		 2717 adapter->rx_ring->total_bytes = 0;
2718 adapter->rx_ring->total_packets = 0;
2719 if (adapter->rx_ring->buddy) {
2720 adapter->rx_ring->buddy->total_bytes = 0;
2721 adapter->rx_ring->buddy->total_packets = 0;
2722 }
2723
9d5c8243
AK		 2724 if (new_itr != adapter->itr) {
2725 /* this attempts to bias the interrupt rate towards Bulk
2726 * by adding intermediate steps when interrupt rate is
2727 * increasing */
2728 new_itr = new_itr > adapter->itr ?
2729 min(adapter->itr + (new_itr >> 2), new_itr) :
2730 new_itr;
2731 /* Don't write the value here; it resets the adapter's
2732 * internal timer, and causes us to delay far longer than
2733 * we should between interrupts. Instead, we write the ITR
2734 * value at the beginning of the next interrupt so the timing
2735 * ends up being correct.
2736 */
2737 adapter->itr = new_itr;
6eb5a7f1
AD		 2738 adapter->rx_ring->itr_val = 1000000000 / (new_itr * 256);
2739 adapter->rx_ring->set_itr = 1;
9d5c8243
AK		 2740 }
2741
2742 return;
2743}
2744
2745
2746#define IGB_TX_FLAGS_CSUM 0x00000001
2747#define IGB_TX_FLAGS_VLAN 0x00000002
2748#define IGB_TX_FLAGS_TSO 0x00000004
2749#define IGB_TX_FLAGS_IPV4 0x00000008
2750#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
2751#define IGB_TX_FLAGS_VLAN_SHIFT 16
2752
2753static inline int igb_tso_adv(struct igb_adapter *adapter,
2754 struct igb_ring *tx_ring,
2755 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
2756{
2757 struct e1000_adv_tx_context_desc *context_desc;
2758 unsigned int i;
2759 int err;
2760 struct igb_buffer *buffer_info;
2761 u32 info = 0, tu_cmd = 0;
2762 u32 mss_l4len_idx, l4len;
2763 *hdr_len = 0;
2764
2765 if (skb_header_cloned(skb)) {
2766 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2767 if (err)
2768 return err;
2769 }
2770
2771 l4len = tcp_hdrlen(skb);
2772 *hdr_len += l4len;
2773
2774 if (skb->protocol == htons(ETH_P_IP)) {
2775 struct iphdr *iph = ip_hdr(skb);
2776 iph->tot_len = 0;
2777 iph->check = 0;
2778 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2779 iph->daddr, 0,
2780 IPPROTO_TCP,
2781 0);
2782 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
2783 ipv6_hdr(skb)->payload_len = 0;
2784 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2785 &ipv6_hdr(skb)->daddr,
2786 0, IPPROTO_TCP, 0);
2787 }
2788
2789 i = tx_ring->next_to_use;
2790
2791 buffer_info = &tx_ring->buffer_info[i];
2792 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2793 /* VLAN MACLEN IPLEN */
2794 if (tx_flags & IGB_TX_FLAGS_VLAN)
2795 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2796 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2797 *hdr_len += skb_network_offset(skb);
2798 info |= skb_network_header_len(skb);
2799 *hdr_len += skb_network_header_len(skb);
2800 context_desc->vlan_macip_lens = cpu_to_le32(info);
2801
2802 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
2803 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2804
2805 if (skb->protocol == htons(ETH_P_IP))
2806 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
2807 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2808
2809 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2810
2811 /* MSS L4LEN IDX */
2812 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
2813 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
2814
7dfc16fa
AD		 2815 /* Context index must be unique per ring. */
2816 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2817 mss_l4len_idx |= tx_ring->queue_index << 4;
9d5c8243
AK		 2818
2819 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
2820 context_desc->seqnum_seed = 0;
2821
2822 buffer_info->time_stamp = jiffies;
0e014cb1 2823 buffer_info->next_to_watch = i;
9d5c8243
AK		 2824 buffer_info->dma = 0;
2825 i++;
2826 if (i == tx_ring->count)
2827 i = 0;
2828
2829 tx_ring->next_to_use = i;
2830
2831 return true;
2832}
2833
2834static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
2835 struct igb_ring *tx_ring,
2836 struct sk_buff *skb, u32 tx_flags)
2837{
2838 struct e1000_adv_tx_context_desc *context_desc;
2839 unsigned int i;
2840 struct igb_buffer *buffer_info;
2841 u32 info = 0, tu_cmd = 0;
2842
2843 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
2844 (tx_flags & IGB_TX_FLAGS_VLAN)) {
2845 i = tx_ring->next_to_use;
2846 buffer_info = &tx_ring->buffer_info[i];
2847 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2848
2849 if (tx_flags & IGB_TX_FLAGS_VLAN)
2850 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2851 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2852 if (skb->ip_summed == CHECKSUM_PARTIAL)
2853 info |= skb_network_header_len(skb);
2854
2855 context_desc->vlan_macip_lens = cpu_to_le32(info);
2856
2857 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2858
2859 if (skb->ip_summed == CHECKSUM_PARTIAL) {
44b0cda3 2860 switch (skb->protocol) {
09640e63 2861 case cpu_to_be16(ETH_P_IP):
9d5c8243 2862 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
44b0cda3
MW		 2863 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
2864 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2865 break;
09640e63 2866 case cpu_to_be16(ETH_P_IPV6):
44b0cda3
MW		 2867 /* XXX what about other V6 headers?? */
2868 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
2869 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2870 break;
2871 default:
2872 if (unlikely(net_ratelimit()))
2873 dev_warn(&adapter->pdev->dev,
2874 "partial checksum but proto=%x!\n",
2875 skb->protocol);
2876 break;
2877 }
9d5c8243
AK		 2878 }
2879
2880 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2881 context_desc->seqnum_seed = 0;
7dfc16fa
AD		 2882 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2883 context_desc->mss_l4len_idx =
2884 cpu_to_le32(tx_ring->queue_index << 4);
265de409
AD		 2885 else
2886 context_desc->mss_l4len_idx = 0;
9d5c8243
AK		 2887
2888 buffer_info->time_stamp = jiffies;
0e014cb1 2889 buffer_info->next_to_watch = i;
9d5c8243
AK		 2890 buffer_info->dma = 0;
2891
2892 i++;
2893 if (i == tx_ring->count)
2894 i = 0;
2895 tx_ring->next_to_use = i;
2896
2897 return true;
2898 }
2899
2900
2901 return false;
2902}
2903
2904#define IGB_MAX_TXD_PWR 16
2905#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
2906
2907static inline int igb_tx_map_adv(struct igb_adapter *adapter,
0e014cb1
AD		 2908 struct igb_ring *tx_ring, struct sk_buff *skb,
2909 unsigned int first)
9d5c8243
AK		 2910{
2911 struct igb_buffer *buffer_info;
2912 unsigned int len = skb_headlen(skb);
2913 unsigned int count = 0, i;
2914 unsigned int f;
2915
2916 i = tx_ring->next_to_use;
2917
2918 buffer_info = &tx_ring->buffer_info[i];
2919 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2920 buffer_info->length = len;
2921 /* set time_stamp *before* dma to help avoid a possible race */
2922 buffer_info->time_stamp = jiffies;
0e014cb1 2923 buffer_info->next_to_watch = i;
9d5c8243
AK		 2924 buffer_info->dma = pci_map_single(adapter->pdev, skb->data, len,
2925 PCI_DMA_TODEVICE);
2926 count++;
2927 i++;
2928 if (i == tx_ring->count)
2929 i = 0;
2930
2931 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
2932 struct skb_frag_struct *frag;
2933
2934 frag = &skb_shinfo(skb)->frags[f];
2935 len = frag->size;
2936
2937 buffer_info = &tx_ring->buffer_info[i];
2938 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2939 buffer_info->length = len;
2940 buffer_info->time_stamp = jiffies;
0e014cb1 2941 buffer_info->next_to_watch = i;
9d5c8243
AK		 2942 buffer_info->dma = pci_map_page(adapter->pdev,
2943 frag->page,
2944 frag->page_offset,
2945 len,
2946 PCI_DMA_TODEVICE);
2947
2948 count++;
2949 i++;
2950 if (i == tx_ring->count)
2951 i = 0;
2952 }
2953
0e014cb1 2954 i = ((i == 0) ? tx_ring->count - 1 : i - 1);
9d5c8243 2955 tx_ring->buffer_info[i].skb = skb;
0e014cb1 2956 tx_ring->buffer_info[first].next_to_watch = i;
9d5c8243
AK		 2957
2958 return count;
2959}
2960
2961static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
2962 struct igb_ring *tx_ring,
2963 int tx_flags, int count, u32 paylen,
2964 u8 hdr_len)
2965{
2966 union e1000_adv_tx_desc *tx_desc = NULL;
2967 struct igb_buffer *buffer_info;
2968 u32 olinfo_status = 0, cmd_type_len;
2969 unsigned int i;
2970
2971 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
2972 E1000_ADVTXD_DCMD_DEXT);
2973
2974 if (tx_flags & IGB_TX_FLAGS_VLAN)
2975 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
2976
2977 if (tx_flags & IGB_TX_FLAGS_TSO) {
2978 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
2979
2980 /* insert tcp checksum */
2981 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2982
2983 /* insert ip checksum */
2984 if (tx_flags & IGB_TX_FLAGS_IPV4)
2985 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
2986
2987 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
2988 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2989 }
2990
7dfc16fa
AD		 2991 if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) &&
2992 (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
2993 IGB_TX_FLAGS_VLAN)))
661086df 2994 olinfo_status |= tx_ring->queue_index << 4;
9d5c8243
AK		 2995
2996 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
2997
2998 i = tx_ring->next_to_use;
2999 while (count--) {
3000 buffer_info = &tx_ring->buffer_info[i];
3001 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
3002 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
3003 tx_desc->read.cmd_type_len =
3004 cpu_to_le32(cmd_type_len | buffer_info->length);
3005 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
3006 i++;
3007 if (i == tx_ring->count)
3008 i = 0;
3009 }
3010
3011 tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
3012 /* Force memory writes to complete before letting h/w
3013 * know there are new descriptors to fetch. (Only
3014 * applicable for weak-ordered memory model archs,
3015 * such as IA-64). */
3016 wmb();
3017
3018 tx_ring->next_to_use = i;
3019 writel(i, adapter->hw.hw_addr + tx_ring->tail);
3020 /* we need this if more than one processor can write to our tail
3021 * at a time, it syncronizes IO on IA64/Altix systems */
3022 mmiowb();
3023}
3024
3025static int __igb_maybe_stop_tx(struct net_device *netdev,
3026 struct igb_ring *tx_ring, int size)
3027{
3028 struct igb_adapter *adapter = netdev_priv(netdev);
3029
661086df 3030 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 3031
9d5c8243
AK		 3032 /* Herbert's original patch had:
3033 * smp_mb__after_netif_stop_queue();
3034 * but since that doesn't exist yet, just open code it. */
3035 smp_mb();
3036
3037 /* We need to check again in a case another CPU has just
3038 * made room available. */
3039 if (IGB_DESC_UNUSED(tx_ring) < size)
3040 return -EBUSY;
3041
3042 /* A reprieve! */
661086df 3043 netif_wake_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 3044 ++adapter->restart_queue;
3045 return 0;
3046}
3047
3048static int igb_maybe_stop_tx(struct net_device *netdev,
3049 struct igb_ring *tx_ring, int size)
3050{
3051 if (IGB_DESC_UNUSED(tx_ring) >= size)
3052 return 0;
3053 return __igb_maybe_stop_tx(netdev, tx_ring, size);
3054}
3055
3056#define TXD_USE_COUNT(S) (((S) >> (IGB_MAX_TXD_PWR)) + 1)
3057
3058static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
3059 struct net_device *netdev,
3060 struct igb_ring *tx_ring)
3061{
3062 struct igb_adapter *adapter = netdev_priv(netdev);
0e014cb1 3063 unsigned int first;
9d5c8243 3064 unsigned int tx_flags = 0;
9d5c8243
AK		 3065 u8 hdr_len = 0;
3066 int tso = 0;
3067
9d5c8243
AK		 3068 if (test_bit(__IGB_DOWN, &adapter->state)) {
3069 dev_kfree_skb_any(skb);
3070 return NETDEV_TX_OK;
3071 }
3072
3073 if (skb->len <= 0) {
3074 dev_kfree_skb_any(skb);
3075 return NETDEV_TX_OK;
3076 }
3077
9d5c8243
AK		 3078 /* need: 1 descriptor per page,
3079 * + 2 desc gap to keep tail from touching head,
3080 * + 1 desc for skb->data,
3081 * + 1 desc for context descriptor,
3082 * otherwise try next time */
3083 if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
3084 /* this is a hard error */
9d5c8243
AK		 3085 return NETDEV_TX_BUSY;
3086 }
6eb5a7f1 3087 skb_orphan(skb);
9d5c8243
AK		 3088
3089 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
3090 tx_flags |= IGB_TX_FLAGS_VLAN;
3091 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
3092 }
3093
661086df
PWJ		 3094 if (skb->protocol == htons(ETH_P_IP))
3095 tx_flags |= IGB_TX_FLAGS_IPV4;
3096
0e014cb1
AD		 3097 first = tx_ring->next_to_use;
3098
9d5c8243
AK		 3099 tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
3100 &hdr_len) : 0;
3101
3102 if (tso < 0) {
3103 dev_kfree_skb_any(skb);
9d5c8243
AK		 3104 return NETDEV_TX_OK;
3105 }
3106
3107 if (tso)
3108 tx_flags |= IGB_TX_FLAGS_TSO;
3109 else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags))
3110 if (skb->ip_summed == CHECKSUM_PARTIAL)
3111 tx_flags |= IGB_TX_FLAGS_CSUM;
3112
9d5c8243 3113 igb_tx_queue_adv(adapter, tx_ring, tx_flags,
0e014cb1 3114 igb_tx_map_adv(adapter, tx_ring, skb, first),
9d5c8243
AK		 3115 skb->len, hdr_len);
3116
3117 netdev->trans_start = jiffies;
3118
3119 /* Make sure there is space in the ring for the next send. */
3120 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
3121
9d5c8243
AK		 3122 return NETDEV_TX_OK;
3123}
3124
3125static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *netdev)
3126{
3127 struct igb_adapter *adapter = netdev_priv(netdev);
661086df
PWJ		 3128 struct igb_ring *tx_ring;
3129
661086df
PWJ		 3130 int r_idx = 0;
3131 r_idx = skb->queue_mapping & (IGB_MAX_TX_QUEUES - 1);
3132 tx_ring = adapter->multi_tx_table[r_idx];
9d5c8243
AK		 3133
3134 /* This goes back to the question of how to logically map a tx queue
3135 * to a flow. Right now, performance is impacted slightly negatively
3136 * if using multiple tx queues. If the stack breaks away from a
3137 * single qdisc implementation, we can look at this again. */
3138 return (igb_xmit_frame_ring_adv(skb, netdev, tx_ring));
3139}
3140
3141/**
3142 * igb_tx_timeout - Respond to a Tx Hang
3143 * @netdev: network interface device structure
3144 **/
3145static void igb_tx_timeout(struct net_device *netdev)
3146{
3147 struct igb_adapter *adapter = netdev_priv(netdev);
3148 struct e1000_hw *hw = &adapter->hw;
3149
3150 /* Do the reset outside of interrupt context */
3151 adapter->tx_timeout_count++;
3152 schedule_work(&adapter->reset_task);
265de409
AD		 3153 wr32(E1000_EICS,
3154 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 3155}
3156
3157static void igb_reset_task(struct work_struct *work)
3158{
3159 struct igb_adapter *adapter;
3160 adapter = container_of(work, struct igb_adapter, reset_task);
3161
3162 igb_reinit_locked(adapter);
3163}
3164
3165/**
3166 * igb_get_stats - Get System Network Statistics
3167 * @netdev: network interface device structure
3168 *
3169 * Returns the address of the device statistics structure.
3170 * The statistics are actually updated from the timer callback.
3171 **/
3172static struct net_device_stats *
3173igb_get_stats(struct net_device *netdev)
3174{
3175 struct igb_adapter *adapter = netdev_priv(netdev);
3176
3177 /* only return the current stats */
3178 return &adapter->net_stats;
3179}
3180
3181/**
3182 * igb_change_mtu - Change the Maximum Transfer Unit
3183 * @netdev: network interface device structure
3184 * @new_mtu: new value for maximum frame size
3185 *
3186 * Returns 0 on success, negative on failure
3187 **/
3188static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3189{
3190 struct igb_adapter *adapter = netdev_priv(netdev);
3191 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3192
3193 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
3194 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3195 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
3196 return -EINVAL;
3197 }
3198
3199#define MAX_STD_JUMBO_FRAME_SIZE 9234
3200 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3201 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
3202 return -EINVAL;
3203 }
3204
3205 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3206 msleep(1);
3207 /* igb_down has a dependency on max_frame_size */
3208 adapter->max_frame_size = max_frame;
3209 if (netif_running(netdev))
3210 igb_down(adapter);
3211
3212 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3213 * means we reserve 2 more, this pushes us to allocate from the next
3214 * larger slab size.
3215 * i.e. RXBUFFER_2048 --> size-4096 slab
3216 */
3217
3218 if (max_frame <= IGB_RXBUFFER_256)
3219 adapter->rx_buffer_len = IGB_RXBUFFER_256;
3220 else if (max_frame <= IGB_RXBUFFER_512)
3221 adapter->rx_buffer_len = IGB_RXBUFFER_512;
3222 else if (max_frame <= IGB_RXBUFFER_1024)
3223 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3224 else if (max_frame <= IGB_RXBUFFER_2048)
3225 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
3226 else
bf36c1a0
AD		 3227#if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
3228 adapter->rx_buffer_len = IGB_RXBUFFER_16384;
3229#else
3230 adapter->rx_buffer_len = PAGE_SIZE / 2;
3231#endif
9d5c8243
AK		 3232 /* adjust allocation if LPE protects us, and we aren't using SBP */
3233 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
3234 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
3235 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3236
3237 dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
3238 netdev->mtu, new_mtu);
3239 netdev->mtu = new_mtu;
3240
3241 if (netif_running(netdev))
3242 igb_up(adapter);
3243 else
3244 igb_reset(adapter);
3245
3246 clear_bit(__IGB_RESETTING, &adapter->state);
3247
3248 return 0;
3249}
3250
3251/**
3252 * igb_update_stats - Update the board statistics counters
3253 * @adapter: board private structure
3254 **/
3255
3256void igb_update_stats(struct igb_adapter *adapter)
3257{
3258 struct e1000_hw *hw = &adapter->hw;
3259 struct pci_dev *pdev = adapter->pdev;
3260 u16 phy_tmp;
3261
3262#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3263
3264 /*
3265 * Prevent stats update while adapter is being reset, or if the pci
3266 * connection is down.
3267 */
3268 if (adapter->link_speed == 0)
3269 return;
3270 if (pci_channel_offline(pdev))
3271 return;
3272
3273 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3274 adapter->stats.gprc += rd32(E1000_GPRC);
3275 adapter->stats.gorc += rd32(E1000_GORCL);
3276 rd32(E1000_GORCH); /* clear GORCL */
3277 adapter->stats.bprc += rd32(E1000_BPRC);
3278 adapter->stats.mprc += rd32(E1000_MPRC);
3279 adapter->stats.roc += rd32(E1000_ROC);
3280
3281 adapter->stats.prc64 += rd32(E1000_PRC64);
3282 adapter->stats.prc127 += rd32(E1000_PRC127);
3283 adapter->stats.prc255 += rd32(E1000_PRC255);
3284 adapter->stats.prc511 += rd32(E1000_PRC511);
3285 adapter->stats.prc1023 += rd32(E1000_PRC1023);
3286 adapter->stats.prc1522 += rd32(E1000_PRC1522);
3287 adapter->stats.symerrs += rd32(E1000_SYMERRS);
3288 adapter->stats.sec += rd32(E1000_SEC);
3289
3290 adapter->stats.mpc += rd32(E1000_MPC);
3291 adapter->stats.scc += rd32(E1000_SCC);
3292 adapter->stats.ecol += rd32(E1000_ECOL);
3293 adapter->stats.mcc += rd32(E1000_MCC);
3294 adapter->stats.latecol += rd32(E1000_LATECOL);
3295 adapter->stats.dc += rd32(E1000_DC);
3296 adapter->stats.rlec += rd32(E1000_RLEC);
3297 adapter->stats.xonrxc += rd32(E1000_XONRXC);
3298 adapter->stats.xontxc += rd32(E1000_XONTXC);
3299 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
3300 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
3301 adapter->stats.fcruc += rd32(E1000_FCRUC);
3302 adapter->stats.gptc += rd32(E1000_GPTC);
3303 adapter->stats.gotc += rd32(E1000_GOTCL);
3304 rd32(E1000_GOTCH); /* clear GOTCL */
3305 adapter->stats.rnbc += rd32(E1000_RNBC);
3306 adapter->stats.ruc += rd32(E1000_RUC);
3307 adapter->stats.rfc += rd32(E1000_RFC);
3308 adapter->stats.rjc += rd32(E1000_RJC);
3309 adapter->stats.tor += rd32(E1000_TORH);
3310 adapter->stats.tot += rd32(E1000_TOTH);
3311 adapter->stats.tpr += rd32(E1000_TPR);
3312
3313 adapter->stats.ptc64 += rd32(E1000_PTC64);
3314 adapter->stats.ptc127 += rd32(E1000_PTC127);
3315 adapter->stats.ptc255 += rd32(E1000_PTC255);
3316 adapter->stats.ptc511 += rd32(E1000_PTC511);
3317 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
3318 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
3319
3320 adapter->stats.mptc += rd32(E1000_MPTC);
3321 adapter->stats.bptc += rd32(E1000_BPTC);
3322
3323 /* used for adaptive IFS */
3324
3325 hw->mac.tx_packet_delta = rd32(E1000_TPT);
3326 adapter->stats.tpt += hw->mac.tx_packet_delta;
3327 hw->mac.collision_delta = rd32(E1000_COLC);
3328 adapter->stats.colc += hw->mac.collision_delta;
3329
3330 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
3331 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3332 adapter->stats.tncrs += rd32(E1000_TNCRS);
3333 adapter->stats.tsctc += rd32(E1000_TSCTC);
3334 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
3335
3336 adapter->stats.iac += rd32(E1000_IAC);
3337 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
3338 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
3339 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
3340 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
3341 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
3342 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
3343 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
3344 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
3345
3346 /* Fill out the OS statistics structure */
3347 adapter->net_stats.multicast = adapter->stats.mprc;
3348 adapter->net_stats.collisions = adapter->stats.colc;
3349
3350 /* Rx Errors */
3351
3352 /* RLEC on some newer hardware can be incorrect so build
3353 * our own version based on RUC and ROC */
3354 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3355 adapter->stats.crcerrs + adapter->stats.algnerrc +
3356 adapter->stats.ruc + adapter->stats.roc +
3357 adapter->stats.cexterr;
3358 adapter->net_stats.rx_length_errors = adapter->stats.ruc +
3359 adapter->stats.roc;
3360 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3361 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
3362 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3363
3364 /* Tx Errors */
3365 adapter->net_stats.tx_errors = adapter->stats.ecol +
3366 adapter->stats.latecol;
3367 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3368 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3369 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3370
3371 /* Tx Dropped needs to be maintained elsewhere */
3372
3373 /* Phy Stats */
3374 if (hw->phy.media_type == e1000_media_type_copper) {
3375 if ((adapter->link_speed == SPEED_1000) &&
f5f4cf08 3376 (!igb_read_phy_reg(hw, PHY_1000T_STATUS,
9d5c8243
AK		 3377 &phy_tmp))) {
3378 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3379 adapter->phy_stats.idle_errors += phy_tmp;
3380 }
3381 }
3382
3383 /* Management Stats */
3384 adapter->stats.mgptc += rd32(E1000_MGTPTC);
3385 adapter->stats.mgprc += rd32(E1000_MGTPRC);
3386 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3387}
3388
3389
3390static irqreturn_t igb_msix_other(int irq, void *data)
3391{
3392 struct net_device *netdev = data;
3393 struct igb_adapter *adapter = netdev_priv(netdev);
3394 struct e1000_hw *hw = &adapter->hw;
844290e5 3395 u32 icr = rd32(E1000_ICR);
9d5c8243 3396
844290e5 3397 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083
AD		 3398
3399 if(icr & E1000_ICR_DOUTSYNC) {
3400 /* HW is reporting DMA is out of sync */
3401 adapter->stats.doosync++;
3402 }
844290e5
PW		 3403 if (!(icr & E1000_ICR_LSC))
3404 goto no_link_interrupt;
3405 hw->mac.get_link_status = 1;
3406 /* guard against interrupt when we're going down */
3407 if (!test_bit(__IGB_DOWN, &adapter->state))
3408 mod_timer(&adapter->watchdog_timer, jiffies + 1);
eebbbdba 3409
9d5c8243 3410no_link_interrupt:
dda0e083 3411 wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC);
844290e5 3412 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 3413
3414 return IRQ_HANDLED;
3415}
3416
3417static irqreturn_t igb_msix_tx(int irq, void *data)
3418{
3419 struct igb_ring *tx_ring = data;
3420 struct igb_adapter *adapter = tx_ring->adapter;
3421 struct e1000_hw *hw = &adapter->hw;
3422
421e02f0 3423#ifdef CONFIG_IGB_DCA
7dfc16fa 3424 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3425 igb_update_tx_dca(tx_ring);
3426#endif
9d5c8243
AK		 3427 tx_ring->total_bytes = 0;
3428 tx_ring->total_packets = 0;
661086df
PWJ		 3429
3430 /* auto mask will automatically reenable the interrupt when we write
3431 * EICS */
3b644cf6 3432 if (!igb_clean_tx_irq(tx_ring))
9d5c8243
AK		 3433 /* Ring was not completely cleaned, so fire another interrupt */
3434 wr32(E1000_EICS, tx_ring->eims_value);
661086df 3435 else
9d5c8243 3436 wr32(E1000_EIMS, tx_ring->eims_value);
661086df 3437
9d5c8243
AK		 3438 return IRQ_HANDLED;
3439}
3440
6eb5a7f1
AD		 3441static void igb_write_itr(struct igb_ring *ring)
3442{
3443 struct e1000_hw *hw = &ring->adapter->hw;
3444 if ((ring->adapter->itr_setting & 3) && ring->set_itr) {
3445 switch (hw->mac.type) {
3446 case e1000_82576:
3447 wr32(ring->itr_register,
3448 ring->itr_val |
3449 0x80000000);
3450 break;
3451 default:
3452 wr32(ring->itr_register,
3453 ring->itr_val |
3454 (ring->itr_val << 16));
3455 break;
3456 }
3457 ring->set_itr = 0;
3458 }
3459}
3460
9d5c8243
AK		 3461static irqreturn_t igb_msix_rx(int irq, void *data)
3462{
3463 struct igb_ring *rx_ring = data;
9d5c8243 3464
844290e5
PW		 3465 /* Write the ITR value calculated at the end of the
3466 * previous interrupt.
3467 */
9d5c8243 3468
6eb5a7f1 3469 igb_write_itr(rx_ring);
9d5c8243 3470
288379f0
BH		 3471 if (napi_schedule_prep(&rx_ring->napi))
3472 __napi_schedule(&rx_ring->napi);
844290e5 3473
421e02f0 3474#ifdef CONFIG_IGB_DCA
8d253320 3475 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3476 igb_update_rx_dca(rx_ring);
3477#endif
3478 return IRQ_HANDLED;
3479}
3480
421e02f0 3481#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 3482static void igb_update_rx_dca(struct igb_ring *rx_ring)
3483{
3484 u32 dca_rxctrl;
3485 struct igb_adapter *adapter = rx_ring->adapter;
3486 struct e1000_hw *hw = &adapter->hw;
3487 int cpu = get_cpu();
26bc19ec 3488 int q = rx_ring->reg_idx;
fe4506b6
JC		 3489
3490 if (rx_ring->cpu != cpu) {
3491 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
2d064c06
AD		 3492 if (hw->mac.type == e1000_82576) {
3493 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
3494 dca_rxctrl |= dca_get_tag(cpu) <<
3495 E1000_DCA_RXCTRL_CPUID_SHIFT;
3496 } else {
3497 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
3498 dca_rxctrl |= dca_get_tag(cpu);
3499 }
fe4506b6
JC		 3500 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
3501 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
3502 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
3503 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
3504 rx_ring->cpu = cpu;
3505 }
3506 put_cpu();
3507}
3508
3509static void igb_update_tx_dca(struct igb_ring *tx_ring)
3510{
3511 u32 dca_txctrl;
3512 struct igb_adapter *adapter = tx_ring->adapter;
3513 struct e1000_hw *hw = &adapter->hw;
3514 int cpu = get_cpu();
26bc19ec 3515 int q = tx_ring->reg_idx;
fe4506b6
JC		 3516
3517 if (tx_ring->cpu != cpu) {
3518 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
2d064c06
AD		 3519 if (hw->mac.type == e1000_82576) {
3520 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
3521 dca_txctrl |= dca_get_tag(cpu) <<
3522 E1000_DCA_TXCTRL_CPUID_SHIFT;
3523 } else {
3524 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
3525 dca_txctrl |= dca_get_tag(cpu);
3526 }
fe4506b6
JC		 3527 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
3528 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
3529 tx_ring->cpu = cpu;
3530 }
3531 put_cpu();
3532}
3533
3534static void igb_setup_dca(struct igb_adapter *adapter)
3535{
3536 int i;
3537
7dfc16fa 3538 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 3539 return;
3540
3541 for (i = 0; i < adapter->num_tx_queues; i++) {
3542 adapter->tx_ring[i].cpu = -1;
3543 igb_update_tx_dca(&adapter->tx_ring[i]);
3544 }
3545 for (i = 0; i < adapter->num_rx_queues; i++) {
3546 adapter->rx_ring[i].cpu = -1;
3547 igb_update_rx_dca(&adapter->rx_ring[i]);
3548 }
3549}
3550
3551static int __igb_notify_dca(struct device *dev, void *data)
3552{
3553 struct net_device *netdev = dev_get_drvdata(dev);
3554 struct igb_adapter *adapter = netdev_priv(netdev);
3555 struct e1000_hw *hw = &adapter->hw;
3556 unsigned long event = *(unsigned long *)data;
3557
3558 switch (event) {
3559 case DCA_PROVIDER_ADD:
3560 /* if already enabled, don't do it again */
7dfc16fa 3561 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 3562 break;
fe4506b6
JC		 3563 /* Always use CB2 mode, difference is masked
3564 * in the CB driver. */
3565 wr32(E1000_DCA_CTRL, 2);
3566 if (dca_add_requester(dev) == 0) {
bbd98fe4 3567 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 3568 dev_info(&adapter->pdev->dev, "DCA enabled\n");
3569 igb_setup_dca(adapter);
3570 break;
3571 }
3572 /* Fall Through since DCA is disabled. */
3573 case DCA_PROVIDER_REMOVE:
7dfc16fa 3574 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 3575 /* without this a class_device is left
3576 * hanging around in the sysfs model */
3577 dca_remove_requester(dev);
3578 dev_info(&adapter->pdev->dev, "DCA disabled\n");
7dfc16fa 3579 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 3580 wr32(E1000_DCA_CTRL, 1);
3581 }
3582 break;
3583 }
bbd98fe4 3584
fe4506b6 3585 return 0;
9d5c8243
AK		 3586}
3587
fe4506b6
JC		 3588static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
3589 void *p)
3590{
3591 int ret_val;
3592
3593 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
3594 __igb_notify_dca);
3595
3596 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
3597}
421e02f0 3598#endif /* CONFIG_IGB_DCA */
9d5c8243
AK		 3599
3600/**
3601 * igb_intr_msi - Interrupt Handler
3602 * @irq: interrupt number
3603 * @data: pointer to a network interface device structure
3604 **/
3605static irqreturn_t igb_intr_msi(int irq, void *data)
3606{
3607 struct net_device *netdev = data;
3608 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 3609 struct e1000_hw *hw = &adapter->hw;
3610 /* read ICR disables interrupts using IAM */
3611 u32 icr = rd32(E1000_ICR);
3612
6eb5a7f1 3613 igb_write_itr(adapter->rx_ring);
9d5c8243 3614
dda0e083
AD		 3615 if(icr & E1000_ICR_DOUTSYNC) {
3616 /* HW is reporting DMA is out of sync */
3617 adapter->stats.doosync++;
3618 }
3619
9d5c8243
AK		 3620 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3621 hw->mac.get_link_status = 1;
3622 if (!test_bit(__IGB_DOWN, &adapter->state))
3623 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3624 }
3625
288379f0 3626 napi_schedule(&adapter->rx_ring[0].napi);
9d5c8243
AK		 3627
3628 return IRQ_HANDLED;
3629}
3630
3631/**
4a3c6433 3632 * igb_intr - Legacy Interrupt Handler
9d5c8243
AK		 3633 * @irq: interrupt number
3634 * @data: pointer to a network interface device structure
3635 **/
3636static irqreturn_t igb_intr(int irq, void *data)
3637{
3638 struct net_device *netdev = data;
3639 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 3640 struct e1000_hw *hw = &adapter->hw;
3641 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
3642 * need for the IMC write */
3643 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 3644 if (!icr)
3645 return IRQ_NONE; /* Not our interrupt */
3646
6eb5a7f1 3647 igb_write_itr(adapter->rx_ring);
9d5c8243
AK		 3648
3649 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
3650 * not set, then the adapter didn't send an interrupt */
3651 if (!(icr & E1000_ICR_INT_ASSERTED))
3652 return IRQ_NONE;
3653
dda0e083
AD		 3654 if(icr & E1000_ICR_DOUTSYNC) {
3655 /* HW is reporting DMA is out of sync */
3656 adapter->stats.doosync++;
3657 }
3658
9d5c8243
AK		 3659 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3660 hw->mac.get_link_status = 1;
3661 /* guard against interrupt when we're going down */
3662 if (!test_bit(__IGB_DOWN, &adapter->state))
3663 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3664 }
3665
288379f0 3666 napi_schedule(&adapter->rx_ring[0].napi);
9d5c8243
AK		 3667
3668 return IRQ_HANDLED;
3669}
3670
3671/**
661086df
PWJ		 3672 * igb_poll - NAPI Rx polling callback
3673 * @napi: napi polling structure
3674 * @budget: count of how many packets we should handle
9d5c8243 3675 **/
661086df 3676static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 3677{
661086df
PWJ		 3678 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3679 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 3680 struct net_device *netdev = adapter->netdev;
661086df 3681 int tx_clean_complete, work_done = 0;
9d5c8243 3682
661086df 3683 /* this poll routine only supports one tx and one rx queue */
421e02f0 3684#ifdef CONFIG_IGB_DCA
7dfc16fa 3685 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3686 igb_update_tx_dca(&adapter->tx_ring[0]);
3687#endif
661086df 3688 tx_clean_complete = igb_clean_tx_irq(&adapter->tx_ring[0]);
fe4506b6 3689
421e02f0 3690#ifdef CONFIG_IGB_DCA
7dfc16fa 3691 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3692 igb_update_rx_dca(&adapter->rx_ring[0]);
3693#endif
661086df 3694 igb_clean_rx_irq_adv(&adapter->rx_ring[0], &work_done, budget);
9d5c8243
AK		 3695
3696 /* If no Tx and not enough Rx work done, exit the polling mode */
3697 if ((tx_clean_complete && (work_done < budget)) ||
3698 !netif_running(netdev)) {
9d5c8243 3699 if (adapter->itr_setting & 3)
6eb5a7f1 3700 igb_set_itr(adapter);
288379f0 3701 napi_complete(napi);
9d5c8243
AK		 3702 if (!test_bit(__IGB_DOWN, &adapter->state))
3703 igb_irq_enable(adapter);
3704 return 0;
3705 }
3706
3707 return 1;
3708}
3709
3710static int igb_clean_rx_ring_msix(struct napi_struct *napi, int budget)
3711{
3712 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3713 struct igb_adapter *adapter = rx_ring->adapter;
3714 struct e1000_hw *hw = &adapter->hw;
3715 struct net_device *netdev = adapter->netdev;
3716 int work_done = 0;
3717
421e02f0 3718#ifdef CONFIG_IGB_DCA
7dfc16fa 3719 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3720 igb_update_rx_dca(rx_ring);
3721#endif
3b644cf6 3722 igb_clean_rx_irq_adv(rx_ring, &work_done, budget);
9d5c8243
AK		 3723
3724
3725 /* If not enough Rx work done, exit the polling mode */
3726 if ((work_done == 0) || !netif_running(netdev)) {
288379f0 3727 napi_complete(napi);
9d5c8243 3728
6eb5a7f1
AD		 3729 if (adapter->itr_setting & 3) {
3730 if (adapter->num_rx_queues == 1)
3731 igb_set_itr(adapter);
3732 else
3733 igb_update_ring_itr(rx_ring);
9d5c8243 3734 }
844290e5
PW		 3735
3736 if (!test_bit(__IGB_DOWN, &adapter->state))
3737 wr32(E1000_EIMS, rx_ring->eims_value);
3738
9d5c8243
AK		 3739 return 0;
3740 }
3741
3742 return 1;
3743}
6d8126f9 3744
9d5c8243
AK		 3745/**
3746 * igb_clean_tx_irq - Reclaim resources after transmit completes
3747 * @adapter: board private structure
3748 * returns true if ring is completely cleaned
3749 **/
3b644cf6 3750static bool igb_clean_tx_irq(struct igb_ring *tx_ring)
9d5c8243 3751{
3b644cf6 3752 struct igb_adapter *adapter = tx_ring->adapter;
3b644cf6 3753 struct net_device *netdev = adapter->netdev;
0e014cb1 3754 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 3755 struct igb_buffer *buffer_info;
3756 struct sk_buff *skb;
0e014cb1 3757 union e1000_adv_tx_desc *tx_desc, *eop_desc;
9d5c8243 3758 unsigned int total_bytes = 0, total_packets = 0;
0e014cb1
AD		 3759 unsigned int i, eop, count = 0;
3760 bool cleaned = false;
9d5c8243 3761
9d5c8243 3762 i = tx_ring->next_to_clean;
0e014cb1
AD		 3763 eop = tx_ring->buffer_info[i].next_to_watch;
3764 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
3765
3766 while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) &&
3767 (count < tx_ring->count)) {
3768 for (cleaned = false; !cleaned; count++) {
3769 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
9d5c8243 3770 buffer_info = &tx_ring->buffer_info[i];
0e014cb1 3771 cleaned = (i == eop);
9d5c8243
AK		 3772 skb = buffer_info->skb;
3773
3774 if (skb) {
3775 unsigned int segs, bytecount;
3776 /* gso_segs is currently only valid for tcp */
3777 segs = skb_shinfo(skb)->gso_segs ?: 1;
3778 /* multiply data chunks by size of headers */
3779 bytecount = ((segs - 1) * skb_headlen(skb)) +
3780 skb->len;
3781 total_packets += segs;
3782 total_bytes += bytecount;
3783 }
3784
3785 igb_unmap_and_free_tx_resource(adapter, buffer_info);
0e014cb1 3786 tx_desc->wb.status = 0;
9d5c8243
AK		 3787
3788 i++;
3789 if (i == tx_ring->count)
3790 i = 0;
9d5c8243 3791 }
0e014cb1
AD		 3792
3793 eop = tx_ring->buffer_info[i].next_to_watch;
3794 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
3795 }
3796
9d5c8243
AK		 3797 tx_ring->next_to_clean = i;
3798
fc7d345d 3799 if (unlikely(count &&
9d5c8243
AK		 3800 netif_carrier_ok(netdev) &&
3801 IGB_DESC_UNUSED(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
3802 /* Make sure that anybody stopping the queue after this
3803 * sees the new next_to_clean.
3804 */
3805 smp_mb();
661086df
PWJ		 3806 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
3807 !(test_bit(__IGB_DOWN, &adapter->state))) {
3808 netif_wake_subqueue(netdev, tx_ring->queue_index);
3809 ++adapter->restart_queue;
3810 }
9d5c8243
AK		 3811 }
3812
3813 if (tx_ring->detect_tx_hung) {
3814 /* Detect a transmit hang in hardware, this serializes the
3815 * check with the clearing of time_stamp and movement of i */
3816 tx_ring->detect_tx_hung = false;
3817 if (tx_ring->buffer_info[i].time_stamp &&
3818 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
3819 (adapter->tx_timeout_factor * HZ))
3820 && !(rd32(E1000_STATUS) &
3821 E1000_STATUS_TXOFF)) {
3822
9d5c8243
AK		 3823 /* detected Tx unit hang */
3824 dev_err(&adapter->pdev->dev,
3825 "Detected Tx Unit Hang\n"
2d064c06 3826 " Tx Queue <%d>\n"
9d5c8243
AK		 3827 " TDH <%x>\n"
3828 " TDT <%x>\n"
3829 " next_to_use <%x>\n"
3830 " next_to_clean <%x>\n"
9d5c8243
AK		 3831 "buffer_info[next_to_clean]\n"
3832 " time_stamp <%lx>\n"
0e014cb1 3833 " next_to_watch <%x>\n"
9d5c8243
AK		 3834 " jiffies <%lx>\n"
3835 " desc.status <%x>\n",
2d064c06 3836 tx_ring->queue_index,
9d5c8243
AK		 3837 readl(adapter->hw.hw_addr + tx_ring->head),
3838 readl(adapter->hw.hw_addr + tx_ring->tail),
3839 tx_ring->next_to_use,
3840 tx_ring->next_to_clean,
9d5c8243 3841 tx_ring->buffer_info[i].time_stamp,
0e014cb1 3842 eop,
9d5c8243 3843 jiffies,
0e014cb1 3844 eop_desc->wb.status);
661086df 3845 netif_stop_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 3846 }
3847 }
3848 tx_ring->total_bytes += total_bytes;
3849 tx_ring->total_packets += total_packets;
e21ed353
AD		 3850 tx_ring->tx_stats.bytes += total_bytes;
3851 tx_ring->tx_stats.packets += total_packets;
9d5c8243
AK		 3852 adapter->net_stats.tx_bytes += total_bytes;
3853 adapter->net_stats.tx_packets += total_packets;
0e014cb1 3854 return (count < tx_ring->count);
9d5c8243
AK		 3855}
3856
9d5c8243
AK		 3857/**
3858 * igb_receive_skb - helper function to handle rx indications
eebbbdba 3859 * @ring: pointer to receive ring receving this packet
9d5c8243
AK		 3860 * @status: descriptor status field as written by hardware
3861 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
3862 * @skb: pointer to sk_buff to be indicated to stack
3863 **/
d3352520
AD		 3864static void igb_receive_skb(struct igb_ring *ring, u8 status,
3865 union e1000_adv_rx_desc * rx_desc,
3866 struct sk_buff *skb)
3867{
3868 struct igb_adapter * adapter = ring->adapter;
3869 bool vlan_extracted = (adapter->vlgrp && (status & E1000_RXD_STAT_VP));
3870
0c8dfc83 3871 skb_record_rx_queue(skb, ring->queue_index);
5c0999b7 3872 if (skb->ip_summed == CHECKSUM_UNNECESSARY) {
d3352520 3873 if (vlan_extracted)
5c0999b7
HX		 3874 vlan_gro_receive(&ring->napi, adapter->vlgrp,
3875 le16_to_cpu(rx_desc->wb.upper.vlan),
3876 skb);
d3352520 3877 else
5c0999b7 3878 napi_gro_receive(&ring->napi, skb);
d3352520 3879 } else {
d3352520
AD		 3880 if (vlan_extracted)
3881 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
3882 le16_to_cpu(rx_desc->wb.upper.vlan));
3883 else
d3352520 3884 netif_receive_skb(skb);
d3352520 3885 }
9d5c8243
AK		 3886}
3887
3888
3889static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
3890 u32 status_err, struct sk_buff *skb)
3891{
3892 skb->ip_summed = CHECKSUM_NONE;
3893
3894 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
3895 if ((status_err & E1000_RXD_STAT_IXSM) || !adapter->rx_csum)
3896 return;
3897 /* TCP/UDP checksum error bit is set */
3898 if (status_err &
3899 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
3900 /* let the stack verify checksum errors */
3901 adapter->hw_csum_err++;
3902 return;
3903 }
3904 /* It must be a TCP or UDP packet with a valid checksum */
3905 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
3906 skb->ip_summed = CHECKSUM_UNNECESSARY;
3907
3908 adapter->hw_csum_good++;
3909}
3910
3b644cf6
MW		 3911static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring,
3912 int *work_done, int budget)
9d5c8243 3913{
3b644cf6 3914 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 3915 struct net_device *netdev = adapter->netdev;
3916 struct pci_dev *pdev = adapter->pdev;
3917 union e1000_adv_rx_desc *rx_desc , *next_rxd;
3918 struct igb_buffer *buffer_info , *next_buffer;
3919 struct sk_buff *skb;
bf36c1a0 3920 unsigned int i;
9d5c8243
AK		 3921 u32 length, hlen, staterr;
3922 bool cleaned = false;
3923 int cleaned_count = 0;
3924 unsigned int total_bytes = 0, total_packets = 0;
3925
3926 i = rx_ring->next_to_clean;
69d3ca53 3927 buffer_info = &rx_ring->buffer_info[i];
9d5c8243
AK		 3928 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3929 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3930
3931 while (staterr & E1000_RXD_STAT_DD) {
3932 if (*work_done >= budget)
3933 break;
3934 (*work_done)++;
9d5c8243 3935
69d3ca53
AD		 3936 skb = buffer_info->skb;
3937 prefetch(skb->data - NET_IP_ALIGN);
3938 buffer_info->skb = NULL;
3939
3940 i++;
3941 if (i == rx_ring->count)
3942 i = 0;
3943 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
3944 prefetch(next_rxd);
3945 next_buffer = &rx_ring->buffer_info[i];
9d5c8243
AK		 3946
3947 length = le16_to_cpu(rx_desc->wb.upper.length);
3948 cleaned = true;
3949 cleaned_count++;
3950
bf36c1a0
AD		 3951 if (!adapter->rx_ps_hdr_size) {
3952 pci_unmap_single(pdev, buffer_info->dma,
3953 adapter->rx_buffer_len +
3954 NET_IP_ALIGN,
3955 PCI_DMA_FROMDEVICE);
3956 skb_put(skb, length);
3957 goto send_up;
9d5c8243
AK		 3958 }
3959
69d3ca53
AD		 3960 /* HW will not DMA in data larger than the given buffer, even
3961 * if it parses the (NFS, of course) header to be larger. In
3962 * that case, it fills the header buffer and spills the rest
3963 * into the page.
3964 */
3965 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
3966 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
3967 if (hlen > adapter->rx_ps_hdr_size)
3968 hlen = adapter->rx_ps_hdr_size;
3969
bf36c1a0
AD		 3970 if (!skb_shinfo(skb)->nr_frags) {
3971 pci_unmap_single(pdev, buffer_info->dma,
3972 adapter->rx_ps_hdr_size +
3973 NET_IP_ALIGN,
3974 PCI_DMA_FROMDEVICE);
3975 skb_put(skb, hlen);
3976 }
3977
3978 if (length) {
9d5c8243 3979 pci_unmap_page(pdev, buffer_info->page_dma,
bf36c1a0 3980 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9d5c8243 3981 buffer_info->page_dma = 0;
bf36c1a0
AD		 3982
3983 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
3984 buffer_info->page,
3985 buffer_info->page_offset,
3986 length);
3987
3988 if ((adapter->rx_buffer_len > (PAGE_SIZE / 2)) ||
3989 (page_count(buffer_info->page) != 1))
3990 buffer_info->page = NULL;
3991 else
3992 get_page(buffer_info->page);
9d5c8243
AK		 3993
3994 skb->len += length;
3995 skb->data_len += length;
9d5c8243 3996
bf36c1a0 3997 skb->truesize += length;
9d5c8243 3998 }
9d5c8243 3999
bf36c1a0 4000 if (!(staterr & E1000_RXD_STAT_EOP)) {
b2d56536
AD		 4001 buffer_info->skb = next_buffer->skb;
4002 buffer_info->dma = next_buffer->dma;
4003 next_buffer->skb = skb;
4004 next_buffer->dma = 0;
bf36c1a0
AD		 4005 goto next_desc;
4006 }
69d3ca53 4007send_up:
9d5c8243
AK		 4008 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
4009 dev_kfree_skb_irq(skb);
4010 goto next_desc;
4011 }
9d5c8243
AK		 4012
4013 total_bytes += skb->len;
4014 total_packets++;
4015
4016 igb_rx_checksum_adv(adapter, staterr, skb);
4017
4018 skb->protocol = eth_type_trans(skb, netdev);
4019
d3352520 4020 igb_receive_skb(rx_ring, staterr, rx_desc, skb);
9d5c8243 4021
9d5c8243
AK		 4022next_desc:
4023 rx_desc->wb.upper.status_error = 0;
4024
4025 /* return some buffers to hardware, one at a time is too slow */
4026 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
3b644cf6 4027 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 4028 cleaned_count = 0;
4029 }
4030
4031 /* use prefetched values */
4032 rx_desc = next_rxd;
4033 buffer_info = next_buffer;
9d5c8243
AK		 4034 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4035 }
bf36c1a0 4036
9d5c8243
AK		 4037 rx_ring->next_to_clean = i;
4038 cleaned_count = IGB_DESC_UNUSED(rx_ring);
4039
4040 if (cleaned_count)
3b644cf6 4041 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 4042
4043 rx_ring->total_packets += total_packets;
4044 rx_ring->total_bytes += total_bytes;
4045 rx_ring->rx_stats.packets += total_packets;
4046 rx_ring->rx_stats.bytes += total_bytes;
4047 adapter->net_stats.rx_bytes += total_bytes;
4048 adapter->net_stats.rx_packets += total_packets;
4049 return cleaned;
4050}
4051
4052
4053/**
4054 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
4055 * @adapter: address of board private structure
4056 **/
3b644cf6 4057static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
9d5c8243
AK		 4058 int cleaned_count)
4059{
3b644cf6 4060 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 4061 struct net_device *netdev = adapter->netdev;
4062 struct pci_dev *pdev = adapter->pdev;
4063 union e1000_adv_rx_desc *rx_desc;
4064 struct igb_buffer *buffer_info;
4065 struct sk_buff *skb;
4066 unsigned int i;
db761762 4067 int bufsz;
9d5c8243
AK		 4068
4069 i = rx_ring->next_to_use;
4070 buffer_info = &rx_ring->buffer_info[i];
4071
db761762
AD		 4072 if (adapter->rx_ps_hdr_size)
4073 bufsz = adapter->rx_ps_hdr_size;
4074 else
4075 bufsz = adapter->rx_buffer_len;
4076 bufsz += NET_IP_ALIGN;
4077
9d5c8243
AK		 4078 while (cleaned_count--) {
4079 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4080
bf36c1a0 4081 if (adapter->rx_ps_hdr_size && !buffer_info->page_dma) {
9d5c8243 4082 if (!buffer_info->page) {
bf36c1a0
AD		 4083 buffer_info->page = alloc_page(GFP_ATOMIC);
4084 if (!buffer_info->page) {
4085 adapter->alloc_rx_buff_failed++;
4086 goto no_buffers;
4087 }
4088 buffer_info->page_offset = 0;
4089 } else {
4090 buffer_info->page_offset ^= PAGE_SIZE / 2;
9d5c8243
AK		 4091 }
4092 buffer_info->page_dma =
db761762 4093 pci_map_page(pdev, buffer_info->page,
bf36c1a0
AD		 4094 buffer_info->page_offset,
4095 PAGE_SIZE / 2,
9d5c8243
AK		 4096 PCI_DMA_FROMDEVICE);
4097 }
4098
4099 if (!buffer_info->skb) {
9d5c8243 4100 skb = netdev_alloc_skb(netdev, bufsz);
9d5c8243
AK		 4101 if (!skb) {
4102 adapter->alloc_rx_buff_failed++;
4103 goto no_buffers;
4104 }
4105
4106 /* Make buffer alignment 2 beyond a 16 byte boundary
4107 * this will result in a 16 byte aligned IP header after
4108 * the 14 byte MAC header is removed
4109 */
4110 skb_reserve(skb, NET_IP_ALIGN);
4111
4112 buffer_info->skb = skb;
4113 buffer_info->dma = pci_map_single(pdev, skb->data,
4114 bufsz,
4115 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 4116 }
4117 /* Refresh the desc even if buffer_addrs didn't change because
4118 * each write-back erases this info. */
4119 if (adapter->rx_ps_hdr_size) {
4120 rx_desc->read.pkt_addr =
4121 cpu_to_le64(buffer_info->page_dma);
4122 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
4123 } else {
4124 rx_desc->read.pkt_addr =
4125 cpu_to_le64(buffer_info->dma);
4126 rx_desc->read.hdr_addr = 0;
4127 }
4128
4129 i++;
4130 if (i == rx_ring->count)
4131 i = 0;
4132 buffer_info = &rx_ring->buffer_info[i];
4133 }
4134
4135no_buffers:
4136 if (rx_ring->next_to_use != i) {
4137 rx_ring->next_to_use = i;
4138 if (i == 0)
4139 i = (rx_ring->count - 1);
4140 else
4141 i--;
4142
4143 /* Force memory writes to complete before letting h/w
4144 * know there are new descriptors to fetch. (Only
4145 * applicable for weak-ordered memory model archs,
4146 * such as IA-64). */
4147 wmb();
4148 writel(i, adapter->hw.hw_addr + rx_ring->tail);
4149 }
4150}
4151
4152/**
4153 * igb_mii_ioctl -
4154 * @netdev:
4155 * @ifreq:
4156 * @cmd:
4157 **/
4158static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4159{
4160 struct igb_adapter *adapter = netdev_priv(netdev);
4161 struct mii_ioctl_data *data = if_mii(ifr);
4162
4163 if (adapter->hw.phy.media_type != e1000_media_type_copper)
4164 return -EOPNOTSUPP;
4165
4166 switch (cmd) {
4167 case SIOCGMIIPHY:
4168 data->phy_id = adapter->hw.phy.addr;
4169 break;
4170 case SIOCGMIIREG:
4171 if (!capable(CAP_NET_ADMIN))
4172 return -EPERM;
f5f4cf08
AD		 4173 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
4174 &data->val_out))
9d5c8243
AK		 4175 return -EIO;
4176 break;
4177 case SIOCSMIIREG:
4178 default:
4179 return -EOPNOTSUPP;
4180 }
4181 return 0;
4182}
4183
4184/**
4185 * igb_ioctl -
4186 * @netdev:
4187 * @ifreq:
4188 * @cmd:
4189 **/
4190static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4191{
4192 switch (cmd) {
4193 case SIOCGMIIPHY:
4194 case SIOCGMIIREG:
4195 case SIOCSMIIREG:
4196 return igb_mii_ioctl(netdev, ifr, cmd);
4197 default:
4198 return -EOPNOTSUPP;
4199 }
4200}
4201
4202static void igb_vlan_rx_register(struct net_device *netdev,
4203 struct vlan_group *grp)
4204{
4205 struct igb_adapter *adapter = netdev_priv(netdev);
4206 struct e1000_hw *hw = &adapter->hw;
4207 u32 ctrl, rctl;
4208
4209 igb_irq_disable(adapter);
4210 adapter->vlgrp = grp;
4211
4212 if (grp) {
4213 /* enable VLAN tag insert/strip */
4214 ctrl = rd32(E1000_CTRL);
4215 ctrl |= E1000_CTRL_VME;
4216 wr32(E1000_CTRL, ctrl);
4217
4218 /* enable VLAN receive filtering */
4219 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 4220 rctl &= ~E1000_RCTL_CFIEN;
4221 wr32(E1000_RCTL, rctl);
4222 igb_update_mng_vlan(adapter);
4223 wr32(E1000_RLPML,
4224 adapter->max_frame_size + VLAN_TAG_SIZE);
4225 } else {
4226 /* disable VLAN tag insert/strip */
4227 ctrl = rd32(E1000_CTRL);
4228 ctrl &= ~E1000_CTRL_VME;
4229 wr32(E1000_CTRL, ctrl);
4230
9d5c8243
AK		 4231 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
4232 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4233 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
4234 }
4235 wr32(E1000_RLPML,
4236 adapter->max_frame_size);
4237 }
4238
4239 if (!test_bit(__IGB_DOWN, &adapter->state))
4240 igb_irq_enable(adapter);
4241}
4242
4243static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
4244{
4245 struct igb_adapter *adapter = netdev_priv(netdev);
4246 struct e1000_hw *hw = &adapter->hw;
4247 u32 vfta, index;
4248
28b0759c 4249 if ((hw->mng_cookie.status &
9d5c8243
AK		 4250 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4251 (vid == adapter->mng_vlan_id))
4252 return;
4253 /* add VID to filter table */
4254 index = (vid >> 5) & 0x7F;
4255 vfta = array_rd32(E1000_VFTA, index);
4256 vfta |= (1 << (vid & 0x1F));
4257 igb_write_vfta(&adapter->hw, index, vfta);
4258}
4259
4260static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
4261{
4262 struct igb_adapter *adapter = netdev_priv(netdev);
4263 struct e1000_hw *hw = &adapter->hw;
4264 u32 vfta, index;
4265
4266 igb_irq_disable(adapter);
4267 vlan_group_set_device(adapter->vlgrp, vid, NULL);
4268
4269 if (!test_bit(__IGB_DOWN, &adapter->state))
4270 igb_irq_enable(adapter);
4271
4272 if ((adapter->hw.mng_cookie.status &
4273 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4274 (vid == adapter->mng_vlan_id)) {
4275 /* release control to f/w */
4276 igb_release_hw_control(adapter);
4277 return;
4278 }
4279
4280 /* remove VID from filter table */
4281 index = (vid >> 5) & 0x7F;
4282 vfta = array_rd32(E1000_VFTA, index);
4283 vfta &= ~(1 << (vid & 0x1F));
4284 igb_write_vfta(&adapter->hw, index, vfta);
4285}
4286
4287static void igb_restore_vlan(struct igb_adapter *adapter)
4288{
4289 igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
4290
4291 if (adapter->vlgrp) {
4292 u16 vid;
4293 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
4294 if (!vlan_group_get_device(adapter->vlgrp, vid))
4295 continue;
4296 igb_vlan_rx_add_vid(adapter->netdev, vid);
4297 }
4298 }
4299}
4300
4301int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
4302{
4303 struct e1000_mac_info *mac = &adapter->hw.mac;
4304
4305 mac->autoneg = 0;
4306
4307 /* Fiber NICs only allow 1000 gbps Full duplex */
4308 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) &&
4309 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
4310 dev_err(&adapter->pdev->dev,
4311 "Unsupported Speed/Duplex configuration\n");
4312 return -EINVAL;
4313 }
4314
4315 switch (spddplx) {
4316 case SPEED_10 + DUPLEX_HALF:
4317 mac->forced_speed_duplex = ADVERTISE_10_HALF;
4318 break;
4319 case SPEED_10 + DUPLEX_FULL:
4320 mac->forced_speed_duplex = ADVERTISE_10_FULL;
4321 break;
4322 case SPEED_100 + DUPLEX_HALF:
4323 mac->forced_speed_duplex = ADVERTISE_100_HALF;
4324 break;
4325 case SPEED_100 + DUPLEX_FULL:
4326 mac->forced_speed_duplex = ADVERTISE_100_FULL;
4327 break;
4328 case SPEED_1000 + DUPLEX_FULL:
4329 mac->autoneg = 1;
4330 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
4331 break;
4332 case SPEED_1000 + DUPLEX_HALF: /* not supported */
4333 default:
4334 dev_err(&adapter->pdev->dev,
4335 "Unsupported Speed/Duplex configuration\n");
4336 return -EINVAL;
4337 }
4338 return 0;
4339}
4340
4341
4342static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
4343{
4344 struct net_device *netdev = pci_get_drvdata(pdev);
4345 struct igb_adapter *adapter = netdev_priv(netdev);
4346 struct e1000_hw *hw = &adapter->hw;
2d064c06 4347 u32 ctrl, rctl, status;
9d5c8243
AK		 4348 u32 wufc = adapter->wol;
4349#ifdef CONFIG_PM
4350 int retval = 0;
4351#endif
4352
4353 netif_device_detach(netdev);
4354
a88f10ec
AD		 4355 if (netif_running(netdev))
4356 igb_close(netdev);
4357
4358 igb_reset_interrupt_capability(adapter);
4359
4360 igb_free_queues(adapter);
9d5c8243
AK		 4361
4362#ifdef CONFIG_PM
4363 retval = pci_save_state(pdev);
4364 if (retval)
4365 return retval;
4366#endif
4367
4368 status = rd32(E1000_STATUS);
4369 if (status & E1000_STATUS_LU)
4370 wufc &= ~E1000_WUFC_LNKC;
4371
4372 if (wufc) {
4373 igb_setup_rctl(adapter);
4374 igb_set_multi(netdev);
4375
4376 /* turn on all-multi mode if wake on multicast is enabled */
4377 if (wufc & E1000_WUFC_MC) {
4378 rctl = rd32(E1000_RCTL);
4379 rctl |= E1000_RCTL_MPE;
4380 wr32(E1000_RCTL, rctl);
4381 }
4382
4383 ctrl = rd32(E1000_CTRL);
4384 /* advertise wake from D3Cold */
4385 #define E1000_CTRL_ADVD3WUC 0x00100000
4386 /* phy power management enable */
4387 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
4388 ctrl |= E1000_CTRL_ADVD3WUC;
4389 wr32(E1000_CTRL, ctrl);
4390
9d5c8243
AK		 4391 /* Allow time for pending master requests to run */
4392 igb_disable_pcie_master(&adapter->hw);
4393
4394 wr32(E1000_WUC, E1000_WUC_PME_EN);
4395 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 4396 } else {
4397 wr32(E1000_WUC, 0);
4398 wr32(E1000_WUFC, 0);
9d5c8243
AK		 4399 }
4400
2d064c06
AD		 4401 /* make sure adapter isn't asleep if manageability/wol is enabled */
4402 if (wufc || adapter->en_mng_pt) {
9d5c8243
AK		 4403 pci_enable_wake(pdev, PCI_D3hot, 1);
4404 pci_enable_wake(pdev, PCI_D3cold, 1);
2d064c06
AD		 4405 } else {
4406 igb_shutdown_fiber_serdes_link_82575(hw);
4407 pci_enable_wake(pdev, PCI_D3hot, 0);
4408 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243
AK		 4409 }
4410
4411 /* Release control of h/w to f/w. If f/w is AMT enabled, this
4412 * would have already happened in close and is redundant. */
4413 igb_release_hw_control(adapter);
4414
4415 pci_disable_device(pdev);
4416
4417 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4418
4419 return 0;
4420}
4421
4422#ifdef CONFIG_PM
4423static int igb_resume(struct pci_dev *pdev)
4424{
4425 struct net_device *netdev = pci_get_drvdata(pdev);
4426 struct igb_adapter *adapter = netdev_priv(netdev);
4427 struct e1000_hw *hw = &adapter->hw;
4428 u32 err;
4429
4430 pci_set_power_state(pdev, PCI_D0);
4431 pci_restore_state(pdev);
42bfd33a 4432
aed5dec3 4433 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 4434 if (err) {
4435 dev_err(&pdev->dev,
4436 "igb: Cannot enable PCI device from suspend\n");
4437 return err;
4438 }
4439 pci_set_master(pdev);
4440
4441 pci_enable_wake(pdev, PCI_D3hot, 0);
4442 pci_enable_wake(pdev, PCI_D3cold, 0);
4443
a88f10ec
AD		 4444 igb_set_interrupt_capability(adapter);
4445
4446 if (igb_alloc_queues(adapter)) {
4447 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
4448 return -ENOMEM;
9d5c8243
AK		 4449 }
4450
4451 /* e1000_power_up_phy(adapter); */
4452
4453 igb_reset(adapter);
a8564f03
AD		 4454
4455 /* let the f/w know that the h/w is now under the control of the
4456 * driver. */
4457 igb_get_hw_control(adapter);
4458
9d5c8243
AK		 4459 wr32(E1000_WUS, ~0);
4460
a88f10ec
AD		 4461 if (netif_running(netdev)) {
4462 err = igb_open(netdev);
4463 if (err)
4464 return err;
4465 }
9d5c8243
AK		 4466
4467 netif_device_attach(netdev);
4468
9d5c8243
AK		 4469 return 0;
4470}
4471#endif
4472
4473static void igb_shutdown(struct pci_dev *pdev)
4474{
4475 igb_suspend(pdev, PMSG_SUSPEND);
4476}
4477
4478#ifdef CONFIG_NET_POLL_CONTROLLER
4479/*
4480 * Polling 'interrupt' - used by things like netconsole to send skbs
4481 * without having to re-enable interrupts. It's not called while
4482 * the interrupt routine is executing.
4483 */
4484static void igb_netpoll(struct net_device *netdev)
4485{
4486 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 4487 struct e1000_hw *hw = &adapter->hw;
9d5c8243 4488 int i;
9d5c8243 4489
eebbbdba
AD		 4490 if (!adapter->msix_entries) {
4491 igb_irq_disable(adapter);
4492 napi_schedule(&adapter->rx_ring[0].napi);
4493 return;
4494 }
9d5c8243 4495
eebbbdba
AD		 4496 for (i = 0; i < adapter->num_tx_queues; i++) {
4497 struct igb_ring *tx_ring = &adapter->tx_ring[i];
4498 wr32(E1000_EIMC, tx_ring->eims_value);
4499 igb_clean_tx_irq(tx_ring);
4500 wr32(E1000_EIMS, tx_ring->eims_value);
4501 }
9d5c8243 4502
eebbbdba
AD		 4503 for (i = 0; i < adapter->num_rx_queues; i++) {
4504 struct igb_ring *rx_ring = &adapter->rx_ring[i];
4505 wr32(E1000_EIMC, rx_ring->eims_value);
4506 napi_schedule(&rx_ring->napi);
4507 }
9d5c8243
AK		 4508}
4509#endif /* CONFIG_NET_POLL_CONTROLLER */
4510
4511/**
4512 * igb_io_error_detected - called when PCI error is detected
4513 * @pdev: Pointer to PCI device
4514 * @state: The current pci connection state
4515 *
4516 * This function is called after a PCI bus error affecting
4517 * this device has been detected.
4518 */
4519static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
4520 pci_channel_state_t state)
4521{
4522 struct net_device *netdev = pci_get_drvdata(pdev);
4523 struct igb_adapter *adapter = netdev_priv(netdev);
4524
4525 netif_device_detach(netdev);
4526
4527 if (netif_running(netdev))
4528 igb_down(adapter);
4529 pci_disable_device(pdev);
4530
4531 /* Request a slot slot reset. */
4532 return PCI_ERS_RESULT_NEED_RESET;
4533}
4534
4535/**
4536 * igb_io_slot_reset - called after the pci bus has been reset.
4537 * @pdev: Pointer to PCI device
4538 *
4539 * Restart the card from scratch, as if from a cold-boot. Implementation
4540 * resembles the first-half of the igb_resume routine.
4541 */
4542static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
4543{
4544 struct net_device *netdev = pci_get_drvdata(pdev);
4545 struct igb_adapter *adapter = netdev_priv(netdev);
4546 struct e1000_hw *hw = &adapter->hw;
40a914fa 4547 pci_ers_result_t result;
42bfd33a 4548 int err;
9d5c8243 4549
aed5dec3 4550 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 4551 dev_err(&pdev->dev,
4552 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 4553 result = PCI_ERS_RESULT_DISCONNECT;
4554 } else {
4555 pci_set_master(pdev);
4556 pci_restore_state(pdev);
9d5c8243 4557
40a914fa
AD		 4558 pci_enable_wake(pdev, PCI_D3hot, 0);
4559 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 4560
40a914fa
AD		 4561 igb_reset(adapter);
4562 wr32(E1000_WUS, ~0);
4563 result = PCI_ERS_RESULT_RECOVERED;
4564 }
9d5c8243 4565
ea943d41
JK		 4566 err = pci_cleanup_aer_uncorrect_error_status(pdev);
4567 if (err) {
4568 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
4569 "failed 0x%0x\n", err);
4570 /* non-fatal, continue */
4571 }
40a914fa
AD		 4572
4573 return result;
9d5c8243
AK		 4574}
4575
4576/**
4577 * igb_io_resume - called when traffic can start flowing again.
4578 * @pdev: Pointer to PCI device
4579 *
4580 * This callback is called when the error recovery driver tells us that
4581 * its OK to resume normal operation. Implementation resembles the
4582 * second-half of the igb_resume routine.
4583 */
4584static void igb_io_resume(struct pci_dev *pdev)
4585{
4586 struct net_device *netdev = pci_get_drvdata(pdev);
4587 struct igb_adapter *adapter = netdev_priv(netdev);
4588
9d5c8243
AK		 4589 if (netif_running(netdev)) {
4590 if (igb_up(adapter)) {
4591 dev_err(&pdev->dev, "igb_up failed after reset\n");
4592 return;
4593 }
4594 }
4595
4596 netif_device_attach(netdev);
4597
4598 /* let the f/w know that the h/w is now under the control of the
4599 * driver. */
4600 igb_get_hw_control(adapter);
9d5c8243
AK		 4601}
4602
4603/* igb_main.c */
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