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igb: fix hw timestamping
[mirror_ubuntu-artful-kernel.git] / drivers / net / igb / igb_main.c
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9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
86d5d38f 4 Copyright(c) 2007-2009 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/module.h>
29#include <linux/types.h>
30#include <linux/init.h>
31#include <linux/vmalloc.h>
32#include <linux/pagemap.h>
33#include <linux/netdevice.h>
9d5c8243 34#include <linux/ipv6.h>
5a0e3ad6 35#include <linux/slab.h>
9d5c8243
AK		 36#include <net/checksum.h>
37#include <net/ip6_checksum.h>
c6cb090b 38#include <linux/net_tstamp.h>
9d5c8243
AK		 39#include <linux/mii.h>
40#include <linux/ethtool.h>
41#include <linux/if_vlan.h>
42#include <linux/pci.h>
c54106bb 43#include <linux/pci-aspm.h>
9d5c8243
AK		 44#include <linux/delay.h>
45#include <linux/interrupt.h>
46#include <linux/if_ether.h>
40a914fa 47#include <linux/aer.h>
421e02f0 48#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 49#include <linux/dca.h>
50#endif
9d5c8243
AK		 51#include "igb.h"
52
0d1fe82d
CW		 53#define MAJ 3
54#define MIN 0
55#define BUILD 6
56#define KFIX 2
57#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
58__stringify(BUILD) "-k" __stringify(KFIX)
9d5c8243
AK		 59char igb_driver_name[] = "igb";
60char igb_driver_version[] = DRV_VERSION;
61static const char igb_driver_string[] =
62 "Intel(R) Gigabit Ethernet Network Driver";
4c4b42cb 63static const char igb_copyright[] = "Copyright (c) 2007-2011 Intel Corporation.";
9d5c8243 64
9d5c8243
AK		 65static const struct e1000_info *igb_info_tbl[] = {
66 [board_82575] = &e1000_82575_info,
67};
68
a3aa1884 69static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = {
d2ba2ed8
AD		 70 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
71 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
72 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
73 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
55cac248
AD		 74 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
75 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
6493d24f 76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
55cac248
AD		 77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
308fb39a
JG		 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
1b5dda33
GJ		 82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
2d064c06 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
747d49ba 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
2d064c06
AD		 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
b894fa26 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
c8ea5ea9 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
95 /* required last entry */
96 {0, }
97};
98
99MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
100
101void igb_reset(struct igb_adapter *);
102static int igb_setup_all_tx_resources(struct igb_adapter *);
103static int igb_setup_all_rx_resources(struct igb_adapter *);
104static void igb_free_all_tx_resources(struct igb_adapter *);
105static void igb_free_all_rx_resources(struct igb_adapter *);
06cf2666 106static void igb_setup_mrqc(struct igb_adapter *);
9d5c8243
AK		 107static int igb_probe(struct pci_dev *, const struct pci_device_id *);
108static void __devexit igb_remove(struct pci_dev *pdev);
673b8b70 109static void igb_init_hw_timer(struct igb_adapter *adapter);
9d5c8243
AK		 110static int igb_sw_init(struct igb_adapter *);
111static int igb_open(struct net_device *);
112static int igb_close(struct net_device *);
113static void igb_configure_tx(struct igb_adapter *);
114static void igb_configure_rx(struct igb_adapter *);
9d5c8243
AK		 115static void igb_clean_all_tx_rings(struct igb_adapter *);
116static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 117static void igb_clean_tx_ring(struct igb_ring *);
118static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 119static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 120static void igb_update_phy_info(unsigned long);
121static void igb_watchdog(unsigned long);
122static void igb_watchdog_task(struct work_struct *);
b1a436c3 123static netdev_tx_t igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
12dcd86b
ED		 124static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
125 struct rtnl_link_stats64 *stats);
9d5c8243
AK		 126static int igb_change_mtu(struct net_device *, int);
127static int igb_set_mac(struct net_device *, void *);
68d480c4 128static void igb_set_uta(struct igb_adapter *adapter);
9d5c8243
AK		 129static irqreturn_t igb_intr(int irq, void *);
130static irqreturn_t igb_intr_msi(int irq, void *);
131static irqreturn_t igb_msix_other(int irq, void *);
047e0030 132static irqreturn_t igb_msix_ring(int irq, void *);
421e02f0 133#ifdef CONFIG_IGB_DCA
047e0030 134static void igb_update_dca(struct igb_q_vector *);
fe4506b6 135static void igb_setup_dca(struct igb_adapter *);
421e02f0 136#endif /* CONFIG_IGB_DCA */
047e0030 137static bool igb_clean_tx_irq(struct igb_q_vector *);
661086df 138static int igb_poll(struct napi_struct *, int);
047e0030 139static bool igb_clean_rx_irq_adv(struct igb_q_vector *, int *, int);
9d5c8243
AK		 140static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
141static void igb_tx_timeout(struct net_device *);
142static void igb_reset_task(struct work_struct *);
143static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
144static void igb_vlan_rx_add_vid(struct net_device *, u16);
145static void igb_vlan_rx_kill_vid(struct net_device *, u16);
146static void igb_restore_vlan(struct igb_adapter *);
26ad9178 147static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
4ae196df
AD		 148static void igb_ping_all_vfs(struct igb_adapter *);
149static void igb_msg_task(struct igb_adapter *);
4ae196df 150static void igb_vmm_control(struct igb_adapter *);
f2ca0dbe 151static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
4ae196df 152static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
8151d294
WM		 153static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
154static int igb_ndo_set_vf_vlan(struct net_device *netdev,
155 int vf, u16 vlan, u8 qos);
156static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate);
157static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
158 struct ifla_vf_info *ivi);
17dc566c 159static void igb_check_vf_rate_limit(struct igb_adapter *);
9d5c8243 160
9d5c8243 161#ifdef CONFIG_PM
3fe7c4c9 162static int igb_suspend(struct pci_dev *, pm_message_t);
9d5c8243
AK		 163static int igb_resume(struct pci_dev *);
164#endif
165static void igb_shutdown(struct pci_dev *);
421e02f0 166#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 167static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
168static struct notifier_block dca_notifier = {
169 .notifier_call = igb_notify_dca,
170 .next = NULL,
171 .priority = 0
172};
173#endif
9d5c8243
AK		 174#ifdef CONFIG_NET_POLL_CONTROLLER
175/* for netdump / net console */
176static void igb_netpoll(struct net_device *);
177#endif
37680117 178#ifdef CONFIG_PCI_IOV
2a3abf6d
AD		 179static unsigned int max_vfs = 0;
180module_param(max_vfs, uint, 0);
181MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
182 "per physical function");
183#endif /* CONFIG_PCI_IOV */
184
9d5c8243
AK		 185static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
186 pci_channel_state_t);
187static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
188static void igb_io_resume(struct pci_dev *);
189
190static struct pci_error_handlers igb_err_handler = {
191 .error_detected = igb_io_error_detected,
192 .slot_reset = igb_io_slot_reset,
193 .resume = igb_io_resume,
194};
195
196
197static struct pci_driver igb_driver = {
198 .name = igb_driver_name,
199 .id_table = igb_pci_tbl,
200 .probe = igb_probe,
201 .remove = __devexit_p(igb_remove),
202#ifdef CONFIG_PM
203 /* Power Managment Hooks */
204 .suspend = igb_suspend,
205 .resume = igb_resume,
206#endif
207 .shutdown = igb_shutdown,
208 .err_handler = &igb_err_handler
209};
210
211MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
212MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
213MODULE_LICENSE("GPL");
214MODULE_VERSION(DRV_VERSION);
215
c97ec42a
TI		 216struct igb_reg_info {
217 u32 ofs;
218 char *name;
219};
220
221static const struct igb_reg_info igb_reg_info_tbl[] = {
222
223 /* General Registers */
224 {E1000_CTRL, "CTRL"},
225 {E1000_STATUS, "STATUS"},
226 {E1000_CTRL_EXT, "CTRL_EXT"},
227
228 /* Interrupt Registers */
229 {E1000_ICR, "ICR"},
230
231 /* RX Registers */
232 {E1000_RCTL, "RCTL"},
233 {E1000_RDLEN(0), "RDLEN"},
234 {E1000_RDH(0), "RDH"},
235 {E1000_RDT(0), "RDT"},
236 {E1000_RXDCTL(0), "RXDCTL"},
237 {E1000_RDBAL(0), "RDBAL"},
238 {E1000_RDBAH(0), "RDBAH"},
239
240 /* TX Registers */
241 {E1000_TCTL, "TCTL"},
242 {E1000_TDBAL(0), "TDBAL"},
243 {E1000_TDBAH(0), "TDBAH"},
244 {E1000_TDLEN(0), "TDLEN"},
245 {E1000_TDH(0), "TDH"},
246 {E1000_TDT(0), "TDT"},
247 {E1000_TXDCTL(0), "TXDCTL"},
248 {E1000_TDFH, "TDFH"},
249 {E1000_TDFT, "TDFT"},
250 {E1000_TDFHS, "TDFHS"},
251 {E1000_TDFPC, "TDFPC"},
252
253 /* List Terminator */
254 {}
255};
256
257/*
258 * igb_regdump - register printout routine
259 */
260static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
261{
262 int n = 0;
263 char rname[16];
264 u32 regs[8];
265
266 switch (reginfo->ofs) {
267 case E1000_RDLEN(0):
268 for (n = 0; n < 4; n++)
269 regs[n] = rd32(E1000_RDLEN(n));
270 break;
271 case E1000_RDH(0):
272 for (n = 0; n < 4; n++)
273 regs[n] = rd32(E1000_RDH(n));
274 break;
275 case E1000_RDT(0):
276 for (n = 0; n < 4; n++)
277 regs[n] = rd32(E1000_RDT(n));
278 break;
279 case E1000_RXDCTL(0):
280 for (n = 0; n < 4; n++)
281 regs[n] = rd32(E1000_RXDCTL(n));
282 break;
283 case E1000_RDBAL(0):
284 for (n = 0; n < 4; n++)
285 regs[n] = rd32(E1000_RDBAL(n));
286 break;
287 case E1000_RDBAH(0):
288 for (n = 0; n < 4; n++)
289 regs[n] = rd32(E1000_RDBAH(n));
290 break;
291 case E1000_TDBAL(0):
292 for (n = 0; n < 4; n++)
293 regs[n] = rd32(E1000_RDBAL(n));
294 break;
295 case E1000_TDBAH(0):
296 for (n = 0; n < 4; n++)
297 regs[n] = rd32(E1000_TDBAH(n));
298 break;
299 case E1000_TDLEN(0):
300 for (n = 0; n < 4; n++)
301 regs[n] = rd32(E1000_TDLEN(n));
302 break;
303 case E1000_TDH(0):
304 for (n = 0; n < 4; n++)
305 regs[n] = rd32(E1000_TDH(n));
306 break;
307 case E1000_TDT(0):
308 for (n = 0; n < 4; n++)
309 regs[n] = rd32(E1000_TDT(n));
310 break;
311 case E1000_TXDCTL(0):
312 for (n = 0; n < 4; n++)
313 regs[n] = rd32(E1000_TXDCTL(n));
314 break;
315 default:
316 printk(KERN_INFO "%-15s %08x\n",
317 reginfo->name, rd32(reginfo->ofs));
318 return;
319 }
320
321 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
322 printk(KERN_INFO "%-15s ", rname);
323 for (n = 0; n < 4; n++)
324 printk(KERN_CONT "%08x ", regs[n]);
325 printk(KERN_CONT "\n");
326}
327
328/*
329 * igb_dump - Print registers, tx-rings and rx-rings
330 */
331static void igb_dump(struct igb_adapter *adapter)
332{
333 struct net_device *netdev = adapter->netdev;
334 struct e1000_hw *hw = &adapter->hw;
335 struct igb_reg_info *reginfo;
336 int n = 0;
337 struct igb_ring *tx_ring;
338 union e1000_adv_tx_desc *tx_desc;
339 struct my_u0 { u64 a; u64 b; } *u0;
340 struct igb_buffer *buffer_info;
341 struct igb_ring *rx_ring;
342 union e1000_adv_rx_desc *rx_desc;
343 u32 staterr;
344 int i = 0;
345
346 if (!netif_msg_hw(adapter))
347 return;
348
349 /* Print netdevice Info */
350 if (netdev) {
351 dev_info(&adapter->pdev->dev, "Net device Info\n");
352 printk(KERN_INFO "Device Name state "
353 "trans_start last_rx\n");
354 printk(KERN_INFO "%-15s %016lX %016lX %016lX\n",
355 netdev->name,
356 netdev->state,
357 netdev->trans_start,
358 netdev->last_rx);
359 }
360
361 /* Print Registers */
362 dev_info(&adapter->pdev->dev, "Register Dump\n");
363 printk(KERN_INFO " Register Name Value\n");
364 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
365 reginfo->name; reginfo++) {
366 igb_regdump(hw, reginfo);
367 }
368
369 /* Print TX Ring Summary */
370 if (!netdev || !netif_running(netdev))
371 goto exit;
372
373 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
374 printk(KERN_INFO "Queue [NTU] [NTC] [bi(ntc)->dma ]"
375 " leng ntw timestamp\n");
376 for (n = 0; n < adapter->num_tx_queues; n++) {
377 tx_ring = adapter->tx_ring[n];
378 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean];
379 printk(KERN_INFO " %5d %5X %5X %016llX %04X %3X %016llX\n",
380 n, tx_ring->next_to_use, tx_ring->next_to_clean,
381 (u64)buffer_info->dma,
382 buffer_info->length,
383 buffer_info->next_to_watch,
384 (u64)buffer_info->time_stamp);
385 }
386
387 /* Print TX Rings */
388 if (!netif_msg_tx_done(adapter))
389 goto rx_ring_summary;
390
391 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
392
393 /* Transmit Descriptor Formats
394 *
395 * Advanced Transmit Descriptor
396 * +--------------------------------------------------------------+
397 * 0 | Buffer Address [63:0] |
398 * +--------------------------------------------------------------+
399 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
400 * +--------------------------------------------------------------+
401 * 63 46 45 40 39 38 36 35 32 31 24 15 0
402 */
403
404 for (n = 0; n < adapter->num_tx_queues; n++) {
405 tx_ring = adapter->tx_ring[n];
406 printk(KERN_INFO "------------------------------------\n");
407 printk(KERN_INFO "TX QUEUE INDEX = %d\n", tx_ring->queue_index);
408 printk(KERN_INFO "------------------------------------\n");
409 printk(KERN_INFO "T [desc] [address 63:0 ] "
410 "[PlPOCIStDDM Ln] [bi->dma ] "
411 "leng ntw timestamp bi->skb\n");
412
413 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
414 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
415 buffer_info = &tx_ring->buffer_info[i];
416 u0 = (struct my_u0 *)tx_desc;
417 printk(KERN_INFO "T [0x%03X] %016llX %016llX %016llX"
418 " %04X %3X %016llX %p", i,
419 le64_to_cpu(u0->a),
420 le64_to_cpu(u0->b),
421 (u64)buffer_info->dma,
422 buffer_info->length,
423 buffer_info->next_to_watch,
424 (u64)buffer_info->time_stamp,
425 buffer_info->skb);
426 if (i == tx_ring->next_to_use &&
427 i == tx_ring->next_to_clean)
428 printk(KERN_CONT " NTC/U\n");
429 else if (i == tx_ring->next_to_use)
430 printk(KERN_CONT " NTU\n");
431 else if (i == tx_ring->next_to_clean)
432 printk(KERN_CONT " NTC\n");
433 else
434 printk(KERN_CONT "\n");
435
436 if (netif_msg_pktdata(adapter) && buffer_info->dma != 0)
437 print_hex_dump(KERN_INFO, "",
438 DUMP_PREFIX_ADDRESS,
439 16, 1, phys_to_virt(buffer_info->dma),
440 buffer_info->length, true);
441 }
442 }
443
444 /* Print RX Rings Summary */
445rx_ring_summary:
446 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
447 printk(KERN_INFO "Queue [NTU] [NTC]\n");
448 for (n = 0; n < adapter->num_rx_queues; n++) {
449 rx_ring = adapter->rx_ring[n];
450 printk(KERN_INFO " %5d %5X %5X\n", n,
451 rx_ring->next_to_use, rx_ring->next_to_clean);
452 }
453
454 /* Print RX Rings */
455 if (!netif_msg_rx_status(adapter))
456 goto exit;
457
458 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
459
460 /* Advanced Receive Descriptor (Read) Format
461 * 63 1 0
462 * +-----------------------------------------------------+
463 * 0 | Packet Buffer Address [63:1] |A0/NSE|
464 * +----------------------------------------------+------+
465 * 8 | Header Buffer Address [63:1] | DD |
466 * +-----------------------------------------------------+
467 *
468 *
469 * Advanced Receive Descriptor (Write-Back) Format
470 *
471 * 63 48 47 32 31 30 21 20 17 16 4 3 0
472 * +------------------------------------------------------+
473 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
474 * | Checksum Ident | | | | Type | Type |
475 * +------------------------------------------------------+
476 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
477 * +------------------------------------------------------+
478 * 63 48 47 32 31 20 19 0
479 */
480
481 for (n = 0; n < adapter->num_rx_queues; n++) {
482 rx_ring = adapter->rx_ring[n];
483 printk(KERN_INFO "------------------------------------\n");
484 printk(KERN_INFO "RX QUEUE INDEX = %d\n", rx_ring->queue_index);
485 printk(KERN_INFO "------------------------------------\n");
486 printk(KERN_INFO "R [desc] [ PktBuf A0] "
487 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
488 "<-- Adv Rx Read format\n");
489 printk(KERN_INFO "RWB[desc] [PcsmIpSHl PtRs] "
490 "[vl er S cks ln] ---------------- [bi->skb] "
491 "<-- Adv Rx Write-Back format\n");
492
493 for (i = 0; i < rx_ring->count; i++) {
494 buffer_info = &rx_ring->buffer_info[i];
495 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
496 u0 = (struct my_u0 *)rx_desc;
497 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
498 if (staterr & E1000_RXD_STAT_DD) {
499 /* Descriptor Done */
500 printk(KERN_INFO "RWB[0x%03X] %016llX "
501 "%016llX ---------------- %p", i,
502 le64_to_cpu(u0->a),
503 le64_to_cpu(u0->b),
504 buffer_info->skb);
505 } else {
506 printk(KERN_INFO "R [0x%03X] %016llX "
507 "%016llX %016llX %p", i,
508 le64_to_cpu(u0->a),
509 le64_to_cpu(u0->b),
510 (u64)buffer_info->dma,
511 buffer_info->skb);
512
513 if (netif_msg_pktdata(adapter)) {
514 print_hex_dump(KERN_INFO, "",
515 DUMP_PREFIX_ADDRESS,
516 16, 1,
517 phys_to_virt(buffer_info->dma),
518 rx_ring->rx_buffer_len, true);
519 if (rx_ring->rx_buffer_len
520 < IGB_RXBUFFER_1024)
521 print_hex_dump(KERN_INFO, "",
522 DUMP_PREFIX_ADDRESS,
523 16, 1,
524 phys_to_virt(
525 buffer_info->page_dma +
526 buffer_info->page_offset),
527 PAGE_SIZE/2, true);
528 }
529 }
530
531 if (i == rx_ring->next_to_use)
532 printk(KERN_CONT " NTU\n");
533 else if (i == rx_ring->next_to_clean)
534 printk(KERN_CONT " NTC\n");
535 else
536 printk(KERN_CONT "\n");
537
538 }
539 }
540
541exit:
542 return;
543}
544
545
38c845c7
PO		 546/**
547 * igb_read_clock - read raw cycle counter (to be used by time counter)
548 */
549static cycle_t igb_read_clock(const struct cyclecounter *tc)
550{
551 struct igb_adapter *adapter =
552 container_of(tc, struct igb_adapter, cycles);
553 struct e1000_hw *hw = &adapter->hw;
c5b9bd5e
AD		 554 u64 stamp = 0;
555 int shift = 0;
38c845c7 556
55cac248
AD		 557 /*
558 * The timestamp latches on lowest register read. For the 82580
559 * the lowest register is SYSTIMR instead of SYSTIML. However we never
560 * adjusted TIMINCA so SYSTIMR will just read as all 0s so ignore it.
561 */
562 if (hw->mac.type == e1000_82580) {
563 stamp = rd32(E1000_SYSTIMR) >> 8;
564 shift = IGB_82580_TSYNC_SHIFT;
565 }
566
c5b9bd5e
AD		 567 stamp |= (u64)rd32(E1000_SYSTIML) << shift;
568 stamp |= (u64)rd32(E1000_SYSTIMH) << (shift + 32);
38c845c7
PO		 569 return stamp;
570}
571
9d5c8243 572/**
c041076a 573 * igb_get_hw_dev - return device
9d5c8243
AK		 574 * used by hardware layer to print debugging information
575 **/
c041076a 576struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
9d5c8243
AK		 577{
578 struct igb_adapter *adapter = hw->back;
c041076a 579 return adapter->netdev;
9d5c8243 580}
38c845c7 581
9d5c8243
AK		 582/**
583 * igb_init_module - Driver Registration Routine
584 *
585 * igb_init_module is the first routine called when the driver is
586 * loaded. All it does is register with the PCI subsystem.
587 **/
588static int __init igb_init_module(void)
589{
590 int ret;
591 printk(KERN_INFO "%s - version %s\n",
592 igb_driver_string, igb_driver_version);
593
594 printk(KERN_INFO "%s\n", igb_copyright);
595
421e02f0 596#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 597 dca_register_notify(&dca_notifier);
598#endif
bbd98fe4 599 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 600 return ret;
601}
602
603module_init(igb_init_module);
604
605/**
606 * igb_exit_module - Driver Exit Cleanup Routine
607 *
608 * igb_exit_module is called just before the driver is removed
609 * from memory.
610 **/
611static void __exit igb_exit_module(void)
612{
421e02f0 613#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 614 dca_unregister_notify(&dca_notifier);
615#endif
9d5c8243
AK		 616 pci_unregister_driver(&igb_driver);
617}
618
619module_exit(igb_exit_module);
620
26bc19ec
AD		 621#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
622/**
623 * igb_cache_ring_register - Descriptor ring to register mapping
624 * @adapter: board private structure to initialize
625 *
626 * Once we know the feature-set enabled for the device, we'll cache
627 * the register offset the descriptor ring is assigned to.
628 **/
629static void igb_cache_ring_register(struct igb_adapter *adapter)
630{
ee1b9f06 631 int i = 0, j = 0;
047e0030 632 u32 rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 633
634 switch (adapter->hw.mac.type) {
635 case e1000_82576:
636 /* The queues are allocated for virtualization such that VF 0
637 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
638 * In order to avoid collision we start at the first free queue
639 * and continue consuming queues in the same sequence
640 */
ee1b9f06 641 if (adapter->vfs_allocated_count) {
a99955fc 642 for (; i < adapter->rss_queues; i++)
3025a446
AD		 643 adapter->rx_ring[i]->reg_idx = rbase_offset +
644 Q_IDX_82576(i);
ee1b9f06 645 }
26bc19ec 646 case e1000_82575:
55cac248 647 case e1000_82580:
d2ba2ed8 648 case e1000_i350:
26bc19ec 649 default:
ee1b9f06 650 for (; i < adapter->num_rx_queues; i++)
3025a446 651 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
ee1b9f06 652 for (; j < adapter->num_tx_queues; j++)
3025a446 653 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
26bc19ec
AD		 654 break;
655 }
656}
657
047e0030
AD		 658static void igb_free_queues(struct igb_adapter *adapter)
659{
3025a446 660 int i;
047e0030 661
3025a446
AD		 662 for (i = 0; i < adapter->num_tx_queues; i++) {
663 kfree(adapter->tx_ring[i]);
664 adapter->tx_ring[i] = NULL;
665 }
666 for (i = 0; i < adapter->num_rx_queues; i++) {
667 kfree(adapter->rx_ring[i]);
668 adapter->rx_ring[i] = NULL;
669 }
047e0030
AD		 670 adapter->num_rx_queues = 0;
671 adapter->num_tx_queues = 0;
672}
673
9d5c8243
AK		 674/**
675 * igb_alloc_queues - Allocate memory for all rings
676 * @adapter: board private structure to initialize
677 *
678 * We allocate one ring per queue at run-time since we don't know the
679 * number of queues at compile-time.
680 **/
681static int igb_alloc_queues(struct igb_adapter *adapter)
682{
3025a446 683 struct igb_ring *ring;
9d5c8243
AK		 684 int i;
685
661086df 686 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446
AD		 687 ring = kzalloc(sizeof(struct igb_ring), GFP_KERNEL);
688 if (!ring)
689 goto err;
68fd9910 690 ring->count = adapter->tx_ring_count;
661086df 691 ring->queue_index = i;
59d71989 692 ring->dev = &adapter->pdev->dev;
e694e964 693 ring->netdev = adapter->netdev;
85ad76b2
AD		 694 /* For 82575, context index must be unique per ring. */
695 if (adapter->hw.mac.type == e1000_82575)
696 ring->flags = IGB_RING_FLAG_TX_CTX_IDX;
3025a446 697 adapter->tx_ring[i] = ring;
661086df 698 }
85ad76b2 699
9d5c8243 700 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446
AD		 701 ring = kzalloc(sizeof(struct igb_ring), GFP_KERNEL);
702 if (!ring)
703 goto err;
68fd9910 704 ring->count = adapter->rx_ring_count;
844290e5 705 ring->queue_index = i;
59d71989 706 ring->dev = &adapter->pdev->dev;
e694e964 707 ring->netdev = adapter->netdev;
4c844851 708 ring->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
85ad76b2
AD		 709 ring->flags = IGB_RING_FLAG_RX_CSUM; /* enable rx checksum */
710 /* set flag indicating ring supports SCTP checksum offload */
711 if (adapter->hw.mac.type >= e1000_82576)
712 ring->flags |= IGB_RING_FLAG_RX_SCTP_CSUM;
3025a446 713 adapter->rx_ring[i] = ring;
9d5c8243 714 }
26bc19ec
AD		 715
716 igb_cache_ring_register(adapter);
9d5c8243 717
047e0030 718 return 0;
a88f10ec 719
047e0030
AD		 720err:
721 igb_free_queues(adapter);
d1a8c9e1 722
047e0030 723 return -ENOMEM;
a88f10ec
AD		 724}
725
9d5c8243 726#define IGB_N0_QUEUE -1
047e0030 727static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
9d5c8243
AK		 728{
729 u32 msixbm = 0;
047e0030 730 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 731 struct e1000_hw *hw = &adapter->hw;
2d064c06 732 u32 ivar, index;
047e0030
AD		 733 int rx_queue = IGB_N0_QUEUE;
734 int tx_queue = IGB_N0_QUEUE;
735
736 if (q_vector->rx_ring)
737 rx_queue = q_vector->rx_ring->reg_idx;
738 if (q_vector->tx_ring)
739 tx_queue = q_vector->tx_ring->reg_idx;
2d064c06
AD		 740
741 switch (hw->mac.type) {
742 case e1000_82575:
9d5c8243
AK		 743 /* The 82575 assigns vectors using a bitmask, which matches the
744 bitmask for the EICR/EIMS/EIMC registers. To assign one
745 or more queues to a vector, we write the appropriate bits
746 into the MSIXBM register for that vector. */
047e0030 747 if (rx_queue > IGB_N0_QUEUE)
9d5c8243 748 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
047e0030 749 if (tx_queue > IGB_N0_QUEUE)
9d5c8243 750 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
feeb2721
AD		 751 if (!adapter->msix_entries && msix_vector == 0)
752 msixbm |= E1000_EIMS_OTHER;
9d5c8243 753 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
047e0030 754 q_vector->eims_value = msixbm;
2d064c06
AD		 755 break;
756 case e1000_82576:
26bc19ec 757 /* 82576 uses a table-based method for assigning vectors.
2d064c06
AD		 758 Each queue has a single entry in the table to which we write
759 a vector number along with a "valid" bit. Sadly, the layout
760 of the table is somewhat counterintuitive. */
761 if (rx_queue > IGB_N0_QUEUE) {
047e0030 762 index = (rx_queue & 0x7);
2d064c06 763 ivar = array_rd32(E1000_IVAR0, index);
047e0030 764 if (rx_queue < 8) {
26bc19ec
AD		 765 /* vector goes into low byte of register */
766 ivar = ivar & 0xFFFFFF00;
767 ivar |= msix_vector | E1000_IVAR_VALID;
047e0030
AD		 768 } else {
769 /* vector goes into third byte of register */
770 ivar = ivar & 0xFF00FFFF;
771 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
2d064c06 772 }
2d064c06
AD		 773 array_wr32(E1000_IVAR0, index, ivar);
774 }
775 if (tx_queue > IGB_N0_QUEUE) {
047e0030 776 index = (tx_queue & 0x7);
2d064c06 777 ivar = array_rd32(E1000_IVAR0, index);
047e0030 778 if (tx_queue < 8) {
26bc19ec
AD		 779 /* vector goes into second byte of register */
780 ivar = ivar & 0xFFFF00FF;
781 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
047e0030
AD		 782 } else {
783 /* vector goes into high byte of register */
784 ivar = ivar & 0x00FFFFFF;
785 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
2d064c06 786 }
2d064c06
AD		 787 array_wr32(E1000_IVAR0, index, ivar);
788 }
047e0030 789 q_vector->eims_value = 1 << msix_vector;
2d064c06 790 break;
55cac248 791 case e1000_82580:
d2ba2ed8 792 case e1000_i350:
55cac248
AD		 793 /* 82580 uses the same table-based approach as 82576 but has fewer
794 entries as a result we carry over for queues greater than 4. */
795 if (rx_queue > IGB_N0_QUEUE) {
796 index = (rx_queue >> 1);
797 ivar = array_rd32(E1000_IVAR0, index);
798 if (rx_queue & 0x1) {
799 /* vector goes into third byte of register */
800 ivar = ivar & 0xFF00FFFF;
801 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
802 } else {
803 /* vector goes into low byte of register */
804 ivar = ivar & 0xFFFFFF00;
805 ivar |= msix_vector | E1000_IVAR_VALID;
806 }
807 array_wr32(E1000_IVAR0, index, ivar);
808 }
809 if (tx_queue > IGB_N0_QUEUE) {
810 index = (tx_queue >> 1);
811 ivar = array_rd32(E1000_IVAR0, index);
812 if (tx_queue & 0x1) {
813 /* vector goes into high byte of register */
814 ivar = ivar & 0x00FFFFFF;
815 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
816 } else {
817 /* vector goes into second byte of register */
818 ivar = ivar & 0xFFFF00FF;
819 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
820 }
821 array_wr32(E1000_IVAR0, index, ivar);
822 }
823 q_vector->eims_value = 1 << msix_vector;
824 break;
2d064c06
AD		 825 default:
826 BUG();
827 break;
828 }
26b39276
AD		 829
830 /* add q_vector eims value to global eims_enable_mask */
831 adapter->eims_enable_mask |= q_vector->eims_value;
832
833 /* configure q_vector to set itr on first interrupt */
834 q_vector->set_itr = 1;
9d5c8243
AK		 835}
836
837/**
838 * igb_configure_msix - Configure MSI-X hardware
839 *
840 * igb_configure_msix sets up the hardware to properly
841 * generate MSI-X interrupts.
842 **/
843static void igb_configure_msix(struct igb_adapter *adapter)
844{
845 u32 tmp;
846 int i, vector = 0;
847 struct e1000_hw *hw = &adapter->hw;
848
849 adapter->eims_enable_mask = 0;
9d5c8243
AK		 850
851 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 852 switch (hw->mac.type) {
853 case e1000_82575:
9d5c8243
AK		 854 tmp = rd32(E1000_CTRL_EXT);
855 /* enable MSI-X PBA support*/
856 tmp |= E1000_CTRL_EXT_PBA_CLR;
857
858 /* Auto-Mask interrupts upon ICR read. */
859 tmp |= E1000_CTRL_EXT_EIAME;
860 tmp |= E1000_CTRL_EXT_IRCA;
861
862 wr32(E1000_CTRL_EXT, tmp);
047e0030
AD		 863
864 /* enable msix_other interrupt */
865 array_wr32(E1000_MSIXBM(0), vector++,
866 E1000_EIMS_OTHER);
844290e5 867 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 868
2d064c06
AD		 869 break;
870
871 case e1000_82576:
55cac248 872 case e1000_82580:
d2ba2ed8 873 case e1000_i350:
047e0030
AD		 874 /* Turn on MSI-X capability first, or our settings
875 * won't stick. And it will take days to debug. */
876 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
877 E1000_GPIE_PBA | E1000_GPIE_EIAME |
878 E1000_GPIE_NSICR);
879
880 /* enable msix_other interrupt */
881 adapter->eims_other = 1 << vector;
2d064c06 882 tmp = (vector++ | E1000_IVAR_VALID) << 8;
2d064c06 883
047e0030 884 wr32(E1000_IVAR_MISC, tmp);
2d064c06
AD		 885 break;
886 default:
887 /* do nothing, since nothing else supports MSI-X */
888 break;
889 } /* switch (hw->mac.type) */
047e0030
AD		 890
891 adapter->eims_enable_mask |= adapter->eims_other;
892
26b39276
AD		 893 for (i = 0; i < adapter->num_q_vectors; i++)
894 igb_assign_vector(adapter->q_vector[i], vector++);
047e0030 895
9d5c8243
AK		 896 wrfl();
897}
898
899/**
900 * igb_request_msix - Initialize MSI-X interrupts
901 *
902 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
903 * kernel.
904 **/
905static int igb_request_msix(struct igb_adapter *adapter)
906{
907 struct net_device *netdev = adapter->netdev;
047e0030 908 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 909 int i, err = 0, vector = 0;
910
047e0030 911 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 912 igb_msix_other, 0, netdev->name, adapter);
047e0030
AD		 913 if (err)
914 goto out;
915 vector++;
916
917 for (i = 0; i < adapter->num_q_vectors; i++) {
918 struct igb_q_vector *q_vector = adapter->q_vector[i];
919
920 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
921
922 if (q_vector->rx_ring && q_vector->tx_ring)
923 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
924 q_vector->rx_ring->queue_index);
925 else if (q_vector->tx_ring)
926 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
927 q_vector->tx_ring->queue_index);
928 else if (q_vector->rx_ring)
929 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
930 q_vector->rx_ring->queue_index);
9d5c8243 931 else
047e0030
AD		 932 sprintf(q_vector->name, "%s-unused", netdev->name);
933
9d5c8243 934 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 935 igb_msix_ring, 0, q_vector->name,
047e0030 936 q_vector);
9d5c8243
AK		 937 if (err)
938 goto out;
9d5c8243
AK		 939 vector++;
940 }
941
9d5c8243
AK		 942 igb_configure_msix(adapter);
943 return 0;
944out:
945 return err;
946}
947
948static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
949{
950 if (adapter->msix_entries) {
951 pci_disable_msix(adapter->pdev);
952 kfree(adapter->msix_entries);
953 adapter->msix_entries = NULL;
047e0030 954 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243 955 pci_disable_msi(adapter->pdev);
047e0030 956 }
9d5c8243
AK		 957}
958
047e0030
AD		 959/**
960 * igb_free_q_vectors - Free memory allocated for interrupt vectors
961 * @adapter: board private structure to initialize
962 *
963 * This function frees the memory allocated to the q_vectors. In addition if
964 * NAPI is enabled it will delete any references to the NAPI struct prior
965 * to freeing the q_vector.
966 **/
967static void igb_free_q_vectors(struct igb_adapter *adapter)
968{
969 int v_idx;
970
971 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
972 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
973 adapter->q_vector[v_idx] = NULL;
fe0592b4
NN		 974 if (!q_vector)
975 continue;
047e0030
AD		 976 netif_napi_del(&q_vector->napi);
977 kfree(q_vector);
978 }
979 adapter->num_q_vectors = 0;
980}
981
982/**
983 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
984 *
985 * This function resets the device so that it has 0 rx queues, tx queues, and
986 * MSI-X interrupts allocated.
987 */
988static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
989{
990 igb_free_queues(adapter);
991 igb_free_q_vectors(adapter);
992 igb_reset_interrupt_capability(adapter);
993}
9d5c8243
AK		 994
995/**
996 * igb_set_interrupt_capability - set MSI or MSI-X if supported
997 *
998 * Attempt to configure interrupts using the best available
999 * capabilities of the hardware and kernel.
1000 **/
21adef3e 1001static int igb_set_interrupt_capability(struct igb_adapter *adapter)
9d5c8243
AK		 1002{
1003 int err;
1004 int numvecs, i;
1005
83b7180d 1006 /* Number of supported queues. */
a99955fc 1007 adapter->num_rx_queues = adapter->rss_queues;
5fa8517f
GR		 1008 if (adapter->vfs_allocated_count)
1009 adapter->num_tx_queues = 1;
1010 else
1011 adapter->num_tx_queues = adapter->rss_queues;
83b7180d 1012
047e0030
AD		 1013 /* start with one vector for every rx queue */
1014 numvecs = adapter->num_rx_queues;
1015
3ad2f3fb 1016 /* if tx handler is separate add 1 for every tx queue */
a99955fc
AD		 1017 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1018 numvecs += adapter->num_tx_queues;
047e0030
AD		 1019
1020 /* store the number of vectors reserved for queues */
1021 adapter->num_q_vectors = numvecs;
1022
1023 /* add 1 vector for link status interrupts */
1024 numvecs++;
9d5c8243
AK		 1025 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
1026 GFP_KERNEL);
1027 if (!adapter->msix_entries)
1028 goto msi_only;
1029
1030 for (i = 0; i < numvecs; i++)
1031 adapter->msix_entries[i].entry = i;
1032
1033 err = pci_enable_msix(adapter->pdev,
1034 adapter->msix_entries,
1035 numvecs);
1036 if (err == 0)
34a20e89 1037 goto out;
9d5c8243
AK		 1038
1039 igb_reset_interrupt_capability(adapter);
1040
1041 /* If we can't do MSI-X, try MSI */
1042msi_only:
2a3abf6d
AD		 1043#ifdef CONFIG_PCI_IOV
1044 /* disable SR-IOV for non MSI-X configurations */
1045 if (adapter->vf_data) {
1046 struct e1000_hw *hw = &adapter->hw;
1047 /* disable iov and allow time for transactions to clear */
1048 pci_disable_sriov(adapter->pdev);
1049 msleep(500);
1050
1051 kfree(adapter->vf_data);
1052 adapter->vf_data = NULL;
1053 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1054 msleep(100);
1055 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1056 }
1057#endif
4fc82adf 1058 adapter->vfs_allocated_count = 0;
a99955fc 1059 adapter->rss_queues = 1;
4fc82adf 1060 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
9d5c8243 1061 adapter->num_rx_queues = 1;
661086df 1062 adapter->num_tx_queues = 1;
047e0030 1063 adapter->num_q_vectors = 1;
9d5c8243 1064 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 1065 adapter->flags |= IGB_FLAG_HAS_MSI;
34a20e89 1066out:
21adef3e
BH		 1067 /* Notify the stack of the (possibly) reduced queue counts. */
1068 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
1069 return netif_set_real_num_rx_queues(adapter->netdev,
1070 adapter->num_rx_queues);
9d5c8243
AK		 1071}
1072
047e0030
AD		 1073/**
1074 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1075 * @adapter: board private structure to initialize
1076 *
1077 * We allocate one q_vector per queue interrupt. If allocation fails we
1078 * return -ENOMEM.
1079 **/
1080static int igb_alloc_q_vectors(struct igb_adapter *adapter)
1081{
1082 struct igb_q_vector *q_vector;
1083 struct e1000_hw *hw = &adapter->hw;
1084 int v_idx;
1085
1086 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
1087 q_vector = kzalloc(sizeof(struct igb_q_vector), GFP_KERNEL);
1088 if (!q_vector)
1089 goto err_out;
1090 q_vector->adapter = adapter;
047e0030
AD		 1091 q_vector->itr_register = hw->hw_addr + E1000_EITR(0);
1092 q_vector->itr_val = IGB_START_ITR;
047e0030
AD		 1093 netif_napi_add(adapter->netdev, &q_vector->napi, igb_poll, 64);
1094 adapter->q_vector[v_idx] = q_vector;
1095 }
1096 return 0;
1097
1098err_out:
fe0592b4 1099 igb_free_q_vectors(adapter);
047e0030
AD		 1100 return -ENOMEM;
1101}
1102
1103static void igb_map_rx_ring_to_vector(struct igb_adapter *adapter,
1104 int ring_idx, int v_idx)
1105{
3025a446 1106 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
047e0030 1107
3025a446 1108 q_vector->rx_ring = adapter->rx_ring[ring_idx];
047e0030 1109 q_vector->rx_ring->q_vector = q_vector;
4fc82adf
AD		 1110 q_vector->itr_val = adapter->rx_itr_setting;
1111 if (q_vector->itr_val && q_vector->itr_val <= 3)
1112 q_vector->itr_val = IGB_START_ITR;
047e0030
AD		 1113}
1114
1115static void igb_map_tx_ring_to_vector(struct igb_adapter *adapter,
1116 int ring_idx, int v_idx)
1117{
3025a446 1118 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
047e0030 1119
3025a446 1120 q_vector->tx_ring = adapter->tx_ring[ring_idx];
047e0030 1121 q_vector->tx_ring->q_vector = q_vector;
4fc82adf
AD		 1122 q_vector->itr_val = adapter->tx_itr_setting;
1123 if (q_vector->itr_val && q_vector->itr_val <= 3)
1124 q_vector->itr_val = IGB_START_ITR;
047e0030
AD		 1125}
1126
1127/**
1128 * igb_map_ring_to_vector - maps allocated queues to vectors
1129 *
1130 * This function maps the recently allocated queues to vectors.
1131 **/
1132static int igb_map_ring_to_vector(struct igb_adapter *adapter)
1133{
1134 int i;
1135 int v_idx = 0;
1136
1137 if ((adapter->num_q_vectors < adapter->num_rx_queues) ||
1138 (adapter->num_q_vectors < adapter->num_tx_queues))
1139 return -ENOMEM;
1140
1141 if (adapter->num_q_vectors >=
1142 (adapter->num_rx_queues + adapter->num_tx_queues)) {
1143 for (i = 0; i < adapter->num_rx_queues; i++)
1144 igb_map_rx_ring_to_vector(adapter, i, v_idx++);
1145 for (i = 0; i < adapter->num_tx_queues; i++)
1146 igb_map_tx_ring_to_vector(adapter, i, v_idx++);
1147 } else {
1148 for (i = 0; i < adapter->num_rx_queues; i++) {
1149 if (i < adapter->num_tx_queues)
1150 igb_map_tx_ring_to_vector(adapter, i, v_idx);
1151 igb_map_rx_ring_to_vector(adapter, i, v_idx++);
1152 }
1153 for (; i < adapter->num_tx_queues; i++)
1154 igb_map_tx_ring_to_vector(adapter, i, v_idx++);
1155 }
1156 return 0;
1157}
1158
1159/**
1160 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1161 *
1162 * This function initializes the interrupts and allocates all of the queues.
1163 **/
1164static int igb_init_interrupt_scheme(struct igb_adapter *adapter)
1165{
1166 struct pci_dev *pdev = adapter->pdev;
1167 int err;
1168
21adef3e
BH		 1169 err = igb_set_interrupt_capability(adapter);
1170 if (err)
1171 return err;
047e0030
AD		 1172
1173 err = igb_alloc_q_vectors(adapter);
1174 if (err) {
1175 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1176 goto err_alloc_q_vectors;
1177 }
1178
1179 err = igb_alloc_queues(adapter);
1180 if (err) {
1181 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1182 goto err_alloc_queues;
1183 }
1184
1185 err = igb_map_ring_to_vector(adapter);
1186 if (err) {
1187 dev_err(&pdev->dev, "Invalid q_vector to ring mapping\n");
1188 goto err_map_queues;
1189 }
1190
1191
1192 return 0;
1193err_map_queues:
1194 igb_free_queues(adapter);
1195err_alloc_queues:
1196 igb_free_q_vectors(adapter);
1197err_alloc_q_vectors:
1198 igb_reset_interrupt_capability(adapter);
1199 return err;
1200}
1201
9d5c8243
AK		 1202/**
1203 * igb_request_irq - initialize interrupts
1204 *
1205 * Attempts to configure interrupts using the best available
1206 * capabilities of the hardware and kernel.
1207 **/
1208static int igb_request_irq(struct igb_adapter *adapter)
1209{
1210 struct net_device *netdev = adapter->netdev;
047e0030 1211 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 1212 int err = 0;
1213
1214 if (adapter->msix_entries) {
1215 err = igb_request_msix(adapter);
844290e5 1216 if (!err)
9d5c8243 1217 goto request_done;
9d5c8243 1218 /* fall back to MSI */
047e0030 1219 igb_clear_interrupt_scheme(adapter);
9d5c8243 1220 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 1221 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1222 igb_free_all_tx_resources(adapter);
1223 igb_free_all_rx_resources(adapter);
047e0030 1224 adapter->num_tx_queues = 1;
9d5c8243 1225 adapter->num_rx_queues = 1;
047e0030
AD		 1226 adapter->num_q_vectors = 1;
1227 err = igb_alloc_q_vectors(adapter);
1228 if (err) {
1229 dev_err(&pdev->dev,
1230 "Unable to allocate memory for vectors\n");
1231 goto request_done;
1232 }
1233 err = igb_alloc_queues(adapter);
1234 if (err) {
1235 dev_err(&pdev->dev,
1236 "Unable to allocate memory for queues\n");
1237 igb_free_q_vectors(adapter);
1238 goto request_done;
1239 }
1240 igb_setup_all_tx_resources(adapter);
1241 igb_setup_all_rx_resources(adapter);
844290e5 1242 } else {
feeb2721 1243 igb_assign_vector(adapter->q_vector[0], 0);
9d5c8243 1244 }
844290e5 1245
7dfc16fa 1246 if (adapter->flags & IGB_FLAG_HAS_MSI) {
a0607fd3 1247 err = request_irq(adapter->pdev->irq, igb_intr_msi, 0,
047e0030 1248 netdev->name, adapter);
9d5c8243
AK		 1249 if (!err)
1250 goto request_done;
047e0030 1251
9d5c8243
AK		 1252 /* fall back to legacy interrupts */
1253 igb_reset_interrupt_capability(adapter);
7dfc16fa 1254 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1255 }
1256
a0607fd3 1257 err = request_irq(adapter->pdev->irq, igb_intr, IRQF_SHARED,
047e0030 1258 netdev->name, adapter);
9d5c8243 1259
6cb5e577 1260 if (err)
9d5c8243
AK		 1261 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
1262 err);
9d5c8243
AK		 1263
1264request_done:
1265 return err;
1266}
1267
1268static void igb_free_irq(struct igb_adapter *adapter)
1269{
9d5c8243
AK		 1270 if (adapter->msix_entries) {
1271 int vector = 0, i;
1272
047e0030 1273 free_irq(adapter->msix_entries[vector++].vector, adapter);
9d5c8243 1274
047e0030
AD		 1275 for (i = 0; i < adapter->num_q_vectors; i++) {
1276 struct igb_q_vector *q_vector = adapter->q_vector[i];
1277 free_irq(adapter->msix_entries[vector++].vector,
1278 q_vector);
1279 }
1280 } else {
1281 free_irq(adapter->pdev->irq, adapter);
9d5c8243 1282 }
9d5c8243
AK		 1283}
1284
1285/**
1286 * igb_irq_disable - Mask off interrupt generation on the NIC
1287 * @adapter: board private structure
1288 **/
1289static void igb_irq_disable(struct igb_adapter *adapter)
1290{
1291 struct e1000_hw *hw = &adapter->hw;
1292
25568a53
AD		 1293 /*
1294 * we need to be careful when disabling interrupts. The VFs are also
1295 * mapped into these registers and so clearing the bits can cause
1296 * issues on the VF drivers so we only need to clear what we set
1297 */
9d5c8243 1298 if (adapter->msix_entries) {
2dfd1212
AD		 1299 u32 regval = rd32(E1000_EIAM);
1300 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1301 wr32(E1000_EIMC, adapter->eims_enable_mask);
1302 regval = rd32(E1000_EIAC);
1303 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 1304 }
844290e5
PW		 1305
1306 wr32(E1000_IAM, 0);
9d5c8243
AK		 1307 wr32(E1000_IMC, ~0);
1308 wrfl();
81a61859
ET		 1309 if (adapter->msix_entries) {
1310 int i;
1311 for (i = 0; i < adapter->num_q_vectors; i++)
1312 synchronize_irq(adapter->msix_entries[i].vector);
1313 } else {
1314 synchronize_irq(adapter->pdev->irq);
1315 }
9d5c8243
AK		 1316}
1317
1318/**
1319 * igb_irq_enable - Enable default interrupt generation settings
1320 * @adapter: board private structure
1321 **/
1322static void igb_irq_enable(struct igb_adapter *adapter)
1323{
1324 struct e1000_hw *hw = &adapter->hw;
1325
1326 if (adapter->msix_entries) {
25568a53 1327 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC;
2dfd1212
AD		 1328 u32 regval = rd32(E1000_EIAC);
1329 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1330 regval = rd32(E1000_EIAM);
1331 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 1332 wr32(E1000_EIMS, adapter->eims_enable_mask);
25568a53 1333 if (adapter->vfs_allocated_count) {
4ae196df 1334 wr32(E1000_MBVFIMR, 0xFF);
25568a53
AD		 1335 ims |= E1000_IMS_VMMB;
1336 }
55cac248
AD		 1337 if (adapter->hw.mac.type == e1000_82580)
1338 ims |= E1000_IMS_DRSTA;
1339
25568a53 1340 wr32(E1000_IMS, ims);
844290e5 1341 } else {
55cac248
AD		 1342 wr32(E1000_IMS, IMS_ENABLE_MASK |
1343 E1000_IMS_DRSTA);
1344 wr32(E1000_IAM, IMS_ENABLE_MASK |
1345 E1000_IMS_DRSTA);
844290e5 1346 }
9d5c8243
AK		 1347}
1348
1349static void igb_update_mng_vlan(struct igb_adapter *adapter)
1350{
51466239 1351 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1352 u16 vid = adapter->hw.mng_cookie.vlan_id;
1353 u16 old_vid = adapter->mng_vlan_id;
51466239
AD		 1354
1355 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1356 /* add VID to filter table */
1357 igb_vfta_set(hw, vid, true);
1358 adapter->mng_vlan_id = vid;
1359 } else {
1360 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1361 }
1362
1363 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1364 (vid != old_vid) &&
1365 !vlan_group_get_device(adapter->vlgrp, old_vid)) {
1366 /* remove VID from filter table */
1367 igb_vfta_set(hw, old_vid, false);
9d5c8243
AK		 1368 }
1369}
1370
1371/**
1372 * igb_release_hw_control - release control of the h/w to f/w
1373 * @adapter: address of board private structure
1374 *
1375 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1376 * For ASF and Pass Through versions of f/w this means that the
1377 * driver is no longer loaded.
1378 *
1379 **/
1380static void igb_release_hw_control(struct igb_adapter *adapter)
1381{
1382 struct e1000_hw *hw = &adapter->hw;
1383 u32 ctrl_ext;
1384
1385 /* Let firmware take over control of h/w */
1386 ctrl_ext = rd32(E1000_CTRL_EXT);
1387 wr32(E1000_CTRL_EXT,
1388 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1389}
1390
9d5c8243
AK		 1391/**
1392 * igb_get_hw_control - get control of the h/w from f/w
1393 * @adapter: address of board private structure
1394 *
1395 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1396 * For ASF and Pass Through versions of f/w this means that
1397 * the driver is loaded.
1398 *
1399 **/
1400static void igb_get_hw_control(struct igb_adapter *adapter)
1401{
1402 struct e1000_hw *hw = &adapter->hw;
1403 u32 ctrl_ext;
1404
1405 /* Let firmware know the driver has taken over */
1406 ctrl_ext = rd32(E1000_CTRL_EXT);
1407 wr32(E1000_CTRL_EXT,
1408 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1409}
1410
9d5c8243
AK		 1411/**
1412 * igb_configure - configure the hardware for RX and TX
1413 * @adapter: private board structure
1414 **/
1415static void igb_configure(struct igb_adapter *adapter)
1416{
1417 struct net_device *netdev = adapter->netdev;
1418 int i;
1419
1420 igb_get_hw_control(adapter);
ff41f8dc 1421 igb_set_rx_mode(netdev);
9d5c8243
AK		 1422
1423 igb_restore_vlan(adapter);
9d5c8243 1424
85b430b4 1425 igb_setup_tctl(adapter);
06cf2666 1426 igb_setup_mrqc(adapter);
9d5c8243 1427 igb_setup_rctl(adapter);
85b430b4
AD		 1428
1429 igb_configure_tx(adapter);
9d5c8243 1430 igb_configure_rx(adapter);
662d7205
AD		 1431
1432 igb_rx_fifo_flush_82575(&adapter->hw);
1433
c493ea45 1434 /* call igb_desc_unused which always leaves
9d5c8243
AK		 1435 * at least 1 descriptor unused to make sure
1436 * next_to_use != next_to_clean */
1437 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 1438 struct igb_ring *ring = adapter->rx_ring[i];
c493ea45 1439 igb_alloc_rx_buffers_adv(ring, igb_desc_unused(ring));
9d5c8243 1440 }
9d5c8243
AK		 1441}
1442
88a268c1
NN		 1443/**
1444 * igb_power_up_link - Power up the phy/serdes link
1445 * @adapter: address of board private structure
1446 **/
1447void igb_power_up_link(struct igb_adapter *adapter)
1448{
1449 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1450 igb_power_up_phy_copper(&adapter->hw);
1451 else
1452 igb_power_up_serdes_link_82575(&adapter->hw);
1453}
1454
1455/**
1456 * igb_power_down_link - Power down the phy/serdes link
1457 * @adapter: address of board private structure
1458 */
1459static void igb_power_down_link(struct igb_adapter *adapter)
1460{
1461 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1462 igb_power_down_phy_copper_82575(&adapter->hw);
1463 else
1464 igb_shutdown_serdes_link_82575(&adapter->hw);
1465}
9d5c8243
AK		 1466
1467/**
1468 * igb_up - Open the interface and prepare it to handle traffic
1469 * @adapter: board private structure
1470 **/
9d5c8243
AK		 1471int igb_up(struct igb_adapter *adapter)
1472{
1473 struct e1000_hw *hw = &adapter->hw;
1474 int i;
1475
1476 /* hardware has been reset, we need to reload some things */
1477 igb_configure(adapter);
1478
1479 clear_bit(__IGB_DOWN, &adapter->state);
1480
047e0030
AD		 1481 for (i = 0; i < adapter->num_q_vectors; i++) {
1482 struct igb_q_vector *q_vector = adapter->q_vector[i];
1483 napi_enable(&q_vector->napi);
1484 }
844290e5 1485 if (adapter->msix_entries)
9d5c8243 1486 igb_configure_msix(adapter);
feeb2721
AD		 1487 else
1488 igb_assign_vector(adapter->q_vector[0], 0);
9d5c8243
AK		 1489
1490 /* Clear any pending interrupts. */
1491 rd32(E1000_ICR);
1492 igb_irq_enable(adapter);
1493
d4960307
AD		 1494 /* notify VFs that reset has been completed */
1495 if (adapter->vfs_allocated_count) {
1496 u32 reg_data = rd32(E1000_CTRL_EXT);
1497 reg_data |= E1000_CTRL_EXT_PFRSTD;
1498 wr32(E1000_CTRL_EXT, reg_data);
1499 }
1500
4cb9be7a
JB		 1501 netif_tx_start_all_queues(adapter->netdev);
1502
25568a53
AD		 1503 /* start the watchdog. */
1504 hw->mac.get_link_status = 1;
1505 schedule_work(&adapter->watchdog_task);
1506
9d5c8243
AK		 1507 return 0;
1508}
1509
1510void igb_down(struct igb_adapter *adapter)
1511{
9d5c8243 1512 struct net_device *netdev = adapter->netdev;
330a6d6a 1513 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1514 u32 tctl, rctl;
1515 int i;
1516
1517 /* signal that we're down so the interrupt handler does not
1518 * reschedule our watchdog timer */
1519 set_bit(__IGB_DOWN, &adapter->state);
1520
1521 /* disable receives in the hardware */
1522 rctl = rd32(E1000_RCTL);
1523 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1524 /* flush and sleep below */
1525
fd2ea0a7 1526 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1527
1528 /* disable transmits in the hardware */
1529 tctl = rd32(E1000_TCTL);
1530 tctl &= ~E1000_TCTL_EN;
1531 wr32(E1000_TCTL, tctl);
1532 /* flush both disables and wait for them to finish */
1533 wrfl();
1534 msleep(10);
1535
047e0030
AD		 1536 for (i = 0; i < adapter->num_q_vectors; i++) {
1537 struct igb_q_vector *q_vector = adapter->q_vector[i];
1538 napi_disable(&q_vector->napi);
1539 }
9d5c8243 1540
9d5c8243
AK		 1541 igb_irq_disable(adapter);
1542
1543 del_timer_sync(&adapter->watchdog_timer);
1544 del_timer_sync(&adapter->phy_info_timer);
1545
9d5c8243 1546 netif_carrier_off(netdev);
04fe6358
AD		 1547
1548 /* record the stats before reset*/
12dcd86b
ED		 1549 spin_lock(&adapter->stats64_lock);
1550 igb_update_stats(adapter, &adapter->stats64);
1551 spin_unlock(&adapter->stats64_lock);
04fe6358 1552
9d5c8243
AK		 1553 adapter->link_speed = 0;
1554 adapter->link_duplex = 0;
1555
3023682e
JK		 1556 if (!pci_channel_offline(adapter->pdev))
1557 igb_reset(adapter);
9d5c8243
AK		 1558 igb_clean_all_tx_rings(adapter);
1559 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1560#ifdef CONFIG_IGB_DCA
1561
1562 /* since we reset the hardware DCA settings were cleared */
1563 igb_setup_dca(adapter);
1564#endif
9d5c8243
AK		 1565}
1566
1567void igb_reinit_locked(struct igb_adapter *adapter)
1568{
1569 WARN_ON(in_interrupt());
1570 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1571 msleep(1);
1572 igb_down(adapter);
1573 igb_up(adapter);
1574 clear_bit(__IGB_RESETTING, &adapter->state);
1575}
1576
1577void igb_reset(struct igb_adapter *adapter)
1578{
090b1795 1579 struct pci_dev *pdev = adapter->pdev;
9d5c8243 1580 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1581 struct e1000_mac_info *mac = &hw->mac;
1582 struct e1000_fc_info *fc = &hw->fc;
9d5c8243
AK		 1583 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
1584 u16 hwm;
1585
1586 /* Repartition Pba for greater than 9k mtu
1587 * To take effect CTRL.RST is required.
1588 */
fa4dfae0 1589 switch (mac->type) {
d2ba2ed8 1590 case e1000_i350:
55cac248
AD		 1591 case e1000_82580:
1592 pba = rd32(E1000_RXPBS);
1593 pba = igb_rxpbs_adjust_82580(pba);
1594 break;
fa4dfae0 1595 case e1000_82576:
d249be54
AD		 1596 pba = rd32(E1000_RXPBS);
1597 pba &= E1000_RXPBS_SIZE_MASK_82576;
fa4dfae0
AD		 1598 break;
1599 case e1000_82575:
1600 default:
1601 pba = E1000_PBA_34K;
1602 break;
2d064c06 1603 }
9d5c8243 1604
2d064c06
AD		 1605 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1606 (mac->type < e1000_82576)) {
9d5c8243
AK		 1607 /* adjust PBA for jumbo frames */
1608 wr32(E1000_PBA, pba);
1609
1610 /* To maintain wire speed transmits, the Tx FIFO should be
1611 * large enough to accommodate two full transmit packets,
1612 * rounded up to the next 1KB and expressed in KB. Likewise,
1613 * the Rx FIFO should be large enough to accommodate at least
1614 * one full receive packet and is similarly rounded up and
1615 * expressed in KB. */
1616 pba = rd32(E1000_PBA);
1617 /* upper 16 bits has Tx packet buffer allocation size in KB */
1618 tx_space = pba >> 16;
1619 /* lower 16 bits has Rx packet buffer allocation size in KB */
1620 pba &= 0xffff;
1621 /* the tx fifo also stores 16 bytes of information about the tx
1622 * but don't include ethernet FCS because hardware appends it */
1623 min_tx_space = (adapter->max_frame_size +
85e8d004 1624 sizeof(union e1000_adv_tx_desc) -
9d5c8243
AK		 1625 ETH_FCS_LEN) * 2;
1626 min_tx_space = ALIGN(min_tx_space, 1024);
1627 min_tx_space >>= 10;
1628 /* software strips receive CRC, so leave room for it */
1629 min_rx_space = adapter->max_frame_size;
1630 min_rx_space = ALIGN(min_rx_space, 1024);
1631 min_rx_space >>= 10;
1632
1633 /* If current Tx allocation is less than the min Tx FIFO size,
1634 * and the min Tx FIFO size is less than the current Rx FIFO
1635 * allocation, take space away from current Rx allocation */
1636 if (tx_space < min_tx_space &&
1637 ((min_tx_space - tx_space) < pba)) {
1638 pba = pba - (min_tx_space - tx_space);
1639
1640 /* if short on rx space, rx wins and must trump tx
1641 * adjustment */
1642 if (pba < min_rx_space)
1643 pba = min_rx_space;
1644 }
2d064c06 1645 wr32(E1000_PBA, pba);
9d5c8243 1646 }
9d5c8243
AK		 1647
1648 /* flow control settings */
1649 /* The high water mark must be low enough to fit one full frame
1650 * (or the size used for early receive) above it in the Rx FIFO.
1651 * Set it to the lower of:
1652 * - 90% of the Rx FIFO size, or
1653 * - the full Rx FIFO size minus one full frame */
1654 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1655 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1656
d405ea3e
AD		 1657 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1658 fc->low_water = fc->high_water - 16;
9d5c8243
AK		 1659 fc->pause_time = 0xFFFF;
1660 fc->send_xon = 1;
0cce119a 1661 fc->current_mode = fc->requested_mode;
9d5c8243 1662
4ae196df
AD		 1663 /* disable receive for all VFs and wait one second */
1664 if (adapter->vfs_allocated_count) {
1665 int i;
1666 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
8fa7e0f7 1667 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
4ae196df
AD		 1668
1669 /* ping all the active vfs to let them know we are going down */
f2ca0dbe 1670 igb_ping_all_vfs(adapter);
4ae196df
AD		 1671
1672 /* disable transmits and receives */
1673 wr32(E1000_VFRE, 0);
1674 wr32(E1000_VFTE, 0);
1675 }
1676
9d5c8243 1677 /* Allow time for pending master requests to run */
330a6d6a 1678 hw->mac.ops.reset_hw(hw);
9d5c8243
AK		 1679 wr32(E1000_WUC, 0);
1680
330a6d6a 1681 if (hw->mac.ops.init_hw(hw))
090b1795 1682 dev_err(&pdev->dev, "Hardware Error\n");
831ec0b4
CW		 1683 if (hw->mac.type > e1000_82580) {
1684 if (adapter->flags & IGB_FLAG_DMAC) {
1685 u32 reg;
1686
1687 /*
1688 * DMA Coalescing high water mark needs to be higher
1689 * than * the * Rx threshold. The Rx threshold is
1690 * currently * pba - 6, so we * should use a high water
1691 * mark of pba * - 4. */
1692 hwm = (pba - 4) << 10;
1693
1694 reg = (((pba-6) << E1000_DMACR_DMACTHR_SHIFT)
1695 & E1000_DMACR_DMACTHR_MASK);
1696
1697 /* transition to L0x or L1 if available..*/
1698 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
1699
1700 /* watchdog timer= +-1000 usec in 32usec intervals */
1701 reg |= (1000 >> 5);
1702 wr32(E1000_DMACR, reg);
1703
1704 /* no lower threshold to disable coalescing(smart fifb)
1705 * -UTRESH=0*/
1706 wr32(E1000_DMCRTRH, 0);
1707
1708 /* set hwm to PBA - 2 * max frame size */
1709 wr32(E1000_FCRTC, hwm);
1710
1711 /*
1712 * This sets the time to wait before requesting tran-
1713 * sition to * low power state to number of usecs needed
1714 * to receive 1 512 * byte frame at gigabit line rate
1715 */
1716 reg = rd32(E1000_DMCTLX);
1717 reg |= IGB_DMCTLX_DCFLUSH_DIS;
1718
1719 /* Delay 255 usec before entering Lx state. */
1720 reg |= 0xFF;
1721 wr32(E1000_DMCTLX, reg);
1722
1723 /* free space in Tx packet buffer to wake from DMAC */
1724 wr32(E1000_DMCTXTH,
1725 (IGB_MIN_TXPBSIZE -
1726 (IGB_TX_BUF_4096 + adapter->max_frame_size))
1727 >> 6);
1728
1729 /* make low power state decision controlled by DMAC */
1730 reg = rd32(E1000_PCIEMISC);
1731 reg |= E1000_PCIEMISC_LX_DECISION;
1732 wr32(E1000_PCIEMISC, reg);
1733 } /* end if IGB_FLAG_DMAC set */
1734 }
55cac248
AD		 1735 if (hw->mac.type == e1000_82580) {
1736 u32 reg = rd32(E1000_PCIEMISC);
1737 wr32(E1000_PCIEMISC,
1738 reg & ~E1000_PCIEMISC_LX_DECISION);
1739 }
88a268c1
NN		 1740 if (!netif_running(adapter->netdev))
1741 igb_power_down_link(adapter);
1742
9d5c8243
AK		 1743 igb_update_mng_vlan(adapter);
1744
1745 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1746 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1747
330a6d6a 1748 igb_get_phy_info(hw);
9d5c8243
AK		 1749}
1750
2e5c6922 1751static const struct net_device_ops igb_netdev_ops = {
559e9c49 1752 .ndo_open = igb_open,
2e5c6922 1753 .ndo_stop = igb_close,
00829823 1754 .ndo_start_xmit = igb_xmit_frame_adv,
12dcd86b 1755 .ndo_get_stats64 = igb_get_stats64,
ff41f8dc
AD		 1756 .ndo_set_rx_mode = igb_set_rx_mode,
1757 .ndo_set_multicast_list = igb_set_rx_mode,
2e5c6922
SH		 1758 .ndo_set_mac_address = igb_set_mac,
1759 .ndo_change_mtu = igb_change_mtu,
1760 .ndo_do_ioctl = igb_ioctl,
1761 .ndo_tx_timeout = igb_tx_timeout,
1762 .ndo_validate_addr = eth_validate_addr,
1763 .ndo_vlan_rx_register = igb_vlan_rx_register,
1764 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1765 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
8151d294
WM		 1766 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
1767 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
1768 .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw,
1769 .ndo_get_vf_config = igb_ndo_get_vf_config,
2e5c6922
SH		 1770#ifdef CONFIG_NET_POLL_CONTROLLER
1771 .ndo_poll_controller = igb_netpoll,
1772#endif
1773};
1774
9d5c8243
AK		 1775/**
1776 * igb_probe - Device Initialization Routine
1777 * @pdev: PCI device information struct
1778 * @ent: entry in igb_pci_tbl
1779 *
1780 * Returns 0 on success, negative on failure
1781 *
1782 * igb_probe initializes an adapter identified by a pci_dev structure.
1783 * The OS initialization, configuring of the adapter private structure,
1784 * and a hardware reset occur.
1785 **/
1786static int __devinit igb_probe(struct pci_dev *pdev,
1787 const struct pci_device_id *ent)
1788{
1789 struct net_device *netdev;
1790 struct igb_adapter *adapter;
1791 struct e1000_hw *hw;
4337e993 1792 u16 eeprom_data = 0;
9835fd73 1793 s32 ret_val;
4337e993 1794 static int global_quad_port_a; /* global quad port a indication */
9d5c8243
AK		 1795 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1796 unsigned long mmio_start, mmio_len;
2d6a5e95 1797 int err, pci_using_dac;
9d5c8243 1798 u16 eeprom_apme_mask = IGB_EEPROM_APME;
9835fd73 1799 u8 part_str[E1000_PBANUM_LENGTH];
9d5c8243 1800
bded64a7
AG		 1801 /* Catch broken hardware that put the wrong VF device ID in
1802 * the PCIe SR-IOV capability.
1803 */
1804 if (pdev->is_virtfn) {
1805 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
1806 pci_name(pdev), pdev->vendor, pdev->device);
1807 return -EINVAL;
1808 }
1809
aed5dec3 1810 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 1811 if (err)
1812 return err;
1813
1814 pci_using_dac = 0;
59d71989 1815 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243 1816 if (!err) {
59d71989 1817 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243
AK		 1818 if (!err)
1819 pci_using_dac = 1;
1820 } else {
59d71989 1821 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243 1822 if (err) {
59d71989 1823 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243
AK		 1824 if (err) {
1825 dev_err(&pdev->dev, "No usable DMA "
1826 "configuration, aborting\n");
1827 goto err_dma;
1828 }
1829 }
1830 }
1831
aed5dec3
AD		 1832 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1833 IORESOURCE_MEM),
1834 igb_driver_name);
9d5c8243
AK		 1835 if (err)
1836 goto err_pci_reg;
1837
19d5afd4 1838 pci_enable_pcie_error_reporting(pdev);
40a914fa 1839
9d5c8243 1840 pci_set_master(pdev);
c682fc23 1841 pci_save_state(pdev);
9d5c8243
AK		 1842
1843 err = -ENOMEM;
1bfaf07b
AD		 1844 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1845 IGB_ABS_MAX_TX_QUEUES);
9d5c8243
AK		 1846 if (!netdev)
1847 goto err_alloc_etherdev;
1848
1849 SET_NETDEV_DEV(netdev, &pdev->dev);
1850
1851 pci_set_drvdata(pdev, netdev);
1852 adapter = netdev_priv(netdev);
1853 adapter->netdev = netdev;
1854 adapter->pdev = pdev;
1855 hw = &adapter->hw;
1856 hw->back = adapter;
1857 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
1858
1859 mmio_start = pci_resource_start(pdev, 0);
1860 mmio_len = pci_resource_len(pdev, 0);
1861
1862 err = -EIO;
28b0759c
AD		 1863 hw->hw_addr = ioremap(mmio_start, mmio_len);
1864 if (!hw->hw_addr)
9d5c8243
AK		 1865 goto err_ioremap;
1866
2e5c6922 1867 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 1868 igb_set_ethtool_ops(netdev);
9d5c8243 1869 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 1870
1871 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1872
1873 netdev->mem_start = mmio_start;
1874 netdev->mem_end = mmio_start + mmio_len;
1875
9d5c8243
AK		 1876 /* PCI config space info */
1877 hw->vendor_id = pdev->vendor;
1878 hw->device_id = pdev->device;
1879 hw->revision_id = pdev->revision;
1880 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1881 hw->subsystem_device_id = pdev->subsystem_device;
1882
9d5c8243
AK		 1883 /* Copy the default MAC, PHY and NVM function pointers */
1884 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1885 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1886 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1887 /* Initialize skew-specific constants */
1888 err = ei->get_invariants(hw);
1889 if (err)
450c87c8 1890 goto err_sw_init;
9d5c8243 1891
450c87c8 1892 /* setup the private structure */
9d5c8243
AK		 1893 err = igb_sw_init(adapter);
1894 if (err)
1895 goto err_sw_init;
1896
1897 igb_get_bus_info_pcie(hw);
1898
1899 hw->phy.autoneg_wait_to_complete = false;
9d5c8243
AK		 1900
1901 /* Copper options */
1902 if (hw->phy.media_type == e1000_media_type_copper) {
1903 hw->phy.mdix = AUTO_ALL_MODES;
1904 hw->phy.disable_polarity_correction = false;
1905 hw->phy.ms_type = e1000_ms_hw_default;
1906 }
1907
1908 if (igb_check_reset_block(hw))
1909 dev_info(&pdev->dev,
1910 "PHY reset is blocked due to SOL/IDER session.\n");
1911
1912 netdev->features = NETIF_F_SG |
7d8eb29e 1913 NETIF_F_IP_CSUM |
9d5c8243
AK		 1914 NETIF_F_HW_VLAN_TX |
1915 NETIF_F_HW_VLAN_RX |
1916 NETIF_F_HW_VLAN_FILTER;
1917
7d8eb29e 1918 netdev->features |= NETIF_F_IPV6_CSUM;
9d5c8243 1919 netdev->features |= NETIF_F_TSO;
9d5c8243 1920 netdev->features |= NETIF_F_TSO6;
5c0999b7 1921 netdev->features |= NETIF_F_GRO;
d3352520 1922
48f29ffc
JK		 1923 netdev->vlan_features |= NETIF_F_TSO;
1924 netdev->vlan_features |= NETIF_F_TSO6;
7d8eb29e 1925 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 1926 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
48f29ffc
JK		 1927 netdev->vlan_features |= NETIF_F_SG;
1928
7b872a55 1929 if (pci_using_dac) {
9d5c8243 1930 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 1931 netdev->vlan_features |= NETIF_F_HIGHDMA;
1932 }
9d5c8243 1933
5b043fb0 1934 if (hw->mac.type >= e1000_82576)
b9473560
JB		 1935 netdev->features |= NETIF_F_SCTP_CSUM;
1936
330a6d6a 1937 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
9d5c8243
AK		 1938
1939 /* before reading the NVM, reset the controller to put the device in a
1940 * known good starting state */
1941 hw->mac.ops.reset_hw(hw);
1942
1943 /* make sure the NVM is good */
4322e561 1944 if (hw->nvm.ops.validate(hw) < 0) {
9d5c8243
AK		 1945 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1946 err = -EIO;
1947 goto err_eeprom;
1948 }
1949
1950 /* copy the MAC address out of the NVM */
1951 if (hw->mac.ops.read_mac_addr(hw))
1952 dev_err(&pdev->dev, "NVM Read Error\n");
1953
1954 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1955 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1956
1957 if (!is_valid_ether_addr(netdev->perm_addr)) {
1958 dev_err(&pdev->dev, "Invalid MAC Address\n");
1959 err = -EIO;
1960 goto err_eeprom;
1961 }
1962
c061b18d 1963 setup_timer(&adapter->watchdog_timer, igb_watchdog,
0e340485 1964 (unsigned long) adapter);
c061b18d 1965 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
0e340485 1966 (unsigned long) adapter);
9d5c8243
AK		 1967
1968 INIT_WORK(&adapter->reset_task, igb_reset_task);
1969 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1970
450c87c8 1971 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 1972 adapter->fc_autoneg = true;
1973 hw->mac.autoneg = true;
1974 hw->phy.autoneg_advertised = 0x2f;
1975
0cce119a
AD		 1976 hw->fc.requested_mode = e1000_fc_default;
1977 hw->fc.current_mode = e1000_fc_default;
9d5c8243 1978
9d5c8243
AK		 1979 igb_validate_mdi_setting(hw);
1980
9d5c8243
AK		 1981 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1982 * enable the ACPI Magic Packet filter
1983 */
1984
a2cf8b6c 1985 if (hw->bus.func == 0)
312c75ae 1986 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
55cac248
AD		 1987 else if (hw->mac.type == e1000_82580)
1988 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
1989 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
1990 &eeprom_data);
a2cf8b6c
AD		 1991 else if (hw->bus.func == 1)
1992 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243
AK		 1993
1994 if (eeprom_data & eeprom_apme_mask)
1995 adapter->eeprom_wol |= E1000_WUFC_MAG;
1996
1997 /* now that we have the eeprom settings, apply the special cases where
1998 * the eeprom may be wrong or the board simply won't support wake on
1999 * lan on a particular port */
2000 switch (pdev->device) {
2001 case E1000_DEV_ID_82575GB_QUAD_COPPER:
2002 adapter->eeprom_wol = 0;
2003 break;
2004 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 2005 case E1000_DEV_ID_82576_FIBER:
2006 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 2007 /* Wake events only supported on port A for dual fiber
2008 * regardless of eeprom setting */
2009 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
2010 adapter->eeprom_wol = 0;
2011 break;
c8ea5ea9 2012 case E1000_DEV_ID_82576_QUAD_COPPER:
d5aa2252 2013 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
c8ea5ea9
AD		 2014 /* if quad port adapter, disable WoL on all but port A */
2015 if (global_quad_port_a != 0)
2016 adapter->eeprom_wol = 0;
2017 else
2018 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2019 /* Reset for multiple quad port adapters */
2020 if (++global_quad_port_a == 4)
2021 global_quad_port_a = 0;
2022 break;
9d5c8243
AK		 2023 }
2024
2025 /* initialize the wol settings based on the eeprom settings */
2026 adapter->wol = adapter->eeprom_wol;
e1b86d84 2027 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
9d5c8243
AK		 2028
2029 /* reset the hardware with the new settings */
2030 igb_reset(adapter);
2031
2032 /* let the f/w know that the h/w is now under the control of the
2033 * driver. */
2034 igb_get_hw_control(adapter);
2035
9d5c8243
AK		 2036 strcpy(netdev->name, "eth%d");
2037 err = register_netdev(netdev);
2038 if (err)
2039 goto err_register;
2040
b168dfc5
JB		 2041 /* carrier off reporting is important to ethtool even BEFORE open */
2042 netif_carrier_off(netdev);
2043
421e02f0 2044#ifdef CONFIG_IGB_DCA
bbd98fe4 2045 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 2046 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 2047 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 2048 igb_setup_dca(adapter);
2049 }
fe4506b6 2050
38c845c7 2051#endif
673b8b70
AB		 2052 /* do hw tstamp init after resetting */
2053 igb_init_hw_timer(adapter);
2054
9d5c8243
AK		 2055 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
2056 /* print bus type/speed/width info */
7c510e4b 2057 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
9d5c8243 2058 netdev->name,
559e9c49 2059 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
ff846f52 2060 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
559e9c49 2061 "unknown"),
59c3de89
AD		 2062 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
2063 (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :
2064 (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" :
2065 "unknown"),
7c510e4b 2066 netdev->dev_addr);
9d5c8243 2067
9835fd73
CW		 2068 ret_val = igb_read_part_string(hw, part_str, E1000_PBANUM_LENGTH);
2069 if (ret_val)
2070 strcpy(part_str, "Unknown");
2071 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
9d5c8243
AK		 2072 dev_info(&pdev->dev,
2073 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
2074 adapter->msix_entries ? "MSI-X" :
7dfc16fa 2075 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243 2076 adapter->num_rx_queues, adapter->num_tx_queues);
09b068d4
CW		 2077 switch (hw->mac.type) {
2078 case e1000_i350:
2079 igb_set_eee_i350(hw);
2080 break;
2081 default:
2082 break;
2083 }
9d5c8243
AK		 2084 return 0;
2085
2086err_register:
2087 igb_release_hw_control(adapter);
2088err_eeprom:
2089 if (!igb_check_reset_block(hw))
f5f4cf08 2090 igb_reset_phy(hw);
9d5c8243
AK		 2091
2092 if (hw->flash_address)
2093 iounmap(hw->flash_address);
9d5c8243 2094err_sw_init:
047e0030 2095 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 2096 iounmap(hw->hw_addr);
2097err_ioremap:
2098 free_netdev(netdev);
2099err_alloc_etherdev:
559e9c49
AD		 2100 pci_release_selected_regions(pdev,
2101 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243
AK		 2102err_pci_reg:
2103err_dma:
2104 pci_disable_device(pdev);
2105 return err;
2106}
2107
2108/**
2109 * igb_remove - Device Removal Routine
2110 * @pdev: PCI device information struct
2111 *
2112 * igb_remove is called by the PCI subsystem to alert the driver
2113 * that it should release a PCI device. The could be caused by a
2114 * Hot-Plug event, or because the driver is going to be removed from
2115 * memory.
2116 **/
2117static void __devexit igb_remove(struct pci_dev *pdev)
2118{
2119 struct net_device *netdev = pci_get_drvdata(pdev);
2120 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 2121 struct e1000_hw *hw = &adapter->hw;
9d5c8243 2122
760141a5
TH		 2123 /*
2124 * The watchdog timer may be rescheduled, so explicitly
2125 * disable watchdog from being rescheduled.
2126 */
9d5c8243
AK		 2127 set_bit(__IGB_DOWN, &adapter->state);
2128 del_timer_sync(&adapter->watchdog_timer);
2129 del_timer_sync(&adapter->phy_info_timer);
2130
760141a5
TH		 2131 cancel_work_sync(&adapter->reset_task);
2132 cancel_work_sync(&adapter->watchdog_task);
9d5c8243 2133
421e02f0 2134#ifdef CONFIG_IGB_DCA
7dfc16fa 2135 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 2136 dev_info(&pdev->dev, "DCA disabled\n");
2137 dca_remove_requester(&pdev->dev);
7dfc16fa 2138 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 2139 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 2140 }
2141#endif
2142
9d5c8243
AK		 2143 /* Release control of h/w to f/w. If f/w is AMT enabled, this
2144 * would have already happened in close and is redundant. */
2145 igb_release_hw_control(adapter);
2146
2147 unregister_netdev(netdev);
2148
047e0030 2149 igb_clear_interrupt_scheme(adapter);
9d5c8243 2150
37680117
AD		 2151#ifdef CONFIG_PCI_IOV
2152 /* reclaim resources allocated to VFs */
2153 if (adapter->vf_data) {
2154 /* disable iov and allow time for transactions to clear */
2155 pci_disable_sriov(pdev);
2156 msleep(500);
2157
2158 kfree(adapter->vf_data);
2159 adapter->vf_data = NULL;
2160 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2161 msleep(100);
2162 dev_info(&pdev->dev, "IOV Disabled\n");
2163 }
2164#endif
559e9c49 2165
28b0759c
AD		 2166 iounmap(hw->hw_addr);
2167 if (hw->flash_address)
2168 iounmap(hw->flash_address);
559e9c49
AD		 2169 pci_release_selected_regions(pdev,
2170 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243
AK		 2171
2172 free_netdev(netdev);
2173
19d5afd4 2174 pci_disable_pcie_error_reporting(pdev);
40a914fa 2175
9d5c8243
AK		 2176 pci_disable_device(pdev);
2177}
2178
a6b623e0
AD		 2179/**
2180 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2181 * @adapter: board private structure to initialize
2182 *
2183 * This function initializes the vf specific data storage and then attempts to
2184 * allocate the VFs. The reason for ordering it this way is because it is much
2185 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2186 * the memory for the VFs.
2187 **/
2188static void __devinit igb_probe_vfs(struct igb_adapter * adapter)
2189{
2190#ifdef CONFIG_PCI_IOV
2191 struct pci_dev *pdev = adapter->pdev;
2192
a6b623e0
AD		 2193 if (adapter->vfs_allocated_count) {
2194 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2195 sizeof(struct vf_data_storage),
2196 GFP_KERNEL);
2197 /* if allocation failed then we do not support SR-IOV */
2198 if (!adapter->vf_data) {
2199 adapter->vfs_allocated_count = 0;
2200 dev_err(&pdev->dev, "Unable to allocate memory for VF "
2201 "Data Storage\n");
2202 }
2203 }
2204
2205 if (pci_enable_sriov(pdev, adapter->vfs_allocated_count)) {
2206 kfree(adapter->vf_data);
2207 adapter->vf_data = NULL;
2208#endif /* CONFIG_PCI_IOV */
2209 adapter->vfs_allocated_count = 0;
2210#ifdef CONFIG_PCI_IOV
2211 } else {
2212 unsigned char mac_addr[ETH_ALEN];
2213 int i;
2214 dev_info(&pdev->dev, "%d vfs allocated\n",
2215 adapter->vfs_allocated_count);
2216 for (i = 0; i < adapter->vfs_allocated_count; i++) {
2217 random_ether_addr(mac_addr);
2218 igb_set_vf_mac(adapter, i, mac_addr);
2219 }
831ec0b4
CW		 2220 /* DMA Coalescing is not supported in IOV mode. */
2221 if (adapter->flags & IGB_FLAG_DMAC)
2222 adapter->flags &= ~IGB_FLAG_DMAC;
a6b623e0
AD		 2223 }
2224#endif /* CONFIG_PCI_IOV */
2225}
2226
115f459a
AD		 2227
2228/**
2229 * igb_init_hw_timer - Initialize hardware timer used with IEEE 1588 timestamp
2230 * @adapter: board private structure to initialize
2231 *
2232 * igb_init_hw_timer initializes the function pointer and values for the hw
2233 * timer found in hardware.
2234 **/
2235static void igb_init_hw_timer(struct igb_adapter *adapter)
2236{
2237 struct e1000_hw *hw = &adapter->hw;
2238
2239 switch (hw->mac.type) {
d2ba2ed8 2240 case e1000_i350:
55cac248
AD		 2241 case e1000_82580:
2242 memset(&adapter->cycles, 0, sizeof(adapter->cycles));
2243 adapter->cycles.read = igb_read_clock;
2244 adapter->cycles.mask = CLOCKSOURCE_MASK(64);
2245 adapter->cycles.mult = 1;
2246 /*
2247 * The 82580 timesync updates the system timer every 8ns by 8ns
2248 * and the value cannot be shifted. Instead we need to shift
2249 * the registers to generate a 64bit timer value. As a result
2250 * SYSTIMR/L/H, TXSTMPL/H, RXSTMPL/H all have to be shifted by
2251 * 24 in order to generate a larger value for synchronization.
2252 */
2253 adapter->cycles.shift = IGB_82580_TSYNC_SHIFT;
2254 /* disable system timer temporarily by setting bit 31 */
2255 wr32(E1000_TSAUXC, 0x80000000);
2256 wrfl();
2257
2258 /* Set registers so that rollover occurs soon to test this. */
2259 wr32(E1000_SYSTIMR, 0x00000000);
2260 wr32(E1000_SYSTIML, 0x80000000);
2261 wr32(E1000_SYSTIMH, 0x000000FF);
2262 wrfl();
2263
2264 /* enable system timer by clearing bit 31 */
2265 wr32(E1000_TSAUXC, 0x0);
2266 wrfl();
2267
2268 timecounter_init(&adapter->clock,
2269 &adapter->cycles,
2270 ktime_to_ns(ktime_get_real()));
2271 /*
2272 * Synchronize our NIC clock against system wall clock. NIC
2273 * time stamp reading requires ~3us per sample, each sample
2274 * was pretty stable even under load => only require 10
2275 * samples for each offset comparison.
2276 */
2277 memset(&adapter->compare, 0, sizeof(adapter->compare));
2278 adapter->compare.source = &adapter->clock;
2279 adapter->compare.target = ktime_get_real;
2280 adapter->compare.num_samples = 10;
2281 timecompare_update(&adapter->compare, 0);
2282 break;
115f459a
AD		 2283 case e1000_82576:
2284 /*
2285 * Initialize hardware timer: we keep it running just in case
2286 * that some program needs it later on.
2287 */
2288 memset(&adapter->cycles, 0, sizeof(adapter->cycles));
2289 adapter->cycles.read = igb_read_clock;
2290 adapter->cycles.mask = CLOCKSOURCE_MASK(64);
2291 adapter->cycles.mult = 1;
2292 /**
2293 * Scale the NIC clock cycle by a large factor so that
2294 * relatively small clock corrections can be added or
2295 * substracted at each clock tick. The drawbacks of a large
2296 * factor are a) that the clock register overflows more quickly
2297 * (not such a big deal) and b) that the increment per tick has
2298 * to fit into 24 bits. As a result we need to use a shift of
2299 * 19 so we can fit a value of 16 into the TIMINCA register.
2300 */
2301 adapter->cycles.shift = IGB_82576_TSYNC_SHIFT;
2302 wr32(E1000_TIMINCA,
2303 (1 << E1000_TIMINCA_16NS_SHIFT) |
2304 (16 << IGB_82576_TSYNC_SHIFT));
2305
2306 /* Set registers so that rollover occurs soon to test this. */
2307 wr32(E1000_SYSTIML, 0x00000000);
2308 wr32(E1000_SYSTIMH, 0xFF800000);
2309 wrfl();
2310
2311 timecounter_init(&adapter->clock,
2312 &adapter->cycles,
2313 ktime_to_ns(ktime_get_real()));
2314 /*
2315 * Synchronize our NIC clock against system wall clock. NIC
2316 * time stamp reading requires ~3us per sample, each sample
2317 * was pretty stable even under load => only require 10
2318 * samples for each offset comparison.
2319 */
2320 memset(&adapter->compare, 0, sizeof(adapter->compare));
2321 adapter->compare.source = &adapter->clock;
2322 adapter->compare.target = ktime_get_real;
2323 adapter->compare.num_samples = 10;
2324 timecompare_update(&adapter->compare, 0);
2325 break;
2326 case e1000_82575:
2327 /* 82575 does not support timesync */
2328 default:
2329 break;
2330 }
2331
2332}
2333
9d5c8243
AK		 2334/**
2335 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2336 * @adapter: board private structure to initialize
2337 *
2338 * igb_sw_init initializes the Adapter private data structure.
2339 * Fields are initialized based on PCI device information and
2340 * OS network device settings (MTU size).
2341 **/
2342static int __devinit igb_sw_init(struct igb_adapter *adapter)
2343{
2344 struct e1000_hw *hw = &adapter->hw;
2345 struct net_device *netdev = adapter->netdev;
2346 struct pci_dev *pdev = adapter->pdev;
2347
2348 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2349
68fd9910
AD		 2350 adapter->tx_ring_count = IGB_DEFAULT_TXD;
2351 adapter->rx_ring_count = IGB_DEFAULT_RXD;
4fc82adf
AD		 2352 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2353 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2354
9d5c8243
AK		 2355 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2356 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2357
12dcd86b 2358 spin_lock_init(&adapter->stats64_lock);
a6b623e0 2359#ifdef CONFIG_PCI_IOV
6b78bb1d
CW		 2360 switch (hw->mac.type) {
2361 case e1000_82576:
2362 case e1000_i350:
9b082d73
SA		 2363 if (max_vfs > 7) {
2364 dev_warn(&pdev->dev,
2365 "Maximum of 7 VFs per PF, using max\n");
2366 adapter->vfs_allocated_count = 7;
2367 } else
2368 adapter->vfs_allocated_count = max_vfs;
6b78bb1d
CW		 2369 break;
2370 default:
2371 break;
2372 }
a6b623e0 2373#endif /* CONFIG_PCI_IOV */
a99955fc
AD		 2374 adapter->rss_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
2375
2376 /*
2377 * if rss_queues > 4 or vfs are going to be allocated with rss_queues
2378 * then we should combine the queues into a queue pair in order to
2379 * conserve interrupts due to limited supply
2380 */
2381 if ((adapter->rss_queues > 4) ||
2382 ((adapter->rss_queues > 1) && (adapter->vfs_allocated_count > 6)))
2383 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2384
a6b623e0 2385 /* This call may decrease the number of queues */
047e0030 2386 if (igb_init_interrupt_scheme(adapter)) {
9d5c8243
AK		 2387 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
2388 return -ENOMEM;
2389 }
2390
a6b623e0
AD		 2391 igb_probe_vfs(adapter);
2392
9d5c8243
AK		 2393 /* Explicitly disable IRQ since the NIC can be in any state. */
2394 igb_irq_disable(adapter);
2395
831ec0b4
CW		 2396 if (hw->mac.type == e1000_i350)
2397 adapter->flags &= ~IGB_FLAG_DMAC;
2398
9d5c8243
AK		 2399 set_bit(__IGB_DOWN, &adapter->state);
2400 return 0;
2401}
2402
2403/**
2404 * igb_open - Called when a network interface is made active
2405 * @netdev: network interface device structure
2406 *
2407 * Returns 0 on success, negative value on failure
2408 *
2409 * The open entry point is called when a network interface is made
2410 * active by the system (IFF_UP). At this point all resources needed
2411 * for transmit and receive operations are allocated, the interrupt
2412 * handler is registered with the OS, the watchdog timer is started,
2413 * and the stack is notified that the interface is ready.
2414 **/
2415static int igb_open(struct net_device *netdev)
2416{
2417 struct igb_adapter *adapter = netdev_priv(netdev);
2418 struct e1000_hw *hw = &adapter->hw;
2419 int err;
2420 int i;
2421
2422 /* disallow open during test */
2423 if (test_bit(__IGB_TESTING, &adapter->state))
2424 return -EBUSY;
2425
b168dfc5
JB		 2426 netif_carrier_off(netdev);
2427
9d5c8243
AK		 2428 /* allocate transmit descriptors */
2429 err = igb_setup_all_tx_resources(adapter);
2430 if (err)
2431 goto err_setup_tx;
2432
2433 /* allocate receive descriptors */
2434 err = igb_setup_all_rx_resources(adapter);
2435 if (err)
2436 goto err_setup_rx;
2437
88a268c1 2438 igb_power_up_link(adapter);
9d5c8243 2439
9d5c8243
AK		 2440 /* before we allocate an interrupt, we must be ready to handle it.
2441 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
2442 * as soon as we call pci_request_irq, so we have to setup our
2443 * clean_rx handler before we do so. */
2444 igb_configure(adapter);
2445
2446 err = igb_request_irq(adapter);
2447 if (err)
2448 goto err_req_irq;
2449
2450 /* From here on the code is the same as igb_up() */
2451 clear_bit(__IGB_DOWN, &adapter->state);
2452
047e0030
AD		 2453 for (i = 0; i < adapter->num_q_vectors; i++) {
2454 struct igb_q_vector *q_vector = adapter->q_vector[i];
2455 napi_enable(&q_vector->napi);
2456 }
9d5c8243
AK		 2457
2458 /* Clear any pending interrupts. */
2459 rd32(E1000_ICR);
844290e5
PW		 2460
2461 igb_irq_enable(adapter);
2462
d4960307
AD		 2463 /* notify VFs that reset has been completed */
2464 if (adapter->vfs_allocated_count) {
2465 u32 reg_data = rd32(E1000_CTRL_EXT);
2466 reg_data |= E1000_CTRL_EXT_PFRSTD;
2467 wr32(E1000_CTRL_EXT, reg_data);
2468 }
2469
d55b53ff
JK		 2470 netif_tx_start_all_queues(netdev);
2471
25568a53
AD		 2472 /* start the watchdog. */
2473 hw->mac.get_link_status = 1;
2474 schedule_work(&adapter->watchdog_task);
9d5c8243
AK		 2475
2476 return 0;
2477
2478err_req_irq:
2479 igb_release_hw_control(adapter);
88a268c1 2480 igb_power_down_link(adapter);
9d5c8243
AK		 2481 igb_free_all_rx_resources(adapter);
2482err_setup_rx:
2483 igb_free_all_tx_resources(adapter);
2484err_setup_tx:
2485 igb_reset(adapter);
2486
2487 return err;
2488}
2489
2490/**
2491 * igb_close - Disables a network interface
2492 * @netdev: network interface device structure
2493 *
2494 * Returns 0, this is not allowed to fail
2495 *
2496 * The close entry point is called when an interface is de-activated
2497 * by the OS. The hardware is still under the driver's control, but
2498 * needs to be disabled. A global MAC reset is issued to stop the
2499 * hardware, and all transmit and receive resources are freed.
2500 **/
2501static int igb_close(struct net_device *netdev)
2502{
2503 struct igb_adapter *adapter = netdev_priv(netdev);
2504
2505 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
2506 igb_down(adapter);
2507
2508 igb_free_irq(adapter);
2509
2510 igb_free_all_tx_resources(adapter);
2511 igb_free_all_rx_resources(adapter);
2512
9d5c8243
AK		 2513 return 0;
2514}
2515
2516/**
2517 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
9d5c8243
AK		 2518 * @tx_ring: tx descriptor ring (for a specific queue) to setup
2519 *
2520 * Return 0 on success, negative on failure
2521 **/
80785298 2522int igb_setup_tx_resources(struct igb_ring *tx_ring)
9d5c8243 2523{
59d71989 2524 struct device *dev = tx_ring->dev;
9d5c8243
AK		 2525 int size;
2526
2527 size = sizeof(struct igb_buffer) * tx_ring->count;
89bf67f1 2528 tx_ring->buffer_info = vzalloc(size);
9d5c8243
AK		 2529 if (!tx_ring->buffer_info)
2530 goto err;
9d5c8243
AK		 2531
2532 /* round up to nearest 4K */
85e8d004 2533 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 2534 tx_ring->size = ALIGN(tx_ring->size, 4096);
2535
59d71989
AD		 2536 tx_ring->desc = dma_alloc_coherent(dev,
2537 tx_ring->size,
2538 &tx_ring->dma,
2539 GFP_KERNEL);
9d5c8243
AK		 2540
2541 if (!tx_ring->desc)
2542 goto err;
2543
9d5c8243
AK		 2544 tx_ring->next_to_use = 0;
2545 tx_ring->next_to_clean = 0;
9d5c8243
AK		 2546 return 0;
2547
2548err:
2549 vfree(tx_ring->buffer_info);
59d71989 2550 dev_err(dev,
9d5c8243
AK		 2551 "Unable to allocate memory for the transmit descriptor ring\n");
2552 return -ENOMEM;
2553}
2554
2555/**
2556 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
2557 * (Descriptors) for all queues
2558 * @adapter: board private structure
2559 *
2560 * Return 0 on success, negative on failure
2561 **/
2562static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
2563{
439705e1 2564 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2565 int i, err = 0;
2566
2567 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 2568 err = igb_setup_tx_resources(adapter->tx_ring[i]);
9d5c8243 2569 if (err) {
439705e1 2570 dev_err(&pdev->dev,
9d5c8243
AK		 2571 "Allocation for Tx Queue %u failed\n", i);
2572 for (i--; i >= 0; i--)
3025a446 2573 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 2574 break;
2575 }
2576 }
2577
a99955fc 2578 for (i = 0; i < IGB_ABS_MAX_TX_QUEUES; i++) {
439705e1 2579 int r_idx = i % adapter->num_tx_queues;
3025a446 2580 adapter->multi_tx_table[i] = adapter->tx_ring[r_idx];
eebbbdba 2581 }
9d5c8243
AK		 2582 return err;
2583}
2584
2585/**
85b430b4
AD		 2586 * igb_setup_tctl - configure the transmit control registers
2587 * @adapter: Board private structure
9d5c8243 2588 **/
d7ee5b3a 2589void igb_setup_tctl(struct igb_adapter *adapter)
9d5c8243 2590{
9d5c8243
AK		 2591 struct e1000_hw *hw = &adapter->hw;
2592 u32 tctl;
9d5c8243 2593
85b430b4
AD		 2594 /* disable queue 0 which is enabled by default on 82575 and 82576 */
2595 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 2596
2597 /* Program the Transmit Control Register */
9d5c8243
AK		 2598 tctl = rd32(E1000_TCTL);
2599 tctl &= ~E1000_TCTL_CT;
2600 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2601 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2602
2603 igb_config_collision_dist(hw);
2604
9d5c8243
AK		 2605 /* Enable transmits */
2606 tctl |= E1000_TCTL_EN;
2607
2608 wr32(E1000_TCTL, tctl);
2609}
2610
85b430b4
AD		 2611/**
2612 * igb_configure_tx_ring - Configure transmit ring after Reset
2613 * @adapter: board private structure
2614 * @ring: tx ring to configure
2615 *
2616 * Configure a transmit ring after a reset.
2617 **/
d7ee5b3a
AD		 2618void igb_configure_tx_ring(struct igb_adapter *adapter,
2619 struct igb_ring *ring)
85b430b4
AD		 2620{
2621 struct e1000_hw *hw = &adapter->hw;
2622 u32 txdctl;
2623 u64 tdba = ring->dma;
2624 int reg_idx = ring->reg_idx;
2625
2626 /* disable the queue */
2627 txdctl = rd32(E1000_TXDCTL(reg_idx));
2628 wr32(E1000_TXDCTL(reg_idx),
2629 txdctl & ~E1000_TXDCTL_QUEUE_ENABLE);
2630 wrfl();
2631 mdelay(10);
2632
2633 wr32(E1000_TDLEN(reg_idx),
2634 ring->count * sizeof(union e1000_adv_tx_desc));
2635 wr32(E1000_TDBAL(reg_idx),
2636 tdba & 0x00000000ffffffffULL);
2637 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
2638
fce99e34
AD		 2639 ring->head = hw->hw_addr + E1000_TDH(reg_idx);
2640 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
2641 writel(0, ring->head);
2642 writel(0, ring->tail);
85b430b4
AD		 2643
2644 txdctl |= IGB_TX_PTHRESH;
2645 txdctl |= IGB_TX_HTHRESH << 8;
2646 txdctl |= IGB_TX_WTHRESH << 16;
2647
2648 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
2649 wr32(E1000_TXDCTL(reg_idx), txdctl);
2650}
2651
2652/**
2653 * igb_configure_tx - Configure transmit Unit after Reset
2654 * @adapter: board private structure
2655 *
2656 * Configure the Tx unit of the MAC after a reset.
2657 **/
2658static void igb_configure_tx(struct igb_adapter *adapter)
2659{
2660 int i;
2661
2662 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 2663 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
85b430b4
AD		 2664}
2665
9d5c8243
AK		 2666/**
2667 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
9d5c8243
AK		 2668 * @rx_ring: rx descriptor ring (for a specific queue) to setup
2669 *
2670 * Returns 0 on success, negative on failure
2671 **/
80785298 2672int igb_setup_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2673{
59d71989 2674 struct device *dev = rx_ring->dev;
9d5c8243
AK		 2675 int size, desc_len;
2676
2677 size = sizeof(struct igb_buffer) * rx_ring->count;
89bf67f1 2678 rx_ring->buffer_info = vzalloc(size);
9d5c8243
AK		 2679 if (!rx_ring->buffer_info)
2680 goto err;
9d5c8243
AK		 2681
2682 desc_len = sizeof(union e1000_adv_rx_desc);
2683
2684 /* Round up to nearest 4K */
2685 rx_ring->size = rx_ring->count * desc_len;
2686 rx_ring->size = ALIGN(rx_ring->size, 4096);
2687
59d71989
AD		 2688 rx_ring->desc = dma_alloc_coherent(dev,
2689 rx_ring->size,
2690 &rx_ring->dma,
2691 GFP_KERNEL);
9d5c8243
AK		 2692
2693 if (!rx_ring->desc)
2694 goto err;
2695
2696 rx_ring->next_to_clean = 0;
2697 rx_ring->next_to_use = 0;
9d5c8243 2698
9d5c8243
AK		 2699 return 0;
2700
2701err:
2702 vfree(rx_ring->buffer_info);
439705e1 2703 rx_ring->buffer_info = NULL;
59d71989
AD		 2704 dev_err(dev, "Unable to allocate memory for the receive descriptor"
2705 " ring\n");
9d5c8243
AK		 2706 return -ENOMEM;
2707}
2708
2709/**
2710 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
2711 * (Descriptors) for all queues
2712 * @adapter: board private structure
2713 *
2714 * Return 0 on success, negative on failure
2715 **/
2716static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
2717{
439705e1 2718 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2719 int i, err = 0;
2720
2721 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 2722 err = igb_setup_rx_resources(adapter->rx_ring[i]);
9d5c8243 2723 if (err) {
439705e1 2724 dev_err(&pdev->dev,
9d5c8243
AK		 2725 "Allocation for Rx Queue %u failed\n", i);
2726 for (i--; i >= 0; i--)
3025a446 2727 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 2728 break;
2729 }
2730 }
2731
2732 return err;
2733}
2734
06cf2666
AD		 2735/**
2736 * igb_setup_mrqc - configure the multiple receive queue control registers
2737 * @adapter: Board private structure
2738 **/
2739static void igb_setup_mrqc(struct igb_adapter *adapter)
2740{
2741 struct e1000_hw *hw = &adapter->hw;
2742 u32 mrqc, rxcsum;
2743 u32 j, num_rx_queues, shift = 0, shift2 = 0;
2744 union e1000_reta {
2745 u32 dword;
2746 u8 bytes[4];
2747 } reta;
2748 static const u8 rsshash[40] = {
2749 0x6d, 0x5a, 0x56, 0xda, 0x25, 0x5b, 0x0e, 0xc2, 0x41, 0x67,
2750 0x25, 0x3d, 0x43, 0xa3, 0x8f, 0xb0, 0xd0, 0xca, 0x2b, 0xcb,
2751 0xae, 0x7b, 0x30, 0xb4, 0x77, 0xcb, 0x2d, 0xa3, 0x80, 0x30,
2752 0xf2, 0x0c, 0x6a, 0x42, 0xb7, 0x3b, 0xbe, 0xac, 0x01, 0xfa };
2753
2754 /* Fill out hash function seeds */
2755 for (j = 0; j < 10; j++) {
2756 u32 rsskey = rsshash[(j * 4)];
2757 rsskey |= rsshash[(j * 4) + 1] << 8;
2758 rsskey |= rsshash[(j * 4) + 2] << 16;
2759 rsskey |= rsshash[(j * 4) + 3] << 24;
2760 array_wr32(E1000_RSSRK(0), j, rsskey);
2761 }
2762
a99955fc 2763 num_rx_queues = adapter->rss_queues;
06cf2666
AD		 2764
2765 if (adapter->vfs_allocated_count) {
2766 /* 82575 and 82576 supports 2 RSS queues for VMDq */
2767 switch (hw->mac.type) {
d2ba2ed8 2768 case e1000_i350:
55cac248
AD		 2769 case e1000_82580:
2770 num_rx_queues = 1;
2771 shift = 0;
2772 break;
06cf2666
AD		 2773 case e1000_82576:
2774 shift = 3;
2775 num_rx_queues = 2;
2776 break;
2777 case e1000_82575:
2778 shift = 2;
2779 shift2 = 6;
2780 default:
2781 break;
2782 }
2783 } else {
2784 if (hw->mac.type == e1000_82575)
2785 shift = 6;
2786 }
2787
2788 for (j = 0; j < (32 * 4); j++) {
2789 reta.bytes[j & 3] = (j % num_rx_queues) << shift;
2790 if (shift2)
2791 reta.bytes[j & 3] |= num_rx_queues << shift2;
2792 if ((j & 3) == 3)
2793 wr32(E1000_RETA(j >> 2), reta.dword);
2794 }
2795
2796 /*
2797 * Disable raw packet checksumming so that RSS hash is placed in
2798 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
2799 * offloads as they are enabled by default
2800 */
2801 rxcsum = rd32(E1000_RXCSUM);
2802 rxcsum |= E1000_RXCSUM_PCSD;
2803
2804 if (adapter->hw.mac.type >= e1000_82576)
2805 /* Enable Receive Checksum Offload for SCTP */
2806 rxcsum |= E1000_RXCSUM_CRCOFL;
2807
2808 /* Don't need to set TUOFL or IPOFL, they default to 1 */
2809 wr32(E1000_RXCSUM, rxcsum);
2810
2811 /* If VMDq is enabled then we set the appropriate mode for that, else
2812 * we default to RSS so that an RSS hash is calculated per packet even
2813 * if we are only using one queue */
2814 if (adapter->vfs_allocated_count) {
2815 if (hw->mac.type > e1000_82575) {
2816 /* Set the default pool for the PF's first queue */
2817 u32 vtctl = rd32(E1000_VT_CTL);
2818 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
2819 E1000_VT_CTL_DISABLE_DEF_POOL);
2820 vtctl |= adapter->vfs_allocated_count <<
2821 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
2822 wr32(E1000_VT_CTL, vtctl);
2823 }
a99955fc 2824 if (adapter->rss_queues > 1)
06cf2666
AD		 2825 mrqc = E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
2826 else
2827 mrqc = E1000_MRQC_ENABLE_VMDQ;
2828 } else {
2829 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
2830 }
2831 igb_vmm_control(adapter);
2832
4478a9cd
AD		 2833 /*
2834 * Generate RSS hash based on TCP port numbers and/or
2835 * IPv4/v6 src and dst addresses since UDP cannot be
2836 * hashed reliably due to IP fragmentation
2837 */
2838 mrqc |= E1000_MRQC_RSS_FIELD_IPV4 |
2839 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2840 E1000_MRQC_RSS_FIELD_IPV6 |
2841 E1000_MRQC_RSS_FIELD_IPV6_TCP |
2842 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
06cf2666
AD		 2843
2844 wr32(E1000_MRQC, mrqc);
2845}
2846
9d5c8243
AK		 2847/**
2848 * igb_setup_rctl - configure the receive control registers
2849 * @adapter: Board private structure
2850 **/
d7ee5b3a 2851void igb_setup_rctl(struct igb_adapter *adapter)
9d5c8243
AK		 2852{
2853 struct e1000_hw *hw = &adapter->hw;
2854 u32 rctl;
9d5c8243
AK		 2855
2856 rctl = rd32(E1000_RCTL);
2857
2858 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 2859 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 2860
69d728ba 2861 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 2862 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 2863
87cb7e8c
AK		 2864 /*
2865 * enable stripping of CRC. It's unlikely this will break BMC
2866 * redirection as it did with e1000. Newer features require
2867 * that the HW strips the CRC.
73cd78f1 2868 */
87cb7e8c 2869 rctl |= E1000_RCTL_SECRC;
9d5c8243 2870
559e9c49 2871 /* disable store bad packets and clear size bits. */
ec54d7d6 2872 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 2873
6ec43fe6
AD		 2874 /* enable LPE to prevent packets larger than max_frame_size */
2875 rctl |= E1000_RCTL_LPE;
9d5c8243 2876
952f72a8
AD		 2877 /* disable queue 0 to prevent tail write w/o re-config */
2878 wr32(E1000_RXDCTL(0), 0);
9d5c8243 2879
e1739522
AD		 2880 /* Attention!!! For SR-IOV PF driver operations you must enable
2881 * queue drop for all VF and PF queues to prevent head of line blocking
2882 * if an un-trusted VF does not provide descriptors to hardware.
2883 */
2884 if (adapter->vfs_allocated_count) {
e1739522
AD		 2885 /* set all queue drop enable bits */
2886 wr32(E1000_QDE, ALL_QUEUES);
e1739522
AD		 2887 }
2888
9d5c8243
AK		 2889 wr32(E1000_RCTL, rctl);
2890}
2891
7d5753f0
AD		 2892static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
2893 int vfn)
2894{
2895 struct e1000_hw *hw = &adapter->hw;
2896 u32 vmolr;
2897
2898 /* if it isn't the PF check to see if VFs are enabled and
2899 * increase the size to support vlan tags */
2900 if (vfn < adapter->vfs_allocated_count &&
2901 adapter->vf_data[vfn].vlans_enabled)
2902 size += VLAN_TAG_SIZE;
2903
2904 vmolr = rd32(E1000_VMOLR(vfn));
2905 vmolr &= ~E1000_VMOLR_RLPML_MASK;
2906 vmolr |= size | E1000_VMOLR_LPE;
2907 wr32(E1000_VMOLR(vfn), vmolr);
2908
2909 return 0;
2910}
2911
e1739522
AD		 2912/**
2913 * igb_rlpml_set - set maximum receive packet size
2914 * @adapter: board private structure
2915 *
2916 * Configure maximum receivable packet size.
2917 **/
2918static void igb_rlpml_set(struct igb_adapter *adapter)
2919{
2920 u32 max_frame_size = adapter->max_frame_size;
2921 struct e1000_hw *hw = &adapter->hw;
2922 u16 pf_id = adapter->vfs_allocated_count;
2923
2924 if (adapter->vlgrp)
2925 max_frame_size += VLAN_TAG_SIZE;
2926
2927 /* if vfs are enabled we set RLPML to the largest possible request
2928 * size and set the VMOLR RLPML to the size we need */
2929 if (pf_id) {
2930 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
7d5753f0 2931 max_frame_size = MAX_JUMBO_FRAME_SIZE;
e1739522
AD		 2932 }
2933
2934 wr32(E1000_RLPML, max_frame_size);
2935}
2936
8151d294
WM		 2937static inline void igb_set_vmolr(struct igb_adapter *adapter,
2938 int vfn, bool aupe)
7d5753f0
AD		 2939{
2940 struct e1000_hw *hw = &adapter->hw;
2941 u32 vmolr;
2942
2943 /*
2944 * This register exists only on 82576 and newer so if we are older then
2945 * we should exit and do nothing
2946 */
2947 if (hw->mac.type < e1000_82576)
2948 return;
2949
2950 vmolr = rd32(E1000_VMOLR(vfn));
8151d294
WM		 2951 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
2952 if (aupe)
2953 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
2954 else
2955 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
7d5753f0
AD		 2956
2957 /* clear all bits that might not be set */
2958 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
2959
a99955fc 2960 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
7d5753f0
AD		 2961 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
2962 /*
2963 * for VMDq only allow the VFs and pool 0 to accept broadcast and
2964 * multicast packets
2965 */
2966 if (vfn <= adapter->vfs_allocated_count)
2967 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
2968
2969 wr32(E1000_VMOLR(vfn), vmolr);
2970}
2971
85b430b4
AD		 2972/**
2973 * igb_configure_rx_ring - Configure a receive ring after Reset
2974 * @adapter: board private structure
2975 * @ring: receive ring to be configured
2976 *
2977 * Configure the Rx unit of the MAC after a reset.
2978 **/
d7ee5b3a
AD		 2979void igb_configure_rx_ring(struct igb_adapter *adapter,
2980 struct igb_ring *ring)
85b430b4
AD		 2981{
2982 struct e1000_hw *hw = &adapter->hw;
2983 u64 rdba = ring->dma;
2984 int reg_idx = ring->reg_idx;
952f72a8 2985 u32 srrctl, rxdctl;
85b430b4
AD		 2986
2987 /* disable the queue */
2988 rxdctl = rd32(E1000_RXDCTL(reg_idx));
2989 wr32(E1000_RXDCTL(reg_idx),
2990 rxdctl & ~E1000_RXDCTL_QUEUE_ENABLE);
2991
2992 /* Set DMA base address registers */
2993 wr32(E1000_RDBAL(reg_idx),
2994 rdba & 0x00000000ffffffffULL);
2995 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
2996 wr32(E1000_RDLEN(reg_idx),
2997 ring->count * sizeof(union e1000_adv_rx_desc));
2998
2999 /* initialize head and tail */
fce99e34
AD		 3000 ring->head = hw->hw_addr + E1000_RDH(reg_idx);
3001 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
3002 writel(0, ring->head);
3003 writel(0, ring->tail);
85b430b4 3004
952f72a8 3005 /* set descriptor configuration */
4c844851
AD		 3006 if (ring->rx_buffer_len < IGB_RXBUFFER_1024) {
3007 srrctl = ALIGN(ring->rx_buffer_len, 64) <<
952f72a8
AD		 3008 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
3009#if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
3010 srrctl |= IGB_RXBUFFER_16384 >>
3011 E1000_SRRCTL_BSIZEPKT_SHIFT;
3012#else
3013 srrctl |= (PAGE_SIZE / 2) >>
3014 E1000_SRRCTL_BSIZEPKT_SHIFT;
3015#endif
3016 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
3017 } else {
4c844851 3018 srrctl = ALIGN(ring->rx_buffer_len, 1024) >>
952f72a8
AD		 3019 E1000_SRRCTL_BSIZEPKT_SHIFT;
3020 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
3021 }
757b77e2
NN		 3022 if (hw->mac.type == e1000_82580)
3023 srrctl |= E1000_SRRCTL_TIMESTAMP;
e6bdb6fe
NN		 3024 /* Only set Drop Enable if we are supporting multiple queues */
3025 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3026 srrctl |= E1000_SRRCTL_DROP_EN;
952f72a8
AD		 3027
3028 wr32(E1000_SRRCTL(reg_idx), srrctl);
3029
7d5753f0 3030 /* set filtering for VMDQ pools */
8151d294 3031 igb_set_vmolr(adapter, reg_idx & 0x7, true);
7d5753f0 3032
85b430b4
AD		 3033 /* enable receive descriptor fetching */
3034 rxdctl = rd32(E1000_RXDCTL(reg_idx));
3035 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
3036 rxdctl &= 0xFFF00000;
3037 rxdctl |= IGB_RX_PTHRESH;
3038 rxdctl |= IGB_RX_HTHRESH << 8;
3039 rxdctl |= IGB_RX_WTHRESH << 16;
3040 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3041}
3042
9d5c8243
AK		 3043/**
3044 * igb_configure_rx - Configure receive Unit after Reset
3045 * @adapter: board private structure
3046 *
3047 * Configure the Rx unit of the MAC after a reset.
3048 **/
3049static void igb_configure_rx(struct igb_adapter *adapter)
3050{
9107584e 3051 int i;
9d5c8243 3052
68d480c4
AD		 3053 /* set UTA to appropriate mode */
3054 igb_set_uta(adapter);
3055
26ad9178
AD		 3056 /* set the correct pool for the PF default MAC address in entry 0 */
3057 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
3058 adapter->vfs_allocated_count);
3059
06cf2666
AD		 3060 /* Setup the HW Rx Head and Tail Descriptor Pointers and
3061 * the Base and Length of the Rx Descriptor Ring */
3062 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3063 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
9d5c8243
AK		 3064}
3065
3066/**
3067 * igb_free_tx_resources - Free Tx Resources per Queue
9d5c8243
AK		 3068 * @tx_ring: Tx descriptor ring for a specific queue
3069 *
3070 * Free all transmit software resources
3071 **/
68fd9910 3072void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3073{
3b644cf6 3074 igb_clean_tx_ring(tx_ring);
9d5c8243
AK		 3075
3076 vfree(tx_ring->buffer_info);
3077 tx_ring->buffer_info = NULL;
3078
439705e1
AD		 3079 /* if not set, then don't free */
3080 if (!tx_ring->desc)
3081 return;
3082
59d71989
AD		 3083 dma_free_coherent(tx_ring->dev, tx_ring->size,
3084 tx_ring->desc, tx_ring->dma);
9d5c8243
AK		 3085
3086 tx_ring->desc = NULL;
3087}
3088
3089/**
3090 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3091 * @adapter: board private structure
3092 *
3093 * Free all transmit software resources
3094 **/
3095static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3096{
3097 int i;
3098
3099 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3100 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3101}
3102
b1a436c3
AD		 3103void igb_unmap_and_free_tx_resource(struct igb_ring *tx_ring,
3104 struct igb_buffer *buffer_info)
9d5c8243 3105{
6366ad33
AD		 3106 if (buffer_info->dma) {
3107 if (buffer_info->mapped_as_page)
59d71989 3108 dma_unmap_page(tx_ring->dev,
6366ad33
AD		 3109 buffer_info->dma,
3110 buffer_info->length,
59d71989 3111 DMA_TO_DEVICE);
6366ad33 3112 else
59d71989 3113 dma_unmap_single(tx_ring->dev,
6366ad33
AD		 3114 buffer_info->dma,
3115 buffer_info->length,
59d71989 3116 DMA_TO_DEVICE);
6366ad33
AD		 3117 buffer_info->dma = 0;
3118 }
9d5c8243
AK		 3119 if (buffer_info->skb) {
3120 dev_kfree_skb_any(buffer_info->skb);
3121 buffer_info->skb = NULL;
3122 }
3123 buffer_info->time_stamp = 0;
6366ad33
AD		 3124 buffer_info->length = 0;
3125 buffer_info->next_to_watch = 0;
3126 buffer_info->mapped_as_page = false;
9d5c8243
AK		 3127}
3128
3129/**
3130 * igb_clean_tx_ring - Free Tx Buffers
9d5c8243
AK		 3131 * @tx_ring: ring to be cleaned
3132 **/
3b644cf6 3133static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243
AK		 3134{
3135 struct igb_buffer *buffer_info;
3136 unsigned long size;
3137 unsigned int i;
3138
3139 if (!tx_ring->buffer_info)
3140 return;
3141 /* Free all the Tx ring sk_buffs */
3142
3143 for (i = 0; i < tx_ring->count; i++) {
3144 buffer_info = &tx_ring->buffer_info[i];
80785298 3145 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
9d5c8243
AK		 3146 }
3147
3148 size = sizeof(struct igb_buffer) * tx_ring->count;
3149 memset(tx_ring->buffer_info, 0, size);
3150
3151 /* Zero out the descriptor ring */
9d5c8243
AK		 3152 memset(tx_ring->desc, 0, tx_ring->size);
3153
3154 tx_ring->next_to_use = 0;
3155 tx_ring->next_to_clean = 0;
9d5c8243
AK		 3156}
3157
3158/**
3159 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3160 * @adapter: board private structure
3161 **/
3162static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3163{
3164 int i;
3165
3166 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3167 igb_clean_tx_ring(adapter->tx_ring[i]);
9d5c8243
AK		 3168}
3169
3170/**
3171 * igb_free_rx_resources - Free Rx Resources
9d5c8243
AK		 3172 * @rx_ring: ring to clean the resources from
3173 *
3174 * Free all receive software resources
3175 **/
68fd9910 3176void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3177{
3b644cf6 3178 igb_clean_rx_ring(rx_ring);
9d5c8243
AK		 3179
3180 vfree(rx_ring->buffer_info);
3181 rx_ring->buffer_info = NULL;
3182
439705e1
AD		 3183 /* if not set, then don't free */
3184 if (!rx_ring->desc)
3185 return;
3186
59d71989
AD		 3187 dma_free_coherent(rx_ring->dev, rx_ring->size,
3188 rx_ring->desc, rx_ring->dma);
9d5c8243
AK		 3189
3190 rx_ring->desc = NULL;
3191}
3192
3193/**
3194 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3195 * @adapter: board private structure
3196 *
3197 * Free all receive software resources
3198 **/
3199static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3200{
3201 int i;
3202
3203 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3204 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3205}
3206
3207/**
3208 * igb_clean_rx_ring - Free Rx Buffers per Queue
9d5c8243
AK		 3209 * @rx_ring: ring to free buffers from
3210 **/
3b644cf6 3211static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243
AK		 3212{
3213 struct igb_buffer *buffer_info;
9d5c8243
AK		 3214 unsigned long size;
3215 unsigned int i;
3216
3217 if (!rx_ring->buffer_info)
3218 return;
439705e1 3219
9d5c8243
AK		 3220 /* Free all the Rx ring sk_buffs */
3221 for (i = 0; i < rx_ring->count; i++) {
3222 buffer_info = &rx_ring->buffer_info[i];
3223 if (buffer_info->dma) {
59d71989 3224 dma_unmap_single(rx_ring->dev,
80785298 3225 buffer_info->dma,
4c844851 3226 rx_ring->rx_buffer_len,
59d71989 3227 DMA_FROM_DEVICE);
9d5c8243
AK		 3228 buffer_info->dma = 0;
3229 }
3230
3231 if (buffer_info->skb) {
3232 dev_kfree_skb(buffer_info->skb);
3233 buffer_info->skb = NULL;
3234 }
6ec43fe6 3235 if (buffer_info->page_dma) {
59d71989 3236 dma_unmap_page(rx_ring->dev,
80785298 3237 buffer_info->page_dma,
6ec43fe6 3238 PAGE_SIZE / 2,
59d71989 3239 DMA_FROM_DEVICE);
6ec43fe6
AD		 3240 buffer_info->page_dma = 0;
3241 }
9d5c8243 3242 if (buffer_info->page) {
9d5c8243
AK		 3243 put_page(buffer_info->page);
3244 buffer_info->page = NULL;
bf36c1a0 3245 buffer_info->page_offset = 0;
9d5c8243
AK		 3246 }
3247 }
3248
9d5c8243
AK		 3249 size = sizeof(struct igb_buffer) * rx_ring->count;
3250 memset(rx_ring->buffer_info, 0, size);
3251
3252 /* Zero out the descriptor ring */
3253 memset(rx_ring->desc, 0, rx_ring->size);
3254
3255 rx_ring->next_to_clean = 0;
3256 rx_ring->next_to_use = 0;
9d5c8243
AK		 3257}
3258
3259/**
3260 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3261 * @adapter: board private structure
3262 **/
3263static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3264{
3265 int i;
3266
3267 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3268 igb_clean_rx_ring(adapter->rx_ring[i]);
9d5c8243
AK		 3269}
3270
3271/**
3272 * igb_set_mac - Change the Ethernet Address of the NIC
3273 * @netdev: network interface device structure
3274 * @p: pointer to an address structure
3275 *
3276 * Returns 0 on success, negative on failure
3277 **/
3278static int igb_set_mac(struct net_device *netdev, void *p)
3279{
3280 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 3281 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 3282 struct sockaddr *addr = p;
3283
3284 if (!is_valid_ether_addr(addr->sa_data))
3285 return -EADDRNOTAVAIL;
3286
3287 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 3288 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 3289
26ad9178
AD		 3290 /* set the correct pool for the new PF MAC address in entry 0 */
3291 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
3292 adapter->vfs_allocated_count);
e1739522 3293
9d5c8243
AK		 3294 return 0;
3295}
3296
3297/**
68d480c4 3298 * igb_write_mc_addr_list - write multicast addresses to MTA
9d5c8243
AK		 3299 * @netdev: network interface device structure
3300 *
68d480c4
AD		 3301 * Writes multicast address list to the MTA hash table.
3302 * Returns: -ENOMEM on failure
3303 * 0 on no addresses written
3304 * X on writing X addresses to MTA
9d5c8243 3305 **/
68d480c4 3306static int igb_write_mc_addr_list(struct net_device *netdev)
9d5c8243
AK		 3307{
3308 struct igb_adapter *adapter = netdev_priv(netdev);
3309 struct e1000_hw *hw = &adapter->hw;
22bedad3 3310 struct netdev_hw_addr *ha;
68d480c4 3311 u8 *mta_list;
9d5c8243
AK		 3312 int i;
3313
4cd24eaf 3314 if (netdev_mc_empty(netdev)) {
68d480c4
AD		 3315 /* nothing to program, so clear mc list */
3316 igb_update_mc_addr_list(hw, NULL, 0);
3317 igb_restore_vf_multicasts(adapter);
3318 return 0;
3319 }
9d5c8243 3320
4cd24eaf 3321 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
68d480c4
AD		 3322 if (!mta_list)
3323 return -ENOMEM;
ff41f8dc 3324
68d480c4 3325 /* The shared function expects a packed array of only addresses. */
48e2f183 3326 i = 0;
22bedad3
JP		 3327 netdev_for_each_mc_addr(ha, netdev)
3328 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
68d480c4 3329
68d480c4
AD		 3330 igb_update_mc_addr_list(hw, mta_list, i);
3331 kfree(mta_list);
3332
4cd24eaf 3333 return netdev_mc_count(netdev);
68d480c4
AD		 3334}
3335
3336/**
3337 * igb_write_uc_addr_list - write unicast addresses to RAR table
3338 * @netdev: network interface device structure
3339 *
3340 * Writes unicast address list to the RAR table.
3341 * Returns: -ENOMEM on failure/insufficient address space
3342 * 0 on no addresses written
3343 * X on writing X addresses to the RAR table
3344 **/
3345static int igb_write_uc_addr_list(struct net_device *netdev)
3346{
3347 struct igb_adapter *adapter = netdev_priv(netdev);
3348 struct e1000_hw *hw = &adapter->hw;
3349 unsigned int vfn = adapter->vfs_allocated_count;
3350 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3351 int count = 0;
3352
3353 /* return ENOMEM indicating insufficient memory for addresses */
32e7bfc4 3354 if (netdev_uc_count(netdev) > rar_entries)
68d480c4 3355 return -ENOMEM;
9d5c8243 3356
32e7bfc4 3357 if (!netdev_uc_empty(netdev) && rar_entries) {
ff41f8dc 3358 struct netdev_hw_addr *ha;
32e7bfc4
JP		 3359
3360 netdev_for_each_uc_addr(ha, netdev) {
ff41f8dc
AD		 3361 if (!rar_entries)
3362 break;
26ad9178
AD		 3363 igb_rar_set_qsel(adapter, ha->addr,
3364 rar_entries--,
68d480c4
AD		 3365 vfn);
3366 count++;
ff41f8dc
AD		 3367 }
3368 }
3369 /* write the addresses in reverse order to avoid write combining */
3370 for (; rar_entries > 0 ; rar_entries--) {
3371 wr32(E1000_RAH(rar_entries), 0);
3372 wr32(E1000_RAL(rar_entries), 0);
3373 }
3374 wrfl();
3375
68d480c4
AD		 3376 return count;
3377}
3378
3379/**
3380 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3381 * @netdev: network interface device structure
3382 *
3383 * The set_rx_mode entry point is called whenever the unicast or multicast
3384 * address lists or the network interface flags are updated. This routine is
3385 * responsible for configuring the hardware for proper unicast, multicast,
3386 * promiscuous mode, and all-multi behavior.
3387 **/
3388static void igb_set_rx_mode(struct net_device *netdev)
3389{
3390 struct igb_adapter *adapter = netdev_priv(netdev);
3391 struct e1000_hw *hw = &adapter->hw;
3392 unsigned int vfn = adapter->vfs_allocated_count;
3393 u32 rctl, vmolr = 0;
3394 int count;
3395
3396 /* Check for Promiscuous and All Multicast modes */
3397 rctl = rd32(E1000_RCTL);
3398
3399 /* clear the effected bits */
3400 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
3401
3402 if (netdev->flags & IFF_PROMISC) {
3403 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3404 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
3405 } else {
3406 if (netdev->flags & IFF_ALLMULTI) {
3407 rctl |= E1000_RCTL_MPE;
3408 vmolr |= E1000_VMOLR_MPME;
3409 } else {
3410 /*
3411 * Write addresses to the MTA, if the attempt fails
3412 * then we should just turn on promiscous mode so
3413 * that we can at least receive multicast traffic
3414 */
3415 count = igb_write_mc_addr_list(netdev);
3416 if (count < 0) {
3417 rctl |= E1000_RCTL_MPE;
3418 vmolr |= E1000_VMOLR_MPME;
3419 } else if (count) {
3420 vmolr |= E1000_VMOLR_ROMPE;
3421 }
3422 }
3423 /*
3424 * Write addresses to available RAR registers, if there is not
3425 * sufficient space to store all the addresses then enable
3426 * unicast promiscous mode
3427 */
3428 count = igb_write_uc_addr_list(netdev);
3429 if (count < 0) {
3430 rctl |= E1000_RCTL_UPE;
3431 vmolr |= E1000_VMOLR_ROPE;
3432 }
3433 rctl |= E1000_RCTL_VFE;
28fc06f5 3434 }
68d480c4 3435 wr32(E1000_RCTL, rctl);
28fc06f5 3436
68d480c4
AD		 3437 /*
3438 * In order to support SR-IOV and eventually VMDq it is necessary to set
3439 * the VMOLR to enable the appropriate modes. Without this workaround
3440 * we will have issues with VLAN tag stripping not being done for frames
3441 * that are only arriving because we are the default pool
3442 */
3443 if (hw->mac.type < e1000_82576)
28fc06f5 3444 return;
9d5c8243 3445
68d480c4
AD		 3446 vmolr |= rd32(E1000_VMOLR(vfn)) &
3447 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
3448 wr32(E1000_VMOLR(vfn), vmolr);
28fc06f5 3449 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 3450}
3451
13800469
GR		 3452static void igb_check_wvbr(struct igb_adapter *adapter)
3453{
3454 struct e1000_hw *hw = &adapter->hw;
3455 u32 wvbr = 0;
3456
3457 switch (hw->mac.type) {
3458 case e1000_82576:
3459 case e1000_i350:
3460 if (!(wvbr = rd32(E1000_WVBR)))
3461 return;
3462 break;
3463 default:
3464 break;
3465 }
3466
3467 adapter->wvbr |= wvbr;
3468}
3469
3470#define IGB_STAGGERED_QUEUE_OFFSET 8
3471
3472static void igb_spoof_check(struct igb_adapter *adapter)
3473{
3474 int j;
3475
3476 if (!adapter->wvbr)
3477 return;
3478
3479 for(j = 0; j < adapter->vfs_allocated_count; j++) {
3480 if (adapter->wvbr & (1 << j) ||
3481 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
3482 dev_warn(&adapter->pdev->dev,
3483 "Spoof event(s) detected on VF %d\n", j);
3484 adapter->wvbr &=
3485 ~((1 << j) |
3486 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
3487 }
3488 }
3489}
3490
9d5c8243
AK		 3491/* Need to wait a few seconds after link up to get diagnostic information from
3492 * the phy */
3493static void igb_update_phy_info(unsigned long data)
3494{
3495 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 3496 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 3497}
3498
4d6b725e
AD		 3499/**
3500 * igb_has_link - check shared code for link and determine up/down
3501 * @adapter: pointer to driver private info
3502 **/
3145535a 3503bool igb_has_link(struct igb_adapter *adapter)
4d6b725e
AD		 3504{
3505 struct e1000_hw *hw = &adapter->hw;
3506 bool link_active = false;
3507 s32 ret_val = 0;
3508
3509 /* get_link_status is set on LSC (link status) interrupt or
3510 * rx sequence error interrupt. get_link_status will stay
3511 * false until the e1000_check_for_link establishes link
3512 * for copper adapters ONLY
3513 */
3514 switch (hw->phy.media_type) {
3515 case e1000_media_type_copper:
3516 if (hw->mac.get_link_status) {
3517 ret_val = hw->mac.ops.check_for_link(hw);
3518 link_active = !hw->mac.get_link_status;
3519 } else {
3520 link_active = true;
3521 }
3522 break;
4d6b725e
AD		 3523 case e1000_media_type_internal_serdes:
3524 ret_val = hw->mac.ops.check_for_link(hw);
3525 link_active = hw->mac.serdes_has_link;
3526 break;
3527 default:
3528 case e1000_media_type_unknown:
3529 break;
3530 }
3531
3532 return link_active;
3533}
3534
9d5c8243
AK		 3535/**
3536 * igb_watchdog - Timer Call-back
3537 * @data: pointer to adapter cast into an unsigned long
3538 **/
3539static void igb_watchdog(unsigned long data)
3540{
3541 struct igb_adapter *adapter = (struct igb_adapter *)data;
3542 /* Do the rest outside of interrupt context */
3543 schedule_work(&adapter->watchdog_task);
3544}
3545
3546static void igb_watchdog_task(struct work_struct *work)
3547{
3548 struct igb_adapter *adapter = container_of(work,
559e9c49
AD		 3549 struct igb_adapter,
3550 watchdog_task);
9d5c8243 3551 struct e1000_hw *hw = &adapter->hw;
9d5c8243 3552 struct net_device *netdev = adapter->netdev;
9d5c8243 3553 u32 link;
7a6ea550 3554 int i;
9d5c8243 3555
4d6b725e 3556 link = igb_has_link(adapter);
9d5c8243
AK		 3557 if (link) {
3558 if (!netif_carrier_ok(netdev)) {
3559 u32 ctrl;
330a6d6a
AD		 3560 hw->mac.ops.get_speed_and_duplex(hw,
3561 &adapter->link_speed,
3562 &adapter->link_duplex);
9d5c8243
AK		 3563
3564 ctrl = rd32(E1000_CTRL);
527d47c1
AD		 3565 /* Links status message must follow this format */
3566 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
9d5c8243 3567 "Flow Control: %s\n",
559e9c49
AD		 3568 netdev->name,
3569 adapter->link_speed,
3570 adapter->link_duplex == FULL_DUPLEX ?
9d5c8243 3571 "Full Duplex" : "Half Duplex",
559e9c49
AD		 3572 ((ctrl & E1000_CTRL_TFCE) &&
3573 (ctrl & E1000_CTRL_RFCE)) ? "RX/TX" :
3574 ((ctrl & E1000_CTRL_RFCE) ? "RX" :
3575 ((ctrl & E1000_CTRL_TFCE) ? "TX" : "None")));
9d5c8243 3576
d07f3e37 3577 /* adjust timeout factor according to speed/duplex */
9d5c8243
AK		 3578 adapter->tx_timeout_factor = 1;
3579 switch (adapter->link_speed) {
3580 case SPEED_10:
9d5c8243
AK		 3581 adapter->tx_timeout_factor = 14;
3582 break;
3583 case SPEED_100:
9d5c8243
AK		 3584 /* maybe add some timeout factor ? */
3585 break;
3586 }
3587
3588 netif_carrier_on(netdev);
9d5c8243 3589
4ae196df 3590 igb_ping_all_vfs(adapter);
17dc566c 3591 igb_check_vf_rate_limit(adapter);
4ae196df 3592
4b1a9877 3593 /* link state has changed, schedule phy info update */
9d5c8243
AK		 3594 if (!test_bit(__IGB_DOWN, &adapter->state))
3595 mod_timer(&adapter->phy_info_timer,
3596 round_jiffies(jiffies + 2 * HZ));
3597 }
3598 } else {
3599 if (netif_carrier_ok(netdev)) {
3600 adapter->link_speed = 0;
3601 adapter->link_duplex = 0;
527d47c1
AD		 3602 /* Links status message must follow this format */
3603 printk(KERN_INFO "igb: %s NIC Link is Down\n",
3604 netdev->name);
9d5c8243 3605 netif_carrier_off(netdev);
4b1a9877 3606
4ae196df
AD		 3607 igb_ping_all_vfs(adapter);
3608
4b1a9877 3609 /* link state has changed, schedule phy info update */
9d5c8243
AK		 3610 if (!test_bit(__IGB_DOWN, &adapter->state))
3611 mod_timer(&adapter->phy_info_timer,
3612 round_jiffies(jiffies + 2 * HZ));
3613 }
3614 }
3615
12dcd86b
ED		 3616 spin_lock(&adapter->stats64_lock);
3617 igb_update_stats(adapter, &adapter->stats64);
3618 spin_unlock(&adapter->stats64_lock);
9d5c8243 3619
dbabb065 3620 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 3621 struct igb_ring *tx_ring = adapter->tx_ring[i];
dbabb065 3622 if (!netif_carrier_ok(netdev)) {
9d5c8243
AK		 3623 /* We've lost link, so the controller stops DMA,
3624 * but we've got queued Tx work that's never going
3625 * to get done, so reset controller to flush Tx.
3626 * (Do the reset outside of interrupt context). */
dbabb065
AD		 3627 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
3628 adapter->tx_timeout_count++;
3629 schedule_work(&adapter->reset_task);
3630 /* return immediately since reset is imminent */
3631 return;
3632 }
9d5c8243 3633 }
9d5c8243 3634
dbabb065
AD		 3635 /* Force detection of hung controller every watchdog period */
3636 tx_ring->detect_tx_hung = true;
3637 }
f7ba205e 3638
9d5c8243 3639 /* Cause software interrupt to ensure rx ring is cleaned */
7a6ea550 3640 if (adapter->msix_entries) {
047e0030
AD		 3641 u32 eics = 0;
3642 for (i = 0; i < adapter->num_q_vectors; i++) {
3643 struct igb_q_vector *q_vector = adapter->q_vector[i];
3644 eics |= q_vector->eims_value;
3645 }
7a6ea550
AD		 3646 wr32(E1000_EICS, eics);
3647 } else {
3648 wr32(E1000_ICS, E1000_ICS_RXDMT0);
3649 }
9d5c8243 3650
13800469
GR		 3651 igb_spoof_check(adapter);
3652
9d5c8243
AK		 3653 /* Reset the timer */
3654 if (!test_bit(__IGB_DOWN, &adapter->state))
3655 mod_timer(&adapter->watchdog_timer,
3656 round_jiffies(jiffies + 2 * HZ));
3657}
3658
3659enum latency_range {
3660 lowest_latency = 0,
3661 low_latency = 1,
3662 bulk_latency = 2,
3663 latency_invalid = 255
3664};
3665
6eb5a7f1
AD		 3666/**
3667 * igb_update_ring_itr - update the dynamic ITR value based on packet size
3668 *
3669 * Stores a new ITR value based on strictly on packet size. This
3670 * algorithm is less sophisticated than that used in igb_update_itr,
3671 * due to the difficulty of synchronizing statistics across multiple
eef35c2d 3672 * receive rings. The divisors and thresholds used by this function
6eb5a7f1
AD		 3673 * were determined based on theoretical maximum wire speed and testing
3674 * data, in order to minimize response time while increasing bulk
3675 * throughput.
3676 * This functionality is controlled by the InterruptThrottleRate module
3677 * parameter (see igb_param.c)
3678 * NOTE: This function is called only when operating in a multiqueue
3679 * receive environment.
047e0030 3680 * @q_vector: pointer to q_vector
6eb5a7f1 3681 **/
047e0030 3682static void igb_update_ring_itr(struct igb_q_vector *q_vector)
9d5c8243 3683{
047e0030 3684 int new_val = q_vector->itr_val;
6eb5a7f1 3685 int avg_wire_size = 0;
047e0030 3686 struct igb_adapter *adapter = q_vector->adapter;
12dcd86b
ED		 3687 struct igb_ring *ring;
3688 unsigned int packets;
9d5c8243 3689
6eb5a7f1
AD		 3690 /* For non-gigabit speeds, just fix the interrupt rate at 4000
3691 * ints/sec - ITR timer value of 120 ticks.
3692 */
3693 if (adapter->link_speed != SPEED_1000) {
047e0030 3694 new_val = 976;
6eb5a7f1 3695 goto set_itr_val;
9d5c8243 3696 }
047e0030 3697
12dcd86b
ED		 3698 ring = q_vector->rx_ring;
3699 if (ring) {
3700 packets = ACCESS_ONCE(ring->total_packets);
3701
3702 if (packets)
3703 avg_wire_size = ring->total_bytes / packets;
047e0030
AD		 3704 }
3705
12dcd86b
ED		 3706 ring = q_vector->tx_ring;
3707 if (ring) {
3708 packets = ACCESS_ONCE(ring->total_packets);
3709
3710 if (packets)
3711 avg_wire_size = max_t(u32, avg_wire_size,
3712 ring->total_bytes / packets);
047e0030
AD		 3713 }
3714
3715 /* if avg_wire_size isn't set no work was done */
3716 if (!avg_wire_size)
3717 goto clear_counts;
9d5c8243 3718
6eb5a7f1
AD		 3719 /* Add 24 bytes to size to account for CRC, preamble, and gap */
3720 avg_wire_size += 24;
3721
3722 /* Don't starve jumbo frames */
3723 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 3724
6eb5a7f1
AD		 3725 /* Give a little boost to mid-size frames */
3726 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
3727 new_val = avg_wire_size / 3;
3728 else
3729 new_val = avg_wire_size / 2;
9d5c8243 3730
abe1c363
NN		 3731 /* when in itr mode 3 do not exceed 20K ints/sec */
3732 if (adapter->rx_itr_setting == 3 && new_val < 196)
3733 new_val = 196;
3734
6eb5a7f1 3735set_itr_val:
047e0030
AD		 3736 if (new_val != q_vector->itr_val) {
3737 q_vector->itr_val = new_val;
3738 q_vector->set_itr = 1;
9d5c8243 3739 }
6eb5a7f1 3740clear_counts:
047e0030
AD		 3741 if (q_vector->rx_ring) {
3742 q_vector->rx_ring->total_bytes = 0;
3743 q_vector->rx_ring->total_packets = 0;
3744 }
3745 if (q_vector->tx_ring) {
3746 q_vector->tx_ring->total_bytes = 0;
3747 q_vector->tx_ring->total_packets = 0;
3748 }
9d5c8243
AK		 3749}
3750
3751/**
3752 * igb_update_itr - update the dynamic ITR value based on statistics
3753 * Stores a new ITR value based on packets and byte
3754 * counts during the last interrupt. The advantage of per interrupt
3755 * computation is faster updates and more accurate ITR for the current
3756 * traffic pattern. Constants in this function were computed
3757 * based on theoretical maximum wire speed and thresholds were set based
3758 * on testing data as well as attempting to minimize response time
3759 * while increasing bulk throughput.
3760 * this functionality is controlled by the InterruptThrottleRate module
3761 * parameter (see igb_param.c)
3762 * NOTE: These calculations are only valid when operating in a single-
3763 * queue environment.
3764 * @adapter: pointer to adapter
047e0030 3765 * @itr_setting: current q_vector->itr_val
9d5c8243
AK		 3766 * @packets: the number of packets during this measurement interval
3767 * @bytes: the number of bytes during this measurement interval
3768 **/
3769static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
3770 int packets, int bytes)
3771{
3772 unsigned int retval = itr_setting;
3773
3774 if (packets == 0)
3775 goto update_itr_done;
3776
3777 switch (itr_setting) {
3778 case lowest_latency:
3779 /* handle TSO and jumbo frames */
3780 if (bytes/packets > 8000)
3781 retval = bulk_latency;
3782 else if ((packets < 5) && (bytes > 512))
3783 retval = low_latency;
3784 break;
3785 case low_latency: /* 50 usec aka 20000 ints/s */
3786 if (bytes > 10000) {
3787 /* this if handles the TSO accounting */
3788 if (bytes/packets > 8000) {
3789 retval = bulk_latency;
3790 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
3791 retval = bulk_latency;
3792 } else if ((packets > 35)) {
3793 retval = lowest_latency;
3794 }
3795 } else if (bytes/packets > 2000) {
3796 retval = bulk_latency;
3797 } else if (packets <= 2 && bytes < 512) {
3798 retval = lowest_latency;
3799 }
3800 break;
3801 case bulk_latency: /* 250 usec aka 4000 ints/s */
3802 if (bytes > 25000) {
3803 if (packets > 35)
3804 retval = low_latency;
1e5c3d21 3805 } else if (bytes < 1500) {
9d5c8243
AK		 3806 retval = low_latency;
3807 }
3808 break;
3809 }
3810
3811update_itr_done:
3812 return retval;
3813}
3814
6eb5a7f1 3815static void igb_set_itr(struct igb_adapter *adapter)
9d5c8243 3816{
047e0030 3817 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243 3818 u16 current_itr;
047e0030 3819 u32 new_itr = q_vector->itr_val;
9d5c8243
AK		 3820
3821 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
3822 if (adapter->link_speed != SPEED_1000) {
3823 current_itr = 0;
3824 new_itr = 4000;
3825 goto set_itr_now;
3826 }
3827
3828 adapter->rx_itr = igb_update_itr(adapter,
3829 adapter->rx_itr,
3025a446
AD		 3830 q_vector->rx_ring->total_packets,
3831 q_vector->rx_ring->total_bytes);
9d5c8243 3832
047e0030
AD		 3833 adapter->tx_itr = igb_update_itr(adapter,
3834 adapter->tx_itr,
3025a446
AD		 3835 q_vector->tx_ring->total_packets,
3836 q_vector->tx_ring->total_bytes);
047e0030 3837 current_itr = max(adapter->rx_itr, adapter->tx_itr);
9d5c8243 3838
6eb5a7f1 3839 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4fc82adf 3840 if (adapter->rx_itr_setting == 3 && current_itr == lowest_latency)
6eb5a7f1
AD		 3841 current_itr = low_latency;
3842
9d5c8243
AK		 3843 switch (current_itr) {
3844 /* counts and packets in update_itr are dependent on these numbers */
3845 case lowest_latency:
78b1f607 3846 new_itr = 56; /* aka 70,000 ints/sec */
9d5c8243
AK		 3847 break;
3848 case low_latency:
78b1f607 3849 new_itr = 196; /* aka 20,000 ints/sec */
9d5c8243
AK		 3850 break;
3851 case bulk_latency:
78b1f607 3852 new_itr = 980; /* aka 4,000 ints/sec */
9d5c8243
AK		 3853 break;
3854 default:
3855 break;
3856 }
3857
3858set_itr_now:
3025a446
AD		 3859 q_vector->rx_ring->total_bytes = 0;
3860 q_vector->rx_ring->total_packets = 0;
3861 q_vector->tx_ring->total_bytes = 0;
3862 q_vector->tx_ring->total_packets = 0;
6eb5a7f1 3863
047e0030 3864 if (new_itr != q_vector->itr_val) {
9d5c8243
AK		 3865 /* this attempts to bias the interrupt rate towards Bulk
3866 * by adding intermediate steps when interrupt rate is
3867 * increasing */
047e0030
AD		 3868 new_itr = new_itr > q_vector->itr_val ?
3869 max((new_itr * q_vector->itr_val) /
3870 (new_itr + (q_vector->itr_val >> 2)),
3871 new_itr) :
9d5c8243
AK		 3872 new_itr;
3873 /* Don't write the value here; it resets the adapter's
3874 * internal timer, and causes us to delay far longer than
3875 * we should between interrupts. Instead, we write the ITR
3876 * value at the beginning of the next interrupt so the timing
3877 * ends up being correct.
3878 */
047e0030
AD		 3879 q_vector->itr_val = new_itr;
3880 q_vector->set_itr = 1;
9d5c8243 3881 }
9d5c8243
AK		 3882}
3883
9d5c8243
AK		 3884#define IGB_TX_FLAGS_CSUM 0x00000001
3885#define IGB_TX_FLAGS_VLAN 0x00000002
3886#define IGB_TX_FLAGS_TSO 0x00000004
3887#define IGB_TX_FLAGS_IPV4 0x00000008
cdfd01fc
AD		 3888#define IGB_TX_FLAGS_TSTAMP 0x00000010
3889#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
3890#define IGB_TX_FLAGS_VLAN_SHIFT 16
9d5c8243 3891
85ad76b2 3892static inline int igb_tso_adv(struct igb_ring *tx_ring,
9d5c8243
AK		 3893 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
3894{
3895 struct e1000_adv_tx_context_desc *context_desc;
3896 unsigned int i;
3897 int err;
3898 struct igb_buffer *buffer_info;
3899 u32 info = 0, tu_cmd = 0;
91d4ee33
NN		 3900 u32 mss_l4len_idx;
3901 u8 l4len;
9d5c8243
AK		 3902
3903 if (skb_header_cloned(skb)) {
3904 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
3905 if (err)
3906 return err;
3907 }
3908
3909 l4len = tcp_hdrlen(skb);
3910 *hdr_len += l4len;
3911
3912 if (skb->protocol == htons(ETH_P_IP)) {
3913 struct iphdr *iph = ip_hdr(skb);
3914 iph->tot_len = 0;
3915 iph->check = 0;
3916 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
3917 iph->daddr, 0,
3918 IPPROTO_TCP,
3919 0);
8e1e8a47 3920 } else if (skb_is_gso_v6(skb)) {
9d5c8243
AK		 3921 ipv6_hdr(skb)->payload_len = 0;
3922 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
3923 &ipv6_hdr(skb)->daddr,
3924 0, IPPROTO_TCP, 0);
3925 }
3926
3927 i = tx_ring->next_to_use;
3928
3929 buffer_info = &tx_ring->buffer_info[i];
3930 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3931 /* VLAN MACLEN IPLEN */
3932 if (tx_flags & IGB_TX_FLAGS_VLAN)
3933 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
3934 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3935 *hdr_len += skb_network_offset(skb);
3936 info |= skb_network_header_len(skb);
3937 *hdr_len += skb_network_header_len(skb);
3938 context_desc->vlan_macip_lens = cpu_to_le32(info);
3939
3940 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
3941 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3942
3943 if (skb->protocol == htons(ETH_P_IP))
3944 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
3945 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3946
3947 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3948
3949 /* MSS L4LEN IDX */
3950 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
3951 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
3952
73cd78f1 3953 /* For 82575, context index must be unique per ring. */
85ad76b2
AD		 3954 if (tx_ring->flags & IGB_RING_FLAG_TX_CTX_IDX)
3955 mss_l4len_idx |= tx_ring->reg_idx << 4;
9d5c8243
AK		 3956
3957 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
3958 context_desc->seqnum_seed = 0;
3959
3960 buffer_info->time_stamp = jiffies;
0e014cb1 3961 buffer_info->next_to_watch = i;
9d5c8243
AK		 3962 buffer_info->dma = 0;
3963 i++;
3964 if (i == tx_ring->count)
3965 i = 0;
3966
3967 tx_ring->next_to_use = i;
3968
3969 return true;
3970}
3971
85ad76b2
AD		 3972static inline bool igb_tx_csum_adv(struct igb_ring *tx_ring,
3973 struct sk_buff *skb, u32 tx_flags)
9d5c8243
AK		 3974{
3975 struct e1000_adv_tx_context_desc *context_desc;
59d71989 3976 struct device *dev = tx_ring->dev;
9d5c8243
AK		 3977 struct igb_buffer *buffer_info;
3978 u32 info = 0, tu_cmd = 0;
80785298 3979 unsigned int i;
9d5c8243
AK		 3980
3981 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
3982 (tx_flags & IGB_TX_FLAGS_VLAN)) {
3983 i = tx_ring->next_to_use;
3984 buffer_info = &tx_ring->buffer_info[i];
3985 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3986
3987 if (tx_flags & IGB_TX_FLAGS_VLAN)
3988 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
cdfd01fc 3989
9d5c8243
AK		 3990 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3991 if (skb->ip_summed == CHECKSUM_PARTIAL)
3992 info |= skb_network_header_len(skb);
3993
3994 context_desc->vlan_macip_lens = cpu_to_le32(info);
3995
3996 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3997
3998 if (skb->ip_summed == CHECKSUM_PARTIAL) {
fa4a7ef3
AJ		 3999 __be16 protocol;
4000
4001 if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
4002 const struct vlan_ethhdr *vhdr =
4003 (const struct vlan_ethhdr*)skb->data;
4004
4005 protocol = vhdr->h_vlan_encapsulated_proto;
4006 } else {
4007 protocol = skb->protocol;
4008 }
4009
4010 switch (protocol) {
09640e63 4011 case cpu_to_be16(ETH_P_IP):
9d5c8243 4012 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
44b0cda3
MW		 4013 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4014 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
b9473560
JB		 4015 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
4016 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
44b0cda3 4017 break;
09640e63 4018 case cpu_to_be16(ETH_P_IPV6):
44b0cda3
MW		 4019 /* XXX what about other V6 headers?? */
4020 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4021 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
b9473560
JB		 4022 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
4023 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
44b0cda3
MW		 4024 break;
4025 default:
4026 if (unlikely(net_ratelimit()))
59d71989 4027 dev_warn(dev,
44b0cda3
MW		 4028 "partial checksum but proto=%x!\n",
4029 skb->protocol);
4030 break;
4031 }
9d5c8243
AK		 4032 }
4033
4034 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
4035 context_desc->seqnum_seed = 0;
85ad76b2 4036 if (tx_ring->flags & IGB_RING_FLAG_TX_CTX_IDX)
7dfc16fa 4037 context_desc->mss_l4len_idx =
85ad76b2 4038 cpu_to_le32(tx_ring->reg_idx << 4);
9d5c8243
AK		 4039
4040 buffer_info->time_stamp = jiffies;
0e014cb1 4041 buffer_info->next_to_watch = i;
9d5c8243
AK		 4042 buffer_info->dma = 0;
4043
4044 i++;
4045 if (i == tx_ring->count)
4046 i = 0;
4047 tx_ring->next_to_use = i;
4048
4049 return true;
4050 }
9d5c8243
AK		 4051 return false;
4052}
4053
4054#define IGB_MAX_TXD_PWR 16
4055#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
4056
80785298 4057static inline int igb_tx_map_adv(struct igb_ring *tx_ring, struct sk_buff *skb,
0e014cb1 4058 unsigned int first)
9d5c8243
AK		 4059{
4060 struct igb_buffer *buffer_info;
59d71989 4061 struct device *dev = tx_ring->dev;
2873957d 4062 unsigned int hlen = skb_headlen(skb);
9d5c8243
AK		 4063 unsigned int count = 0, i;
4064 unsigned int f;
2873957d 4065 u16 gso_segs = skb_shinfo(skb)->gso_segs ?: 1;
9d5c8243
AK		 4066
4067 i = tx_ring->next_to_use;
4068
4069 buffer_info = &tx_ring->buffer_info[i];
2873957d
NN		 4070 BUG_ON(hlen >= IGB_MAX_DATA_PER_TXD);
4071 buffer_info->length = hlen;
9d5c8243
AK		 4072 /* set time_stamp *before* dma to help avoid a possible race */
4073 buffer_info->time_stamp = jiffies;
0e014cb1 4074 buffer_info->next_to_watch = i;
2873957d 4075 buffer_info->dma = dma_map_single(dev, skb->data, hlen,
59d71989
AD		 4076 DMA_TO_DEVICE);
4077 if (dma_mapping_error(dev, buffer_info->dma))
6366ad33 4078 goto dma_error;
9d5c8243
AK		 4079
4080 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
2873957d
NN		 4081 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[f];
4082 unsigned int len = frag->size;
9d5c8243 4083
8581145f 4084 count++;
65689fef
AD		 4085 i++;
4086 if (i == tx_ring->count)
4087 i = 0;
4088
9d5c8243
AK		 4089 buffer_info = &tx_ring->buffer_info[i];
4090 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
4091 buffer_info->length = len;
4092 buffer_info->time_stamp = jiffies;
0e014cb1 4093 buffer_info->next_to_watch = i;
6366ad33 4094 buffer_info->mapped_as_page = true;
59d71989 4095 buffer_info->dma = dma_map_page(dev,
6366ad33
AD		 4096 frag->page,
4097 frag->page_offset,
4098 len,
59d71989
AD		 4099 DMA_TO_DEVICE);
4100 if (dma_mapping_error(dev, buffer_info->dma))
6366ad33
AD		 4101 goto dma_error;
4102
9d5c8243
AK		 4103 }
4104
9d5c8243 4105 tx_ring->buffer_info[i].skb = skb;
2244d07b 4106 tx_ring->buffer_info[i].tx_flags = skb_shinfo(skb)->tx_flags;
2873957d
NN		 4107 /* multiply data chunks by size of headers */
4108 tx_ring->buffer_info[i].bytecount = ((gso_segs - 1) * hlen) + skb->len;
4109 tx_ring->buffer_info[i].gso_segs = gso_segs;
0e014cb1 4110 tx_ring->buffer_info[first].next_to_watch = i;
9d5c8243 4111
cdfd01fc 4112 return ++count;
6366ad33
AD		 4113
4114dma_error:
59d71989 4115 dev_err(dev, "TX DMA map failed\n");
6366ad33
AD		 4116
4117 /* clear timestamp and dma mappings for failed buffer_info mapping */
4118 buffer_info->dma = 0;
4119 buffer_info->time_stamp = 0;
4120 buffer_info->length = 0;
4121 buffer_info->next_to_watch = 0;
4122 buffer_info->mapped_as_page = false;
6366ad33
AD		 4123
4124 /* clear timestamp and dma mappings for remaining portion of packet */
a77ff709
NN		 4125 while (count--) {
4126 if (i == 0)
4127 i = tx_ring->count;
6366ad33 4128 i--;
6366ad33
AD		 4129 buffer_info = &tx_ring->buffer_info[i];
4130 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
4131 }
4132
4133 return 0;
9d5c8243
AK		 4134}
4135
85ad76b2 4136static inline void igb_tx_queue_adv(struct igb_ring *tx_ring,
91d4ee33 4137 u32 tx_flags, int count, u32 paylen,
9d5c8243
AK		 4138 u8 hdr_len)
4139{
cdfd01fc 4140 union e1000_adv_tx_desc *tx_desc;
9d5c8243
AK		 4141 struct igb_buffer *buffer_info;
4142 u32 olinfo_status = 0, cmd_type_len;
cdfd01fc 4143 unsigned int i = tx_ring->next_to_use;
9d5c8243
AK		 4144
4145 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
4146 E1000_ADVTXD_DCMD_DEXT);
4147
4148 if (tx_flags & IGB_TX_FLAGS_VLAN)
4149 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
4150
33af6bcc
PO		 4151 if (tx_flags & IGB_TX_FLAGS_TSTAMP)
4152 cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP;
4153
9d5c8243
AK		 4154 if (tx_flags & IGB_TX_FLAGS_TSO) {
4155 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
4156
4157 /* insert tcp checksum */
4158 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
4159
4160 /* insert ip checksum */
4161 if (tx_flags & IGB_TX_FLAGS_IPV4)
4162 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
4163
4164 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
4165 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
4166 }
4167
85ad76b2
AD		 4168 if ((tx_ring->flags & IGB_RING_FLAG_TX_CTX_IDX) &&
4169 (tx_flags & (IGB_TX_FLAGS_CSUM |
4170 IGB_TX_FLAGS_TSO |
7dfc16fa 4171 IGB_TX_FLAGS_VLAN)))
85ad76b2 4172 olinfo_status |= tx_ring->reg_idx << 4;
9d5c8243
AK		 4173
4174 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
4175
cdfd01fc 4176 do {
9d5c8243
AK		 4177 buffer_info = &tx_ring->buffer_info[i];
4178 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
4179 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
4180 tx_desc->read.cmd_type_len =
4181 cpu_to_le32(cmd_type_len | buffer_info->length);
4182 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
cdfd01fc 4183 count--;
9d5c8243
AK		 4184 i++;
4185 if (i == tx_ring->count)
4186 i = 0;
cdfd01fc 4187 } while (count > 0);
9d5c8243 4188
85ad76b2 4189 tx_desc->read.cmd_type_len |= cpu_to_le32(IGB_ADVTXD_DCMD);
9d5c8243
AK		 4190 /* Force memory writes to complete before letting h/w
4191 * know there are new descriptors to fetch. (Only
4192 * applicable for weak-ordered memory model archs,
4193 * such as IA-64). */
4194 wmb();
4195
4196 tx_ring->next_to_use = i;
fce99e34 4197 writel(i, tx_ring->tail);
9d5c8243
AK		 4198 /* we need this if more than one processor can write to our tail
4199 * at a time, it syncronizes IO on IA64/Altix systems */
4200 mmiowb();
4201}
4202
e694e964 4203static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, int size)
9d5c8243 4204{
e694e964
AD		 4205 struct net_device *netdev = tx_ring->netdev;
4206
661086df 4207 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 4208
9d5c8243
AK		 4209 /* Herbert's original patch had:
4210 * smp_mb__after_netif_stop_queue();
4211 * but since that doesn't exist yet, just open code it. */
4212 smp_mb();
4213
4214 /* We need to check again in a case another CPU has just
4215 * made room available. */
c493ea45 4216 if (igb_desc_unused(tx_ring) < size)
9d5c8243
AK		 4217 return -EBUSY;
4218
4219 /* A reprieve! */
661086df 4220 netif_wake_subqueue(netdev, tx_ring->queue_index);
12dcd86b
ED		 4221
4222 u64_stats_update_begin(&tx_ring->tx_syncp2);
4223 tx_ring->tx_stats.restart_queue2++;
4224 u64_stats_update_end(&tx_ring->tx_syncp2);
4225
9d5c8243
AK		 4226 return 0;
4227}
4228
717ba089 4229static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, int size)
9d5c8243 4230{
c493ea45 4231 if (igb_desc_unused(tx_ring) >= size)
9d5c8243 4232 return 0;
e694e964 4233 return __igb_maybe_stop_tx(tx_ring, size);
9d5c8243
AK		 4234}
4235
b1a436c3
AD		 4236netdev_tx_t igb_xmit_frame_ring_adv(struct sk_buff *skb,
4237 struct igb_ring *tx_ring)
9d5c8243 4238{
cdfd01fc 4239 int tso = 0, count;
91d4ee33
NN		 4240 u32 tx_flags = 0;
4241 u16 first;
4242 u8 hdr_len = 0;
9d5c8243 4243
9d5c8243
AK		 4244 /* need: 1 descriptor per page,
4245 * + 2 desc gap to keep tail from touching head,
4246 * + 1 desc for skb->data,
4247 * + 1 desc for context descriptor,
4248 * otherwise try next time */
e694e964 4249 if (igb_maybe_stop_tx(tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
9d5c8243 4250 /* this is a hard error */
9d5c8243
AK		 4251 return NETDEV_TX_BUSY;
4252 }
33af6bcc 4253
2244d07b
OH		 4254 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
4255 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
33af6bcc 4256 tx_flags |= IGB_TX_FLAGS_TSTAMP;
33af6bcc 4257 }
9d5c8243 4258
eab6d18d 4259 if (vlan_tx_tag_present(skb)) {
9d5c8243
AK		 4260 tx_flags |= IGB_TX_FLAGS_VLAN;
4261 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
4262 }
4263
661086df
PWJ		 4264 if (skb->protocol == htons(ETH_P_IP))
4265 tx_flags |= IGB_TX_FLAGS_IPV4;
4266
0e014cb1 4267 first = tx_ring->next_to_use;
85ad76b2
AD		 4268 if (skb_is_gso(skb)) {
4269 tso = igb_tso_adv(tx_ring, skb, tx_flags, &hdr_len);
cdfd01fc 4270
85ad76b2
AD		 4271 if (tso < 0) {
4272 dev_kfree_skb_any(skb);
4273 return NETDEV_TX_OK;
4274 }
9d5c8243
AK		 4275 }
4276
4277 if (tso)
4278 tx_flags |= IGB_TX_FLAGS_TSO;
85ad76b2 4279 else if (igb_tx_csum_adv(tx_ring, skb, tx_flags) &&
bc1cbd34
AD		 4280 (skb->ip_summed == CHECKSUM_PARTIAL))
4281 tx_flags |= IGB_TX_FLAGS_CSUM;
9d5c8243 4282
65689fef 4283 /*
cdfd01fc 4284 * count reflects descriptors mapped, if 0 or less then mapping error
65689fef
AD		 4285 * has occured and we need to rewind the descriptor queue
4286 */
80785298 4287 count = igb_tx_map_adv(tx_ring, skb, first);
6366ad33 4288 if (!count) {
65689fef
AD		 4289 dev_kfree_skb_any(skb);
4290 tx_ring->buffer_info[first].time_stamp = 0;
4291 tx_ring->next_to_use = first;
85ad76b2 4292 return NETDEV_TX_OK;
65689fef 4293 }
9d5c8243 4294
85ad76b2
AD		 4295 igb_tx_queue_adv(tx_ring, tx_flags, count, skb->len, hdr_len);
4296
4297 /* Make sure there is space in the ring for the next send. */
e694e964 4298 igb_maybe_stop_tx(tx_ring, MAX_SKB_FRAGS + 4);
85ad76b2 4299
9d5c8243
AK		 4300 return NETDEV_TX_OK;
4301}
4302
3b29a56d
SH		 4303static netdev_tx_t igb_xmit_frame_adv(struct sk_buff *skb,
4304 struct net_device *netdev)
9d5c8243
AK		 4305{
4306 struct igb_adapter *adapter = netdev_priv(netdev);
661086df 4307 struct igb_ring *tx_ring;
661086df 4308 int r_idx = 0;
b1a436c3
AD		 4309
4310 if (test_bit(__IGB_DOWN, &adapter->state)) {
4311 dev_kfree_skb_any(skb);
4312 return NETDEV_TX_OK;
4313 }
4314
4315 if (skb->len <= 0) {
4316 dev_kfree_skb_any(skb);
4317 return NETDEV_TX_OK;
4318 }
4319
1bfaf07b 4320 r_idx = skb->queue_mapping & (IGB_ABS_MAX_TX_QUEUES - 1);
661086df 4321 tx_ring = adapter->multi_tx_table[r_idx];
9d5c8243
AK		 4322
4323 /* This goes back to the question of how to logically map a tx queue
4324 * to a flow. Right now, performance is impacted slightly negatively
4325 * if using multiple tx queues. If the stack breaks away from a
4326 * single qdisc implementation, we can look at this again. */
e694e964 4327 return igb_xmit_frame_ring_adv(skb, tx_ring);
9d5c8243
AK		 4328}
4329
4330/**
4331 * igb_tx_timeout - Respond to a Tx Hang
4332 * @netdev: network interface device structure
4333 **/
4334static void igb_tx_timeout(struct net_device *netdev)
4335{
4336 struct igb_adapter *adapter = netdev_priv(netdev);
4337 struct e1000_hw *hw = &adapter->hw;
4338
4339 /* Do the reset outside of interrupt context */
4340 adapter->tx_timeout_count++;
f7ba205e 4341
55cac248
AD		 4342 if (hw->mac.type == e1000_82580)
4343 hw->dev_spec._82575.global_device_reset = true;
4344
9d5c8243 4345 schedule_work(&adapter->reset_task);
265de409
AD		 4346 wr32(E1000_EICS,
4347 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 4348}
4349
4350static void igb_reset_task(struct work_struct *work)
4351{
4352 struct igb_adapter *adapter;
4353 adapter = container_of(work, struct igb_adapter, reset_task);
4354
c97ec42a
TI		 4355 igb_dump(adapter);
4356 netdev_err(adapter->netdev, "Reset adapter\n");
9d5c8243
AK		 4357 igb_reinit_locked(adapter);
4358}
4359
4360/**
12dcd86b 4361 * igb_get_stats64 - Get System Network Statistics
9d5c8243 4362 * @netdev: network interface device structure
12dcd86b 4363 * @stats: rtnl_link_stats64 pointer
9d5c8243 4364 *
9d5c8243 4365 **/
12dcd86b
ED		 4366static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
4367 struct rtnl_link_stats64 *stats)
9d5c8243 4368{
12dcd86b
ED		 4369 struct igb_adapter *adapter = netdev_priv(netdev);
4370
4371 spin_lock(&adapter->stats64_lock);
4372 igb_update_stats(adapter, &adapter->stats64);
4373 memcpy(stats, &adapter->stats64, sizeof(*stats));
4374 spin_unlock(&adapter->stats64_lock);
4375
4376 return stats;
9d5c8243
AK		 4377}
4378
4379/**
4380 * igb_change_mtu - Change the Maximum Transfer Unit
4381 * @netdev: network interface device structure
4382 * @new_mtu: new value for maximum frame size
4383 *
4384 * Returns 0 on success, negative on failure
4385 **/
4386static int igb_change_mtu(struct net_device *netdev, int new_mtu)
4387{
4388 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 4389 struct pci_dev *pdev = adapter->pdev;
9d5c8243 4390 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4c844851 4391 u32 rx_buffer_len, i;
9d5c8243 4392
c809d227 4393 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
090b1795 4394 dev_err(&pdev->dev, "Invalid MTU setting\n");
9d5c8243
AK		 4395 return -EINVAL;
4396 }
4397
9d5c8243 4398 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
090b1795 4399 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
9d5c8243
AK		 4400 return -EINVAL;
4401 }
4402
4403 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
4404 msleep(1);
73cd78f1 4405
9d5c8243
AK		 4406 /* igb_down has a dependency on max_frame_size */
4407 adapter->max_frame_size = max_frame;
559e9c49 4408
9d5c8243
AK		 4409 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
4410 * means we reserve 2 more, this pushes us to allocate from the next
4411 * larger slab size.
4412 * i.e. RXBUFFER_2048 --> size-4096 slab
4413 */
4414
757b77e2
NN		 4415 if (adapter->hw.mac.type == e1000_82580)
4416 max_frame += IGB_TS_HDR_LEN;
4417
7d95b717 4418 if (max_frame <= IGB_RXBUFFER_1024)
4c844851 4419 rx_buffer_len = IGB_RXBUFFER_1024;
6ec43fe6 4420 else if (max_frame <= MAXIMUM_ETHERNET_VLAN_SIZE)
4c844851 4421 rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
6ec43fe6 4422 else
4c844851
AD		 4423 rx_buffer_len = IGB_RXBUFFER_128;
4424
757b77e2
NN		 4425 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN + IGB_TS_HDR_LEN) ||
4426 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE + IGB_TS_HDR_LEN))
4427 rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE + IGB_TS_HDR_LEN;
4428
4429 if ((adapter->hw.mac.type == e1000_82580) &&
4430 (rx_buffer_len == IGB_RXBUFFER_128))
4431 rx_buffer_len += IGB_RXBUFFER_64;
4432
4c844851
AD		 4433 if (netif_running(netdev))
4434 igb_down(adapter);
9d5c8243 4435
090b1795 4436 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
9d5c8243
AK		 4437 netdev->mtu, new_mtu);
4438 netdev->mtu = new_mtu;
4439
4c844851 4440 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 4441 adapter->rx_ring[i]->rx_buffer_len = rx_buffer_len;
4c844851 4442
9d5c8243
AK		 4443 if (netif_running(netdev))
4444 igb_up(adapter);
4445 else
4446 igb_reset(adapter);
4447
4448 clear_bit(__IGB_RESETTING, &adapter->state);
4449
4450 return 0;
4451}
4452
4453/**
4454 * igb_update_stats - Update the board statistics counters
4455 * @adapter: board private structure
4456 **/
4457
12dcd86b
ED		 4458void igb_update_stats(struct igb_adapter *adapter,
4459 struct rtnl_link_stats64 *net_stats)
9d5c8243
AK		 4460{
4461 struct e1000_hw *hw = &adapter->hw;
4462 struct pci_dev *pdev = adapter->pdev;
fa3d9a6d 4463 u32 reg, mpc;
9d5c8243 4464 u16 phy_tmp;
3f9c0164
AD		 4465 int i;
4466 u64 bytes, packets;
12dcd86b
ED		 4467 unsigned int start;
4468 u64 _bytes, _packets;
9d5c8243
AK		 4469
4470#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
4471
4472 /*
4473 * Prevent stats update while adapter is being reset, or if the pci
4474 * connection is down.
4475 */
4476 if (adapter->link_speed == 0)
4477 return;
4478 if (pci_channel_offline(pdev))
4479 return;
4480
3f9c0164
AD		 4481 bytes = 0;
4482 packets = 0;
4483 for (i = 0; i < adapter->num_rx_queues; i++) {
4484 u32 rqdpc_tmp = rd32(E1000_RQDPC(i)) & 0x0FFF;
3025a446 4485 struct igb_ring *ring = adapter->rx_ring[i];
12dcd86b 4486
3025a446 4487 ring->rx_stats.drops += rqdpc_tmp;
128e45eb 4488 net_stats->rx_fifo_errors += rqdpc_tmp;
12dcd86b
ED		 4489
4490 do {
4491 start = u64_stats_fetch_begin_bh(&ring->rx_syncp);
4492 _bytes = ring->rx_stats.bytes;
4493 _packets = ring->rx_stats.packets;
4494 } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start));
4495 bytes += _bytes;
4496 packets += _packets;
3f9c0164
AD		 4497 }
4498
128e45eb
AD		 4499 net_stats->rx_bytes = bytes;
4500 net_stats->rx_packets = packets;
3f9c0164
AD		 4501
4502 bytes = 0;
4503 packets = 0;
4504 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 4505 struct igb_ring *ring = adapter->tx_ring[i];
12dcd86b
ED		 4506 do {
4507 start = u64_stats_fetch_begin_bh(&ring->tx_syncp);
4508 _bytes = ring->tx_stats.bytes;
4509 _packets = ring->tx_stats.packets;
4510 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start));
4511 bytes += _bytes;
4512 packets += _packets;
3f9c0164 4513 }
128e45eb
AD		 4514 net_stats->tx_bytes = bytes;
4515 net_stats->tx_packets = packets;
3f9c0164
AD		 4516
4517 /* read stats registers */
9d5c8243
AK		 4518 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
4519 adapter->stats.gprc += rd32(E1000_GPRC);
4520 adapter->stats.gorc += rd32(E1000_GORCL);
4521 rd32(E1000_GORCH); /* clear GORCL */
4522 adapter->stats.bprc += rd32(E1000_BPRC);
4523 adapter->stats.mprc += rd32(E1000_MPRC);
4524 adapter->stats.roc += rd32(E1000_ROC);
4525
4526 adapter->stats.prc64 += rd32(E1000_PRC64);
4527 adapter->stats.prc127 += rd32(E1000_PRC127);
4528 adapter->stats.prc255 += rd32(E1000_PRC255);
4529 adapter->stats.prc511 += rd32(E1000_PRC511);
4530 adapter->stats.prc1023 += rd32(E1000_PRC1023);
4531 adapter->stats.prc1522 += rd32(E1000_PRC1522);
4532 adapter->stats.symerrs += rd32(E1000_SYMERRS);
4533 adapter->stats.sec += rd32(E1000_SEC);
4534
fa3d9a6d
MW		 4535 mpc = rd32(E1000_MPC);
4536 adapter->stats.mpc += mpc;
4537 net_stats->rx_fifo_errors += mpc;
9d5c8243
AK		 4538 adapter->stats.scc += rd32(E1000_SCC);
4539 adapter->stats.ecol += rd32(E1000_ECOL);
4540 adapter->stats.mcc += rd32(E1000_MCC);
4541 adapter->stats.latecol += rd32(E1000_LATECOL);
4542 adapter->stats.dc += rd32(E1000_DC);
4543 adapter->stats.rlec += rd32(E1000_RLEC);
4544 adapter->stats.xonrxc += rd32(E1000_XONRXC);
4545 adapter->stats.xontxc += rd32(E1000_XONTXC);
4546 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
4547 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
4548 adapter->stats.fcruc += rd32(E1000_FCRUC);
4549 adapter->stats.gptc += rd32(E1000_GPTC);
4550 adapter->stats.gotc += rd32(E1000_GOTCL);
4551 rd32(E1000_GOTCH); /* clear GOTCL */
fa3d9a6d 4552 adapter->stats.rnbc += rd32(E1000_RNBC);
9d5c8243
AK		 4553 adapter->stats.ruc += rd32(E1000_RUC);
4554 adapter->stats.rfc += rd32(E1000_RFC);
4555 adapter->stats.rjc += rd32(E1000_RJC);
4556 adapter->stats.tor += rd32(E1000_TORH);
4557 adapter->stats.tot += rd32(E1000_TOTH);
4558 adapter->stats.tpr += rd32(E1000_TPR);
4559
4560 adapter->stats.ptc64 += rd32(E1000_PTC64);
4561 adapter->stats.ptc127 += rd32(E1000_PTC127);
4562 adapter->stats.ptc255 += rd32(E1000_PTC255);
4563 adapter->stats.ptc511 += rd32(E1000_PTC511);
4564 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
4565 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
4566
4567 adapter->stats.mptc += rd32(E1000_MPTC);
4568 adapter->stats.bptc += rd32(E1000_BPTC);
4569
2d0b0f69
NN		 4570 adapter->stats.tpt += rd32(E1000_TPT);
4571 adapter->stats.colc += rd32(E1000_COLC);
9d5c8243
AK		 4572
4573 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
43915c7c
NN		 4574 /* read internal phy specific stats */
4575 reg = rd32(E1000_CTRL_EXT);
4576 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
4577 adapter->stats.rxerrc += rd32(E1000_RXERRC);
4578 adapter->stats.tncrs += rd32(E1000_TNCRS);
4579 }
4580
9d5c8243
AK		 4581 adapter->stats.tsctc += rd32(E1000_TSCTC);
4582 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
4583
4584 adapter->stats.iac += rd32(E1000_IAC);
4585 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
4586 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
4587 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
4588 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
4589 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
4590 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
4591 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
4592 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
4593
4594 /* Fill out the OS statistics structure */
128e45eb
AD		 4595 net_stats->multicast = adapter->stats.mprc;
4596 net_stats->collisions = adapter->stats.colc;
9d5c8243
AK		 4597
4598 /* Rx Errors */
4599
4600 /* RLEC on some newer hardware can be incorrect so build
8c0ab70a 4601 * our own version based on RUC and ROC */
128e45eb 4602 net_stats->rx_errors = adapter->stats.rxerrc +
9d5c8243
AK		 4603 adapter->stats.crcerrs + adapter->stats.algnerrc +
4604 adapter->stats.ruc + adapter->stats.roc +
4605 adapter->stats.cexterr;
128e45eb
AD		 4606 net_stats->rx_length_errors = adapter->stats.ruc +
4607 adapter->stats.roc;
4608 net_stats->rx_crc_errors = adapter->stats.crcerrs;
4609 net_stats->rx_frame_errors = adapter->stats.algnerrc;
4610 net_stats->rx_missed_errors = adapter->stats.mpc;
9d5c8243
AK		 4611
4612 /* Tx Errors */
128e45eb
AD		 4613 net_stats->tx_errors = adapter->stats.ecol +
4614 adapter->stats.latecol;
4615 net_stats->tx_aborted_errors = adapter->stats.ecol;
4616 net_stats->tx_window_errors = adapter->stats.latecol;
4617 net_stats->tx_carrier_errors = adapter->stats.tncrs;
9d5c8243
AK		 4618
4619 /* Tx Dropped needs to be maintained elsewhere */
4620
4621 /* Phy Stats */
4622 if (hw->phy.media_type == e1000_media_type_copper) {
4623 if ((adapter->link_speed == SPEED_1000) &&
73cd78f1 4624 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
9d5c8243
AK		 4625 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
4626 adapter->phy_stats.idle_errors += phy_tmp;
4627 }
4628 }
4629
4630 /* Management Stats */
4631 adapter->stats.mgptc += rd32(E1000_MGTPTC);
4632 adapter->stats.mgprc += rd32(E1000_MGTPRC);
4633 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
0a915b95
CW		 4634
4635 /* OS2BMC Stats */
4636 reg = rd32(E1000_MANC);
4637 if (reg & E1000_MANC_EN_BMC2OS) {
4638 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
4639 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
4640 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
4641 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
4642 }
9d5c8243
AK		 4643}
4644
9d5c8243
AK		 4645static irqreturn_t igb_msix_other(int irq, void *data)
4646{
047e0030 4647 struct igb_adapter *adapter = data;
9d5c8243 4648 struct e1000_hw *hw = &adapter->hw;
844290e5 4649 u32 icr = rd32(E1000_ICR);
844290e5 4650 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083 4651
7f081d40
AD		 4652 if (icr & E1000_ICR_DRSTA)
4653 schedule_work(&adapter->reset_task);
4654
047e0030 4655 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 4656 /* HW is reporting DMA is out of sync */
4657 adapter->stats.doosync++;
13800469
GR		 4658 /* The DMA Out of Sync is also indication of a spoof event
4659 * in IOV mode. Check the Wrong VM Behavior register to
4660 * see if it is really a spoof event. */
4661 igb_check_wvbr(adapter);
dda0e083 4662 }
eebbbdba 4663
4ae196df
AD		 4664 /* Check for a mailbox event */
4665 if (icr & E1000_ICR_VMMB)
4666 igb_msg_task(adapter);
4667
4668 if (icr & E1000_ICR_LSC) {
4669 hw->mac.get_link_status = 1;
4670 /* guard against interrupt when we're going down */
4671 if (!test_bit(__IGB_DOWN, &adapter->state))
4672 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4673 }
4674
25568a53
AD		 4675 if (adapter->vfs_allocated_count)
4676 wr32(E1000_IMS, E1000_IMS_LSC |
4677 E1000_IMS_VMMB |
4678 E1000_IMS_DOUTSYNC);
4679 else
4680 wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC);
844290e5 4681 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 4682
4683 return IRQ_HANDLED;
4684}
4685
047e0030 4686static void igb_write_itr(struct igb_q_vector *q_vector)
9d5c8243 4687{
26b39276 4688 struct igb_adapter *adapter = q_vector->adapter;
047e0030 4689 u32 itr_val = q_vector->itr_val & 0x7FFC;
9d5c8243 4690
047e0030
AD		 4691 if (!q_vector->set_itr)
4692 return;
73cd78f1 4693
047e0030
AD		 4694 if (!itr_val)
4695 itr_val = 0x4;
661086df 4696
26b39276
AD		 4697 if (adapter->hw.mac.type == e1000_82575)
4698 itr_val |= itr_val << 16;
661086df 4699 else
047e0030 4700 itr_val |= 0x8000000;
661086df 4701
047e0030
AD		 4702 writel(itr_val, q_vector->itr_register);
4703 q_vector->set_itr = 0;
6eb5a7f1
AD		 4704}
4705
047e0030 4706static irqreturn_t igb_msix_ring(int irq, void *data)
9d5c8243 4707{
047e0030 4708 struct igb_q_vector *q_vector = data;
9d5c8243 4709
047e0030
AD		 4710 /* Write the ITR value calculated from the previous interrupt. */
4711 igb_write_itr(q_vector);
9d5c8243 4712
047e0030 4713 napi_schedule(&q_vector->napi);
844290e5 4714
047e0030 4715 return IRQ_HANDLED;
fe4506b6
JC		 4716}
4717
421e02f0 4718#ifdef CONFIG_IGB_DCA
047e0030 4719static void igb_update_dca(struct igb_q_vector *q_vector)
fe4506b6 4720{
047e0030 4721 struct igb_adapter *adapter = q_vector->adapter;
fe4506b6
JC		 4722 struct e1000_hw *hw = &adapter->hw;
4723 int cpu = get_cpu();
fe4506b6 4724
047e0030
AD		 4725 if (q_vector->cpu == cpu)
4726 goto out_no_update;
4727
4728 if (q_vector->tx_ring) {
4729 int q = q_vector->tx_ring->reg_idx;
4730 u32 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
4731 if (hw->mac.type == e1000_82575) {
4732 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
4733 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
2d064c06 4734 } else {
047e0030
AD		 4735 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
4736 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
4737 E1000_DCA_TXCTRL_CPUID_SHIFT;
4738 }
4739 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
4740 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
4741 }
4742 if (q_vector->rx_ring) {
4743 int q = q_vector->rx_ring->reg_idx;
4744 u32 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
4745 if (hw->mac.type == e1000_82575) {
2d064c06 4746 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
92be7917 4747 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
047e0030
AD		 4748 } else {
4749 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
4750 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
4751 E1000_DCA_RXCTRL_CPUID_SHIFT;
2d064c06 4752 }
fe4506b6
JC		 4753 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
4754 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
4755 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
4756 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
fe4506b6 4757 }
047e0030
AD		 4758 q_vector->cpu = cpu;
4759out_no_update:
fe4506b6
JC		 4760 put_cpu();
4761}
4762
4763static void igb_setup_dca(struct igb_adapter *adapter)
4764{
7e0e99ef 4765 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 4766 int i;
4767
7dfc16fa 4768 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 4769 return;
4770
7e0e99ef
AD		 4771 /* Always use CB2 mode, difference is masked in the CB driver. */
4772 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
4773
047e0030 4774 for (i = 0; i < adapter->num_q_vectors; i++) {
26b39276
AD		 4775 adapter->q_vector[i]->cpu = -1;
4776 igb_update_dca(adapter->q_vector[i]);
fe4506b6
JC		 4777 }
4778}
4779
4780static int __igb_notify_dca(struct device *dev, void *data)
4781{
4782 struct net_device *netdev = dev_get_drvdata(dev);
4783 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 4784 struct pci_dev *pdev = adapter->pdev;
fe4506b6
JC		 4785 struct e1000_hw *hw = &adapter->hw;
4786 unsigned long event = *(unsigned long *)data;
4787
4788 switch (event) {
4789 case DCA_PROVIDER_ADD:
4790 /* if already enabled, don't do it again */
7dfc16fa 4791 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 4792 break;
fe4506b6 4793 if (dca_add_requester(dev) == 0) {
bbd98fe4 4794 adapter->flags |= IGB_FLAG_DCA_ENABLED;
090b1795 4795 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 4796 igb_setup_dca(adapter);
4797 break;
4798 }
4799 /* Fall Through since DCA is disabled. */
4800 case DCA_PROVIDER_REMOVE:
7dfc16fa 4801 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6 4802 /* without this a class_device is left
047e0030 4803 * hanging around in the sysfs model */
fe4506b6 4804 dca_remove_requester(dev);
090b1795 4805 dev_info(&pdev->dev, "DCA disabled\n");
7dfc16fa 4806 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 4807 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 4808 }
4809 break;
4810 }
bbd98fe4 4811
fe4506b6 4812 return 0;
9d5c8243
AK		 4813}
4814
fe4506b6
JC		 4815static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
4816 void *p)
4817{
4818 int ret_val;
4819
4820 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
4821 __igb_notify_dca);
4822
4823 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
4824}
421e02f0 4825#endif /* CONFIG_IGB_DCA */
9d5c8243 4826
4ae196df
AD		 4827static void igb_ping_all_vfs(struct igb_adapter *adapter)
4828{
4829 struct e1000_hw *hw = &adapter->hw;
4830 u32 ping;
4831 int i;
4832
4833 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
4834 ping = E1000_PF_CONTROL_MSG;
f2ca0dbe 4835 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
4ae196df
AD		 4836 ping |= E1000_VT_MSGTYPE_CTS;
4837 igb_write_mbx(hw, &ping, 1, i);
4838 }
4839}
4840
7d5753f0
AD		 4841static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
4842{
4843 struct e1000_hw *hw = &adapter->hw;
4844 u32 vmolr = rd32(E1000_VMOLR(vf));
4845 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4846
d85b9004 4847 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
7d5753f0
AD		 4848 IGB_VF_FLAG_MULTI_PROMISC);
4849 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
4850
4851 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
4852 vmolr |= E1000_VMOLR_MPME;
d85b9004 4853 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
7d5753f0
AD		 4854 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
4855 } else {
4856 /*
4857 * if we have hashes and we are clearing a multicast promisc
4858 * flag we need to write the hashes to the MTA as this step
4859 * was previously skipped
4860 */
4861 if (vf_data->num_vf_mc_hashes > 30) {
4862 vmolr |= E1000_VMOLR_MPME;
4863 } else if (vf_data->num_vf_mc_hashes) {
4864 int j;
4865 vmolr |= E1000_VMOLR_ROMPE;
4866 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
4867 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
4868 }
4869 }
4870
4871 wr32(E1000_VMOLR(vf), vmolr);
4872
4873 /* there are flags left unprocessed, likely not supported */
4874 if (*msgbuf & E1000_VT_MSGINFO_MASK)
4875 return -EINVAL;
4876
4877 return 0;
4878
4879}
4880
4ae196df
AD		 4881static int igb_set_vf_multicasts(struct igb_adapter *adapter,
4882 u32 *msgbuf, u32 vf)
4883{
4884 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
4885 u16 *hash_list = (u16 *)&msgbuf[1];
4886 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4887 int i;
4888
7d5753f0 4889 /* salt away the number of multicast addresses assigned
4ae196df
AD		 4890 * to this VF for later use to restore when the PF multi cast
4891 * list changes
4892 */
4893 vf_data->num_vf_mc_hashes = n;
4894
7d5753f0
AD		 4895 /* only up to 30 hash values supported */
4896 if (n > 30)
4897 n = 30;
4898
4899 /* store the hashes for later use */
4ae196df 4900 for (i = 0; i < n; i++)
a419aef8 4901 vf_data->vf_mc_hashes[i] = hash_list[i];
4ae196df
AD		 4902
4903 /* Flush and reset the mta with the new values */
ff41f8dc 4904 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 4905
4906 return 0;
4907}
4908
4909static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
4910{
4911 struct e1000_hw *hw = &adapter->hw;
4912 struct vf_data_storage *vf_data;
4913 int i, j;
4914
4915 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7d5753f0
AD		 4916 u32 vmolr = rd32(E1000_VMOLR(i));
4917 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
4918
4ae196df 4919 vf_data = &adapter->vf_data[i];
7d5753f0
AD		 4920
4921 if ((vf_data->num_vf_mc_hashes > 30) ||
4922 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
4923 vmolr |= E1000_VMOLR_MPME;
4924 } else if (vf_data->num_vf_mc_hashes) {
4925 vmolr |= E1000_VMOLR_ROMPE;
4926 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
4927 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
4928 }
4929 wr32(E1000_VMOLR(i), vmolr);
4ae196df
AD		 4930 }
4931}
4932
4933static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
4934{
4935 struct e1000_hw *hw = &adapter->hw;
4936 u32 pool_mask, reg, vid;
4937 int i;
4938
4939 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
4940
4941 /* Find the vlan filter for this id */
4942 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4943 reg = rd32(E1000_VLVF(i));
4944
4945 /* remove the vf from the pool */
4946 reg &= ~pool_mask;
4947
4948 /* if pool is empty then remove entry from vfta */
4949 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
4950 (reg & E1000_VLVF_VLANID_ENABLE)) {
4951 reg = 0;
4952 vid = reg & E1000_VLVF_VLANID_MASK;
4953 igb_vfta_set(hw, vid, false);
4954 }
4955
4956 wr32(E1000_VLVF(i), reg);
4957 }
ae641bdc
AD		 4958
4959 adapter->vf_data[vf].vlans_enabled = 0;
4ae196df
AD		 4960}
4961
4962static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
4963{
4964 struct e1000_hw *hw = &adapter->hw;
4965 u32 reg, i;
4966
51466239
AD		 4967 /* The vlvf table only exists on 82576 hardware and newer */
4968 if (hw->mac.type < e1000_82576)
4969 return -1;
4970
4971 /* we only need to do this if VMDq is enabled */
4ae196df
AD		 4972 if (!adapter->vfs_allocated_count)
4973 return -1;
4974
4975 /* Find the vlan filter for this id */
4976 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4977 reg = rd32(E1000_VLVF(i));
4978 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
4979 vid == (reg & E1000_VLVF_VLANID_MASK))
4980 break;
4981 }
4982
4983 if (add) {
4984 if (i == E1000_VLVF_ARRAY_SIZE) {
4985 /* Did not find a matching VLAN ID entry that was
4986 * enabled. Search for a free filter entry, i.e.
4987 * one without the enable bit set
4988 */
4989 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4990 reg = rd32(E1000_VLVF(i));
4991 if (!(reg & E1000_VLVF_VLANID_ENABLE))
4992 break;
4993 }
4994 }
4995 if (i < E1000_VLVF_ARRAY_SIZE) {
4996 /* Found an enabled/available entry */
4997 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
4998
4999 /* if !enabled we need to set this up in vfta */
5000 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
51466239
AD		 5001 /* add VID to filter table */
5002 igb_vfta_set(hw, vid, true);
4ae196df
AD		 5003 reg |= E1000_VLVF_VLANID_ENABLE;
5004 }
cad6d05f
AD		 5005 reg &= ~E1000_VLVF_VLANID_MASK;
5006 reg |= vid;
4ae196df 5007 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5008
5009 /* do not modify RLPML for PF devices */
5010 if (vf >= adapter->vfs_allocated_count)
5011 return 0;
5012
5013 if (!adapter->vf_data[vf].vlans_enabled) {
5014 u32 size;
5015 reg = rd32(E1000_VMOLR(vf));
5016 size = reg & E1000_VMOLR_RLPML_MASK;
5017 size += 4;
5018 reg &= ~E1000_VMOLR_RLPML_MASK;
5019 reg |= size;
5020 wr32(E1000_VMOLR(vf), reg);
5021 }
ae641bdc 5022
51466239 5023 adapter->vf_data[vf].vlans_enabled++;
4ae196df
AD		 5024 return 0;
5025 }
5026 } else {
5027 if (i < E1000_VLVF_ARRAY_SIZE) {
5028 /* remove vf from the pool */
5029 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5030 /* if pool is empty then remove entry from vfta */
5031 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5032 reg = 0;
5033 igb_vfta_set(hw, vid, false);
5034 }
5035 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5036
5037 /* do not modify RLPML for PF devices */
5038 if (vf >= adapter->vfs_allocated_count)
5039 return 0;
5040
5041 adapter->vf_data[vf].vlans_enabled--;
5042 if (!adapter->vf_data[vf].vlans_enabled) {
5043 u32 size;
5044 reg = rd32(E1000_VMOLR(vf));
5045 size = reg & E1000_VMOLR_RLPML_MASK;
5046 size -= 4;
5047 reg &= ~E1000_VMOLR_RLPML_MASK;
5048 reg |= size;
5049 wr32(E1000_VMOLR(vf), reg);
5050 }
4ae196df
AD		 5051 }
5052 }
8151d294
WM		 5053 return 0;
5054}
5055
5056static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5057{
5058 struct e1000_hw *hw = &adapter->hw;
5059
5060 if (vid)
5061 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5062 else
5063 wr32(E1000_VMVIR(vf), 0);
5064}
5065
5066static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5067 int vf, u16 vlan, u8 qos)
5068{
5069 int err = 0;
5070 struct igb_adapter *adapter = netdev_priv(netdev);
5071
5072 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5073 return -EINVAL;
5074 if (vlan || qos) {
5075 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5076 if (err)
5077 goto out;
5078 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5079 igb_set_vmolr(adapter, vf, !vlan);
5080 adapter->vf_data[vf].pf_vlan = vlan;
5081 adapter->vf_data[vf].pf_qos = qos;
5082 dev_info(&adapter->pdev->dev,
5083 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5084 if (test_bit(__IGB_DOWN, &adapter->state)) {
5085 dev_warn(&adapter->pdev->dev,
5086 "The VF VLAN has been set,"
5087 " but the PF device is not up.\n");
5088 dev_warn(&adapter->pdev->dev,
5089 "Bring the PF device up before"
5090 " attempting to use the VF device.\n");
5091 }
5092 } else {
5093 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
5094 false, vf);
5095 igb_set_vmvir(adapter, vlan, vf);
5096 igb_set_vmolr(adapter, vf, true);
5097 adapter->vf_data[vf].pf_vlan = 0;
5098 adapter->vf_data[vf].pf_qos = 0;
5099 }
5100out:
5101 return err;
4ae196df
AD		 5102}
5103
5104static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5105{
5106 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5107 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
5108
5109 return igb_vlvf_set(adapter, vid, add, vf);
5110}
5111
f2ca0dbe 5112static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
4ae196df 5113{
8fa7e0f7
GR		 5114 /* clear flags - except flag that indicates PF has set the MAC */
5115 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
f2ca0dbe 5116 adapter->vf_data[vf].last_nack = jiffies;
4ae196df
AD		 5117
5118 /* reset offloads to defaults */
8151d294 5119 igb_set_vmolr(adapter, vf, true);
4ae196df
AD		 5120
5121 /* reset vlans for device */
5122 igb_clear_vf_vfta(adapter, vf);
8151d294
WM		 5123 if (adapter->vf_data[vf].pf_vlan)
5124 igb_ndo_set_vf_vlan(adapter->netdev, vf,
5125 adapter->vf_data[vf].pf_vlan,
5126 adapter->vf_data[vf].pf_qos);
5127 else
5128 igb_clear_vf_vfta(adapter, vf);
4ae196df
AD		 5129
5130 /* reset multicast table array for vf */
5131 adapter->vf_data[vf].num_vf_mc_hashes = 0;
5132
5133 /* Flush and reset the mta with the new values */
ff41f8dc 5134 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5135}
5136
f2ca0dbe
AD		 5137static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
5138{
5139 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5140
5141 /* generate a new mac address as we were hotplug removed/added */
8151d294
WM		 5142 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
5143 random_ether_addr(vf_mac);
f2ca0dbe
AD		 5144
5145 /* process remaining reset events */
5146 igb_vf_reset(adapter, vf);
5147}
5148
5149static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4ae196df
AD		 5150{
5151 struct e1000_hw *hw = &adapter->hw;
5152 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 5153 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 5154 u32 reg, msgbuf[3];
5155 u8 *addr = (u8 *)(&msgbuf[1]);
5156
5157 /* process all the same items cleared in a function level reset */
f2ca0dbe 5158 igb_vf_reset(adapter, vf);
4ae196df
AD		 5159
5160 /* set vf mac address */
26ad9178 5161 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4ae196df
AD		 5162
5163 /* enable transmit and receive for vf */
5164 reg = rd32(E1000_VFTE);
5165 wr32(E1000_VFTE, reg | (1 << vf));
5166 reg = rd32(E1000_VFRE);
5167 wr32(E1000_VFRE, reg | (1 << vf));
5168
8fa7e0f7 5169 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
4ae196df
AD		 5170
5171 /* reply to reset with ack and vf mac address */
5172 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
5173 memcpy(addr, vf_mac, 6);
5174 igb_write_mbx(hw, msgbuf, 3, vf);
5175}
5176
5177static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
5178{
de42edde
GR		 5179 /*
5180 * The VF MAC Address is stored in a packed array of bytes
5181 * starting at the second 32 bit word of the msg array
5182 */
f2ca0dbe
AD		 5183 unsigned char *addr = (char *)&msg[1];
5184 int err = -1;
4ae196df 5185
f2ca0dbe
AD		 5186 if (is_valid_ether_addr(addr))
5187 err = igb_set_vf_mac(adapter, vf, addr);
4ae196df 5188
f2ca0dbe 5189 return err;
4ae196df
AD		 5190}
5191
5192static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
5193{
5194 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 5195 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 5196 u32 msg = E1000_VT_MSGTYPE_NACK;
5197
5198 /* if device isn't clear to send it shouldn't be reading either */
f2ca0dbe
AD		 5199 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
5200 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
4ae196df 5201 igb_write_mbx(hw, &msg, 1, vf);
f2ca0dbe 5202 vf_data->last_nack = jiffies;
4ae196df
AD		 5203 }
5204}
5205
f2ca0dbe 5206static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4ae196df 5207{
f2ca0dbe
AD		 5208 struct pci_dev *pdev = adapter->pdev;
5209 u32 msgbuf[E1000_VFMAILBOX_SIZE];
4ae196df 5210 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 5211 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 5212 s32 retval;
5213
f2ca0dbe 5214 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
4ae196df 5215
fef45f4c
AD		 5216 if (retval) {
5217 /* if receive failed revoke VF CTS stats and restart init */
f2ca0dbe 5218 dev_err(&pdev->dev, "Error receiving message from VF\n");
fef45f4c
AD		 5219 vf_data->flags &= ~IGB_VF_FLAG_CTS;
5220 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5221 return;
5222 goto out;
5223 }
4ae196df
AD		 5224
5225 /* this is a message we already processed, do nothing */
5226 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
f2ca0dbe 5227 return;
4ae196df
AD		 5228
5229 /*
5230 * until the vf completes a reset it should not be
5231 * allowed to start any configuration.
5232 */
5233
5234 if (msgbuf[0] == E1000_VF_RESET) {
5235 igb_vf_reset_msg(adapter, vf);
f2ca0dbe 5236 return;
4ae196df
AD		 5237 }
5238
f2ca0dbe 5239 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
fef45f4c
AD		 5240 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5241 return;
5242 retval = -1;
5243 goto out;
4ae196df
AD		 5244 }
5245
5246 switch ((msgbuf[0] & 0xFFFF)) {
5247 case E1000_VF_SET_MAC_ADDR:
a6b5ea35
GR		 5248 retval = -EINVAL;
5249 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
5250 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
5251 else
5252 dev_warn(&pdev->dev,
5253 "VF %d attempted to override administratively "
5254 "set MAC address\nReload the VF driver to "
5255 "resume operations\n", vf);
4ae196df 5256 break;
7d5753f0
AD		 5257 case E1000_VF_SET_PROMISC:
5258 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
5259 break;
4ae196df
AD		 5260 case E1000_VF_SET_MULTICAST:
5261 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
5262 break;
5263 case E1000_VF_SET_LPE:
5264 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
5265 break;
5266 case E1000_VF_SET_VLAN:
a6b5ea35
GR		 5267 retval = -1;
5268 if (vf_data->pf_vlan)
5269 dev_warn(&pdev->dev,
5270 "VF %d attempted to override administratively "
5271 "set VLAN tag\nReload the VF driver to "
5272 "resume operations\n", vf);
8151d294
WM		 5273 else
5274 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4ae196df
AD		 5275 break;
5276 default:
090b1795 5277 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4ae196df
AD		 5278 retval = -1;
5279 break;
5280 }
5281
fef45f4c
AD		 5282 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
5283out:
4ae196df
AD		 5284 /* notify the VF of the results of what it sent us */
5285 if (retval)
5286 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
5287 else
5288 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
5289
4ae196df 5290 igb_write_mbx(hw, msgbuf, 1, vf);
f2ca0dbe 5291}
4ae196df 5292
f2ca0dbe
AD		 5293static void igb_msg_task(struct igb_adapter *adapter)
5294{
5295 struct e1000_hw *hw = &adapter->hw;
5296 u32 vf;
5297
5298 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
5299 /* process any reset requests */
5300 if (!igb_check_for_rst(hw, vf))
5301 igb_vf_reset_event(adapter, vf);
5302
5303 /* process any messages pending */
5304 if (!igb_check_for_msg(hw, vf))
5305 igb_rcv_msg_from_vf(adapter, vf);
5306
5307 /* process any acks */
5308 if (!igb_check_for_ack(hw, vf))
5309 igb_rcv_ack_from_vf(adapter, vf);
5310 }
4ae196df
AD		 5311}
5312
68d480c4
AD		 5313/**
5314 * igb_set_uta - Set unicast filter table address
5315 * @adapter: board private structure
5316 *
5317 * The unicast table address is a register array of 32-bit registers.
5318 * The table is meant to be used in a way similar to how the MTA is used
5319 * however due to certain limitations in the hardware it is necessary to
5320 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscous
5321 * enable bit to allow vlan tag stripping when promiscous mode is enabled
5322 **/
5323static void igb_set_uta(struct igb_adapter *adapter)
5324{
5325 struct e1000_hw *hw = &adapter->hw;
5326 int i;
5327
5328 /* The UTA table only exists on 82576 hardware and newer */
5329 if (hw->mac.type < e1000_82576)
5330 return;
5331
5332 /* we only need to do this if VMDq is enabled */
5333 if (!adapter->vfs_allocated_count)
5334 return;
5335
5336 for (i = 0; i < hw->mac.uta_reg_count; i++)
5337 array_wr32(E1000_UTA, i, ~0);
5338}
5339
9d5c8243
AK		 5340/**
5341 * igb_intr_msi - Interrupt Handler
5342 * @irq: interrupt number
5343 * @data: pointer to a network interface device structure
5344 **/
5345static irqreturn_t igb_intr_msi(int irq, void *data)
5346{
047e0030
AD		 5347 struct igb_adapter *adapter = data;
5348 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 5349 struct e1000_hw *hw = &adapter->hw;
5350 /* read ICR disables interrupts using IAM */
5351 u32 icr = rd32(E1000_ICR);
5352
047e0030 5353 igb_write_itr(q_vector);
9d5c8243 5354
7f081d40
AD		 5355 if (icr & E1000_ICR_DRSTA)
5356 schedule_work(&adapter->reset_task);
5357
047e0030 5358 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5359 /* HW is reporting DMA is out of sync */
5360 adapter->stats.doosync++;
5361 }
5362
9d5c8243
AK		 5363 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5364 hw->mac.get_link_status = 1;
5365 if (!test_bit(__IGB_DOWN, &adapter->state))
5366 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5367 }
5368
047e0030 5369 napi_schedule(&q_vector->napi);
9d5c8243
AK		 5370
5371 return IRQ_HANDLED;
5372}
5373
5374/**
4a3c6433 5375 * igb_intr - Legacy Interrupt Handler
9d5c8243
AK		 5376 * @irq: interrupt number
5377 * @data: pointer to a network interface device structure
5378 **/
5379static irqreturn_t igb_intr(int irq, void *data)
5380{
047e0030
AD		 5381 struct igb_adapter *adapter = data;
5382 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 5383 struct e1000_hw *hw = &adapter->hw;
5384 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
5385 * need for the IMC write */
5386 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 5387 if (!icr)
5388 return IRQ_NONE; /* Not our interrupt */
5389
047e0030 5390 igb_write_itr(q_vector);
9d5c8243
AK		 5391
5392 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
5393 * not set, then the adapter didn't send an interrupt */
5394 if (!(icr & E1000_ICR_INT_ASSERTED))
5395 return IRQ_NONE;
5396
7f081d40
AD		 5397 if (icr & E1000_ICR_DRSTA)
5398 schedule_work(&adapter->reset_task);
5399
047e0030 5400 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5401 /* HW is reporting DMA is out of sync */
5402 adapter->stats.doosync++;
5403 }
5404
9d5c8243
AK		 5405 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5406 hw->mac.get_link_status = 1;
5407 /* guard against interrupt when we're going down */
5408 if (!test_bit(__IGB_DOWN, &adapter->state))
5409 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5410 }
5411
047e0030 5412 napi_schedule(&q_vector->napi);
9d5c8243
AK		 5413
5414 return IRQ_HANDLED;
5415}
5416
047e0030 5417static inline void igb_ring_irq_enable(struct igb_q_vector *q_vector)
9d5c8243 5418{
047e0030 5419 struct igb_adapter *adapter = q_vector->adapter;
46544258 5420 struct e1000_hw *hw = &adapter->hw;
9d5c8243 5421
4fc82adf
AD		 5422 if ((q_vector->rx_ring && (adapter->rx_itr_setting & 3)) ||
5423 (!q_vector->rx_ring && (adapter->tx_itr_setting & 3))) {
047e0030 5424 if (!adapter->msix_entries)
6eb5a7f1 5425 igb_set_itr(adapter);
46544258 5426 else
047e0030 5427 igb_update_ring_itr(q_vector);
9d5c8243
AK		 5428 }
5429
46544258
AD		 5430 if (!test_bit(__IGB_DOWN, &adapter->state)) {
5431 if (adapter->msix_entries)
047e0030 5432 wr32(E1000_EIMS, q_vector->eims_value);
46544258
AD		 5433 else
5434 igb_irq_enable(adapter);
5435 }
9d5c8243
AK		 5436}
5437
46544258
AD		 5438/**
5439 * igb_poll - NAPI Rx polling callback
5440 * @napi: napi polling structure
5441 * @budget: count of how many packets we should handle
5442 **/
5443static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 5444{
047e0030
AD		 5445 struct igb_q_vector *q_vector = container_of(napi,
5446 struct igb_q_vector,
5447 napi);
5448 int tx_clean_complete = 1, work_done = 0;
9d5c8243 5449
421e02f0 5450#ifdef CONFIG_IGB_DCA
047e0030
AD		 5451 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
5452 igb_update_dca(q_vector);
fe4506b6 5453#endif
047e0030
AD		 5454 if (q_vector->tx_ring)
5455 tx_clean_complete = igb_clean_tx_irq(q_vector);
9d5c8243 5456
047e0030
AD		 5457 if (q_vector->rx_ring)
5458 igb_clean_rx_irq_adv(q_vector, &work_done, budget);
5459
5460 if (!tx_clean_complete)
5461 work_done = budget;
46544258 5462
9d5c8243 5463 /* If not enough Rx work done, exit the polling mode */
5e6d5b17 5464 if (work_done < budget) {
288379f0 5465 napi_complete(napi);
047e0030 5466 igb_ring_irq_enable(q_vector);
9d5c8243
AK		 5467 }
5468
46544258 5469 return work_done;
9d5c8243 5470}
6d8126f9 5471
33af6bcc 5472/**
c5b9bd5e 5473 * igb_systim_to_hwtstamp - convert system time value to hw timestamp
33af6bcc 5474 * @adapter: board private structure
c5b9bd5e
AD		 5475 * @shhwtstamps: timestamp structure to update
5476 * @regval: unsigned 64bit system time value.
5477 *
5478 * We need to convert the system time value stored in the RX/TXSTMP registers
5479 * into a hwtstamp which can be used by the upper level timestamping functions
5480 */
5481static void igb_systim_to_hwtstamp(struct igb_adapter *adapter,
5482 struct skb_shared_hwtstamps *shhwtstamps,
5483 u64 regval)
5484{
5485 u64 ns;
5486
55cac248
AD		 5487 /*
5488 * The 82580 starts with 1ns at bit 0 in RX/TXSTMPL, shift this up to
5489 * 24 to match clock shift we setup earlier.
5490 */
5491 if (adapter->hw.mac.type == e1000_82580)
5492 regval <<= IGB_82580_TSYNC_SHIFT;
5493
c5b9bd5e
AD		 5494 ns = timecounter_cyc2time(&adapter->clock, regval);
5495 timecompare_update(&adapter->compare, ns);
5496 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps));
5497 shhwtstamps->hwtstamp = ns_to_ktime(ns);
5498 shhwtstamps->syststamp = timecompare_transform(&adapter->compare, ns);
5499}
5500
5501/**
5502 * igb_tx_hwtstamp - utility function which checks for TX time stamp
5503 * @q_vector: pointer to q_vector containing needed info
2873957d 5504 * @buffer: pointer to igb_buffer structure
33af6bcc
PO		 5505 *
5506 * If we were asked to do hardware stamping and such a time stamp is
5507 * available, then it must have been for this skb here because we only
5508 * allow only one such packet into the queue.
5509 */
2873957d 5510static void igb_tx_hwtstamp(struct igb_q_vector *q_vector, struct igb_buffer *buffer_info)
33af6bcc 5511{
c5b9bd5e 5512 struct igb_adapter *adapter = q_vector->adapter;
33af6bcc 5513 struct e1000_hw *hw = &adapter->hw;
c5b9bd5e
AD		 5514 struct skb_shared_hwtstamps shhwtstamps;
5515 u64 regval;
33af6bcc 5516
c5b9bd5e 5517 /* if skb does not support hw timestamp or TX stamp not valid exit */
2244d07b 5518 if (likely(!(buffer_info->tx_flags & SKBTX_HW_TSTAMP)) ||
c5b9bd5e
AD		 5519 !(rd32(E1000_TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID))
5520 return;
5521
5522 regval = rd32(E1000_TXSTMPL);
5523 regval |= (u64)rd32(E1000_TXSTMPH) << 32;
5524
5525 igb_systim_to_hwtstamp(adapter, &shhwtstamps, regval);
2873957d 5526 skb_tstamp_tx(buffer_info->skb, &shhwtstamps);
33af6bcc
PO		 5527}
5528
9d5c8243
AK		 5529/**
5530 * igb_clean_tx_irq - Reclaim resources after transmit completes
047e0030 5531 * @q_vector: pointer to q_vector containing needed info
9d5c8243
AK		 5532 * returns true if ring is completely cleaned
5533 **/
047e0030 5534static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
9d5c8243 5535{
047e0030
AD		 5536 struct igb_adapter *adapter = q_vector->adapter;
5537 struct igb_ring *tx_ring = q_vector->tx_ring;
e694e964 5538 struct net_device *netdev = tx_ring->netdev;
0e014cb1 5539 struct e1000_hw *hw = &adapter->hw;
9d5c8243 5540 struct igb_buffer *buffer_info;
0e014cb1 5541 union e1000_adv_tx_desc *tx_desc, *eop_desc;
9d5c8243 5542 unsigned int total_bytes = 0, total_packets = 0;
0e014cb1
AD		 5543 unsigned int i, eop, count = 0;
5544 bool cleaned = false;
9d5c8243 5545
9d5c8243 5546 i = tx_ring->next_to_clean;
0e014cb1
AD		 5547 eop = tx_ring->buffer_info[i].next_to_watch;
5548 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
5549
5550 while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) &&
5551 (count < tx_ring->count)) {
2d0bb1c1 5552 rmb(); /* read buffer_info after eop_desc status */
0e014cb1
AD		 5553 for (cleaned = false; !cleaned; count++) {
5554 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
9d5c8243 5555 buffer_info = &tx_ring->buffer_info[i];
0e014cb1 5556 cleaned = (i == eop);
9d5c8243 5557
2873957d
NN		 5558 if (buffer_info->skb) {
5559 total_bytes += buffer_info->bytecount;
9d5c8243 5560 /* gso_segs is currently only valid for tcp */
2873957d
NN		 5561 total_packets += buffer_info->gso_segs;
5562 igb_tx_hwtstamp(q_vector, buffer_info);
9d5c8243
AK		 5563 }
5564
80785298 5565 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
0e014cb1 5566 tx_desc->wb.status = 0;
9d5c8243
AK		 5567
5568 i++;
5569 if (i == tx_ring->count)
5570 i = 0;
9d5c8243 5571 }
0e014cb1
AD		 5572 eop = tx_ring->buffer_info[i].next_to_watch;
5573 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
5574 }
5575
9d5c8243
AK		 5576 tx_ring->next_to_clean = i;
5577
fc7d345d 5578 if (unlikely(count &&
9d5c8243 5579 netif_carrier_ok(netdev) &&
c493ea45 5580 igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
9d5c8243
AK		 5581 /* Make sure that anybody stopping the queue after this
5582 * sees the new next_to_clean.
5583 */
5584 smp_mb();
661086df
PWJ		 5585 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
5586 !(test_bit(__IGB_DOWN, &adapter->state))) {
5587 netif_wake_subqueue(netdev, tx_ring->queue_index);
12dcd86b
ED		 5588
5589 u64_stats_update_begin(&tx_ring->tx_syncp);
04a5fcaa 5590 tx_ring->tx_stats.restart_queue++;
12dcd86b 5591 u64_stats_update_end(&tx_ring->tx_syncp);
661086df 5592 }
9d5c8243
AK		 5593 }
5594
5595 if (tx_ring->detect_tx_hung) {
5596 /* Detect a transmit hang in hardware, this serializes the
5597 * check with the clearing of time_stamp and movement of i */
5598 tx_ring->detect_tx_hung = false;
5599 if (tx_ring->buffer_info[i].time_stamp &&
5600 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
8e95a202
JP		 5601 (adapter->tx_timeout_factor * HZ)) &&
5602 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
9d5c8243 5603
9d5c8243 5604 /* detected Tx unit hang */
59d71989 5605 dev_err(tx_ring->dev,
9d5c8243 5606 "Detected Tx Unit Hang\n"
2d064c06 5607 " Tx Queue <%d>\n"
9d5c8243
AK		 5608 " TDH <%x>\n"
5609 " TDT <%x>\n"
5610 " next_to_use <%x>\n"
5611 " next_to_clean <%x>\n"
9d5c8243
AK		 5612 "buffer_info[next_to_clean]\n"
5613 " time_stamp <%lx>\n"
0e014cb1 5614 " next_to_watch <%x>\n"
9d5c8243
AK		 5615 " jiffies <%lx>\n"
5616 " desc.status <%x>\n",
2d064c06 5617 tx_ring->queue_index,
fce99e34
AD		 5618 readl(tx_ring->head),
5619 readl(tx_ring->tail),
9d5c8243
AK		 5620 tx_ring->next_to_use,
5621 tx_ring->next_to_clean,
f7ba205e 5622 tx_ring->buffer_info[eop].time_stamp,
0e014cb1 5623 eop,
9d5c8243 5624 jiffies,
0e014cb1 5625 eop_desc->wb.status);
661086df 5626 netif_stop_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 5627 }
5628 }
5629 tx_ring->total_bytes += total_bytes;
5630 tx_ring->total_packets += total_packets;
12dcd86b 5631 u64_stats_update_begin(&tx_ring->tx_syncp);
e21ed353
AD		 5632 tx_ring->tx_stats.bytes += total_bytes;
5633 tx_ring->tx_stats.packets += total_packets;
12dcd86b 5634 u64_stats_update_end(&tx_ring->tx_syncp);
807540ba 5635 return count < tx_ring->count;
9d5c8243
AK		 5636}
5637
9d5c8243
AK		 5638/**
5639 * igb_receive_skb - helper function to handle rx indications
047e0030
AD		 5640 * @q_vector: structure containing interrupt and ring information
5641 * @skb: packet to send up
5642 * @vlan_tag: vlan tag for packet
9d5c8243 5643 **/
047e0030
AD		 5644static void igb_receive_skb(struct igb_q_vector *q_vector,
5645 struct sk_buff *skb,
5646 u16 vlan_tag)
5647{
5648 struct igb_adapter *adapter = q_vector->adapter;
5649
31b24b95 5650 if (vlan_tag && adapter->vlgrp)
047e0030
AD		 5651 vlan_gro_receive(&q_vector->napi, adapter->vlgrp,
5652 vlan_tag, skb);
182ff8df 5653 else
047e0030 5654 napi_gro_receive(&q_vector->napi, skb);
9d5c8243
AK		 5655}
5656
04a5fcaa 5657static inline void igb_rx_checksum_adv(struct igb_ring *ring,
9d5c8243
AK		 5658 u32 status_err, struct sk_buff *skb)
5659{
bc8acf2c 5660 skb_checksum_none_assert(skb);
9d5c8243
AK		 5661
5662 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
85ad76b2
AD		 5663 if (!(ring->flags & IGB_RING_FLAG_RX_CSUM) ||
5664 (status_err & E1000_RXD_STAT_IXSM))
9d5c8243 5665 return;
85ad76b2 5666
9d5c8243
AK		 5667 /* TCP/UDP checksum error bit is set */
5668 if (status_err &
5669 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
b9473560
JB		 5670 /*
5671 * work around errata with sctp packets where the TCPE aka
5672 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
5673 * packets, (aka let the stack check the crc32c)
5674 */
85ad76b2 5675 if ((skb->len == 60) &&
12dcd86b
ED		 5676 (ring->flags & IGB_RING_FLAG_RX_SCTP_CSUM)) {
5677 u64_stats_update_begin(&ring->rx_syncp);
04a5fcaa 5678 ring->rx_stats.csum_err++;
12dcd86b
ED		 5679 u64_stats_update_end(&ring->rx_syncp);
5680 }
9d5c8243 5681 /* let the stack verify checksum errors */
9d5c8243
AK		 5682 return;
5683 }
5684 /* It must be a TCP or UDP packet with a valid checksum */
5685 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
5686 skb->ip_summed = CHECKSUM_UNNECESSARY;
5687
59d71989 5688 dev_dbg(ring->dev, "cksum success: bits %08X\n", status_err);
9d5c8243
AK		 5689}
5690
757b77e2 5691static void igb_rx_hwtstamp(struct igb_q_vector *q_vector, u32 staterr,
c5b9bd5e
AD		 5692 struct sk_buff *skb)
5693{
5694 struct igb_adapter *adapter = q_vector->adapter;
5695 struct e1000_hw *hw = &adapter->hw;
5696 u64 regval;
5697
5698 /*
5699 * If this bit is set, then the RX registers contain the time stamp. No
5700 * other packet will be time stamped until we read these registers, so
5701 * read the registers to make them available again. Because only one
5702 * packet can be time stamped at a time, we know that the register
5703 * values must belong to this one here and therefore we don't need to
5704 * compare any of the additional attributes stored for it.
5705 *
2244d07b 5706 * If nothing went wrong, then it should have a shared tx_flags that we
c5b9bd5e
AD		 5707 * can turn into a skb_shared_hwtstamps.
5708 */
757b77e2
NN		 5709 if (staterr & E1000_RXDADV_STAT_TSIP) {
5710 u32 *stamp = (u32 *)skb->data;
5711 regval = le32_to_cpu(*(stamp + 2));
5712 regval |= (u64)le32_to_cpu(*(stamp + 3)) << 32;
5713 skb_pull(skb, IGB_TS_HDR_LEN);
5714 } else {
5715 if(!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
5716 return;
c5b9bd5e 5717
757b77e2
NN		 5718 regval = rd32(E1000_RXSTMPL);
5719 regval |= (u64)rd32(E1000_RXSTMPH) << 32;
5720 }
c5b9bd5e
AD		 5721
5722 igb_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval);
5723}
4c844851 5724static inline u16 igb_get_hlen(struct igb_ring *rx_ring,
2d94d8ab
AD		 5725 union e1000_adv_rx_desc *rx_desc)
5726{
5727 /* HW will not DMA in data larger than the given buffer, even if it
5728 * parses the (NFS, of course) header to be larger. In that case, it
5729 * fills the header buffer and spills the rest into the page.
5730 */
5731 u16 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
5732 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
4c844851
AD		 5733 if (hlen > rx_ring->rx_buffer_len)
5734 hlen = rx_ring->rx_buffer_len;
2d94d8ab
AD		 5735 return hlen;
5736}
5737
047e0030
AD		 5738static bool igb_clean_rx_irq_adv(struct igb_q_vector *q_vector,
5739 int *work_done, int budget)
9d5c8243 5740{
047e0030 5741 struct igb_ring *rx_ring = q_vector->rx_ring;
e694e964 5742 struct net_device *netdev = rx_ring->netdev;
59d71989 5743 struct device *dev = rx_ring->dev;
9d5c8243
AK		 5744 union e1000_adv_rx_desc *rx_desc , *next_rxd;
5745 struct igb_buffer *buffer_info , *next_buffer;
5746 struct sk_buff *skb;
9d5c8243
AK		 5747 bool cleaned = false;
5748 int cleaned_count = 0;
d1eff350 5749 int current_node = numa_node_id();
9d5c8243 5750 unsigned int total_bytes = 0, total_packets = 0;
73cd78f1 5751 unsigned int i;
2d94d8ab
AD		 5752 u32 staterr;
5753 u16 length;
047e0030 5754 u16 vlan_tag;
9d5c8243
AK		 5755
5756 i = rx_ring->next_to_clean;
69d3ca53 5757 buffer_info = &rx_ring->buffer_info[i];
9d5c8243
AK		 5758 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
5759 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
5760
5761 while (staterr & E1000_RXD_STAT_DD) {
5762 if (*work_done >= budget)
5763 break;
5764 (*work_done)++;
2d0bb1c1 5765 rmb(); /* read descriptor and rx_buffer_info after status DD */
9d5c8243 5766
69d3ca53
AD		 5767 skb = buffer_info->skb;
5768 prefetch(skb->data - NET_IP_ALIGN);
5769 buffer_info->skb = NULL;
5770
5771 i++;
5772 if (i == rx_ring->count)
5773 i = 0;
42d0781a 5774
69d3ca53
AD		 5775 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
5776 prefetch(next_rxd);
5777 next_buffer = &rx_ring->buffer_info[i];
9d5c8243
AK		 5778
5779 length = le16_to_cpu(rx_desc->wb.upper.length);
5780 cleaned = true;
5781 cleaned_count++;
5782
2d94d8ab 5783 if (buffer_info->dma) {
59d71989 5784 dma_unmap_single(dev, buffer_info->dma,
4c844851 5785 rx_ring->rx_buffer_len,
59d71989 5786 DMA_FROM_DEVICE);
91615f76 5787 buffer_info->dma = 0;
4c844851 5788 if (rx_ring->rx_buffer_len >= IGB_RXBUFFER_1024) {
6ec43fe6
AD		 5789 skb_put(skb, length);
5790 goto send_up;
5791 }
4c844851 5792 skb_put(skb, igb_get_hlen(rx_ring, rx_desc));
bf36c1a0
AD		 5793 }
5794
5795 if (length) {
59d71989
AD		 5796 dma_unmap_page(dev, buffer_info->page_dma,
5797 PAGE_SIZE / 2, DMA_FROM_DEVICE);
9d5c8243 5798 buffer_info->page_dma = 0;
bf36c1a0 5799
aa913403 5800 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
bf36c1a0
AD		 5801 buffer_info->page,
5802 buffer_info->page_offset,
5803 length);
5804
d1eff350
AD		 5805 if ((page_count(buffer_info->page) != 1) ||
5806 (page_to_nid(buffer_info->page) != current_node))
bf36c1a0
AD		 5807 buffer_info->page = NULL;
5808 else
5809 get_page(buffer_info->page);
9d5c8243
AK		 5810
5811 skb->len += length;
5812 skb->data_len += length;
bf36c1a0 5813 skb->truesize += length;
9d5c8243 5814 }
9d5c8243 5815
bf36c1a0 5816 if (!(staterr & E1000_RXD_STAT_EOP)) {
b2d56536
AD		 5817 buffer_info->skb = next_buffer->skb;
5818 buffer_info->dma = next_buffer->dma;
5819 next_buffer->skb = skb;
5820 next_buffer->dma = 0;
bf36c1a0
AD		 5821 goto next_desc;
5822 }
69d3ca53 5823send_up:
9d5c8243
AK		 5824 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
5825 dev_kfree_skb_irq(skb);
5826 goto next_desc;
5827 }
9d5c8243 5828
757b77e2
NN		 5829 if (staterr & (E1000_RXDADV_STAT_TSIP | E1000_RXDADV_STAT_TS))
5830 igb_rx_hwtstamp(q_vector, staterr, skb);
9d5c8243
AK		 5831 total_bytes += skb->len;
5832 total_packets++;
5833
85ad76b2 5834 igb_rx_checksum_adv(rx_ring, staterr, skb);
9d5c8243
AK		 5835
5836 skb->protocol = eth_type_trans(skb, netdev);
047e0030
AD		 5837 skb_record_rx_queue(skb, rx_ring->queue_index);
5838
5839 vlan_tag = ((staterr & E1000_RXD_STAT_VP) ?
5840 le16_to_cpu(rx_desc->wb.upper.vlan) : 0);
9d5c8243 5841
047e0030 5842 igb_receive_skb(q_vector, skb, vlan_tag);
9d5c8243 5843
9d5c8243
AK		 5844next_desc:
5845 rx_desc->wb.upper.status_error = 0;
5846
5847 /* return some buffers to hardware, one at a time is too slow */
5848 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
3b644cf6 5849 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 5850 cleaned_count = 0;
5851 }
5852
5853 /* use prefetched values */
5854 rx_desc = next_rxd;
5855 buffer_info = next_buffer;
9d5c8243
AK		 5856 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
5857 }
bf36c1a0 5858
9d5c8243 5859 rx_ring->next_to_clean = i;
c493ea45 5860 cleaned_count = igb_desc_unused(rx_ring);
9d5c8243
AK		 5861
5862 if (cleaned_count)
3b644cf6 5863 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 5864
5865 rx_ring->total_packets += total_packets;
5866 rx_ring->total_bytes += total_bytes;
12dcd86b 5867 u64_stats_update_begin(&rx_ring->rx_syncp);
9d5c8243
AK		 5868 rx_ring->rx_stats.packets += total_packets;
5869 rx_ring->rx_stats.bytes += total_bytes;
12dcd86b 5870 u64_stats_update_end(&rx_ring->rx_syncp);
9d5c8243
AK		 5871 return cleaned;
5872}
5873
9d5c8243
AK		 5874/**
5875 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
5876 * @adapter: address of board private structure
5877 **/
d7ee5b3a 5878void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring, int cleaned_count)
9d5c8243 5879{
e694e964 5880 struct net_device *netdev = rx_ring->netdev;
9d5c8243
AK		 5881 union e1000_adv_rx_desc *rx_desc;
5882 struct igb_buffer *buffer_info;
5883 struct sk_buff *skb;
5884 unsigned int i;
db761762 5885 int bufsz;
9d5c8243
AK		 5886
5887 i = rx_ring->next_to_use;
5888 buffer_info = &rx_ring->buffer_info[i];
5889
4c844851 5890 bufsz = rx_ring->rx_buffer_len;
db761762 5891
9d5c8243
AK		 5892 while (cleaned_count--) {
5893 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
5894
6ec43fe6 5895 if ((bufsz < IGB_RXBUFFER_1024) && !buffer_info->page_dma) {
9d5c8243 5896 if (!buffer_info->page) {
42d0781a 5897 buffer_info->page = netdev_alloc_page(netdev);
12dcd86b
ED		 5898 if (unlikely(!buffer_info->page)) {
5899 u64_stats_update_begin(&rx_ring->rx_syncp);
04a5fcaa 5900 rx_ring->rx_stats.alloc_failed++;
12dcd86b 5901 u64_stats_update_end(&rx_ring->rx_syncp);
bf36c1a0
AD		 5902 goto no_buffers;
5903 }
5904 buffer_info->page_offset = 0;
5905 } else {
5906 buffer_info->page_offset ^= PAGE_SIZE / 2;
9d5c8243
AK		 5907 }
5908 buffer_info->page_dma =
59d71989 5909 dma_map_page(rx_ring->dev, buffer_info->page,
bf36c1a0
AD		 5910 buffer_info->page_offset,
5911 PAGE_SIZE / 2,
59d71989
AD		 5912 DMA_FROM_DEVICE);
5913 if (dma_mapping_error(rx_ring->dev,
5914 buffer_info->page_dma)) {
42d0781a 5915 buffer_info->page_dma = 0;
12dcd86b 5916 u64_stats_update_begin(&rx_ring->rx_syncp);
42d0781a 5917 rx_ring->rx_stats.alloc_failed++;
12dcd86b 5918 u64_stats_update_end(&rx_ring->rx_syncp);
42d0781a
AD		 5919 goto no_buffers;
5920 }
9d5c8243
AK		 5921 }
5922
42d0781a
AD		 5923 skb = buffer_info->skb;
5924 if (!skb) {
89d71a66 5925 skb = netdev_alloc_skb_ip_align(netdev, bufsz);
12dcd86b
ED		 5926 if (unlikely(!skb)) {
5927 u64_stats_update_begin(&rx_ring->rx_syncp);
04a5fcaa 5928 rx_ring->rx_stats.alloc_failed++;
12dcd86b 5929 u64_stats_update_end(&rx_ring->rx_syncp);
9d5c8243
AK		 5930 goto no_buffers;
5931 }
5932
9d5c8243 5933 buffer_info->skb = skb;
42d0781a
AD		 5934 }
5935 if (!buffer_info->dma) {
59d71989 5936 buffer_info->dma = dma_map_single(rx_ring->dev,
80785298 5937 skb->data,
9d5c8243 5938 bufsz,
59d71989
AD		 5939 DMA_FROM_DEVICE);
5940 if (dma_mapping_error(rx_ring->dev,
5941 buffer_info->dma)) {
42d0781a 5942 buffer_info->dma = 0;
12dcd86b 5943 u64_stats_update_begin(&rx_ring->rx_syncp);
42d0781a 5944 rx_ring->rx_stats.alloc_failed++;
12dcd86b 5945 u64_stats_update_end(&rx_ring->rx_syncp);
42d0781a
AD		 5946 goto no_buffers;
5947 }
9d5c8243
AK		 5948 }
5949 /* Refresh the desc even if buffer_addrs didn't change because
5950 * each write-back erases this info. */
6ec43fe6 5951 if (bufsz < IGB_RXBUFFER_1024) {
9d5c8243
AK		 5952 rx_desc->read.pkt_addr =
5953 cpu_to_le64(buffer_info->page_dma);
5954 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
5955 } else {
42d0781a 5956 rx_desc->read.pkt_addr = cpu_to_le64(buffer_info->dma);
9d5c8243
AK		 5957 rx_desc->read.hdr_addr = 0;
5958 }
5959
5960 i++;
5961 if (i == rx_ring->count)
5962 i = 0;
5963 buffer_info = &rx_ring->buffer_info[i];
5964 }
5965
5966no_buffers:
5967 if (rx_ring->next_to_use != i) {
5968 rx_ring->next_to_use = i;
5969 if (i == 0)
5970 i = (rx_ring->count - 1);
5971 else
5972 i--;
5973
5974 /* Force memory writes to complete before letting h/w
5975 * know there are new descriptors to fetch. (Only
5976 * applicable for weak-ordered memory model archs,
5977 * such as IA-64). */
5978 wmb();
fce99e34 5979 writel(i, rx_ring->tail);
9d5c8243
AK		 5980 }
5981}
5982
5983/**
5984 * igb_mii_ioctl -
5985 * @netdev:
5986 * @ifreq:
5987 * @cmd:
5988 **/
5989static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5990{
5991 struct igb_adapter *adapter = netdev_priv(netdev);
5992 struct mii_ioctl_data *data = if_mii(ifr);
5993
5994 if (adapter->hw.phy.media_type != e1000_media_type_copper)
5995 return -EOPNOTSUPP;
5996
5997 switch (cmd) {
5998 case SIOCGMIIPHY:
5999 data->phy_id = adapter->hw.phy.addr;
6000 break;
6001 case SIOCGMIIREG:
f5f4cf08
AD		 6002 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
6003 &data->val_out))
9d5c8243
AK		 6004 return -EIO;
6005 break;
6006 case SIOCSMIIREG:
6007 default:
6008 return -EOPNOTSUPP;
6009 }
6010 return 0;
6011}
6012
c6cb090b
PO		 6013/**
6014 * igb_hwtstamp_ioctl - control hardware time stamping
6015 * @netdev:
6016 * @ifreq:
6017 * @cmd:
6018 *
33af6bcc
PO		 6019 * Outgoing time stamping can be enabled and disabled. Play nice and
6020 * disable it when requested, although it shouldn't case any overhead
6021 * when no packet needs it. At most one packet in the queue may be
6022 * marked for time stamping, otherwise it would be impossible to tell
6023 * for sure to which packet the hardware time stamp belongs.
6024 *
6025 * Incoming time stamping has to be configured via the hardware
6026 * filters. Not all combinations are supported, in particular event
6027 * type has to be specified. Matching the kind of event packet is
6028 * not supported, with the exception of "all V2 events regardless of
6029 * level 2 or 4".
6030 *
c6cb090b
PO		 6031 **/
6032static int igb_hwtstamp_ioctl(struct net_device *netdev,
6033 struct ifreq *ifr, int cmd)
6034{
33af6bcc
PO		 6035 struct igb_adapter *adapter = netdev_priv(netdev);
6036 struct e1000_hw *hw = &adapter->hw;
c6cb090b 6037 struct hwtstamp_config config;
c5b9bd5e
AD		 6038 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
6039 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
33af6bcc 6040 u32 tsync_rx_cfg = 0;
c5b9bd5e
AD		 6041 bool is_l4 = false;
6042 bool is_l2 = false;
33af6bcc 6043 u32 regval;
c6cb090b
PO		 6044
6045 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
6046 return -EFAULT;
6047
6048 /* reserved for future extensions */
6049 if (config.flags)
6050 return -EINVAL;
6051
33af6bcc
PO		 6052 switch (config.tx_type) {
6053 case HWTSTAMP_TX_OFF:
c5b9bd5e 6054 tsync_tx_ctl = 0;
33af6bcc 6055 case HWTSTAMP_TX_ON:
33af6bcc
PO		 6056 break;
6057 default:
6058 return -ERANGE;
6059 }
6060
6061 switch (config.rx_filter) {
6062 case HWTSTAMP_FILTER_NONE:
c5b9bd5e 6063 tsync_rx_ctl = 0;
33af6bcc
PO		 6064 break;
6065 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
6066 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
6067 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
6068 case HWTSTAMP_FILTER_ALL:
6069 /*
6070 * register TSYNCRXCFG must be set, therefore it is not
6071 * possible to time stamp both Sync and Delay_Req messages
6072 * => fall back to time stamping all packets
6073 */
c5b9bd5e 6074 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
33af6bcc
PO		 6075 config.rx_filter = HWTSTAMP_FILTER_ALL;
6076 break;
6077 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
c5b9bd5e 6078 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
33af6bcc 6079 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
c5b9bd5e 6080 is_l4 = true;
33af6bcc
PO		 6081 break;
6082 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
c5b9bd5e 6083 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
33af6bcc 6084 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
c5b9bd5e 6085 is_l4 = true;
33af6bcc
PO		 6086 break;
6087 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
6088 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
c5b9bd5e 6089 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
33af6bcc 6090 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE;
c5b9bd5e
AD		 6091 is_l2 = true;
6092 is_l4 = true;
33af6bcc
PO		 6093 config.rx_filter = HWTSTAMP_FILTER_SOME;
6094 break;
6095 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
6096 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
c5b9bd5e 6097 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
33af6bcc 6098 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE;
c5b9bd5e
AD		 6099 is_l2 = true;
6100 is_l4 = true;
33af6bcc
PO		 6101 config.rx_filter = HWTSTAMP_FILTER_SOME;
6102 break;
6103 case HWTSTAMP_FILTER_PTP_V2_EVENT:
6104 case HWTSTAMP_FILTER_PTP_V2_SYNC:
6105 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
c5b9bd5e 6106 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
33af6bcc 6107 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
c5b9bd5e 6108 is_l2 = true;
33af6bcc
PO		 6109 break;
6110 default:
6111 return -ERANGE;
6112 }
6113
c5b9bd5e
AD		 6114 if (hw->mac.type == e1000_82575) {
6115 if (tsync_rx_ctl | tsync_tx_ctl)
6116 return -EINVAL;
6117 return 0;
6118 }
6119
757b77e2
NN		 6120 /*
6121 * Per-packet timestamping only works if all packets are
6122 * timestamped, so enable timestamping in all packets as
6123 * long as one rx filter was configured.
6124 */
6125 if ((hw->mac.type == e1000_82580) && tsync_rx_ctl) {
6126 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
6127 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
6128 }
6129
33af6bcc
PO		 6130 /* enable/disable TX */
6131 regval = rd32(E1000_TSYNCTXCTL);
c5b9bd5e
AD		 6132 regval &= ~E1000_TSYNCTXCTL_ENABLED;
6133 regval |= tsync_tx_ctl;
33af6bcc
PO		 6134 wr32(E1000_TSYNCTXCTL, regval);
6135
c5b9bd5e 6136 /* enable/disable RX */
33af6bcc 6137 regval = rd32(E1000_TSYNCRXCTL);
c5b9bd5e
AD		 6138 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
6139 regval |= tsync_rx_ctl;
33af6bcc 6140 wr32(E1000_TSYNCRXCTL, regval);
33af6bcc 6141
c5b9bd5e
AD		 6142 /* define which PTP packets are time stamped */
6143 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
33af6bcc 6144
c5b9bd5e
AD		 6145 /* define ethertype filter for timestamped packets */
6146 if (is_l2)
6147 wr32(E1000_ETQF(3),
6148 (E1000_ETQF_FILTER_ENABLE | /* enable filter */
6149 E1000_ETQF_1588 | /* enable timestamping */
6150 ETH_P_1588)); /* 1588 eth protocol type */
6151 else
6152 wr32(E1000_ETQF(3), 0);
6153
6154#define PTP_PORT 319
6155 /* L4 Queue Filter[3]: filter by destination port and protocol */
6156 if (is_l4) {
6157 u32 ftqf = (IPPROTO_UDP /* UDP */
6158 | E1000_FTQF_VF_BP /* VF not compared */
6159 | E1000_FTQF_1588_TIME_STAMP /* Enable Timestamping */
6160 | E1000_FTQF_MASK); /* mask all inputs */
6161 ftqf &= ~E1000_FTQF_MASK_PROTO_BP; /* enable protocol check */
6162
6163 wr32(E1000_IMIR(3), htons(PTP_PORT));
6164 wr32(E1000_IMIREXT(3),
6165 (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP));
6166 if (hw->mac.type == e1000_82576) {
6167 /* enable source port check */
6168 wr32(E1000_SPQF(3), htons(PTP_PORT));
6169 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
6170 }
6171 wr32(E1000_FTQF(3), ftqf);
6172 } else {
6173 wr32(E1000_FTQF(3), E1000_FTQF_MASK);
6174 }
33af6bcc
PO		 6175 wrfl();
6176
6177 adapter->hwtstamp_config = config;
6178
6179 /* clear TX/RX time stamp registers, just to be sure */
6180 regval = rd32(E1000_TXSTMPH);
6181 regval = rd32(E1000_RXSTMPH);
c6cb090b 6182
33af6bcc
PO		 6183 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
6184 -EFAULT : 0;
c6cb090b
PO		 6185}
6186
9d5c8243
AK		 6187/**
6188 * igb_ioctl -
6189 * @netdev:
6190 * @ifreq:
6191 * @cmd:
6192 **/
6193static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6194{
6195 switch (cmd) {
6196 case SIOCGMIIPHY:
6197 case SIOCGMIIREG:
6198 case SIOCSMIIREG:
6199 return igb_mii_ioctl(netdev, ifr, cmd);
c6cb090b
PO		 6200 case SIOCSHWTSTAMP:
6201 return igb_hwtstamp_ioctl(netdev, ifr, cmd);
9d5c8243
AK		 6202 default:
6203 return -EOPNOTSUPP;
6204 }
6205}
6206
009bc06e
AD		 6207s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6208{
6209 struct igb_adapter *adapter = hw->back;
6210 u16 cap_offset;
6211
6212 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
6213 if (!cap_offset)
6214 return -E1000_ERR_CONFIG;
6215
6216 pci_read_config_word(adapter->pdev, cap_offset + reg, value);
6217
6218 return 0;
6219}
6220
6221s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6222{
6223 struct igb_adapter *adapter = hw->back;
6224 u16 cap_offset;
6225
6226 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
6227 if (!cap_offset)
6228 return -E1000_ERR_CONFIG;
6229
6230 pci_write_config_word(adapter->pdev, cap_offset + reg, *value);
6231
6232 return 0;
6233}
6234
9d5c8243
AK		 6235static void igb_vlan_rx_register(struct net_device *netdev,
6236 struct vlan_group *grp)
6237{
6238 struct igb_adapter *adapter = netdev_priv(netdev);
6239 struct e1000_hw *hw = &adapter->hw;
6240 u32 ctrl, rctl;
6241
6242 igb_irq_disable(adapter);
6243 adapter->vlgrp = grp;
6244
6245 if (grp) {
6246 /* enable VLAN tag insert/strip */
6247 ctrl = rd32(E1000_CTRL);
6248 ctrl |= E1000_CTRL_VME;
6249 wr32(E1000_CTRL, ctrl);
6250
51466239 6251 /* Disable CFI check */
9d5c8243 6252 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 6253 rctl &= ~E1000_RCTL_CFIEN;
6254 wr32(E1000_RCTL, rctl);
9d5c8243
AK		 6255 } else {
6256 /* disable VLAN tag insert/strip */
6257 ctrl = rd32(E1000_CTRL);
6258 ctrl &= ~E1000_CTRL_VME;
6259 wr32(E1000_CTRL, ctrl);
9d5c8243
AK		 6260 }
6261
e1739522
AD		 6262 igb_rlpml_set(adapter);
6263
9d5c8243
AK		 6264 if (!test_bit(__IGB_DOWN, &adapter->state))
6265 igb_irq_enable(adapter);
6266}
6267
6268static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
6269{
6270 struct igb_adapter *adapter = netdev_priv(netdev);
6271 struct e1000_hw *hw = &adapter->hw;
4ae196df 6272 int pf_id = adapter->vfs_allocated_count;
9d5c8243 6273
51466239
AD		 6274 /* attempt to add filter to vlvf array */
6275 igb_vlvf_set(adapter, vid, true, pf_id);
4ae196df 6276
51466239
AD		 6277 /* add the filter since PF can receive vlans w/o entry in vlvf */
6278 igb_vfta_set(hw, vid, true);
9d5c8243
AK		 6279}
6280
6281static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
6282{
6283 struct igb_adapter *adapter = netdev_priv(netdev);
6284 struct e1000_hw *hw = &adapter->hw;
4ae196df 6285 int pf_id = adapter->vfs_allocated_count;
51466239 6286 s32 err;
9d5c8243
AK		 6287
6288 igb_irq_disable(adapter);
6289 vlan_group_set_device(adapter->vlgrp, vid, NULL);
6290
6291 if (!test_bit(__IGB_DOWN, &adapter->state))
6292 igb_irq_enable(adapter);
6293
51466239
AD		 6294 /* remove vlan from VLVF table array */
6295 err = igb_vlvf_set(adapter, vid, false, pf_id);
9d5c8243 6296
51466239
AD		 6297 /* if vid was not present in VLVF just remove it from table */
6298 if (err)
4ae196df 6299 igb_vfta_set(hw, vid, false);
9d5c8243
AK		 6300}
6301
6302static void igb_restore_vlan(struct igb_adapter *adapter)
6303{
6304 igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
6305
6306 if (adapter->vlgrp) {
6307 u16 vid;
b738127d 6308 for (vid = 0; vid < VLAN_N_VID; vid++) {
9d5c8243
AK		 6309 if (!vlan_group_get_device(adapter->vlgrp, vid))
6310 continue;
6311 igb_vlan_rx_add_vid(adapter->netdev, vid);
6312 }
6313 }
6314}
6315
6316int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
6317{
090b1795 6318 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 6319 struct e1000_mac_info *mac = &adapter->hw.mac;
6320
6321 mac->autoneg = 0;
6322
cd2638a8
CW		 6323 /* Fiber NIC's only allow 1000 Gbps Full duplex */
6324 if ((adapter->hw.phy.media_type == e1000_media_type_internal_serdes) &&
6325 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
6326 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
6327 return -EINVAL;
6328 }
6329
9d5c8243
AK		 6330 switch (spddplx) {
6331 case SPEED_10 + DUPLEX_HALF:
6332 mac->forced_speed_duplex = ADVERTISE_10_HALF;
6333 break;
6334 case SPEED_10 + DUPLEX_FULL:
6335 mac->forced_speed_duplex = ADVERTISE_10_FULL;
6336 break;
6337 case SPEED_100 + DUPLEX_HALF:
6338 mac->forced_speed_duplex = ADVERTISE_100_HALF;
6339 break;
6340 case SPEED_100 + DUPLEX_FULL:
6341 mac->forced_speed_duplex = ADVERTISE_100_FULL;
6342 break;
6343 case SPEED_1000 + DUPLEX_FULL:
6344 mac->autoneg = 1;
6345 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
6346 break;
6347 case SPEED_1000 + DUPLEX_HALF: /* not supported */
6348 default:
090b1795 6349 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
9d5c8243
AK		 6350 return -EINVAL;
6351 }
6352 return 0;
6353}
6354
3fe7c4c9 6355static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake)
9d5c8243
AK		 6356{
6357 struct net_device *netdev = pci_get_drvdata(pdev);
6358 struct igb_adapter *adapter = netdev_priv(netdev);
6359 struct e1000_hw *hw = &adapter->hw;
2d064c06 6360 u32 ctrl, rctl, status;
9d5c8243
AK		 6361 u32 wufc = adapter->wol;
6362#ifdef CONFIG_PM
6363 int retval = 0;
6364#endif
6365
6366 netif_device_detach(netdev);
6367
a88f10ec
AD		 6368 if (netif_running(netdev))
6369 igb_close(netdev);
6370
047e0030 6371 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 6372
6373#ifdef CONFIG_PM
6374 retval = pci_save_state(pdev);
6375 if (retval)
6376 return retval;
6377#endif
6378
6379 status = rd32(E1000_STATUS);
6380 if (status & E1000_STATUS_LU)
6381 wufc &= ~E1000_WUFC_LNKC;
6382
6383 if (wufc) {
6384 igb_setup_rctl(adapter);
ff41f8dc 6385 igb_set_rx_mode(netdev);
9d5c8243
AK		 6386
6387 /* turn on all-multi mode if wake on multicast is enabled */
6388 if (wufc & E1000_WUFC_MC) {
6389 rctl = rd32(E1000_RCTL);
6390 rctl |= E1000_RCTL_MPE;
6391 wr32(E1000_RCTL, rctl);
6392 }
6393
6394 ctrl = rd32(E1000_CTRL);
6395 /* advertise wake from D3Cold */
6396 #define E1000_CTRL_ADVD3WUC 0x00100000
6397 /* phy power management enable */
6398 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
6399 ctrl |= E1000_CTRL_ADVD3WUC;
6400 wr32(E1000_CTRL, ctrl);
6401
9d5c8243 6402 /* Allow time for pending master requests to run */
330a6d6a 6403 igb_disable_pcie_master(hw);
9d5c8243
AK		 6404
6405 wr32(E1000_WUC, E1000_WUC_PME_EN);
6406 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 6407 } else {
6408 wr32(E1000_WUC, 0);
6409 wr32(E1000_WUFC, 0);
9d5c8243
AK		 6410 }
6411
3fe7c4c9
RW		 6412 *enable_wake = wufc || adapter->en_mng_pt;
6413 if (!*enable_wake)
88a268c1
NN		 6414 igb_power_down_link(adapter);
6415 else
6416 igb_power_up_link(adapter);
9d5c8243
AK		 6417
6418 /* Release control of h/w to f/w. If f/w is AMT enabled, this
6419 * would have already happened in close and is redundant. */
6420 igb_release_hw_control(adapter);
6421
6422 pci_disable_device(pdev);
6423
9d5c8243
AK		 6424 return 0;
6425}
6426
6427#ifdef CONFIG_PM
3fe7c4c9
RW		 6428static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
6429{
6430 int retval;
6431 bool wake;
6432
6433 retval = __igb_shutdown(pdev, &wake);
6434 if (retval)
6435 return retval;
6436
6437 if (wake) {
6438 pci_prepare_to_sleep(pdev);
6439 } else {
6440 pci_wake_from_d3(pdev, false);
6441 pci_set_power_state(pdev, PCI_D3hot);
6442 }
6443
6444 return 0;
6445}
6446
9d5c8243
AK		 6447static int igb_resume(struct pci_dev *pdev)
6448{
6449 struct net_device *netdev = pci_get_drvdata(pdev);
6450 struct igb_adapter *adapter = netdev_priv(netdev);
6451 struct e1000_hw *hw = &adapter->hw;
6452 u32 err;
6453
6454 pci_set_power_state(pdev, PCI_D0);
6455 pci_restore_state(pdev);
b94f2d77 6456 pci_save_state(pdev);
42bfd33a 6457
aed5dec3 6458 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 6459 if (err) {
6460 dev_err(&pdev->dev,
6461 "igb: Cannot enable PCI device from suspend\n");
6462 return err;
6463 }
6464 pci_set_master(pdev);
6465
6466 pci_enable_wake(pdev, PCI_D3hot, 0);
6467 pci_enable_wake(pdev, PCI_D3cold, 0);
6468
047e0030 6469 if (igb_init_interrupt_scheme(adapter)) {
a88f10ec
AD		 6470 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
6471 return -ENOMEM;
9d5c8243
AK		 6472 }
6473
9d5c8243 6474 igb_reset(adapter);
a8564f03
AD		 6475
6476 /* let the f/w know that the h/w is now under the control of the
6477 * driver. */
6478 igb_get_hw_control(adapter);
6479
9d5c8243
AK		 6480 wr32(E1000_WUS, ~0);
6481
a88f10ec
AD		 6482 if (netif_running(netdev)) {
6483 err = igb_open(netdev);
6484 if (err)
6485 return err;
6486 }
9d5c8243
AK		 6487
6488 netif_device_attach(netdev);
6489
9d5c8243
AK		 6490 return 0;
6491}
6492#endif
6493
6494static void igb_shutdown(struct pci_dev *pdev)
6495{
3fe7c4c9
RW		 6496 bool wake;
6497
6498 __igb_shutdown(pdev, &wake);
6499
6500 if (system_state == SYSTEM_POWER_OFF) {
6501 pci_wake_from_d3(pdev, wake);
6502 pci_set_power_state(pdev, PCI_D3hot);
6503 }
9d5c8243
AK		 6504}
6505
6506#ifdef CONFIG_NET_POLL_CONTROLLER
6507/*
6508 * Polling 'interrupt' - used by things like netconsole to send skbs
6509 * without having to re-enable interrupts. It's not called while
6510 * the interrupt routine is executing.
6511 */
6512static void igb_netpoll(struct net_device *netdev)
6513{
6514 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 6515 struct e1000_hw *hw = &adapter->hw;
9d5c8243 6516 int i;
9d5c8243 6517
eebbbdba 6518 if (!adapter->msix_entries) {
047e0030 6519 struct igb_q_vector *q_vector = adapter->q_vector[0];
eebbbdba 6520 igb_irq_disable(adapter);
047e0030 6521 napi_schedule(&q_vector->napi);
eebbbdba
AD		 6522 return;
6523 }
9d5c8243 6524
047e0030
AD		 6525 for (i = 0; i < adapter->num_q_vectors; i++) {
6526 struct igb_q_vector *q_vector = adapter->q_vector[i];
6527 wr32(E1000_EIMC, q_vector->eims_value);
6528 napi_schedule(&q_vector->napi);
eebbbdba 6529 }
9d5c8243
AK		 6530}
6531#endif /* CONFIG_NET_POLL_CONTROLLER */
6532
6533/**
6534 * igb_io_error_detected - called when PCI error is detected
6535 * @pdev: Pointer to PCI device
6536 * @state: The current pci connection state
6537 *
6538 * This function is called after a PCI bus error affecting
6539 * this device has been detected.
6540 */
6541static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
6542 pci_channel_state_t state)
6543{
6544 struct net_device *netdev = pci_get_drvdata(pdev);
6545 struct igb_adapter *adapter = netdev_priv(netdev);
6546
6547 netif_device_detach(netdev);
6548
59ed6eec
AD		 6549 if (state == pci_channel_io_perm_failure)
6550 return PCI_ERS_RESULT_DISCONNECT;
6551
9d5c8243
AK		 6552 if (netif_running(netdev))
6553 igb_down(adapter);
6554 pci_disable_device(pdev);
6555
6556 /* Request a slot slot reset. */
6557 return PCI_ERS_RESULT_NEED_RESET;
6558}
6559
6560/**
6561 * igb_io_slot_reset - called after the pci bus has been reset.
6562 * @pdev: Pointer to PCI device
6563 *
6564 * Restart the card from scratch, as if from a cold-boot. Implementation
6565 * resembles the first-half of the igb_resume routine.
6566 */
6567static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
6568{
6569 struct net_device *netdev = pci_get_drvdata(pdev);
6570 struct igb_adapter *adapter = netdev_priv(netdev);
6571 struct e1000_hw *hw = &adapter->hw;
40a914fa 6572 pci_ers_result_t result;
42bfd33a 6573 int err;
9d5c8243 6574
aed5dec3 6575 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 6576 dev_err(&pdev->dev,
6577 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 6578 result = PCI_ERS_RESULT_DISCONNECT;
6579 } else {
6580 pci_set_master(pdev);
6581 pci_restore_state(pdev);
b94f2d77 6582 pci_save_state(pdev);
9d5c8243 6583
40a914fa
AD		 6584 pci_enable_wake(pdev, PCI_D3hot, 0);
6585 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 6586
40a914fa
AD		 6587 igb_reset(adapter);
6588 wr32(E1000_WUS, ~0);
6589 result = PCI_ERS_RESULT_RECOVERED;
6590 }
9d5c8243 6591
ea943d41
JK		 6592 err = pci_cleanup_aer_uncorrect_error_status(pdev);
6593 if (err) {
6594 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
6595 "failed 0x%0x\n", err);
6596 /* non-fatal, continue */
6597 }
40a914fa
AD		 6598
6599 return result;
9d5c8243
AK		 6600}
6601
6602/**
6603 * igb_io_resume - called when traffic can start flowing again.
6604 * @pdev: Pointer to PCI device
6605 *
6606 * This callback is called when the error recovery driver tells us that
6607 * its OK to resume normal operation. Implementation resembles the
6608 * second-half of the igb_resume routine.
6609 */
6610static void igb_io_resume(struct pci_dev *pdev)
6611{
6612 struct net_device *netdev = pci_get_drvdata(pdev);
6613 struct igb_adapter *adapter = netdev_priv(netdev);
6614
9d5c8243
AK		 6615 if (netif_running(netdev)) {
6616 if (igb_up(adapter)) {
6617 dev_err(&pdev->dev, "igb_up failed after reset\n");
6618 return;
6619 }
6620 }
6621
6622 netif_device_attach(netdev);
6623
6624 /* let the f/w know that the h/w is now under the control of the
6625 * driver. */
6626 igb_get_hw_control(adapter);
9d5c8243
AK		 6627}
6628
26ad9178
AD		 6629static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
6630 u8 qsel)
6631{
6632 u32 rar_low, rar_high;
6633 struct e1000_hw *hw = &adapter->hw;
6634
6635 /* HW expects these in little endian so we reverse the byte order
6636 * from network order (big endian) to little endian
6637 */
6638 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
6639 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
6640 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
6641
6642 /* Indicate to hardware the Address is Valid. */
6643 rar_high |= E1000_RAH_AV;
6644
6645 if (hw->mac.type == e1000_82575)
6646 rar_high |= E1000_RAH_POOL_1 * qsel;
6647 else
6648 rar_high |= E1000_RAH_POOL_1 << qsel;
6649
6650 wr32(E1000_RAL(index), rar_low);
6651 wrfl();
6652 wr32(E1000_RAH(index), rar_high);
6653 wrfl();
6654}
6655
4ae196df
AD		 6656static int igb_set_vf_mac(struct igb_adapter *adapter,
6657 int vf, unsigned char *mac_addr)
6658{
6659 struct e1000_hw *hw = &adapter->hw;
ff41f8dc
AD		 6660 /* VF MAC addresses start at end of receive addresses and moves
6661 * torwards the first, as a result a collision should not be possible */
6662 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 6663
37680117 6664 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 6665
26ad9178 6666 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
4ae196df
AD		 6667
6668 return 0;
6669}
6670
8151d294
WM		 6671static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
6672{
6673 struct igb_adapter *adapter = netdev_priv(netdev);
6674 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
6675 return -EINVAL;
6676 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
6677 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
6678 dev_info(&adapter->pdev->dev, "Reload the VF driver to make this"
6679 " change effective.");
6680 if (test_bit(__IGB_DOWN, &adapter->state)) {
6681 dev_warn(&adapter->pdev->dev, "The VF MAC address has been set,"
6682 " but the PF device is not up.\n");
6683 dev_warn(&adapter->pdev->dev, "Bring the PF device up before"
6684 " attempting to use the VF device.\n");
6685 }
6686 return igb_set_vf_mac(adapter, vf, mac);
6687}
6688
17dc566c
LL		 6689static int igb_link_mbps(int internal_link_speed)
6690{
6691 switch (internal_link_speed) {
6692 case SPEED_100:
6693 return 100;
6694 case SPEED_1000:
6695 return 1000;
6696 default:
6697 return 0;
6698 }
6699}
6700
6701static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
6702 int link_speed)
6703{
6704 int rf_dec, rf_int;
6705 u32 bcnrc_val;
6706
6707 if (tx_rate != 0) {
6708 /* Calculate the rate factor values to set */
6709 rf_int = link_speed / tx_rate;
6710 rf_dec = (link_speed - (rf_int * tx_rate));
6711 rf_dec = (rf_dec * (1<<E1000_RTTBCNRC_RF_INT_SHIFT)) / tx_rate;
6712
6713 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
6714 bcnrc_val |= ((rf_int<<E1000_RTTBCNRC_RF_INT_SHIFT) &
6715 E1000_RTTBCNRC_RF_INT_MASK);
6716 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
6717 } else {
6718 bcnrc_val = 0;
6719 }
6720
6721 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
6722 wr32(E1000_RTTBCNRC, bcnrc_val);
6723}
6724
6725static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
6726{
6727 int actual_link_speed, i;
6728 bool reset_rate = false;
6729
6730 /* VF TX rate limit was not set or not supported */
6731 if ((adapter->vf_rate_link_speed == 0) ||
6732 (adapter->hw.mac.type != e1000_82576))
6733 return;
6734
6735 actual_link_speed = igb_link_mbps(adapter->link_speed);
6736 if (actual_link_speed != adapter->vf_rate_link_speed) {
6737 reset_rate = true;
6738 adapter->vf_rate_link_speed = 0;
6739 dev_info(&adapter->pdev->dev,
6740 "Link speed has been changed. VF Transmit "
6741 "rate is disabled\n");
6742 }
6743
6744 for (i = 0; i < adapter->vfs_allocated_count; i++) {
6745 if (reset_rate)
6746 adapter->vf_data[i].tx_rate = 0;
6747
6748 igb_set_vf_rate_limit(&adapter->hw, i,
6749 adapter->vf_data[i].tx_rate,
6750 actual_link_speed);
6751 }
6752}
6753
8151d294
WM		 6754static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate)
6755{
17dc566c
LL		 6756 struct igb_adapter *adapter = netdev_priv(netdev);
6757 struct e1000_hw *hw = &adapter->hw;
6758 int actual_link_speed;
6759
6760 if (hw->mac.type != e1000_82576)
6761 return -EOPNOTSUPP;
6762
6763 actual_link_speed = igb_link_mbps(adapter->link_speed);
6764 if ((vf >= adapter->vfs_allocated_count) ||
6765 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
6766 (tx_rate < 0) || (tx_rate > actual_link_speed))
6767 return -EINVAL;
6768
6769 adapter->vf_rate_link_speed = actual_link_speed;
6770 adapter->vf_data[vf].tx_rate = (u16)tx_rate;
6771 igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed);
6772
6773 return 0;
8151d294
WM		 6774}
6775
6776static int igb_ndo_get_vf_config(struct net_device *netdev,
6777 int vf, struct ifla_vf_info *ivi)
6778{
6779 struct igb_adapter *adapter = netdev_priv(netdev);
6780 if (vf >= adapter->vfs_allocated_count)
6781 return -EINVAL;
6782 ivi->vf = vf;
6783 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
17dc566c 6784 ivi->tx_rate = adapter->vf_data[vf].tx_rate;
8151d294
WM		 6785 ivi->vlan = adapter->vf_data[vf].pf_vlan;
6786 ivi->qos = adapter->vf_data[vf].pf_qos;
6787 return 0;
6788}
6789
4ae196df
AD		 6790static void igb_vmm_control(struct igb_adapter *adapter)
6791{
6792 struct e1000_hw *hw = &adapter->hw;
10d8e907 6793 u32 reg;
4ae196df 6794
52a1dd4d
AD		 6795 switch (hw->mac.type) {
6796 case e1000_82575:
6797 default:
6798 /* replication is not supported for 82575 */
4ae196df 6799 return;
52a1dd4d
AD		 6800 case e1000_82576:
6801 /* notify HW that the MAC is adding vlan tags */
6802 reg = rd32(E1000_DTXCTL);
6803 reg |= E1000_DTXCTL_VLAN_ADDED;
6804 wr32(E1000_DTXCTL, reg);
6805 case e1000_82580:
6806 /* enable replication vlan tag stripping */
6807 reg = rd32(E1000_RPLOLR);
6808 reg |= E1000_RPLOLR_STRVLAN;
6809 wr32(E1000_RPLOLR, reg);
d2ba2ed8
AD		 6810 case e1000_i350:
6811 /* none of the above registers are supported by i350 */
52a1dd4d
AD		 6812 break;
6813 }
10d8e907 6814
d4960307
AD		 6815 if (adapter->vfs_allocated_count) {
6816 igb_vmdq_set_loopback_pf(hw, true);
6817 igb_vmdq_set_replication_pf(hw, true);
13800469
GR		 6818 igb_vmdq_set_anti_spoofing_pf(hw, true,
6819 adapter->vfs_allocated_count);
d4960307
AD		 6820 } else {
6821 igb_vmdq_set_loopback_pf(hw, false);
6822 igb_vmdq_set_replication_pf(hw, false);
6823 }
4ae196df
AD		 6824}
6825
9d5c8243 6826/* igb_main.c */
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