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CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
86d5d38f 4 Copyright(c) 2007-2009 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/module.h>
29#include <linux/types.h>
30#include <linux/init.h>
31#include <linux/vmalloc.h>
32#include <linux/pagemap.h>
33#include <linux/netdevice.h>
9d5c8243
AK		 34#include <linux/ipv6.h>
35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
c6cb090b 37#include <linux/net_tstamp.h>
9d5c8243
AK		 38#include <linux/mii.h>
39#include <linux/ethtool.h>
40#include <linux/if_vlan.h>
41#include <linux/pci.h>
c54106bb 42#include <linux/pci-aspm.h>
9d5c8243
AK		 43#include <linux/delay.h>
44#include <linux/interrupt.h>
45#include <linux/if_ether.h>
40a914fa 46#include <linux/aer.h>
421e02f0 47#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 48#include <linux/dca.h>
49#endif
9d5c8243
AK		 50#include "igb.h"
51
86d5d38f 52#define DRV_VERSION "1.3.16-k2"
9d5c8243
AK		 53char igb_driver_name[] = "igb";
54char igb_driver_version[] = DRV_VERSION;
55static const char igb_driver_string[] =
56 "Intel(R) Gigabit Ethernet Network Driver";
86d5d38f 57static const char igb_copyright[] = "Copyright (c) 2007-2009 Intel Corporation.";
9d5c8243 58
9d5c8243
AK		 59static const struct e1000_info *igb_info_tbl[] = {
60 [board_82575] = &e1000_82575_info,
61};
62
63static struct pci_device_id igb_pci_tbl[] = {
2d064c06 64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
747d49ba 66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
2d064c06
AD		 67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
c8ea5ea9 70 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 71 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
72 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
73 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
74 /* required last entry */
75 {0, }
76};
77
78MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
79
80void igb_reset(struct igb_adapter *);
81static int igb_setup_all_tx_resources(struct igb_adapter *);
82static int igb_setup_all_rx_resources(struct igb_adapter *);
83static void igb_free_all_tx_resources(struct igb_adapter *);
84static void igb_free_all_rx_resources(struct igb_adapter *);
9d5c8243
AK		 85void igb_update_stats(struct igb_adapter *);
86static int igb_probe(struct pci_dev *, const struct pci_device_id *);
87static void __devexit igb_remove(struct pci_dev *pdev);
88static int igb_sw_init(struct igb_adapter *);
89static int igb_open(struct net_device *);
90static int igb_close(struct net_device *);
91static void igb_configure_tx(struct igb_adapter *);
92static void igb_configure_rx(struct igb_adapter *);
93static void igb_setup_rctl(struct igb_adapter *);
94static void igb_clean_all_tx_rings(struct igb_adapter *);
95static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 96static void igb_clean_tx_ring(struct igb_ring *);
97static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 98static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 99static void igb_update_phy_info(unsigned long);
100static void igb_watchdog(unsigned long);
101static void igb_watchdog_task(struct work_struct *);
3b29a56d
SH		 102static netdev_tx_t igb_xmit_frame_ring_adv(struct sk_buff *,
103 struct net_device *,
104 struct igb_ring *);
105static netdev_tx_t igb_xmit_frame_adv(struct sk_buff *skb,
106 struct net_device *);
9d5c8243
AK		 107static struct net_device_stats *igb_get_stats(struct net_device *);
108static int igb_change_mtu(struct net_device *, int);
109static int igb_set_mac(struct net_device *, void *);
68d480c4 110static void igb_set_uta(struct igb_adapter *adapter);
9d5c8243
AK		 111static irqreturn_t igb_intr(int irq, void *);
112static irqreturn_t igb_intr_msi(int irq, void *);
113static irqreturn_t igb_msix_other(int irq, void *);
114static irqreturn_t igb_msix_rx(int irq, void *);
115static irqreturn_t igb_msix_tx(int irq, void *);
421e02f0 116#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 117static void igb_update_rx_dca(struct igb_ring *);
118static void igb_update_tx_dca(struct igb_ring *);
119static void igb_setup_dca(struct igb_adapter *);
421e02f0 120#endif /* CONFIG_IGB_DCA */
3b644cf6 121static bool igb_clean_tx_irq(struct igb_ring *);
661086df 122static int igb_poll(struct napi_struct *, int);
3b644cf6
MW		 123static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int);
124static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
9d5c8243
AK		 125static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
126static void igb_tx_timeout(struct net_device *);
127static void igb_reset_task(struct work_struct *);
128static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
129static void igb_vlan_rx_add_vid(struct net_device *, u16);
130static void igb_vlan_rx_kill_vid(struct net_device *, u16);
131static void igb_restore_vlan(struct igb_adapter *);
26ad9178 132static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
4ae196df
AD		 133static void igb_ping_all_vfs(struct igb_adapter *);
134static void igb_msg_task(struct igb_adapter *);
135static int igb_rcv_msg_from_vf(struct igb_adapter *, u32);
4ae196df 136static void igb_vmm_control(struct igb_adapter *);
4ae196df
AD		 137static int igb_set_vf_mac(struct igb_adapter *adapter, int, unsigned char *);
138static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
9d5c8243 139
c8159b2d
ED		 140static inline void igb_set_vmolr(struct e1000_hw *hw, int vfn)
141{
142 u32 reg_data;
143
144 reg_data = rd32(E1000_VMOLR(vfn));
145 reg_data |= E1000_VMOLR_BAM | /* Accept broadcast */
c8159b2d
ED		 146 E1000_VMOLR_ROMPE | /* Accept packets matched in MTA */
147 E1000_VMOLR_AUPE | /* Accept untagged packets */
148 E1000_VMOLR_STRVLAN; /* Strip vlan tags */
149 wr32(E1000_VMOLR(vfn), reg_data);
150}
151
152static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
153 int vfn)
154{
155 struct e1000_hw *hw = &adapter->hw;
156 u32 vmolr;
157
ae641bdc
AD		 158 /* if it isn't the PF check to see if VFs are enabled and
159 * increase the size to support vlan tags */
160 if (vfn < adapter->vfs_allocated_count &&
161 adapter->vf_data[vfn].vlans_enabled)
162 size += VLAN_TAG_SIZE;
163
c8159b2d
ED		 164 vmolr = rd32(E1000_VMOLR(vfn));
165 vmolr &= ~E1000_VMOLR_RLPML_MASK;
166 vmolr |= size | E1000_VMOLR_LPE;
167 wr32(E1000_VMOLR(vfn), vmolr);
168
169 return 0;
170}
171
9d5c8243 172#ifdef CONFIG_PM
3fe7c4c9 173static int igb_suspend(struct pci_dev *, pm_message_t);
9d5c8243
AK		 174static int igb_resume(struct pci_dev *);
175#endif
176static void igb_shutdown(struct pci_dev *);
421e02f0 177#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 178static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
179static struct notifier_block dca_notifier = {
180 .notifier_call = igb_notify_dca,
181 .next = NULL,
182 .priority = 0
183};
184#endif
9d5c8243
AK		 185#ifdef CONFIG_NET_POLL_CONTROLLER
186/* for netdump / net console */
187static void igb_netpoll(struct net_device *);
188#endif
37680117 189#ifdef CONFIG_PCI_IOV
2a3abf6d
AD		 190static unsigned int max_vfs = 0;
191module_param(max_vfs, uint, 0);
192MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
193 "per physical function");
194#endif /* CONFIG_PCI_IOV */
195
9d5c8243
AK		 196static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
197 pci_channel_state_t);
198static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
199static void igb_io_resume(struct pci_dev *);
200
201static struct pci_error_handlers igb_err_handler = {
202 .error_detected = igb_io_error_detected,
203 .slot_reset = igb_io_slot_reset,
204 .resume = igb_io_resume,
205};
206
207
208static struct pci_driver igb_driver = {
209 .name = igb_driver_name,
210 .id_table = igb_pci_tbl,
211 .probe = igb_probe,
212 .remove = __devexit_p(igb_remove),
213#ifdef CONFIG_PM
214 /* Power Managment Hooks */
215 .suspend = igb_suspend,
216 .resume = igb_resume,
217#endif
218 .shutdown = igb_shutdown,
219 .err_handler = &igb_err_handler
220};
221
7dfc16fa
AD		 222static int global_quad_port_a; /* global quad port a indication */
223
9d5c8243
AK		 224MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
225MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
226MODULE_LICENSE("GPL");
227MODULE_VERSION(DRV_VERSION);
228
38c845c7
PO		 229/**
230 * Scale the NIC clock cycle by a large factor so that
231 * relatively small clock corrections can be added or
232 * substracted at each clock tick. The drawbacks of a
233 * large factor are a) that the clock register overflows
234 * more quickly (not such a big deal) and b) that the
235 * increment per tick has to fit into 24 bits.
236 *
237 * Note that
238 * TIMINCA = IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS *
239 * IGB_TSYNC_SCALE
240 * TIMINCA += TIMINCA * adjustment [ppm] / 1e9
241 *
242 * The base scale factor is intentionally a power of two
243 * so that the division in %struct timecounter can be done with
244 * a shift.
245 */
246#define IGB_TSYNC_SHIFT (19)
247#define IGB_TSYNC_SCALE (1<<IGB_TSYNC_SHIFT)
248
249/**
250 * The duration of one clock cycle of the NIC.
251 *
252 * @todo This hard-coded value is part of the specification and might change
253 * in future hardware revisions. Add revision check.
254 */
255#define IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS 16
256
257#if (IGB_TSYNC_SCALE * IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS) >= (1<<24)
258# error IGB_TSYNC_SCALE and/or IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS are too large to fit into TIMINCA
259#endif
260
261/**
262 * igb_read_clock - read raw cycle counter (to be used by time counter)
263 */
264static cycle_t igb_read_clock(const struct cyclecounter *tc)
265{
266 struct igb_adapter *adapter =
267 container_of(tc, struct igb_adapter, cycles);
268 struct e1000_hw *hw = &adapter->hw;
269 u64 stamp;
270
271 stamp = rd32(E1000_SYSTIML);
272 stamp |= (u64)rd32(E1000_SYSTIMH) << 32ULL;
273
274 return stamp;
275}
276
9d5c8243
AK		 277#ifdef DEBUG
278/**
279 * igb_get_hw_dev_name - return device name string
280 * used by hardware layer to print debugging information
281 **/
282char *igb_get_hw_dev_name(struct e1000_hw *hw)
283{
284 struct igb_adapter *adapter = hw->back;
285 return adapter->netdev->name;
286}
38c845c7
PO		 287
288/**
289 * igb_get_time_str - format current NIC and system time as string
290 */
291static char *igb_get_time_str(struct igb_adapter *adapter,
292 char buffer[160])
293{
294 cycle_t hw = adapter->cycles.read(&adapter->cycles);
295 struct timespec nic = ns_to_timespec(timecounter_read(&adapter->clock));
296 struct timespec sys;
297 struct timespec delta;
298 getnstimeofday(&sys);
299
300 delta = timespec_sub(nic, sys);
301
302 sprintf(buffer,
33af6bcc
PO		 303 "HW %llu, NIC %ld.%09lus, SYS %ld.%09lus, NIC-SYS %lds + %09luns",
304 hw,
38c845c7
PO		 305 (long)nic.tv_sec, nic.tv_nsec,
306 (long)sys.tv_sec, sys.tv_nsec,
307 (long)delta.tv_sec, delta.tv_nsec);
308
309 return buffer;
310}
9d5c8243
AK		 311#endif
312
c493ea45
AD		 313/**
314 * igb_desc_unused - calculate if we have unused descriptors
315 **/
316static int igb_desc_unused(struct igb_ring *ring)
317{
318 if (ring->next_to_clean > ring->next_to_use)
319 return ring->next_to_clean - ring->next_to_use - 1;
320
321 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
322}
323
9d5c8243
AK		 324/**
325 * igb_init_module - Driver Registration Routine
326 *
327 * igb_init_module is the first routine called when the driver is
328 * loaded. All it does is register with the PCI subsystem.
329 **/
330static int __init igb_init_module(void)
331{
332 int ret;
333 printk(KERN_INFO "%s - version %s\n",
334 igb_driver_string, igb_driver_version);
335
336 printk(KERN_INFO "%s\n", igb_copyright);
337
7dfc16fa
AD		 338 global_quad_port_a = 0;
339
421e02f0 340#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 341 dca_register_notify(&dca_notifier);
342#endif
bbd98fe4
AD		 343
344 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 345 return ret;
346}
347
348module_init(igb_init_module);
349
350/**
351 * igb_exit_module - Driver Exit Cleanup Routine
352 *
353 * igb_exit_module is called just before the driver is removed
354 * from memory.
355 **/
356static void __exit igb_exit_module(void)
357{
421e02f0 358#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 359 dca_unregister_notify(&dca_notifier);
360#endif
9d5c8243
AK		 361 pci_unregister_driver(&igb_driver);
362}
363
364module_exit(igb_exit_module);
365
26bc19ec
AD		 366#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
367/**
368 * igb_cache_ring_register - Descriptor ring to register mapping
369 * @adapter: board private structure to initialize
370 *
371 * Once we know the feature-set enabled for the device, we'll cache
372 * the register offset the descriptor ring is assigned to.
373 **/
374static void igb_cache_ring_register(struct igb_adapter *adapter)
375{
376 int i;
1bfaf07b 377 unsigned int rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 378
379 switch (adapter->hw.mac.type) {
380 case e1000_82576:
381 /* The queues are allocated for virtualization such that VF 0
382 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
383 * In order to avoid collision we start at the first free queue
384 * and continue consuming queues in the same sequence
385 */
386 for (i = 0; i < adapter->num_rx_queues; i++)
1bfaf07b
AD		 387 adapter->rx_ring[i].reg_idx = rbase_offset +
388 Q_IDX_82576(i);
26bc19ec 389 for (i = 0; i < adapter->num_tx_queues; i++)
1bfaf07b
AD		 390 adapter->tx_ring[i].reg_idx = rbase_offset +
391 Q_IDX_82576(i);
26bc19ec
AD		 392 break;
393 case e1000_82575:
394 default:
395 for (i = 0; i < adapter->num_rx_queues; i++)
396 adapter->rx_ring[i].reg_idx = i;
397 for (i = 0; i < adapter->num_tx_queues; i++)
398 adapter->tx_ring[i].reg_idx = i;
399 break;
400 }
401}
402
9d5c8243
AK		 403/**
404 * igb_alloc_queues - Allocate memory for all rings
405 * @adapter: board private structure to initialize
406 *
407 * We allocate one ring per queue at run-time since we don't know the
408 * number of queues at compile-time.
409 **/
410static int igb_alloc_queues(struct igb_adapter *adapter)
411{
412 int i;
413
414 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
415 sizeof(struct igb_ring), GFP_KERNEL);
416 if (!adapter->tx_ring)
417 return -ENOMEM;
418
419 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
420 sizeof(struct igb_ring), GFP_KERNEL);
421 if (!adapter->rx_ring) {
422 kfree(adapter->tx_ring);
423 return -ENOMEM;
424 }
425
6eb5a7f1
AD		 426 adapter->rx_ring->buddy = adapter->tx_ring;
427
661086df
PWJ		 428 for (i = 0; i < adapter->num_tx_queues; i++) {
429 struct igb_ring *ring = &(adapter->tx_ring[i]);
68fd9910 430 ring->count = adapter->tx_ring_count;
661086df
PWJ		 431 ring->adapter = adapter;
432 ring->queue_index = i;
433 }
9d5c8243
AK		 434 for (i = 0; i < adapter->num_rx_queues; i++) {
435 struct igb_ring *ring = &(adapter->rx_ring[i]);
68fd9910 436 ring->count = adapter->rx_ring_count;
9d5c8243 437 ring->adapter = adapter;
844290e5 438 ring->queue_index = i;
9d5c8243
AK		 439 ring->itr_register = E1000_ITR;
440
844290e5 441 /* set a default napi handler for each rx_ring */
661086df 442 netif_napi_add(adapter->netdev, &ring->napi, igb_poll, 64);
9d5c8243 443 }
26bc19ec
AD		 444
445 igb_cache_ring_register(adapter);
9d5c8243
AK		 446 return 0;
447}
448
a88f10ec
AD		 449static void igb_free_queues(struct igb_adapter *adapter)
450{
451 int i;
452
453 for (i = 0; i < adapter->num_rx_queues; i++)
454 netif_napi_del(&adapter->rx_ring[i].napi);
455
d1a8c9e1
AD		 456 adapter->num_rx_queues = 0;
457 adapter->num_tx_queues = 0;
458
a88f10ec
AD		 459 kfree(adapter->tx_ring);
460 kfree(adapter->rx_ring);
461}
462
9d5c8243
AK		 463#define IGB_N0_QUEUE -1
464static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
465 int tx_queue, int msix_vector)
466{
467 u32 msixbm = 0;
468 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 469 u32 ivar, index;
470
471 switch (hw->mac.type) {
472 case e1000_82575:
9d5c8243
AK		 473 /* The 82575 assigns vectors using a bitmask, which matches the
474 bitmask for the EICR/EIMS/EIMC registers. To assign one
475 or more queues to a vector, we write the appropriate bits
476 into the MSIXBM register for that vector. */
477 if (rx_queue > IGB_N0_QUEUE) {
478 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
479 adapter->rx_ring[rx_queue].eims_value = msixbm;
480 }
481 if (tx_queue > IGB_N0_QUEUE) {
482 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
483 adapter->tx_ring[tx_queue].eims_value =
484 E1000_EICR_TX_QUEUE0 << tx_queue;
485 }
486 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
2d064c06
AD		 487 break;
488 case e1000_82576:
26bc19ec 489 /* 82576 uses a table-based method for assigning vectors.
2d064c06
AD		 490 Each queue has a single entry in the table to which we write
491 a vector number along with a "valid" bit. Sadly, the layout
492 of the table is somewhat counterintuitive. */
493 if (rx_queue > IGB_N0_QUEUE) {
1bfaf07b 494 index = (rx_queue >> 1) + adapter->vfs_allocated_count;
2d064c06 495 ivar = array_rd32(E1000_IVAR0, index);
26bc19ec 496 if (rx_queue & 0x1) {
2d064c06
AD		 497 /* vector goes into third byte of register */
498 ivar = ivar & 0xFF00FFFF;
499 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
26bc19ec
AD		 500 } else {
501 /* vector goes into low byte of register */
502 ivar = ivar & 0xFFFFFF00;
503 ivar |= msix_vector | E1000_IVAR_VALID;
2d064c06
AD		 504 }
505 adapter->rx_ring[rx_queue].eims_value= 1 << msix_vector;
506 array_wr32(E1000_IVAR0, index, ivar);
507 }
508 if (tx_queue > IGB_N0_QUEUE) {
1bfaf07b 509 index = (tx_queue >> 1) + adapter->vfs_allocated_count;
2d064c06 510 ivar = array_rd32(E1000_IVAR0, index);
26bc19ec 511 if (tx_queue & 0x1) {
2d064c06
AD		 512 /* vector goes into high byte of register */
513 ivar = ivar & 0x00FFFFFF;
514 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
26bc19ec
AD		 515 } else {
516 /* vector goes into second byte of register */
517 ivar = ivar & 0xFFFF00FF;
518 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
2d064c06
AD		 519 }
520 adapter->tx_ring[tx_queue].eims_value= 1 << msix_vector;
521 array_wr32(E1000_IVAR0, index, ivar);
522 }
523 break;
524 default:
525 BUG();
526 break;
527 }
9d5c8243
AK		 528}
529
530/**
531 * igb_configure_msix - Configure MSI-X hardware
532 *
533 * igb_configure_msix sets up the hardware to properly
534 * generate MSI-X interrupts.
535 **/
536static void igb_configure_msix(struct igb_adapter *adapter)
537{
538 u32 tmp;
539 int i, vector = 0;
540 struct e1000_hw *hw = &adapter->hw;
541
542 adapter->eims_enable_mask = 0;
2d064c06
AD		 543 if (hw->mac.type == e1000_82576)
544 /* Turn on MSI-X capability first, or our settings
545 * won't stick. And it will take days to debug. */
546 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
eebbbdba 547 E1000_GPIE_PBA | E1000_GPIE_EIAME |
2d064c06 548 E1000_GPIE_NSICR);
9d5c8243
AK		 549
550 for (i = 0; i < adapter->num_tx_queues; i++) {
551 struct igb_ring *tx_ring = &adapter->tx_ring[i];
552 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
553 adapter->eims_enable_mask |= tx_ring->eims_value;
554 if (tx_ring->itr_val)
6eb5a7f1 555 writel(tx_ring->itr_val,
9d5c8243
AK		 556 hw->hw_addr + tx_ring->itr_register);
557 else
558 writel(1, hw->hw_addr + tx_ring->itr_register);
559 }
560
561 for (i = 0; i < adapter->num_rx_queues; i++) {
562 struct igb_ring *rx_ring = &adapter->rx_ring[i];
25ac3c24 563 rx_ring->buddy = NULL;
9d5c8243
AK		 564 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
565 adapter->eims_enable_mask |= rx_ring->eims_value;
566 if (rx_ring->itr_val)
6eb5a7f1 567 writel(rx_ring->itr_val,
9d5c8243
AK		 568 hw->hw_addr + rx_ring->itr_register);
569 else
570 writel(1, hw->hw_addr + rx_ring->itr_register);
571 }
572
573
574 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 575 switch (hw->mac.type) {
576 case e1000_82575:
9d5c8243
AK		 577 array_wr32(E1000_MSIXBM(0), vector++,
578 E1000_EIMS_OTHER);
579
9d5c8243
AK		 580 tmp = rd32(E1000_CTRL_EXT);
581 /* enable MSI-X PBA support*/
582 tmp |= E1000_CTRL_EXT_PBA_CLR;
583
584 /* Auto-Mask interrupts upon ICR read. */
585 tmp |= E1000_CTRL_EXT_EIAME;
586 tmp |= E1000_CTRL_EXT_IRCA;
587
588 wr32(E1000_CTRL_EXT, tmp);
589 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
844290e5 590 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 591
2d064c06
AD		 592 break;
593
594 case e1000_82576:
595 tmp = (vector++ | E1000_IVAR_VALID) << 8;
596 wr32(E1000_IVAR_MISC, tmp);
597
598 adapter->eims_enable_mask = (1 << (vector)) - 1;
599 adapter->eims_other = 1 << (vector - 1);
600 break;
601 default:
602 /* do nothing, since nothing else supports MSI-X */
603 break;
604 } /* switch (hw->mac.type) */
9d5c8243
AK		 605 wrfl();
606}
607
608/**
609 * igb_request_msix - Initialize MSI-X interrupts
610 *
611 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
612 * kernel.
613 **/
614static int igb_request_msix(struct igb_adapter *adapter)
615{
616 struct net_device *netdev = adapter->netdev;
617 int i, err = 0, vector = 0;
618
619 vector = 0;
620
621 for (i = 0; i < adapter->num_tx_queues; i++) {
622 struct igb_ring *ring = &(adapter->tx_ring[i]);
cb7b48f6 623 sprintf(ring->name, "%s-tx-%d", netdev->name, i);
9d5c8243
AK		 624 err = request_irq(adapter->msix_entries[vector].vector,
625 &igb_msix_tx, 0, ring->name,
626 &(adapter->tx_ring[i]));
627 if (err)
628 goto out;
629 ring->itr_register = E1000_EITR(0) + (vector << 2);
6eb5a7f1 630 ring->itr_val = 976; /* ~4000 ints/sec */
9d5c8243
AK		 631 vector++;
632 }
633 for (i = 0; i < adapter->num_rx_queues; i++) {
634 struct igb_ring *ring = &(adapter->rx_ring[i]);
635 if (strlen(netdev->name) < (IFNAMSIZ - 5))
cb7b48f6 636 sprintf(ring->name, "%s-rx-%d", netdev->name, i);
9d5c8243
AK		 637 else
638 memcpy(ring->name, netdev->name, IFNAMSIZ);
639 err = request_irq(adapter->msix_entries[vector].vector,
640 &igb_msix_rx, 0, ring->name,
641 &(adapter->rx_ring[i]));
642 if (err)
643 goto out;
644 ring->itr_register = E1000_EITR(0) + (vector << 2);
645 ring->itr_val = adapter->itr;
646 vector++;
647 }
648
649 err = request_irq(adapter->msix_entries[vector].vector,
650 &igb_msix_other, 0, netdev->name, netdev);
651 if (err)
652 goto out;
653
9d5c8243
AK		 654 igb_configure_msix(adapter);
655 return 0;
656out:
657 return err;
658}
659
660static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
661{
662 if (adapter->msix_entries) {
663 pci_disable_msix(adapter->pdev);
664 kfree(adapter->msix_entries);
665 adapter->msix_entries = NULL;
7dfc16fa 666 } else if (adapter->flags & IGB_FLAG_HAS_MSI)
9d5c8243
AK		 667 pci_disable_msi(adapter->pdev);
668 return;
669}
670
671
672/**
673 * igb_set_interrupt_capability - set MSI or MSI-X if supported
674 *
675 * Attempt to configure interrupts using the best available
676 * capabilities of the hardware and kernel.
677 **/
678static void igb_set_interrupt_capability(struct igb_adapter *adapter)
679{
680 int err;
681 int numvecs, i;
682
83b7180d
AD		 683 /* Number of supported queues. */
684 /* Having more queues than CPUs doesn't make sense. */
685 adapter->num_rx_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
686 adapter->num_tx_queues = min_t(u32, IGB_MAX_TX_QUEUES, num_online_cpus());
687
9d5c8243
AK		 688 numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1;
689 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
690 GFP_KERNEL);
691 if (!adapter->msix_entries)
692 goto msi_only;
693
694 for (i = 0; i < numvecs; i++)
695 adapter->msix_entries[i].entry = i;
696
697 err = pci_enable_msix(adapter->pdev,
698 adapter->msix_entries,
699 numvecs);
700 if (err == 0)
34a20e89 701 goto out;
9d5c8243
AK		 702
703 igb_reset_interrupt_capability(adapter);
704
705 /* If we can't do MSI-X, try MSI */
706msi_only:
2a3abf6d
AD		 707#ifdef CONFIG_PCI_IOV
708 /* disable SR-IOV for non MSI-X configurations */
709 if (adapter->vf_data) {
710 struct e1000_hw *hw = &adapter->hw;
711 /* disable iov and allow time for transactions to clear */
712 pci_disable_sriov(adapter->pdev);
713 msleep(500);
714
715 kfree(adapter->vf_data);
716 adapter->vf_data = NULL;
717 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
718 msleep(100);
719 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
720 }
721#endif
9d5c8243 722 adapter->num_rx_queues = 1;
661086df 723 adapter->num_tx_queues = 1;
9d5c8243 724 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 725 adapter->flags |= IGB_FLAG_HAS_MSI;
34a20e89 726out:
661086df 727 /* Notify the stack of the (possibly) reduced Tx Queue count. */
fd2ea0a7 728 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
9d5c8243
AK		 729 return;
730}
731
732/**
733 * igb_request_irq - initialize interrupts
734 *
735 * Attempts to configure interrupts using the best available
736 * capabilities of the hardware and kernel.
737 **/
738static int igb_request_irq(struct igb_adapter *adapter)
739{
740 struct net_device *netdev = adapter->netdev;
741 struct e1000_hw *hw = &adapter->hw;
742 int err = 0;
743
744 if (adapter->msix_entries) {
745 err = igb_request_msix(adapter);
844290e5 746 if (!err)
9d5c8243 747 goto request_done;
9d5c8243
AK		 748 /* fall back to MSI */
749 igb_reset_interrupt_capability(adapter);
750 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 751 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 752 igb_free_all_tx_resources(adapter);
753 igb_free_all_rx_resources(adapter);
754 adapter->num_rx_queues = 1;
755 igb_alloc_queues(adapter);
844290e5 756 } else {
2d064c06
AD		 757 switch (hw->mac.type) {
758 case e1000_82575:
759 wr32(E1000_MSIXBM(0),
760 (E1000_EICR_RX_QUEUE0 | E1000_EIMS_OTHER));
761 break;
762 case e1000_82576:
763 wr32(E1000_IVAR0, E1000_IVAR_VALID);
764 break;
765 default:
766 break;
767 }
9d5c8243 768 }
844290e5 769
7dfc16fa 770 if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243
AK		 771 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
772 netdev->name, netdev);
773 if (!err)
774 goto request_done;
775 /* fall back to legacy interrupts */
776 igb_reset_interrupt_capability(adapter);
7dfc16fa 777 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 778 }
779
780 err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
781 netdev->name, netdev);
782
6cb5e577 783 if (err)
9d5c8243
AK		 784 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
785 err);
9d5c8243
AK		 786
787request_done:
788 return err;
789}
790
791static void igb_free_irq(struct igb_adapter *adapter)
792{
793 struct net_device *netdev = adapter->netdev;
794
795 if (adapter->msix_entries) {
796 int vector = 0, i;
797
798 for (i = 0; i < adapter->num_tx_queues; i++)
799 free_irq(adapter->msix_entries[vector++].vector,
800 &(adapter->tx_ring[i]));
801 for (i = 0; i < adapter->num_rx_queues; i++)
802 free_irq(adapter->msix_entries[vector++].vector,
803 &(adapter->rx_ring[i]));
804
805 free_irq(adapter->msix_entries[vector++].vector, netdev);
806 return;
807 }
808
809 free_irq(adapter->pdev->irq, netdev);
810}
811
812/**
813 * igb_irq_disable - Mask off interrupt generation on the NIC
814 * @adapter: board private structure
815 **/
816static void igb_irq_disable(struct igb_adapter *adapter)
817{
818 struct e1000_hw *hw = &adapter->hw;
819
820 if (adapter->msix_entries) {
2dfd1212
AD		 821 u32 regval = rd32(E1000_EIAM);
822 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
823 wr32(E1000_EIMC, adapter->eims_enable_mask);
824 regval = rd32(E1000_EIAC);
825 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 826 }
844290e5
PW		 827
828 wr32(E1000_IAM, 0);
9d5c8243
AK		 829 wr32(E1000_IMC, ~0);
830 wrfl();
831 synchronize_irq(adapter->pdev->irq);
832}
833
834/**
835 * igb_irq_enable - Enable default interrupt generation settings
836 * @adapter: board private structure
837 **/
838static void igb_irq_enable(struct igb_adapter *adapter)
839{
840 struct e1000_hw *hw = &adapter->hw;
841
842 if (adapter->msix_entries) {
2dfd1212
AD		 843 u32 regval = rd32(E1000_EIAC);
844 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
845 regval = rd32(E1000_EIAM);
846 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 847 wr32(E1000_EIMS, adapter->eims_enable_mask);
4ae196df
AD		 848 if (adapter->vfs_allocated_count)
849 wr32(E1000_MBVFIMR, 0xFF);
850 wr32(E1000_IMS, (E1000_IMS_LSC | E1000_IMS_VMMB |
851 E1000_IMS_DOUTSYNC));
844290e5
PW		 852 } else {
853 wr32(E1000_IMS, IMS_ENABLE_MASK);
854 wr32(E1000_IAM, IMS_ENABLE_MASK);
855 }
9d5c8243
AK		 856}
857
858static void igb_update_mng_vlan(struct igb_adapter *adapter)
859{
860 struct net_device *netdev = adapter->netdev;
861 u16 vid = adapter->hw.mng_cookie.vlan_id;
862 u16 old_vid = adapter->mng_vlan_id;
863 if (adapter->vlgrp) {
864 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
865 if (adapter->hw.mng_cookie.status &
866 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
867 igb_vlan_rx_add_vid(netdev, vid);
868 adapter->mng_vlan_id = vid;
869 } else
870 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
871
872 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
873 (vid != old_vid) &&
874 !vlan_group_get_device(adapter->vlgrp, old_vid))
875 igb_vlan_rx_kill_vid(netdev, old_vid);
876 } else
877 adapter->mng_vlan_id = vid;
878 }
879}
880
881/**
882 * igb_release_hw_control - release control of the h/w to f/w
883 * @adapter: address of board private structure
884 *
885 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
886 * For ASF and Pass Through versions of f/w this means that the
887 * driver is no longer loaded.
888 *
889 **/
890static void igb_release_hw_control(struct igb_adapter *adapter)
891{
892 struct e1000_hw *hw = &adapter->hw;
893 u32 ctrl_ext;
894
895 /* Let firmware take over control of h/w */
896 ctrl_ext = rd32(E1000_CTRL_EXT);
897 wr32(E1000_CTRL_EXT,
898 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
899}
900
901
902/**
903 * igb_get_hw_control - get control of the h/w from f/w
904 * @adapter: address of board private structure
905 *
906 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
907 * For ASF and Pass Through versions of f/w this means that
908 * the driver is loaded.
909 *
910 **/
911static void igb_get_hw_control(struct igb_adapter *adapter)
912{
913 struct e1000_hw *hw = &adapter->hw;
914 u32 ctrl_ext;
915
916 /* Let firmware know the driver has taken over */
917 ctrl_ext = rd32(E1000_CTRL_EXT);
918 wr32(E1000_CTRL_EXT,
919 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
920}
921
9d5c8243
AK		 922/**
923 * igb_configure - configure the hardware for RX and TX
924 * @adapter: private board structure
925 **/
926static void igb_configure(struct igb_adapter *adapter)
927{
928 struct net_device *netdev = adapter->netdev;
929 int i;
930
931 igb_get_hw_control(adapter);
ff41f8dc 932 igb_set_rx_mode(netdev);
9d5c8243
AK		 933
934 igb_restore_vlan(adapter);
9d5c8243
AK		 935
936 igb_configure_tx(adapter);
937 igb_setup_rctl(adapter);
938 igb_configure_rx(adapter);
662d7205
AD		 939
940 igb_rx_fifo_flush_82575(&adapter->hw);
941
c493ea45 942 /* call igb_desc_unused which always leaves
9d5c8243
AK		 943 * at least 1 descriptor unused to make sure
944 * next_to_use != next_to_clean */
945 for (i = 0; i < adapter->num_rx_queues; i++) {
946 struct igb_ring *ring = &adapter->rx_ring[i];
c493ea45 947 igb_alloc_rx_buffers_adv(ring, igb_desc_unused(ring));
9d5c8243
AK		 948 }
949
950
951 adapter->tx_queue_len = netdev->tx_queue_len;
952}
953
954
955/**
956 * igb_up - Open the interface and prepare it to handle traffic
957 * @adapter: board private structure
958 **/
959
960int igb_up(struct igb_adapter *adapter)
961{
962 struct e1000_hw *hw = &adapter->hw;
963 int i;
964
965 /* hardware has been reset, we need to reload some things */
966 igb_configure(adapter);
967
968 clear_bit(__IGB_DOWN, &adapter->state);
969
844290e5
PW		 970 for (i = 0; i < adapter->num_rx_queues; i++)
971 napi_enable(&adapter->rx_ring[i].napi);
972 if (adapter->msix_entries)
9d5c8243 973 igb_configure_msix(adapter);
9d5c8243 974
4ae196df 975 igb_vmm_control(adapter);
e1739522
AD		 976 igb_set_vmolr(hw, adapter->vfs_allocated_count);
977
9d5c8243
AK		 978 /* Clear any pending interrupts. */
979 rd32(E1000_ICR);
980 igb_irq_enable(adapter);
981
4cb9be7a
JB		 982 netif_tx_start_all_queues(adapter->netdev);
983
9d5c8243
AK		 984 /* Fire a link change interrupt to start the watchdog. */
985 wr32(E1000_ICS, E1000_ICS_LSC);
986 return 0;
987}
988
989void igb_down(struct igb_adapter *adapter)
990{
991 struct e1000_hw *hw = &adapter->hw;
992 struct net_device *netdev = adapter->netdev;
993 u32 tctl, rctl;
994 int i;
995
996 /* signal that we're down so the interrupt handler does not
997 * reschedule our watchdog timer */
998 set_bit(__IGB_DOWN, &adapter->state);
999
1000 /* disable receives in the hardware */
1001 rctl = rd32(E1000_RCTL);
1002 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1003 /* flush and sleep below */
1004
fd2ea0a7 1005 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1006
1007 /* disable transmits in the hardware */
1008 tctl = rd32(E1000_TCTL);
1009 tctl &= ~E1000_TCTL_EN;
1010 wr32(E1000_TCTL, tctl);
1011 /* flush both disables and wait for them to finish */
1012 wrfl();
1013 msleep(10);
1014
844290e5
PW		 1015 for (i = 0; i < adapter->num_rx_queues; i++)
1016 napi_disable(&adapter->rx_ring[i].napi);
9d5c8243 1017
9d5c8243
AK		 1018 igb_irq_disable(adapter);
1019
1020 del_timer_sync(&adapter->watchdog_timer);
1021 del_timer_sync(&adapter->phy_info_timer);
1022
1023 netdev->tx_queue_len = adapter->tx_queue_len;
1024 netif_carrier_off(netdev);
04fe6358
AD		 1025
1026 /* record the stats before reset*/
1027 igb_update_stats(adapter);
1028
9d5c8243
AK		 1029 adapter->link_speed = 0;
1030 adapter->link_duplex = 0;
1031
3023682e
JK		 1032 if (!pci_channel_offline(adapter->pdev))
1033 igb_reset(adapter);
9d5c8243
AK		 1034 igb_clean_all_tx_rings(adapter);
1035 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1036#ifdef CONFIG_IGB_DCA
1037
1038 /* since we reset the hardware DCA settings were cleared */
1039 igb_setup_dca(adapter);
1040#endif
9d5c8243
AK		 1041}
1042
1043void igb_reinit_locked(struct igb_adapter *adapter)
1044{
1045 WARN_ON(in_interrupt());
1046 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1047 msleep(1);
1048 igb_down(adapter);
1049 igb_up(adapter);
1050 clear_bit(__IGB_RESETTING, &adapter->state);
1051}
1052
1053void igb_reset(struct igb_adapter *adapter)
1054{
1055 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1056 struct e1000_mac_info *mac = &hw->mac;
1057 struct e1000_fc_info *fc = &hw->fc;
9d5c8243
AK		 1058 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
1059 u16 hwm;
1060
1061 /* Repartition Pba for greater than 9k mtu
1062 * To take effect CTRL.RST is required.
1063 */
fa4dfae0
AD		 1064 switch (mac->type) {
1065 case e1000_82576:
2d064c06 1066 pba = E1000_PBA_64K;
fa4dfae0
AD		 1067 break;
1068 case e1000_82575:
1069 default:
1070 pba = E1000_PBA_34K;
1071 break;
2d064c06 1072 }
9d5c8243 1073
2d064c06
AD		 1074 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1075 (mac->type < e1000_82576)) {
9d5c8243
AK		 1076 /* adjust PBA for jumbo frames */
1077 wr32(E1000_PBA, pba);
1078
1079 /* To maintain wire speed transmits, the Tx FIFO should be
1080 * large enough to accommodate two full transmit packets,
1081 * rounded up to the next 1KB and expressed in KB. Likewise,
1082 * the Rx FIFO should be large enough to accommodate at least
1083 * one full receive packet and is similarly rounded up and
1084 * expressed in KB. */
1085 pba = rd32(E1000_PBA);
1086 /* upper 16 bits has Tx packet buffer allocation size in KB */
1087 tx_space = pba >> 16;
1088 /* lower 16 bits has Rx packet buffer allocation size in KB */
1089 pba &= 0xffff;
1090 /* the tx fifo also stores 16 bytes of information about the tx
1091 * but don't include ethernet FCS because hardware appends it */
1092 min_tx_space = (adapter->max_frame_size +
85e8d004 1093 sizeof(union e1000_adv_tx_desc) -
9d5c8243
AK		 1094 ETH_FCS_LEN) * 2;
1095 min_tx_space = ALIGN(min_tx_space, 1024);
1096 min_tx_space >>= 10;
1097 /* software strips receive CRC, so leave room for it */
1098 min_rx_space = adapter->max_frame_size;
1099 min_rx_space = ALIGN(min_rx_space, 1024);
1100 min_rx_space >>= 10;
1101
1102 /* If current Tx allocation is less than the min Tx FIFO size,
1103 * and the min Tx FIFO size is less than the current Rx FIFO
1104 * allocation, take space away from current Rx allocation */
1105 if (tx_space < min_tx_space &&
1106 ((min_tx_space - tx_space) < pba)) {
1107 pba = pba - (min_tx_space - tx_space);
1108
1109 /* if short on rx space, rx wins and must trump tx
1110 * adjustment */
1111 if (pba < min_rx_space)
1112 pba = min_rx_space;
1113 }
2d064c06 1114 wr32(E1000_PBA, pba);
9d5c8243 1115 }
9d5c8243
AK		 1116
1117 /* flow control settings */
1118 /* The high water mark must be low enough to fit one full frame
1119 * (or the size used for early receive) above it in the Rx FIFO.
1120 * Set it to the lower of:
1121 * - 90% of the Rx FIFO size, or
1122 * - the full Rx FIFO size minus one full frame */
1123 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1124 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1125
2d064c06
AD		 1126 if (mac->type < e1000_82576) {
1127 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
1128 fc->low_water = fc->high_water - 8;
1129 } else {
1130 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1131 fc->low_water = fc->high_water - 16;
1132 }
9d5c8243
AK		 1133 fc->pause_time = 0xFFFF;
1134 fc->send_xon = 1;
0cce119a 1135 fc->current_mode = fc->requested_mode;
9d5c8243 1136
4ae196df
AD		 1137 /* disable receive for all VFs and wait one second */
1138 if (adapter->vfs_allocated_count) {
1139 int i;
1140 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
1141 adapter->vf_data[i].clear_to_send = false;
1142
1143 /* ping all the active vfs to let them know we are going down */
1144 igb_ping_all_vfs(adapter);
1145
1146 /* disable transmits and receives */
1147 wr32(E1000_VFRE, 0);
1148 wr32(E1000_VFTE, 0);
1149 }
1150
9d5c8243
AK		 1151 /* Allow time for pending master requests to run */
1152 adapter->hw.mac.ops.reset_hw(&adapter->hw);
1153 wr32(E1000_WUC, 0);
1154
1155 if (adapter->hw.mac.ops.init_hw(&adapter->hw))
1156 dev_err(&adapter->pdev->dev, "Hardware Error\n");
1157
1158 igb_update_mng_vlan(adapter);
1159
1160 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1161 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1162
1163 igb_reset_adaptive(&adapter->hw);
f5f4cf08 1164 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 1165}
1166
2e5c6922
SH		 1167static const struct net_device_ops igb_netdev_ops = {
1168 .ndo_open = igb_open,
1169 .ndo_stop = igb_close,
00829823 1170 .ndo_start_xmit = igb_xmit_frame_adv,
2e5c6922 1171 .ndo_get_stats = igb_get_stats,
ff41f8dc
AD		 1172 .ndo_set_rx_mode = igb_set_rx_mode,
1173 .ndo_set_multicast_list = igb_set_rx_mode,
2e5c6922
SH		 1174 .ndo_set_mac_address = igb_set_mac,
1175 .ndo_change_mtu = igb_change_mtu,
1176 .ndo_do_ioctl = igb_ioctl,
1177 .ndo_tx_timeout = igb_tx_timeout,
1178 .ndo_validate_addr = eth_validate_addr,
1179 .ndo_vlan_rx_register = igb_vlan_rx_register,
1180 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1181 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
1182#ifdef CONFIG_NET_POLL_CONTROLLER
1183 .ndo_poll_controller = igb_netpoll,
1184#endif
1185};
1186
9d5c8243
AK		 1187/**
1188 * igb_probe - Device Initialization Routine
1189 * @pdev: PCI device information struct
1190 * @ent: entry in igb_pci_tbl
1191 *
1192 * Returns 0 on success, negative on failure
1193 *
1194 * igb_probe initializes an adapter identified by a pci_dev structure.
1195 * The OS initialization, configuring of the adapter private structure,
1196 * and a hardware reset occur.
1197 **/
1198static int __devinit igb_probe(struct pci_dev *pdev,
1199 const struct pci_device_id *ent)
1200{
1201 struct net_device *netdev;
1202 struct igb_adapter *adapter;
1203 struct e1000_hw *hw;
1204 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1205 unsigned long mmio_start, mmio_len;
2d6a5e95 1206 int err, pci_using_dac;
682337fe 1207 u16 eeprom_data = 0;
9d5c8243
AK		 1208 u16 eeprom_apme_mask = IGB_EEPROM_APME;
1209 u32 part_num;
1210
aed5dec3 1211 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 1212 if (err)
1213 return err;
1214
1215 pci_using_dac = 0;
6a35528a 1216 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
9d5c8243 1217 if (!err) {
6a35528a 1218 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
9d5c8243
AK		 1219 if (!err)
1220 pci_using_dac = 1;
1221 } else {
284901a9 1222 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
9d5c8243 1223 if (err) {
284901a9 1224 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
9d5c8243
AK		 1225 if (err) {
1226 dev_err(&pdev->dev, "No usable DMA "
1227 "configuration, aborting\n");
1228 goto err_dma;
1229 }
1230 }
1231 }
1232
aed5dec3
AD		 1233 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1234 IORESOURCE_MEM),
1235 igb_driver_name);
9d5c8243
AK		 1236 if (err)
1237 goto err_pci_reg;
1238
19d5afd4 1239 pci_enable_pcie_error_reporting(pdev);
40a914fa 1240
9d5c8243 1241 pci_set_master(pdev);
c682fc23 1242 pci_save_state(pdev);
9d5c8243
AK		 1243
1244 err = -ENOMEM;
1bfaf07b
AD		 1245 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1246 IGB_ABS_MAX_TX_QUEUES);
9d5c8243
AK		 1247 if (!netdev)
1248 goto err_alloc_etherdev;
1249
1250 SET_NETDEV_DEV(netdev, &pdev->dev);
1251
1252 pci_set_drvdata(pdev, netdev);
1253 adapter = netdev_priv(netdev);
1254 adapter->netdev = netdev;
1255 adapter->pdev = pdev;
1256 hw = &adapter->hw;
1257 hw->back = adapter;
1258 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
1259
1260 mmio_start = pci_resource_start(pdev, 0);
1261 mmio_len = pci_resource_len(pdev, 0);
1262
1263 err = -EIO;
28b0759c
AD		 1264 hw->hw_addr = ioremap(mmio_start, mmio_len);
1265 if (!hw->hw_addr)
9d5c8243
AK		 1266 goto err_ioremap;
1267
2e5c6922 1268 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 1269 igb_set_ethtool_ops(netdev);
9d5c8243 1270 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 1271
1272 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1273
1274 netdev->mem_start = mmio_start;
1275 netdev->mem_end = mmio_start + mmio_len;
1276
9d5c8243
AK		 1277 /* PCI config space info */
1278 hw->vendor_id = pdev->vendor;
1279 hw->device_id = pdev->device;
1280 hw->revision_id = pdev->revision;
1281 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1282 hw->subsystem_device_id = pdev->subsystem_device;
1283
1284 /* setup the private structure */
1285 hw->back = adapter;
1286 /* Copy the default MAC, PHY and NVM function pointers */
1287 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1288 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1289 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1290 /* Initialize skew-specific constants */
1291 err = ei->get_invariants(hw);
1292 if (err)
450c87c8 1293 goto err_sw_init;
9d5c8243 1294
2a3abf6d
AD		 1295#ifdef CONFIG_PCI_IOV
1296 /* since iov functionality isn't critical to base device function we
1297 * can accept failure. If it fails we don't allow iov to be enabled */
1298 if (hw->mac.type == e1000_82576) {
1299 /* 82576 supports a maximum of 7 VFs in addition to the PF */
1300 unsigned int num_vfs = (max_vfs > 7) ? 7 : max_vfs;
1301 int i;
1302 unsigned char mac_addr[ETH_ALEN];
1303
9ca046d5 1304 if (num_vfs) {
2a3abf6d
AD		 1305 adapter->vf_data = kcalloc(num_vfs,
1306 sizeof(struct vf_data_storage),
1307 GFP_KERNEL);
9ca046d5
AD		 1308 if (!adapter->vf_data) {
1309 dev_err(&pdev->dev,
1310 "Could not allocate VF private data - "
1311 "IOV enable failed\n");
2a3abf6d 1312 } else {
9ca046d5
AD		 1313 err = pci_enable_sriov(pdev, num_vfs);
1314 if (!err) {
1315 adapter->vfs_allocated_count = num_vfs;
1316 dev_info(&pdev->dev,
1317 "%d vfs allocated\n",
1318 num_vfs);
1319 for (i = 0;
1320 i < adapter->vfs_allocated_count;
1321 i++) {
1322 random_ether_addr(mac_addr);
1323 igb_set_vf_mac(adapter, i,
1324 mac_addr);
1325 }
1326 } else {
1327 kfree(adapter->vf_data);
1328 adapter->vf_data = NULL;
1329 }
2a3abf6d
AD		 1330 }
1331 }
1332 }
1333
1334#endif
450c87c8 1335 /* setup the private structure */
9d5c8243
AK		 1336 err = igb_sw_init(adapter);
1337 if (err)
1338 goto err_sw_init;
1339
1340 igb_get_bus_info_pcie(hw);
1341
7dfc16fa
AD		 1342 /* set flags */
1343 switch (hw->mac.type) {
7dfc16fa 1344 case e1000_82575:
7dfc16fa
AD		 1345 adapter->flags |= IGB_FLAG_NEED_CTX_IDX;
1346 break;
bbd98fe4 1347 case e1000_82576:
7dfc16fa
AD		 1348 default:
1349 break;
1350 }
1351
9d5c8243
AK		 1352 hw->phy.autoneg_wait_to_complete = false;
1353 hw->mac.adaptive_ifs = true;
1354
1355 /* Copper options */
1356 if (hw->phy.media_type == e1000_media_type_copper) {
1357 hw->phy.mdix = AUTO_ALL_MODES;
1358 hw->phy.disable_polarity_correction = false;
1359 hw->phy.ms_type = e1000_ms_hw_default;
1360 }
1361
1362 if (igb_check_reset_block(hw))
1363 dev_info(&pdev->dev,
1364 "PHY reset is blocked due to SOL/IDER session.\n");
1365
1366 netdev->features = NETIF_F_SG |
7d8eb29e 1367 NETIF_F_IP_CSUM |
9d5c8243
AK		 1368 NETIF_F_HW_VLAN_TX |
1369 NETIF_F_HW_VLAN_RX |
1370 NETIF_F_HW_VLAN_FILTER;
1371
7d8eb29e 1372 netdev->features |= NETIF_F_IPV6_CSUM;
9d5c8243 1373 netdev->features |= NETIF_F_TSO;
9d5c8243 1374 netdev->features |= NETIF_F_TSO6;
48f29ffc 1375
5c0999b7 1376 netdev->features |= NETIF_F_GRO;
d3352520 1377
48f29ffc
JK		 1378 netdev->vlan_features |= NETIF_F_TSO;
1379 netdev->vlan_features |= NETIF_F_TSO6;
7d8eb29e 1380 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 1381 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
48f29ffc
JK		 1382 netdev->vlan_features |= NETIF_F_SG;
1383
9d5c8243
AK		 1384 if (pci_using_dac)
1385 netdev->features |= NETIF_F_HIGHDMA;
1386
b9473560
JB		 1387 if (adapter->hw.mac.type == e1000_82576)
1388 netdev->features |= NETIF_F_SCTP_CSUM;
1389
9d5c8243
AK		 1390 adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1391
1392 /* before reading the NVM, reset the controller to put the device in a
1393 * known good starting state */
1394 hw->mac.ops.reset_hw(hw);
1395
1396 /* make sure the NVM is good */
1397 if (igb_validate_nvm_checksum(hw) < 0) {
1398 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1399 err = -EIO;
1400 goto err_eeprom;
1401 }
1402
1403 /* copy the MAC address out of the NVM */
1404 if (hw->mac.ops.read_mac_addr(hw))
1405 dev_err(&pdev->dev, "NVM Read Error\n");
1406
1407 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1408 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1409
1410 if (!is_valid_ether_addr(netdev->perm_addr)) {
1411 dev_err(&pdev->dev, "Invalid MAC Address\n");
1412 err = -EIO;
1413 goto err_eeprom;
1414 }
1415
0e340485
AD		 1416 setup_timer(&adapter->watchdog_timer, &igb_watchdog,
1417 (unsigned long) adapter);
1418 setup_timer(&adapter->phy_info_timer, &igb_update_phy_info,
1419 (unsigned long) adapter);
9d5c8243
AK		 1420
1421 INIT_WORK(&adapter->reset_task, igb_reset_task);
1422 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1423
450c87c8 1424 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 1425 adapter->fc_autoneg = true;
1426 hw->mac.autoneg = true;
1427 hw->phy.autoneg_advertised = 0x2f;
1428
0cce119a
AD		 1429 hw->fc.requested_mode = e1000_fc_default;
1430 hw->fc.current_mode = e1000_fc_default;
9d5c8243 1431
cbd347ad 1432 adapter->itr_setting = IGB_DEFAULT_ITR;
9d5c8243
AK		 1433 adapter->itr = IGB_START_ITR;
1434
1435 igb_validate_mdi_setting(hw);
1436
9d5c8243
AK		 1437 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1438 * enable the ACPI Magic Packet filter
1439 */
1440
a2cf8b6c 1441 if (hw->bus.func == 0)
312c75ae 1442 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
a2cf8b6c
AD		 1443 else if (hw->bus.func == 1)
1444 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243
AK		 1445
1446 if (eeprom_data & eeprom_apme_mask)
1447 adapter->eeprom_wol |= E1000_WUFC_MAG;
1448
1449 /* now that we have the eeprom settings, apply the special cases where
1450 * the eeprom may be wrong or the board simply won't support wake on
1451 * lan on a particular port */
1452 switch (pdev->device) {
1453 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1454 adapter->eeprom_wol = 0;
1455 break;
1456 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 1457 case E1000_DEV_ID_82576_FIBER:
1458 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 1459 /* Wake events only supported on port A for dual fiber
1460 * regardless of eeprom setting */
1461 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1462 adapter->eeprom_wol = 0;
1463 break;
c8ea5ea9
AD		 1464 case E1000_DEV_ID_82576_QUAD_COPPER:
1465 /* if quad port adapter, disable WoL on all but port A */
1466 if (global_quad_port_a != 0)
1467 adapter->eeprom_wol = 0;
1468 else
1469 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
1470 /* Reset for multiple quad port adapters */
1471 if (++global_quad_port_a == 4)
1472 global_quad_port_a = 0;
1473 break;
9d5c8243
AK		 1474 }
1475
1476 /* initialize the wol settings based on the eeprom settings */
1477 adapter->wol = adapter->eeprom_wol;
e1b86d84 1478 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
9d5c8243
AK		 1479
1480 /* reset the hardware with the new settings */
1481 igb_reset(adapter);
1482
1483 /* let the f/w know that the h/w is now under the control of the
1484 * driver. */
1485 igb_get_hw_control(adapter);
1486
9d5c8243
AK		 1487 strcpy(netdev->name, "eth%d");
1488 err = register_netdev(netdev);
1489 if (err)
1490 goto err_register;
1491
b168dfc5
JB		 1492 /* carrier off reporting is important to ethtool even BEFORE open */
1493 netif_carrier_off(netdev);
1494
421e02f0 1495#ifdef CONFIG_IGB_DCA
bbd98fe4 1496 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 1497 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 1498 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 1499 igb_setup_dca(adapter);
1500 }
1501#endif
1502
38c845c7
PO		 1503 /*
1504 * Initialize hardware timer: we keep it running just in case
1505 * that some program needs it later on.
1506 */
1507 memset(&adapter->cycles, 0, sizeof(adapter->cycles));
1508 adapter->cycles.read = igb_read_clock;
1509 adapter->cycles.mask = CLOCKSOURCE_MASK(64);
1510 adapter->cycles.mult = 1;
1511 adapter->cycles.shift = IGB_TSYNC_SHIFT;
1512 wr32(E1000_TIMINCA,
1513 (1<<24) |
1514 IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS * IGB_TSYNC_SCALE);
1515#if 0
1516 /*
1517 * Avoid rollover while we initialize by resetting the time counter.
1518 */
1519 wr32(E1000_SYSTIML, 0x00000000);
1520 wr32(E1000_SYSTIMH, 0x00000000);
1521#else
1522 /*
1523 * Set registers so that rollover occurs soon to test this.
1524 */
1525 wr32(E1000_SYSTIML, 0x00000000);
1526 wr32(E1000_SYSTIMH, 0xFF800000);
1527#endif
1528 wrfl();
1529 timecounter_init(&adapter->clock,
1530 &adapter->cycles,
1531 ktime_to_ns(ktime_get_real()));
1532
33af6bcc
PO		 1533 /*
1534 * Synchronize our NIC clock against system wall clock. NIC
1535 * time stamp reading requires ~3us per sample, each sample
1536 * was pretty stable even under load => only require 10
1537 * samples for each offset comparison.
1538 */
1539 memset(&adapter->compare, 0, sizeof(adapter->compare));
1540 adapter->compare.source = &adapter->clock;
1541 adapter->compare.target = ktime_get_real;
1542 adapter->compare.num_samples = 10;
1543 timecompare_update(&adapter->compare, 0);
1544
38c845c7
PO		 1545#ifdef DEBUG
1546 {
1547 char buffer[160];
1548 printk(KERN_DEBUG
1549 "igb: %s: hw %p initialized timer\n",
1550 igb_get_time_str(adapter, buffer),
1551 &adapter->hw);
1552 }
1553#endif
1554
9d5c8243
AK		 1555 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1556 /* print bus type/speed/width info */
7c510e4b 1557 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
9d5c8243
AK		 1558 netdev->name,
1559 ((hw->bus.speed == e1000_bus_speed_2500)
1560 ? "2.5Gb/s" : "unknown"),
59c3de89
AD		 1561 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
1562 (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :
1563 (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" :
1564 "unknown"),
7c510e4b 1565 netdev->dev_addr);
9d5c8243
AK		 1566
1567 igb_read_part_num(hw, &part_num);
1568 dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1569 (part_num >> 8), (part_num & 0xff));
1570
1571 dev_info(&pdev->dev,
1572 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1573 adapter->msix_entries ? "MSI-X" :
7dfc16fa 1574 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243
AK		 1575 adapter->num_rx_queues, adapter->num_tx_queues);
1576
9d5c8243
AK		 1577 return 0;
1578
1579err_register:
1580 igb_release_hw_control(adapter);
1581err_eeprom:
1582 if (!igb_check_reset_block(hw))
f5f4cf08 1583 igb_reset_phy(hw);
9d5c8243
AK		 1584
1585 if (hw->flash_address)
1586 iounmap(hw->flash_address);
1587
a88f10ec 1588 igb_free_queues(adapter);
9d5c8243 1589err_sw_init:
9d5c8243
AK		 1590 iounmap(hw->hw_addr);
1591err_ioremap:
1592 free_netdev(netdev);
1593err_alloc_etherdev:
aed5dec3
AD		 1594 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1595 IORESOURCE_MEM));
9d5c8243
AK		 1596err_pci_reg:
1597err_dma:
1598 pci_disable_device(pdev);
1599 return err;
1600}
1601
1602/**
1603 * igb_remove - Device Removal Routine
1604 * @pdev: PCI device information struct
1605 *
1606 * igb_remove is called by the PCI subsystem to alert the driver
1607 * that it should release a PCI device. The could be caused by a
1608 * Hot-Plug event, or because the driver is going to be removed from
1609 * memory.
1610 **/
1611static void __devexit igb_remove(struct pci_dev *pdev)
1612{
1613 struct net_device *netdev = pci_get_drvdata(pdev);
1614 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 1615 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1616
1617 /* flush_scheduled work may reschedule our watchdog task, so
1618 * explicitly disable watchdog tasks from being rescheduled */
1619 set_bit(__IGB_DOWN, &adapter->state);
1620 del_timer_sync(&adapter->watchdog_timer);
1621 del_timer_sync(&adapter->phy_info_timer);
1622
1623 flush_scheduled_work();
1624
421e02f0 1625#ifdef CONFIG_IGB_DCA
7dfc16fa 1626 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 1627 dev_info(&pdev->dev, "DCA disabled\n");
1628 dca_remove_requester(&pdev->dev);
7dfc16fa 1629 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 1630 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 1631 }
1632#endif
1633
9d5c8243
AK		 1634 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1635 * would have already happened in close and is redundant. */
1636 igb_release_hw_control(adapter);
1637
1638 unregister_netdev(netdev);
1639
f5f4cf08
AD		 1640 if (!igb_check_reset_block(&adapter->hw))
1641 igb_reset_phy(&adapter->hw);
9d5c8243 1642
9d5c8243
AK		 1643 igb_reset_interrupt_capability(adapter);
1644
a88f10ec 1645 igb_free_queues(adapter);
9d5c8243 1646
37680117
AD		 1647#ifdef CONFIG_PCI_IOV
1648 /* reclaim resources allocated to VFs */
1649 if (adapter->vf_data) {
1650 /* disable iov and allow time for transactions to clear */
1651 pci_disable_sriov(pdev);
1652 msleep(500);
1653
1654 kfree(adapter->vf_data);
1655 adapter->vf_data = NULL;
1656 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1657 msleep(100);
1658 dev_info(&pdev->dev, "IOV Disabled\n");
1659 }
1660#endif
28b0759c
AD		 1661 iounmap(hw->hw_addr);
1662 if (hw->flash_address)
1663 iounmap(hw->flash_address);
aed5dec3
AD		 1664 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1665 IORESOURCE_MEM));
9d5c8243
AK		 1666
1667 free_netdev(netdev);
1668
19d5afd4 1669 pci_disable_pcie_error_reporting(pdev);
40a914fa 1670
9d5c8243
AK		 1671 pci_disable_device(pdev);
1672}
1673
1674/**
1675 * igb_sw_init - Initialize general software structures (struct igb_adapter)
1676 * @adapter: board private structure to initialize
1677 *
1678 * igb_sw_init initializes the Adapter private data structure.
1679 * Fields are initialized based on PCI device information and
1680 * OS network device settings (MTU size).
1681 **/
1682static int __devinit igb_sw_init(struct igb_adapter *adapter)
1683{
1684 struct e1000_hw *hw = &adapter->hw;
1685 struct net_device *netdev = adapter->netdev;
1686 struct pci_dev *pdev = adapter->pdev;
1687
1688 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1689
68fd9910
AD		 1690 adapter->tx_ring_count = IGB_DEFAULT_TXD;
1691 adapter->rx_ring_count = IGB_DEFAULT_RXD;
9d5c8243
AK		 1692 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1693 adapter->rx_ps_hdr_size = 0; /* disable packet split */
1694 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1695 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1696
661086df
PWJ		 1697 /* This call may decrease the number of queues depending on
1698 * interrupt mode. */
9d5c8243
AK		 1699 igb_set_interrupt_capability(adapter);
1700
1701 if (igb_alloc_queues(adapter)) {
1702 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1703 return -ENOMEM;
1704 }
1705
1706 /* Explicitly disable IRQ since the NIC can be in any state. */
1707 igb_irq_disable(adapter);
1708
1709 set_bit(__IGB_DOWN, &adapter->state);
1710 return 0;
1711}
1712
1713/**
1714 * igb_open - Called when a network interface is made active
1715 * @netdev: network interface device structure
1716 *
1717 * Returns 0 on success, negative value on failure
1718 *
1719 * The open entry point is called when a network interface is made
1720 * active by the system (IFF_UP). At this point all resources needed
1721 * for transmit and receive operations are allocated, the interrupt
1722 * handler is registered with the OS, the watchdog timer is started,
1723 * and the stack is notified that the interface is ready.
1724 **/
1725static int igb_open(struct net_device *netdev)
1726{
1727 struct igb_adapter *adapter = netdev_priv(netdev);
1728 struct e1000_hw *hw = &adapter->hw;
1729 int err;
1730 int i;
1731
1732 /* disallow open during test */
1733 if (test_bit(__IGB_TESTING, &adapter->state))
1734 return -EBUSY;
1735
b168dfc5
JB		 1736 netif_carrier_off(netdev);
1737
9d5c8243
AK		 1738 /* allocate transmit descriptors */
1739 err = igb_setup_all_tx_resources(adapter);
1740 if (err)
1741 goto err_setup_tx;
1742
1743 /* allocate receive descriptors */
1744 err = igb_setup_all_rx_resources(adapter);
1745 if (err)
1746 goto err_setup_rx;
1747
1748 /* e1000_power_up_phy(adapter); */
1749
1750 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1751 if ((adapter->hw.mng_cookie.status &
1752 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1753 igb_update_mng_vlan(adapter);
1754
1755 /* before we allocate an interrupt, we must be ready to handle it.
1756 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1757 * as soon as we call pci_request_irq, so we have to setup our
1758 * clean_rx handler before we do so. */
1759 igb_configure(adapter);
1760
4ae196df 1761 igb_vmm_control(adapter);
e1739522
AD		 1762 igb_set_vmolr(hw, adapter->vfs_allocated_count);
1763
9d5c8243
AK		 1764 err = igb_request_irq(adapter);
1765 if (err)
1766 goto err_req_irq;
1767
1768 /* From here on the code is the same as igb_up() */
1769 clear_bit(__IGB_DOWN, &adapter->state);
1770
844290e5
PW		 1771 for (i = 0; i < adapter->num_rx_queues; i++)
1772 napi_enable(&adapter->rx_ring[i].napi);
9d5c8243
AK		 1773
1774 /* Clear any pending interrupts. */
1775 rd32(E1000_ICR);
844290e5
PW		 1776
1777 igb_irq_enable(adapter);
1778
d55b53ff
JK		 1779 netif_tx_start_all_queues(netdev);
1780
9d5c8243
AK		 1781 /* Fire a link status change interrupt to start the watchdog. */
1782 wr32(E1000_ICS, E1000_ICS_LSC);
1783
1784 return 0;
1785
1786err_req_irq:
1787 igb_release_hw_control(adapter);
1788 /* e1000_power_down_phy(adapter); */
1789 igb_free_all_rx_resources(adapter);
1790err_setup_rx:
1791 igb_free_all_tx_resources(adapter);
1792err_setup_tx:
1793 igb_reset(adapter);
1794
1795 return err;
1796}
1797
1798/**
1799 * igb_close - Disables a network interface
1800 * @netdev: network interface device structure
1801 *
1802 * Returns 0, this is not allowed to fail
1803 *
1804 * The close entry point is called when an interface is de-activated
1805 * by the OS. The hardware is still under the driver's control, but
1806 * needs to be disabled. A global MAC reset is issued to stop the
1807 * hardware, and all transmit and receive resources are freed.
1808 **/
1809static int igb_close(struct net_device *netdev)
1810{
1811 struct igb_adapter *adapter = netdev_priv(netdev);
1812
1813 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1814 igb_down(adapter);
1815
1816 igb_free_irq(adapter);
1817
1818 igb_free_all_tx_resources(adapter);
1819 igb_free_all_rx_resources(adapter);
1820
1821 /* kill manageability vlan ID if supported, but not if a vlan with
1822 * the same ID is registered on the host OS (let 8021q kill it) */
1823 if ((adapter->hw.mng_cookie.status &
1824 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1825 !(adapter->vlgrp &&
1826 vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1827 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1828
1829 return 0;
1830}
1831
1832/**
1833 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
1834 * @adapter: board private structure
1835 * @tx_ring: tx descriptor ring (for a specific queue) to setup
1836 *
1837 * Return 0 on success, negative on failure
1838 **/
9d5c8243
AK		 1839int igb_setup_tx_resources(struct igb_adapter *adapter,
1840 struct igb_ring *tx_ring)
1841{
1842 struct pci_dev *pdev = adapter->pdev;
1843 int size;
1844
1845 size = sizeof(struct igb_buffer) * tx_ring->count;
1846 tx_ring->buffer_info = vmalloc(size);
1847 if (!tx_ring->buffer_info)
1848 goto err;
1849 memset(tx_ring->buffer_info, 0, size);
1850
1851 /* round up to nearest 4K */
85e8d004 1852 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 1853 tx_ring->size = ALIGN(tx_ring->size, 4096);
1854
1855 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1856 &tx_ring->dma);
1857
1858 if (!tx_ring->desc)
1859 goto err;
1860
1861 tx_ring->adapter = adapter;
1862 tx_ring->next_to_use = 0;
1863 tx_ring->next_to_clean = 0;
9d5c8243
AK		 1864 return 0;
1865
1866err:
1867 vfree(tx_ring->buffer_info);
1868 dev_err(&adapter->pdev->dev,
1869 "Unable to allocate memory for the transmit descriptor ring\n");
1870 return -ENOMEM;
1871}
1872
1873/**
1874 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1875 * (Descriptors) for all queues
1876 * @adapter: board private structure
1877 *
1878 * Return 0 on success, negative on failure
1879 **/
1880static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1881{
1882 int i, err = 0;
661086df 1883 int r_idx;
9d5c8243
AK		 1884
1885 for (i = 0; i < adapter->num_tx_queues; i++) {
1886 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1887 if (err) {
1888 dev_err(&adapter->pdev->dev,
1889 "Allocation for Tx Queue %u failed\n", i);
1890 for (i--; i >= 0; i--)
3b644cf6 1891 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 1892 break;
1893 }
1894 }
1895
661086df
PWJ		 1896 for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
1897 r_idx = i % adapter->num_tx_queues;
1898 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
eebbbdba 1899 }
9d5c8243
AK		 1900 return err;
1901}
1902
1903/**
1904 * igb_configure_tx - Configure transmit Unit after Reset
1905 * @adapter: board private structure
1906 *
1907 * Configure the Tx unit of the MAC after a reset.
1908 **/
1909static void igb_configure_tx(struct igb_adapter *adapter)
1910{
0e014cb1 1911 u64 tdba;
9d5c8243
AK		 1912 struct e1000_hw *hw = &adapter->hw;
1913 u32 tctl;
1914 u32 txdctl, txctrl;
26bc19ec 1915 int i, j;
9d5c8243
AK		 1916
1917 for (i = 0; i < adapter->num_tx_queues; i++) {
73cd78f1 1918 struct igb_ring *ring = &adapter->tx_ring[i];
26bc19ec
AD		 1919 j = ring->reg_idx;
1920 wr32(E1000_TDLEN(j),
85e8d004 1921 ring->count * sizeof(union e1000_adv_tx_desc));
9d5c8243 1922 tdba = ring->dma;
26bc19ec 1923 wr32(E1000_TDBAL(j),
73cd78f1 1924 tdba & 0x00000000ffffffffULL);
26bc19ec 1925 wr32(E1000_TDBAH(j), tdba >> 32);
9d5c8243 1926
26bc19ec
AD		 1927 ring->head = E1000_TDH(j);
1928 ring->tail = E1000_TDT(j);
9d5c8243
AK		 1929 writel(0, hw->hw_addr + ring->tail);
1930 writel(0, hw->hw_addr + ring->head);
26bc19ec 1931 txdctl = rd32(E1000_TXDCTL(j));
9d5c8243 1932 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
26bc19ec 1933 wr32(E1000_TXDCTL(j), txdctl);
9d5c8243
AK		 1934
1935 /* Turn off Relaxed Ordering on head write-backs. The
1936 * writebacks MUST be delivered in order or it will
1937 * completely screw up our bookeeping.
1938 */
26bc19ec 1939 txctrl = rd32(E1000_DCA_TXCTRL(j));
9d5c8243 1940 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
26bc19ec 1941 wr32(E1000_DCA_TXCTRL(j), txctrl);
9d5c8243
AK		 1942 }
1943
e1739522
AD		 1944 /* disable queue 0 to prevent tail bump w/o re-configuration */
1945 if (adapter->vfs_allocated_count)
1946 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 1947
1948 /* Program the Transmit Control Register */
9d5c8243
AK		 1949 tctl = rd32(E1000_TCTL);
1950 tctl &= ~E1000_TCTL_CT;
1951 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1952 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1953
1954 igb_config_collision_dist(hw);
1955
1956 /* Setup Transmit Descriptor Settings for eop descriptor */
1957 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
1958
1959 /* Enable transmits */
1960 tctl |= E1000_TCTL_EN;
1961
1962 wr32(E1000_TCTL, tctl);
1963}
1964
1965/**
1966 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
1967 * @adapter: board private structure
1968 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1969 *
1970 * Returns 0 on success, negative on failure
1971 **/
9d5c8243
AK		 1972int igb_setup_rx_resources(struct igb_adapter *adapter,
1973 struct igb_ring *rx_ring)
1974{
1975 struct pci_dev *pdev = adapter->pdev;
1976 int size, desc_len;
1977
1978 size = sizeof(struct igb_buffer) * rx_ring->count;
1979 rx_ring->buffer_info = vmalloc(size);
1980 if (!rx_ring->buffer_info)
1981 goto err;
1982 memset(rx_ring->buffer_info, 0, size);
1983
1984 desc_len = sizeof(union e1000_adv_rx_desc);
1985
1986 /* Round up to nearest 4K */
1987 rx_ring->size = rx_ring->count * desc_len;
1988 rx_ring->size = ALIGN(rx_ring->size, 4096);
1989
1990 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1991 &rx_ring->dma);
1992
1993 if (!rx_ring->desc)
1994 goto err;
1995
1996 rx_ring->next_to_clean = 0;
1997 rx_ring->next_to_use = 0;
9d5c8243
AK		 1998
1999 rx_ring->adapter = adapter;
9d5c8243
AK		 2000
2001 return 0;
2002
2003err:
2004 vfree(rx_ring->buffer_info);
2005 dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
2006 "the receive descriptor ring\n");
2007 return -ENOMEM;
2008}
2009
2010/**
2011 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
2012 * (Descriptors) for all queues
2013 * @adapter: board private structure
2014 *
2015 * Return 0 on success, negative on failure
2016 **/
2017static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
2018{
2019 int i, err = 0;
2020
2021 for (i = 0; i < adapter->num_rx_queues; i++) {
2022 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
2023 if (err) {
2024 dev_err(&adapter->pdev->dev,
2025 "Allocation for Rx Queue %u failed\n", i);
2026 for (i--; i >= 0; i--)
3b644cf6 2027 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 2028 break;
2029 }
2030 }
2031
2032 return err;
2033}
2034
2035/**
2036 * igb_setup_rctl - configure the receive control registers
2037 * @adapter: Board private structure
2038 **/
2039static void igb_setup_rctl(struct igb_adapter *adapter)
2040{
2041 struct e1000_hw *hw = &adapter->hw;
2042 u32 rctl;
2043 u32 srrctl = 0;
77a22941 2044 int i;
9d5c8243
AK		 2045
2046 rctl = rd32(E1000_RCTL);
2047
2048 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 2049 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 2050
69d728ba 2051 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 2052 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 2053
87cb7e8c
AK		 2054 /*
2055 * enable stripping of CRC. It's unlikely this will break BMC
2056 * redirection as it did with e1000. Newer features require
2057 * that the HW strips the CRC.
73cd78f1 2058 */
87cb7e8c 2059 rctl |= E1000_RCTL_SECRC;
9d5c8243 2060
9b07f3d3 2061 /*
ec54d7d6 2062 * disable store bad packets and clear size bits.
9b07f3d3 2063 */
ec54d7d6 2064 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 2065
ec54d7d6 2066 /* enable LPE when to prevent packets larger than max_frame_size */
9b07f3d3 2067 rctl |= E1000_RCTL_LPE;
b4557be2
AD		 2068
2069 /* Setup buffer sizes */
2070 switch (adapter->rx_buffer_len) {
2071 case IGB_RXBUFFER_256:
2072 rctl |= E1000_RCTL_SZ_256;
2073 break;
2074 case IGB_RXBUFFER_512:
2075 rctl |= E1000_RCTL_SZ_512;
2076 break;
2077 default:
2078 srrctl = ALIGN(adapter->rx_buffer_len, 1024)
2079 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2080 break;
9d5c8243
AK		 2081 }
2082
2083 /* 82575 and greater support packet-split where the protocol
2084 * header is placed in skb->data and the packet data is
2085 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
2086 * In the case of a non-split, skb->data is linearly filled,
2087 * followed by the page buffers. Therefore, skb->data is
2088 * sized to hold the largest protocol header.
2089 */
2090 /* allocations using alloc_page take too long for regular MTU
2091 * so only enable packet split for jumbo frames */
ec54d7d6 2092 if (adapter->netdev->mtu > ETH_DATA_LEN) {
9d5c8243 2093 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
bf36c1a0 2094 srrctl |= adapter->rx_ps_hdr_size <<
9d5c8243 2095 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
9d5c8243
AK		 2096 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2097 } else {
2098 adapter->rx_ps_hdr_size = 0;
2099 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2100 }
2101
e1739522
AD		 2102 /* Attention!!! For SR-IOV PF driver operations you must enable
2103 * queue drop for all VF and PF queues to prevent head of line blocking
2104 * if an un-trusted VF does not provide descriptors to hardware.
2105 */
2106 if (adapter->vfs_allocated_count) {
2107 u32 vmolr;
2108
e1739522
AD		 2109 /* set all queue drop enable bits */
2110 wr32(E1000_QDE, ALL_QUEUES);
2111 srrctl |= E1000_SRRCTL_DROP_EN;
2112
2113 /* disable queue 0 to prevent tail write w/o re-config */
2114 wr32(E1000_RXDCTL(0), 0);
2115
77a22941 2116 vmolr = rd32(E1000_VMOLR(adapter->vfs_allocated_count));
e1739522
AD		 2117 if (rctl & E1000_RCTL_LPE)
2118 vmolr |= E1000_VMOLR_LPE;
77a22941 2119 if (adapter->num_rx_queues > 1)
e1739522 2120 vmolr |= E1000_VMOLR_RSSE;
77a22941 2121 wr32(E1000_VMOLR(adapter->vfs_allocated_count), vmolr);
e1739522
AD		 2122 }
2123
26bc19ec 2124 for (i = 0; i < adapter->num_rx_queues; i++) {
77a22941 2125 int j = adapter->rx_ring[i].reg_idx;
26bc19ec
AD		 2126 wr32(E1000_SRRCTL(j), srrctl);
2127 }
9d5c8243
AK		 2128
2129 wr32(E1000_RCTL, rctl);
2130}
2131
e1739522
AD		 2132/**
2133 * igb_rlpml_set - set maximum receive packet size
2134 * @adapter: board private structure
2135 *
2136 * Configure maximum receivable packet size.
2137 **/
2138static void igb_rlpml_set(struct igb_adapter *adapter)
2139{
2140 u32 max_frame_size = adapter->max_frame_size;
2141 struct e1000_hw *hw = &adapter->hw;
2142 u16 pf_id = adapter->vfs_allocated_count;
2143
2144 if (adapter->vlgrp)
2145 max_frame_size += VLAN_TAG_SIZE;
2146
2147 /* if vfs are enabled we set RLPML to the largest possible request
2148 * size and set the VMOLR RLPML to the size we need */
2149 if (pf_id) {
2150 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
2151 max_frame_size = MAX_STD_JUMBO_FRAME_SIZE + VLAN_TAG_SIZE;
2152 }
2153
2154 wr32(E1000_RLPML, max_frame_size);
2155}
2156
2157/**
2158 * igb_configure_vt_default_pool - Configure VT default pool
2159 * @adapter: board private structure
2160 *
2161 * Configure the default pool
2162 **/
2163static void igb_configure_vt_default_pool(struct igb_adapter *adapter)
2164{
2165 struct e1000_hw *hw = &adapter->hw;
2166 u16 pf_id = adapter->vfs_allocated_count;
2167 u32 vtctl;
2168
2169 /* not in sr-iov mode - do nothing */
2170 if (!pf_id)
2171 return;
2172
2173 vtctl = rd32(E1000_VT_CTL);
2174 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
2175 E1000_VT_CTL_DISABLE_DEF_POOL);
2176 vtctl |= pf_id << E1000_VT_CTL_DEFAULT_POOL_SHIFT;
2177 wr32(E1000_VT_CTL, vtctl);
2178}
2179
9d5c8243
AK		 2180/**
2181 * igb_configure_rx - Configure receive Unit after Reset
2182 * @adapter: board private structure
2183 *
2184 * Configure the Rx unit of the MAC after a reset.
2185 **/
2186static void igb_configure_rx(struct igb_adapter *adapter)
2187{
2188 u64 rdba;
2189 struct e1000_hw *hw = &adapter->hw;
2190 u32 rctl, rxcsum;
2191 u32 rxdctl;
9107584e 2192 int i;
9d5c8243
AK		 2193
2194 /* disable receives while setting up the descriptors */
2195 rctl = rd32(E1000_RCTL);
2196 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
2197 wrfl();
2198 mdelay(10);
2199
2200 if (adapter->itr_setting > 3)
6eb5a7f1 2201 wr32(E1000_ITR, adapter->itr);
9d5c8243
AK		 2202
2203 /* Setup the HW Rx Head and Tail Descriptor Pointers and
2204 * the Base and Length of the Rx Descriptor Ring */
2205 for (i = 0; i < adapter->num_rx_queues; i++) {
73cd78f1 2206 struct igb_ring *ring = &adapter->rx_ring[i];
9107584e 2207 int j = ring->reg_idx;
9d5c8243 2208 rdba = ring->dma;
26bc19ec 2209 wr32(E1000_RDBAL(j),
73cd78f1 2210 rdba & 0x00000000ffffffffULL);
26bc19ec
AD		 2211 wr32(E1000_RDBAH(j), rdba >> 32);
2212 wr32(E1000_RDLEN(j),
73cd78f1 2213 ring->count * sizeof(union e1000_adv_rx_desc));
9d5c8243 2214
26bc19ec
AD		 2215 ring->head = E1000_RDH(j);
2216 ring->tail = E1000_RDT(j);
9d5c8243
AK		 2217 writel(0, hw->hw_addr + ring->tail);
2218 writel(0, hw->hw_addr + ring->head);
2219
26bc19ec 2220 rxdctl = rd32(E1000_RXDCTL(j));
9d5c8243
AK		 2221 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2222 rxdctl &= 0xFFF00000;
2223 rxdctl |= IGB_RX_PTHRESH;
2224 rxdctl |= IGB_RX_HTHRESH << 8;
2225 rxdctl |= IGB_RX_WTHRESH << 16;
26bc19ec 2226 wr32(E1000_RXDCTL(j), rxdctl);
9d5c8243
AK		 2227 }
2228
2229 if (adapter->num_rx_queues > 1) {
2230 u32 random[10];
2231 u32 mrqc;
2232 u32 j, shift;
2233 union e1000_reta {
2234 u32 dword;
2235 u8 bytes[4];
2236 } reta;
2237
2238 get_random_bytes(&random[0], 40);
2239
2d064c06
AD		 2240 if (hw->mac.type >= e1000_82576)
2241 shift = 0;
2242 else
2243 shift = 6;
9d5c8243
AK		 2244 for (j = 0; j < (32 * 4); j++) {
2245 reta.bytes[j & 3] =
26bc19ec 2246 adapter->rx_ring[(j % adapter->num_rx_queues)].reg_idx << shift;
9d5c8243
AK		 2247 if ((j & 3) == 3)
2248 writel(reta.dword,
2249 hw->hw_addr + E1000_RETA(0) + (j & ~3));
2250 }
e1739522
AD		 2251 if (adapter->vfs_allocated_count)
2252 mrqc = E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
2253 else
2254 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
9d5c8243
AK		 2255
2256 /* Fill out hash function seeds */
2257 for (j = 0; j < 10; j++)
2258 array_wr32(E1000_RSSRK(0), j, random[j]);
2259
2260 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2261 E1000_MRQC_RSS_FIELD_IPV4_TCP);
2262 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2263 E1000_MRQC_RSS_FIELD_IPV6_TCP);
2264 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
2265 E1000_MRQC_RSS_FIELD_IPV6_UDP);
2266 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2267 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2268
9d5c8243 2269 wr32(E1000_MRQC, mrqc);
2844f797 2270 } else if (adapter->vfs_allocated_count) {
e1739522 2271 /* Enable multi-queue for sr-iov */
2844f797 2272 wr32(E1000_MRQC, E1000_MRQC_ENABLE_VMDQ);
9d5c8243
AK		 2273 }
2274
2844f797
AD		 2275 /* Enable Receive Checksum Offload for TCP and UDP */
2276 rxcsum = rd32(E1000_RXCSUM);
2277 /* Disable raw packet checksumming */
2278 rxcsum |= E1000_RXCSUM_PCSD;
7beb0146
AD		 2279
2280 if (adapter->hw.mac.type == e1000_82576)
b9473560
JB		 2281 /* Enable Receive Checksum Offload for SCTP */
2282 rxcsum |= E1000_RXCSUM_CRCOFL;
2283
7beb0146 2284 /* Don't need to set TUOFL or IPOFL, they default to 1 */
2844f797
AD		 2285 wr32(E1000_RXCSUM, rxcsum);
2286
e1739522
AD		 2287 /* Set the default pool for the PF's first queue */
2288 igb_configure_vt_default_pool(adapter);
2289
68d480c4
AD		 2290 /* set UTA to appropriate mode */
2291 igb_set_uta(adapter);
2292
26ad9178
AD		 2293 /* set the correct pool for the PF default MAC address in entry 0 */
2294 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
2295 adapter->vfs_allocated_count);
2296
e1739522 2297 igb_rlpml_set(adapter);
9d5c8243
AK		 2298
2299 /* Enable Receives */
2300 wr32(E1000_RCTL, rctl);
2301}
2302
2303/**
2304 * igb_free_tx_resources - Free Tx Resources per Queue
9d5c8243
AK		 2305 * @tx_ring: Tx descriptor ring for a specific queue
2306 *
2307 * Free all transmit software resources
2308 **/
68fd9910 2309void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 2310{
3b644cf6 2311 struct pci_dev *pdev = tx_ring->adapter->pdev;
9d5c8243 2312
3b644cf6 2313 igb_clean_tx_ring(tx_ring);
9d5c8243
AK		 2314
2315 vfree(tx_ring->buffer_info);
2316 tx_ring->buffer_info = NULL;
2317
2318 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
2319
2320 tx_ring->desc = NULL;
2321}
2322
2323/**
2324 * igb_free_all_tx_resources - Free Tx Resources for All Queues
2325 * @adapter: board private structure
2326 *
2327 * Free all transmit software resources
2328 **/
2329static void igb_free_all_tx_resources(struct igb_adapter *adapter)
2330{
2331 int i;
2332
2333 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2334 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 2335}
2336
2337static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
2338 struct igb_buffer *buffer_info)
2339{
65689fef 2340 buffer_info->dma = 0;
9d5c8243 2341 if (buffer_info->skb) {
65689fef
AD		 2342 skb_dma_unmap(&adapter->pdev->dev, buffer_info->skb,
2343 DMA_TO_DEVICE);
9d5c8243
AK		 2344 dev_kfree_skb_any(buffer_info->skb);
2345 buffer_info->skb = NULL;
2346 }
2347 buffer_info->time_stamp = 0;
2348 /* buffer_info must be completely set up in the transmit path */
2349}
2350
2351/**
2352 * igb_clean_tx_ring - Free Tx Buffers
9d5c8243
AK		 2353 * @tx_ring: ring to be cleaned
2354 **/
3b644cf6 2355static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 2356{
3b644cf6 2357 struct igb_adapter *adapter = tx_ring->adapter;
9d5c8243
AK		 2358 struct igb_buffer *buffer_info;
2359 unsigned long size;
2360 unsigned int i;
2361
2362 if (!tx_ring->buffer_info)
2363 return;
2364 /* Free all the Tx ring sk_buffs */
2365
2366 for (i = 0; i < tx_ring->count; i++) {
2367 buffer_info = &tx_ring->buffer_info[i];
2368 igb_unmap_and_free_tx_resource(adapter, buffer_info);
2369 }
2370
2371 size = sizeof(struct igb_buffer) * tx_ring->count;
2372 memset(tx_ring->buffer_info, 0, size);
2373
2374 /* Zero out the descriptor ring */
2375
2376 memset(tx_ring->desc, 0, tx_ring->size);
2377
2378 tx_ring->next_to_use = 0;
2379 tx_ring->next_to_clean = 0;
2380
2381 writel(0, adapter->hw.hw_addr + tx_ring->head);
2382 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2383}
2384
2385/**
2386 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2387 * @adapter: board private structure
2388 **/
2389static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2390{
2391 int i;
2392
2393 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2394 igb_clean_tx_ring(&adapter->tx_ring[i]);
9d5c8243
AK		 2395}
2396
2397/**
2398 * igb_free_rx_resources - Free Rx Resources
9d5c8243
AK		 2399 * @rx_ring: ring to clean the resources from
2400 *
2401 * Free all receive software resources
2402 **/
68fd9910 2403void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2404{
3b644cf6 2405 struct pci_dev *pdev = rx_ring->adapter->pdev;
9d5c8243 2406
3b644cf6 2407 igb_clean_rx_ring(rx_ring);
9d5c8243
AK		 2408
2409 vfree(rx_ring->buffer_info);
2410 rx_ring->buffer_info = NULL;
2411
2412 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2413
2414 rx_ring->desc = NULL;
2415}
2416
2417/**
2418 * igb_free_all_rx_resources - Free Rx Resources for All Queues
2419 * @adapter: board private structure
2420 *
2421 * Free all receive software resources
2422 **/
2423static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2424{
2425 int i;
2426
2427 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2428 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 2429}
2430
2431/**
2432 * igb_clean_rx_ring - Free Rx Buffers per Queue
9d5c8243
AK		 2433 * @rx_ring: ring to free buffers from
2434 **/
3b644cf6 2435static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 2436{
3b644cf6 2437 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 2438 struct igb_buffer *buffer_info;
2439 struct pci_dev *pdev = adapter->pdev;
2440 unsigned long size;
2441 unsigned int i;
2442
2443 if (!rx_ring->buffer_info)
2444 return;
2445 /* Free all the Rx ring sk_buffs */
2446 for (i = 0; i < rx_ring->count; i++) {
2447 buffer_info = &rx_ring->buffer_info[i];
2448 if (buffer_info->dma) {
2449 if (adapter->rx_ps_hdr_size)
2450 pci_unmap_single(pdev, buffer_info->dma,
2451 adapter->rx_ps_hdr_size,
2452 PCI_DMA_FROMDEVICE);
2453 else
2454 pci_unmap_single(pdev, buffer_info->dma,
2455 adapter->rx_buffer_len,
2456 PCI_DMA_FROMDEVICE);
2457 buffer_info->dma = 0;
2458 }
2459
2460 if (buffer_info->skb) {
2461 dev_kfree_skb(buffer_info->skb);
2462 buffer_info->skb = NULL;
2463 }
2464 if (buffer_info->page) {
bf36c1a0
AD		 2465 if (buffer_info->page_dma)
2466 pci_unmap_page(pdev, buffer_info->page_dma,
2467 PAGE_SIZE / 2,
2468 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 2469 put_page(buffer_info->page);
2470 buffer_info->page = NULL;
2471 buffer_info->page_dma = 0;
bf36c1a0 2472 buffer_info->page_offset = 0;
9d5c8243
AK		 2473 }
2474 }
2475
9d5c8243
AK		 2476 size = sizeof(struct igb_buffer) * rx_ring->count;
2477 memset(rx_ring->buffer_info, 0, size);
2478
2479 /* Zero out the descriptor ring */
2480 memset(rx_ring->desc, 0, rx_ring->size);
2481
2482 rx_ring->next_to_clean = 0;
2483 rx_ring->next_to_use = 0;
2484
2485 writel(0, adapter->hw.hw_addr + rx_ring->head);
2486 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2487}
2488
2489/**
2490 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2491 * @adapter: board private structure
2492 **/
2493static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2494{
2495 int i;
2496
2497 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2498 igb_clean_rx_ring(&adapter->rx_ring[i]);
9d5c8243
AK		 2499}
2500
2501/**
2502 * igb_set_mac - Change the Ethernet Address of the NIC
2503 * @netdev: network interface device structure
2504 * @p: pointer to an address structure
2505 *
2506 * Returns 0 on success, negative on failure
2507 **/
2508static int igb_set_mac(struct net_device *netdev, void *p)
2509{
2510 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 2511 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 2512 struct sockaddr *addr = p;
2513
2514 if (!is_valid_ether_addr(addr->sa_data))
2515 return -EADDRNOTAVAIL;
2516
2517 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 2518 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 2519
26ad9178
AD		 2520 /* set the correct pool for the new PF MAC address in entry 0 */
2521 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
2522 adapter->vfs_allocated_count);
e1739522 2523
9d5c8243
AK		 2524 return 0;
2525}
2526
2527/**
68d480c4 2528 * igb_write_mc_addr_list - write multicast addresses to MTA
9d5c8243
AK		 2529 * @netdev: network interface device structure
2530 *
68d480c4
AD		 2531 * Writes multicast address list to the MTA hash table.
2532 * Returns: -ENOMEM on failure
2533 * 0 on no addresses written
2534 * X on writing X addresses to MTA
9d5c8243 2535 **/
68d480c4 2536static int igb_write_mc_addr_list(struct net_device *netdev)
9d5c8243
AK		 2537{
2538 struct igb_adapter *adapter = netdev_priv(netdev);
2539 struct e1000_hw *hw = &adapter->hw;
ff41f8dc 2540 struct dev_mc_list *mc_ptr = netdev->mc_list;
68d480c4
AD		 2541 u8 *mta_list;
2542 u32 vmolr = 0;
9d5c8243
AK		 2543 int i;
2544
68d480c4
AD		 2545 if (!netdev->mc_count) {
2546 /* nothing to program, so clear mc list */
2547 igb_update_mc_addr_list(hw, NULL, 0);
2548 igb_restore_vf_multicasts(adapter);
2549 return 0;
2550 }
9d5c8243 2551
68d480c4
AD		 2552 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2553 if (!mta_list)
2554 return -ENOMEM;
ff41f8dc 2555
68d480c4
AD		 2556 /* set vmolr receive overflow multicast bit */
2557 vmolr |= E1000_VMOLR_ROMPE;
2558
2559 /* The shared function expects a packed array of only addresses. */
2560 mc_ptr = netdev->mc_list;
2561
2562 for (i = 0; i < netdev->mc_count; i++) {
2563 if (!mc_ptr)
2564 break;
2565 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2566 mc_ptr = mc_ptr->next;
746b9f02 2567 }
68d480c4
AD		 2568 igb_update_mc_addr_list(hw, mta_list, i);
2569 kfree(mta_list);
2570
2571 return netdev->mc_count;
2572}
2573
2574/**
2575 * igb_write_uc_addr_list - write unicast addresses to RAR table
2576 * @netdev: network interface device structure
2577 *
2578 * Writes unicast address list to the RAR table.
2579 * Returns: -ENOMEM on failure/insufficient address space
2580 * 0 on no addresses written
2581 * X on writing X addresses to the RAR table
2582 **/
2583static int igb_write_uc_addr_list(struct net_device *netdev)
2584{
2585 struct igb_adapter *adapter = netdev_priv(netdev);
2586 struct e1000_hw *hw = &adapter->hw;
2587 unsigned int vfn = adapter->vfs_allocated_count;
2588 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
2589 int count = 0;
2590
2591 /* return ENOMEM indicating insufficient memory for addresses */
2592 if (netdev->uc.count > rar_entries)
2593 return -ENOMEM;
9d5c8243 2594
ff41f8dc
AD		 2595 if (netdev->uc.count && rar_entries) {
2596 struct netdev_hw_addr *ha;
2597 list_for_each_entry(ha, &netdev->uc.list, list) {
2598 if (!rar_entries)
2599 break;
26ad9178
AD		 2600 igb_rar_set_qsel(adapter, ha->addr,
2601 rar_entries--,
68d480c4
AD		 2602 vfn);
2603 count++;
ff41f8dc
AD		 2604 }
2605 }
2606 /* write the addresses in reverse order to avoid write combining */
2607 for (; rar_entries > 0 ; rar_entries--) {
2608 wr32(E1000_RAH(rar_entries), 0);
2609 wr32(E1000_RAL(rar_entries), 0);
2610 }
2611 wrfl();
2612
68d480c4
AD		 2613 return count;
2614}
2615
2616/**
2617 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
2618 * @netdev: network interface device structure
2619 *
2620 * The set_rx_mode entry point is called whenever the unicast or multicast
2621 * address lists or the network interface flags are updated. This routine is
2622 * responsible for configuring the hardware for proper unicast, multicast,
2623 * promiscuous mode, and all-multi behavior.
2624 **/
2625static void igb_set_rx_mode(struct net_device *netdev)
2626{
2627 struct igb_adapter *adapter = netdev_priv(netdev);
2628 struct e1000_hw *hw = &adapter->hw;
2629 unsigned int vfn = adapter->vfs_allocated_count;
2630 u32 rctl, vmolr = 0;
2631 int count;
2632
2633 /* Check for Promiscuous and All Multicast modes */
2634 rctl = rd32(E1000_RCTL);
2635
2636 /* clear the effected bits */
2637 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
2638
2639 if (netdev->flags & IFF_PROMISC) {
2640 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2641 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
2642 } else {
2643 if (netdev->flags & IFF_ALLMULTI) {
2644 rctl |= E1000_RCTL_MPE;
2645 vmolr |= E1000_VMOLR_MPME;
2646 } else {
2647 /*
2648 * Write addresses to the MTA, if the attempt fails
2649 * then we should just turn on promiscous mode so
2650 * that we can at least receive multicast traffic
2651 */
2652 count = igb_write_mc_addr_list(netdev);
2653 if (count < 0) {
2654 rctl |= E1000_RCTL_MPE;
2655 vmolr |= E1000_VMOLR_MPME;
2656 } else if (count) {
2657 vmolr |= E1000_VMOLR_ROMPE;
2658 }
2659 }
2660 /*
2661 * Write addresses to available RAR registers, if there is not
2662 * sufficient space to store all the addresses then enable
2663 * unicast promiscous mode
2664 */
2665 count = igb_write_uc_addr_list(netdev);
2666 if (count < 0) {
2667 rctl |= E1000_RCTL_UPE;
2668 vmolr |= E1000_VMOLR_ROPE;
2669 }
2670 rctl |= E1000_RCTL_VFE;
28fc06f5 2671 }
68d480c4 2672 wr32(E1000_RCTL, rctl);
28fc06f5 2673
68d480c4
AD		 2674 /*
2675 * In order to support SR-IOV and eventually VMDq it is necessary to set
2676 * the VMOLR to enable the appropriate modes. Without this workaround
2677 * we will have issues with VLAN tag stripping not being done for frames
2678 * that are only arriving because we are the default pool
2679 */
2680 if (hw->mac.type < e1000_82576)
28fc06f5 2681 return;
9d5c8243 2682
68d480c4
AD		 2683 vmolr |= rd32(E1000_VMOLR(vfn)) &
2684 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
2685 wr32(E1000_VMOLR(vfn), vmolr);
28fc06f5 2686 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 2687}
2688
2689/* Need to wait a few seconds after link up to get diagnostic information from
2690 * the phy */
2691static void igb_update_phy_info(unsigned long data)
2692{
2693 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 2694 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 2695}
2696
4d6b725e
AD		 2697/**
2698 * igb_has_link - check shared code for link and determine up/down
2699 * @adapter: pointer to driver private info
2700 **/
2701static bool igb_has_link(struct igb_adapter *adapter)
2702{
2703 struct e1000_hw *hw = &adapter->hw;
2704 bool link_active = false;
2705 s32 ret_val = 0;
2706
2707 /* get_link_status is set on LSC (link status) interrupt or
2708 * rx sequence error interrupt. get_link_status will stay
2709 * false until the e1000_check_for_link establishes link
2710 * for copper adapters ONLY
2711 */
2712 switch (hw->phy.media_type) {
2713 case e1000_media_type_copper:
2714 if (hw->mac.get_link_status) {
2715 ret_val = hw->mac.ops.check_for_link(hw);
2716 link_active = !hw->mac.get_link_status;
2717 } else {
2718 link_active = true;
2719 }
2720 break;
4d6b725e
AD		 2721 case e1000_media_type_internal_serdes:
2722 ret_val = hw->mac.ops.check_for_link(hw);
2723 link_active = hw->mac.serdes_has_link;
2724 break;
2725 default:
2726 case e1000_media_type_unknown:
2727 break;
2728 }
2729
2730 return link_active;
2731}
2732
9d5c8243
AK		 2733/**
2734 * igb_watchdog - Timer Call-back
2735 * @data: pointer to adapter cast into an unsigned long
2736 **/
2737static void igb_watchdog(unsigned long data)
2738{
2739 struct igb_adapter *adapter = (struct igb_adapter *)data;
2740 /* Do the rest outside of interrupt context */
2741 schedule_work(&adapter->watchdog_task);
2742}
2743
2744static void igb_watchdog_task(struct work_struct *work)
2745{
2746 struct igb_adapter *adapter = container_of(work,
2747 struct igb_adapter, watchdog_task);
2748 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 2749 struct net_device *netdev = adapter->netdev;
2750 struct igb_ring *tx_ring = adapter->tx_ring;
9d5c8243 2751 u32 link;
7a6ea550 2752 u32 eics = 0;
7a6ea550 2753 int i;
9d5c8243 2754
4d6b725e
AD		 2755 link = igb_has_link(adapter);
2756 if ((netif_carrier_ok(netdev)) && link)
9d5c8243
AK		 2757 goto link_up;
2758
9d5c8243
AK		 2759 if (link) {
2760 if (!netif_carrier_ok(netdev)) {
2761 u32 ctrl;
2762 hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2763 &adapter->link_speed,
2764 &adapter->link_duplex);
2765
2766 ctrl = rd32(E1000_CTRL);
527d47c1
AD		 2767 /* Links status message must follow this format */
2768 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
9d5c8243 2769 "Flow Control: %s\n",
527d47c1 2770 netdev->name,
9d5c8243
AK		 2771 adapter->link_speed,
2772 adapter->link_duplex == FULL_DUPLEX ?
2773 "Full Duplex" : "Half Duplex",
2774 ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2775 E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2776 E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2777 E1000_CTRL_TFCE) ? "TX" : "None")));
2778
2779 /* tweak tx_queue_len according to speed/duplex and
2780 * adjust the timeout factor */
2781 netdev->tx_queue_len = adapter->tx_queue_len;
2782 adapter->tx_timeout_factor = 1;
2783 switch (adapter->link_speed) {
2784 case SPEED_10:
2785 netdev->tx_queue_len = 10;
2786 adapter->tx_timeout_factor = 14;
2787 break;
2788 case SPEED_100:
2789 netdev->tx_queue_len = 100;
2790 /* maybe add some timeout factor ? */
2791 break;
2792 }
2793
2794 netif_carrier_on(netdev);
9d5c8243 2795
4ae196df
AD		 2796 igb_ping_all_vfs(adapter);
2797
4b1a9877 2798 /* link state has changed, schedule phy info update */
9d5c8243
AK		 2799 if (!test_bit(__IGB_DOWN, &adapter->state))
2800 mod_timer(&adapter->phy_info_timer,
2801 round_jiffies(jiffies + 2 * HZ));
2802 }
2803 } else {
2804 if (netif_carrier_ok(netdev)) {
2805 adapter->link_speed = 0;
2806 adapter->link_duplex = 0;
527d47c1
AD		 2807 /* Links status message must follow this format */
2808 printk(KERN_INFO "igb: %s NIC Link is Down\n",
2809 netdev->name);
9d5c8243 2810 netif_carrier_off(netdev);
4b1a9877 2811
4ae196df
AD		 2812 igb_ping_all_vfs(adapter);
2813
4b1a9877 2814 /* link state has changed, schedule phy info update */
9d5c8243
AK		 2815 if (!test_bit(__IGB_DOWN, &adapter->state))
2816 mod_timer(&adapter->phy_info_timer,
2817 round_jiffies(jiffies + 2 * HZ));
2818 }
2819 }
2820
2821link_up:
2822 igb_update_stats(adapter);
2823
4b1a9877 2824 hw->mac.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
9d5c8243 2825 adapter->tpt_old = adapter->stats.tpt;
4b1a9877 2826 hw->mac.collision_delta = adapter->stats.colc - adapter->colc_old;
9d5c8243
AK		 2827 adapter->colc_old = adapter->stats.colc;
2828
2829 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2830 adapter->gorc_old = adapter->stats.gorc;
2831 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2832 adapter->gotc_old = adapter->stats.gotc;
2833
2834 igb_update_adaptive(&adapter->hw);
2835
2836 if (!netif_carrier_ok(netdev)) {
c493ea45 2837 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
9d5c8243
AK		 2838 /* We've lost link, so the controller stops DMA,
2839 * but we've got queued Tx work that's never going
2840 * to get done, so reset controller to flush Tx.
2841 * (Do the reset outside of interrupt context). */
2842 adapter->tx_timeout_count++;
2843 schedule_work(&adapter->reset_task);
c2d5ab49
JB		 2844 /* return immediately since reset is imminent */
2845 return;
9d5c8243
AK		 2846 }
2847 }
2848
2849 /* Cause software interrupt to ensure rx ring is cleaned */
7a6ea550
AD		 2850 if (adapter->msix_entries) {
2851 for (i = 0; i < adapter->num_rx_queues; i++)
2852 eics |= adapter->rx_ring[i].eims_value;
2853 wr32(E1000_EICS, eics);
2854 } else {
2855 wr32(E1000_ICS, E1000_ICS_RXDMT0);
2856 }
9d5c8243
AK		 2857
2858 /* Force detection of hung controller every watchdog period */
2859 tx_ring->detect_tx_hung = true;
2860
2861 /* Reset the timer */
2862 if (!test_bit(__IGB_DOWN, &adapter->state))
2863 mod_timer(&adapter->watchdog_timer,
2864 round_jiffies(jiffies + 2 * HZ));
2865}
2866
2867enum latency_range {
2868 lowest_latency = 0,
2869 low_latency = 1,
2870 bulk_latency = 2,
2871 latency_invalid = 255
2872};
2873
2874
6eb5a7f1
AD		 2875/**
2876 * igb_update_ring_itr - update the dynamic ITR value based on packet size
2877 *
2878 * Stores a new ITR value based on strictly on packet size. This
2879 * algorithm is less sophisticated than that used in igb_update_itr,
2880 * due to the difficulty of synchronizing statistics across multiple
2881 * receive rings. The divisors and thresholds used by this fuction
2882 * were determined based on theoretical maximum wire speed and testing
2883 * data, in order to minimize response time while increasing bulk
2884 * throughput.
2885 * This functionality is controlled by the InterruptThrottleRate module
2886 * parameter (see igb_param.c)
2887 * NOTE: This function is called only when operating in a multiqueue
2888 * receive environment.
2889 * @rx_ring: pointer to ring
2890 **/
2891static void igb_update_ring_itr(struct igb_ring *rx_ring)
9d5c8243 2892{
6eb5a7f1
AD		 2893 int new_val = rx_ring->itr_val;
2894 int avg_wire_size = 0;
2895 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 2896
6eb5a7f1
AD		 2897 if (!rx_ring->total_packets)
2898 goto clear_counts; /* no packets, so don't do anything */
9d5c8243 2899
6eb5a7f1
AD		 2900 /* For non-gigabit speeds, just fix the interrupt rate at 4000
2901 * ints/sec - ITR timer value of 120 ticks.
2902 */
2903 if (adapter->link_speed != SPEED_1000) {
2904 new_val = 120;
2905 goto set_itr_val;
9d5c8243 2906 }
6eb5a7f1 2907 avg_wire_size = rx_ring->total_bytes / rx_ring->total_packets;
9d5c8243 2908
6eb5a7f1
AD		 2909 /* Add 24 bytes to size to account for CRC, preamble, and gap */
2910 avg_wire_size += 24;
2911
2912 /* Don't starve jumbo frames */
2913 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 2914
6eb5a7f1
AD		 2915 /* Give a little boost to mid-size frames */
2916 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
2917 new_val = avg_wire_size / 3;
2918 else
2919 new_val = avg_wire_size / 2;
9d5c8243 2920
6eb5a7f1 2921set_itr_val:
9d5c8243
AK		 2922 if (new_val != rx_ring->itr_val) {
2923 rx_ring->itr_val = new_val;
6eb5a7f1 2924 rx_ring->set_itr = 1;
9d5c8243 2925 }
6eb5a7f1
AD		 2926clear_counts:
2927 rx_ring->total_bytes = 0;
2928 rx_ring->total_packets = 0;
9d5c8243
AK		 2929}
2930
2931/**
2932 * igb_update_itr - update the dynamic ITR value based on statistics
2933 * Stores a new ITR value based on packets and byte
2934 * counts during the last interrupt. The advantage of per interrupt
2935 * computation is faster updates and more accurate ITR for the current
2936 * traffic pattern. Constants in this function were computed
2937 * based on theoretical maximum wire speed and thresholds were set based
2938 * on testing data as well as attempting to minimize response time
2939 * while increasing bulk throughput.
2940 * this functionality is controlled by the InterruptThrottleRate module
2941 * parameter (see igb_param.c)
2942 * NOTE: These calculations are only valid when operating in a single-
2943 * queue environment.
2944 * @adapter: pointer to adapter
2945 * @itr_setting: current adapter->itr
2946 * @packets: the number of packets during this measurement interval
2947 * @bytes: the number of bytes during this measurement interval
2948 **/
2949static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
2950 int packets, int bytes)
2951{
2952 unsigned int retval = itr_setting;
2953
2954 if (packets == 0)
2955 goto update_itr_done;
2956
2957 switch (itr_setting) {
2958 case lowest_latency:
2959 /* handle TSO and jumbo frames */
2960 if (bytes/packets > 8000)
2961 retval = bulk_latency;
2962 else if ((packets < 5) && (bytes > 512))
2963 retval = low_latency;
2964 break;
2965 case low_latency: /* 50 usec aka 20000 ints/s */
2966 if (bytes > 10000) {
2967 /* this if handles the TSO accounting */
2968 if (bytes/packets > 8000) {
2969 retval = bulk_latency;
2970 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
2971 retval = bulk_latency;
2972 } else if ((packets > 35)) {
2973 retval = lowest_latency;
2974 }
2975 } else if (bytes/packets > 2000) {
2976 retval = bulk_latency;
2977 } else if (packets <= 2 && bytes < 512) {
2978 retval = lowest_latency;
2979 }
2980 break;
2981 case bulk_latency: /* 250 usec aka 4000 ints/s */
2982 if (bytes > 25000) {
2983 if (packets > 35)
2984 retval = low_latency;
1e5c3d21 2985 } else if (bytes < 1500) {
9d5c8243
AK		 2986 retval = low_latency;
2987 }
2988 break;
2989 }
2990
2991update_itr_done:
2992 return retval;
2993}
2994
6eb5a7f1 2995static void igb_set_itr(struct igb_adapter *adapter)
9d5c8243
AK		 2996{
2997 u16 current_itr;
2998 u32 new_itr = adapter->itr;
2999
3000 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
3001 if (adapter->link_speed != SPEED_1000) {
3002 current_itr = 0;
3003 new_itr = 4000;
3004 goto set_itr_now;
3005 }
3006
3007 adapter->rx_itr = igb_update_itr(adapter,
3008 adapter->rx_itr,
3009 adapter->rx_ring->total_packets,
3010 adapter->rx_ring->total_bytes);
9d5c8243 3011
6eb5a7f1 3012 if (adapter->rx_ring->buddy) {
9d5c8243
AK		 3013 adapter->tx_itr = igb_update_itr(adapter,
3014 adapter->tx_itr,
3015 adapter->tx_ring->total_packets,
3016 adapter->tx_ring->total_bytes);
9d5c8243
AK		 3017 current_itr = max(adapter->rx_itr, adapter->tx_itr);
3018 } else {
3019 current_itr = adapter->rx_itr;
3020 }
3021
6eb5a7f1 3022 /* conservative mode (itr 3) eliminates the lowest_latency setting */
73cd78f1 3023 if (adapter->itr_setting == 3 && current_itr == lowest_latency)
6eb5a7f1
AD		 3024 current_itr = low_latency;
3025
9d5c8243
AK		 3026 switch (current_itr) {
3027 /* counts and packets in update_itr are dependent on these numbers */
3028 case lowest_latency:
78b1f607 3029 new_itr = 56; /* aka 70,000 ints/sec */
9d5c8243
AK		 3030 break;
3031 case low_latency:
78b1f607 3032 new_itr = 196; /* aka 20,000 ints/sec */
9d5c8243
AK		 3033 break;
3034 case bulk_latency:
78b1f607 3035 new_itr = 980; /* aka 4,000 ints/sec */
9d5c8243
AK		 3036 break;
3037 default:
3038 break;
3039 }
3040
3041set_itr_now:
6eb5a7f1
AD		 3042 adapter->rx_ring->total_bytes = 0;
3043 adapter->rx_ring->total_packets = 0;
3044 if (adapter->rx_ring->buddy) {
3045 adapter->rx_ring->buddy->total_bytes = 0;
3046 adapter->rx_ring->buddy->total_packets = 0;
3047 }
3048
9d5c8243
AK		 3049 if (new_itr != adapter->itr) {
3050 /* this attempts to bias the interrupt rate towards Bulk
3051 * by adding intermediate steps when interrupt rate is
3052 * increasing */
3053 new_itr = new_itr > adapter->itr ?
78b1f607
AD		 3054 max((new_itr * adapter->itr) /
3055 (new_itr + (adapter->itr >> 2)), new_itr) :
9d5c8243
AK		 3056 new_itr;
3057 /* Don't write the value here; it resets the adapter's
3058 * internal timer, and causes us to delay far longer than
3059 * we should between interrupts. Instead, we write the ITR
3060 * value at the beginning of the next interrupt so the timing
3061 * ends up being correct.
3062 */
3063 adapter->itr = new_itr;
78b1f607 3064 adapter->rx_ring->itr_val = new_itr;
6eb5a7f1 3065 adapter->rx_ring->set_itr = 1;
9d5c8243
AK		 3066 }
3067
3068 return;
3069}
3070
3071
3072#define IGB_TX_FLAGS_CSUM 0x00000001
3073#define IGB_TX_FLAGS_VLAN 0x00000002
3074#define IGB_TX_FLAGS_TSO 0x00000004
3075#define IGB_TX_FLAGS_IPV4 0x00000008
33af6bcc 3076#define IGB_TX_FLAGS_TSTAMP 0x00000010
9d5c8243
AK		 3077#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
3078#define IGB_TX_FLAGS_VLAN_SHIFT 16
3079
3080static inline int igb_tso_adv(struct igb_adapter *adapter,
3081 struct igb_ring *tx_ring,
3082 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
3083{
3084 struct e1000_adv_tx_context_desc *context_desc;
3085 unsigned int i;
3086 int err;
3087 struct igb_buffer *buffer_info;
3088 u32 info = 0, tu_cmd = 0;
3089 u32 mss_l4len_idx, l4len;
3090 *hdr_len = 0;
3091
3092 if (skb_header_cloned(skb)) {
3093 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
3094 if (err)
3095 return err;
3096 }
3097
3098 l4len = tcp_hdrlen(skb);
3099 *hdr_len += l4len;
3100
3101 if (skb->protocol == htons(ETH_P_IP)) {
3102 struct iphdr *iph = ip_hdr(skb);
3103 iph->tot_len = 0;
3104 iph->check = 0;
3105 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
3106 iph->daddr, 0,
3107 IPPROTO_TCP,
3108 0);
3109 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
3110 ipv6_hdr(skb)->payload_len = 0;
3111 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
3112 &ipv6_hdr(skb)->daddr,
3113 0, IPPROTO_TCP, 0);
3114 }
3115
3116 i = tx_ring->next_to_use;
3117
3118 buffer_info = &tx_ring->buffer_info[i];
3119 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3120 /* VLAN MACLEN IPLEN */
3121 if (tx_flags & IGB_TX_FLAGS_VLAN)
3122 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
3123 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3124 *hdr_len += skb_network_offset(skb);
3125 info |= skb_network_header_len(skb);
3126 *hdr_len += skb_network_header_len(skb);
3127 context_desc->vlan_macip_lens = cpu_to_le32(info);
3128
3129 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
3130 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3131
3132 if (skb->protocol == htons(ETH_P_IP))
3133 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
3134 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3135
3136 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3137
3138 /* MSS L4LEN IDX */
3139 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
3140 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
3141
73cd78f1 3142 /* For 82575, context index must be unique per ring. */
7dfc16fa
AD		 3143 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
3144 mss_l4len_idx |= tx_ring->queue_index << 4;
9d5c8243
AK		 3145
3146 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
3147 context_desc->seqnum_seed = 0;
3148
3149 buffer_info->time_stamp = jiffies;
0e014cb1 3150 buffer_info->next_to_watch = i;
9d5c8243
AK		 3151 buffer_info->dma = 0;
3152 i++;
3153 if (i == tx_ring->count)
3154 i = 0;
3155
3156 tx_ring->next_to_use = i;
3157
3158 return true;
3159}
3160
3161static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
3162 struct igb_ring *tx_ring,
3163 struct sk_buff *skb, u32 tx_flags)
3164{
3165 struct e1000_adv_tx_context_desc *context_desc;
3166 unsigned int i;
3167 struct igb_buffer *buffer_info;
3168 u32 info = 0, tu_cmd = 0;
3169
3170 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
3171 (tx_flags & IGB_TX_FLAGS_VLAN)) {
3172 i = tx_ring->next_to_use;
3173 buffer_info = &tx_ring->buffer_info[i];
3174 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3175
3176 if (tx_flags & IGB_TX_FLAGS_VLAN)
3177 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
3178 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3179 if (skb->ip_summed == CHECKSUM_PARTIAL)
3180 info |= skb_network_header_len(skb);
3181
3182 context_desc->vlan_macip_lens = cpu_to_le32(info);
3183
3184 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3185
3186 if (skb->ip_summed == CHECKSUM_PARTIAL) {
fa4a7ef3
AJ		 3187 __be16 protocol;
3188
3189 if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
3190 const struct vlan_ethhdr *vhdr =
3191 (const struct vlan_ethhdr*)skb->data;
3192
3193 protocol = vhdr->h_vlan_encapsulated_proto;
3194 } else {
3195 protocol = skb->protocol;
3196 }
3197
3198 switch (protocol) {
09640e63 3199 case cpu_to_be16(ETH_P_IP):
9d5c8243 3200 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
44b0cda3
MW		 3201 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
3202 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
b9473560
JB		 3203 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
3204 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
44b0cda3 3205 break;
09640e63 3206 case cpu_to_be16(ETH_P_IPV6):
44b0cda3
MW		 3207 /* XXX what about other V6 headers?? */
3208 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
3209 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
b9473560
JB		 3210 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
3211 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
44b0cda3
MW		 3212 break;
3213 default:
3214 if (unlikely(net_ratelimit()))
3215 dev_warn(&adapter->pdev->dev,
3216 "partial checksum but proto=%x!\n",
3217 skb->protocol);
3218 break;
3219 }
9d5c8243
AK		 3220 }
3221
3222 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3223 context_desc->seqnum_seed = 0;
7dfc16fa
AD		 3224 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
3225 context_desc->mss_l4len_idx =
3226 cpu_to_le32(tx_ring->queue_index << 4);
265de409
AD		 3227 else
3228 context_desc->mss_l4len_idx = 0;
9d5c8243
AK		 3229
3230 buffer_info->time_stamp = jiffies;
0e014cb1 3231 buffer_info->next_to_watch = i;
9d5c8243
AK		 3232 buffer_info->dma = 0;
3233
3234 i++;
3235 if (i == tx_ring->count)
3236 i = 0;
3237 tx_ring->next_to_use = i;
3238
3239 return true;
3240 }
9d5c8243
AK		 3241 return false;
3242}
3243
3244#define IGB_MAX_TXD_PWR 16
3245#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
3246
3247static inline int igb_tx_map_adv(struct igb_adapter *adapter,
0e014cb1
AD		 3248 struct igb_ring *tx_ring, struct sk_buff *skb,
3249 unsigned int first)
9d5c8243
AK		 3250{
3251 struct igb_buffer *buffer_info;
3252 unsigned int len = skb_headlen(skb);
3253 unsigned int count = 0, i;
3254 unsigned int f;
65689fef 3255 dma_addr_t *map;
9d5c8243
AK		 3256
3257 i = tx_ring->next_to_use;
3258
65689fef
AD		 3259 if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
3260 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
3261 return 0;
3262 }
3263
3264 map = skb_shinfo(skb)->dma_maps;
3265
9d5c8243
AK		 3266 buffer_info = &tx_ring->buffer_info[i];
3267 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3268 buffer_info->length = len;
3269 /* set time_stamp *before* dma to help avoid a possible race */
3270 buffer_info->time_stamp = jiffies;
0e014cb1 3271 buffer_info->next_to_watch = i;
042a53a9 3272 buffer_info->dma = skb_shinfo(skb)->dma_head;
9d5c8243
AK		 3273
3274 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
3275 struct skb_frag_struct *frag;
3276
65689fef
AD		 3277 i++;
3278 if (i == tx_ring->count)
3279 i = 0;
3280
9d5c8243
AK		 3281 frag = &skb_shinfo(skb)->frags[f];
3282 len = frag->size;
3283
3284 buffer_info = &tx_ring->buffer_info[i];
3285 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3286 buffer_info->length = len;
3287 buffer_info->time_stamp = jiffies;
0e014cb1 3288 buffer_info->next_to_watch = i;
65689fef 3289 buffer_info->dma = map[count];
9d5c8243 3290 count++;
9d5c8243
AK		 3291 }
3292
9d5c8243 3293 tx_ring->buffer_info[i].skb = skb;
0e014cb1 3294 tx_ring->buffer_info[first].next_to_watch = i;
9d5c8243 3295
042a53a9 3296 return count + 1;
9d5c8243
AK		 3297}
3298
3299static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
3300 struct igb_ring *tx_ring,
3301 int tx_flags, int count, u32 paylen,
3302 u8 hdr_len)
3303{
3304 union e1000_adv_tx_desc *tx_desc = NULL;
3305 struct igb_buffer *buffer_info;
3306 u32 olinfo_status = 0, cmd_type_len;
3307 unsigned int i;
3308
3309 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
3310 E1000_ADVTXD_DCMD_DEXT);
3311
3312 if (tx_flags & IGB_TX_FLAGS_VLAN)
3313 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3314
33af6bcc
PO		 3315 if (tx_flags & IGB_TX_FLAGS_TSTAMP)
3316 cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP;
3317
9d5c8243
AK		 3318 if (tx_flags & IGB_TX_FLAGS_TSO) {
3319 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3320
3321 /* insert tcp checksum */
3322 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3323
3324 /* insert ip checksum */
3325 if (tx_flags & IGB_TX_FLAGS_IPV4)
3326 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3327
3328 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
3329 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3330 }
3331
7dfc16fa
AD		 3332 if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) &&
3333 (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
3334 IGB_TX_FLAGS_VLAN)))
661086df 3335 olinfo_status |= tx_ring->queue_index << 4;
9d5c8243
AK		 3336
3337 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
3338
3339 i = tx_ring->next_to_use;
3340 while (count--) {
3341 buffer_info = &tx_ring->buffer_info[i];
3342 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
3343 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
3344 tx_desc->read.cmd_type_len =
3345 cpu_to_le32(cmd_type_len | buffer_info->length);
3346 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
3347 i++;
3348 if (i == tx_ring->count)
3349 i = 0;
3350 }
3351
3352 tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
3353 /* Force memory writes to complete before letting h/w
3354 * know there are new descriptors to fetch. (Only
3355 * applicable for weak-ordered memory model archs,
3356 * such as IA-64). */
3357 wmb();
3358
3359 tx_ring->next_to_use = i;
3360 writel(i, adapter->hw.hw_addr + tx_ring->tail);
3361 /* we need this if more than one processor can write to our tail
3362 * at a time, it syncronizes IO on IA64/Altix systems */
3363 mmiowb();
3364}
3365
3366static int __igb_maybe_stop_tx(struct net_device *netdev,
3367 struct igb_ring *tx_ring, int size)
3368{
3369 struct igb_adapter *adapter = netdev_priv(netdev);
3370
661086df 3371 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 3372
9d5c8243
AK		 3373 /* Herbert's original patch had:
3374 * smp_mb__after_netif_stop_queue();
3375 * but since that doesn't exist yet, just open code it. */
3376 smp_mb();
3377
3378 /* We need to check again in a case another CPU has just
3379 * made room available. */
c493ea45 3380 if (igb_desc_unused(tx_ring) < size)
9d5c8243
AK		 3381 return -EBUSY;
3382
3383 /* A reprieve! */
661086df 3384 netif_wake_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 3385 ++adapter->restart_queue;
3386 return 0;
3387}
3388
3389static int igb_maybe_stop_tx(struct net_device *netdev,
3390 struct igb_ring *tx_ring, int size)
3391{
c493ea45 3392 if (igb_desc_unused(tx_ring) >= size)
9d5c8243
AK		 3393 return 0;
3394 return __igb_maybe_stop_tx(netdev, tx_ring, size);
3395}
3396
3b29a56d
SH		 3397static netdev_tx_t igb_xmit_frame_ring_adv(struct sk_buff *skb,
3398 struct net_device *netdev,
3399 struct igb_ring *tx_ring)
9d5c8243
AK		 3400{
3401 struct igb_adapter *adapter = netdev_priv(netdev);
0e014cb1 3402 unsigned int first;
9d5c8243 3403 unsigned int tx_flags = 0;
9d5c8243 3404 u8 hdr_len = 0;
65689fef 3405 int count = 0;
9d5c8243 3406 int tso = 0;
33af6bcc 3407 union skb_shared_tx *shtx;
9d5c8243 3408
9d5c8243
AK		 3409 if (test_bit(__IGB_DOWN, &adapter->state)) {
3410 dev_kfree_skb_any(skb);
3411 return NETDEV_TX_OK;
3412 }
3413
3414 if (skb->len <= 0) {
3415 dev_kfree_skb_any(skb);
3416 return NETDEV_TX_OK;
3417 }
3418
9d5c8243
AK		 3419 /* need: 1 descriptor per page,
3420 * + 2 desc gap to keep tail from touching head,
3421 * + 1 desc for skb->data,
3422 * + 1 desc for context descriptor,
3423 * otherwise try next time */
3424 if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
3425 /* this is a hard error */
9d5c8243
AK		 3426 return NETDEV_TX_BUSY;
3427 }
33af6bcc
PO		 3428
3429 /*
3430 * TODO: check that there currently is no other packet with
3431 * time stamping in the queue
3432 *
3433 * When doing time stamping, keep the connection to the socket
3434 * a while longer: it is still needed by skb_hwtstamp_tx(),
3435 * called either in igb_tx_hwtstamp() or by our caller when
3436 * doing software time stamping.
3437 */
3438 shtx = skb_tx(skb);
3439 if (unlikely(shtx->hardware)) {
3440 shtx->in_progress = 1;
3441 tx_flags |= IGB_TX_FLAGS_TSTAMP;
33af6bcc 3442 }
9d5c8243
AK		 3443
3444 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
3445 tx_flags |= IGB_TX_FLAGS_VLAN;
3446 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
3447 }
3448
661086df
PWJ		 3449 if (skb->protocol == htons(ETH_P_IP))
3450 tx_flags |= IGB_TX_FLAGS_IPV4;
3451
0e014cb1 3452 first = tx_ring->next_to_use;
9d5c8243
AK		 3453 tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
3454 &hdr_len) : 0;
3455
3456 if (tso < 0) {
3457 dev_kfree_skb_any(skb);
9d5c8243
AK		 3458 return NETDEV_TX_OK;
3459 }
3460
3461 if (tso)
3462 tx_flags |= IGB_TX_FLAGS_TSO;
bc1cbd34
AD		 3463 else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags) &&
3464 (skb->ip_summed == CHECKSUM_PARTIAL))
3465 tx_flags |= IGB_TX_FLAGS_CSUM;
9d5c8243 3466
65689fef
AD		 3467 /*
3468 * count reflects descriptors mapped, if 0 then mapping error
3469 * has occured and we need to rewind the descriptor queue
3470 */
3471 count = igb_tx_map_adv(adapter, tx_ring, skb, first);
3472
3473 if (count) {
3474 igb_tx_queue_adv(adapter, tx_ring, tx_flags, count,
3475 skb->len, hdr_len);
65689fef
AD		 3476 /* Make sure there is space in the ring for the next send. */
3477 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
3478 } else {
3479 dev_kfree_skb_any(skb);
3480 tx_ring->buffer_info[first].time_stamp = 0;
3481 tx_ring->next_to_use = first;
3482 }
9d5c8243 3483
9d5c8243
AK		 3484 return NETDEV_TX_OK;
3485}
3486
3b29a56d
SH		 3487static netdev_tx_t igb_xmit_frame_adv(struct sk_buff *skb,
3488 struct net_device *netdev)
9d5c8243
AK		 3489{
3490 struct igb_adapter *adapter = netdev_priv(netdev);
661086df
PWJ		 3491 struct igb_ring *tx_ring;
3492
661086df 3493 int r_idx = 0;
1bfaf07b 3494 r_idx = skb->queue_mapping & (IGB_ABS_MAX_TX_QUEUES - 1);
661086df 3495 tx_ring = adapter->multi_tx_table[r_idx];
9d5c8243
AK		 3496
3497 /* This goes back to the question of how to logically map a tx queue
3498 * to a flow. Right now, performance is impacted slightly negatively
3499 * if using multiple tx queues. If the stack breaks away from a
3500 * single qdisc implementation, we can look at this again. */
3b29a56d 3501 return igb_xmit_frame_ring_adv(skb, netdev, tx_ring);
9d5c8243
AK		 3502}
3503
3504/**
3505 * igb_tx_timeout - Respond to a Tx Hang
3506 * @netdev: network interface device structure
3507 **/
3508static void igb_tx_timeout(struct net_device *netdev)
3509{
3510 struct igb_adapter *adapter = netdev_priv(netdev);
3511 struct e1000_hw *hw = &adapter->hw;
3512
3513 /* Do the reset outside of interrupt context */
3514 adapter->tx_timeout_count++;
3515 schedule_work(&adapter->reset_task);
265de409
AD		 3516 wr32(E1000_EICS,
3517 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 3518}
3519
3520static void igb_reset_task(struct work_struct *work)
3521{
3522 struct igb_adapter *adapter;
3523 adapter = container_of(work, struct igb_adapter, reset_task);
3524
3525 igb_reinit_locked(adapter);
3526}
3527
3528/**
3529 * igb_get_stats - Get System Network Statistics
3530 * @netdev: network interface device structure
3531 *
3532 * Returns the address of the device statistics structure.
3533 * The statistics are actually updated from the timer callback.
3534 **/
73cd78f1 3535static struct net_device_stats *igb_get_stats(struct net_device *netdev)
9d5c8243 3536{
9d5c8243 3537 /* only return the current stats */
8d24e933 3538 return &netdev->stats;
9d5c8243
AK		 3539}
3540
3541/**
3542 * igb_change_mtu - Change the Maximum Transfer Unit
3543 * @netdev: network interface device structure
3544 * @new_mtu: new value for maximum frame size
3545 *
3546 * Returns 0 on success, negative on failure
3547 **/
3548static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3549{
3550 struct igb_adapter *adapter = netdev_priv(netdev);
3551 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3552
3553 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
3554 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3555 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
3556 return -EINVAL;
3557 }
3558
9d5c8243
AK		 3559 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3560 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
3561 return -EINVAL;
3562 }
3563
3564 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3565 msleep(1);
73cd78f1 3566
9d5c8243
AK		 3567 /* igb_down has a dependency on max_frame_size */
3568 adapter->max_frame_size = max_frame;
3569 if (netif_running(netdev))
3570 igb_down(adapter);
3571
3572 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3573 * means we reserve 2 more, this pushes us to allocate from the next
3574 * larger slab size.
3575 * i.e. RXBUFFER_2048 --> size-4096 slab
3576 */
3577
3578 if (max_frame <= IGB_RXBUFFER_256)
3579 adapter->rx_buffer_len = IGB_RXBUFFER_256;
3580 else if (max_frame <= IGB_RXBUFFER_512)
3581 adapter->rx_buffer_len = IGB_RXBUFFER_512;
3582 else if (max_frame <= IGB_RXBUFFER_1024)
3583 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3584 else if (max_frame <= IGB_RXBUFFER_2048)
3585 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
3586 else
bf36c1a0
AD		 3587#if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
3588 adapter->rx_buffer_len = IGB_RXBUFFER_16384;
3589#else
3590 adapter->rx_buffer_len = PAGE_SIZE / 2;
3591#endif
e1739522
AD		 3592
3593 /* if sr-iov is enabled we need to force buffer size to 1K or larger */
3594 if (adapter->vfs_allocated_count &&
3595 (adapter->rx_buffer_len < IGB_RXBUFFER_1024))
3596 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3597
9d5c8243
AK		 3598 /* adjust allocation if LPE protects us, and we aren't using SBP */
3599 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
3600 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
3601 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3602
3603 dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
3604 netdev->mtu, new_mtu);
3605 netdev->mtu = new_mtu;
3606
3607 if (netif_running(netdev))
3608 igb_up(adapter);
3609 else
3610 igb_reset(adapter);
3611
3612 clear_bit(__IGB_RESETTING, &adapter->state);
3613
3614 return 0;
3615}
3616
3617/**
3618 * igb_update_stats - Update the board statistics counters
3619 * @adapter: board private structure
3620 **/
3621
3622void igb_update_stats(struct igb_adapter *adapter)
3623{
8d24e933 3624 struct net_device *netdev = adapter->netdev;
9d5c8243
AK		 3625 struct e1000_hw *hw = &adapter->hw;
3626 struct pci_dev *pdev = adapter->pdev;
3627 u16 phy_tmp;
3628
3629#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3630
3631 /*
3632 * Prevent stats update while adapter is being reset, or if the pci
3633 * connection is down.
3634 */
3635 if (adapter->link_speed == 0)
3636 return;
3637 if (pci_channel_offline(pdev))
3638 return;
3639
3640 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3641 adapter->stats.gprc += rd32(E1000_GPRC);
3642 adapter->stats.gorc += rd32(E1000_GORCL);
3643 rd32(E1000_GORCH); /* clear GORCL */
3644 adapter->stats.bprc += rd32(E1000_BPRC);
3645 adapter->stats.mprc += rd32(E1000_MPRC);
3646 adapter->stats.roc += rd32(E1000_ROC);
3647
3648 adapter->stats.prc64 += rd32(E1000_PRC64);
3649 adapter->stats.prc127 += rd32(E1000_PRC127);
3650 adapter->stats.prc255 += rd32(E1000_PRC255);
3651 adapter->stats.prc511 += rd32(E1000_PRC511);
3652 adapter->stats.prc1023 += rd32(E1000_PRC1023);
3653 adapter->stats.prc1522 += rd32(E1000_PRC1522);
3654 adapter->stats.symerrs += rd32(E1000_SYMERRS);
3655 adapter->stats.sec += rd32(E1000_SEC);
3656
3657 adapter->stats.mpc += rd32(E1000_MPC);
3658 adapter->stats.scc += rd32(E1000_SCC);
3659 adapter->stats.ecol += rd32(E1000_ECOL);
3660 adapter->stats.mcc += rd32(E1000_MCC);
3661 adapter->stats.latecol += rd32(E1000_LATECOL);
3662 adapter->stats.dc += rd32(E1000_DC);
3663 adapter->stats.rlec += rd32(E1000_RLEC);
3664 adapter->stats.xonrxc += rd32(E1000_XONRXC);
3665 adapter->stats.xontxc += rd32(E1000_XONTXC);
3666 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
3667 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
3668 adapter->stats.fcruc += rd32(E1000_FCRUC);
3669 adapter->stats.gptc += rd32(E1000_GPTC);
3670 adapter->stats.gotc += rd32(E1000_GOTCL);
3671 rd32(E1000_GOTCH); /* clear GOTCL */
3672 adapter->stats.rnbc += rd32(E1000_RNBC);
3673 adapter->stats.ruc += rd32(E1000_RUC);
3674 adapter->stats.rfc += rd32(E1000_RFC);
3675 adapter->stats.rjc += rd32(E1000_RJC);
3676 adapter->stats.tor += rd32(E1000_TORH);
3677 adapter->stats.tot += rd32(E1000_TOTH);
3678 adapter->stats.tpr += rd32(E1000_TPR);
3679
3680 adapter->stats.ptc64 += rd32(E1000_PTC64);
3681 adapter->stats.ptc127 += rd32(E1000_PTC127);
3682 adapter->stats.ptc255 += rd32(E1000_PTC255);
3683 adapter->stats.ptc511 += rd32(E1000_PTC511);
3684 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
3685 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
3686
3687 adapter->stats.mptc += rd32(E1000_MPTC);
3688 adapter->stats.bptc += rd32(E1000_BPTC);
3689
3690 /* used for adaptive IFS */
3691
3692 hw->mac.tx_packet_delta = rd32(E1000_TPT);
3693 adapter->stats.tpt += hw->mac.tx_packet_delta;
3694 hw->mac.collision_delta = rd32(E1000_COLC);
3695 adapter->stats.colc += hw->mac.collision_delta;
3696
3697 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
3698 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3699 adapter->stats.tncrs += rd32(E1000_TNCRS);
3700 adapter->stats.tsctc += rd32(E1000_TSCTC);
3701 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
3702
3703 adapter->stats.iac += rd32(E1000_IAC);
3704 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
3705 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
3706 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
3707 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
3708 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
3709 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
3710 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
3711 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
3712
3713 /* Fill out the OS statistics structure */
8d24e933
AK		 3714 netdev->stats.multicast = adapter->stats.mprc;
3715 netdev->stats.collisions = adapter->stats.colc;
9d5c8243
AK		 3716
3717 /* Rx Errors */
3718
8c0ab70a
JDB		 3719 if (hw->mac.type != e1000_82575) {
3720 u32 rqdpc_tmp;
3ea73afa 3721 u64 rqdpc_total = 0;
8c0ab70a
JDB		 3722 int i;
3723 /* Read out drops stats per RX queue. Notice RQDPC (Receive
3724 * Queue Drop Packet Count) stats only gets incremented, if
3725 * the DROP_EN but it set (in the SRRCTL register for that
3726 * queue). If DROP_EN bit is NOT set, then the some what
3727 * equivalent count is stored in RNBC (not per queue basis).
3728 * Also note the drop count is due to lack of available
3729 * descriptors.
3730 */
3731 for (i = 0; i < adapter->num_rx_queues; i++) {
3732 rqdpc_tmp = rd32(E1000_RQDPC(i)) & 0xFFF;
3733 adapter->rx_ring[i].rx_stats.drops += rqdpc_tmp;
3ea73afa 3734 rqdpc_total += adapter->rx_ring[i].rx_stats.drops;
8c0ab70a 3735 }
8d24e933 3736 netdev->stats.rx_fifo_errors = rqdpc_total;
8c0ab70a
JDB		 3737 }
3738
3ea73afa
JDB		 3739 /* Note RNBC (Receive No Buffers Count) is an not an exact
3740 * drop count as the hardware FIFO might save the day. Thats
3741 * one of the reason for saving it in rx_fifo_errors, as its
3742 * potentially not a true drop.
3743 */
8d24e933 3744 netdev->stats.rx_fifo_errors += adapter->stats.rnbc;
3ea73afa 3745
9d5c8243 3746 /* RLEC on some newer hardware can be incorrect so build
8c0ab70a 3747 * our own version based on RUC and ROC */
8d24e933 3748 netdev->stats.rx_errors = adapter->stats.rxerrc +
9d5c8243
AK		 3749 adapter->stats.crcerrs + adapter->stats.algnerrc +
3750 adapter->stats.ruc + adapter->stats.roc +
3751 adapter->stats.cexterr;
8d24e933 3752 netdev->stats.rx_length_errors = adapter->stats.ruc +
9d5c8243 3753 adapter->stats.roc;
8d24e933
AK		 3754 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
3755 netdev->stats.rx_frame_errors = adapter->stats.algnerrc;
3756 netdev->stats.rx_missed_errors = adapter->stats.mpc;
9d5c8243
AK		 3757
3758 /* Tx Errors */
8d24e933 3759 netdev->stats.tx_errors = adapter->stats.ecol +
9d5c8243 3760 adapter->stats.latecol;
8d24e933
AK		 3761 netdev->stats.tx_aborted_errors = adapter->stats.ecol;
3762 netdev->stats.tx_window_errors = adapter->stats.latecol;
3763 netdev->stats.tx_carrier_errors = adapter->stats.tncrs;
9d5c8243
AK		 3764
3765 /* Tx Dropped needs to be maintained elsewhere */
3766
3767 /* Phy Stats */
3768 if (hw->phy.media_type == e1000_media_type_copper) {
3769 if ((adapter->link_speed == SPEED_1000) &&
73cd78f1 3770 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
9d5c8243
AK		 3771 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3772 adapter->phy_stats.idle_errors += phy_tmp;
3773 }
3774 }
3775
3776 /* Management Stats */
3777 adapter->stats.mgptc += rd32(E1000_MGTPTC);
3778 adapter->stats.mgprc += rd32(E1000_MGTPRC);
3779 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3780}
3781
9d5c8243
AK		 3782static irqreturn_t igb_msix_other(int irq, void *data)
3783{
3784 struct net_device *netdev = data;
3785 struct igb_adapter *adapter = netdev_priv(netdev);
3786 struct e1000_hw *hw = &adapter->hw;
844290e5 3787 u32 icr = rd32(E1000_ICR);
9d5c8243 3788
844290e5 3789 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083
AD		 3790
3791 if(icr & E1000_ICR_DOUTSYNC) {
3792 /* HW is reporting DMA is out of sync */
3793 adapter->stats.doosync++;
3794 }
eebbbdba 3795
4ae196df
AD		 3796 /* Check for a mailbox event */
3797 if (icr & E1000_ICR_VMMB)
3798 igb_msg_task(adapter);
3799
3800 if (icr & E1000_ICR_LSC) {
3801 hw->mac.get_link_status = 1;
3802 /* guard against interrupt when we're going down */
3803 if (!test_bit(__IGB_DOWN, &adapter->state))
3804 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3805 }
3806
3807 wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_VMMB);
844290e5 3808 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 3809
3810 return IRQ_HANDLED;
3811}
3812
3813static irqreturn_t igb_msix_tx(int irq, void *data)
3814{
3815 struct igb_ring *tx_ring = data;
3816 struct igb_adapter *adapter = tx_ring->adapter;
3817 struct e1000_hw *hw = &adapter->hw;
3818
421e02f0 3819#ifdef CONFIG_IGB_DCA
7dfc16fa 3820 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3821 igb_update_tx_dca(tx_ring);
3822#endif
73cd78f1 3823
9d5c8243
AK		 3824 tx_ring->total_bytes = 0;
3825 tx_ring->total_packets = 0;
661086df
PWJ		 3826
3827 /* auto mask will automatically reenable the interrupt when we write
3828 * EICS */
3b644cf6 3829 if (!igb_clean_tx_irq(tx_ring))
9d5c8243
AK		 3830 /* Ring was not completely cleaned, so fire another interrupt */
3831 wr32(E1000_EICS, tx_ring->eims_value);
661086df 3832 else
9d5c8243 3833 wr32(E1000_EIMS, tx_ring->eims_value);
661086df 3834
9d5c8243
AK		 3835 return IRQ_HANDLED;
3836}
3837
6eb5a7f1
AD		 3838static void igb_write_itr(struct igb_ring *ring)
3839{
3840 struct e1000_hw *hw = &ring->adapter->hw;
3841 if ((ring->adapter->itr_setting & 3) && ring->set_itr) {
3842 switch (hw->mac.type) {
3843 case e1000_82576:
73cd78f1 3844 wr32(ring->itr_register, ring->itr_val |
6eb5a7f1
AD		 3845 0x80000000);
3846 break;
3847 default:
73cd78f1 3848 wr32(ring->itr_register, ring->itr_val |
6eb5a7f1
AD		 3849 (ring->itr_val << 16));
3850 break;
3851 }
3852 ring->set_itr = 0;
3853 }
3854}
3855
9d5c8243
AK		 3856static irqreturn_t igb_msix_rx(int irq, void *data)
3857{
3858 struct igb_ring *rx_ring = data;
9d5c8243 3859
844290e5
PW		 3860 /* Write the ITR value calculated at the end of the
3861 * previous interrupt.
3862 */
9d5c8243 3863
6eb5a7f1 3864 igb_write_itr(rx_ring);
9d5c8243 3865
288379f0
BH		 3866 if (napi_schedule_prep(&rx_ring->napi))
3867 __napi_schedule(&rx_ring->napi);
844290e5 3868
421e02f0 3869#ifdef CONFIG_IGB_DCA
8d253320 3870 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3871 igb_update_rx_dca(rx_ring);
3872#endif
3873 return IRQ_HANDLED;
3874}
3875
421e02f0 3876#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 3877static void igb_update_rx_dca(struct igb_ring *rx_ring)
3878{
3879 u32 dca_rxctrl;
3880 struct igb_adapter *adapter = rx_ring->adapter;
3881 struct e1000_hw *hw = &adapter->hw;
3882 int cpu = get_cpu();
26bc19ec 3883 int q = rx_ring->reg_idx;
fe4506b6
JC		 3884
3885 if (rx_ring->cpu != cpu) {
3886 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
2d064c06
AD		 3887 if (hw->mac.type == e1000_82576) {
3888 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
92be7917 3889 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
2d064c06
AD		 3890 E1000_DCA_RXCTRL_CPUID_SHIFT;
3891 } else {
3892 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
92be7917 3893 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
2d064c06 3894 }
fe4506b6
JC		 3895 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
3896 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
3897 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
3898 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
3899 rx_ring->cpu = cpu;
3900 }
3901 put_cpu();
3902}
3903
3904static void igb_update_tx_dca(struct igb_ring *tx_ring)
3905{
3906 u32 dca_txctrl;
3907 struct igb_adapter *adapter = tx_ring->adapter;
3908 struct e1000_hw *hw = &adapter->hw;
3909 int cpu = get_cpu();
26bc19ec 3910 int q = tx_ring->reg_idx;
fe4506b6
JC		 3911
3912 if (tx_ring->cpu != cpu) {
3913 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
2d064c06
AD		 3914 if (hw->mac.type == e1000_82576) {
3915 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
92be7917 3916 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
2d064c06
AD		 3917 E1000_DCA_TXCTRL_CPUID_SHIFT;
3918 } else {
3919 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
92be7917 3920 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
2d064c06 3921 }
fe4506b6
JC		 3922 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
3923 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
3924 tx_ring->cpu = cpu;
3925 }
3926 put_cpu();
3927}
3928
3929static void igb_setup_dca(struct igb_adapter *adapter)
3930{
7e0e99ef 3931 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 3932 int i;
3933
7dfc16fa 3934 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 3935 return;
3936
7e0e99ef
AD		 3937 /* Always use CB2 mode, difference is masked in the CB driver. */
3938 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
3939
fe4506b6
JC		 3940 for (i = 0; i < adapter->num_tx_queues; i++) {
3941 adapter->tx_ring[i].cpu = -1;
3942 igb_update_tx_dca(&adapter->tx_ring[i]);
3943 }
3944 for (i = 0; i < adapter->num_rx_queues; i++) {
3945 adapter->rx_ring[i].cpu = -1;
3946 igb_update_rx_dca(&adapter->rx_ring[i]);
3947 }
3948}
3949
3950static int __igb_notify_dca(struct device *dev, void *data)
3951{
3952 struct net_device *netdev = dev_get_drvdata(dev);
3953 struct igb_adapter *adapter = netdev_priv(netdev);
3954 struct e1000_hw *hw = &adapter->hw;
3955 unsigned long event = *(unsigned long *)data;
3956
3957 switch (event) {
3958 case DCA_PROVIDER_ADD:
3959 /* if already enabled, don't do it again */
7dfc16fa 3960 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 3961 break;
fe4506b6
JC		 3962 /* Always use CB2 mode, difference is masked
3963 * in the CB driver. */
cbd347ad 3964 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
fe4506b6 3965 if (dca_add_requester(dev) == 0) {
bbd98fe4 3966 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 3967 dev_info(&adapter->pdev->dev, "DCA enabled\n");
3968 igb_setup_dca(adapter);
3969 break;
3970 }
3971 /* Fall Through since DCA is disabled. */
3972 case DCA_PROVIDER_REMOVE:
7dfc16fa 3973 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 3974 /* without this a class_device is left
3975 * hanging around in the sysfs model */
3976 dca_remove_requester(dev);
3977 dev_info(&adapter->pdev->dev, "DCA disabled\n");
7dfc16fa 3978 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 3979 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 3980 }
3981 break;
3982 }
bbd98fe4 3983
fe4506b6 3984 return 0;
9d5c8243
AK		 3985}
3986
fe4506b6
JC		 3987static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
3988 void *p)
3989{
3990 int ret_val;
3991
3992 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
3993 __igb_notify_dca);
3994
3995 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
3996}
421e02f0 3997#endif /* CONFIG_IGB_DCA */
9d5c8243 3998
4ae196df
AD		 3999static void igb_ping_all_vfs(struct igb_adapter *adapter)
4000{
4001 struct e1000_hw *hw = &adapter->hw;
4002 u32 ping;
4003 int i;
4004
4005 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
4006 ping = E1000_PF_CONTROL_MSG;
4007 if (adapter->vf_data[i].clear_to_send)
4008 ping |= E1000_VT_MSGTYPE_CTS;
4009 igb_write_mbx(hw, &ping, 1, i);
4010 }
4011}
4012
4013static int igb_set_vf_multicasts(struct igb_adapter *adapter,
4014 u32 *msgbuf, u32 vf)
4015{
4016 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
4017 u16 *hash_list = (u16 *)&msgbuf[1];
4018 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4019 int i;
4020
4021 /* only up to 30 hash values supported */
4022 if (n > 30)
4023 n = 30;
4024
4025 /* salt away the number of multi cast addresses assigned
4026 * to this VF for later use to restore when the PF multi cast
4027 * list changes
4028 */
4029 vf_data->num_vf_mc_hashes = n;
4030
4031 /* VFs are limited to using the MTA hash table for their multicast
4032 * addresses */
4033 for (i = 0; i < n; i++)
a419aef8 4034 vf_data->vf_mc_hashes[i] = hash_list[i];
4ae196df
AD		 4035
4036 /* Flush and reset the mta with the new values */
ff41f8dc 4037 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 4038
4039 return 0;
4040}
4041
4042static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
4043{
4044 struct e1000_hw *hw = &adapter->hw;
4045 struct vf_data_storage *vf_data;
4046 int i, j;
4047
4048 for (i = 0; i < adapter->vfs_allocated_count; i++) {
4049 vf_data = &adapter->vf_data[i];
75f4f382 4050 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
4ae196df
AD		 4051 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
4052 }
4053}
4054
4055static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
4056{
4057 struct e1000_hw *hw = &adapter->hw;
4058 u32 pool_mask, reg, vid;
4059 int i;
4060
4061 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
4062
4063 /* Find the vlan filter for this id */
4064 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4065 reg = rd32(E1000_VLVF(i));
4066
4067 /* remove the vf from the pool */
4068 reg &= ~pool_mask;
4069
4070 /* if pool is empty then remove entry from vfta */
4071 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
4072 (reg & E1000_VLVF_VLANID_ENABLE)) {
4073 reg = 0;
4074 vid = reg & E1000_VLVF_VLANID_MASK;
4075 igb_vfta_set(hw, vid, false);
4076 }
4077
4078 wr32(E1000_VLVF(i), reg);
4079 }
ae641bdc
AD		 4080
4081 adapter->vf_data[vf].vlans_enabled = 0;
4ae196df
AD		 4082}
4083
4084static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
4085{
4086 struct e1000_hw *hw = &adapter->hw;
4087 u32 reg, i;
4088
4089 /* It is an error to call this function when VFs are not enabled */
4090 if (!adapter->vfs_allocated_count)
4091 return -1;
4092
4093 /* Find the vlan filter for this id */
4094 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4095 reg = rd32(E1000_VLVF(i));
4096 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
4097 vid == (reg & E1000_VLVF_VLANID_MASK))
4098 break;
4099 }
4100
4101 if (add) {
4102 if (i == E1000_VLVF_ARRAY_SIZE) {
4103 /* Did not find a matching VLAN ID entry that was
4104 * enabled. Search for a free filter entry, i.e.
4105 * one without the enable bit set
4106 */
4107 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4108 reg = rd32(E1000_VLVF(i));
4109 if (!(reg & E1000_VLVF_VLANID_ENABLE))
4110 break;
4111 }
4112 }
4113 if (i < E1000_VLVF_ARRAY_SIZE) {
4114 /* Found an enabled/available entry */
4115 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
4116
4117 /* if !enabled we need to set this up in vfta */
4118 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
cad6d05f
AD		 4119 /* add VID to filter table, if bit already set
4120 * PF must have added it outside of table */
4121 if (igb_vfta_set(hw, vid, true))
4122 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT +
4123 adapter->vfs_allocated_count);
4ae196df
AD		 4124 reg |= E1000_VLVF_VLANID_ENABLE;
4125 }
cad6d05f
AD		 4126 reg &= ~E1000_VLVF_VLANID_MASK;
4127 reg |= vid;
4ae196df
AD		 4128
4129 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 4130
4131 /* do not modify RLPML for PF devices */
4132 if (vf >= adapter->vfs_allocated_count)
4133 return 0;
4134
4135 if (!adapter->vf_data[vf].vlans_enabled) {
4136 u32 size;
4137 reg = rd32(E1000_VMOLR(vf));
4138 size = reg & E1000_VMOLR_RLPML_MASK;
4139 size += 4;
4140 reg &= ~E1000_VMOLR_RLPML_MASK;
4141 reg |= size;
4142 wr32(E1000_VMOLR(vf), reg);
4143 }
4144 adapter->vf_data[vf].vlans_enabled++;
4145
4ae196df
AD		 4146 return 0;
4147 }
4148 } else {
4149 if (i < E1000_VLVF_ARRAY_SIZE) {
4150 /* remove vf from the pool */
4151 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
4152 /* if pool is empty then remove entry from vfta */
4153 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
4154 reg = 0;
4155 igb_vfta_set(hw, vid, false);
4156 }
4157 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 4158
4159 /* do not modify RLPML for PF devices */
4160 if (vf >= adapter->vfs_allocated_count)
4161 return 0;
4162
4163 adapter->vf_data[vf].vlans_enabled--;
4164 if (!adapter->vf_data[vf].vlans_enabled) {
4165 u32 size;
4166 reg = rd32(E1000_VMOLR(vf));
4167 size = reg & E1000_VMOLR_RLPML_MASK;
4168 size -= 4;
4169 reg &= ~E1000_VMOLR_RLPML_MASK;
4170 reg |= size;
4171 wr32(E1000_VMOLR(vf), reg);
4172 }
4ae196df
AD		 4173 return 0;
4174 }
4175 }
4176 return -1;
4177}
4178
4179static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
4180{
4181 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
4182 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
4183
4184 return igb_vlvf_set(adapter, vid, add, vf);
4185}
4186
4187static inline void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
4188{
4189 struct e1000_hw *hw = &adapter->hw;
4190
4191 /* disable mailbox functionality for vf */
4192 adapter->vf_data[vf].clear_to_send = false;
4193
4194 /* reset offloads to defaults */
4195 igb_set_vmolr(hw, vf);
4196
4197 /* reset vlans for device */
4198 igb_clear_vf_vfta(adapter, vf);
4199
4200 /* reset multicast table array for vf */
4201 adapter->vf_data[vf].num_vf_mc_hashes = 0;
4202
4203 /* Flush and reset the mta with the new values */
ff41f8dc 4204 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 4205}
4206
4207static inline void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4208{
4209 struct e1000_hw *hw = &adapter->hw;
4210 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 4211 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 4212 u32 reg, msgbuf[3];
4213 u8 *addr = (u8 *)(&msgbuf[1]);
4214
4215 /* process all the same items cleared in a function level reset */
4216 igb_vf_reset_event(adapter, vf);
4217
4218 /* set vf mac address */
26ad9178 4219 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4ae196df
AD		 4220
4221 /* enable transmit and receive for vf */
4222 reg = rd32(E1000_VFTE);
4223 wr32(E1000_VFTE, reg | (1 << vf));
4224 reg = rd32(E1000_VFRE);
4225 wr32(E1000_VFRE, reg | (1 << vf));
4226
4227 /* enable mailbox functionality for vf */
4228 adapter->vf_data[vf].clear_to_send = true;
4229
4230 /* reply to reset with ack and vf mac address */
4231 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
4232 memcpy(addr, vf_mac, 6);
4233 igb_write_mbx(hw, msgbuf, 3, vf);
4234}
4235
4236static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
4237{
4238 unsigned char *addr = (char *)&msg[1];
4239 int err = -1;
4240
4241 if (is_valid_ether_addr(addr))
4242 err = igb_set_vf_mac(adapter, vf, addr);
4243
4244 return err;
4245
4246}
4247
4248static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
4249{
4250 struct e1000_hw *hw = &adapter->hw;
4251 u32 msg = E1000_VT_MSGTYPE_NACK;
4252
4253 /* if device isn't clear to send it shouldn't be reading either */
4254 if (!adapter->vf_data[vf].clear_to_send)
4255 igb_write_mbx(hw, &msg, 1, vf);
4256}
4257
4258
4259static void igb_msg_task(struct igb_adapter *adapter)
4260{
4261 struct e1000_hw *hw = &adapter->hw;
4262 u32 vf;
4263
4264 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
4265 /* process any reset requests */
4266 if (!igb_check_for_rst(hw, vf)) {
4267 adapter->vf_data[vf].clear_to_send = false;
4268 igb_vf_reset_event(adapter, vf);
4269 }
4270
4271 /* process any messages pending */
4272 if (!igb_check_for_msg(hw, vf))
4273 igb_rcv_msg_from_vf(adapter, vf);
4274
4275 /* process any acks */
4276 if (!igb_check_for_ack(hw, vf))
4277 igb_rcv_ack_from_vf(adapter, vf);
4278
4279 }
4280}
4281
4282static int igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4283{
4284 u32 mbx_size = E1000_VFMAILBOX_SIZE;
4285 u32 msgbuf[mbx_size];
4286 struct e1000_hw *hw = &adapter->hw;
4287 s32 retval;
4288
4289 retval = igb_read_mbx(hw, msgbuf, mbx_size, vf);
4290
4291 if (retval)
4292 dev_err(&adapter->pdev->dev,
4293 "Error receiving message from VF\n");
4294
4295 /* this is a message we already processed, do nothing */
4296 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
4297 return retval;
4298
4299 /*
4300 * until the vf completes a reset it should not be
4301 * allowed to start any configuration.
4302 */
4303
4304 if (msgbuf[0] == E1000_VF_RESET) {
4305 igb_vf_reset_msg(adapter, vf);
4306
4307 return retval;
4308 }
4309
4310 if (!adapter->vf_data[vf].clear_to_send) {
4311 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4312 igb_write_mbx(hw, msgbuf, 1, vf);
4313 return retval;
4314 }
4315
4316 switch ((msgbuf[0] & 0xFFFF)) {
4317 case E1000_VF_SET_MAC_ADDR:
4318 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
4319 break;
4320 case E1000_VF_SET_MULTICAST:
4321 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
4322 break;
4323 case E1000_VF_SET_LPE:
4324 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
4325 break;
4326 case E1000_VF_SET_VLAN:
4327 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4328 break;
4329 default:
4330 dev_err(&adapter->pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4331 retval = -1;
4332 break;
4333 }
4334
4335 /* notify the VF of the results of what it sent us */
4336 if (retval)
4337 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4338 else
4339 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
4340
4341 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
4342
4343 igb_write_mbx(hw, msgbuf, 1, vf);
4344
4345 return retval;
4346}
4347
68d480c4
AD		 4348/**
4349 * igb_set_uta - Set unicast filter table address
4350 * @adapter: board private structure
4351 *
4352 * The unicast table address is a register array of 32-bit registers.
4353 * The table is meant to be used in a way similar to how the MTA is used
4354 * however due to certain limitations in the hardware it is necessary to
4355 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscous
4356 * enable bit to allow vlan tag stripping when promiscous mode is enabled
4357 **/
4358static void igb_set_uta(struct igb_adapter *adapter)
4359{
4360 struct e1000_hw *hw = &adapter->hw;
4361 int i;
4362
4363 /* The UTA table only exists on 82576 hardware and newer */
4364 if (hw->mac.type < e1000_82576)
4365 return;
4366
4367 /* we only need to do this if VMDq is enabled */
4368 if (!adapter->vfs_allocated_count)
4369 return;
4370
4371 for (i = 0; i < hw->mac.uta_reg_count; i++)
4372 array_wr32(E1000_UTA, i, ~0);
4373}
4374
9d5c8243
AK		 4375/**
4376 * igb_intr_msi - Interrupt Handler
4377 * @irq: interrupt number
4378 * @data: pointer to a network interface device structure
4379 **/
4380static irqreturn_t igb_intr_msi(int irq, void *data)
4381{
4382 struct net_device *netdev = data;
4383 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 4384 struct e1000_hw *hw = &adapter->hw;
4385 /* read ICR disables interrupts using IAM */
4386 u32 icr = rd32(E1000_ICR);
4387
6eb5a7f1 4388 igb_write_itr(adapter->rx_ring);
9d5c8243 4389
dda0e083
AD		 4390 if(icr & E1000_ICR_DOUTSYNC) {
4391 /* HW is reporting DMA is out of sync */
4392 adapter->stats.doosync++;
4393 }
4394
9d5c8243
AK		 4395 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4396 hw->mac.get_link_status = 1;
4397 if (!test_bit(__IGB_DOWN, &adapter->state))
4398 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4399 }
4400
288379f0 4401 napi_schedule(&adapter->rx_ring[0].napi);
9d5c8243
AK		 4402
4403 return IRQ_HANDLED;
4404}
4405
4406/**
4a3c6433 4407 * igb_intr - Legacy Interrupt Handler
9d5c8243
AK		 4408 * @irq: interrupt number
4409 * @data: pointer to a network interface device structure
4410 **/
4411static irqreturn_t igb_intr(int irq, void *data)
4412{
4413 struct net_device *netdev = data;
4414 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 4415 struct e1000_hw *hw = &adapter->hw;
4416 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
4417 * need for the IMC write */
4418 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 4419 if (!icr)
4420 return IRQ_NONE; /* Not our interrupt */
4421
6eb5a7f1 4422 igb_write_itr(adapter->rx_ring);
9d5c8243
AK		 4423
4424 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
4425 * not set, then the adapter didn't send an interrupt */
4426 if (!(icr & E1000_ICR_INT_ASSERTED))
4427 return IRQ_NONE;
4428
dda0e083
AD		 4429 if(icr & E1000_ICR_DOUTSYNC) {
4430 /* HW is reporting DMA is out of sync */
4431 adapter->stats.doosync++;
4432 }
4433
9d5c8243
AK		 4434 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4435 hw->mac.get_link_status = 1;
4436 /* guard against interrupt when we're going down */
4437 if (!test_bit(__IGB_DOWN, &adapter->state))
4438 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4439 }
4440
288379f0 4441 napi_schedule(&adapter->rx_ring[0].napi);
9d5c8243
AK		 4442
4443 return IRQ_HANDLED;
4444}
4445
46544258 4446static inline void igb_rx_irq_enable(struct igb_ring *rx_ring)
9d5c8243 4447{
661086df 4448 struct igb_adapter *adapter = rx_ring->adapter;
46544258 4449 struct e1000_hw *hw = &adapter->hw;
9d5c8243 4450
46544258
AD		 4451 if (adapter->itr_setting & 3) {
4452 if (adapter->num_rx_queues == 1)
6eb5a7f1 4453 igb_set_itr(adapter);
46544258
AD		 4454 else
4455 igb_update_ring_itr(rx_ring);
9d5c8243
AK		 4456 }
4457
46544258
AD		 4458 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4459 if (adapter->msix_entries)
4460 wr32(E1000_EIMS, rx_ring->eims_value);
4461 else
4462 igb_irq_enable(adapter);
4463 }
9d5c8243
AK		 4464}
4465
46544258
AD		 4466/**
4467 * igb_poll - NAPI Rx polling callback
4468 * @napi: napi polling structure
4469 * @budget: count of how many packets we should handle
4470 **/
4471static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243
AK		 4472{
4473 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
9d5c8243
AK		 4474 int work_done = 0;
4475
421e02f0 4476#ifdef CONFIG_IGB_DCA
bd38e5d1 4477 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 4478 igb_update_rx_dca(rx_ring);
4479#endif
3b644cf6 4480 igb_clean_rx_irq_adv(rx_ring, &work_done, budget);
9d5c8243 4481
46544258
AD		 4482 if (rx_ring->buddy) {
4483#ifdef CONFIG_IGB_DCA
bd38e5d1 4484 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
46544258
AD		 4485 igb_update_tx_dca(rx_ring->buddy);
4486#endif
4487 if (!igb_clean_tx_irq(rx_ring->buddy))
4488 work_done = budget;
4489 }
4490
9d5c8243 4491 /* If not enough Rx work done, exit the polling mode */
5e6d5b17 4492 if (work_done < budget) {
288379f0 4493 napi_complete(napi);
46544258 4494 igb_rx_irq_enable(rx_ring);
9d5c8243
AK		 4495 }
4496
46544258 4497 return work_done;
9d5c8243 4498}
6d8126f9 4499
33af6bcc
PO		 4500/**
4501 * igb_hwtstamp - utility function which checks for TX time stamp
4502 * @adapter: board private structure
4503 * @skb: packet that was just sent
4504 *
4505 * If we were asked to do hardware stamping and such a time stamp is
4506 * available, then it must have been for this skb here because we only
4507 * allow only one such packet into the queue.
4508 */
4509static void igb_tx_hwtstamp(struct igb_adapter *adapter, struct sk_buff *skb)
4510{
4511 union skb_shared_tx *shtx = skb_tx(skb);
4512 struct e1000_hw *hw = &adapter->hw;
4513
4514 if (unlikely(shtx->hardware)) {
4515 u32 valid = rd32(E1000_TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID;
4516 if (valid) {
4517 u64 regval = rd32(E1000_TXSTMPL);
4518 u64 ns;
4519 struct skb_shared_hwtstamps shhwtstamps;
4520
4521 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
4522 regval |= (u64)rd32(E1000_TXSTMPH) << 32;
4523 ns = timecounter_cyc2time(&adapter->clock,
4524 regval);
4525 timecompare_update(&adapter->compare, ns);
4526 shhwtstamps.hwtstamp = ns_to_ktime(ns);
4527 shhwtstamps.syststamp =
4528 timecompare_transform(&adapter->compare, ns);
4529 skb_tstamp_tx(skb, &shhwtstamps);
4530 }
33af6bcc
PO		 4531 }
4532}
4533
9d5c8243
AK		 4534/**
4535 * igb_clean_tx_irq - Reclaim resources after transmit completes
4536 * @adapter: board private structure
4537 * returns true if ring is completely cleaned
4538 **/
3b644cf6 4539static bool igb_clean_tx_irq(struct igb_ring *tx_ring)
9d5c8243 4540{
3b644cf6 4541 struct igb_adapter *adapter = tx_ring->adapter;
3b644cf6 4542 struct net_device *netdev = adapter->netdev;
0e014cb1 4543 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 4544 struct igb_buffer *buffer_info;
4545 struct sk_buff *skb;
0e014cb1 4546 union e1000_adv_tx_desc *tx_desc, *eop_desc;
9d5c8243 4547 unsigned int total_bytes = 0, total_packets = 0;
0e014cb1
AD		 4548 unsigned int i, eop, count = 0;
4549 bool cleaned = false;
9d5c8243 4550
9d5c8243 4551 i = tx_ring->next_to_clean;
0e014cb1
AD		 4552 eop = tx_ring->buffer_info[i].next_to_watch;
4553 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4554
4555 while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) &&
4556 (count < tx_ring->count)) {
4557 for (cleaned = false; !cleaned; count++) {
4558 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
9d5c8243 4559 buffer_info = &tx_ring->buffer_info[i];
0e014cb1 4560 cleaned = (i == eop);
9d5c8243
AK		 4561 skb = buffer_info->skb;
4562
4563 if (skb) {
4564 unsigned int segs, bytecount;
4565 /* gso_segs is currently only valid for tcp */
4566 segs = skb_shinfo(skb)->gso_segs ?: 1;
4567 /* multiply data chunks by size of headers */
4568 bytecount = ((segs - 1) * skb_headlen(skb)) +
4569 skb->len;
4570 total_packets += segs;
4571 total_bytes += bytecount;
33af6bcc
PO		 4572
4573 igb_tx_hwtstamp(adapter, skb);
9d5c8243
AK		 4574 }
4575
4576 igb_unmap_and_free_tx_resource(adapter, buffer_info);
0e014cb1 4577 tx_desc->wb.status = 0;
9d5c8243
AK		 4578
4579 i++;
4580 if (i == tx_ring->count)
4581 i = 0;
9d5c8243 4582 }
0e014cb1
AD		 4583 eop = tx_ring->buffer_info[i].next_to_watch;
4584 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4585 }
4586
9d5c8243
AK		 4587 tx_ring->next_to_clean = i;
4588
fc7d345d 4589 if (unlikely(count &&
9d5c8243 4590 netif_carrier_ok(netdev) &&
c493ea45 4591 igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
9d5c8243
AK		 4592 /* Make sure that anybody stopping the queue after this
4593 * sees the new next_to_clean.
4594 */
4595 smp_mb();
661086df
PWJ		 4596 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
4597 !(test_bit(__IGB_DOWN, &adapter->state))) {
4598 netif_wake_subqueue(netdev, tx_ring->queue_index);
4599 ++adapter->restart_queue;
4600 }
9d5c8243
AK		 4601 }
4602
4603 if (tx_ring->detect_tx_hung) {
4604 /* Detect a transmit hang in hardware, this serializes the
4605 * check with the clearing of time_stamp and movement of i */
4606 tx_ring->detect_tx_hung = false;
4607 if (tx_ring->buffer_info[i].time_stamp &&
4608 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
4609 (adapter->tx_timeout_factor * HZ))
4610 && !(rd32(E1000_STATUS) &
4611 E1000_STATUS_TXOFF)) {
4612
9d5c8243
AK		 4613 /* detected Tx unit hang */
4614 dev_err(&adapter->pdev->dev,
4615 "Detected Tx Unit Hang\n"
2d064c06 4616 " Tx Queue <%d>\n"
9d5c8243
AK		 4617 " TDH <%x>\n"
4618 " TDT <%x>\n"
4619 " next_to_use <%x>\n"
4620 " next_to_clean <%x>\n"
9d5c8243
AK		 4621 "buffer_info[next_to_clean]\n"
4622 " time_stamp <%lx>\n"
0e014cb1 4623 " next_to_watch <%x>\n"
9d5c8243
AK		 4624 " jiffies <%lx>\n"
4625 " desc.status <%x>\n",
2d064c06 4626 tx_ring->queue_index,
9d5c8243
AK		 4627 readl(adapter->hw.hw_addr + tx_ring->head),
4628 readl(adapter->hw.hw_addr + tx_ring->tail),
4629 tx_ring->next_to_use,
4630 tx_ring->next_to_clean,
9d5c8243 4631 tx_ring->buffer_info[i].time_stamp,
0e014cb1 4632 eop,
9d5c8243 4633 jiffies,
0e014cb1 4634 eop_desc->wb.status);
661086df 4635 netif_stop_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 4636 }
4637 }
4638 tx_ring->total_bytes += total_bytes;
4639 tx_ring->total_packets += total_packets;
e21ed353
AD		 4640 tx_ring->tx_stats.bytes += total_bytes;
4641 tx_ring->tx_stats.packets += total_packets;
8d24e933
AK		 4642 netdev->stats.tx_bytes += total_bytes;
4643 netdev->stats.tx_packets += total_packets;
0e014cb1 4644 return (count < tx_ring->count);
9d5c8243
AK		 4645}
4646
9d5c8243
AK		 4647/**
4648 * igb_receive_skb - helper function to handle rx indications
eebbbdba 4649 * @ring: pointer to receive ring receving this packet
9d5c8243 4650 * @status: descriptor status field as written by hardware
73cd78f1 4651 * @rx_desc: receive descriptor containing vlan and type information.
9d5c8243
AK		 4652 * @skb: pointer to sk_buff to be indicated to stack
4653 **/
d3352520
AD		 4654static void igb_receive_skb(struct igb_ring *ring, u8 status,
4655 union e1000_adv_rx_desc * rx_desc,
4656 struct sk_buff *skb)
4657{
4658 struct igb_adapter * adapter = ring->adapter;
4659 bool vlan_extracted = (adapter->vlgrp && (status & E1000_RXD_STAT_VP));
4660
0c8dfc83 4661 skb_record_rx_queue(skb, ring->queue_index);
182ff8df
AD		 4662 if (vlan_extracted)
4663 vlan_gro_receive(&ring->napi, adapter->vlgrp,
4664 le16_to_cpu(rx_desc->wb.upper.vlan),
4665 skb);
4666 else
4667 napi_gro_receive(&ring->napi, skb);
9d5c8243
AK		 4668}
4669
9d5c8243
AK		 4670static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
4671 u32 status_err, struct sk_buff *skb)
4672{
4673 skb->ip_summed = CHECKSUM_NONE;
4674
4675 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
7beb0146
AD		 4676 if ((status_err & E1000_RXD_STAT_IXSM) ||
4677 (adapter->flags & IGB_FLAG_RX_CSUM_DISABLED))
9d5c8243
AK		 4678 return;
4679 /* TCP/UDP checksum error bit is set */
4680 if (status_err &
4681 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
b9473560
JB		 4682 /*
4683 * work around errata with sctp packets where the TCPE aka
4684 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
4685 * packets, (aka let the stack check the crc32c)
4686 */
4687 if (!((adapter->hw.mac.type == e1000_82576) &&
4688 (skb->len == 60)))
4689 adapter->hw_csum_err++;
9d5c8243 4690 /* let the stack verify checksum errors */
9d5c8243
AK		 4691 return;
4692 }
4693 /* It must be a TCP or UDP packet with a valid checksum */
4694 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
4695 skb->ip_summed = CHECKSUM_UNNECESSARY;
4696
b9473560 4697 dev_dbg(&adapter->pdev->dev, "cksum success: bits %08X\n", status_err);
9d5c8243
AK		 4698 adapter->hw_csum_good++;
4699}
4700
2d94d8ab
AD		 4701static inline u16 igb_get_hlen(struct igb_adapter *adapter,
4702 union e1000_adv_rx_desc *rx_desc)
4703{
4704 /* HW will not DMA in data larger than the given buffer, even if it
4705 * parses the (NFS, of course) header to be larger. In that case, it
4706 * fills the header buffer and spills the rest into the page.
4707 */
4708 u16 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
4709 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
4710 if (hlen > adapter->rx_ps_hdr_size)
4711 hlen = adapter->rx_ps_hdr_size;
4712 return hlen;
4713}
4714
3b644cf6
MW		 4715static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring,
4716 int *work_done, int budget)
9d5c8243 4717{
3b644cf6 4718 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 4719 struct net_device *netdev = adapter->netdev;
33af6bcc 4720 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 4721 struct pci_dev *pdev = adapter->pdev;
4722 union e1000_adv_rx_desc *rx_desc , *next_rxd;
4723 struct igb_buffer *buffer_info , *next_buffer;
4724 struct sk_buff *skb;
9d5c8243
AK		 4725 bool cleaned = false;
4726 int cleaned_count = 0;
4727 unsigned int total_bytes = 0, total_packets = 0;
73cd78f1 4728 unsigned int i;
2d94d8ab
AD		 4729 u32 staterr;
4730 u16 length;
9d5c8243
AK		 4731
4732 i = rx_ring->next_to_clean;
69d3ca53 4733 buffer_info = &rx_ring->buffer_info[i];
9d5c8243
AK		 4734 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4735 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4736
4737 while (staterr & E1000_RXD_STAT_DD) {
4738 if (*work_done >= budget)
4739 break;
4740 (*work_done)++;
9d5c8243 4741
69d3ca53
AD		 4742 skb = buffer_info->skb;
4743 prefetch(skb->data - NET_IP_ALIGN);
4744 buffer_info->skb = NULL;
4745
4746 i++;
4747 if (i == rx_ring->count)
4748 i = 0;
4749 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
4750 prefetch(next_rxd);
4751 next_buffer = &rx_ring->buffer_info[i];
9d5c8243
AK		 4752
4753 length = le16_to_cpu(rx_desc->wb.upper.length);
4754 cleaned = true;
4755 cleaned_count++;
4756
91615f76 4757 /* this is the fast path for the non-packet split case */
bf36c1a0
AD		 4758 if (!adapter->rx_ps_hdr_size) {
4759 pci_unmap_single(pdev, buffer_info->dma,
91615f76 4760 adapter->rx_buffer_len,
bf36c1a0 4761 PCI_DMA_FROMDEVICE);
91615f76 4762 buffer_info->dma = 0;
bf36c1a0
AD		 4763 skb_put(skb, length);
4764 goto send_up;
9d5c8243
AK		 4765 }
4766
2d94d8ab
AD		 4767 if (buffer_info->dma) {
4768 u16 hlen = igb_get_hlen(adapter, rx_desc);
bf36c1a0 4769 pci_unmap_single(pdev, buffer_info->dma,
91615f76 4770 adapter->rx_ps_hdr_size,
bf36c1a0 4771 PCI_DMA_FROMDEVICE);
91615f76 4772 buffer_info->dma = 0;
bf36c1a0
AD		 4773 skb_put(skb, hlen);
4774 }
4775
4776 if (length) {
9d5c8243 4777 pci_unmap_page(pdev, buffer_info->page_dma,
bf36c1a0 4778 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9d5c8243 4779 buffer_info->page_dma = 0;
bf36c1a0
AD		 4780
4781 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
4782 buffer_info->page,
4783 buffer_info->page_offset,
4784 length);
4785
4786 if ((adapter->rx_buffer_len > (PAGE_SIZE / 2)) ||
4787 (page_count(buffer_info->page) != 1))
4788 buffer_info->page = NULL;
4789 else
4790 get_page(buffer_info->page);
9d5c8243
AK		 4791
4792 skb->len += length;
4793 skb->data_len += length;
9d5c8243 4794
bf36c1a0 4795 skb->truesize += length;
9d5c8243 4796 }
9d5c8243 4797
bf36c1a0 4798 if (!(staterr & E1000_RXD_STAT_EOP)) {
b2d56536
AD		 4799 buffer_info->skb = next_buffer->skb;
4800 buffer_info->dma = next_buffer->dma;
4801 next_buffer->skb = skb;
4802 next_buffer->dma = 0;
bf36c1a0
AD		 4803 goto next_desc;
4804 }
69d3ca53 4805send_up:
33af6bcc
PO		 4806 /*
4807 * If this bit is set, then the RX registers contain
4808 * the time stamp. No other packet will be time
4809 * stamped until we read these registers, so read the
4810 * registers to make them available again. Because
4811 * only one packet can be time stamped at a time, we
4812 * know that the register values must belong to this
4813 * one here and therefore we don't need to compare
4814 * any of the additional attributes stored for it.
4815 *
4816 * If nothing went wrong, then it should have a
4817 * skb_shared_tx that we can turn into a
4818 * skb_shared_hwtstamps.
4819 *
4820 * TODO: can time stamping be triggered (thus locking
4821 * the registers) without the packet reaching this point
4822 * here? In that case RX time stamping would get stuck.
4823 *
4824 * TODO: in "time stamp all packets" mode this bit is
4825 * not set. Need a global flag for this mode and then
4826 * always read the registers. Cannot be done without
4827 * a race condition.
4828 */
4829 if (unlikely(staterr & E1000_RXD_STAT_TS)) {
4830 u64 regval;
4831 u64 ns;
4832 struct skb_shared_hwtstamps *shhwtstamps =
4833 skb_hwtstamps(skb);
4834
4835 WARN(!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID),
4836 "igb: no RX time stamp available for time stamped packet");
4837 regval = rd32(E1000_RXSTMPL);
4838 regval |= (u64)rd32(E1000_RXSTMPH) << 32;
4839 ns = timecounter_cyc2time(&adapter->clock, regval);
4840 timecompare_update(&adapter->compare, ns);
4841 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
4842 shhwtstamps->hwtstamp = ns_to_ktime(ns);
4843 shhwtstamps->syststamp =
4844 timecompare_transform(&adapter->compare, ns);
4845 }
4846
9d5c8243
AK		 4847 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
4848 dev_kfree_skb_irq(skb);
4849 goto next_desc;
4850 }
9d5c8243
AK		 4851
4852 total_bytes += skb->len;
4853 total_packets++;
4854
4855 igb_rx_checksum_adv(adapter, staterr, skb);
4856
4857 skb->protocol = eth_type_trans(skb, netdev);
4858
d3352520 4859 igb_receive_skb(rx_ring, staterr, rx_desc, skb);
9d5c8243 4860
9d5c8243
AK		 4861next_desc:
4862 rx_desc->wb.upper.status_error = 0;
4863
4864 /* return some buffers to hardware, one at a time is too slow */
4865 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
3b644cf6 4866 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 4867 cleaned_count = 0;
4868 }
4869
4870 /* use prefetched values */
4871 rx_desc = next_rxd;
4872 buffer_info = next_buffer;
9d5c8243
AK		 4873 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4874 }
bf36c1a0 4875
9d5c8243 4876 rx_ring->next_to_clean = i;
c493ea45 4877 cleaned_count = igb_desc_unused(rx_ring);
9d5c8243
AK		 4878
4879 if (cleaned_count)
3b644cf6 4880 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 4881
4882 rx_ring->total_packets += total_packets;
4883 rx_ring->total_bytes += total_bytes;
4884 rx_ring->rx_stats.packets += total_packets;
4885 rx_ring->rx_stats.bytes += total_bytes;
8d24e933
AK		 4886 netdev->stats.rx_bytes += total_bytes;
4887 netdev->stats.rx_packets += total_packets;
9d5c8243
AK		 4888 return cleaned;
4889}
4890
9d5c8243
AK		 4891/**
4892 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
4893 * @adapter: address of board private structure
4894 **/
3b644cf6 4895static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
9d5c8243
AK		 4896 int cleaned_count)
4897{
3b644cf6 4898 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 4899 struct net_device *netdev = adapter->netdev;
4900 struct pci_dev *pdev = adapter->pdev;
4901 union e1000_adv_rx_desc *rx_desc;
4902 struct igb_buffer *buffer_info;
4903 struct sk_buff *skb;
4904 unsigned int i;
db761762 4905 int bufsz;
9d5c8243
AK		 4906
4907 i = rx_ring->next_to_use;
4908 buffer_info = &rx_ring->buffer_info[i];
4909
db761762
AD		 4910 if (adapter->rx_ps_hdr_size)
4911 bufsz = adapter->rx_ps_hdr_size;
4912 else
4913 bufsz = adapter->rx_buffer_len;
db761762 4914
9d5c8243
AK		 4915 while (cleaned_count--) {
4916 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4917
bf36c1a0 4918 if (adapter->rx_ps_hdr_size && !buffer_info->page_dma) {
9d5c8243 4919 if (!buffer_info->page) {
bf36c1a0
AD		 4920 buffer_info->page = alloc_page(GFP_ATOMIC);
4921 if (!buffer_info->page) {
4922 adapter->alloc_rx_buff_failed++;
4923 goto no_buffers;
4924 }
4925 buffer_info->page_offset = 0;
4926 } else {
4927 buffer_info->page_offset ^= PAGE_SIZE / 2;
9d5c8243
AK		 4928 }
4929 buffer_info->page_dma =
db761762 4930 pci_map_page(pdev, buffer_info->page,
bf36c1a0
AD		 4931 buffer_info->page_offset,
4932 PAGE_SIZE / 2,
9d5c8243
AK		 4933 PCI_DMA_FROMDEVICE);
4934 }
4935
4936 if (!buffer_info->skb) {
89d71a66 4937 skb = netdev_alloc_skb_ip_align(netdev, bufsz);
9d5c8243
AK		 4938 if (!skb) {
4939 adapter->alloc_rx_buff_failed++;
4940 goto no_buffers;
4941 }
4942
9d5c8243
AK		 4943 buffer_info->skb = skb;
4944 buffer_info->dma = pci_map_single(pdev, skb->data,
4945 bufsz,
4946 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 4947 }
4948 /* Refresh the desc even if buffer_addrs didn't change because
4949 * each write-back erases this info. */
4950 if (adapter->rx_ps_hdr_size) {
4951 rx_desc->read.pkt_addr =
4952 cpu_to_le64(buffer_info->page_dma);
4953 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
4954 } else {
4955 rx_desc->read.pkt_addr =
4956 cpu_to_le64(buffer_info->dma);
4957 rx_desc->read.hdr_addr = 0;
4958 }
4959
4960 i++;
4961 if (i == rx_ring->count)
4962 i = 0;
4963 buffer_info = &rx_ring->buffer_info[i];
4964 }
4965
4966no_buffers:
4967 if (rx_ring->next_to_use != i) {
4968 rx_ring->next_to_use = i;
4969 if (i == 0)
4970 i = (rx_ring->count - 1);
4971 else
4972 i--;
4973
4974 /* Force memory writes to complete before letting h/w
4975 * know there are new descriptors to fetch. (Only
4976 * applicable for weak-ordered memory model archs,
4977 * such as IA-64). */
4978 wmb();
4979 writel(i, adapter->hw.hw_addr + rx_ring->tail);
4980 }
4981}
4982
4983/**
4984 * igb_mii_ioctl -
4985 * @netdev:
4986 * @ifreq:
4987 * @cmd:
4988 **/
4989static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4990{
4991 struct igb_adapter *adapter = netdev_priv(netdev);
4992 struct mii_ioctl_data *data = if_mii(ifr);
4993
4994 if (adapter->hw.phy.media_type != e1000_media_type_copper)
4995 return -EOPNOTSUPP;
4996
4997 switch (cmd) {
4998 case SIOCGMIIPHY:
4999 data->phy_id = adapter->hw.phy.addr;
5000 break;
5001 case SIOCGMIIREG:
f5f4cf08
AD		 5002 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
5003 &data->val_out))
9d5c8243
AK		 5004 return -EIO;
5005 break;
5006 case SIOCSMIIREG:
5007 default:
5008 return -EOPNOTSUPP;
5009 }
5010 return 0;
5011}
5012
c6cb090b
PO		 5013/**
5014 * igb_hwtstamp_ioctl - control hardware time stamping
5015 * @netdev:
5016 * @ifreq:
5017 * @cmd:
5018 *
33af6bcc
PO		 5019 * Outgoing time stamping can be enabled and disabled. Play nice and
5020 * disable it when requested, although it shouldn't case any overhead
5021 * when no packet needs it. At most one packet in the queue may be
5022 * marked for time stamping, otherwise it would be impossible to tell
5023 * for sure to which packet the hardware time stamp belongs.
5024 *
5025 * Incoming time stamping has to be configured via the hardware
5026 * filters. Not all combinations are supported, in particular event
5027 * type has to be specified. Matching the kind of event packet is
5028 * not supported, with the exception of "all V2 events regardless of
5029 * level 2 or 4".
5030 *
c6cb090b
PO		 5031 **/
5032static int igb_hwtstamp_ioctl(struct net_device *netdev,
5033 struct ifreq *ifr, int cmd)
5034{
33af6bcc
PO		 5035 struct igb_adapter *adapter = netdev_priv(netdev);
5036 struct e1000_hw *hw = &adapter->hw;
c6cb090b 5037 struct hwtstamp_config config;
33af6bcc
PO		 5038 u32 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
5039 u32 tsync_rx_ctl_bit = E1000_TSYNCRXCTL_ENABLED;
5040 u32 tsync_rx_ctl_type = 0;
5041 u32 tsync_rx_cfg = 0;
5042 int is_l4 = 0;
5043 int is_l2 = 0;
5044 short port = 319; /* PTP */
5045 u32 regval;
c6cb090b
PO		 5046
5047 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
5048 return -EFAULT;
5049
5050 /* reserved for future extensions */
5051 if (config.flags)
5052 return -EINVAL;
5053
33af6bcc
PO		 5054 switch (config.tx_type) {
5055 case HWTSTAMP_TX_OFF:
5056 tsync_tx_ctl_bit = 0;
5057 break;
5058 case HWTSTAMP_TX_ON:
5059 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
5060 break;
5061 default:
5062 return -ERANGE;
5063 }
5064
5065 switch (config.rx_filter) {
5066 case HWTSTAMP_FILTER_NONE:
5067 tsync_rx_ctl_bit = 0;
5068 break;
5069 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
5070 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
5071 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
5072 case HWTSTAMP_FILTER_ALL:
5073 /*
5074 * register TSYNCRXCFG must be set, therefore it is not
5075 * possible to time stamp both Sync and Delay_Req messages
5076 * => fall back to time stamping all packets
5077 */
5078 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_ALL;
5079 config.rx_filter = HWTSTAMP_FILTER_ALL;
5080 break;
5081 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
5082 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
5083 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
5084 is_l4 = 1;
5085 break;
5086 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
5087 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
5088 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
5089 is_l4 = 1;
5090 break;
5091 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
5092 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
5093 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
5094 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE;
5095 is_l2 = 1;
5096 is_l4 = 1;
5097 config.rx_filter = HWTSTAMP_FILTER_SOME;
5098 break;
5099 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
5100 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
5101 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
5102 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE;
5103 is_l2 = 1;
5104 is_l4 = 1;
5105 config.rx_filter = HWTSTAMP_FILTER_SOME;
5106 break;
5107 case HWTSTAMP_FILTER_PTP_V2_EVENT:
5108 case HWTSTAMP_FILTER_PTP_V2_SYNC:
5109 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
5110 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_EVENT_V2;
5111 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
5112 is_l2 = 1;
5113 break;
5114 default:
5115 return -ERANGE;
5116 }
5117
5118 /* enable/disable TX */
5119 regval = rd32(E1000_TSYNCTXCTL);
5120 regval = (regval & ~E1000_TSYNCTXCTL_ENABLED) | tsync_tx_ctl_bit;
5121 wr32(E1000_TSYNCTXCTL, regval);
5122
5123 /* enable/disable RX, define which PTP packets are time stamped */
5124 regval = rd32(E1000_TSYNCRXCTL);
5125 regval = (regval & ~E1000_TSYNCRXCTL_ENABLED) | tsync_rx_ctl_bit;
5126 regval = (regval & ~0xE) | tsync_rx_ctl_type;
5127 wr32(E1000_TSYNCRXCTL, regval);
5128 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
5129
5130 /*
5131 * Ethertype Filter Queue Filter[0][15:0] = 0x88F7
5132 * (Ethertype to filter on)
5133 * Ethertype Filter Queue Filter[0][26] = 0x1 (Enable filter)
5134 * Ethertype Filter Queue Filter[0][30] = 0x1 (Enable Timestamping)
5135 */
5136 wr32(E1000_ETQF0, is_l2 ? 0x440088f7 : 0);
5137
5138 /* L4 Queue Filter[0]: only filter by source and destination port */
5139 wr32(E1000_SPQF0, htons(port));
5140 wr32(E1000_IMIREXT(0), is_l4 ?
5141 ((1<<12) | (1<<19) /* bypass size and control flags */) : 0);
5142 wr32(E1000_IMIR(0), is_l4 ?
5143 (htons(port)
5144 | (0<<16) /* immediate interrupt disabled */
5145 | 0 /* (1<<17) bit cleared: do not bypass
5146 destination port check */)
5147 : 0);
5148 wr32(E1000_FTQF0, is_l4 ?
5149 (0x11 /* UDP */
5150 | (1<<15) /* VF not compared */
5151 | (1<<27) /* Enable Timestamping */
5152 | (7<<28) /* only source port filter enabled,
5153 source/target address and protocol
5154 masked */)
5155 : ((1<<15) | (15<<28) /* all mask bits set = filter not
5156 enabled */));
5157
5158 wrfl();
5159
5160 adapter->hwtstamp_config = config;
5161
5162 /* clear TX/RX time stamp registers, just to be sure */
5163 regval = rd32(E1000_TXSTMPH);
5164 regval = rd32(E1000_RXSTMPH);
c6cb090b 5165
33af6bcc
PO		 5166 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
5167 -EFAULT : 0;
c6cb090b
PO		 5168}
5169
9d5c8243
AK		 5170/**
5171 * igb_ioctl -
5172 * @netdev:
5173 * @ifreq:
5174 * @cmd:
5175 **/
5176static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5177{
5178 switch (cmd) {
5179 case SIOCGMIIPHY:
5180 case SIOCGMIIREG:
5181 case SIOCSMIIREG:
5182 return igb_mii_ioctl(netdev, ifr, cmd);
c6cb090b
PO		 5183 case SIOCSHWTSTAMP:
5184 return igb_hwtstamp_ioctl(netdev, ifr, cmd);
9d5c8243
AK		 5185 default:
5186 return -EOPNOTSUPP;
5187 }
5188}
5189
009bc06e
AD		 5190s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
5191{
5192 struct igb_adapter *adapter = hw->back;
5193 u16 cap_offset;
5194
5195 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
5196 if (!cap_offset)
5197 return -E1000_ERR_CONFIG;
5198
5199 pci_read_config_word(adapter->pdev, cap_offset + reg, value);
5200
5201 return 0;
5202}
5203
5204s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
5205{
5206 struct igb_adapter *adapter = hw->back;
5207 u16 cap_offset;
5208
5209 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
5210 if (!cap_offset)
5211 return -E1000_ERR_CONFIG;
5212
5213 pci_write_config_word(adapter->pdev, cap_offset + reg, *value);
5214
5215 return 0;
5216}
5217
9d5c8243
AK		 5218static void igb_vlan_rx_register(struct net_device *netdev,
5219 struct vlan_group *grp)
5220{
5221 struct igb_adapter *adapter = netdev_priv(netdev);
5222 struct e1000_hw *hw = &adapter->hw;
5223 u32 ctrl, rctl;
5224
5225 igb_irq_disable(adapter);
5226 adapter->vlgrp = grp;
5227
5228 if (grp) {
5229 /* enable VLAN tag insert/strip */
5230 ctrl = rd32(E1000_CTRL);
5231 ctrl |= E1000_CTRL_VME;
5232 wr32(E1000_CTRL, ctrl);
5233
5234 /* enable VLAN receive filtering */
5235 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 5236 rctl &= ~E1000_RCTL_CFIEN;
5237 wr32(E1000_RCTL, rctl);
5238 igb_update_mng_vlan(adapter);
9d5c8243
AK		 5239 } else {
5240 /* disable VLAN tag insert/strip */
5241 ctrl = rd32(E1000_CTRL);
5242 ctrl &= ~E1000_CTRL_VME;
5243 wr32(E1000_CTRL, ctrl);
5244
9d5c8243
AK		 5245 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
5246 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
5247 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
5248 }
9d5c8243
AK		 5249 }
5250
e1739522
AD		 5251 igb_rlpml_set(adapter);
5252
9d5c8243
AK		 5253 if (!test_bit(__IGB_DOWN, &adapter->state))
5254 igb_irq_enable(adapter);
5255}
5256
5257static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
5258{
5259 struct igb_adapter *adapter = netdev_priv(netdev);
5260 struct e1000_hw *hw = &adapter->hw;
4ae196df 5261 int pf_id = adapter->vfs_allocated_count;
9d5c8243 5262
28b0759c 5263 if ((hw->mng_cookie.status &
9d5c8243
AK		 5264 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
5265 (vid == adapter->mng_vlan_id))
5266 return;
4ae196df
AD		 5267
5268 /* add vid to vlvf if sr-iov is enabled,
5269 * if that fails add directly to filter table */
5270 if (igb_vlvf_set(adapter, vid, true, pf_id))
5271 igb_vfta_set(hw, vid, true);
5272
9d5c8243
AK		 5273}
5274
5275static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
5276{
5277 struct igb_adapter *adapter = netdev_priv(netdev);
5278 struct e1000_hw *hw = &adapter->hw;
4ae196df 5279 int pf_id = adapter->vfs_allocated_count;
9d5c8243
AK		 5280
5281 igb_irq_disable(adapter);
5282 vlan_group_set_device(adapter->vlgrp, vid, NULL);
5283
5284 if (!test_bit(__IGB_DOWN, &adapter->state))
5285 igb_irq_enable(adapter);
5286
5287 if ((adapter->hw.mng_cookie.status &
5288 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
5289 (vid == adapter->mng_vlan_id)) {
5290 /* release control to f/w */
5291 igb_release_hw_control(adapter);
5292 return;
5293 }
5294
4ae196df
AD		 5295 /* remove vid from vlvf if sr-iov is enabled,
5296 * if not in vlvf remove from vfta */
5297 if (igb_vlvf_set(adapter, vid, false, pf_id))
5298 igb_vfta_set(hw, vid, false);
9d5c8243
AK		 5299}
5300
5301static void igb_restore_vlan(struct igb_adapter *adapter)
5302{
5303 igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
5304
5305 if (adapter->vlgrp) {
5306 u16 vid;
5307 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
5308 if (!vlan_group_get_device(adapter->vlgrp, vid))
5309 continue;
5310 igb_vlan_rx_add_vid(adapter->netdev, vid);
5311 }
5312 }
5313}
5314
5315int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
5316{
5317 struct e1000_mac_info *mac = &adapter->hw.mac;
5318
5319 mac->autoneg = 0;
5320
9d5c8243
AK		 5321 switch (spddplx) {
5322 case SPEED_10 + DUPLEX_HALF:
5323 mac->forced_speed_duplex = ADVERTISE_10_HALF;
5324 break;
5325 case SPEED_10 + DUPLEX_FULL:
5326 mac->forced_speed_duplex = ADVERTISE_10_FULL;
5327 break;
5328 case SPEED_100 + DUPLEX_HALF:
5329 mac->forced_speed_duplex = ADVERTISE_100_HALF;
5330 break;
5331 case SPEED_100 + DUPLEX_FULL:
5332 mac->forced_speed_duplex = ADVERTISE_100_FULL;
5333 break;
5334 case SPEED_1000 + DUPLEX_FULL:
5335 mac->autoneg = 1;
5336 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
5337 break;
5338 case SPEED_1000 + DUPLEX_HALF: /* not supported */
5339 default:
5340 dev_err(&adapter->pdev->dev,
5341 "Unsupported Speed/Duplex configuration\n");
5342 return -EINVAL;
5343 }
5344 return 0;
5345}
5346
3fe7c4c9 5347static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake)
9d5c8243
AK		 5348{
5349 struct net_device *netdev = pci_get_drvdata(pdev);
5350 struct igb_adapter *adapter = netdev_priv(netdev);
5351 struct e1000_hw *hw = &adapter->hw;
2d064c06 5352 u32 ctrl, rctl, status;
9d5c8243
AK		 5353 u32 wufc = adapter->wol;
5354#ifdef CONFIG_PM
5355 int retval = 0;
5356#endif
5357
5358 netif_device_detach(netdev);
5359
a88f10ec
AD		 5360 if (netif_running(netdev))
5361 igb_close(netdev);
5362
5363 igb_reset_interrupt_capability(adapter);
5364
5365 igb_free_queues(adapter);
9d5c8243
AK		 5366
5367#ifdef CONFIG_PM
5368 retval = pci_save_state(pdev);
5369 if (retval)
5370 return retval;
5371#endif
5372
5373 status = rd32(E1000_STATUS);
5374 if (status & E1000_STATUS_LU)
5375 wufc &= ~E1000_WUFC_LNKC;
5376
5377 if (wufc) {
5378 igb_setup_rctl(adapter);
ff41f8dc 5379 igb_set_rx_mode(netdev);
9d5c8243
AK		 5380
5381 /* turn on all-multi mode if wake on multicast is enabled */
5382 if (wufc & E1000_WUFC_MC) {
5383 rctl = rd32(E1000_RCTL);
5384 rctl |= E1000_RCTL_MPE;
5385 wr32(E1000_RCTL, rctl);
5386 }
5387
5388 ctrl = rd32(E1000_CTRL);
5389 /* advertise wake from D3Cold */
5390 #define E1000_CTRL_ADVD3WUC 0x00100000
5391 /* phy power management enable */
5392 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
5393 ctrl |= E1000_CTRL_ADVD3WUC;
5394 wr32(E1000_CTRL, ctrl);
5395
9d5c8243
AK		 5396 /* Allow time for pending master requests to run */
5397 igb_disable_pcie_master(&adapter->hw);
5398
5399 wr32(E1000_WUC, E1000_WUC_PME_EN);
5400 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 5401 } else {
5402 wr32(E1000_WUC, 0);
5403 wr32(E1000_WUFC, 0);
9d5c8243
AK		 5404 }
5405
3fe7c4c9
RW		 5406 *enable_wake = wufc || adapter->en_mng_pt;
5407 if (!*enable_wake)
2fb02a26 5408 igb_shutdown_serdes_link_82575(hw);
9d5c8243
AK		 5409
5410 /* Release control of h/w to f/w. If f/w is AMT enabled, this
5411 * would have already happened in close and is redundant. */
5412 igb_release_hw_control(adapter);
5413
5414 pci_disable_device(pdev);
5415
9d5c8243
AK		 5416 return 0;
5417}
5418
5419#ifdef CONFIG_PM
3fe7c4c9
RW		 5420static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
5421{
5422 int retval;
5423 bool wake;
5424
5425 retval = __igb_shutdown(pdev, &wake);
5426 if (retval)
5427 return retval;
5428
5429 if (wake) {
5430 pci_prepare_to_sleep(pdev);
5431 } else {
5432 pci_wake_from_d3(pdev, false);
5433 pci_set_power_state(pdev, PCI_D3hot);
5434 }
5435
5436 return 0;
5437}
5438
9d5c8243
AK		 5439static int igb_resume(struct pci_dev *pdev)
5440{
5441 struct net_device *netdev = pci_get_drvdata(pdev);
5442 struct igb_adapter *adapter = netdev_priv(netdev);
5443 struct e1000_hw *hw = &adapter->hw;
5444 u32 err;
5445
5446 pci_set_power_state(pdev, PCI_D0);
5447 pci_restore_state(pdev);
42bfd33a 5448
aed5dec3 5449 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 5450 if (err) {
5451 dev_err(&pdev->dev,
5452 "igb: Cannot enable PCI device from suspend\n");
5453 return err;
5454 }
5455 pci_set_master(pdev);
5456
5457 pci_enable_wake(pdev, PCI_D3hot, 0);
5458 pci_enable_wake(pdev, PCI_D3cold, 0);
5459
a88f10ec
AD		 5460 igb_set_interrupt_capability(adapter);
5461
5462 if (igb_alloc_queues(adapter)) {
5463 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
5464 return -ENOMEM;
9d5c8243
AK		 5465 }
5466
5467 /* e1000_power_up_phy(adapter); */
5468
5469 igb_reset(adapter);
a8564f03
AD		 5470
5471 /* let the f/w know that the h/w is now under the control of the
5472 * driver. */
5473 igb_get_hw_control(adapter);
5474
9d5c8243
AK		 5475 wr32(E1000_WUS, ~0);
5476
a88f10ec
AD		 5477 if (netif_running(netdev)) {
5478 err = igb_open(netdev);
5479 if (err)
5480 return err;
5481 }
9d5c8243
AK		 5482
5483 netif_device_attach(netdev);
5484
9d5c8243
AK		 5485 return 0;
5486}
5487#endif
5488
5489static void igb_shutdown(struct pci_dev *pdev)
5490{
3fe7c4c9
RW		 5491 bool wake;
5492
5493 __igb_shutdown(pdev, &wake);
5494
5495 if (system_state == SYSTEM_POWER_OFF) {
5496 pci_wake_from_d3(pdev, wake);
5497 pci_set_power_state(pdev, PCI_D3hot);
5498 }
9d5c8243
AK		 5499}
5500
5501#ifdef CONFIG_NET_POLL_CONTROLLER
5502/*
5503 * Polling 'interrupt' - used by things like netconsole to send skbs
5504 * without having to re-enable interrupts. It's not called while
5505 * the interrupt routine is executing.
5506 */
5507static void igb_netpoll(struct net_device *netdev)
5508{
5509 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 5510 struct e1000_hw *hw = &adapter->hw;
9d5c8243 5511 int i;
9d5c8243 5512
eebbbdba
AD		 5513 if (!adapter->msix_entries) {
5514 igb_irq_disable(adapter);
5515 napi_schedule(&adapter->rx_ring[0].napi);
5516 return;
5517 }
9d5c8243 5518
eebbbdba
AD		 5519 for (i = 0; i < adapter->num_tx_queues; i++) {
5520 struct igb_ring *tx_ring = &adapter->tx_ring[i];
5521 wr32(E1000_EIMC, tx_ring->eims_value);
5522 igb_clean_tx_irq(tx_ring);
5523 wr32(E1000_EIMS, tx_ring->eims_value);
5524 }
9d5c8243 5525
eebbbdba
AD		 5526 for (i = 0; i < adapter->num_rx_queues; i++) {
5527 struct igb_ring *rx_ring = &adapter->rx_ring[i];
5528 wr32(E1000_EIMC, rx_ring->eims_value);
5529 napi_schedule(&rx_ring->napi);
5530 }
9d5c8243
AK		 5531}
5532#endif /* CONFIG_NET_POLL_CONTROLLER */
5533
5534/**
5535 * igb_io_error_detected - called when PCI error is detected
5536 * @pdev: Pointer to PCI device
5537 * @state: The current pci connection state
5538 *
5539 * This function is called after a PCI bus error affecting
5540 * this device has been detected.
5541 */
5542static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
5543 pci_channel_state_t state)
5544{
5545 struct net_device *netdev = pci_get_drvdata(pdev);
5546 struct igb_adapter *adapter = netdev_priv(netdev);
5547
5548 netif_device_detach(netdev);
5549
59ed6eec
AD		 5550 if (state == pci_channel_io_perm_failure)
5551 return PCI_ERS_RESULT_DISCONNECT;
5552
9d5c8243
AK		 5553 if (netif_running(netdev))
5554 igb_down(adapter);
5555 pci_disable_device(pdev);
5556
5557 /* Request a slot slot reset. */
5558 return PCI_ERS_RESULT_NEED_RESET;
5559}
5560
5561/**
5562 * igb_io_slot_reset - called after the pci bus has been reset.
5563 * @pdev: Pointer to PCI device
5564 *
5565 * Restart the card from scratch, as if from a cold-boot. Implementation
5566 * resembles the first-half of the igb_resume routine.
5567 */
5568static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
5569{
5570 struct net_device *netdev = pci_get_drvdata(pdev);
5571 struct igb_adapter *adapter = netdev_priv(netdev);
5572 struct e1000_hw *hw = &adapter->hw;
40a914fa 5573 pci_ers_result_t result;
42bfd33a 5574 int err;
9d5c8243 5575
aed5dec3 5576 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 5577 dev_err(&pdev->dev,
5578 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 5579 result = PCI_ERS_RESULT_DISCONNECT;
5580 } else {
5581 pci_set_master(pdev);
5582 pci_restore_state(pdev);
9d5c8243 5583
40a914fa
AD		 5584 pci_enable_wake(pdev, PCI_D3hot, 0);
5585 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 5586
40a914fa
AD		 5587 igb_reset(adapter);
5588 wr32(E1000_WUS, ~0);
5589 result = PCI_ERS_RESULT_RECOVERED;
5590 }
9d5c8243 5591
ea943d41
JK		 5592 err = pci_cleanup_aer_uncorrect_error_status(pdev);
5593 if (err) {
5594 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
5595 "failed 0x%0x\n", err);
5596 /* non-fatal, continue */
5597 }
40a914fa
AD		 5598
5599 return result;
9d5c8243
AK		 5600}
5601
5602/**
5603 * igb_io_resume - called when traffic can start flowing again.
5604 * @pdev: Pointer to PCI device
5605 *
5606 * This callback is called when the error recovery driver tells us that
5607 * its OK to resume normal operation. Implementation resembles the
5608 * second-half of the igb_resume routine.
5609 */
5610static void igb_io_resume(struct pci_dev *pdev)
5611{
5612 struct net_device *netdev = pci_get_drvdata(pdev);
5613 struct igb_adapter *adapter = netdev_priv(netdev);
5614
9d5c8243
AK		 5615 if (netif_running(netdev)) {
5616 if (igb_up(adapter)) {
5617 dev_err(&pdev->dev, "igb_up failed after reset\n");
5618 return;
5619 }
5620 }
5621
5622 netif_device_attach(netdev);
5623
5624 /* let the f/w know that the h/w is now under the control of the
5625 * driver. */
5626 igb_get_hw_control(adapter);
9d5c8243
AK		 5627}
5628
26ad9178
AD		 5629static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
5630 u8 qsel)
5631{
5632 u32 rar_low, rar_high;
5633 struct e1000_hw *hw = &adapter->hw;
5634
5635 /* HW expects these in little endian so we reverse the byte order
5636 * from network order (big endian) to little endian
5637 */
5638 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
5639 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
5640 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
5641
5642 /* Indicate to hardware the Address is Valid. */
5643 rar_high |= E1000_RAH_AV;
5644
5645 if (hw->mac.type == e1000_82575)
5646 rar_high |= E1000_RAH_POOL_1 * qsel;
5647 else
5648 rar_high |= E1000_RAH_POOL_1 << qsel;
5649
5650 wr32(E1000_RAL(index), rar_low);
5651 wrfl();
5652 wr32(E1000_RAH(index), rar_high);
5653 wrfl();
5654}
5655
4ae196df
AD		 5656static int igb_set_vf_mac(struct igb_adapter *adapter,
5657 int vf, unsigned char *mac_addr)
5658{
5659 struct e1000_hw *hw = &adapter->hw;
ff41f8dc
AD		 5660 /* VF MAC addresses start at end of receive addresses and moves
5661 * torwards the first, as a result a collision should not be possible */
5662 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 5663
37680117 5664 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 5665
26ad9178 5666 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
4ae196df
AD		 5667
5668 return 0;
5669}
5670
5671static void igb_vmm_control(struct igb_adapter *adapter)
5672{
5673 struct e1000_hw *hw = &adapter->hw;
5674 u32 reg_data;
5675
5676 if (!adapter->vfs_allocated_count)
5677 return;
5678
5679 /* VF's need PF reset indication before they
5680 * can send/receive mail */
5681 reg_data = rd32(E1000_CTRL_EXT);
5682 reg_data |= E1000_CTRL_EXT_PFRSTD;
5683 wr32(E1000_CTRL_EXT, reg_data);
5684
5685 igb_vmdq_set_loopback_pf(hw, true);
5686 igb_vmdq_set_replication_pf(hw, true);
5687}
5688
9d5c8243 5689/* igb_main.c */
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