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igb: Add support for quad port WOL and feature flags
[mirror_ubuntu-zesty-kernel.git] / drivers / net / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/module.h>
29#include <linux/types.h>
30#include <linux/init.h>
31#include <linux/vmalloc.h>
32#include <linux/pagemap.h>
33#include <linux/netdevice.h>
9d5c8243
AK		 34#include <linux/ipv6.h>
35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
37#include <linux/mii.h>
38#include <linux/ethtool.h>
39#include <linux/if_vlan.h>
40#include <linux/pci.h>
41#include <linux/delay.h>
42#include <linux/interrupt.h>
43#include <linux/if_ether.h>
fe4506b6
JC		 44#ifdef CONFIG_DCA
45#include <linux/dca.h>
46#endif
9d5c8243
AK		 47#include "igb.h"
48
0024fd00 49#define DRV_VERSION "1.2.45-k2"
9d5c8243
AK		 50char igb_driver_name[] = "igb";
51char igb_driver_version[] = DRV_VERSION;
52static const char igb_driver_string[] =
53 "Intel(R) Gigabit Ethernet Network Driver";
2d064c06 54static const char igb_copyright[] = "Copyright (c) 2008 Intel Corporation.";
9d5c8243 55
9d5c8243
AK		 56static const struct e1000_info *igb_info_tbl[] = {
57 [board_82575] = &e1000_82575_info,
58};
59
60static struct pci_device_id igb_pci_tbl[] = {
2d064c06
AD		 61 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
62 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
63 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
68 /* required last entry */
69 {0, }
70};
71
72MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
73
74void igb_reset(struct igb_adapter *);
75static int igb_setup_all_tx_resources(struct igb_adapter *);
76static int igb_setup_all_rx_resources(struct igb_adapter *);
77static void igb_free_all_tx_resources(struct igb_adapter *);
78static void igb_free_all_rx_resources(struct igb_adapter *);
3b644cf6
MW		 79static void igb_free_tx_resources(struct igb_ring *);
80static void igb_free_rx_resources(struct igb_ring *);
9d5c8243
AK		 81void igb_update_stats(struct igb_adapter *);
82static int igb_probe(struct pci_dev *, const struct pci_device_id *);
83static void __devexit igb_remove(struct pci_dev *pdev);
84static int igb_sw_init(struct igb_adapter *);
85static int igb_open(struct net_device *);
86static int igb_close(struct net_device *);
87static void igb_configure_tx(struct igb_adapter *);
88static void igb_configure_rx(struct igb_adapter *);
89static void igb_setup_rctl(struct igb_adapter *);
90static void igb_clean_all_tx_rings(struct igb_adapter *);
91static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 92static void igb_clean_tx_ring(struct igb_ring *);
93static void igb_clean_rx_ring(struct igb_ring *);
9d5c8243
AK		 94static void igb_set_multi(struct net_device *);
95static void igb_update_phy_info(unsigned long);
96static void igb_watchdog(unsigned long);
97static void igb_watchdog_task(struct work_struct *);
98static int igb_xmit_frame_ring_adv(struct sk_buff *, struct net_device *,
99 struct igb_ring *);
100static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
101static struct net_device_stats *igb_get_stats(struct net_device *);
102static int igb_change_mtu(struct net_device *, int);
103static int igb_set_mac(struct net_device *, void *);
104static irqreturn_t igb_intr(int irq, void *);
105static irqreturn_t igb_intr_msi(int irq, void *);
106static irqreturn_t igb_msix_other(int irq, void *);
107static irqreturn_t igb_msix_rx(int irq, void *);
108static irqreturn_t igb_msix_tx(int irq, void *);
109static int igb_clean_rx_ring_msix(struct napi_struct *, int);
fe4506b6
JC		 110#ifdef CONFIG_DCA
111static void igb_update_rx_dca(struct igb_ring *);
112static void igb_update_tx_dca(struct igb_ring *);
113static void igb_setup_dca(struct igb_adapter *);
114#endif /* CONFIG_DCA */
3b644cf6 115static bool igb_clean_tx_irq(struct igb_ring *);
661086df 116static int igb_poll(struct napi_struct *, int);
3b644cf6
MW		 117static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int);
118static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
9d5c8243
AK		 119static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
120static void igb_tx_timeout(struct net_device *);
121static void igb_reset_task(struct work_struct *);
122static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
123static void igb_vlan_rx_add_vid(struct net_device *, u16);
124static void igb_vlan_rx_kill_vid(struct net_device *, u16);
125static void igb_restore_vlan(struct igb_adapter *);
126
127static int igb_suspend(struct pci_dev *, pm_message_t);
128#ifdef CONFIG_PM
129static int igb_resume(struct pci_dev *);
130#endif
131static void igb_shutdown(struct pci_dev *);
fe4506b6
JC		 132#ifdef CONFIG_DCA
133static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
134static struct notifier_block dca_notifier = {
135 .notifier_call = igb_notify_dca,
136 .next = NULL,
137 .priority = 0
138};
139#endif
9d5c8243
AK		 140
141#ifdef CONFIG_NET_POLL_CONTROLLER
142/* for netdump / net console */
143static void igb_netpoll(struct net_device *);
144#endif
145
146static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
147 pci_channel_state_t);
148static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
149static void igb_io_resume(struct pci_dev *);
150
151static struct pci_error_handlers igb_err_handler = {
152 .error_detected = igb_io_error_detected,
153 .slot_reset = igb_io_slot_reset,
154 .resume = igb_io_resume,
155};
156
157
158static struct pci_driver igb_driver = {
159 .name = igb_driver_name,
160 .id_table = igb_pci_tbl,
161 .probe = igb_probe,
162 .remove = __devexit_p(igb_remove),
163#ifdef CONFIG_PM
164 /* Power Managment Hooks */
165 .suspend = igb_suspend,
166 .resume = igb_resume,
167#endif
168 .shutdown = igb_shutdown,
169 .err_handler = &igb_err_handler
170};
171
7dfc16fa
AD		 172static int global_quad_port_a; /* global quad port a indication */
173
9d5c8243
AK		 174MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
175MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
176MODULE_LICENSE("GPL");
177MODULE_VERSION(DRV_VERSION);
178
179#ifdef DEBUG
180/**
181 * igb_get_hw_dev_name - return device name string
182 * used by hardware layer to print debugging information
183 **/
184char *igb_get_hw_dev_name(struct e1000_hw *hw)
185{
186 struct igb_adapter *adapter = hw->back;
187 return adapter->netdev->name;
188}
189#endif
190
191/**
192 * igb_init_module - Driver Registration Routine
193 *
194 * igb_init_module is the first routine called when the driver is
195 * loaded. All it does is register with the PCI subsystem.
196 **/
197static int __init igb_init_module(void)
198{
199 int ret;
200 printk(KERN_INFO "%s - version %s\n",
201 igb_driver_string, igb_driver_version);
202
203 printk(KERN_INFO "%s\n", igb_copyright);
204
7dfc16fa
AD		 205 global_quad_port_a = 0;
206
9d5c8243 207 ret = pci_register_driver(&igb_driver);
fe4506b6
JC		 208#ifdef CONFIG_DCA
209 dca_register_notify(&dca_notifier);
210#endif
9d5c8243
AK		 211 return ret;
212}
213
214module_init(igb_init_module);
215
216/**
217 * igb_exit_module - Driver Exit Cleanup Routine
218 *
219 * igb_exit_module is called just before the driver is removed
220 * from memory.
221 **/
222static void __exit igb_exit_module(void)
223{
fe4506b6
JC		 224#ifdef CONFIG_DCA
225 dca_unregister_notify(&dca_notifier);
226#endif
9d5c8243
AK		 227 pci_unregister_driver(&igb_driver);
228}
229
230module_exit(igb_exit_module);
231
232/**
233 * igb_alloc_queues - Allocate memory for all rings
234 * @adapter: board private structure to initialize
235 *
236 * We allocate one ring per queue at run-time since we don't know the
237 * number of queues at compile-time.
238 **/
239static int igb_alloc_queues(struct igb_adapter *adapter)
240{
241 int i;
242
243 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
244 sizeof(struct igb_ring), GFP_KERNEL);
245 if (!adapter->tx_ring)
246 return -ENOMEM;
247
248 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
249 sizeof(struct igb_ring), GFP_KERNEL);
250 if (!adapter->rx_ring) {
251 kfree(adapter->tx_ring);
252 return -ENOMEM;
253 }
254
661086df
PWJ		 255 for (i = 0; i < adapter->num_tx_queues; i++) {
256 struct igb_ring *ring = &(adapter->tx_ring[i]);
257 ring->adapter = adapter;
258 ring->queue_index = i;
259 }
9d5c8243
AK		 260 for (i = 0; i < adapter->num_rx_queues; i++) {
261 struct igb_ring *ring = &(adapter->rx_ring[i]);
262 ring->adapter = adapter;
844290e5 263 ring->queue_index = i;
9d5c8243
AK		 264 ring->itr_register = E1000_ITR;
265
844290e5 266 /* set a default napi handler for each rx_ring */
661086df 267 netif_napi_add(adapter->netdev, &ring->napi, igb_poll, 64);
9d5c8243
AK		 268 }
269 return 0;
270}
271
272#define IGB_N0_QUEUE -1
273static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
274 int tx_queue, int msix_vector)
275{
276 u32 msixbm = 0;
277 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 278 u32 ivar, index;
279
280 switch (hw->mac.type) {
281 case e1000_82575:
9d5c8243
AK		 282 /* The 82575 assigns vectors using a bitmask, which matches the
283 bitmask for the EICR/EIMS/EIMC registers. To assign one
284 or more queues to a vector, we write the appropriate bits
285 into the MSIXBM register for that vector. */
286 if (rx_queue > IGB_N0_QUEUE) {
287 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
288 adapter->rx_ring[rx_queue].eims_value = msixbm;
289 }
290 if (tx_queue > IGB_N0_QUEUE) {
291 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
292 adapter->tx_ring[tx_queue].eims_value =
293 E1000_EICR_TX_QUEUE0 << tx_queue;
294 }
295 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
2d064c06
AD		 296 break;
297 case e1000_82576:
298 /* Kawela uses a table-based method for assigning vectors.
299 Each queue has a single entry in the table to which we write
300 a vector number along with a "valid" bit. Sadly, the layout
301 of the table is somewhat counterintuitive. */
302 if (rx_queue > IGB_N0_QUEUE) {
303 index = (rx_queue & 0x7);
304 ivar = array_rd32(E1000_IVAR0, index);
305 if (rx_queue < 8) {
306 /* vector goes into low byte of register */
307 ivar = ivar & 0xFFFFFF00;
308 ivar |= msix_vector | E1000_IVAR_VALID;
309 } else {
310 /* vector goes into third byte of register */
311 ivar = ivar & 0xFF00FFFF;
312 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
313 }
314 adapter->rx_ring[rx_queue].eims_value= 1 << msix_vector;
315 array_wr32(E1000_IVAR0, index, ivar);
316 }
317 if (tx_queue > IGB_N0_QUEUE) {
318 index = (tx_queue & 0x7);
319 ivar = array_rd32(E1000_IVAR0, index);
320 if (tx_queue < 8) {
321 /* vector goes into second byte of register */
322 ivar = ivar & 0xFFFF00FF;
323 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
324 } else {
325 /* vector goes into high byte of register */
326 ivar = ivar & 0x00FFFFFF;
327 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
328 }
329 adapter->tx_ring[tx_queue].eims_value= 1 << msix_vector;
330 array_wr32(E1000_IVAR0, index, ivar);
331 }
332 break;
333 default:
334 BUG();
335 break;
336 }
9d5c8243
AK		 337}
338
339/**
340 * igb_configure_msix - Configure MSI-X hardware
341 *
342 * igb_configure_msix sets up the hardware to properly
343 * generate MSI-X interrupts.
344 **/
345static void igb_configure_msix(struct igb_adapter *adapter)
346{
347 u32 tmp;
348 int i, vector = 0;
349 struct e1000_hw *hw = &adapter->hw;
350
351 adapter->eims_enable_mask = 0;
2d064c06
AD		 352 if (hw->mac.type == e1000_82576)
353 /* Turn on MSI-X capability first, or our settings
354 * won't stick. And it will take days to debug. */
355 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
356 E1000_GPIE_PBA | E1000_GPIE_EIAME |
357 E1000_GPIE_NSICR);
9d5c8243
AK		 358
359 for (i = 0; i < adapter->num_tx_queues; i++) {
360 struct igb_ring *tx_ring = &adapter->tx_ring[i];
361 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
362 adapter->eims_enable_mask |= tx_ring->eims_value;
363 if (tx_ring->itr_val)
364 writel(1000000000 / (tx_ring->itr_val * 256),
365 hw->hw_addr + tx_ring->itr_register);
366 else
367 writel(1, hw->hw_addr + tx_ring->itr_register);
368 }
369
370 for (i = 0; i < adapter->num_rx_queues; i++) {
371 struct igb_ring *rx_ring = &adapter->rx_ring[i];
372 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
373 adapter->eims_enable_mask |= rx_ring->eims_value;
374 if (rx_ring->itr_val)
375 writel(1000000000 / (rx_ring->itr_val * 256),
376 hw->hw_addr + rx_ring->itr_register);
377 else
378 writel(1, hw->hw_addr + rx_ring->itr_register);
379 }
380
381
382 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 383 switch (hw->mac.type) {
384 case e1000_82575:
9d5c8243
AK		 385 array_wr32(E1000_MSIXBM(0), vector++,
386 E1000_EIMS_OTHER);
387
9d5c8243
AK		 388 tmp = rd32(E1000_CTRL_EXT);
389 /* enable MSI-X PBA support*/
390 tmp |= E1000_CTRL_EXT_PBA_CLR;
391
392 /* Auto-Mask interrupts upon ICR read. */
393 tmp |= E1000_CTRL_EXT_EIAME;
394 tmp |= E1000_CTRL_EXT_IRCA;
395
396 wr32(E1000_CTRL_EXT, tmp);
397 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
844290e5 398 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 399
2d064c06
AD		 400 break;
401
402 case e1000_82576:
403 tmp = (vector++ | E1000_IVAR_VALID) << 8;
404 wr32(E1000_IVAR_MISC, tmp);
405
406 adapter->eims_enable_mask = (1 << (vector)) - 1;
407 adapter->eims_other = 1 << (vector - 1);
408 break;
409 default:
410 /* do nothing, since nothing else supports MSI-X */
411 break;
412 } /* switch (hw->mac.type) */
9d5c8243
AK		 413 wrfl();
414}
415
416/**
417 * igb_request_msix - Initialize MSI-X interrupts
418 *
419 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
420 * kernel.
421 **/
422static int igb_request_msix(struct igb_adapter *adapter)
423{
424 struct net_device *netdev = adapter->netdev;
425 int i, err = 0, vector = 0;
426
427 vector = 0;
428
429 for (i = 0; i < adapter->num_tx_queues; i++) {
430 struct igb_ring *ring = &(adapter->tx_ring[i]);
431 sprintf(ring->name, "%s-tx%d", netdev->name, i);
432 err = request_irq(adapter->msix_entries[vector].vector,
433 &igb_msix_tx, 0, ring->name,
434 &(adapter->tx_ring[i]));
435 if (err)
436 goto out;
437 ring->itr_register = E1000_EITR(0) + (vector << 2);
438 ring->itr_val = adapter->itr;
439 vector++;
440 }
441 for (i = 0; i < adapter->num_rx_queues; i++) {
442 struct igb_ring *ring = &(adapter->rx_ring[i]);
443 if (strlen(netdev->name) < (IFNAMSIZ - 5))
444 sprintf(ring->name, "%s-rx%d", netdev->name, i);
445 else
446 memcpy(ring->name, netdev->name, IFNAMSIZ);
447 err = request_irq(adapter->msix_entries[vector].vector,
448 &igb_msix_rx, 0, ring->name,
449 &(adapter->rx_ring[i]));
450 if (err)
451 goto out;
452 ring->itr_register = E1000_EITR(0) + (vector << 2);
453 ring->itr_val = adapter->itr;
844290e5
PW		 454 /* overwrite the poll routine for MSIX, we've already done
455 * netif_napi_add */
456 ring->napi.poll = &igb_clean_rx_ring_msix;
9d5c8243
AK		 457 vector++;
458 }
459
460 err = request_irq(adapter->msix_entries[vector].vector,
461 &igb_msix_other, 0, netdev->name, netdev);
462 if (err)
463 goto out;
464
9d5c8243
AK		 465 igb_configure_msix(adapter);
466 return 0;
467out:
468 return err;
469}
470
471static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
472{
473 if (adapter->msix_entries) {
474 pci_disable_msix(adapter->pdev);
475 kfree(adapter->msix_entries);
476 adapter->msix_entries = NULL;
7dfc16fa 477 } else if (adapter->flags & IGB_FLAG_HAS_MSI)
9d5c8243
AK		 478 pci_disable_msi(adapter->pdev);
479 return;
480}
481
482
483/**
484 * igb_set_interrupt_capability - set MSI or MSI-X if supported
485 *
486 * Attempt to configure interrupts using the best available
487 * capabilities of the hardware and kernel.
488 **/
489static void igb_set_interrupt_capability(struct igb_adapter *adapter)
490{
491 int err;
492 int numvecs, i;
493
494 numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1;
495 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
496 GFP_KERNEL);
497 if (!adapter->msix_entries)
498 goto msi_only;
499
500 for (i = 0; i < numvecs; i++)
501 adapter->msix_entries[i].entry = i;
502
503 err = pci_enable_msix(adapter->pdev,
504 adapter->msix_entries,
505 numvecs);
506 if (err == 0)
507 return;
508
509 igb_reset_interrupt_capability(adapter);
510
511 /* If we can't do MSI-X, try MSI */
512msi_only:
513 adapter->num_rx_queues = 1;
661086df 514 adapter->num_tx_queues = 1;
9d5c8243 515 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 516 adapter->flags |= IGB_FLAG_HAS_MSI;
661086df
PWJ		 517
518#ifdef CONFIG_NETDEVICES_MULTIQUEUE
519 /* Notify the stack of the (possibly) reduced Tx Queue count. */
520 adapter->netdev->egress_subqueue_count = adapter->num_tx_queues;
521#endif
9d5c8243
AK		 522 return;
523}
524
525/**
526 * igb_request_irq - initialize interrupts
527 *
528 * Attempts to configure interrupts using the best available
529 * capabilities of the hardware and kernel.
530 **/
531static int igb_request_irq(struct igb_adapter *adapter)
532{
533 struct net_device *netdev = adapter->netdev;
534 struct e1000_hw *hw = &adapter->hw;
535 int err = 0;
536
537 if (adapter->msix_entries) {
538 err = igb_request_msix(adapter);
844290e5 539 if (!err)
9d5c8243 540 goto request_done;
9d5c8243
AK		 541 /* fall back to MSI */
542 igb_reset_interrupt_capability(adapter);
543 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 544 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 545 igb_free_all_tx_resources(adapter);
546 igb_free_all_rx_resources(adapter);
547 adapter->num_rx_queues = 1;
548 igb_alloc_queues(adapter);
844290e5 549 } else {
2d064c06
AD		 550 switch (hw->mac.type) {
551 case e1000_82575:
552 wr32(E1000_MSIXBM(0),
553 (E1000_EICR_RX_QUEUE0 | E1000_EIMS_OTHER));
554 break;
555 case e1000_82576:
556 wr32(E1000_IVAR0, E1000_IVAR_VALID);
557 break;
558 default:
559 break;
560 }
9d5c8243 561 }
844290e5 562
7dfc16fa 563 if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243
AK		 564 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
565 netdev->name, netdev);
566 if (!err)
567 goto request_done;
568 /* fall back to legacy interrupts */
569 igb_reset_interrupt_capability(adapter);
7dfc16fa 570 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 571 }
572
573 err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
574 netdev->name, netdev);
575
6cb5e577 576 if (err)
9d5c8243
AK		 577 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
578 err);
9d5c8243
AK		 579
580request_done:
581 return err;
582}
583
584static void igb_free_irq(struct igb_adapter *adapter)
585{
586 struct net_device *netdev = adapter->netdev;
587
588 if (adapter->msix_entries) {
589 int vector = 0, i;
590
591 for (i = 0; i < adapter->num_tx_queues; i++)
592 free_irq(adapter->msix_entries[vector++].vector,
593 &(adapter->tx_ring[i]));
594 for (i = 0; i < adapter->num_rx_queues; i++)
595 free_irq(adapter->msix_entries[vector++].vector,
596 &(adapter->rx_ring[i]));
597
598 free_irq(adapter->msix_entries[vector++].vector, netdev);
599 return;
600 }
601
602 free_irq(adapter->pdev->irq, netdev);
603}
604
605/**
606 * igb_irq_disable - Mask off interrupt generation on the NIC
607 * @adapter: board private structure
608 **/
609static void igb_irq_disable(struct igb_adapter *adapter)
610{
611 struct e1000_hw *hw = &adapter->hw;
612
613 if (adapter->msix_entries) {
844290e5 614 wr32(E1000_EIAM, 0);
9d5c8243
AK		 615 wr32(E1000_EIMC, ~0);
616 wr32(E1000_EIAC, 0);
617 }
844290e5
PW		 618
619 wr32(E1000_IAM, 0);
9d5c8243
AK		 620 wr32(E1000_IMC, ~0);
621 wrfl();
622 synchronize_irq(adapter->pdev->irq);
623}
624
625/**
626 * igb_irq_enable - Enable default interrupt generation settings
627 * @adapter: board private structure
628 **/
629static void igb_irq_enable(struct igb_adapter *adapter)
630{
631 struct e1000_hw *hw = &adapter->hw;
632
633 if (adapter->msix_entries) {
844290e5
PW		 634 wr32(E1000_EIAC, adapter->eims_enable_mask);
635 wr32(E1000_EIAM, adapter->eims_enable_mask);
636 wr32(E1000_EIMS, adapter->eims_enable_mask);
9d5c8243 637 wr32(E1000_IMS, E1000_IMS_LSC);
844290e5
PW		 638 } else {
639 wr32(E1000_IMS, IMS_ENABLE_MASK);
640 wr32(E1000_IAM, IMS_ENABLE_MASK);
641 }
9d5c8243
AK		 642}
643
644static void igb_update_mng_vlan(struct igb_adapter *adapter)
645{
646 struct net_device *netdev = adapter->netdev;
647 u16 vid = adapter->hw.mng_cookie.vlan_id;
648 u16 old_vid = adapter->mng_vlan_id;
649 if (adapter->vlgrp) {
650 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
651 if (adapter->hw.mng_cookie.status &
652 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
653 igb_vlan_rx_add_vid(netdev, vid);
654 adapter->mng_vlan_id = vid;
655 } else
656 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
657
658 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
659 (vid != old_vid) &&
660 !vlan_group_get_device(adapter->vlgrp, old_vid))
661 igb_vlan_rx_kill_vid(netdev, old_vid);
662 } else
663 adapter->mng_vlan_id = vid;
664 }
665}
666
667/**
668 * igb_release_hw_control - release control of the h/w to f/w
669 * @adapter: address of board private structure
670 *
671 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
672 * For ASF and Pass Through versions of f/w this means that the
673 * driver is no longer loaded.
674 *
675 **/
676static void igb_release_hw_control(struct igb_adapter *adapter)
677{
678 struct e1000_hw *hw = &adapter->hw;
679 u32 ctrl_ext;
680
681 /* Let firmware take over control of h/w */
682 ctrl_ext = rd32(E1000_CTRL_EXT);
683 wr32(E1000_CTRL_EXT,
684 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
685}
686
687
688/**
689 * igb_get_hw_control - get control of the h/w from f/w
690 * @adapter: address of board private structure
691 *
692 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
693 * For ASF and Pass Through versions of f/w this means that
694 * the driver is loaded.
695 *
696 **/
697static void igb_get_hw_control(struct igb_adapter *adapter)
698{
699 struct e1000_hw *hw = &adapter->hw;
700 u32 ctrl_ext;
701
702 /* Let firmware know the driver has taken over */
703 ctrl_ext = rd32(E1000_CTRL_EXT);
704 wr32(E1000_CTRL_EXT,
705 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
706}
707
708static void igb_init_manageability(struct igb_adapter *adapter)
709{
710 struct e1000_hw *hw = &adapter->hw;
711
712 if (adapter->en_mng_pt) {
713 u32 manc2h = rd32(E1000_MANC2H);
714 u32 manc = rd32(E1000_MANC);
715
9d5c8243
AK		 716 /* enable receiving management packets to the host */
717 /* this will probably generate destination unreachable messages
718 * from the host OS, but the packets will be handled on SMBUS */
719 manc |= E1000_MANC_EN_MNG2HOST;
720#define E1000_MNG2HOST_PORT_623 (1 << 5)
721#define E1000_MNG2HOST_PORT_664 (1 << 6)
722 manc2h |= E1000_MNG2HOST_PORT_623;
723 manc2h |= E1000_MNG2HOST_PORT_664;
724 wr32(E1000_MANC2H, manc2h);
725
726 wr32(E1000_MANC, manc);
727 }
728}
729
9d5c8243
AK		 730/**
731 * igb_configure - configure the hardware for RX and TX
732 * @adapter: private board structure
733 **/
734static void igb_configure(struct igb_adapter *adapter)
735{
736 struct net_device *netdev = adapter->netdev;
737 int i;
738
739 igb_get_hw_control(adapter);
740 igb_set_multi(netdev);
741
742 igb_restore_vlan(adapter);
743 igb_init_manageability(adapter);
744
745 igb_configure_tx(adapter);
746 igb_setup_rctl(adapter);
747 igb_configure_rx(adapter);
662d7205
AD		 748
749 igb_rx_fifo_flush_82575(&adapter->hw);
750
9d5c8243
AK		 751 /* call IGB_DESC_UNUSED which always leaves
752 * at least 1 descriptor unused to make sure
753 * next_to_use != next_to_clean */
754 for (i = 0; i < adapter->num_rx_queues; i++) {
755 struct igb_ring *ring = &adapter->rx_ring[i];
3b644cf6 756 igb_alloc_rx_buffers_adv(ring, IGB_DESC_UNUSED(ring));
9d5c8243
AK		 757 }
758
759
760 adapter->tx_queue_len = netdev->tx_queue_len;
761}
762
763
764/**
765 * igb_up - Open the interface and prepare it to handle traffic
766 * @adapter: board private structure
767 **/
768
769int igb_up(struct igb_adapter *adapter)
770{
771 struct e1000_hw *hw = &adapter->hw;
772 int i;
773
774 /* hardware has been reset, we need to reload some things */
775 igb_configure(adapter);
776
777 clear_bit(__IGB_DOWN, &adapter->state);
778
844290e5
PW		 779 for (i = 0; i < adapter->num_rx_queues; i++)
780 napi_enable(&adapter->rx_ring[i].napi);
781 if (adapter->msix_entries)
9d5c8243 782 igb_configure_msix(adapter);
9d5c8243
AK		 783
784 /* Clear any pending interrupts. */
785 rd32(E1000_ICR);
786 igb_irq_enable(adapter);
787
788 /* Fire a link change interrupt to start the watchdog. */
789 wr32(E1000_ICS, E1000_ICS_LSC);
790 return 0;
791}
792
793void igb_down(struct igb_adapter *adapter)
794{
795 struct e1000_hw *hw = &adapter->hw;
796 struct net_device *netdev = adapter->netdev;
797 u32 tctl, rctl;
798 int i;
799
800 /* signal that we're down so the interrupt handler does not
801 * reschedule our watchdog timer */
802 set_bit(__IGB_DOWN, &adapter->state);
803
804 /* disable receives in the hardware */
805 rctl = rd32(E1000_RCTL);
806 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
807 /* flush and sleep below */
808
809 netif_stop_queue(netdev);
661086df
PWJ		 810#ifdef CONFIG_NETDEVICES_MULTIQUEUE
811 for (i = 0; i < adapter->num_tx_queues; i++)
812 netif_stop_subqueue(netdev, i);
813#endif
9d5c8243
AK		 814
815 /* disable transmits in the hardware */
816 tctl = rd32(E1000_TCTL);
817 tctl &= ~E1000_TCTL_EN;
818 wr32(E1000_TCTL, tctl);
819 /* flush both disables and wait for them to finish */
820 wrfl();
821 msleep(10);
822
844290e5
PW		 823 for (i = 0; i < adapter->num_rx_queues; i++)
824 napi_disable(&adapter->rx_ring[i].napi);
9d5c8243 825
9d5c8243
AK		 826 igb_irq_disable(adapter);
827
828 del_timer_sync(&adapter->watchdog_timer);
829 del_timer_sync(&adapter->phy_info_timer);
830
831 netdev->tx_queue_len = adapter->tx_queue_len;
832 netif_carrier_off(netdev);
833 adapter->link_speed = 0;
834 adapter->link_duplex = 0;
835
3023682e
JK		 836 if (!pci_channel_offline(adapter->pdev))
837 igb_reset(adapter);
9d5c8243
AK		 838 igb_clean_all_tx_rings(adapter);
839 igb_clean_all_rx_rings(adapter);
840}
841
842void igb_reinit_locked(struct igb_adapter *adapter)
843{
844 WARN_ON(in_interrupt());
845 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
846 msleep(1);
847 igb_down(adapter);
848 igb_up(adapter);
849 clear_bit(__IGB_RESETTING, &adapter->state);
850}
851
852void igb_reset(struct igb_adapter *adapter)
853{
854 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 855 struct e1000_mac_info *mac = &hw->mac;
856 struct e1000_fc_info *fc = &hw->fc;
9d5c8243
AK		 857 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
858 u16 hwm;
859
860 /* Repartition Pba for greater than 9k mtu
861 * To take effect CTRL.RST is required.
862 */
2d064c06 863 if (mac->type != e1000_82576) {
9d5c8243 864 pba = E1000_PBA_34K;
2d064c06
AD		 865 }
866 else {
867 pba = E1000_PBA_64K;
868 }
9d5c8243 869
2d064c06
AD		 870 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
871 (mac->type < e1000_82576)) {
9d5c8243
AK		 872 /* adjust PBA for jumbo frames */
873 wr32(E1000_PBA, pba);
874
875 /* To maintain wire speed transmits, the Tx FIFO should be
876 * large enough to accommodate two full transmit packets,
877 * rounded up to the next 1KB and expressed in KB. Likewise,
878 * the Rx FIFO should be large enough to accommodate at least
879 * one full receive packet and is similarly rounded up and
880 * expressed in KB. */
881 pba = rd32(E1000_PBA);
882 /* upper 16 bits has Tx packet buffer allocation size in KB */
883 tx_space = pba >> 16;
884 /* lower 16 bits has Rx packet buffer allocation size in KB */
885 pba &= 0xffff;
886 /* the tx fifo also stores 16 bytes of information about the tx
887 * but don't include ethernet FCS because hardware appends it */
888 min_tx_space = (adapter->max_frame_size +
889 sizeof(struct e1000_tx_desc) -
890 ETH_FCS_LEN) * 2;
891 min_tx_space = ALIGN(min_tx_space, 1024);
892 min_tx_space >>= 10;
893 /* software strips receive CRC, so leave room for it */
894 min_rx_space = adapter->max_frame_size;
895 min_rx_space = ALIGN(min_rx_space, 1024);
896 min_rx_space >>= 10;
897
898 /* If current Tx allocation is less than the min Tx FIFO size,
899 * and the min Tx FIFO size is less than the current Rx FIFO
900 * allocation, take space away from current Rx allocation */
901 if (tx_space < min_tx_space &&
902 ((min_tx_space - tx_space) < pba)) {
903 pba = pba - (min_tx_space - tx_space);
904
905 /* if short on rx space, rx wins and must trump tx
906 * adjustment */
907 if (pba < min_rx_space)
908 pba = min_rx_space;
909 }
2d064c06 910 wr32(E1000_PBA, pba);
9d5c8243 911 }
9d5c8243
AK		 912
913 /* flow control settings */
914 /* The high water mark must be low enough to fit one full frame
915 * (or the size used for early receive) above it in the Rx FIFO.
916 * Set it to the lower of:
917 * - 90% of the Rx FIFO size, or
918 * - the full Rx FIFO size minus one full frame */
919 hwm = min(((pba << 10) * 9 / 10),
2d064c06 920 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 921
2d064c06
AD		 922 if (mac->type < e1000_82576) {
923 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
924 fc->low_water = fc->high_water - 8;
925 } else {
926 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
927 fc->low_water = fc->high_water - 16;
928 }
9d5c8243
AK		 929 fc->pause_time = 0xFFFF;
930 fc->send_xon = 1;
931 fc->type = fc->original_type;
932
933 /* Allow time for pending master requests to run */
934 adapter->hw.mac.ops.reset_hw(&adapter->hw);
935 wr32(E1000_WUC, 0);
936
937 if (adapter->hw.mac.ops.init_hw(&adapter->hw))
938 dev_err(&adapter->pdev->dev, "Hardware Error\n");
939
940 igb_update_mng_vlan(adapter);
941
942 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
943 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
944
945 igb_reset_adaptive(&adapter->hw);
68707acb
BH		 946 if (adapter->hw.phy.ops.get_phy_info)
947 adapter->hw.phy.ops.get_phy_info(&adapter->hw);
9d5c8243
AK		 948}
949
42bfd33a
TI		 950/**
951 * igb_is_need_ioport - determine if an adapter needs ioport resources or not
952 * @pdev: PCI device information struct
953 *
954 * Returns true if an adapter needs ioport resources
955 **/
956static int igb_is_need_ioport(struct pci_dev *pdev)
957{
958 switch (pdev->device) {
959 /* Currently there are no adapters that need ioport resources */
960 default:
961 return false;
962 }
963}
964
9d5c8243
AK		 965/**
966 * igb_probe - Device Initialization Routine
967 * @pdev: PCI device information struct
968 * @ent: entry in igb_pci_tbl
969 *
970 * Returns 0 on success, negative on failure
971 *
972 * igb_probe initializes an adapter identified by a pci_dev structure.
973 * The OS initialization, configuring of the adapter private structure,
974 * and a hardware reset occur.
975 **/
976static int __devinit igb_probe(struct pci_dev *pdev,
977 const struct pci_device_id *ent)
978{
979 struct net_device *netdev;
980 struct igb_adapter *adapter;
981 struct e1000_hw *hw;
982 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
983 unsigned long mmio_start, mmio_len;
9d5c8243
AK		 984 int i, err, pci_using_dac;
985 u16 eeprom_data = 0;
986 u16 eeprom_apme_mask = IGB_EEPROM_APME;
987 u32 part_num;
42bfd33a 988 int bars, need_ioport;
9d5c8243 989
42bfd33a
TI		 990 /* do not allocate ioport bars when not needed */
991 need_ioport = igb_is_need_ioport(pdev);
992 if (need_ioport) {
993 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
994 err = pci_enable_device(pdev);
995 } else {
996 bars = pci_select_bars(pdev, IORESOURCE_MEM);
997 err = pci_enable_device_mem(pdev);
998 }
9d5c8243
AK		 999 if (err)
1000 return err;
1001
1002 pci_using_dac = 0;
1003 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
1004 if (!err) {
1005 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1006 if (!err)
1007 pci_using_dac = 1;
1008 } else {
1009 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1010 if (err) {
1011 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1012 if (err) {
1013 dev_err(&pdev->dev, "No usable DMA "
1014 "configuration, aborting\n");
1015 goto err_dma;
1016 }
1017 }
1018 }
1019
42bfd33a 1020 err = pci_request_selected_regions(pdev, bars, igb_driver_name);
9d5c8243
AK		 1021 if (err)
1022 goto err_pci_reg;
1023
1024 pci_set_master(pdev);
c682fc23 1025 pci_save_state(pdev);
9d5c8243
AK		 1026
1027 err = -ENOMEM;
661086df
PWJ		 1028#ifdef CONFIG_NETDEVICES_MULTIQUEUE
1029 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), IGB_MAX_TX_QUEUES);
1030#else
9d5c8243 1031 netdev = alloc_etherdev(sizeof(struct igb_adapter));
661086df 1032#endif /* CONFIG_NETDEVICES_MULTIQUEUE */
9d5c8243
AK		 1033 if (!netdev)
1034 goto err_alloc_etherdev;
1035
1036 SET_NETDEV_DEV(netdev, &pdev->dev);
1037
1038 pci_set_drvdata(pdev, netdev);
1039 adapter = netdev_priv(netdev);
1040 adapter->netdev = netdev;
1041 adapter->pdev = pdev;
1042 hw = &adapter->hw;
1043 hw->back = adapter;
1044 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
42bfd33a
TI		 1045 adapter->bars = bars;
1046 adapter->need_ioport = need_ioport;
9d5c8243
AK		 1047
1048 mmio_start = pci_resource_start(pdev, 0);
1049 mmio_len = pci_resource_len(pdev, 0);
1050
1051 err = -EIO;
1052 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
1053 if (!adapter->hw.hw_addr)
1054 goto err_ioremap;
1055
1056 netdev->open = &igb_open;
1057 netdev->stop = &igb_close;
1058 netdev->get_stats = &igb_get_stats;
1059 netdev->set_multicast_list = &igb_set_multi;
1060 netdev->set_mac_address = &igb_set_mac;
1061 netdev->change_mtu = &igb_change_mtu;
1062 netdev->do_ioctl = &igb_ioctl;
1063 igb_set_ethtool_ops(netdev);
1064 netdev->tx_timeout = &igb_tx_timeout;
1065 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 1066 netdev->vlan_rx_register = igb_vlan_rx_register;
1067 netdev->vlan_rx_add_vid = igb_vlan_rx_add_vid;
1068 netdev->vlan_rx_kill_vid = igb_vlan_rx_kill_vid;
1069#ifdef CONFIG_NET_POLL_CONTROLLER
1070 netdev->poll_controller = igb_netpoll;
1071#endif
1072 netdev->hard_start_xmit = &igb_xmit_frame_adv;
1073
1074 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1075
1076 netdev->mem_start = mmio_start;
1077 netdev->mem_end = mmio_start + mmio_len;
1078
9d5c8243
AK		 1079 /* PCI config space info */
1080 hw->vendor_id = pdev->vendor;
1081 hw->device_id = pdev->device;
1082 hw->revision_id = pdev->revision;
1083 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1084 hw->subsystem_device_id = pdev->subsystem_device;
1085
1086 /* setup the private structure */
1087 hw->back = adapter;
1088 /* Copy the default MAC, PHY and NVM function pointers */
1089 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1090 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1091 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1092 /* Initialize skew-specific constants */
1093 err = ei->get_invariants(hw);
1094 if (err)
1095 goto err_hw_init;
1096
1097 err = igb_sw_init(adapter);
1098 if (err)
1099 goto err_sw_init;
1100
1101 igb_get_bus_info_pcie(hw);
1102
7dfc16fa
AD		 1103 /* set flags */
1104 switch (hw->mac.type) {
1105 case e1000_82576:
1106 case e1000_82575:
1107 adapter->flags |= IGB_FLAG_HAS_DCA;
1108 adapter->flags |= IGB_FLAG_NEED_CTX_IDX;
1109 break;
1110 default:
1111 break;
1112 }
1113
9d5c8243
AK		 1114 hw->phy.autoneg_wait_to_complete = false;
1115 hw->mac.adaptive_ifs = true;
1116
1117 /* Copper options */
1118 if (hw->phy.media_type == e1000_media_type_copper) {
1119 hw->phy.mdix = AUTO_ALL_MODES;
1120 hw->phy.disable_polarity_correction = false;
1121 hw->phy.ms_type = e1000_ms_hw_default;
1122 }
1123
1124 if (igb_check_reset_block(hw))
1125 dev_info(&pdev->dev,
1126 "PHY reset is blocked due to SOL/IDER session.\n");
1127
1128 netdev->features = NETIF_F_SG |
1129 NETIF_F_HW_CSUM |
1130 NETIF_F_HW_VLAN_TX |
1131 NETIF_F_HW_VLAN_RX |
1132 NETIF_F_HW_VLAN_FILTER;
1133
1134 netdev->features |= NETIF_F_TSO;
9d5c8243 1135 netdev->features |= NETIF_F_TSO6;
48f29ffc
JK		 1136
1137 netdev->vlan_features |= NETIF_F_TSO;
1138 netdev->vlan_features |= NETIF_F_TSO6;
1139 netdev->vlan_features |= NETIF_F_HW_CSUM;
1140 netdev->vlan_features |= NETIF_F_SG;
1141
9d5c8243
AK		 1142 if (pci_using_dac)
1143 netdev->features |= NETIF_F_HIGHDMA;
1144
661086df
PWJ		 1145#ifdef CONFIG_NETDEVICES_MULTIQUEUE
1146 netdev->features |= NETIF_F_MULTI_QUEUE;
1147#endif
1148
9d5c8243
AK		 1149 netdev->features |= NETIF_F_LLTX;
1150 adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1151
1152 /* before reading the NVM, reset the controller to put the device in a
1153 * known good starting state */
1154 hw->mac.ops.reset_hw(hw);
1155
1156 /* make sure the NVM is good */
1157 if (igb_validate_nvm_checksum(hw) < 0) {
1158 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1159 err = -EIO;
1160 goto err_eeprom;
1161 }
1162
1163 /* copy the MAC address out of the NVM */
1164 if (hw->mac.ops.read_mac_addr(hw))
1165 dev_err(&pdev->dev, "NVM Read Error\n");
1166
1167 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1168 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1169
1170 if (!is_valid_ether_addr(netdev->perm_addr)) {
1171 dev_err(&pdev->dev, "Invalid MAC Address\n");
1172 err = -EIO;
1173 goto err_eeprom;
1174 }
1175
1176 init_timer(&adapter->watchdog_timer);
1177 adapter->watchdog_timer.function = &igb_watchdog;
1178 adapter->watchdog_timer.data = (unsigned long) adapter;
1179
1180 init_timer(&adapter->phy_info_timer);
1181 adapter->phy_info_timer.function = &igb_update_phy_info;
1182 adapter->phy_info_timer.data = (unsigned long) adapter;
1183
1184 INIT_WORK(&adapter->reset_task, igb_reset_task);
1185 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1186
1187 /* Initialize link & ring properties that are user-changeable */
1188 adapter->tx_ring->count = 256;
1189 for (i = 0; i < adapter->num_tx_queues; i++)
1190 adapter->tx_ring[i].count = adapter->tx_ring->count;
1191 adapter->rx_ring->count = 256;
1192 for (i = 0; i < adapter->num_rx_queues; i++)
1193 adapter->rx_ring[i].count = adapter->rx_ring->count;
1194
1195 adapter->fc_autoneg = true;
1196 hw->mac.autoneg = true;
1197 hw->phy.autoneg_advertised = 0x2f;
1198
1199 hw->fc.original_type = e1000_fc_default;
1200 hw->fc.type = e1000_fc_default;
1201
1202 adapter->itr_setting = 3;
1203 adapter->itr = IGB_START_ITR;
1204
1205 igb_validate_mdi_setting(hw);
1206
1207 adapter->rx_csum = 1;
1208
1209 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1210 * enable the ACPI Magic Packet filter
1211 */
1212
1213 if (hw->bus.func == 0 ||
1214 hw->device_id == E1000_DEV_ID_82575EB_COPPER)
1215 hw->nvm.ops.read_nvm(hw, NVM_INIT_CONTROL3_PORT_A, 1,
1216 &eeprom_data);
1217
1218 if (eeprom_data & eeprom_apme_mask)
1219 adapter->eeprom_wol |= E1000_WUFC_MAG;
1220
1221 /* now that we have the eeprom settings, apply the special cases where
1222 * the eeprom may be wrong or the board simply won't support wake on
1223 * lan on a particular port */
1224 switch (pdev->device) {
1225 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1226 adapter->eeprom_wol = 0;
1227 break;
1228 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 1229 case E1000_DEV_ID_82576_FIBER:
1230 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 1231 /* Wake events only supported on port A for dual fiber
1232 * regardless of eeprom setting */
1233 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1234 adapter->eeprom_wol = 0;
1235 break;
7dfc16fa
AD		 1236 case E1000_DEV_ID_82576_QUAD_COPPER:
1237 /* if quad port adapter, disable WoL on all but port A */
1238 if (global_quad_port_a != 0)
1239 adapter->eeprom_wol = 0;
1240 else
1241 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
1242 /* Reset for multiple quad port adapters */
1243 if (++global_quad_port_a == 4)
1244 global_quad_port_a = 0;
1245 break;
9d5c8243
AK		 1246 }
1247
1248 /* initialize the wol settings based on the eeprom settings */
1249 adapter->wol = adapter->eeprom_wol;
1250
1251 /* reset the hardware with the new settings */
1252 igb_reset(adapter);
1253
1254 /* let the f/w know that the h/w is now under the control of the
1255 * driver. */
1256 igb_get_hw_control(adapter);
1257
1258 /* tell the stack to leave us alone until igb_open() is called */
1259 netif_carrier_off(netdev);
1260 netif_stop_queue(netdev);
661086df
PWJ		 1261#ifdef CONFIG_NETDEVICES_MULTIQUEUE
1262 for (i = 0; i < adapter->num_tx_queues; i++)
1263 netif_stop_subqueue(netdev, i);
1264#endif
9d5c8243
AK		 1265
1266 strcpy(netdev->name, "eth%d");
1267 err = register_netdev(netdev);
1268 if (err)
1269 goto err_register;
1270
fe4506b6 1271#ifdef CONFIG_DCA
7dfc16fa
AD		 1272 if ((adapter->flags & IGB_FLAG_HAS_DCA) &&
1273 (dca_add_requester(&pdev->dev) == 0)) {
1274 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 1275 dev_info(&pdev->dev, "DCA enabled\n");
1276 /* Always use CB2 mode, difference is masked
1277 * in the CB driver. */
1278 wr32(E1000_DCA_CTRL, 2);
1279 igb_setup_dca(adapter);
1280 }
1281#endif
1282
9d5c8243
AK		 1283 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1284 /* print bus type/speed/width info */
1285 dev_info(&pdev->dev,
1286 "%s: (PCIe:%s:%s) %02x:%02x:%02x:%02x:%02x:%02x\n",
1287 netdev->name,
1288 ((hw->bus.speed == e1000_bus_speed_2500)
1289 ? "2.5Gb/s" : "unknown"),
1290 ((hw->bus.width == e1000_bus_width_pcie_x4)
1291 ? "Width x4" : (hw->bus.width == e1000_bus_width_pcie_x1)
1292 ? "Width x1" : "unknown"),
1293 netdev->dev_addr[0], netdev->dev_addr[1], netdev->dev_addr[2],
1294 netdev->dev_addr[3], netdev->dev_addr[4], netdev->dev_addr[5]);
1295
1296 igb_read_part_num(hw, &part_num);
1297 dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1298 (part_num >> 8), (part_num & 0xff));
1299
1300 dev_info(&pdev->dev,
1301 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1302 adapter->msix_entries ? "MSI-X" :
7dfc16fa 1303 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243
AK		 1304 adapter->num_rx_queues, adapter->num_tx_queues);
1305
9d5c8243
AK		 1306 return 0;
1307
1308err_register:
1309 igb_release_hw_control(adapter);
1310err_eeprom:
1311 if (!igb_check_reset_block(hw))
1312 hw->phy.ops.reset_phy(hw);
1313
1314 if (hw->flash_address)
1315 iounmap(hw->flash_address);
1316
1317 igb_remove_device(hw);
1318 kfree(adapter->tx_ring);
1319 kfree(adapter->rx_ring);
1320err_sw_init:
1321err_hw_init:
1322 iounmap(hw->hw_addr);
1323err_ioremap:
1324 free_netdev(netdev);
1325err_alloc_etherdev:
42bfd33a 1326 pci_release_selected_regions(pdev, bars);
9d5c8243
AK		 1327err_pci_reg:
1328err_dma:
1329 pci_disable_device(pdev);
1330 return err;
1331}
1332
1333/**
1334 * igb_remove - Device Removal Routine
1335 * @pdev: PCI device information struct
1336 *
1337 * igb_remove is called by the PCI subsystem to alert the driver
1338 * that it should release a PCI device. The could be caused by a
1339 * Hot-Plug event, or because the driver is going to be removed from
1340 * memory.
1341 **/
1342static void __devexit igb_remove(struct pci_dev *pdev)
1343{
1344 struct net_device *netdev = pci_get_drvdata(pdev);
1345 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 1346 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1347
1348 /* flush_scheduled work may reschedule our watchdog task, so
1349 * explicitly disable watchdog tasks from being rescheduled */
1350 set_bit(__IGB_DOWN, &adapter->state);
1351 del_timer_sync(&adapter->watchdog_timer);
1352 del_timer_sync(&adapter->phy_info_timer);
1353
1354 flush_scheduled_work();
1355
fe4506b6 1356#ifdef CONFIG_DCA
7dfc16fa 1357 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 1358 dev_info(&pdev->dev, "DCA disabled\n");
1359 dca_remove_requester(&pdev->dev);
7dfc16fa 1360 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 1361 wr32(E1000_DCA_CTRL, 1);
1362 }
1363#endif
1364
9d5c8243
AK		 1365 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1366 * would have already happened in close and is redundant. */
1367 igb_release_hw_control(adapter);
1368
1369 unregister_netdev(netdev);
1370
1371 if (!igb_check_reset_block(&adapter->hw))
1372 adapter->hw.phy.ops.reset_phy(&adapter->hw);
1373
1374 igb_remove_device(&adapter->hw);
1375 igb_reset_interrupt_capability(adapter);
1376
1377 kfree(adapter->tx_ring);
1378 kfree(adapter->rx_ring);
1379
1380 iounmap(adapter->hw.hw_addr);
1381 if (adapter->hw.flash_address)
1382 iounmap(adapter->hw.flash_address);
42bfd33a 1383 pci_release_selected_regions(pdev, adapter->bars);
9d5c8243
AK		 1384
1385 free_netdev(netdev);
1386
1387 pci_disable_device(pdev);
1388}
1389
1390/**
1391 * igb_sw_init - Initialize general software structures (struct igb_adapter)
1392 * @adapter: board private structure to initialize
1393 *
1394 * igb_sw_init initializes the Adapter private data structure.
1395 * Fields are initialized based on PCI device information and
1396 * OS network device settings (MTU size).
1397 **/
1398static int __devinit igb_sw_init(struct igb_adapter *adapter)
1399{
1400 struct e1000_hw *hw = &adapter->hw;
1401 struct net_device *netdev = adapter->netdev;
1402 struct pci_dev *pdev = adapter->pdev;
1403
1404 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1405
1406 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1407 adapter->rx_ps_hdr_size = 0; /* disable packet split */
1408 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1409 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1410
1411 /* Number of supported queues. */
1412 /* Having more queues than CPUs doesn't make sense. */
661086df
PWJ		 1413 adapter->num_rx_queues = min((u32)IGB_MAX_RX_QUEUES, (u32)num_online_cpus());
1414#ifdef CONFIG_NETDEVICES_MULTIQUEUE
1415 adapter->num_tx_queues = min(IGB_MAX_TX_QUEUES, num_online_cpus());
1416#else
9d5c8243 1417 adapter->num_tx_queues = 1;
661086df 1418#endif /* CONFIG_NET_MULTI_QUEUE_DEVICE */
9d5c8243 1419
661086df
PWJ		 1420 /* This call may decrease the number of queues depending on
1421 * interrupt mode. */
9d5c8243
AK		 1422 igb_set_interrupt_capability(adapter);
1423
1424 if (igb_alloc_queues(adapter)) {
1425 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1426 return -ENOMEM;
1427 }
1428
1429 /* Explicitly disable IRQ since the NIC can be in any state. */
1430 igb_irq_disable(adapter);
1431
1432 set_bit(__IGB_DOWN, &adapter->state);
1433 return 0;
1434}
1435
1436/**
1437 * igb_open - Called when a network interface is made active
1438 * @netdev: network interface device structure
1439 *
1440 * Returns 0 on success, negative value on failure
1441 *
1442 * The open entry point is called when a network interface is made
1443 * active by the system (IFF_UP). At this point all resources needed
1444 * for transmit and receive operations are allocated, the interrupt
1445 * handler is registered with the OS, the watchdog timer is started,
1446 * and the stack is notified that the interface is ready.
1447 **/
1448static int igb_open(struct net_device *netdev)
1449{
1450 struct igb_adapter *adapter = netdev_priv(netdev);
1451 struct e1000_hw *hw = &adapter->hw;
1452 int err;
1453 int i;
1454
1455 /* disallow open during test */
1456 if (test_bit(__IGB_TESTING, &adapter->state))
1457 return -EBUSY;
1458
1459 /* allocate transmit descriptors */
1460 err = igb_setup_all_tx_resources(adapter);
1461 if (err)
1462 goto err_setup_tx;
1463
1464 /* allocate receive descriptors */
1465 err = igb_setup_all_rx_resources(adapter);
1466 if (err)
1467 goto err_setup_rx;
1468
1469 /* e1000_power_up_phy(adapter); */
1470
1471 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1472 if ((adapter->hw.mng_cookie.status &
1473 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1474 igb_update_mng_vlan(adapter);
1475
1476 /* before we allocate an interrupt, we must be ready to handle it.
1477 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1478 * as soon as we call pci_request_irq, so we have to setup our
1479 * clean_rx handler before we do so. */
1480 igb_configure(adapter);
1481
1482 err = igb_request_irq(adapter);
1483 if (err)
1484 goto err_req_irq;
1485
1486 /* From here on the code is the same as igb_up() */
1487 clear_bit(__IGB_DOWN, &adapter->state);
1488
844290e5
PW		 1489 for (i = 0; i < adapter->num_rx_queues; i++)
1490 napi_enable(&adapter->rx_ring[i].napi);
9d5c8243
AK		 1491
1492 /* Clear any pending interrupts. */
1493 rd32(E1000_ICR);
844290e5
PW		 1494
1495 igb_irq_enable(adapter);
1496
9d5c8243
AK		 1497 /* Fire a link status change interrupt to start the watchdog. */
1498 wr32(E1000_ICS, E1000_ICS_LSC);
1499
1500 return 0;
1501
1502err_req_irq:
1503 igb_release_hw_control(adapter);
1504 /* e1000_power_down_phy(adapter); */
1505 igb_free_all_rx_resources(adapter);
1506err_setup_rx:
1507 igb_free_all_tx_resources(adapter);
1508err_setup_tx:
1509 igb_reset(adapter);
1510
1511 return err;
1512}
1513
1514/**
1515 * igb_close - Disables a network interface
1516 * @netdev: network interface device structure
1517 *
1518 * Returns 0, this is not allowed to fail
1519 *
1520 * The close entry point is called when an interface is de-activated
1521 * by the OS. The hardware is still under the driver's control, but
1522 * needs to be disabled. A global MAC reset is issued to stop the
1523 * hardware, and all transmit and receive resources are freed.
1524 **/
1525static int igb_close(struct net_device *netdev)
1526{
1527 struct igb_adapter *adapter = netdev_priv(netdev);
1528
1529 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1530 igb_down(adapter);
1531
1532 igb_free_irq(adapter);
1533
1534 igb_free_all_tx_resources(adapter);
1535 igb_free_all_rx_resources(adapter);
1536
1537 /* kill manageability vlan ID if supported, but not if a vlan with
1538 * the same ID is registered on the host OS (let 8021q kill it) */
1539 if ((adapter->hw.mng_cookie.status &
1540 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1541 !(adapter->vlgrp &&
1542 vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1543 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1544
1545 return 0;
1546}
1547
1548/**
1549 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
1550 * @adapter: board private structure
1551 * @tx_ring: tx descriptor ring (for a specific queue) to setup
1552 *
1553 * Return 0 on success, negative on failure
1554 **/
1555
1556int igb_setup_tx_resources(struct igb_adapter *adapter,
1557 struct igb_ring *tx_ring)
1558{
1559 struct pci_dev *pdev = adapter->pdev;
1560 int size;
1561
1562 size = sizeof(struct igb_buffer) * tx_ring->count;
1563 tx_ring->buffer_info = vmalloc(size);
1564 if (!tx_ring->buffer_info)
1565 goto err;
1566 memset(tx_ring->buffer_info, 0, size);
1567
1568 /* round up to nearest 4K */
1569 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc)
1570 + sizeof(u32);
1571 tx_ring->size = ALIGN(tx_ring->size, 4096);
1572
1573 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1574 &tx_ring->dma);
1575
1576 if (!tx_ring->desc)
1577 goto err;
1578
1579 tx_ring->adapter = adapter;
1580 tx_ring->next_to_use = 0;
1581 tx_ring->next_to_clean = 0;
9d5c8243
AK		 1582 return 0;
1583
1584err:
1585 vfree(tx_ring->buffer_info);
1586 dev_err(&adapter->pdev->dev,
1587 "Unable to allocate memory for the transmit descriptor ring\n");
1588 return -ENOMEM;
1589}
1590
1591/**
1592 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1593 * (Descriptors) for all queues
1594 * @adapter: board private structure
1595 *
1596 * Return 0 on success, negative on failure
1597 **/
1598static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1599{
1600 int i, err = 0;
661086df
PWJ		 1601#ifdef CONFIG_NETDEVICES_MULTIQUEUE
1602 int r_idx;
1603#endif
9d5c8243
AK		 1604
1605 for (i = 0; i < adapter->num_tx_queues; i++) {
1606 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1607 if (err) {
1608 dev_err(&adapter->pdev->dev,
1609 "Allocation for Tx Queue %u failed\n", i);
1610 for (i--; i >= 0; i--)
3b644cf6 1611 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 1612 break;
1613 }
1614 }
1615
661086df
PWJ		 1616#ifdef CONFIG_NETDEVICES_MULTIQUEUE
1617 for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
1618 r_idx = i % adapter->num_tx_queues;
1619 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
1620 }
1621#endif
9d5c8243
AK		 1622 return err;
1623}
1624
1625/**
1626 * igb_configure_tx - Configure transmit Unit after Reset
1627 * @adapter: board private structure
1628 *
1629 * Configure the Tx unit of the MAC after a reset.
1630 **/
1631static void igb_configure_tx(struct igb_adapter *adapter)
1632{
1633 u64 tdba, tdwba;
1634 struct e1000_hw *hw = &adapter->hw;
1635 u32 tctl;
1636 u32 txdctl, txctrl;
1637 int i;
1638
1639 for (i = 0; i < adapter->num_tx_queues; i++) {
1640 struct igb_ring *ring = &(adapter->tx_ring[i]);
1641
1642 wr32(E1000_TDLEN(i),
1643 ring->count * sizeof(struct e1000_tx_desc));
1644 tdba = ring->dma;
1645 wr32(E1000_TDBAL(i),
1646 tdba & 0x00000000ffffffffULL);
1647 wr32(E1000_TDBAH(i), tdba >> 32);
1648
1649 tdwba = ring->dma + ring->count * sizeof(struct e1000_tx_desc);
1650 tdwba |= 1; /* enable head wb */
1651 wr32(E1000_TDWBAL(i),
1652 tdwba & 0x00000000ffffffffULL);
1653 wr32(E1000_TDWBAH(i), tdwba >> 32);
1654
1655 ring->head = E1000_TDH(i);
1656 ring->tail = E1000_TDT(i);
1657 writel(0, hw->hw_addr + ring->tail);
1658 writel(0, hw->hw_addr + ring->head);
1659 txdctl = rd32(E1000_TXDCTL(i));
1660 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1661 wr32(E1000_TXDCTL(i), txdctl);
1662
1663 /* Turn off Relaxed Ordering on head write-backs. The
1664 * writebacks MUST be delivered in order or it will
1665 * completely screw up our bookeeping.
1666 */
1667 txctrl = rd32(E1000_DCA_TXCTRL(i));
1668 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1669 wr32(E1000_DCA_TXCTRL(i), txctrl);
1670 }
1671
1672
1673
1674 /* Use the default values for the Tx Inter Packet Gap (IPG) timer */
1675
1676 /* Program the Transmit Control Register */
1677
1678 tctl = rd32(E1000_TCTL);
1679 tctl &= ~E1000_TCTL_CT;
1680 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1681 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1682
1683 igb_config_collision_dist(hw);
1684
1685 /* Setup Transmit Descriptor Settings for eop descriptor */
1686 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
1687
1688 /* Enable transmits */
1689 tctl |= E1000_TCTL_EN;
1690
1691 wr32(E1000_TCTL, tctl);
1692}
1693
1694/**
1695 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
1696 * @adapter: board private structure
1697 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1698 *
1699 * Returns 0 on success, negative on failure
1700 **/
1701
1702int igb_setup_rx_resources(struct igb_adapter *adapter,
1703 struct igb_ring *rx_ring)
1704{
1705 struct pci_dev *pdev = adapter->pdev;
1706 int size, desc_len;
1707
1708 size = sizeof(struct igb_buffer) * rx_ring->count;
1709 rx_ring->buffer_info = vmalloc(size);
1710 if (!rx_ring->buffer_info)
1711 goto err;
1712 memset(rx_ring->buffer_info, 0, size);
1713
1714 desc_len = sizeof(union e1000_adv_rx_desc);
1715
1716 /* Round up to nearest 4K */
1717 rx_ring->size = rx_ring->count * desc_len;
1718 rx_ring->size = ALIGN(rx_ring->size, 4096);
1719
1720 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1721 &rx_ring->dma);
1722
1723 if (!rx_ring->desc)
1724 goto err;
1725
1726 rx_ring->next_to_clean = 0;
1727 rx_ring->next_to_use = 0;
1728 rx_ring->pending_skb = NULL;
1729
1730 rx_ring->adapter = adapter;
9d5c8243
AK		 1731
1732 return 0;
1733
1734err:
1735 vfree(rx_ring->buffer_info);
1736 dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
1737 "the receive descriptor ring\n");
1738 return -ENOMEM;
1739}
1740
1741/**
1742 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
1743 * (Descriptors) for all queues
1744 * @adapter: board private structure
1745 *
1746 * Return 0 on success, negative on failure
1747 **/
1748static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
1749{
1750 int i, err = 0;
1751
1752 for (i = 0; i < adapter->num_rx_queues; i++) {
1753 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1754 if (err) {
1755 dev_err(&adapter->pdev->dev,
1756 "Allocation for Rx Queue %u failed\n", i);
1757 for (i--; i >= 0; i--)
3b644cf6 1758 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 1759 break;
1760 }
1761 }
1762
1763 return err;
1764}
1765
1766/**
1767 * igb_setup_rctl - configure the receive control registers
1768 * @adapter: Board private structure
1769 **/
1770static void igb_setup_rctl(struct igb_adapter *adapter)
1771{
1772 struct e1000_hw *hw = &adapter->hw;
1773 u32 rctl;
1774 u32 srrctl = 0;
1775 int i;
1776
1777 rctl = rd32(E1000_RCTL);
1778
1779 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
1780
1781 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
1782 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
1783 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
1784
87cb7e8c
AK		 1785 /*
1786 * enable stripping of CRC. It's unlikely this will break BMC
1787 * redirection as it did with e1000. Newer features require
1788 * that the HW strips the CRC.
9d5c8243 1789 */
87cb7e8c 1790 rctl |= E1000_RCTL_SECRC;
9d5c8243
AK		 1791
1792 rctl &= ~E1000_RCTL_SBP;
1793
1794 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1795 rctl &= ~E1000_RCTL_LPE;
1796 else
1797 rctl |= E1000_RCTL_LPE;
1798 if (adapter->rx_buffer_len <= IGB_RXBUFFER_2048) {
1799 /* Setup buffer sizes */
1800 rctl &= ~E1000_RCTL_SZ_4096;
1801 rctl |= E1000_RCTL_BSEX;
1802 switch (adapter->rx_buffer_len) {
1803 case IGB_RXBUFFER_256:
1804 rctl |= E1000_RCTL_SZ_256;
1805 rctl &= ~E1000_RCTL_BSEX;
1806 break;
1807 case IGB_RXBUFFER_512:
1808 rctl |= E1000_RCTL_SZ_512;
1809 rctl &= ~E1000_RCTL_BSEX;
1810 break;
1811 case IGB_RXBUFFER_1024:
1812 rctl |= E1000_RCTL_SZ_1024;
1813 rctl &= ~E1000_RCTL_BSEX;
1814 break;
1815 case IGB_RXBUFFER_2048:
1816 default:
1817 rctl |= E1000_RCTL_SZ_2048;
1818 rctl &= ~E1000_RCTL_BSEX;
1819 break;
1820 case IGB_RXBUFFER_4096:
1821 rctl |= E1000_RCTL_SZ_4096;
1822 break;
1823 case IGB_RXBUFFER_8192:
1824 rctl |= E1000_RCTL_SZ_8192;
1825 break;
1826 case IGB_RXBUFFER_16384:
1827 rctl |= E1000_RCTL_SZ_16384;
1828 break;
1829 }
1830 } else {
1831 rctl &= ~E1000_RCTL_BSEX;
1832 srrctl = adapter->rx_buffer_len >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1833 }
1834
1835 /* 82575 and greater support packet-split where the protocol
1836 * header is placed in skb->data and the packet data is
1837 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
1838 * In the case of a non-split, skb->data is linearly filled,
1839 * followed by the page buffers. Therefore, skb->data is
1840 * sized to hold the largest protocol header.
1841 */
1842 /* allocations using alloc_page take too long for regular MTU
1843 * so only enable packet split for jumbo frames */
1844 if (rctl & E1000_RCTL_LPE) {
1845 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
1846 srrctl = adapter->rx_ps_hdr_size <<
1847 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
1848 /* buffer size is ALWAYS one page */
1849 srrctl |= PAGE_SIZE >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1850 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1851 } else {
1852 adapter->rx_ps_hdr_size = 0;
1853 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
1854 }
1855
1856 for (i = 0; i < adapter->num_rx_queues; i++)
1857 wr32(E1000_SRRCTL(i), srrctl);
1858
1859 wr32(E1000_RCTL, rctl);
1860}
1861
1862/**
1863 * igb_configure_rx - Configure receive Unit after Reset
1864 * @adapter: board private structure
1865 *
1866 * Configure the Rx unit of the MAC after a reset.
1867 **/
1868static void igb_configure_rx(struct igb_adapter *adapter)
1869{
1870 u64 rdba;
1871 struct e1000_hw *hw = &adapter->hw;
1872 u32 rctl, rxcsum;
1873 u32 rxdctl;
1874 int i;
1875
1876 /* disable receives while setting up the descriptors */
1877 rctl = rd32(E1000_RCTL);
1878 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1879 wrfl();
1880 mdelay(10);
1881
1882 if (adapter->itr_setting > 3)
1883 wr32(E1000_ITR,
1884 1000000000 / (adapter->itr * 256));
1885
1886 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1887 * the Base and Length of the Rx Descriptor Ring */
1888 for (i = 0; i < adapter->num_rx_queues; i++) {
1889 struct igb_ring *ring = &(adapter->rx_ring[i]);
1890 rdba = ring->dma;
1891 wr32(E1000_RDBAL(i),
1892 rdba & 0x00000000ffffffffULL);
1893 wr32(E1000_RDBAH(i), rdba >> 32);
1894 wr32(E1000_RDLEN(i),
1895 ring->count * sizeof(union e1000_adv_rx_desc));
1896
1897 ring->head = E1000_RDH(i);
1898 ring->tail = E1000_RDT(i);
1899 writel(0, hw->hw_addr + ring->tail);
1900 writel(0, hw->hw_addr + ring->head);
1901
1902 rxdctl = rd32(E1000_RXDCTL(i));
1903 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
1904 rxdctl &= 0xFFF00000;
1905 rxdctl |= IGB_RX_PTHRESH;
1906 rxdctl |= IGB_RX_HTHRESH << 8;
1907 rxdctl |= IGB_RX_WTHRESH << 16;
1908 wr32(E1000_RXDCTL(i), rxdctl);
1909 }
1910
1911 if (adapter->num_rx_queues > 1) {
1912 u32 random[10];
1913 u32 mrqc;
1914 u32 j, shift;
1915 union e1000_reta {
1916 u32 dword;
1917 u8 bytes[4];
1918 } reta;
1919
1920 get_random_bytes(&random[0], 40);
1921
2d064c06
AD		 1922 if (hw->mac.type >= e1000_82576)
1923 shift = 0;
1924 else
1925 shift = 6;
9d5c8243
AK		 1926 for (j = 0; j < (32 * 4); j++) {
1927 reta.bytes[j & 3] =
1928 (j % adapter->num_rx_queues) << shift;
1929 if ((j & 3) == 3)
1930 writel(reta.dword,
1931 hw->hw_addr + E1000_RETA(0) + (j & ~3));
1932 }
1933 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
1934
1935 /* Fill out hash function seeds */
1936 for (j = 0; j < 10; j++)
1937 array_wr32(E1000_RSSRK(0), j, random[j]);
1938
1939 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
1940 E1000_MRQC_RSS_FIELD_IPV4_TCP);
1941 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
1942 E1000_MRQC_RSS_FIELD_IPV6_TCP);
1943 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
1944 E1000_MRQC_RSS_FIELD_IPV6_UDP);
1945 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
1946 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
1947
1948
1949 wr32(E1000_MRQC, mrqc);
1950
1951 /* Multiqueue and raw packet checksumming are mutually
1952 * exclusive. Note that this not the same as TCP/IP
1953 * checksumming, which works fine. */
1954 rxcsum = rd32(E1000_RXCSUM);
1955 rxcsum |= E1000_RXCSUM_PCSD;
1956 wr32(E1000_RXCSUM, rxcsum);
1957 } else {
1958 /* Enable Receive Checksum Offload for TCP and UDP */
1959 rxcsum = rd32(E1000_RXCSUM);
1960 if (adapter->rx_csum) {
1961 rxcsum |= E1000_RXCSUM_TUOFL;
1962
1963 /* Enable IPv4 payload checksum for UDP fragments
1964 * Must be used in conjunction with packet-split. */
1965 if (adapter->rx_ps_hdr_size)
1966 rxcsum |= E1000_RXCSUM_IPPCSE;
1967 } else {
1968 rxcsum &= ~E1000_RXCSUM_TUOFL;
1969 /* don't need to clear IPPCSE as it defaults to 0 */
1970 }
1971 wr32(E1000_RXCSUM, rxcsum);
1972 }
1973
1974 if (adapter->vlgrp)
1975 wr32(E1000_RLPML,
1976 adapter->max_frame_size + VLAN_TAG_SIZE);
1977 else
1978 wr32(E1000_RLPML, adapter->max_frame_size);
1979
1980 /* Enable Receives */
1981 wr32(E1000_RCTL, rctl);
1982}
1983
1984/**
1985 * igb_free_tx_resources - Free Tx Resources per Queue
1986 * @adapter: board private structure
1987 * @tx_ring: Tx descriptor ring for a specific queue
1988 *
1989 * Free all transmit software resources
1990 **/
3b644cf6 1991static void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 1992{
3b644cf6 1993 struct pci_dev *pdev = tx_ring->adapter->pdev;
9d5c8243 1994
3b644cf6 1995 igb_clean_tx_ring(tx_ring);
9d5c8243
AK		 1996
1997 vfree(tx_ring->buffer_info);
1998 tx_ring->buffer_info = NULL;
1999
2000 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
2001
2002 tx_ring->desc = NULL;
2003}
2004
2005/**
2006 * igb_free_all_tx_resources - Free Tx Resources for All Queues
2007 * @adapter: board private structure
2008 *
2009 * Free all transmit software resources
2010 **/
2011static void igb_free_all_tx_resources(struct igb_adapter *adapter)
2012{
2013 int i;
2014
2015 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2016 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 2017}
2018
2019static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
2020 struct igb_buffer *buffer_info)
2021{
2022 if (buffer_info->dma) {
2023 pci_unmap_page(adapter->pdev,
2024 buffer_info->dma,
2025 buffer_info->length,
2026 PCI_DMA_TODEVICE);
2027 buffer_info->dma = 0;
2028 }
2029 if (buffer_info->skb) {
2030 dev_kfree_skb_any(buffer_info->skb);
2031 buffer_info->skb = NULL;
2032 }
2033 buffer_info->time_stamp = 0;
2034 /* buffer_info must be completely set up in the transmit path */
2035}
2036
2037/**
2038 * igb_clean_tx_ring - Free Tx Buffers
2039 * @adapter: board private structure
2040 * @tx_ring: ring to be cleaned
2041 **/
3b644cf6 2042static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 2043{
3b644cf6 2044 struct igb_adapter *adapter = tx_ring->adapter;
9d5c8243
AK		 2045 struct igb_buffer *buffer_info;
2046 unsigned long size;
2047 unsigned int i;
2048
2049 if (!tx_ring->buffer_info)
2050 return;
2051 /* Free all the Tx ring sk_buffs */
2052
2053 for (i = 0; i < tx_ring->count; i++) {
2054 buffer_info = &tx_ring->buffer_info[i];
2055 igb_unmap_and_free_tx_resource(adapter, buffer_info);
2056 }
2057
2058 size = sizeof(struct igb_buffer) * tx_ring->count;
2059 memset(tx_ring->buffer_info, 0, size);
2060
2061 /* Zero out the descriptor ring */
2062
2063 memset(tx_ring->desc, 0, tx_ring->size);
2064
2065 tx_ring->next_to_use = 0;
2066 tx_ring->next_to_clean = 0;
2067
2068 writel(0, adapter->hw.hw_addr + tx_ring->head);
2069 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2070}
2071
2072/**
2073 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2074 * @adapter: board private structure
2075 **/
2076static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2077{
2078 int i;
2079
2080 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2081 igb_clean_tx_ring(&adapter->tx_ring[i]);
9d5c8243
AK		 2082}
2083
2084/**
2085 * igb_free_rx_resources - Free Rx Resources
2086 * @adapter: board private structure
2087 * @rx_ring: ring to clean the resources from
2088 *
2089 * Free all receive software resources
2090 **/
3b644cf6 2091static void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2092{
3b644cf6 2093 struct pci_dev *pdev = rx_ring->adapter->pdev;
9d5c8243 2094
3b644cf6 2095 igb_clean_rx_ring(rx_ring);
9d5c8243
AK		 2096
2097 vfree(rx_ring->buffer_info);
2098 rx_ring->buffer_info = NULL;
2099
2100 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2101
2102 rx_ring->desc = NULL;
2103}
2104
2105/**
2106 * igb_free_all_rx_resources - Free Rx Resources for All Queues
2107 * @adapter: board private structure
2108 *
2109 * Free all receive software resources
2110 **/
2111static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2112{
2113 int i;
2114
2115 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2116 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 2117}
2118
2119/**
2120 * igb_clean_rx_ring - Free Rx Buffers per Queue
2121 * @adapter: board private structure
2122 * @rx_ring: ring to free buffers from
2123 **/
3b644cf6 2124static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 2125{
3b644cf6 2126 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 2127 struct igb_buffer *buffer_info;
2128 struct pci_dev *pdev = adapter->pdev;
2129 unsigned long size;
2130 unsigned int i;
2131
2132 if (!rx_ring->buffer_info)
2133 return;
2134 /* Free all the Rx ring sk_buffs */
2135 for (i = 0; i < rx_ring->count; i++) {
2136 buffer_info = &rx_ring->buffer_info[i];
2137 if (buffer_info->dma) {
2138 if (adapter->rx_ps_hdr_size)
2139 pci_unmap_single(pdev, buffer_info->dma,
2140 adapter->rx_ps_hdr_size,
2141 PCI_DMA_FROMDEVICE);
2142 else
2143 pci_unmap_single(pdev, buffer_info->dma,
2144 adapter->rx_buffer_len,
2145 PCI_DMA_FROMDEVICE);
2146 buffer_info->dma = 0;
2147 }
2148
2149 if (buffer_info->skb) {
2150 dev_kfree_skb(buffer_info->skb);
2151 buffer_info->skb = NULL;
2152 }
2153 if (buffer_info->page) {
2154 pci_unmap_page(pdev, buffer_info->page_dma,
2155 PAGE_SIZE, PCI_DMA_FROMDEVICE);
2156 put_page(buffer_info->page);
2157 buffer_info->page = NULL;
2158 buffer_info->page_dma = 0;
2159 }
2160 }
2161
2162 /* there also may be some cached data from a chained receive */
2163 if (rx_ring->pending_skb) {
2164 dev_kfree_skb(rx_ring->pending_skb);
2165 rx_ring->pending_skb = NULL;
2166 }
2167
2168 size = sizeof(struct igb_buffer) * rx_ring->count;
2169 memset(rx_ring->buffer_info, 0, size);
2170
2171 /* Zero out the descriptor ring */
2172 memset(rx_ring->desc, 0, rx_ring->size);
2173
2174 rx_ring->next_to_clean = 0;
2175 rx_ring->next_to_use = 0;
2176
2177 writel(0, adapter->hw.hw_addr + rx_ring->head);
2178 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2179}
2180
2181/**
2182 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2183 * @adapter: board private structure
2184 **/
2185static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2186{
2187 int i;
2188
2189 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2190 igb_clean_rx_ring(&adapter->rx_ring[i]);
9d5c8243
AK		 2191}
2192
2193/**
2194 * igb_set_mac - Change the Ethernet Address of the NIC
2195 * @netdev: network interface device structure
2196 * @p: pointer to an address structure
2197 *
2198 * Returns 0 on success, negative on failure
2199 **/
2200static int igb_set_mac(struct net_device *netdev, void *p)
2201{
2202 struct igb_adapter *adapter = netdev_priv(netdev);
2203 struct sockaddr *addr = p;
2204
2205 if (!is_valid_ether_addr(addr->sa_data))
2206 return -EADDRNOTAVAIL;
2207
2208 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2209 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
2210
2211 adapter->hw.mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
2212
2213 return 0;
2214}
2215
2216/**
2217 * igb_set_multi - Multicast and Promiscuous mode set
2218 * @netdev: network interface device structure
2219 *
2220 * The set_multi entry point is called whenever the multicast address
2221 * list or the network interface flags are updated. This routine is
2222 * responsible for configuring the hardware for proper multicast,
2223 * promiscuous mode, and all-multi behavior.
2224 **/
2225static void igb_set_multi(struct net_device *netdev)
2226{
2227 struct igb_adapter *adapter = netdev_priv(netdev);
2228 struct e1000_hw *hw = &adapter->hw;
2229 struct e1000_mac_info *mac = &hw->mac;
2230 struct dev_mc_list *mc_ptr;
2231 u8 *mta_list;
2232 u32 rctl;
2233 int i;
2234
2235 /* Check for Promiscuous and All Multicast modes */
2236
2237 rctl = rd32(E1000_RCTL);
2238
2239 if (netdev->flags & IFF_PROMISC)
2240 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2241 else if (netdev->flags & IFF_ALLMULTI) {
2242 rctl |= E1000_RCTL_MPE;
2243 rctl &= ~E1000_RCTL_UPE;
2244 } else
2245 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
2246
2247 wr32(E1000_RCTL, rctl);
2248
2249 if (!netdev->mc_count) {
2250 /* nothing to program, so clear mc list */
2d064c06 2251 igb_update_mc_addr_list_82575(hw, NULL, 0, 1,
9d5c8243
AK		 2252 mac->rar_entry_count);
2253 return;
2254 }
2255
2256 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2257 if (!mta_list)
2258 return;
2259
2260 /* The shared function expects a packed array of only addresses. */
2261 mc_ptr = netdev->mc_list;
2262
2263 for (i = 0; i < netdev->mc_count; i++) {
2264 if (!mc_ptr)
2265 break;
2266 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2267 mc_ptr = mc_ptr->next;
2268 }
2d064c06
AD		 2269 igb_update_mc_addr_list_82575(hw, mta_list, i, 1,
2270 mac->rar_entry_count);
9d5c8243
AK		 2271 kfree(mta_list);
2272}
2273
2274/* Need to wait a few seconds after link up to get diagnostic information from
2275 * the phy */
2276static void igb_update_phy_info(unsigned long data)
2277{
2278 struct igb_adapter *adapter = (struct igb_adapter *) data;
68707acb
BH		 2279 if (adapter->hw.phy.ops.get_phy_info)
2280 adapter->hw.phy.ops.get_phy_info(&adapter->hw);
9d5c8243
AK		 2281}
2282
2283/**
2284 * igb_watchdog - Timer Call-back
2285 * @data: pointer to adapter cast into an unsigned long
2286 **/
2287static void igb_watchdog(unsigned long data)
2288{
2289 struct igb_adapter *adapter = (struct igb_adapter *)data;
2290 /* Do the rest outside of interrupt context */
2291 schedule_work(&adapter->watchdog_task);
2292}
2293
2294static void igb_watchdog_task(struct work_struct *work)
2295{
2296 struct igb_adapter *adapter = container_of(work,
2297 struct igb_adapter, watchdog_task);
2298 struct e1000_hw *hw = &adapter->hw;
2299
2300 struct net_device *netdev = adapter->netdev;
2301 struct igb_ring *tx_ring = adapter->tx_ring;
2302 struct e1000_mac_info *mac = &adapter->hw.mac;
2303 u32 link;
2304 s32 ret_val;
661086df
PWJ		 2305#ifdef CONFIG_NETDEVICES_MULTIQUEUE
2306 int i;
2307#endif
9d5c8243
AK		 2308
2309 if ((netif_carrier_ok(netdev)) &&
2310 (rd32(E1000_STATUS) & E1000_STATUS_LU))
2311 goto link_up;
2312
2313 ret_val = hw->mac.ops.check_for_link(&adapter->hw);
2314 if ((ret_val == E1000_ERR_PHY) &&
2315 (hw->phy.type == e1000_phy_igp_3) &&
2316 (rd32(E1000_CTRL) &
2317 E1000_PHY_CTRL_GBE_DISABLE))
2318 dev_info(&adapter->pdev->dev,
2319 "Gigabit has been disabled, downgrading speed\n");
2320
2321 if ((hw->phy.media_type == e1000_media_type_internal_serdes) &&
2322 !(rd32(E1000_TXCW) & E1000_TXCW_ANE))
2323 link = mac->serdes_has_link;
2324 else
2325 link = rd32(E1000_STATUS) &
2326 E1000_STATUS_LU;
2327
2328 if (link) {
2329 if (!netif_carrier_ok(netdev)) {
2330 u32 ctrl;
2331 hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2332 &adapter->link_speed,
2333 &adapter->link_duplex);
2334
2335 ctrl = rd32(E1000_CTRL);
2336 dev_info(&adapter->pdev->dev,
2337 "NIC Link is Up %d Mbps %s, "
2338 "Flow Control: %s\n",
2339 adapter->link_speed,
2340 adapter->link_duplex == FULL_DUPLEX ?
2341 "Full Duplex" : "Half Duplex",
2342 ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2343 E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2344 E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2345 E1000_CTRL_TFCE) ? "TX" : "None")));
2346
2347 /* tweak tx_queue_len according to speed/duplex and
2348 * adjust the timeout factor */
2349 netdev->tx_queue_len = adapter->tx_queue_len;
2350 adapter->tx_timeout_factor = 1;
2351 switch (adapter->link_speed) {
2352 case SPEED_10:
2353 netdev->tx_queue_len = 10;
2354 adapter->tx_timeout_factor = 14;
2355 break;
2356 case SPEED_100:
2357 netdev->tx_queue_len = 100;
2358 /* maybe add some timeout factor ? */
2359 break;
2360 }
2361
2362 netif_carrier_on(netdev);
2363 netif_wake_queue(netdev);
661086df
PWJ		 2364#ifdef CONFIG_NETDEVICES_MULTIQUEUE
2365 for (i = 0; i < adapter->num_tx_queues; i++)
2366 netif_wake_subqueue(netdev, i);
2367#endif
9d5c8243
AK		 2368
2369 if (!test_bit(__IGB_DOWN, &adapter->state))
2370 mod_timer(&adapter->phy_info_timer,
2371 round_jiffies(jiffies + 2 * HZ));
2372 }
2373 } else {
2374 if (netif_carrier_ok(netdev)) {
2375 adapter->link_speed = 0;
2376 adapter->link_duplex = 0;
2377 dev_info(&adapter->pdev->dev, "NIC Link is Down\n");
2378 netif_carrier_off(netdev);
2379 netif_stop_queue(netdev);
661086df
PWJ		 2380#ifdef CONFIG_NETDEVICES_MULTIQUEUE
2381 for (i = 0; i < adapter->num_tx_queues; i++)
2382 netif_stop_subqueue(netdev, i);
2383#endif
9d5c8243
AK		 2384 if (!test_bit(__IGB_DOWN, &adapter->state))
2385 mod_timer(&adapter->phy_info_timer,
2386 round_jiffies(jiffies + 2 * HZ));
2387 }
2388 }
2389
2390link_up:
2391 igb_update_stats(adapter);
2392
2393 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2394 adapter->tpt_old = adapter->stats.tpt;
2395 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
2396 adapter->colc_old = adapter->stats.colc;
2397
2398 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2399 adapter->gorc_old = adapter->stats.gorc;
2400 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2401 adapter->gotc_old = adapter->stats.gotc;
2402
2403 igb_update_adaptive(&adapter->hw);
2404
2405 if (!netif_carrier_ok(netdev)) {
2406 if (IGB_DESC_UNUSED(tx_ring) + 1 < tx_ring->count) {
2407 /* We've lost link, so the controller stops DMA,
2408 * but we've got queued Tx work that's never going
2409 * to get done, so reset controller to flush Tx.
2410 * (Do the reset outside of interrupt context). */
2411 adapter->tx_timeout_count++;
2412 schedule_work(&adapter->reset_task);
2413 }
2414 }
2415
2416 /* Cause software interrupt to ensure rx ring is cleaned */
2417 wr32(E1000_ICS, E1000_ICS_RXDMT0);
2418
2419 /* Force detection of hung controller every watchdog period */
2420 tx_ring->detect_tx_hung = true;
2421
2422 /* Reset the timer */
2423 if (!test_bit(__IGB_DOWN, &adapter->state))
2424 mod_timer(&adapter->watchdog_timer,
2425 round_jiffies(jiffies + 2 * HZ));
2426}
2427
2428enum latency_range {
2429 lowest_latency = 0,
2430 low_latency = 1,
2431 bulk_latency = 2,
2432 latency_invalid = 255
2433};
2434
2435
2436static void igb_lower_rx_eitr(struct igb_adapter *adapter,
2437 struct igb_ring *rx_ring)
2438{
2439 struct e1000_hw *hw = &adapter->hw;
2440 int new_val;
2441
2442 new_val = rx_ring->itr_val / 2;
2443 if (new_val < IGB_MIN_DYN_ITR)
2444 new_val = IGB_MIN_DYN_ITR;
2445
2446 if (new_val != rx_ring->itr_val) {
2447 rx_ring->itr_val = new_val;
2448 wr32(rx_ring->itr_register,
2449 1000000000 / (new_val * 256));
2450 }
2451}
2452
2453static void igb_raise_rx_eitr(struct igb_adapter *adapter,
2454 struct igb_ring *rx_ring)
2455{
2456 struct e1000_hw *hw = &adapter->hw;
2457 int new_val;
2458
2459 new_val = rx_ring->itr_val * 2;
2460 if (new_val > IGB_MAX_DYN_ITR)
2461 new_val = IGB_MAX_DYN_ITR;
2462
2463 if (new_val != rx_ring->itr_val) {
2464 rx_ring->itr_val = new_val;
2465 wr32(rx_ring->itr_register,
2466 1000000000 / (new_val * 256));
2467 }
2468}
2469
2470/**
2471 * igb_update_itr - update the dynamic ITR value based on statistics
2472 * Stores a new ITR value based on packets and byte
2473 * counts during the last interrupt. The advantage of per interrupt
2474 * computation is faster updates and more accurate ITR for the current
2475 * traffic pattern. Constants in this function were computed
2476 * based on theoretical maximum wire speed and thresholds were set based
2477 * on testing data as well as attempting to minimize response time
2478 * while increasing bulk throughput.
2479 * this functionality is controlled by the InterruptThrottleRate module
2480 * parameter (see igb_param.c)
2481 * NOTE: These calculations are only valid when operating in a single-
2482 * queue environment.
2483 * @adapter: pointer to adapter
2484 * @itr_setting: current adapter->itr
2485 * @packets: the number of packets during this measurement interval
2486 * @bytes: the number of bytes during this measurement interval
2487 **/
2488static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
2489 int packets, int bytes)
2490{
2491 unsigned int retval = itr_setting;
2492
2493 if (packets == 0)
2494 goto update_itr_done;
2495
2496 switch (itr_setting) {
2497 case lowest_latency:
2498 /* handle TSO and jumbo frames */
2499 if (bytes/packets > 8000)
2500 retval = bulk_latency;
2501 else if ((packets < 5) && (bytes > 512))
2502 retval = low_latency;
2503 break;
2504 case low_latency: /* 50 usec aka 20000 ints/s */
2505 if (bytes > 10000) {
2506 /* this if handles the TSO accounting */
2507 if (bytes/packets > 8000) {
2508 retval = bulk_latency;
2509 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
2510 retval = bulk_latency;
2511 } else if ((packets > 35)) {
2512 retval = lowest_latency;
2513 }
2514 } else if (bytes/packets > 2000) {
2515 retval = bulk_latency;
2516 } else if (packets <= 2 && bytes < 512) {
2517 retval = lowest_latency;
2518 }
2519 break;
2520 case bulk_latency: /* 250 usec aka 4000 ints/s */
2521 if (bytes > 25000) {
2522 if (packets > 35)
2523 retval = low_latency;
2524 } else if (bytes < 6000) {
2525 retval = low_latency;
2526 }
2527 break;
2528 }
2529
2530update_itr_done:
2531 return retval;
2532}
2533
2534static void igb_set_itr(struct igb_adapter *adapter, u16 itr_register,
2535 int rx_only)
2536{
2537 u16 current_itr;
2538 u32 new_itr = adapter->itr;
2539
2540 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2541 if (adapter->link_speed != SPEED_1000) {
2542 current_itr = 0;
2543 new_itr = 4000;
2544 goto set_itr_now;
2545 }
2546
2547 adapter->rx_itr = igb_update_itr(adapter,
2548 adapter->rx_itr,
2549 adapter->rx_ring->total_packets,
2550 adapter->rx_ring->total_bytes);
2551 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2552 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2553 adapter->rx_itr = low_latency;
2554
2555 if (!rx_only) {
2556 adapter->tx_itr = igb_update_itr(adapter,
2557 adapter->tx_itr,
2558 adapter->tx_ring->total_packets,
2559 adapter->tx_ring->total_bytes);
2560 /* conservative mode (itr 3) eliminates the
2561 * lowest_latency setting */
2562 if (adapter->itr_setting == 3 &&
2563 adapter->tx_itr == lowest_latency)
2564 adapter->tx_itr = low_latency;
2565
2566 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2567 } else {
2568 current_itr = adapter->rx_itr;
2569 }
2570
2571 switch (current_itr) {
2572 /* counts and packets in update_itr are dependent on these numbers */
2573 case lowest_latency:
2574 new_itr = 70000;
2575 break;
2576 case low_latency:
2577 new_itr = 20000; /* aka hwitr = ~200 */
2578 break;
2579 case bulk_latency:
2580 new_itr = 4000;
2581 break;
2582 default:
2583 break;
2584 }
2585
2586set_itr_now:
2587 if (new_itr != adapter->itr) {
2588 /* this attempts to bias the interrupt rate towards Bulk
2589 * by adding intermediate steps when interrupt rate is
2590 * increasing */
2591 new_itr = new_itr > adapter->itr ?
2592 min(adapter->itr + (new_itr >> 2), new_itr) :
2593 new_itr;
2594 /* Don't write the value here; it resets the adapter's
2595 * internal timer, and causes us to delay far longer than
2596 * we should between interrupts. Instead, we write the ITR
2597 * value at the beginning of the next interrupt so the timing
2598 * ends up being correct.
2599 */
2600 adapter->itr = new_itr;
2601 adapter->set_itr = 1;
2602 }
2603
2604 return;
2605}
2606
2607
2608#define IGB_TX_FLAGS_CSUM 0x00000001
2609#define IGB_TX_FLAGS_VLAN 0x00000002
2610#define IGB_TX_FLAGS_TSO 0x00000004
2611#define IGB_TX_FLAGS_IPV4 0x00000008
2612#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
2613#define IGB_TX_FLAGS_VLAN_SHIFT 16
2614
2615static inline int igb_tso_adv(struct igb_adapter *adapter,
2616 struct igb_ring *tx_ring,
2617 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
2618{
2619 struct e1000_adv_tx_context_desc *context_desc;
2620 unsigned int i;
2621 int err;
2622 struct igb_buffer *buffer_info;
2623 u32 info = 0, tu_cmd = 0;
2624 u32 mss_l4len_idx, l4len;
2625 *hdr_len = 0;
2626
2627 if (skb_header_cloned(skb)) {
2628 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2629 if (err)
2630 return err;
2631 }
2632
2633 l4len = tcp_hdrlen(skb);
2634 *hdr_len += l4len;
2635
2636 if (skb->protocol == htons(ETH_P_IP)) {
2637 struct iphdr *iph = ip_hdr(skb);
2638 iph->tot_len = 0;
2639 iph->check = 0;
2640 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2641 iph->daddr, 0,
2642 IPPROTO_TCP,
2643 0);
2644 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
2645 ipv6_hdr(skb)->payload_len = 0;
2646 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2647 &ipv6_hdr(skb)->daddr,
2648 0, IPPROTO_TCP, 0);
2649 }
2650
2651 i = tx_ring->next_to_use;
2652
2653 buffer_info = &tx_ring->buffer_info[i];
2654 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2655 /* VLAN MACLEN IPLEN */
2656 if (tx_flags & IGB_TX_FLAGS_VLAN)
2657 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2658 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2659 *hdr_len += skb_network_offset(skb);
2660 info |= skb_network_header_len(skb);
2661 *hdr_len += skb_network_header_len(skb);
2662 context_desc->vlan_macip_lens = cpu_to_le32(info);
2663
2664 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
2665 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2666
2667 if (skb->protocol == htons(ETH_P_IP))
2668 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
2669 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2670
2671 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2672
2673 /* MSS L4LEN IDX */
2674 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
2675 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
2676
7dfc16fa
AD		 2677 /* Context index must be unique per ring. */
2678 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2679 mss_l4len_idx |= tx_ring->queue_index << 4;
9d5c8243
AK		 2680
2681 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
2682 context_desc->seqnum_seed = 0;
2683
2684 buffer_info->time_stamp = jiffies;
2685 buffer_info->dma = 0;
2686 i++;
2687 if (i == tx_ring->count)
2688 i = 0;
2689
2690 tx_ring->next_to_use = i;
2691
2692 return true;
2693}
2694
2695static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
2696 struct igb_ring *tx_ring,
2697 struct sk_buff *skb, u32 tx_flags)
2698{
2699 struct e1000_adv_tx_context_desc *context_desc;
2700 unsigned int i;
2701 struct igb_buffer *buffer_info;
2702 u32 info = 0, tu_cmd = 0;
2703
2704 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
2705 (tx_flags & IGB_TX_FLAGS_VLAN)) {
2706 i = tx_ring->next_to_use;
2707 buffer_info = &tx_ring->buffer_info[i];
2708 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2709
2710 if (tx_flags & IGB_TX_FLAGS_VLAN)
2711 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2712 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2713 if (skb->ip_summed == CHECKSUM_PARTIAL)
2714 info |= skb_network_header_len(skb);
2715
2716 context_desc->vlan_macip_lens = cpu_to_le32(info);
2717
2718 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2719
2720 if (skb->ip_summed == CHECKSUM_PARTIAL) {
44b0cda3
MW		 2721 switch (skb->protocol) {
2722 case __constant_htons(ETH_P_IP):
9d5c8243 2723 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
44b0cda3
MW		 2724 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
2725 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2726 break;
2727 case __constant_htons(ETH_P_IPV6):
2728 /* XXX what about other V6 headers?? */
2729 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
2730 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2731 break;
2732 default:
2733 if (unlikely(net_ratelimit()))
2734 dev_warn(&adapter->pdev->dev,
2735 "partial checksum but proto=%x!\n",
2736 skb->protocol);
2737 break;
2738 }
9d5c8243
AK		 2739 }
2740
2741 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2742 context_desc->seqnum_seed = 0;
7dfc16fa
AD		 2743 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2744 context_desc->mss_l4len_idx =
2745 cpu_to_le32(tx_ring->queue_index << 4);
9d5c8243
AK		 2746
2747 buffer_info->time_stamp = jiffies;
2748 buffer_info->dma = 0;
2749
2750 i++;
2751 if (i == tx_ring->count)
2752 i = 0;
2753 tx_ring->next_to_use = i;
2754
2755 return true;
2756 }
2757
2758
2759 return false;
2760}
2761
2762#define IGB_MAX_TXD_PWR 16
2763#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
2764
2765static inline int igb_tx_map_adv(struct igb_adapter *adapter,
2766 struct igb_ring *tx_ring,
2767 struct sk_buff *skb)
2768{
2769 struct igb_buffer *buffer_info;
2770 unsigned int len = skb_headlen(skb);
2771 unsigned int count = 0, i;
2772 unsigned int f;
2773
2774 i = tx_ring->next_to_use;
2775
2776 buffer_info = &tx_ring->buffer_info[i];
2777 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2778 buffer_info->length = len;
2779 /* set time_stamp *before* dma to help avoid a possible race */
2780 buffer_info->time_stamp = jiffies;
2781 buffer_info->dma = pci_map_single(adapter->pdev, skb->data, len,
2782 PCI_DMA_TODEVICE);
2783 count++;
2784 i++;
2785 if (i == tx_ring->count)
2786 i = 0;
2787
2788 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
2789 struct skb_frag_struct *frag;
2790
2791 frag = &skb_shinfo(skb)->frags[f];
2792 len = frag->size;
2793
2794 buffer_info = &tx_ring->buffer_info[i];
2795 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2796 buffer_info->length = len;
2797 buffer_info->time_stamp = jiffies;
2798 buffer_info->dma = pci_map_page(adapter->pdev,
2799 frag->page,
2800 frag->page_offset,
2801 len,
2802 PCI_DMA_TODEVICE);
2803
2804 count++;
2805 i++;
2806 if (i == tx_ring->count)
2807 i = 0;
2808 }
2809
2810 i = (i == 0) ? tx_ring->count - 1 : i - 1;
2811 tx_ring->buffer_info[i].skb = skb;
2812
2813 return count;
2814}
2815
2816static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
2817 struct igb_ring *tx_ring,
2818 int tx_flags, int count, u32 paylen,
2819 u8 hdr_len)
2820{
2821 union e1000_adv_tx_desc *tx_desc = NULL;
2822 struct igb_buffer *buffer_info;
2823 u32 olinfo_status = 0, cmd_type_len;
2824 unsigned int i;
2825
2826 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
2827 E1000_ADVTXD_DCMD_DEXT);
2828
2829 if (tx_flags & IGB_TX_FLAGS_VLAN)
2830 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
2831
2832 if (tx_flags & IGB_TX_FLAGS_TSO) {
2833 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
2834
2835 /* insert tcp checksum */
2836 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2837
2838 /* insert ip checksum */
2839 if (tx_flags & IGB_TX_FLAGS_IPV4)
2840 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
2841
2842 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
2843 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2844 }
2845
7dfc16fa
AD		 2846 if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) &&
2847 (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
2848 IGB_TX_FLAGS_VLAN)))
661086df 2849 olinfo_status |= tx_ring->queue_index << 4;
9d5c8243
AK		 2850
2851 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
2852
2853 i = tx_ring->next_to_use;
2854 while (count--) {
2855 buffer_info = &tx_ring->buffer_info[i];
2856 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
2857 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
2858 tx_desc->read.cmd_type_len =
2859 cpu_to_le32(cmd_type_len | buffer_info->length);
2860 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
2861 i++;
2862 if (i == tx_ring->count)
2863 i = 0;
2864 }
2865
2866 tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
2867 /* Force memory writes to complete before letting h/w
2868 * know there are new descriptors to fetch. (Only
2869 * applicable for weak-ordered memory model archs,
2870 * such as IA-64). */
2871 wmb();
2872
2873 tx_ring->next_to_use = i;
2874 writel(i, adapter->hw.hw_addr + tx_ring->tail);
2875 /* we need this if more than one processor can write to our tail
2876 * at a time, it syncronizes IO on IA64/Altix systems */
2877 mmiowb();
2878}
2879
2880static int __igb_maybe_stop_tx(struct net_device *netdev,
2881 struct igb_ring *tx_ring, int size)
2882{
2883 struct igb_adapter *adapter = netdev_priv(netdev);
2884
661086df
PWJ		 2885#ifdef CONFIG_NETDEVICES_MULTIQUEUE
2886 netif_stop_subqueue(netdev, tx_ring->queue_index);
2887#else
9d5c8243 2888 netif_stop_queue(netdev);
661086df
PWJ		 2889#endif
2890
9d5c8243
AK		 2891 /* Herbert's original patch had:
2892 * smp_mb__after_netif_stop_queue();
2893 * but since that doesn't exist yet, just open code it. */
2894 smp_mb();
2895
2896 /* We need to check again in a case another CPU has just
2897 * made room available. */
2898 if (IGB_DESC_UNUSED(tx_ring) < size)
2899 return -EBUSY;
2900
2901 /* A reprieve! */
661086df
PWJ		 2902#ifdef CONFIG_NETDEVICES_MULTIQUEUE
2903 netif_wake_subqueue(netdev, tx_ring->queue_index);
2904#else
2905 netif_wake_queue(netdev);
2906#endif
9d5c8243
AK		 2907 ++adapter->restart_queue;
2908 return 0;
2909}
2910
2911static int igb_maybe_stop_tx(struct net_device *netdev,
2912 struct igb_ring *tx_ring, int size)
2913{
2914 if (IGB_DESC_UNUSED(tx_ring) >= size)
2915 return 0;
2916 return __igb_maybe_stop_tx(netdev, tx_ring, size);
2917}
2918
2919#define TXD_USE_COUNT(S) (((S) >> (IGB_MAX_TXD_PWR)) + 1)
2920
2921static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
2922 struct net_device *netdev,
2923 struct igb_ring *tx_ring)
2924{
2925 struct igb_adapter *adapter = netdev_priv(netdev);
2926 unsigned int tx_flags = 0;
2927 unsigned int len;
9d5c8243
AK		 2928 u8 hdr_len = 0;
2929 int tso = 0;
2930
2931 len = skb_headlen(skb);
2932
2933 if (test_bit(__IGB_DOWN, &adapter->state)) {
2934 dev_kfree_skb_any(skb);
2935 return NETDEV_TX_OK;
2936 }
2937
2938 if (skb->len <= 0) {
2939 dev_kfree_skb_any(skb);
2940 return NETDEV_TX_OK;
2941 }
2942
9d5c8243
AK		 2943 /* need: 1 descriptor per page,
2944 * + 2 desc gap to keep tail from touching head,
2945 * + 1 desc for skb->data,
2946 * + 1 desc for context descriptor,
2947 * otherwise try next time */
2948 if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
2949 /* this is a hard error */
9d5c8243
AK		 2950 return NETDEV_TX_BUSY;
2951 }
2952
2953 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
2954 tx_flags |= IGB_TX_FLAGS_VLAN;
2955 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
2956 }
2957
661086df
PWJ		 2958 if (skb->protocol == htons(ETH_P_IP))
2959 tx_flags |= IGB_TX_FLAGS_IPV4;
2960
9d5c8243
AK		 2961 tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
2962 &hdr_len) : 0;
2963
2964 if (tso < 0) {
2965 dev_kfree_skb_any(skb);
9d5c8243
AK		 2966 return NETDEV_TX_OK;
2967 }
2968
2969 if (tso)
2970 tx_flags |= IGB_TX_FLAGS_TSO;
2971 else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags))
2972 if (skb->ip_summed == CHECKSUM_PARTIAL)
2973 tx_flags |= IGB_TX_FLAGS_CSUM;
2974
9d5c8243
AK		 2975 igb_tx_queue_adv(adapter, tx_ring, tx_flags,
2976 igb_tx_map_adv(adapter, tx_ring, skb),
2977 skb->len, hdr_len);
2978
2979 netdev->trans_start = jiffies;
2980
2981 /* Make sure there is space in the ring for the next send. */
2982 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
2983
9d5c8243
AK		 2984 return NETDEV_TX_OK;
2985}
2986
2987static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *netdev)
2988{
2989 struct igb_adapter *adapter = netdev_priv(netdev);
661086df
PWJ		 2990 struct igb_ring *tx_ring;
2991
2992#ifdef CONFIG_NETDEVICES_MULTIQUEUE
2993 int r_idx = 0;
2994 r_idx = skb->queue_mapping & (IGB_MAX_TX_QUEUES - 1);
2995 tx_ring = adapter->multi_tx_table[r_idx];
2996#else
2997 tx_ring = &adapter->tx_ring[0];
2998#endif
2999
9d5c8243
AK		 3000
3001 /* This goes back to the question of how to logically map a tx queue
3002 * to a flow. Right now, performance is impacted slightly negatively
3003 * if using multiple tx queues. If the stack breaks away from a
3004 * single qdisc implementation, we can look at this again. */
3005 return (igb_xmit_frame_ring_adv(skb, netdev, tx_ring));
3006}
3007
3008/**
3009 * igb_tx_timeout - Respond to a Tx Hang
3010 * @netdev: network interface device structure
3011 **/
3012static void igb_tx_timeout(struct net_device *netdev)
3013{
3014 struct igb_adapter *adapter = netdev_priv(netdev);
3015 struct e1000_hw *hw = &adapter->hw;
3016
3017 /* Do the reset outside of interrupt context */
3018 adapter->tx_timeout_count++;
3019 schedule_work(&adapter->reset_task);
3020 wr32(E1000_EICS, adapter->eims_enable_mask &
3021 ~(E1000_EIMS_TCP_TIMER | E1000_EIMS_OTHER));
3022}
3023
3024static void igb_reset_task(struct work_struct *work)
3025{
3026 struct igb_adapter *adapter;
3027 adapter = container_of(work, struct igb_adapter, reset_task);
3028
3029 igb_reinit_locked(adapter);
3030}
3031
3032/**
3033 * igb_get_stats - Get System Network Statistics
3034 * @netdev: network interface device structure
3035 *
3036 * Returns the address of the device statistics structure.
3037 * The statistics are actually updated from the timer callback.
3038 **/
3039static struct net_device_stats *
3040igb_get_stats(struct net_device *netdev)
3041{
3042 struct igb_adapter *adapter = netdev_priv(netdev);
3043
3044 /* only return the current stats */
3045 return &adapter->net_stats;
3046}
3047
3048/**
3049 * igb_change_mtu - Change the Maximum Transfer Unit
3050 * @netdev: network interface device structure
3051 * @new_mtu: new value for maximum frame size
3052 *
3053 * Returns 0 on success, negative on failure
3054 **/
3055static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3056{
3057 struct igb_adapter *adapter = netdev_priv(netdev);
3058 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3059
3060 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
3061 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3062 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
3063 return -EINVAL;
3064 }
3065
3066#define MAX_STD_JUMBO_FRAME_SIZE 9234
3067 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3068 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
3069 return -EINVAL;
3070 }
3071
3072 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3073 msleep(1);
3074 /* igb_down has a dependency on max_frame_size */
3075 adapter->max_frame_size = max_frame;
3076 if (netif_running(netdev))
3077 igb_down(adapter);
3078
3079 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3080 * means we reserve 2 more, this pushes us to allocate from the next
3081 * larger slab size.
3082 * i.e. RXBUFFER_2048 --> size-4096 slab
3083 */
3084
3085 if (max_frame <= IGB_RXBUFFER_256)
3086 adapter->rx_buffer_len = IGB_RXBUFFER_256;
3087 else if (max_frame <= IGB_RXBUFFER_512)
3088 adapter->rx_buffer_len = IGB_RXBUFFER_512;
3089 else if (max_frame <= IGB_RXBUFFER_1024)
3090 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3091 else if (max_frame <= IGB_RXBUFFER_2048)
3092 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
3093 else
3094 adapter->rx_buffer_len = IGB_RXBUFFER_4096;
3095 /* adjust allocation if LPE protects us, and we aren't using SBP */
3096 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
3097 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
3098 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3099
3100 dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
3101 netdev->mtu, new_mtu);
3102 netdev->mtu = new_mtu;
3103
3104 if (netif_running(netdev))
3105 igb_up(adapter);
3106 else
3107 igb_reset(adapter);
3108
3109 clear_bit(__IGB_RESETTING, &adapter->state);
3110
3111 return 0;
3112}
3113
3114/**
3115 * igb_update_stats - Update the board statistics counters
3116 * @adapter: board private structure
3117 **/
3118
3119void igb_update_stats(struct igb_adapter *adapter)
3120{
3121 struct e1000_hw *hw = &adapter->hw;
3122 struct pci_dev *pdev = adapter->pdev;
3123 u16 phy_tmp;
3124
3125#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3126
3127 /*
3128 * Prevent stats update while adapter is being reset, or if the pci
3129 * connection is down.
3130 */
3131 if (adapter->link_speed == 0)
3132 return;
3133 if (pci_channel_offline(pdev))
3134 return;
3135
3136 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3137 adapter->stats.gprc += rd32(E1000_GPRC);
3138 adapter->stats.gorc += rd32(E1000_GORCL);
3139 rd32(E1000_GORCH); /* clear GORCL */
3140 adapter->stats.bprc += rd32(E1000_BPRC);
3141 adapter->stats.mprc += rd32(E1000_MPRC);
3142 adapter->stats.roc += rd32(E1000_ROC);
3143
3144 adapter->stats.prc64 += rd32(E1000_PRC64);
3145 adapter->stats.prc127 += rd32(E1000_PRC127);
3146 adapter->stats.prc255 += rd32(E1000_PRC255);
3147 adapter->stats.prc511 += rd32(E1000_PRC511);
3148 adapter->stats.prc1023 += rd32(E1000_PRC1023);
3149 adapter->stats.prc1522 += rd32(E1000_PRC1522);
3150 adapter->stats.symerrs += rd32(E1000_SYMERRS);
3151 adapter->stats.sec += rd32(E1000_SEC);
3152
3153 adapter->stats.mpc += rd32(E1000_MPC);
3154 adapter->stats.scc += rd32(E1000_SCC);
3155 adapter->stats.ecol += rd32(E1000_ECOL);
3156 adapter->stats.mcc += rd32(E1000_MCC);
3157 adapter->stats.latecol += rd32(E1000_LATECOL);
3158 adapter->stats.dc += rd32(E1000_DC);
3159 adapter->stats.rlec += rd32(E1000_RLEC);
3160 adapter->stats.xonrxc += rd32(E1000_XONRXC);
3161 adapter->stats.xontxc += rd32(E1000_XONTXC);
3162 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
3163 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
3164 adapter->stats.fcruc += rd32(E1000_FCRUC);
3165 adapter->stats.gptc += rd32(E1000_GPTC);
3166 adapter->stats.gotc += rd32(E1000_GOTCL);
3167 rd32(E1000_GOTCH); /* clear GOTCL */
3168 adapter->stats.rnbc += rd32(E1000_RNBC);
3169 adapter->stats.ruc += rd32(E1000_RUC);
3170 adapter->stats.rfc += rd32(E1000_RFC);
3171 adapter->stats.rjc += rd32(E1000_RJC);
3172 adapter->stats.tor += rd32(E1000_TORH);
3173 adapter->stats.tot += rd32(E1000_TOTH);
3174 adapter->stats.tpr += rd32(E1000_TPR);
3175
3176 adapter->stats.ptc64 += rd32(E1000_PTC64);
3177 adapter->stats.ptc127 += rd32(E1000_PTC127);
3178 adapter->stats.ptc255 += rd32(E1000_PTC255);
3179 adapter->stats.ptc511 += rd32(E1000_PTC511);
3180 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
3181 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
3182
3183 adapter->stats.mptc += rd32(E1000_MPTC);
3184 adapter->stats.bptc += rd32(E1000_BPTC);
3185
3186 /* used for adaptive IFS */
3187
3188 hw->mac.tx_packet_delta = rd32(E1000_TPT);
3189 adapter->stats.tpt += hw->mac.tx_packet_delta;
3190 hw->mac.collision_delta = rd32(E1000_COLC);
3191 adapter->stats.colc += hw->mac.collision_delta;
3192
3193 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
3194 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3195 adapter->stats.tncrs += rd32(E1000_TNCRS);
3196 adapter->stats.tsctc += rd32(E1000_TSCTC);
3197 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
3198
3199 adapter->stats.iac += rd32(E1000_IAC);
3200 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
3201 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
3202 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
3203 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
3204 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
3205 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
3206 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
3207 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
3208
3209 /* Fill out the OS statistics structure */
3210 adapter->net_stats.multicast = adapter->stats.mprc;
3211 adapter->net_stats.collisions = adapter->stats.colc;
3212
3213 /* Rx Errors */
3214
3215 /* RLEC on some newer hardware can be incorrect so build
3216 * our own version based on RUC and ROC */
3217 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3218 adapter->stats.crcerrs + adapter->stats.algnerrc +
3219 adapter->stats.ruc + adapter->stats.roc +
3220 adapter->stats.cexterr;
3221 adapter->net_stats.rx_length_errors = adapter->stats.ruc +
3222 adapter->stats.roc;
3223 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3224 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
3225 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3226
3227 /* Tx Errors */
3228 adapter->net_stats.tx_errors = adapter->stats.ecol +
3229 adapter->stats.latecol;
3230 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3231 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3232 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3233
3234 /* Tx Dropped needs to be maintained elsewhere */
3235
3236 /* Phy Stats */
3237 if (hw->phy.media_type == e1000_media_type_copper) {
3238 if ((adapter->link_speed == SPEED_1000) &&
3239 (!hw->phy.ops.read_phy_reg(hw, PHY_1000T_STATUS,
3240 &phy_tmp))) {
3241 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3242 adapter->phy_stats.idle_errors += phy_tmp;
3243 }
3244 }
3245
3246 /* Management Stats */
3247 adapter->stats.mgptc += rd32(E1000_MGTPTC);
3248 adapter->stats.mgprc += rd32(E1000_MGTPRC);
3249 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3250}
3251
3252
3253static irqreturn_t igb_msix_other(int irq, void *data)
3254{
3255 struct net_device *netdev = data;
3256 struct igb_adapter *adapter = netdev_priv(netdev);
3257 struct e1000_hw *hw = &adapter->hw;
844290e5 3258 u32 icr = rd32(E1000_ICR);
9d5c8243 3259
844290e5
PW		 3260 /* reading ICR causes bit 31 of EICR to be cleared */
3261 if (!(icr & E1000_ICR_LSC))
3262 goto no_link_interrupt;
3263 hw->mac.get_link_status = 1;
3264 /* guard against interrupt when we're going down */
3265 if (!test_bit(__IGB_DOWN, &adapter->state))
3266 mod_timer(&adapter->watchdog_timer, jiffies + 1);
661086df 3267
9d5c8243
AK		 3268no_link_interrupt:
3269 wr32(E1000_IMS, E1000_IMS_LSC);
844290e5 3270 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 3271
3272 return IRQ_HANDLED;
3273}
3274
3275static irqreturn_t igb_msix_tx(int irq, void *data)
3276{
3277 struct igb_ring *tx_ring = data;
3278 struct igb_adapter *adapter = tx_ring->adapter;
3279 struct e1000_hw *hw = &adapter->hw;
3280
3281 if (!tx_ring->itr_val)
3282 wr32(E1000_EIMC, tx_ring->eims_value);
fe4506b6 3283#ifdef CONFIG_DCA
7dfc16fa 3284 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3285 igb_update_tx_dca(tx_ring);
3286#endif
9d5c8243
AK		 3287 tx_ring->total_bytes = 0;
3288 tx_ring->total_packets = 0;
661086df
PWJ		 3289
3290 /* auto mask will automatically reenable the interrupt when we write
3291 * EICS */
3b644cf6 3292 if (!igb_clean_tx_irq(tx_ring))
9d5c8243
AK		 3293 /* Ring was not completely cleaned, so fire another interrupt */
3294 wr32(E1000_EICS, tx_ring->eims_value);
661086df 3295 else
9d5c8243 3296 wr32(E1000_EIMS, tx_ring->eims_value);
661086df 3297
9d5c8243
AK		 3298 return IRQ_HANDLED;
3299}
3300
3301static irqreturn_t igb_msix_rx(int irq, void *data)
3302{
3303 struct igb_ring *rx_ring = data;
3304 struct igb_adapter *adapter = rx_ring->adapter;
3305 struct e1000_hw *hw = &adapter->hw;
3306
844290e5
PW		 3307 /* Write the ITR value calculated at the end of the
3308 * previous interrupt.
3309 */
9d5c8243 3310
844290e5
PW		 3311 if (adapter->set_itr) {
3312 wr32(rx_ring->itr_register,
3313 1000000000 / (rx_ring->itr_val * 256));
3314 adapter->set_itr = 0;
9d5c8243
AK		 3315 }
3316
844290e5
PW		 3317 if (netif_rx_schedule_prep(adapter->netdev, &rx_ring->napi))
3318 __netif_rx_schedule(adapter->netdev, &rx_ring->napi);
3319
fe4506b6 3320#ifdef CONFIG_DCA
7dfc16fa 3321 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3322 igb_update_rx_dca(rx_ring);
3323#endif
3324 return IRQ_HANDLED;
3325}
3326
3327#ifdef CONFIG_DCA
3328static void igb_update_rx_dca(struct igb_ring *rx_ring)
3329{
3330 u32 dca_rxctrl;
3331 struct igb_adapter *adapter = rx_ring->adapter;
3332 struct e1000_hw *hw = &adapter->hw;
3333 int cpu = get_cpu();
3334 int q = rx_ring - adapter->rx_ring;
3335
3336 if (rx_ring->cpu != cpu) {
3337 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
2d064c06
AD		 3338 if (hw->mac.type == e1000_82576) {
3339 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
3340 dca_rxctrl |= dca_get_tag(cpu) <<
3341 E1000_DCA_RXCTRL_CPUID_SHIFT;
3342 } else {
3343 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
3344 dca_rxctrl |= dca_get_tag(cpu);
3345 }
fe4506b6
JC		 3346 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
3347 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
3348 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
3349 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
3350 rx_ring->cpu = cpu;
3351 }
3352 put_cpu();
3353}
3354
3355static void igb_update_tx_dca(struct igb_ring *tx_ring)
3356{
3357 u32 dca_txctrl;
3358 struct igb_adapter *adapter = tx_ring->adapter;
3359 struct e1000_hw *hw = &adapter->hw;
3360 int cpu = get_cpu();
3361 int q = tx_ring - adapter->tx_ring;
3362
3363 if (tx_ring->cpu != cpu) {
3364 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
2d064c06
AD		 3365 if (hw->mac.type == e1000_82576) {
3366 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
3367 dca_txctrl |= dca_get_tag(cpu) <<
3368 E1000_DCA_TXCTRL_CPUID_SHIFT;
3369 } else {
3370 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
3371 dca_txctrl |= dca_get_tag(cpu);
3372 }
fe4506b6
JC		 3373 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
3374 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
3375 tx_ring->cpu = cpu;
3376 }
3377 put_cpu();
3378}
3379
3380static void igb_setup_dca(struct igb_adapter *adapter)
3381{
3382 int i;
3383
7dfc16fa 3384 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 3385 return;
3386
3387 for (i = 0; i < adapter->num_tx_queues; i++) {
3388 adapter->tx_ring[i].cpu = -1;
3389 igb_update_tx_dca(&adapter->tx_ring[i]);
3390 }
3391 for (i = 0; i < adapter->num_rx_queues; i++) {
3392 adapter->rx_ring[i].cpu = -1;
3393 igb_update_rx_dca(&adapter->rx_ring[i]);
3394 }
3395}
3396
3397static int __igb_notify_dca(struct device *dev, void *data)
3398{
3399 struct net_device *netdev = dev_get_drvdata(dev);
3400 struct igb_adapter *adapter = netdev_priv(netdev);
3401 struct e1000_hw *hw = &adapter->hw;
3402 unsigned long event = *(unsigned long *)data;
3403
7dfc16fa
AD		 3404 if (!(adapter->flags & IGB_FLAG_HAS_DCA))
3405 goto out;
3406
fe4506b6
JC		 3407 switch (event) {
3408 case DCA_PROVIDER_ADD:
3409 /* if already enabled, don't do it again */
7dfc16fa 3410 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 3411 break;
7dfc16fa 3412 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 3413 /* Always use CB2 mode, difference is masked
3414 * in the CB driver. */
3415 wr32(E1000_DCA_CTRL, 2);
3416 if (dca_add_requester(dev) == 0) {
3417 dev_info(&adapter->pdev->dev, "DCA enabled\n");
3418 igb_setup_dca(adapter);
3419 break;
3420 }
3421 /* Fall Through since DCA is disabled. */
3422 case DCA_PROVIDER_REMOVE:
7dfc16fa 3423 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 3424 /* without this a class_device is left
3425 * hanging around in the sysfs model */
3426 dca_remove_requester(dev);
3427 dev_info(&adapter->pdev->dev, "DCA disabled\n");
7dfc16fa 3428 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 3429 wr32(E1000_DCA_CTRL, 1);
3430 }
3431 break;
3432 }
7dfc16fa 3433out:
fe4506b6 3434 return 0;
9d5c8243
AK		 3435}
3436
fe4506b6
JC		 3437static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
3438 void *p)
3439{
3440 int ret_val;
3441
3442 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
3443 __igb_notify_dca);
3444
3445 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
3446}
3447#endif /* CONFIG_DCA */
9d5c8243
AK		 3448
3449/**
3450 * igb_intr_msi - Interrupt Handler
3451 * @irq: interrupt number
3452 * @data: pointer to a network interface device structure
3453 **/
3454static irqreturn_t igb_intr_msi(int irq, void *data)
3455{
3456 struct net_device *netdev = data;
3457 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 3458 struct e1000_hw *hw = &adapter->hw;
3459 /* read ICR disables interrupts using IAM */
3460 u32 icr = rd32(E1000_ICR);
3461
3462 /* Write the ITR value calculated at the end of the
3463 * previous interrupt.
3464 */
3465 if (adapter->set_itr) {
844290e5 3466 wr32(E1000_ITR, 1000000000 / (adapter->itr * 256));
9d5c8243
AK		 3467 adapter->set_itr = 0;
3468 }
3469
9d5c8243
AK		 3470 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3471 hw->mac.get_link_status = 1;
3472 if (!test_bit(__IGB_DOWN, &adapter->state))
3473 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3474 }
3475
844290e5 3476 netif_rx_schedule(netdev, &adapter->rx_ring[0].napi);
9d5c8243
AK		 3477
3478 return IRQ_HANDLED;
3479}
3480
3481/**
3482 * igb_intr - Interrupt Handler
3483 * @irq: interrupt number
3484 * @data: pointer to a network interface device structure
3485 **/
3486static irqreturn_t igb_intr(int irq, void *data)
3487{
3488 struct net_device *netdev = data;
3489 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 3490 struct e1000_hw *hw = &adapter->hw;
3491 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
3492 * need for the IMC write */
3493 u32 icr = rd32(E1000_ICR);
3494 u32 eicr = 0;
3495 if (!icr)
3496 return IRQ_NONE; /* Not our interrupt */
3497
3498 /* Write the ITR value calculated at the end of the
3499 * previous interrupt.
3500 */
3501 if (adapter->set_itr) {
844290e5 3502 wr32(E1000_ITR, 1000000000 / (adapter->itr * 256));
9d5c8243
AK		 3503 adapter->set_itr = 0;
3504 }
3505
3506 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
3507 * not set, then the adapter didn't send an interrupt */
3508 if (!(icr & E1000_ICR_INT_ASSERTED))
3509 return IRQ_NONE;
3510
3511 eicr = rd32(E1000_EICR);
3512
3513 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3514 hw->mac.get_link_status = 1;
3515 /* guard against interrupt when we're going down */
3516 if (!test_bit(__IGB_DOWN, &adapter->state))
3517 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3518 }
3519
844290e5 3520 netif_rx_schedule(netdev, &adapter->rx_ring[0].napi);
9d5c8243
AK		 3521
3522 return IRQ_HANDLED;
3523}
3524
3525/**
661086df
PWJ		 3526 * igb_poll - NAPI Rx polling callback
3527 * @napi: napi polling structure
3528 * @budget: count of how many packets we should handle
9d5c8243 3529 **/
661086df 3530static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 3531{
661086df
PWJ		 3532 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3533 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 3534 struct net_device *netdev = adapter->netdev;
661086df 3535 int tx_clean_complete, work_done = 0;
9d5c8243 3536
661086df 3537 /* this poll routine only supports one tx and one rx queue */
fe4506b6 3538#ifdef CONFIG_DCA
7dfc16fa 3539 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3540 igb_update_tx_dca(&adapter->tx_ring[0]);
3541#endif
661086df 3542 tx_clean_complete = igb_clean_tx_irq(&adapter->tx_ring[0]);
fe4506b6
JC		 3543
3544#ifdef CONFIG_DCA
7dfc16fa 3545 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3546 igb_update_rx_dca(&adapter->rx_ring[0]);
3547#endif
661086df 3548 igb_clean_rx_irq_adv(&adapter->rx_ring[0], &work_done, budget);
9d5c8243
AK		 3549
3550 /* If no Tx and not enough Rx work done, exit the polling mode */
3551 if ((tx_clean_complete && (work_done < budget)) ||
3552 !netif_running(netdev)) {
9d5c8243
AK		 3553 if (adapter->itr_setting & 3)
3554 igb_set_itr(adapter, E1000_ITR, false);
3555 netif_rx_complete(netdev, napi);
3556 if (!test_bit(__IGB_DOWN, &adapter->state))
3557 igb_irq_enable(adapter);
3558 return 0;
3559 }
3560
3561 return 1;
3562}
3563
3564static int igb_clean_rx_ring_msix(struct napi_struct *napi, int budget)
3565{
3566 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3567 struct igb_adapter *adapter = rx_ring->adapter;
3568 struct e1000_hw *hw = &adapter->hw;
3569 struct net_device *netdev = adapter->netdev;
3570 int work_done = 0;
3571
3572 /* Keep link state information with original netdev */
3573 if (!netif_carrier_ok(netdev))
3574 goto quit_polling;
3575
fe4506b6 3576#ifdef CONFIG_DCA
7dfc16fa 3577 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3578 igb_update_rx_dca(rx_ring);
3579#endif
3b644cf6 3580 igb_clean_rx_irq_adv(rx_ring, &work_done, budget);
9d5c8243
AK		 3581
3582
3583 /* If not enough Rx work done, exit the polling mode */
3584 if ((work_done == 0) || !netif_running(netdev)) {
3585quit_polling:
3586 netif_rx_complete(netdev, napi);
3587
3588 wr32(E1000_EIMS, rx_ring->eims_value);
3589 if ((adapter->itr_setting & 3) && !rx_ring->no_itr_adjust &&
3590 (rx_ring->total_packets > IGB_DYN_ITR_PACKET_THRESHOLD)) {
3591 int mean_size = rx_ring->total_bytes /
3592 rx_ring->total_packets;
3593 if (mean_size < IGB_DYN_ITR_LENGTH_LOW)
3594 igb_raise_rx_eitr(adapter, rx_ring);
3595 else if (mean_size > IGB_DYN_ITR_LENGTH_HIGH)
3596 igb_lower_rx_eitr(adapter, rx_ring);
3597 }
844290e5
PW		 3598
3599 if (!test_bit(__IGB_DOWN, &adapter->state))
3600 wr32(E1000_EIMS, rx_ring->eims_value);
3601
9d5c8243
AK		 3602 return 0;
3603 }
3604
3605 return 1;
3606}
6d8126f9
AV		 3607
3608static inline u32 get_head(struct igb_ring *tx_ring)
3609{
3610 void *end = (struct e1000_tx_desc *)tx_ring->desc + tx_ring->count;
3611 return le32_to_cpu(*(volatile __le32 *)end);
3612}
3613
9d5c8243
AK		 3614/**
3615 * igb_clean_tx_irq - Reclaim resources after transmit completes
3616 * @adapter: board private structure
3617 * returns true if ring is completely cleaned
3618 **/
3b644cf6 3619static bool igb_clean_tx_irq(struct igb_ring *tx_ring)
9d5c8243 3620{
3b644cf6 3621 struct igb_adapter *adapter = tx_ring->adapter;
9d5c8243 3622 struct e1000_hw *hw = &adapter->hw;
3b644cf6 3623 struct net_device *netdev = adapter->netdev;
9d5c8243
AK		 3624 struct e1000_tx_desc *tx_desc;
3625 struct igb_buffer *buffer_info;
3626 struct sk_buff *skb;
3627 unsigned int i;
3628 u32 head, oldhead;
3629 unsigned int count = 0;
3630 bool cleaned = false;
3631 bool retval = true;
3632 unsigned int total_bytes = 0, total_packets = 0;
3633
3634 rmb();
6d8126f9 3635 head = get_head(tx_ring);
9d5c8243
AK		 3636 i = tx_ring->next_to_clean;
3637 while (1) {
3638 while (i != head) {
3639 cleaned = true;
3640 tx_desc = E1000_TX_DESC(*tx_ring, i);
3641 buffer_info = &tx_ring->buffer_info[i];
3642 skb = buffer_info->skb;
3643
3644 if (skb) {
3645 unsigned int segs, bytecount;
3646 /* gso_segs is currently only valid for tcp */
3647 segs = skb_shinfo(skb)->gso_segs ?: 1;
3648 /* multiply data chunks by size of headers */
3649 bytecount = ((segs - 1) * skb_headlen(skb)) +
3650 skb->len;
3651 total_packets += segs;
3652 total_bytes += bytecount;
3653 }
3654
3655 igb_unmap_and_free_tx_resource(adapter, buffer_info);
3656 tx_desc->upper.data = 0;
3657
3658 i++;
3659 if (i == tx_ring->count)
3660 i = 0;
3661
3662 count++;
3663 if (count == IGB_MAX_TX_CLEAN) {
3664 retval = false;
3665 goto done_cleaning;
3666 }
3667 }
3668 oldhead = head;
3669 rmb();
6d8126f9 3670 head = get_head(tx_ring);
9d5c8243
AK		 3671 if (head == oldhead)
3672 goto done_cleaning;
3673 } /* while (1) */
3674
3675done_cleaning:
3676 tx_ring->next_to_clean = i;
3677
3678 if (unlikely(cleaned &&
3679 netif_carrier_ok(netdev) &&
3680 IGB_DESC_UNUSED(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
3681 /* Make sure that anybody stopping the queue after this
3682 * sees the new next_to_clean.
3683 */
3684 smp_mb();
661086df
PWJ		 3685#ifdef CONFIG_NETDEVICES_MULTIQUEUE
3686 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
3687 !(test_bit(__IGB_DOWN, &adapter->state))) {
3688 netif_wake_subqueue(netdev, tx_ring->queue_index);
3689 ++adapter->restart_queue;
3690 }
3691#else
9d5c8243
AK		 3692 if (netif_queue_stopped(netdev) &&
3693 !(test_bit(__IGB_DOWN, &adapter->state))) {
3694 netif_wake_queue(netdev);
3695 ++adapter->restart_queue;
3696 }
661086df 3697#endif
9d5c8243
AK		 3698 }
3699
3700 if (tx_ring->detect_tx_hung) {
3701 /* Detect a transmit hang in hardware, this serializes the
3702 * check with the clearing of time_stamp and movement of i */
3703 tx_ring->detect_tx_hung = false;
3704 if (tx_ring->buffer_info[i].time_stamp &&
3705 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
3706 (adapter->tx_timeout_factor * HZ))
3707 && !(rd32(E1000_STATUS) &
3708 E1000_STATUS_TXOFF)) {
3709
3710 tx_desc = E1000_TX_DESC(*tx_ring, i);
3711 /* detected Tx unit hang */
3712 dev_err(&adapter->pdev->dev,
3713 "Detected Tx Unit Hang\n"
2d064c06 3714 " Tx Queue <%d>\n"
9d5c8243
AK		 3715 " TDH <%x>\n"
3716 " TDT <%x>\n"
3717 " next_to_use <%x>\n"
3718 " next_to_clean <%x>\n"
3719 " head (WB) <%x>\n"
3720 "buffer_info[next_to_clean]\n"
3721 " time_stamp <%lx>\n"
3722 " jiffies <%lx>\n"
3723 " desc.status <%x>\n",
2d064c06 3724 tx_ring->queue_index,
9d5c8243
AK		 3725 readl(adapter->hw.hw_addr + tx_ring->head),
3726 readl(adapter->hw.hw_addr + tx_ring->tail),
3727 tx_ring->next_to_use,
3728 tx_ring->next_to_clean,
3729 head,
3730 tx_ring->buffer_info[i].time_stamp,
3731 jiffies,
3732 tx_desc->upper.fields.status);
661086df
PWJ		 3733#ifdef CONFIG_NETDEVICES_MULTIQUEUE
3734 netif_stop_subqueue(netdev, tx_ring->queue_index);
3735#else
9d5c8243 3736 netif_stop_queue(netdev);
661086df 3737#endif
9d5c8243
AK		 3738 }
3739 }
3740 tx_ring->total_bytes += total_bytes;
3741 tx_ring->total_packets += total_packets;
e21ed353
AD		 3742 tx_ring->tx_stats.bytes += total_bytes;
3743 tx_ring->tx_stats.packets += total_packets;
9d5c8243
AK		 3744 adapter->net_stats.tx_bytes += total_bytes;
3745 adapter->net_stats.tx_packets += total_packets;
3746 return retval;
3747}
3748
3749
3750/**
3751 * igb_receive_skb - helper function to handle rx indications
3752 * @adapter: board private structure
3753 * @status: descriptor status field as written by hardware
3754 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
3755 * @skb: pointer to sk_buff to be indicated to stack
3756 **/
6d8126f9 3757static void igb_receive_skb(struct igb_adapter *adapter, u8 status, __le16 vlan,
9d5c8243
AK		 3758 struct sk_buff *skb)
3759{
3760 if (adapter->vlgrp && (status & E1000_RXD_STAT_VP))
3761 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
38b22195 3762 le16_to_cpu(vlan));
9d5c8243
AK		 3763 else
3764 netif_receive_skb(skb);
3765}
3766
3767
3768static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
3769 u32 status_err, struct sk_buff *skb)
3770{
3771 skb->ip_summed = CHECKSUM_NONE;
3772
3773 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
3774 if ((status_err & E1000_RXD_STAT_IXSM) || !adapter->rx_csum)
3775 return;
3776 /* TCP/UDP checksum error bit is set */
3777 if (status_err &
3778 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
3779 /* let the stack verify checksum errors */
3780 adapter->hw_csum_err++;
3781 return;
3782 }
3783 /* It must be a TCP or UDP packet with a valid checksum */
3784 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
3785 skb->ip_summed = CHECKSUM_UNNECESSARY;
3786
3787 adapter->hw_csum_good++;
3788}
3789
3b644cf6
MW		 3790static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring,
3791 int *work_done, int budget)
9d5c8243 3792{
3b644cf6 3793 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 3794 struct net_device *netdev = adapter->netdev;
3795 struct pci_dev *pdev = adapter->pdev;
3796 union e1000_adv_rx_desc *rx_desc , *next_rxd;
3797 struct igb_buffer *buffer_info , *next_buffer;
3798 struct sk_buff *skb;
3799 unsigned int i, j;
3800 u32 length, hlen, staterr;
3801 bool cleaned = false;
3802 int cleaned_count = 0;
3803 unsigned int total_bytes = 0, total_packets = 0;
3804
3805 i = rx_ring->next_to_clean;
3806 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3807 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3808
3809 while (staterr & E1000_RXD_STAT_DD) {
3810 if (*work_done >= budget)
3811 break;
3812 (*work_done)++;
3813 buffer_info = &rx_ring->buffer_info[i];
3814
3815 /* HW will not DMA in data larger than the given buffer, even
3816 * if it parses the (NFS, of course) header to be larger. In
3817 * that case, it fills the header buffer and spills the rest
3818 * into the page.
3819 */
7deb07b1
AV		 3820 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
3821 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
9d5c8243
AK		 3822 if (hlen > adapter->rx_ps_hdr_size)
3823 hlen = adapter->rx_ps_hdr_size;
3824
3825 length = le16_to_cpu(rx_desc->wb.upper.length);
3826 cleaned = true;
3827 cleaned_count++;
3828
3829 if (rx_ring->pending_skb != NULL) {
3830 skb = rx_ring->pending_skb;
3831 rx_ring->pending_skb = NULL;
3832 j = rx_ring->pending_skb_page;
3833 } else {
3834 skb = buffer_info->skb;
3835 prefetch(skb->data - NET_IP_ALIGN);
3836 buffer_info->skb = NULL;
3837 if (hlen) {
3838 pci_unmap_single(pdev, buffer_info->dma,
3839 adapter->rx_ps_hdr_size +
3840 NET_IP_ALIGN,
3841 PCI_DMA_FROMDEVICE);
3842 skb_put(skb, hlen);
3843 } else {
3844 pci_unmap_single(pdev, buffer_info->dma,
3845 adapter->rx_buffer_len +
3846 NET_IP_ALIGN,
3847 PCI_DMA_FROMDEVICE);
3848 skb_put(skb, length);
3849 goto send_up;
3850 }
3851 j = 0;
3852 }
3853
3854 while (length) {
3855 pci_unmap_page(pdev, buffer_info->page_dma,
3856 PAGE_SIZE, PCI_DMA_FROMDEVICE);
3857 buffer_info->page_dma = 0;
3858 skb_fill_page_desc(skb, j, buffer_info->page,
3859 0, length);
3860 buffer_info->page = NULL;
3861
3862 skb->len += length;
3863 skb->data_len += length;
3864 skb->truesize += length;
3865 rx_desc->wb.upper.status_error = 0;
3866 if (staterr & E1000_RXD_STAT_EOP)
3867 break;
3868
3869 j++;
3870 cleaned_count++;
3871 i++;
3872 if (i == rx_ring->count)
3873 i = 0;
3874
3875 buffer_info = &rx_ring->buffer_info[i];
3876 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3877 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3878 length = le16_to_cpu(rx_desc->wb.upper.length);
3879 if (!(staterr & E1000_RXD_STAT_DD)) {
3880 rx_ring->pending_skb = skb;
3881 rx_ring->pending_skb_page = j;
3882 goto out;
3883 }
3884 }
3885send_up:
9d5c8243
AK		 3886 i++;
3887 if (i == rx_ring->count)
3888 i = 0;
3889 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
3890 prefetch(next_rxd);
3891 next_buffer = &rx_ring->buffer_info[i];
3892
3893 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
3894 dev_kfree_skb_irq(skb);
3895 goto next_desc;
3896 }
3897 rx_ring->no_itr_adjust |= (staterr & E1000_RXD_STAT_DYNINT);
3898
3899 total_bytes += skb->len;
3900 total_packets++;
3901
3902 igb_rx_checksum_adv(adapter, staterr, skb);
3903
3904 skb->protocol = eth_type_trans(skb, netdev);
3905
3906 igb_receive_skb(adapter, staterr, rx_desc->wb.upper.vlan, skb);
3907
3908 netdev->last_rx = jiffies;
3909
3910next_desc:
3911 rx_desc->wb.upper.status_error = 0;
3912
3913 /* return some buffers to hardware, one at a time is too slow */
3914 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
3b644cf6 3915 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 3916 cleaned_count = 0;
3917 }
3918
3919 /* use prefetched values */
3920 rx_desc = next_rxd;
3921 buffer_info = next_buffer;
3922
3923 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3924 }
3925out:
3926 rx_ring->next_to_clean = i;
3927 cleaned_count = IGB_DESC_UNUSED(rx_ring);
3928
3929 if (cleaned_count)
3b644cf6 3930 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 3931
3932 rx_ring->total_packets += total_packets;
3933 rx_ring->total_bytes += total_bytes;
3934 rx_ring->rx_stats.packets += total_packets;
3935 rx_ring->rx_stats.bytes += total_bytes;
3936 adapter->net_stats.rx_bytes += total_bytes;
3937 adapter->net_stats.rx_packets += total_packets;
3938 return cleaned;
3939}
3940
3941
3942/**
3943 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
3944 * @adapter: address of board private structure
3945 **/
3b644cf6 3946static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
9d5c8243
AK		 3947 int cleaned_count)
3948{
3b644cf6 3949 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 3950 struct net_device *netdev = adapter->netdev;
3951 struct pci_dev *pdev = adapter->pdev;
3952 union e1000_adv_rx_desc *rx_desc;
3953 struct igb_buffer *buffer_info;
3954 struct sk_buff *skb;
3955 unsigned int i;
3956
3957 i = rx_ring->next_to_use;
3958 buffer_info = &rx_ring->buffer_info[i];
3959
3960 while (cleaned_count--) {
3961 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3962
3963 if (adapter->rx_ps_hdr_size && !buffer_info->page) {
3964 buffer_info->page = alloc_page(GFP_ATOMIC);
3965 if (!buffer_info->page) {
3966 adapter->alloc_rx_buff_failed++;
3967 goto no_buffers;
3968 }
3969 buffer_info->page_dma =
3970 pci_map_page(pdev,
3971 buffer_info->page,
3972 0, PAGE_SIZE,
3973 PCI_DMA_FROMDEVICE);
3974 }
3975
3976 if (!buffer_info->skb) {
3977 int bufsz;
3978
3979 if (adapter->rx_ps_hdr_size)
3980 bufsz = adapter->rx_ps_hdr_size;
3981 else
3982 bufsz = adapter->rx_buffer_len;
3983 bufsz += NET_IP_ALIGN;
3984 skb = netdev_alloc_skb(netdev, bufsz);
3985
3986 if (!skb) {
3987 adapter->alloc_rx_buff_failed++;
3988 goto no_buffers;
3989 }
3990
3991 /* Make buffer alignment 2 beyond a 16 byte boundary
3992 * this will result in a 16 byte aligned IP header after
3993 * the 14 byte MAC header is removed
3994 */
3995 skb_reserve(skb, NET_IP_ALIGN);
3996
3997 buffer_info->skb = skb;
3998 buffer_info->dma = pci_map_single(pdev, skb->data,
3999 bufsz,
4000 PCI_DMA_FROMDEVICE);
4001
4002 }
4003 /* Refresh the desc even if buffer_addrs didn't change because
4004 * each write-back erases this info. */
4005 if (adapter->rx_ps_hdr_size) {
4006 rx_desc->read.pkt_addr =
4007 cpu_to_le64(buffer_info->page_dma);
4008 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
4009 } else {
4010 rx_desc->read.pkt_addr =
4011 cpu_to_le64(buffer_info->dma);
4012 rx_desc->read.hdr_addr = 0;
4013 }
4014
4015 i++;
4016 if (i == rx_ring->count)
4017 i = 0;
4018 buffer_info = &rx_ring->buffer_info[i];
4019 }
4020
4021no_buffers:
4022 if (rx_ring->next_to_use != i) {
4023 rx_ring->next_to_use = i;
4024 if (i == 0)
4025 i = (rx_ring->count - 1);
4026 else
4027 i--;
4028
4029 /* Force memory writes to complete before letting h/w
4030 * know there are new descriptors to fetch. (Only
4031 * applicable for weak-ordered memory model archs,
4032 * such as IA-64). */
4033 wmb();
4034 writel(i, adapter->hw.hw_addr + rx_ring->tail);
4035 }
4036}
4037
4038/**
4039 * igb_mii_ioctl -
4040 * @netdev:
4041 * @ifreq:
4042 * @cmd:
4043 **/
4044static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4045{
4046 struct igb_adapter *adapter = netdev_priv(netdev);
4047 struct mii_ioctl_data *data = if_mii(ifr);
4048
4049 if (adapter->hw.phy.media_type != e1000_media_type_copper)
4050 return -EOPNOTSUPP;
4051
4052 switch (cmd) {
4053 case SIOCGMIIPHY:
4054 data->phy_id = adapter->hw.phy.addr;
4055 break;
4056 case SIOCGMIIREG:
4057 if (!capable(CAP_NET_ADMIN))
4058 return -EPERM;
4059 if (adapter->hw.phy.ops.read_phy_reg(&adapter->hw,
4060 data->reg_num
4061 & 0x1F, &data->val_out))
4062 return -EIO;
4063 break;
4064 case SIOCSMIIREG:
4065 default:
4066 return -EOPNOTSUPP;
4067 }
4068 return 0;
4069}
4070
4071/**
4072 * igb_ioctl -
4073 * @netdev:
4074 * @ifreq:
4075 * @cmd:
4076 **/
4077static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4078{
4079 switch (cmd) {
4080 case SIOCGMIIPHY:
4081 case SIOCGMIIREG:
4082 case SIOCSMIIREG:
4083 return igb_mii_ioctl(netdev, ifr, cmd);
4084 default:
4085 return -EOPNOTSUPP;
4086 }
4087}
4088
4089static void igb_vlan_rx_register(struct net_device *netdev,
4090 struct vlan_group *grp)
4091{
4092 struct igb_adapter *adapter = netdev_priv(netdev);
4093 struct e1000_hw *hw = &adapter->hw;
4094 u32 ctrl, rctl;
4095
4096 igb_irq_disable(adapter);
4097 adapter->vlgrp = grp;
4098
4099 if (grp) {
4100 /* enable VLAN tag insert/strip */
4101 ctrl = rd32(E1000_CTRL);
4102 ctrl |= E1000_CTRL_VME;
4103 wr32(E1000_CTRL, ctrl);
4104
4105 /* enable VLAN receive filtering */
4106 rctl = rd32(E1000_RCTL);
4107 rctl |= E1000_RCTL_VFE;
4108 rctl &= ~E1000_RCTL_CFIEN;
4109 wr32(E1000_RCTL, rctl);
4110 igb_update_mng_vlan(adapter);
4111 wr32(E1000_RLPML,
4112 adapter->max_frame_size + VLAN_TAG_SIZE);
4113 } else {
4114 /* disable VLAN tag insert/strip */
4115 ctrl = rd32(E1000_CTRL);
4116 ctrl &= ~E1000_CTRL_VME;
4117 wr32(E1000_CTRL, ctrl);
4118
4119 /* disable VLAN filtering */
4120 rctl = rd32(E1000_RCTL);
4121 rctl &= ~E1000_RCTL_VFE;
4122 wr32(E1000_RCTL, rctl);
4123 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
4124 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4125 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
4126 }
4127 wr32(E1000_RLPML,
4128 adapter->max_frame_size);
4129 }
4130
4131 if (!test_bit(__IGB_DOWN, &adapter->state))
4132 igb_irq_enable(adapter);
4133}
4134
4135static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
4136{
4137 struct igb_adapter *adapter = netdev_priv(netdev);
4138 struct e1000_hw *hw = &adapter->hw;
4139 u32 vfta, index;
4140
4141 if ((adapter->hw.mng_cookie.status &
4142 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4143 (vid == adapter->mng_vlan_id))
4144 return;
4145 /* add VID to filter table */
4146 index = (vid >> 5) & 0x7F;
4147 vfta = array_rd32(E1000_VFTA, index);
4148 vfta |= (1 << (vid & 0x1F));
4149 igb_write_vfta(&adapter->hw, index, vfta);
4150}
4151
4152static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
4153{
4154 struct igb_adapter *adapter = netdev_priv(netdev);
4155 struct e1000_hw *hw = &adapter->hw;
4156 u32 vfta, index;
4157
4158 igb_irq_disable(adapter);
4159 vlan_group_set_device(adapter->vlgrp, vid, NULL);
4160
4161 if (!test_bit(__IGB_DOWN, &adapter->state))
4162 igb_irq_enable(adapter);
4163
4164 if ((adapter->hw.mng_cookie.status &
4165 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4166 (vid == adapter->mng_vlan_id)) {
4167 /* release control to f/w */
4168 igb_release_hw_control(adapter);
4169 return;
4170 }
4171
4172 /* remove VID from filter table */
4173 index = (vid >> 5) & 0x7F;
4174 vfta = array_rd32(E1000_VFTA, index);
4175 vfta &= ~(1 << (vid & 0x1F));
4176 igb_write_vfta(&adapter->hw, index, vfta);
4177}
4178
4179static void igb_restore_vlan(struct igb_adapter *adapter)
4180{
4181 igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
4182
4183 if (adapter->vlgrp) {
4184 u16 vid;
4185 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
4186 if (!vlan_group_get_device(adapter->vlgrp, vid))
4187 continue;
4188 igb_vlan_rx_add_vid(adapter->netdev, vid);
4189 }
4190 }
4191}
4192
4193int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
4194{
4195 struct e1000_mac_info *mac = &adapter->hw.mac;
4196
4197 mac->autoneg = 0;
4198
4199 /* Fiber NICs only allow 1000 gbps Full duplex */
4200 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) &&
4201 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
4202 dev_err(&adapter->pdev->dev,
4203 "Unsupported Speed/Duplex configuration\n");
4204 return -EINVAL;
4205 }
4206
4207 switch (spddplx) {
4208 case SPEED_10 + DUPLEX_HALF:
4209 mac->forced_speed_duplex = ADVERTISE_10_HALF;
4210 break;
4211 case SPEED_10 + DUPLEX_FULL:
4212 mac->forced_speed_duplex = ADVERTISE_10_FULL;
4213 break;
4214 case SPEED_100 + DUPLEX_HALF:
4215 mac->forced_speed_duplex = ADVERTISE_100_HALF;
4216 break;
4217 case SPEED_100 + DUPLEX_FULL:
4218 mac->forced_speed_duplex = ADVERTISE_100_FULL;
4219 break;
4220 case SPEED_1000 + DUPLEX_FULL:
4221 mac->autoneg = 1;
4222 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
4223 break;
4224 case SPEED_1000 + DUPLEX_HALF: /* not supported */
4225 default:
4226 dev_err(&adapter->pdev->dev,
4227 "Unsupported Speed/Duplex configuration\n");
4228 return -EINVAL;
4229 }
4230 return 0;
4231}
4232
4233
4234static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
4235{
4236 struct net_device *netdev = pci_get_drvdata(pdev);
4237 struct igb_adapter *adapter = netdev_priv(netdev);
4238 struct e1000_hw *hw = &adapter->hw;
2d064c06 4239 u32 ctrl, rctl, status;
9d5c8243
AK		 4240 u32 wufc = adapter->wol;
4241#ifdef CONFIG_PM
4242 int retval = 0;
4243#endif
4244
4245 netif_device_detach(netdev);
4246
4247 if (netif_running(netdev)) {
4248 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
4249 igb_down(adapter);
4250 igb_free_irq(adapter);
4251 }
4252
4253#ifdef CONFIG_PM
4254 retval = pci_save_state(pdev);
4255 if (retval)
4256 return retval;
4257#endif
4258
4259 status = rd32(E1000_STATUS);
4260 if (status & E1000_STATUS_LU)
4261 wufc &= ~E1000_WUFC_LNKC;
4262
4263 if (wufc) {
4264 igb_setup_rctl(adapter);
4265 igb_set_multi(netdev);
4266
4267 /* turn on all-multi mode if wake on multicast is enabled */
4268 if (wufc & E1000_WUFC_MC) {
4269 rctl = rd32(E1000_RCTL);
4270 rctl |= E1000_RCTL_MPE;
4271 wr32(E1000_RCTL, rctl);
4272 }
4273
4274 ctrl = rd32(E1000_CTRL);
4275 /* advertise wake from D3Cold */
4276 #define E1000_CTRL_ADVD3WUC 0x00100000
4277 /* phy power management enable */
4278 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
4279 ctrl |= E1000_CTRL_ADVD3WUC;
4280 wr32(E1000_CTRL, ctrl);
4281
9d5c8243
AK		 4282 /* Allow time for pending master requests to run */
4283 igb_disable_pcie_master(&adapter->hw);
4284
4285 wr32(E1000_WUC, E1000_WUC_PME_EN);
4286 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 4287 } else {
4288 wr32(E1000_WUC, 0);
4289 wr32(E1000_WUFC, 0);
9d5c8243
AK		 4290 }
4291
2d064c06
AD		 4292 /* make sure adapter isn't asleep if manageability/wol is enabled */
4293 if (wufc || adapter->en_mng_pt) {
9d5c8243
AK		 4294 pci_enable_wake(pdev, PCI_D3hot, 1);
4295 pci_enable_wake(pdev, PCI_D3cold, 1);
2d064c06
AD		 4296 } else {
4297 igb_shutdown_fiber_serdes_link_82575(hw);
4298 pci_enable_wake(pdev, PCI_D3hot, 0);
4299 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243
AK		 4300 }
4301
4302 /* Release control of h/w to f/w. If f/w is AMT enabled, this
4303 * would have already happened in close and is redundant. */
4304 igb_release_hw_control(adapter);
4305
4306 pci_disable_device(pdev);
4307
4308 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4309
4310 return 0;
4311}
4312
4313#ifdef CONFIG_PM
4314static int igb_resume(struct pci_dev *pdev)
4315{
4316 struct net_device *netdev = pci_get_drvdata(pdev);
4317 struct igb_adapter *adapter = netdev_priv(netdev);
4318 struct e1000_hw *hw = &adapter->hw;
4319 u32 err;
4320
4321 pci_set_power_state(pdev, PCI_D0);
4322 pci_restore_state(pdev);
42bfd33a
TI		 4323
4324 if (adapter->need_ioport)
4325 err = pci_enable_device(pdev);
4326 else
4327 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 4328 if (err) {
4329 dev_err(&pdev->dev,
4330 "igb: Cannot enable PCI device from suspend\n");
4331 return err;
4332 }
4333 pci_set_master(pdev);
4334
4335 pci_enable_wake(pdev, PCI_D3hot, 0);
4336 pci_enable_wake(pdev, PCI_D3cold, 0);
4337
4338 if (netif_running(netdev)) {
4339 err = igb_request_irq(adapter);
4340 if (err)
4341 return err;
4342 }
4343
4344 /* e1000_power_up_phy(adapter); */
4345
4346 igb_reset(adapter);
4347 wr32(E1000_WUS, ~0);
4348
4349 igb_init_manageability(adapter);
4350
4351 if (netif_running(netdev))
4352 igb_up(adapter);
4353
4354 netif_device_attach(netdev);
4355
4356 /* let the f/w know that the h/w is now under the control of the
4357 * driver. */
4358 igb_get_hw_control(adapter);
4359
4360 return 0;
4361}
4362#endif
4363
4364static void igb_shutdown(struct pci_dev *pdev)
4365{
4366 igb_suspend(pdev, PMSG_SUSPEND);
4367}
4368
4369#ifdef CONFIG_NET_POLL_CONTROLLER
4370/*
4371 * Polling 'interrupt' - used by things like netconsole to send skbs
4372 * without having to re-enable interrupts. It's not called while
4373 * the interrupt routine is executing.
4374 */
4375static void igb_netpoll(struct net_device *netdev)
4376{
4377 struct igb_adapter *adapter = netdev_priv(netdev);
4378 int i;
4379 int work_done = 0;
4380
4381 igb_irq_disable(adapter);
7dfc16fa
AD		 4382 adapter->flags |= IGB_FLAG_IN_NETPOLL;
4383
9d5c8243 4384 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 4385 igb_clean_tx_irq(&adapter->tx_ring[i]);
9d5c8243
AK		 4386
4387 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 4388 igb_clean_rx_irq_adv(&adapter->rx_ring[i],
9d5c8243
AK		 4389 &work_done,
4390 adapter->rx_ring[i].napi.weight);
4391
7dfc16fa 4392 adapter->flags &= ~IGB_FLAG_IN_NETPOLL;
9d5c8243
AK		 4393 igb_irq_enable(adapter);
4394}
4395#endif /* CONFIG_NET_POLL_CONTROLLER */
4396
4397/**
4398 * igb_io_error_detected - called when PCI error is detected
4399 * @pdev: Pointer to PCI device
4400 * @state: The current pci connection state
4401 *
4402 * This function is called after a PCI bus error affecting
4403 * this device has been detected.
4404 */
4405static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
4406 pci_channel_state_t state)
4407{
4408 struct net_device *netdev = pci_get_drvdata(pdev);
4409 struct igb_adapter *adapter = netdev_priv(netdev);
4410
4411 netif_device_detach(netdev);
4412
4413 if (netif_running(netdev))
4414 igb_down(adapter);
4415 pci_disable_device(pdev);
4416
4417 /* Request a slot slot reset. */
4418 return PCI_ERS_RESULT_NEED_RESET;
4419}
4420
4421/**
4422 * igb_io_slot_reset - called after the pci bus has been reset.
4423 * @pdev: Pointer to PCI device
4424 *
4425 * Restart the card from scratch, as if from a cold-boot. Implementation
4426 * resembles the first-half of the igb_resume routine.
4427 */
4428static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
4429{
4430 struct net_device *netdev = pci_get_drvdata(pdev);
4431 struct igb_adapter *adapter = netdev_priv(netdev);
4432 struct e1000_hw *hw = &adapter->hw;
42bfd33a 4433 int err;
9d5c8243 4434
42bfd33a
TI		 4435 if (adapter->need_ioport)
4436 err = pci_enable_device(pdev);
4437 else
4438 err = pci_enable_device_mem(pdev);
4439 if (err) {
9d5c8243
AK		 4440 dev_err(&pdev->dev,
4441 "Cannot re-enable PCI device after reset.\n");
4442 return PCI_ERS_RESULT_DISCONNECT;
4443 }
4444 pci_set_master(pdev);
c682fc23 4445 pci_restore_state(pdev);
9d5c8243
AK		 4446
4447 pci_enable_wake(pdev, PCI_D3hot, 0);
4448 pci_enable_wake(pdev, PCI_D3cold, 0);
4449
4450 igb_reset(adapter);
4451 wr32(E1000_WUS, ~0);
4452
4453 return PCI_ERS_RESULT_RECOVERED;
4454}
4455
4456/**
4457 * igb_io_resume - called when traffic can start flowing again.
4458 * @pdev: Pointer to PCI device
4459 *
4460 * This callback is called when the error recovery driver tells us that
4461 * its OK to resume normal operation. Implementation resembles the
4462 * second-half of the igb_resume routine.
4463 */
4464static void igb_io_resume(struct pci_dev *pdev)
4465{
4466 struct net_device *netdev = pci_get_drvdata(pdev);
4467 struct igb_adapter *adapter = netdev_priv(netdev);
4468
4469 igb_init_manageability(adapter);
4470
4471 if (netif_running(netdev)) {
4472 if (igb_up(adapter)) {
4473 dev_err(&pdev->dev, "igb_up failed after reset\n");
4474 return;
4475 }
4476 }
4477
4478 netif_device_attach(netdev);
4479
4480 /* let the f/w know that the h/w is now under the control of the
4481 * driver. */
4482 igb_get_hw_control(adapter);
4483
4484}
4485
4486/* igb_main.c */
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