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igb: move initialization of number of queues into set_interrupt_capability
[mirror_ubuntu-zesty-kernel.git] / drivers / net / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/module.h>
29#include <linux/types.h>
30#include <linux/init.h>
31#include <linux/vmalloc.h>
32#include <linux/pagemap.h>
33#include <linux/netdevice.h>
9d5c8243
AK		 34#include <linux/ipv6.h>
35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
37#include <linux/mii.h>
38#include <linux/ethtool.h>
39#include <linux/if_vlan.h>
40#include <linux/pci.h>
c54106bb 41#include <linux/pci-aspm.h>
9d5c8243
AK		 42#include <linux/delay.h>
43#include <linux/interrupt.h>
44#include <linux/if_ether.h>
40a914fa 45#include <linux/aer.h>
421e02f0 46#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 47#include <linux/dca.h>
48#endif
9d5c8243
AK		 49#include "igb.h"
50
0024fd00 51#define DRV_VERSION "1.2.45-k2"
9d5c8243
AK		 52char igb_driver_name[] = "igb";
53char igb_driver_version[] = DRV_VERSION;
54static const char igb_driver_string[] =
55 "Intel(R) Gigabit Ethernet Network Driver";
2d064c06 56static const char igb_copyright[] = "Copyright (c) 2008 Intel Corporation.";
9d5c8243 57
9d5c8243
AK		 58static const struct e1000_info *igb_info_tbl[] = {
59 [board_82575] = &e1000_82575_info,
60};
61
62static struct pci_device_id igb_pci_tbl[] = {
2d064c06
AD		 63 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
9d5c8243
AK		 66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
69 /* required last entry */
70 {0, }
71};
72
73MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
74
75void igb_reset(struct igb_adapter *);
76static int igb_setup_all_tx_resources(struct igb_adapter *);
77static int igb_setup_all_rx_resources(struct igb_adapter *);
78static void igb_free_all_tx_resources(struct igb_adapter *);
79static void igb_free_all_rx_resources(struct igb_adapter *);
9d5c8243
AK		 80void igb_update_stats(struct igb_adapter *);
81static int igb_probe(struct pci_dev *, const struct pci_device_id *);
82static void __devexit igb_remove(struct pci_dev *pdev);
83static int igb_sw_init(struct igb_adapter *);
84static int igb_open(struct net_device *);
85static int igb_close(struct net_device *);
86static void igb_configure_tx(struct igb_adapter *);
87static void igb_configure_rx(struct igb_adapter *);
88static void igb_setup_rctl(struct igb_adapter *);
89static void igb_clean_all_tx_rings(struct igb_adapter *);
90static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 91static void igb_clean_tx_ring(struct igb_ring *);
92static void igb_clean_rx_ring(struct igb_ring *);
9d5c8243
AK		 93static void igb_set_multi(struct net_device *);
94static void igb_update_phy_info(unsigned long);
95static void igb_watchdog(unsigned long);
96static void igb_watchdog_task(struct work_struct *);
97static int igb_xmit_frame_ring_adv(struct sk_buff *, struct net_device *,
98 struct igb_ring *);
99static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
100static struct net_device_stats *igb_get_stats(struct net_device *);
101static int igb_change_mtu(struct net_device *, int);
102static int igb_set_mac(struct net_device *, void *);
103static irqreturn_t igb_intr(int irq, void *);
104static irqreturn_t igb_intr_msi(int irq, void *);
105static irqreturn_t igb_msix_other(int irq, void *);
106static irqreturn_t igb_msix_rx(int irq, void *);
107static irqreturn_t igb_msix_tx(int irq, void *);
108static int igb_clean_rx_ring_msix(struct napi_struct *, int);
421e02f0 109#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 110static void igb_update_rx_dca(struct igb_ring *);
111static void igb_update_tx_dca(struct igb_ring *);
112static void igb_setup_dca(struct igb_adapter *);
421e02f0 113#endif /* CONFIG_IGB_DCA */
3b644cf6 114static bool igb_clean_tx_irq(struct igb_ring *);
661086df 115static int igb_poll(struct napi_struct *, int);
3b644cf6
MW		 116static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int);
117static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
9d5c8243
AK		 118static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
119static void igb_tx_timeout(struct net_device *);
120static void igb_reset_task(struct work_struct *);
121static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
122static void igb_vlan_rx_add_vid(struct net_device *, u16);
123static void igb_vlan_rx_kill_vid(struct net_device *, u16);
124static void igb_restore_vlan(struct igb_adapter *);
125
126static int igb_suspend(struct pci_dev *, pm_message_t);
127#ifdef CONFIG_PM
128static int igb_resume(struct pci_dev *);
129#endif
130static void igb_shutdown(struct pci_dev *);
421e02f0 131#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 132static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
133static struct notifier_block dca_notifier = {
134 .notifier_call = igb_notify_dca,
135 .next = NULL,
136 .priority = 0
137};
138#endif
9d5c8243
AK		 139
140#ifdef CONFIG_NET_POLL_CONTROLLER
141/* for netdump / net console */
142static void igb_netpoll(struct net_device *);
143#endif
144
145static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
146 pci_channel_state_t);
147static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
148static void igb_io_resume(struct pci_dev *);
149
150static struct pci_error_handlers igb_err_handler = {
151 .error_detected = igb_io_error_detected,
152 .slot_reset = igb_io_slot_reset,
153 .resume = igb_io_resume,
154};
155
156
157static struct pci_driver igb_driver = {
158 .name = igb_driver_name,
159 .id_table = igb_pci_tbl,
160 .probe = igb_probe,
161 .remove = __devexit_p(igb_remove),
162#ifdef CONFIG_PM
163 /* Power Managment Hooks */
164 .suspend = igb_suspend,
165 .resume = igb_resume,
166#endif
167 .shutdown = igb_shutdown,
168 .err_handler = &igb_err_handler
169};
170
7dfc16fa
AD		 171static int global_quad_port_a; /* global quad port a indication */
172
9d5c8243
AK		 173MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
174MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
175MODULE_LICENSE("GPL");
176MODULE_VERSION(DRV_VERSION);
177
178#ifdef DEBUG
179/**
180 * igb_get_hw_dev_name - return device name string
181 * used by hardware layer to print debugging information
182 **/
183char *igb_get_hw_dev_name(struct e1000_hw *hw)
184{
185 struct igb_adapter *adapter = hw->back;
186 return adapter->netdev->name;
187}
188#endif
189
190/**
191 * igb_init_module - Driver Registration Routine
192 *
193 * igb_init_module is the first routine called when the driver is
194 * loaded. All it does is register with the PCI subsystem.
195 **/
196static int __init igb_init_module(void)
197{
198 int ret;
199 printk(KERN_INFO "%s - version %s\n",
200 igb_driver_string, igb_driver_version);
201
202 printk(KERN_INFO "%s\n", igb_copyright);
203
7dfc16fa
AD		 204 global_quad_port_a = 0;
205
421e02f0 206#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 207 dca_register_notify(&dca_notifier);
208#endif
bbd98fe4
AD		 209
210 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 211 return ret;
212}
213
214module_init(igb_init_module);
215
216/**
217 * igb_exit_module - Driver Exit Cleanup Routine
218 *
219 * igb_exit_module is called just before the driver is removed
220 * from memory.
221 **/
222static void __exit igb_exit_module(void)
223{
421e02f0 224#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 225 dca_unregister_notify(&dca_notifier);
226#endif
9d5c8243
AK		 227 pci_unregister_driver(&igb_driver);
228}
229
230module_exit(igb_exit_module);
231
26bc19ec
AD		 232#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
233/**
234 * igb_cache_ring_register - Descriptor ring to register mapping
235 * @adapter: board private structure to initialize
236 *
237 * Once we know the feature-set enabled for the device, we'll cache
238 * the register offset the descriptor ring is assigned to.
239 **/
240static void igb_cache_ring_register(struct igb_adapter *adapter)
241{
242 int i;
243
244 switch (adapter->hw.mac.type) {
245 case e1000_82576:
246 /* The queues are allocated for virtualization such that VF 0
247 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
248 * In order to avoid collision we start at the first free queue
249 * and continue consuming queues in the same sequence
250 */
251 for (i = 0; i < adapter->num_rx_queues; i++)
252 adapter->rx_ring[i].reg_idx = Q_IDX_82576(i);
253 for (i = 0; i < adapter->num_tx_queues; i++)
254 adapter->tx_ring[i].reg_idx = Q_IDX_82576(i);
255 break;
256 case e1000_82575:
257 default:
258 for (i = 0; i < adapter->num_rx_queues; i++)
259 adapter->rx_ring[i].reg_idx = i;
260 for (i = 0; i < adapter->num_tx_queues; i++)
261 adapter->tx_ring[i].reg_idx = i;
262 break;
263 }
264}
265
9d5c8243
AK		 266/**
267 * igb_alloc_queues - Allocate memory for all rings
268 * @adapter: board private structure to initialize
269 *
270 * We allocate one ring per queue at run-time since we don't know the
271 * number of queues at compile-time.
272 **/
273static int igb_alloc_queues(struct igb_adapter *adapter)
274{
275 int i;
276
277 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
278 sizeof(struct igb_ring), GFP_KERNEL);
279 if (!adapter->tx_ring)
280 return -ENOMEM;
281
282 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
283 sizeof(struct igb_ring), GFP_KERNEL);
284 if (!adapter->rx_ring) {
285 kfree(adapter->tx_ring);
286 return -ENOMEM;
287 }
288
6eb5a7f1
AD		 289 adapter->rx_ring->buddy = adapter->tx_ring;
290
661086df
PWJ		 291 for (i = 0; i < adapter->num_tx_queues; i++) {
292 struct igb_ring *ring = &(adapter->tx_ring[i]);
68fd9910 293 ring->count = adapter->tx_ring_count;
661086df
PWJ		 294 ring->adapter = adapter;
295 ring->queue_index = i;
296 }
9d5c8243
AK		 297 for (i = 0; i < adapter->num_rx_queues; i++) {
298 struct igb_ring *ring = &(adapter->rx_ring[i]);
68fd9910 299 ring->count = adapter->rx_ring_count;
9d5c8243 300 ring->adapter = adapter;
844290e5 301 ring->queue_index = i;
9d5c8243
AK		 302 ring->itr_register = E1000_ITR;
303
844290e5 304 /* set a default napi handler for each rx_ring */
661086df 305 netif_napi_add(adapter->netdev, &ring->napi, igb_poll, 64);
9d5c8243 306 }
26bc19ec
AD		 307
308 igb_cache_ring_register(adapter);
9d5c8243
AK		 309 return 0;
310}
311
a88f10ec
AD		 312static void igb_free_queues(struct igb_adapter *adapter)
313{
314 int i;
315
316 for (i = 0; i < adapter->num_rx_queues; i++)
317 netif_napi_del(&adapter->rx_ring[i].napi);
318
319 kfree(adapter->tx_ring);
320 kfree(adapter->rx_ring);
321}
322
9d5c8243
AK		 323#define IGB_N0_QUEUE -1
324static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
325 int tx_queue, int msix_vector)
326{
327 u32 msixbm = 0;
328 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 329 u32 ivar, index;
330
331 switch (hw->mac.type) {
332 case e1000_82575:
9d5c8243
AK		 333 /* The 82575 assigns vectors using a bitmask, which matches the
334 bitmask for the EICR/EIMS/EIMC registers. To assign one
335 or more queues to a vector, we write the appropriate bits
336 into the MSIXBM register for that vector. */
337 if (rx_queue > IGB_N0_QUEUE) {
338 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
339 adapter->rx_ring[rx_queue].eims_value = msixbm;
340 }
341 if (tx_queue > IGB_N0_QUEUE) {
342 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
343 adapter->tx_ring[tx_queue].eims_value =
344 E1000_EICR_TX_QUEUE0 << tx_queue;
345 }
346 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
2d064c06
AD		 347 break;
348 case e1000_82576:
26bc19ec 349 /* 82576 uses a table-based method for assigning vectors.
2d064c06
AD		 350 Each queue has a single entry in the table to which we write
351 a vector number along with a "valid" bit. Sadly, the layout
352 of the table is somewhat counterintuitive. */
353 if (rx_queue > IGB_N0_QUEUE) {
26bc19ec 354 index = (rx_queue >> 1);
2d064c06 355 ivar = array_rd32(E1000_IVAR0, index);
26bc19ec 356 if (rx_queue & 0x1) {
2d064c06
AD		 357 /* vector goes into third byte of register */
358 ivar = ivar & 0xFF00FFFF;
359 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
26bc19ec
AD		 360 } else {
361 /* vector goes into low byte of register */
362 ivar = ivar & 0xFFFFFF00;
363 ivar |= msix_vector | E1000_IVAR_VALID;
2d064c06
AD		 364 }
365 adapter->rx_ring[rx_queue].eims_value= 1 << msix_vector;
366 array_wr32(E1000_IVAR0, index, ivar);
367 }
368 if (tx_queue > IGB_N0_QUEUE) {
26bc19ec 369 index = (tx_queue >> 1);
2d064c06 370 ivar = array_rd32(E1000_IVAR0, index);
26bc19ec 371 if (tx_queue & 0x1) {
2d064c06
AD		 372 /* vector goes into high byte of register */
373 ivar = ivar & 0x00FFFFFF;
374 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
26bc19ec
AD		 375 } else {
376 /* vector goes into second byte of register */
377 ivar = ivar & 0xFFFF00FF;
378 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
2d064c06
AD		 379 }
380 adapter->tx_ring[tx_queue].eims_value= 1 << msix_vector;
381 array_wr32(E1000_IVAR0, index, ivar);
382 }
383 break;
384 default:
385 BUG();
386 break;
387 }
9d5c8243
AK		 388}
389
390/**
391 * igb_configure_msix - Configure MSI-X hardware
392 *
393 * igb_configure_msix sets up the hardware to properly
394 * generate MSI-X interrupts.
395 **/
396static void igb_configure_msix(struct igb_adapter *adapter)
397{
398 u32 tmp;
399 int i, vector = 0;
400 struct e1000_hw *hw = &adapter->hw;
401
402 adapter->eims_enable_mask = 0;
2d064c06
AD		 403 if (hw->mac.type == e1000_82576)
404 /* Turn on MSI-X capability first, or our settings
405 * won't stick. And it will take days to debug. */
406 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
407 E1000_GPIE_PBA | E1000_GPIE_EIAME |
408 E1000_GPIE_NSICR);
9d5c8243
AK		 409
410 for (i = 0; i < adapter->num_tx_queues; i++) {
411 struct igb_ring *tx_ring = &adapter->tx_ring[i];
412 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
413 adapter->eims_enable_mask |= tx_ring->eims_value;
414 if (tx_ring->itr_val)
6eb5a7f1 415 writel(tx_ring->itr_val,
9d5c8243
AK		 416 hw->hw_addr + tx_ring->itr_register);
417 else
418 writel(1, hw->hw_addr + tx_ring->itr_register);
419 }
420
421 for (i = 0; i < adapter->num_rx_queues; i++) {
422 struct igb_ring *rx_ring = &adapter->rx_ring[i];
25ac3c24 423 rx_ring->buddy = NULL;
9d5c8243
AK		 424 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
425 adapter->eims_enable_mask |= rx_ring->eims_value;
426 if (rx_ring->itr_val)
6eb5a7f1 427 writel(rx_ring->itr_val,
9d5c8243
AK		 428 hw->hw_addr + rx_ring->itr_register);
429 else
430 writel(1, hw->hw_addr + rx_ring->itr_register);
431 }
432
433
434 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 435 switch (hw->mac.type) {
436 case e1000_82575:
9d5c8243
AK		 437 array_wr32(E1000_MSIXBM(0), vector++,
438 E1000_EIMS_OTHER);
439
9d5c8243
AK		 440 tmp = rd32(E1000_CTRL_EXT);
441 /* enable MSI-X PBA support*/
442 tmp |= E1000_CTRL_EXT_PBA_CLR;
443
444 /* Auto-Mask interrupts upon ICR read. */
445 tmp |= E1000_CTRL_EXT_EIAME;
446 tmp |= E1000_CTRL_EXT_IRCA;
447
448 wr32(E1000_CTRL_EXT, tmp);
449 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
844290e5 450 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 451
2d064c06
AD		 452 break;
453
454 case e1000_82576:
455 tmp = (vector++ | E1000_IVAR_VALID) << 8;
456 wr32(E1000_IVAR_MISC, tmp);
457
458 adapter->eims_enable_mask = (1 << (vector)) - 1;
459 adapter->eims_other = 1 << (vector - 1);
460 break;
461 default:
462 /* do nothing, since nothing else supports MSI-X */
463 break;
464 } /* switch (hw->mac.type) */
9d5c8243
AK		 465 wrfl();
466}
467
468/**
469 * igb_request_msix - Initialize MSI-X interrupts
470 *
471 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
472 * kernel.
473 **/
474static int igb_request_msix(struct igb_adapter *adapter)
475{
476 struct net_device *netdev = adapter->netdev;
477 int i, err = 0, vector = 0;
478
479 vector = 0;
480
481 for (i = 0; i < adapter->num_tx_queues; i++) {
482 struct igb_ring *ring = &(adapter->tx_ring[i]);
cb7b48f6 483 sprintf(ring->name, "%s-tx-%d", netdev->name, i);
9d5c8243
AK		 484 err = request_irq(adapter->msix_entries[vector].vector,
485 &igb_msix_tx, 0, ring->name,
486 &(adapter->tx_ring[i]));
487 if (err)
488 goto out;
489 ring->itr_register = E1000_EITR(0) + (vector << 2);
6eb5a7f1 490 ring->itr_val = 976; /* ~4000 ints/sec */
9d5c8243
AK		 491 vector++;
492 }
493 for (i = 0; i < adapter->num_rx_queues; i++) {
494 struct igb_ring *ring = &(adapter->rx_ring[i]);
495 if (strlen(netdev->name) < (IFNAMSIZ - 5))
cb7b48f6 496 sprintf(ring->name, "%s-rx-%d", netdev->name, i);
9d5c8243
AK		 497 else
498 memcpy(ring->name, netdev->name, IFNAMSIZ);
499 err = request_irq(adapter->msix_entries[vector].vector,
500 &igb_msix_rx, 0, ring->name,
501 &(adapter->rx_ring[i]));
502 if (err)
503 goto out;
504 ring->itr_register = E1000_EITR(0) + (vector << 2);
505 ring->itr_val = adapter->itr;
844290e5
PW		 506 /* overwrite the poll routine for MSIX, we've already done
507 * netif_napi_add */
508 ring->napi.poll = &igb_clean_rx_ring_msix;
9d5c8243
AK		 509 vector++;
510 }
511
512 err = request_irq(adapter->msix_entries[vector].vector,
513 &igb_msix_other, 0, netdev->name, netdev);
514 if (err)
515 goto out;
516
9d5c8243
AK		 517 igb_configure_msix(adapter);
518 return 0;
519out:
520 return err;
521}
522
523static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
524{
525 if (adapter->msix_entries) {
526 pci_disable_msix(adapter->pdev);
527 kfree(adapter->msix_entries);
528 adapter->msix_entries = NULL;
7dfc16fa 529 } else if (adapter->flags & IGB_FLAG_HAS_MSI)
9d5c8243
AK		 530 pci_disable_msi(adapter->pdev);
531 return;
532}
533
534
535/**
536 * igb_set_interrupt_capability - set MSI or MSI-X if supported
537 *
538 * Attempt to configure interrupts using the best available
539 * capabilities of the hardware and kernel.
540 **/
541static void igb_set_interrupt_capability(struct igb_adapter *adapter)
542{
543 int err;
544 int numvecs, i;
545
83b7180d
AD		 546 /* Number of supported queues. */
547 /* Having more queues than CPUs doesn't make sense. */
548 adapter->num_rx_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
549 adapter->num_tx_queues = min_t(u32, IGB_MAX_TX_QUEUES, num_online_cpus());
550
9d5c8243
AK		 551 numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1;
552 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
553 GFP_KERNEL);
554 if (!adapter->msix_entries)
555 goto msi_only;
556
557 for (i = 0; i < numvecs; i++)
558 adapter->msix_entries[i].entry = i;
559
560 err = pci_enable_msix(adapter->pdev,
561 adapter->msix_entries,
562 numvecs);
563 if (err == 0)
34a20e89 564 goto out;
9d5c8243
AK		 565
566 igb_reset_interrupt_capability(adapter);
567
568 /* If we can't do MSI-X, try MSI */
569msi_only:
570 adapter->num_rx_queues = 1;
661086df 571 adapter->num_tx_queues = 1;
9d5c8243 572 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 573 adapter->flags |= IGB_FLAG_HAS_MSI;
34a20e89 574out:
661086df 575 /* Notify the stack of the (possibly) reduced Tx Queue count. */
fd2ea0a7 576 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
9d5c8243
AK		 577 return;
578}
579
580/**
581 * igb_request_irq - initialize interrupts
582 *
583 * Attempts to configure interrupts using the best available
584 * capabilities of the hardware and kernel.
585 **/
586static int igb_request_irq(struct igb_adapter *adapter)
587{
588 struct net_device *netdev = adapter->netdev;
589 struct e1000_hw *hw = &adapter->hw;
590 int err = 0;
591
592 if (adapter->msix_entries) {
593 err = igb_request_msix(adapter);
844290e5 594 if (!err)
9d5c8243 595 goto request_done;
9d5c8243
AK		 596 /* fall back to MSI */
597 igb_reset_interrupt_capability(adapter);
598 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 599 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 600 igb_free_all_tx_resources(adapter);
601 igb_free_all_rx_resources(adapter);
602 adapter->num_rx_queues = 1;
603 igb_alloc_queues(adapter);
844290e5 604 } else {
2d064c06
AD		 605 switch (hw->mac.type) {
606 case e1000_82575:
607 wr32(E1000_MSIXBM(0),
608 (E1000_EICR_RX_QUEUE0 | E1000_EIMS_OTHER));
609 break;
610 case e1000_82576:
611 wr32(E1000_IVAR0, E1000_IVAR_VALID);
612 break;
613 default:
614 break;
615 }
9d5c8243 616 }
844290e5 617
7dfc16fa 618 if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243
AK		 619 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
620 netdev->name, netdev);
621 if (!err)
622 goto request_done;
623 /* fall back to legacy interrupts */
624 igb_reset_interrupt_capability(adapter);
7dfc16fa 625 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 626 }
627
628 err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
629 netdev->name, netdev);
630
6cb5e577 631 if (err)
9d5c8243
AK		 632 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
633 err);
9d5c8243
AK		 634
635request_done:
636 return err;
637}
638
639static void igb_free_irq(struct igb_adapter *adapter)
640{
641 struct net_device *netdev = adapter->netdev;
642
643 if (adapter->msix_entries) {
644 int vector = 0, i;
645
646 for (i = 0; i < adapter->num_tx_queues; i++)
647 free_irq(adapter->msix_entries[vector++].vector,
648 &(adapter->tx_ring[i]));
649 for (i = 0; i < adapter->num_rx_queues; i++)
650 free_irq(adapter->msix_entries[vector++].vector,
651 &(adapter->rx_ring[i]));
652
653 free_irq(adapter->msix_entries[vector++].vector, netdev);
654 return;
655 }
656
657 free_irq(adapter->pdev->irq, netdev);
658}
659
660/**
661 * igb_irq_disable - Mask off interrupt generation on the NIC
662 * @adapter: board private structure
663 **/
664static void igb_irq_disable(struct igb_adapter *adapter)
665{
666 struct e1000_hw *hw = &adapter->hw;
667
668 if (adapter->msix_entries) {
844290e5 669 wr32(E1000_EIAM, 0);
9d5c8243
AK		 670 wr32(E1000_EIMC, ~0);
671 wr32(E1000_EIAC, 0);
672 }
844290e5
PW		 673
674 wr32(E1000_IAM, 0);
9d5c8243
AK		 675 wr32(E1000_IMC, ~0);
676 wrfl();
677 synchronize_irq(adapter->pdev->irq);
678}
679
680/**
681 * igb_irq_enable - Enable default interrupt generation settings
682 * @adapter: board private structure
683 **/
684static void igb_irq_enable(struct igb_adapter *adapter)
685{
686 struct e1000_hw *hw = &adapter->hw;
687
688 if (adapter->msix_entries) {
844290e5
PW		 689 wr32(E1000_EIAC, adapter->eims_enable_mask);
690 wr32(E1000_EIAM, adapter->eims_enable_mask);
691 wr32(E1000_EIMS, adapter->eims_enable_mask);
9d5c8243 692 wr32(E1000_IMS, E1000_IMS_LSC);
844290e5
PW		 693 } else {
694 wr32(E1000_IMS, IMS_ENABLE_MASK);
695 wr32(E1000_IAM, IMS_ENABLE_MASK);
696 }
9d5c8243
AK		 697}
698
699static void igb_update_mng_vlan(struct igb_adapter *adapter)
700{
701 struct net_device *netdev = adapter->netdev;
702 u16 vid = adapter->hw.mng_cookie.vlan_id;
703 u16 old_vid = adapter->mng_vlan_id;
704 if (adapter->vlgrp) {
705 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
706 if (adapter->hw.mng_cookie.status &
707 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
708 igb_vlan_rx_add_vid(netdev, vid);
709 adapter->mng_vlan_id = vid;
710 } else
711 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
712
713 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
714 (vid != old_vid) &&
715 !vlan_group_get_device(adapter->vlgrp, old_vid))
716 igb_vlan_rx_kill_vid(netdev, old_vid);
717 } else
718 adapter->mng_vlan_id = vid;
719 }
720}
721
722/**
723 * igb_release_hw_control - release control of the h/w to f/w
724 * @adapter: address of board private structure
725 *
726 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
727 * For ASF and Pass Through versions of f/w this means that the
728 * driver is no longer loaded.
729 *
730 **/
731static void igb_release_hw_control(struct igb_adapter *adapter)
732{
733 struct e1000_hw *hw = &adapter->hw;
734 u32 ctrl_ext;
735
736 /* Let firmware take over control of h/w */
737 ctrl_ext = rd32(E1000_CTRL_EXT);
738 wr32(E1000_CTRL_EXT,
739 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
740}
741
742
743/**
744 * igb_get_hw_control - get control of the h/w from f/w
745 * @adapter: address of board private structure
746 *
747 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
748 * For ASF and Pass Through versions of f/w this means that
749 * the driver is loaded.
750 *
751 **/
752static void igb_get_hw_control(struct igb_adapter *adapter)
753{
754 struct e1000_hw *hw = &adapter->hw;
755 u32 ctrl_ext;
756
757 /* Let firmware know the driver has taken over */
758 ctrl_ext = rd32(E1000_CTRL_EXT);
759 wr32(E1000_CTRL_EXT,
760 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
761}
762
9d5c8243
AK		 763/**
764 * igb_configure - configure the hardware for RX and TX
765 * @adapter: private board structure
766 **/
767static void igb_configure(struct igb_adapter *adapter)
768{
769 struct net_device *netdev = adapter->netdev;
770 int i;
771
772 igb_get_hw_control(adapter);
773 igb_set_multi(netdev);
774
775 igb_restore_vlan(adapter);
9d5c8243
AK		 776
777 igb_configure_tx(adapter);
778 igb_setup_rctl(adapter);
779 igb_configure_rx(adapter);
662d7205
AD		 780
781 igb_rx_fifo_flush_82575(&adapter->hw);
782
9d5c8243
AK		 783 /* call IGB_DESC_UNUSED which always leaves
784 * at least 1 descriptor unused to make sure
785 * next_to_use != next_to_clean */
786 for (i = 0; i < adapter->num_rx_queues; i++) {
787 struct igb_ring *ring = &adapter->rx_ring[i];
3b644cf6 788 igb_alloc_rx_buffers_adv(ring, IGB_DESC_UNUSED(ring));
9d5c8243
AK		 789 }
790
791
792 adapter->tx_queue_len = netdev->tx_queue_len;
793}
794
795
796/**
797 * igb_up - Open the interface and prepare it to handle traffic
798 * @adapter: board private structure
799 **/
800
801int igb_up(struct igb_adapter *adapter)
802{
803 struct e1000_hw *hw = &adapter->hw;
804 int i;
805
806 /* hardware has been reset, we need to reload some things */
807 igb_configure(adapter);
808
809 clear_bit(__IGB_DOWN, &adapter->state);
810
844290e5
PW		 811 for (i = 0; i < adapter->num_rx_queues; i++)
812 napi_enable(&adapter->rx_ring[i].napi);
813 if (adapter->msix_entries)
9d5c8243 814 igb_configure_msix(adapter);
9d5c8243
AK		 815
816 /* Clear any pending interrupts. */
817 rd32(E1000_ICR);
818 igb_irq_enable(adapter);
819
820 /* Fire a link change interrupt to start the watchdog. */
821 wr32(E1000_ICS, E1000_ICS_LSC);
822 return 0;
823}
824
825void igb_down(struct igb_adapter *adapter)
826{
827 struct e1000_hw *hw = &adapter->hw;
828 struct net_device *netdev = adapter->netdev;
829 u32 tctl, rctl;
830 int i;
831
832 /* signal that we're down so the interrupt handler does not
833 * reschedule our watchdog timer */
834 set_bit(__IGB_DOWN, &adapter->state);
835
836 /* disable receives in the hardware */
837 rctl = rd32(E1000_RCTL);
838 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
839 /* flush and sleep below */
840
fd2ea0a7 841 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 842
843 /* disable transmits in the hardware */
844 tctl = rd32(E1000_TCTL);
845 tctl &= ~E1000_TCTL_EN;
846 wr32(E1000_TCTL, tctl);
847 /* flush both disables and wait for them to finish */
848 wrfl();
849 msleep(10);
850
844290e5
PW		 851 for (i = 0; i < adapter->num_rx_queues; i++)
852 napi_disable(&adapter->rx_ring[i].napi);
9d5c8243 853
9d5c8243
AK		 854 igb_irq_disable(adapter);
855
856 del_timer_sync(&adapter->watchdog_timer);
857 del_timer_sync(&adapter->phy_info_timer);
858
859 netdev->tx_queue_len = adapter->tx_queue_len;
860 netif_carrier_off(netdev);
861 adapter->link_speed = 0;
862 adapter->link_duplex = 0;
863
3023682e
JK		 864 if (!pci_channel_offline(adapter->pdev))
865 igb_reset(adapter);
9d5c8243
AK		 866 igb_clean_all_tx_rings(adapter);
867 igb_clean_all_rx_rings(adapter);
868}
869
870void igb_reinit_locked(struct igb_adapter *adapter)
871{
872 WARN_ON(in_interrupt());
873 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
874 msleep(1);
875 igb_down(adapter);
876 igb_up(adapter);
877 clear_bit(__IGB_RESETTING, &adapter->state);
878}
879
880void igb_reset(struct igb_adapter *adapter)
881{
882 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 883 struct e1000_mac_info *mac = &hw->mac;
884 struct e1000_fc_info *fc = &hw->fc;
9d5c8243
AK		 885 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
886 u16 hwm;
887
888 /* Repartition Pba for greater than 9k mtu
889 * To take effect CTRL.RST is required.
890 */
2d064c06 891 if (mac->type != e1000_82576) {
9d5c8243 892 pba = E1000_PBA_34K;
2d064c06
AD		 893 }
894 else {
895 pba = E1000_PBA_64K;
896 }
9d5c8243 897
2d064c06
AD		 898 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
899 (mac->type < e1000_82576)) {
9d5c8243
AK		 900 /* adjust PBA for jumbo frames */
901 wr32(E1000_PBA, pba);
902
903 /* To maintain wire speed transmits, the Tx FIFO should be
904 * large enough to accommodate two full transmit packets,
905 * rounded up to the next 1KB and expressed in KB. Likewise,
906 * the Rx FIFO should be large enough to accommodate at least
907 * one full receive packet and is similarly rounded up and
908 * expressed in KB. */
909 pba = rd32(E1000_PBA);
910 /* upper 16 bits has Tx packet buffer allocation size in KB */
911 tx_space = pba >> 16;
912 /* lower 16 bits has Rx packet buffer allocation size in KB */
913 pba &= 0xffff;
914 /* the tx fifo also stores 16 bytes of information about the tx
915 * but don't include ethernet FCS because hardware appends it */
916 min_tx_space = (adapter->max_frame_size +
917 sizeof(struct e1000_tx_desc) -
918 ETH_FCS_LEN) * 2;
919 min_tx_space = ALIGN(min_tx_space, 1024);
920 min_tx_space >>= 10;
921 /* software strips receive CRC, so leave room for it */
922 min_rx_space = adapter->max_frame_size;
923 min_rx_space = ALIGN(min_rx_space, 1024);
924 min_rx_space >>= 10;
925
926 /* If current Tx allocation is less than the min Tx FIFO size,
927 * and the min Tx FIFO size is less than the current Rx FIFO
928 * allocation, take space away from current Rx allocation */
929 if (tx_space < min_tx_space &&
930 ((min_tx_space - tx_space) < pba)) {
931 pba = pba - (min_tx_space - tx_space);
932
933 /* if short on rx space, rx wins and must trump tx
934 * adjustment */
935 if (pba < min_rx_space)
936 pba = min_rx_space;
937 }
2d064c06 938 wr32(E1000_PBA, pba);
9d5c8243 939 }
9d5c8243
AK		 940
941 /* flow control settings */
942 /* The high water mark must be low enough to fit one full frame
943 * (or the size used for early receive) above it in the Rx FIFO.
944 * Set it to the lower of:
945 * - 90% of the Rx FIFO size, or
946 * - the full Rx FIFO size minus one full frame */
947 hwm = min(((pba << 10) * 9 / 10),
2d064c06 948 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 949
2d064c06
AD		 950 if (mac->type < e1000_82576) {
951 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
952 fc->low_water = fc->high_water - 8;
953 } else {
954 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
955 fc->low_water = fc->high_water - 16;
956 }
9d5c8243
AK		 957 fc->pause_time = 0xFFFF;
958 fc->send_xon = 1;
959 fc->type = fc->original_type;
960
961 /* Allow time for pending master requests to run */
962 adapter->hw.mac.ops.reset_hw(&adapter->hw);
963 wr32(E1000_WUC, 0);
964
965 if (adapter->hw.mac.ops.init_hw(&adapter->hw))
966 dev_err(&adapter->pdev->dev, "Hardware Error\n");
967
968 igb_update_mng_vlan(adapter);
969
970 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
971 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
972
973 igb_reset_adaptive(&adapter->hw);
f5f4cf08 974 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 975}
976
42bfd33a
TI		 977/**
978 * igb_is_need_ioport - determine if an adapter needs ioport resources or not
979 * @pdev: PCI device information struct
980 *
981 * Returns true if an adapter needs ioport resources
982 **/
983static int igb_is_need_ioport(struct pci_dev *pdev)
984{
985 switch (pdev->device) {
986 /* Currently there are no adapters that need ioport resources */
987 default:
988 return false;
989 }
990}
991
2e5c6922
SH		 992static const struct net_device_ops igb_netdev_ops = {
993 .ndo_open = igb_open,
994 .ndo_stop = igb_close,
00829823 995 .ndo_start_xmit = igb_xmit_frame_adv,
2e5c6922
SH		 996 .ndo_get_stats = igb_get_stats,
997 .ndo_set_multicast_list = igb_set_multi,
998 .ndo_set_mac_address = igb_set_mac,
999 .ndo_change_mtu = igb_change_mtu,
1000 .ndo_do_ioctl = igb_ioctl,
1001 .ndo_tx_timeout = igb_tx_timeout,
1002 .ndo_validate_addr = eth_validate_addr,
1003 .ndo_vlan_rx_register = igb_vlan_rx_register,
1004 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1005 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
1006#ifdef CONFIG_NET_POLL_CONTROLLER
1007 .ndo_poll_controller = igb_netpoll,
1008#endif
1009};
1010
9d5c8243
AK		 1011/**
1012 * igb_probe - Device Initialization Routine
1013 * @pdev: PCI device information struct
1014 * @ent: entry in igb_pci_tbl
1015 *
1016 * Returns 0 on success, negative on failure
1017 *
1018 * igb_probe initializes an adapter identified by a pci_dev structure.
1019 * The OS initialization, configuring of the adapter private structure,
1020 * and a hardware reset occur.
1021 **/
1022static int __devinit igb_probe(struct pci_dev *pdev,
1023 const struct pci_device_id *ent)
1024{
1025 struct net_device *netdev;
1026 struct igb_adapter *adapter;
1027 struct e1000_hw *hw;
c54106bb 1028 struct pci_dev *us_dev;
9d5c8243
AK		 1029 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1030 unsigned long mmio_start, mmio_len;
c54106bb
AD		 1031 int i, err, pci_using_dac, pos;
1032 u16 eeprom_data = 0, state = 0;
9d5c8243
AK		 1033 u16 eeprom_apme_mask = IGB_EEPROM_APME;
1034 u32 part_num;
42bfd33a 1035 int bars, need_ioport;
9d5c8243 1036
42bfd33a
TI		 1037 /* do not allocate ioport bars when not needed */
1038 need_ioport = igb_is_need_ioport(pdev);
1039 if (need_ioport) {
1040 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
1041 err = pci_enable_device(pdev);
1042 } else {
1043 bars = pci_select_bars(pdev, IORESOURCE_MEM);
1044 err = pci_enable_device_mem(pdev);
1045 }
9d5c8243
AK		 1046 if (err)
1047 return err;
1048
1049 pci_using_dac = 0;
1050 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
1051 if (!err) {
1052 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1053 if (!err)
1054 pci_using_dac = 1;
1055 } else {
1056 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1057 if (err) {
1058 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1059 if (err) {
1060 dev_err(&pdev->dev, "No usable DMA "
1061 "configuration, aborting\n");
1062 goto err_dma;
1063 }
1064 }
1065 }
1066
c54106bb
AD		 1067 /* 82575 requires that the pci-e link partner disable the L0s state */
1068 switch (pdev->device) {
1069 case E1000_DEV_ID_82575EB_COPPER:
1070 case E1000_DEV_ID_82575EB_FIBER_SERDES:
1071 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1072 us_dev = pdev->bus->self;
1073 pos = pci_find_capability(us_dev, PCI_CAP_ID_EXP);
1074 if (pos) {
1075 pci_read_config_word(us_dev, pos + PCI_EXP_LNKCTL,
1076 &state);
1077 state &= ~PCIE_LINK_STATE_L0S;
1078 pci_write_config_word(us_dev, pos + PCI_EXP_LNKCTL,
1079 state);
ac450208
BH		 1080 dev_info(&pdev->dev,
1081 "Disabling ASPM L0s upstream switch port %s\n",
1082 pci_name(us_dev));
c54106bb
AD		 1083 }
1084 default:
1085 break;
1086 }
1087
42bfd33a 1088 err = pci_request_selected_regions(pdev, bars, igb_driver_name);
9d5c8243
AK		 1089 if (err)
1090 goto err_pci_reg;
1091
ea943d41
JK		 1092 err = pci_enable_pcie_error_reporting(pdev);
1093 if (err) {
1094 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
1095 "0x%x\n", err);
1096 /* non-fatal, continue */
1097 }
40a914fa 1098
9d5c8243 1099 pci_set_master(pdev);
c682fc23 1100 pci_save_state(pdev);
9d5c8243
AK		 1101
1102 err = -ENOMEM;
661086df 1103 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), IGB_MAX_TX_QUEUES);
9d5c8243
AK		 1104 if (!netdev)
1105 goto err_alloc_etherdev;
1106
1107 SET_NETDEV_DEV(netdev, &pdev->dev);
1108
1109 pci_set_drvdata(pdev, netdev);
1110 adapter = netdev_priv(netdev);
1111 adapter->netdev = netdev;
1112 adapter->pdev = pdev;
1113 hw = &adapter->hw;
1114 hw->back = adapter;
1115 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
42bfd33a
TI		 1116 adapter->bars = bars;
1117 adapter->need_ioport = need_ioport;
9d5c8243
AK		 1118
1119 mmio_start = pci_resource_start(pdev, 0);
1120 mmio_len = pci_resource_len(pdev, 0);
1121
1122 err = -EIO;
1123 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
1124 if (!adapter->hw.hw_addr)
1125 goto err_ioremap;
1126
2e5c6922 1127 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 1128 igb_set_ethtool_ops(netdev);
9d5c8243 1129 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 1130
1131 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1132
1133 netdev->mem_start = mmio_start;
1134 netdev->mem_end = mmio_start + mmio_len;
1135
9d5c8243
AK		 1136 /* PCI config space info */
1137 hw->vendor_id = pdev->vendor;
1138 hw->device_id = pdev->device;
1139 hw->revision_id = pdev->revision;
1140 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1141 hw->subsystem_device_id = pdev->subsystem_device;
1142
1143 /* setup the private structure */
1144 hw->back = adapter;
1145 /* Copy the default MAC, PHY and NVM function pointers */
1146 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1147 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1148 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1149 /* Initialize skew-specific constants */
1150 err = ei->get_invariants(hw);
1151 if (err)
1152 goto err_hw_init;
1153
1154 err = igb_sw_init(adapter);
1155 if (err)
1156 goto err_sw_init;
1157
1158 igb_get_bus_info_pcie(hw);
1159
7dfc16fa
AD		 1160 /* set flags */
1161 switch (hw->mac.type) {
7dfc16fa 1162 case e1000_82575:
7dfc16fa
AD		 1163 adapter->flags |= IGB_FLAG_NEED_CTX_IDX;
1164 break;
bbd98fe4 1165 case e1000_82576:
7dfc16fa
AD		 1166 default:
1167 break;
1168 }
1169
9d5c8243
AK		 1170 hw->phy.autoneg_wait_to_complete = false;
1171 hw->mac.adaptive_ifs = true;
1172
1173 /* Copper options */
1174 if (hw->phy.media_type == e1000_media_type_copper) {
1175 hw->phy.mdix = AUTO_ALL_MODES;
1176 hw->phy.disable_polarity_correction = false;
1177 hw->phy.ms_type = e1000_ms_hw_default;
1178 }
1179
1180 if (igb_check_reset_block(hw))
1181 dev_info(&pdev->dev,
1182 "PHY reset is blocked due to SOL/IDER session.\n");
1183
1184 netdev->features = NETIF_F_SG |
1185 NETIF_F_HW_CSUM |
1186 NETIF_F_HW_VLAN_TX |
1187 NETIF_F_HW_VLAN_RX |
1188 NETIF_F_HW_VLAN_FILTER;
1189
1190 netdev->features |= NETIF_F_TSO;
9d5c8243 1191 netdev->features |= NETIF_F_TSO6;
48f29ffc 1192
d3352520 1193#ifdef CONFIG_IGB_LRO
5c0999b7 1194 netdev->features |= NETIF_F_GRO;
d3352520
AD		 1195#endif
1196
48f29ffc
JK		 1197 netdev->vlan_features |= NETIF_F_TSO;
1198 netdev->vlan_features |= NETIF_F_TSO6;
1199 netdev->vlan_features |= NETIF_F_HW_CSUM;
1200 netdev->vlan_features |= NETIF_F_SG;
1201
9d5c8243
AK		 1202 if (pci_using_dac)
1203 netdev->features |= NETIF_F_HIGHDMA;
1204
9d5c8243
AK		 1205 adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1206
1207 /* before reading the NVM, reset the controller to put the device in a
1208 * known good starting state */
1209 hw->mac.ops.reset_hw(hw);
1210
1211 /* make sure the NVM is good */
1212 if (igb_validate_nvm_checksum(hw) < 0) {
1213 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1214 err = -EIO;
1215 goto err_eeprom;
1216 }
1217
1218 /* copy the MAC address out of the NVM */
1219 if (hw->mac.ops.read_mac_addr(hw))
1220 dev_err(&pdev->dev, "NVM Read Error\n");
1221
1222 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1223 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1224
1225 if (!is_valid_ether_addr(netdev->perm_addr)) {
1226 dev_err(&pdev->dev, "Invalid MAC Address\n");
1227 err = -EIO;
1228 goto err_eeprom;
1229 }
1230
1231 init_timer(&adapter->watchdog_timer);
1232 adapter->watchdog_timer.function = &igb_watchdog;
1233 adapter->watchdog_timer.data = (unsigned long) adapter;
1234
1235 init_timer(&adapter->phy_info_timer);
1236 adapter->phy_info_timer.function = &igb_update_phy_info;
1237 adapter->phy_info_timer.data = (unsigned long) adapter;
1238
1239 INIT_WORK(&adapter->reset_task, igb_reset_task);
1240 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1241
1242 /* Initialize link & ring properties that are user-changeable */
1243 adapter->tx_ring->count = 256;
1244 for (i = 0; i < adapter->num_tx_queues; i++)
1245 adapter->tx_ring[i].count = adapter->tx_ring->count;
1246 adapter->rx_ring->count = 256;
1247 for (i = 0; i < adapter->num_rx_queues; i++)
1248 adapter->rx_ring[i].count = adapter->rx_ring->count;
1249
1250 adapter->fc_autoneg = true;
1251 hw->mac.autoneg = true;
1252 hw->phy.autoneg_advertised = 0x2f;
1253
1254 hw->fc.original_type = e1000_fc_default;
1255 hw->fc.type = e1000_fc_default;
1256
1257 adapter->itr_setting = 3;
1258 adapter->itr = IGB_START_ITR;
1259
1260 igb_validate_mdi_setting(hw);
1261
1262 adapter->rx_csum = 1;
1263
1264 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1265 * enable the ACPI Magic Packet filter
1266 */
1267
1268 if (hw->bus.func == 0 ||
1269 hw->device_id == E1000_DEV_ID_82575EB_COPPER)
1270 hw->nvm.ops.read_nvm(hw, NVM_INIT_CONTROL3_PORT_A, 1,
1271 &eeprom_data);
1272
1273 if (eeprom_data & eeprom_apme_mask)
1274 adapter->eeprom_wol |= E1000_WUFC_MAG;
1275
1276 /* now that we have the eeprom settings, apply the special cases where
1277 * the eeprom may be wrong or the board simply won't support wake on
1278 * lan on a particular port */
1279 switch (pdev->device) {
1280 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1281 adapter->eeprom_wol = 0;
1282 break;
1283 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 1284 case E1000_DEV_ID_82576_FIBER:
1285 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 1286 /* Wake events only supported on port A for dual fiber
1287 * regardless of eeprom setting */
1288 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1289 adapter->eeprom_wol = 0;
1290 break;
1291 }
1292
1293 /* initialize the wol settings based on the eeprom settings */
1294 adapter->wol = adapter->eeprom_wol;
e1b86d84 1295 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
9d5c8243
AK		 1296
1297 /* reset the hardware with the new settings */
1298 igb_reset(adapter);
1299
1300 /* let the f/w know that the h/w is now under the control of the
1301 * driver. */
1302 igb_get_hw_control(adapter);
1303
1304 /* tell the stack to leave us alone until igb_open() is called */
1305 netif_carrier_off(netdev);
fd2ea0a7 1306 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1307
1308 strcpy(netdev->name, "eth%d");
1309 err = register_netdev(netdev);
1310 if (err)
1311 goto err_register;
1312
421e02f0 1313#ifdef CONFIG_IGB_DCA
bbd98fe4 1314 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 1315 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 1316 dev_info(&pdev->dev, "DCA enabled\n");
1317 /* Always use CB2 mode, difference is masked
1318 * in the CB driver. */
1319 wr32(E1000_DCA_CTRL, 2);
1320 igb_setup_dca(adapter);
1321 }
1322#endif
1323
9d5c8243
AK		 1324 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1325 /* print bus type/speed/width info */
7c510e4b 1326 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
9d5c8243
AK		 1327 netdev->name,
1328 ((hw->bus.speed == e1000_bus_speed_2500)
1329 ? "2.5Gb/s" : "unknown"),
1330 ((hw->bus.width == e1000_bus_width_pcie_x4)
1331 ? "Width x4" : (hw->bus.width == e1000_bus_width_pcie_x1)
1332 ? "Width x1" : "unknown"),
7c510e4b 1333 netdev->dev_addr);
9d5c8243
AK		 1334
1335 igb_read_part_num(hw, &part_num);
1336 dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1337 (part_num >> 8), (part_num & 0xff));
1338
1339 dev_info(&pdev->dev,
1340 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1341 adapter->msix_entries ? "MSI-X" :
7dfc16fa 1342 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243
AK		 1343 adapter->num_rx_queues, adapter->num_tx_queues);
1344
9d5c8243
AK		 1345 return 0;
1346
1347err_register:
1348 igb_release_hw_control(adapter);
1349err_eeprom:
1350 if (!igb_check_reset_block(hw))
f5f4cf08 1351 igb_reset_phy(hw);
9d5c8243
AK		 1352
1353 if (hw->flash_address)
1354 iounmap(hw->flash_address);
1355
1356 igb_remove_device(hw);
a88f10ec 1357 igb_free_queues(adapter);
9d5c8243
AK		 1358err_sw_init:
1359err_hw_init:
1360 iounmap(hw->hw_addr);
1361err_ioremap:
1362 free_netdev(netdev);
1363err_alloc_etherdev:
42bfd33a 1364 pci_release_selected_regions(pdev, bars);
9d5c8243
AK		 1365err_pci_reg:
1366err_dma:
1367 pci_disable_device(pdev);
1368 return err;
1369}
1370
1371/**
1372 * igb_remove - Device Removal Routine
1373 * @pdev: PCI device information struct
1374 *
1375 * igb_remove is called by the PCI subsystem to alert the driver
1376 * that it should release a PCI device. The could be caused by a
1377 * Hot-Plug event, or because the driver is going to be removed from
1378 * memory.
1379 **/
1380static void __devexit igb_remove(struct pci_dev *pdev)
1381{
1382 struct net_device *netdev = pci_get_drvdata(pdev);
1383 struct igb_adapter *adapter = netdev_priv(netdev);
421e02f0 1384#ifdef CONFIG_IGB_DCA
fe4506b6 1385 struct e1000_hw *hw = &adapter->hw;
9280fa52 1386#endif
ea943d41 1387 int err;
9d5c8243
AK		 1388
1389 /* flush_scheduled work may reschedule our watchdog task, so
1390 * explicitly disable watchdog tasks from being rescheduled */
1391 set_bit(__IGB_DOWN, &adapter->state);
1392 del_timer_sync(&adapter->watchdog_timer);
1393 del_timer_sync(&adapter->phy_info_timer);
1394
1395 flush_scheduled_work();
1396
421e02f0 1397#ifdef CONFIG_IGB_DCA
7dfc16fa 1398 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 1399 dev_info(&pdev->dev, "DCA disabled\n");
1400 dca_remove_requester(&pdev->dev);
7dfc16fa 1401 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 1402 wr32(E1000_DCA_CTRL, 1);
1403 }
1404#endif
1405
9d5c8243
AK		 1406 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1407 * would have already happened in close and is redundant. */
1408 igb_release_hw_control(adapter);
1409
1410 unregister_netdev(netdev);
1411
f5f4cf08
AD		 1412 if (!igb_check_reset_block(&adapter->hw))
1413 igb_reset_phy(&adapter->hw);
9d5c8243
AK		 1414
1415 igb_remove_device(&adapter->hw);
1416 igb_reset_interrupt_capability(adapter);
1417
a88f10ec 1418 igb_free_queues(adapter);
9d5c8243
AK		 1419
1420 iounmap(adapter->hw.hw_addr);
1421 if (adapter->hw.flash_address)
1422 iounmap(adapter->hw.flash_address);
42bfd33a 1423 pci_release_selected_regions(pdev, adapter->bars);
9d5c8243
AK		 1424
1425 free_netdev(netdev);
1426
ea943d41
JK		 1427 err = pci_disable_pcie_error_reporting(pdev);
1428 if (err)
1429 dev_err(&pdev->dev,
1430 "pci_disable_pcie_error_reporting failed 0x%x\n", err);
40a914fa 1431
9d5c8243
AK		 1432 pci_disable_device(pdev);
1433}
1434
1435/**
1436 * igb_sw_init - Initialize general software structures (struct igb_adapter)
1437 * @adapter: board private structure to initialize
1438 *
1439 * igb_sw_init initializes the Adapter private data structure.
1440 * Fields are initialized based on PCI device information and
1441 * OS network device settings (MTU size).
1442 **/
1443static int __devinit igb_sw_init(struct igb_adapter *adapter)
1444{
1445 struct e1000_hw *hw = &adapter->hw;
1446 struct net_device *netdev = adapter->netdev;
1447 struct pci_dev *pdev = adapter->pdev;
1448
1449 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1450
68fd9910
AD		 1451 adapter->tx_ring_count = IGB_DEFAULT_TXD;
1452 adapter->rx_ring_count = IGB_DEFAULT_RXD;
9d5c8243
AK		 1453 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1454 adapter->rx_ps_hdr_size = 0; /* disable packet split */
1455 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1456 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1457
661086df
PWJ		 1458 /* This call may decrease the number of queues depending on
1459 * interrupt mode. */
9d5c8243
AK		 1460 igb_set_interrupt_capability(adapter);
1461
1462 if (igb_alloc_queues(adapter)) {
1463 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1464 return -ENOMEM;
1465 }
1466
1467 /* Explicitly disable IRQ since the NIC can be in any state. */
1468 igb_irq_disable(adapter);
1469
1470 set_bit(__IGB_DOWN, &adapter->state);
1471 return 0;
1472}
1473
1474/**
1475 * igb_open - Called when a network interface is made active
1476 * @netdev: network interface device structure
1477 *
1478 * Returns 0 on success, negative value on failure
1479 *
1480 * The open entry point is called when a network interface is made
1481 * active by the system (IFF_UP). At this point all resources needed
1482 * for transmit and receive operations are allocated, the interrupt
1483 * handler is registered with the OS, the watchdog timer is started,
1484 * and the stack is notified that the interface is ready.
1485 **/
1486static int igb_open(struct net_device *netdev)
1487{
1488 struct igb_adapter *adapter = netdev_priv(netdev);
1489 struct e1000_hw *hw = &adapter->hw;
1490 int err;
1491 int i;
1492
1493 /* disallow open during test */
1494 if (test_bit(__IGB_TESTING, &adapter->state))
1495 return -EBUSY;
1496
1497 /* allocate transmit descriptors */
1498 err = igb_setup_all_tx_resources(adapter);
1499 if (err)
1500 goto err_setup_tx;
1501
1502 /* allocate receive descriptors */
1503 err = igb_setup_all_rx_resources(adapter);
1504 if (err)
1505 goto err_setup_rx;
1506
1507 /* e1000_power_up_phy(adapter); */
1508
1509 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1510 if ((adapter->hw.mng_cookie.status &
1511 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1512 igb_update_mng_vlan(adapter);
1513
1514 /* before we allocate an interrupt, we must be ready to handle it.
1515 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1516 * as soon as we call pci_request_irq, so we have to setup our
1517 * clean_rx handler before we do so. */
1518 igb_configure(adapter);
1519
1520 err = igb_request_irq(adapter);
1521 if (err)
1522 goto err_req_irq;
1523
1524 /* From here on the code is the same as igb_up() */
1525 clear_bit(__IGB_DOWN, &adapter->state);
1526
844290e5
PW		 1527 for (i = 0; i < adapter->num_rx_queues; i++)
1528 napi_enable(&adapter->rx_ring[i].napi);
9d5c8243
AK		 1529
1530 /* Clear any pending interrupts. */
1531 rd32(E1000_ICR);
844290e5
PW		 1532
1533 igb_irq_enable(adapter);
1534
d55b53ff
JK		 1535 netif_tx_start_all_queues(netdev);
1536
9d5c8243
AK		 1537 /* Fire a link status change interrupt to start the watchdog. */
1538 wr32(E1000_ICS, E1000_ICS_LSC);
1539
1540 return 0;
1541
1542err_req_irq:
1543 igb_release_hw_control(adapter);
1544 /* e1000_power_down_phy(adapter); */
1545 igb_free_all_rx_resources(adapter);
1546err_setup_rx:
1547 igb_free_all_tx_resources(adapter);
1548err_setup_tx:
1549 igb_reset(adapter);
1550
1551 return err;
1552}
1553
1554/**
1555 * igb_close - Disables a network interface
1556 * @netdev: network interface device structure
1557 *
1558 * Returns 0, this is not allowed to fail
1559 *
1560 * The close entry point is called when an interface is de-activated
1561 * by the OS. The hardware is still under the driver's control, but
1562 * needs to be disabled. A global MAC reset is issued to stop the
1563 * hardware, and all transmit and receive resources are freed.
1564 **/
1565static int igb_close(struct net_device *netdev)
1566{
1567 struct igb_adapter *adapter = netdev_priv(netdev);
1568
1569 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1570 igb_down(adapter);
1571
1572 igb_free_irq(adapter);
1573
1574 igb_free_all_tx_resources(adapter);
1575 igb_free_all_rx_resources(adapter);
1576
1577 /* kill manageability vlan ID if supported, but not if a vlan with
1578 * the same ID is registered on the host OS (let 8021q kill it) */
1579 if ((adapter->hw.mng_cookie.status &
1580 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1581 !(adapter->vlgrp &&
1582 vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1583 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1584
1585 return 0;
1586}
1587
1588/**
1589 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
1590 * @adapter: board private structure
1591 * @tx_ring: tx descriptor ring (for a specific queue) to setup
1592 *
1593 * Return 0 on success, negative on failure
1594 **/
1595
1596int igb_setup_tx_resources(struct igb_adapter *adapter,
1597 struct igb_ring *tx_ring)
1598{
1599 struct pci_dev *pdev = adapter->pdev;
1600 int size;
1601
1602 size = sizeof(struct igb_buffer) * tx_ring->count;
1603 tx_ring->buffer_info = vmalloc(size);
1604 if (!tx_ring->buffer_info)
1605 goto err;
1606 memset(tx_ring->buffer_info, 0, size);
1607
1608 /* round up to nearest 4K */
0e014cb1 1609 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
9d5c8243
AK		 1610 tx_ring->size = ALIGN(tx_ring->size, 4096);
1611
1612 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1613 &tx_ring->dma);
1614
1615 if (!tx_ring->desc)
1616 goto err;
1617
1618 tx_ring->adapter = adapter;
1619 tx_ring->next_to_use = 0;
1620 tx_ring->next_to_clean = 0;
9d5c8243
AK		 1621 return 0;
1622
1623err:
1624 vfree(tx_ring->buffer_info);
1625 dev_err(&adapter->pdev->dev,
1626 "Unable to allocate memory for the transmit descriptor ring\n");
1627 return -ENOMEM;
1628}
1629
1630/**
1631 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1632 * (Descriptors) for all queues
1633 * @adapter: board private structure
1634 *
1635 * Return 0 on success, negative on failure
1636 **/
1637static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1638{
1639 int i, err = 0;
661086df 1640 int r_idx;
9d5c8243
AK		 1641
1642 for (i = 0; i < adapter->num_tx_queues; i++) {
1643 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1644 if (err) {
1645 dev_err(&adapter->pdev->dev,
1646 "Allocation for Tx Queue %u failed\n", i);
1647 for (i--; i >= 0; i--)
3b644cf6 1648 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 1649 break;
1650 }
1651 }
1652
661086df
PWJ		 1653 for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
1654 r_idx = i % adapter->num_tx_queues;
1655 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
1656 }
9d5c8243
AK		 1657 return err;
1658}
1659
1660/**
1661 * igb_configure_tx - Configure transmit Unit after Reset
1662 * @adapter: board private structure
1663 *
1664 * Configure the Tx unit of the MAC after a reset.
1665 **/
1666static void igb_configure_tx(struct igb_adapter *adapter)
1667{
0e014cb1 1668 u64 tdba;
9d5c8243
AK		 1669 struct e1000_hw *hw = &adapter->hw;
1670 u32 tctl;
1671 u32 txdctl, txctrl;
26bc19ec 1672 int i, j;
9d5c8243
AK		 1673
1674 for (i = 0; i < adapter->num_tx_queues; i++) {
1675 struct igb_ring *ring = &(adapter->tx_ring[i]);
26bc19ec
AD		 1676 j = ring->reg_idx;
1677 wr32(E1000_TDLEN(j),
9d5c8243
AK		 1678 ring->count * sizeof(struct e1000_tx_desc));
1679 tdba = ring->dma;
26bc19ec 1680 wr32(E1000_TDBAL(j),
9d5c8243 1681 tdba & 0x00000000ffffffffULL);
26bc19ec 1682 wr32(E1000_TDBAH(j), tdba >> 32);
9d5c8243 1683
26bc19ec
AD		 1684 ring->head = E1000_TDH(j);
1685 ring->tail = E1000_TDT(j);
9d5c8243
AK		 1686 writel(0, hw->hw_addr + ring->tail);
1687 writel(0, hw->hw_addr + ring->head);
26bc19ec 1688 txdctl = rd32(E1000_TXDCTL(j));
9d5c8243 1689 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
26bc19ec 1690 wr32(E1000_TXDCTL(j), txdctl);
9d5c8243
AK		 1691
1692 /* Turn off Relaxed Ordering on head write-backs. The
1693 * writebacks MUST be delivered in order or it will
1694 * completely screw up our bookeeping.
1695 */
26bc19ec 1696 txctrl = rd32(E1000_DCA_TXCTRL(j));
9d5c8243 1697 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
26bc19ec 1698 wr32(E1000_DCA_TXCTRL(j), txctrl);
9d5c8243
AK		 1699 }
1700
1701
1702
1703 /* Use the default values for the Tx Inter Packet Gap (IPG) timer */
1704
1705 /* Program the Transmit Control Register */
1706
1707 tctl = rd32(E1000_TCTL);
1708 tctl &= ~E1000_TCTL_CT;
1709 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1710 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1711
1712 igb_config_collision_dist(hw);
1713
1714 /* Setup Transmit Descriptor Settings for eop descriptor */
1715 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
1716
1717 /* Enable transmits */
1718 tctl |= E1000_TCTL_EN;
1719
1720 wr32(E1000_TCTL, tctl);
1721}
1722
1723/**
1724 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
1725 * @adapter: board private structure
1726 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1727 *
1728 * Returns 0 on success, negative on failure
1729 **/
1730
1731int igb_setup_rx_resources(struct igb_adapter *adapter,
1732 struct igb_ring *rx_ring)
1733{
1734 struct pci_dev *pdev = adapter->pdev;
1735 int size, desc_len;
1736
1737 size = sizeof(struct igb_buffer) * rx_ring->count;
1738 rx_ring->buffer_info = vmalloc(size);
1739 if (!rx_ring->buffer_info)
1740 goto err;
1741 memset(rx_ring->buffer_info, 0, size);
1742
1743 desc_len = sizeof(union e1000_adv_rx_desc);
1744
1745 /* Round up to nearest 4K */
1746 rx_ring->size = rx_ring->count * desc_len;
1747 rx_ring->size = ALIGN(rx_ring->size, 4096);
1748
1749 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1750 &rx_ring->dma);
1751
1752 if (!rx_ring->desc)
1753 goto err;
1754
1755 rx_ring->next_to_clean = 0;
1756 rx_ring->next_to_use = 0;
9d5c8243
AK		 1757
1758 rx_ring->adapter = adapter;
9d5c8243
AK		 1759
1760 return 0;
1761
1762err:
1763 vfree(rx_ring->buffer_info);
1764 dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
1765 "the receive descriptor ring\n");
1766 return -ENOMEM;
1767}
1768
1769/**
1770 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
1771 * (Descriptors) for all queues
1772 * @adapter: board private structure
1773 *
1774 * Return 0 on success, negative on failure
1775 **/
1776static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
1777{
1778 int i, err = 0;
1779
1780 for (i = 0; i < adapter->num_rx_queues; i++) {
1781 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1782 if (err) {
1783 dev_err(&adapter->pdev->dev,
1784 "Allocation for Rx Queue %u failed\n", i);
1785 for (i--; i >= 0; i--)
3b644cf6 1786 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 1787 break;
1788 }
1789 }
1790
1791 return err;
1792}
1793
1794/**
1795 * igb_setup_rctl - configure the receive control registers
1796 * @adapter: Board private structure
1797 **/
1798static void igb_setup_rctl(struct igb_adapter *adapter)
1799{
1800 struct e1000_hw *hw = &adapter->hw;
1801 u32 rctl;
1802 u32 srrctl = 0;
26bc19ec 1803 int i, j;
9d5c8243
AK		 1804
1805 rctl = rd32(E1000_RCTL);
1806
1807 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 1808 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 1809
69d728ba 1810 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
9d5c8243
AK		 1811 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
1812
87cb7e8c
AK		 1813 /*
1814 * enable stripping of CRC. It's unlikely this will break BMC
1815 * redirection as it did with e1000. Newer features require
1816 * that the HW strips the CRC.
9d5c8243 1817 */
87cb7e8c 1818 rctl |= E1000_RCTL_SECRC;
9d5c8243 1819
9b07f3d3 1820 /*
ec54d7d6 1821 * disable store bad packets and clear size bits.
9b07f3d3 1822 */
ec54d7d6 1823 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 1824
ec54d7d6 1825 /* enable LPE when to prevent packets larger than max_frame_size */
9b07f3d3 1826 rctl |= E1000_RCTL_LPE;
b4557be2
AD		 1827
1828 /* Setup buffer sizes */
1829 switch (adapter->rx_buffer_len) {
1830 case IGB_RXBUFFER_256:
1831 rctl |= E1000_RCTL_SZ_256;
1832 break;
1833 case IGB_RXBUFFER_512:
1834 rctl |= E1000_RCTL_SZ_512;
1835 break;
1836 default:
1837 srrctl = ALIGN(adapter->rx_buffer_len, 1024)
1838 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1839 break;
9d5c8243
AK		 1840 }
1841
1842 /* 82575 and greater support packet-split where the protocol
1843 * header is placed in skb->data and the packet data is
1844 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
1845 * In the case of a non-split, skb->data is linearly filled,
1846 * followed by the page buffers. Therefore, skb->data is
1847 * sized to hold the largest protocol header.
1848 */
1849 /* allocations using alloc_page take too long for regular MTU
1850 * so only enable packet split for jumbo frames */
ec54d7d6 1851 if (adapter->netdev->mtu > ETH_DATA_LEN) {
9d5c8243 1852 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
bf36c1a0 1853 srrctl |= adapter->rx_ps_hdr_size <<
9d5c8243 1854 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
9d5c8243
AK		 1855 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1856 } else {
1857 adapter->rx_ps_hdr_size = 0;
1858 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
1859 }
1860
26bc19ec
AD		 1861 for (i = 0; i < adapter->num_rx_queues; i++) {
1862 j = adapter->rx_ring[i].reg_idx;
1863 wr32(E1000_SRRCTL(j), srrctl);
1864 }
9d5c8243
AK		 1865
1866 wr32(E1000_RCTL, rctl);
1867}
1868
1869/**
1870 * igb_configure_rx - Configure receive Unit after Reset
1871 * @adapter: board private structure
1872 *
1873 * Configure the Rx unit of the MAC after a reset.
1874 **/
1875static void igb_configure_rx(struct igb_adapter *adapter)
1876{
1877 u64 rdba;
1878 struct e1000_hw *hw = &adapter->hw;
1879 u32 rctl, rxcsum;
1880 u32 rxdctl;
26bc19ec 1881 int i, j;
9d5c8243
AK		 1882
1883 /* disable receives while setting up the descriptors */
1884 rctl = rd32(E1000_RCTL);
1885 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1886 wrfl();
1887 mdelay(10);
1888
1889 if (adapter->itr_setting > 3)
6eb5a7f1 1890 wr32(E1000_ITR, adapter->itr);
9d5c8243
AK		 1891
1892 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1893 * the Base and Length of the Rx Descriptor Ring */
1894 for (i = 0; i < adapter->num_rx_queues; i++) {
1895 struct igb_ring *ring = &(adapter->rx_ring[i]);
26bc19ec 1896 j = ring->reg_idx;
9d5c8243 1897 rdba = ring->dma;
26bc19ec 1898 wr32(E1000_RDBAL(j),
9d5c8243 1899 rdba & 0x00000000ffffffffULL);
26bc19ec
AD		 1900 wr32(E1000_RDBAH(j), rdba >> 32);
1901 wr32(E1000_RDLEN(j),
9d5c8243
AK		 1902 ring->count * sizeof(union e1000_adv_rx_desc));
1903
26bc19ec
AD		 1904 ring->head = E1000_RDH(j);
1905 ring->tail = E1000_RDT(j);
9d5c8243
AK		 1906 writel(0, hw->hw_addr + ring->tail);
1907 writel(0, hw->hw_addr + ring->head);
1908
26bc19ec 1909 rxdctl = rd32(E1000_RXDCTL(j));
9d5c8243
AK		 1910 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
1911 rxdctl &= 0xFFF00000;
1912 rxdctl |= IGB_RX_PTHRESH;
1913 rxdctl |= IGB_RX_HTHRESH << 8;
1914 rxdctl |= IGB_RX_WTHRESH << 16;
26bc19ec 1915 wr32(E1000_RXDCTL(j), rxdctl);
9d5c8243
AK		 1916 }
1917
1918 if (adapter->num_rx_queues > 1) {
1919 u32 random[10];
1920 u32 mrqc;
1921 u32 j, shift;
1922 union e1000_reta {
1923 u32 dword;
1924 u8 bytes[4];
1925 } reta;
1926
1927 get_random_bytes(&random[0], 40);
1928
2d064c06
AD		 1929 if (hw->mac.type >= e1000_82576)
1930 shift = 0;
1931 else
1932 shift = 6;
9d5c8243
AK		 1933 for (j = 0; j < (32 * 4); j++) {
1934 reta.bytes[j & 3] =
26bc19ec 1935 adapter->rx_ring[(j % adapter->num_rx_queues)].reg_idx << shift;
9d5c8243
AK		 1936 if ((j & 3) == 3)
1937 writel(reta.dword,
1938 hw->hw_addr + E1000_RETA(0) + (j & ~3));
1939 }
1940 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
1941
1942 /* Fill out hash function seeds */
1943 for (j = 0; j < 10; j++)
1944 array_wr32(E1000_RSSRK(0), j, random[j]);
1945
1946 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
1947 E1000_MRQC_RSS_FIELD_IPV4_TCP);
1948 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
1949 E1000_MRQC_RSS_FIELD_IPV6_TCP);
1950 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
1951 E1000_MRQC_RSS_FIELD_IPV6_UDP);
1952 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
1953 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
1954
1955
1956 wr32(E1000_MRQC, mrqc);
1957
1958 /* Multiqueue and raw packet checksumming are mutually
1959 * exclusive. Note that this not the same as TCP/IP
1960 * checksumming, which works fine. */
1961 rxcsum = rd32(E1000_RXCSUM);
1962 rxcsum |= E1000_RXCSUM_PCSD;
1963 wr32(E1000_RXCSUM, rxcsum);
1964 } else {
1965 /* Enable Receive Checksum Offload for TCP and UDP */
1966 rxcsum = rd32(E1000_RXCSUM);
1967 if (adapter->rx_csum) {
1968 rxcsum |= E1000_RXCSUM_TUOFL;
1969
1970 /* Enable IPv4 payload checksum for UDP fragments
1971 * Must be used in conjunction with packet-split. */
1972 if (adapter->rx_ps_hdr_size)
1973 rxcsum |= E1000_RXCSUM_IPPCSE;
1974 } else {
1975 rxcsum &= ~E1000_RXCSUM_TUOFL;
1976 /* don't need to clear IPPCSE as it defaults to 0 */
1977 }
1978 wr32(E1000_RXCSUM, rxcsum);
1979 }
1980
1981 if (adapter->vlgrp)
1982 wr32(E1000_RLPML,
1983 adapter->max_frame_size + VLAN_TAG_SIZE);
1984 else
1985 wr32(E1000_RLPML, adapter->max_frame_size);
1986
1987 /* Enable Receives */
1988 wr32(E1000_RCTL, rctl);
1989}
1990
1991/**
1992 * igb_free_tx_resources - Free Tx Resources per Queue
9d5c8243
AK		 1993 * @tx_ring: Tx descriptor ring for a specific queue
1994 *
1995 * Free all transmit software resources
1996 **/
68fd9910 1997void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 1998{
3b644cf6 1999 struct pci_dev *pdev = tx_ring->adapter->pdev;
9d5c8243 2000
3b644cf6 2001 igb_clean_tx_ring(tx_ring);
9d5c8243
AK		 2002
2003 vfree(tx_ring->buffer_info);
2004 tx_ring->buffer_info = NULL;
2005
2006 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
2007
2008 tx_ring->desc = NULL;
2009}
2010
2011/**
2012 * igb_free_all_tx_resources - Free Tx Resources for All Queues
2013 * @adapter: board private structure
2014 *
2015 * Free all transmit software resources
2016 **/
2017static void igb_free_all_tx_resources(struct igb_adapter *adapter)
2018{
2019 int i;
2020
2021 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2022 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 2023}
2024
2025static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
2026 struct igb_buffer *buffer_info)
2027{
2028 if (buffer_info->dma) {
2029 pci_unmap_page(adapter->pdev,
2030 buffer_info->dma,
2031 buffer_info->length,
2032 PCI_DMA_TODEVICE);
2033 buffer_info->dma = 0;
2034 }
2035 if (buffer_info->skb) {
2036 dev_kfree_skb_any(buffer_info->skb);
2037 buffer_info->skb = NULL;
2038 }
2039 buffer_info->time_stamp = 0;
2040 /* buffer_info must be completely set up in the transmit path */
2041}
2042
2043/**
2044 * igb_clean_tx_ring - Free Tx Buffers
9d5c8243
AK		 2045 * @tx_ring: ring to be cleaned
2046 **/
3b644cf6 2047static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 2048{
3b644cf6 2049 struct igb_adapter *adapter = tx_ring->adapter;
9d5c8243
AK		 2050 struct igb_buffer *buffer_info;
2051 unsigned long size;
2052 unsigned int i;
2053
2054 if (!tx_ring->buffer_info)
2055 return;
2056 /* Free all the Tx ring sk_buffs */
2057
2058 for (i = 0; i < tx_ring->count; i++) {
2059 buffer_info = &tx_ring->buffer_info[i];
2060 igb_unmap_and_free_tx_resource(adapter, buffer_info);
2061 }
2062
2063 size = sizeof(struct igb_buffer) * tx_ring->count;
2064 memset(tx_ring->buffer_info, 0, size);
2065
2066 /* Zero out the descriptor ring */
2067
2068 memset(tx_ring->desc, 0, tx_ring->size);
2069
2070 tx_ring->next_to_use = 0;
2071 tx_ring->next_to_clean = 0;
2072
2073 writel(0, adapter->hw.hw_addr + tx_ring->head);
2074 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2075}
2076
2077/**
2078 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2079 * @adapter: board private structure
2080 **/
2081static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2082{
2083 int i;
2084
2085 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2086 igb_clean_tx_ring(&adapter->tx_ring[i]);
9d5c8243
AK		 2087}
2088
2089/**
2090 * igb_free_rx_resources - Free Rx Resources
9d5c8243
AK		 2091 * @rx_ring: ring to clean the resources from
2092 *
2093 * Free all receive software resources
2094 **/
68fd9910 2095void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2096{
3b644cf6 2097 struct pci_dev *pdev = rx_ring->adapter->pdev;
9d5c8243 2098
3b644cf6 2099 igb_clean_rx_ring(rx_ring);
9d5c8243
AK		 2100
2101 vfree(rx_ring->buffer_info);
2102 rx_ring->buffer_info = NULL;
2103
2104 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2105
2106 rx_ring->desc = NULL;
2107}
2108
2109/**
2110 * igb_free_all_rx_resources - Free Rx Resources for All Queues
2111 * @adapter: board private structure
2112 *
2113 * Free all receive software resources
2114 **/
2115static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2116{
2117 int i;
2118
2119 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2120 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 2121}
2122
2123/**
2124 * igb_clean_rx_ring - Free Rx Buffers per Queue
9d5c8243
AK		 2125 * @rx_ring: ring to free buffers from
2126 **/
3b644cf6 2127static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 2128{
3b644cf6 2129 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 2130 struct igb_buffer *buffer_info;
2131 struct pci_dev *pdev = adapter->pdev;
2132 unsigned long size;
2133 unsigned int i;
2134
2135 if (!rx_ring->buffer_info)
2136 return;
2137 /* Free all the Rx ring sk_buffs */
2138 for (i = 0; i < rx_ring->count; i++) {
2139 buffer_info = &rx_ring->buffer_info[i];
2140 if (buffer_info->dma) {
2141 if (adapter->rx_ps_hdr_size)
2142 pci_unmap_single(pdev, buffer_info->dma,
2143 adapter->rx_ps_hdr_size,
2144 PCI_DMA_FROMDEVICE);
2145 else
2146 pci_unmap_single(pdev, buffer_info->dma,
2147 adapter->rx_buffer_len,
2148 PCI_DMA_FROMDEVICE);
2149 buffer_info->dma = 0;
2150 }
2151
2152 if (buffer_info->skb) {
2153 dev_kfree_skb(buffer_info->skb);
2154 buffer_info->skb = NULL;
2155 }
2156 if (buffer_info->page) {
bf36c1a0
AD		 2157 if (buffer_info->page_dma)
2158 pci_unmap_page(pdev, buffer_info->page_dma,
2159 PAGE_SIZE / 2,
2160 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 2161 put_page(buffer_info->page);
2162 buffer_info->page = NULL;
2163 buffer_info->page_dma = 0;
bf36c1a0 2164 buffer_info->page_offset = 0;
9d5c8243
AK		 2165 }
2166 }
2167
9d5c8243
AK		 2168 size = sizeof(struct igb_buffer) * rx_ring->count;
2169 memset(rx_ring->buffer_info, 0, size);
2170
2171 /* Zero out the descriptor ring */
2172 memset(rx_ring->desc, 0, rx_ring->size);
2173
2174 rx_ring->next_to_clean = 0;
2175 rx_ring->next_to_use = 0;
2176
2177 writel(0, adapter->hw.hw_addr + rx_ring->head);
2178 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2179}
2180
2181/**
2182 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2183 * @adapter: board private structure
2184 **/
2185static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2186{
2187 int i;
2188
2189 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2190 igb_clean_rx_ring(&adapter->rx_ring[i]);
9d5c8243
AK		 2191}
2192
2193/**
2194 * igb_set_mac - Change the Ethernet Address of the NIC
2195 * @netdev: network interface device structure
2196 * @p: pointer to an address structure
2197 *
2198 * Returns 0 on success, negative on failure
2199 **/
2200static int igb_set_mac(struct net_device *netdev, void *p)
2201{
2202 struct igb_adapter *adapter = netdev_priv(netdev);
2203 struct sockaddr *addr = p;
2204
2205 if (!is_valid_ether_addr(addr->sa_data))
2206 return -EADDRNOTAVAIL;
2207
2208 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2209 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
2210
2211 adapter->hw.mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
2212
2213 return 0;
2214}
2215
2216/**
2217 * igb_set_multi - Multicast and Promiscuous mode set
2218 * @netdev: network interface device structure
2219 *
2220 * The set_multi entry point is called whenever the multicast address
2221 * list or the network interface flags are updated. This routine is
2222 * responsible for configuring the hardware for proper multicast,
2223 * promiscuous mode, and all-multi behavior.
2224 **/
2225static void igb_set_multi(struct net_device *netdev)
2226{
2227 struct igb_adapter *adapter = netdev_priv(netdev);
2228 struct e1000_hw *hw = &adapter->hw;
2229 struct e1000_mac_info *mac = &hw->mac;
2230 struct dev_mc_list *mc_ptr;
2231 u8 *mta_list;
2232 u32 rctl;
2233 int i;
2234
2235 /* Check for Promiscuous and All Multicast modes */
2236
2237 rctl = rd32(E1000_RCTL);
2238
746b9f02 2239 if (netdev->flags & IFF_PROMISC) {
9d5c8243 2240 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
746b9f02
PM		 2241 rctl &= ~E1000_RCTL_VFE;
2242 } else {
2243 if (netdev->flags & IFF_ALLMULTI) {
2244 rctl |= E1000_RCTL_MPE;
2245 rctl &= ~E1000_RCTL_UPE;
2246 } else
2247 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
78ed11a5 2248 rctl |= E1000_RCTL_VFE;
746b9f02 2249 }
9d5c8243
AK		 2250 wr32(E1000_RCTL, rctl);
2251
2252 if (!netdev->mc_count) {
2253 /* nothing to program, so clear mc list */
2d064c06 2254 igb_update_mc_addr_list_82575(hw, NULL, 0, 1,
9d5c8243
AK		 2255 mac->rar_entry_count);
2256 return;
2257 }
2258
2259 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2260 if (!mta_list)
2261 return;
2262
2263 /* The shared function expects a packed array of only addresses. */
2264 mc_ptr = netdev->mc_list;
2265
2266 for (i = 0; i < netdev->mc_count; i++) {
2267 if (!mc_ptr)
2268 break;
2269 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2270 mc_ptr = mc_ptr->next;
2271 }
2d064c06
AD		 2272 igb_update_mc_addr_list_82575(hw, mta_list, i, 1,
2273 mac->rar_entry_count);
9d5c8243
AK		 2274 kfree(mta_list);
2275}
2276
2277/* Need to wait a few seconds after link up to get diagnostic information from
2278 * the phy */
2279static void igb_update_phy_info(unsigned long data)
2280{
2281 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 2282 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 2283}
2284
2285/**
2286 * igb_watchdog - Timer Call-back
2287 * @data: pointer to adapter cast into an unsigned long
2288 **/
2289static void igb_watchdog(unsigned long data)
2290{
2291 struct igb_adapter *adapter = (struct igb_adapter *)data;
2292 /* Do the rest outside of interrupt context */
2293 schedule_work(&adapter->watchdog_task);
2294}
2295
2296static void igb_watchdog_task(struct work_struct *work)
2297{
2298 struct igb_adapter *adapter = container_of(work,
2299 struct igb_adapter, watchdog_task);
2300 struct e1000_hw *hw = &adapter->hw;
2301
2302 struct net_device *netdev = adapter->netdev;
2303 struct igb_ring *tx_ring = adapter->tx_ring;
2304 struct e1000_mac_info *mac = &adapter->hw.mac;
2305 u32 link;
7a6ea550 2306 u32 eics = 0;
9d5c8243 2307 s32 ret_val;
7a6ea550 2308 int i;
9d5c8243
AK		 2309
2310 if ((netif_carrier_ok(netdev)) &&
2311 (rd32(E1000_STATUS) & E1000_STATUS_LU))
2312 goto link_up;
2313
2314 ret_val = hw->mac.ops.check_for_link(&adapter->hw);
2315 if ((ret_val == E1000_ERR_PHY) &&
2316 (hw->phy.type == e1000_phy_igp_3) &&
2317 (rd32(E1000_CTRL) &
2318 E1000_PHY_CTRL_GBE_DISABLE))
2319 dev_info(&adapter->pdev->dev,
2320 "Gigabit has been disabled, downgrading speed\n");
2321
2322 if ((hw->phy.media_type == e1000_media_type_internal_serdes) &&
2323 !(rd32(E1000_TXCW) & E1000_TXCW_ANE))
2324 link = mac->serdes_has_link;
2325 else
2326 link = rd32(E1000_STATUS) &
2327 E1000_STATUS_LU;
2328
2329 if (link) {
2330 if (!netif_carrier_ok(netdev)) {
2331 u32 ctrl;
2332 hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2333 &adapter->link_speed,
2334 &adapter->link_duplex);
2335
2336 ctrl = rd32(E1000_CTRL);
527d47c1
AD		 2337 /* Links status message must follow this format */
2338 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
9d5c8243 2339 "Flow Control: %s\n",
527d47c1 2340 netdev->name,
9d5c8243
AK		 2341 adapter->link_speed,
2342 adapter->link_duplex == FULL_DUPLEX ?
2343 "Full Duplex" : "Half Duplex",
2344 ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2345 E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2346 E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2347 E1000_CTRL_TFCE) ? "TX" : "None")));
2348
2349 /* tweak tx_queue_len according to speed/duplex and
2350 * adjust the timeout factor */
2351 netdev->tx_queue_len = adapter->tx_queue_len;
2352 adapter->tx_timeout_factor = 1;
2353 switch (adapter->link_speed) {
2354 case SPEED_10:
2355 netdev->tx_queue_len = 10;
2356 adapter->tx_timeout_factor = 14;
2357 break;
2358 case SPEED_100:
2359 netdev->tx_queue_len = 100;
2360 /* maybe add some timeout factor ? */
2361 break;
2362 }
2363
2364 netif_carrier_on(netdev);
fd2ea0a7 2365 netif_tx_wake_all_queues(netdev);
9d5c8243
AK		 2366
2367 if (!test_bit(__IGB_DOWN, &adapter->state))
2368 mod_timer(&adapter->phy_info_timer,
2369 round_jiffies(jiffies + 2 * HZ));
2370 }
2371 } else {
2372 if (netif_carrier_ok(netdev)) {
2373 adapter->link_speed = 0;
2374 adapter->link_duplex = 0;
527d47c1
AD		 2375 /* Links status message must follow this format */
2376 printk(KERN_INFO "igb: %s NIC Link is Down\n",
2377 netdev->name);
9d5c8243 2378 netif_carrier_off(netdev);
fd2ea0a7 2379 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 2380 if (!test_bit(__IGB_DOWN, &adapter->state))
2381 mod_timer(&adapter->phy_info_timer,
2382 round_jiffies(jiffies + 2 * HZ));
2383 }
2384 }
2385
2386link_up:
2387 igb_update_stats(adapter);
2388
2389 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2390 adapter->tpt_old = adapter->stats.tpt;
2391 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
2392 adapter->colc_old = adapter->stats.colc;
2393
2394 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2395 adapter->gorc_old = adapter->stats.gorc;
2396 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2397 adapter->gotc_old = adapter->stats.gotc;
2398
2399 igb_update_adaptive(&adapter->hw);
2400
2401 if (!netif_carrier_ok(netdev)) {
2402 if (IGB_DESC_UNUSED(tx_ring) + 1 < tx_ring->count) {
2403 /* We've lost link, so the controller stops DMA,
2404 * but we've got queued Tx work that's never going
2405 * to get done, so reset controller to flush Tx.
2406 * (Do the reset outside of interrupt context). */
2407 adapter->tx_timeout_count++;
2408 schedule_work(&adapter->reset_task);
2409 }
2410 }
2411
2412 /* Cause software interrupt to ensure rx ring is cleaned */
7a6ea550
AD		 2413 if (adapter->msix_entries) {
2414 for (i = 0; i < adapter->num_rx_queues; i++)
2415 eics |= adapter->rx_ring[i].eims_value;
2416 wr32(E1000_EICS, eics);
2417 } else {
2418 wr32(E1000_ICS, E1000_ICS_RXDMT0);
2419 }
9d5c8243
AK		 2420
2421 /* Force detection of hung controller every watchdog period */
2422 tx_ring->detect_tx_hung = true;
2423
2424 /* Reset the timer */
2425 if (!test_bit(__IGB_DOWN, &adapter->state))
2426 mod_timer(&adapter->watchdog_timer,
2427 round_jiffies(jiffies + 2 * HZ));
2428}
2429
2430enum latency_range {
2431 lowest_latency = 0,
2432 low_latency = 1,
2433 bulk_latency = 2,
2434 latency_invalid = 255
2435};
2436
2437
6eb5a7f1
AD		 2438/**
2439 * igb_update_ring_itr - update the dynamic ITR value based on packet size
2440 *
2441 * Stores a new ITR value based on strictly on packet size. This
2442 * algorithm is less sophisticated than that used in igb_update_itr,
2443 * due to the difficulty of synchronizing statistics across multiple
2444 * receive rings. The divisors and thresholds used by this fuction
2445 * were determined based on theoretical maximum wire speed and testing
2446 * data, in order to minimize response time while increasing bulk
2447 * throughput.
2448 * This functionality is controlled by the InterruptThrottleRate module
2449 * parameter (see igb_param.c)
2450 * NOTE: This function is called only when operating in a multiqueue
2451 * receive environment.
2452 * @rx_ring: pointer to ring
2453 **/
2454static void igb_update_ring_itr(struct igb_ring *rx_ring)
9d5c8243 2455{
6eb5a7f1
AD		 2456 int new_val = rx_ring->itr_val;
2457 int avg_wire_size = 0;
2458 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 2459
6eb5a7f1
AD		 2460 if (!rx_ring->total_packets)
2461 goto clear_counts; /* no packets, so don't do anything */
9d5c8243 2462
6eb5a7f1
AD		 2463 /* For non-gigabit speeds, just fix the interrupt rate at 4000
2464 * ints/sec - ITR timer value of 120 ticks.
2465 */
2466 if (adapter->link_speed != SPEED_1000) {
2467 new_val = 120;
2468 goto set_itr_val;
9d5c8243 2469 }
6eb5a7f1 2470 avg_wire_size = rx_ring->total_bytes / rx_ring->total_packets;
9d5c8243 2471
6eb5a7f1
AD		 2472 /* Add 24 bytes to size to account for CRC, preamble, and gap */
2473 avg_wire_size += 24;
2474
2475 /* Don't starve jumbo frames */
2476 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 2477
6eb5a7f1
AD		 2478 /* Give a little boost to mid-size frames */
2479 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
2480 new_val = avg_wire_size / 3;
2481 else
2482 new_val = avg_wire_size / 2;
9d5c8243 2483
6eb5a7f1 2484set_itr_val:
9d5c8243
AK		 2485 if (new_val != rx_ring->itr_val) {
2486 rx_ring->itr_val = new_val;
6eb5a7f1 2487 rx_ring->set_itr = 1;
9d5c8243 2488 }
6eb5a7f1
AD		 2489clear_counts:
2490 rx_ring->total_bytes = 0;
2491 rx_ring->total_packets = 0;
9d5c8243
AK		 2492}
2493
2494/**
2495 * igb_update_itr - update the dynamic ITR value based on statistics
2496 * Stores a new ITR value based on packets and byte
2497 * counts during the last interrupt. The advantage of per interrupt
2498 * computation is faster updates and more accurate ITR for the current
2499 * traffic pattern. Constants in this function were computed
2500 * based on theoretical maximum wire speed and thresholds were set based
2501 * on testing data as well as attempting to minimize response time
2502 * while increasing bulk throughput.
2503 * this functionality is controlled by the InterruptThrottleRate module
2504 * parameter (see igb_param.c)
2505 * NOTE: These calculations are only valid when operating in a single-
2506 * queue environment.
2507 * @adapter: pointer to adapter
2508 * @itr_setting: current adapter->itr
2509 * @packets: the number of packets during this measurement interval
2510 * @bytes: the number of bytes during this measurement interval
2511 **/
2512static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
2513 int packets, int bytes)
2514{
2515 unsigned int retval = itr_setting;
2516
2517 if (packets == 0)
2518 goto update_itr_done;
2519
2520 switch (itr_setting) {
2521 case lowest_latency:
2522 /* handle TSO and jumbo frames */
2523 if (bytes/packets > 8000)
2524 retval = bulk_latency;
2525 else if ((packets < 5) && (bytes > 512))
2526 retval = low_latency;
2527 break;
2528 case low_latency: /* 50 usec aka 20000 ints/s */
2529 if (bytes > 10000) {
2530 /* this if handles the TSO accounting */
2531 if (bytes/packets > 8000) {
2532 retval = bulk_latency;
2533 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
2534 retval = bulk_latency;
2535 } else if ((packets > 35)) {
2536 retval = lowest_latency;
2537 }
2538 } else if (bytes/packets > 2000) {
2539 retval = bulk_latency;
2540 } else if (packets <= 2 && bytes < 512) {
2541 retval = lowest_latency;
2542 }
2543 break;
2544 case bulk_latency: /* 250 usec aka 4000 ints/s */
2545 if (bytes > 25000) {
2546 if (packets > 35)
2547 retval = low_latency;
2548 } else if (bytes < 6000) {
2549 retval = low_latency;
2550 }
2551 break;
2552 }
2553
2554update_itr_done:
2555 return retval;
2556}
2557
6eb5a7f1 2558static void igb_set_itr(struct igb_adapter *adapter)
9d5c8243
AK		 2559{
2560 u16 current_itr;
2561 u32 new_itr = adapter->itr;
2562
2563 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2564 if (adapter->link_speed != SPEED_1000) {
2565 current_itr = 0;
2566 new_itr = 4000;
2567 goto set_itr_now;
2568 }
2569
2570 adapter->rx_itr = igb_update_itr(adapter,
2571 adapter->rx_itr,
2572 adapter->rx_ring->total_packets,
2573 adapter->rx_ring->total_bytes);
9d5c8243 2574
6eb5a7f1 2575 if (adapter->rx_ring->buddy) {
9d5c8243
AK		 2576 adapter->tx_itr = igb_update_itr(adapter,
2577 adapter->tx_itr,
2578 adapter->tx_ring->total_packets,
2579 adapter->tx_ring->total_bytes);
9d5c8243
AK		 2580
2581 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2582 } else {
2583 current_itr = adapter->rx_itr;
2584 }
2585
6eb5a7f1
AD		 2586 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2587 if (adapter->itr_setting == 3 &&
2588 current_itr == lowest_latency)
2589 current_itr = low_latency;
2590
9d5c8243
AK		 2591 switch (current_itr) {
2592 /* counts and packets in update_itr are dependent on these numbers */
2593 case lowest_latency:
2594 new_itr = 70000;
2595 break;
2596 case low_latency:
2597 new_itr = 20000; /* aka hwitr = ~200 */
2598 break;
2599 case bulk_latency:
2600 new_itr = 4000;
2601 break;
2602 default:
2603 break;
2604 }
2605
2606set_itr_now:
6eb5a7f1
AD		 2607 adapter->rx_ring->total_bytes = 0;
2608 adapter->rx_ring->total_packets = 0;
2609 if (adapter->rx_ring->buddy) {
2610 adapter->rx_ring->buddy->total_bytes = 0;
2611 adapter->rx_ring->buddy->total_packets = 0;
2612 }
2613
9d5c8243
AK		 2614 if (new_itr != adapter->itr) {
2615 /* this attempts to bias the interrupt rate towards Bulk
2616 * by adding intermediate steps when interrupt rate is
2617 * increasing */
2618 new_itr = new_itr > adapter->itr ?
2619 min(adapter->itr + (new_itr >> 2), new_itr) :
2620 new_itr;
2621 /* Don't write the value here; it resets the adapter's
2622 * internal timer, and causes us to delay far longer than
2623 * we should between interrupts. Instead, we write the ITR
2624 * value at the beginning of the next interrupt so the timing
2625 * ends up being correct.
2626 */
2627 adapter->itr = new_itr;
6eb5a7f1
AD		 2628 adapter->rx_ring->itr_val = 1000000000 / (new_itr * 256);
2629 adapter->rx_ring->set_itr = 1;
9d5c8243
AK		 2630 }
2631
2632 return;
2633}
2634
2635
2636#define IGB_TX_FLAGS_CSUM 0x00000001
2637#define IGB_TX_FLAGS_VLAN 0x00000002
2638#define IGB_TX_FLAGS_TSO 0x00000004
2639#define IGB_TX_FLAGS_IPV4 0x00000008
2640#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
2641#define IGB_TX_FLAGS_VLAN_SHIFT 16
2642
2643static inline int igb_tso_adv(struct igb_adapter *adapter,
2644 struct igb_ring *tx_ring,
2645 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
2646{
2647 struct e1000_adv_tx_context_desc *context_desc;
2648 unsigned int i;
2649 int err;
2650 struct igb_buffer *buffer_info;
2651 u32 info = 0, tu_cmd = 0;
2652 u32 mss_l4len_idx, l4len;
2653 *hdr_len = 0;
2654
2655 if (skb_header_cloned(skb)) {
2656 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2657 if (err)
2658 return err;
2659 }
2660
2661 l4len = tcp_hdrlen(skb);
2662 *hdr_len += l4len;
2663
2664 if (skb->protocol == htons(ETH_P_IP)) {
2665 struct iphdr *iph = ip_hdr(skb);
2666 iph->tot_len = 0;
2667 iph->check = 0;
2668 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2669 iph->daddr, 0,
2670 IPPROTO_TCP,
2671 0);
2672 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
2673 ipv6_hdr(skb)->payload_len = 0;
2674 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2675 &ipv6_hdr(skb)->daddr,
2676 0, IPPROTO_TCP, 0);
2677 }
2678
2679 i = tx_ring->next_to_use;
2680
2681 buffer_info = &tx_ring->buffer_info[i];
2682 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2683 /* VLAN MACLEN IPLEN */
2684 if (tx_flags & IGB_TX_FLAGS_VLAN)
2685 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2686 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2687 *hdr_len += skb_network_offset(skb);
2688 info |= skb_network_header_len(skb);
2689 *hdr_len += skb_network_header_len(skb);
2690 context_desc->vlan_macip_lens = cpu_to_le32(info);
2691
2692 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
2693 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2694
2695 if (skb->protocol == htons(ETH_P_IP))
2696 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
2697 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2698
2699 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2700
2701 /* MSS L4LEN IDX */
2702 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
2703 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
2704
7dfc16fa
AD		 2705 /* Context index must be unique per ring. */
2706 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2707 mss_l4len_idx |= tx_ring->queue_index << 4;
9d5c8243
AK		 2708
2709 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
2710 context_desc->seqnum_seed = 0;
2711
2712 buffer_info->time_stamp = jiffies;
0e014cb1 2713 buffer_info->next_to_watch = i;
9d5c8243
AK		 2714 buffer_info->dma = 0;
2715 i++;
2716 if (i == tx_ring->count)
2717 i = 0;
2718
2719 tx_ring->next_to_use = i;
2720
2721 return true;
2722}
2723
2724static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
2725 struct igb_ring *tx_ring,
2726 struct sk_buff *skb, u32 tx_flags)
2727{
2728 struct e1000_adv_tx_context_desc *context_desc;
2729 unsigned int i;
2730 struct igb_buffer *buffer_info;
2731 u32 info = 0, tu_cmd = 0;
2732
2733 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
2734 (tx_flags & IGB_TX_FLAGS_VLAN)) {
2735 i = tx_ring->next_to_use;
2736 buffer_info = &tx_ring->buffer_info[i];
2737 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2738
2739 if (tx_flags & IGB_TX_FLAGS_VLAN)
2740 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2741 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2742 if (skb->ip_summed == CHECKSUM_PARTIAL)
2743 info |= skb_network_header_len(skb);
2744
2745 context_desc->vlan_macip_lens = cpu_to_le32(info);
2746
2747 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2748
2749 if (skb->ip_summed == CHECKSUM_PARTIAL) {
44b0cda3 2750 switch (skb->protocol) {
09640e63 2751 case cpu_to_be16(ETH_P_IP):
9d5c8243 2752 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
44b0cda3
MW		 2753 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
2754 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2755 break;
09640e63 2756 case cpu_to_be16(ETH_P_IPV6):
44b0cda3
MW		 2757 /* XXX what about other V6 headers?? */
2758 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
2759 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2760 break;
2761 default:
2762 if (unlikely(net_ratelimit()))
2763 dev_warn(&adapter->pdev->dev,
2764 "partial checksum but proto=%x!\n",
2765 skb->protocol);
2766 break;
2767 }
9d5c8243
AK		 2768 }
2769
2770 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2771 context_desc->seqnum_seed = 0;
7dfc16fa
AD		 2772 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2773 context_desc->mss_l4len_idx =
2774 cpu_to_le32(tx_ring->queue_index << 4);
9d5c8243
AK		 2775
2776 buffer_info->time_stamp = jiffies;
0e014cb1 2777 buffer_info->next_to_watch = i;
9d5c8243
AK		 2778 buffer_info->dma = 0;
2779
2780 i++;
2781 if (i == tx_ring->count)
2782 i = 0;
2783 tx_ring->next_to_use = i;
2784
2785 return true;
2786 }
2787
2788
2789 return false;
2790}
2791
2792#define IGB_MAX_TXD_PWR 16
2793#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
2794
2795static inline int igb_tx_map_adv(struct igb_adapter *adapter,
0e014cb1
AD		 2796 struct igb_ring *tx_ring, struct sk_buff *skb,
2797 unsigned int first)
9d5c8243
AK		 2798{
2799 struct igb_buffer *buffer_info;
2800 unsigned int len = skb_headlen(skb);
2801 unsigned int count = 0, i;
2802 unsigned int f;
2803
2804 i = tx_ring->next_to_use;
2805
2806 buffer_info = &tx_ring->buffer_info[i];
2807 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2808 buffer_info->length = len;
2809 /* set time_stamp *before* dma to help avoid a possible race */
2810 buffer_info->time_stamp = jiffies;
0e014cb1 2811 buffer_info->next_to_watch = i;
9d5c8243
AK		 2812 buffer_info->dma = pci_map_single(adapter->pdev, skb->data, len,
2813 PCI_DMA_TODEVICE);
2814 count++;
2815 i++;
2816 if (i == tx_ring->count)
2817 i = 0;
2818
2819 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
2820 struct skb_frag_struct *frag;
2821
2822 frag = &skb_shinfo(skb)->frags[f];
2823 len = frag->size;
2824
2825 buffer_info = &tx_ring->buffer_info[i];
2826 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2827 buffer_info->length = len;
2828 buffer_info->time_stamp = jiffies;
0e014cb1 2829 buffer_info->next_to_watch = i;
9d5c8243
AK		 2830 buffer_info->dma = pci_map_page(adapter->pdev,
2831 frag->page,
2832 frag->page_offset,
2833 len,
2834 PCI_DMA_TODEVICE);
2835
2836 count++;
2837 i++;
2838 if (i == tx_ring->count)
2839 i = 0;
2840 }
2841
0e014cb1 2842 i = ((i == 0) ? tx_ring->count - 1 : i - 1);
9d5c8243 2843 tx_ring->buffer_info[i].skb = skb;
0e014cb1 2844 tx_ring->buffer_info[first].next_to_watch = i;
9d5c8243
AK		 2845
2846 return count;
2847}
2848
2849static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
2850 struct igb_ring *tx_ring,
2851 int tx_flags, int count, u32 paylen,
2852 u8 hdr_len)
2853{
2854 union e1000_adv_tx_desc *tx_desc = NULL;
2855 struct igb_buffer *buffer_info;
2856 u32 olinfo_status = 0, cmd_type_len;
2857 unsigned int i;
2858
2859 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
2860 E1000_ADVTXD_DCMD_DEXT);
2861
2862 if (tx_flags & IGB_TX_FLAGS_VLAN)
2863 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
2864
2865 if (tx_flags & IGB_TX_FLAGS_TSO) {
2866 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
2867
2868 /* insert tcp checksum */
2869 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2870
2871 /* insert ip checksum */
2872 if (tx_flags & IGB_TX_FLAGS_IPV4)
2873 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
2874
2875 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
2876 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2877 }
2878
7dfc16fa
AD		 2879 if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) &&
2880 (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
2881 IGB_TX_FLAGS_VLAN)))
661086df 2882 olinfo_status |= tx_ring->queue_index << 4;
9d5c8243
AK		 2883
2884 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
2885
2886 i = tx_ring->next_to_use;
2887 while (count--) {
2888 buffer_info = &tx_ring->buffer_info[i];
2889 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
2890 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
2891 tx_desc->read.cmd_type_len =
2892 cpu_to_le32(cmd_type_len | buffer_info->length);
2893 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
2894 i++;
2895 if (i == tx_ring->count)
2896 i = 0;
2897 }
2898
2899 tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
2900 /* Force memory writes to complete before letting h/w
2901 * know there are new descriptors to fetch. (Only
2902 * applicable for weak-ordered memory model archs,
2903 * such as IA-64). */
2904 wmb();
2905
2906 tx_ring->next_to_use = i;
2907 writel(i, adapter->hw.hw_addr + tx_ring->tail);
2908 /* we need this if more than one processor can write to our tail
2909 * at a time, it syncronizes IO on IA64/Altix systems */
2910 mmiowb();
2911}
2912
2913static int __igb_maybe_stop_tx(struct net_device *netdev,
2914 struct igb_ring *tx_ring, int size)
2915{
2916 struct igb_adapter *adapter = netdev_priv(netdev);
2917
661086df 2918 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 2919
9d5c8243
AK		 2920 /* Herbert's original patch had:
2921 * smp_mb__after_netif_stop_queue();
2922 * but since that doesn't exist yet, just open code it. */
2923 smp_mb();
2924
2925 /* We need to check again in a case another CPU has just
2926 * made room available. */
2927 if (IGB_DESC_UNUSED(tx_ring) < size)
2928 return -EBUSY;
2929
2930 /* A reprieve! */
661086df 2931 netif_wake_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 2932 ++adapter->restart_queue;
2933 return 0;
2934}
2935
2936static int igb_maybe_stop_tx(struct net_device *netdev,
2937 struct igb_ring *tx_ring, int size)
2938{
2939 if (IGB_DESC_UNUSED(tx_ring) >= size)
2940 return 0;
2941 return __igb_maybe_stop_tx(netdev, tx_ring, size);
2942}
2943
2944#define TXD_USE_COUNT(S) (((S) >> (IGB_MAX_TXD_PWR)) + 1)
2945
2946static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
2947 struct net_device *netdev,
2948 struct igb_ring *tx_ring)
2949{
2950 struct igb_adapter *adapter = netdev_priv(netdev);
0e014cb1 2951 unsigned int first;
9d5c8243
AK		 2952 unsigned int tx_flags = 0;
2953 unsigned int len;
9d5c8243
AK		 2954 u8 hdr_len = 0;
2955 int tso = 0;
2956
2957 len = skb_headlen(skb);
2958
2959 if (test_bit(__IGB_DOWN, &adapter->state)) {
2960 dev_kfree_skb_any(skb);
2961 return NETDEV_TX_OK;
2962 }
2963
2964 if (skb->len <= 0) {
2965 dev_kfree_skb_any(skb);
2966 return NETDEV_TX_OK;
2967 }
2968
9d5c8243
AK		 2969 /* need: 1 descriptor per page,
2970 * + 2 desc gap to keep tail from touching head,
2971 * + 1 desc for skb->data,
2972 * + 1 desc for context descriptor,
2973 * otherwise try next time */
2974 if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
2975 /* this is a hard error */
9d5c8243
AK		 2976 return NETDEV_TX_BUSY;
2977 }
6eb5a7f1 2978 skb_orphan(skb);
9d5c8243
AK		 2979
2980 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
2981 tx_flags |= IGB_TX_FLAGS_VLAN;
2982 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
2983 }
2984
661086df
PWJ		 2985 if (skb->protocol == htons(ETH_P_IP))
2986 tx_flags |= IGB_TX_FLAGS_IPV4;
2987
0e014cb1
AD		 2988 first = tx_ring->next_to_use;
2989
9d5c8243
AK		 2990 tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
2991 &hdr_len) : 0;
2992
2993 if (tso < 0) {
2994 dev_kfree_skb_any(skb);
9d5c8243
AK		 2995 return NETDEV_TX_OK;
2996 }
2997
2998 if (tso)
2999 tx_flags |= IGB_TX_FLAGS_TSO;
3000 else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags))
3001 if (skb->ip_summed == CHECKSUM_PARTIAL)
3002 tx_flags |= IGB_TX_FLAGS_CSUM;
3003
9d5c8243 3004 igb_tx_queue_adv(adapter, tx_ring, tx_flags,
0e014cb1 3005 igb_tx_map_adv(adapter, tx_ring, skb, first),
9d5c8243
AK		 3006 skb->len, hdr_len);
3007
3008 netdev->trans_start = jiffies;
3009
3010 /* Make sure there is space in the ring for the next send. */
3011 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
3012
9d5c8243
AK		 3013 return NETDEV_TX_OK;
3014}
3015
3016static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *netdev)
3017{
3018 struct igb_adapter *adapter = netdev_priv(netdev);
661086df
PWJ		 3019 struct igb_ring *tx_ring;
3020
661086df
PWJ		 3021 int r_idx = 0;
3022 r_idx = skb->queue_mapping & (IGB_MAX_TX_QUEUES - 1);
3023 tx_ring = adapter->multi_tx_table[r_idx];
9d5c8243
AK		 3024
3025 /* This goes back to the question of how to logically map a tx queue
3026 * to a flow. Right now, performance is impacted slightly negatively
3027 * if using multiple tx queues. If the stack breaks away from a
3028 * single qdisc implementation, we can look at this again. */
3029 return (igb_xmit_frame_ring_adv(skb, netdev, tx_ring));
3030}
3031
3032/**
3033 * igb_tx_timeout - Respond to a Tx Hang
3034 * @netdev: network interface device structure
3035 **/
3036static void igb_tx_timeout(struct net_device *netdev)
3037{
3038 struct igb_adapter *adapter = netdev_priv(netdev);
3039 struct e1000_hw *hw = &adapter->hw;
3040
3041 /* Do the reset outside of interrupt context */
3042 adapter->tx_timeout_count++;
3043 schedule_work(&adapter->reset_task);
3044 wr32(E1000_EICS, adapter->eims_enable_mask &
3045 ~(E1000_EIMS_TCP_TIMER | E1000_EIMS_OTHER));
3046}
3047
3048static void igb_reset_task(struct work_struct *work)
3049{
3050 struct igb_adapter *adapter;
3051 adapter = container_of(work, struct igb_adapter, reset_task);
3052
3053 igb_reinit_locked(adapter);
3054}
3055
3056/**
3057 * igb_get_stats - Get System Network Statistics
3058 * @netdev: network interface device structure
3059 *
3060 * Returns the address of the device statistics structure.
3061 * The statistics are actually updated from the timer callback.
3062 **/
3063static struct net_device_stats *
3064igb_get_stats(struct net_device *netdev)
3065{
3066 struct igb_adapter *adapter = netdev_priv(netdev);
3067
3068 /* only return the current stats */
3069 return &adapter->net_stats;
3070}
3071
3072/**
3073 * igb_change_mtu - Change the Maximum Transfer Unit
3074 * @netdev: network interface device structure
3075 * @new_mtu: new value for maximum frame size
3076 *
3077 * Returns 0 on success, negative on failure
3078 **/
3079static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3080{
3081 struct igb_adapter *adapter = netdev_priv(netdev);
3082 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3083
3084 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
3085 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3086 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
3087 return -EINVAL;
3088 }
3089
3090#define MAX_STD_JUMBO_FRAME_SIZE 9234
3091 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3092 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
3093 return -EINVAL;
3094 }
3095
3096 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3097 msleep(1);
3098 /* igb_down has a dependency on max_frame_size */
3099 adapter->max_frame_size = max_frame;
3100 if (netif_running(netdev))
3101 igb_down(adapter);
3102
3103 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3104 * means we reserve 2 more, this pushes us to allocate from the next
3105 * larger slab size.
3106 * i.e. RXBUFFER_2048 --> size-4096 slab
3107 */
3108
3109 if (max_frame <= IGB_RXBUFFER_256)
3110 adapter->rx_buffer_len = IGB_RXBUFFER_256;
3111 else if (max_frame <= IGB_RXBUFFER_512)
3112 adapter->rx_buffer_len = IGB_RXBUFFER_512;
3113 else if (max_frame <= IGB_RXBUFFER_1024)
3114 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3115 else if (max_frame <= IGB_RXBUFFER_2048)
3116 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
3117 else
bf36c1a0
AD		 3118#if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
3119 adapter->rx_buffer_len = IGB_RXBUFFER_16384;
3120#else
3121 adapter->rx_buffer_len = PAGE_SIZE / 2;
3122#endif
9d5c8243
AK		 3123 /* adjust allocation if LPE protects us, and we aren't using SBP */
3124 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
3125 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
3126 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3127
3128 dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
3129 netdev->mtu, new_mtu);
3130 netdev->mtu = new_mtu;
3131
3132 if (netif_running(netdev))
3133 igb_up(adapter);
3134 else
3135 igb_reset(adapter);
3136
3137 clear_bit(__IGB_RESETTING, &adapter->state);
3138
3139 return 0;
3140}
3141
3142/**
3143 * igb_update_stats - Update the board statistics counters
3144 * @adapter: board private structure
3145 **/
3146
3147void igb_update_stats(struct igb_adapter *adapter)
3148{
3149 struct e1000_hw *hw = &adapter->hw;
3150 struct pci_dev *pdev = adapter->pdev;
3151 u16 phy_tmp;
3152
3153#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3154
3155 /*
3156 * Prevent stats update while adapter is being reset, or if the pci
3157 * connection is down.
3158 */
3159 if (adapter->link_speed == 0)
3160 return;
3161 if (pci_channel_offline(pdev))
3162 return;
3163
3164 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3165 adapter->stats.gprc += rd32(E1000_GPRC);
3166 adapter->stats.gorc += rd32(E1000_GORCL);
3167 rd32(E1000_GORCH); /* clear GORCL */
3168 adapter->stats.bprc += rd32(E1000_BPRC);
3169 adapter->stats.mprc += rd32(E1000_MPRC);
3170 adapter->stats.roc += rd32(E1000_ROC);
3171
3172 adapter->stats.prc64 += rd32(E1000_PRC64);
3173 adapter->stats.prc127 += rd32(E1000_PRC127);
3174 adapter->stats.prc255 += rd32(E1000_PRC255);
3175 adapter->stats.prc511 += rd32(E1000_PRC511);
3176 adapter->stats.prc1023 += rd32(E1000_PRC1023);
3177 adapter->stats.prc1522 += rd32(E1000_PRC1522);
3178 adapter->stats.symerrs += rd32(E1000_SYMERRS);
3179 adapter->stats.sec += rd32(E1000_SEC);
3180
3181 adapter->stats.mpc += rd32(E1000_MPC);
3182 adapter->stats.scc += rd32(E1000_SCC);
3183 adapter->stats.ecol += rd32(E1000_ECOL);
3184 adapter->stats.mcc += rd32(E1000_MCC);
3185 adapter->stats.latecol += rd32(E1000_LATECOL);
3186 adapter->stats.dc += rd32(E1000_DC);
3187 adapter->stats.rlec += rd32(E1000_RLEC);
3188 adapter->stats.xonrxc += rd32(E1000_XONRXC);
3189 adapter->stats.xontxc += rd32(E1000_XONTXC);
3190 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
3191 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
3192 adapter->stats.fcruc += rd32(E1000_FCRUC);
3193 adapter->stats.gptc += rd32(E1000_GPTC);
3194 adapter->stats.gotc += rd32(E1000_GOTCL);
3195 rd32(E1000_GOTCH); /* clear GOTCL */
3196 adapter->stats.rnbc += rd32(E1000_RNBC);
3197 adapter->stats.ruc += rd32(E1000_RUC);
3198 adapter->stats.rfc += rd32(E1000_RFC);
3199 adapter->stats.rjc += rd32(E1000_RJC);
3200 adapter->stats.tor += rd32(E1000_TORH);
3201 adapter->stats.tot += rd32(E1000_TOTH);
3202 adapter->stats.tpr += rd32(E1000_TPR);
3203
3204 adapter->stats.ptc64 += rd32(E1000_PTC64);
3205 adapter->stats.ptc127 += rd32(E1000_PTC127);
3206 adapter->stats.ptc255 += rd32(E1000_PTC255);
3207 adapter->stats.ptc511 += rd32(E1000_PTC511);
3208 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
3209 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
3210
3211 adapter->stats.mptc += rd32(E1000_MPTC);
3212 adapter->stats.bptc += rd32(E1000_BPTC);
3213
3214 /* used for adaptive IFS */
3215
3216 hw->mac.tx_packet_delta = rd32(E1000_TPT);
3217 adapter->stats.tpt += hw->mac.tx_packet_delta;
3218 hw->mac.collision_delta = rd32(E1000_COLC);
3219 adapter->stats.colc += hw->mac.collision_delta;
3220
3221 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
3222 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3223 adapter->stats.tncrs += rd32(E1000_TNCRS);
3224 adapter->stats.tsctc += rd32(E1000_TSCTC);
3225 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
3226
3227 adapter->stats.iac += rd32(E1000_IAC);
3228 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
3229 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
3230 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
3231 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
3232 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
3233 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
3234 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
3235 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
3236
3237 /* Fill out the OS statistics structure */
3238 adapter->net_stats.multicast = adapter->stats.mprc;
3239 adapter->net_stats.collisions = adapter->stats.colc;
3240
3241 /* Rx Errors */
3242
3243 /* RLEC on some newer hardware can be incorrect so build
3244 * our own version based on RUC and ROC */
3245 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3246 adapter->stats.crcerrs + adapter->stats.algnerrc +
3247 adapter->stats.ruc + adapter->stats.roc +
3248 adapter->stats.cexterr;
3249 adapter->net_stats.rx_length_errors = adapter->stats.ruc +
3250 adapter->stats.roc;
3251 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3252 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
3253 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3254
3255 /* Tx Errors */
3256 adapter->net_stats.tx_errors = adapter->stats.ecol +
3257 adapter->stats.latecol;
3258 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3259 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3260 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3261
3262 /* Tx Dropped needs to be maintained elsewhere */
3263
3264 /* Phy Stats */
3265 if (hw->phy.media_type == e1000_media_type_copper) {
3266 if ((adapter->link_speed == SPEED_1000) &&
f5f4cf08 3267 (!igb_read_phy_reg(hw, PHY_1000T_STATUS,
9d5c8243
AK		 3268 &phy_tmp))) {
3269 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3270 adapter->phy_stats.idle_errors += phy_tmp;
3271 }
3272 }
3273
3274 /* Management Stats */
3275 adapter->stats.mgptc += rd32(E1000_MGTPTC);
3276 adapter->stats.mgprc += rd32(E1000_MGTPRC);
3277 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3278}
3279
3280
3281static irqreturn_t igb_msix_other(int irq, void *data)
3282{
3283 struct net_device *netdev = data;
3284 struct igb_adapter *adapter = netdev_priv(netdev);
3285 struct e1000_hw *hw = &adapter->hw;
844290e5 3286 u32 icr = rd32(E1000_ICR);
9d5c8243 3287
844290e5
PW		 3288 /* reading ICR causes bit 31 of EICR to be cleared */
3289 if (!(icr & E1000_ICR_LSC))
3290 goto no_link_interrupt;
3291 hw->mac.get_link_status = 1;
3292 /* guard against interrupt when we're going down */
3293 if (!test_bit(__IGB_DOWN, &adapter->state))
3294 mod_timer(&adapter->watchdog_timer, jiffies + 1);
661086df 3295
9d5c8243
AK		 3296no_link_interrupt:
3297 wr32(E1000_IMS, E1000_IMS_LSC);
844290e5 3298 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 3299
3300 return IRQ_HANDLED;
3301}
3302
3303static irqreturn_t igb_msix_tx(int irq, void *data)
3304{
3305 struct igb_ring *tx_ring = data;
3306 struct igb_adapter *adapter = tx_ring->adapter;
3307 struct e1000_hw *hw = &adapter->hw;
3308
421e02f0 3309#ifdef CONFIG_IGB_DCA
7dfc16fa 3310 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3311 igb_update_tx_dca(tx_ring);
3312#endif
9d5c8243
AK		 3313 tx_ring->total_bytes = 0;
3314 tx_ring->total_packets = 0;
661086df
PWJ		 3315
3316 /* auto mask will automatically reenable the interrupt when we write
3317 * EICS */
3b644cf6 3318 if (!igb_clean_tx_irq(tx_ring))
9d5c8243
AK		 3319 /* Ring was not completely cleaned, so fire another interrupt */
3320 wr32(E1000_EICS, tx_ring->eims_value);
661086df 3321 else
9d5c8243 3322 wr32(E1000_EIMS, tx_ring->eims_value);
661086df 3323
9d5c8243
AK		 3324 return IRQ_HANDLED;
3325}
3326
6eb5a7f1
AD		 3327static void igb_write_itr(struct igb_ring *ring)
3328{
3329 struct e1000_hw *hw = &ring->adapter->hw;
3330 if ((ring->adapter->itr_setting & 3) && ring->set_itr) {
3331 switch (hw->mac.type) {
3332 case e1000_82576:
3333 wr32(ring->itr_register,
3334 ring->itr_val |
3335 0x80000000);
3336 break;
3337 default:
3338 wr32(ring->itr_register,
3339 ring->itr_val |
3340 (ring->itr_val << 16));
3341 break;
3342 }
3343 ring->set_itr = 0;
3344 }
3345}
3346
9d5c8243
AK		 3347static irqreturn_t igb_msix_rx(int irq, void *data)
3348{
3349 struct igb_ring *rx_ring = data;
9d5c8243 3350
844290e5
PW		 3351 /* Write the ITR value calculated at the end of the
3352 * previous interrupt.
3353 */
9d5c8243 3354
6eb5a7f1 3355 igb_write_itr(rx_ring);
9d5c8243 3356
288379f0
BH		 3357 if (napi_schedule_prep(&rx_ring->napi))
3358 __napi_schedule(&rx_ring->napi);
844290e5 3359
421e02f0 3360#ifdef CONFIG_IGB_DCA
8d253320 3361 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3362 igb_update_rx_dca(rx_ring);
3363#endif
3364 return IRQ_HANDLED;
3365}
3366
421e02f0 3367#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 3368static void igb_update_rx_dca(struct igb_ring *rx_ring)
3369{
3370 u32 dca_rxctrl;
3371 struct igb_adapter *adapter = rx_ring->adapter;
3372 struct e1000_hw *hw = &adapter->hw;
3373 int cpu = get_cpu();
26bc19ec 3374 int q = rx_ring->reg_idx;
fe4506b6
JC		 3375
3376 if (rx_ring->cpu != cpu) {
3377 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
2d064c06
AD		 3378 if (hw->mac.type == e1000_82576) {
3379 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
3380 dca_rxctrl |= dca_get_tag(cpu) <<
3381 E1000_DCA_RXCTRL_CPUID_SHIFT;
3382 } else {
3383 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
3384 dca_rxctrl |= dca_get_tag(cpu);
3385 }
fe4506b6
JC		 3386 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
3387 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
3388 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
3389 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
3390 rx_ring->cpu = cpu;
3391 }
3392 put_cpu();
3393}
3394
3395static void igb_update_tx_dca(struct igb_ring *tx_ring)
3396{
3397 u32 dca_txctrl;
3398 struct igb_adapter *adapter = tx_ring->adapter;
3399 struct e1000_hw *hw = &adapter->hw;
3400 int cpu = get_cpu();
26bc19ec 3401 int q = tx_ring->reg_idx;
fe4506b6
JC		 3402
3403 if (tx_ring->cpu != cpu) {
3404 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
2d064c06
AD		 3405 if (hw->mac.type == e1000_82576) {
3406 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
3407 dca_txctrl |= dca_get_tag(cpu) <<
3408 E1000_DCA_TXCTRL_CPUID_SHIFT;
3409 } else {
3410 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
3411 dca_txctrl |= dca_get_tag(cpu);
3412 }
fe4506b6
JC		 3413 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
3414 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
3415 tx_ring->cpu = cpu;
3416 }
3417 put_cpu();
3418}
3419
3420static void igb_setup_dca(struct igb_adapter *adapter)
3421{
3422 int i;
3423
7dfc16fa 3424 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 3425 return;
3426
3427 for (i = 0; i < adapter->num_tx_queues; i++) {
3428 adapter->tx_ring[i].cpu = -1;
3429 igb_update_tx_dca(&adapter->tx_ring[i]);
3430 }
3431 for (i = 0; i < adapter->num_rx_queues; i++) {
3432 adapter->rx_ring[i].cpu = -1;
3433 igb_update_rx_dca(&adapter->rx_ring[i]);
3434 }
3435}
3436
3437static int __igb_notify_dca(struct device *dev, void *data)
3438{
3439 struct net_device *netdev = dev_get_drvdata(dev);
3440 struct igb_adapter *adapter = netdev_priv(netdev);
3441 struct e1000_hw *hw = &adapter->hw;
3442 unsigned long event = *(unsigned long *)data;
3443
3444 switch (event) {
3445 case DCA_PROVIDER_ADD:
3446 /* if already enabled, don't do it again */
7dfc16fa 3447 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 3448 break;
fe4506b6
JC		 3449 /* Always use CB2 mode, difference is masked
3450 * in the CB driver. */
3451 wr32(E1000_DCA_CTRL, 2);
3452 if (dca_add_requester(dev) == 0) {
bbd98fe4 3453 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 3454 dev_info(&adapter->pdev->dev, "DCA enabled\n");
3455 igb_setup_dca(adapter);
3456 break;
3457 }
3458 /* Fall Through since DCA is disabled. */
3459 case DCA_PROVIDER_REMOVE:
7dfc16fa 3460 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 3461 /* without this a class_device is left
3462 * hanging around in the sysfs model */
3463 dca_remove_requester(dev);
3464 dev_info(&adapter->pdev->dev, "DCA disabled\n");
7dfc16fa 3465 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 3466 wr32(E1000_DCA_CTRL, 1);
3467 }
3468 break;
3469 }
bbd98fe4 3470
fe4506b6 3471 return 0;
9d5c8243
AK		 3472}
3473
fe4506b6
JC		 3474static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
3475 void *p)
3476{
3477 int ret_val;
3478
3479 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
3480 __igb_notify_dca);
3481
3482 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
3483}
421e02f0 3484#endif /* CONFIG_IGB_DCA */
9d5c8243
AK		 3485
3486/**
3487 * igb_intr_msi - Interrupt Handler
3488 * @irq: interrupt number
3489 * @data: pointer to a network interface device structure
3490 **/
3491static irqreturn_t igb_intr_msi(int irq, void *data)
3492{
3493 struct net_device *netdev = data;
3494 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 3495 struct e1000_hw *hw = &adapter->hw;
3496 /* read ICR disables interrupts using IAM */
3497 u32 icr = rd32(E1000_ICR);
3498
6eb5a7f1 3499 igb_write_itr(adapter->rx_ring);
9d5c8243 3500
9d5c8243
AK		 3501 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3502 hw->mac.get_link_status = 1;
3503 if (!test_bit(__IGB_DOWN, &adapter->state))
3504 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3505 }
3506
288379f0 3507 napi_schedule(&adapter->rx_ring[0].napi);
9d5c8243
AK		 3508
3509 return IRQ_HANDLED;
3510}
3511
3512/**
3513 * igb_intr - Interrupt Handler
3514 * @irq: interrupt number
3515 * @data: pointer to a network interface device structure
3516 **/
3517static irqreturn_t igb_intr(int irq, void *data)
3518{
3519 struct net_device *netdev = data;
3520 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 3521 struct e1000_hw *hw = &adapter->hw;
3522 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
3523 * need for the IMC write */
3524 u32 icr = rd32(E1000_ICR);
3525 u32 eicr = 0;
3526 if (!icr)
3527 return IRQ_NONE; /* Not our interrupt */
3528
6eb5a7f1 3529 igb_write_itr(adapter->rx_ring);
9d5c8243
AK		 3530
3531 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
3532 * not set, then the adapter didn't send an interrupt */
3533 if (!(icr & E1000_ICR_INT_ASSERTED))
3534 return IRQ_NONE;
3535
3536 eicr = rd32(E1000_EICR);
3537
3538 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3539 hw->mac.get_link_status = 1;
3540 /* guard against interrupt when we're going down */
3541 if (!test_bit(__IGB_DOWN, &adapter->state))
3542 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3543 }
3544
288379f0 3545 napi_schedule(&adapter->rx_ring[0].napi);
9d5c8243
AK		 3546
3547 return IRQ_HANDLED;
3548}
3549
3550/**
661086df
PWJ		 3551 * igb_poll - NAPI Rx polling callback
3552 * @napi: napi polling structure
3553 * @budget: count of how many packets we should handle
9d5c8243 3554 **/
661086df 3555static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 3556{
661086df
PWJ		 3557 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3558 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 3559 struct net_device *netdev = adapter->netdev;
661086df 3560 int tx_clean_complete, work_done = 0;
9d5c8243 3561
661086df 3562 /* this poll routine only supports one tx and one rx queue */
421e02f0 3563#ifdef CONFIG_IGB_DCA
7dfc16fa 3564 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3565 igb_update_tx_dca(&adapter->tx_ring[0]);
3566#endif
661086df 3567 tx_clean_complete = igb_clean_tx_irq(&adapter->tx_ring[0]);
fe4506b6 3568
421e02f0 3569#ifdef CONFIG_IGB_DCA
7dfc16fa 3570 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3571 igb_update_rx_dca(&adapter->rx_ring[0]);
3572#endif
661086df 3573 igb_clean_rx_irq_adv(&adapter->rx_ring[0], &work_done, budget);
9d5c8243
AK		 3574
3575 /* If no Tx and not enough Rx work done, exit the polling mode */
3576 if ((tx_clean_complete && (work_done < budget)) ||
3577 !netif_running(netdev)) {
9d5c8243 3578 if (adapter->itr_setting & 3)
6eb5a7f1 3579 igb_set_itr(adapter);
288379f0 3580 napi_complete(napi);
9d5c8243
AK		 3581 if (!test_bit(__IGB_DOWN, &adapter->state))
3582 igb_irq_enable(adapter);
3583 return 0;
3584 }
3585
3586 return 1;
3587}
3588
3589static int igb_clean_rx_ring_msix(struct napi_struct *napi, int budget)
3590{
3591 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3592 struct igb_adapter *adapter = rx_ring->adapter;
3593 struct e1000_hw *hw = &adapter->hw;
3594 struct net_device *netdev = adapter->netdev;
3595 int work_done = 0;
3596
421e02f0 3597#ifdef CONFIG_IGB_DCA
7dfc16fa 3598 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3599 igb_update_rx_dca(rx_ring);
3600#endif
3b644cf6 3601 igb_clean_rx_irq_adv(rx_ring, &work_done, budget);
9d5c8243
AK		 3602
3603
3604 /* If not enough Rx work done, exit the polling mode */
3605 if ((work_done == 0) || !netif_running(netdev)) {
288379f0 3606 napi_complete(napi);
9d5c8243 3607
6eb5a7f1
AD		 3608 if (adapter->itr_setting & 3) {
3609 if (adapter->num_rx_queues == 1)
3610 igb_set_itr(adapter);
3611 else
3612 igb_update_ring_itr(rx_ring);
9d5c8243 3613 }
844290e5
PW		 3614
3615 if (!test_bit(__IGB_DOWN, &adapter->state))
3616 wr32(E1000_EIMS, rx_ring->eims_value);
3617
9d5c8243
AK		 3618 return 0;
3619 }
3620
3621 return 1;
3622}
6d8126f9 3623
9d5c8243
AK		 3624/**
3625 * igb_clean_tx_irq - Reclaim resources after transmit completes
3626 * @adapter: board private structure
3627 * returns true if ring is completely cleaned
3628 **/
3b644cf6 3629static bool igb_clean_tx_irq(struct igb_ring *tx_ring)
9d5c8243 3630{
3b644cf6 3631 struct igb_adapter *adapter = tx_ring->adapter;
3b644cf6 3632 struct net_device *netdev = adapter->netdev;
0e014cb1 3633 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 3634 struct igb_buffer *buffer_info;
3635 struct sk_buff *skb;
0e014cb1 3636 union e1000_adv_tx_desc *tx_desc, *eop_desc;
9d5c8243 3637 unsigned int total_bytes = 0, total_packets = 0;
0e014cb1
AD		 3638 unsigned int i, eop, count = 0;
3639 bool cleaned = false;
9d5c8243 3640
9d5c8243 3641 i = tx_ring->next_to_clean;
0e014cb1
AD		 3642 eop = tx_ring->buffer_info[i].next_to_watch;
3643 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
3644
3645 while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) &&
3646 (count < tx_ring->count)) {
3647 for (cleaned = false; !cleaned; count++) {
3648 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
9d5c8243 3649 buffer_info = &tx_ring->buffer_info[i];
0e014cb1 3650 cleaned = (i == eop);
9d5c8243
AK		 3651 skb = buffer_info->skb;
3652
3653 if (skb) {
3654 unsigned int segs, bytecount;
3655 /* gso_segs is currently only valid for tcp */
3656 segs = skb_shinfo(skb)->gso_segs ?: 1;
3657 /* multiply data chunks by size of headers */
3658 bytecount = ((segs - 1) * skb_headlen(skb)) +
3659 skb->len;
3660 total_packets += segs;
3661 total_bytes += bytecount;
3662 }
3663
3664 igb_unmap_and_free_tx_resource(adapter, buffer_info);
0e014cb1 3665 tx_desc->wb.status = 0;
9d5c8243
AK		 3666
3667 i++;
3668 if (i == tx_ring->count)
3669 i = 0;
9d5c8243 3670 }
0e014cb1
AD		 3671
3672 eop = tx_ring->buffer_info[i].next_to_watch;
3673 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
3674 }
3675
9d5c8243
AK		 3676 tx_ring->next_to_clean = i;
3677
fc7d345d 3678 if (unlikely(count &&
9d5c8243
AK		 3679 netif_carrier_ok(netdev) &&
3680 IGB_DESC_UNUSED(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
3681 /* Make sure that anybody stopping the queue after this
3682 * sees the new next_to_clean.
3683 */
3684 smp_mb();
661086df
PWJ		 3685 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
3686 !(test_bit(__IGB_DOWN, &adapter->state))) {
3687 netif_wake_subqueue(netdev, tx_ring->queue_index);
3688 ++adapter->restart_queue;
3689 }
9d5c8243
AK		 3690 }
3691
3692 if (tx_ring->detect_tx_hung) {
3693 /* Detect a transmit hang in hardware, this serializes the
3694 * check with the clearing of time_stamp and movement of i */
3695 tx_ring->detect_tx_hung = false;
3696 if (tx_ring->buffer_info[i].time_stamp &&
3697 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
3698 (adapter->tx_timeout_factor * HZ))
3699 && !(rd32(E1000_STATUS) &
3700 E1000_STATUS_TXOFF)) {
3701
9d5c8243
AK		 3702 /* detected Tx unit hang */
3703 dev_err(&adapter->pdev->dev,
3704 "Detected Tx Unit Hang\n"
2d064c06 3705 " Tx Queue <%d>\n"
9d5c8243
AK		 3706 " TDH <%x>\n"
3707 " TDT <%x>\n"
3708 " next_to_use <%x>\n"
3709 " next_to_clean <%x>\n"
9d5c8243
AK		 3710 "buffer_info[next_to_clean]\n"
3711 " time_stamp <%lx>\n"
0e014cb1 3712 " next_to_watch <%x>\n"
9d5c8243
AK		 3713 " jiffies <%lx>\n"
3714 " desc.status <%x>\n",
2d064c06 3715 tx_ring->queue_index,
9d5c8243
AK		 3716 readl(adapter->hw.hw_addr + tx_ring->head),
3717 readl(adapter->hw.hw_addr + tx_ring->tail),
3718 tx_ring->next_to_use,
3719 tx_ring->next_to_clean,
9d5c8243 3720 tx_ring->buffer_info[i].time_stamp,
0e014cb1 3721 eop,
9d5c8243 3722 jiffies,
0e014cb1 3723 eop_desc->wb.status);
661086df 3724 netif_stop_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 3725 }
3726 }
3727 tx_ring->total_bytes += total_bytes;
3728 tx_ring->total_packets += total_packets;
e21ed353
AD		 3729 tx_ring->tx_stats.bytes += total_bytes;
3730 tx_ring->tx_stats.packets += total_packets;
9d5c8243
AK		 3731 adapter->net_stats.tx_bytes += total_bytes;
3732 adapter->net_stats.tx_packets += total_packets;
0e014cb1 3733 return (count < tx_ring->count);
9d5c8243
AK		 3734}
3735
9d5c8243
AK		 3736/**
3737 * igb_receive_skb - helper function to handle rx indications
d3352520 3738 * @ring: pointer to receive ring receving this packet
9d5c8243
AK		 3739 * @status: descriptor status field as written by hardware
3740 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
3741 * @skb: pointer to sk_buff to be indicated to stack
3742 **/
d3352520
AD		 3743static void igb_receive_skb(struct igb_ring *ring, u8 status,
3744 union e1000_adv_rx_desc * rx_desc,
3745 struct sk_buff *skb)
3746{
3747 struct igb_adapter * adapter = ring->adapter;
3748 bool vlan_extracted = (adapter->vlgrp && (status & E1000_RXD_STAT_VP));
3749
0c8dfc83 3750 skb_record_rx_queue(skb, ring->queue_index);
5c0999b7 3751 if (skb->ip_summed == CHECKSUM_UNNECESSARY) {
d3352520 3752 if (vlan_extracted)
5c0999b7
HX		 3753 vlan_gro_receive(&ring->napi, adapter->vlgrp,
3754 le16_to_cpu(rx_desc->wb.upper.vlan),
3755 skb);
d3352520 3756 else
5c0999b7 3757 napi_gro_receive(&ring->napi, skb);
d3352520 3758 } else {
d3352520
AD		 3759 if (vlan_extracted)
3760 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
3761 le16_to_cpu(rx_desc->wb.upper.vlan));
3762 else
d3352520 3763 netif_receive_skb(skb);
d3352520 3764 }
9d5c8243
AK		 3765}
3766
3767
3768static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
3769 u32 status_err, struct sk_buff *skb)
3770{
3771 skb->ip_summed = CHECKSUM_NONE;
3772
3773 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
3774 if ((status_err & E1000_RXD_STAT_IXSM) || !adapter->rx_csum)
3775 return;
3776 /* TCP/UDP checksum error bit is set */
3777 if (status_err &
3778 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
3779 /* let the stack verify checksum errors */
3780 adapter->hw_csum_err++;
3781 return;
3782 }
3783 /* It must be a TCP or UDP packet with a valid checksum */
3784 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
3785 skb->ip_summed = CHECKSUM_UNNECESSARY;
3786
3787 adapter->hw_csum_good++;
3788}
3789
3b644cf6
MW		 3790static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring,
3791 int *work_done, int budget)
9d5c8243 3792{
3b644cf6 3793 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 3794 struct net_device *netdev = adapter->netdev;
3795 struct pci_dev *pdev = adapter->pdev;
3796 union e1000_adv_rx_desc *rx_desc , *next_rxd;
3797 struct igb_buffer *buffer_info , *next_buffer;
3798 struct sk_buff *skb;
bf36c1a0 3799 unsigned int i;
9d5c8243
AK		 3800 u32 length, hlen, staterr;
3801 bool cleaned = false;
3802 int cleaned_count = 0;
3803 unsigned int total_bytes = 0, total_packets = 0;
3804
3805 i = rx_ring->next_to_clean;
69d3ca53 3806 buffer_info = &rx_ring->buffer_info[i];
9d5c8243
AK		 3807 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3808 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3809
3810 while (staterr & E1000_RXD_STAT_DD) {
3811 if (*work_done >= budget)
3812 break;
3813 (*work_done)++;
9d5c8243 3814
69d3ca53
AD		 3815 skb = buffer_info->skb;
3816 prefetch(skb->data - NET_IP_ALIGN);
3817 buffer_info->skb = NULL;
3818
3819 i++;
3820 if (i == rx_ring->count)
3821 i = 0;
3822 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
3823 prefetch(next_rxd);
3824 next_buffer = &rx_ring->buffer_info[i];
9d5c8243
AK		 3825
3826 length = le16_to_cpu(rx_desc->wb.upper.length);
3827 cleaned = true;
3828 cleaned_count++;
3829
bf36c1a0
AD		 3830 if (!adapter->rx_ps_hdr_size) {
3831 pci_unmap_single(pdev, buffer_info->dma,
3832 adapter->rx_buffer_len +
3833 NET_IP_ALIGN,
3834 PCI_DMA_FROMDEVICE);
3835 skb_put(skb, length);
3836 goto send_up;
9d5c8243
AK		 3837 }
3838
69d3ca53
AD		 3839 /* HW will not DMA in data larger than the given buffer, even
3840 * if it parses the (NFS, of course) header to be larger. In
3841 * that case, it fills the header buffer and spills the rest
3842 * into the page.
3843 */
3844 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
3845 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
3846 if (hlen > adapter->rx_ps_hdr_size)
3847 hlen = adapter->rx_ps_hdr_size;
3848
bf36c1a0
AD		 3849 if (!skb_shinfo(skb)->nr_frags) {
3850 pci_unmap_single(pdev, buffer_info->dma,
3851 adapter->rx_ps_hdr_size +
3852 NET_IP_ALIGN,
3853 PCI_DMA_FROMDEVICE);
3854 skb_put(skb, hlen);
3855 }
3856
3857 if (length) {
9d5c8243 3858 pci_unmap_page(pdev, buffer_info->page_dma,
bf36c1a0 3859 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9d5c8243 3860 buffer_info->page_dma = 0;
bf36c1a0
AD		 3861
3862 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
3863 buffer_info->page,
3864 buffer_info->page_offset,
3865 length);
3866
3867 if ((adapter->rx_buffer_len > (PAGE_SIZE / 2)) ||
3868 (page_count(buffer_info->page) != 1))
3869 buffer_info->page = NULL;
3870 else
3871 get_page(buffer_info->page);
9d5c8243
AK		 3872
3873 skb->len += length;
3874 skb->data_len += length;
9d5c8243 3875
bf36c1a0 3876 skb->truesize += length;
9d5c8243 3877 }
9d5c8243 3878
bf36c1a0 3879 if (!(staterr & E1000_RXD_STAT_EOP)) {
b2d56536
AD		 3880 buffer_info->skb = next_buffer->skb;
3881 buffer_info->dma = next_buffer->dma;
3882 next_buffer->skb = skb;
3883 next_buffer->dma = 0;
bf36c1a0
AD		 3884 goto next_desc;
3885 }
69d3ca53 3886send_up:
9d5c8243
AK		 3887 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
3888 dev_kfree_skb_irq(skb);
3889 goto next_desc;
3890 }
9d5c8243
AK		 3891
3892 total_bytes += skb->len;
3893 total_packets++;
3894
3895 igb_rx_checksum_adv(adapter, staterr, skb);
3896
3897 skb->protocol = eth_type_trans(skb, netdev);
3898
d3352520 3899 igb_receive_skb(rx_ring, staterr, rx_desc, skb);
9d5c8243 3900
9d5c8243
AK		 3901next_desc:
3902 rx_desc->wb.upper.status_error = 0;
3903
3904 /* return some buffers to hardware, one at a time is too slow */
3905 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
3b644cf6 3906 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 3907 cleaned_count = 0;
3908 }
3909
3910 /* use prefetched values */
3911 rx_desc = next_rxd;
3912 buffer_info = next_buffer;
9d5c8243
AK		 3913 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3914 }
bf36c1a0 3915
9d5c8243
AK		 3916 rx_ring->next_to_clean = i;
3917 cleaned_count = IGB_DESC_UNUSED(rx_ring);
3918
3919 if (cleaned_count)
3b644cf6 3920 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 3921
3922 rx_ring->total_packets += total_packets;
3923 rx_ring->total_bytes += total_bytes;
3924 rx_ring->rx_stats.packets += total_packets;
3925 rx_ring->rx_stats.bytes += total_bytes;
3926 adapter->net_stats.rx_bytes += total_bytes;
3927 adapter->net_stats.rx_packets += total_packets;
3928 return cleaned;
3929}
3930
3931
3932/**
3933 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
3934 * @adapter: address of board private structure
3935 **/
3b644cf6 3936static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
9d5c8243
AK		 3937 int cleaned_count)
3938{
3b644cf6 3939 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 3940 struct net_device *netdev = adapter->netdev;
3941 struct pci_dev *pdev = adapter->pdev;
3942 union e1000_adv_rx_desc *rx_desc;
3943 struct igb_buffer *buffer_info;
3944 struct sk_buff *skb;
3945 unsigned int i;
db761762 3946 int bufsz;
9d5c8243
AK		 3947
3948 i = rx_ring->next_to_use;
3949 buffer_info = &rx_ring->buffer_info[i];
3950
db761762
AD		 3951 if (adapter->rx_ps_hdr_size)
3952 bufsz = adapter->rx_ps_hdr_size;
3953 else
3954 bufsz = adapter->rx_buffer_len;
3955 bufsz += NET_IP_ALIGN;
3956
9d5c8243
AK		 3957 while (cleaned_count--) {
3958 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3959
bf36c1a0 3960 if (adapter->rx_ps_hdr_size && !buffer_info->page_dma) {
9d5c8243 3961 if (!buffer_info->page) {
bf36c1a0
AD		 3962 buffer_info->page = alloc_page(GFP_ATOMIC);
3963 if (!buffer_info->page) {
3964 adapter->alloc_rx_buff_failed++;
3965 goto no_buffers;
3966 }
3967 buffer_info->page_offset = 0;
3968 } else {
3969 buffer_info->page_offset ^= PAGE_SIZE / 2;
9d5c8243
AK		 3970 }
3971 buffer_info->page_dma =
db761762 3972 pci_map_page(pdev, buffer_info->page,
bf36c1a0
AD		 3973 buffer_info->page_offset,
3974 PAGE_SIZE / 2,
9d5c8243
AK		 3975 PCI_DMA_FROMDEVICE);
3976 }
3977
3978 if (!buffer_info->skb) {
9d5c8243 3979 skb = netdev_alloc_skb(netdev, bufsz);
9d5c8243
AK		 3980 if (!skb) {
3981 adapter->alloc_rx_buff_failed++;
3982 goto no_buffers;
3983 }
3984
3985 /* Make buffer alignment 2 beyond a 16 byte boundary
3986 * this will result in a 16 byte aligned IP header after
3987 * the 14 byte MAC header is removed
3988 */
3989 skb_reserve(skb, NET_IP_ALIGN);
3990
3991 buffer_info->skb = skb;
3992 buffer_info->dma = pci_map_single(pdev, skb->data,
3993 bufsz,
3994 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 3995 }
3996 /* Refresh the desc even if buffer_addrs didn't change because
3997 * each write-back erases this info. */
3998 if (adapter->rx_ps_hdr_size) {
3999 rx_desc->read.pkt_addr =
4000 cpu_to_le64(buffer_info->page_dma);
4001 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
4002 } else {
4003 rx_desc->read.pkt_addr =
4004 cpu_to_le64(buffer_info->dma);
4005 rx_desc->read.hdr_addr = 0;
4006 }
4007
4008 i++;
4009 if (i == rx_ring->count)
4010 i = 0;
4011 buffer_info = &rx_ring->buffer_info[i];
4012 }
4013
4014no_buffers:
4015 if (rx_ring->next_to_use != i) {
4016 rx_ring->next_to_use = i;
4017 if (i == 0)
4018 i = (rx_ring->count - 1);
4019 else
4020 i--;
4021
4022 /* Force memory writes to complete before letting h/w
4023 * know there are new descriptors to fetch. (Only
4024 * applicable for weak-ordered memory model archs,
4025 * such as IA-64). */
4026 wmb();
4027 writel(i, adapter->hw.hw_addr + rx_ring->tail);
4028 }
4029}
4030
4031/**
4032 * igb_mii_ioctl -
4033 * @netdev:
4034 * @ifreq:
4035 * @cmd:
4036 **/
4037static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4038{
4039 struct igb_adapter *adapter = netdev_priv(netdev);
4040 struct mii_ioctl_data *data = if_mii(ifr);
4041
4042 if (adapter->hw.phy.media_type != e1000_media_type_copper)
4043 return -EOPNOTSUPP;
4044
4045 switch (cmd) {
4046 case SIOCGMIIPHY:
4047 data->phy_id = adapter->hw.phy.addr;
4048 break;
4049 case SIOCGMIIREG:
4050 if (!capable(CAP_NET_ADMIN))
4051 return -EPERM;
f5f4cf08
AD		 4052 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
4053 &data->val_out))
9d5c8243
AK		 4054 return -EIO;
4055 break;
4056 case SIOCSMIIREG:
4057 default:
4058 return -EOPNOTSUPP;
4059 }
4060 return 0;
4061}
4062
4063/**
4064 * igb_ioctl -
4065 * @netdev:
4066 * @ifreq:
4067 * @cmd:
4068 **/
4069static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4070{
4071 switch (cmd) {
4072 case SIOCGMIIPHY:
4073 case SIOCGMIIREG:
4074 case SIOCSMIIREG:
4075 return igb_mii_ioctl(netdev, ifr, cmd);
4076 default:
4077 return -EOPNOTSUPP;
4078 }
4079}
4080
4081static void igb_vlan_rx_register(struct net_device *netdev,
4082 struct vlan_group *grp)
4083{
4084 struct igb_adapter *adapter = netdev_priv(netdev);
4085 struct e1000_hw *hw = &adapter->hw;
4086 u32 ctrl, rctl;
4087
4088 igb_irq_disable(adapter);
4089 adapter->vlgrp = grp;
4090
4091 if (grp) {
4092 /* enable VLAN tag insert/strip */
4093 ctrl = rd32(E1000_CTRL);
4094 ctrl |= E1000_CTRL_VME;
4095 wr32(E1000_CTRL, ctrl);
4096
4097 /* enable VLAN receive filtering */
4098 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 4099 rctl &= ~E1000_RCTL_CFIEN;
4100 wr32(E1000_RCTL, rctl);
4101 igb_update_mng_vlan(adapter);
4102 wr32(E1000_RLPML,
4103 adapter->max_frame_size + VLAN_TAG_SIZE);
4104 } else {
4105 /* disable VLAN tag insert/strip */
4106 ctrl = rd32(E1000_CTRL);
4107 ctrl &= ~E1000_CTRL_VME;
4108 wr32(E1000_CTRL, ctrl);
4109
9d5c8243
AK		 4110 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
4111 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4112 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
4113 }
4114 wr32(E1000_RLPML,
4115 adapter->max_frame_size);
4116 }
4117
4118 if (!test_bit(__IGB_DOWN, &adapter->state))
4119 igb_irq_enable(adapter);
4120}
4121
4122static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
4123{
4124 struct igb_adapter *adapter = netdev_priv(netdev);
4125 struct e1000_hw *hw = &adapter->hw;
4126 u32 vfta, index;
4127
4128 if ((adapter->hw.mng_cookie.status &
4129 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4130 (vid == adapter->mng_vlan_id))
4131 return;
4132 /* add VID to filter table */
4133 index = (vid >> 5) & 0x7F;
4134 vfta = array_rd32(E1000_VFTA, index);
4135 vfta |= (1 << (vid & 0x1F));
4136 igb_write_vfta(&adapter->hw, index, vfta);
4137}
4138
4139static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
4140{
4141 struct igb_adapter *adapter = netdev_priv(netdev);
4142 struct e1000_hw *hw = &adapter->hw;
4143 u32 vfta, index;
4144
4145 igb_irq_disable(adapter);
4146 vlan_group_set_device(adapter->vlgrp, vid, NULL);
4147
4148 if (!test_bit(__IGB_DOWN, &adapter->state))
4149 igb_irq_enable(adapter);
4150
4151 if ((adapter->hw.mng_cookie.status &
4152 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4153 (vid == adapter->mng_vlan_id)) {
4154 /* release control to f/w */
4155 igb_release_hw_control(adapter);
4156 return;
4157 }
4158
4159 /* remove VID from filter table */
4160 index = (vid >> 5) & 0x7F;
4161 vfta = array_rd32(E1000_VFTA, index);
4162 vfta &= ~(1 << (vid & 0x1F));
4163 igb_write_vfta(&adapter->hw, index, vfta);
4164}
4165
4166static void igb_restore_vlan(struct igb_adapter *adapter)
4167{
4168 igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
4169
4170 if (adapter->vlgrp) {
4171 u16 vid;
4172 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
4173 if (!vlan_group_get_device(adapter->vlgrp, vid))
4174 continue;
4175 igb_vlan_rx_add_vid(adapter->netdev, vid);
4176 }
4177 }
4178}
4179
4180int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
4181{
4182 struct e1000_mac_info *mac = &adapter->hw.mac;
4183
4184 mac->autoneg = 0;
4185
4186 /* Fiber NICs only allow 1000 gbps Full duplex */
4187 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) &&
4188 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
4189 dev_err(&adapter->pdev->dev,
4190 "Unsupported Speed/Duplex configuration\n");
4191 return -EINVAL;
4192 }
4193
4194 switch (spddplx) {
4195 case SPEED_10 + DUPLEX_HALF:
4196 mac->forced_speed_duplex = ADVERTISE_10_HALF;
4197 break;
4198 case SPEED_10 + DUPLEX_FULL:
4199 mac->forced_speed_duplex = ADVERTISE_10_FULL;
4200 break;
4201 case SPEED_100 + DUPLEX_HALF:
4202 mac->forced_speed_duplex = ADVERTISE_100_HALF;
4203 break;
4204 case SPEED_100 + DUPLEX_FULL:
4205 mac->forced_speed_duplex = ADVERTISE_100_FULL;
4206 break;
4207 case SPEED_1000 + DUPLEX_FULL:
4208 mac->autoneg = 1;
4209 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
4210 break;
4211 case SPEED_1000 + DUPLEX_HALF: /* not supported */
4212 default:
4213 dev_err(&adapter->pdev->dev,
4214 "Unsupported Speed/Duplex configuration\n");
4215 return -EINVAL;
4216 }
4217 return 0;
4218}
4219
4220
4221static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
4222{
4223 struct net_device *netdev = pci_get_drvdata(pdev);
4224 struct igb_adapter *adapter = netdev_priv(netdev);
4225 struct e1000_hw *hw = &adapter->hw;
2d064c06 4226 u32 ctrl, rctl, status;
9d5c8243
AK		 4227 u32 wufc = adapter->wol;
4228#ifdef CONFIG_PM
4229 int retval = 0;
4230#endif
4231
4232 netif_device_detach(netdev);
4233
a88f10ec
AD		 4234 if (netif_running(netdev))
4235 igb_close(netdev);
4236
4237 igb_reset_interrupt_capability(adapter);
4238
4239 igb_free_queues(adapter);
9d5c8243
AK		 4240
4241#ifdef CONFIG_PM
4242 retval = pci_save_state(pdev);
4243 if (retval)
4244 return retval;
4245#endif
4246
4247 status = rd32(E1000_STATUS);
4248 if (status & E1000_STATUS_LU)
4249 wufc &= ~E1000_WUFC_LNKC;
4250
4251 if (wufc) {
4252 igb_setup_rctl(adapter);
4253 igb_set_multi(netdev);
4254
4255 /* turn on all-multi mode if wake on multicast is enabled */
4256 if (wufc & E1000_WUFC_MC) {
4257 rctl = rd32(E1000_RCTL);
4258 rctl |= E1000_RCTL_MPE;
4259 wr32(E1000_RCTL, rctl);
4260 }
4261
4262 ctrl = rd32(E1000_CTRL);
4263 /* advertise wake from D3Cold */
4264 #define E1000_CTRL_ADVD3WUC 0x00100000
4265 /* phy power management enable */
4266 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
4267 ctrl |= E1000_CTRL_ADVD3WUC;
4268 wr32(E1000_CTRL, ctrl);
4269
9d5c8243
AK		 4270 /* Allow time for pending master requests to run */
4271 igb_disable_pcie_master(&adapter->hw);
4272
4273 wr32(E1000_WUC, E1000_WUC_PME_EN);
4274 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 4275 } else {
4276 wr32(E1000_WUC, 0);
4277 wr32(E1000_WUFC, 0);
9d5c8243
AK		 4278 }
4279
2d064c06
AD		 4280 /* make sure adapter isn't asleep if manageability/wol is enabled */
4281 if (wufc || adapter->en_mng_pt) {
9d5c8243
AK		 4282 pci_enable_wake(pdev, PCI_D3hot, 1);
4283 pci_enable_wake(pdev, PCI_D3cold, 1);
2d064c06
AD		 4284 } else {
4285 igb_shutdown_fiber_serdes_link_82575(hw);
4286 pci_enable_wake(pdev, PCI_D3hot, 0);
4287 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243
AK		 4288 }
4289
4290 /* Release control of h/w to f/w. If f/w is AMT enabled, this
4291 * would have already happened in close and is redundant. */
4292 igb_release_hw_control(adapter);
4293
4294 pci_disable_device(pdev);
4295
4296 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4297
4298 return 0;
4299}
4300
4301#ifdef CONFIG_PM
4302static int igb_resume(struct pci_dev *pdev)
4303{
4304 struct net_device *netdev = pci_get_drvdata(pdev);
4305 struct igb_adapter *adapter = netdev_priv(netdev);
4306 struct e1000_hw *hw = &adapter->hw;
4307 u32 err;
4308
4309 pci_set_power_state(pdev, PCI_D0);
4310 pci_restore_state(pdev);
42bfd33a
TI		 4311
4312 if (adapter->need_ioport)
4313 err = pci_enable_device(pdev);
4314 else
4315 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 4316 if (err) {
4317 dev_err(&pdev->dev,
4318 "igb: Cannot enable PCI device from suspend\n");
4319 return err;
4320 }
4321 pci_set_master(pdev);
4322
4323 pci_enable_wake(pdev, PCI_D3hot, 0);
4324 pci_enable_wake(pdev, PCI_D3cold, 0);
4325
a88f10ec
AD		 4326 igb_set_interrupt_capability(adapter);
4327
4328 if (igb_alloc_queues(adapter)) {
4329 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
4330 return -ENOMEM;
9d5c8243
AK		 4331 }
4332
4333 /* e1000_power_up_phy(adapter); */
4334
4335 igb_reset(adapter);
4336 wr32(E1000_WUS, ~0);
4337
a88f10ec
AD		 4338 if (netif_running(netdev)) {
4339 err = igb_open(netdev);
4340 if (err)
4341 return err;
4342 }
9d5c8243
AK		 4343
4344 netif_device_attach(netdev);
4345
4346 /* let the f/w know that the h/w is now under the control of the
4347 * driver. */
4348 igb_get_hw_control(adapter);
4349
4350 return 0;
4351}
4352#endif
4353
4354static void igb_shutdown(struct pci_dev *pdev)
4355{
4356 igb_suspend(pdev, PMSG_SUSPEND);
4357}
4358
4359#ifdef CONFIG_NET_POLL_CONTROLLER
4360/*
4361 * Polling 'interrupt' - used by things like netconsole to send skbs
4362 * without having to re-enable interrupts. It's not called while
4363 * the interrupt routine is executing.
4364 */
4365static void igb_netpoll(struct net_device *netdev)
4366{
4367 struct igb_adapter *adapter = netdev_priv(netdev);
4368 int i;
4369 int work_done = 0;
4370
4371 igb_irq_disable(adapter);
7dfc16fa
AD		 4372 adapter->flags |= IGB_FLAG_IN_NETPOLL;
4373
9d5c8243 4374 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 4375 igb_clean_tx_irq(&adapter->tx_ring[i]);
9d5c8243
AK		 4376
4377 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 4378 igb_clean_rx_irq_adv(&adapter->rx_ring[i],
9d5c8243
AK		 4379 &work_done,
4380 adapter->rx_ring[i].napi.weight);
4381
7dfc16fa 4382 adapter->flags &= ~IGB_FLAG_IN_NETPOLL;
9d5c8243
AK		 4383 igb_irq_enable(adapter);
4384}
4385#endif /* CONFIG_NET_POLL_CONTROLLER */
4386
4387/**
4388 * igb_io_error_detected - called when PCI error is detected
4389 * @pdev: Pointer to PCI device
4390 * @state: The current pci connection state
4391 *
4392 * This function is called after a PCI bus error affecting
4393 * this device has been detected.
4394 */
4395static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
4396 pci_channel_state_t state)
4397{
4398 struct net_device *netdev = pci_get_drvdata(pdev);
4399 struct igb_adapter *adapter = netdev_priv(netdev);
4400
4401 netif_device_detach(netdev);
4402
4403 if (netif_running(netdev))
4404 igb_down(adapter);
4405 pci_disable_device(pdev);
4406
4407 /* Request a slot slot reset. */
4408 return PCI_ERS_RESULT_NEED_RESET;
4409}
4410
4411/**
4412 * igb_io_slot_reset - called after the pci bus has been reset.
4413 * @pdev: Pointer to PCI device
4414 *
4415 * Restart the card from scratch, as if from a cold-boot. Implementation
4416 * resembles the first-half of the igb_resume routine.
4417 */
4418static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
4419{
4420 struct net_device *netdev = pci_get_drvdata(pdev);
4421 struct igb_adapter *adapter = netdev_priv(netdev);
4422 struct e1000_hw *hw = &adapter->hw;
40a914fa 4423 pci_ers_result_t result;
42bfd33a 4424 int err;
9d5c8243 4425
42bfd33a
TI		 4426 if (adapter->need_ioport)
4427 err = pci_enable_device(pdev);
4428 else
4429 err = pci_enable_device_mem(pdev);
40a914fa 4430
42bfd33a 4431 if (err) {
9d5c8243
AK		 4432 dev_err(&pdev->dev,
4433 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 4434 result = PCI_ERS_RESULT_DISCONNECT;
4435 } else {
4436 pci_set_master(pdev);
4437 pci_restore_state(pdev);
9d5c8243 4438
40a914fa
AD		 4439 pci_enable_wake(pdev, PCI_D3hot, 0);
4440 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 4441
40a914fa
AD		 4442 igb_reset(adapter);
4443 wr32(E1000_WUS, ~0);
4444 result = PCI_ERS_RESULT_RECOVERED;
4445 }
9d5c8243 4446
ea943d41
JK		 4447 err = pci_cleanup_aer_uncorrect_error_status(pdev);
4448 if (err) {
4449 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
4450 "failed 0x%0x\n", err);
4451 /* non-fatal, continue */
4452 }
40a914fa
AD		 4453
4454 return result;
9d5c8243
AK		 4455}
4456
4457/**
4458 * igb_io_resume - called when traffic can start flowing again.
4459 * @pdev: Pointer to PCI device
4460 *
4461 * This callback is called when the error recovery driver tells us that
4462 * its OK to resume normal operation. Implementation resembles the
4463 * second-half of the igb_resume routine.
4464 */
4465static void igb_io_resume(struct pci_dev *pdev)
4466{
4467 struct net_device *netdev = pci_get_drvdata(pdev);
4468 struct igb_adapter *adapter = netdev_priv(netdev);
4469
9d5c8243
AK		 4470 if (netif_running(netdev)) {
4471 if (igb_up(adapter)) {
4472 dev_err(&pdev->dev, "igb_up failed after reset\n");
4473 return;
4474 }
4475 }
4476
4477 netif_device_attach(netdev);
4478
4479 /* let the f/w know that the h/w is now under the control of the
4480 * driver. */
4481 igb_get_hw_control(adapter);
9d5c8243
AK		 4482}
4483
4484/* igb_main.c */
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