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igb: remove disable_av variable from mac_info struct
[mirror_ubuntu-zesty-kernel.git] / drivers / net / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/module.h>
29#include <linux/types.h>
30#include <linux/init.h>
31#include <linux/vmalloc.h>
32#include <linux/pagemap.h>
33#include <linux/netdevice.h>
9d5c8243
AK		 34#include <linux/ipv6.h>
35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
37#include <linux/mii.h>
38#include <linux/ethtool.h>
39#include <linux/if_vlan.h>
40#include <linux/pci.h>
c54106bb 41#include <linux/pci-aspm.h>
9d5c8243
AK		 42#include <linux/delay.h>
43#include <linux/interrupt.h>
44#include <linux/if_ether.h>
40a914fa 45#include <linux/aer.h>
421e02f0 46#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 47#include <linux/dca.h>
48#endif
9d5c8243
AK		 49#include "igb.h"
50
0024fd00 51#define DRV_VERSION "1.2.45-k2"
9d5c8243
AK		 52char igb_driver_name[] = "igb";
53char igb_driver_version[] = DRV_VERSION;
54static const char igb_driver_string[] =
55 "Intel(R) Gigabit Ethernet Network Driver";
2d064c06 56static const char igb_copyright[] = "Copyright (c) 2008 Intel Corporation.";
9d5c8243 57
9d5c8243
AK		 58static const struct e1000_info *igb_info_tbl[] = {
59 [board_82575] = &e1000_82575_info,
60};
61
62static struct pci_device_id igb_pci_tbl[] = {
2d064c06
AD		 63 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
9d5c8243
AK		 66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
69 /* required last entry */
70 {0, }
71};
72
73MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
74
75void igb_reset(struct igb_adapter *);
76static int igb_setup_all_tx_resources(struct igb_adapter *);
77static int igb_setup_all_rx_resources(struct igb_adapter *);
78static void igb_free_all_tx_resources(struct igb_adapter *);
79static void igb_free_all_rx_resources(struct igb_adapter *);
9d5c8243
AK		 80void igb_update_stats(struct igb_adapter *);
81static int igb_probe(struct pci_dev *, const struct pci_device_id *);
82static void __devexit igb_remove(struct pci_dev *pdev);
83static int igb_sw_init(struct igb_adapter *);
84static int igb_open(struct net_device *);
85static int igb_close(struct net_device *);
86static void igb_configure_tx(struct igb_adapter *);
87static void igb_configure_rx(struct igb_adapter *);
88static void igb_setup_rctl(struct igb_adapter *);
89static void igb_clean_all_tx_rings(struct igb_adapter *);
90static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 91static void igb_clean_tx_ring(struct igb_ring *);
92static void igb_clean_rx_ring(struct igb_ring *);
9d5c8243
AK		 93static void igb_set_multi(struct net_device *);
94static void igb_update_phy_info(unsigned long);
95static void igb_watchdog(unsigned long);
96static void igb_watchdog_task(struct work_struct *);
97static int igb_xmit_frame_ring_adv(struct sk_buff *, struct net_device *,
98 struct igb_ring *);
99static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
100static struct net_device_stats *igb_get_stats(struct net_device *);
101static int igb_change_mtu(struct net_device *, int);
102static int igb_set_mac(struct net_device *, void *);
103static irqreturn_t igb_intr(int irq, void *);
104static irqreturn_t igb_intr_msi(int irq, void *);
105static irqreturn_t igb_msix_other(int irq, void *);
106static irqreturn_t igb_msix_rx(int irq, void *);
107static irqreturn_t igb_msix_tx(int irq, void *);
108static int igb_clean_rx_ring_msix(struct napi_struct *, int);
421e02f0 109#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 110static void igb_update_rx_dca(struct igb_ring *);
111static void igb_update_tx_dca(struct igb_ring *);
112static void igb_setup_dca(struct igb_adapter *);
421e02f0 113#endif /* CONFIG_IGB_DCA */
3b644cf6 114static bool igb_clean_tx_irq(struct igb_ring *);
661086df 115static int igb_poll(struct napi_struct *, int);
3b644cf6
MW		 116static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int);
117static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
9d5c8243
AK		 118static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
119static void igb_tx_timeout(struct net_device *);
120static void igb_reset_task(struct work_struct *);
121static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
122static void igb_vlan_rx_add_vid(struct net_device *, u16);
123static void igb_vlan_rx_kill_vid(struct net_device *, u16);
124static void igb_restore_vlan(struct igb_adapter *);
125
126static int igb_suspend(struct pci_dev *, pm_message_t);
127#ifdef CONFIG_PM
128static int igb_resume(struct pci_dev *);
129#endif
130static void igb_shutdown(struct pci_dev *);
421e02f0 131#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 132static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
133static struct notifier_block dca_notifier = {
134 .notifier_call = igb_notify_dca,
135 .next = NULL,
136 .priority = 0
137};
138#endif
9d5c8243
AK		 139
140#ifdef CONFIG_NET_POLL_CONTROLLER
141/* for netdump / net console */
142static void igb_netpoll(struct net_device *);
143#endif
144
145static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
146 pci_channel_state_t);
147static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
148static void igb_io_resume(struct pci_dev *);
149
150static struct pci_error_handlers igb_err_handler = {
151 .error_detected = igb_io_error_detected,
152 .slot_reset = igb_io_slot_reset,
153 .resume = igb_io_resume,
154};
155
156
157static struct pci_driver igb_driver = {
158 .name = igb_driver_name,
159 .id_table = igb_pci_tbl,
160 .probe = igb_probe,
161 .remove = __devexit_p(igb_remove),
162#ifdef CONFIG_PM
163 /* Power Managment Hooks */
164 .suspend = igb_suspend,
165 .resume = igb_resume,
166#endif
167 .shutdown = igb_shutdown,
168 .err_handler = &igb_err_handler
169};
170
7dfc16fa
AD		 171static int global_quad_port_a; /* global quad port a indication */
172
9d5c8243
AK		 173MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
174MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
175MODULE_LICENSE("GPL");
176MODULE_VERSION(DRV_VERSION);
177
178#ifdef DEBUG
179/**
180 * igb_get_hw_dev_name - return device name string
181 * used by hardware layer to print debugging information
182 **/
183char *igb_get_hw_dev_name(struct e1000_hw *hw)
184{
185 struct igb_adapter *adapter = hw->back;
186 return adapter->netdev->name;
187}
188#endif
189
190/**
191 * igb_init_module - Driver Registration Routine
192 *
193 * igb_init_module is the first routine called when the driver is
194 * loaded. All it does is register with the PCI subsystem.
195 **/
196static int __init igb_init_module(void)
197{
198 int ret;
199 printk(KERN_INFO "%s - version %s\n",
200 igb_driver_string, igb_driver_version);
201
202 printk(KERN_INFO "%s\n", igb_copyright);
203
7dfc16fa
AD		 204 global_quad_port_a = 0;
205
421e02f0 206#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 207 dca_register_notify(&dca_notifier);
208#endif
bbd98fe4
AD		 209
210 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 211 return ret;
212}
213
214module_init(igb_init_module);
215
216/**
217 * igb_exit_module - Driver Exit Cleanup Routine
218 *
219 * igb_exit_module is called just before the driver is removed
220 * from memory.
221 **/
222static void __exit igb_exit_module(void)
223{
421e02f0 224#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 225 dca_unregister_notify(&dca_notifier);
226#endif
9d5c8243
AK		 227 pci_unregister_driver(&igb_driver);
228}
229
230module_exit(igb_exit_module);
231
26bc19ec
AD		 232#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
233/**
234 * igb_cache_ring_register - Descriptor ring to register mapping
235 * @adapter: board private structure to initialize
236 *
237 * Once we know the feature-set enabled for the device, we'll cache
238 * the register offset the descriptor ring is assigned to.
239 **/
240static void igb_cache_ring_register(struct igb_adapter *adapter)
241{
242 int i;
243
244 switch (adapter->hw.mac.type) {
245 case e1000_82576:
246 /* The queues are allocated for virtualization such that VF 0
247 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
248 * In order to avoid collision we start at the first free queue
249 * and continue consuming queues in the same sequence
250 */
251 for (i = 0; i < adapter->num_rx_queues; i++)
252 adapter->rx_ring[i].reg_idx = Q_IDX_82576(i);
253 for (i = 0; i < adapter->num_tx_queues; i++)
254 adapter->tx_ring[i].reg_idx = Q_IDX_82576(i);
255 break;
256 case e1000_82575:
257 default:
258 for (i = 0; i < adapter->num_rx_queues; i++)
259 adapter->rx_ring[i].reg_idx = i;
260 for (i = 0; i < adapter->num_tx_queues; i++)
261 adapter->tx_ring[i].reg_idx = i;
262 break;
263 }
264}
265
9d5c8243
AK		 266/**
267 * igb_alloc_queues - Allocate memory for all rings
268 * @adapter: board private structure to initialize
269 *
270 * We allocate one ring per queue at run-time since we don't know the
271 * number of queues at compile-time.
272 **/
273static int igb_alloc_queues(struct igb_adapter *adapter)
274{
275 int i;
276
277 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
278 sizeof(struct igb_ring), GFP_KERNEL);
279 if (!adapter->tx_ring)
280 return -ENOMEM;
281
282 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
283 sizeof(struct igb_ring), GFP_KERNEL);
284 if (!adapter->rx_ring) {
285 kfree(adapter->tx_ring);
286 return -ENOMEM;
287 }
288
6eb5a7f1
AD		 289 adapter->rx_ring->buddy = adapter->tx_ring;
290
661086df
PWJ		 291 for (i = 0; i < adapter->num_tx_queues; i++) {
292 struct igb_ring *ring = &(adapter->tx_ring[i]);
68fd9910 293 ring->count = adapter->tx_ring_count;
661086df
PWJ		 294 ring->adapter = adapter;
295 ring->queue_index = i;
296 }
9d5c8243
AK		 297 for (i = 0; i < adapter->num_rx_queues; i++) {
298 struct igb_ring *ring = &(adapter->rx_ring[i]);
68fd9910 299 ring->count = adapter->rx_ring_count;
9d5c8243 300 ring->adapter = adapter;
844290e5 301 ring->queue_index = i;
9d5c8243
AK		 302 ring->itr_register = E1000_ITR;
303
844290e5 304 /* set a default napi handler for each rx_ring */
661086df 305 netif_napi_add(adapter->netdev, &ring->napi, igb_poll, 64);
9d5c8243 306 }
26bc19ec
AD		 307
308 igb_cache_ring_register(adapter);
9d5c8243
AK		 309 return 0;
310}
311
a88f10ec
AD		 312static void igb_free_queues(struct igb_adapter *adapter)
313{
314 int i;
315
316 for (i = 0; i < adapter->num_rx_queues; i++)
317 netif_napi_del(&adapter->rx_ring[i].napi);
318
319 kfree(adapter->tx_ring);
320 kfree(adapter->rx_ring);
321}
322
9d5c8243
AK		 323#define IGB_N0_QUEUE -1
324static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
325 int tx_queue, int msix_vector)
326{
327 u32 msixbm = 0;
328 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 329 u32 ivar, index;
330
331 switch (hw->mac.type) {
332 case e1000_82575:
9d5c8243
AK		 333 /* The 82575 assigns vectors using a bitmask, which matches the
334 bitmask for the EICR/EIMS/EIMC registers. To assign one
335 or more queues to a vector, we write the appropriate bits
336 into the MSIXBM register for that vector. */
337 if (rx_queue > IGB_N0_QUEUE) {
338 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
339 adapter->rx_ring[rx_queue].eims_value = msixbm;
340 }
341 if (tx_queue > IGB_N0_QUEUE) {
342 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
343 adapter->tx_ring[tx_queue].eims_value =
344 E1000_EICR_TX_QUEUE0 << tx_queue;
345 }
346 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
2d064c06
AD		 347 break;
348 case e1000_82576:
26bc19ec 349 /* 82576 uses a table-based method for assigning vectors.
2d064c06
AD		 350 Each queue has a single entry in the table to which we write
351 a vector number along with a "valid" bit. Sadly, the layout
352 of the table is somewhat counterintuitive. */
353 if (rx_queue > IGB_N0_QUEUE) {
26bc19ec 354 index = (rx_queue >> 1);
2d064c06 355 ivar = array_rd32(E1000_IVAR0, index);
26bc19ec 356 if (rx_queue & 0x1) {
2d064c06
AD		 357 /* vector goes into third byte of register */
358 ivar = ivar & 0xFF00FFFF;
359 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
26bc19ec
AD		 360 } else {
361 /* vector goes into low byte of register */
362 ivar = ivar & 0xFFFFFF00;
363 ivar |= msix_vector | E1000_IVAR_VALID;
2d064c06
AD		 364 }
365 adapter->rx_ring[rx_queue].eims_value= 1 << msix_vector;
366 array_wr32(E1000_IVAR0, index, ivar);
367 }
368 if (tx_queue > IGB_N0_QUEUE) {
26bc19ec 369 index = (tx_queue >> 1);
2d064c06 370 ivar = array_rd32(E1000_IVAR0, index);
26bc19ec 371 if (tx_queue & 0x1) {
2d064c06
AD		 372 /* vector goes into high byte of register */
373 ivar = ivar & 0x00FFFFFF;
374 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
26bc19ec
AD		 375 } else {
376 /* vector goes into second byte of register */
377 ivar = ivar & 0xFFFF00FF;
378 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
2d064c06
AD		 379 }
380 adapter->tx_ring[tx_queue].eims_value= 1 << msix_vector;
381 array_wr32(E1000_IVAR0, index, ivar);
382 }
383 break;
384 default:
385 BUG();
386 break;
387 }
9d5c8243
AK		 388}
389
390/**
391 * igb_configure_msix - Configure MSI-X hardware
392 *
393 * igb_configure_msix sets up the hardware to properly
394 * generate MSI-X interrupts.
395 **/
396static void igb_configure_msix(struct igb_adapter *adapter)
397{
398 u32 tmp;
399 int i, vector = 0;
400 struct e1000_hw *hw = &adapter->hw;
401
402 adapter->eims_enable_mask = 0;
2d064c06
AD		 403 if (hw->mac.type == e1000_82576)
404 /* Turn on MSI-X capability first, or our settings
405 * won't stick. And it will take days to debug. */
406 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
eebbbdba 407 E1000_GPIE_PBA | E1000_GPIE_EIAME |
2d064c06 408 E1000_GPIE_NSICR);
9d5c8243
AK		 409
410 for (i = 0; i < adapter->num_tx_queues; i++) {
411 struct igb_ring *tx_ring = &adapter->tx_ring[i];
412 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
413 adapter->eims_enable_mask |= tx_ring->eims_value;
414 if (tx_ring->itr_val)
6eb5a7f1 415 writel(tx_ring->itr_val,
9d5c8243
AK		 416 hw->hw_addr + tx_ring->itr_register);
417 else
418 writel(1, hw->hw_addr + tx_ring->itr_register);
419 }
420
421 for (i = 0; i < adapter->num_rx_queues; i++) {
422 struct igb_ring *rx_ring = &adapter->rx_ring[i];
25ac3c24 423 rx_ring->buddy = NULL;
9d5c8243
AK		 424 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
425 adapter->eims_enable_mask |= rx_ring->eims_value;
426 if (rx_ring->itr_val)
6eb5a7f1 427 writel(rx_ring->itr_val,
9d5c8243
AK		 428 hw->hw_addr + rx_ring->itr_register);
429 else
430 writel(1, hw->hw_addr + rx_ring->itr_register);
431 }
432
433
434 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 435 switch (hw->mac.type) {
436 case e1000_82575:
9d5c8243
AK		 437 array_wr32(E1000_MSIXBM(0), vector++,
438 E1000_EIMS_OTHER);
439
9d5c8243
AK		 440 tmp = rd32(E1000_CTRL_EXT);
441 /* enable MSI-X PBA support*/
442 tmp |= E1000_CTRL_EXT_PBA_CLR;
443
444 /* Auto-Mask interrupts upon ICR read. */
445 tmp |= E1000_CTRL_EXT_EIAME;
446 tmp |= E1000_CTRL_EXT_IRCA;
447
448 wr32(E1000_CTRL_EXT, tmp);
449 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
844290e5 450 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 451
2d064c06
AD		 452 break;
453
454 case e1000_82576:
455 tmp = (vector++ | E1000_IVAR_VALID) << 8;
456 wr32(E1000_IVAR_MISC, tmp);
457
458 adapter->eims_enable_mask = (1 << (vector)) - 1;
459 adapter->eims_other = 1 << (vector - 1);
460 break;
461 default:
462 /* do nothing, since nothing else supports MSI-X */
463 break;
464 } /* switch (hw->mac.type) */
9d5c8243
AK		 465 wrfl();
466}
467
468/**
469 * igb_request_msix - Initialize MSI-X interrupts
470 *
471 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
472 * kernel.
473 **/
474static int igb_request_msix(struct igb_adapter *adapter)
475{
476 struct net_device *netdev = adapter->netdev;
477 int i, err = 0, vector = 0;
478
479 vector = 0;
480
481 for (i = 0; i < adapter->num_tx_queues; i++) {
482 struct igb_ring *ring = &(adapter->tx_ring[i]);
cb7b48f6 483 sprintf(ring->name, "%s-tx-%d", netdev->name, i);
9d5c8243
AK		 484 err = request_irq(adapter->msix_entries[vector].vector,
485 &igb_msix_tx, 0, ring->name,
486 &(adapter->tx_ring[i]));
487 if (err)
488 goto out;
489 ring->itr_register = E1000_EITR(0) + (vector << 2);
6eb5a7f1 490 ring->itr_val = 976; /* ~4000 ints/sec */
9d5c8243
AK		 491 vector++;
492 }
493 for (i = 0; i < adapter->num_rx_queues; i++) {
494 struct igb_ring *ring = &(adapter->rx_ring[i]);
495 if (strlen(netdev->name) < (IFNAMSIZ - 5))
cb7b48f6 496 sprintf(ring->name, "%s-rx-%d", netdev->name, i);
9d5c8243
AK		 497 else
498 memcpy(ring->name, netdev->name, IFNAMSIZ);
499 err = request_irq(adapter->msix_entries[vector].vector,
500 &igb_msix_rx, 0, ring->name,
501 &(adapter->rx_ring[i]));
502 if (err)
503 goto out;
504 ring->itr_register = E1000_EITR(0) + (vector << 2);
505 ring->itr_val = adapter->itr;
844290e5
PW		 506 /* overwrite the poll routine for MSIX, we've already done
507 * netif_napi_add */
508 ring->napi.poll = &igb_clean_rx_ring_msix;
9d5c8243
AK		 509 vector++;
510 }
511
512 err = request_irq(adapter->msix_entries[vector].vector,
513 &igb_msix_other, 0, netdev->name, netdev);
514 if (err)
515 goto out;
516
9d5c8243
AK		 517 igb_configure_msix(adapter);
518 return 0;
519out:
520 return err;
521}
522
523static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
524{
525 if (adapter->msix_entries) {
526 pci_disable_msix(adapter->pdev);
527 kfree(adapter->msix_entries);
528 adapter->msix_entries = NULL;
7dfc16fa 529 } else if (adapter->flags & IGB_FLAG_HAS_MSI)
9d5c8243
AK		 530 pci_disable_msi(adapter->pdev);
531 return;
532}
533
534
535/**
536 * igb_set_interrupt_capability - set MSI or MSI-X if supported
537 *
538 * Attempt to configure interrupts using the best available
539 * capabilities of the hardware and kernel.
540 **/
541static void igb_set_interrupt_capability(struct igb_adapter *adapter)
542{
543 int err;
544 int numvecs, i;
545
83b7180d
AD		 546 /* Number of supported queues. */
547 /* Having more queues than CPUs doesn't make sense. */
548 adapter->num_rx_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
549 adapter->num_tx_queues = min_t(u32, IGB_MAX_TX_QUEUES, num_online_cpus());
550
9d5c8243
AK		 551 numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1;
552 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
553 GFP_KERNEL);
554 if (!adapter->msix_entries)
555 goto msi_only;
556
557 for (i = 0; i < numvecs; i++)
558 adapter->msix_entries[i].entry = i;
559
560 err = pci_enable_msix(adapter->pdev,
561 adapter->msix_entries,
562 numvecs);
563 if (err == 0)
34a20e89 564 goto out;
9d5c8243
AK		 565
566 igb_reset_interrupt_capability(adapter);
567
568 /* If we can't do MSI-X, try MSI */
569msi_only:
570 adapter->num_rx_queues = 1;
661086df 571 adapter->num_tx_queues = 1;
9d5c8243 572 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 573 adapter->flags |= IGB_FLAG_HAS_MSI;
34a20e89 574out:
661086df 575 /* Notify the stack of the (possibly) reduced Tx Queue count. */
fd2ea0a7 576 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
9d5c8243
AK		 577 return;
578}
579
580/**
581 * igb_request_irq - initialize interrupts
582 *
583 * Attempts to configure interrupts using the best available
584 * capabilities of the hardware and kernel.
585 **/
586static int igb_request_irq(struct igb_adapter *adapter)
587{
588 struct net_device *netdev = adapter->netdev;
589 struct e1000_hw *hw = &adapter->hw;
590 int err = 0;
591
592 if (adapter->msix_entries) {
593 err = igb_request_msix(adapter);
844290e5 594 if (!err)
9d5c8243 595 goto request_done;
9d5c8243
AK		 596 /* fall back to MSI */
597 igb_reset_interrupt_capability(adapter);
598 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 599 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 600 igb_free_all_tx_resources(adapter);
601 igb_free_all_rx_resources(adapter);
602 adapter->num_rx_queues = 1;
603 igb_alloc_queues(adapter);
844290e5 604 } else {
2d064c06
AD		 605 switch (hw->mac.type) {
606 case e1000_82575:
607 wr32(E1000_MSIXBM(0),
608 (E1000_EICR_RX_QUEUE0 | E1000_EIMS_OTHER));
609 break;
610 case e1000_82576:
611 wr32(E1000_IVAR0, E1000_IVAR_VALID);
612 break;
613 default:
614 break;
615 }
9d5c8243 616 }
844290e5 617
7dfc16fa 618 if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243
AK		 619 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
620 netdev->name, netdev);
621 if (!err)
622 goto request_done;
623 /* fall back to legacy interrupts */
624 igb_reset_interrupt_capability(adapter);
7dfc16fa 625 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 626 }
627
628 err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
629 netdev->name, netdev);
630
6cb5e577 631 if (err)
9d5c8243
AK		 632 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
633 err);
9d5c8243
AK		 634
635request_done:
636 return err;
637}
638
639static void igb_free_irq(struct igb_adapter *adapter)
640{
641 struct net_device *netdev = adapter->netdev;
642
643 if (adapter->msix_entries) {
644 int vector = 0, i;
645
646 for (i = 0; i < adapter->num_tx_queues; i++)
647 free_irq(adapter->msix_entries[vector++].vector,
648 &(adapter->tx_ring[i]));
649 for (i = 0; i < adapter->num_rx_queues; i++)
650 free_irq(adapter->msix_entries[vector++].vector,
651 &(adapter->rx_ring[i]));
652
653 free_irq(adapter->msix_entries[vector++].vector, netdev);
654 return;
655 }
656
657 free_irq(adapter->pdev->irq, netdev);
658}
659
660/**
661 * igb_irq_disable - Mask off interrupt generation on the NIC
662 * @adapter: board private structure
663 **/
664static void igb_irq_disable(struct igb_adapter *adapter)
665{
666 struct e1000_hw *hw = &adapter->hw;
667
668 if (adapter->msix_entries) {
844290e5 669 wr32(E1000_EIAM, 0);
9d5c8243
AK		 670 wr32(E1000_EIMC, ~0);
671 wr32(E1000_EIAC, 0);
672 }
844290e5
PW		 673
674 wr32(E1000_IAM, 0);
9d5c8243
AK		 675 wr32(E1000_IMC, ~0);
676 wrfl();
677 synchronize_irq(adapter->pdev->irq);
678}
679
680/**
681 * igb_irq_enable - Enable default interrupt generation settings
682 * @adapter: board private structure
683 **/
684static void igb_irq_enable(struct igb_adapter *adapter)
685{
686 struct e1000_hw *hw = &adapter->hw;
687
688 if (adapter->msix_entries) {
844290e5
PW		 689 wr32(E1000_EIAC, adapter->eims_enable_mask);
690 wr32(E1000_EIAM, adapter->eims_enable_mask);
691 wr32(E1000_EIMS, adapter->eims_enable_mask);
dda0e083 692 wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC);
844290e5
PW		 693 } else {
694 wr32(E1000_IMS, IMS_ENABLE_MASK);
695 wr32(E1000_IAM, IMS_ENABLE_MASK);
696 }
9d5c8243
AK		 697}
698
699static void igb_update_mng_vlan(struct igb_adapter *adapter)
700{
701 struct net_device *netdev = adapter->netdev;
702 u16 vid = adapter->hw.mng_cookie.vlan_id;
703 u16 old_vid = adapter->mng_vlan_id;
704 if (adapter->vlgrp) {
705 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
706 if (adapter->hw.mng_cookie.status &
707 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
708 igb_vlan_rx_add_vid(netdev, vid);
709 adapter->mng_vlan_id = vid;
710 } else
711 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
712
713 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
714 (vid != old_vid) &&
715 !vlan_group_get_device(adapter->vlgrp, old_vid))
716 igb_vlan_rx_kill_vid(netdev, old_vid);
717 } else
718 adapter->mng_vlan_id = vid;
719 }
720}
721
722/**
723 * igb_release_hw_control - release control of the h/w to f/w
724 * @adapter: address of board private structure
725 *
726 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
727 * For ASF and Pass Through versions of f/w this means that the
728 * driver is no longer loaded.
729 *
730 **/
731static void igb_release_hw_control(struct igb_adapter *adapter)
732{
733 struct e1000_hw *hw = &adapter->hw;
734 u32 ctrl_ext;
735
736 /* Let firmware take over control of h/w */
737 ctrl_ext = rd32(E1000_CTRL_EXT);
738 wr32(E1000_CTRL_EXT,
739 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
740}
741
742
743/**
744 * igb_get_hw_control - get control of the h/w from f/w
745 * @adapter: address of board private structure
746 *
747 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
748 * For ASF and Pass Through versions of f/w this means that
749 * the driver is loaded.
750 *
751 **/
752static void igb_get_hw_control(struct igb_adapter *adapter)
753{
754 struct e1000_hw *hw = &adapter->hw;
755 u32 ctrl_ext;
756
757 /* Let firmware know the driver has taken over */
758 ctrl_ext = rd32(E1000_CTRL_EXT);
759 wr32(E1000_CTRL_EXT,
760 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
761}
762
9d5c8243
AK		 763/**
764 * igb_configure - configure the hardware for RX and TX
765 * @adapter: private board structure
766 **/
767static void igb_configure(struct igb_adapter *adapter)
768{
769 struct net_device *netdev = adapter->netdev;
770 int i;
771
772 igb_get_hw_control(adapter);
773 igb_set_multi(netdev);
774
775 igb_restore_vlan(adapter);
9d5c8243
AK		 776
777 igb_configure_tx(adapter);
778 igb_setup_rctl(adapter);
779 igb_configure_rx(adapter);
662d7205
AD		 780
781 igb_rx_fifo_flush_82575(&adapter->hw);
782
9d5c8243
AK		 783 /* call IGB_DESC_UNUSED which always leaves
784 * at least 1 descriptor unused to make sure
785 * next_to_use != next_to_clean */
786 for (i = 0; i < adapter->num_rx_queues; i++) {
787 struct igb_ring *ring = &adapter->rx_ring[i];
3b644cf6 788 igb_alloc_rx_buffers_adv(ring, IGB_DESC_UNUSED(ring));
9d5c8243
AK		 789 }
790
791
792 adapter->tx_queue_len = netdev->tx_queue_len;
793}
794
795
796/**
797 * igb_up - Open the interface and prepare it to handle traffic
798 * @adapter: board private structure
799 **/
800
801int igb_up(struct igb_adapter *adapter)
802{
803 struct e1000_hw *hw = &adapter->hw;
804 int i;
805
806 /* hardware has been reset, we need to reload some things */
807 igb_configure(adapter);
808
809 clear_bit(__IGB_DOWN, &adapter->state);
810
844290e5
PW		 811 for (i = 0; i < adapter->num_rx_queues; i++)
812 napi_enable(&adapter->rx_ring[i].napi);
813 if (adapter->msix_entries)
9d5c8243 814 igb_configure_msix(adapter);
9d5c8243
AK		 815
816 /* Clear any pending interrupts. */
817 rd32(E1000_ICR);
818 igb_irq_enable(adapter);
819
820 /* Fire a link change interrupt to start the watchdog. */
821 wr32(E1000_ICS, E1000_ICS_LSC);
822 return 0;
823}
824
825void igb_down(struct igb_adapter *adapter)
826{
827 struct e1000_hw *hw = &adapter->hw;
828 struct net_device *netdev = adapter->netdev;
829 u32 tctl, rctl;
830 int i;
831
832 /* signal that we're down so the interrupt handler does not
833 * reschedule our watchdog timer */
834 set_bit(__IGB_DOWN, &adapter->state);
835
836 /* disable receives in the hardware */
837 rctl = rd32(E1000_RCTL);
838 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
839 /* flush and sleep below */
840
fd2ea0a7 841 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 842
843 /* disable transmits in the hardware */
844 tctl = rd32(E1000_TCTL);
845 tctl &= ~E1000_TCTL_EN;
846 wr32(E1000_TCTL, tctl);
847 /* flush both disables and wait for them to finish */
848 wrfl();
849 msleep(10);
850
844290e5
PW		 851 for (i = 0; i < adapter->num_rx_queues; i++)
852 napi_disable(&adapter->rx_ring[i].napi);
9d5c8243 853
9d5c8243
AK		 854 igb_irq_disable(adapter);
855
856 del_timer_sync(&adapter->watchdog_timer);
857 del_timer_sync(&adapter->phy_info_timer);
858
859 netdev->tx_queue_len = adapter->tx_queue_len;
860 netif_carrier_off(netdev);
861 adapter->link_speed = 0;
862 adapter->link_duplex = 0;
863
3023682e
JK		 864 if (!pci_channel_offline(adapter->pdev))
865 igb_reset(adapter);
9d5c8243
AK		 866 igb_clean_all_tx_rings(adapter);
867 igb_clean_all_rx_rings(adapter);
868}
869
870void igb_reinit_locked(struct igb_adapter *adapter)
871{
872 WARN_ON(in_interrupt());
873 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
874 msleep(1);
875 igb_down(adapter);
876 igb_up(adapter);
877 clear_bit(__IGB_RESETTING, &adapter->state);
878}
879
880void igb_reset(struct igb_adapter *adapter)
881{
882 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 883 struct e1000_mac_info *mac = &hw->mac;
884 struct e1000_fc_info *fc = &hw->fc;
9d5c8243
AK		 885 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
886 u16 hwm;
887
888 /* Repartition Pba for greater than 9k mtu
889 * To take effect CTRL.RST is required.
890 */
fa4dfae0
AD		 891 switch (mac->type) {
892 case e1000_82576:
2d064c06 893 pba = E1000_PBA_64K;
fa4dfae0
AD		 894 break;
895 case e1000_82575:
896 default:
897 pba = E1000_PBA_34K;
898 break;
2d064c06 899 }
9d5c8243 900
2d064c06
AD		 901 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
902 (mac->type < e1000_82576)) {
9d5c8243
AK		 903 /* adjust PBA for jumbo frames */
904 wr32(E1000_PBA, pba);
905
906 /* To maintain wire speed transmits, the Tx FIFO should be
907 * large enough to accommodate two full transmit packets,
908 * rounded up to the next 1KB and expressed in KB. Likewise,
909 * the Rx FIFO should be large enough to accommodate at least
910 * one full receive packet and is similarly rounded up and
911 * expressed in KB. */
912 pba = rd32(E1000_PBA);
913 /* upper 16 bits has Tx packet buffer allocation size in KB */
914 tx_space = pba >> 16;
915 /* lower 16 bits has Rx packet buffer allocation size in KB */
916 pba &= 0xffff;
917 /* the tx fifo also stores 16 bytes of information about the tx
918 * but don't include ethernet FCS because hardware appends it */
919 min_tx_space = (adapter->max_frame_size +
920 sizeof(struct e1000_tx_desc) -
921 ETH_FCS_LEN) * 2;
922 min_tx_space = ALIGN(min_tx_space, 1024);
923 min_tx_space >>= 10;
924 /* software strips receive CRC, so leave room for it */
925 min_rx_space = adapter->max_frame_size;
926 min_rx_space = ALIGN(min_rx_space, 1024);
927 min_rx_space >>= 10;
928
929 /* If current Tx allocation is less than the min Tx FIFO size,
930 * and the min Tx FIFO size is less than the current Rx FIFO
931 * allocation, take space away from current Rx allocation */
932 if (tx_space < min_tx_space &&
933 ((min_tx_space - tx_space) < pba)) {
934 pba = pba - (min_tx_space - tx_space);
935
936 /* if short on rx space, rx wins and must trump tx
937 * adjustment */
938 if (pba < min_rx_space)
939 pba = min_rx_space;
940 }
2d064c06 941 wr32(E1000_PBA, pba);
9d5c8243 942 }
9d5c8243
AK		 943
944 /* flow control settings */
945 /* The high water mark must be low enough to fit one full frame
946 * (or the size used for early receive) above it in the Rx FIFO.
947 * Set it to the lower of:
948 * - 90% of the Rx FIFO size, or
949 * - the full Rx FIFO size minus one full frame */
950 hwm = min(((pba << 10) * 9 / 10),
2d064c06 951 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 952
2d064c06
AD		 953 if (mac->type < e1000_82576) {
954 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
955 fc->low_water = fc->high_water - 8;
956 } else {
957 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
958 fc->low_water = fc->high_water - 16;
959 }
9d5c8243
AK		 960 fc->pause_time = 0xFFFF;
961 fc->send_xon = 1;
962 fc->type = fc->original_type;
963
964 /* Allow time for pending master requests to run */
965 adapter->hw.mac.ops.reset_hw(&adapter->hw);
966 wr32(E1000_WUC, 0);
967
968 if (adapter->hw.mac.ops.init_hw(&adapter->hw))
969 dev_err(&adapter->pdev->dev, "Hardware Error\n");
970
971 igb_update_mng_vlan(adapter);
972
973 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
974 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
975
976 igb_reset_adaptive(&adapter->hw);
f5f4cf08 977 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 978}
979
2e5c6922
SH		 980static const struct net_device_ops igb_netdev_ops = {
981 .ndo_open = igb_open,
982 .ndo_stop = igb_close,
00829823 983 .ndo_start_xmit = igb_xmit_frame_adv,
2e5c6922
SH		 984 .ndo_get_stats = igb_get_stats,
985 .ndo_set_multicast_list = igb_set_multi,
986 .ndo_set_mac_address = igb_set_mac,
987 .ndo_change_mtu = igb_change_mtu,
988 .ndo_do_ioctl = igb_ioctl,
989 .ndo_tx_timeout = igb_tx_timeout,
990 .ndo_validate_addr = eth_validate_addr,
991 .ndo_vlan_rx_register = igb_vlan_rx_register,
992 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
993 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
994#ifdef CONFIG_NET_POLL_CONTROLLER
995 .ndo_poll_controller = igb_netpoll,
996#endif
997};
998
9d5c8243
AK		 999/**
1000 * igb_probe - Device Initialization Routine
1001 * @pdev: PCI device information struct
1002 * @ent: entry in igb_pci_tbl
1003 *
1004 * Returns 0 on success, negative on failure
1005 *
1006 * igb_probe initializes an adapter identified by a pci_dev structure.
1007 * The OS initialization, configuring of the adapter private structure,
1008 * and a hardware reset occur.
1009 **/
1010static int __devinit igb_probe(struct pci_dev *pdev,
1011 const struct pci_device_id *ent)
1012{
1013 struct net_device *netdev;
1014 struct igb_adapter *adapter;
1015 struct e1000_hw *hw;
c54106bb 1016 struct pci_dev *us_dev;
9d5c8243
AK		 1017 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1018 unsigned long mmio_start, mmio_len;
c54106bb
AD		 1019 int i, err, pci_using_dac, pos;
1020 u16 eeprom_data = 0, state = 0;
9d5c8243
AK		 1021 u16 eeprom_apme_mask = IGB_EEPROM_APME;
1022 u32 part_num;
1023
aed5dec3 1024 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 1025 if (err)
1026 return err;
1027
1028 pci_using_dac = 0;
1029 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
1030 if (!err) {
1031 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1032 if (!err)
1033 pci_using_dac = 1;
1034 } else {
1035 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1036 if (err) {
1037 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1038 if (err) {
1039 dev_err(&pdev->dev, "No usable DMA "
1040 "configuration, aborting\n");
1041 goto err_dma;
1042 }
1043 }
1044 }
1045
c54106bb
AD		 1046 /* 82575 requires that the pci-e link partner disable the L0s state */
1047 switch (pdev->device) {
1048 case E1000_DEV_ID_82575EB_COPPER:
1049 case E1000_DEV_ID_82575EB_FIBER_SERDES:
1050 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1051 us_dev = pdev->bus->self;
1052 pos = pci_find_capability(us_dev, PCI_CAP_ID_EXP);
1053 if (pos) {
1054 pci_read_config_word(us_dev, pos + PCI_EXP_LNKCTL,
1055 &state);
1056 state &= ~PCIE_LINK_STATE_L0S;
1057 pci_write_config_word(us_dev, pos + PCI_EXP_LNKCTL,
1058 state);
ac450208
BH		 1059 dev_info(&pdev->dev,
1060 "Disabling ASPM L0s upstream switch port %s\n",
1061 pci_name(us_dev));
c54106bb
AD		 1062 }
1063 default:
1064 break;
1065 }
1066
aed5dec3
AD		 1067 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1068 IORESOURCE_MEM),
1069 igb_driver_name);
9d5c8243
AK		 1070 if (err)
1071 goto err_pci_reg;
1072
ea943d41
JK		 1073 err = pci_enable_pcie_error_reporting(pdev);
1074 if (err) {
1075 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
1076 "0x%x\n", err);
1077 /* non-fatal, continue */
1078 }
40a914fa 1079
9d5c8243 1080 pci_set_master(pdev);
c682fc23 1081 pci_save_state(pdev);
9d5c8243
AK		 1082
1083 err = -ENOMEM;
661086df 1084 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), IGB_MAX_TX_QUEUES);
9d5c8243
AK		 1085 if (!netdev)
1086 goto err_alloc_etherdev;
1087
1088 SET_NETDEV_DEV(netdev, &pdev->dev);
1089
1090 pci_set_drvdata(pdev, netdev);
1091 adapter = netdev_priv(netdev);
1092 adapter->netdev = netdev;
1093 adapter->pdev = pdev;
1094 hw = &adapter->hw;
1095 hw->back = adapter;
1096 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
1097
1098 mmio_start = pci_resource_start(pdev, 0);
1099 mmio_len = pci_resource_len(pdev, 0);
1100
1101 err = -EIO;
28b0759c
AD		 1102 hw->hw_addr = ioremap(mmio_start, mmio_len);
1103 if (!hw->hw_addr)
9d5c8243
AK		 1104 goto err_ioremap;
1105
2e5c6922 1106 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 1107 igb_set_ethtool_ops(netdev);
9d5c8243 1108 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 1109
1110 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1111
1112 netdev->mem_start = mmio_start;
1113 netdev->mem_end = mmio_start + mmio_len;
1114
9d5c8243
AK		 1115 /* PCI config space info */
1116 hw->vendor_id = pdev->vendor;
1117 hw->device_id = pdev->device;
1118 hw->revision_id = pdev->revision;
1119 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1120 hw->subsystem_device_id = pdev->subsystem_device;
1121
1122 /* setup the private structure */
1123 hw->back = adapter;
1124 /* Copy the default MAC, PHY and NVM function pointers */
1125 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1126 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1127 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1128 /* Initialize skew-specific constants */
1129 err = ei->get_invariants(hw);
1130 if (err)
1131 goto err_hw_init;
1132
1133 err = igb_sw_init(adapter);
1134 if (err)
1135 goto err_sw_init;
1136
1137 igb_get_bus_info_pcie(hw);
1138
7dfc16fa
AD		 1139 /* set flags */
1140 switch (hw->mac.type) {
7dfc16fa 1141 case e1000_82575:
7dfc16fa
AD		 1142 adapter->flags |= IGB_FLAG_NEED_CTX_IDX;
1143 break;
bbd98fe4 1144 case e1000_82576:
7dfc16fa
AD		 1145 default:
1146 break;
1147 }
1148
9d5c8243
AK		 1149 hw->phy.autoneg_wait_to_complete = false;
1150 hw->mac.adaptive_ifs = true;
1151
1152 /* Copper options */
1153 if (hw->phy.media_type == e1000_media_type_copper) {
1154 hw->phy.mdix = AUTO_ALL_MODES;
1155 hw->phy.disable_polarity_correction = false;
1156 hw->phy.ms_type = e1000_ms_hw_default;
1157 }
1158
1159 if (igb_check_reset_block(hw))
1160 dev_info(&pdev->dev,
1161 "PHY reset is blocked due to SOL/IDER session.\n");
1162
1163 netdev->features = NETIF_F_SG |
7d8eb29e 1164 NETIF_F_IP_CSUM |
9d5c8243
AK		 1165 NETIF_F_HW_VLAN_TX |
1166 NETIF_F_HW_VLAN_RX |
1167 NETIF_F_HW_VLAN_FILTER;
1168
7d8eb29e 1169 netdev->features |= NETIF_F_IPV6_CSUM;
9d5c8243 1170 netdev->features |= NETIF_F_TSO;
9d5c8243 1171 netdev->features |= NETIF_F_TSO6;
48f29ffc 1172
d3352520 1173#ifdef CONFIG_IGB_LRO
5c0999b7 1174 netdev->features |= NETIF_F_GRO;
d3352520
AD		 1175#endif
1176
48f29ffc
JK		 1177 netdev->vlan_features |= NETIF_F_TSO;
1178 netdev->vlan_features |= NETIF_F_TSO6;
7d8eb29e 1179 netdev->vlan_features |= NETIF_F_IP_CSUM;
48f29ffc
JK		 1180 netdev->vlan_features |= NETIF_F_SG;
1181
9d5c8243
AK		 1182 if (pci_using_dac)
1183 netdev->features |= NETIF_F_HIGHDMA;
1184
9d5c8243
AK		 1185 adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1186
1187 /* before reading the NVM, reset the controller to put the device in a
1188 * known good starting state */
1189 hw->mac.ops.reset_hw(hw);
1190
1191 /* make sure the NVM is good */
1192 if (igb_validate_nvm_checksum(hw) < 0) {
1193 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1194 err = -EIO;
1195 goto err_eeprom;
1196 }
1197
1198 /* copy the MAC address out of the NVM */
1199 if (hw->mac.ops.read_mac_addr(hw))
1200 dev_err(&pdev->dev, "NVM Read Error\n");
1201
1202 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1203 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1204
1205 if (!is_valid_ether_addr(netdev->perm_addr)) {
1206 dev_err(&pdev->dev, "Invalid MAC Address\n");
1207 err = -EIO;
1208 goto err_eeprom;
1209 }
1210
1211 init_timer(&adapter->watchdog_timer);
1212 adapter->watchdog_timer.function = &igb_watchdog;
1213 adapter->watchdog_timer.data = (unsigned long) adapter;
1214
1215 init_timer(&adapter->phy_info_timer);
1216 adapter->phy_info_timer.function = &igb_update_phy_info;
1217 adapter->phy_info_timer.data = (unsigned long) adapter;
1218
1219 INIT_WORK(&adapter->reset_task, igb_reset_task);
1220 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1221
1222 /* Initialize link & ring properties that are user-changeable */
1223 adapter->tx_ring->count = 256;
1224 for (i = 0; i < adapter->num_tx_queues; i++)
1225 adapter->tx_ring[i].count = adapter->tx_ring->count;
1226 adapter->rx_ring->count = 256;
1227 for (i = 0; i < adapter->num_rx_queues; i++)
1228 adapter->rx_ring[i].count = adapter->rx_ring->count;
1229
1230 adapter->fc_autoneg = true;
1231 hw->mac.autoneg = true;
1232 hw->phy.autoneg_advertised = 0x2f;
1233
1234 hw->fc.original_type = e1000_fc_default;
1235 hw->fc.type = e1000_fc_default;
1236
1237 adapter->itr_setting = 3;
1238 adapter->itr = IGB_START_ITR;
1239
1240 igb_validate_mdi_setting(hw);
1241
1242 adapter->rx_csum = 1;
1243
1244 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1245 * enable the ACPI Magic Packet filter
1246 */
1247
1248 if (hw->bus.func == 0 ||
1249 hw->device_id == E1000_DEV_ID_82575EB_COPPER)
312c75ae 1250 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
9d5c8243
AK		 1251
1252 if (eeprom_data & eeprom_apme_mask)
1253 adapter->eeprom_wol |= E1000_WUFC_MAG;
1254
1255 /* now that we have the eeprom settings, apply the special cases where
1256 * the eeprom may be wrong or the board simply won't support wake on
1257 * lan on a particular port */
1258 switch (pdev->device) {
1259 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1260 adapter->eeprom_wol = 0;
1261 break;
1262 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 1263 case E1000_DEV_ID_82576_FIBER:
1264 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 1265 /* Wake events only supported on port A for dual fiber
1266 * regardless of eeprom setting */
1267 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1268 adapter->eeprom_wol = 0;
1269 break;
1270 }
1271
1272 /* initialize the wol settings based on the eeprom settings */
1273 adapter->wol = adapter->eeprom_wol;
e1b86d84 1274 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
9d5c8243
AK		 1275
1276 /* reset the hardware with the new settings */
1277 igb_reset(adapter);
1278
1279 /* let the f/w know that the h/w is now under the control of the
1280 * driver. */
1281 igb_get_hw_control(adapter);
1282
1283 /* tell the stack to leave us alone until igb_open() is called */
1284 netif_carrier_off(netdev);
fd2ea0a7 1285 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1286
1287 strcpy(netdev->name, "eth%d");
1288 err = register_netdev(netdev);
1289 if (err)
1290 goto err_register;
1291
421e02f0 1292#ifdef CONFIG_IGB_DCA
bbd98fe4 1293 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 1294 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 1295 dev_info(&pdev->dev, "DCA enabled\n");
1296 /* Always use CB2 mode, difference is masked
1297 * in the CB driver. */
1298 wr32(E1000_DCA_CTRL, 2);
1299 igb_setup_dca(adapter);
1300 }
1301#endif
1302
9d5c8243
AK		 1303 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1304 /* print bus type/speed/width info */
7c510e4b 1305 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
9d5c8243
AK		 1306 netdev->name,
1307 ((hw->bus.speed == e1000_bus_speed_2500)
1308 ? "2.5Gb/s" : "unknown"),
1309 ((hw->bus.width == e1000_bus_width_pcie_x4)
1310 ? "Width x4" : (hw->bus.width == e1000_bus_width_pcie_x1)
1311 ? "Width x1" : "unknown"),
7c510e4b 1312 netdev->dev_addr);
9d5c8243
AK		 1313
1314 igb_read_part_num(hw, &part_num);
1315 dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1316 (part_num >> 8), (part_num & 0xff));
1317
1318 dev_info(&pdev->dev,
1319 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1320 adapter->msix_entries ? "MSI-X" :
7dfc16fa 1321 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243
AK		 1322 adapter->num_rx_queues, adapter->num_tx_queues);
1323
9d5c8243
AK		 1324 return 0;
1325
1326err_register:
1327 igb_release_hw_control(adapter);
1328err_eeprom:
1329 if (!igb_check_reset_block(hw))
f5f4cf08 1330 igb_reset_phy(hw);
9d5c8243
AK		 1331
1332 if (hw->flash_address)
1333 iounmap(hw->flash_address);
1334
a88f10ec 1335 igb_free_queues(adapter);
9d5c8243
AK		 1336err_sw_init:
1337err_hw_init:
1338 iounmap(hw->hw_addr);
1339err_ioremap:
1340 free_netdev(netdev);
1341err_alloc_etherdev:
aed5dec3
AD		 1342 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1343 IORESOURCE_MEM));
9d5c8243
AK		 1344err_pci_reg:
1345err_dma:
1346 pci_disable_device(pdev);
1347 return err;
1348}
1349
1350/**
1351 * igb_remove - Device Removal Routine
1352 * @pdev: PCI device information struct
1353 *
1354 * igb_remove is called by the PCI subsystem to alert the driver
1355 * that it should release a PCI device. The could be caused by a
1356 * Hot-Plug event, or because the driver is going to be removed from
1357 * memory.
1358 **/
1359static void __devexit igb_remove(struct pci_dev *pdev)
1360{
1361 struct net_device *netdev = pci_get_drvdata(pdev);
1362 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 1363 struct e1000_hw *hw = &adapter->hw;
ea943d41 1364 int err;
9d5c8243
AK		 1365
1366 /* flush_scheduled work may reschedule our watchdog task, so
1367 * explicitly disable watchdog tasks from being rescheduled */
1368 set_bit(__IGB_DOWN, &adapter->state);
1369 del_timer_sync(&adapter->watchdog_timer);
1370 del_timer_sync(&adapter->phy_info_timer);
1371
1372 flush_scheduled_work();
1373
421e02f0 1374#ifdef CONFIG_IGB_DCA
7dfc16fa 1375 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 1376 dev_info(&pdev->dev, "DCA disabled\n");
1377 dca_remove_requester(&pdev->dev);
7dfc16fa 1378 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 1379 wr32(E1000_DCA_CTRL, 1);
1380 }
1381#endif
1382
9d5c8243
AK		 1383 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1384 * would have already happened in close and is redundant. */
1385 igb_release_hw_control(adapter);
1386
1387 unregister_netdev(netdev);
1388
f5f4cf08
AD		 1389 if (!igb_check_reset_block(&adapter->hw))
1390 igb_reset_phy(&adapter->hw);
9d5c8243 1391
9d5c8243
AK		 1392 igb_reset_interrupt_capability(adapter);
1393
a88f10ec 1394 igb_free_queues(adapter);
9d5c8243 1395
28b0759c
AD		 1396 iounmap(hw->hw_addr);
1397 if (hw->flash_address)
1398 iounmap(hw->flash_address);
aed5dec3
AD		 1399 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1400 IORESOURCE_MEM));
9d5c8243
AK		 1401
1402 free_netdev(netdev);
1403
ea943d41
JK		 1404 err = pci_disable_pcie_error_reporting(pdev);
1405 if (err)
1406 dev_err(&pdev->dev,
1407 "pci_disable_pcie_error_reporting failed 0x%x\n", err);
40a914fa 1408
9d5c8243
AK		 1409 pci_disable_device(pdev);
1410}
1411
1412/**
1413 * igb_sw_init - Initialize general software structures (struct igb_adapter)
1414 * @adapter: board private structure to initialize
1415 *
1416 * igb_sw_init initializes the Adapter private data structure.
1417 * Fields are initialized based on PCI device information and
1418 * OS network device settings (MTU size).
1419 **/
1420static int __devinit igb_sw_init(struct igb_adapter *adapter)
1421{
1422 struct e1000_hw *hw = &adapter->hw;
1423 struct net_device *netdev = adapter->netdev;
1424 struct pci_dev *pdev = adapter->pdev;
1425
1426 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1427
68fd9910
AD		 1428 adapter->tx_ring_count = IGB_DEFAULT_TXD;
1429 adapter->rx_ring_count = IGB_DEFAULT_RXD;
9d5c8243
AK		 1430 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1431 adapter->rx_ps_hdr_size = 0; /* disable packet split */
1432 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1433 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1434
661086df
PWJ		 1435 /* This call may decrease the number of queues depending on
1436 * interrupt mode. */
9d5c8243
AK		 1437 igb_set_interrupt_capability(adapter);
1438
1439 if (igb_alloc_queues(adapter)) {
1440 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1441 return -ENOMEM;
1442 }
1443
1444 /* Explicitly disable IRQ since the NIC can be in any state. */
1445 igb_irq_disable(adapter);
1446
1447 set_bit(__IGB_DOWN, &adapter->state);
1448 return 0;
1449}
1450
1451/**
1452 * igb_open - Called when a network interface is made active
1453 * @netdev: network interface device structure
1454 *
1455 * Returns 0 on success, negative value on failure
1456 *
1457 * The open entry point is called when a network interface is made
1458 * active by the system (IFF_UP). At this point all resources needed
1459 * for transmit and receive operations are allocated, the interrupt
1460 * handler is registered with the OS, the watchdog timer is started,
1461 * and the stack is notified that the interface is ready.
1462 **/
1463static int igb_open(struct net_device *netdev)
1464{
1465 struct igb_adapter *adapter = netdev_priv(netdev);
1466 struct e1000_hw *hw = &adapter->hw;
1467 int err;
1468 int i;
1469
1470 /* disallow open during test */
1471 if (test_bit(__IGB_TESTING, &adapter->state))
1472 return -EBUSY;
1473
1474 /* allocate transmit descriptors */
1475 err = igb_setup_all_tx_resources(adapter);
1476 if (err)
1477 goto err_setup_tx;
1478
1479 /* allocate receive descriptors */
1480 err = igb_setup_all_rx_resources(adapter);
1481 if (err)
1482 goto err_setup_rx;
1483
1484 /* e1000_power_up_phy(adapter); */
1485
1486 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1487 if ((adapter->hw.mng_cookie.status &
1488 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1489 igb_update_mng_vlan(adapter);
1490
1491 /* before we allocate an interrupt, we must be ready to handle it.
1492 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1493 * as soon as we call pci_request_irq, so we have to setup our
1494 * clean_rx handler before we do so. */
1495 igb_configure(adapter);
1496
1497 err = igb_request_irq(adapter);
1498 if (err)
1499 goto err_req_irq;
1500
1501 /* From here on the code is the same as igb_up() */
1502 clear_bit(__IGB_DOWN, &adapter->state);
1503
844290e5
PW		 1504 for (i = 0; i < adapter->num_rx_queues; i++)
1505 napi_enable(&adapter->rx_ring[i].napi);
9d5c8243
AK		 1506
1507 /* Clear any pending interrupts. */
1508 rd32(E1000_ICR);
844290e5
PW		 1509
1510 igb_irq_enable(adapter);
1511
d55b53ff
JK		 1512 netif_tx_start_all_queues(netdev);
1513
9d5c8243
AK		 1514 /* Fire a link status change interrupt to start the watchdog. */
1515 wr32(E1000_ICS, E1000_ICS_LSC);
1516
1517 return 0;
1518
1519err_req_irq:
1520 igb_release_hw_control(adapter);
1521 /* e1000_power_down_phy(adapter); */
1522 igb_free_all_rx_resources(adapter);
1523err_setup_rx:
1524 igb_free_all_tx_resources(adapter);
1525err_setup_tx:
1526 igb_reset(adapter);
1527
1528 return err;
1529}
1530
1531/**
1532 * igb_close - Disables a network interface
1533 * @netdev: network interface device structure
1534 *
1535 * Returns 0, this is not allowed to fail
1536 *
1537 * The close entry point is called when an interface is de-activated
1538 * by the OS. The hardware is still under the driver's control, but
1539 * needs to be disabled. A global MAC reset is issued to stop the
1540 * hardware, and all transmit and receive resources are freed.
1541 **/
1542static int igb_close(struct net_device *netdev)
1543{
1544 struct igb_adapter *adapter = netdev_priv(netdev);
1545
1546 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1547 igb_down(adapter);
1548
1549 igb_free_irq(adapter);
1550
1551 igb_free_all_tx_resources(adapter);
1552 igb_free_all_rx_resources(adapter);
1553
1554 /* kill manageability vlan ID if supported, but not if a vlan with
1555 * the same ID is registered on the host OS (let 8021q kill it) */
1556 if ((adapter->hw.mng_cookie.status &
1557 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1558 !(adapter->vlgrp &&
1559 vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1560 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1561
1562 return 0;
1563}
1564
1565/**
1566 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
1567 * @adapter: board private structure
1568 * @tx_ring: tx descriptor ring (for a specific queue) to setup
1569 *
1570 * Return 0 on success, negative on failure
1571 **/
1572
1573int igb_setup_tx_resources(struct igb_adapter *adapter,
1574 struct igb_ring *tx_ring)
1575{
1576 struct pci_dev *pdev = adapter->pdev;
1577 int size;
1578
1579 size = sizeof(struct igb_buffer) * tx_ring->count;
1580 tx_ring->buffer_info = vmalloc(size);
1581 if (!tx_ring->buffer_info)
1582 goto err;
1583 memset(tx_ring->buffer_info, 0, size);
1584
1585 /* round up to nearest 4K */
0e014cb1 1586 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
9d5c8243
AK		 1587 tx_ring->size = ALIGN(tx_ring->size, 4096);
1588
1589 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1590 &tx_ring->dma);
1591
1592 if (!tx_ring->desc)
1593 goto err;
1594
1595 tx_ring->adapter = adapter;
1596 tx_ring->next_to_use = 0;
1597 tx_ring->next_to_clean = 0;
9d5c8243
AK		 1598 return 0;
1599
1600err:
1601 vfree(tx_ring->buffer_info);
1602 dev_err(&adapter->pdev->dev,
1603 "Unable to allocate memory for the transmit descriptor ring\n");
1604 return -ENOMEM;
1605}
1606
1607/**
1608 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1609 * (Descriptors) for all queues
1610 * @adapter: board private structure
1611 *
1612 * Return 0 on success, negative on failure
1613 **/
1614static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1615{
1616 int i, err = 0;
661086df 1617 int r_idx;
9d5c8243
AK		 1618
1619 for (i = 0; i < adapter->num_tx_queues; i++) {
1620 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1621 if (err) {
1622 dev_err(&adapter->pdev->dev,
1623 "Allocation for Tx Queue %u failed\n", i);
1624 for (i--; i >= 0; i--)
3b644cf6 1625 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 1626 break;
1627 }
1628 }
1629
661086df
PWJ		 1630 for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
1631 r_idx = i % adapter->num_tx_queues;
1632 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
eebbbdba 1633 }
9d5c8243
AK		 1634 return err;
1635}
1636
1637/**
1638 * igb_configure_tx - Configure transmit Unit after Reset
1639 * @adapter: board private structure
1640 *
1641 * Configure the Tx unit of the MAC after a reset.
1642 **/
1643static void igb_configure_tx(struct igb_adapter *adapter)
1644{
0e014cb1 1645 u64 tdba;
9d5c8243
AK		 1646 struct e1000_hw *hw = &adapter->hw;
1647 u32 tctl;
1648 u32 txdctl, txctrl;
26bc19ec 1649 int i, j;
9d5c8243
AK		 1650
1651 for (i = 0; i < adapter->num_tx_queues; i++) {
1652 struct igb_ring *ring = &(adapter->tx_ring[i]);
26bc19ec
AD		 1653 j = ring->reg_idx;
1654 wr32(E1000_TDLEN(j),
9d5c8243
AK		 1655 ring->count * sizeof(struct e1000_tx_desc));
1656 tdba = ring->dma;
26bc19ec 1657 wr32(E1000_TDBAL(j),
9d5c8243 1658 tdba & 0x00000000ffffffffULL);
26bc19ec 1659 wr32(E1000_TDBAH(j), tdba >> 32);
9d5c8243 1660
26bc19ec
AD		 1661 ring->head = E1000_TDH(j);
1662 ring->tail = E1000_TDT(j);
9d5c8243
AK		 1663 writel(0, hw->hw_addr + ring->tail);
1664 writel(0, hw->hw_addr + ring->head);
26bc19ec 1665 txdctl = rd32(E1000_TXDCTL(j));
9d5c8243 1666 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
26bc19ec 1667 wr32(E1000_TXDCTL(j), txdctl);
9d5c8243
AK		 1668
1669 /* Turn off Relaxed Ordering on head write-backs. The
1670 * writebacks MUST be delivered in order or it will
1671 * completely screw up our bookeeping.
1672 */
26bc19ec 1673 txctrl = rd32(E1000_DCA_TXCTRL(j));
9d5c8243 1674 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
26bc19ec 1675 wr32(E1000_DCA_TXCTRL(j), txctrl);
9d5c8243
AK		 1676 }
1677
1678
1679
1680 /* Use the default values for the Tx Inter Packet Gap (IPG) timer */
1681
1682 /* Program the Transmit Control Register */
1683
1684 tctl = rd32(E1000_TCTL);
1685 tctl &= ~E1000_TCTL_CT;
1686 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1687 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1688
1689 igb_config_collision_dist(hw);
1690
1691 /* Setup Transmit Descriptor Settings for eop descriptor */
1692 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
1693
1694 /* Enable transmits */
1695 tctl |= E1000_TCTL_EN;
1696
1697 wr32(E1000_TCTL, tctl);
1698}
1699
1700/**
1701 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
1702 * @adapter: board private structure
1703 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1704 *
1705 * Returns 0 on success, negative on failure
1706 **/
1707
1708int igb_setup_rx_resources(struct igb_adapter *adapter,
1709 struct igb_ring *rx_ring)
1710{
1711 struct pci_dev *pdev = adapter->pdev;
1712 int size, desc_len;
1713
1714 size = sizeof(struct igb_buffer) * rx_ring->count;
1715 rx_ring->buffer_info = vmalloc(size);
1716 if (!rx_ring->buffer_info)
1717 goto err;
1718 memset(rx_ring->buffer_info, 0, size);
1719
1720 desc_len = sizeof(union e1000_adv_rx_desc);
1721
1722 /* Round up to nearest 4K */
1723 rx_ring->size = rx_ring->count * desc_len;
1724 rx_ring->size = ALIGN(rx_ring->size, 4096);
1725
1726 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1727 &rx_ring->dma);
1728
1729 if (!rx_ring->desc)
1730 goto err;
1731
1732 rx_ring->next_to_clean = 0;
1733 rx_ring->next_to_use = 0;
9d5c8243
AK		 1734
1735 rx_ring->adapter = adapter;
9d5c8243
AK		 1736
1737 return 0;
1738
1739err:
1740 vfree(rx_ring->buffer_info);
1741 dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
1742 "the receive descriptor ring\n");
1743 return -ENOMEM;
1744}
1745
1746/**
1747 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
1748 * (Descriptors) for all queues
1749 * @adapter: board private structure
1750 *
1751 * Return 0 on success, negative on failure
1752 **/
1753static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
1754{
1755 int i, err = 0;
1756
1757 for (i = 0; i < adapter->num_rx_queues; i++) {
1758 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1759 if (err) {
1760 dev_err(&adapter->pdev->dev,
1761 "Allocation for Rx Queue %u failed\n", i);
1762 for (i--; i >= 0; i--)
3b644cf6 1763 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 1764 break;
1765 }
1766 }
1767
1768 return err;
1769}
1770
1771/**
1772 * igb_setup_rctl - configure the receive control registers
1773 * @adapter: Board private structure
1774 **/
1775static void igb_setup_rctl(struct igb_adapter *adapter)
1776{
1777 struct e1000_hw *hw = &adapter->hw;
1778 u32 rctl;
1779 u32 srrctl = 0;
26bc19ec 1780 int i, j;
9d5c8243
AK		 1781
1782 rctl = rd32(E1000_RCTL);
1783
1784 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 1785 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 1786
69d728ba 1787 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 1788 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 1789
87cb7e8c
AK		 1790 /*
1791 * enable stripping of CRC. It's unlikely this will break BMC
1792 * redirection as it did with e1000. Newer features require
1793 * that the HW strips the CRC.
9d5c8243 1794 */
87cb7e8c 1795 rctl |= E1000_RCTL_SECRC;
9d5c8243 1796
9b07f3d3 1797 /*
ec54d7d6 1798 * disable store bad packets and clear size bits.
9b07f3d3 1799 */
ec54d7d6 1800 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 1801
ec54d7d6 1802 /* enable LPE when to prevent packets larger than max_frame_size */
9b07f3d3 1803 rctl |= E1000_RCTL_LPE;
b4557be2
AD		 1804
1805 /* Setup buffer sizes */
1806 switch (adapter->rx_buffer_len) {
1807 case IGB_RXBUFFER_256:
1808 rctl |= E1000_RCTL_SZ_256;
1809 break;
1810 case IGB_RXBUFFER_512:
1811 rctl |= E1000_RCTL_SZ_512;
1812 break;
1813 default:
1814 srrctl = ALIGN(adapter->rx_buffer_len, 1024)
1815 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1816 break;
9d5c8243
AK		 1817 }
1818
1819 /* 82575 and greater support packet-split where the protocol
1820 * header is placed in skb->data and the packet data is
1821 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
1822 * In the case of a non-split, skb->data is linearly filled,
1823 * followed by the page buffers. Therefore, skb->data is
1824 * sized to hold the largest protocol header.
1825 */
1826 /* allocations using alloc_page take too long for regular MTU
1827 * so only enable packet split for jumbo frames */
ec54d7d6 1828 if (adapter->netdev->mtu > ETH_DATA_LEN) {
9d5c8243 1829 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
bf36c1a0 1830 srrctl |= adapter->rx_ps_hdr_size <<
9d5c8243 1831 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
9d5c8243
AK		 1832 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1833 } else {
1834 adapter->rx_ps_hdr_size = 0;
1835 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
1836 }
1837
26bc19ec
AD		 1838 for (i = 0; i < adapter->num_rx_queues; i++) {
1839 j = adapter->rx_ring[i].reg_idx;
1840 wr32(E1000_SRRCTL(j), srrctl);
1841 }
9d5c8243
AK		 1842
1843 wr32(E1000_RCTL, rctl);
1844}
1845
1846/**
1847 * igb_configure_rx - Configure receive Unit after Reset
1848 * @adapter: board private structure
1849 *
1850 * Configure the Rx unit of the MAC after a reset.
1851 **/
1852static void igb_configure_rx(struct igb_adapter *adapter)
1853{
1854 u64 rdba;
1855 struct e1000_hw *hw = &adapter->hw;
1856 u32 rctl, rxcsum;
1857 u32 rxdctl;
26bc19ec 1858 int i, j;
9d5c8243
AK		 1859
1860 /* disable receives while setting up the descriptors */
1861 rctl = rd32(E1000_RCTL);
1862 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1863 wrfl();
1864 mdelay(10);
1865
1866 if (adapter->itr_setting > 3)
6eb5a7f1 1867 wr32(E1000_ITR, adapter->itr);
9d5c8243
AK		 1868
1869 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1870 * the Base and Length of the Rx Descriptor Ring */
1871 for (i = 0; i < adapter->num_rx_queues; i++) {
1872 struct igb_ring *ring = &(adapter->rx_ring[i]);
26bc19ec 1873 j = ring->reg_idx;
9d5c8243 1874 rdba = ring->dma;
26bc19ec 1875 wr32(E1000_RDBAL(j),
9d5c8243 1876 rdba & 0x00000000ffffffffULL);
26bc19ec
AD		 1877 wr32(E1000_RDBAH(j), rdba >> 32);
1878 wr32(E1000_RDLEN(j),
9d5c8243
AK		 1879 ring->count * sizeof(union e1000_adv_rx_desc));
1880
26bc19ec
AD		 1881 ring->head = E1000_RDH(j);
1882 ring->tail = E1000_RDT(j);
9d5c8243
AK		 1883 writel(0, hw->hw_addr + ring->tail);
1884 writel(0, hw->hw_addr + ring->head);
1885
26bc19ec 1886 rxdctl = rd32(E1000_RXDCTL(j));
9d5c8243
AK		 1887 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
1888 rxdctl &= 0xFFF00000;
1889 rxdctl |= IGB_RX_PTHRESH;
1890 rxdctl |= IGB_RX_HTHRESH << 8;
1891 rxdctl |= IGB_RX_WTHRESH << 16;
26bc19ec 1892 wr32(E1000_RXDCTL(j), rxdctl);
9d5c8243
AK		 1893 }
1894
1895 if (adapter->num_rx_queues > 1) {
1896 u32 random[10];
1897 u32 mrqc;
1898 u32 j, shift;
1899 union e1000_reta {
1900 u32 dword;
1901 u8 bytes[4];
1902 } reta;
1903
1904 get_random_bytes(&random[0], 40);
1905
2d064c06
AD		 1906 if (hw->mac.type >= e1000_82576)
1907 shift = 0;
1908 else
1909 shift = 6;
9d5c8243
AK		 1910 for (j = 0; j < (32 * 4); j++) {
1911 reta.bytes[j & 3] =
26bc19ec 1912 adapter->rx_ring[(j % adapter->num_rx_queues)].reg_idx << shift;
9d5c8243
AK		 1913 if ((j & 3) == 3)
1914 writel(reta.dword,
1915 hw->hw_addr + E1000_RETA(0) + (j & ~3));
1916 }
1917 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
1918
1919 /* Fill out hash function seeds */
1920 for (j = 0; j < 10; j++)
1921 array_wr32(E1000_RSSRK(0), j, random[j]);
1922
1923 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
1924 E1000_MRQC_RSS_FIELD_IPV4_TCP);
1925 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
1926 E1000_MRQC_RSS_FIELD_IPV6_TCP);
1927 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
1928 E1000_MRQC_RSS_FIELD_IPV6_UDP);
1929 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
1930 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
1931
1932
1933 wr32(E1000_MRQC, mrqc);
1934
1935 /* Multiqueue and raw packet checksumming are mutually
1936 * exclusive. Note that this not the same as TCP/IP
1937 * checksumming, which works fine. */
1938 rxcsum = rd32(E1000_RXCSUM);
1939 rxcsum |= E1000_RXCSUM_PCSD;
1940 wr32(E1000_RXCSUM, rxcsum);
1941 } else {
1942 /* Enable Receive Checksum Offload for TCP and UDP */
1943 rxcsum = rd32(E1000_RXCSUM);
1944 if (adapter->rx_csum) {
1945 rxcsum |= E1000_RXCSUM_TUOFL;
1946
1947 /* Enable IPv4 payload checksum for UDP fragments
1948 * Must be used in conjunction with packet-split. */
1949 if (adapter->rx_ps_hdr_size)
1950 rxcsum |= E1000_RXCSUM_IPPCSE;
1951 } else {
1952 rxcsum &= ~E1000_RXCSUM_TUOFL;
1953 /* don't need to clear IPPCSE as it defaults to 0 */
1954 }
1955 wr32(E1000_RXCSUM, rxcsum);
1956 }
1957
1958 if (adapter->vlgrp)
1959 wr32(E1000_RLPML,
1960 adapter->max_frame_size + VLAN_TAG_SIZE);
1961 else
1962 wr32(E1000_RLPML, adapter->max_frame_size);
1963
1964 /* Enable Receives */
1965 wr32(E1000_RCTL, rctl);
1966}
1967
1968/**
1969 * igb_free_tx_resources - Free Tx Resources per Queue
9d5c8243
AK		 1970 * @tx_ring: Tx descriptor ring for a specific queue
1971 *
1972 * Free all transmit software resources
1973 **/
68fd9910 1974void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 1975{
3b644cf6 1976 struct pci_dev *pdev = tx_ring->adapter->pdev;
9d5c8243 1977
3b644cf6 1978 igb_clean_tx_ring(tx_ring);
9d5c8243
AK		 1979
1980 vfree(tx_ring->buffer_info);
1981 tx_ring->buffer_info = NULL;
1982
1983 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1984
1985 tx_ring->desc = NULL;
1986}
1987
1988/**
1989 * igb_free_all_tx_resources - Free Tx Resources for All Queues
1990 * @adapter: board private structure
1991 *
1992 * Free all transmit software resources
1993 **/
1994static void igb_free_all_tx_resources(struct igb_adapter *adapter)
1995{
1996 int i;
1997
1998 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 1999 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 2000}
2001
2002static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
2003 struct igb_buffer *buffer_info)
2004{
2005 if (buffer_info->dma) {
2006 pci_unmap_page(adapter->pdev,
2007 buffer_info->dma,
2008 buffer_info->length,
2009 PCI_DMA_TODEVICE);
2010 buffer_info->dma = 0;
2011 }
2012 if (buffer_info->skb) {
2013 dev_kfree_skb_any(buffer_info->skb);
2014 buffer_info->skb = NULL;
2015 }
2016 buffer_info->time_stamp = 0;
2017 /* buffer_info must be completely set up in the transmit path */
2018}
2019
2020/**
2021 * igb_clean_tx_ring - Free Tx Buffers
9d5c8243
AK		 2022 * @tx_ring: ring to be cleaned
2023 **/
3b644cf6 2024static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 2025{
3b644cf6 2026 struct igb_adapter *adapter = tx_ring->adapter;
9d5c8243
AK		 2027 struct igb_buffer *buffer_info;
2028 unsigned long size;
2029 unsigned int i;
2030
2031 if (!tx_ring->buffer_info)
2032 return;
2033 /* Free all the Tx ring sk_buffs */
2034
2035 for (i = 0; i < tx_ring->count; i++) {
2036 buffer_info = &tx_ring->buffer_info[i];
2037 igb_unmap_and_free_tx_resource(adapter, buffer_info);
2038 }
2039
2040 size = sizeof(struct igb_buffer) * tx_ring->count;
2041 memset(tx_ring->buffer_info, 0, size);
2042
2043 /* Zero out the descriptor ring */
2044
2045 memset(tx_ring->desc, 0, tx_ring->size);
2046
2047 tx_ring->next_to_use = 0;
2048 tx_ring->next_to_clean = 0;
2049
2050 writel(0, adapter->hw.hw_addr + tx_ring->head);
2051 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2052}
2053
2054/**
2055 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2056 * @adapter: board private structure
2057 **/
2058static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2059{
2060 int i;
2061
2062 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2063 igb_clean_tx_ring(&adapter->tx_ring[i]);
9d5c8243
AK		 2064}
2065
2066/**
2067 * igb_free_rx_resources - Free Rx Resources
9d5c8243
AK		 2068 * @rx_ring: ring to clean the resources from
2069 *
2070 * Free all receive software resources
2071 **/
68fd9910 2072void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2073{
3b644cf6 2074 struct pci_dev *pdev = rx_ring->adapter->pdev;
9d5c8243 2075
3b644cf6 2076 igb_clean_rx_ring(rx_ring);
9d5c8243
AK		 2077
2078 vfree(rx_ring->buffer_info);
2079 rx_ring->buffer_info = NULL;
2080
2081 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2082
2083 rx_ring->desc = NULL;
2084}
2085
2086/**
2087 * igb_free_all_rx_resources - Free Rx Resources for All Queues
2088 * @adapter: board private structure
2089 *
2090 * Free all receive software resources
2091 **/
2092static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2093{
2094 int i;
2095
2096 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2097 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 2098}
2099
2100/**
2101 * igb_clean_rx_ring - Free Rx Buffers per Queue
9d5c8243
AK		 2102 * @rx_ring: ring to free buffers from
2103 **/
3b644cf6 2104static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 2105{
3b644cf6 2106 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 2107 struct igb_buffer *buffer_info;
2108 struct pci_dev *pdev = adapter->pdev;
2109 unsigned long size;
2110 unsigned int i;
2111
2112 if (!rx_ring->buffer_info)
2113 return;
2114 /* Free all the Rx ring sk_buffs */
2115 for (i = 0; i < rx_ring->count; i++) {
2116 buffer_info = &rx_ring->buffer_info[i];
2117 if (buffer_info->dma) {
2118 if (adapter->rx_ps_hdr_size)
2119 pci_unmap_single(pdev, buffer_info->dma,
2120 adapter->rx_ps_hdr_size,
2121 PCI_DMA_FROMDEVICE);
2122 else
2123 pci_unmap_single(pdev, buffer_info->dma,
2124 adapter->rx_buffer_len,
2125 PCI_DMA_FROMDEVICE);
2126 buffer_info->dma = 0;
2127 }
2128
2129 if (buffer_info->skb) {
2130 dev_kfree_skb(buffer_info->skb);
2131 buffer_info->skb = NULL;
2132 }
2133 if (buffer_info->page) {
bf36c1a0
AD		 2134 if (buffer_info->page_dma)
2135 pci_unmap_page(pdev, buffer_info->page_dma,
2136 PAGE_SIZE / 2,
2137 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 2138 put_page(buffer_info->page);
2139 buffer_info->page = NULL;
2140 buffer_info->page_dma = 0;
bf36c1a0 2141 buffer_info->page_offset = 0;
9d5c8243
AK		 2142 }
2143 }
2144
9d5c8243
AK		 2145 size = sizeof(struct igb_buffer) * rx_ring->count;
2146 memset(rx_ring->buffer_info, 0, size);
2147
2148 /* Zero out the descriptor ring */
2149 memset(rx_ring->desc, 0, rx_ring->size);
2150
2151 rx_ring->next_to_clean = 0;
2152 rx_ring->next_to_use = 0;
2153
2154 writel(0, adapter->hw.hw_addr + rx_ring->head);
2155 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2156}
2157
2158/**
2159 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2160 * @adapter: board private structure
2161 **/
2162static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2163{
2164 int i;
2165
2166 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2167 igb_clean_rx_ring(&adapter->rx_ring[i]);
9d5c8243
AK		 2168}
2169
2170/**
2171 * igb_set_mac - Change the Ethernet Address of the NIC
2172 * @netdev: network interface device structure
2173 * @p: pointer to an address structure
2174 *
2175 * Returns 0 on success, negative on failure
2176 **/
2177static int igb_set_mac(struct net_device *netdev, void *p)
2178{
2179 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 2180 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 2181 struct sockaddr *addr = p;
2182
2183 if (!is_valid_ether_addr(addr->sa_data))
2184 return -EADDRNOTAVAIL;
2185
2186 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 2187 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 2188
28b0759c 2189 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
9d5c8243
AK		 2190
2191 return 0;
2192}
2193
2194/**
2195 * igb_set_multi - Multicast and Promiscuous mode set
2196 * @netdev: network interface device structure
2197 *
2198 * The set_multi entry point is called whenever the multicast address
2199 * list or the network interface flags are updated. This routine is
2200 * responsible for configuring the hardware for proper multicast,
2201 * promiscuous mode, and all-multi behavior.
2202 **/
2203static void igb_set_multi(struct net_device *netdev)
2204{
2205 struct igb_adapter *adapter = netdev_priv(netdev);
2206 struct e1000_hw *hw = &adapter->hw;
2207 struct e1000_mac_info *mac = &hw->mac;
2208 struct dev_mc_list *mc_ptr;
2209 u8 *mta_list;
2210 u32 rctl;
2211 int i;
2212
2213 /* Check for Promiscuous and All Multicast modes */
2214
2215 rctl = rd32(E1000_RCTL);
2216
746b9f02 2217 if (netdev->flags & IFF_PROMISC) {
9d5c8243 2218 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
746b9f02
PM		 2219 rctl &= ~E1000_RCTL_VFE;
2220 } else {
2221 if (netdev->flags & IFF_ALLMULTI) {
2222 rctl |= E1000_RCTL_MPE;
2223 rctl &= ~E1000_RCTL_UPE;
2224 } else
2225 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
78ed11a5 2226 rctl |= E1000_RCTL_VFE;
746b9f02 2227 }
9d5c8243
AK		 2228 wr32(E1000_RCTL, rctl);
2229
2230 if (!netdev->mc_count) {
2231 /* nothing to program, so clear mc list */
8a900862
AD		 2232 igb_update_mc_addr_list(hw, NULL, 0, 1,
2233 mac->rar_entry_count);
9d5c8243
AK		 2234 return;
2235 }
2236
2237 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2238 if (!mta_list)
2239 return;
2240
2241 /* The shared function expects a packed array of only addresses. */
2242 mc_ptr = netdev->mc_list;
2243
2244 for (i = 0; i < netdev->mc_count; i++) {
2245 if (!mc_ptr)
2246 break;
2247 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2248 mc_ptr = mc_ptr->next;
2249 }
8a900862 2250 igb_update_mc_addr_list(hw, mta_list, i, 1, mac->rar_entry_count);
9d5c8243
AK		 2251 kfree(mta_list);
2252}
2253
2254/* Need to wait a few seconds after link up to get diagnostic information from
2255 * the phy */
2256static void igb_update_phy_info(unsigned long data)
2257{
2258 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 2259 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 2260}
2261
4d6b725e
AD		 2262/**
2263 * igb_has_link - check shared code for link and determine up/down
2264 * @adapter: pointer to driver private info
2265 **/
2266static bool igb_has_link(struct igb_adapter *adapter)
2267{
2268 struct e1000_hw *hw = &adapter->hw;
2269 bool link_active = false;
2270 s32 ret_val = 0;
2271
2272 /* get_link_status is set on LSC (link status) interrupt or
2273 * rx sequence error interrupt. get_link_status will stay
2274 * false until the e1000_check_for_link establishes link
2275 * for copper adapters ONLY
2276 */
2277 switch (hw->phy.media_type) {
2278 case e1000_media_type_copper:
2279 if (hw->mac.get_link_status) {
2280 ret_val = hw->mac.ops.check_for_link(hw);
2281 link_active = !hw->mac.get_link_status;
2282 } else {
2283 link_active = true;
2284 }
2285 break;
2286 case e1000_media_type_fiber:
2287 ret_val = hw->mac.ops.check_for_link(hw);
2288 link_active = !!(rd32(E1000_STATUS) & E1000_STATUS_LU);
2289 break;
2290 case e1000_media_type_internal_serdes:
2291 ret_val = hw->mac.ops.check_for_link(hw);
2292 link_active = hw->mac.serdes_has_link;
2293 break;
2294 default:
2295 case e1000_media_type_unknown:
2296 break;
2297 }
2298
2299 return link_active;
2300}
2301
9d5c8243
AK		 2302/**
2303 * igb_watchdog - Timer Call-back
2304 * @data: pointer to adapter cast into an unsigned long
2305 **/
2306static void igb_watchdog(unsigned long data)
2307{
2308 struct igb_adapter *adapter = (struct igb_adapter *)data;
2309 /* Do the rest outside of interrupt context */
2310 schedule_work(&adapter->watchdog_task);
2311}
2312
2313static void igb_watchdog_task(struct work_struct *work)
2314{
2315 struct igb_adapter *adapter = container_of(work,
2316 struct igb_adapter, watchdog_task);
2317 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 2318 struct net_device *netdev = adapter->netdev;
2319 struct igb_ring *tx_ring = adapter->tx_ring;
9d5c8243 2320 u32 link;
7a6ea550 2321 u32 eics = 0;
7a6ea550 2322 int i;
9d5c8243 2323
4d6b725e
AD		 2324 link = igb_has_link(adapter);
2325 if ((netif_carrier_ok(netdev)) && link)
9d5c8243
AK		 2326 goto link_up;
2327
9d5c8243
AK		 2328 if (link) {
2329 if (!netif_carrier_ok(netdev)) {
2330 u32 ctrl;
2331 hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2332 &adapter->link_speed,
2333 &adapter->link_duplex);
2334
2335 ctrl = rd32(E1000_CTRL);
527d47c1
AD		 2336 /* Links status message must follow this format */
2337 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
9d5c8243 2338 "Flow Control: %s\n",
527d47c1 2339 netdev->name,
9d5c8243
AK		 2340 adapter->link_speed,
2341 adapter->link_duplex == FULL_DUPLEX ?
2342 "Full Duplex" : "Half Duplex",
2343 ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2344 E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2345 E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2346 E1000_CTRL_TFCE) ? "TX" : "None")));
2347
2348 /* tweak tx_queue_len according to speed/duplex and
2349 * adjust the timeout factor */
2350 netdev->tx_queue_len = adapter->tx_queue_len;
2351 adapter->tx_timeout_factor = 1;
2352 switch (adapter->link_speed) {
2353 case SPEED_10:
2354 netdev->tx_queue_len = 10;
2355 adapter->tx_timeout_factor = 14;
2356 break;
2357 case SPEED_100:
2358 netdev->tx_queue_len = 100;
2359 /* maybe add some timeout factor ? */
2360 break;
2361 }
2362
2363 netif_carrier_on(netdev);
fd2ea0a7 2364 netif_tx_wake_all_queues(netdev);
9d5c8243 2365
4b1a9877 2366 /* link state has changed, schedule phy info update */
9d5c8243
AK		 2367 if (!test_bit(__IGB_DOWN, &adapter->state))
2368 mod_timer(&adapter->phy_info_timer,
2369 round_jiffies(jiffies + 2 * HZ));
2370 }
2371 } else {
2372 if (netif_carrier_ok(netdev)) {
2373 adapter->link_speed = 0;
2374 adapter->link_duplex = 0;
527d47c1
AD		 2375 /* Links status message must follow this format */
2376 printk(KERN_INFO "igb: %s NIC Link is Down\n",
2377 netdev->name);
9d5c8243 2378 netif_carrier_off(netdev);
fd2ea0a7 2379 netif_tx_stop_all_queues(netdev);
4b1a9877
AD		 2380
2381 /* link state has changed, schedule phy info update */
9d5c8243
AK		 2382 if (!test_bit(__IGB_DOWN, &adapter->state))
2383 mod_timer(&adapter->phy_info_timer,
2384 round_jiffies(jiffies + 2 * HZ));
2385 }
2386 }
2387
2388link_up:
2389 igb_update_stats(adapter);
2390
4b1a9877 2391 hw->mac.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
9d5c8243 2392 adapter->tpt_old = adapter->stats.tpt;
4b1a9877 2393 hw->mac.collision_delta = adapter->stats.colc - adapter->colc_old;
9d5c8243
AK		 2394 adapter->colc_old = adapter->stats.colc;
2395
2396 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2397 adapter->gorc_old = adapter->stats.gorc;
2398 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2399 adapter->gotc_old = adapter->stats.gotc;
2400
2401 igb_update_adaptive(&adapter->hw);
2402
2403 if (!netif_carrier_ok(netdev)) {
2404 if (IGB_DESC_UNUSED(tx_ring) + 1 < tx_ring->count) {
2405 /* We've lost link, so the controller stops DMA,
2406 * but we've got queued Tx work that's never going
2407 * to get done, so reset controller to flush Tx.
2408 * (Do the reset outside of interrupt context). */
2409 adapter->tx_timeout_count++;
2410 schedule_work(&adapter->reset_task);
2411 }
2412 }
2413
2414 /* Cause software interrupt to ensure rx ring is cleaned */
7a6ea550
AD		 2415 if (adapter->msix_entries) {
2416 for (i = 0; i < adapter->num_rx_queues; i++)
2417 eics |= adapter->rx_ring[i].eims_value;
2418 wr32(E1000_EICS, eics);
2419 } else {
2420 wr32(E1000_ICS, E1000_ICS_RXDMT0);
2421 }
9d5c8243
AK		 2422
2423 /* Force detection of hung controller every watchdog period */
2424 tx_ring->detect_tx_hung = true;
2425
2426 /* Reset the timer */
2427 if (!test_bit(__IGB_DOWN, &adapter->state))
2428 mod_timer(&adapter->watchdog_timer,
2429 round_jiffies(jiffies + 2 * HZ));
2430}
2431
2432enum latency_range {
2433 lowest_latency = 0,
2434 low_latency = 1,
2435 bulk_latency = 2,
2436 latency_invalid = 255
2437};
2438
2439
6eb5a7f1
AD		 2440/**
2441 * igb_update_ring_itr - update the dynamic ITR value based on packet size
2442 *
2443 * Stores a new ITR value based on strictly on packet size. This
2444 * algorithm is less sophisticated than that used in igb_update_itr,
2445 * due to the difficulty of synchronizing statistics across multiple
2446 * receive rings. The divisors and thresholds used by this fuction
2447 * were determined based on theoretical maximum wire speed and testing
2448 * data, in order to minimize response time while increasing bulk
2449 * throughput.
2450 * This functionality is controlled by the InterruptThrottleRate module
2451 * parameter (see igb_param.c)
2452 * NOTE: This function is called only when operating in a multiqueue
2453 * receive environment.
2454 * @rx_ring: pointer to ring
2455 **/
2456static void igb_update_ring_itr(struct igb_ring *rx_ring)
9d5c8243 2457{
6eb5a7f1
AD		 2458 int new_val = rx_ring->itr_val;
2459 int avg_wire_size = 0;
2460 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 2461
6eb5a7f1
AD		 2462 if (!rx_ring->total_packets)
2463 goto clear_counts; /* no packets, so don't do anything */
9d5c8243 2464
6eb5a7f1
AD		 2465 /* For non-gigabit speeds, just fix the interrupt rate at 4000
2466 * ints/sec - ITR timer value of 120 ticks.
2467 */
2468 if (adapter->link_speed != SPEED_1000) {
2469 new_val = 120;
2470 goto set_itr_val;
9d5c8243 2471 }
6eb5a7f1 2472 avg_wire_size = rx_ring->total_bytes / rx_ring->total_packets;
9d5c8243 2473
6eb5a7f1
AD		 2474 /* Add 24 bytes to size to account for CRC, preamble, and gap */
2475 avg_wire_size += 24;
2476
2477 /* Don't starve jumbo frames */
2478 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 2479
6eb5a7f1
AD		 2480 /* Give a little boost to mid-size frames */
2481 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
2482 new_val = avg_wire_size / 3;
2483 else
2484 new_val = avg_wire_size / 2;
9d5c8243 2485
6eb5a7f1 2486set_itr_val:
9d5c8243
AK		 2487 if (new_val != rx_ring->itr_val) {
2488 rx_ring->itr_val = new_val;
6eb5a7f1 2489 rx_ring->set_itr = 1;
9d5c8243 2490 }
6eb5a7f1
AD		 2491clear_counts:
2492 rx_ring->total_bytes = 0;
2493 rx_ring->total_packets = 0;
9d5c8243
AK		 2494}
2495
2496/**
2497 * igb_update_itr - update the dynamic ITR value based on statistics
2498 * Stores a new ITR value based on packets and byte
2499 * counts during the last interrupt. The advantage of per interrupt
2500 * computation is faster updates and more accurate ITR for the current
2501 * traffic pattern. Constants in this function were computed
2502 * based on theoretical maximum wire speed and thresholds were set based
2503 * on testing data as well as attempting to minimize response time
2504 * while increasing bulk throughput.
2505 * this functionality is controlled by the InterruptThrottleRate module
2506 * parameter (see igb_param.c)
2507 * NOTE: These calculations are only valid when operating in a single-
2508 * queue environment.
2509 * @adapter: pointer to adapter
2510 * @itr_setting: current adapter->itr
2511 * @packets: the number of packets during this measurement interval
2512 * @bytes: the number of bytes during this measurement interval
2513 **/
2514static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
2515 int packets, int bytes)
2516{
2517 unsigned int retval = itr_setting;
2518
2519 if (packets == 0)
2520 goto update_itr_done;
2521
2522 switch (itr_setting) {
2523 case lowest_latency:
2524 /* handle TSO and jumbo frames */
2525 if (bytes/packets > 8000)
2526 retval = bulk_latency;
2527 else if ((packets < 5) && (bytes > 512))
2528 retval = low_latency;
2529 break;
2530 case low_latency: /* 50 usec aka 20000 ints/s */
2531 if (bytes > 10000) {
2532 /* this if handles the TSO accounting */
2533 if (bytes/packets > 8000) {
2534 retval = bulk_latency;
2535 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
2536 retval = bulk_latency;
2537 } else if ((packets > 35)) {
2538 retval = lowest_latency;
2539 }
2540 } else if (bytes/packets > 2000) {
2541 retval = bulk_latency;
2542 } else if (packets <= 2 && bytes < 512) {
2543 retval = lowest_latency;
2544 }
2545 break;
2546 case bulk_latency: /* 250 usec aka 4000 ints/s */
2547 if (bytes > 25000) {
2548 if (packets > 35)
2549 retval = low_latency;
2550 } else if (bytes < 6000) {
2551 retval = low_latency;
2552 }
2553 break;
2554 }
2555
2556update_itr_done:
2557 return retval;
2558}
2559
6eb5a7f1 2560static void igb_set_itr(struct igb_adapter *adapter)
9d5c8243
AK		 2561{
2562 u16 current_itr;
2563 u32 new_itr = adapter->itr;
2564
2565 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2566 if (adapter->link_speed != SPEED_1000) {
2567 current_itr = 0;
2568 new_itr = 4000;
2569 goto set_itr_now;
2570 }
2571
2572 adapter->rx_itr = igb_update_itr(adapter,
2573 adapter->rx_itr,
2574 adapter->rx_ring->total_packets,
2575 adapter->rx_ring->total_bytes);
9d5c8243 2576
6eb5a7f1 2577 if (adapter->rx_ring->buddy) {
9d5c8243
AK		 2578 adapter->tx_itr = igb_update_itr(adapter,
2579 adapter->tx_itr,
2580 adapter->tx_ring->total_packets,
2581 adapter->tx_ring->total_bytes);
9d5c8243
AK		 2582
2583 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2584 } else {
2585 current_itr = adapter->rx_itr;
2586 }
2587
6eb5a7f1
AD		 2588 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2589 if (adapter->itr_setting == 3 &&
2590 current_itr == lowest_latency)
2591 current_itr = low_latency;
2592
9d5c8243
AK		 2593 switch (current_itr) {
2594 /* counts and packets in update_itr are dependent on these numbers */
2595 case lowest_latency:
2596 new_itr = 70000;
2597 break;
2598 case low_latency:
2599 new_itr = 20000; /* aka hwitr = ~200 */
2600 break;
2601 case bulk_latency:
2602 new_itr = 4000;
2603 break;
2604 default:
2605 break;
2606 }
2607
2608set_itr_now:
6eb5a7f1
AD		 2609 adapter->rx_ring->total_bytes = 0;
2610 adapter->rx_ring->total_packets = 0;
2611 if (adapter->rx_ring->buddy) {
2612 adapter->rx_ring->buddy->total_bytes = 0;
2613 adapter->rx_ring->buddy->total_packets = 0;
2614 }
2615
9d5c8243
AK		 2616 if (new_itr != adapter->itr) {
2617 /* this attempts to bias the interrupt rate towards Bulk
2618 * by adding intermediate steps when interrupt rate is
2619 * increasing */
2620 new_itr = new_itr > adapter->itr ?
2621 min(adapter->itr + (new_itr >> 2), new_itr) :
2622 new_itr;
2623 /* Don't write the value here; it resets the adapter's
2624 * internal timer, and causes us to delay far longer than
2625 * we should between interrupts. Instead, we write the ITR
2626 * value at the beginning of the next interrupt so the timing
2627 * ends up being correct.
2628 */
2629 adapter->itr = new_itr;
6eb5a7f1
AD		 2630 adapter->rx_ring->itr_val = 1000000000 / (new_itr * 256);
2631 adapter->rx_ring->set_itr = 1;
9d5c8243
AK		 2632 }
2633
2634 return;
2635}
2636
2637
2638#define IGB_TX_FLAGS_CSUM 0x00000001
2639#define IGB_TX_FLAGS_VLAN 0x00000002
2640#define IGB_TX_FLAGS_TSO 0x00000004
2641#define IGB_TX_FLAGS_IPV4 0x00000008
2642#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
2643#define IGB_TX_FLAGS_VLAN_SHIFT 16
2644
2645static inline int igb_tso_adv(struct igb_adapter *adapter,
2646 struct igb_ring *tx_ring,
2647 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
2648{
2649 struct e1000_adv_tx_context_desc *context_desc;
2650 unsigned int i;
2651 int err;
2652 struct igb_buffer *buffer_info;
2653 u32 info = 0, tu_cmd = 0;
2654 u32 mss_l4len_idx, l4len;
2655 *hdr_len = 0;
2656
2657 if (skb_header_cloned(skb)) {
2658 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2659 if (err)
2660 return err;
2661 }
2662
2663 l4len = tcp_hdrlen(skb);
2664 *hdr_len += l4len;
2665
2666 if (skb->protocol == htons(ETH_P_IP)) {
2667 struct iphdr *iph = ip_hdr(skb);
2668 iph->tot_len = 0;
2669 iph->check = 0;
2670 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2671 iph->daddr, 0,
2672 IPPROTO_TCP,
2673 0);
2674 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
2675 ipv6_hdr(skb)->payload_len = 0;
2676 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2677 &ipv6_hdr(skb)->daddr,
2678 0, IPPROTO_TCP, 0);
2679 }
2680
2681 i = tx_ring->next_to_use;
2682
2683 buffer_info = &tx_ring->buffer_info[i];
2684 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2685 /* VLAN MACLEN IPLEN */
2686 if (tx_flags & IGB_TX_FLAGS_VLAN)
2687 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2688 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2689 *hdr_len += skb_network_offset(skb);
2690 info |= skb_network_header_len(skb);
2691 *hdr_len += skb_network_header_len(skb);
2692 context_desc->vlan_macip_lens = cpu_to_le32(info);
2693
2694 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
2695 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2696
2697 if (skb->protocol == htons(ETH_P_IP))
2698 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
2699 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2700
2701 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2702
2703 /* MSS L4LEN IDX */
2704 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
2705 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
2706
7dfc16fa
AD		 2707 /* Context index must be unique per ring. */
2708 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2709 mss_l4len_idx |= tx_ring->queue_index << 4;
9d5c8243
AK		 2710
2711 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
2712 context_desc->seqnum_seed = 0;
2713
2714 buffer_info->time_stamp = jiffies;
0e014cb1 2715 buffer_info->next_to_watch = i;
9d5c8243
AK		 2716 buffer_info->dma = 0;
2717 i++;
2718 if (i == tx_ring->count)
2719 i = 0;
2720
2721 tx_ring->next_to_use = i;
2722
2723 return true;
2724}
2725
2726static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
2727 struct igb_ring *tx_ring,
2728 struct sk_buff *skb, u32 tx_flags)
2729{
2730 struct e1000_adv_tx_context_desc *context_desc;
2731 unsigned int i;
2732 struct igb_buffer *buffer_info;
2733 u32 info = 0, tu_cmd = 0;
2734
2735 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
2736 (tx_flags & IGB_TX_FLAGS_VLAN)) {
2737 i = tx_ring->next_to_use;
2738 buffer_info = &tx_ring->buffer_info[i];
2739 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2740
2741 if (tx_flags & IGB_TX_FLAGS_VLAN)
2742 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2743 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2744 if (skb->ip_summed == CHECKSUM_PARTIAL)
2745 info |= skb_network_header_len(skb);
2746
2747 context_desc->vlan_macip_lens = cpu_to_le32(info);
2748
2749 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2750
2751 if (skb->ip_summed == CHECKSUM_PARTIAL) {
44b0cda3 2752 switch (skb->protocol) {
09640e63 2753 case cpu_to_be16(ETH_P_IP):
9d5c8243 2754 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
44b0cda3
MW		 2755 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
2756 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2757 break;
09640e63 2758 case cpu_to_be16(ETH_P_IPV6):
44b0cda3
MW		 2759 /* XXX what about other V6 headers?? */
2760 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
2761 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2762 break;
2763 default:
2764 if (unlikely(net_ratelimit()))
2765 dev_warn(&adapter->pdev->dev,
2766 "partial checksum but proto=%x!\n",
2767 skb->protocol);
2768 break;
2769 }
9d5c8243
AK		 2770 }
2771
2772 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2773 context_desc->seqnum_seed = 0;
7dfc16fa
AD		 2774 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2775 context_desc->mss_l4len_idx =
2776 cpu_to_le32(tx_ring->queue_index << 4);
9d5c8243
AK		 2777
2778 buffer_info->time_stamp = jiffies;
0e014cb1 2779 buffer_info->next_to_watch = i;
9d5c8243
AK		 2780 buffer_info->dma = 0;
2781
2782 i++;
2783 if (i == tx_ring->count)
2784 i = 0;
2785 tx_ring->next_to_use = i;
2786
2787 return true;
2788 }
2789
2790
2791 return false;
2792}
2793
2794#define IGB_MAX_TXD_PWR 16
2795#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
2796
2797static inline int igb_tx_map_adv(struct igb_adapter *adapter,
0e014cb1
AD		 2798 struct igb_ring *tx_ring, struct sk_buff *skb,
2799 unsigned int first)
9d5c8243
AK		 2800{
2801 struct igb_buffer *buffer_info;
2802 unsigned int len = skb_headlen(skb);
2803 unsigned int count = 0, i;
2804 unsigned int f;
2805
2806 i = tx_ring->next_to_use;
2807
2808 buffer_info = &tx_ring->buffer_info[i];
2809 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2810 buffer_info->length = len;
2811 /* set time_stamp *before* dma to help avoid a possible race */
2812 buffer_info->time_stamp = jiffies;
0e014cb1 2813 buffer_info->next_to_watch = i;
9d5c8243
AK		 2814 buffer_info->dma = pci_map_single(adapter->pdev, skb->data, len,
2815 PCI_DMA_TODEVICE);
2816 count++;
2817 i++;
2818 if (i == tx_ring->count)
2819 i = 0;
2820
2821 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
2822 struct skb_frag_struct *frag;
2823
2824 frag = &skb_shinfo(skb)->frags[f];
2825 len = frag->size;
2826
2827 buffer_info = &tx_ring->buffer_info[i];
2828 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2829 buffer_info->length = len;
2830 buffer_info->time_stamp = jiffies;
0e014cb1 2831 buffer_info->next_to_watch = i;
9d5c8243
AK		 2832 buffer_info->dma = pci_map_page(adapter->pdev,
2833 frag->page,
2834 frag->page_offset,
2835 len,
2836 PCI_DMA_TODEVICE);
2837
2838 count++;
2839 i++;
2840 if (i == tx_ring->count)
2841 i = 0;
2842 }
2843
0e014cb1 2844 i = ((i == 0) ? tx_ring->count - 1 : i - 1);
9d5c8243 2845 tx_ring->buffer_info[i].skb = skb;
0e014cb1 2846 tx_ring->buffer_info[first].next_to_watch = i;
9d5c8243
AK		 2847
2848 return count;
2849}
2850
2851static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
2852 struct igb_ring *tx_ring,
2853 int tx_flags, int count, u32 paylen,
2854 u8 hdr_len)
2855{
2856 union e1000_adv_tx_desc *tx_desc = NULL;
2857 struct igb_buffer *buffer_info;
2858 u32 olinfo_status = 0, cmd_type_len;
2859 unsigned int i;
2860
2861 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
2862 E1000_ADVTXD_DCMD_DEXT);
2863
2864 if (tx_flags & IGB_TX_FLAGS_VLAN)
2865 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
2866
2867 if (tx_flags & IGB_TX_FLAGS_TSO) {
2868 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
2869
2870 /* insert tcp checksum */
2871 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2872
2873 /* insert ip checksum */
2874 if (tx_flags & IGB_TX_FLAGS_IPV4)
2875 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
2876
2877 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
2878 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2879 }
2880
7dfc16fa
AD		 2881 if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) &&
2882 (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
2883 IGB_TX_FLAGS_VLAN)))
661086df 2884 olinfo_status |= tx_ring->queue_index << 4;
9d5c8243
AK		 2885
2886 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
2887
2888 i = tx_ring->next_to_use;
2889 while (count--) {
2890 buffer_info = &tx_ring->buffer_info[i];
2891 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
2892 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
2893 tx_desc->read.cmd_type_len =
2894 cpu_to_le32(cmd_type_len | buffer_info->length);
2895 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
2896 i++;
2897 if (i == tx_ring->count)
2898 i = 0;
2899 }
2900
2901 tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
2902 /* Force memory writes to complete before letting h/w
2903 * know there are new descriptors to fetch. (Only
2904 * applicable for weak-ordered memory model archs,
2905 * such as IA-64). */
2906 wmb();
2907
2908 tx_ring->next_to_use = i;
2909 writel(i, adapter->hw.hw_addr + tx_ring->tail);
2910 /* we need this if more than one processor can write to our tail
2911 * at a time, it syncronizes IO on IA64/Altix systems */
2912 mmiowb();
2913}
2914
2915static int __igb_maybe_stop_tx(struct net_device *netdev,
2916 struct igb_ring *tx_ring, int size)
2917{
2918 struct igb_adapter *adapter = netdev_priv(netdev);
2919
661086df 2920 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 2921
9d5c8243
AK		 2922 /* Herbert's original patch had:
2923 * smp_mb__after_netif_stop_queue();
2924 * but since that doesn't exist yet, just open code it. */
2925 smp_mb();
2926
2927 /* We need to check again in a case another CPU has just
2928 * made room available. */
2929 if (IGB_DESC_UNUSED(tx_ring) < size)
2930 return -EBUSY;
2931
2932 /* A reprieve! */
661086df 2933 netif_wake_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 2934 ++adapter->restart_queue;
2935 return 0;
2936}
2937
2938static int igb_maybe_stop_tx(struct net_device *netdev,
2939 struct igb_ring *tx_ring, int size)
2940{
2941 if (IGB_DESC_UNUSED(tx_ring) >= size)
2942 return 0;
2943 return __igb_maybe_stop_tx(netdev, tx_ring, size);
2944}
2945
2946#define TXD_USE_COUNT(S) (((S) >> (IGB_MAX_TXD_PWR)) + 1)
2947
2948static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
2949 struct net_device *netdev,
2950 struct igb_ring *tx_ring)
2951{
2952 struct igb_adapter *adapter = netdev_priv(netdev);
0e014cb1 2953 unsigned int first;
9d5c8243
AK		 2954 unsigned int tx_flags = 0;
2955 unsigned int len;
9d5c8243
AK		 2956 u8 hdr_len = 0;
2957 int tso = 0;
2958
2959 len = skb_headlen(skb);
2960
2961 if (test_bit(__IGB_DOWN, &adapter->state)) {
2962 dev_kfree_skb_any(skb);
2963 return NETDEV_TX_OK;
2964 }
2965
2966 if (skb->len <= 0) {
2967 dev_kfree_skb_any(skb);
2968 return NETDEV_TX_OK;
2969 }
2970
9d5c8243
AK		 2971 /* need: 1 descriptor per page,
2972 * + 2 desc gap to keep tail from touching head,
2973 * + 1 desc for skb->data,
2974 * + 1 desc for context descriptor,
2975 * otherwise try next time */
2976 if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
2977 /* this is a hard error */
9d5c8243
AK		 2978 return NETDEV_TX_BUSY;
2979 }
6eb5a7f1 2980 skb_orphan(skb);
9d5c8243
AK		 2981
2982 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
2983 tx_flags |= IGB_TX_FLAGS_VLAN;
2984 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
2985 }
2986
661086df
PWJ		 2987 if (skb->protocol == htons(ETH_P_IP))
2988 tx_flags |= IGB_TX_FLAGS_IPV4;
2989
0e014cb1
AD		 2990 first = tx_ring->next_to_use;
2991
9d5c8243
AK		 2992 tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
2993 &hdr_len) : 0;
2994
2995 if (tso < 0) {
2996 dev_kfree_skb_any(skb);
9d5c8243
AK		 2997 return NETDEV_TX_OK;
2998 }
2999
3000 if (tso)
3001 tx_flags |= IGB_TX_FLAGS_TSO;
3002 else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags))
3003 if (skb->ip_summed == CHECKSUM_PARTIAL)
3004 tx_flags |= IGB_TX_FLAGS_CSUM;
3005
9d5c8243 3006 igb_tx_queue_adv(adapter, tx_ring, tx_flags,
0e014cb1 3007 igb_tx_map_adv(adapter, tx_ring, skb, first),
9d5c8243
AK		 3008 skb->len, hdr_len);
3009
3010 netdev->trans_start = jiffies;
3011
3012 /* Make sure there is space in the ring for the next send. */
3013 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
3014
9d5c8243
AK		 3015 return NETDEV_TX_OK;
3016}
3017
3018static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *netdev)
3019{
3020 struct igb_adapter *adapter = netdev_priv(netdev);
661086df
PWJ		 3021 struct igb_ring *tx_ring;
3022
661086df
PWJ		 3023 int r_idx = 0;
3024 r_idx = skb->queue_mapping & (IGB_MAX_TX_QUEUES - 1);
3025 tx_ring = adapter->multi_tx_table[r_idx];
9d5c8243
AK		 3026
3027 /* This goes back to the question of how to logically map a tx queue
3028 * to a flow. Right now, performance is impacted slightly negatively
3029 * if using multiple tx queues. If the stack breaks away from a
3030 * single qdisc implementation, we can look at this again. */
3031 return (igb_xmit_frame_ring_adv(skb, netdev, tx_ring));
3032}
3033
3034/**
3035 * igb_tx_timeout - Respond to a Tx Hang
3036 * @netdev: network interface device structure
3037 **/
3038static void igb_tx_timeout(struct net_device *netdev)
3039{
3040 struct igb_adapter *adapter = netdev_priv(netdev);
3041 struct e1000_hw *hw = &adapter->hw;
3042
3043 /* Do the reset outside of interrupt context */
3044 adapter->tx_timeout_count++;
3045 schedule_work(&adapter->reset_task);
3046 wr32(E1000_EICS, adapter->eims_enable_mask &
3047 ~(E1000_EIMS_TCP_TIMER | E1000_EIMS_OTHER));
3048}
3049
3050static void igb_reset_task(struct work_struct *work)
3051{
3052 struct igb_adapter *adapter;
3053 adapter = container_of(work, struct igb_adapter, reset_task);
3054
3055 igb_reinit_locked(adapter);
3056}
3057
3058/**
3059 * igb_get_stats - Get System Network Statistics
3060 * @netdev: network interface device structure
3061 *
3062 * Returns the address of the device statistics structure.
3063 * The statistics are actually updated from the timer callback.
3064 **/
3065static struct net_device_stats *
3066igb_get_stats(struct net_device *netdev)
3067{
3068 struct igb_adapter *adapter = netdev_priv(netdev);
3069
3070 /* only return the current stats */
3071 return &adapter->net_stats;
3072}
3073
3074/**
3075 * igb_change_mtu - Change the Maximum Transfer Unit
3076 * @netdev: network interface device structure
3077 * @new_mtu: new value for maximum frame size
3078 *
3079 * Returns 0 on success, negative on failure
3080 **/
3081static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3082{
3083 struct igb_adapter *adapter = netdev_priv(netdev);
3084 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3085
3086 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
3087 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3088 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
3089 return -EINVAL;
3090 }
3091
3092#define MAX_STD_JUMBO_FRAME_SIZE 9234
3093 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3094 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
3095 return -EINVAL;
3096 }
3097
3098 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3099 msleep(1);
3100 /* igb_down has a dependency on max_frame_size */
3101 adapter->max_frame_size = max_frame;
3102 if (netif_running(netdev))
3103 igb_down(adapter);
3104
3105 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3106 * means we reserve 2 more, this pushes us to allocate from the next
3107 * larger slab size.
3108 * i.e. RXBUFFER_2048 --> size-4096 slab
3109 */
3110
3111 if (max_frame <= IGB_RXBUFFER_256)
3112 adapter->rx_buffer_len = IGB_RXBUFFER_256;
3113 else if (max_frame <= IGB_RXBUFFER_512)
3114 adapter->rx_buffer_len = IGB_RXBUFFER_512;
3115 else if (max_frame <= IGB_RXBUFFER_1024)
3116 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3117 else if (max_frame <= IGB_RXBUFFER_2048)
3118 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
3119 else
bf36c1a0
AD		 3120#if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
3121 adapter->rx_buffer_len = IGB_RXBUFFER_16384;
3122#else
3123 adapter->rx_buffer_len = PAGE_SIZE / 2;
3124#endif
9d5c8243
AK		 3125 /* adjust allocation if LPE protects us, and we aren't using SBP */
3126 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
3127 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
3128 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3129
3130 dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
3131 netdev->mtu, new_mtu);
3132 netdev->mtu = new_mtu;
3133
3134 if (netif_running(netdev))
3135 igb_up(adapter);
3136 else
3137 igb_reset(adapter);
3138
3139 clear_bit(__IGB_RESETTING, &adapter->state);
3140
3141 return 0;
3142}
3143
3144/**
3145 * igb_update_stats - Update the board statistics counters
3146 * @adapter: board private structure
3147 **/
3148
3149void igb_update_stats(struct igb_adapter *adapter)
3150{
3151 struct e1000_hw *hw = &adapter->hw;
3152 struct pci_dev *pdev = adapter->pdev;
3153 u16 phy_tmp;
3154
3155#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3156
3157 /*
3158 * Prevent stats update while adapter is being reset, or if the pci
3159 * connection is down.
3160 */
3161 if (adapter->link_speed == 0)
3162 return;
3163 if (pci_channel_offline(pdev))
3164 return;
3165
3166 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3167 adapter->stats.gprc += rd32(E1000_GPRC);
3168 adapter->stats.gorc += rd32(E1000_GORCL);
3169 rd32(E1000_GORCH); /* clear GORCL */
3170 adapter->stats.bprc += rd32(E1000_BPRC);
3171 adapter->stats.mprc += rd32(E1000_MPRC);
3172 adapter->stats.roc += rd32(E1000_ROC);
3173
3174 adapter->stats.prc64 += rd32(E1000_PRC64);
3175 adapter->stats.prc127 += rd32(E1000_PRC127);
3176 adapter->stats.prc255 += rd32(E1000_PRC255);
3177 adapter->stats.prc511 += rd32(E1000_PRC511);
3178 adapter->stats.prc1023 += rd32(E1000_PRC1023);
3179 adapter->stats.prc1522 += rd32(E1000_PRC1522);
3180 adapter->stats.symerrs += rd32(E1000_SYMERRS);
3181 adapter->stats.sec += rd32(E1000_SEC);
3182
3183 adapter->stats.mpc += rd32(E1000_MPC);
3184 adapter->stats.scc += rd32(E1000_SCC);
3185 adapter->stats.ecol += rd32(E1000_ECOL);
3186 adapter->stats.mcc += rd32(E1000_MCC);
3187 adapter->stats.latecol += rd32(E1000_LATECOL);
3188 adapter->stats.dc += rd32(E1000_DC);
3189 adapter->stats.rlec += rd32(E1000_RLEC);
3190 adapter->stats.xonrxc += rd32(E1000_XONRXC);
3191 adapter->stats.xontxc += rd32(E1000_XONTXC);
3192 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
3193 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
3194 adapter->stats.fcruc += rd32(E1000_FCRUC);
3195 adapter->stats.gptc += rd32(E1000_GPTC);
3196 adapter->stats.gotc += rd32(E1000_GOTCL);
3197 rd32(E1000_GOTCH); /* clear GOTCL */
3198 adapter->stats.rnbc += rd32(E1000_RNBC);
3199 adapter->stats.ruc += rd32(E1000_RUC);
3200 adapter->stats.rfc += rd32(E1000_RFC);
3201 adapter->stats.rjc += rd32(E1000_RJC);
3202 adapter->stats.tor += rd32(E1000_TORH);
3203 adapter->stats.tot += rd32(E1000_TOTH);
3204 adapter->stats.tpr += rd32(E1000_TPR);
3205
3206 adapter->stats.ptc64 += rd32(E1000_PTC64);
3207 adapter->stats.ptc127 += rd32(E1000_PTC127);
3208 adapter->stats.ptc255 += rd32(E1000_PTC255);
3209 adapter->stats.ptc511 += rd32(E1000_PTC511);
3210 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
3211 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
3212
3213 adapter->stats.mptc += rd32(E1000_MPTC);
3214 adapter->stats.bptc += rd32(E1000_BPTC);
3215
3216 /* used for adaptive IFS */
3217
3218 hw->mac.tx_packet_delta = rd32(E1000_TPT);
3219 adapter->stats.tpt += hw->mac.tx_packet_delta;
3220 hw->mac.collision_delta = rd32(E1000_COLC);
3221 adapter->stats.colc += hw->mac.collision_delta;
3222
3223 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
3224 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3225 adapter->stats.tncrs += rd32(E1000_TNCRS);
3226 adapter->stats.tsctc += rd32(E1000_TSCTC);
3227 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
3228
3229 adapter->stats.iac += rd32(E1000_IAC);
3230 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
3231 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
3232 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
3233 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
3234 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
3235 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
3236 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
3237 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
3238
3239 /* Fill out the OS statistics structure */
3240 adapter->net_stats.multicast = adapter->stats.mprc;
3241 adapter->net_stats.collisions = adapter->stats.colc;
3242
3243 /* Rx Errors */
3244
3245 /* RLEC on some newer hardware can be incorrect so build
3246 * our own version based on RUC and ROC */
3247 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3248 adapter->stats.crcerrs + adapter->stats.algnerrc +
3249 adapter->stats.ruc + adapter->stats.roc +
3250 adapter->stats.cexterr;
3251 adapter->net_stats.rx_length_errors = adapter->stats.ruc +
3252 adapter->stats.roc;
3253 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3254 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
3255 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3256
3257 /* Tx Errors */
3258 adapter->net_stats.tx_errors = adapter->stats.ecol +
3259 adapter->stats.latecol;
3260 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3261 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3262 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3263
3264 /* Tx Dropped needs to be maintained elsewhere */
3265
3266 /* Phy Stats */
3267 if (hw->phy.media_type == e1000_media_type_copper) {
3268 if ((adapter->link_speed == SPEED_1000) &&
f5f4cf08 3269 (!igb_read_phy_reg(hw, PHY_1000T_STATUS,
9d5c8243
AK		 3270 &phy_tmp))) {
3271 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3272 adapter->phy_stats.idle_errors += phy_tmp;
3273 }
3274 }
3275
3276 /* Management Stats */
3277 adapter->stats.mgptc += rd32(E1000_MGTPTC);
3278 adapter->stats.mgprc += rd32(E1000_MGTPRC);
3279 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3280}
3281
3282
3283static irqreturn_t igb_msix_other(int irq, void *data)
3284{
3285 struct net_device *netdev = data;
3286 struct igb_adapter *adapter = netdev_priv(netdev);
3287 struct e1000_hw *hw = &adapter->hw;
844290e5 3288 u32 icr = rd32(E1000_ICR);
9d5c8243 3289
844290e5 3290 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083
AD		 3291
3292 if(icr & E1000_ICR_DOUTSYNC) {
3293 /* HW is reporting DMA is out of sync */
3294 adapter->stats.doosync++;
3295 }
844290e5
PW		 3296 if (!(icr & E1000_ICR_LSC))
3297 goto no_link_interrupt;
3298 hw->mac.get_link_status = 1;
3299 /* guard against interrupt when we're going down */
3300 if (!test_bit(__IGB_DOWN, &adapter->state))
3301 mod_timer(&adapter->watchdog_timer, jiffies + 1);
eebbbdba 3302
9d5c8243 3303no_link_interrupt:
dda0e083 3304 wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC);
844290e5 3305 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 3306
3307 return IRQ_HANDLED;
3308}
3309
3310static irqreturn_t igb_msix_tx(int irq, void *data)
3311{
3312 struct igb_ring *tx_ring = data;
3313 struct igb_adapter *adapter = tx_ring->adapter;
3314 struct e1000_hw *hw = &adapter->hw;
3315
421e02f0 3316#ifdef CONFIG_IGB_DCA
7dfc16fa 3317 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3318 igb_update_tx_dca(tx_ring);
3319#endif
9d5c8243
AK		 3320 tx_ring->total_bytes = 0;
3321 tx_ring->total_packets = 0;
661086df
PWJ		 3322
3323 /* auto mask will automatically reenable the interrupt when we write
3324 * EICS */
3b644cf6 3325 if (!igb_clean_tx_irq(tx_ring))
9d5c8243
AK		 3326 /* Ring was not completely cleaned, so fire another interrupt */
3327 wr32(E1000_EICS, tx_ring->eims_value);
661086df 3328 else
9d5c8243 3329 wr32(E1000_EIMS, tx_ring->eims_value);
661086df 3330
9d5c8243
AK		 3331 return IRQ_HANDLED;
3332}
3333
6eb5a7f1
AD		 3334static void igb_write_itr(struct igb_ring *ring)
3335{
3336 struct e1000_hw *hw = &ring->adapter->hw;
3337 if ((ring->adapter->itr_setting & 3) && ring->set_itr) {
3338 switch (hw->mac.type) {
3339 case e1000_82576:
3340 wr32(ring->itr_register,
3341 ring->itr_val |
3342 0x80000000);
3343 break;
3344 default:
3345 wr32(ring->itr_register,
3346 ring->itr_val |
3347 (ring->itr_val << 16));
3348 break;
3349 }
3350 ring->set_itr = 0;
3351 }
3352}
3353
9d5c8243
AK		 3354static irqreturn_t igb_msix_rx(int irq, void *data)
3355{
3356 struct igb_ring *rx_ring = data;
9d5c8243 3357
844290e5
PW		 3358 /* Write the ITR value calculated at the end of the
3359 * previous interrupt.
3360 */
9d5c8243 3361
6eb5a7f1 3362 igb_write_itr(rx_ring);
9d5c8243 3363
288379f0
BH		 3364 if (napi_schedule_prep(&rx_ring->napi))
3365 __napi_schedule(&rx_ring->napi);
844290e5 3366
421e02f0 3367#ifdef CONFIG_IGB_DCA
8d253320 3368 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3369 igb_update_rx_dca(rx_ring);
3370#endif
3371 return IRQ_HANDLED;
3372}
3373
421e02f0 3374#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 3375static void igb_update_rx_dca(struct igb_ring *rx_ring)
3376{
3377 u32 dca_rxctrl;
3378 struct igb_adapter *adapter = rx_ring->adapter;
3379 struct e1000_hw *hw = &adapter->hw;
3380 int cpu = get_cpu();
26bc19ec 3381 int q = rx_ring->reg_idx;
fe4506b6
JC		 3382
3383 if (rx_ring->cpu != cpu) {
3384 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
2d064c06
AD		 3385 if (hw->mac.type == e1000_82576) {
3386 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
3387 dca_rxctrl |= dca_get_tag(cpu) <<
3388 E1000_DCA_RXCTRL_CPUID_SHIFT;
3389 } else {
3390 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
3391 dca_rxctrl |= dca_get_tag(cpu);
3392 }
fe4506b6
JC		 3393 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
3394 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
3395 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
3396 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
3397 rx_ring->cpu = cpu;
3398 }
3399 put_cpu();
3400}
3401
3402static void igb_update_tx_dca(struct igb_ring *tx_ring)
3403{
3404 u32 dca_txctrl;
3405 struct igb_adapter *adapter = tx_ring->adapter;
3406 struct e1000_hw *hw = &adapter->hw;
3407 int cpu = get_cpu();
26bc19ec 3408 int q = tx_ring->reg_idx;
fe4506b6
JC		 3409
3410 if (tx_ring->cpu != cpu) {
3411 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
2d064c06
AD		 3412 if (hw->mac.type == e1000_82576) {
3413 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
3414 dca_txctrl |= dca_get_tag(cpu) <<
3415 E1000_DCA_TXCTRL_CPUID_SHIFT;
3416 } else {
3417 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
3418 dca_txctrl |= dca_get_tag(cpu);
3419 }
fe4506b6
JC		 3420 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
3421 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
3422 tx_ring->cpu = cpu;
3423 }
3424 put_cpu();
3425}
3426
3427static void igb_setup_dca(struct igb_adapter *adapter)
3428{
3429 int i;
3430
7dfc16fa 3431 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 3432 return;
3433
3434 for (i = 0; i < adapter->num_tx_queues; i++) {
3435 adapter->tx_ring[i].cpu = -1;
3436 igb_update_tx_dca(&adapter->tx_ring[i]);
3437 }
3438 for (i = 0; i < adapter->num_rx_queues; i++) {
3439 adapter->rx_ring[i].cpu = -1;
3440 igb_update_rx_dca(&adapter->rx_ring[i]);
3441 }
3442}
3443
3444static int __igb_notify_dca(struct device *dev, void *data)
3445{
3446 struct net_device *netdev = dev_get_drvdata(dev);
3447 struct igb_adapter *adapter = netdev_priv(netdev);
3448 struct e1000_hw *hw = &adapter->hw;
3449 unsigned long event = *(unsigned long *)data;
3450
3451 switch (event) {
3452 case DCA_PROVIDER_ADD:
3453 /* if already enabled, don't do it again */
7dfc16fa 3454 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 3455 break;
fe4506b6
JC		 3456 /* Always use CB2 mode, difference is masked
3457 * in the CB driver. */
3458 wr32(E1000_DCA_CTRL, 2);
3459 if (dca_add_requester(dev) == 0) {
bbd98fe4 3460 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 3461 dev_info(&adapter->pdev->dev, "DCA enabled\n");
3462 igb_setup_dca(adapter);
3463 break;
3464 }
3465 /* Fall Through since DCA is disabled. */
3466 case DCA_PROVIDER_REMOVE:
7dfc16fa 3467 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 3468 /* without this a class_device is left
3469 * hanging around in the sysfs model */
3470 dca_remove_requester(dev);
3471 dev_info(&adapter->pdev->dev, "DCA disabled\n");
7dfc16fa 3472 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 3473 wr32(E1000_DCA_CTRL, 1);
3474 }
3475 break;
3476 }
bbd98fe4 3477
fe4506b6 3478 return 0;
9d5c8243
AK		 3479}
3480
fe4506b6
JC		 3481static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
3482 void *p)
3483{
3484 int ret_val;
3485
3486 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
3487 __igb_notify_dca);
3488
3489 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
3490}
421e02f0 3491#endif /* CONFIG_IGB_DCA */
9d5c8243
AK		 3492
3493/**
3494 * igb_intr_msi - Interrupt Handler
3495 * @irq: interrupt number
3496 * @data: pointer to a network interface device structure
3497 **/
3498static irqreturn_t igb_intr_msi(int irq, void *data)
3499{
3500 struct net_device *netdev = data;
3501 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 3502 struct e1000_hw *hw = &adapter->hw;
3503 /* read ICR disables interrupts using IAM */
3504 u32 icr = rd32(E1000_ICR);
3505
6eb5a7f1 3506 igb_write_itr(adapter->rx_ring);
9d5c8243 3507
dda0e083
AD		 3508 if(icr & E1000_ICR_DOUTSYNC) {
3509 /* HW is reporting DMA is out of sync */
3510 adapter->stats.doosync++;
3511 }
3512
9d5c8243
AK		 3513 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3514 hw->mac.get_link_status = 1;
3515 if (!test_bit(__IGB_DOWN, &adapter->state))
3516 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3517 }
3518
288379f0 3519 napi_schedule(&adapter->rx_ring[0].napi);
9d5c8243
AK		 3520
3521 return IRQ_HANDLED;
3522}
3523
3524/**
4a3c6433 3525 * igb_intr - Legacy Interrupt Handler
9d5c8243
AK		 3526 * @irq: interrupt number
3527 * @data: pointer to a network interface device structure
3528 **/
3529static irqreturn_t igb_intr(int irq, void *data)
3530{
3531 struct net_device *netdev = data;
3532 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 3533 struct e1000_hw *hw = &adapter->hw;
3534 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
3535 * need for the IMC write */
3536 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 3537 if (!icr)
3538 return IRQ_NONE; /* Not our interrupt */
3539
6eb5a7f1 3540 igb_write_itr(adapter->rx_ring);
9d5c8243
AK		 3541
3542 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
3543 * not set, then the adapter didn't send an interrupt */
3544 if (!(icr & E1000_ICR_INT_ASSERTED))
3545 return IRQ_NONE;
3546
dda0e083
AD		 3547 if(icr & E1000_ICR_DOUTSYNC) {
3548 /* HW is reporting DMA is out of sync */
3549 adapter->stats.doosync++;
3550 }
3551
9d5c8243
AK		 3552 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3553 hw->mac.get_link_status = 1;
3554 /* guard against interrupt when we're going down */
3555 if (!test_bit(__IGB_DOWN, &adapter->state))
3556 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3557 }
3558
288379f0 3559 napi_schedule(&adapter->rx_ring[0].napi);
9d5c8243
AK		 3560
3561 return IRQ_HANDLED;
3562}
3563
3564/**
661086df
PWJ		 3565 * igb_poll - NAPI Rx polling callback
3566 * @napi: napi polling structure
3567 * @budget: count of how many packets we should handle
9d5c8243 3568 **/
661086df 3569static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 3570{
661086df
PWJ		 3571 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3572 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 3573 struct net_device *netdev = adapter->netdev;
661086df 3574 int tx_clean_complete, work_done = 0;
9d5c8243 3575
661086df 3576 /* this poll routine only supports one tx and one rx queue */
421e02f0 3577#ifdef CONFIG_IGB_DCA
7dfc16fa 3578 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3579 igb_update_tx_dca(&adapter->tx_ring[0]);
3580#endif
661086df 3581 tx_clean_complete = igb_clean_tx_irq(&adapter->tx_ring[0]);
fe4506b6 3582
421e02f0 3583#ifdef CONFIG_IGB_DCA
7dfc16fa 3584 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3585 igb_update_rx_dca(&adapter->rx_ring[0]);
3586#endif
661086df 3587 igb_clean_rx_irq_adv(&adapter->rx_ring[0], &work_done, budget);
9d5c8243
AK		 3588
3589 /* If no Tx and not enough Rx work done, exit the polling mode */
3590 if ((tx_clean_complete && (work_done < budget)) ||
3591 !netif_running(netdev)) {
9d5c8243 3592 if (adapter->itr_setting & 3)
6eb5a7f1 3593 igb_set_itr(adapter);
288379f0 3594 napi_complete(napi);
9d5c8243
AK		 3595 if (!test_bit(__IGB_DOWN, &adapter->state))
3596 igb_irq_enable(adapter);
3597 return 0;
3598 }
3599
3600 return 1;
3601}
3602
3603static int igb_clean_rx_ring_msix(struct napi_struct *napi, int budget)
3604{
3605 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3606 struct igb_adapter *adapter = rx_ring->adapter;
3607 struct e1000_hw *hw = &adapter->hw;
3608 struct net_device *netdev = adapter->netdev;
3609 int work_done = 0;
3610
421e02f0 3611#ifdef CONFIG_IGB_DCA
7dfc16fa 3612 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3613 igb_update_rx_dca(rx_ring);
3614#endif
3b644cf6 3615 igb_clean_rx_irq_adv(rx_ring, &work_done, budget);
9d5c8243
AK		 3616
3617
3618 /* If not enough Rx work done, exit the polling mode */
3619 if ((work_done == 0) || !netif_running(netdev)) {
288379f0 3620 napi_complete(napi);
9d5c8243 3621
6eb5a7f1
AD		 3622 if (adapter->itr_setting & 3) {
3623 if (adapter->num_rx_queues == 1)
3624 igb_set_itr(adapter);
3625 else
3626 igb_update_ring_itr(rx_ring);
9d5c8243 3627 }
844290e5
PW		 3628
3629 if (!test_bit(__IGB_DOWN, &adapter->state))
3630 wr32(E1000_EIMS, rx_ring->eims_value);
3631
9d5c8243
AK		 3632 return 0;
3633 }
3634
3635 return 1;
3636}
6d8126f9 3637
9d5c8243
AK		 3638/**
3639 * igb_clean_tx_irq - Reclaim resources after transmit completes
3640 * @adapter: board private structure
3641 * returns true if ring is completely cleaned
3642 **/
3b644cf6 3643static bool igb_clean_tx_irq(struct igb_ring *tx_ring)
9d5c8243 3644{
3b644cf6 3645 struct igb_adapter *adapter = tx_ring->adapter;
3b644cf6 3646 struct net_device *netdev = adapter->netdev;
0e014cb1 3647 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 3648 struct igb_buffer *buffer_info;
3649 struct sk_buff *skb;
0e014cb1 3650 union e1000_adv_tx_desc *tx_desc, *eop_desc;
9d5c8243 3651 unsigned int total_bytes = 0, total_packets = 0;
0e014cb1
AD		 3652 unsigned int i, eop, count = 0;
3653 bool cleaned = false;
9d5c8243 3654
9d5c8243 3655 i = tx_ring->next_to_clean;
0e014cb1
AD		 3656 eop = tx_ring->buffer_info[i].next_to_watch;
3657 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
3658
3659 while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) &&
3660 (count < tx_ring->count)) {
3661 for (cleaned = false; !cleaned; count++) {
3662 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
9d5c8243 3663 buffer_info = &tx_ring->buffer_info[i];
0e014cb1 3664 cleaned = (i == eop);
9d5c8243
AK		 3665 skb = buffer_info->skb;
3666
3667 if (skb) {
3668 unsigned int segs, bytecount;
3669 /* gso_segs is currently only valid for tcp */
3670 segs = skb_shinfo(skb)->gso_segs ?: 1;
3671 /* multiply data chunks by size of headers */
3672 bytecount = ((segs - 1) * skb_headlen(skb)) +
3673 skb->len;
3674 total_packets += segs;
3675 total_bytes += bytecount;
3676 }
3677
3678 igb_unmap_and_free_tx_resource(adapter, buffer_info);
0e014cb1 3679 tx_desc->wb.status = 0;
9d5c8243
AK		 3680
3681 i++;
3682 if (i == tx_ring->count)
3683 i = 0;
9d5c8243 3684 }
0e014cb1
AD		 3685
3686 eop = tx_ring->buffer_info[i].next_to_watch;
3687 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
3688 }
3689
9d5c8243
AK		 3690 tx_ring->next_to_clean = i;
3691
fc7d345d 3692 if (unlikely(count &&
9d5c8243
AK		 3693 netif_carrier_ok(netdev) &&
3694 IGB_DESC_UNUSED(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
3695 /* Make sure that anybody stopping the queue after this
3696 * sees the new next_to_clean.
3697 */
3698 smp_mb();
661086df
PWJ		 3699 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
3700 !(test_bit(__IGB_DOWN, &adapter->state))) {
3701 netif_wake_subqueue(netdev, tx_ring->queue_index);
3702 ++adapter->restart_queue;
3703 }
9d5c8243
AK		 3704 }
3705
3706 if (tx_ring->detect_tx_hung) {
3707 /* Detect a transmit hang in hardware, this serializes the
3708 * check with the clearing of time_stamp and movement of i */
3709 tx_ring->detect_tx_hung = false;
3710 if (tx_ring->buffer_info[i].time_stamp &&
3711 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
3712 (adapter->tx_timeout_factor * HZ))
3713 && !(rd32(E1000_STATUS) &
3714 E1000_STATUS_TXOFF)) {
3715
9d5c8243
AK		 3716 /* detected Tx unit hang */
3717 dev_err(&adapter->pdev->dev,
3718 "Detected Tx Unit Hang\n"
2d064c06 3719 " Tx Queue <%d>\n"
9d5c8243
AK		 3720 " TDH <%x>\n"
3721 " TDT <%x>\n"
3722 " next_to_use <%x>\n"
3723 " next_to_clean <%x>\n"
9d5c8243
AK		 3724 "buffer_info[next_to_clean]\n"
3725 " time_stamp <%lx>\n"
0e014cb1 3726 " next_to_watch <%x>\n"
9d5c8243
AK		 3727 " jiffies <%lx>\n"
3728 " desc.status <%x>\n",
2d064c06 3729 tx_ring->queue_index,
9d5c8243
AK		 3730 readl(adapter->hw.hw_addr + tx_ring->head),
3731 readl(adapter->hw.hw_addr + tx_ring->tail),
3732 tx_ring->next_to_use,
3733 tx_ring->next_to_clean,
9d5c8243 3734 tx_ring->buffer_info[i].time_stamp,
0e014cb1 3735 eop,
9d5c8243 3736 jiffies,
0e014cb1 3737 eop_desc->wb.status);
661086df 3738 netif_stop_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 3739 }
3740 }
3741 tx_ring->total_bytes += total_bytes;
3742 tx_ring->total_packets += total_packets;
e21ed353
AD		 3743 tx_ring->tx_stats.bytes += total_bytes;
3744 tx_ring->tx_stats.packets += total_packets;
9d5c8243
AK		 3745 adapter->net_stats.tx_bytes += total_bytes;
3746 adapter->net_stats.tx_packets += total_packets;
0e014cb1 3747 return (count < tx_ring->count);
9d5c8243
AK		 3748}
3749
9d5c8243
AK		 3750/**
3751 * igb_receive_skb - helper function to handle rx indications
eebbbdba 3752 * @ring: pointer to receive ring receving this packet
9d5c8243
AK		 3753 * @status: descriptor status field as written by hardware
3754 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
3755 * @skb: pointer to sk_buff to be indicated to stack
3756 **/
d3352520
AD		 3757static void igb_receive_skb(struct igb_ring *ring, u8 status,
3758 union e1000_adv_rx_desc * rx_desc,
3759 struct sk_buff *skb)
3760{
3761 struct igb_adapter * adapter = ring->adapter;
3762 bool vlan_extracted = (adapter->vlgrp && (status & E1000_RXD_STAT_VP));
3763
0c8dfc83 3764 skb_record_rx_queue(skb, ring->queue_index);
5c0999b7 3765 if (skb->ip_summed == CHECKSUM_UNNECESSARY) {
d3352520 3766 if (vlan_extracted)
5c0999b7
HX		 3767 vlan_gro_receive(&ring->napi, adapter->vlgrp,
3768 le16_to_cpu(rx_desc->wb.upper.vlan),
3769 skb);
d3352520 3770 else
5c0999b7 3771 napi_gro_receive(&ring->napi, skb);
d3352520 3772 } else {
d3352520
AD		 3773 if (vlan_extracted)
3774 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
3775 le16_to_cpu(rx_desc->wb.upper.vlan));
3776 else
d3352520 3777 netif_receive_skb(skb);
d3352520 3778 }
9d5c8243
AK		 3779}
3780
3781
3782static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
3783 u32 status_err, struct sk_buff *skb)
3784{
3785 skb->ip_summed = CHECKSUM_NONE;
3786
3787 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
3788 if ((status_err & E1000_RXD_STAT_IXSM) || !adapter->rx_csum)
3789 return;
3790 /* TCP/UDP checksum error bit is set */
3791 if (status_err &
3792 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
3793 /* let the stack verify checksum errors */
3794 adapter->hw_csum_err++;
3795 return;
3796 }
3797 /* It must be a TCP or UDP packet with a valid checksum */
3798 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
3799 skb->ip_summed = CHECKSUM_UNNECESSARY;
3800
3801 adapter->hw_csum_good++;
3802}
3803
3b644cf6
MW		 3804static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring,
3805 int *work_done, int budget)
9d5c8243 3806{
3b644cf6 3807 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 3808 struct net_device *netdev = adapter->netdev;
3809 struct pci_dev *pdev = adapter->pdev;
3810 union e1000_adv_rx_desc *rx_desc , *next_rxd;
3811 struct igb_buffer *buffer_info , *next_buffer;
3812 struct sk_buff *skb;
bf36c1a0 3813 unsigned int i;
9d5c8243
AK		 3814 u32 length, hlen, staterr;
3815 bool cleaned = false;
3816 int cleaned_count = 0;
3817 unsigned int total_bytes = 0, total_packets = 0;
3818
3819 i = rx_ring->next_to_clean;
69d3ca53 3820 buffer_info = &rx_ring->buffer_info[i];
9d5c8243
AK		 3821 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3822 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3823
3824 while (staterr & E1000_RXD_STAT_DD) {
3825 if (*work_done >= budget)
3826 break;
3827 (*work_done)++;
9d5c8243 3828
69d3ca53
AD		 3829 skb = buffer_info->skb;
3830 prefetch(skb->data - NET_IP_ALIGN);
3831 buffer_info->skb = NULL;
3832
3833 i++;
3834 if (i == rx_ring->count)
3835 i = 0;
3836 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
3837 prefetch(next_rxd);
3838 next_buffer = &rx_ring->buffer_info[i];
9d5c8243
AK		 3839
3840 length = le16_to_cpu(rx_desc->wb.upper.length);
3841 cleaned = true;
3842 cleaned_count++;
3843
bf36c1a0
AD		 3844 if (!adapter->rx_ps_hdr_size) {
3845 pci_unmap_single(pdev, buffer_info->dma,
3846 adapter->rx_buffer_len +
3847 NET_IP_ALIGN,
3848 PCI_DMA_FROMDEVICE);
3849 skb_put(skb, length);
3850 goto send_up;
9d5c8243
AK		 3851 }
3852
69d3ca53
AD		 3853 /* HW will not DMA in data larger than the given buffer, even
3854 * if it parses the (NFS, of course) header to be larger. In
3855 * that case, it fills the header buffer and spills the rest
3856 * into the page.
3857 */
3858 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
3859 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
3860 if (hlen > adapter->rx_ps_hdr_size)
3861 hlen = adapter->rx_ps_hdr_size;
3862
bf36c1a0
AD		 3863 if (!skb_shinfo(skb)->nr_frags) {
3864 pci_unmap_single(pdev, buffer_info->dma,
3865 adapter->rx_ps_hdr_size +
3866 NET_IP_ALIGN,
3867 PCI_DMA_FROMDEVICE);
3868 skb_put(skb, hlen);
3869 }
3870
3871 if (length) {
9d5c8243 3872 pci_unmap_page(pdev, buffer_info->page_dma,
bf36c1a0 3873 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9d5c8243 3874 buffer_info->page_dma = 0;
bf36c1a0
AD		 3875
3876 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
3877 buffer_info->page,
3878 buffer_info->page_offset,
3879 length);
3880
3881 if ((adapter->rx_buffer_len > (PAGE_SIZE / 2)) ||
3882 (page_count(buffer_info->page) != 1))
3883 buffer_info->page = NULL;
3884 else
3885 get_page(buffer_info->page);
9d5c8243
AK		 3886
3887 skb->len += length;
3888 skb->data_len += length;
9d5c8243 3889
bf36c1a0 3890 skb->truesize += length;
9d5c8243 3891 }
9d5c8243 3892
bf36c1a0 3893 if (!(staterr & E1000_RXD_STAT_EOP)) {
b2d56536
AD		 3894 buffer_info->skb = next_buffer->skb;
3895 buffer_info->dma = next_buffer->dma;
3896 next_buffer->skb = skb;
3897 next_buffer->dma = 0;
bf36c1a0
AD		 3898 goto next_desc;
3899 }
69d3ca53 3900send_up:
9d5c8243
AK		 3901 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
3902 dev_kfree_skb_irq(skb);
3903 goto next_desc;
3904 }
9d5c8243
AK		 3905
3906 total_bytes += skb->len;
3907 total_packets++;
3908
3909 igb_rx_checksum_adv(adapter, staterr, skb);
3910
3911 skb->protocol = eth_type_trans(skb, netdev);
3912
d3352520 3913 igb_receive_skb(rx_ring, staterr, rx_desc, skb);
9d5c8243 3914
9d5c8243
AK		 3915next_desc:
3916 rx_desc->wb.upper.status_error = 0;
3917
3918 /* return some buffers to hardware, one at a time is too slow */
3919 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
3b644cf6 3920 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 3921 cleaned_count = 0;
3922 }
3923
3924 /* use prefetched values */
3925 rx_desc = next_rxd;
3926 buffer_info = next_buffer;
9d5c8243
AK		 3927 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3928 }
bf36c1a0 3929
9d5c8243
AK		 3930 rx_ring->next_to_clean = i;
3931 cleaned_count = IGB_DESC_UNUSED(rx_ring);
3932
3933 if (cleaned_count)
3b644cf6 3934 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 3935
3936 rx_ring->total_packets += total_packets;
3937 rx_ring->total_bytes += total_bytes;
3938 rx_ring->rx_stats.packets += total_packets;
3939 rx_ring->rx_stats.bytes += total_bytes;
3940 adapter->net_stats.rx_bytes += total_bytes;
3941 adapter->net_stats.rx_packets += total_packets;
3942 return cleaned;
3943}
3944
3945
3946/**
3947 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
3948 * @adapter: address of board private structure
3949 **/
3b644cf6 3950static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
9d5c8243
AK		 3951 int cleaned_count)
3952{
3b644cf6 3953 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 3954 struct net_device *netdev = adapter->netdev;
3955 struct pci_dev *pdev = adapter->pdev;
3956 union e1000_adv_rx_desc *rx_desc;
3957 struct igb_buffer *buffer_info;
3958 struct sk_buff *skb;
3959 unsigned int i;
db761762 3960 int bufsz;
9d5c8243
AK		 3961
3962 i = rx_ring->next_to_use;
3963 buffer_info = &rx_ring->buffer_info[i];
3964
db761762
AD		 3965 if (adapter->rx_ps_hdr_size)
3966 bufsz = adapter->rx_ps_hdr_size;
3967 else
3968 bufsz = adapter->rx_buffer_len;
3969 bufsz += NET_IP_ALIGN;
3970
9d5c8243
AK		 3971 while (cleaned_count--) {
3972 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3973
bf36c1a0 3974 if (adapter->rx_ps_hdr_size && !buffer_info->page_dma) {
9d5c8243 3975 if (!buffer_info->page) {
bf36c1a0
AD		 3976 buffer_info->page = alloc_page(GFP_ATOMIC);
3977 if (!buffer_info->page) {
3978 adapter->alloc_rx_buff_failed++;
3979 goto no_buffers;
3980 }
3981 buffer_info->page_offset = 0;
3982 } else {
3983 buffer_info->page_offset ^= PAGE_SIZE / 2;
9d5c8243
AK		 3984 }
3985 buffer_info->page_dma =
db761762 3986 pci_map_page(pdev, buffer_info->page,
bf36c1a0
AD		 3987 buffer_info->page_offset,
3988 PAGE_SIZE / 2,
9d5c8243
AK		 3989 PCI_DMA_FROMDEVICE);
3990 }
3991
3992 if (!buffer_info->skb) {
9d5c8243 3993 skb = netdev_alloc_skb(netdev, bufsz);
9d5c8243
AK		 3994 if (!skb) {
3995 adapter->alloc_rx_buff_failed++;
3996 goto no_buffers;
3997 }
3998
3999 /* Make buffer alignment 2 beyond a 16 byte boundary
4000 * this will result in a 16 byte aligned IP header after
4001 * the 14 byte MAC header is removed
4002 */
4003 skb_reserve(skb, NET_IP_ALIGN);
4004
4005 buffer_info->skb = skb;
4006 buffer_info->dma = pci_map_single(pdev, skb->data,
4007 bufsz,
4008 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 4009 }
4010 /* Refresh the desc even if buffer_addrs didn't change because
4011 * each write-back erases this info. */
4012 if (adapter->rx_ps_hdr_size) {
4013 rx_desc->read.pkt_addr =
4014 cpu_to_le64(buffer_info->page_dma);
4015 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
4016 } else {
4017 rx_desc->read.pkt_addr =
4018 cpu_to_le64(buffer_info->dma);
4019 rx_desc->read.hdr_addr = 0;
4020 }
4021
4022 i++;
4023 if (i == rx_ring->count)
4024 i = 0;
4025 buffer_info = &rx_ring->buffer_info[i];
4026 }
4027
4028no_buffers:
4029 if (rx_ring->next_to_use != i) {
4030 rx_ring->next_to_use = i;
4031 if (i == 0)
4032 i = (rx_ring->count - 1);
4033 else
4034 i--;
4035
4036 /* Force memory writes to complete before letting h/w
4037 * know there are new descriptors to fetch. (Only
4038 * applicable for weak-ordered memory model archs,
4039 * such as IA-64). */
4040 wmb();
4041 writel(i, adapter->hw.hw_addr + rx_ring->tail);
4042 }
4043}
4044
4045/**
4046 * igb_mii_ioctl -
4047 * @netdev:
4048 * @ifreq:
4049 * @cmd:
4050 **/
4051static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4052{
4053 struct igb_adapter *adapter = netdev_priv(netdev);
4054 struct mii_ioctl_data *data = if_mii(ifr);
4055
4056 if (adapter->hw.phy.media_type != e1000_media_type_copper)
4057 return -EOPNOTSUPP;
4058
4059 switch (cmd) {
4060 case SIOCGMIIPHY:
4061 data->phy_id = adapter->hw.phy.addr;
4062 break;
4063 case SIOCGMIIREG:
4064 if (!capable(CAP_NET_ADMIN))
4065 return -EPERM;
f5f4cf08
AD		 4066 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
4067 &data->val_out))
9d5c8243
AK		 4068 return -EIO;
4069 break;
4070 case SIOCSMIIREG:
4071 default:
4072 return -EOPNOTSUPP;
4073 }
4074 return 0;
4075}
4076
4077/**
4078 * igb_ioctl -
4079 * @netdev:
4080 * @ifreq:
4081 * @cmd:
4082 **/
4083static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4084{
4085 switch (cmd) {
4086 case SIOCGMIIPHY:
4087 case SIOCGMIIREG:
4088 case SIOCSMIIREG:
4089 return igb_mii_ioctl(netdev, ifr, cmd);
4090 default:
4091 return -EOPNOTSUPP;
4092 }
4093}
4094
4095static void igb_vlan_rx_register(struct net_device *netdev,
4096 struct vlan_group *grp)
4097{
4098 struct igb_adapter *adapter = netdev_priv(netdev);
4099 struct e1000_hw *hw = &adapter->hw;
4100 u32 ctrl, rctl;
4101
4102 igb_irq_disable(adapter);
4103 adapter->vlgrp = grp;
4104
4105 if (grp) {
4106 /* enable VLAN tag insert/strip */
4107 ctrl = rd32(E1000_CTRL);
4108 ctrl |= E1000_CTRL_VME;
4109 wr32(E1000_CTRL, ctrl);
4110
4111 /* enable VLAN receive filtering */
4112 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 4113 rctl &= ~E1000_RCTL_CFIEN;
4114 wr32(E1000_RCTL, rctl);
4115 igb_update_mng_vlan(adapter);
4116 wr32(E1000_RLPML,
4117 adapter->max_frame_size + VLAN_TAG_SIZE);
4118 } else {
4119 /* disable VLAN tag insert/strip */
4120 ctrl = rd32(E1000_CTRL);
4121 ctrl &= ~E1000_CTRL_VME;
4122 wr32(E1000_CTRL, ctrl);
4123
9d5c8243
AK		 4124 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
4125 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4126 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
4127 }
4128 wr32(E1000_RLPML,
4129 adapter->max_frame_size);
4130 }
4131
4132 if (!test_bit(__IGB_DOWN, &adapter->state))
4133 igb_irq_enable(adapter);
4134}
4135
4136static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
4137{
4138 struct igb_adapter *adapter = netdev_priv(netdev);
4139 struct e1000_hw *hw = &adapter->hw;
4140 u32 vfta, index;
4141
28b0759c 4142 if ((hw->mng_cookie.status &
9d5c8243
AK		 4143 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4144 (vid == adapter->mng_vlan_id))
4145 return;
4146 /* add VID to filter table */
4147 index = (vid >> 5) & 0x7F;
4148 vfta = array_rd32(E1000_VFTA, index);
4149 vfta |= (1 << (vid & 0x1F));
4150 igb_write_vfta(&adapter->hw, index, vfta);
4151}
4152
4153static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
4154{
4155 struct igb_adapter *adapter = netdev_priv(netdev);
4156 struct e1000_hw *hw = &adapter->hw;
4157 u32 vfta, index;
4158
4159 igb_irq_disable(adapter);
4160 vlan_group_set_device(adapter->vlgrp, vid, NULL);
4161
4162 if (!test_bit(__IGB_DOWN, &adapter->state))
4163 igb_irq_enable(adapter);
4164
4165 if ((adapter->hw.mng_cookie.status &
4166 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4167 (vid == adapter->mng_vlan_id)) {
4168 /* release control to f/w */
4169 igb_release_hw_control(adapter);
4170 return;
4171 }
4172
4173 /* remove VID from filter table */
4174 index = (vid >> 5) & 0x7F;
4175 vfta = array_rd32(E1000_VFTA, index);
4176 vfta &= ~(1 << (vid & 0x1F));
4177 igb_write_vfta(&adapter->hw, index, vfta);
4178}
4179
4180static void igb_restore_vlan(struct igb_adapter *adapter)
4181{
4182 igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
4183
4184 if (adapter->vlgrp) {
4185 u16 vid;
4186 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
4187 if (!vlan_group_get_device(adapter->vlgrp, vid))
4188 continue;
4189 igb_vlan_rx_add_vid(adapter->netdev, vid);
4190 }
4191 }
4192}
4193
4194int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
4195{
4196 struct e1000_mac_info *mac = &adapter->hw.mac;
4197
4198 mac->autoneg = 0;
4199
4200 /* Fiber NICs only allow 1000 gbps Full duplex */
4201 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) &&
4202 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
4203 dev_err(&adapter->pdev->dev,
4204 "Unsupported Speed/Duplex configuration\n");
4205 return -EINVAL;
4206 }
4207
4208 switch (spddplx) {
4209 case SPEED_10 + DUPLEX_HALF:
4210 mac->forced_speed_duplex = ADVERTISE_10_HALF;
4211 break;
4212 case SPEED_10 + DUPLEX_FULL:
4213 mac->forced_speed_duplex = ADVERTISE_10_FULL;
4214 break;
4215 case SPEED_100 + DUPLEX_HALF:
4216 mac->forced_speed_duplex = ADVERTISE_100_HALF;
4217 break;
4218 case SPEED_100 + DUPLEX_FULL:
4219 mac->forced_speed_duplex = ADVERTISE_100_FULL;
4220 break;
4221 case SPEED_1000 + DUPLEX_FULL:
4222 mac->autoneg = 1;
4223 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
4224 break;
4225 case SPEED_1000 + DUPLEX_HALF: /* not supported */
4226 default:
4227 dev_err(&adapter->pdev->dev,
4228 "Unsupported Speed/Duplex configuration\n");
4229 return -EINVAL;
4230 }
4231 return 0;
4232}
4233
4234
4235static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
4236{
4237 struct net_device *netdev = pci_get_drvdata(pdev);
4238 struct igb_adapter *adapter = netdev_priv(netdev);
4239 struct e1000_hw *hw = &adapter->hw;
2d064c06 4240 u32 ctrl, rctl, status;
9d5c8243
AK		 4241 u32 wufc = adapter->wol;
4242#ifdef CONFIG_PM
4243 int retval = 0;
4244#endif
4245
4246 netif_device_detach(netdev);
4247
a88f10ec
AD		 4248 if (netif_running(netdev))
4249 igb_close(netdev);
4250
4251 igb_reset_interrupt_capability(adapter);
4252
4253 igb_free_queues(adapter);
9d5c8243
AK		 4254
4255#ifdef CONFIG_PM
4256 retval = pci_save_state(pdev);
4257 if (retval)
4258 return retval;
4259#endif
4260
4261 status = rd32(E1000_STATUS);
4262 if (status & E1000_STATUS_LU)
4263 wufc &= ~E1000_WUFC_LNKC;
4264
4265 if (wufc) {
4266 igb_setup_rctl(adapter);
4267 igb_set_multi(netdev);
4268
4269 /* turn on all-multi mode if wake on multicast is enabled */
4270 if (wufc & E1000_WUFC_MC) {
4271 rctl = rd32(E1000_RCTL);
4272 rctl |= E1000_RCTL_MPE;
4273 wr32(E1000_RCTL, rctl);
4274 }
4275
4276 ctrl = rd32(E1000_CTRL);
4277 /* advertise wake from D3Cold */
4278 #define E1000_CTRL_ADVD3WUC 0x00100000
4279 /* phy power management enable */
4280 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
4281 ctrl |= E1000_CTRL_ADVD3WUC;
4282 wr32(E1000_CTRL, ctrl);
4283
9d5c8243
AK		 4284 /* Allow time for pending master requests to run */
4285 igb_disable_pcie_master(&adapter->hw);
4286
4287 wr32(E1000_WUC, E1000_WUC_PME_EN);
4288 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 4289 } else {
4290 wr32(E1000_WUC, 0);
4291 wr32(E1000_WUFC, 0);
9d5c8243
AK		 4292 }
4293
2d064c06
AD		 4294 /* make sure adapter isn't asleep if manageability/wol is enabled */
4295 if (wufc || adapter->en_mng_pt) {
9d5c8243
AK		 4296 pci_enable_wake(pdev, PCI_D3hot, 1);
4297 pci_enable_wake(pdev, PCI_D3cold, 1);
2d064c06
AD		 4298 } else {
4299 igb_shutdown_fiber_serdes_link_82575(hw);
4300 pci_enable_wake(pdev, PCI_D3hot, 0);
4301 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243
AK		 4302 }
4303
4304 /* Release control of h/w to f/w. If f/w is AMT enabled, this
4305 * would have already happened in close and is redundant. */
4306 igb_release_hw_control(adapter);
4307
4308 pci_disable_device(pdev);
4309
4310 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4311
4312 return 0;
4313}
4314
4315#ifdef CONFIG_PM
4316static int igb_resume(struct pci_dev *pdev)
4317{
4318 struct net_device *netdev = pci_get_drvdata(pdev);
4319 struct igb_adapter *adapter = netdev_priv(netdev);
4320 struct e1000_hw *hw = &adapter->hw;
4321 u32 err;
4322
4323 pci_set_power_state(pdev, PCI_D0);
4324 pci_restore_state(pdev);
42bfd33a 4325
aed5dec3 4326 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 4327 if (err) {
4328 dev_err(&pdev->dev,
4329 "igb: Cannot enable PCI device from suspend\n");
4330 return err;
4331 }
4332 pci_set_master(pdev);
4333
4334 pci_enable_wake(pdev, PCI_D3hot, 0);
4335 pci_enable_wake(pdev, PCI_D3cold, 0);
4336
a88f10ec
AD		 4337 igb_set_interrupt_capability(adapter);
4338
4339 if (igb_alloc_queues(adapter)) {
4340 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
4341 return -ENOMEM;
9d5c8243
AK		 4342 }
4343
4344 /* e1000_power_up_phy(adapter); */
4345
4346 igb_reset(adapter);
a8564f03
AD		 4347
4348 /* let the f/w know that the h/w is now under the control of the
4349 * driver. */
4350 igb_get_hw_control(adapter);
4351
9d5c8243
AK		 4352 wr32(E1000_WUS, ~0);
4353
a88f10ec
AD		 4354 if (netif_running(netdev)) {
4355 err = igb_open(netdev);
4356 if (err)
4357 return err;
4358 }
9d5c8243
AK		 4359
4360 netif_device_attach(netdev);
4361
9d5c8243
AK		 4362 return 0;
4363}
4364#endif
4365
4366static void igb_shutdown(struct pci_dev *pdev)
4367{
4368 igb_suspend(pdev, PMSG_SUSPEND);
4369}
4370
4371#ifdef CONFIG_NET_POLL_CONTROLLER
4372/*
4373 * Polling 'interrupt' - used by things like netconsole to send skbs
4374 * without having to re-enable interrupts. It's not called while
4375 * the interrupt routine is executing.
4376 */
4377static void igb_netpoll(struct net_device *netdev)
4378{
4379 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 4380 struct e1000_hw *hw = &adapter->hw;
9d5c8243 4381 int i;
9d5c8243 4382
eebbbdba
AD		 4383 if (!adapter->msix_entries) {
4384 igb_irq_disable(adapter);
4385 napi_schedule(&adapter->rx_ring[0].napi);
4386 return;
4387 }
9d5c8243 4388
eebbbdba
AD		 4389 for (i = 0; i < adapter->num_tx_queues; i++) {
4390 struct igb_ring *tx_ring = &adapter->tx_ring[i];
4391 wr32(E1000_EIMC, tx_ring->eims_value);
4392 igb_clean_tx_irq(tx_ring);
4393 wr32(E1000_EIMS, tx_ring->eims_value);
4394 }
9d5c8243 4395
eebbbdba
AD		 4396 for (i = 0; i < adapter->num_rx_queues; i++) {
4397 struct igb_ring *rx_ring = &adapter->rx_ring[i];
4398 wr32(E1000_EIMC, rx_ring->eims_value);
4399 napi_schedule(&rx_ring->napi);
4400 }
9d5c8243
AK		 4401}
4402#endif /* CONFIG_NET_POLL_CONTROLLER */
4403
4404/**
4405 * igb_io_error_detected - called when PCI error is detected
4406 * @pdev: Pointer to PCI device
4407 * @state: The current pci connection state
4408 *
4409 * This function is called after a PCI bus error affecting
4410 * this device has been detected.
4411 */
4412static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
4413 pci_channel_state_t state)
4414{
4415 struct net_device *netdev = pci_get_drvdata(pdev);
4416 struct igb_adapter *adapter = netdev_priv(netdev);
4417
4418 netif_device_detach(netdev);
4419
4420 if (netif_running(netdev))
4421 igb_down(adapter);
4422 pci_disable_device(pdev);
4423
4424 /* Request a slot slot reset. */
4425 return PCI_ERS_RESULT_NEED_RESET;
4426}
4427
4428/**
4429 * igb_io_slot_reset - called after the pci bus has been reset.
4430 * @pdev: Pointer to PCI device
4431 *
4432 * Restart the card from scratch, as if from a cold-boot. Implementation
4433 * resembles the first-half of the igb_resume routine.
4434 */
4435static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
4436{
4437 struct net_device *netdev = pci_get_drvdata(pdev);
4438 struct igb_adapter *adapter = netdev_priv(netdev);
4439 struct e1000_hw *hw = &adapter->hw;
40a914fa 4440 pci_ers_result_t result;
42bfd33a 4441 int err;
9d5c8243 4442
aed5dec3 4443 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 4444 dev_err(&pdev->dev,
4445 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 4446 result = PCI_ERS_RESULT_DISCONNECT;
4447 } else {
4448 pci_set_master(pdev);
4449 pci_restore_state(pdev);
9d5c8243 4450
40a914fa
AD		 4451 pci_enable_wake(pdev, PCI_D3hot, 0);
4452 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 4453
40a914fa
AD		 4454 igb_reset(adapter);
4455 wr32(E1000_WUS, ~0);
4456 result = PCI_ERS_RESULT_RECOVERED;
4457 }
9d5c8243 4458
ea943d41
JK		 4459 err = pci_cleanup_aer_uncorrect_error_status(pdev);
4460 if (err) {
4461 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
4462 "failed 0x%0x\n", err);
4463 /* non-fatal, continue */
4464 }
40a914fa
AD		 4465
4466 return result;
9d5c8243
AK		 4467}
4468
4469/**
4470 * igb_io_resume - called when traffic can start flowing again.
4471 * @pdev: Pointer to PCI device
4472 *
4473 * This callback is called when the error recovery driver tells us that
4474 * its OK to resume normal operation. Implementation resembles the
4475 * second-half of the igb_resume routine.
4476 */
4477static void igb_io_resume(struct pci_dev *pdev)
4478{
4479 struct net_device *netdev = pci_get_drvdata(pdev);
4480 struct igb_adapter *adapter = netdev_priv(netdev);
4481
9d5c8243
AK		 4482 if (netif_running(netdev)) {
4483 if (igb_up(adapter)) {
4484 dev_err(&pdev->dev, "igb_up failed after reset\n");
4485 return;
4486 }
4487 }
4488
4489 netif_device_attach(netdev);
4490
4491 /* let the f/w know that the h/w is now under the control of the
4492 * driver. */
4493 igb_get_hw_control(adapter);
9d5c8243
AK		 4494}
4495
4496/* igb_main.c */
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