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igb: support wol on second port
[mirror_ubuntu-zesty-kernel.git] / drivers / net / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
86d5d38f 4 Copyright(c) 2007-2009 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/module.h>
29#include <linux/types.h>
30#include <linux/init.h>
31#include <linux/vmalloc.h>
32#include <linux/pagemap.h>
33#include <linux/netdevice.h>
9d5c8243
AK		 34#include <linux/ipv6.h>
35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
c6cb090b 37#include <linux/net_tstamp.h>
9d5c8243
AK		 38#include <linux/mii.h>
39#include <linux/ethtool.h>
40#include <linux/if_vlan.h>
41#include <linux/pci.h>
c54106bb 42#include <linux/pci-aspm.h>
9d5c8243
AK		 43#include <linux/delay.h>
44#include <linux/interrupt.h>
45#include <linux/if_ether.h>
40a914fa 46#include <linux/aer.h>
421e02f0 47#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 48#include <linux/dca.h>
49#endif
9d5c8243
AK		 50#include "igb.h"
51
86d5d38f 52#define DRV_VERSION "1.3.16-k2"
9d5c8243
AK		 53char igb_driver_name[] = "igb";
54char igb_driver_version[] = DRV_VERSION;
55static const char igb_driver_string[] =
56 "Intel(R) Gigabit Ethernet Network Driver";
86d5d38f 57static const char igb_copyright[] = "Copyright (c) 2007-2009 Intel Corporation.";
9d5c8243 58
9d5c8243
AK		 59static const struct e1000_info *igb_info_tbl[] = {
60 [board_82575] = &e1000_82575_info,
61};
62
63static struct pci_device_id igb_pci_tbl[] = {
2d064c06
AD		 64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
9d5c8243
AK		 67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
70 /* required last entry */
71 {0, }
72};
73
74MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
75
76void igb_reset(struct igb_adapter *);
77static int igb_setup_all_tx_resources(struct igb_adapter *);
78static int igb_setup_all_rx_resources(struct igb_adapter *);
79static void igb_free_all_tx_resources(struct igb_adapter *);
80static void igb_free_all_rx_resources(struct igb_adapter *);
9d5c8243
AK		 81void igb_update_stats(struct igb_adapter *);
82static int igb_probe(struct pci_dev *, const struct pci_device_id *);
83static void __devexit igb_remove(struct pci_dev *pdev);
84static int igb_sw_init(struct igb_adapter *);
85static int igb_open(struct net_device *);
86static int igb_close(struct net_device *);
87static void igb_configure_tx(struct igb_adapter *);
88static void igb_configure_rx(struct igb_adapter *);
89static void igb_setup_rctl(struct igb_adapter *);
90static void igb_clean_all_tx_rings(struct igb_adapter *);
91static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 92static void igb_clean_tx_ring(struct igb_ring *);
93static void igb_clean_rx_ring(struct igb_ring *);
9d5c8243
AK		 94static void igb_set_multi(struct net_device *);
95static void igb_update_phy_info(unsigned long);
96static void igb_watchdog(unsigned long);
97static void igb_watchdog_task(struct work_struct *);
98static int igb_xmit_frame_ring_adv(struct sk_buff *, struct net_device *,
99 struct igb_ring *);
100static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
101static struct net_device_stats *igb_get_stats(struct net_device *);
102static int igb_change_mtu(struct net_device *, int);
103static int igb_set_mac(struct net_device *, void *);
104static irqreturn_t igb_intr(int irq, void *);
105static irqreturn_t igb_intr_msi(int irq, void *);
106static irqreturn_t igb_msix_other(int irq, void *);
107static irqreturn_t igb_msix_rx(int irq, void *);
108static irqreturn_t igb_msix_tx(int irq, void *);
421e02f0 109#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 110static void igb_update_rx_dca(struct igb_ring *);
111static void igb_update_tx_dca(struct igb_ring *);
112static void igb_setup_dca(struct igb_adapter *);
421e02f0 113#endif /* CONFIG_IGB_DCA */
3b644cf6 114static bool igb_clean_tx_irq(struct igb_ring *);
661086df 115static int igb_poll(struct napi_struct *, int);
3b644cf6
MW		 116static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int);
117static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
9d5c8243
AK		 118static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
119static void igb_tx_timeout(struct net_device *);
120static void igb_reset_task(struct work_struct *);
121static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
122static void igb_vlan_rx_add_vid(struct net_device *, u16);
123static void igb_vlan_rx_kill_vid(struct net_device *, u16);
124static void igb_restore_vlan(struct igb_adapter *);
4ae196df
AD		 125static void igb_ping_all_vfs(struct igb_adapter *);
126static void igb_msg_task(struct igb_adapter *);
127static int igb_rcv_msg_from_vf(struct igb_adapter *, u32);
e1739522
AD		 128static inline void igb_set_rah_pool(struct e1000_hw *, int , int);
129static void igb_set_mc_list_pools(struct igb_adapter *, int, u16);
4ae196df 130static void igb_vmm_control(struct igb_adapter *);
e1739522 131static inline void igb_set_vmolr(struct e1000_hw *, int);
4ae196df
AD		 132static inline int igb_set_vf_rlpml(struct igb_adapter *, int, int);
133static int igb_set_vf_mac(struct igb_adapter *adapter, int, unsigned char *);
134static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
9d5c8243
AK		 135
136static int igb_suspend(struct pci_dev *, pm_message_t);
137#ifdef CONFIG_PM
138static int igb_resume(struct pci_dev *);
139#endif
140static void igb_shutdown(struct pci_dev *);
421e02f0 141#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 142static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
143static struct notifier_block dca_notifier = {
144 .notifier_call = igb_notify_dca,
145 .next = NULL,
146 .priority = 0
147};
148#endif
9d5c8243
AK		 149#ifdef CONFIG_NET_POLL_CONTROLLER
150/* for netdump / net console */
151static void igb_netpoll(struct net_device *);
152#endif
153
37680117
AD		 154#ifdef CONFIG_PCI_IOV
155static ssize_t igb_set_num_vfs(struct device *, struct device_attribute *,
156 const char *, size_t);
157static ssize_t igb_show_num_vfs(struct device *, struct device_attribute *,
158 char *);
159DEVICE_ATTR(num_vfs, S_IRUGO | S_IWUSR, igb_show_num_vfs, igb_set_num_vfs);
160#endif
9d5c8243
AK		 161static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
162 pci_channel_state_t);
163static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
164static void igb_io_resume(struct pci_dev *);
165
166static struct pci_error_handlers igb_err_handler = {
167 .error_detected = igb_io_error_detected,
168 .slot_reset = igb_io_slot_reset,
169 .resume = igb_io_resume,
170};
171
172
173static struct pci_driver igb_driver = {
174 .name = igb_driver_name,
175 .id_table = igb_pci_tbl,
176 .probe = igb_probe,
177 .remove = __devexit_p(igb_remove),
178#ifdef CONFIG_PM
179 /* Power Managment Hooks */
180 .suspend = igb_suspend,
181 .resume = igb_resume,
182#endif
183 .shutdown = igb_shutdown,
184 .err_handler = &igb_err_handler
185};
186
7dfc16fa
AD		 187static int global_quad_port_a; /* global quad port a indication */
188
9d5c8243
AK		 189MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
190MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
191MODULE_LICENSE("GPL");
192MODULE_VERSION(DRV_VERSION);
193
38c845c7
PO		 194/**
195 * Scale the NIC clock cycle by a large factor so that
196 * relatively small clock corrections can be added or
197 * substracted at each clock tick. The drawbacks of a
198 * large factor are a) that the clock register overflows
199 * more quickly (not such a big deal) and b) that the
200 * increment per tick has to fit into 24 bits.
201 *
202 * Note that
203 * TIMINCA = IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS *
204 * IGB_TSYNC_SCALE
205 * TIMINCA += TIMINCA * adjustment [ppm] / 1e9
206 *
207 * The base scale factor is intentionally a power of two
208 * so that the division in %struct timecounter can be done with
209 * a shift.
210 */
211#define IGB_TSYNC_SHIFT (19)
212#define IGB_TSYNC_SCALE (1<<IGB_TSYNC_SHIFT)
213
214/**
215 * The duration of one clock cycle of the NIC.
216 *
217 * @todo This hard-coded value is part of the specification and might change
218 * in future hardware revisions. Add revision check.
219 */
220#define IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS 16
221
222#if (IGB_TSYNC_SCALE * IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS) >= (1<<24)
223# error IGB_TSYNC_SCALE and/or IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS are too large to fit into TIMINCA
224#endif
225
226/**
227 * igb_read_clock - read raw cycle counter (to be used by time counter)
228 */
229static cycle_t igb_read_clock(const struct cyclecounter *tc)
230{
231 struct igb_adapter *adapter =
232 container_of(tc, struct igb_adapter, cycles);
233 struct e1000_hw *hw = &adapter->hw;
234 u64 stamp;
235
236 stamp = rd32(E1000_SYSTIML);
237 stamp |= (u64)rd32(E1000_SYSTIMH) << 32ULL;
238
239 return stamp;
240}
241
9d5c8243
AK		 242#ifdef DEBUG
243/**
244 * igb_get_hw_dev_name - return device name string
245 * used by hardware layer to print debugging information
246 **/
247char *igb_get_hw_dev_name(struct e1000_hw *hw)
248{
249 struct igb_adapter *adapter = hw->back;
250 return adapter->netdev->name;
251}
38c845c7
PO		 252
253/**
254 * igb_get_time_str - format current NIC and system time as string
255 */
256static char *igb_get_time_str(struct igb_adapter *adapter,
257 char buffer[160])
258{
259 cycle_t hw = adapter->cycles.read(&adapter->cycles);
260 struct timespec nic = ns_to_timespec(timecounter_read(&adapter->clock));
261 struct timespec sys;
262 struct timespec delta;
263 getnstimeofday(&sys);
264
265 delta = timespec_sub(nic, sys);
266
267 sprintf(buffer,
33af6bcc
PO		 268 "HW %llu, NIC %ld.%09lus, SYS %ld.%09lus, NIC-SYS %lds + %09luns",
269 hw,
38c845c7
PO		 270 (long)nic.tv_sec, nic.tv_nsec,
271 (long)sys.tv_sec, sys.tv_nsec,
272 (long)delta.tv_sec, delta.tv_nsec);
273
274 return buffer;
275}
9d5c8243
AK		 276#endif
277
278/**
279 * igb_init_module - Driver Registration Routine
280 *
281 * igb_init_module is the first routine called when the driver is
282 * loaded. All it does is register with the PCI subsystem.
283 **/
284static int __init igb_init_module(void)
285{
286 int ret;
287 printk(KERN_INFO "%s - version %s\n",
288 igb_driver_string, igb_driver_version);
289
290 printk(KERN_INFO "%s\n", igb_copyright);
291
7dfc16fa
AD		 292 global_quad_port_a = 0;
293
421e02f0 294#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 295 dca_register_notify(&dca_notifier);
296#endif
bbd98fe4
AD		 297
298 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 299 return ret;
300}
301
302module_init(igb_init_module);
303
304/**
305 * igb_exit_module - Driver Exit Cleanup Routine
306 *
307 * igb_exit_module is called just before the driver is removed
308 * from memory.
309 **/
310static void __exit igb_exit_module(void)
311{
421e02f0 312#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 313 dca_unregister_notify(&dca_notifier);
314#endif
9d5c8243
AK		 315 pci_unregister_driver(&igb_driver);
316}
317
318module_exit(igb_exit_module);
319
26bc19ec
AD		 320#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
321/**
322 * igb_cache_ring_register - Descriptor ring to register mapping
323 * @adapter: board private structure to initialize
324 *
325 * Once we know the feature-set enabled for the device, we'll cache
326 * the register offset the descriptor ring is assigned to.
327 **/
328static void igb_cache_ring_register(struct igb_adapter *adapter)
329{
330 int i;
1bfaf07b 331 unsigned int rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 332
333 switch (adapter->hw.mac.type) {
334 case e1000_82576:
335 /* The queues are allocated for virtualization such that VF 0
336 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
337 * In order to avoid collision we start at the first free queue
338 * and continue consuming queues in the same sequence
339 */
340 for (i = 0; i < adapter->num_rx_queues; i++)
1bfaf07b
AD		 341 adapter->rx_ring[i].reg_idx = rbase_offset +
342 Q_IDX_82576(i);
26bc19ec 343 for (i = 0; i < adapter->num_tx_queues; i++)
1bfaf07b
AD		 344 adapter->tx_ring[i].reg_idx = rbase_offset +
345 Q_IDX_82576(i);
26bc19ec
AD		 346 break;
347 case e1000_82575:
348 default:
349 for (i = 0; i < adapter->num_rx_queues; i++)
350 adapter->rx_ring[i].reg_idx = i;
351 for (i = 0; i < adapter->num_tx_queues; i++)
352 adapter->tx_ring[i].reg_idx = i;
353 break;
354 }
355}
356
9d5c8243
AK		 357/**
358 * igb_alloc_queues - Allocate memory for all rings
359 * @adapter: board private structure to initialize
360 *
361 * We allocate one ring per queue at run-time since we don't know the
362 * number of queues at compile-time.
363 **/
364static int igb_alloc_queues(struct igb_adapter *adapter)
365{
366 int i;
367
368 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
369 sizeof(struct igb_ring), GFP_KERNEL);
370 if (!adapter->tx_ring)
371 return -ENOMEM;
372
373 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
374 sizeof(struct igb_ring), GFP_KERNEL);
375 if (!adapter->rx_ring) {
376 kfree(adapter->tx_ring);
377 return -ENOMEM;
378 }
379
6eb5a7f1
AD		 380 adapter->rx_ring->buddy = adapter->tx_ring;
381
661086df
PWJ		 382 for (i = 0; i < adapter->num_tx_queues; i++) {
383 struct igb_ring *ring = &(adapter->tx_ring[i]);
68fd9910 384 ring->count = adapter->tx_ring_count;
661086df
PWJ		 385 ring->adapter = adapter;
386 ring->queue_index = i;
387 }
9d5c8243
AK		 388 for (i = 0; i < adapter->num_rx_queues; i++) {
389 struct igb_ring *ring = &(adapter->rx_ring[i]);
68fd9910 390 ring->count = adapter->rx_ring_count;
9d5c8243 391 ring->adapter = adapter;
844290e5 392 ring->queue_index = i;
9d5c8243
AK		 393 ring->itr_register = E1000_ITR;
394
844290e5 395 /* set a default napi handler for each rx_ring */
661086df 396 netif_napi_add(adapter->netdev, &ring->napi, igb_poll, 64);
9d5c8243 397 }
26bc19ec
AD		 398
399 igb_cache_ring_register(adapter);
9d5c8243
AK		 400 return 0;
401}
402
a88f10ec
AD		 403static void igb_free_queues(struct igb_adapter *adapter)
404{
405 int i;
406
407 for (i = 0; i < adapter->num_rx_queues; i++)
408 netif_napi_del(&adapter->rx_ring[i].napi);
409
410 kfree(adapter->tx_ring);
411 kfree(adapter->rx_ring);
412}
413
9d5c8243
AK		 414#define IGB_N0_QUEUE -1
415static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
416 int tx_queue, int msix_vector)
417{
418 u32 msixbm = 0;
419 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 420 u32 ivar, index;
421
422 switch (hw->mac.type) {
423 case e1000_82575:
9d5c8243
AK		 424 /* The 82575 assigns vectors using a bitmask, which matches the
425 bitmask for the EICR/EIMS/EIMC registers. To assign one
426 or more queues to a vector, we write the appropriate bits
427 into the MSIXBM register for that vector. */
428 if (rx_queue > IGB_N0_QUEUE) {
429 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
430 adapter->rx_ring[rx_queue].eims_value = msixbm;
431 }
432 if (tx_queue > IGB_N0_QUEUE) {
433 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
434 adapter->tx_ring[tx_queue].eims_value =
435 E1000_EICR_TX_QUEUE0 << tx_queue;
436 }
437 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
2d064c06
AD		 438 break;
439 case e1000_82576:
26bc19ec 440 /* 82576 uses a table-based method for assigning vectors.
2d064c06
AD		 441 Each queue has a single entry in the table to which we write
442 a vector number along with a "valid" bit. Sadly, the layout
443 of the table is somewhat counterintuitive. */
444 if (rx_queue > IGB_N0_QUEUE) {
1bfaf07b 445 index = (rx_queue >> 1) + adapter->vfs_allocated_count;
2d064c06 446 ivar = array_rd32(E1000_IVAR0, index);
26bc19ec 447 if (rx_queue & 0x1) {
2d064c06
AD		 448 /* vector goes into third byte of register */
449 ivar = ivar & 0xFF00FFFF;
450 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
26bc19ec
AD		 451 } else {
452 /* vector goes into low byte of register */
453 ivar = ivar & 0xFFFFFF00;
454 ivar |= msix_vector | E1000_IVAR_VALID;
2d064c06
AD		 455 }
456 adapter->rx_ring[rx_queue].eims_value= 1 << msix_vector;
457 array_wr32(E1000_IVAR0, index, ivar);
458 }
459 if (tx_queue > IGB_N0_QUEUE) {
1bfaf07b 460 index = (tx_queue >> 1) + adapter->vfs_allocated_count;
2d064c06 461 ivar = array_rd32(E1000_IVAR0, index);
26bc19ec 462 if (tx_queue & 0x1) {
2d064c06
AD		 463 /* vector goes into high byte of register */
464 ivar = ivar & 0x00FFFFFF;
465 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
26bc19ec
AD		 466 } else {
467 /* vector goes into second byte of register */
468 ivar = ivar & 0xFFFF00FF;
469 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
2d064c06
AD		 470 }
471 adapter->tx_ring[tx_queue].eims_value= 1 << msix_vector;
472 array_wr32(E1000_IVAR0, index, ivar);
473 }
474 break;
475 default:
476 BUG();
477 break;
478 }
9d5c8243
AK		 479}
480
481/**
482 * igb_configure_msix - Configure MSI-X hardware
483 *
484 * igb_configure_msix sets up the hardware to properly
485 * generate MSI-X interrupts.
486 **/
487static void igb_configure_msix(struct igb_adapter *adapter)
488{
489 u32 tmp;
490 int i, vector = 0;
491 struct e1000_hw *hw = &adapter->hw;
492
493 adapter->eims_enable_mask = 0;
2d064c06
AD		 494 if (hw->mac.type == e1000_82576)
495 /* Turn on MSI-X capability first, or our settings
496 * won't stick. And it will take days to debug. */
497 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
eebbbdba 498 E1000_GPIE_PBA | E1000_GPIE_EIAME |
2d064c06 499 E1000_GPIE_NSICR);
9d5c8243
AK		 500
501 for (i = 0; i < adapter->num_tx_queues; i++) {
502 struct igb_ring *tx_ring = &adapter->tx_ring[i];
503 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
504 adapter->eims_enable_mask |= tx_ring->eims_value;
505 if (tx_ring->itr_val)
6eb5a7f1 506 writel(tx_ring->itr_val,
9d5c8243
AK		 507 hw->hw_addr + tx_ring->itr_register);
508 else
509 writel(1, hw->hw_addr + tx_ring->itr_register);
510 }
511
512 for (i = 0; i < adapter->num_rx_queues; i++) {
513 struct igb_ring *rx_ring = &adapter->rx_ring[i];
25ac3c24 514 rx_ring->buddy = NULL;
9d5c8243
AK		 515 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
516 adapter->eims_enable_mask |= rx_ring->eims_value;
517 if (rx_ring->itr_val)
6eb5a7f1 518 writel(rx_ring->itr_val,
9d5c8243
AK		 519 hw->hw_addr + rx_ring->itr_register);
520 else
521 writel(1, hw->hw_addr + rx_ring->itr_register);
522 }
523
524
525 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 526 switch (hw->mac.type) {
527 case e1000_82575:
9d5c8243
AK		 528 array_wr32(E1000_MSIXBM(0), vector++,
529 E1000_EIMS_OTHER);
530
9d5c8243
AK		 531 tmp = rd32(E1000_CTRL_EXT);
532 /* enable MSI-X PBA support*/
533 tmp |= E1000_CTRL_EXT_PBA_CLR;
534
535 /* Auto-Mask interrupts upon ICR read. */
536 tmp |= E1000_CTRL_EXT_EIAME;
537 tmp |= E1000_CTRL_EXT_IRCA;
538
539 wr32(E1000_CTRL_EXT, tmp);
540 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
844290e5 541 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 542
2d064c06
AD		 543 break;
544
545 case e1000_82576:
546 tmp = (vector++ | E1000_IVAR_VALID) << 8;
547 wr32(E1000_IVAR_MISC, tmp);
548
549 adapter->eims_enable_mask = (1 << (vector)) - 1;
550 adapter->eims_other = 1 << (vector - 1);
551 break;
552 default:
553 /* do nothing, since nothing else supports MSI-X */
554 break;
555 } /* switch (hw->mac.type) */
9d5c8243
AK		 556 wrfl();
557}
558
559/**
560 * igb_request_msix - Initialize MSI-X interrupts
561 *
562 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
563 * kernel.
564 **/
565static int igb_request_msix(struct igb_adapter *adapter)
566{
567 struct net_device *netdev = adapter->netdev;
568 int i, err = 0, vector = 0;
569
570 vector = 0;
571
572 for (i = 0; i < adapter->num_tx_queues; i++) {
573 struct igb_ring *ring = &(adapter->tx_ring[i]);
cb7b48f6 574 sprintf(ring->name, "%s-tx-%d", netdev->name, i);
9d5c8243
AK		 575 err = request_irq(adapter->msix_entries[vector].vector,
576 &igb_msix_tx, 0, ring->name,
577 &(adapter->tx_ring[i]));
578 if (err)
579 goto out;
580 ring->itr_register = E1000_EITR(0) + (vector << 2);
6eb5a7f1 581 ring->itr_val = 976; /* ~4000 ints/sec */
9d5c8243
AK		 582 vector++;
583 }
584 for (i = 0; i < adapter->num_rx_queues; i++) {
585 struct igb_ring *ring = &(adapter->rx_ring[i]);
586 if (strlen(netdev->name) < (IFNAMSIZ - 5))
cb7b48f6 587 sprintf(ring->name, "%s-rx-%d", netdev->name, i);
9d5c8243
AK		 588 else
589 memcpy(ring->name, netdev->name, IFNAMSIZ);
590 err = request_irq(adapter->msix_entries[vector].vector,
591 &igb_msix_rx, 0, ring->name,
592 &(adapter->rx_ring[i]));
593 if (err)
594 goto out;
595 ring->itr_register = E1000_EITR(0) + (vector << 2);
596 ring->itr_val = adapter->itr;
597 vector++;
598 }
599
600 err = request_irq(adapter->msix_entries[vector].vector,
601 &igb_msix_other, 0, netdev->name, netdev);
602 if (err)
603 goto out;
604
9d5c8243
AK		 605 igb_configure_msix(adapter);
606 return 0;
607out:
608 return err;
609}
610
611static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
612{
613 if (adapter->msix_entries) {
614 pci_disable_msix(adapter->pdev);
615 kfree(adapter->msix_entries);
616 adapter->msix_entries = NULL;
7dfc16fa 617 } else if (adapter->flags & IGB_FLAG_HAS_MSI)
9d5c8243
AK		 618 pci_disable_msi(adapter->pdev);
619 return;
620}
621
622
623/**
624 * igb_set_interrupt_capability - set MSI or MSI-X if supported
625 *
626 * Attempt to configure interrupts using the best available
627 * capabilities of the hardware and kernel.
628 **/
629static void igb_set_interrupt_capability(struct igb_adapter *adapter)
630{
631 int err;
632 int numvecs, i;
633
83b7180d
AD		 634 /* Number of supported queues. */
635 /* Having more queues than CPUs doesn't make sense. */
636 adapter->num_rx_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
637 adapter->num_tx_queues = min_t(u32, IGB_MAX_TX_QUEUES, num_online_cpus());
638
9d5c8243
AK		 639 numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1;
640 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
641 GFP_KERNEL);
642 if (!adapter->msix_entries)
643 goto msi_only;
644
645 for (i = 0; i < numvecs; i++)
646 adapter->msix_entries[i].entry = i;
647
648 err = pci_enable_msix(adapter->pdev,
649 adapter->msix_entries,
650 numvecs);
651 if (err == 0)
34a20e89 652 goto out;
9d5c8243
AK		 653
654 igb_reset_interrupt_capability(adapter);
655
656 /* If we can't do MSI-X, try MSI */
657msi_only:
658 adapter->num_rx_queues = 1;
661086df 659 adapter->num_tx_queues = 1;
9d5c8243 660 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 661 adapter->flags |= IGB_FLAG_HAS_MSI;
34a20e89 662out:
661086df 663 /* Notify the stack of the (possibly) reduced Tx Queue count. */
fd2ea0a7 664 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
9d5c8243
AK		 665 return;
666}
667
668/**
669 * igb_request_irq - initialize interrupts
670 *
671 * Attempts to configure interrupts using the best available
672 * capabilities of the hardware and kernel.
673 **/
674static int igb_request_irq(struct igb_adapter *adapter)
675{
676 struct net_device *netdev = adapter->netdev;
677 struct e1000_hw *hw = &adapter->hw;
678 int err = 0;
679
680 if (adapter->msix_entries) {
681 err = igb_request_msix(adapter);
844290e5 682 if (!err)
9d5c8243 683 goto request_done;
9d5c8243
AK		 684 /* fall back to MSI */
685 igb_reset_interrupt_capability(adapter);
686 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 687 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 688 igb_free_all_tx_resources(adapter);
689 igb_free_all_rx_resources(adapter);
690 adapter->num_rx_queues = 1;
691 igb_alloc_queues(adapter);
844290e5 692 } else {
2d064c06
AD		 693 switch (hw->mac.type) {
694 case e1000_82575:
695 wr32(E1000_MSIXBM(0),
696 (E1000_EICR_RX_QUEUE0 | E1000_EIMS_OTHER));
697 break;
698 case e1000_82576:
699 wr32(E1000_IVAR0, E1000_IVAR_VALID);
700 break;
701 default:
702 break;
703 }
9d5c8243 704 }
844290e5 705
7dfc16fa 706 if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243
AK		 707 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
708 netdev->name, netdev);
709 if (!err)
710 goto request_done;
711 /* fall back to legacy interrupts */
712 igb_reset_interrupt_capability(adapter);
7dfc16fa 713 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 714 }
715
716 err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
717 netdev->name, netdev);
718
6cb5e577 719 if (err)
9d5c8243
AK		 720 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
721 err);
9d5c8243
AK		 722
723request_done:
724 return err;
725}
726
727static void igb_free_irq(struct igb_adapter *adapter)
728{
729 struct net_device *netdev = adapter->netdev;
730
731 if (adapter->msix_entries) {
732 int vector = 0, i;
733
734 for (i = 0; i < adapter->num_tx_queues; i++)
735 free_irq(adapter->msix_entries[vector++].vector,
736 &(adapter->tx_ring[i]));
737 for (i = 0; i < adapter->num_rx_queues; i++)
738 free_irq(adapter->msix_entries[vector++].vector,
739 &(adapter->rx_ring[i]));
740
741 free_irq(adapter->msix_entries[vector++].vector, netdev);
742 return;
743 }
744
745 free_irq(adapter->pdev->irq, netdev);
746}
747
748/**
749 * igb_irq_disable - Mask off interrupt generation on the NIC
750 * @adapter: board private structure
751 **/
752static void igb_irq_disable(struct igb_adapter *adapter)
753{
754 struct e1000_hw *hw = &adapter->hw;
755
756 if (adapter->msix_entries) {
844290e5 757 wr32(E1000_EIAM, 0);
9d5c8243
AK		 758 wr32(E1000_EIMC, ~0);
759 wr32(E1000_EIAC, 0);
760 }
844290e5
PW		 761
762 wr32(E1000_IAM, 0);
9d5c8243
AK		 763 wr32(E1000_IMC, ~0);
764 wrfl();
765 synchronize_irq(adapter->pdev->irq);
766}
767
768/**
769 * igb_irq_enable - Enable default interrupt generation settings
770 * @adapter: board private structure
771 **/
772static void igb_irq_enable(struct igb_adapter *adapter)
773{
774 struct e1000_hw *hw = &adapter->hw;
775
776 if (adapter->msix_entries) {
844290e5
PW		 777 wr32(E1000_EIAC, adapter->eims_enable_mask);
778 wr32(E1000_EIAM, adapter->eims_enable_mask);
779 wr32(E1000_EIMS, adapter->eims_enable_mask);
4ae196df
AD		 780 if (adapter->vfs_allocated_count)
781 wr32(E1000_MBVFIMR, 0xFF);
782 wr32(E1000_IMS, (E1000_IMS_LSC | E1000_IMS_VMMB |
783 E1000_IMS_DOUTSYNC));
844290e5
PW		 784 } else {
785 wr32(E1000_IMS, IMS_ENABLE_MASK);
786 wr32(E1000_IAM, IMS_ENABLE_MASK);
787 }
9d5c8243
AK		 788}
789
790static void igb_update_mng_vlan(struct igb_adapter *adapter)
791{
792 struct net_device *netdev = adapter->netdev;
793 u16 vid = adapter->hw.mng_cookie.vlan_id;
794 u16 old_vid = adapter->mng_vlan_id;
795 if (adapter->vlgrp) {
796 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
797 if (adapter->hw.mng_cookie.status &
798 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
799 igb_vlan_rx_add_vid(netdev, vid);
800 adapter->mng_vlan_id = vid;
801 } else
802 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
803
804 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
805 (vid != old_vid) &&
806 !vlan_group_get_device(adapter->vlgrp, old_vid))
807 igb_vlan_rx_kill_vid(netdev, old_vid);
808 } else
809 adapter->mng_vlan_id = vid;
810 }
811}
812
813/**
814 * igb_release_hw_control - release control of the h/w to f/w
815 * @adapter: address of board private structure
816 *
817 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
818 * For ASF and Pass Through versions of f/w this means that the
819 * driver is no longer loaded.
820 *
821 **/
822static void igb_release_hw_control(struct igb_adapter *adapter)
823{
824 struct e1000_hw *hw = &adapter->hw;
825 u32 ctrl_ext;
826
827 /* Let firmware take over control of h/w */
828 ctrl_ext = rd32(E1000_CTRL_EXT);
829 wr32(E1000_CTRL_EXT,
830 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
831}
832
833
834/**
835 * igb_get_hw_control - get control of the h/w from f/w
836 * @adapter: address of board private structure
837 *
838 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
839 * For ASF and Pass Through versions of f/w this means that
840 * the driver is loaded.
841 *
842 **/
843static void igb_get_hw_control(struct igb_adapter *adapter)
844{
845 struct e1000_hw *hw = &adapter->hw;
846 u32 ctrl_ext;
847
848 /* Let firmware know the driver has taken over */
849 ctrl_ext = rd32(E1000_CTRL_EXT);
850 wr32(E1000_CTRL_EXT,
851 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
852}
853
9d5c8243
AK		 854/**
855 * igb_configure - configure the hardware for RX and TX
856 * @adapter: private board structure
857 **/
858static void igb_configure(struct igb_adapter *adapter)
859{
860 struct net_device *netdev = adapter->netdev;
861 int i;
862
863 igb_get_hw_control(adapter);
864 igb_set_multi(netdev);
865
866 igb_restore_vlan(adapter);
9d5c8243
AK		 867
868 igb_configure_tx(adapter);
869 igb_setup_rctl(adapter);
870 igb_configure_rx(adapter);
662d7205
AD		 871
872 igb_rx_fifo_flush_82575(&adapter->hw);
873
9d5c8243
AK		 874 /* call IGB_DESC_UNUSED which always leaves
875 * at least 1 descriptor unused to make sure
876 * next_to_use != next_to_clean */
877 for (i = 0; i < adapter->num_rx_queues; i++) {
878 struct igb_ring *ring = &adapter->rx_ring[i];
3b644cf6 879 igb_alloc_rx_buffers_adv(ring, IGB_DESC_UNUSED(ring));
9d5c8243
AK		 880 }
881
882
883 adapter->tx_queue_len = netdev->tx_queue_len;
884}
885
886
887/**
888 * igb_up - Open the interface and prepare it to handle traffic
889 * @adapter: board private structure
890 **/
891
892int igb_up(struct igb_adapter *adapter)
893{
894 struct e1000_hw *hw = &adapter->hw;
895 int i;
896
897 /* hardware has been reset, we need to reload some things */
898 igb_configure(adapter);
899
900 clear_bit(__IGB_DOWN, &adapter->state);
901
844290e5
PW		 902 for (i = 0; i < adapter->num_rx_queues; i++)
903 napi_enable(&adapter->rx_ring[i].napi);
904 if (adapter->msix_entries)
9d5c8243 905 igb_configure_msix(adapter);
9d5c8243 906
4ae196df 907 igb_vmm_control(adapter);
e1739522
AD		 908 igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
909 igb_set_vmolr(hw, adapter->vfs_allocated_count);
910
9d5c8243
AK		 911 /* Clear any pending interrupts. */
912 rd32(E1000_ICR);
913 igb_irq_enable(adapter);
914
915 /* Fire a link change interrupt to start the watchdog. */
916 wr32(E1000_ICS, E1000_ICS_LSC);
917 return 0;
918}
919
920void igb_down(struct igb_adapter *adapter)
921{
922 struct e1000_hw *hw = &adapter->hw;
923 struct net_device *netdev = adapter->netdev;
924 u32 tctl, rctl;
925 int i;
926
927 /* signal that we're down so the interrupt handler does not
928 * reschedule our watchdog timer */
929 set_bit(__IGB_DOWN, &adapter->state);
930
931 /* disable receives in the hardware */
932 rctl = rd32(E1000_RCTL);
933 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
934 /* flush and sleep below */
935
fd2ea0a7 936 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 937
938 /* disable transmits in the hardware */
939 tctl = rd32(E1000_TCTL);
940 tctl &= ~E1000_TCTL_EN;
941 wr32(E1000_TCTL, tctl);
942 /* flush both disables and wait for them to finish */
943 wrfl();
944 msleep(10);
945
844290e5
PW		 946 for (i = 0; i < adapter->num_rx_queues; i++)
947 napi_disable(&adapter->rx_ring[i].napi);
9d5c8243 948
9d5c8243
AK		 949 igb_irq_disable(adapter);
950
951 del_timer_sync(&adapter->watchdog_timer);
952 del_timer_sync(&adapter->phy_info_timer);
953
954 netdev->tx_queue_len = adapter->tx_queue_len;
955 netif_carrier_off(netdev);
04fe6358
AD		 956
957 /* record the stats before reset*/
958 igb_update_stats(adapter);
959
9d5c8243
AK		 960 adapter->link_speed = 0;
961 adapter->link_duplex = 0;
962
3023682e
JK		 963 if (!pci_channel_offline(adapter->pdev))
964 igb_reset(adapter);
9d5c8243
AK		 965 igb_clean_all_tx_rings(adapter);
966 igb_clean_all_rx_rings(adapter);
967}
968
969void igb_reinit_locked(struct igb_adapter *adapter)
970{
971 WARN_ON(in_interrupt());
972 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
973 msleep(1);
974 igb_down(adapter);
975 igb_up(adapter);
976 clear_bit(__IGB_RESETTING, &adapter->state);
977}
978
979void igb_reset(struct igb_adapter *adapter)
980{
981 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 982 struct e1000_mac_info *mac = &hw->mac;
983 struct e1000_fc_info *fc = &hw->fc;
9d5c8243
AK		 984 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
985 u16 hwm;
986
987 /* Repartition Pba for greater than 9k mtu
988 * To take effect CTRL.RST is required.
989 */
fa4dfae0
AD		 990 switch (mac->type) {
991 case e1000_82576:
2d064c06 992 pba = E1000_PBA_64K;
fa4dfae0
AD		 993 break;
994 case e1000_82575:
995 default:
996 pba = E1000_PBA_34K;
997 break;
2d064c06 998 }
9d5c8243 999
2d064c06
AD		 1000 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1001 (mac->type < e1000_82576)) {
9d5c8243
AK		 1002 /* adjust PBA for jumbo frames */
1003 wr32(E1000_PBA, pba);
1004
1005 /* To maintain wire speed transmits, the Tx FIFO should be
1006 * large enough to accommodate two full transmit packets,
1007 * rounded up to the next 1KB and expressed in KB. Likewise,
1008 * the Rx FIFO should be large enough to accommodate at least
1009 * one full receive packet and is similarly rounded up and
1010 * expressed in KB. */
1011 pba = rd32(E1000_PBA);
1012 /* upper 16 bits has Tx packet buffer allocation size in KB */
1013 tx_space = pba >> 16;
1014 /* lower 16 bits has Rx packet buffer allocation size in KB */
1015 pba &= 0xffff;
1016 /* the tx fifo also stores 16 bytes of information about the tx
1017 * but don't include ethernet FCS because hardware appends it */
1018 min_tx_space = (adapter->max_frame_size +
85e8d004 1019 sizeof(union e1000_adv_tx_desc) -
9d5c8243
AK		 1020 ETH_FCS_LEN) * 2;
1021 min_tx_space = ALIGN(min_tx_space, 1024);
1022 min_tx_space >>= 10;
1023 /* software strips receive CRC, so leave room for it */
1024 min_rx_space = adapter->max_frame_size;
1025 min_rx_space = ALIGN(min_rx_space, 1024);
1026 min_rx_space >>= 10;
1027
1028 /* If current Tx allocation is less than the min Tx FIFO size,
1029 * and the min Tx FIFO size is less than the current Rx FIFO
1030 * allocation, take space away from current Rx allocation */
1031 if (tx_space < min_tx_space &&
1032 ((min_tx_space - tx_space) < pba)) {
1033 pba = pba - (min_tx_space - tx_space);
1034
1035 /* if short on rx space, rx wins and must trump tx
1036 * adjustment */
1037 if (pba < min_rx_space)
1038 pba = min_rx_space;
1039 }
2d064c06 1040 wr32(E1000_PBA, pba);
9d5c8243 1041 }
9d5c8243
AK		 1042
1043 /* flow control settings */
1044 /* The high water mark must be low enough to fit one full frame
1045 * (or the size used for early receive) above it in the Rx FIFO.
1046 * Set it to the lower of:
1047 * - 90% of the Rx FIFO size, or
1048 * - the full Rx FIFO size minus one full frame */
1049 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1050 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1051
2d064c06
AD		 1052 if (mac->type < e1000_82576) {
1053 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
1054 fc->low_water = fc->high_water - 8;
1055 } else {
1056 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1057 fc->low_water = fc->high_water - 16;
1058 }
9d5c8243
AK		 1059 fc->pause_time = 0xFFFF;
1060 fc->send_xon = 1;
1061 fc->type = fc->original_type;
1062
4ae196df
AD		 1063 /* disable receive for all VFs and wait one second */
1064 if (adapter->vfs_allocated_count) {
1065 int i;
1066 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
1067 adapter->vf_data[i].clear_to_send = false;
1068
1069 /* ping all the active vfs to let them know we are going down */
1070 igb_ping_all_vfs(adapter);
1071
1072 /* disable transmits and receives */
1073 wr32(E1000_VFRE, 0);
1074 wr32(E1000_VFTE, 0);
1075 }
1076
9d5c8243
AK		 1077 /* Allow time for pending master requests to run */
1078 adapter->hw.mac.ops.reset_hw(&adapter->hw);
1079 wr32(E1000_WUC, 0);
1080
1081 if (adapter->hw.mac.ops.init_hw(&adapter->hw))
1082 dev_err(&adapter->pdev->dev, "Hardware Error\n");
1083
1084 igb_update_mng_vlan(adapter);
1085
1086 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1087 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1088
1089 igb_reset_adaptive(&adapter->hw);
f5f4cf08 1090 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 1091}
1092
2e5c6922
SH		 1093static const struct net_device_ops igb_netdev_ops = {
1094 .ndo_open = igb_open,
1095 .ndo_stop = igb_close,
00829823 1096 .ndo_start_xmit = igb_xmit_frame_adv,
2e5c6922
SH		 1097 .ndo_get_stats = igb_get_stats,
1098 .ndo_set_multicast_list = igb_set_multi,
1099 .ndo_set_mac_address = igb_set_mac,
1100 .ndo_change_mtu = igb_change_mtu,
1101 .ndo_do_ioctl = igb_ioctl,
1102 .ndo_tx_timeout = igb_tx_timeout,
1103 .ndo_validate_addr = eth_validate_addr,
1104 .ndo_vlan_rx_register = igb_vlan_rx_register,
1105 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1106 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
1107#ifdef CONFIG_NET_POLL_CONTROLLER
1108 .ndo_poll_controller = igb_netpoll,
1109#endif
1110};
1111
9d5c8243
AK		 1112/**
1113 * igb_probe - Device Initialization Routine
1114 * @pdev: PCI device information struct
1115 * @ent: entry in igb_pci_tbl
1116 *
1117 * Returns 0 on success, negative on failure
1118 *
1119 * igb_probe initializes an adapter identified by a pci_dev structure.
1120 * The OS initialization, configuring of the adapter private structure,
1121 * and a hardware reset occur.
1122 **/
1123static int __devinit igb_probe(struct pci_dev *pdev,
1124 const struct pci_device_id *ent)
1125{
1126 struct net_device *netdev;
1127 struct igb_adapter *adapter;
1128 struct e1000_hw *hw;
c54106bb 1129 struct pci_dev *us_dev;
9d5c8243
AK		 1130 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1131 unsigned long mmio_start, mmio_len;
450c87c8 1132 int err, pci_using_dac, pos;
c54106bb 1133 u16 eeprom_data = 0, state = 0;
9d5c8243
AK		 1134 u16 eeprom_apme_mask = IGB_EEPROM_APME;
1135 u32 part_num;
1136
aed5dec3 1137 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 1138 if (err)
1139 return err;
1140
1141 pci_using_dac = 0;
1142 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
1143 if (!err) {
1144 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1145 if (!err)
1146 pci_using_dac = 1;
1147 } else {
1148 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1149 if (err) {
1150 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1151 if (err) {
1152 dev_err(&pdev->dev, "No usable DMA "
1153 "configuration, aborting\n");
1154 goto err_dma;
1155 }
1156 }
1157 }
1158
c54106bb
AD		 1159 /* 82575 requires that the pci-e link partner disable the L0s state */
1160 switch (pdev->device) {
1161 case E1000_DEV_ID_82575EB_COPPER:
1162 case E1000_DEV_ID_82575EB_FIBER_SERDES:
1163 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1164 us_dev = pdev->bus->self;
1165 pos = pci_find_capability(us_dev, PCI_CAP_ID_EXP);
1166 if (pos) {
1167 pci_read_config_word(us_dev, pos + PCI_EXP_LNKCTL,
1168 &state);
1169 state &= ~PCIE_LINK_STATE_L0S;
1170 pci_write_config_word(us_dev, pos + PCI_EXP_LNKCTL,
1171 state);
ac450208
BH		 1172 dev_info(&pdev->dev,
1173 "Disabling ASPM L0s upstream switch port %s\n",
1174 pci_name(us_dev));
c54106bb
AD		 1175 }
1176 default:
1177 break;
1178 }
1179
aed5dec3
AD		 1180 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1181 IORESOURCE_MEM),
1182 igb_driver_name);
9d5c8243
AK		 1183 if (err)
1184 goto err_pci_reg;
1185
ea943d41
JK		 1186 err = pci_enable_pcie_error_reporting(pdev);
1187 if (err) {
1188 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
1189 "0x%x\n", err);
1190 /* non-fatal, continue */
1191 }
40a914fa 1192
9d5c8243 1193 pci_set_master(pdev);
c682fc23 1194 pci_save_state(pdev);
9d5c8243
AK		 1195
1196 err = -ENOMEM;
1bfaf07b
AD		 1197 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1198 IGB_ABS_MAX_TX_QUEUES);
9d5c8243
AK		 1199 if (!netdev)
1200 goto err_alloc_etherdev;
1201
1202 SET_NETDEV_DEV(netdev, &pdev->dev);
1203
1204 pci_set_drvdata(pdev, netdev);
1205 adapter = netdev_priv(netdev);
1206 adapter->netdev = netdev;
1207 adapter->pdev = pdev;
1208 hw = &adapter->hw;
1209 hw->back = adapter;
1210 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
1211
1212 mmio_start = pci_resource_start(pdev, 0);
1213 mmio_len = pci_resource_len(pdev, 0);
1214
1215 err = -EIO;
28b0759c
AD		 1216 hw->hw_addr = ioremap(mmio_start, mmio_len);
1217 if (!hw->hw_addr)
9d5c8243
AK		 1218 goto err_ioremap;
1219
2e5c6922 1220 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 1221 igb_set_ethtool_ops(netdev);
9d5c8243 1222 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 1223
1224 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1225
1226 netdev->mem_start = mmio_start;
1227 netdev->mem_end = mmio_start + mmio_len;
1228
9d5c8243
AK		 1229 /* PCI config space info */
1230 hw->vendor_id = pdev->vendor;
1231 hw->device_id = pdev->device;
1232 hw->revision_id = pdev->revision;
1233 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1234 hw->subsystem_device_id = pdev->subsystem_device;
1235
1236 /* setup the private structure */
1237 hw->back = adapter;
1238 /* Copy the default MAC, PHY and NVM function pointers */
1239 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1240 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1241 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1242 /* Initialize skew-specific constants */
1243 err = ei->get_invariants(hw);
1244 if (err)
450c87c8 1245 goto err_sw_init;
9d5c8243 1246
450c87c8 1247 /* setup the private structure */
9d5c8243
AK		 1248 err = igb_sw_init(adapter);
1249 if (err)
1250 goto err_sw_init;
1251
1252 igb_get_bus_info_pcie(hw);
1253
7dfc16fa
AD		 1254 /* set flags */
1255 switch (hw->mac.type) {
7dfc16fa 1256 case e1000_82575:
7dfc16fa
AD		 1257 adapter->flags |= IGB_FLAG_NEED_CTX_IDX;
1258 break;
bbd98fe4 1259 case e1000_82576:
7dfc16fa
AD		 1260 default:
1261 break;
1262 }
1263
9d5c8243
AK		 1264 hw->phy.autoneg_wait_to_complete = false;
1265 hw->mac.adaptive_ifs = true;
1266
1267 /* Copper options */
1268 if (hw->phy.media_type == e1000_media_type_copper) {
1269 hw->phy.mdix = AUTO_ALL_MODES;
1270 hw->phy.disable_polarity_correction = false;
1271 hw->phy.ms_type = e1000_ms_hw_default;
1272 }
1273
1274 if (igb_check_reset_block(hw))
1275 dev_info(&pdev->dev,
1276 "PHY reset is blocked due to SOL/IDER session.\n");
1277
1278 netdev->features = NETIF_F_SG |
7d8eb29e 1279 NETIF_F_IP_CSUM |
9d5c8243
AK		 1280 NETIF_F_HW_VLAN_TX |
1281 NETIF_F_HW_VLAN_RX |
1282 NETIF_F_HW_VLAN_FILTER;
1283
7d8eb29e 1284 netdev->features |= NETIF_F_IPV6_CSUM;
9d5c8243 1285 netdev->features |= NETIF_F_TSO;
9d5c8243 1286 netdev->features |= NETIF_F_TSO6;
48f29ffc 1287
5c0999b7 1288 netdev->features |= NETIF_F_GRO;
d3352520 1289
48f29ffc
JK		 1290 netdev->vlan_features |= NETIF_F_TSO;
1291 netdev->vlan_features |= NETIF_F_TSO6;
7d8eb29e 1292 netdev->vlan_features |= NETIF_F_IP_CSUM;
48f29ffc
JK		 1293 netdev->vlan_features |= NETIF_F_SG;
1294
9d5c8243
AK		 1295 if (pci_using_dac)
1296 netdev->features |= NETIF_F_HIGHDMA;
1297
9d5c8243
AK		 1298 adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1299
1300 /* before reading the NVM, reset the controller to put the device in a
1301 * known good starting state */
1302 hw->mac.ops.reset_hw(hw);
1303
1304 /* make sure the NVM is good */
1305 if (igb_validate_nvm_checksum(hw) < 0) {
1306 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1307 err = -EIO;
1308 goto err_eeprom;
1309 }
1310
1311 /* copy the MAC address out of the NVM */
1312 if (hw->mac.ops.read_mac_addr(hw))
1313 dev_err(&pdev->dev, "NVM Read Error\n");
1314
1315 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1316 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1317
1318 if (!is_valid_ether_addr(netdev->perm_addr)) {
1319 dev_err(&pdev->dev, "Invalid MAC Address\n");
1320 err = -EIO;
1321 goto err_eeprom;
1322 }
1323
1324 init_timer(&adapter->watchdog_timer);
1325 adapter->watchdog_timer.function = &igb_watchdog;
1326 adapter->watchdog_timer.data = (unsigned long) adapter;
1327
1328 init_timer(&adapter->phy_info_timer);
1329 adapter->phy_info_timer.function = &igb_update_phy_info;
1330 adapter->phy_info_timer.data = (unsigned long) adapter;
1331
1332 INIT_WORK(&adapter->reset_task, igb_reset_task);
1333 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1334
450c87c8 1335 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 1336 adapter->fc_autoneg = true;
1337 hw->mac.autoneg = true;
1338 hw->phy.autoneg_advertised = 0x2f;
1339
1340 hw->fc.original_type = e1000_fc_default;
1341 hw->fc.type = e1000_fc_default;
1342
cbd347ad 1343 adapter->itr_setting = IGB_DEFAULT_ITR;
9d5c8243
AK		 1344 adapter->itr = IGB_START_ITR;
1345
1346 igb_validate_mdi_setting(hw);
1347
1348 adapter->rx_csum = 1;
1349
1350 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1351 * enable the ACPI Magic Packet filter
1352 */
1353
a2cf8b6c 1354 if (hw->bus.func == 0)
312c75ae 1355 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
a2cf8b6c
AD		 1356 else if (hw->bus.func == 1)
1357 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243
AK		 1358
1359 if (eeprom_data & eeprom_apme_mask)
1360 adapter->eeprom_wol |= E1000_WUFC_MAG;
1361
1362 /* now that we have the eeprom settings, apply the special cases where
1363 * the eeprom may be wrong or the board simply won't support wake on
1364 * lan on a particular port */
1365 switch (pdev->device) {
1366 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1367 adapter->eeprom_wol = 0;
1368 break;
1369 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 1370 case E1000_DEV_ID_82576_FIBER:
1371 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 1372 /* Wake events only supported on port A for dual fiber
1373 * regardless of eeprom setting */
1374 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1375 adapter->eeprom_wol = 0;
1376 break;
1377 }
1378
1379 /* initialize the wol settings based on the eeprom settings */
1380 adapter->wol = adapter->eeprom_wol;
e1b86d84 1381 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
9d5c8243
AK		 1382
1383 /* reset the hardware with the new settings */
1384 igb_reset(adapter);
1385
1386 /* let the f/w know that the h/w is now under the control of the
1387 * driver. */
1388 igb_get_hw_control(adapter);
1389
1390 /* tell the stack to leave us alone until igb_open() is called */
1391 netif_carrier_off(netdev);
fd2ea0a7 1392 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1393
1394 strcpy(netdev->name, "eth%d");
1395 err = register_netdev(netdev);
1396 if (err)
1397 goto err_register;
1398
37680117
AD		 1399#ifdef CONFIG_PCI_IOV
1400 /* since iov functionality isn't critical to base device function we
1401 * can accept failure. If it fails we don't allow iov to be enabled */
1402 if (hw->mac.type == e1000_82576) {
1403 err = pci_enable_sriov(pdev, 0);
1404 if (!err)
1405 err = device_create_file(&netdev->dev,
1406 &dev_attr_num_vfs);
1407 if (err)
1408 dev_err(&pdev->dev, "Failed to initialize IOV\n");
1409 }
1410
1411#endif
421e02f0 1412#ifdef CONFIG_IGB_DCA
bbd98fe4 1413 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 1414 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 1415 dev_info(&pdev->dev, "DCA enabled\n");
1416 /* Always use CB2 mode, difference is masked
1417 * in the CB driver. */
cbd347ad 1418 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
fe4506b6
JC		 1419 igb_setup_dca(adapter);
1420 }
1421#endif
1422
38c845c7
PO		 1423 /*
1424 * Initialize hardware timer: we keep it running just in case
1425 * that some program needs it later on.
1426 */
1427 memset(&adapter->cycles, 0, sizeof(adapter->cycles));
1428 adapter->cycles.read = igb_read_clock;
1429 adapter->cycles.mask = CLOCKSOURCE_MASK(64);
1430 adapter->cycles.mult = 1;
1431 adapter->cycles.shift = IGB_TSYNC_SHIFT;
1432 wr32(E1000_TIMINCA,
1433 (1<<24) |
1434 IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS * IGB_TSYNC_SCALE);
1435#if 0
1436 /*
1437 * Avoid rollover while we initialize by resetting the time counter.
1438 */
1439 wr32(E1000_SYSTIML, 0x00000000);
1440 wr32(E1000_SYSTIMH, 0x00000000);
1441#else
1442 /*
1443 * Set registers so that rollover occurs soon to test this.
1444 */
1445 wr32(E1000_SYSTIML, 0x00000000);
1446 wr32(E1000_SYSTIMH, 0xFF800000);
1447#endif
1448 wrfl();
1449 timecounter_init(&adapter->clock,
1450 &adapter->cycles,
1451 ktime_to_ns(ktime_get_real()));
1452
33af6bcc
PO		 1453 /*
1454 * Synchronize our NIC clock against system wall clock. NIC
1455 * time stamp reading requires ~3us per sample, each sample
1456 * was pretty stable even under load => only require 10
1457 * samples for each offset comparison.
1458 */
1459 memset(&adapter->compare, 0, sizeof(adapter->compare));
1460 adapter->compare.source = &adapter->clock;
1461 adapter->compare.target = ktime_get_real;
1462 adapter->compare.num_samples = 10;
1463 timecompare_update(&adapter->compare, 0);
1464
38c845c7
PO		 1465#ifdef DEBUG
1466 {
1467 char buffer[160];
1468 printk(KERN_DEBUG
1469 "igb: %s: hw %p initialized timer\n",
1470 igb_get_time_str(adapter, buffer),
1471 &adapter->hw);
1472 }
1473#endif
1474
9d5c8243
AK		 1475 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1476 /* print bus type/speed/width info */
7c510e4b 1477 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
9d5c8243
AK		 1478 netdev->name,
1479 ((hw->bus.speed == e1000_bus_speed_2500)
1480 ? "2.5Gb/s" : "unknown"),
1481 ((hw->bus.width == e1000_bus_width_pcie_x4)
1482 ? "Width x4" : (hw->bus.width == e1000_bus_width_pcie_x1)
1483 ? "Width x1" : "unknown"),
7c510e4b 1484 netdev->dev_addr);
9d5c8243
AK		 1485
1486 igb_read_part_num(hw, &part_num);
1487 dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1488 (part_num >> 8), (part_num & 0xff));
1489
1490 dev_info(&pdev->dev,
1491 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1492 adapter->msix_entries ? "MSI-X" :
7dfc16fa 1493 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243
AK		 1494 adapter->num_rx_queues, adapter->num_tx_queues);
1495
9d5c8243
AK		 1496 return 0;
1497
1498err_register:
1499 igb_release_hw_control(adapter);
1500err_eeprom:
1501 if (!igb_check_reset_block(hw))
f5f4cf08 1502 igb_reset_phy(hw);
9d5c8243
AK		 1503
1504 if (hw->flash_address)
1505 iounmap(hw->flash_address);
1506
a88f10ec 1507 igb_free_queues(adapter);
9d5c8243 1508err_sw_init:
9d5c8243
AK		 1509 iounmap(hw->hw_addr);
1510err_ioremap:
1511 free_netdev(netdev);
1512err_alloc_etherdev:
aed5dec3
AD		 1513 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1514 IORESOURCE_MEM));
9d5c8243
AK		 1515err_pci_reg:
1516err_dma:
1517 pci_disable_device(pdev);
1518 return err;
1519}
1520
1521/**
1522 * igb_remove - Device Removal Routine
1523 * @pdev: PCI device information struct
1524 *
1525 * igb_remove is called by the PCI subsystem to alert the driver
1526 * that it should release a PCI device. The could be caused by a
1527 * Hot-Plug event, or because the driver is going to be removed from
1528 * memory.
1529 **/
1530static void __devexit igb_remove(struct pci_dev *pdev)
1531{
1532 struct net_device *netdev = pci_get_drvdata(pdev);
1533 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 1534 struct e1000_hw *hw = &adapter->hw;
ea943d41 1535 int err;
9d5c8243
AK		 1536
1537 /* flush_scheduled work may reschedule our watchdog task, so
1538 * explicitly disable watchdog tasks from being rescheduled */
1539 set_bit(__IGB_DOWN, &adapter->state);
1540 del_timer_sync(&adapter->watchdog_timer);
1541 del_timer_sync(&adapter->phy_info_timer);
1542
1543 flush_scheduled_work();
1544
421e02f0 1545#ifdef CONFIG_IGB_DCA
7dfc16fa 1546 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 1547 dev_info(&pdev->dev, "DCA disabled\n");
1548 dca_remove_requester(&pdev->dev);
7dfc16fa 1549 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 1550 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 1551 }
1552#endif
1553
9d5c8243
AK		 1554 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1555 * would have already happened in close and is redundant. */
1556 igb_release_hw_control(adapter);
1557
1558 unregister_netdev(netdev);
1559
f5f4cf08
AD		 1560 if (!igb_check_reset_block(&adapter->hw))
1561 igb_reset_phy(&adapter->hw);
9d5c8243 1562
9d5c8243
AK		 1563 igb_reset_interrupt_capability(adapter);
1564
a88f10ec 1565 igb_free_queues(adapter);
9d5c8243 1566
37680117
AD		 1567#ifdef CONFIG_PCI_IOV
1568 /* reclaim resources allocated to VFs */
1569 if (adapter->vf_data) {
1570 /* disable iov and allow time for transactions to clear */
1571 pci_disable_sriov(pdev);
1572 msleep(500);
1573
1574 kfree(adapter->vf_data);
1575 adapter->vf_data = NULL;
1576 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1577 msleep(100);
1578 dev_info(&pdev->dev, "IOV Disabled\n");
1579 }
1580#endif
28b0759c
AD		 1581 iounmap(hw->hw_addr);
1582 if (hw->flash_address)
1583 iounmap(hw->flash_address);
aed5dec3
AD		 1584 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1585 IORESOURCE_MEM));
9d5c8243
AK		 1586
1587 free_netdev(netdev);
1588
ea943d41
JK		 1589 err = pci_disable_pcie_error_reporting(pdev);
1590 if (err)
1591 dev_err(&pdev->dev,
1592 "pci_disable_pcie_error_reporting failed 0x%x\n", err);
40a914fa 1593
9d5c8243
AK		 1594 pci_disable_device(pdev);
1595}
1596
1597/**
1598 * igb_sw_init - Initialize general software structures (struct igb_adapter)
1599 * @adapter: board private structure to initialize
1600 *
1601 * igb_sw_init initializes the Adapter private data structure.
1602 * Fields are initialized based on PCI device information and
1603 * OS network device settings (MTU size).
1604 **/
1605static int __devinit igb_sw_init(struct igb_adapter *adapter)
1606{
1607 struct e1000_hw *hw = &adapter->hw;
1608 struct net_device *netdev = adapter->netdev;
1609 struct pci_dev *pdev = adapter->pdev;
1610
1611 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1612
68fd9910
AD		 1613 adapter->tx_ring_count = IGB_DEFAULT_TXD;
1614 adapter->rx_ring_count = IGB_DEFAULT_RXD;
9d5c8243
AK		 1615 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1616 adapter->rx_ps_hdr_size = 0; /* disable packet split */
1617 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1618 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1619
661086df
PWJ		 1620 /* This call may decrease the number of queues depending on
1621 * interrupt mode. */
9d5c8243
AK		 1622 igb_set_interrupt_capability(adapter);
1623
1624 if (igb_alloc_queues(adapter)) {
1625 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1626 return -ENOMEM;
1627 }
1628
1629 /* Explicitly disable IRQ since the NIC can be in any state. */
1630 igb_irq_disable(adapter);
1631
1632 set_bit(__IGB_DOWN, &adapter->state);
1633 return 0;
1634}
1635
1636/**
1637 * igb_open - Called when a network interface is made active
1638 * @netdev: network interface device structure
1639 *
1640 * Returns 0 on success, negative value on failure
1641 *
1642 * The open entry point is called when a network interface is made
1643 * active by the system (IFF_UP). At this point all resources needed
1644 * for transmit and receive operations are allocated, the interrupt
1645 * handler is registered with the OS, the watchdog timer is started,
1646 * and the stack is notified that the interface is ready.
1647 **/
1648static int igb_open(struct net_device *netdev)
1649{
1650 struct igb_adapter *adapter = netdev_priv(netdev);
1651 struct e1000_hw *hw = &adapter->hw;
1652 int err;
1653 int i;
1654
1655 /* disallow open during test */
1656 if (test_bit(__IGB_TESTING, &adapter->state))
1657 return -EBUSY;
1658
1659 /* allocate transmit descriptors */
1660 err = igb_setup_all_tx_resources(adapter);
1661 if (err)
1662 goto err_setup_tx;
1663
1664 /* allocate receive descriptors */
1665 err = igb_setup_all_rx_resources(adapter);
1666 if (err)
1667 goto err_setup_rx;
1668
1669 /* e1000_power_up_phy(adapter); */
1670
1671 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1672 if ((adapter->hw.mng_cookie.status &
1673 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1674 igb_update_mng_vlan(adapter);
1675
1676 /* before we allocate an interrupt, we must be ready to handle it.
1677 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1678 * as soon as we call pci_request_irq, so we have to setup our
1679 * clean_rx handler before we do so. */
1680 igb_configure(adapter);
1681
4ae196df 1682 igb_vmm_control(adapter);
e1739522
AD		 1683 igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
1684 igb_set_vmolr(hw, adapter->vfs_allocated_count);
1685
9d5c8243
AK		 1686 err = igb_request_irq(adapter);
1687 if (err)
1688 goto err_req_irq;
1689
1690 /* From here on the code is the same as igb_up() */
1691 clear_bit(__IGB_DOWN, &adapter->state);
1692
844290e5
PW		 1693 for (i = 0; i < adapter->num_rx_queues; i++)
1694 napi_enable(&adapter->rx_ring[i].napi);
9d5c8243
AK		 1695
1696 /* Clear any pending interrupts. */
1697 rd32(E1000_ICR);
844290e5
PW		 1698
1699 igb_irq_enable(adapter);
1700
d55b53ff
JK		 1701 netif_tx_start_all_queues(netdev);
1702
9d5c8243
AK		 1703 /* Fire a link status change interrupt to start the watchdog. */
1704 wr32(E1000_ICS, E1000_ICS_LSC);
1705
1706 return 0;
1707
1708err_req_irq:
1709 igb_release_hw_control(adapter);
1710 /* e1000_power_down_phy(adapter); */
1711 igb_free_all_rx_resources(adapter);
1712err_setup_rx:
1713 igb_free_all_tx_resources(adapter);
1714err_setup_tx:
1715 igb_reset(adapter);
1716
1717 return err;
1718}
1719
1720/**
1721 * igb_close - Disables a network interface
1722 * @netdev: network interface device structure
1723 *
1724 * Returns 0, this is not allowed to fail
1725 *
1726 * The close entry point is called when an interface is de-activated
1727 * by the OS. The hardware is still under the driver's control, but
1728 * needs to be disabled. A global MAC reset is issued to stop the
1729 * hardware, and all transmit and receive resources are freed.
1730 **/
1731static int igb_close(struct net_device *netdev)
1732{
1733 struct igb_adapter *adapter = netdev_priv(netdev);
1734
1735 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1736 igb_down(adapter);
1737
1738 igb_free_irq(adapter);
1739
1740 igb_free_all_tx_resources(adapter);
1741 igb_free_all_rx_resources(adapter);
1742
1743 /* kill manageability vlan ID if supported, but not if a vlan with
1744 * the same ID is registered on the host OS (let 8021q kill it) */
1745 if ((adapter->hw.mng_cookie.status &
1746 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1747 !(adapter->vlgrp &&
1748 vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1749 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1750
1751 return 0;
1752}
1753
1754/**
1755 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
1756 * @adapter: board private structure
1757 * @tx_ring: tx descriptor ring (for a specific queue) to setup
1758 *
1759 * Return 0 on success, negative on failure
1760 **/
9d5c8243
AK		 1761int igb_setup_tx_resources(struct igb_adapter *adapter,
1762 struct igb_ring *tx_ring)
1763{
1764 struct pci_dev *pdev = adapter->pdev;
1765 int size;
1766
1767 size = sizeof(struct igb_buffer) * tx_ring->count;
1768 tx_ring->buffer_info = vmalloc(size);
1769 if (!tx_ring->buffer_info)
1770 goto err;
1771 memset(tx_ring->buffer_info, 0, size);
1772
1773 /* round up to nearest 4K */
85e8d004 1774 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 1775 tx_ring->size = ALIGN(tx_ring->size, 4096);
1776
1777 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1778 &tx_ring->dma);
1779
1780 if (!tx_ring->desc)
1781 goto err;
1782
1783 tx_ring->adapter = adapter;
1784 tx_ring->next_to_use = 0;
1785 tx_ring->next_to_clean = 0;
9d5c8243
AK		 1786 return 0;
1787
1788err:
1789 vfree(tx_ring->buffer_info);
1790 dev_err(&adapter->pdev->dev,
1791 "Unable to allocate memory for the transmit descriptor ring\n");
1792 return -ENOMEM;
1793}
1794
1795/**
1796 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1797 * (Descriptors) for all queues
1798 * @adapter: board private structure
1799 *
1800 * Return 0 on success, negative on failure
1801 **/
1802static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1803{
1804 int i, err = 0;
661086df 1805 int r_idx;
9d5c8243
AK		 1806
1807 for (i = 0; i < adapter->num_tx_queues; i++) {
1808 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1809 if (err) {
1810 dev_err(&adapter->pdev->dev,
1811 "Allocation for Tx Queue %u failed\n", i);
1812 for (i--; i >= 0; i--)
3b644cf6 1813 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 1814 break;
1815 }
1816 }
1817
661086df
PWJ		 1818 for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
1819 r_idx = i % adapter->num_tx_queues;
1820 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
eebbbdba 1821 }
9d5c8243
AK		 1822 return err;
1823}
1824
1825/**
1826 * igb_configure_tx - Configure transmit Unit after Reset
1827 * @adapter: board private structure
1828 *
1829 * Configure the Tx unit of the MAC after a reset.
1830 **/
1831static void igb_configure_tx(struct igb_adapter *adapter)
1832{
0e014cb1 1833 u64 tdba;
9d5c8243
AK		 1834 struct e1000_hw *hw = &adapter->hw;
1835 u32 tctl;
1836 u32 txdctl, txctrl;
26bc19ec 1837 int i, j;
9d5c8243
AK		 1838
1839 for (i = 0; i < adapter->num_tx_queues; i++) {
73cd78f1 1840 struct igb_ring *ring = &adapter->tx_ring[i];
26bc19ec
AD		 1841 j = ring->reg_idx;
1842 wr32(E1000_TDLEN(j),
85e8d004 1843 ring->count * sizeof(union e1000_adv_tx_desc));
9d5c8243 1844 tdba = ring->dma;
26bc19ec 1845 wr32(E1000_TDBAL(j),
73cd78f1 1846 tdba & 0x00000000ffffffffULL);
26bc19ec 1847 wr32(E1000_TDBAH(j), tdba >> 32);
9d5c8243 1848
26bc19ec
AD		 1849 ring->head = E1000_TDH(j);
1850 ring->tail = E1000_TDT(j);
9d5c8243
AK		 1851 writel(0, hw->hw_addr + ring->tail);
1852 writel(0, hw->hw_addr + ring->head);
26bc19ec 1853 txdctl = rd32(E1000_TXDCTL(j));
9d5c8243 1854 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
26bc19ec 1855 wr32(E1000_TXDCTL(j), txdctl);
9d5c8243
AK		 1856
1857 /* Turn off Relaxed Ordering on head write-backs. The
1858 * writebacks MUST be delivered in order or it will
1859 * completely screw up our bookeeping.
1860 */
26bc19ec 1861 txctrl = rd32(E1000_DCA_TXCTRL(j));
9d5c8243 1862 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
26bc19ec 1863 wr32(E1000_DCA_TXCTRL(j), txctrl);
9d5c8243
AK		 1864 }
1865
e1739522
AD		 1866 /* disable queue 0 to prevent tail bump w/o re-configuration */
1867 if (adapter->vfs_allocated_count)
1868 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 1869
1870 /* Program the Transmit Control Register */
9d5c8243
AK		 1871 tctl = rd32(E1000_TCTL);
1872 tctl &= ~E1000_TCTL_CT;
1873 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1874 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1875
1876 igb_config_collision_dist(hw);
1877
1878 /* Setup Transmit Descriptor Settings for eop descriptor */
1879 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
1880
1881 /* Enable transmits */
1882 tctl |= E1000_TCTL_EN;
1883
1884 wr32(E1000_TCTL, tctl);
1885}
1886
1887/**
1888 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
1889 * @adapter: board private structure
1890 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1891 *
1892 * Returns 0 on success, negative on failure
1893 **/
9d5c8243
AK		 1894int igb_setup_rx_resources(struct igb_adapter *adapter,
1895 struct igb_ring *rx_ring)
1896{
1897 struct pci_dev *pdev = adapter->pdev;
1898 int size, desc_len;
1899
1900 size = sizeof(struct igb_buffer) * rx_ring->count;
1901 rx_ring->buffer_info = vmalloc(size);
1902 if (!rx_ring->buffer_info)
1903 goto err;
1904 memset(rx_ring->buffer_info, 0, size);
1905
1906 desc_len = sizeof(union e1000_adv_rx_desc);
1907
1908 /* Round up to nearest 4K */
1909 rx_ring->size = rx_ring->count * desc_len;
1910 rx_ring->size = ALIGN(rx_ring->size, 4096);
1911
1912 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1913 &rx_ring->dma);
1914
1915 if (!rx_ring->desc)
1916 goto err;
1917
1918 rx_ring->next_to_clean = 0;
1919 rx_ring->next_to_use = 0;
9d5c8243
AK		 1920
1921 rx_ring->adapter = adapter;
9d5c8243
AK		 1922
1923 return 0;
1924
1925err:
1926 vfree(rx_ring->buffer_info);
1927 dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
1928 "the receive descriptor ring\n");
1929 return -ENOMEM;
1930}
1931
1932/**
1933 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
1934 * (Descriptors) for all queues
1935 * @adapter: board private structure
1936 *
1937 * Return 0 on success, negative on failure
1938 **/
1939static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
1940{
1941 int i, err = 0;
1942
1943 for (i = 0; i < adapter->num_rx_queues; i++) {
1944 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1945 if (err) {
1946 dev_err(&adapter->pdev->dev,
1947 "Allocation for Rx Queue %u failed\n", i);
1948 for (i--; i >= 0; i--)
3b644cf6 1949 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 1950 break;
1951 }
1952 }
1953
1954 return err;
1955}
1956
1957/**
1958 * igb_setup_rctl - configure the receive control registers
1959 * @adapter: Board private structure
1960 **/
1961static void igb_setup_rctl(struct igb_adapter *adapter)
1962{
1963 struct e1000_hw *hw = &adapter->hw;
1964 u32 rctl;
1965 u32 srrctl = 0;
26bc19ec 1966 int i, j;
9d5c8243
AK		 1967
1968 rctl = rd32(E1000_RCTL);
1969
1970 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 1971 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 1972
69d728ba 1973 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 1974 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 1975
87cb7e8c
AK		 1976 /*
1977 * enable stripping of CRC. It's unlikely this will break BMC
1978 * redirection as it did with e1000. Newer features require
1979 * that the HW strips the CRC.
73cd78f1 1980 */
87cb7e8c 1981 rctl |= E1000_RCTL_SECRC;
9d5c8243 1982
9b07f3d3 1983 /*
ec54d7d6 1984 * disable store bad packets and clear size bits.
9b07f3d3 1985 */
ec54d7d6 1986 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 1987
ec54d7d6 1988 /* enable LPE when to prevent packets larger than max_frame_size */
9b07f3d3 1989 rctl |= E1000_RCTL_LPE;
b4557be2
AD		 1990
1991 /* Setup buffer sizes */
1992 switch (adapter->rx_buffer_len) {
1993 case IGB_RXBUFFER_256:
1994 rctl |= E1000_RCTL_SZ_256;
1995 break;
1996 case IGB_RXBUFFER_512:
1997 rctl |= E1000_RCTL_SZ_512;
1998 break;
1999 default:
2000 srrctl = ALIGN(adapter->rx_buffer_len, 1024)
2001 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2002 break;
9d5c8243
AK		 2003 }
2004
2005 /* 82575 and greater support packet-split where the protocol
2006 * header is placed in skb->data and the packet data is
2007 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
2008 * In the case of a non-split, skb->data is linearly filled,
2009 * followed by the page buffers. Therefore, skb->data is
2010 * sized to hold the largest protocol header.
2011 */
2012 /* allocations using alloc_page take too long for regular MTU
2013 * so only enable packet split for jumbo frames */
ec54d7d6 2014 if (adapter->netdev->mtu > ETH_DATA_LEN) {
9d5c8243 2015 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
bf36c1a0 2016 srrctl |= adapter->rx_ps_hdr_size <<
9d5c8243 2017 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
9d5c8243
AK		 2018 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2019 } else {
2020 adapter->rx_ps_hdr_size = 0;
2021 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2022 }
2023
e1739522
AD		 2024 /* Attention!!! For SR-IOV PF driver operations you must enable
2025 * queue drop for all VF and PF queues to prevent head of line blocking
2026 * if an un-trusted VF does not provide descriptors to hardware.
2027 */
2028 if (adapter->vfs_allocated_count) {
2029 u32 vmolr;
2030
2031 j = adapter->rx_ring[0].reg_idx;
2032
2033 /* set all queue drop enable bits */
2034 wr32(E1000_QDE, ALL_QUEUES);
2035 srrctl |= E1000_SRRCTL_DROP_EN;
2036
2037 /* disable queue 0 to prevent tail write w/o re-config */
2038 wr32(E1000_RXDCTL(0), 0);
2039
2040 vmolr = rd32(E1000_VMOLR(j));
2041 if (rctl & E1000_RCTL_LPE)
2042 vmolr |= E1000_VMOLR_LPE;
2043 if (adapter->num_rx_queues > 0)
2044 vmolr |= E1000_VMOLR_RSSE;
2045 wr32(E1000_VMOLR(j), vmolr);
2046 }
2047
26bc19ec
AD		 2048 for (i = 0; i < adapter->num_rx_queues; i++) {
2049 j = adapter->rx_ring[i].reg_idx;
2050 wr32(E1000_SRRCTL(j), srrctl);
2051 }
9d5c8243
AK		 2052
2053 wr32(E1000_RCTL, rctl);
2054}
2055
e1739522
AD		 2056/**
2057 * igb_rlpml_set - set maximum receive packet size
2058 * @adapter: board private structure
2059 *
2060 * Configure maximum receivable packet size.
2061 **/
2062static void igb_rlpml_set(struct igb_adapter *adapter)
2063{
2064 u32 max_frame_size = adapter->max_frame_size;
2065 struct e1000_hw *hw = &adapter->hw;
2066 u16 pf_id = adapter->vfs_allocated_count;
2067
2068 if (adapter->vlgrp)
2069 max_frame_size += VLAN_TAG_SIZE;
2070
2071 /* if vfs are enabled we set RLPML to the largest possible request
2072 * size and set the VMOLR RLPML to the size we need */
2073 if (pf_id) {
2074 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
2075 max_frame_size = MAX_STD_JUMBO_FRAME_SIZE + VLAN_TAG_SIZE;
2076 }
2077
2078 wr32(E1000_RLPML, max_frame_size);
2079}
2080
2081/**
2082 * igb_configure_vt_default_pool - Configure VT default pool
2083 * @adapter: board private structure
2084 *
2085 * Configure the default pool
2086 **/
2087static void igb_configure_vt_default_pool(struct igb_adapter *adapter)
2088{
2089 struct e1000_hw *hw = &adapter->hw;
2090 u16 pf_id = adapter->vfs_allocated_count;
2091 u32 vtctl;
2092
2093 /* not in sr-iov mode - do nothing */
2094 if (!pf_id)
2095 return;
2096
2097 vtctl = rd32(E1000_VT_CTL);
2098 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
2099 E1000_VT_CTL_DISABLE_DEF_POOL);
2100 vtctl |= pf_id << E1000_VT_CTL_DEFAULT_POOL_SHIFT;
2101 wr32(E1000_VT_CTL, vtctl);
2102}
2103
9d5c8243
AK		 2104/**
2105 * igb_configure_rx - Configure receive Unit after Reset
2106 * @adapter: board private structure
2107 *
2108 * Configure the Rx unit of the MAC after a reset.
2109 **/
2110static void igb_configure_rx(struct igb_adapter *adapter)
2111{
2112 u64 rdba;
2113 struct e1000_hw *hw = &adapter->hw;
2114 u32 rctl, rxcsum;
2115 u32 rxdctl;
9107584e 2116 int i;
9d5c8243
AK		 2117
2118 /* disable receives while setting up the descriptors */
2119 rctl = rd32(E1000_RCTL);
2120 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
2121 wrfl();
2122 mdelay(10);
2123
2124 if (adapter->itr_setting > 3)
6eb5a7f1 2125 wr32(E1000_ITR, adapter->itr);
9d5c8243
AK		 2126
2127 /* Setup the HW Rx Head and Tail Descriptor Pointers and
2128 * the Base and Length of the Rx Descriptor Ring */
2129 for (i = 0; i < adapter->num_rx_queues; i++) {
73cd78f1 2130 struct igb_ring *ring = &adapter->rx_ring[i];
9107584e 2131 int j = ring->reg_idx;
9d5c8243 2132 rdba = ring->dma;
26bc19ec 2133 wr32(E1000_RDBAL(j),
73cd78f1 2134 rdba & 0x00000000ffffffffULL);
26bc19ec
AD		 2135 wr32(E1000_RDBAH(j), rdba >> 32);
2136 wr32(E1000_RDLEN(j),
73cd78f1 2137 ring->count * sizeof(union e1000_adv_rx_desc));
9d5c8243 2138
26bc19ec
AD		 2139 ring->head = E1000_RDH(j);
2140 ring->tail = E1000_RDT(j);
9d5c8243
AK		 2141 writel(0, hw->hw_addr + ring->tail);
2142 writel(0, hw->hw_addr + ring->head);
2143
26bc19ec 2144 rxdctl = rd32(E1000_RXDCTL(j));
9d5c8243
AK		 2145 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2146 rxdctl &= 0xFFF00000;
2147 rxdctl |= IGB_RX_PTHRESH;
2148 rxdctl |= IGB_RX_HTHRESH << 8;
2149 rxdctl |= IGB_RX_WTHRESH << 16;
26bc19ec 2150 wr32(E1000_RXDCTL(j), rxdctl);
9d5c8243
AK		 2151 }
2152
2153 if (adapter->num_rx_queues > 1) {
2154 u32 random[10];
2155 u32 mrqc;
2156 u32 j, shift;
2157 union e1000_reta {
2158 u32 dword;
2159 u8 bytes[4];
2160 } reta;
2161
2162 get_random_bytes(&random[0], 40);
2163
2d064c06
AD		 2164 if (hw->mac.type >= e1000_82576)
2165 shift = 0;
2166 else
2167 shift = 6;
9d5c8243
AK		 2168 for (j = 0; j < (32 * 4); j++) {
2169 reta.bytes[j & 3] =
26bc19ec 2170 adapter->rx_ring[(j % adapter->num_rx_queues)].reg_idx << shift;
9d5c8243
AK		 2171 if ((j & 3) == 3)
2172 writel(reta.dword,
2173 hw->hw_addr + E1000_RETA(0) + (j & ~3));
2174 }
e1739522
AD		 2175 if (adapter->vfs_allocated_count)
2176 mrqc = E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
2177 else
2178 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
9d5c8243
AK		 2179
2180 /* Fill out hash function seeds */
2181 for (j = 0; j < 10; j++)
2182 array_wr32(E1000_RSSRK(0), j, random[j]);
2183
2184 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2185 E1000_MRQC_RSS_FIELD_IPV4_TCP);
2186 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2187 E1000_MRQC_RSS_FIELD_IPV6_TCP);
2188 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
2189 E1000_MRQC_RSS_FIELD_IPV6_UDP);
2190 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2191 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2192
2193
2194 wr32(E1000_MRQC, mrqc);
2195
2196 /* Multiqueue and raw packet checksumming are mutually
2197 * exclusive. Note that this not the same as TCP/IP
2198 * checksumming, which works fine. */
2199 rxcsum = rd32(E1000_RXCSUM);
2200 rxcsum |= E1000_RXCSUM_PCSD;
2201 wr32(E1000_RXCSUM, rxcsum);
2202 } else {
e1739522
AD		 2203 /* Enable multi-queue for sr-iov */
2204 if (adapter->vfs_allocated_count)
2205 wr32(E1000_MRQC, E1000_MRQC_ENABLE_VMDQ);
9d5c8243
AK		 2206 /* Enable Receive Checksum Offload for TCP and UDP */
2207 rxcsum = rd32(E1000_RXCSUM);
56fbbb4e
AD		 2208 if (adapter->rx_csum)
2209 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPPCSE;
2210 else
2211 rxcsum &= ~(E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPPCSE);
2212
9d5c8243
AK		 2213 wr32(E1000_RXCSUM, rxcsum);
2214 }
2215
e1739522
AD		 2216 /* Set the default pool for the PF's first queue */
2217 igb_configure_vt_default_pool(adapter);
2218
2219 igb_rlpml_set(adapter);
9d5c8243
AK		 2220
2221 /* Enable Receives */
2222 wr32(E1000_RCTL, rctl);
2223}
2224
2225/**
2226 * igb_free_tx_resources - Free Tx Resources per Queue
9d5c8243
AK		 2227 * @tx_ring: Tx descriptor ring for a specific queue
2228 *
2229 * Free all transmit software resources
2230 **/
68fd9910 2231void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 2232{
3b644cf6 2233 struct pci_dev *pdev = tx_ring->adapter->pdev;
9d5c8243 2234
3b644cf6 2235 igb_clean_tx_ring(tx_ring);
9d5c8243
AK		 2236
2237 vfree(tx_ring->buffer_info);
2238 tx_ring->buffer_info = NULL;
2239
2240 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
2241
2242 tx_ring->desc = NULL;
2243}
2244
2245/**
2246 * igb_free_all_tx_resources - Free Tx Resources for All Queues
2247 * @adapter: board private structure
2248 *
2249 * Free all transmit software resources
2250 **/
2251static void igb_free_all_tx_resources(struct igb_adapter *adapter)
2252{
2253 int i;
2254
2255 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2256 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 2257}
2258
2259static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
2260 struct igb_buffer *buffer_info)
2261{
2262 if (buffer_info->dma) {
2263 pci_unmap_page(adapter->pdev,
2264 buffer_info->dma,
2265 buffer_info->length,
2266 PCI_DMA_TODEVICE);
2267 buffer_info->dma = 0;
2268 }
2269 if (buffer_info->skb) {
2270 dev_kfree_skb_any(buffer_info->skb);
2271 buffer_info->skb = NULL;
2272 }
2273 buffer_info->time_stamp = 0;
73cd78f1 2274 buffer_info->next_to_watch = 0;
9d5c8243
AK		 2275 /* buffer_info must be completely set up in the transmit path */
2276}
2277
2278/**
2279 * igb_clean_tx_ring - Free Tx Buffers
9d5c8243
AK		 2280 * @tx_ring: ring to be cleaned
2281 **/
3b644cf6 2282static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 2283{
3b644cf6 2284 struct igb_adapter *adapter = tx_ring->adapter;
9d5c8243
AK		 2285 struct igb_buffer *buffer_info;
2286 unsigned long size;
2287 unsigned int i;
2288
2289 if (!tx_ring->buffer_info)
2290 return;
2291 /* Free all the Tx ring sk_buffs */
2292
2293 for (i = 0; i < tx_ring->count; i++) {
2294 buffer_info = &tx_ring->buffer_info[i];
2295 igb_unmap_and_free_tx_resource(adapter, buffer_info);
2296 }
2297
2298 size = sizeof(struct igb_buffer) * tx_ring->count;
2299 memset(tx_ring->buffer_info, 0, size);
2300
2301 /* Zero out the descriptor ring */
2302
2303 memset(tx_ring->desc, 0, tx_ring->size);
2304
2305 tx_ring->next_to_use = 0;
2306 tx_ring->next_to_clean = 0;
2307
2308 writel(0, adapter->hw.hw_addr + tx_ring->head);
2309 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2310}
2311
2312/**
2313 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2314 * @adapter: board private structure
2315 **/
2316static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2317{
2318 int i;
2319
2320 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2321 igb_clean_tx_ring(&adapter->tx_ring[i]);
9d5c8243
AK		 2322}
2323
2324/**
2325 * igb_free_rx_resources - Free Rx Resources
9d5c8243
AK		 2326 * @rx_ring: ring to clean the resources from
2327 *
2328 * Free all receive software resources
2329 **/
68fd9910 2330void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2331{
3b644cf6 2332 struct pci_dev *pdev = rx_ring->adapter->pdev;
9d5c8243 2333
3b644cf6 2334 igb_clean_rx_ring(rx_ring);
9d5c8243
AK		 2335
2336 vfree(rx_ring->buffer_info);
2337 rx_ring->buffer_info = NULL;
2338
2339 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2340
2341 rx_ring->desc = NULL;
2342}
2343
2344/**
2345 * igb_free_all_rx_resources - Free Rx Resources for All Queues
2346 * @adapter: board private structure
2347 *
2348 * Free all receive software resources
2349 **/
2350static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2351{
2352 int i;
2353
2354 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2355 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 2356}
2357
2358/**
2359 * igb_clean_rx_ring - Free Rx Buffers per Queue
9d5c8243
AK		 2360 * @rx_ring: ring to free buffers from
2361 **/
3b644cf6 2362static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 2363{
3b644cf6 2364 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 2365 struct igb_buffer *buffer_info;
2366 struct pci_dev *pdev = adapter->pdev;
2367 unsigned long size;
2368 unsigned int i;
2369
2370 if (!rx_ring->buffer_info)
2371 return;
2372 /* Free all the Rx ring sk_buffs */
2373 for (i = 0; i < rx_ring->count; i++) {
2374 buffer_info = &rx_ring->buffer_info[i];
2375 if (buffer_info->dma) {
2376 if (adapter->rx_ps_hdr_size)
2377 pci_unmap_single(pdev, buffer_info->dma,
2378 adapter->rx_ps_hdr_size,
2379 PCI_DMA_FROMDEVICE);
2380 else
2381 pci_unmap_single(pdev, buffer_info->dma,
2382 adapter->rx_buffer_len,
2383 PCI_DMA_FROMDEVICE);
2384 buffer_info->dma = 0;
2385 }
2386
2387 if (buffer_info->skb) {
2388 dev_kfree_skb(buffer_info->skb);
2389 buffer_info->skb = NULL;
2390 }
2391 if (buffer_info->page) {
bf36c1a0
AD		 2392 if (buffer_info->page_dma)
2393 pci_unmap_page(pdev, buffer_info->page_dma,
2394 PAGE_SIZE / 2,
2395 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 2396 put_page(buffer_info->page);
2397 buffer_info->page = NULL;
2398 buffer_info->page_dma = 0;
bf36c1a0 2399 buffer_info->page_offset = 0;
9d5c8243
AK		 2400 }
2401 }
2402
9d5c8243
AK		 2403 size = sizeof(struct igb_buffer) * rx_ring->count;
2404 memset(rx_ring->buffer_info, 0, size);
2405
2406 /* Zero out the descriptor ring */
2407 memset(rx_ring->desc, 0, rx_ring->size);
2408
2409 rx_ring->next_to_clean = 0;
2410 rx_ring->next_to_use = 0;
2411
2412 writel(0, adapter->hw.hw_addr + rx_ring->head);
2413 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2414}
2415
2416/**
2417 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2418 * @adapter: board private structure
2419 **/
2420static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2421{
2422 int i;
2423
2424 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2425 igb_clean_rx_ring(&adapter->rx_ring[i]);
9d5c8243
AK		 2426}
2427
2428/**
2429 * igb_set_mac - Change the Ethernet Address of the NIC
2430 * @netdev: network interface device structure
2431 * @p: pointer to an address structure
2432 *
2433 * Returns 0 on success, negative on failure
2434 **/
2435static int igb_set_mac(struct net_device *netdev, void *p)
2436{
2437 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 2438 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 2439 struct sockaddr *addr = p;
2440
2441 if (!is_valid_ether_addr(addr->sa_data))
2442 return -EADDRNOTAVAIL;
2443
2444 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 2445 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 2446
28b0759c 2447 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
9d5c8243 2448
e1739522
AD		 2449 igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
2450
9d5c8243
AK		 2451 return 0;
2452}
2453
2454/**
2455 * igb_set_multi - Multicast and Promiscuous mode set
2456 * @netdev: network interface device structure
2457 *
2458 * The set_multi entry point is called whenever the multicast address
2459 * list or the network interface flags are updated. This routine is
2460 * responsible for configuring the hardware for proper multicast,
2461 * promiscuous mode, and all-multi behavior.
2462 **/
2463static void igb_set_multi(struct net_device *netdev)
2464{
2465 struct igb_adapter *adapter = netdev_priv(netdev);
2466 struct e1000_hw *hw = &adapter->hw;
2467 struct e1000_mac_info *mac = &hw->mac;
2468 struct dev_mc_list *mc_ptr;
2469 u8 *mta_list;
2470 u32 rctl;
2471 int i;
2472
2473 /* Check for Promiscuous and All Multicast modes */
2474
2475 rctl = rd32(E1000_RCTL);
2476
746b9f02 2477 if (netdev->flags & IFF_PROMISC) {
9d5c8243 2478 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
746b9f02
PM		 2479 rctl &= ~E1000_RCTL_VFE;
2480 } else {
2481 if (netdev->flags & IFF_ALLMULTI) {
2482 rctl |= E1000_RCTL_MPE;
2483 rctl &= ~E1000_RCTL_UPE;
2484 } else
2485 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
78ed11a5 2486 rctl |= E1000_RCTL_VFE;
746b9f02 2487 }
9d5c8243
AK		 2488 wr32(E1000_RCTL, rctl);
2489
2490 if (!netdev->mc_count) {
2491 /* nothing to program, so clear mc list */
8a900862
AD		 2492 igb_update_mc_addr_list(hw, NULL, 0, 1,
2493 mac->rar_entry_count);
9d5c8243
AK		 2494 return;
2495 }
2496
2497 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2498 if (!mta_list)
2499 return;
2500
2501 /* The shared function expects a packed array of only addresses. */
2502 mc_ptr = netdev->mc_list;
2503
2504 for (i = 0; i < netdev->mc_count; i++) {
2505 if (!mc_ptr)
2506 break;
2507 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2508 mc_ptr = mc_ptr->next;
2509 }
e1739522
AD		 2510 igb_update_mc_addr_list(hw, mta_list, i,
2511 adapter->vfs_allocated_count + 1,
2512 mac->rar_entry_count);
2513
2514 igb_set_mc_list_pools(adapter, i, mac->rar_entry_count);
4ae196df
AD		 2515 igb_restore_vf_multicasts(adapter);
2516
9d5c8243
AK		 2517 kfree(mta_list);
2518}
2519
2520/* Need to wait a few seconds after link up to get diagnostic information from
2521 * the phy */
2522static void igb_update_phy_info(unsigned long data)
2523{
2524 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 2525 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 2526}
2527
4d6b725e
AD		 2528/**
2529 * igb_has_link - check shared code for link and determine up/down
2530 * @adapter: pointer to driver private info
2531 **/
2532static bool igb_has_link(struct igb_adapter *adapter)
2533{
2534 struct e1000_hw *hw = &adapter->hw;
2535 bool link_active = false;
2536 s32 ret_val = 0;
2537
2538 /* get_link_status is set on LSC (link status) interrupt or
2539 * rx sequence error interrupt. get_link_status will stay
2540 * false until the e1000_check_for_link establishes link
2541 * for copper adapters ONLY
2542 */
2543 switch (hw->phy.media_type) {
2544 case e1000_media_type_copper:
2545 if (hw->mac.get_link_status) {
2546 ret_val = hw->mac.ops.check_for_link(hw);
2547 link_active = !hw->mac.get_link_status;
2548 } else {
2549 link_active = true;
2550 }
2551 break;
2552 case e1000_media_type_fiber:
2553 ret_val = hw->mac.ops.check_for_link(hw);
2554 link_active = !!(rd32(E1000_STATUS) & E1000_STATUS_LU);
2555 break;
2556 case e1000_media_type_internal_serdes:
2557 ret_val = hw->mac.ops.check_for_link(hw);
2558 link_active = hw->mac.serdes_has_link;
2559 break;
2560 default:
2561 case e1000_media_type_unknown:
2562 break;
2563 }
2564
2565 return link_active;
2566}
2567
9d5c8243
AK		 2568/**
2569 * igb_watchdog - Timer Call-back
2570 * @data: pointer to adapter cast into an unsigned long
2571 **/
2572static void igb_watchdog(unsigned long data)
2573{
2574 struct igb_adapter *adapter = (struct igb_adapter *)data;
2575 /* Do the rest outside of interrupt context */
2576 schedule_work(&adapter->watchdog_task);
2577}
2578
2579static void igb_watchdog_task(struct work_struct *work)
2580{
2581 struct igb_adapter *adapter = container_of(work,
2582 struct igb_adapter, watchdog_task);
2583 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 2584 struct net_device *netdev = adapter->netdev;
2585 struct igb_ring *tx_ring = adapter->tx_ring;
9d5c8243 2586 u32 link;
7a6ea550 2587 u32 eics = 0;
7a6ea550 2588 int i;
9d5c8243 2589
4d6b725e
AD		 2590 link = igb_has_link(adapter);
2591 if ((netif_carrier_ok(netdev)) && link)
9d5c8243
AK		 2592 goto link_up;
2593
9d5c8243
AK		 2594 if (link) {
2595 if (!netif_carrier_ok(netdev)) {
2596 u32 ctrl;
2597 hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2598 &adapter->link_speed,
2599 &adapter->link_duplex);
2600
2601 ctrl = rd32(E1000_CTRL);
527d47c1
AD		 2602 /* Links status message must follow this format */
2603 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
9d5c8243 2604 "Flow Control: %s\n",
527d47c1 2605 netdev->name,
9d5c8243
AK		 2606 adapter->link_speed,
2607 adapter->link_duplex == FULL_DUPLEX ?
2608 "Full Duplex" : "Half Duplex",
2609 ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2610 E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2611 E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2612 E1000_CTRL_TFCE) ? "TX" : "None")));
2613
2614 /* tweak tx_queue_len according to speed/duplex and
2615 * adjust the timeout factor */
2616 netdev->tx_queue_len = adapter->tx_queue_len;
2617 adapter->tx_timeout_factor = 1;
2618 switch (adapter->link_speed) {
2619 case SPEED_10:
2620 netdev->tx_queue_len = 10;
2621 adapter->tx_timeout_factor = 14;
2622 break;
2623 case SPEED_100:
2624 netdev->tx_queue_len = 100;
2625 /* maybe add some timeout factor ? */
2626 break;
2627 }
2628
2629 netif_carrier_on(netdev);
fd2ea0a7 2630 netif_tx_wake_all_queues(netdev);
9d5c8243 2631
4ae196df
AD		 2632 igb_ping_all_vfs(adapter);
2633
4b1a9877 2634 /* link state has changed, schedule phy info update */
9d5c8243
AK		 2635 if (!test_bit(__IGB_DOWN, &adapter->state))
2636 mod_timer(&adapter->phy_info_timer,
2637 round_jiffies(jiffies + 2 * HZ));
2638 }
2639 } else {
2640 if (netif_carrier_ok(netdev)) {
2641 adapter->link_speed = 0;
2642 adapter->link_duplex = 0;
527d47c1
AD		 2643 /* Links status message must follow this format */
2644 printk(KERN_INFO "igb: %s NIC Link is Down\n",
2645 netdev->name);
9d5c8243 2646 netif_carrier_off(netdev);
fd2ea0a7 2647 netif_tx_stop_all_queues(netdev);
4b1a9877 2648
4ae196df
AD		 2649 igb_ping_all_vfs(adapter);
2650
4b1a9877 2651 /* link state has changed, schedule phy info update */
9d5c8243
AK		 2652 if (!test_bit(__IGB_DOWN, &adapter->state))
2653 mod_timer(&adapter->phy_info_timer,
2654 round_jiffies(jiffies + 2 * HZ));
2655 }
2656 }
2657
2658link_up:
2659 igb_update_stats(adapter);
2660
4b1a9877 2661 hw->mac.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
9d5c8243 2662 adapter->tpt_old = adapter->stats.tpt;
4b1a9877 2663 hw->mac.collision_delta = adapter->stats.colc - adapter->colc_old;
9d5c8243
AK		 2664 adapter->colc_old = adapter->stats.colc;
2665
2666 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2667 adapter->gorc_old = adapter->stats.gorc;
2668 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2669 adapter->gotc_old = adapter->stats.gotc;
2670
2671 igb_update_adaptive(&adapter->hw);
2672
2673 if (!netif_carrier_ok(netdev)) {
2674 if (IGB_DESC_UNUSED(tx_ring) + 1 < tx_ring->count) {
2675 /* We've lost link, so the controller stops DMA,
2676 * but we've got queued Tx work that's never going
2677 * to get done, so reset controller to flush Tx.
2678 * (Do the reset outside of interrupt context). */
2679 adapter->tx_timeout_count++;
2680 schedule_work(&adapter->reset_task);
2681 }
2682 }
2683
2684 /* Cause software interrupt to ensure rx ring is cleaned */
7a6ea550
AD		 2685 if (adapter->msix_entries) {
2686 for (i = 0; i < adapter->num_rx_queues; i++)
2687 eics |= adapter->rx_ring[i].eims_value;
2688 wr32(E1000_EICS, eics);
2689 } else {
2690 wr32(E1000_ICS, E1000_ICS_RXDMT0);
2691 }
9d5c8243
AK		 2692
2693 /* Force detection of hung controller every watchdog period */
2694 tx_ring->detect_tx_hung = true;
2695
2696 /* Reset the timer */
2697 if (!test_bit(__IGB_DOWN, &adapter->state))
2698 mod_timer(&adapter->watchdog_timer,
2699 round_jiffies(jiffies + 2 * HZ));
2700}
2701
2702enum latency_range {
2703 lowest_latency = 0,
2704 low_latency = 1,
2705 bulk_latency = 2,
2706 latency_invalid = 255
2707};
2708
2709
6eb5a7f1
AD		 2710/**
2711 * igb_update_ring_itr - update the dynamic ITR value based on packet size
2712 *
2713 * Stores a new ITR value based on strictly on packet size. This
2714 * algorithm is less sophisticated than that used in igb_update_itr,
2715 * due to the difficulty of synchronizing statistics across multiple
2716 * receive rings. The divisors and thresholds used by this fuction
2717 * were determined based on theoretical maximum wire speed and testing
2718 * data, in order to minimize response time while increasing bulk
2719 * throughput.
2720 * This functionality is controlled by the InterruptThrottleRate module
2721 * parameter (see igb_param.c)
2722 * NOTE: This function is called only when operating in a multiqueue
2723 * receive environment.
2724 * @rx_ring: pointer to ring
2725 **/
2726static void igb_update_ring_itr(struct igb_ring *rx_ring)
9d5c8243 2727{
6eb5a7f1
AD		 2728 int new_val = rx_ring->itr_val;
2729 int avg_wire_size = 0;
2730 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 2731
6eb5a7f1
AD		 2732 if (!rx_ring->total_packets)
2733 goto clear_counts; /* no packets, so don't do anything */
9d5c8243 2734
6eb5a7f1
AD		 2735 /* For non-gigabit speeds, just fix the interrupt rate at 4000
2736 * ints/sec - ITR timer value of 120 ticks.
2737 */
2738 if (adapter->link_speed != SPEED_1000) {
2739 new_val = 120;
2740 goto set_itr_val;
9d5c8243 2741 }
6eb5a7f1 2742 avg_wire_size = rx_ring->total_bytes / rx_ring->total_packets;
9d5c8243 2743
6eb5a7f1
AD		 2744 /* Add 24 bytes to size to account for CRC, preamble, and gap */
2745 avg_wire_size += 24;
2746
2747 /* Don't starve jumbo frames */
2748 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 2749
6eb5a7f1
AD		 2750 /* Give a little boost to mid-size frames */
2751 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
2752 new_val = avg_wire_size / 3;
2753 else
2754 new_val = avg_wire_size / 2;
9d5c8243 2755
6eb5a7f1 2756set_itr_val:
9d5c8243
AK		 2757 if (new_val != rx_ring->itr_val) {
2758 rx_ring->itr_val = new_val;
6eb5a7f1 2759 rx_ring->set_itr = 1;
9d5c8243 2760 }
6eb5a7f1
AD		 2761clear_counts:
2762 rx_ring->total_bytes = 0;
2763 rx_ring->total_packets = 0;
9d5c8243
AK		 2764}
2765
2766/**
2767 * igb_update_itr - update the dynamic ITR value based on statistics
2768 * Stores a new ITR value based on packets and byte
2769 * counts during the last interrupt. The advantage of per interrupt
2770 * computation is faster updates and more accurate ITR for the current
2771 * traffic pattern. Constants in this function were computed
2772 * based on theoretical maximum wire speed and thresholds were set based
2773 * on testing data as well as attempting to minimize response time
2774 * while increasing bulk throughput.
2775 * this functionality is controlled by the InterruptThrottleRate module
2776 * parameter (see igb_param.c)
2777 * NOTE: These calculations are only valid when operating in a single-
2778 * queue environment.
2779 * @adapter: pointer to adapter
2780 * @itr_setting: current adapter->itr
2781 * @packets: the number of packets during this measurement interval
2782 * @bytes: the number of bytes during this measurement interval
2783 **/
2784static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
2785 int packets, int bytes)
2786{
2787 unsigned int retval = itr_setting;
2788
2789 if (packets == 0)
2790 goto update_itr_done;
2791
2792 switch (itr_setting) {
2793 case lowest_latency:
2794 /* handle TSO and jumbo frames */
2795 if (bytes/packets > 8000)
2796 retval = bulk_latency;
2797 else if ((packets < 5) && (bytes > 512))
2798 retval = low_latency;
2799 break;
2800 case low_latency: /* 50 usec aka 20000 ints/s */
2801 if (bytes > 10000) {
2802 /* this if handles the TSO accounting */
2803 if (bytes/packets > 8000) {
2804 retval = bulk_latency;
2805 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
2806 retval = bulk_latency;
2807 } else if ((packets > 35)) {
2808 retval = lowest_latency;
2809 }
2810 } else if (bytes/packets > 2000) {
2811 retval = bulk_latency;
2812 } else if (packets <= 2 && bytes < 512) {
2813 retval = lowest_latency;
2814 }
2815 break;
2816 case bulk_latency: /* 250 usec aka 4000 ints/s */
2817 if (bytes > 25000) {
2818 if (packets > 35)
2819 retval = low_latency;
1e5c3d21 2820 } else if (bytes < 1500) {
9d5c8243
AK		 2821 retval = low_latency;
2822 }
2823 break;
2824 }
2825
2826update_itr_done:
2827 return retval;
2828}
2829
6eb5a7f1 2830static void igb_set_itr(struct igb_adapter *adapter)
9d5c8243
AK		 2831{
2832 u16 current_itr;
2833 u32 new_itr = adapter->itr;
2834
2835 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2836 if (adapter->link_speed != SPEED_1000) {
2837 current_itr = 0;
2838 new_itr = 4000;
2839 goto set_itr_now;
2840 }
2841
2842 adapter->rx_itr = igb_update_itr(adapter,
2843 adapter->rx_itr,
2844 adapter->rx_ring->total_packets,
2845 adapter->rx_ring->total_bytes);
9d5c8243 2846
6eb5a7f1 2847 if (adapter->rx_ring->buddy) {
9d5c8243
AK		 2848 adapter->tx_itr = igb_update_itr(adapter,
2849 adapter->tx_itr,
2850 adapter->tx_ring->total_packets,
2851 adapter->tx_ring->total_bytes);
9d5c8243
AK		 2852 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2853 } else {
2854 current_itr = adapter->rx_itr;
2855 }
2856
6eb5a7f1 2857 /* conservative mode (itr 3) eliminates the lowest_latency setting */
73cd78f1 2858 if (adapter->itr_setting == 3 && current_itr == lowest_latency)
6eb5a7f1
AD		 2859 current_itr = low_latency;
2860
9d5c8243
AK		 2861 switch (current_itr) {
2862 /* counts and packets in update_itr are dependent on these numbers */
2863 case lowest_latency:
2864 new_itr = 70000;
2865 break;
2866 case low_latency:
2867 new_itr = 20000; /* aka hwitr = ~200 */
2868 break;
2869 case bulk_latency:
2870 new_itr = 4000;
2871 break;
2872 default:
2873 break;
2874 }
2875
2876set_itr_now:
6eb5a7f1
AD		 2877 adapter->rx_ring->total_bytes = 0;
2878 adapter->rx_ring->total_packets = 0;
2879 if (adapter->rx_ring->buddy) {
2880 adapter->rx_ring->buddy->total_bytes = 0;
2881 adapter->rx_ring->buddy->total_packets = 0;
2882 }
2883
9d5c8243
AK		 2884 if (new_itr != adapter->itr) {
2885 /* this attempts to bias the interrupt rate towards Bulk
2886 * by adding intermediate steps when interrupt rate is
2887 * increasing */
2888 new_itr = new_itr > adapter->itr ?
2889 min(adapter->itr + (new_itr >> 2), new_itr) :
2890 new_itr;
2891 /* Don't write the value here; it resets the adapter's
2892 * internal timer, and causes us to delay far longer than
2893 * we should between interrupts. Instead, we write the ITR
2894 * value at the beginning of the next interrupt so the timing
2895 * ends up being correct.
2896 */
2897 adapter->itr = new_itr;
6eb5a7f1
AD		 2898 adapter->rx_ring->itr_val = 1000000000 / (new_itr * 256);
2899 adapter->rx_ring->set_itr = 1;
9d5c8243
AK		 2900 }
2901
2902 return;
2903}
2904
2905
2906#define IGB_TX_FLAGS_CSUM 0x00000001
2907#define IGB_TX_FLAGS_VLAN 0x00000002
2908#define IGB_TX_FLAGS_TSO 0x00000004
2909#define IGB_TX_FLAGS_IPV4 0x00000008
33af6bcc 2910#define IGB_TX_FLAGS_TSTAMP 0x00000010
9d5c8243
AK		 2911#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
2912#define IGB_TX_FLAGS_VLAN_SHIFT 16
2913
2914static inline int igb_tso_adv(struct igb_adapter *adapter,
2915 struct igb_ring *tx_ring,
2916 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
2917{
2918 struct e1000_adv_tx_context_desc *context_desc;
2919 unsigned int i;
2920 int err;
2921 struct igb_buffer *buffer_info;
2922 u32 info = 0, tu_cmd = 0;
2923 u32 mss_l4len_idx, l4len;
2924 *hdr_len = 0;
2925
2926 if (skb_header_cloned(skb)) {
2927 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2928 if (err)
2929 return err;
2930 }
2931
2932 l4len = tcp_hdrlen(skb);
2933 *hdr_len += l4len;
2934
2935 if (skb->protocol == htons(ETH_P_IP)) {
2936 struct iphdr *iph = ip_hdr(skb);
2937 iph->tot_len = 0;
2938 iph->check = 0;
2939 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2940 iph->daddr, 0,
2941 IPPROTO_TCP,
2942 0);
2943 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
2944 ipv6_hdr(skb)->payload_len = 0;
2945 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2946 &ipv6_hdr(skb)->daddr,
2947 0, IPPROTO_TCP, 0);
2948 }
2949
2950 i = tx_ring->next_to_use;
2951
2952 buffer_info = &tx_ring->buffer_info[i];
2953 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2954 /* VLAN MACLEN IPLEN */
2955 if (tx_flags & IGB_TX_FLAGS_VLAN)
2956 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2957 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2958 *hdr_len += skb_network_offset(skb);
2959 info |= skb_network_header_len(skb);
2960 *hdr_len += skb_network_header_len(skb);
2961 context_desc->vlan_macip_lens = cpu_to_le32(info);
2962
2963 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
2964 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2965
2966 if (skb->protocol == htons(ETH_P_IP))
2967 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
2968 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2969
2970 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2971
2972 /* MSS L4LEN IDX */
2973 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
2974 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
2975
73cd78f1 2976 /* For 82575, context index must be unique per ring. */
7dfc16fa
AD		 2977 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2978 mss_l4len_idx |= tx_ring->queue_index << 4;
9d5c8243
AK		 2979
2980 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
2981 context_desc->seqnum_seed = 0;
2982
2983 buffer_info->time_stamp = jiffies;
0e014cb1 2984 buffer_info->next_to_watch = i;
9d5c8243
AK		 2985 buffer_info->dma = 0;
2986 i++;
2987 if (i == tx_ring->count)
2988 i = 0;
2989
2990 tx_ring->next_to_use = i;
2991
2992 return true;
2993}
2994
2995static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
2996 struct igb_ring *tx_ring,
2997 struct sk_buff *skb, u32 tx_flags)
2998{
2999 struct e1000_adv_tx_context_desc *context_desc;
3000 unsigned int i;
3001 struct igb_buffer *buffer_info;
3002 u32 info = 0, tu_cmd = 0;
3003
3004 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
3005 (tx_flags & IGB_TX_FLAGS_VLAN)) {
3006 i = tx_ring->next_to_use;
3007 buffer_info = &tx_ring->buffer_info[i];
3008 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3009
3010 if (tx_flags & IGB_TX_FLAGS_VLAN)
3011 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
3012 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3013 if (skb->ip_summed == CHECKSUM_PARTIAL)
3014 info |= skb_network_header_len(skb);
3015
3016 context_desc->vlan_macip_lens = cpu_to_le32(info);
3017
3018 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3019
3020 if (skb->ip_summed == CHECKSUM_PARTIAL) {
44b0cda3 3021 switch (skb->protocol) {
09640e63 3022 case cpu_to_be16(ETH_P_IP):
9d5c8243 3023 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
44b0cda3
MW		 3024 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
3025 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3026 break;
09640e63 3027 case cpu_to_be16(ETH_P_IPV6):
44b0cda3
MW		 3028 /* XXX what about other V6 headers?? */
3029 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
3030 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3031 break;
3032 default:
3033 if (unlikely(net_ratelimit()))
3034 dev_warn(&adapter->pdev->dev,
3035 "partial checksum but proto=%x!\n",
3036 skb->protocol);
3037 break;
3038 }
9d5c8243
AK		 3039 }
3040
3041 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3042 context_desc->seqnum_seed = 0;
7dfc16fa
AD		 3043 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
3044 context_desc->mss_l4len_idx =
3045 cpu_to_le32(tx_ring->queue_index << 4);
265de409
AD		 3046 else
3047 context_desc->mss_l4len_idx = 0;
9d5c8243
AK		 3048
3049 buffer_info->time_stamp = jiffies;
0e014cb1 3050 buffer_info->next_to_watch = i;
9d5c8243
AK		 3051 buffer_info->dma = 0;
3052
3053 i++;
3054 if (i == tx_ring->count)
3055 i = 0;
3056 tx_ring->next_to_use = i;
3057
3058 return true;
3059 }
9d5c8243
AK		 3060 return false;
3061}
3062
3063#define IGB_MAX_TXD_PWR 16
3064#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
3065
3066static inline int igb_tx_map_adv(struct igb_adapter *adapter,
0e014cb1
AD		 3067 struct igb_ring *tx_ring, struct sk_buff *skb,
3068 unsigned int first)
9d5c8243
AK		 3069{
3070 struct igb_buffer *buffer_info;
3071 unsigned int len = skb_headlen(skb);
3072 unsigned int count = 0, i;
3073 unsigned int f;
3074
3075 i = tx_ring->next_to_use;
3076
3077 buffer_info = &tx_ring->buffer_info[i];
3078 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3079 buffer_info->length = len;
3080 /* set time_stamp *before* dma to help avoid a possible race */
3081 buffer_info->time_stamp = jiffies;
0e014cb1 3082 buffer_info->next_to_watch = i;
9d5c8243
AK		 3083 buffer_info->dma = pci_map_single(adapter->pdev, skb->data, len,
3084 PCI_DMA_TODEVICE);
3085 count++;
3086 i++;
3087 if (i == tx_ring->count)
3088 i = 0;
3089
3090 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
3091 struct skb_frag_struct *frag;
3092
3093 frag = &skb_shinfo(skb)->frags[f];
3094 len = frag->size;
3095
3096 buffer_info = &tx_ring->buffer_info[i];
3097 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3098 buffer_info->length = len;
3099 buffer_info->time_stamp = jiffies;
0e014cb1 3100 buffer_info->next_to_watch = i;
9d5c8243
AK		 3101 buffer_info->dma = pci_map_page(adapter->pdev,
3102 frag->page,
3103 frag->page_offset,
3104 len,
3105 PCI_DMA_TODEVICE);
3106
3107 count++;
3108 i++;
3109 if (i == tx_ring->count)
3110 i = 0;
3111 }
3112
0e014cb1 3113 i = ((i == 0) ? tx_ring->count - 1 : i - 1);
9d5c8243 3114 tx_ring->buffer_info[i].skb = skb;
0e014cb1 3115 tx_ring->buffer_info[first].next_to_watch = i;
9d5c8243
AK		 3116
3117 return count;
3118}
3119
3120static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
3121 struct igb_ring *tx_ring,
3122 int tx_flags, int count, u32 paylen,
3123 u8 hdr_len)
3124{
3125 union e1000_adv_tx_desc *tx_desc = NULL;
3126 struct igb_buffer *buffer_info;
3127 u32 olinfo_status = 0, cmd_type_len;
3128 unsigned int i;
3129
3130 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
3131 E1000_ADVTXD_DCMD_DEXT);
3132
3133 if (tx_flags & IGB_TX_FLAGS_VLAN)
3134 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3135
33af6bcc
PO		 3136 if (tx_flags & IGB_TX_FLAGS_TSTAMP)
3137 cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP;
3138
9d5c8243
AK		 3139 if (tx_flags & IGB_TX_FLAGS_TSO) {
3140 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3141
3142 /* insert tcp checksum */
3143 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3144
3145 /* insert ip checksum */
3146 if (tx_flags & IGB_TX_FLAGS_IPV4)
3147 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3148
3149 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
3150 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3151 }
3152
7dfc16fa
AD		 3153 if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) &&
3154 (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
3155 IGB_TX_FLAGS_VLAN)))
661086df 3156 olinfo_status |= tx_ring->queue_index << 4;
9d5c8243
AK		 3157
3158 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
3159
3160 i = tx_ring->next_to_use;
3161 while (count--) {
3162 buffer_info = &tx_ring->buffer_info[i];
3163 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
3164 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
3165 tx_desc->read.cmd_type_len =
3166 cpu_to_le32(cmd_type_len | buffer_info->length);
3167 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
3168 i++;
3169 if (i == tx_ring->count)
3170 i = 0;
3171 }
3172
3173 tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
3174 /* Force memory writes to complete before letting h/w
3175 * know there are new descriptors to fetch. (Only
3176 * applicable for weak-ordered memory model archs,
3177 * such as IA-64). */
3178 wmb();
3179
3180 tx_ring->next_to_use = i;
3181 writel(i, adapter->hw.hw_addr + tx_ring->tail);
3182 /* we need this if more than one processor can write to our tail
3183 * at a time, it syncronizes IO on IA64/Altix systems */
3184 mmiowb();
3185}
3186
3187static int __igb_maybe_stop_tx(struct net_device *netdev,
3188 struct igb_ring *tx_ring, int size)
3189{
3190 struct igb_adapter *adapter = netdev_priv(netdev);
3191
661086df 3192 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 3193
9d5c8243
AK		 3194 /* Herbert's original patch had:
3195 * smp_mb__after_netif_stop_queue();
3196 * but since that doesn't exist yet, just open code it. */
3197 smp_mb();
3198
3199 /* We need to check again in a case another CPU has just
3200 * made room available. */
3201 if (IGB_DESC_UNUSED(tx_ring) < size)
3202 return -EBUSY;
3203
3204 /* A reprieve! */
661086df 3205 netif_wake_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 3206 ++adapter->restart_queue;
3207 return 0;
3208}
3209
3210static int igb_maybe_stop_tx(struct net_device *netdev,
3211 struct igb_ring *tx_ring, int size)
3212{
3213 if (IGB_DESC_UNUSED(tx_ring) >= size)
3214 return 0;
3215 return __igb_maybe_stop_tx(netdev, tx_ring, size);
3216}
3217
9d5c8243
AK		 3218static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
3219 struct net_device *netdev,
3220 struct igb_ring *tx_ring)
3221{
3222 struct igb_adapter *adapter = netdev_priv(netdev);
0e014cb1 3223 unsigned int first;
9d5c8243 3224 unsigned int tx_flags = 0;
9d5c8243
AK		 3225 u8 hdr_len = 0;
3226 int tso = 0;
33af6bcc 3227 union skb_shared_tx *shtx;
9d5c8243 3228
9d5c8243
AK		 3229 if (test_bit(__IGB_DOWN, &adapter->state)) {
3230 dev_kfree_skb_any(skb);
3231 return NETDEV_TX_OK;
3232 }
3233
3234 if (skb->len <= 0) {
3235 dev_kfree_skb_any(skb);
3236 return NETDEV_TX_OK;
3237 }
3238
9d5c8243
AK		 3239 /* need: 1 descriptor per page,
3240 * + 2 desc gap to keep tail from touching head,
3241 * + 1 desc for skb->data,
3242 * + 1 desc for context descriptor,
3243 * otherwise try next time */
3244 if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
3245 /* this is a hard error */
9d5c8243
AK		 3246 return NETDEV_TX_BUSY;
3247 }
33af6bcc
PO		 3248
3249 /*
3250 * TODO: check that there currently is no other packet with
3251 * time stamping in the queue
3252 *
3253 * When doing time stamping, keep the connection to the socket
3254 * a while longer: it is still needed by skb_hwtstamp_tx(),
3255 * called either in igb_tx_hwtstamp() or by our caller when
3256 * doing software time stamping.
3257 */
3258 shtx = skb_tx(skb);
3259 if (unlikely(shtx->hardware)) {
3260 shtx->in_progress = 1;
3261 tx_flags |= IGB_TX_FLAGS_TSTAMP;
33af6bcc 3262 }
9d5c8243
AK		 3263
3264 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
3265 tx_flags |= IGB_TX_FLAGS_VLAN;
3266 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
3267 }
3268
661086df
PWJ		 3269 if (skb->protocol == htons(ETH_P_IP))
3270 tx_flags |= IGB_TX_FLAGS_IPV4;
3271
0e014cb1 3272 first = tx_ring->next_to_use;
9d5c8243
AK		 3273 tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
3274 &hdr_len) : 0;
3275
3276 if (tso < 0) {
3277 dev_kfree_skb_any(skb);
9d5c8243
AK		 3278 return NETDEV_TX_OK;
3279 }
3280
3281 if (tso)
3282 tx_flags |= IGB_TX_FLAGS_TSO;
bc1cbd34
AD		 3283 else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags) &&
3284 (skb->ip_summed == CHECKSUM_PARTIAL))
3285 tx_flags |= IGB_TX_FLAGS_CSUM;
9d5c8243 3286
9d5c8243 3287 igb_tx_queue_adv(adapter, tx_ring, tx_flags,
0e014cb1 3288 igb_tx_map_adv(adapter, tx_ring, skb, first),
9d5c8243
AK		 3289 skb->len, hdr_len);
3290
3291 netdev->trans_start = jiffies;
3292
3293 /* Make sure there is space in the ring for the next send. */
3294 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
3295
9d5c8243
AK		 3296 return NETDEV_TX_OK;
3297}
3298
3299static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *netdev)
3300{
3301 struct igb_adapter *adapter = netdev_priv(netdev);
661086df
PWJ		 3302 struct igb_ring *tx_ring;
3303
661086df 3304 int r_idx = 0;
1bfaf07b 3305 r_idx = skb->queue_mapping & (IGB_ABS_MAX_TX_QUEUES - 1);
661086df 3306 tx_ring = adapter->multi_tx_table[r_idx];
9d5c8243
AK		 3307
3308 /* This goes back to the question of how to logically map a tx queue
3309 * to a flow. Right now, performance is impacted slightly negatively
3310 * if using multiple tx queues. If the stack breaks away from a
3311 * single qdisc implementation, we can look at this again. */
3312 return (igb_xmit_frame_ring_adv(skb, netdev, tx_ring));
3313}
3314
3315/**
3316 * igb_tx_timeout - Respond to a Tx Hang
3317 * @netdev: network interface device structure
3318 **/
3319static void igb_tx_timeout(struct net_device *netdev)
3320{
3321 struct igb_adapter *adapter = netdev_priv(netdev);
3322 struct e1000_hw *hw = &adapter->hw;
3323
3324 /* Do the reset outside of interrupt context */
3325 adapter->tx_timeout_count++;
3326 schedule_work(&adapter->reset_task);
265de409
AD		 3327 wr32(E1000_EICS,
3328 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 3329}
3330
3331static void igb_reset_task(struct work_struct *work)
3332{
3333 struct igb_adapter *adapter;
3334 adapter = container_of(work, struct igb_adapter, reset_task);
3335
3336 igb_reinit_locked(adapter);
3337}
3338
3339/**
3340 * igb_get_stats - Get System Network Statistics
3341 * @netdev: network interface device structure
3342 *
3343 * Returns the address of the device statistics structure.
3344 * The statistics are actually updated from the timer callback.
3345 **/
73cd78f1 3346static struct net_device_stats *igb_get_stats(struct net_device *netdev)
9d5c8243
AK		 3347{
3348 struct igb_adapter *adapter = netdev_priv(netdev);
3349
3350 /* only return the current stats */
3351 return &adapter->net_stats;
3352}
3353
3354/**
3355 * igb_change_mtu - Change the Maximum Transfer Unit
3356 * @netdev: network interface device structure
3357 * @new_mtu: new value for maximum frame size
3358 *
3359 * Returns 0 on success, negative on failure
3360 **/
3361static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3362{
3363 struct igb_adapter *adapter = netdev_priv(netdev);
3364 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3365
3366 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
3367 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3368 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
3369 return -EINVAL;
3370 }
3371
9d5c8243
AK		 3372 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3373 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
3374 return -EINVAL;
3375 }
3376
3377 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3378 msleep(1);
73cd78f1 3379
9d5c8243
AK		 3380 /* igb_down has a dependency on max_frame_size */
3381 adapter->max_frame_size = max_frame;
3382 if (netif_running(netdev))
3383 igb_down(adapter);
3384
3385 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3386 * means we reserve 2 more, this pushes us to allocate from the next
3387 * larger slab size.
3388 * i.e. RXBUFFER_2048 --> size-4096 slab
3389 */
3390
3391 if (max_frame <= IGB_RXBUFFER_256)
3392 adapter->rx_buffer_len = IGB_RXBUFFER_256;
3393 else if (max_frame <= IGB_RXBUFFER_512)
3394 adapter->rx_buffer_len = IGB_RXBUFFER_512;
3395 else if (max_frame <= IGB_RXBUFFER_1024)
3396 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3397 else if (max_frame <= IGB_RXBUFFER_2048)
3398 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
3399 else
bf36c1a0
AD		 3400#if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
3401 adapter->rx_buffer_len = IGB_RXBUFFER_16384;
3402#else
3403 adapter->rx_buffer_len = PAGE_SIZE / 2;
3404#endif
e1739522
AD		 3405
3406 /* if sr-iov is enabled we need to force buffer size to 1K or larger */
3407 if (adapter->vfs_allocated_count &&
3408 (adapter->rx_buffer_len < IGB_RXBUFFER_1024))
3409 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3410
9d5c8243
AK		 3411 /* adjust allocation if LPE protects us, and we aren't using SBP */
3412 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
3413 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
3414 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3415
3416 dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
3417 netdev->mtu, new_mtu);
3418 netdev->mtu = new_mtu;
3419
3420 if (netif_running(netdev))
3421 igb_up(adapter);
3422 else
3423 igb_reset(adapter);
3424
3425 clear_bit(__IGB_RESETTING, &adapter->state);
3426
3427 return 0;
3428}
3429
3430/**
3431 * igb_update_stats - Update the board statistics counters
3432 * @adapter: board private structure
3433 **/
3434
3435void igb_update_stats(struct igb_adapter *adapter)
3436{
3437 struct e1000_hw *hw = &adapter->hw;
3438 struct pci_dev *pdev = adapter->pdev;
3439 u16 phy_tmp;
3440
3441#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3442
3443 /*
3444 * Prevent stats update while adapter is being reset, or if the pci
3445 * connection is down.
3446 */
3447 if (adapter->link_speed == 0)
3448 return;
3449 if (pci_channel_offline(pdev))
3450 return;
3451
3452 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3453 adapter->stats.gprc += rd32(E1000_GPRC);
3454 adapter->stats.gorc += rd32(E1000_GORCL);
3455 rd32(E1000_GORCH); /* clear GORCL */
3456 adapter->stats.bprc += rd32(E1000_BPRC);
3457 adapter->stats.mprc += rd32(E1000_MPRC);
3458 adapter->stats.roc += rd32(E1000_ROC);
3459
3460 adapter->stats.prc64 += rd32(E1000_PRC64);
3461 adapter->stats.prc127 += rd32(E1000_PRC127);
3462 adapter->stats.prc255 += rd32(E1000_PRC255);
3463 adapter->stats.prc511 += rd32(E1000_PRC511);
3464 adapter->stats.prc1023 += rd32(E1000_PRC1023);
3465 adapter->stats.prc1522 += rd32(E1000_PRC1522);
3466 adapter->stats.symerrs += rd32(E1000_SYMERRS);
3467 adapter->stats.sec += rd32(E1000_SEC);
3468
3469 adapter->stats.mpc += rd32(E1000_MPC);
3470 adapter->stats.scc += rd32(E1000_SCC);
3471 adapter->stats.ecol += rd32(E1000_ECOL);
3472 adapter->stats.mcc += rd32(E1000_MCC);
3473 adapter->stats.latecol += rd32(E1000_LATECOL);
3474 adapter->stats.dc += rd32(E1000_DC);
3475 adapter->stats.rlec += rd32(E1000_RLEC);
3476 adapter->stats.xonrxc += rd32(E1000_XONRXC);
3477 adapter->stats.xontxc += rd32(E1000_XONTXC);
3478 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
3479 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
3480 adapter->stats.fcruc += rd32(E1000_FCRUC);
3481 adapter->stats.gptc += rd32(E1000_GPTC);
3482 adapter->stats.gotc += rd32(E1000_GOTCL);
3483 rd32(E1000_GOTCH); /* clear GOTCL */
3484 adapter->stats.rnbc += rd32(E1000_RNBC);
3485 adapter->stats.ruc += rd32(E1000_RUC);
3486 adapter->stats.rfc += rd32(E1000_RFC);
3487 adapter->stats.rjc += rd32(E1000_RJC);
3488 adapter->stats.tor += rd32(E1000_TORH);
3489 adapter->stats.tot += rd32(E1000_TOTH);
3490 adapter->stats.tpr += rd32(E1000_TPR);
3491
3492 adapter->stats.ptc64 += rd32(E1000_PTC64);
3493 adapter->stats.ptc127 += rd32(E1000_PTC127);
3494 adapter->stats.ptc255 += rd32(E1000_PTC255);
3495 adapter->stats.ptc511 += rd32(E1000_PTC511);
3496 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
3497 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
3498
3499 adapter->stats.mptc += rd32(E1000_MPTC);
3500 adapter->stats.bptc += rd32(E1000_BPTC);
3501
3502 /* used for adaptive IFS */
3503
3504 hw->mac.tx_packet_delta = rd32(E1000_TPT);
3505 adapter->stats.tpt += hw->mac.tx_packet_delta;
3506 hw->mac.collision_delta = rd32(E1000_COLC);
3507 adapter->stats.colc += hw->mac.collision_delta;
3508
3509 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
3510 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3511 adapter->stats.tncrs += rd32(E1000_TNCRS);
3512 adapter->stats.tsctc += rd32(E1000_TSCTC);
3513 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
3514
3515 adapter->stats.iac += rd32(E1000_IAC);
3516 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
3517 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
3518 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
3519 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
3520 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
3521 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
3522 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
3523 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
3524
3525 /* Fill out the OS statistics structure */
3526 adapter->net_stats.multicast = adapter->stats.mprc;
3527 adapter->net_stats.collisions = adapter->stats.colc;
3528
3529 /* Rx Errors */
3530
3531 /* RLEC on some newer hardware can be incorrect so build
3532 * our own version based on RUC and ROC */
3533 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3534 adapter->stats.crcerrs + adapter->stats.algnerrc +
3535 adapter->stats.ruc + adapter->stats.roc +
3536 adapter->stats.cexterr;
3537 adapter->net_stats.rx_length_errors = adapter->stats.ruc +
3538 adapter->stats.roc;
3539 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3540 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
3541 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3542
3543 /* Tx Errors */
3544 adapter->net_stats.tx_errors = adapter->stats.ecol +
3545 adapter->stats.latecol;
3546 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3547 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3548 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3549
3550 /* Tx Dropped needs to be maintained elsewhere */
3551
3552 /* Phy Stats */
3553 if (hw->phy.media_type == e1000_media_type_copper) {
3554 if ((adapter->link_speed == SPEED_1000) &&
73cd78f1 3555 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
9d5c8243
AK		 3556 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3557 adapter->phy_stats.idle_errors += phy_tmp;
3558 }
3559 }
3560
3561 /* Management Stats */
3562 adapter->stats.mgptc += rd32(E1000_MGTPTC);
3563 adapter->stats.mgprc += rd32(E1000_MGTPRC);
3564 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3565}
3566
9d5c8243
AK		 3567static irqreturn_t igb_msix_other(int irq, void *data)
3568{
3569 struct net_device *netdev = data;
3570 struct igb_adapter *adapter = netdev_priv(netdev);
3571 struct e1000_hw *hw = &adapter->hw;
844290e5 3572 u32 icr = rd32(E1000_ICR);
9d5c8243 3573
844290e5 3574 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083
AD		 3575
3576 if(icr & E1000_ICR_DOUTSYNC) {
3577 /* HW is reporting DMA is out of sync */
3578 adapter->stats.doosync++;
3579 }
eebbbdba 3580
4ae196df
AD		 3581 /* Check for a mailbox event */
3582 if (icr & E1000_ICR_VMMB)
3583 igb_msg_task(adapter);
3584
3585 if (icr & E1000_ICR_LSC) {
3586 hw->mac.get_link_status = 1;
3587 /* guard against interrupt when we're going down */
3588 if (!test_bit(__IGB_DOWN, &adapter->state))
3589 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3590 }
3591
3592 wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_VMMB);
844290e5 3593 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 3594
3595 return IRQ_HANDLED;
3596}
3597
3598static irqreturn_t igb_msix_tx(int irq, void *data)
3599{
3600 struct igb_ring *tx_ring = data;
3601 struct igb_adapter *adapter = tx_ring->adapter;
3602 struct e1000_hw *hw = &adapter->hw;
3603
421e02f0 3604#ifdef CONFIG_IGB_DCA
7dfc16fa 3605 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3606 igb_update_tx_dca(tx_ring);
3607#endif
73cd78f1 3608
9d5c8243
AK		 3609 tx_ring->total_bytes = 0;
3610 tx_ring->total_packets = 0;
661086df
PWJ		 3611
3612 /* auto mask will automatically reenable the interrupt when we write
3613 * EICS */
3b644cf6 3614 if (!igb_clean_tx_irq(tx_ring))
9d5c8243
AK		 3615 /* Ring was not completely cleaned, so fire another interrupt */
3616 wr32(E1000_EICS, tx_ring->eims_value);
661086df 3617 else
9d5c8243 3618 wr32(E1000_EIMS, tx_ring->eims_value);
661086df 3619
9d5c8243
AK		 3620 return IRQ_HANDLED;
3621}
3622
6eb5a7f1
AD		 3623static void igb_write_itr(struct igb_ring *ring)
3624{
3625 struct e1000_hw *hw = &ring->adapter->hw;
3626 if ((ring->adapter->itr_setting & 3) && ring->set_itr) {
3627 switch (hw->mac.type) {
3628 case e1000_82576:
73cd78f1 3629 wr32(ring->itr_register, ring->itr_val |
6eb5a7f1
AD		 3630 0x80000000);
3631 break;
3632 default:
73cd78f1 3633 wr32(ring->itr_register, ring->itr_val |
6eb5a7f1
AD		 3634 (ring->itr_val << 16));
3635 break;
3636 }
3637 ring->set_itr = 0;
3638 }
3639}
3640
9d5c8243
AK		 3641static irqreturn_t igb_msix_rx(int irq, void *data)
3642{
3643 struct igb_ring *rx_ring = data;
9d5c8243 3644
844290e5
PW		 3645 /* Write the ITR value calculated at the end of the
3646 * previous interrupt.
3647 */
9d5c8243 3648
6eb5a7f1 3649 igb_write_itr(rx_ring);
9d5c8243 3650
288379f0
BH		 3651 if (napi_schedule_prep(&rx_ring->napi))
3652 __napi_schedule(&rx_ring->napi);
844290e5 3653
421e02f0 3654#ifdef CONFIG_IGB_DCA
8d253320 3655 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3656 igb_update_rx_dca(rx_ring);
3657#endif
3658 return IRQ_HANDLED;
3659}
3660
421e02f0 3661#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 3662static void igb_update_rx_dca(struct igb_ring *rx_ring)
3663{
3664 u32 dca_rxctrl;
3665 struct igb_adapter *adapter = rx_ring->adapter;
3666 struct e1000_hw *hw = &adapter->hw;
3667 int cpu = get_cpu();
26bc19ec 3668 int q = rx_ring->reg_idx;
fe4506b6
JC		 3669
3670 if (rx_ring->cpu != cpu) {
3671 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
2d064c06
AD		 3672 if (hw->mac.type == e1000_82576) {
3673 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
92be7917 3674 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
2d064c06
AD		 3675 E1000_DCA_RXCTRL_CPUID_SHIFT;
3676 } else {
3677 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
92be7917 3678 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
2d064c06 3679 }
fe4506b6
JC		 3680 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
3681 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
3682 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
3683 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
3684 rx_ring->cpu = cpu;
3685 }
3686 put_cpu();
3687}
3688
3689static void igb_update_tx_dca(struct igb_ring *tx_ring)
3690{
3691 u32 dca_txctrl;
3692 struct igb_adapter *adapter = tx_ring->adapter;
3693 struct e1000_hw *hw = &adapter->hw;
3694 int cpu = get_cpu();
26bc19ec 3695 int q = tx_ring->reg_idx;
fe4506b6
JC		 3696
3697 if (tx_ring->cpu != cpu) {
3698 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
2d064c06
AD		 3699 if (hw->mac.type == e1000_82576) {
3700 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
92be7917 3701 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
2d064c06
AD		 3702 E1000_DCA_TXCTRL_CPUID_SHIFT;
3703 } else {
3704 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
92be7917 3705 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
2d064c06 3706 }
fe4506b6
JC		 3707 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
3708 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
3709 tx_ring->cpu = cpu;
3710 }
3711 put_cpu();
3712}
3713
3714static void igb_setup_dca(struct igb_adapter *adapter)
3715{
3716 int i;
3717
7dfc16fa 3718 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 3719 return;
3720
3721 for (i = 0; i < adapter->num_tx_queues; i++) {
3722 adapter->tx_ring[i].cpu = -1;
3723 igb_update_tx_dca(&adapter->tx_ring[i]);
3724 }
3725 for (i = 0; i < adapter->num_rx_queues; i++) {
3726 adapter->rx_ring[i].cpu = -1;
3727 igb_update_rx_dca(&adapter->rx_ring[i]);
3728 }
3729}
3730
3731static int __igb_notify_dca(struct device *dev, void *data)
3732{
3733 struct net_device *netdev = dev_get_drvdata(dev);
3734 struct igb_adapter *adapter = netdev_priv(netdev);
3735 struct e1000_hw *hw = &adapter->hw;
3736 unsigned long event = *(unsigned long *)data;
3737
3738 switch (event) {
3739 case DCA_PROVIDER_ADD:
3740 /* if already enabled, don't do it again */
7dfc16fa 3741 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 3742 break;
fe4506b6
JC		 3743 /* Always use CB2 mode, difference is masked
3744 * in the CB driver. */
cbd347ad 3745 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
fe4506b6 3746 if (dca_add_requester(dev) == 0) {
bbd98fe4 3747 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 3748 dev_info(&adapter->pdev->dev, "DCA enabled\n");
3749 igb_setup_dca(adapter);
3750 break;
3751 }
3752 /* Fall Through since DCA is disabled. */
3753 case DCA_PROVIDER_REMOVE:
7dfc16fa 3754 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 3755 /* without this a class_device is left
3756 * hanging around in the sysfs model */
3757 dca_remove_requester(dev);
3758 dev_info(&adapter->pdev->dev, "DCA disabled\n");
7dfc16fa 3759 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 3760 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 3761 }
3762 break;
3763 }
bbd98fe4 3764
fe4506b6 3765 return 0;
9d5c8243
AK		 3766}
3767
fe4506b6
JC		 3768static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
3769 void *p)
3770{
3771 int ret_val;
3772
3773 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
3774 __igb_notify_dca);
3775
3776 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
3777}
421e02f0 3778#endif /* CONFIG_IGB_DCA */
9d5c8243 3779
4ae196df
AD		 3780static void igb_ping_all_vfs(struct igb_adapter *adapter)
3781{
3782 struct e1000_hw *hw = &adapter->hw;
3783 u32 ping;
3784 int i;
3785
3786 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
3787 ping = E1000_PF_CONTROL_MSG;
3788 if (adapter->vf_data[i].clear_to_send)
3789 ping |= E1000_VT_MSGTYPE_CTS;
3790 igb_write_mbx(hw, &ping, 1, i);
3791 }
3792}
3793
3794static int igb_set_vf_multicasts(struct igb_adapter *adapter,
3795 u32 *msgbuf, u32 vf)
3796{
3797 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
3798 u16 *hash_list = (u16 *)&msgbuf[1];
3799 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
3800 int i;
3801
3802 /* only up to 30 hash values supported */
3803 if (n > 30)
3804 n = 30;
3805
3806 /* salt away the number of multi cast addresses assigned
3807 * to this VF for later use to restore when the PF multi cast
3808 * list changes
3809 */
3810 vf_data->num_vf_mc_hashes = n;
3811
3812 /* VFs are limited to using the MTA hash table for their multicast
3813 * addresses */
3814 for (i = 0; i < n; i++)
3815 vf_data->vf_mc_hashes[i] = hash_list[i];;
3816
3817 /* Flush and reset the mta with the new values */
3818 igb_set_multi(adapter->netdev);
3819
3820 return 0;
3821}
3822
3823static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
3824{
3825 struct e1000_hw *hw = &adapter->hw;
3826 struct vf_data_storage *vf_data;
3827 int i, j;
3828
3829 for (i = 0; i < adapter->vfs_allocated_count; i++) {
3830 vf_data = &adapter->vf_data[i];
3831 for (j = 0; j < vf_data[i].num_vf_mc_hashes; j++)
3832 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
3833 }
3834}
3835
3836static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
3837{
3838 struct e1000_hw *hw = &adapter->hw;
3839 u32 pool_mask, reg, vid;
3840 int i;
3841
3842 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
3843
3844 /* Find the vlan filter for this id */
3845 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
3846 reg = rd32(E1000_VLVF(i));
3847
3848 /* remove the vf from the pool */
3849 reg &= ~pool_mask;
3850
3851 /* if pool is empty then remove entry from vfta */
3852 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
3853 (reg & E1000_VLVF_VLANID_ENABLE)) {
3854 reg = 0;
3855 vid = reg & E1000_VLVF_VLANID_MASK;
3856 igb_vfta_set(hw, vid, false);
3857 }
3858
3859 wr32(E1000_VLVF(i), reg);
3860 }
3861}
3862
3863static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
3864{
3865 struct e1000_hw *hw = &adapter->hw;
3866 u32 reg, i;
3867
3868 /* It is an error to call this function when VFs are not enabled */
3869 if (!adapter->vfs_allocated_count)
3870 return -1;
3871
3872 /* Find the vlan filter for this id */
3873 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
3874 reg = rd32(E1000_VLVF(i));
3875 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
3876 vid == (reg & E1000_VLVF_VLANID_MASK))
3877 break;
3878 }
3879
3880 if (add) {
3881 if (i == E1000_VLVF_ARRAY_SIZE) {
3882 /* Did not find a matching VLAN ID entry that was
3883 * enabled. Search for a free filter entry, i.e.
3884 * one without the enable bit set
3885 */
3886 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
3887 reg = rd32(E1000_VLVF(i));
3888 if (!(reg & E1000_VLVF_VLANID_ENABLE))
3889 break;
3890 }
3891 }
3892 if (i < E1000_VLVF_ARRAY_SIZE) {
3893 /* Found an enabled/available entry */
3894 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
3895
3896 /* if !enabled we need to set this up in vfta */
3897 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
3898 /* add VID to filter table */
3899 igb_vfta_set(hw, vid, true);
3900 reg |= E1000_VLVF_VLANID_ENABLE;
3901 }
3902
3903 wr32(E1000_VLVF(i), reg);
3904 return 0;
3905 }
3906 } else {
3907 if (i < E1000_VLVF_ARRAY_SIZE) {
3908 /* remove vf from the pool */
3909 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
3910 /* if pool is empty then remove entry from vfta */
3911 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
3912 reg = 0;
3913 igb_vfta_set(hw, vid, false);
3914 }
3915 wr32(E1000_VLVF(i), reg);
3916 return 0;
3917 }
3918 }
3919 return -1;
3920}
3921
3922static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
3923{
3924 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
3925 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
3926
3927 return igb_vlvf_set(adapter, vid, add, vf);
3928}
3929
3930static inline void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
3931{
3932 struct e1000_hw *hw = &adapter->hw;
3933
3934 /* disable mailbox functionality for vf */
3935 adapter->vf_data[vf].clear_to_send = false;
3936
3937 /* reset offloads to defaults */
3938 igb_set_vmolr(hw, vf);
3939
3940 /* reset vlans for device */
3941 igb_clear_vf_vfta(adapter, vf);
3942
3943 /* reset multicast table array for vf */
3944 adapter->vf_data[vf].num_vf_mc_hashes = 0;
3945
3946 /* Flush and reset the mta with the new values */
3947 igb_set_multi(adapter->netdev);
3948}
3949
3950static inline void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
3951{
3952 struct e1000_hw *hw = &adapter->hw;
3953 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
3954 u32 reg, msgbuf[3];
3955 u8 *addr = (u8 *)(&msgbuf[1]);
3956
3957 /* process all the same items cleared in a function level reset */
3958 igb_vf_reset_event(adapter, vf);
3959
3960 /* set vf mac address */
3961 igb_rar_set(hw, vf_mac, vf + 1);
3962 igb_set_rah_pool(hw, vf, vf + 1);
3963
3964 /* enable transmit and receive for vf */
3965 reg = rd32(E1000_VFTE);
3966 wr32(E1000_VFTE, reg | (1 << vf));
3967 reg = rd32(E1000_VFRE);
3968 wr32(E1000_VFRE, reg | (1 << vf));
3969
3970 /* enable mailbox functionality for vf */
3971 adapter->vf_data[vf].clear_to_send = true;
3972
3973 /* reply to reset with ack and vf mac address */
3974 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
3975 memcpy(addr, vf_mac, 6);
3976 igb_write_mbx(hw, msgbuf, 3, vf);
3977}
3978
3979static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
3980{
3981 unsigned char *addr = (char *)&msg[1];
3982 int err = -1;
3983
3984 if (is_valid_ether_addr(addr))
3985 err = igb_set_vf_mac(adapter, vf, addr);
3986
3987 return err;
3988
3989}
3990
3991static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
3992{
3993 struct e1000_hw *hw = &adapter->hw;
3994 u32 msg = E1000_VT_MSGTYPE_NACK;
3995
3996 /* if device isn't clear to send it shouldn't be reading either */
3997 if (!adapter->vf_data[vf].clear_to_send)
3998 igb_write_mbx(hw, &msg, 1, vf);
3999}
4000
4001
4002static void igb_msg_task(struct igb_adapter *adapter)
4003{
4004 struct e1000_hw *hw = &adapter->hw;
4005 u32 vf;
4006
4007 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
4008 /* process any reset requests */
4009 if (!igb_check_for_rst(hw, vf)) {
4010 adapter->vf_data[vf].clear_to_send = false;
4011 igb_vf_reset_event(adapter, vf);
4012 }
4013
4014 /* process any messages pending */
4015 if (!igb_check_for_msg(hw, vf))
4016 igb_rcv_msg_from_vf(adapter, vf);
4017
4018 /* process any acks */
4019 if (!igb_check_for_ack(hw, vf))
4020 igb_rcv_ack_from_vf(adapter, vf);
4021
4022 }
4023}
4024
4025static int igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4026{
4027 u32 mbx_size = E1000_VFMAILBOX_SIZE;
4028 u32 msgbuf[mbx_size];
4029 struct e1000_hw *hw = &adapter->hw;
4030 s32 retval;
4031
4032 retval = igb_read_mbx(hw, msgbuf, mbx_size, vf);
4033
4034 if (retval)
4035 dev_err(&adapter->pdev->dev,
4036 "Error receiving message from VF\n");
4037
4038 /* this is a message we already processed, do nothing */
4039 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
4040 return retval;
4041
4042 /*
4043 * until the vf completes a reset it should not be
4044 * allowed to start any configuration.
4045 */
4046
4047 if (msgbuf[0] == E1000_VF_RESET) {
4048 igb_vf_reset_msg(adapter, vf);
4049
4050 return retval;
4051 }
4052
4053 if (!adapter->vf_data[vf].clear_to_send) {
4054 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4055 igb_write_mbx(hw, msgbuf, 1, vf);
4056 return retval;
4057 }
4058
4059 switch ((msgbuf[0] & 0xFFFF)) {
4060 case E1000_VF_SET_MAC_ADDR:
4061 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
4062 break;
4063 case E1000_VF_SET_MULTICAST:
4064 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
4065 break;
4066 case E1000_VF_SET_LPE:
4067 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
4068 break;
4069 case E1000_VF_SET_VLAN:
4070 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4071 break;
4072 default:
4073 dev_err(&adapter->pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4074 retval = -1;
4075 break;
4076 }
4077
4078 /* notify the VF of the results of what it sent us */
4079 if (retval)
4080 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4081 else
4082 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
4083
4084 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
4085
4086 igb_write_mbx(hw, msgbuf, 1, vf);
4087
4088 return retval;
4089}
4090
9d5c8243
AK		 4091/**
4092 * igb_intr_msi - Interrupt Handler
4093 * @irq: interrupt number
4094 * @data: pointer to a network interface device structure
4095 **/
4096static irqreturn_t igb_intr_msi(int irq, void *data)
4097{
4098 struct net_device *netdev = data;
4099 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 4100 struct e1000_hw *hw = &adapter->hw;
4101 /* read ICR disables interrupts using IAM */
4102 u32 icr = rd32(E1000_ICR);
4103
6eb5a7f1 4104 igb_write_itr(adapter->rx_ring);
9d5c8243 4105
dda0e083
AD		 4106 if(icr & E1000_ICR_DOUTSYNC) {
4107 /* HW is reporting DMA is out of sync */
4108 adapter->stats.doosync++;
4109 }
4110
9d5c8243
AK		 4111 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4112 hw->mac.get_link_status = 1;
4113 if (!test_bit(__IGB_DOWN, &adapter->state))
4114 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4115 }
4116
288379f0 4117 napi_schedule(&adapter->rx_ring[0].napi);
9d5c8243
AK		 4118
4119 return IRQ_HANDLED;
4120}
4121
4122/**
4a3c6433 4123 * igb_intr - Legacy Interrupt Handler
9d5c8243
AK		 4124 * @irq: interrupt number
4125 * @data: pointer to a network interface device structure
4126 **/
4127static irqreturn_t igb_intr(int irq, void *data)
4128{
4129 struct net_device *netdev = data;
4130 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 4131 struct e1000_hw *hw = &adapter->hw;
4132 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
4133 * need for the IMC write */
4134 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 4135 if (!icr)
4136 return IRQ_NONE; /* Not our interrupt */
4137
6eb5a7f1 4138 igb_write_itr(adapter->rx_ring);
9d5c8243
AK		 4139
4140 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
4141 * not set, then the adapter didn't send an interrupt */
4142 if (!(icr & E1000_ICR_INT_ASSERTED))
4143 return IRQ_NONE;
4144
dda0e083
AD		 4145 if(icr & E1000_ICR_DOUTSYNC) {
4146 /* HW is reporting DMA is out of sync */
4147 adapter->stats.doosync++;
4148 }
4149
9d5c8243
AK		 4150 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4151 hw->mac.get_link_status = 1;
4152 /* guard against interrupt when we're going down */
4153 if (!test_bit(__IGB_DOWN, &adapter->state))
4154 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4155 }
4156
288379f0 4157 napi_schedule(&adapter->rx_ring[0].napi);
9d5c8243
AK		 4158
4159 return IRQ_HANDLED;
4160}
4161
46544258 4162static inline void igb_rx_irq_enable(struct igb_ring *rx_ring)
9d5c8243 4163{
661086df 4164 struct igb_adapter *adapter = rx_ring->adapter;
46544258 4165 struct e1000_hw *hw = &adapter->hw;
9d5c8243 4166
46544258
AD		 4167 if (adapter->itr_setting & 3) {
4168 if (adapter->num_rx_queues == 1)
6eb5a7f1 4169 igb_set_itr(adapter);
46544258
AD		 4170 else
4171 igb_update_ring_itr(rx_ring);
9d5c8243
AK		 4172 }
4173
46544258
AD		 4174 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4175 if (adapter->msix_entries)
4176 wr32(E1000_EIMS, rx_ring->eims_value);
4177 else
4178 igb_irq_enable(adapter);
4179 }
9d5c8243
AK		 4180}
4181
46544258
AD		 4182/**
4183 * igb_poll - NAPI Rx polling callback
4184 * @napi: napi polling structure
4185 * @budget: count of how many packets we should handle
4186 **/
4187static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243
AK		 4188{
4189 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
9d5c8243
AK		 4190 int work_done = 0;
4191
421e02f0 4192#ifdef CONFIG_IGB_DCA
bd38e5d1 4193 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 4194 igb_update_rx_dca(rx_ring);
4195#endif
3b644cf6 4196 igb_clean_rx_irq_adv(rx_ring, &work_done, budget);
9d5c8243 4197
46544258
AD		 4198 if (rx_ring->buddy) {
4199#ifdef CONFIG_IGB_DCA
bd38e5d1 4200 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
46544258
AD		 4201 igb_update_tx_dca(rx_ring->buddy);
4202#endif
4203 if (!igb_clean_tx_irq(rx_ring->buddy))
4204 work_done = budget;
4205 }
4206
9d5c8243 4207 /* If not enough Rx work done, exit the polling mode */
5e6d5b17 4208 if (work_done < budget) {
288379f0 4209 napi_complete(napi);
46544258 4210 igb_rx_irq_enable(rx_ring);
9d5c8243
AK		 4211 }
4212
46544258 4213 return work_done;
9d5c8243 4214}
6d8126f9 4215
33af6bcc
PO		 4216/**
4217 * igb_hwtstamp - utility function which checks for TX time stamp
4218 * @adapter: board private structure
4219 * @skb: packet that was just sent
4220 *
4221 * If we were asked to do hardware stamping and such a time stamp is
4222 * available, then it must have been for this skb here because we only
4223 * allow only one such packet into the queue.
4224 */
4225static void igb_tx_hwtstamp(struct igb_adapter *adapter, struct sk_buff *skb)
4226{
4227 union skb_shared_tx *shtx = skb_tx(skb);
4228 struct e1000_hw *hw = &adapter->hw;
4229
4230 if (unlikely(shtx->hardware)) {
4231 u32 valid = rd32(E1000_TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID;
4232 if (valid) {
4233 u64 regval = rd32(E1000_TXSTMPL);
4234 u64 ns;
4235 struct skb_shared_hwtstamps shhwtstamps;
4236
4237 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
4238 regval |= (u64)rd32(E1000_TXSTMPH) << 32;
4239 ns = timecounter_cyc2time(&adapter->clock,
4240 regval);
4241 timecompare_update(&adapter->compare, ns);
4242 shhwtstamps.hwtstamp = ns_to_ktime(ns);
4243 shhwtstamps.syststamp =
4244 timecompare_transform(&adapter->compare, ns);
4245 skb_tstamp_tx(skb, &shhwtstamps);
4246 }
33af6bcc
PO		 4247 }
4248}
4249
9d5c8243
AK		 4250/**
4251 * igb_clean_tx_irq - Reclaim resources after transmit completes
4252 * @adapter: board private structure
4253 * returns true if ring is completely cleaned
4254 **/
3b644cf6 4255static bool igb_clean_tx_irq(struct igb_ring *tx_ring)
9d5c8243 4256{
3b644cf6 4257 struct igb_adapter *adapter = tx_ring->adapter;
3b644cf6 4258 struct net_device *netdev = adapter->netdev;
0e014cb1 4259 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 4260 struct igb_buffer *buffer_info;
4261 struct sk_buff *skb;
0e014cb1 4262 union e1000_adv_tx_desc *tx_desc, *eop_desc;
9d5c8243 4263 unsigned int total_bytes = 0, total_packets = 0;
0e014cb1
AD		 4264 unsigned int i, eop, count = 0;
4265 bool cleaned = false;
9d5c8243 4266
9d5c8243 4267 i = tx_ring->next_to_clean;
0e014cb1
AD		 4268 eop = tx_ring->buffer_info[i].next_to_watch;
4269 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4270
4271 while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) &&
4272 (count < tx_ring->count)) {
4273 for (cleaned = false; !cleaned; count++) {
4274 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
9d5c8243 4275 buffer_info = &tx_ring->buffer_info[i];
0e014cb1 4276 cleaned = (i == eop);
9d5c8243
AK		 4277 skb = buffer_info->skb;
4278
4279 if (skb) {
4280 unsigned int segs, bytecount;
4281 /* gso_segs is currently only valid for tcp */
4282 segs = skb_shinfo(skb)->gso_segs ?: 1;
4283 /* multiply data chunks by size of headers */
4284 bytecount = ((segs - 1) * skb_headlen(skb)) +
4285 skb->len;
4286 total_packets += segs;
4287 total_bytes += bytecount;
33af6bcc
PO		 4288
4289 igb_tx_hwtstamp(adapter, skb);
9d5c8243
AK		 4290 }
4291
4292 igb_unmap_and_free_tx_resource(adapter, buffer_info);
0e014cb1 4293 tx_desc->wb.status = 0;
9d5c8243
AK		 4294
4295 i++;
4296 if (i == tx_ring->count)
4297 i = 0;
9d5c8243 4298 }
0e014cb1
AD		 4299 eop = tx_ring->buffer_info[i].next_to_watch;
4300 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4301 }
4302
9d5c8243
AK		 4303 tx_ring->next_to_clean = i;
4304
fc7d345d 4305 if (unlikely(count &&
9d5c8243
AK		 4306 netif_carrier_ok(netdev) &&
4307 IGB_DESC_UNUSED(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
4308 /* Make sure that anybody stopping the queue after this
4309 * sees the new next_to_clean.
4310 */
4311 smp_mb();
661086df
PWJ		 4312 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
4313 !(test_bit(__IGB_DOWN, &adapter->state))) {
4314 netif_wake_subqueue(netdev, tx_ring->queue_index);
4315 ++adapter->restart_queue;
4316 }
9d5c8243
AK		 4317 }
4318
4319 if (tx_ring->detect_tx_hung) {
4320 /* Detect a transmit hang in hardware, this serializes the
4321 * check with the clearing of time_stamp and movement of i */
4322 tx_ring->detect_tx_hung = false;
4323 if (tx_ring->buffer_info[i].time_stamp &&
4324 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
4325 (adapter->tx_timeout_factor * HZ))
4326 && !(rd32(E1000_STATUS) &
4327 E1000_STATUS_TXOFF)) {
4328
9d5c8243
AK		 4329 /* detected Tx unit hang */
4330 dev_err(&adapter->pdev->dev,
4331 "Detected Tx Unit Hang\n"
2d064c06 4332 " Tx Queue <%d>\n"
9d5c8243
AK		 4333 " TDH <%x>\n"
4334 " TDT <%x>\n"
4335 " next_to_use <%x>\n"
4336 " next_to_clean <%x>\n"
9d5c8243
AK		 4337 "buffer_info[next_to_clean]\n"
4338 " time_stamp <%lx>\n"
0e014cb1 4339 " next_to_watch <%x>\n"
9d5c8243
AK		 4340 " jiffies <%lx>\n"
4341 " desc.status <%x>\n",
2d064c06 4342 tx_ring->queue_index,
9d5c8243
AK		 4343 readl(adapter->hw.hw_addr + tx_ring->head),
4344 readl(adapter->hw.hw_addr + tx_ring->tail),
4345 tx_ring->next_to_use,
4346 tx_ring->next_to_clean,
9d5c8243 4347 tx_ring->buffer_info[i].time_stamp,
0e014cb1 4348 eop,
9d5c8243 4349 jiffies,
0e014cb1 4350 eop_desc->wb.status);
661086df 4351 netif_stop_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 4352 }
4353 }
4354 tx_ring->total_bytes += total_bytes;
4355 tx_ring->total_packets += total_packets;
e21ed353
AD		 4356 tx_ring->tx_stats.bytes += total_bytes;
4357 tx_ring->tx_stats.packets += total_packets;
9d5c8243
AK		 4358 adapter->net_stats.tx_bytes += total_bytes;
4359 adapter->net_stats.tx_packets += total_packets;
0e014cb1 4360 return (count < tx_ring->count);
9d5c8243
AK		 4361}
4362
9d5c8243
AK		 4363/**
4364 * igb_receive_skb - helper function to handle rx indications
eebbbdba 4365 * @ring: pointer to receive ring receving this packet
9d5c8243 4366 * @status: descriptor status field as written by hardware
73cd78f1 4367 * @rx_desc: receive descriptor containing vlan and type information.
9d5c8243
AK		 4368 * @skb: pointer to sk_buff to be indicated to stack
4369 **/
d3352520
AD		 4370static void igb_receive_skb(struct igb_ring *ring, u8 status,
4371 union e1000_adv_rx_desc * rx_desc,
4372 struct sk_buff *skb)
4373{
4374 struct igb_adapter * adapter = ring->adapter;
4375 bool vlan_extracted = (adapter->vlgrp && (status & E1000_RXD_STAT_VP));
4376
0c8dfc83 4377 skb_record_rx_queue(skb, ring->queue_index);
5c0999b7 4378 if (skb->ip_summed == CHECKSUM_UNNECESSARY) {
d3352520 4379 if (vlan_extracted)
5c0999b7
HX		 4380 vlan_gro_receive(&ring->napi, adapter->vlgrp,
4381 le16_to_cpu(rx_desc->wb.upper.vlan),
4382 skb);
d3352520 4383 else
5c0999b7 4384 napi_gro_receive(&ring->napi, skb);
d3352520 4385 } else {
d3352520
AD		 4386 if (vlan_extracted)
4387 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
4388 le16_to_cpu(rx_desc->wb.upper.vlan));
4389 else
d3352520 4390 netif_receive_skb(skb);
d3352520 4391 }
9d5c8243
AK		 4392}
4393
9d5c8243
AK		 4394static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
4395 u32 status_err, struct sk_buff *skb)
4396{
4397 skb->ip_summed = CHECKSUM_NONE;
4398
4399 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
4400 if ((status_err & E1000_RXD_STAT_IXSM) || !adapter->rx_csum)
4401 return;
4402 /* TCP/UDP checksum error bit is set */
4403 if (status_err &
4404 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
4405 /* let the stack verify checksum errors */
4406 adapter->hw_csum_err++;
4407 return;
4408 }
4409 /* It must be a TCP or UDP packet with a valid checksum */
4410 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
4411 skb->ip_summed = CHECKSUM_UNNECESSARY;
4412
4413 adapter->hw_csum_good++;
4414}
4415
3b644cf6
MW		 4416static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring,
4417 int *work_done, int budget)
9d5c8243 4418{
3b644cf6 4419 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 4420 struct net_device *netdev = adapter->netdev;
33af6bcc 4421 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 4422 struct pci_dev *pdev = adapter->pdev;
4423 union e1000_adv_rx_desc *rx_desc , *next_rxd;
4424 struct igb_buffer *buffer_info , *next_buffer;
4425 struct sk_buff *skb;
9d5c8243
AK		 4426 bool cleaned = false;
4427 int cleaned_count = 0;
4428 unsigned int total_bytes = 0, total_packets = 0;
73cd78f1
AD		 4429 unsigned int i;
4430 u32 length, hlen, staterr;
9d5c8243
AK		 4431
4432 i = rx_ring->next_to_clean;
69d3ca53 4433 buffer_info = &rx_ring->buffer_info[i];
9d5c8243
AK		 4434 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4435 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4436
4437 while (staterr & E1000_RXD_STAT_DD) {
4438 if (*work_done >= budget)
4439 break;
4440 (*work_done)++;
9d5c8243 4441
69d3ca53
AD		 4442 skb = buffer_info->skb;
4443 prefetch(skb->data - NET_IP_ALIGN);
4444 buffer_info->skb = NULL;
4445
4446 i++;
4447 if (i == rx_ring->count)
4448 i = 0;
4449 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
4450 prefetch(next_rxd);
4451 next_buffer = &rx_ring->buffer_info[i];
9d5c8243
AK		 4452
4453 length = le16_to_cpu(rx_desc->wb.upper.length);
4454 cleaned = true;
4455 cleaned_count++;
4456
bf36c1a0
AD		 4457 if (!adapter->rx_ps_hdr_size) {
4458 pci_unmap_single(pdev, buffer_info->dma,
4459 adapter->rx_buffer_len +
4460 NET_IP_ALIGN,
4461 PCI_DMA_FROMDEVICE);
4462 skb_put(skb, length);
4463 goto send_up;
9d5c8243
AK		 4464 }
4465
69d3ca53
AD		 4466 /* HW will not DMA in data larger than the given buffer, even
4467 * if it parses the (NFS, of course) header to be larger. In
4468 * that case, it fills the header buffer and spills the rest
4469 * into the page.
4470 */
4471 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
4472 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
4473 if (hlen > adapter->rx_ps_hdr_size)
4474 hlen = adapter->rx_ps_hdr_size;
4475
bf36c1a0
AD		 4476 if (!skb_shinfo(skb)->nr_frags) {
4477 pci_unmap_single(pdev, buffer_info->dma,
73cd78f1 4478 adapter->rx_ps_hdr_size + NET_IP_ALIGN,
bf36c1a0
AD		 4479 PCI_DMA_FROMDEVICE);
4480 skb_put(skb, hlen);
4481 }
4482
4483 if (length) {
9d5c8243 4484 pci_unmap_page(pdev, buffer_info->page_dma,
bf36c1a0 4485 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9d5c8243 4486 buffer_info->page_dma = 0;
bf36c1a0
AD		 4487
4488 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
4489 buffer_info->page,
4490 buffer_info->page_offset,
4491 length);
4492
4493 if ((adapter->rx_buffer_len > (PAGE_SIZE / 2)) ||
4494 (page_count(buffer_info->page) != 1))
4495 buffer_info->page = NULL;
4496 else
4497 get_page(buffer_info->page);
9d5c8243
AK		 4498
4499 skb->len += length;
4500 skb->data_len += length;
9d5c8243 4501
bf36c1a0 4502 skb->truesize += length;
9d5c8243 4503 }
9d5c8243 4504
bf36c1a0 4505 if (!(staterr & E1000_RXD_STAT_EOP)) {
b2d56536
AD		 4506 buffer_info->skb = next_buffer->skb;
4507 buffer_info->dma = next_buffer->dma;
4508 next_buffer->skb = skb;
4509 next_buffer->dma = 0;
bf36c1a0
AD		 4510 goto next_desc;
4511 }
69d3ca53 4512send_up:
33af6bcc
PO		 4513 /*
4514 * If this bit is set, then the RX registers contain
4515 * the time stamp. No other packet will be time
4516 * stamped until we read these registers, so read the
4517 * registers to make them available again. Because
4518 * only one packet can be time stamped at a time, we
4519 * know that the register values must belong to this
4520 * one here and therefore we don't need to compare
4521 * any of the additional attributes stored for it.
4522 *
4523 * If nothing went wrong, then it should have a
4524 * skb_shared_tx that we can turn into a
4525 * skb_shared_hwtstamps.
4526 *
4527 * TODO: can time stamping be triggered (thus locking
4528 * the registers) without the packet reaching this point
4529 * here? In that case RX time stamping would get stuck.
4530 *
4531 * TODO: in "time stamp all packets" mode this bit is
4532 * not set. Need a global flag for this mode and then
4533 * always read the registers. Cannot be done without
4534 * a race condition.
4535 */
4536 if (unlikely(staterr & E1000_RXD_STAT_TS)) {
4537 u64 regval;
4538 u64 ns;
4539 struct skb_shared_hwtstamps *shhwtstamps =
4540 skb_hwtstamps(skb);
4541
4542 WARN(!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID),
4543 "igb: no RX time stamp available for time stamped packet");
4544 regval = rd32(E1000_RXSTMPL);
4545 regval |= (u64)rd32(E1000_RXSTMPH) << 32;
4546 ns = timecounter_cyc2time(&adapter->clock, regval);
4547 timecompare_update(&adapter->compare, ns);
4548 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
4549 shhwtstamps->hwtstamp = ns_to_ktime(ns);
4550 shhwtstamps->syststamp =
4551 timecompare_transform(&adapter->compare, ns);
4552 }
4553
9d5c8243
AK		 4554 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
4555 dev_kfree_skb_irq(skb);
4556 goto next_desc;
4557 }
9d5c8243
AK		 4558
4559 total_bytes += skb->len;
4560 total_packets++;
4561
4562 igb_rx_checksum_adv(adapter, staterr, skb);
4563
4564 skb->protocol = eth_type_trans(skb, netdev);
4565
d3352520 4566 igb_receive_skb(rx_ring, staterr, rx_desc, skb);
9d5c8243 4567
9d5c8243
AK		 4568next_desc:
4569 rx_desc->wb.upper.status_error = 0;
4570
4571 /* return some buffers to hardware, one at a time is too slow */
4572 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
3b644cf6 4573 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 4574 cleaned_count = 0;
4575 }
4576
4577 /* use prefetched values */
4578 rx_desc = next_rxd;
4579 buffer_info = next_buffer;
9d5c8243
AK		 4580 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4581 }
bf36c1a0 4582
9d5c8243
AK		 4583 rx_ring->next_to_clean = i;
4584 cleaned_count = IGB_DESC_UNUSED(rx_ring);
4585
4586 if (cleaned_count)
3b644cf6 4587 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 4588
4589 rx_ring->total_packets += total_packets;
4590 rx_ring->total_bytes += total_bytes;
4591 rx_ring->rx_stats.packets += total_packets;
4592 rx_ring->rx_stats.bytes += total_bytes;
4593 adapter->net_stats.rx_bytes += total_bytes;
4594 adapter->net_stats.rx_packets += total_packets;
4595 return cleaned;
4596}
4597
9d5c8243
AK		 4598/**
4599 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
4600 * @adapter: address of board private structure
4601 **/
3b644cf6 4602static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
9d5c8243
AK		 4603 int cleaned_count)
4604{
3b644cf6 4605 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 4606 struct net_device *netdev = adapter->netdev;
4607 struct pci_dev *pdev = adapter->pdev;
4608 union e1000_adv_rx_desc *rx_desc;
4609 struct igb_buffer *buffer_info;
4610 struct sk_buff *skb;
4611 unsigned int i;
db761762 4612 int bufsz;
9d5c8243
AK		 4613
4614 i = rx_ring->next_to_use;
4615 buffer_info = &rx_ring->buffer_info[i];
4616
db761762
AD		 4617 if (adapter->rx_ps_hdr_size)
4618 bufsz = adapter->rx_ps_hdr_size;
4619 else
4620 bufsz = adapter->rx_buffer_len;
4621 bufsz += NET_IP_ALIGN;
4622
9d5c8243
AK		 4623 while (cleaned_count--) {
4624 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4625
bf36c1a0 4626 if (adapter->rx_ps_hdr_size && !buffer_info->page_dma) {
9d5c8243 4627 if (!buffer_info->page) {
bf36c1a0
AD		 4628 buffer_info->page = alloc_page(GFP_ATOMIC);
4629 if (!buffer_info->page) {
4630 adapter->alloc_rx_buff_failed++;
4631 goto no_buffers;
4632 }
4633 buffer_info->page_offset = 0;
4634 } else {
4635 buffer_info->page_offset ^= PAGE_SIZE / 2;
9d5c8243
AK		 4636 }
4637 buffer_info->page_dma =
db761762 4638 pci_map_page(pdev, buffer_info->page,
bf36c1a0
AD		 4639 buffer_info->page_offset,
4640 PAGE_SIZE / 2,
9d5c8243
AK		 4641 PCI_DMA_FROMDEVICE);
4642 }
4643
4644 if (!buffer_info->skb) {
9d5c8243 4645 skb = netdev_alloc_skb(netdev, bufsz);
9d5c8243
AK		 4646 if (!skb) {
4647 adapter->alloc_rx_buff_failed++;
4648 goto no_buffers;
4649 }
4650
4651 /* Make buffer alignment 2 beyond a 16 byte boundary
4652 * this will result in a 16 byte aligned IP header after
4653 * the 14 byte MAC header is removed
4654 */
4655 skb_reserve(skb, NET_IP_ALIGN);
4656
4657 buffer_info->skb = skb;
4658 buffer_info->dma = pci_map_single(pdev, skb->data,
4659 bufsz,
4660 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 4661 }
4662 /* Refresh the desc even if buffer_addrs didn't change because
4663 * each write-back erases this info. */
4664 if (adapter->rx_ps_hdr_size) {
4665 rx_desc->read.pkt_addr =
4666 cpu_to_le64(buffer_info->page_dma);
4667 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
4668 } else {
4669 rx_desc->read.pkt_addr =
4670 cpu_to_le64(buffer_info->dma);
4671 rx_desc->read.hdr_addr = 0;
4672 }
4673
4674 i++;
4675 if (i == rx_ring->count)
4676 i = 0;
4677 buffer_info = &rx_ring->buffer_info[i];
4678 }
4679
4680no_buffers:
4681 if (rx_ring->next_to_use != i) {
4682 rx_ring->next_to_use = i;
4683 if (i == 0)
4684 i = (rx_ring->count - 1);
4685 else
4686 i--;
4687
4688 /* Force memory writes to complete before letting h/w
4689 * know there are new descriptors to fetch. (Only
4690 * applicable for weak-ordered memory model archs,
4691 * such as IA-64). */
4692 wmb();
4693 writel(i, adapter->hw.hw_addr + rx_ring->tail);
4694 }
4695}
4696
4697/**
4698 * igb_mii_ioctl -
4699 * @netdev:
4700 * @ifreq:
4701 * @cmd:
4702 **/
4703static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4704{
4705 struct igb_adapter *adapter = netdev_priv(netdev);
4706 struct mii_ioctl_data *data = if_mii(ifr);
4707
4708 if (adapter->hw.phy.media_type != e1000_media_type_copper)
4709 return -EOPNOTSUPP;
4710
4711 switch (cmd) {
4712 case SIOCGMIIPHY:
4713 data->phy_id = adapter->hw.phy.addr;
4714 break;
4715 case SIOCGMIIREG:
4716 if (!capable(CAP_NET_ADMIN))
4717 return -EPERM;
f5f4cf08
AD		 4718 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
4719 &data->val_out))
9d5c8243
AK		 4720 return -EIO;
4721 break;
4722 case SIOCSMIIREG:
4723 default:
4724 return -EOPNOTSUPP;
4725 }
4726 return 0;
4727}
4728
c6cb090b
PO		 4729/**
4730 * igb_hwtstamp_ioctl - control hardware time stamping
4731 * @netdev:
4732 * @ifreq:
4733 * @cmd:
4734 *
33af6bcc
PO		 4735 * Outgoing time stamping can be enabled and disabled. Play nice and
4736 * disable it when requested, although it shouldn't case any overhead
4737 * when no packet needs it. At most one packet in the queue may be
4738 * marked for time stamping, otherwise it would be impossible to tell
4739 * for sure to which packet the hardware time stamp belongs.
4740 *
4741 * Incoming time stamping has to be configured via the hardware
4742 * filters. Not all combinations are supported, in particular event
4743 * type has to be specified. Matching the kind of event packet is
4744 * not supported, with the exception of "all V2 events regardless of
4745 * level 2 or 4".
4746 *
c6cb090b
PO		 4747 **/
4748static int igb_hwtstamp_ioctl(struct net_device *netdev,
4749 struct ifreq *ifr, int cmd)
4750{
33af6bcc
PO		 4751 struct igb_adapter *adapter = netdev_priv(netdev);
4752 struct e1000_hw *hw = &adapter->hw;
c6cb090b 4753 struct hwtstamp_config config;
33af6bcc
PO		 4754 u32 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
4755 u32 tsync_rx_ctl_bit = E1000_TSYNCRXCTL_ENABLED;
4756 u32 tsync_rx_ctl_type = 0;
4757 u32 tsync_rx_cfg = 0;
4758 int is_l4 = 0;
4759 int is_l2 = 0;
4760 short port = 319; /* PTP */
4761 u32 regval;
c6cb090b
PO		 4762
4763 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
4764 return -EFAULT;
4765
4766 /* reserved for future extensions */
4767 if (config.flags)
4768 return -EINVAL;
4769
33af6bcc
PO		 4770 switch (config.tx_type) {
4771 case HWTSTAMP_TX_OFF:
4772 tsync_tx_ctl_bit = 0;
4773 break;
4774 case HWTSTAMP_TX_ON:
4775 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
4776 break;
4777 default:
4778 return -ERANGE;
4779 }
4780
4781 switch (config.rx_filter) {
4782 case HWTSTAMP_FILTER_NONE:
4783 tsync_rx_ctl_bit = 0;
4784 break;
4785 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4786 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4787 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4788 case HWTSTAMP_FILTER_ALL:
4789 /*
4790 * register TSYNCRXCFG must be set, therefore it is not
4791 * possible to time stamp both Sync and Delay_Req messages
4792 * => fall back to time stamping all packets
4793 */
4794 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_ALL;
4795 config.rx_filter = HWTSTAMP_FILTER_ALL;
4796 break;
4797 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4798 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
4799 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
4800 is_l4 = 1;
4801 break;
4802 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4803 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
4804 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
4805 is_l4 = 1;
4806 break;
4807 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4808 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4809 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
4810 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE;
4811 is_l2 = 1;
4812 is_l4 = 1;
4813 config.rx_filter = HWTSTAMP_FILTER_SOME;
4814 break;
4815 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4816 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4817 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
4818 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE;
4819 is_l2 = 1;
4820 is_l4 = 1;
4821 config.rx_filter = HWTSTAMP_FILTER_SOME;
4822 break;
4823 case HWTSTAMP_FILTER_PTP_V2_EVENT:
4824 case HWTSTAMP_FILTER_PTP_V2_SYNC:
4825 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4826 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_EVENT_V2;
4827 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
4828 is_l2 = 1;
4829 break;
4830 default:
4831 return -ERANGE;
4832 }
4833
4834 /* enable/disable TX */
4835 regval = rd32(E1000_TSYNCTXCTL);
4836 regval = (regval & ~E1000_TSYNCTXCTL_ENABLED) | tsync_tx_ctl_bit;
4837 wr32(E1000_TSYNCTXCTL, regval);
4838
4839 /* enable/disable RX, define which PTP packets are time stamped */
4840 regval = rd32(E1000_TSYNCRXCTL);
4841 regval = (regval & ~E1000_TSYNCRXCTL_ENABLED) | tsync_rx_ctl_bit;
4842 regval = (regval & ~0xE) | tsync_rx_ctl_type;
4843 wr32(E1000_TSYNCRXCTL, regval);
4844 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
4845
4846 /*
4847 * Ethertype Filter Queue Filter[0][15:0] = 0x88F7
4848 * (Ethertype to filter on)
4849 * Ethertype Filter Queue Filter[0][26] = 0x1 (Enable filter)
4850 * Ethertype Filter Queue Filter[0][30] = 0x1 (Enable Timestamping)
4851 */
4852 wr32(E1000_ETQF0, is_l2 ? 0x440088f7 : 0);
4853
4854 /* L4 Queue Filter[0]: only filter by source and destination port */
4855 wr32(E1000_SPQF0, htons(port));
4856 wr32(E1000_IMIREXT(0), is_l4 ?
4857 ((1<<12) | (1<<19) /* bypass size and control flags */) : 0);
4858 wr32(E1000_IMIR(0), is_l4 ?
4859 (htons(port)
4860 | (0<<16) /* immediate interrupt disabled */
4861 | 0 /* (1<<17) bit cleared: do not bypass
4862 destination port check */)
4863 : 0);
4864 wr32(E1000_FTQF0, is_l4 ?
4865 (0x11 /* UDP */
4866 | (1<<15) /* VF not compared */
4867 | (1<<27) /* Enable Timestamping */
4868 | (7<<28) /* only source port filter enabled,
4869 source/target address and protocol
4870 masked */)
4871 : ((1<<15) | (15<<28) /* all mask bits set = filter not
4872 enabled */));
4873
4874 wrfl();
4875
4876 adapter->hwtstamp_config = config;
4877
4878 /* clear TX/RX time stamp registers, just to be sure */
4879 regval = rd32(E1000_TXSTMPH);
4880 regval = rd32(E1000_RXSTMPH);
c6cb090b 4881
33af6bcc
PO		 4882 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
4883 -EFAULT : 0;
c6cb090b
PO		 4884}
4885
9d5c8243
AK		 4886/**
4887 * igb_ioctl -
4888 * @netdev:
4889 * @ifreq:
4890 * @cmd:
4891 **/
4892static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4893{
4894 switch (cmd) {
4895 case SIOCGMIIPHY:
4896 case SIOCGMIIREG:
4897 case SIOCSMIIREG:
4898 return igb_mii_ioctl(netdev, ifr, cmd);
c6cb090b
PO		 4899 case SIOCSHWTSTAMP:
4900 return igb_hwtstamp_ioctl(netdev, ifr, cmd);
9d5c8243
AK		 4901 default:
4902 return -EOPNOTSUPP;
4903 }
4904}
4905
4906static void igb_vlan_rx_register(struct net_device *netdev,
4907 struct vlan_group *grp)
4908{
4909 struct igb_adapter *adapter = netdev_priv(netdev);
4910 struct e1000_hw *hw = &adapter->hw;
4911 u32 ctrl, rctl;
4912
4913 igb_irq_disable(adapter);
4914 adapter->vlgrp = grp;
4915
4916 if (grp) {
4917 /* enable VLAN tag insert/strip */
4918 ctrl = rd32(E1000_CTRL);
4919 ctrl |= E1000_CTRL_VME;
4920 wr32(E1000_CTRL, ctrl);
4921
4922 /* enable VLAN receive filtering */
4923 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 4924 rctl &= ~E1000_RCTL_CFIEN;
4925 wr32(E1000_RCTL, rctl);
4926 igb_update_mng_vlan(adapter);
9d5c8243
AK		 4927 } else {
4928 /* disable VLAN tag insert/strip */
4929 ctrl = rd32(E1000_CTRL);
4930 ctrl &= ~E1000_CTRL_VME;
4931 wr32(E1000_CTRL, ctrl);
4932
9d5c8243
AK		 4933 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
4934 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4935 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
4936 }
9d5c8243
AK		 4937 }
4938
e1739522
AD		 4939 igb_rlpml_set(adapter);
4940
9d5c8243
AK		 4941 if (!test_bit(__IGB_DOWN, &adapter->state))
4942 igb_irq_enable(adapter);
4943}
4944
4945static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
4946{
4947 struct igb_adapter *adapter = netdev_priv(netdev);
4948 struct e1000_hw *hw = &adapter->hw;
4ae196df 4949 int pf_id = adapter->vfs_allocated_count;
9d5c8243 4950
28b0759c 4951 if ((hw->mng_cookie.status &
9d5c8243
AK		 4952 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4953 (vid == adapter->mng_vlan_id))
4954 return;
4ae196df
AD		 4955
4956 /* add vid to vlvf if sr-iov is enabled,
4957 * if that fails add directly to filter table */
4958 if (igb_vlvf_set(adapter, vid, true, pf_id))
4959 igb_vfta_set(hw, vid, true);
4960
9d5c8243
AK		 4961}
4962
4963static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
4964{
4965 struct igb_adapter *adapter = netdev_priv(netdev);
4966 struct e1000_hw *hw = &adapter->hw;
4ae196df 4967 int pf_id = adapter->vfs_allocated_count;
9d5c8243
AK		 4968
4969 igb_irq_disable(adapter);
4970 vlan_group_set_device(adapter->vlgrp, vid, NULL);
4971
4972 if (!test_bit(__IGB_DOWN, &adapter->state))
4973 igb_irq_enable(adapter);
4974
4975 if ((adapter->hw.mng_cookie.status &
4976 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4977 (vid == adapter->mng_vlan_id)) {
4978 /* release control to f/w */
4979 igb_release_hw_control(adapter);
4980 return;
4981 }
4982
4ae196df
AD		 4983 /* remove vid from vlvf if sr-iov is enabled,
4984 * if not in vlvf remove from vfta */
4985 if (igb_vlvf_set(adapter, vid, false, pf_id))
4986 igb_vfta_set(hw, vid, false);
9d5c8243
AK		 4987}
4988
4989static void igb_restore_vlan(struct igb_adapter *adapter)
4990{
4991 igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
4992
4993 if (adapter->vlgrp) {
4994 u16 vid;
4995 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
4996 if (!vlan_group_get_device(adapter->vlgrp, vid))
4997 continue;
4998 igb_vlan_rx_add_vid(adapter->netdev, vid);
4999 }
5000 }
5001}
5002
5003int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
5004{
5005 struct e1000_mac_info *mac = &adapter->hw.mac;
5006
5007 mac->autoneg = 0;
5008
5009 /* Fiber NICs only allow 1000 gbps Full duplex */
5010 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) &&
5011 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
5012 dev_err(&adapter->pdev->dev,
5013 "Unsupported Speed/Duplex configuration\n");
5014 return -EINVAL;
5015 }
5016
5017 switch (spddplx) {
5018 case SPEED_10 + DUPLEX_HALF:
5019 mac->forced_speed_duplex = ADVERTISE_10_HALF;
5020 break;
5021 case SPEED_10 + DUPLEX_FULL:
5022 mac->forced_speed_duplex = ADVERTISE_10_FULL;
5023 break;
5024 case SPEED_100 + DUPLEX_HALF:
5025 mac->forced_speed_duplex = ADVERTISE_100_HALF;
5026 break;
5027 case SPEED_100 + DUPLEX_FULL:
5028 mac->forced_speed_duplex = ADVERTISE_100_FULL;
5029 break;
5030 case SPEED_1000 + DUPLEX_FULL:
5031 mac->autoneg = 1;
5032 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
5033 break;
5034 case SPEED_1000 + DUPLEX_HALF: /* not supported */
5035 default:
5036 dev_err(&adapter->pdev->dev,
5037 "Unsupported Speed/Duplex configuration\n");
5038 return -EINVAL;
5039 }
5040 return 0;
5041}
5042
9d5c8243
AK		 5043static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
5044{
5045 struct net_device *netdev = pci_get_drvdata(pdev);
5046 struct igb_adapter *adapter = netdev_priv(netdev);
5047 struct e1000_hw *hw = &adapter->hw;
2d064c06 5048 u32 ctrl, rctl, status;
9d5c8243
AK		 5049 u32 wufc = adapter->wol;
5050#ifdef CONFIG_PM
5051 int retval = 0;
5052#endif
5053
5054 netif_device_detach(netdev);
5055
a88f10ec
AD		 5056 if (netif_running(netdev))
5057 igb_close(netdev);
5058
5059 igb_reset_interrupt_capability(adapter);
5060
5061 igb_free_queues(adapter);
9d5c8243
AK		 5062
5063#ifdef CONFIG_PM
5064 retval = pci_save_state(pdev);
5065 if (retval)
5066 return retval;
5067#endif
5068
5069 status = rd32(E1000_STATUS);
5070 if (status & E1000_STATUS_LU)
5071 wufc &= ~E1000_WUFC_LNKC;
5072
5073 if (wufc) {
5074 igb_setup_rctl(adapter);
5075 igb_set_multi(netdev);
5076
5077 /* turn on all-multi mode if wake on multicast is enabled */
5078 if (wufc & E1000_WUFC_MC) {
5079 rctl = rd32(E1000_RCTL);
5080 rctl |= E1000_RCTL_MPE;
5081 wr32(E1000_RCTL, rctl);
5082 }
5083
5084 ctrl = rd32(E1000_CTRL);
5085 /* advertise wake from D3Cold */
5086 #define E1000_CTRL_ADVD3WUC 0x00100000
5087 /* phy power management enable */
5088 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
5089 ctrl |= E1000_CTRL_ADVD3WUC;
5090 wr32(E1000_CTRL, ctrl);
5091
9d5c8243
AK		 5092 /* Allow time for pending master requests to run */
5093 igb_disable_pcie_master(&adapter->hw);
5094
5095 wr32(E1000_WUC, E1000_WUC_PME_EN);
5096 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 5097 } else {
5098 wr32(E1000_WUC, 0);
5099 wr32(E1000_WUFC, 0);
9d5c8243
AK		 5100 }
5101
2d064c06
AD		 5102 /* make sure adapter isn't asleep if manageability/wol is enabled */
5103 if (wufc || adapter->en_mng_pt) {
9d5c8243
AK		 5104 pci_enable_wake(pdev, PCI_D3hot, 1);
5105 pci_enable_wake(pdev, PCI_D3cold, 1);
2d064c06
AD		 5106 } else {
5107 igb_shutdown_fiber_serdes_link_82575(hw);
5108 pci_enable_wake(pdev, PCI_D3hot, 0);
5109 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243
AK		 5110 }
5111
5112 /* Release control of h/w to f/w. If f/w is AMT enabled, this
5113 * would have already happened in close and is redundant. */
5114 igb_release_hw_control(adapter);
5115
5116 pci_disable_device(pdev);
5117
5118 pci_set_power_state(pdev, pci_choose_state(pdev, state));
5119
5120 return 0;
5121}
5122
5123#ifdef CONFIG_PM
5124static int igb_resume(struct pci_dev *pdev)
5125{
5126 struct net_device *netdev = pci_get_drvdata(pdev);
5127 struct igb_adapter *adapter = netdev_priv(netdev);
5128 struct e1000_hw *hw = &adapter->hw;
5129 u32 err;
5130
5131 pci_set_power_state(pdev, PCI_D0);
5132 pci_restore_state(pdev);
42bfd33a 5133
aed5dec3 5134 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 5135 if (err) {
5136 dev_err(&pdev->dev,
5137 "igb: Cannot enable PCI device from suspend\n");
5138 return err;
5139 }
5140 pci_set_master(pdev);
5141
5142 pci_enable_wake(pdev, PCI_D3hot, 0);
5143 pci_enable_wake(pdev, PCI_D3cold, 0);
5144
a88f10ec
AD		 5145 igb_set_interrupt_capability(adapter);
5146
5147 if (igb_alloc_queues(adapter)) {
5148 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
5149 return -ENOMEM;
9d5c8243
AK		 5150 }
5151
5152 /* e1000_power_up_phy(adapter); */
5153
5154 igb_reset(adapter);
a8564f03
AD		 5155
5156 /* let the f/w know that the h/w is now under the control of the
5157 * driver. */
5158 igb_get_hw_control(adapter);
5159
9d5c8243
AK		 5160 wr32(E1000_WUS, ~0);
5161
a88f10ec
AD		 5162 if (netif_running(netdev)) {
5163 err = igb_open(netdev);
5164 if (err)
5165 return err;
5166 }
9d5c8243
AK		 5167
5168 netif_device_attach(netdev);
5169
9d5c8243
AK		 5170 return 0;
5171}
5172#endif
5173
5174static void igb_shutdown(struct pci_dev *pdev)
5175{
5176 igb_suspend(pdev, PMSG_SUSPEND);
5177}
5178
5179#ifdef CONFIG_NET_POLL_CONTROLLER
5180/*
5181 * Polling 'interrupt' - used by things like netconsole to send skbs
5182 * without having to re-enable interrupts. It's not called while
5183 * the interrupt routine is executing.
5184 */
5185static void igb_netpoll(struct net_device *netdev)
5186{
5187 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 5188 struct e1000_hw *hw = &adapter->hw;
9d5c8243 5189 int i;
9d5c8243 5190
eebbbdba
AD		 5191 if (!adapter->msix_entries) {
5192 igb_irq_disable(adapter);
5193 napi_schedule(&adapter->rx_ring[0].napi);
5194 return;
5195 }
9d5c8243 5196
eebbbdba
AD		 5197 for (i = 0; i < adapter->num_tx_queues; i++) {
5198 struct igb_ring *tx_ring = &adapter->tx_ring[i];
5199 wr32(E1000_EIMC, tx_ring->eims_value);
5200 igb_clean_tx_irq(tx_ring);
5201 wr32(E1000_EIMS, tx_ring->eims_value);
5202 }
9d5c8243 5203
eebbbdba
AD		 5204 for (i = 0; i < adapter->num_rx_queues; i++) {
5205 struct igb_ring *rx_ring = &adapter->rx_ring[i];
5206 wr32(E1000_EIMC, rx_ring->eims_value);
5207 napi_schedule(&rx_ring->napi);
5208 }
9d5c8243
AK		 5209}
5210#endif /* CONFIG_NET_POLL_CONTROLLER */
5211
5212/**
5213 * igb_io_error_detected - called when PCI error is detected
5214 * @pdev: Pointer to PCI device
5215 * @state: The current pci connection state
5216 *
5217 * This function is called after a PCI bus error affecting
5218 * this device has been detected.
5219 */
5220static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
5221 pci_channel_state_t state)
5222{
5223 struct net_device *netdev = pci_get_drvdata(pdev);
5224 struct igb_adapter *adapter = netdev_priv(netdev);
5225
5226 netif_device_detach(netdev);
5227
5228 if (netif_running(netdev))
5229 igb_down(adapter);
5230 pci_disable_device(pdev);
5231
5232 /* Request a slot slot reset. */
5233 return PCI_ERS_RESULT_NEED_RESET;
5234}
5235
5236/**
5237 * igb_io_slot_reset - called after the pci bus has been reset.
5238 * @pdev: Pointer to PCI device
5239 *
5240 * Restart the card from scratch, as if from a cold-boot. Implementation
5241 * resembles the first-half of the igb_resume routine.
5242 */
5243static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
5244{
5245 struct net_device *netdev = pci_get_drvdata(pdev);
5246 struct igb_adapter *adapter = netdev_priv(netdev);
5247 struct e1000_hw *hw = &adapter->hw;
40a914fa 5248 pci_ers_result_t result;
42bfd33a 5249 int err;
9d5c8243 5250
aed5dec3 5251 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 5252 dev_err(&pdev->dev,
5253 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 5254 result = PCI_ERS_RESULT_DISCONNECT;
5255 } else {
5256 pci_set_master(pdev);
5257 pci_restore_state(pdev);
9d5c8243 5258
40a914fa
AD		 5259 pci_enable_wake(pdev, PCI_D3hot, 0);
5260 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 5261
40a914fa
AD		 5262 igb_reset(adapter);
5263 wr32(E1000_WUS, ~0);
5264 result = PCI_ERS_RESULT_RECOVERED;
5265 }
9d5c8243 5266
ea943d41
JK		 5267 err = pci_cleanup_aer_uncorrect_error_status(pdev);
5268 if (err) {
5269 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
5270 "failed 0x%0x\n", err);
5271 /* non-fatal, continue */
5272 }
40a914fa
AD		 5273
5274 return result;
9d5c8243
AK		 5275}
5276
5277/**
5278 * igb_io_resume - called when traffic can start flowing again.
5279 * @pdev: Pointer to PCI device
5280 *
5281 * This callback is called when the error recovery driver tells us that
5282 * its OK to resume normal operation. Implementation resembles the
5283 * second-half of the igb_resume routine.
5284 */
5285static void igb_io_resume(struct pci_dev *pdev)
5286{
5287 struct net_device *netdev = pci_get_drvdata(pdev);
5288 struct igb_adapter *adapter = netdev_priv(netdev);
5289
9d5c8243
AK		 5290 if (netif_running(netdev)) {
5291 if (igb_up(adapter)) {
5292 dev_err(&pdev->dev, "igb_up failed after reset\n");
5293 return;
5294 }
5295 }
5296
5297 netif_device_attach(netdev);
5298
5299 /* let the f/w know that the h/w is now under the control of the
5300 * driver. */
5301 igb_get_hw_control(adapter);
9d5c8243
AK		 5302}
5303
e1739522
AD		 5304static inline void igb_set_vmolr(struct e1000_hw *hw, int vfn)
5305{
5306 u32 reg_data;
5307
5308 reg_data = rd32(E1000_VMOLR(vfn));
5309 reg_data |= E1000_VMOLR_BAM | /* Accept broadcast */
5310 E1000_VMOLR_ROPE | /* Accept packets matched in UTA */
5311 E1000_VMOLR_ROMPE | /* Accept packets matched in MTA */
5312 E1000_VMOLR_AUPE | /* Accept untagged packets */
5313 E1000_VMOLR_STRVLAN; /* Strip vlan tags */
5314 wr32(E1000_VMOLR(vfn), reg_data);
5315}
5316
4ae196df
AD		 5317static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
5318 int vfn)
e1739522
AD		 5319{
5320 struct e1000_hw *hw = &adapter->hw;
5321 u32 vmolr;
5322
5323 vmolr = rd32(E1000_VMOLR(vfn));
5324 vmolr &= ~E1000_VMOLR_RLPML_MASK;
5325 vmolr |= size | E1000_VMOLR_LPE;
5326 wr32(E1000_VMOLR(vfn), vmolr);
4ae196df
AD		 5327
5328 return 0;
e1739522
AD		 5329}
5330
5331static inline void igb_set_rah_pool(struct e1000_hw *hw, int pool, int entry)
5332{
5333 u32 reg_data;
5334
5335 reg_data = rd32(E1000_RAH(entry));
5336 reg_data &= ~E1000_RAH_POOL_MASK;
5337 reg_data |= E1000_RAH_POOL_1 << pool;;
5338 wr32(E1000_RAH(entry), reg_data);
5339}
5340
5341static void igb_set_mc_list_pools(struct igb_adapter *adapter,
5342 int entry_count, u16 total_rar_filters)
5343{
5344 struct e1000_hw *hw = &adapter->hw;
5345 int i = adapter->vfs_allocated_count + 1;
5346
5347 if ((i + entry_count) < total_rar_filters)
5348 total_rar_filters = i + entry_count;
5349
5350 for (; i < total_rar_filters; i++)
5351 igb_set_rah_pool(hw, adapter->vfs_allocated_count, i);
5352}
5353
4ae196df
AD		 5354static int igb_set_vf_mac(struct igb_adapter *adapter,
5355 int vf, unsigned char *mac_addr)
5356{
5357 struct e1000_hw *hw = &adapter->hw;
5358 int rar_entry = vf + 1; /* VF MAC addresses start at entry 1 */
5359
5360 igb_rar_set(hw, mac_addr, rar_entry);
5361
37680117 5362 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df
AD		 5363
5364 igb_set_rah_pool(hw, vf, rar_entry);
5365
5366 return 0;
5367}
5368
5369static void igb_vmm_control(struct igb_adapter *adapter)
5370{
5371 struct e1000_hw *hw = &adapter->hw;
5372 u32 reg_data;
5373
5374 if (!adapter->vfs_allocated_count)
5375 return;
5376
5377 /* VF's need PF reset indication before they
5378 * can send/receive mail */
5379 reg_data = rd32(E1000_CTRL_EXT);
5380 reg_data |= E1000_CTRL_EXT_PFRSTD;
5381 wr32(E1000_CTRL_EXT, reg_data);
5382
5383 igb_vmdq_set_loopback_pf(hw, true);
5384 igb_vmdq_set_replication_pf(hw, true);
5385}
5386
37680117
AD		 5387#ifdef CONFIG_PCI_IOV
5388static ssize_t igb_show_num_vfs(struct device *dev,
5389 struct device_attribute *attr, char *buf)
5390{
5391 struct igb_adapter *adapter = netdev_priv(to_net_dev(dev));
5392
5393 return sprintf(buf, "%d\n", adapter->vfs_allocated_count);
5394}
5395
5396static ssize_t igb_set_num_vfs(struct device *dev,
5397 struct device_attribute *attr,
5398 const char *buf, size_t count)
5399{
5400 struct net_device *netdev = to_net_dev(dev);
5401 struct igb_adapter *adapter = netdev_priv(netdev);
5402 struct e1000_hw *hw = &adapter->hw;
5403 struct pci_dev *pdev = adapter->pdev;
5404 unsigned int num_vfs, i;
5405 unsigned char mac_addr[ETH_ALEN];
5406 int err;
5407
5408 sscanf(buf, "%u", &num_vfs);
5409
5410 if (num_vfs > 7)
5411 num_vfs = 7;
5412
5413 /* value unchanged do nothing */
5414 if (num_vfs == adapter->vfs_allocated_count)
5415 return count;
5416
5417 if (netdev->flags & IFF_UP)
5418 igb_close(netdev);
5419
5420 igb_reset_interrupt_capability(adapter);
5421 igb_free_queues(adapter);
5422 adapter->tx_ring = NULL;
5423 adapter->rx_ring = NULL;
5424 adapter->vfs_allocated_count = 0;
5425
5426 /* reclaim resources allocated to VFs since we are changing count */
5427 if (adapter->vf_data) {
5428 /* disable iov and allow time for transactions to clear */
5429 pci_disable_sriov(pdev);
5430 msleep(500);
5431
5432 kfree(adapter->vf_data);
5433 adapter->vf_data = NULL;
5434 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
5435 msleep(100);
5436 dev_info(&pdev->dev, "IOV Disabled\n");
5437 }
5438
5439 if (num_vfs) {
5440 adapter->vf_data = kcalloc(num_vfs,
5441 sizeof(struct vf_data_storage),
5442 GFP_KERNEL);
5443 if (!adapter->vf_data) {
5444 dev_err(&pdev->dev, "Could not allocate VF private "
5445 "data - IOV enable failed\n");
5446 } else {
5447 err = pci_enable_sriov(pdev, num_vfs);
5448 if (!err) {
5449 adapter->vfs_allocated_count = num_vfs;
5450 dev_info(&pdev->dev, "%d vfs allocated\n", num_vfs);
5451 for (i = 0; i < adapter->vfs_allocated_count; i++) {
5452 random_ether_addr(mac_addr);
5453 igb_set_vf_mac(adapter, i, mac_addr);
5454 }
5455 } else {
5456 kfree(adapter->vf_data);
5457 adapter->vf_data = NULL;
5458 }
5459 }
5460 }
5461
5462 igb_set_interrupt_capability(adapter);
5463 igb_alloc_queues(adapter);
5464 igb_reset(adapter);
5465
5466 if (netdev->flags & IFF_UP)
5467 igb_open(netdev);
5468
5469 return count;
5470}
5471#endif /* CONFIG_PCI_IOV */
9d5c8243 5472/* igb_main.c */
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