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9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
86d5d38f 4 Copyright(c) 2007-2009 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/module.h>
29#include <linux/types.h>
30#include <linux/init.h>
31#include <linux/vmalloc.h>
32#include <linux/pagemap.h>
33#include <linux/netdevice.h>
9d5c8243 34#include <linux/ipv6.h>
5a0e3ad6 35#include <linux/slab.h>
9d5c8243
AK		 36#include <net/checksum.h>
37#include <net/ip6_checksum.h>
c6cb090b 38#include <linux/net_tstamp.h>
9d5c8243
AK		 39#include <linux/mii.h>
40#include <linux/ethtool.h>
41#include <linux/if_vlan.h>
42#include <linux/pci.h>
c54106bb 43#include <linux/pci-aspm.h>
9d5c8243
AK		 44#include <linux/delay.h>
45#include <linux/interrupt.h>
46#include <linux/if_ether.h>
40a914fa 47#include <linux/aer.h>
421e02f0 48#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 49#include <linux/dca.h>
50#endif
9d5c8243
AK		 51#include "igb.h"
52
55cac248 53#define DRV_VERSION "2.1.0-k2"
9d5c8243
AK		 54char igb_driver_name[] = "igb";
55char igb_driver_version[] = DRV_VERSION;
56static const char igb_driver_string[] =
57 "Intel(R) Gigabit Ethernet Network Driver";
86d5d38f 58static const char igb_copyright[] = "Copyright (c) 2007-2009 Intel Corporation.";
9d5c8243 59
9d5c8243
AK		 60static const struct e1000_info *igb_info_tbl[] = {
61 [board_82575] = &e1000_82575_info,
62};
63
a3aa1884 64static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = {
d2ba2ed8
AD		 65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
55cac248
AD		 69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
70 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
71 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
72 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
73 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
2d064c06 74 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 75 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
747d49ba 76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
2d064c06
AD		 77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
b894fa26 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
c8ea5ea9 81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
85 /* required last entry */
86 {0, }
87};
88
89MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
90
91void igb_reset(struct igb_adapter *);
92static int igb_setup_all_tx_resources(struct igb_adapter *);
93static int igb_setup_all_rx_resources(struct igb_adapter *);
94static void igb_free_all_tx_resources(struct igb_adapter *);
95static void igb_free_all_rx_resources(struct igb_adapter *);
06cf2666 96static void igb_setup_mrqc(struct igb_adapter *);
9d5c8243
AK		 97void igb_update_stats(struct igb_adapter *);
98static int igb_probe(struct pci_dev *, const struct pci_device_id *);
99static void __devexit igb_remove(struct pci_dev *pdev);
100static int igb_sw_init(struct igb_adapter *);
101static int igb_open(struct net_device *);
102static int igb_close(struct net_device *);
103static void igb_configure_tx(struct igb_adapter *);
104static void igb_configure_rx(struct igb_adapter *);
9d5c8243
AK		 105static void igb_clean_all_tx_rings(struct igb_adapter *);
106static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 107static void igb_clean_tx_ring(struct igb_ring *);
108static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 109static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 110static void igb_update_phy_info(unsigned long);
111static void igb_watchdog(unsigned long);
112static void igb_watchdog_task(struct work_struct *);
b1a436c3 113static netdev_tx_t igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
9d5c8243
AK		 114static struct net_device_stats *igb_get_stats(struct net_device *);
115static int igb_change_mtu(struct net_device *, int);
116static int igb_set_mac(struct net_device *, void *);
68d480c4 117static void igb_set_uta(struct igb_adapter *adapter);
9d5c8243
AK		 118static irqreturn_t igb_intr(int irq, void *);
119static irqreturn_t igb_intr_msi(int irq, void *);
120static irqreturn_t igb_msix_other(int irq, void *);
047e0030 121static irqreturn_t igb_msix_ring(int irq, void *);
421e02f0 122#ifdef CONFIG_IGB_DCA
047e0030 123static void igb_update_dca(struct igb_q_vector *);
fe4506b6 124static void igb_setup_dca(struct igb_adapter *);
421e02f0 125#endif /* CONFIG_IGB_DCA */
047e0030 126static bool igb_clean_tx_irq(struct igb_q_vector *);
661086df 127static int igb_poll(struct napi_struct *, int);
047e0030 128static bool igb_clean_rx_irq_adv(struct igb_q_vector *, int *, int);
9d5c8243
AK		 129static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
130static void igb_tx_timeout(struct net_device *);
131static void igb_reset_task(struct work_struct *);
132static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
133static void igb_vlan_rx_add_vid(struct net_device *, u16);
134static void igb_vlan_rx_kill_vid(struct net_device *, u16);
135static void igb_restore_vlan(struct igb_adapter *);
26ad9178 136static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
4ae196df
AD		 137static void igb_ping_all_vfs(struct igb_adapter *);
138static void igb_msg_task(struct igb_adapter *);
4ae196df 139static void igb_vmm_control(struct igb_adapter *);
f2ca0dbe 140static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
4ae196df 141static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
8151d294
WM		 142static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
143static int igb_ndo_set_vf_vlan(struct net_device *netdev,
144 int vf, u16 vlan, u8 qos);
145static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate);
146static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
147 struct ifla_vf_info *ivi);
9d5c8243 148
9d5c8243 149#ifdef CONFIG_PM
3fe7c4c9 150static int igb_suspend(struct pci_dev *, pm_message_t);
9d5c8243
AK		 151static int igb_resume(struct pci_dev *);
152#endif
153static void igb_shutdown(struct pci_dev *);
421e02f0 154#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 155static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
156static struct notifier_block dca_notifier = {
157 .notifier_call = igb_notify_dca,
158 .next = NULL,
159 .priority = 0
160};
161#endif
9d5c8243
AK		 162#ifdef CONFIG_NET_POLL_CONTROLLER
163/* for netdump / net console */
164static void igb_netpoll(struct net_device *);
165#endif
37680117 166#ifdef CONFIG_PCI_IOV
2a3abf6d
AD		 167static unsigned int max_vfs = 0;
168module_param(max_vfs, uint, 0);
169MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
170 "per physical function");
171#endif /* CONFIG_PCI_IOV */
172
9d5c8243
AK		 173static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
174 pci_channel_state_t);
175static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
176static void igb_io_resume(struct pci_dev *);
177
178static struct pci_error_handlers igb_err_handler = {
179 .error_detected = igb_io_error_detected,
180 .slot_reset = igb_io_slot_reset,
181 .resume = igb_io_resume,
182};
183
184
185static struct pci_driver igb_driver = {
186 .name = igb_driver_name,
187 .id_table = igb_pci_tbl,
188 .probe = igb_probe,
189 .remove = __devexit_p(igb_remove),
190#ifdef CONFIG_PM
191 /* Power Managment Hooks */
192 .suspend = igb_suspend,
193 .resume = igb_resume,
194#endif
195 .shutdown = igb_shutdown,
196 .err_handler = &igb_err_handler
197};
198
199MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
200MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
201MODULE_LICENSE("GPL");
202MODULE_VERSION(DRV_VERSION);
203
c97ec42a
TI		 204struct igb_reg_info {
205 u32 ofs;
206 char *name;
207};
208
209static const struct igb_reg_info igb_reg_info_tbl[] = {
210
211 /* General Registers */
212 {E1000_CTRL, "CTRL"},
213 {E1000_STATUS, "STATUS"},
214 {E1000_CTRL_EXT, "CTRL_EXT"},
215
216 /* Interrupt Registers */
217 {E1000_ICR, "ICR"},
218
219 /* RX Registers */
220 {E1000_RCTL, "RCTL"},
221 {E1000_RDLEN(0), "RDLEN"},
222 {E1000_RDH(0), "RDH"},
223 {E1000_RDT(0), "RDT"},
224 {E1000_RXDCTL(0), "RXDCTL"},
225 {E1000_RDBAL(0), "RDBAL"},
226 {E1000_RDBAH(0), "RDBAH"},
227
228 /* TX Registers */
229 {E1000_TCTL, "TCTL"},
230 {E1000_TDBAL(0), "TDBAL"},
231 {E1000_TDBAH(0), "TDBAH"},
232 {E1000_TDLEN(0), "TDLEN"},
233 {E1000_TDH(0), "TDH"},
234 {E1000_TDT(0), "TDT"},
235 {E1000_TXDCTL(0), "TXDCTL"},
236 {E1000_TDFH, "TDFH"},
237 {E1000_TDFT, "TDFT"},
238 {E1000_TDFHS, "TDFHS"},
239 {E1000_TDFPC, "TDFPC"},
240
241 /* List Terminator */
242 {}
243};
244
245/*
246 * igb_regdump - register printout routine
247 */
248static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
249{
250 int n = 0;
251 char rname[16];
252 u32 regs[8];
253
254 switch (reginfo->ofs) {
255 case E1000_RDLEN(0):
256 for (n = 0; n < 4; n++)
257 regs[n] = rd32(E1000_RDLEN(n));
258 break;
259 case E1000_RDH(0):
260 for (n = 0; n < 4; n++)
261 regs[n] = rd32(E1000_RDH(n));
262 break;
263 case E1000_RDT(0):
264 for (n = 0; n < 4; n++)
265 regs[n] = rd32(E1000_RDT(n));
266 break;
267 case E1000_RXDCTL(0):
268 for (n = 0; n < 4; n++)
269 regs[n] = rd32(E1000_RXDCTL(n));
270 break;
271 case E1000_RDBAL(0):
272 for (n = 0; n < 4; n++)
273 regs[n] = rd32(E1000_RDBAL(n));
274 break;
275 case E1000_RDBAH(0):
276 for (n = 0; n < 4; n++)
277 regs[n] = rd32(E1000_RDBAH(n));
278 break;
279 case E1000_TDBAL(0):
280 for (n = 0; n < 4; n++)
281 regs[n] = rd32(E1000_RDBAL(n));
282 break;
283 case E1000_TDBAH(0):
284 for (n = 0; n < 4; n++)
285 regs[n] = rd32(E1000_TDBAH(n));
286 break;
287 case E1000_TDLEN(0):
288 for (n = 0; n < 4; n++)
289 regs[n] = rd32(E1000_TDLEN(n));
290 break;
291 case E1000_TDH(0):
292 for (n = 0; n < 4; n++)
293 regs[n] = rd32(E1000_TDH(n));
294 break;
295 case E1000_TDT(0):
296 for (n = 0; n < 4; n++)
297 regs[n] = rd32(E1000_TDT(n));
298 break;
299 case E1000_TXDCTL(0):
300 for (n = 0; n < 4; n++)
301 regs[n] = rd32(E1000_TXDCTL(n));
302 break;
303 default:
304 printk(KERN_INFO "%-15s %08x\n",
305 reginfo->name, rd32(reginfo->ofs));
306 return;
307 }
308
309 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
310 printk(KERN_INFO "%-15s ", rname);
311 for (n = 0; n < 4; n++)
312 printk(KERN_CONT "%08x ", regs[n]);
313 printk(KERN_CONT "\n");
314}
315
316/*
317 * igb_dump - Print registers, tx-rings and rx-rings
318 */
319static void igb_dump(struct igb_adapter *adapter)
320{
321 struct net_device *netdev = adapter->netdev;
322 struct e1000_hw *hw = &adapter->hw;
323 struct igb_reg_info *reginfo;
324 int n = 0;
325 struct igb_ring *tx_ring;
326 union e1000_adv_tx_desc *tx_desc;
327 struct my_u0 { u64 a; u64 b; } *u0;
328 struct igb_buffer *buffer_info;
329 struct igb_ring *rx_ring;
330 union e1000_adv_rx_desc *rx_desc;
331 u32 staterr;
332 int i = 0;
333
334 if (!netif_msg_hw(adapter))
335 return;
336
337 /* Print netdevice Info */
338 if (netdev) {
339 dev_info(&adapter->pdev->dev, "Net device Info\n");
340 printk(KERN_INFO "Device Name state "
341 "trans_start last_rx\n");
342 printk(KERN_INFO "%-15s %016lX %016lX %016lX\n",
343 netdev->name,
344 netdev->state,
345 netdev->trans_start,
346 netdev->last_rx);
347 }
348
349 /* Print Registers */
350 dev_info(&adapter->pdev->dev, "Register Dump\n");
351 printk(KERN_INFO " Register Name Value\n");
352 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
353 reginfo->name; reginfo++) {
354 igb_regdump(hw, reginfo);
355 }
356
357 /* Print TX Ring Summary */
358 if (!netdev || !netif_running(netdev))
359 goto exit;
360
361 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
362 printk(KERN_INFO "Queue [NTU] [NTC] [bi(ntc)->dma ]"
363 " leng ntw timestamp\n");
364 for (n = 0; n < adapter->num_tx_queues; n++) {
365 tx_ring = adapter->tx_ring[n];
366 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean];
367 printk(KERN_INFO " %5d %5X %5X %016llX %04X %3X %016llX\n",
368 n, tx_ring->next_to_use, tx_ring->next_to_clean,
369 (u64)buffer_info->dma,
370 buffer_info->length,
371 buffer_info->next_to_watch,
372 (u64)buffer_info->time_stamp);
373 }
374
375 /* Print TX Rings */
376 if (!netif_msg_tx_done(adapter))
377 goto rx_ring_summary;
378
379 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
380
381 /* Transmit Descriptor Formats
382 *
383 * Advanced Transmit Descriptor
384 * +--------------------------------------------------------------+
385 * 0 | Buffer Address [63:0] |
386 * +--------------------------------------------------------------+
387 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
388 * +--------------------------------------------------------------+
389 * 63 46 45 40 39 38 36 35 32 31 24 15 0
390 */
391
392 for (n = 0; n < adapter->num_tx_queues; n++) {
393 tx_ring = adapter->tx_ring[n];
394 printk(KERN_INFO "------------------------------------\n");
395 printk(KERN_INFO "TX QUEUE INDEX = %d\n", tx_ring->queue_index);
396 printk(KERN_INFO "------------------------------------\n");
397 printk(KERN_INFO "T [desc] [address 63:0 ] "
398 "[PlPOCIStDDM Ln] [bi->dma ] "
399 "leng ntw timestamp bi->skb\n");
400
401 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
402 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
403 buffer_info = &tx_ring->buffer_info[i];
404 u0 = (struct my_u0 *)tx_desc;
405 printk(KERN_INFO "T [0x%03X] %016llX %016llX %016llX"
406 " %04X %3X %016llX %p", i,
407 le64_to_cpu(u0->a),
408 le64_to_cpu(u0->b),
409 (u64)buffer_info->dma,
410 buffer_info->length,
411 buffer_info->next_to_watch,
412 (u64)buffer_info->time_stamp,
413 buffer_info->skb);
414 if (i == tx_ring->next_to_use &&
415 i == tx_ring->next_to_clean)
416 printk(KERN_CONT " NTC/U\n");
417 else if (i == tx_ring->next_to_use)
418 printk(KERN_CONT " NTU\n");
419 else if (i == tx_ring->next_to_clean)
420 printk(KERN_CONT " NTC\n");
421 else
422 printk(KERN_CONT "\n");
423
424 if (netif_msg_pktdata(adapter) && buffer_info->dma != 0)
425 print_hex_dump(KERN_INFO, "",
426 DUMP_PREFIX_ADDRESS,
427 16, 1, phys_to_virt(buffer_info->dma),
428 buffer_info->length, true);
429 }
430 }
431
432 /* Print RX Rings Summary */
433rx_ring_summary:
434 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
435 printk(KERN_INFO "Queue [NTU] [NTC]\n");
436 for (n = 0; n < adapter->num_rx_queues; n++) {
437 rx_ring = adapter->rx_ring[n];
438 printk(KERN_INFO " %5d %5X %5X\n", n,
439 rx_ring->next_to_use, rx_ring->next_to_clean);
440 }
441
442 /* Print RX Rings */
443 if (!netif_msg_rx_status(adapter))
444 goto exit;
445
446 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
447
448 /* Advanced Receive Descriptor (Read) Format
449 * 63 1 0
450 * +-----------------------------------------------------+
451 * 0 | Packet Buffer Address [63:1] |A0/NSE|
452 * +----------------------------------------------+------+
453 * 8 | Header Buffer Address [63:1] | DD |
454 * +-----------------------------------------------------+
455 *
456 *
457 * Advanced Receive Descriptor (Write-Back) Format
458 *
459 * 63 48 47 32 31 30 21 20 17 16 4 3 0
460 * +------------------------------------------------------+
461 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
462 * | Checksum Ident | | | | Type | Type |
463 * +------------------------------------------------------+
464 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
465 * +------------------------------------------------------+
466 * 63 48 47 32 31 20 19 0
467 */
468
469 for (n = 0; n < adapter->num_rx_queues; n++) {
470 rx_ring = adapter->rx_ring[n];
471 printk(KERN_INFO "------------------------------------\n");
472 printk(KERN_INFO "RX QUEUE INDEX = %d\n", rx_ring->queue_index);
473 printk(KERN_INFO "------------------------------------\n");
474 printk(KERN_INFO "R [desc] [ PktBuf A0] "
475 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
476 "<-- Adv Rx Read format\n");
477 printk(KERN_INFO "RWB[desc] [PcsmIpSHl PtRs] "
478 "[vl er S cks ln] ---------------- [bi->skb] "
479 "<-- Adv Rx Write-Back format\n");
480
481 for (i = 0; i < rx_ring->count; i++) {
482 buffer_info = &rx_ring->buffer_info[i];
483 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
484 u0 = (struct my_u0 *)rx_desc;
485 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
486 if (staterr & E1000_RXD_STAT_DD) {
487 /* Descriptor Done */
488 printk(KERN_INFO "RWB[0x%03X] %016llX "
489 "%016llX ---------------- %p", i,
490 le64_to_cpu(u0->a),
491 le64_to_cpu(u0->b),
492 buffer_info->skb);
493 } else {
494 printk(KERN_INFO "R [0x%03X] %016llX "
495 "%016llX %016llX %p", i,
496 le64_to_cpu(u0->a),
497 le64_to_cpu(u0->b),
498 (u64)buffer_info->dma,
499 buffer_info->skb);
500
501 if (netif_msg_pktdata(adapter)) {
502 print_hex_dump(KERN_INFO, "",
503 DUMP_PREFIX_ADDRESS,
504 16, 1,
505 phys_to_virt(buffer_info->dma),
506 rx_ring->rx_buffer_len, true);
507 if (rx_ring->rx_buffer_len
508 < IGB_RXBUFFER_1024)
509 print_hex_dump(KERN_INFO, "",
510 DUMP_PREFIX_ADDRESS,
511 16, 1,
512 phys_to_virt(
513 buffer_info->page_dma +
514 buffer_info->page_offset),
515 PAGE_SIZE/2, true);
516 }
517 }
518
519 if (i == rx_ring->next_to_use)
520 printk(KERN_CONT " NTU\n");
521 else if (i == rx_ring->next_to_clean)
522 printk(KERN_CONT " NTC\n");
523 else
524 printk(KERN_CONT "\n");
525
526 }
527 }
528
529exit:
530 return;
531}
532
533
38c845c7
PO		 534/**
535 * igb_read_clock - read raw cycle counter (to be used by time counter)
536 */
537static cycle_t igb_read_clock(const struct cyclecounter *tc)
538{
539 struct igb_adapter *adapter =
540 container_of(tc, struct igb_adapter, cycles);
541 struct e1000_hw *hw = &adapter->hw;
c5b9bd5e
AD		 542 u64 stamp = 0;
543 int shift = 0;
38c845c7 544
55cac248
AD		 545 /*
546 * The timestamp latches on lowest register read. For the 82580
547 * the lowest register is SYSTIMR instead of SYSTIML. However we never
548 * adjusted TIMINCA so SYSTIMR will just read as all 0s so ignore it.
549 */
550 if (hw->mac.type == e1000_82580) {
551 stamp = rd32(E1000_SYSTIMR) >> 8;
552 shift = IGB_82580_TSYNC_SHIFT;
553 }
554
c5b9bd5e
AD		 555 stamp |= (u64)rd32(E1000_SYSTIML) << shift;
556 stamp |= (u64)rd32(E1000_SYSTIMH) << (shift + 32);
38c845c7
PO		 557 return stamp;
558}
559
9d5c8243 560/**
c041076a 561 * igb_get_hw_dev - return device
9d5c8243
AK		 562 * used by hardware layer to print debugging information
563 **/
c041076a 564struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
9d5c8243
AK		 565{
566 struct igb_adapter *adapter = hw->back;
c041076a 567 return adapter->netdev;
9d5c8243 568}
38c845c7 569
9d5c8243
AK		 570/**
571 * igb_init_module - Driver Registration Routine
572 *
573 * igb_init_module is the first routine called when the driver is
574 * loaded. All it does is register with the PCI subsystem.
575 **/
576static int __init igb_init_module(void)
577{
578 int ret;
579 printk(KERN_INFO "%s - version %s\n",
580 igb_driver_string, igb_driver_version);
581
582 printk(KERN_INFO "%s\n", igb_copyright);
583
421e02f0 584#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 585 dca_register_notify(&dca_notifier);
586#endif
bbd98fe4 587 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 588 return ret;
589}
590
591module_init(igb_init_module);
592
593/**
594 * igb_exit_module - Driver Exit Cleanup Routine
595 *
596 * igb_exit_module is called just before the driver is removed
597 * from memory.
598 **/
599static void __exit igb_exit_module(void)
600{
421e02f0 601#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 602 dca_unregister_notify(&dca_notifier);
603#endif
9d5c8243
AK		 604 pci_unregister_driver(&igb_driver);
605}
606
607module_exit(igb_exit_module);
608
26bc19ec
AD		 609#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
610/**
611 * igb_cache_ring_register - Descriptor ring to register mapping
612 * @adapter: board private structure to initialize
613 *
614 * Once we know the feature-set enabled for the device, we'll cache
615 * the register offset the descriptor ring is assigned to.
616 **/
617static void igb_cache_ring_register(struct igb_adapter *adapter)
618{
ee1b9f06 619 int i = 0, j = 0;
047e0030 620 u32 rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 621
622 switch (adapter->hw.mac.type) {
623 case e1000_82576:
624 /* The queues are allocated for virtualization such that VF 0
625 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
626 * In order to avoid collision we start at the first free queue
627 * and continue consuming queues in the same sequence
628 */
ee1b9f06 629 if (adapter->vfs_allocated_count) {
a99955fc 630 for (; i < adapter->rss_queues; i++)
3025a446
AD		 631 adapter->rx_ring[i]->reg_idx = rbase_offset +
632 Q_IDX_82576(i);
a99955fc 633 for (; j < adapter->rss_queues; j++)
3025a446
AD		 634 adapter->tx_ring[j]->reg_idx = rbase_offset +
635 Q_IDX_82576(j);
ee1b9f06 636 }
26bc19ec 637 case e1000_82575:
55cac248 638 case e1000_82580:
d2ba2ed8 639 case e1000_i350:
26bc19ec 640 default:
ee1b9f06 641 for (; i < adapter->num_rx_queues; i++)
3025a446 642 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
ee1b9f06 643 for (; j < adapter->num_tx_queues; j++)
3025a446 644 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
26bc19ec
AD		 645 break;
646 }
647}
648
047e0030
AD		 649static void igb_free_queues(struct igb_adapter *adapter)
650{
3025a446 651 int i;
047e0030 652
3025a446
AD		 653 for (i = 0; i < adapter->num_tx_queues; i++) {
654 kfree(adapter->tx_ring[i]);
655 adapter->tx_ring[i] = NULL;
656 }
657 for (i = 0; i < adapter->num_rx_queues; i++) {
658 kfree(adapter->rx_ring[i]);
659 adapter->rx_ring[i] = NULL;
660 }
047e0030
AD		 661 adapter->num_rx_queues = 0;
662 adapter->num_tx_queues = 0;
663}
664
9d5c8243
AK		 665/**
666 * igb_alloc_queues - Allocate memory for all rings
667 * @adapter: board private structure to initialize
668 *
669 * We allocate one ring per queue at run-time since we don't know the
670 * number of queues at compile-time.
671 **/
672static int igb_alloc_queues(struct igb_adapter *adapter)
673{
3025a446 674 struct igb_ring *ring;
9d5c8243
AK		 675 int i;
676
661086df 677 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446
AD		 678 ring = kzalloc(sizeof(struct igb_ring), GFP_KERNEL);
679 if (!ring)
680 goto err;
68fd9910 681 ring->count = adapter->tx_ring_count;
661086df 682 ring->queue_index = i;
59d71989 683 ring->dev = &adapter->pdev->dev;
e694e964 684 ring->netdev = adapter->netdev;
85ad76b2
AD		 685 /* For 82575, context index must be unique per ring. */
686 if (adapter->hw.mac.type == e1000_82575)
687 ring->flags = IGB_RING_FLAG_TX_CTX_IDX;
3025a446 688 adapter->tx_ring[i] = ring;
661086df 689 }
85ad76b2 690
9d5c8243 691 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446
AD		 692 ring = kzalloc(sizeof(struct igb_ring), GFP_KERNEL);
693 if (!ring)
694 goto err;
68fd9910 695 ring->count = adapter->rx_ring_count;
844290e5 696 ring->queue_index = i;
59d71989 697 ring->dev = &adapter->pdev->dev;
e694e964 698 ring->netdev = adapter->netdev;
4c844851 699 ring->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
85ad76b2
AD		 700 ring->flags = IGB_RING_FLAG_RX_CSUM; /* enable rx checksum */
701 /* set flag indicating ring supports SCTP checksum offload */
702 if (adapter->hw.mac.type >= e1000_82576)
703 ring->flags |= IGB_RING_FLAG_RX_SCTP_CSUM;
3025a446 704 adapter->rx_ring[i] = ring;
9d5c8243 705 }
26bc19ec
AD		 706
707 igb_cache_ring_register(adapter);
9d5c8243 708
047e0030 709 return 0;
a88f10ec 710
047e0030
AD		 711err:
712 igb_free_queues(adapter);
d1a8c9e1 713
047e0030 714 return -ENOMEM;
a88f10ec
AD		 715}
716
9d5c8243 717#define IGB_N0_QUEUE -1
047e0030 718static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
9d5c8243
AK		 719{
720 u32 msixbm = 0;
047e0030 721 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 722 struct e1000_hw *hw = &adapter->hw;
2d064c06 723 u32 ivar, index;
047e0030
AD		 724 int rx_queue = IGB_N0_QUEUE;
725 int tx_queue = IGB_N0_QUEUE;
726
727 if (q_vector->rx_ring)
728 rx_queue = q_vector->rx_ring->reg_idx;
729 if (q_vector->tx_ring)
730 tx_queue = q_vector->tx_ring->reg_idx;
2d064c06
AD		 731
732 switch (hw->mac.type) {
733 case e1000_82575:
9d5c8243
AK		 734 /* The 82575 assigns vectors using a bitmask, which matches the
735 bitmask for the EICR/EIMS/EIMC registers. To assign one
736 or more queues to a vector, we write the appropriate bits
737 into the MSIXBM register for that vector. */
047e0030 738 if (rx_queue > IGB_N0_QUEUE)
9d5c8243 739 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
047e0030 740 if (tx_queue > IGB_N0_QUEUE)
9d5c8243 741 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
feeb2721
AD		 742 if (!adapter->msix_entries && msix_vector == 0)
743 msixbm |= E1000_EIMS_OTHER;
9d5c8243 744 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
047e0030 745 q_vector->eims_value = msixbm;
2d064c06
AD		 746 break;
747 case e1000_82576:
26bc19ec 748 /* 82576 uses a table-based method for assigning vectors.
2d064c06
AD		 749 Each queue has a single entry in the table to which we write
750 a vector number along with a "valid" bit. Sadly, the layout
751 of the table is somewhat counterintuitive. */
752 if (rx_queue > IGB_N0_QUEUE) {
047e0030 753 index = (rx_queue & 0x7);
2d064c06 754 ivar = array_rd32(E1000_IVAR0, index);
047e0030 755 if (rx_queue < 8) {
26bc19ec
AD		 756 /* vector goes into low byte of register */
757 ivar = ivar & 0xFFFFFF00;
758 ivar |= msix_vector | E1000_IVAR_VALID;
047e0030
AD		 759 } else {
760 /* vector goes into third byte of register */
761 ivar = ivar & 0xFF00FFFF;
762 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
2d064c06 763 }
2d064c06
AD		 764 array_wr32(E1000_IVAR0, index, ivar);
765 }
766 if (tx_queue > IGB_N0_QUEUE) {
047e0030 767 index = (tx_queue & 0x7);
2d064c06 768 ivar = array_rd32(E1000_IVAR0, index);
047e0030 769 if (tx_queue < 8) {
26bc19ec
AD		 770 /* vector goes into second byte of register */
771 ivar = ivar & 0xFFFF00FF;
772 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
047e0030
AD		 773 } else {
774 /* vector goes into high byte of register */
775 ivar = ivar & 0x00FFFFFF;
776 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
2d064c06 777 }
2d064c06
AD		 778 array_wr32(E1000_IVAR0, index, ivar);
779 }
047e0030 780 q_vector->eims_value = 1 << msix_vector;
2d064c06 781 break;
55cac248 782 case e1000_82580:
d2ba2ed8 783 case e1000_i350:
55cac248
AD		 784 /* 82580 uses the same table-based approach as 82576 but has fewer
785 entries as a result we carry over for queues greater than 4. */
786 if (rx_queue > IGB_N0_QUEUE) {
787 index = (rx_queue >> 1);
788 ivar = array_rd32(E1000_IVAR0, index);
789 if (rx_queue & 0x1) {
790 /* vector goes into third byte of register */
791 ivar = ivar & 0xFF00FFFF;
792 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
793 } else {
794 /* vector goes into low byte of register */
795 ivar = ivar & 0xFFFFFF00;
796 ivar |= msix_vector | E1000_IVAR_VALID;
797 }
798 array_wr32(E1000_IVAR0, index, ivar);
799 }
800 if (tx_queue > IGB_N0_QUEUE) {
801 index = (tx_queue >> 1);
802 ivar = array_rd32(E1000_IVAR0, index);
803 if (tx_queue & 0x1) {
804 /* vector goes into high byte of register */
805 ivar = ivar & 0x00FFFFFF;
806 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
807 } else {
808 /* vector goes into second byte of register */
809 ivar = ivar & 0xFFFF00FF;
810 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
811 }
812 array_wr32(E1000_IVAR0, index, ivar);
813 }
814 q_vector->eims_value = 1 << msix_vector;
815 break;
2d064c06
AD		 816 default:
817 BUG();
818 break;
819 }
26b39276
AD		 820
821 /* add q_vector eims value to global eims_enable_mask */
822 adapter->eims_enable_mask |= q_vector->eims_value;
823
824 /* configure q_vector to set itr on first interrupt */
825 q_vector->set_itr = 1;
9d5c8243
AK		 826}
827
828/**
829 * igb_configure_msix - Configure MSI-X hardware
830 *
831 * igb_configure_msix sets up the hardware to properly
832 * generate MSI-X interrupts.
833 **/
834static void igb_configure_msix(struct igb_adapter *adapter)
835{
836 u32 tmp;
837 int i, vector = 0;
838 struct e1000_hw *hw = &adapter->hw;
839
840 adapter->eims_enable_mask = 0;
9d5c8243
AK		 841
842 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 843 switch (hw->mac.type) {
844 case e1000_82575:
9d5c8243
AK		 845 tmp = rd32(E1000_CTRL_EXT);
846 /* enable MSI-X PBA support*/
847 tmp |= E1000_CTRL_EXT_PBA_CLR;
848
849 /* Auto-Mask interrupts upon ICR read. */
850 tmp |= E1000_CTRL_EXT_EIAME;
851 tmp |= E1000_CTRL_EXT_IRCA;
852
853 wr32(E1000_CTRL_EXT, tmp);
047e0030
AD		 854
855 /* enable msix_other interrupt */
856 array_wr32(E1000_MSIXBM(0), vector++,
857 E1000_EIMS_OTHER);
844290e5 858 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 859
2d064c06
AD		 860 break;
861
862 case e1000_82576:
55cac248 863 case e1000_82580:
d2ba2ed8 864 case e1000_i350:
047e0030
AD		 865 /* Turn on MSI-X capability first, or our settings
866 * won't stick. And it will take days to debug. */
867 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
868 E1000_GPIE_PBA | E1000_GPIE_EIAME |
869 E1000_GPIE_NSICR);
870
871 /* enable msix_other interrupt */
872 adapter->eims_other = 1 << vector;
2d064c06 873 tmp = (vector++ | E1000_IVAR_VALID) << 8;
2d064c06 874
047e0030 875 wr32(E1000_IVAR_MISC, tmp);
2d064c06
AD		 876 break;
877 default:
878 /* do nothing, since nothing else supports MSI-X */
879 break;
880 } /* switch (hw->mac.type) */
047e0030
AD		 881
882 adapter->eims_enable_mask |= adapter->eims_other;
883
26b39276
AD		 884 for (i = 0; i < adapter->num_q_vectors; i++)
885 igb_assign_vector(adapter->q_vector[i], vector++);
047e0030 886
9d5c8243
AK		 887 wrfl();
888}
889
890/**
891 * igb_request_msix - Initialize MSI-X interrupts
892 *
893 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
894 * kernel.
895 **/
896static int igb_request_msix(struct igb_adapter *adapter)
897{
898 struct net_device *netdev = adapter->netdev;
047e0030 899 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 900 int i, err = 0, vector = 0;
901
047e0030 902 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 903 igb_msix_other, 0, netdev->name, adapter);
047e0030
AD		 904 if (err)
905 goto out;
906 vector++;
907
908 for (i = 0; i < adapter->num_q_vectors; i++) {
909 struct igb_q_vector *q_vector = adapter->q_vector[i];
910
911 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
912
913 if (q_vector->rx_ring && q_vector->tx_ring)
914 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
915 q_vector->rx_ring->queue_index);
916 else if (q_vector->tx_ring)
917 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
918 q_vector->tx_ring->queue_index);
919 else if (q_vector->rx_ring)
920 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
921 q_vector->rx_ring->queue_index);
9d5c8243 922 else
047e0030
AD		 923 sprintf(q_vector->name, "%s-unused", netdev->name);
924
9d5c8243 925 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 926 igb_msix_ring, 0, q_vector->name,
047e0030 927 q_vector);
9d5c8243
AK		 928 if (err)
929 goto out;
9d5c8243
AK		 930 vector++;
931 }
932
9d5c8243
AK		 933 igb_configure_msix(adapter);
934 return 0;
935out:
936 return err;
937}
938
939static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
940{
941 if (adapter->msix_entries) {
942 pci_disable_msix(adapter->pdev);
943 kfree(adapter->msix_entries);
944 adapter->msix_entries = NULL;
047e0030 945 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243 946 pci_disable_msi(adapter->pdev);
047e0030 947 }
9d5c8243
AK		 948}
949
047e0030
AD		 950/**
951 * igb_free_q_vectors - Free memory allocated for interrupt vectors
952 * @adapter: board private structure to initialize
953 *
954 * This function frees the memory allocated to the q_vectors. In addition if
955 * NAPI is enabled it will delete any references to the NAPI struct prior
956 * to freeing the q_vector.
957 **/
958static void igb_free_q_vectors(struct igb_adapter *adapter)
959{
960 int v_idx;
961
962 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
963 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
964 adapter->q_vector[v_idx] = NULL;
fe0592b4
NN		 965 if (!q_vector)
966 continue;
047e0030
AD		 967 netif_napi_del(&q_vector->napi);
968 kfree(q_vector);
969 }
970 adapter->num_q_vectors = 0;
971}
972
973/**
974 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
975 *
976 * This function resets the device so that it has 0 rx queues, tx queues, and
977 * MSI-X interrupts allocated.
978 */
979static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
980{
981 igb_free_queues(adapter);
982 igb_free_q_vectors(adapter);
983 igb_reset_interrupt_capability(adapter);
984}
9d5c8243
AK		 985
986/**
987 * igb_set_interrupt_capability - set MSI or MSI-X if supported
988 *
989 * Attempt to configure interrupts using the best available
990 * capabilities of the hardware and kernel.
991 **/
992static void igb_set_interrupt_capability(struct igb_adapter *adapter)
993{
994 int err;
995 int numvecs, i;
996
83b7180d 997 /* Number of supported queues. */
a99955fc
AD		 998 adapter->num_rx_queues = adapter->rss_queues;
999 adapter->num_tx_queues = adapter->rss_queues;
83b7180d 1000
047e0030
AD		 1001 /* start with one vector for every rx queue */
1002 numvecs = adapter->num_rx_queues;
1003
3ad2f3fb 1004 /* if tx handler is separate add 1 for every tx queue */
a99955fc
AD		 1005 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1006 numvecs += adapter->num_tx_queues;
047e0030
AD		 1007
1008 /* store the number of vectors reserved for queues */
1009 adapter->num_q_vectors = numvecs;
1010
1011 /* add 1 vector for link status interrupts */
1012 numvecs++;
9d5c8243
AK		 1013 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
1014 GFP_KERNEL);
1015 if (!adapter->msix_entries)
1016 goto msi_only;
1017
1018 for (i = 0; i < numvecs; i++)
1019 adapter->msix_entries[i].entry = i;
1020
1021 err = pci_enable_msix(adapter->pdev,
1022 adapter->msix_entries,
1023 numvecs);
1024 if (err == 0)
34a20e89 1025 goto out;
9d5c8243
AK		 1026
1027 igb_reset_interrupt_capability(adapter);
1028
1029 /* If we can't do MSI-X, try MSI */
1030msi_only:
2a3abf6d
AD		 1031#ifdef CONFIG_PCI_IOV
1032 /* disable SR-IOV for non MSI-X configurations */
1033 if (adapter->vf_data) {
1034 struct e1000_hw *hw = &adapter->hw;
1035 /* disable iov and allow time for transactions to clear */
1036 pci_disable_sriov(adapter->pdev);
1037 msleep(500);
1038
1039 kfree(adapter->vf_data);
1040 adapter->vf_data = NULL;
1041 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1042 msleep(100);
1043 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1044 }
1045#endif
4fc82adf 1046 adapter->vfs_allocated_count = 0;
a99955fc 1047 adapter->rss_queues = 1;
4fc82adf 1048 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
9d5c8243 1049 adapter->num_rx_queues = 1;
661086df 1050 adapter->num_tx_queues = 1;
047e0030 1051 adapter->num_q_vectors = 1;
9d5c8243 1052 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 1053 adapter->flags |= IGB_FLAG_HAS_MSI;
34a20e89 1054out:
661086df 1055 /* Notify the stack of the (possibly) reduced Tx Queue count. */
fd2ea0a7 1056 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
9d5c8243
AK		 1057 return;
1058}
1059
047e0030
AD		 1060/**
1061 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1062 * @adapter: board private structure to initialize
1063 *
1064 * We allocate one q_vector per queue interrupt. If allocation fails we
1065 * return -ENOMEM.
1066 **/
1067static int igb_alloc_q_vectors(struct igb_adapter *adapter)
1068{
1069 struct igb_q_vector *q_vector;
1070 struct e1000_hw *hw = &adapter->hw;
1071 int v_idx;
1072
1073 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
1074 q_vector = kzalloc(sizeof(struct igb_q_vector), GFP_KERNEL);
1075 if (!q_vector)
1076 goto err_out;
1077 q_vector->adapter = adapter;
047e0030
AD		 1078 q_vector->itr_register = hw->hw_addr + E1000_EITR(0);
1079 q_vector->itr_val = IGB_START_ITR;
047e0030
AD		 1080 netif_napi_add(adapter->netdev, &q_vector->napi, igb_poll, 64);
1081 adapter->q_vector[v_idx] = q_vector;
1082 }
1083 return 0;
1084
1085err_out:
fe0592b4 1086 igb_free_q_vectors(adapter);
047e0030
AD		 1087 return -ENOMEM;
1088}
1089
1090static void igb_map_rx_ring_to_vector(struct igb_adapter *adapter,
1091 int ring_idx, int v_idx)
1092{
3025a446 1093 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
047e0030 1094
3025a446 1095 q_vector->rx_ring = adapter->rx_ring[ring_idx];
047e0030 1096 q_vector->rx_ring->q_vector = q_vector;
4fc82adf
AD		 1097 q_vector->itr_val = adapter->rx_itr_setting;
1098 if (q_vector->itr_val && q_vector->itr_val <= 3)
1099 q_vector->itr_val = IGB_START_ITR;
047e0030
AD		 1100}
1101
1102static void igb_map_tx_ring_to_vector(struct igb_adapter *adapter,
1103 int ring_idx, int v_idx)
1104{
3025a446 1105 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
047e0030 1106
3025a446 1107 q_vector->tx_ring = adapter->tx_ring[ring_idx];
047e0030 1108 q_vector->tx_ring->q_vector = q_vector;
4fc82adf
AD		 1109 q_vector->itr_val = adapter->tx_itr_setting;
1110 if (q_vector->itr_val && q_vector->itr_val <= 3)
1111 q_vector->itr_val = IGB_START_ITR;
047e0030
AD		 1112}
1113
1114/**
1115 * igb_map_ring_to_vector - maps allocated queues to vectors
1116 *
1117 * This function maps the recently allocated queues to vectors.
1118 **/
1119static int igb_map_ring_to_vector(struct igb_adapter *adapter)
1120{
1121 int i;
1122 int v_idx = 0;
1123
1124 if ((adapter->num_q_vectors < adapter->num_rx_queues) ||
1125 (adapter->num_q_vectors < adapter->num_tx_queues))
1126 return -ENOMEM;
1127
1128 if (adapter->num_q_vectors >=
1129 (adapter->num_rx_queues + adapter->num_tx_queues)) {
1130 for (i = 0; i < adapter->num_rx_queues; i++)
1131 igb_map_rx_ring_to_vector(adapter, i, v_idx++);
1132 for (i = 0; i < adapter->num_tx_queues; i++)
1133 igb_map_tx_ring_to_vector(adapter, i, v_idx++);
1134 } else {
1135 for (i = 0; i < adapter->num_rx_queues; i++) {
1136 if (i < adapter->num_tx_queues)
1137 igb_map_tx_ring_to_vector(adapter, i, v_idx);
1138 igb_map_rx_ring_to_vector(adapter, i, v_idx++);
1139 }
1140 for (; i < adapter->num_tx_queues; i++)
1141 igb_map_tx_ring_to_vector(adapter, i, v_idx++);
1142 }
1143 return 0;
1144}
1145
1146/**
1147 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1148 *
1149 * This function initializes the interrupts and allocates all of the queues.
1150 **/
1151static int igb_init_interrupt_scheme(struct igb_adapter *adapter)
1152{
1153 struct pci_dev *pdev = adapter->pdev;
1154 int err;
1155
1156 igb_set_interrupt_capability(adapter);
1157
1158 err = igb_alloc_q_vectors(adapter);
1159 if (err) {
1160 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1161 goto err_alloc_q_vectors;
1162 }
1163
1164 err = igb_alloc_queues(adapter);
1165 if (err) {
1166 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1167 goto err_alloc_queues;
1168 }
1169
1170 err = igb_map_ring_to_vector(adapter);
1171 if (err) {
1172 dev_err(&pdev->dev, "Invalid q_vector to ring mapping\n");
1173 goto err_map_queues;
1174 }
1175
1176
1177 return 0;
1178err_map_queues:
1179 igb_free_queues(adapter);
1180err_alloc_queues:
1181 igb_free_q_vectors(adapter);
1182err_alloc_q_vectors:
1183 igb_reset_interrupt_capability(adapter);
1184 return err;
1185}
1186
9d5c8243
AK		 1187/**
1188 * igb_request_irq - initialize interrupts
1189 *
1190 * Attempts to configure interrupts using the best available
1191 * capabilities of the hardware and kernel.
1192 **/
1193static int igb_request_irq(struct igb_adapter *adapter)
1194{
1195 struct net_device *netdev = adapter->netdev;
047e0030 1196 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 1197 int err = 0;
1198
1199 if (adapter->msix_entries) {
1200 err = igb_request_msix(adapter);
844290e5 1201 if (!err)
9d5c8243 1202 goto request_done;
9d5c8243 1203 /* fall back to MSI */
047e0030 1204 igb_clear_interrupt_scheme(adapter);
9d5c8243 1205 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 1206 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1207 igb_free_all_tx_resources(adapter);
1208 igb_free_all_rx_resources(adapter);
047e0030 1209 adapter->num_tx_queues = 1;
9d5c8243 1210 adapter->num_rx_queues = 1;
047e0030
AD		 1211 adapter->num_q_vectors = 1;
1212 err = igb_alloc_q_vectors(adapter);
1213 if (err) {
1214 dev_err(&pdev->dev,
1215 "Unable to allocate memory for vectors\n");
1216 goto request_done;
1217 }
1218 err = igb_alloc_queues(adapter);
1219 if (err) {
1220 dev_err(&pdev->dev,
1221 "Unable to allocate memory for queues\n");
1222 igb_free_q_vectors(adapter);
1223 goto request_done;
1224 }
1225 igb_setup_all_tx_resources(adapter);
1226 igb_setup_all_rx_resources(adapter);
844290e5 1227 } else {
feeb2721 1228 igb_assign_vector(adapter->q_vector[0], 0);
9d5c8243 1229 }
844290e5 1230
7dfc16fa 1231 if (adapter->flags & IGB_FLAG_HAS_MSI) {
a0607fd3 1232 err = request_irq(adapter->pdev->irq, igb_intr_msi, 0,
047e0030 1233 netdev->name, adapter);
9d5c8243
AK		 1234 if (!err)
1235 goto request_done;
047e0030 1236
9d5c8243
AK		 1237 /* fall back to legacy interrupts */
1238 igb_reset_interrupt_capability(adapter);
7dfc16fa 1239 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1240 }
1241
a0607fd3 1242 err = request_irq(adapter->pdev->irq, igb_intr, IRQF_SHARED,
047e0030 1243 netdev->name, adapter);
9d5c8243 1244
6cb5e577 1245 if (err)
9d5c8243
AK		 1246 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
1247 err);
9d5c8243
AK		 1248
1249request_done:
1250 return err;
1251}
1252
1253static void igb_free_irq(struct igb_adapter *adapter)
1254{
9d5c8243
AK		 1255 if (adapter->msix_entries) {
1256 int vector = 0, i;
1257
047e0030 1258 free_irq(adapter->msix_entries[vector++].vector, adapter);
9d5c8243 1259
047e0030
AD		 1260 for (i = 0; i < adapter->num_q_vectors; i++) {
1261 struct igb_q_vector *q_vector = adapter->q_vector[i];
1262 free_irq(adapter->msix_entries[vector++].vector,
1263 q_vector);
1264 }
1265 } else {
1266 free_irq(adapter->pdev->irq, adapter);
9d5c8243 1267 }
9d5c8243
AK		 1268}
1269
1270/**
1271 * igb_irq_disable - Mask off interrupt generation on the NIC
1272 * @adapter: board private structure
1273 **/
1274static void igb_irq_disable(struct igb_adapter *adapter)
1275{
1276 struct e1000_hw *hw = &adapter->hw;
1277
25568a53
AD		 1278 /*
1279 * we need to be careful when disabling interrupts. The VFs are also
1280 * mapped into these registers and so clearing the bits can cause
1281 * issues on the VF drivers so we only need to clear what we set
1282 */
9d5c8243 1283 if (adapter->msix_entries) {
2dfd1212
AD		 1284 u32 regval = rd32(E1000_EIAM);
1285 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1286 wr32(E1000_EIMC, adapter->eims_enable_mask);
1287 regval = rd32(E1000_EIAC);
1288 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 1289 }
844290e5
PW		 1290
1291 wr32(E1000_IAM, 0);
9d5c8243
AK		 1292 wr32(E1000_IMC, ~0);
1293 wrfl();
1294 synchronize_irq(adapter->pdev->irq);
1295}
1296
1297/**
1298 * igb_irq_enable - Enable default interrupt generation settings
1299 * @adapter: board private structure
1300 **/
1301static void igb_irq_enable(struct igb_adapter *adapter)
1302{
1303 struct e1000_hw *hw = &adapter->hw;
1304
1305 if (adapter->msix_entries) {
25568a53 1306 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC;
2dfd1212
AD		 1307 u32 regval = rd32(E1000_EIAC);
1308 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1309 regval = rd32(E1000_EIAM);
1310 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 1311 wr32(E1000_EIMS, adapter->eims_enable_mask);
25568a53 1312 if (adapter->vfs_allocated_count) {
4ae196df 1313 wr32(E1000_MBVFIMR, 0xFF);
25568a53
AD		 1314 ims |= E1000_IMS_VMMB;
1315 }
55cac248
AD		 1316 if (adapter->hw.mac.type == e1000_82580)
1317 ims |= E1000_IMS_DRSTA;
1318
25568a53 1319 wr32(E1000_IMS, ims);
844290e5 1320 } else {
55cac248
AD		 1321 wr32(E1000_IMS, IMS_ENABLE_MASK |
1322 E1000_IMS_DRSTA);
1323 wr32(E1000_IAM, IMS_ENABLE_MASK |
1324 E1000_IMS_DRSTA);
844290e5 1325 }
9d5c8243
AK		 1326}
1327
1328static void igb_update_mng_vlan(struct igb_adapter *adapter)
1329{
51466239 1330 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1331 u16 vid = adapter->hw.mng_cookie.vlan_id;
1332 u16 old_vid = adapter->mng_vlan_id;
51466239
AD		 1333
1334 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1335 /* add VID to filter table */
1336 igb_vfta_set(hw, vid, true);
1337 adapter->mng_vlan_id = vid;
1338 } else {
1339 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1340 }
1341
1342 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1343 (vid != old_vid) &&
1344 !vlan_group_get_device(adapter->vlgrp, old_vid)) {
1345 /* remove VID from filter table */
1346 igb_vfta_set(hw, old_vid, false);
9d5c8243
AK		 1347 }
1348}
1349
1350/**
1351 * igb_release_hw_control - release control of the h/w to f/w
1352 * @adapter: address of board private structure
1353 *
1354 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1355 * For ASF and Pass Through versions of f/w this means that the
1356 * driver is no longer loaded.
1357 *
1358 **/
1359static void igb_release_hw_control(struct igb_adapter *adapter)
1360{
1361 struct e1000_hw *hw = &adapter->hw;
1362 u32 ctrl_ext;
1363
1364 /* Let firmware take over control of h/w */
1365 ctrl_ext = rd32(E1000_CTRL_EXT);
1366 wr32(E1000_CTRL_EXT,
1367 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1368}
1369
9d5c8243
AK		 1370/**
1371 * igb_get_hw_control - get control of the h/w from f/w
1372 * @adapter: address of board private structure
1373 *
1374 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1375 * For ASF and Pass Through versions of f/w this means that
1376 * the driver is loaded.
1377 *
1378 **/
1379static void igb_get_hw_control(struct igb_adapter *adapter)
1380{
1381 struct e1000_hw *hw = &adapter->hw;
1382 u32 ctrl_ext;
1383
1384 /* Let firmware know the driver has taken over */
1385 ctrl_ext = rd32(E1000_CTRL_EXT);
1386 wr32(E1000_CTRL_EXT,
1387 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1388}
1389
9d5c8243
AK		 1390/**
1391 * igb_configure - configure the hardware for RX and TX
1392 * @adapter: private board structure
1393 **/
1394static void igb_configure(struct igb_adapter *adapter)
1395{
1396 struct net_device *netdev = adapter->netdev;
1397 int i;
1398
1399 igb_get_hw_control(adapter);
ff41f8dc 1400 igb_set_rx_mode(netdev);
9d5c8243
AK		 1401
1402 igb_restore_vlan(adapter);
9d5c8243 1403
85b430b4 1404 igb_setup_tctl(adapter);
06cf2666 1405 igb_setup_mrqc(adapter);
9d5c8243 1406 igb_setup_rctl(adapter);
85b430b4
AD		 1407
1408 igb_configure_tx(adapter);
9d5c8243 1409 igb_configure_rx(adapter);
662d7205
AD		 1410
1411 igb_rx_fifo_flush_82575(&adapter->hw);
1412
c493ea45 1413 /* call igb_desc_unused which always leaves
9d5c8243
AK		 1414 * at least 1 descriptor unused to make sure
1415 * next_to_use != next_to_clean */
1416 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 1417 struct igb_ring *ring = adapter->rx_ring[i];
c493ea45 1418 igb_alloc_rx_buffers_adv(ring, igb_desc_unused(ring));
9d5c8243 1419 }
9d5c8243
AK		 1420}
1421
88a268c1
NN		 1422/**
1423 * igb_power_up_link - Power up the phy/serdes link
1424 * @adapter: address of board private structure
1425 **/
1426void igb_power_up_link(struct igb_adapter *adapter)
1427{
1428 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1429 igb_power_up_phy_copper(&adapter->hw);
1430 else
1431 igb_power_up_serdes_link_82575(&adapter->hw);
1432}
1433
1434/**
1435 * igb_power_down_link - Power down the phy/serdes link
1436 * @adapter: address of board private structure
1437 */
1438static void igb_power_down_link(struct igb_adapter *adapter)
1439{
1440 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1441 igb_power_down_phy_copper_82575(&adapter->hw);
1442 else
1443 igb_shutdown_serdes_link_82575(&adapter->hw);
1444}
9d5c8243
AK		 1445
1446/**
1447 * igb_up - Open the interface and prepare it to handle traffic
1448 * @adapter: board private structure
1449 **/
9d5c8243
AK		 1450int igb_up(struct igb_adapter *adapter)
1451{
1452 struct e1000_hw *hw = &adapter->hw;
1453 int i;
1454
1455 /* hardware has been reset, we need to reload some things */
1456 igb_configure(adapter);
1457
1458 clear_bit(__IGB_DOWN, &adapter->state);
1459
047e0030
AD		 1460 for (i = 0; i < adapter->num_q_vectors; i++) {
1461 struct igb_q_vector *q_vector = adapter->q_vector[i];
1462 napi_enable(&q_vector->napi);
1463 }
844290e5 1464 if (adapter->msix_entries)
9d5c8243 1465 igb_configure_msix(adapter);
feeb2721
AD		 1466 else
1467 igb_assign_vector(adapter->q_vector[0], 0);
9d5c8243
AK		 1468
1469 /* Clear any pending interrupts. */
1470 rd32(E1000_ICR);
1471 igb_irq_enable(adapter);
1472
d4960307
AD		 1473 /* notify VFs that reset has been completed */
1474 if (adapter->vfs_allocated_count) {
1475 u32 reg_data = rd32(E1000_CTRL_EXT);
1476 reg_data |= E1000_CTRL_EXT_PFRSTD;
1477 wr32(E1000_CTRL_EXT, reg_data);
1478 }
1479
4cb9be7a
JB		 1480 netif_tx_start_all_queues(adapter->netdev);
1481
25568a53
AD		 1482 /* start the watchdog. */
1483 hw->mac.get_link_status = 1;
1484 schedule_work(&adapter->watchdog_task);
1485
9d5c8243
AK		 1486 return 0;
1487}
1488
1489void igb_down(struct igb_adapter *adapter)
1490{
9d5c8243 1491 struct net_device *netdev = adapter->netdev;
330a6d6a 1492 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1493 u32 tctl, rctl;
1494 int i;
1495
1496 /* signal that we're down so the interrupt handler does not
1497 * reschedule our watchdog timer */
1498 set_bit(__IGB_DOWN, &adapter->state);
1499
1500 /* disable receives in the hardware */
1501 rctl = rd32(E1000_RCTL);
1502 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1503 /* flush and sleep below */
1504
fd2ea0a7 1505 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1506
1507 /* disable transmits in the hardware */
1508 tctl = rd32(E1000_TCTL);
1509 tctl &= ~E1000_TCTL_EN;
1510 wr32(E1000_TCTL, tctl);
1511 /* flush both disables and wait for them to finish */
1512 wrfl();
1513 msleep(10);
1514
047e0030
AD		 1515 for (i = 0; i < adapter->num_q_vectors; i++) {
1516 struct igb_q_vector *q_vector = adapter->q_vector[i];
1517 napi_disable(&q_vector->napi);
1518 }
9d5c8243 1519
9d5c8243
AK		 1520 igb_irq_disable(adapter);
1521
1522 del_timer_sync(&adapter->watchdog_timer);
1523 del_timer_sync(&adapter->phy_info_timer);
1524
9d5c8243 1525 netif_carrier_off(netdev);
04fe6358
AD		 1526
1527 /* record the stats before reset*/
1528 igb_update_stats(adapter);
1529
9d5c8243
AK		 1530 adapter->link_speed = 0;
1531 adapter->link_duplex = 0;
1532
3023682e
JK		 1533 if (!pci_channel_offline(adapter->pdev))
1534 igb_reset(adapter);
9d5c8243
AK		 1535 igb_clean_all_tx_rings(adapter);
1536 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1537#ifdef CONFIG_IGB_DCA
1538
1539 /* since we reset the hardware DCA settings were cleared */
1540 igb_setup_dca(adapter);
1541#endif
9d5c8243
AK		 1542}
1543
1544void igb_reinit_locked(struct igb_adapter *adapter)
1545{
1546 WARN_ON(in_interrupt());
1547 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1548 msleep(1);
1549 igb_down(adapter);
1550 igb_up(adapter);
1551 clear_bit(__IGB_RESETTING, &adapter->state);
1552}
1553
1554void igb_reset(struct igb_adapter *adapter)
1555{
090b1795 1556 struct pci_dev *pdev = adapter->pdev;
9d5c8243 1557 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1558 struct e1000_mac_info *mac = &hw->mac;
1559 struct e1000_fc_info *fc = &hw->fc;
9d5c8243
AK		 1560 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
1561 u16 hwm;
1562
1563 /* Repartition Pba for greater than 9k mtu
1564 * To take effect CTRL.RST is required.
1565 */
fa4dfae0 1566 switch (mac->type) {
d2ba2ed8 1567 case e1000_i350:
55cac248
AD		 1568 case e1000_82580:
1569 pba = rd32(E1000_RXPBS);
1570 pba = igb_rxpbs_adjust_82580(pba);
1571 break;
fa4dfae0 1572 case e1000_82576:
d249be54
AD		 1573 pba = rd32(E1000_RXPBS);
1574 pba &= E1000_RXPBS_SIZE_MASK_82576;
fa4dfae0
AD		 1575 break;
1576 case e1000_82575:
1577 default:
1578 pba = E1000_PBA_34K;
1579 break;
2d064c06 1580 }
9d5c8243 1581
2d064c06
AD		 1582 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1583 (mac->type < e1000_82576)) {
9d5c8243
AK		 1584 /* adjust PBA for jumbo frames */
1585 wr32(E1000_PBA, pba);
1586
1587 /* To maintain wire speed transmits, the Tx FIFO should be
1588 * large enough to accommodate two full transmit packets,
1589 * rounded up to the next 1KB and expressed in KB. Likewise,
1590 * the Rx FIFO should be large enough to accommodate at least
1591 * one full receive packet and is similarly rounded up and
1592 * expressed in KB. */
1593 pba = rd32(E1000_PBA);
1594 /* upper 16 bits has Tx packet buffer allocation size in KB */
1595 tx_space = pba >> 16;
1596 /* lower 16 bits has Rx packet buffer allocation size in KB */
1597 pba &= 0xffff;
1598 /* the tx fifo also stores 16 bytes of information about the tx
1599 * but don't include ethernet FCS because hardware appends it */
1600 min_tx_space = (adapter->max_frame_size +
85e8d004 1601 sizeof(union e1000_adv_tx_desc) -
9d5c8243
AK		 1602 ETH_FCS_LEN) * 2;
1603 min_tx_space = ALIGN(min_tx_space, 1024);
1604 min_tx_space >>= 10;
1605 /* software strips receive CRC, so leave room for it */
1606 min_rx_space = adapter->max_frame_size;
1607 min_rx_space = ALIGN(min_rx_space, 1024);
1608 min_rx_space >>= 10;
1609
1610 /* If current Tx allocation is less than the min Tx FIFO size,
1611 * and the min Tx FIFO size is less than the current Rx FIFO
1612 * allocation, take space away from current Rx allocation */
1613 if (tx_space < min_tx_space &&
1614 ((min_tx_space - tx_space) < pba)) {
1615 pba = pba - (min_tx_space - tx_space);
1616
1617 /* if short on rx space, rx wins and must trump tx
1618 * adjustment */
1619 if (pba < min_rx_space)
1620 pba = min_rx_space;
1621 }
2d064c06 1622 wr32(E1000_PBA, pba);
9d5c8243 1623 }
9d5c8243
AK		 1624
1625 /* flow control settings */
1626 /* The high water mark must be low enough to fit one full frame
1627 * (or the size used for early receive) above it in the Rx FIFO.
1628 * Set it to the lower of:
1629 * - 90% of the Rx FIFO size, or
1630 * - the full Rx FIFO size minus one full frame */
1631 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1632 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1633
d405ea3e
AD		 1634 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1635 fc->low_water = fc->high_water - 16;
9d5c8243
AK		 1636 fc->pause_time = 0xFFFF;
1637 fc->send_xon = 1;
0cce119a 1638 fc->current_mode = fc->requested_mode;
9d5c8243 1639
4ae196df
AD		 1640 /* disable receive for all VFs and wait one second */
1641 if (adapter->vfs_allocated_count) {
1642 int i;
1643 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
f2ca0dbe 1644 adapter->vf_data[i].flags = 0;
4ae196df
AD		 1645
1646 /* ping all the active vfs to let them know we are going down */
f2ca0dbe 1647 igb_ping_all_vfs(adapter);
4ae196df
AD		 1648
1649 /* disable transmits and receives */
1650 wr32(E1000_VFRE, 0);
1651 wr32(E1000_VFTE, 0);
1652 }
1653
9d5c8243 1654 /* Allow time for pending master requests to run */
330a6d6a 1655 hw->mac.ops.reset_hw(hw);
9d5c8243
AK		 1656 wr32(E1000_WUC, 0);
1657
330a6d6a 1658 if (hw->mac.ops.init_hw(hw))
090b1795 1659 dev_err(&pdev->dev, "Hardware Error\n");
9d5c8243 1660
55cac248
AD		 1661 if (hw->mac.type == e1000_82580) {
1662 u32 reg = rd32(E1000_PCIEMISC);
1663 wr32(E1000_PCIEMISC,
1664 reg & ~E1000_PCIEMISC_LX_DECISION);
1665 }
88a268c1
NN		 1666 if (!netif_running(adapter->netdev))
1667 igb_power_down_link(adapter);
1668
9d5c8243
AK		 1669 igb_update_mng_vlan(adapter);
1670
1671 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1672 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1673
330a6d6a 1674 igb_get_phy_info(hw);
9d5c8243
AK		 1675}
1676
2e5c6922 1677static const struct net_device_ops igb_netdev_ops = {
559e9c49 1678 .ndo_open = igb_open,
2e5c6922 1679 .ndo_stop = igb_close,
00829823 1680 .ndo_start_xmit = igb_xmit_frame_adv,
2e5c6922 1681 .ndo_get_stats = igb_get_stats,
ff41f8dc
AD		 1682 .ndo_set_rx_mode = igb_set_rx_mode,
1683 .ndo_set_multicast_list = igb_set_rx_mode,
2e5c6922
SH		 1684 .ndo_set_mac_address = igb_set_mac,
1685 .ndo_change_mtu = igb_change_mtu,
1686 .ndo_do_ioctl = igb_ioctl,
1687 .ndo_tx_timeout = igb_tx_timeout,
1688 .ndo_validate_addr = eth_validate_addr,
1689 .ndo_vlan_rx_register = igb_vlan_rx_register,
1690 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1691 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
8151d294
WM		 1692 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
1693 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
1694 .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw,
1695 .ndo_get_vf_config = igb_ndo_get_vf_config,
2e5c6922
SH		 1696#ifdef CONFIG_NET_POLL_CONTROLLER
1697 .ndo_poll_controller = igb_netpoll,
1698#endif
1699};
1700
9d5c8243
AK		 1701/**
1702 * igb_probe - Device Initialization Routine
1703 * @pdev: PCI device information struct
1704 * @ent: entry in igb_pci_tbl
1705 *
1706 * Returns 0 on success, negative on failure
1707 *
1708 * igb_probe initializes an adapter identified by a pci_dev structure.
1709 * The OS initialization, configuring of the adapter private structure,
1710 * and a hardware reset occur.
1711 **/
1712static int __devinit igb_probe(struct pci_dev *pdev,
1713 const struct pci_device_id *ent)
1714{
1715 struct net_device *netdev;
1716 struct igb_adapter *adapter;
1717 struct e1000_hw *hw;
4337e993
AD		 1718 u16 eeprom_data = 0;
1719 static int global_quad_port_a; /* global quad port a indication */
9d5c8243
AK		 1720 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1721 unsigned long mmio_start, mmio_len;
2d6a5e95 1722 int err, pci_using_dac;
9d5c8243
AK		 1723 u16 eeprom_apme_mask = IGB_EEPROM_APME;
1724 u32 part_num;
1725
aed5dec3 1726 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 1727 if (err)
1728 return err;
1729
1730 pci_using_dac = 0;
59d71989 1731 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243 1732 if (!err) {
59d71989 1733 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243
AK		 1734 if (!err)
1735 pci_using_dac = 1;
1736 } else {
59d71989 1737 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243 1738 if (err) {
59d71989 1739 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243
AK		 1740 if (err) {
1741 dev_err(&pdev->dev, "No usable DMA "
1742 "configuration, aborting\n");
1743 goto err_dma;
1744 }
1745 }
1746 }
1747
aed5dec3
AD		 1748 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1749 IORESOURCE_MEM),
1750 igb_driver_name);
9d5c8243
AK		 1751 if (err)
1752 goto err_pci_reg;
1753
19d5afd4 1754 pci_enable_pcie_error_reporting(pdev);
40a914fa 1755
9d5c8243 1756 pci_set_master(pdev);
c682fc23 1757 pci_save_state(pdev);
9d5c8243
AK		 1758
1759 err = -ENOMEM;
1bfaf07b
AD		 1760 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1761 IGB_ABS_MAX_TX_QUEUES);
9d5c8243
AK		 1762 if (!netdev)
1763 goto err_alloc_etherdev;
1764
1765 SET_NETDEV_DEV(netdev, &pdev->dev);
1766
1767 pci_set_drvdata(pdev, netdev);
1768 adapter = netdev_priv(netdev);
1769 adapter->netdev = netdev;
1770 adapter->pdev = pdev;
1771 hw = &adapter->hw;
1772 hw->back = adapter;
1773 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
1774
1775 mmio_start = pci_resource_start(pdev, 0);
1776 mmio_len = pci_resource_len(pdev, 0);
1777
1778 err = -EIO;
28b0759c
AD		 1779 hw->hw_addr = ioremap(mmio_start, mmio_len);
1780 if (!hw->hw_addr)
9d5c8243
AK		 1781 goto err_ioremap;
1782
2e5c6922 1783 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 1784 igb_set_ethtool_ops(netdev);
9d5c8243 1785 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 1786
1787 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1788
1789 netdev->mem_start = mmio_start;
1790 netdev->mem_end = mmio_start + mmio_len;
1791
9d5c8243
AK		 1792 /* PCI config space info */
1793 hw->vendor_id = pdev->vendor;
1794 hw->device_id = pdev->device;
1795 hw->revision_id = pdev->revision;
1796 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1797 hw->subsystem_device_id = pdev->subsystem_device;
1798
9d5c8243
AK		 1799 /* Copy the default MAC, PHY and NVM function pointers */
1800 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1801 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1802 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1803 /* Initialize skew-specific constants */
1804 err = ei->get_invariants(hw);
1805 if (err)
450c87c8 1806 goto err_sw_init;
9d5c8243 1807
450c87c8 1808 /* setup the private structure */
9d5c8243
AK		 1809 err = igb_sw_init(adapter);
1810 if (err)
1811 goto err_sw_init;
1812
1813 igb_get_bus_info_pcie(hw);
1814
1815 hw->phy.autoneg_wait_to_complete = false;
9d5c8243
AK		 1816
1817 /* Copper options */
1818 if (hw->phy.media_type == e1000_media_type_copper) {
1819 hw->phy.mdix = AUTO_ALL_MODES;
1820 hw->phy.disable_polarity_correction = false;
1821 hw->phy.ms_type = e1000_ms_hw_default;
1822 }
1823
1824 if (igb_check_reset_block(hw))
1825 dev_info(&pdev->dev,
1826 "PHY reset is blocked due to SOL/IDER session.\n");
1827
1828 netdev->features = NETIF_F_SG |
7d8eb29e 1829 NETIF_F_IP_CSUM |
9d5c8243
AK		 1830 NETIF_F_HW_VLAN_TX |
1831 NETIF_F_HW_VLAN_RX |
1832 NETIF_F_HW_VLAN_FILTER;
1833
7d8eb29e 1834 netdev->features |= NETIF_F_IPV6_CSUM;
9d5c8243 1835 netdev->features |= NETIF_F_TSO;
9d5c8243 1836 netdev->features |= NETIF_F_TSO6;
5c0999b7 1837 netdev->features |= NETIF_F_GRO;
d3352520 1838
48f29ffc
JK		 1839 netdev->vlan_features |= NETIF_F_TSO;
1840 netdev->vlan_features |= NETIF_F_TSO6;
7d8eb29e 1841 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 1842 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
48f29ffc
JK		 1843 netdev->vlan_features |= NETIF_F_SG;
1844
9d5c8243
AK		 1845 if (pci_using_dac)
1846 netdev->features |= NETIF_F_HIGHDMA;
1847
5b043fb0 1848 if (hw->mac.type >= e1000_82576)
b9473560
JB		 1849 netdev->features |= NETIF_F_SCTP_CSUM;
1850
330a6d6a 1851 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
9d5c8243
AK		 1852
1853 /* before reading the NVM, reset the controller to put the device in a
1854 * known good starting state */
1855 hw->mac.ops.reset_hw(hw);
1856
1857 /* make sure the NVM is good */
1858 if (igb_validate_nvm_checksum(hw) < 0) {
1859 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1860 err = -EIO;
1861 goto err_eeprom;
1862 }
1863
1864 /* copy the MAC address out of the NVM */
1865 if (hw->mac.ops.read_mac_addr(hw))
1866 dev_err(&pdev->dev, "NVM Read Error\n");
1867
1868 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1869 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1870
1871 if (!is_valid_ether_addr(netdev->perm_addr)) {
1872 dev_err(&pdev->dev, "Invalid MAC Address\n");
1873 err = -EIO;
1874 goto err_eeprom;
1875 }
1876
0e340485
AD		 1877 setup_timer(&adapter->watchdog_timer, &igb_watchdog,
1878 (unsigned long) adapter);
1879 setup_timer(&adapter->phy_info_timer, &igb_update_phy_info,
1880 (unsigned long) adapter);
9d5c8243
AK		 1881
1882 INIT_WORK(&adapter->reset_task, igb_reset_task);
1883 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1884
450c87c8 1885 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 1886 adapter->fc_autoneg = true;
1887 hw->mac.autoneg = true;
1888 hw->phy.autoneg_advertised = 0x2f;
1889
0cce119a
AD		 1890 hw->fc.requested_mode = e1000_fc_default;
1891 hw->fc.current_mode = e1000_fc_default;
9d5c8243 1892
9d5c8243
AK		 1893 igb_validate_mdi_setting(hw);
1894
9d5c8243
AK		 1895 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1896 * enable the ACPI Magic Packet filter
1897 */
1898
a2cf8b6c 1899 if (hw->bus.func == 0)
312c75ae 1900 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
55cac248
AD		 1901 else if (hw->mac.type == e1000_82580)
1902 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
1903 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
1904 &eeprom_data);
a2cf8b6c
AD		 1905 else if (hw->bus.func == 1)
1906 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243
AK		 1907
1908 if (eeprom_data & eeprom_apme_mask)
1909 adapter->eeprom_wol |= E1000_WUFC_MAG;
1910
1911 /* now that we have the eeprom settings, apply the special cases where
1912 * the eeprom may be wrong or the board simply won't support wake on
1913 * lan on a particular port */
1914 switch (pdev->device) {
1915 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1916 adapter->eeprom_wol = 0;
1917 break;
1918 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 1919 case E1000_DEV_ID_82576_FIBER:
1920 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 1921 /* Wake events only supported on port A for dual fiber
1922 * regardless of eeprom setting */
1923 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1924 adapter->eeprom_wol = 0;
1925 break;
c8ea5ea9 1926 case E1000_DEV_ID_82576_QUAD_COPPER:
d5aa2252 1927 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
c8ea5ea9
AD		 1928 /* if quad port adapter, disable WoL on all but port A */
1929 if (global_quad_port_a != 0)
1930 adapter->eeprom_wol = 0;
1931 else
1932 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
1933 /* Reset for multiple quad port adapters */
1934 if (++global_quad_port_a == 4)
1935 global_quad_port_a = 0;
1936 break;
9d5c8243
AK		 1937 }
1938
1939 /* initialize the wol settings based on the eeprom settings */
1940 adapter->wol = adapter->eeprom_wol;
e1b86d84 1941 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
9d5c8243
AK		 1942
1943 /* reset the hardware with the new settings */
1944 igb_reset(adapter);
1945
1946 /* let the f/w know that the h/w is now under the control of the
1947 * driver. */
1948 igb_get_hw_control(adapter);
1949
9d5c8243
AK		 1950 strcpy(netdev->name, "eth%d");
1951 err = register_netdev(netdev);
1952 if (err)
1953 goto err_register;
1954
b168dfc5
JB		 1955 /* carrier off reporting is important to ethtool even BEFORE open */
1956 netif_carrier_off(netdev);
1957
421e02f0 1958#ifdef CONFIG_IGB_DCA
bbd98fe4 1959 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 1960 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 1961 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 1962 igb_setup_dca(adapter);
1963 }
fe4506b6 1964
38c845c7 1965#endif
9d5c8243
AK		 1966 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1967 /* print bus type/speed/width info */
7c510e4b 1968 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
9d5c8243 1969 netdev->name,
559e9c49 1970 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
ff846f52 1971 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
559e9c49 1972 "unknown"),
59c3de89
AD		 1973 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
1974 (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :
1975 (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" :
1976 "unknown"),
7c510e4b 1977 netdev->dev_addr);
9d5c8243
AK		 1978
1979 igb_read_part_num(hw, &part_num);
1980 dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1981 (part_num >> 8), (part_num & 0xff));
1982
1983 dev_info(&pdev->dev,
1984 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1985 adapter->msix_entries ? "MSI-X" :
7dfc16fa 1986 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243
AK		 1987 adapter->num_rx_queues, adapter->num_tx_queues);
1988
9d5c8243
AK		 1989 return 0;
1990
1991err_register:
1992 igb_release_hw_control(adapter);
1993err_eeprom:
1994 if (!igb_check_reset_block(hw))
f5f4cf08 1995 igb_reset_phy(hw);
9d5c8243
AK		 1996
1997 if (hw->flash_address)
1998 iounmap(hw->flash_address);
9d5c8243 1999err_sw_init:
047e0030 2000 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 2001 iounmap(hw->hw_addr);
2002err_ioremap:
2003 free_netdev(netdev);
2004err_alloc_etherdev:
559e9c49
AD		 2005 pci_release_selected_regions(pdev,
2006 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243
AK		 2007err_pci_reg:
2008err_dma:
2009 pci_disable_device(pdev);
2010 return err;
2011}
2012
2013/**
2014 * igb_remove - Device Removal Routine
2015 * @pdev: PCI device information struct
2016 *
2017 * igb_remove is called by the PCI subsystem to alert the driver
2018 * that it should release a PCI device. The could be caused by a
2019 * Hot-Plug event, or because the driver is going to be removed from
2020 * memory.
2021 **/
2022static void __devexit igb_remove(struct pci_dev *pdev)
2023{
2024 struct net_device *netdev = pci_get_drvdata(pdev);
2025 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 2026 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 2027
2028 /* flush_scheduled work may reschedule our watchdog task, so
2029 * explicitly disable watchdog tasks from being rescheduled */
2030 set_bit(__IGB_DOWN, &adapter->state);
2031 del_timer_sync(&adapter->watchdog_timer);
2032 del_timer_sync(&adapter->phy_info_timer);
2033
2034 flush_scheduled_work();
2035
421e02f0 2036#ifdef CONFIG_IGB_DCA
7dfc16fa 2037 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 2038 dev_info(&pdev->dev, "DCA disabled\n");
2039 dca_remove_requester(&pdev->dev);
7dfc16fa 2040 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 2041 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 2042 }
2043#endif
2044
9d5c8243
AK		 2045 /* Release control of h/w to f/w. If f/w is AMT enabled, this
2046 * would have already happened in close and is redundant. */
2047 igb_release_hw_control(adapter);
2048
2049 unregister_netdev(netdev);
2050
047e0030 2051 igb_clear_interrupt_scheme(adapter);
9d5c8243 2052
37680117
AD		 2053#ifdef CONFIG_PCI_IOV
2054 /* reclaim resources allocated to VFs */
2055 if (adapter->vf_data) {
2056 /* disable iov and allow time for transactions to clear */
2057 pci_disable_sriov(pdev);
2058 msleep(500);
2059
2060 kfree(adapter->vf_data);
2061 adapter->vf_data = NULL;
2062 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2063 msleep(100);
2064 dev_info(&pdev->dev, "IOV Disabled\n");
2065 }
2066#endif
559e9c49 2067
28b0759c
AD		 2068 iounmap(hw->hw_addr);
2069 if (hw->flash_address)
2070 iounmap(hw->flash_address);
559e9c49
AD		 2071 pci_release_selected_regions(pdev,
2072 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243
AK		 2073
2074 free_netdev(netdev);
2075
19d5afd4 2076 pci_disable_pcie_error_reporting(pdev);
40a914fa 2077
9d5c8243
AK		 2078 pci_disable_device(pdev);
2079}
2080
a6b623e0
AD		 2081/**
2082 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2083 * @adapter: board private structure to initialize
2084 *
2085 * This function initializes the vf specific data storage and then attempts to
2086 * allocate the VFs. The reason for ordering it this way is because it is much
2087 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2088 * the memory for the VFs.
2089 **/
2090static void __devinit igb_probe_vfs(struct igb_adapter * adapter)
2091{
2092#ifdef CONFIG_PCI_IOV
2093 struct pci_dev *pdev = adapter->pdev;
2094
2095 if (adapter->vfs_allocated_count > 7)
2096 adapter->vfs_allocated_count = 7;
2097
2098 if (adapter->vfs_allocated_count) {
2099 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2100 sizeof(struct vf_data_storage),
2101 GFP_KERNEL);
2102 /* if allocation failed then we do not support SR-IOV */
2103 if (!adapter->vf_data) {
2104 adapter->vfs_allocated_count = 0;
2105 dev_err(&pdev->dev, "Unable to allocate memory for VF "
2106 "Data Storage\n");
2107 }
2108 }
2109
2110 if (pci_enable_sriov(pdev, adapter->vfs_allocated_count)) {
2111 kfree(adapter->vf_data);
2112 adapter->vf_data = NULL;
2113#endif /* CONFIG_PCI_IOV */
2114 adapter->vfs_allocated_count = 0;
2115#ifdef CONFIG_PCI_IOV
2116 } else {
2117 unsigned char mac_addr[ETH_ALEN];
2118 int i;
2119 dev_info(&pdev->dev, "%d vfs allocated\n",
2120 adapter->vfs_allocated_count);
2121 for (i = 0; i < adapter->vfs_allocated_count; i++) {
2122 random_ether_addr(mac_addr);
2123 igb_set_vf_mac(adapter, i, mac_addr);
2124 }
2125 }
2126#endif /* CONFIG_PCI_IOV */
2127}
2128
115f459a
AD		 2129
2130/**
2131 * igb_init_hw_timer - Initialize hardware timer used with IEEE 1588 timestamp
2132 * @adapter: board private structure to initialize
2133 *
2134 * igb_init_hw_timer initializes the function pointer and values for the hw
2135 * timer found in hardware.
2136 **/
2137static void igb_init_hw_timer(struct igb_adapter *adapter)
2138{
2139 struct e1000_hw *hw = &adapter->hw;
2140
2141 switch (hw->mac.type) {
d2ba2ed8 2142 case e1000_i350:
55cac248
AD		 2143 case e1000_82580:
2144 memset(&adapter->cycles, 0, sizeof(adapter->cycles));
2145 adapter->cycles.read = igb_read_clock;
2146 adapter->cycles.mask = CLOCKSOURCE_MASK(64);
2147 adapter->cycles.mult = 1;
2148 /*
2149 * The 82580 timesync updates the system timer every 8ns by 8ns
2150 * and the value cannot be shifted. Instead we need to shift
2151 * the registers to generate a 64bit timer value. As a result
2152 * SYSTIMR/L/H, TXSTMPL/H, RXSTMPL/H all have to be shifted by
2153 * 24 in order to generate a larger value for synchronization.
2154 */
2155 adapter->cycles.shift = IGB_82580_TSYNC_SHIFT;
2156 /* disable system timer temporarily by setting bit 31 */
2157 wr32(E1000_TSAUXC, 0x80000000);
2158 wrfl();
2159
2160 /* Set registers so that rollover occurs soon to test this. */
2161 wr32(E1000_SYSTIMR, 0x00000000);
2162 wr32(E1000_SYSTIML, 0x80000000);
2163 wr32(E1000_SYSTIMH, 0x000000FF);
2164 wrfl();
2165
2166 /* enable system timer by clearing bit 31 */
2167 wr32(E1000_TSAUXC, 0x0);
2168 wrfl();
2169
2170 timecounter_init(&adapter->clock,
2171 &adapter->cycles,
2172 ktime_to_ns(ktime_get_real()));
2173 /*
2174 * Synchronize our NIC clock against system wall clock. NIC
2175 * time stamp reading requires ~3us per sample, each sample
2176 * was pretty stable even under load => only require 10
2177 * samples for each offset comparison.
2178 */
2179 memset(&adapter->compare, 0, sizeof(adapter->compare));
2180 adapter->compare.source = &adapter->clock;
2181 adapter->compare.target = ktime_get_real;
2182 adapter->compare.num_samples = 10;
2183 timecompare_update(&adapter->compare, 0);
2184 break;
115f459a
AD		 2185 case e1000_82576:
2186 /*
2187 * Initialize hardware timer: we keep it running just in case
2188 * that some program needs it later on.
2189 */
2190 memset(&adapter->cycles, 0, sizeof(adapter->cycles));
2191 adapter->cycles.read = igb_read_clock;
2192 adapter->cycles.mask = CLOCKSOURCE_MASK(64);
2193 adapter->cycles.mult = 1;
2194 /**
2195 * Scale the NIC clock cycle by a large factor so that
2196 * relatively small clock corrections can be added or
2197 * substracted at each clock tick. The drawbacks of a large
2198 * factor are a) that the clock register overflows more quickly
2199 * (not such a big deal) and b) that the increment per tick has
2200 * to fit into 24 bits. As a result we need to use a shift of
2201 * 19 so we can fit a value of 16 into the TIMINCA register.
2202 */
2203 adapter->cycles.shift = IGB_82576_TSYNC_SHIFT;
2204 wr32(E1000_TIMINCA,
2205 (1 << E1000_TIMINCA_16NS_SHIFT) |
2206 (16 << IGB_82576_TSYNC_SHIFT));
2207
2208 /* Set registers so that rollover occurs soon to test this. */
2209 wr32(E1000_SYSTIML, 0x00000000);
2210 wr32(E1000_SYSTIMH, 0xFF800000);
2211 wrfl();
2212
2213 timecounter_init(&adapter->clock,
2214 &adapter->cycles,
2215 ktime_to_ns(ktime_get_real()));
2216 /*
2217 * Synchronize our NIC clock against system wall clock. NIC
2218 * time stamp reading requires ~3us per sample, each sample
2219 * was pretty stable even under load => only require 10
2220 * samples for each offset comparison.
2221 */
2222 memset(&adapter->compare, 0, sizeof(adapter->compare));
2223 adapter->compare.source = &adapter->clock;
2224 adapter->compare.target = ktime_get_real;
2225 adapter->compare.num_samples = 10;
2226 timecompare_update(&adapter->compare, 0);
2227 break;
2228 case e1000_82575:
2229 /* 82575 does not support timesync */
2230 default:
2231 break;
2232 }
2233
2234}
2235
9d5c8243
AK		 2236/**
2237 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2238 * @adapter: board private structure to initialize
2239 *
2240 * igb_sw_init initializes the Adapter private data structure.
2241 * Fields are initialized based on PCI device information and
2242 * OS network device settings (MTU size).
2243 **/
2244static int __devinit igb_sw_init(struct igb_adapter *adapter)
2245{
2246 struct e1000_hw *hw = &adapter->hw;
2247 struct net_device *netdev = adapter->netdev;
2248 struct pci_dev *pdev = adapter->pdev;
2249
2250 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2251
68fd9910
AD		 2252 adapter->tx_ring_count = IGB_DEFAULT_TXD;
2253 adapter->rx_ring_count = IGB_DEFAULT_RXD;
4fc82adf
AD		 2254 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2255 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2256
9d5c8243
AK		 2257 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2258 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2259
a6b623e0
AD		 2260#ifdef CONFIG_PCI_IOV
2261 if (hw->mac.type == e1000_82576)
2262 adapter->vfs_allocated_count = max_vfs;
2263
2264#endif /* CONFIG_PCI_IOV */
a99955fc
AD		 2265 adapter->rss_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
2266
2267 /*
2268 * if rss_queues > 4 or vfs are going to be allocated with rss_queues
2269 * then we should combine the queues into a queue pair in order to
2270 * conserve interrupts due to limited supply
2271 */
2272 if ((adapter->rss_queues > 4) ||
2273 ((adapter->rss_queues > 1) && (adapter->vfs_allocated_count > 6)))
2274 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2275
a6b623e0 2276 /* This call may decrease the number of queues */
047e0030 2277 if (igb_init_interrupt_scheme(adapter)) {
9d5c8243
AK		 2278 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
2279 return -ENOMEM;
2280 }
2281
115f459a 2282 igb_init_hw_timer(adapter);
a6b623e0
AD		 2283 igb_probe_vfs(adapter);
2284
9d5c8243
AK		 2285 /* Explicitly disable IRQ since the NIC can be in any state. */
2286 igb_irq_disable(adapter);
2287
2288 set_bit(__IGB_DOWN, &adapter->state);
2289 return 0;
2290}
2291
2292/**
2293 * igb_open - Called when a network interface is made active
2294 * @netdev: network interface device structure
2295 *
2296 * Returns 0 on success, negative value on failure
2297 *
2298 * The open entry point is called when a network interface is made
2299 * active by the system (IFF_UP). At this point all resources needed
2300 * for transmit and receive operations are allocated, the interrupt
2301 * handler is registered with the OS, the watchdog timer is started,
2302 * and the stack is notified that the interface is ready.
2303 **/
2304static int igb_open(struct net_device *netdev)
2305{
2306 struct igb_adapter *adapter = netdev_priv(netdev);
2307 struct e1000_hw *hw = &adapter->hw;
2308 int err;
2309 int i;
2310
2311 /* disallow open during test */
2312 if (test_bit(__IGB_TESTING, &adapter->state))
2313 return -EBUSY;
2314
b168dfc5
JB		 2315 netif_carrier_off(netdev);
2316
9d5c8243
AK		 2317 /* allocate transmit descriptors */
2318 err = igb_setup_all_tx_resources(adapter);
2319 if (err)
2320 goto err_setup_tx;
2321
2322 /* allocate receive descriptors */
2323 err = igb_setup_all_rx_resources(adapter);
2324 if (err)
2325 goto err_setup_rx;
2326
88a268c1 2327 igb_power_up_link(adapter);
9d5c8243 2328
9d5c8243
AK		 2329 /* before we allocate an interrupt, we must be ready to handle it.
2330 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
2331 * as soon as we call pci_request_irq, so we have to setup our
2332 * clean_rx handler before we do so. */
2333 igb_configure(adapter);
2334
2335 err = igb_request_irq(adapter);
2336 if (err)
2337 goto err_req_irq;
2338
2339 /* From here on the code is the same as igb_up() */
2340 clear_bit(__IGB_DOWN, &adapter->state);
2341
047e0030
AD		 2342 for (i = 0; i < adapter->num_q_vectors; i++) {
2343 struct igb_q_vector *q_vector = adapter->q_vector[i];
2344 napi_enable(&q_vector->napi);
2345 }
9d5c8243
AK		 2346
2347 /* Clear any pending interrupts. */
2348 rd32(E1000_ICR);
844290e5
PW		 2349
2350 igb_irq_enable(adapter);
2351
d4960307
AD		 2352 /* notify VFs that reset has been completed */
2353 if (adapter->vfs_allocated_count) {
2354 u32 reg_data = rd32(E1000_CTRL_EXT);
2355 reg_data |= E1000_CTRL_EXT_PFRSTD;
2356 wr32(E1000_CTRL_EXT, reg_data);
2357 }
2358
d55b53ff
JK		 2359 netif_tx_start_all_queues(netdev);
2360
25568a53
AD		 2361 /* start the watchdog. */
2362 hw->mac.get_link_status = 1;
2363 schedule_work(&adapter->watchdog_task);
9d5c8243
AK		 2364
2365 return 0;
2366
2367err_req_irq:
2368 igb_release_hw_control(adapter);
88a268c1 2369 igb_power_down_link(adapter);
9d5c8243
AK		 2370 igb_free_all_rx_resources(adapter);
2371err_setup_rx:
2372 igb_free_all_tx_resources(adapter);
2373err_setup_tx:
2374 igb_reset(adapter);
2375
2376 return err;
2377}
2378
2379/**
2380 * igb_close - Disables a network interface
2381 * @netdev: network interface device structure
2382 *
2383 * Returns 0, this is not allowed to fail
2384 *
2385 * The close entry point is called when an interface is de-activated
2386 * by the OS. The hardware is still under the driver's control, but
2387 * needs to be disabled. A global MAC reset is issued to stop the
2388 * hardware, and all transmit and receive resources are freed.
2389 **/
2390static int igb_close(struct net_device *netdev)
2391{
2392 struct igb_adapter *adapter = netdev_priv(netdev);
2393
2394 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
2395 igb_down(adapter);
2396
2397 igb_free_irq(adapter);
2398
2399 igb_free_all_tx_resources(adapter);
2400 igb_free_all_rx_resources(adapter);
2401
9d5c8243
AK		 2402 return 0;
2403}
2404
2405/**
2406 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
9d5c8243
AK		 2407 * @tx_ring: tx descriptor ring (for a specific queue) to setup
2408 *
2409 * Return 0 on success, negative on failure
2410 **/
80785298 2411int igb_setup_tx_resources(struct igb_ring *tx_ring)
9d5c8243 2412{
59d71989 2413 struct device *dev = tx_ring->dev;
9d5c8243
AK		 2414 int size;
2415
2416 size = sizeof(struct igb_buffer) * tx_ring->count;
2417 tx_ring->buffer_info = vmalloc(size);
2418 if (!tx_ring->buffer_info)
2419 goto err;
2420 memset(tx_ring->buffer_info, 0, size);
2421
2422 /* round up to nearest 4K */
85e8d004 2423 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 2424 tx_ring->size = ALIGN(tx_ring->size, 4096);
2425
59d71989
AD		 2426 tx_ring->desc = dma_alloc_coherent(dev,
2427 tx_ring->size,
2428 &tx_ring->dma,
2429 GFP_KERNEL);
9d5c8243
AK		 2430
2431 if (!tx_ring->desc)
2432 goto err;
2433
9d5c8243
AK		 2434 tx_ring->next_to_use = 0;
2435 tx_ring->next_to_clean = 0;
9d5c8243
AK		 2436 return 0;
2437
2438err:
2439 vfree(tx_ring->buffer_info);
59d71989 2440 dev_err(dev,
9d5c8243
AK		 2441 "Unable to allocate memory for the transmit descriptor ring\n");
2442 return -ENOMEM;
2443}
2444
2445/**
2446 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
2447 * (Descriptors) for all queues
2448 * @adapter: board private structure
2449 *
2450 * Return 0 on success, negative on failure
2451 **/
2452static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
2453{
439705e1 2454 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2455 int i, err = 0;
2456
2457 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 2458 err = igb_setup_tx_resources(adapter->tx_ring[i]);
9d5c8243 2459 if (err) {
439705e1 2460 dev_err(&pdev->dev,
9d5c8243
AK		 2461 "Allocation for Tx Queue %u failed\n", i);
2462 for (i--; i >= 0; i--)
3025a446 2463 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 2464 break;
2465 }
2466 }
2467
a99955fc 2468 for (i = 0; i < IGB_ABS_MAX_TX_QUEUES; i++) {
439705e1 2469 int r_idx = i % adapter->num_tx_queues;
3025a446 2470 adapter->multi_tx_table[i] = adapter->tx_ring[r_idx];
eebbbdba 2471 }
9d5c8243
AK		 2472 return err;
2473}
2474
2475/**
85b430b4
AD		 2476 * igb_setup_tctl - configure the transmit control registers
2477 * @adapter: Board private structure
9d5c8243 2478 **/
d7ee5b3a 2479void igb_setup_tctl(struct igb_adapter *adapter)
9d5c8243 2480{
9d5c8243
AK		 2481 struct e1000_hw *hw = &adapter->hw;
2482 u32 tctl;
9d5c8243 2483
85b430b4
AD		 2484 /* disable queue 0 which is enabled by default on 82575 and 82576 */
2485 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 2486
2487 /* Program the Transmit Control Register */
9d5c8243
AK		 2488 tctl = rd32(E1000_TCTL);
2489 tctl &= ~E1000_TCTL_CT;
2490 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2491 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2492
2493 igb_config_collision_dist(hw);
2494
9d5c8243
AK		 2495 /* Enable transmits */
2496 tctl |= E1000_TCTL_EN;
2497
2498 wr32(E1000_TCTL, tctl);
2499}
2500
85b430b4
AD		 2501/**
2502 * igb_configure_tx_ring - Configure transmit ring after Reset
2503 * @adapter: board private structure
2504 * @ring: tx ring to configure
2505 *
2506 * Configure a transmit ring after a reset.
2507 **/
d7ee5b3a
AD		 2508void igb_configure_tx_ring(struct igb_adapter *adapter,
2509 struct igb_ring *ring)
85b430b4
AD		 2510{
2511 struct e1000_hw *hw = &adapter->hw;
2512 u32 txdctl;
2513 u64 tdba = ring->dma;
2514 int reg_idx = ring->reg_idx;
2515
2516 /* disable the queue */
2517 txdctl = rd32(E1000_TXDCTL(reg_idx));
2518 wr32(E1000_TXDCTL(reg_idx),
2519 txdctl & ~E1000_TXDCTL_QUEUE_ENABLE);
2520 wrfl();
2521 mdelay(10);
2522
2523 wr32(E1000_TDLEN(reg_idx),
2524 ring->count * sizeof(union e1000_adv_tx_desc));
2525 wr32(E1000_TDBAL(reg_idx),
2526 tdba & 0x00000000ffffffffULL);
2527 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
2528
fce99e34
AD		 2529 ring->head = hw->hw_addr + E1000_TDH(reg_idx);
2530 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
2531 writel(0, ring->head);
2532 writel(0, ring->tail);
85b430b4
AD		 2533
2534 txdctl |= IGB_TX_PTHRESH;
2535 txdctl |= IGB_TX_HTHRESH << 8;
2536 txdctl |= IGB_TX_WTHRESH << 16;
2537
2538 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
2539 wr32(E1000_TXDCTL(reg_idx), txdctl);
2540}
2541
2542/**
2543 * igb_configure_tx - Configure transmit Unit after Reset
2544 * @adapter: board private structure
2545 *
2546 * Configure the Tx unit of the MAC after a reset.
2547 **/
2548static void igb_configure_tx(struct igb_adapter *adapter)
2549{
2550 int i;
2551
2552 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 2553 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
85b430b4
AD		 2554}
2555
9d5c8243
AK		 2556/**
2557 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
9d5c8243
AK		 2558 * @rx_ring: rx descriptor ring (for a specific queue) to setup
2559 *
2560 * Returns 0 on success, negative on failure
2561 **/
80785298 2562int igb_setup_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2563{
59d71989 2564 struct device *dev = rx_ring->dev;
9d5c8243
AK		 2565 int size, desc_len;
2566
2567 size = sizeof(struct igb_buffer) * rx_ring->count;
2568 rx_ring->buffer_info = vmalloc(size);
2569 if (!rx_ring->buffer_info)
2570 goto err;
2571 memset(rx_ring->buffer_info, 0, size);
2572
2573 desc_len = sizeof(union e1000_adv_rx_desc);
2574
2575 /* Round up to nearest 4K */
2576 rx_ring->size = rx_ring->count * desc_len;
2577 rx_ring->size = ALIGN(rx_ring->size, 4096);
2578
59d71989
AD		 2579 rx_ring->desc = dma_alloc_coherent(dev,
2580 rx_ring->size,
2581 &rx_ring->dma,
2582 GFP_KERNEL);
9d5c8243
AK		 2583
2584 if (!rx_ring->desc)
2585 goto err;
2586
2587 rx_ring->next_to_clean = 0;
2588 rx_ring->next_to_use = 0;
9d5c8243 2589
9d5c8243
AK		 2590 return 0;
2591
2592err:
2593 vfree(rx_ring->buffer_info);
439705e1 2594 rx_ring->buffer_info = NULL;
59d71989
AD		 2595 dev_err(dev, "Unable to allocate memory for the receive descriptor"
2596 " ring\n");
9d5c8243
AK		 2597 return -ENOMEM;
2598}
2599
2600/**
2601 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
2602 * (Descriptors) for all queues
2603 * @adapter: board private structure
2604 *
2605 * Return 0 on success, negative on failure
2606 **/
2607static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
2608{
439705e1 2609 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2610 int i, err = 0;
2611
2612 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 2613 err = igb_setup_rx_resources(adapter->rx_ring[i]);
9d5c8243 2614 if (err) {
439705e1 2615 dev_err(&pdev->dev,
9d5c8243
AK		 2616 "Allocation for Rx Queue %u failed\n", i);
2617 for (i--; i >= 0; i--)
3025a446 2618 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 2619 break;
2620 }
2621 }
2622
2623 return err;
2624}
2625
06cf2666
AD		 2626/**
2627 * igb_setup_mrqc - configure the multiple receive queue control registers
2628 * @adapter: Board private structure
2629 **/
2630static void igb_setup_mrqc(struct igb_adapter *adapter)
2631{
2632 struct e1000_hw *hw = &adapter->hw;
2633 u32 mrqc, rxcsum;
2634 u32 j, num_rx_queues, shift = 0, shift2 = 0;
2635 union e1000_reta {
2636 u32 dword;
2637 u8 bytes[4];
2638 } reta;
2639 static const u8 rsshash[40] = {
2640 0x6d, 0x5a, 0x56, 0xda, 0x25, 0x5b, 0x0e, 0xc2, 0x41, 0x67,
2641 0x25, 0x3d, 0x43, 0xa3, 0x8f, 0xb0, 0xd0, 0xca, 0x2b, 0xcb,
2642 0xae, 0x7b, 0x30, 0xb4, 0x77, 0xcb, 0x2d, 0xa3, 0x80, 0x30,
2643 0xf2, 0x0c, 0x6a, 0x42, 0xb7, 0x3b, 0xbe, 0xac, 0x01, 0xfa };
2644
2645 /* Fill out hash function seeds */
2646 for (j = 0; j < 10; j++) {
2647 u32 rsskey = rsshash[(j * 4)];
2648 rsskey |= rsshash[(j * 4) + 1] << 8;
2649 rsskey |= rsshash[(j * 4) + 2] << 16;
2650 rsskey |= rsshash[(j * 4) + 3] << 24;
2651 array_wr32(E1000_RSSRK(0), j, rsskey);
2652 }
2653
a99955fc 2654 num_rx_queues = adapter->rss_queues;
06cf2666
AD		 2655
2656 if (adapter->vfs_allocated_count) {
2657 /* 82575 and 82576 supports 2 RSS queues for VMDq */
2658 switch (hw->mac.type) {
d2ba2ed8 2659 case e1000_i350:
55cac248
AD		 2660 case e1000_82580:
2661 num_rx_queues = 1;
2662 shift = 0;
2663 break;
06cf2666
AD		 2664 case e1000_82576:
2665 shift = 3;
2666 num_rx_queues = 2;
2667 break;
2668 case e1000_82575:
2669 shift = 2;
2670 shift2 = 6;
2671 default:
2672 break;
2673 }
2674 } else {
2675 if (hw->mac.type == e1000_82575)
2676 shift = 6;
2677 }
2678
2679 for (j = 0; j < (32 * 4); j++) {
2680 reta.bytes[j & 3] = (j % num_rx_queues) << shift;
2681 if (shift2)
2682 reta.bytes[j & 3] |= num_rx_queues << shift2;
2683 if ((j & 3) == 3)
2684 wr32(E1000_RETA(j >> 2), reta.dword);
2685 }
2686
2687 /*
2688 * Disable raw packet checksumming so that RSS hash is placed in
2689 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
2690 * offloads as they are enabled by default
2691 */
2692 rxcsum = rd32(E1000_RXCSUM);
2693 rxcsum |= E1000_RXCSUM_PCSD;
2694
2695 if (adapter->hw.mac.type >= e1000_82576)
2696 /* Enable Receive Checksum Offload for SCTP */
2697 rxcsum |= E1000_RXCSUM_CRCOFL;
2698
2699 /* Don't need to set TUOFL or IPOFL, they default to 1 */
2700 wr32(E1000_RXCSUM, rxcsum);
2701
2702 /* If VMDq is enabled then we set the appropriate mode for that, else
2703 * we default to RSS so that an RSS hash is calculated per packet even
2704 * if we are only using one queue */
2705 if (adapter->vfs_allocated_count) {
2706 if (hw->mac.type > e1000_82575) {
2707 /* Set the default pool for the PF's first queue */
2708 u32 vtctl = rd32(E1000_VT_CTL);
2709 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
2710 E1000_VT_CTL_DISABLE_DEF_POOL);
2711 vtctl |= adapter->vfs_allocated_count <<
2712 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
2713 wr32(E1000_VT_CTL, vtctl);
2714 }
a99955fc 2715 if (adapter->rss_queues > 1)
06cf2666
AD		 2716 mrqc = E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
2717 else
2718 mrqc = E1000_MRQC_ENABLE_VMDQ;
2719 } else {
2720 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
2721 }
2722 igb_vmm_control(adapter);
2723
2724 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2725 E1000_MRQC_RSS_FIELD_IPV4_TCP);
2726 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2727 E1000_MRQC_RSS_FIELD_IPV6_TCP);
2728 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
2729 E1000_MRQC_RSS_FIELD_IPV6_UDP);
2730 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2731 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2732
2733 wr32(E1000_MRQC, mrqc);
2734}
2735
9d5c8243
AK		 2736/**
2737 * igb_setup_rctl - configure the receive control registers
2738 * @adapter: Board private structure
2739 **/
d7ee5b3a 2740void igb_setup_rctl(struct igb_adapter *adapter)
9d5c8243
AK		 2741{
2742 struct e1000_hw *hw = &adapter->hw;
2743 u32 rctl;
9d5c8243
AK		 2744
2745 rctl = rd32(E1000_RCTL);
2746
2747 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 2748 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 2749
69d728ba 2750 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 2751 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 2752
87cb7e8c
AK		 2753 /*
2754 * enable stripping of CRC. It's unlikely this will break BMC
2755 * redirection as it did with e1000. Newer features require
2756 * that the HW strips the CRC.
73cd78f1 2757 */
87cb7e8c 2758 rctl |= E1000_RCTL_SECRC;
9d5c8243 2759
559e9c49 2760 /* disable store bad packets and clear size bits. */
ec54d7d6 2761 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 2762
6ec43fe6
AD		 2763 /* enable LPE to prevent packets larger than max_frame_size */
2764 rctl |= E1000_RCTL_LPE;
9d5c8243 2765
952f72a8
AD		 2766 /* disable queue 0 to prevent tail write w/o re-config */
2767 wr32(E1000_RXDCTL(0), 0);
9d5c8243 2768
e1739522
AD		 2769 /* Attention!!! For SR-IOV PF driver operations you must enable
2770 * queue drop for all VF and PF queues to prevent head of line blocking
2771 * if an un-trusted VF does not provide descriptors to hardware.
2772 */
2773 if (adapter->vfs_allocated_count) {
e1739522
AD		 2774 /* set all queue drop enable bits */
2775 wr32(E1000_QDE, ALL_QUEUES);
e1739522
AD		 2776 }
2777
9d5c8243
AK		 2778 wr32(E1000_RCTL, rctl);
2779}
2780
7d5753f0
AD		 2781static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
2782 int vfn)
2783{
2784 struct e1000_hw *hw = &adapter->hw;
2785 u32 vmolr;
2786
2787 /* if it isn't the PF check to see if VFs are enabled and
2788 * increase the size to support vlan tags */
2789 if (vfn < adapter->vfs_allocated_count &&
2790 adapter->vf_data[vfn].vlans_enabled)
2791 size += VLAN_TAG_SIZE;
2792
2793 vmolr = rd32(E1000_VMOLR(vfn));
2794 vmolr &= ~E1000_VMOLR_RLPML_MASK;
2795 vmolr |= size | E1000_VMOLR_LPE;
2796 wr32(E1000_VMOLR(vfn), vmolr);
2797
2798 return 0;
2799}
2800
e1739522
AD		 2801/**
2802 * igb_rlpml_set - set maximum receive packet size
2803 * @adapter: board private structure
2804 *
2805 * Configure maximum receivable packet size.
2806 **/
2807static void igb_rlpml_set(struct igb_adapter *adapter)
2808{
2809 u32 max_frame_size = adapter->max_frame_size;
2810 struct e1000_hw *hw = &adapter->hw;
2811 u16 pf_id = adapter->vfs_allocated_count;
2812
2813 if (adapter->vlgrp)
2814 max_frame_size += VLAN_TAG_SIZE;
2815
2816 /* if vfs are enabled we set RLPML to the largest possible request
2817 * size and set the VMOLR RLPML to the size we need */
2818 if (pf_id) {
2819 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
7d5753f0 2820 max_frame_size = MAX_JUMBO_FRAME_SIZE;
e1739522
AD		 2821 }
2822
2823 wr32(E1000_RLPML, max_frame_size);
2824}
2825
8151d294
WM		 2826static inline void igb_set_vmolr(struct igb_adapter *adapter,
2827 int vfn, bool aupe)
7d5753f0
AD		 2828{
2829 struct e1000_hw *hw = &adapter->hw;
2830 u32 vmolr;
2831
2832 /*
2833 * This register exists only on 82576 and newer so if we are older then
2834 * we should exit and do nothing
2835 */
2836 if (hw->mac.type < e1000_82576)
2837 return;
2838
2839 vmolr = rd32(E1000_VMOLR(vfn));
8151d294
WM		 2840 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
2841 if (aupe)
2842 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
2843 else
2844 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
7d5753f0
AD		 2845
2846 /* clear all bits that might not be set */
2847 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
2848
a99955fc 2849 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
7d5753f0
AD		 2850 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
2851 /*
2852 * for VMDq only allow the VFs and pool 0 to accept broadcast and
2853 * multicast packets
2854 */
2855 if (vfn <= adapter->vfs_allocated_count)
2856 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
2857
2858 wr32(E1000_VMOLR(vfn), vmolr);
2859}
2860
85b430b4
AD		 2861/**
2862 * igb_configure_rx_ring - Configure a receive ring after Reset
2863 * @adapter: board private structure
2864 * @ring: receive ring to be configured
2865 *
2866 * Configure the Rx unit of the MAC after a reset.
2867 **/
d7ee5b3a
AD		 2868void igb_configure_rx_ring(struct igb_adapter *adapter,
2869 struct igb_ring *ring)
85b430b4
AD		 2870{
2871 struct e1000_hw *hw = &adapter->hw;
2872 u64 rdba = ring->dma;
2873 int reg_idx = ring->reg_idx;
952f72a8 2874 u32 srrctl, rxdctl;
85b430b4
AD		 2875
2876 /* disable the queue */
2877 rxdctl = rd32(E1000_RXDCTL(reg_idx));
2878 wr32(E1000_RXDCTL(reg_idx),
2879 rxdctl & ~E1000_RXDCTL_QUEUE_ENABLE);
2880
2881 /* Set DMA base address registers */
2882 wr32(E1000_RDBAL(reg_idx),
2883 rdba & 0x00000000ffffffffULL);
2884 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
2885 wr32(E1000_RDLEN(reg_idx),
2886 ring->count * sizeof(union e1000_adv_rx_desc));
2887
2888 /* initialize head and tail */
fce99e34
AD		 2889 ring->head = hw->hw_addr + E1000_RDH(reg_idx);
2890 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
2891 writel(0, ring->head);
2892 writel(0, ring->tail);
85b430b4 2893
952f72a8 2894 /* set descriptor configuration */
4c844851
AD		 2895 if (ring->rx_buffer_len < IGB_RXBUFFER_1024) {
2896 srrctl = ALIGN(ring->rx_buffer_len, 64) <<
952f72a8
AD		 2897 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2898#if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
2899 srrctl |= IGB_RXBUFFER_16384 >>
2900 E1000_SRRCTL_BSIZEPKT_SHIFT;
2901#else
2902 srrctl |= (PAGE_SIZE / 2) >>
2903 E1000_SRRCTL_BSIZEPKT_SHIFT;
2904#endif
2905 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2906 } else {
4c844851 2907 srrctl = ALIGN(ring->rx_buffer_len, 1024) >>
952f72a8
AD		 2908 E1000_SRRCTL_BSIZEPKT_SHIFT;
2909 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2910 }
757b77e2
NN		 2911 if (hw->mac.type == e1000_82580)
2912 srrctl |= E1000_SRRCTL_TIMESTAMP;
e6bdb6fe
NN		 2913 /* Only set Drop Enable if we are supporting multiple queues */
2914 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
2915 srrctl |= E1000_SRRCTL_DROP_EN;
952f72a8
AD		 2916
2917 wr32(E1000_SRRCTL(reg_idx), srrctl);
2918
7d5753f0 2919 /* set filtering for VMDQ pools */
8151d294 2920 igb_set_vmolr(adapter, reg_idx & 0x7, true);
7d5753f0 2921
85b430b4
AD		 2922 /* enable receive descriptor fetching */
2923 rxdctl = rd32(E1000_RXDCTL(reg_idx));
2924 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2925 rxdctl &= 0xFFF00000;
2926 rxdctl |= IGB_RX_PTHRESH;
2927 rxdctl |= IGB_RX_HTHRESH << 8;
2928 rxdctl |= IGB_RX_WTHRESH << 16;
2929 wr32(E1000_RXDCTL(reg_idx), rxdctl);
2930}
2931
9d5c8243
AK		 2932/**
2933 * igb_configure_rx - Configure receive Unit after Reset
2934 * @adapter: board private structure
2935 *
2936 * Configure the Rx unit of the MAC after a reset.
2937 **/
2938static void igb_configure_rx(struct igb_adapter *adapter)
2939{
9107584e 2940 int i;
9d5c8243 2941
68d480c4
AD		 2942 /* set UTA to appropriate mode */
2943 igb_set_uta(adapter);
2944
26ad9178
AD		 2945 /* set the correct pool for the PF default MAC address in entry 0 */
2946 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
2947 adapter->vfs_allocated_count);
2948
06cf2666
AD		 2949 /* Setup the HW Rx Head and Tail Descriptor Pointers and
2950 * the Base and Length of the Rx Descriptor Ring */
2951 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 2952 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
9d5c8243
AK		 2953}
2954
2955/**
2956 * igb_free_tx_resources - Free Tx Resources per Queue
9d5c8243
AK		 2957 * @tx_ring: Tx descriptor ring for a specific queue
2958 *
2959 * Free all transmit software resources
2960 **/
68fd9910 2961void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 2962{
3b644cf6 2963 igb_clean_tx_ring(tx_ring);
9d5c8243
AK		 2964
2965 vfree(tx_ring->buffer_info);
2966 tx_ring->buffer_info = NULL;
2967
439705e1
AD		 2968 /* if not set, then don't free */
2969 if (!tx_ring->desc)
2970 return;
2971
59d71989
AD		 2972 dma_free_coherent(tx_ring->dev, tx_ring->size,
2973 tx_ring->desc, tx_ring->dma);
9d5c8243
AK		 2974
2975 tx_ring->desc = NULL;
2976}
2977
2978/**
2979 * igb_free_all_tx_resources - Free Tx Resources for All Queues
2980 * @adapter: board private structure
2981 *
2982 * Free all transmit software resources
2983 **/
2984static void igb_free_all_tx_resources(struct igb_adapter *adapter)
2985{
2986 int i;
2987
2988 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 2989 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 2990}
2991
b1a436c3
AD		 2992void igb_unmap_and_free_tx_resource(struct igb_ring *tx_ring,
2993 struct igb_buffer *buffer_info)
9d5c8243 2994{
6366ad33
AD		 2995 if (buffer_info->dma) {
2996 if (buffer_info->mapped_as_page)
59d71989 2997 dma_unmap_page(tx_ring->dev,
6366ad33
AD		 2998 buffer_info->dma,
2999 buffer_info->length,
59d71989 3000 DMA_TO_DEVICE);
6366ad33 3001 else
59d71989 3002 dma_unmap_single(tx_ring->dev,
6366ad33
AD		 3003 buffer_info->dma,
3004 buffer_info->length,
59d71989 3005 DMA_TO_DEVICE);
6366ad33
AD		 3006 buffer_info->dma = 0;
3007 }
9d5c8243
AK		 3008 if (buffer_info->skb) {
3009 dev_kfree_skb_any(buffer_info->skb);
3010 buffer_info->skb = NULL;
3011 }
3012 buffer_info->time_stamp = 0;
6366ad33
AD		 3013 buffer_info->length = 0;
3014 buffer_info->next_to_watch = 0;
3015 buffer_info->mapped_as_page = false;
9d5c8243
AK		 3016}
3017
3018/**
3019 * igb_clean_tx_ring - Free Tx Buffers
9d5c8243
AK		 3020 * @tx_ring: ring to be cleaned
3021 **/
3b644cf6 3022static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243
AK		 3023{
3024 struct igb_buffer *buffer_info;
3025 unsigned long size;
3026 unsigned int i;
3027
3028 if (!tx_ring->buffer_info)
3029 return;
3030 /* Free all the Tx ring sk_buffs */
3031
3032 for (i = 0; i < tx_ring->count; i++) {
3033 buffer_info = &tx_ring->buffer_info[i];
80785298 3034 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
9d5c8243
AK		 3035 }
3036
3037 size = sizeof(struct igb_buffer) * tx_ring->count;
3038 memset(tx_ring->buffer_info, 0, size);
3039
3040 /* Zero out the descriptor ring */
9d5c8243
AK		 3041 memset(tx_ring->desc, 0, tx_ring->size);
3042
3043 tx_ring->next_to_use = 0;
3044 tx_ring->next_to_clean = 0;
9d5c8243
AK		 3045}
3046
3047/**
3048 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3049 * @adapter: board private structure
3050 **/
3051static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3052{
3053 int i;
3054
3055 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3056 igb_clean_tx_ring(adapter->tx_ring[i]);
9d5c8243
AK		 3057}
3058
3059/**
3060 * igb_free_rx_resources - Free Rx Resources
9d5c8243
AK		 3061 * @rx_ring: ring to clean the resources from
3062 *
3063 * Free all receive software resources
3064 **/
68fd9910 3065void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3066{
3b644cf6 3067 igb_clean_rx_ring(rx_ring);
9d5c8243
AK		 3068
3069 vfree(rx_ring->buffer_info);
3070 rx_ring->buffer_info = NULL;
3071
439705e1
AD		 3072 /* if not set, then don't free */
3073 if (!rx_ring->desc)
3074 return;
3075
59d71989
AD		 3076 dma_free_coherent(rx_ring->dev, rx_ring->size,
3077 rx_ring->desc, rx_ring->dma);
9d5c8243
AK		 3078
3079 rx_ring->desc = NULL;
3080}
3081
3082/**
3083 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3084 * @adapter: board private structure
3085 *
3086 * Free all receive software resources
3087 **/
3088static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3089{
3090 int i;
3091
3092 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3093 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3094}
3095
3096/**
3097 * igb_clean_rx_ring - Free Rx Buffers per Queue
9d5c8243
AK		 3098 * @rx_ring: ring to free buffers from
3099 **/
3b644cf6 3100static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243
AK		 3101{
3102 struct igb_buffer *buffer_info;
9d5c8243
AK		 3103 unsigned long size;
3104 unsigned int i;
3105
3106 if (!rx_ring->buffer_info)
3107 return;
439705e1 3108
9d5c8243
AK		 3109 /* Free all the Rx ring sk_buffs */
3110 for (i = 0; i < rx_ring->count; i++) {
3111 buffer_info = &rx_ring->buffer_info[i];
3112 if (buffer_info->dma) {
59d71989 3113 dma_unmap_single(rx_ring->dev,
80785298 3114 buffer_info->dma,
4c844851 3115 rx_ring->rx_buffer_len,
59d71989 3116 DMA_FROM_DEVICE);
9d5c8243
AK		 3117 buffer_info->dma = 0;
3118 }
3119
3120 if (buffer_info->skb) {
3121 dev_kfree_skb(buffer_info->skb);
3122 buffer_info->skb = NULL;
3123 }
6ec43fe6 3124 if (buffer_info->page_dma) {
59d71989 3125 dma_unmap_page(rx_ring->dev,
80785298 3126 buffer_info->page_dma,
6ec43fe6 3127 PAGE_SIZE / 2,
59d71989 3128 DMA_FROM_DEVICE);
6ec43fe6
AD		 3129 buffer_info->page_dma = 0;
3130 }
9d5c8243 3131 if (buffer_info->page) {
9d5c8243
AK		 3132 put_page(buffer_info->page);
3133 buffer_info->page = NULL;
bf36c1a0 3134 buffer_info->page_offset = 0;
9d5c8243
AK		 3135 }
3136 }
3137
9d5c8243
AK		 3138 size = sizeof(struct igb_buffer) * rx_ring->count;
3139 memset(rx_ring->buffer_info, 0, size);
3140
3141 /* Zero out the descriptor ring */
3142 memset(rx_ring->desc, 0, rx_ring->size);
3143
3144 rx_ring->next_to_clean = 0;
3145 rx_ring->next_to_use = 0;
9d5c8243
AK		 3146}
3147
3148/**
3149 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3150 * @adapter: board private structure
3151 **/
3152static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3153{
3154 int i;
3155
3156 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3157 igb_clean_rx_ring(adapter->rx_ring[i]);
9d5c8243
AK		 3158}
3159
3160/**
3161 * igb_set_mac - Change the Ethernet Address of the NIC
3162 * @netdev: network interface device structure
3163 * @p: pointer to an address structure
3164 *
3165 * Returns 0 on success, negative on failure
3166 **/
3167static int igb_set_mac(struct net_device *netdev, void *p)
3168{
3169 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 3170 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 3171 struct sockaddr *addr = p;
3172
3173 if (!is_valid_ether_addr(addr->sa_data))
3174 return -EADDRNOTAVAIL;
3175
3176 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 3177 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 3178
26ad9178
AD		 3179 /* set the correct pool for the new PF MAC address in entry 0 */
3180 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
3181 adapter->vfs_allocated_count);
e1739522 3182
9d5c8243
AK		 3183 return 0;
3184}
3185
3186/**
68d480c4 3187 * igb_write_mc_addr_list - write multicast addresses to MTA
9d5c8243
AK		 3188 * @netdev: network interface device structure
3189 *
68d480c4
AD		 3190 * Writes multicast address list to the MTA hash table.
3191 * Returns: -ENOMEM on failure
3192 * 0 on no addresses written
3193 * X on writing X addresses to MTA
9d5c8243 3194 **/
68d480c4 3195static int igb_write_mc_addr_list(struct net_device *netdev)
9d5c8243
AK		 3196{
3197 struct igb_adapter *adapter = netdev_priv(netdev);
3198 struct e1000_hw *hw = &adapter->hw;
22bedad3 3199 struct netdev_hw_addr *ha;
68d480c4 3200 u8 *mta_list;
9d5c8243
AK		 3201 int i;
3202
4cd24eaf 3203 if (netdev_mc_empty(netdev)) {
68d480c4
AD		 3204 /* nothing to program, so clear mc list */
3205 igb_update_mc_addr_list(hw, NULL, 0);
3206 igb_restore_vf_multicasts(adapter);
3207 return 0;
3208 }
9d5c8243 3209
4cd24eaf 3210 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
68d480c4
AD		 3211 if (!mta_list)
3212 return -ENOMEM;
ff41f8dc 3213
68d480c4 3214 /* The shared function expects a packed array of only addresses. */
48e2f183 3215 i = 0;
22bedad3
JP		 3216 netdev_for_each_mc_addr(ha, netdev)
3217 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
68d480c4 3218
68d480c4
AD		 3219 igb_update_mc_addr_list(hw, mta_list, i);
3220 kfree(mta_list);
3221
4cd24eaf 3222 return netdev_mc_count(netdev);
68d480c4
AD		 3223}
3224
3225/**
3226 * igb_write_uc_addr_list - write unicast addresses to RAR table
3227 * @netdev: network interface device structure
3228 *
3229 * Writes unicast address list to the RAR table.
3230 * Returns: -ENOMEM on failure/insufficient address space
3231 * 0 on no addresses written
3232 * X on writing X addresses to the RAR table
3233 **/
3234static int igb_write_uc_addr_list(struct net_device *netdev)
3235{
3236 struct igb_adapter *adapter = netdev_priv(netdev);
3237 struct e1000_hw *hw = &adapter->hw;
3238 unsigned int vfn = adapter->vfs_allocated_count;
3239 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3240 int count = 0;
3241
3242 /* return ENOMEM indicating insufficient memory for addresses */
32e7bfc4 3243 if (netdev_uc_count(netdev) > rar_entries)
68d480c4 3244 return -ENOMEM;
9d5c8243 3245
32e7bfc4 3246 if (!netdev_uc_empty(netdev) && rar_entries) {
ff41f8dc 3247 struct netdev_hw_addr *ha;
32e7bfc4
JP		 3248
3249 netdev_for_each_uc_addr(ha, netdev) {
ff41f8dc
AD		 3250 if (!rar_entries)
3251 break;
26ad9178
AD		 3252 igb_rar_set_qsel(adapter, ha->addr,
3253 rar_entries--,
68d480c4
AD		 3254 vfn);
3255 count++;
ff41f8dc
AD		 3256 }
3257 }
3258 /* write the addresses in reverse order to avoid write combining */
3259 for (; rar_entries > 0 ; rar_entries--) {
3260 wr32(E1000_RAH(rar_entries), 0);
3261 wr32(E1000_RAL(rar_entries), 0);
3262 }
3263 wrfl();
3264
68d480c4
AD		 3265 return count;
3266}
3267
3268/**
3269 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3270 * @netdev: network interface device structure
3271 *
3272 * The set_rx_mode entry point is called whenever the unicast or multicast
3273 * address lists or the network interface flags are updated. This routine is
3274 * responsible for configuring the hardware for proper unicast, multicast,
3275 * promiscuous mode, and all-multi behavior.
3276 **/
3277static void igb_set_rx_mode(struct net_device *netdev)
3278{
3279 struct igb_adapter *adapter = netdev_priv(netdev);
3280 struct e1000_hw *hw = &adapter->hw;
3281 unsigned int vfn = adapter->vfs_allocated_count;
3282 u32 rctl, vmolr = 0;
3283 int count;
3284
3285 /* Check for Promiscuous and All Multicast modes */
3286 rctl = rd32(E1000_RCTL);
3287
3288 /* clear the effected bits */
3289 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
3290
3291 if (netdev->flags & IFF_PROMISC) {
3292 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3293 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
3294 } else {
3295 if (netdev->flags & IFF_ALLMULTI) {
3296 rctl |= E1000_RCTL_MPE;
3297 vmolr |= E1000_VMOLR_MPME;
3298 } else {
3299 /*
3300 * Write addresses to the MTA, if the attempt fails
3301 * then we should just turn on promiscous mode so
3302 * that we can at least receive multicast traffic
3303 */
3304 count = igb_write_mc_addr_list(netdev);
3305 if (count < 0) {
3306 rctl |= E1000_RCTL_MPE;
3307 vmolr |= E1000_VMOLR_MPME;
3308 } else if (count) {
3309 vmolr |= E1000_VMOLR_ROMPE;
3310 }
3311 }
3312 /*
3313 * Write addresses to available RAR registers, if there is not
3314 * sufficient space to store all the addresses then enable
3315 * unicast promiscous mode
3316 */
3317 count = igb_write_uc_addr_list(netdev);
3318 if (count < 0) {
3319 rctl |= E1000_RCTL_UPE;
3320 vmolr |= E1000_VMOLR_ROPE;
3321 }
3322 rctl |= E1000_RCTL_VFE;
28fc06f5 3323 }
68d480c4 3324 wr32(E1000_RCTL, rctl);
28fc06f5 3325
68d480c4
AD		 3326 /*
3327 * In order to support SR-IOV and eventually VMDq it is necessary to set
3328 * the VMOLR to enable the appropriate modes. Without this workaround
3329 * we will have issues with VLAN tag stripping not being done for frames
3330 * that are only arriving because we are the default pool
3331 */
3332 if (hw->mac.type < e1000_82576)
28fc06f5 3333 return;
9d5c8243 3334
68d480c4
AD		 3335 vmolr |= rd32(E1000_VMOLR(vfn)) &
3336 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
3337 wr32(E1000_VMOLR(vfn), vmolr);
28fc06f5 3338 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 3339}
3340
3341/* Need to wait a few seconds after link up to get diagnostic information from
3342 * the phy */
3343static void igb_update_phy_info(unsigned long data)
3344{
3345 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 3346 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 3347}
3348
4d6b725e
AD		 3349/**
3350 * igb_has_link - check shared code for link and determine up/down
3351 * @adapter: pointer to driver private info
3352 **/
3145535a 3353bool igb_has_link(struct igb_adapter *adapter)
4d6b725e
AD		 3354{
3355 struct e1000_hw *hw = &adapter->hw;
3356 bool link_active = false;
3357 s32 ret_val = 0;
3358
3359 /* get_link_status is set on LSC (link status) interrupt or
3360 * rx sequence error interrupt. get_link_status will stay
3361 * false until the e1000_check_for_link establishes link
3362 * for copper adapters ONLY
3363 */
3364 switch (hw->phy.media_type) {
3365 case e1000_media_type_copper:
3366 if (hw->mac.get_link_status) {
3367 ret_val = hw->mac.ops.check_for_link(hw);
3368 link_active = !hw->mac.get_link_status;
3369 } else {
3370 link_active = true;
3371 }
3372 break;
4d6b725e
AD		 3373 case e1000_media_type_internal_serdes:
3374 ret_val = hw->mac.ops.check_for_link(hw);
3375 link_active = hw->mac.serdes_has_link;
3376 break;
3377 default:
3378 case e1000_media_type_unknown:
3379 break;
3380 }
3381
3382 return link_active;
3383}
3384
9d5c8243
AK		 3385/**
3386 * igb_watchdog - Timer Call-back
3387 * @data: pointer to adapter cast into an unsigned long
3388 **/
3389static void igb_watchdog(unsigned long data)
3390{
3391 struct igb_adapter *adapter = (struct igb_adapter *)data;
3392 /* Do the rest outside of interrupt context */
3393 schedule_work(&adapter->watchdog_task);
3394}
3395
3396static void igb_watchdog_task(struct work_struct *work)
3397{
3398 struct igb_adapter *adapter = container_of(work,
559e9c49
AD		 3399 struct igb_adapter,
3400 watchdog_task);
9d5c8243 3401 struct e1000_hw *hw = &adapter->hw;
9d5c8243 3402 struct net_device *netdev = adapter->netdev;
9d5c8243 3403 u32 link;
7a6ea550 3404 int i;
9d5c8243 3405
4d6b725e 3406 link = igb_has_link(adapter);
9d5c8243
AK		 3407 if (link) {
3408 if (!netif_carrier_ok(netdev)) {
3409 u32 ctrl;
330a6d6a
AD		 3410 hw->mac.ops.get_speed_and_duplex(hw,
3411 &adapter->link_speed,
3412 &adapter->link_duplex);
9d5c8243
AK		 3413
3414 ctrl = rd32(E1000_CTRL);
527d47c1
AD		 3415 /* Links status message must follow this format */
3416 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
9d5c8243 3417 "Flow Control: %s\n",
559e9c49
AD		 3418 netdev->name,
3419 adapter->link_speed,
3420 adapter->link_duplex == FULL_DUPLEX ?
9d5c8243 3421 "Full Duplex" : "Half Duplex",
559e9c49
AD		 3422 ((ctrl & E1000_CTRL_TFCE) &&
3423 (ctrl & E1000_CTRL_RFCE)) ? "RX/TX" :
3424 ((ctrl & E1000_CTRL_RFCE) ? "RX" :
3425 ((ctrl & E1000_CTRL_TFCE) ? "TX" : "None")));
9d5c8243 3426
d07f3e37 3427 /* adjust timeout factor according to speed/duplex */
9d5c8243
AK		 3428 adapter->tx_timeout_factor = 1;
3429 switch (adapter->link_speed) {
3430 case SPEED_10:
9d5c8243
AK		 3431 adapter->tx_timeout_factor = 14;
3432 break;
3433 case SPEED_100:
9d5c8243
AK		 3434 /* maybe add some timeout factor ? */
3435 break;
3436 }
3437
3438 netif_carrier_on(netdev);
9d5c8243 3439
4ae196df
AD		 3440 igb_ping_all_vfs(adapter);
3441
4b1a9877 3442 /* link state has changed, schedule phy info update */
9d5c8243
AK		 3443 if (!test_bit(__IGB_DOWN, &adapter->state))
3444 mod_timer(&adapter->phy_info_timer,
3445 round_jiffies(jiffies + 2 * HZ));
3446 }
3447 } else {
3448 if (netif_carrier_ok(netdev)) {
3449 adapter->link_speed = 0;
3450 adapter->link_duplex = 0;
527d47c1
AD		 3451 /* Links status message must follow this format */
3452 printk(KERN_INFO "igb: %s NIC Link is Down\n",
3453 netdev->name);
9d5c8243 3454 netif_carrier_off(netdev);
4b1a9877 3455
4ae196df
AD		 3456 igb_ping_all_vfs(adapter);
3457
4b1a9877 3458 /* link state has changed, schedule phy info update */
9d5c8243
AK		 3459 if (!test_bit(__IGB_DOWN, &adapter->state))
3460 mod_timer(&adapter->phy_info_timer,
3461 round_jiffies(jiffies + 2 * HZ));
3462 }
3463 }
3464
9d5c8243 3465 igb_update_stats(adapter);
9d5c8243 3466
dbabb065 3467 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 3468 struct igb_ring *tx_ring = adapter->tx_ring[i];
dbabb065 3469 if (!netif_carrier_ok(netdev)) {
9d5c8243
AK		 3470 /* We've lost link, so the controller stops DMA,
3471 * but we've got queued Tx work that's never going
3472 * to get done, so reset controller to flush Tx.
3473 * (Do the reset outside of interrupt context). */
dbabb065
AD		 3474 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
3475 adapter->tx_timeout_count++;
3476 schedule_work(&adapter->reset_task);
3477 /* return immediately since reset is imminent */
3478 return;
3479 }
9d5c8243 3480 }
9d5c8243 3481
dbabb065
AD		 3482 /* Force detection of hung controller every watchdog period */
3483 tx_ring->detect_tx_hung = true;
3484 }
f7ba205e 3485
9d5c8243 3486 /* Cause software interrupt to ensure rx ring is cleaned */
7a6ea550 3487 if (adapter->msix_entries) {
047e0030
AD		 3488 u32 eics = 0;
3489 for (i = 0; i < adapter->num_q_vectors; i++) {
3490 struct igb_q_vector *q_vector = adapter->q_vector[i];
3491 eics |= q_vector->eims_value;
3492 }
7a6ea550
AD		 3493 wr32(E1000_EICS, eics);
3494 } else {
3495 wr32(E1000_ICS, E1000_ICS_RXDMT0);
3496 }
9d5c8243 3497
9d5c8243
AK		 3498 /* Reset the timer */
3499 if (!test_bit(__IGB_DOWN, &adapter->state))
3500 mod_timer(&adapter->watchdog_timer,
3501 round_jiffies(jiffies + 2 * HZ));
3502}
3503
3504enum latency_range {
3505 lowest_latency = 0,
3506 low_latency = 1,
3507 bulk_latency = 2,
3508 latency_invalid = 255
3509};
3510
6eb5a7f1
AD		 3511/**
3512 * igb_update_ring_itr - update the dynamic ITR value based on packet size
3513 *
3514 * Stores a new ITR value based on strictly on packet size. This
3515 * algorithm is less sophisticated than that used in igb_update_itr,
3516 * due to the difficulty of synchronizing statistics across multiple
3517 * receive rings. The divisors and thresholds used by this fuction
3518 * were determined based on theoretical maximum wire speed and testing
3519 * data, in order to minimize response time while increasing bulk
3520 * throughput.
3521 * This functionality is controlled by the InterruptThrottleRate module
3522 * parameter (see igb_param.c)
3523 * NOTE: This function is called only when operating in a multiqueue
3524 * receive environment.
047e0030 3525 * @q_vector: pointer to q_vector
6eb5a7f1 3526 **/
047e0030 3527static void igb_update_ring_itr(struct igb_q_vector *q_vector)
9d5c8243 3528{
047e0030 3529 int new_val = q_vector->itr_val;
6eb5a7f1 3530 int avg_wire_size = 0;
047e0030 3531 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 3532
6eb5a7f1
AD		 3533 /* For non-gigabit speeds, just fix the interrupt rate at 4000
3534 * ints/sec - ITR timer value of 120 ticks.
3535 */
3536 if (adapter->link_speed != SPEED_1000) {
047e0030 3537 new_val = 976;
6eb5a7f1 3538 goto set_itr_val;
9d5c8243 3539 }
047e0030
AD		 3540
3541 if (q_vector->rx_ring && q_vector->rx_ring->total_packets) {
3542 struct igb_ring *ring = q_vector->rx_ring;
3543 avg_wire_size = ring->total_bytes / ring->total_packets;
3544 }
3545
3546 if (q_vector->tx_ring && q_vector->tx_ring->total_packets) {
3547 struct igb_ring *ring = q_vector->tx_ring;
3548 avg_wire_size = max_t(u32, avg_wire_size,
3549 (ring->total_bytes /
3550 ring->total_packets));
3551 }
3552
3553 /* if avg_wire_size isn't set no work was done */
3554 if (!avg_wire_size)
3555 goto clear_counts;
9d5c8243 3556
6eb5a7f1
AD		 3557 /* Add 24 bytes to size to account for CRC, preamble, and gap */
3558 avg_wire_size += 24;
3559
3560 /* Don't starve jumbo frames */
3561 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 3562
6eb5a7f1
AD		 3563 /* Give a little boost to mid-size frames */
3564 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
3565 new_val = avg_wire_size / 3;
3566 else
3567 new_val = avg_wire_size / 2;
9d5c8243 3568
abe1c363
NN		 3569 /* when in itr mode 3 do not exceed 20K ints/sec */
3570 if (adapter->rx_itr_setting == 3 && new_val < 196)
3571 new_val = 196;
3572
6eb5a7f1 3573set_itr_val:
047e0030
AD		 3574 if (new_val != q_vector->itr_val) {
3575 q_vector->itr_val = new_val;
3576 q_vector->set_itr = 1;
9d5c8243 3577 }
6eb5a7f1 3578clear_counts:
047e0030
AD		 3579 if (q_vector->rx_ring) {
3580 q_vector->rx_ring->total_bytes = 0;
3581 q_vector->rx_ring->total_packets = 0;
3582 }
3583 if (q_vector->tx_ring) {
3584 q_vector->tx_ring->total_bytes = 0;
3585 q_vector->tx_ring->total_packets = 0;
3586 }
9d5c8243
AK		 3587}
3588
3589/**
3590 * igb_update_itr - update the dynamic ITR value based on statistics
3591 * Stores a new ITR value based on packets and byte
3592 * counts during the last interrupt. The advantage of per interrupt
3593 * computation is faster updates and more accurate ITR for the current
3594 * traffic pattern. Constants in this function were computed
3595 * based on theoretical maximum wire speed and thresholds were set based
3596 * on testing data as well as attempting to minimize response time
3597 * while increasing bulk throughput.
3598 * this functionality is controlled by the InterruptThrottleRate module
3599 * parameter (see igb_param.c)
3600 * NOTE: These calculations are only valid when operating in a single-
3601 * queue environment.
3602 * @adapter: pointer to adapter
047e0030 3603 * @itr_setting: current q_vector->itr_val
9d5c8243
AK		 3604 * @packets: the number of packets during this measurement interval
3605 * @bytes: the number of bytes during this measurement interval
3606 **/
3607static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
3608 int packets, int bytes)
3609{
3610 unsigned int retval = itr_setting;
3611
3612 if (packets == 0)
3613 goto update_itr_done;
3614
3615 switch (itr_setting) {
3616 case lowest_latency:
3617 /* handle TSO and jumbo frames */
3618 if (bytes/packets > 8000)
3619 retval = bulk_latency;
3620 else if ((packets < 5) && (bytes > 512))
3621 retval = low_latency;
3622 break;
3623 case low_latency: /* 50 usec aka 20000 ints/s */
3624 if (bytes > 10000) {
3625 /* this if handles the TSO accounting */
3626 if (bytes/packets > 8000) {
3627 retval = bulk_latency;
3628 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
3629 retval = bulk_latency;
3630 } else if ((packets > 35)) {
3631 retval = lowest_latency;
3632 }
3633 } else if (bytes/packets > 2000) {
3634 retval = bulk_latency;
3635 } else if (packets <= 2 && bytes < 512) {
3636 retval = lowest_latency;
3637 }
3638 break;
3639 case bulk_latency: /* 250 usec aka 4000 ints/s */
3640 if (bytes > 25000) {
3641 if (packets > 35)
3642 retval = low_latency;
1e5c3d21 3643 } else if (bytes < 1500) {
9d5c8243
AK		 3644 retval = low_latency;
3645 }
3646 break;
3647 }
3648
3649update_itr_done:
3650 return retval;
3651}
3652
6eb5a7f1 3653static void igb_set_itr(struct igb_adapter *adapter)
9d5c8243 3654{
047e0030 3655 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243 3656 u16 current_itr;
047e0030 3657 u32 new_itr = q_vector->itr_val;
9d5c8243
AK		 3658
3659 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
3660 if (adapter->link_speed != SPEED_1000) {
3661 current_itr = 0;
3662 new_itr = 4000;
3663 goto set_itr_now;
3664 }
3665
3666 adapter->rx_itr = igb_update_itr(adapter,
3667 adapter->rx_itr,
3025a446
AD		 3668 q_vector->rx_ring->total_packets,
3669 q_vector->rx_ring->total_bytes);
9d5c8243 3670
047e0030
AD		 3671 adapter->tx_itr = igb_update_itr(adapter,
3672 adapter->tx_itr,
3025a446
AD		 3673 q_vector->tx_ring->total_packets,
3674 q_vector->tx_ring->total_bytes);
047e0030 3675 current_itr = max(adapter->rx_itr, adapter->tx_itr);
9d5c8243 3676
6eb5a7f1 3677 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4fc82adf 3678 if (adapter->rx_itr_setting == 3 && current_itr == lowest_latency)
6eb5a7f1
AD		 3679 current_itr = low_latency;
3680
9d5c8243
AK		 3681 switch (current_itr) {
3682 /* counts and packets in update_itr are dependent on these numbers */
3683 case lowest_latency:
78b1f607 3684 new_itr = 56; /* aka 70,000 ints/sec */
9d5c8243
AK		 3685 break;
3686 case low_latency:
78b1f607 3687 new_itr = 196; /* aka 20,000 ints/sec */
9d5c8243
AK		 3688 break;
3689 case bulk_latency:
78b1f607 3690 new_itr = 980; /* aka 4,000 ints/sec */
9d5c8243
AK		 3691 break;
3692 default:
3693 break;
3694 }
3695
3696set_itr_now:
3025a446
AD		 3697 q_vector->rx_ring->total_bytes = 0;
3698 q_vector->rx_ring->total_packets = 0;
3699 q_vector->tx_ring->total_bytes = 0;
3700 q_vector->tx_ring->total_packets = 0;
6eb5a7f1 3701
047e0030 3702 if (new_itr != q_vector->itr_val) {
9d5c8243
AK		 3703 /* this attempts to bias the interrupt rate towards Bulk
3704 * by adding intermediate steps when interrupt rate is
3705 * increasing */
047e0030
AD		 3706 new_itr = new_itr > q_vector->itr_val ?
3707 max((new_itr * q_vector->itr_val) /
3708 (new_itr + (q_vector->itr_val >> 2)),
3709 new_itr) :
9d5c8243
AK		 3710 new_itr;
3711 /* Don't write the value here; it resets the adapter's
3712 * internal timer, and causes us to delay far longer than
3713 * we should between interrupts. Instead, we write the ITR
3714 * value at the beginning of the next interrupt so the timing
3715 * ends up being correct.
3716 */
047e0030
AD		 3717 q_vector->itr_val = new_itr;
3718 q_vector->set_itr = 1;
9d5c8243
AK		 3719 }
3720
3721 return;
3722}
3723
9d5c8243
AK		 3724#define IGB_TX_FLAGS_CSUM 0x00000001
3725#define IGB_TX_FLAGS_VLAN 0x00000002
3726#define IGB_TX_FLAGS_TSO 0x00000004
3727#define IGB_TX_FLAGS_IPV4 0x00000008
cdfd01fc
AD		 3728#define IGB_TX_FLAGS_TSTAMP 0x00000010
3729#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
3730#define IGB_TX_FLAGS_VLAN_SHIFT 16
9d5c8243 3731
85ad76b2 3732static inline int igb_tso_adv(struct igb_ring *tx_ring,
9d5c8243
AK		 3733 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
3734{
3735 struct e1000_adv_tx_context_desc *context_desc;
3736 unsigned int i;
3737 int err;
3738 struct igb_buffer *buffer_info;
3739 u32 info = 0, tu_cmd = 0;
91d4ee33
NN		 3740 u32 mss_l4len_idx;
3741 u8 l4len;
9d5c8243
AK		 3742
3743 if (skb_header_cloned(skb)) {
3744 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
3745 if (err)
3746 return err;
3747 }
3748
3749 l4len = tcp_hdrlen(skb);
3750 *hdr_len += l4len;
3751
3752 if (skb->protocol == htons(ETH_P_IP)) {
3753 struct iphdr *iph = ip_hdr(skb);
3754 iph->tot_len = 0;
3755 iph->check = 0;
3756 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
3757 iph->daddr, 0,
3758 IPPROTO_TCP,
3759 0);
8e1e8a47 3760 } else if (skb_is_gso_v6(skb)) {
9d5c8243
AK		 3761 ipv6_hdr(skb)->payload_len = 0;
3762 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
3763 &ipv6_hdr(skb)->daddr,
3764 0, IPPROTO_TCP, 0);
3765 }
3766
3767 i = tx_ring->next_to_use;
3768
3769 buffer_info = &tx_ring->buffer_info[i];
3770 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3771 /* VLAN MACLEN IPLEN */
3772 if (tx_flags & IGB_TX_FLAGS_VLAN)
3773 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
3774 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3775 *hdr_len += skb_network_offset(skb);
3776 info |= skb_network_header_len(skb);
3777 *hdr_len += skb_network_header_len(skb);
3778 context_desc->vlan_macip_lens = cpu_to_le32(info);
3779
3780 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
3781 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3782
3783 if (skb->protocol == htons(ETH_P_IP))
3784 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
3785 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3786
3787 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3788
3789 /* MSS L4LEN IDX */
3790 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
3791 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
3792
73cd78f1 3793 /* For 82575, context index must be unique per ring. */
85ad76b2
AD		 3794 if (tx_ring->flags & IGB_RING_FLAG_TX_CTX_IDX)
3795 mss_l4len_idx |= tx_ring->reg_idx << 4;
9d5c8243
AK		 3796
3797 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
3798 context_desc->seqnum_seed = 0;
3799
3800 buffer_info->time_stamp = jiffies;
0e014cb1 3801 buffer_info->next_to_watch = i;
9d5c8243
AK		 3802 buffer_info->dma = 0;
3803 i++;
3804 if (i == tx_ring->count)
3805 i = 0;
3806
3807 tx_ring->next_to_use = i;
3808
3809 return true;
3810}
3811
85ad76b2
AD		 3812static inline bool igb_tx_csum_adv(struct igb_ring *tx_ring,
3813 struct sk_buff *skb, u32 tx_flags)
9d5c8243
AK		 3814{
3815 struct e1000_adv_tx_context_desc *context_desc;
59d71989 3816 struct device *dev = tx_ring->dev;
9d5c8243
AK		 3817 struct igb_buffer *buffer_info;
3818 u32 info = 0, tu_cmd = 0;
80785298 3819 unsigned int i;
9d5c8243
AK		 3820
3821 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
3822 (tx_flags & IGB_TX_FLAGS_VLAN)) {
3823 i = tx_ring->next_to_use;
3824 buffer_info = &tx_ring->buffer_info[i];
3825 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3826
3827 if (tx_flags & IGB_TX_FLAGS_VLAN)
3828 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
cdfd01fc 3829
9d5c8243
AK		 3830 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3831 if (skb->ip_summed == CHECKSUM_PARTIAL)
3832 info |= skb_network_header_len(skb);
3833
3834 context_desc->vlan_macip_lens = cpu_to_le32(info);
3835
3836 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3837
3838 if (skb->ip_summed == CHECKSUM_PARTIAL) {
fa4a7ef3
AJ		 3839 __be16 protocol;
3840
3841 if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
3842 const struct vlan_ethhdr *vhdr =
3843 (const struct vlan_ethhdr*)skb->data;
3844
3845 protocol = vhdr->h_vlan_encapsulated_proto;
3846 } else {
3847 protocol = skb->protocol;
3848 }
3849
3850 switch (protocol) {
09640e63 3851 case cpu_to_be16(ETH_P_IP):
9d5c8243 3852 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
44b0cda3
MW		 3853 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
3854 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
b9473560
JB		 3855 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
3856 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
44b0cda3 3857 break;
09640e63 3858 case cpu_to_be16(ETH_P_IPV6):
44b0cda3
MW		 3859 /* XXX what about other V6 headers?? */
3860 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
3861 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
b9473560
JB		 3862 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
3863 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
44b0cda3
MW		 3864 break;
3865 default:
3866 if (unlikely(net_ratelimit()))
59d71989 3867 dev_warn(dev,
44b0cda3
MW		 3868 "partial checksum but proto=%x!\n",
3869 skb->protocol);
3870 break;
3871 }
9d5c8243
AK		 3872 }
3873
3874 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3875 context_desc->seqnum_seed = 0;
85ad76b2 3876 if (tx_ring->flags & IGB_RING_FLAG_TX_CTX_IDX)
7dfc16fa 3877 context_desc->mss_l4len_idx =
85ad76b2 3878 cpu_to_le32(tx_ring->reg_idx << 4);
9d5c8243
AK		 3879
3880 buffer_info->time_stamp = jiffies;
0e014cb1 3881 buffer_info->next_to_watch = i;
9d5c8243
AK		 3882 buffer_info->dma = 0;
3883
3884 i++;
3885 if (i == tx_ring->count)
3886 i = 0;
3887 tx_ring->next_to_use = i;
3888
3889 return true;
3890 }
9d5c8243
AK		 3891 return false;
3892}
3893
3894#define IGB_MAX_TXD_PWR 16
3895#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
3896
80785298 3897static inline int igb_tx_map_adv(struct igb_ring *tx_ring, struct sk_buff *skb,
0e014cb1 3898 unsigned int first)
9d5c8243
AK		 3899{
3900 struct igb_buffer *buffer_info;
59d71989 3901 struct device *dev = tx_ring->dev;
9d5c8243
AK		 3902 unsigned int len = skb_headlen(skb);
3903 unsigned int count = 0, i;
3904 unsigned int f;
3905
3906 i = tx_ring->next_to_use;
3907
3908 buffer_info = &tx_ring->buffer_info[i];
3909 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3910 buffer_info->length = len;
3911 /* set time_stamp *before* dma to help avoid a possible race */
3912 buffer_info->time_stamp = jiffies;
0e014cb1 3913 buffer_info->next_to_watch = i;
59d71989
AD		 3914 buffer_info->dma = dma_map_single(dev, skb->data, len,
3915 DMA_TO_DEVICE);
3916 if (dma_mapping_error(dev, buffer_info->dma))
6366ad33 3917 goto dma_error;
9d5c8243
AK		 3918
3919 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
3920 struct skb_frag_struct *frag;
3921
8581145f 3922 count++;
65689fef
AD		 3923 i++;
3924 if (i == tx_ring->count)
3925 i = 0;
3926
9d5c8243
AK		 3927 frag = &skb_shinfo(skb)->frags[f];
3928 len = frag->size;
3929
3930 buffer_info = &tx_ring->buffer_info[i];
3931 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3932 buffer_info->length = len;
3933 buffer_info->time_stamp = jiffies;
0e014cb1 3934 buffer_info->next_to_watch = i;
6366ad33 3935 buffer_info->mapped_as_page = true;
59d71989 3936 buffer_info->dma = dma_map_page(dev,
6366ad33
AD		 3937 frag->page,
3938 frag->page_offset,
3939 len,
59d71989
AD		 3940 DMA_TO_DEVICE);
3941 if (dma_mapping_error(dev, buffer_info->dma))
6366ad33
AD		 3942 goto dma_error;
3943
9d5c8243
AK		 3944 }
3945
9d5c8243 3946 tx_ring->buffer_info[i].skb = skb;
40e90c26 3947 tx_ring->buffer_info[i].gso_segs = skb_shinfo(skb)->gso_segs ?: 1;
0e014cb1 3948 tx_ring->buffer_info[first].next_to_watch = i;
9d5c8243 3949
cdfd01fc 3950 return ++count;
6366ad33
AD		 3951
3952dma_error:
59d71989 3953 dev_err(dev, "TX DMA map failed\n");
6366ad33
AD		 3954
3955 /* clear timestamp and dma mappings for failed buffer_info mapping */
3956 buffer_info->dma = 0;
3957 buffer_info->time_stamp = 0;
3958 buffer_info->length = 0;
3959 buffer_info->next_to_watch = 0;
3960 buffer_info->mapped_as_page = false;
6366ad33
AD		 3961
3962 /* clear timestamp and dma mappings for remaining portion of packet */
a77ff709
NN		 3963 while (count--) {
3964 if (i == 0)
3965 i = tx_ring->count;
6366ad33 3966 i--;
6366ad33
AD		 3967 buffer_info = &tx_ring->buffer_info[i];
3968 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
3969 }
3970
3971 return 0;
9d5c8243
AK		 3972}
3973
85ad76b2 3974static inline void igb_tx_queue_adv(struct igb_ring *tx_ring,
91d4ee33 3975 u32 tx_flags, int count, u32 paylen,
9d5c8243
AK		 3976 u8 hdr_len)
3977{
cdfd01fc 3978 union e1000_adv_tx_desc *tx_desc;
9d5c8243
AK		 3979 struct igb_buffer *buffer_info;
3980 u32 olinfo_status = 0, cmd_type_len;
cdfd01fc 3981 unsigned int i = tx_ring->next_to_use;
9d5c8243
AK		 3982
3983 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
3984 E1000_ADVTXD_DCMD_DEXT);
3985
3986 if (tx_flags & IGB_TX_FLAGS_VLAN)
3987 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3988
33af6bcc
PO		 3989 if (tx_flags & IGB_TX_FLAGS_TSTAMP)
3990 cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP;
3991
9d5c8243
AK		 3992 if (tx_flags & IGB_TX_FLAGS_TSO) {
3993 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3994
3995 /* insert tcp checksum */
3996 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3997
3998 /* insert ip checksum */
3999 if (tx_flags & IGB_TX_FLAGS_IPV4)
4000 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
4001
4002 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
4003 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
4004 }
4005
85ad76b2
AD		 4006 if ((tx_ring->flags & IGB_RING_FLAG_TX_CTX_IDX) &&
4007 (tx_flags & (IGB_TX_FLAGS_CSUM |
4008 IGB_TX_FLAGS_TSO |
7dfc16fa 4009 IGB_TX_FLAGS_VLAN)))
85ad76b2 4010 olinfo_status |= tx_ring->reg_idx << 4;
9d5c8243
AK		 4011
4012 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
4013
cdfd01fc 4014 do {
9d5c8243
AK		 4015 buffer_info = &tx_ring->buffer_info[i];
4016 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
4017 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
4018 tx_desc->read.cmd_type_len =
4019 cpu_to_le32(cmd_type_len | buffer_info->length);
4020 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
cdfd01fc 4021 count--;
9d5c8243
AK		 4022 i++;
4023 if (i == tx_ring->count)
4024 i = 0;
cdfd01fc 4025 } while (count > 0);
9d5c8243 4026
85ad76b2 4027 tx_desc->read.cmd_type_len |= cpu_to_le32(IGB_ADVTXD_DCMD);
9d5c8243
AK		 4028 /* Force memory writes to complete before letting h/w
4029 * know there are new descriptors to fetch. (Only
4030 * applicable for weak-ordered memory model archs,
4031 * such as IA-64). */
4032 wmb();
4033
4034 tx_ring->next_to_use = i;
fce99e34 4035 writel(i, tx_ring->tail);
9d5c8243
AK		 4036 /* we need this if more than one processor can write to our tail
4037 * at a time, it syncronizes IO on IA64/Altix systems */
4038 mmiowb();
4039}
4040
e694e964 4041static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, int size)
9d5c8243 4042{
e694e964
AD		 4043 struct net_device *netdev = tx_ring->netdev;
4044
661086df 4045 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 4046
9d5c8243
AK		 4047 /* Herbert's original patch had:
4048 * smp_mb__after_netif_stop_queue();
4049 * but since that doesn't exist yet, just open code it. */
4050 smp_mb();
4051
4052 /* We need to check again in a case another CPU has just
4053 * made room available. */
c493ea45 4054 if (igb_desc_unused(tx_ring) < size)
9d5c8243
AK		 4055 return -EBUSY;
4056
4057 /* A reprieve! */
661086df 4058 netif_wake_subqueue(netdev, tx_ring->queue_index);
04a5fcaa 4059 tx_ring->tx_stats.restart_queue++;
9d5c8243
AK		 4060 return 0;
4061}
4062
717ba089 4063static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, int size)
9d5c8243 4064{
c493ea45 4065 if (igb_desc_unused(tx_ring) >= size)
9d5c8243 4066 return 0;
e694e964 4067 return __igb_maybe_stop_tx(tx_ring, size);
9d5c8243
AK		 4068}
4069
b1a436c3
AD		 4070netdev_tx_t igb_xmit_frame_ring_adv(struct sk_buff *skb,
4071 struct igb_ring *tx_ring)
9d5c8243 4072{
e694e964 4073 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
cdfd01fc 4074 int tso = 0, count;
91d4ee33
NN		 4075 u32 tx_flags = 0;
4076 u16 first;
4077 u8 hdr_len = 0;
c5b9bd5e 4078 union skb_shared_tx *shtx = skb_tx(skb);
9d5c8243 4079
9d5c8243
AK		 4080 /* need: 1 descriptor per page,
4081 * + 2 desc gap to keep tail from touching head,
4082 * + 1 desc for skb->data,
4083 * + 1 desc for context descriptor,
4084 * otherwise try next time */
e694e964 4085 if (igb_maybe_stop_tx(tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
9d5c8243 4086 /* this is a hard error */
9d5c8243
AK		 4087 return NETDEV_TX_BUSY;
4088 }
33af6bcc 4089
33af6bcc
PO		 4090 if (unlikely(shtx->hardware)) {
4091 shtx->in_progress = 1;
4092 tx_flags |= IGB_TX_FLAGS_TSTAMP;
33af6bcc 4093 }
9d5c8243 4094
cdfd01fc 4095 if (vlan_tx_tag_present(skb) && adapter->vlgrp) {
9d5c8243
AK		 4096 tx_flags |= IGB_TX_FLAGS_VLAN;
4097 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
4098 }
4099
661086df
PWJ		 4100 if (skb->protocol == htons(ETH_P_IP))
4101 tx_flags |= IGB_TX_FLAGS_IPV4;
4102
0e014cb1 4103 first = tx_ring->next_to_use;
85ad76b2
AD		 4104 if (skb_is_gso(skb)) {
4105 tso = igb_tso_adv(tx_ring, skb, tx_flags, &hdr_len);
cdfd01fc 4106
85ad76b2
AD		 4107 if (tso < 0) {
4108 dev_kfree_skb_any(skb);
4109 return NETDEV_TX_OK;
4110 }
9d5c8243
AK		 4111 }
4112
4113 if (tso)
4114 tx_flags |= IGB_TX_FLAGS_TSO;
85ad76b2 4115 else if (igb_tx_csum_adv(tx_ring, skb, tx_flags) &&
bc1cbd34
AD		 4116 (skb->ip_summed == CHECKSUM_PARTIAL))
4117 tx_flags |= IGB_TX_FLAGS_CSUM;
9d5c8243 4118
65689fef 4119 /*
cdfd01fc 4120 * count reflects descriptors mapped, if 0 or less then mapping error
65689fef
AD		 4121 * has occured and we need to rewind the descriptor queue
4122 */
80785298 4123 count = igb_tx_map_adv(tx_ring, skb, first);
6366ad33 4124 if (!count) {
65689fef
AD		 4125 dev_kfree_skb_any(skb);
4126 tx_ring->buffer_info[first].time_stamp = 0;
4127 tx_ring->next_to_use = first;
85ad76b2 4128 return NETDEV_TX_OK;
65689fef 4129 }
9d5c8243 4130
85ad76b2
AD		 4131 igb_tx_queue_adv(tx_ring, tx_flags, count, skb->len, hdr_len);
4132
4133 /* Make sure there is space in the ring for the next send. */
e694e964 4134 igb_maybe_stop_tx(tx_ring, MAX_SKB_FRAGS + 4);
85ad76b2 4135
9d5c8243
AK		 4136 return NETDEV_TX_OK;
4137}
4138
3b29a56d
SH		 4139static netdev_tx_t igb_xmit_frame_adv(struct sk_buff *skb,
4140 struct net_device *netdev)
9d5c8243
AK		 4141{
4142 struct igb_adapter *adapter = netdev_priv(netdev);
661086df 4143 struct igb_ring *tx_ring;
661086df 4144 int r_idx = 0;
b1a436c3
AD		 4145
4146 if (test_bit(__IGB_DOWN, &adapter->state)) {
4147 dev_kfree_skb_any(skb);
4148 return NETDEV_TX_OK;
4149 }
4150
4151 if (skb->len <= 0) {
4152 dev_kfree_skb_any(skb);
4153 return NETDEV_TX_OK;
4154 }
4155
1bfaf07b 4156 r_idx = skb->queue_mapping & (IGB_ABS_MAX_TX_QUEUES - 1);
661086df 4157 tx_ring = adapter->multi_tx_table[r_idx];
9d5c8243
AK		 4158
4159 /* This goes back to the question of how to logically map a tx queue
4160 * to a flow. Right now, performance is impacted slightly negatively
4161 * if using multiple tx queues. If the stack breaks away from a
4162 * single qdisc implementation, we can look at this again. */
e694e964 4163 return igb_xmit_frame_ring_adv(skb, tx_ring);
9d5c8243
AK		 4164}
4165
4166/**
4167 * igb_tx_timeout - Respond to a Tx Hang
4168 * @netdev: network interface device structure
4169 **/
4170static void igb_tx_timeout(struct net_device *netdev)
4171{
4172 struct igb_adapter *adapter = netdev_priv(netdev);
4173 struct e1000_hw *hw = &adapter->hw;
4174
4175 /* Do the reset outside of interrupt context */
4176 adapter->tx_timeout_count++;
f7ba205e 4177
55cac248
AD		 4178 if (hw->mac.type == e1000_82580)
4179 hw->dev_spec._82575.global_device_reset = true;
4180
9d5c8243 4181 schedule_work(&adapter->reset_task);
265de409
AD		 4182 wr32(E1000_EICS,
4183 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 4184}
4185
4186static void igb_reset_task(struct work_struct *work)
4187{
4188 struct igb_adapter *adapter;
4189 adapter = container_of(work, struct igb_adapter, reset_task);
4190
c97ec42a
TI		 4191 igb_dump(adapter);
4192 netdev_err(adapter->netdev, "Reset adapter\n");
9d5c8243
AK		 4193 igb_reinit_locked(adapter);
4194}
4195
4196/**
4197 * igb_get_stats - Get System Network Statistics
4198 * @netdev: network interface device structure
4199 *
4200 * Returns the address of the device statistics structure.
4201 * The statistics are actually updated from the timer callback.
4202 **/
73cd78f1 4203static struct net_device_stats *igb_get_stats(struct net_device *netdev)
9d5c8243 4204{
9d5c8243 4205 /* only return the current stats */
8d24e933 4206 return &netdev->stats;
9d5c8243
AK		 4207}
4208
4209/**
4210 * igb_change_mtu - Change the Maximum Transfer Unit
4211 * @netdev: network interface device structure
4212 * @new_mtu: new value for maximum frame size
4213 *
4214 * Returns 0 on success, negative on failure
4215 **/
4216static int igb_change_mtu(struct net_device *netdev, int new_mtu)
4217{
4218 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 4219 struct pci_dev *pdev = adapter->pdev;
9d5c8243 4220 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4c844851 4221 u32 rx_buffer_len, i;
9d5c8243 4222
c809d227 4223 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
090b1795 4224 dev_err(&pdev->dev, "Invalid MTU setting\n");
9d5c8243
AK		 4225 return -EINVAL;
4226 }
4227
9d5c8243 4228 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
090b1795 4229 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
9d5c8243
AK		 4230 return -EINVAL;
4231 }
4232
4233 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
4234 msleep(1);
73cd78f1 4235
9d5c8243
AK		 4236 /* igb_down has a dependency on max_frame_size */
4237 adapter->max_frame_size = max_frame;
559e9c49 4238
9d5c8243
AK		 4239 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
4240 * means we reserve 2 more, this pushes us to allocate from the next
4241 * larger slab size.
4242 * i.e. RXBUFFER_2048 --> size-4096 slab
4243 */
4244
757b77e2
NN		 4245 if (adapter->hw.mac.type == e1000_82580)
4246 max_frame += IGB_TS_HDR_LEN;
4247
7d95b717 4248 if (max_frame <= IGB_RXBUFFER_1024)
4c844851 4249 rx_buffer_len = IGB_RXBUFFER_1024;
6ec43fe6 4250 else if (max_frame <= MAXIMUM_ETHERNET_VLAN_SIZE)
4c844851 4251 rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
6ec43fe6 4252 else
4c844851
AD		 4253 rx_buffer_len = IGB_RXBUFFER_128;
4254
757b77e2
NN		 4255 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN + IGB_TS_HDR_LEN) ||
4256 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE + IGB_TS_HDR_LEN))
4257 rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE + IGB_TS_HDR_LEN;
4258
4259 if ((adapter->hw.mac.type == e1000_82580) &&
4260 (rx_buffer_len == IGB_RXBUFFER_128))
4261 rx_buffer_len += IGB_RXBUFFER_64;
4262
4c844851
AD		 4263 if (netif_running(netdev))
4264 igb_down(adapter);
9d5c8243 4265
090b1795 4266 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
9d5c8243
AK		 4267 netdev->mtu, new_mtu);
4268 netdev->mtu = new_mtu;
4269
4c844851 4270 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 4271 adapter->rx_ring[i]->rx_buffer_len = rx_buffer_len;
4c844851 4272
9d5c8243
AK		 4273 if (netif_running(netdev))
4274 igb_up(adapter);
4275 else
4276 igb_reset(adapter);
4277
4278 clear_bit(__IGB_RESETTING, &adapter->state);
4279
4280 return 0;
4281}
4282
4283/**
4284 * igb_update_stats - Update the board statistics counters
4285 * @adapter: board private structure
4286 **/
4287
4288void igb_update_stats(struct igb_adapter *adapter)
4289{
128e45eb 4290 struct net_device_stats *net_stats = igb_get_stats(adapter->netdev);
9d5c8243
AK		 4291 struct e1000_hw *hw = &adapter->hw;
4292 struct pci_dev *pdev = adapter->pdev;
fa3d9a6d 4293 u32 reg, mpc;
9d5c8243 4294 u16 phy_tmp;
3f9c0164
AD		 4295 int i;
4296 u64 bytes, packets;
9d5c8243
AK		 4297
4298#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
4299
4300 /*
4301 * Prevent stats update while adapter is being reset, or if the pci
4302 * connection is down.
4303 */
4304 if (adapter->link_speed == 0)
4305 return;
4306 if (pci_channel_offline(pdev))
4307 return;
4308
3f9c0164
AD		 4309 bytes = 0;
4310 packets = 0;
4311 for (i = 0; i < adapter->num_rx_queues; i++) {
4312 u32 rqdpc_tmp = rd32(E1000_RQDPC(i)) & 0x0FFF;
3025a446
AD		 4313 struct igb_ring *ring = adapter->rx_ring[i];
4314 ring->rx_stats.drops += rqdpc_tmp;
128e45eb 4315 net_stats->rx_fifo_errors += rqdpc_tmp;
3025a446
AD		 4316 bytes += ring->rx_stats.bytes;
4317 packets += ring->rx_stats.packets;
3f9c0164
AD		 4318 }
4319
128e45eb
AD		 4320 net_stats->rx_bytes = bytes;
4321 net_stats->rx_packets = packets;
3f9c0164
AD		 4322
4323 bytes = 0;
4324 packets = 0;
4325 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446
AD		 4326 struct igb_ring *ring = adapter->tx_ring[i];
4327 bytes += ring->tx_stats.bytes;
4328 packets += ring->tx_stats.packets;
3f9c0164 4329 }
128e45eb
AD		 4330 net_stats->tx_bytes = bytes;
4331 net_stats->tx_packets = packets;
3f9c0164
AD		 4332
4333 /* read stats registers */
9d5c8243
AK		 4334 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
4335 adapter->stats.gprc += rd32(E1000_GPRC);
4336 adapter->stats.gorc += rd32(E1000_GORCL);
4337 rd32(E1000_GORCH); /* clear GORCL */
4338 adapter->stats.bprc += rd32(E1000_BPRC);
4339 adapter->stats.mprc += rd32(E1000_MPRC);
4340 adapter->stats.roc += rd32(E1000_ROC);
4341
4342 adapter->stats.prc64 += rd32(E1000_PRC64);
4343 adapter->stats.prc127 += rd32(E1000_PRC127);
4344 adapter->stats.prc255 += rd32(E1000_PRC255);
4345 adapter->stats.prc511 += rd32(E1000_PRC511);
4346 adapter->stats.prc1023 += rd32(E1000_PRC1023);
4347 adapter->stats.prc1522 += rd32(E1000_PRC1522);
4348 adapter->stats.symerrs += rd32(E1000_SYMERRS);
4349 adapter->stats.sec += rd32(E1000_SEC);
4350
fa3d9a6d
MW		 4351 mpc = rd32(E1000_MPC);
4352 adapter->stats.mpc += mpc;
4353 net_stats->rx_fifo_errors += mpc;
9d5c8243
AK		 4354 adapter->stats.scc += rd32(E1000_SCC);
4355 adapter->stats.ecol += rd32(E1000_ECOL);
4356 adapter->stats.mcc += rd32(E1000_MCC);
4357 adapter->stats.latecol += rd32(E1000_LATECOL);
4358 adapter->stats.dc += rd32(E1000_DC);
4359 adapter->stats.rlec += rd32(E1000_RLEC);
4360 adapter->stats.xonrxc += rd32(E1000_XONRXC);
4361 adapter->stats.xontxc += rd32(E1000_XONTXC);
4362 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
4363 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
4364 adapter->stats.fcruc += rd32(E1000_FCRUC);
4365 adapter->stats.gptc += rd32(E1000_GPTC);
4366 adapter->stats.gotc += rd32(E1000_GOTCL);
4367 rd32(E1000_GOTCH); /* clear GOTCL */
fa3d9a6d 4368 adapter->stats.rnbc += rd32(E1000_RNBC);
9d5c8243
AK		 4369 adapter->stats.ruc += rd32(E1000_RUC);
4370 adapter->stats.rfc += rd32(E1000_RFC);
4371 adapter->stats.rjc += rd32(E1000_RJC);
4372 adapter->stats.tor += rd32(E1000_TORH);
4373 adapter->stats.tot += rd32(E1000_TOTH);
4374 adapter->stats.tpr += rd32(E1000_TPR);
4375
4376 adapter->stats.ptc64 += rd32(E1000_PTC64);
4377 adapter->stats.ptc127 += rd32(E1000_PTC127);
4378 adapter->stats.ptc255 += rd32(E1000_PTC255);
4379 adapter->stats.ptc511 += rd32(E1000_PTC511);
4380 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
4381 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
4382
4383 adapter->stats.mptc += rd32(E1000_MPTC);
4384 adapter->stats.bptc += rd32(E1000_BPTC);
4385
2d0b0f69
NN		 4386 adapter->stats.tpt += rd32(E1000_TPT);
4387 adapter->stats.colc += rd32(E1000_COLC);
9d5c8243
AK		 4388
4389 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
43915c7c
NN		 4390 /* read internal phy specific stats */
4391 reg = rd32(E1000_CTRL_EXT);
4392 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
4393 adapter->stats.rxerrc += rd32(E1000_RXERRC);
4394 adapter->stats.tncrs += rd32(E1000_TNCRS);
4395 }
4396
9d5c8243
AK		 4397 adapter->stats.tsctc += rd32(E1000_TSCTC);
4398 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
4399
4400 adapter->stats.iac += rd32(E1000_IAC);
4401 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
4402 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
4403 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
4404 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
4405 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
4406 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
4407 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
4408 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
4409
4410 /* Fill out the OS statistics structure */
128e45eb
AD		 4411 net_stats->multicast = adapter->stats.mprc;
4412 net_stats->collisions = adapter->stats.colc;
9d5c8243
AK		 4413
4414 /* Rx Errors */
4415
4416 /* RLEC on some newer hardware can be incorrect so build
8c0ab70a 4417 * our own version based on RUC and ROC */
128e45eb 4418 net_stats->rx_errors = adapter->stats.rxerrc +
9d5c8243
AK		 4419 adapter->stats.crcerrs + adapter->stats.algnerrc +
4420 adapter->stats.ruc + adapter->stats.roc +
4421 adapter->stats.cexterr;
128e45eb
AD		 4422 net_stats->rx_length_errors = adapter->stats.ruc +
4423 adapter->stats.roc;
4424 net_stats->rx_crc_errors = adapter->stats.crcerrs;
4425 net_stats->rx_frame_errors = adapter->stats.algnerrc;
4426 net_stats->rx_missed_errors = adapter->stats.mpc;
9d5c8243
AK		 4427
4428 /* Tx Errors */
128e45eb
AD		 4429 net_stats->tx_errors = adapter->stats.ecol +
4430 adapter->stats.latecol;
4431 net_stats->tx_aborted_errors = adapter->stats.ecol;
4432 net_stats->tx_window_errors = adapter->stats.latecol;
4433 net_stats->tx_carrier_errors = adapter->stats.tncrs;
9d5c8243
AK		 4434
4435 /* Tx Dropped needs to be maintained elsewhere */
4436
4437 /* Phy Stats */
4438 if (hw->phy.media_type == e1000_media_type_copper) {
4439 if ((adapter->link_speed == SPEED_1000) &&
73cd78f1 4440 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
9d5c8243
AK		 4441 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
4442 adapter->phy_stats.idle_errors += phy_tmp;
4443 }
4444 }
4445
4446 /* Management Stats */
4447 adapter->stats.mgptc += rd32(E1000_MGTPTC);
4448 adapter->stats.mgprc += rd32(E1000_MGTPRC);
4449 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
4450}
4451
9d5c8243
AK		 4452static irqreturn_t igb_msix_other(int irq, void *data)
4453{
047e0030 4454 struct igb_adapter *adapter = data;
9d5c8243 4455 struct e1000_hw *hw = &adapter->hw;
844290e5 4456 u32 icr = rd32(E1000_ICR);
844290e5 4457 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083 4458
7f081d40
AD		 4459 if (icr & E1000_ICR_DRSTA)
4460 schedule_work(&adapter->reset_task);
4461
047e0030 4462 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 4463 /* HW is reporting DMA is out of sync */
4464 adapter->stats.doosync++;
4465 }
eebbbdba 4466
4ae196df
AD		 4467 /* Check for a mailbox event */
4468 if (icr & E1000_ICR_VMMB)
4469 igb_msg_task(adapter);
4470
4471 if (icr & E1000_ICR_LSC) {
4472 hw->mac.get_link_status = 1;
4473 /* guard against interrupt when we're going down */
4474 if (!test_bit(__IGB_DOWN, &adapter->state))
4475 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4476 }
4477
25568a53
AD		 4478 if (adapter->vfs_allocated_count)
4479 wr32(E1000_IMS, E1000_IMS_LSC |
4480 E1000_IMS_VMMB |
4481 E1000_IMS_DOUTSYNC);
4482 else
4483 wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC);
844290e5 4484 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 4485
4486 return IRQ_HANDLED;
4487}
4488
047e0030 4489static void igb_write_itr(struct igb_q_vector *q_vector)
9d5c8243 4490{
26b39276 4491 struct igb_adapter *adapter = q_vector->adapter;
047e0030 4492 u32 itr_val = q_vector->itr_val & 0x7FFC;
9d5c8243 4493
047e0030
AD		 4494 if (!q_vector->set_itr)
4495 return;
73cd78f1 4496
047e0030
AD		 4497 if (!itr_val)
4498 itr_val = 0x4;
661086df 4499
26b39276
AD		 4500 if (adapter->hw.mac.type == e1000_82575)
4501 itr_val |= itr_val << 16;
661086df 4502 else
047e0030 4503 itr_val |= 0x8000000;
661086df 4504
047e0030
AD		 4505 writel(itr_val, q_vector->itr_register);
4506 q_vector->set_itr = 0;
6eb5a7f1
AD		 4507}
4508
047e0030 4509static irqreturn_t igb_msix_ring(int irq, void *data)
9d5c8243 4510{
047e0030 4511 struct igb_q_vector *q_vector = data;
9d5c8243 4512
047e0030
AD		 4513 /* Write the ITR value calculated from the previous interrupt. */
4514 igb_write_itr(q_vector);
9d5c8243 4515
047e0030 4516 napi_schedule(&q_vector->napi);
844290e5 4517
047e0030 4518 return IRQ_HANDLED;
fe4506b6
JC		 4519}
4520
421e02f0 4521#ifdef CONFIG_IGB_DCA
047e0030 4522static void igb_update_dca(struct igb_q_vector *q_vector)
fe4506b6 4523{
047e0030 4524 struct igb_adapter *adapter = q_vector->adapter;
fe4506b6
JC		 4525 struct e1000_hw *hw = &adapter->hw;
4526 int cpu = get_cpu();
fe4506b6 4527
047e0030
AD		 4528 if (q_vector->cpu == cpu)
4529 goto out_no_update;
4530
4531 if (q_vector->tx_ring) {
4532 int q = q_vector->tx_ring->reg_idx;
4533 u32 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
4534 if (hw->mac.type == e1000_82575) {
4535 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
4536 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
2d064c06 4537 } else {
047e0030
AD		 4538 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
4539 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
4540 E1000_DCA_TXCTRL_CPUID_SHIFT;
4541 }
4542 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
4543 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
4544 }
4545 if (q_vector->rx_ring) {
4546 int q = q_vector->rx_ring->reg_idx;
4547 u32 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
4548 if (hw->mac.type == e1000_82575) {
2d064c06 4549 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
92be7917 4550 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
047e0030
AD		 4551 } else {
4552 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
4553 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
4554 E1000_DCA_RXCTRL_CPUID_SHIFT;
2d064c06 4555 }
fe4506b6
JC		 4556 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
4557 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
4558 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
4559 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
fe4506b6 4560 }
047e0030
AD		 4561 q_vector->cpu = cpu;
4562out_no_update:
fe4506b6
JC		 4563 put_cpu();
4564}
4565
4566static void igb_setup_dca(struct igb_adapter *adapter)
4567{
7e0e99ef 4568 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 4569 int i;
4570
7dfc16fa 4571 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 4572 return;
4573
7e0e99ef
AD		 4574 /* Always use CB2 mode, difference is masked in the CB driver. */
4575 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
4576
047e0030 4577 for (i = 0; i < adapter->num_q_vectors; i++) {
26b39276
AD		 4578 adapter->q_vector[i]->cpu = -1;
4579 igb_update_dca(adapter->q_vector[i]);
fe4506b6
JC		 4580 }
4581}
4582
4583static int __igb_notify_dca(struct device *dev, void *data)
4584{
4585 struct net_device *netdev = dev_get_drvdata(dev);
4586 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 4587 struct pci_dev *pdev = adapter->pdev;
fe4506b6
JC		 4588 struct e1000_hw *hw = &adapter->hw;
4589 unsigned long event = *(unsigned long *)data;
4590
4591 switch (event) {
4592 case DCA_PROVIDER_ADD:
4593 /* if already enabled, don't do it again */
7dfc16fa 4594 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 4595 break;
fe4506b6 4596 if (dca_add_requester(dev) == 0) {
bbd98fe4 4597 adapter->flags |= IGB_FLAG_DCA_ENABLED;
090b1795 4598 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 4599 igb_setup_dca(adapter);
4600 break;
4601 }
4602 /* Fall Through since DCA is disabled. */
4603 case DCA_PROVIDER_REMOVE:
7dfc16fa 4604 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6 4605 /* without this a class_device is left
047e0030 4606 * hanging around in the sysfs model */
fe4506b6 4607 dca_remove_requester(dev);
090b1795 4608 dev_info(&pdev->dev, "DCA disabled\n");
7dfc16fa 4609 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 4610 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 4611 }
4612 break;
4613 }
bbd98fe4 4614
fe4506b6 4615 return 0;
9d5c8243
AK		 4616}
4617
fe4506b6
JC		 4618static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
4619 void *p)
4620{
4621 int ret_val;
4622
4623 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
4624 __igb_notify_dca);
4625
4626 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
4627}
421e02f0 4628#endif /* CONFIG_IGB_DCA */
9d5c8243 4629
4ae196df
AD		 4630static void igb_ping_all_vfs(struct igb_adapter *adapter)
4631{
4632 struct e1000_hw *hw = &adapter->hw;
4633 u32 ping;
4634 int i;
4635
4636 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
4637 ping = E1000_PF_CONTROL_MSG;
f2ca0dbe 4638 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
4ae196df
AD		 4639 ping |= E1000_VT_MSGTYPE_CTS;
4640 igb_write_mbx(hw, &ping, 1, i);
4641 }
4642}
4643
7d5753f0
AD		 4644static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
4645{
4646 struct e1000_hw *hw = &adapter->hw;
4647 u32 vmolr = rd32(E1000_VMOLR(vf));
4648 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4649
4650 vf_data->flags |= ~(IGB_VF_FLAG_UNI_PROMISC |
4651 IGB_VF_FLAG_MULTI_PROMISC);
4652 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
4653
4654 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
4655 vmolr |= E1000_VMOLR_MPME;
4656 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
4657 } else {
4658 /*
4659 * if we have hashes and we are clearing a multicast promisc
4660 * flag we need to write the hashes to the MTA as this step
4661 * was previously skipped
4662 */
4663 if (vf_data->num_vf_mc_hashes > 30) {
4664 vmolr |= E1000_VMOLR_MPME;
4665 } else if (vf_data->num_vf_mc_hashes) {
4666 int j;
4667 vmolr |= E1000_VMOLR_ROMPE;
4668 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
4669 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
4670 }
4671 }
4672
4673 wr32(E1000_VMOLR(vf), vmolr);
4674
4675 /* there are flags left unprocessed, likely not supported */
4676 if (*msgbuf & E1000_VT_MSGINFO_MASK)
4677 return -EINVAL;
4678
4679 return 0;
4680
4681}
4682
4ae196df
AD		 4683static int igb_set_vf_multicasts(struct igb_adapter *adapter,
4684 u32 *msgbuf, u32 vf)
4685{
4686 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
4687 u16 *hash_list = (u16 *)&msgbuf[1];
4688 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4689 int i;
4690
7d5753f0 4691 /* salt away the number of multicast addresses assigned
4ae196df
AD		 4692 * to this VF for later use to restore when the PF multi cast
4693 * list changes
4694 */
4695 vf_data->num_vf_mc_hashes = n;
4696
7d5753f0
AD		 4697 /* only up to 30 hash values supported */
4698 if (n > 30)
4699 n = 30;
4700
4701 /* store the hashes for later use */
4ae196df 4702 for (i = 0; i < n; i++)
a419aef8 4703 vf_data->vf_mc_hashes[i] = hash_list[i];
4ae196df
AD		 4704
4705 /* Flush and reset the mta with the new values */
ff41f8dc 4706 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 4707
4708 return 0;
4709}
4710
4711static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
4712{
4713 struct e1000_hw *hw = &adapter->hw;
4714 struct vf_data_storage *vf_data;
4715 int i, j;
4716
4717 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7d5753f0
AD		 4718 u32 vmolr = rd32(E1000_VMOLR(i));
4719 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
4720
4ae196df 4721 vf_data = &adapter->vf_data[i];
7d5753f0
AD		 4722
4723 if ((vf_data->num_vf_mc_hashes > 30) ||
4724 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
4725 vmolr |= E1000_VMOLR_MPME;
4726 } else if (vf_data->num_vf_mc_hashes) {
4727 vmolr |= E1000_VMOLR_ROMPE;
4728 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
4729 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
4730 }
4731 wr32(E1000_VMOLR(i), vmolr);
4ae196df
AD		 4732 }
4733}
4734
4735static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
4736{
4737 struct e1000_hw *hw = &adapter->hw;
4738 u32 pool_mask, reg, vid;
4739 int i;
4740
4741 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
4742
4743 /* Find the vlan filter for this id */
4744 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4745 reg = rd32(E1000_VLVF(i));
4746
4747 /* remove the vf from the pool */
4748 reg &= ~pool_mask;
4749
4750 /* if pool is empty then remove entry from vfta */
4751 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
4752 (reg & E1000_VLVF_VLANID_ENABLE)) {
4753 reg = 0;
4754 vid = reg & E1000_VLVF_VLANID_MASK;
4755 igb_vfta_set(hw, vid, false);
4756 }
4757
4758 wr32(E1000_VLVF(i), reg);
4759 }
ae641bdc
AD		 4760
4761 adapter->vf_data[vf].vlans_enabled = 0;
4ae196df
AD		 4762}
4763
4764static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
4765{
4766 struct e1000_hw *hw = &adapter->hw;
4767 u32 reg, i;
4768
51466239
AD		 4769 /* The vlvf table only exists on 82576 hardware and newer */
4770 if (hw->mac.type < e1000_82576)
4771 return -1;
4772
4773 /* we only need to do this if VMDq is enabled */
4ae196df
AD		 4774 if (!adapter->vfs_allocated_count)
4775 return -1;
4776
4777 /* Find the vlan filter for this id */
4778 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4779 reg = rd32(E1000_VLVF(i));
4780 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
4781 vid == (reg & E1000_VLVF_VLANID_MASK))
4782 break;
4783 }
4784
4785 if (add) {
4786 if (i == E1000_VLVF_ARRAY_SIZE) {
4787 /* Did not find a matching VLAN ID entry that was
4788 * enabled. Search for a free filter entry, i.e.
4789 * one without the enable bit set
4790 */
4791 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4792 reg = rd32(E1000_VLVF(i));
4793 if (!(reg & E1000_VLVF_VLANID_ENABLE))
4794 break;
4795 }
4796 }
4797 if (i < E1000_VLVF_ARRAY_SIZE) {
4798 /* Found an enabled/available entry */
4799 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
4800
4801 /* if !enabled we need to set this up in vfta */
4802 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
51466239
AD		 4803 /* add VID to filter table */
4804 igb_vfta_set(hw, vid, true);
4ae196df
AD		 4805 reg |= E1000_VLVF_VLANID_ENABLE;
4806 }
cad6d05f
AD		 4807 reg &= ~E1000_VLVF_VLANID_MASK;
4808 reg |= vid;
4ae196df 4809 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 4810
4811 /* do not modify RLPML for PF devices */
4812 if (vf >= adapter->vfs_allocated_count)
4813 return 0;
4814
4815 if (!adapter->vf_data[vf].vlans_enabled) {
4816 u32 size;
4817 reg = rd32(E1000_VMOLR(vf));
4818 size = reg & E1000_VMOLR_RLPML_MASK;
4819 size += 4;
4820 reg &= ~E1000_VMOLR_RLPML_MASK;
4821 reg |= size;
4822 wr32(E1000_VMOLR(vf), reg);
4823 }
ae641bdc 4824
51466239 4825 adapter->vf_data[vf].vlans_enabled++;
4ae196df
AD		 4826 return 0;
4827 }
4828 } else {
4829 if (i < E1000_VLVF_ARRAY_SIZE) {
4830 /* remove vf from the pool */
4831 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
4832 /* if pool is empty then remove entry from vfta */
4833 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
4834 reg = 0;
4835 igb_vfta_set(hw, vid, false);
4836 }
4837 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 4838
4839 /* do not modify RLPML for PF devices */
4840 if (vf >= adapter->vfs_allocated_count)
4841 return 0;
4842
4843 adapter->vf_data[vf].vlans_enabled--;
4844 if (!adapter->vf_data[vf].vlans_enabled) {
4845 u32 size;
4846 reg = rd32(E1000_VMOLR(vf));
4847 size = reg & E1000_VMOLR_RLPML_MASK;
4848 size -= 4;
4849 reg &= ~E1000_VMOLR_RLPML_MASK;
4850 reg |= size;
4851 wr32(E1000_VMOLR(vf), reg);
4852 }
4ae196df
AD		 4853 }
4854 }
8151d294
WM		 4855 return 0;
4856}
4857
4858static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
4859{
4860 struct e1000_hw *hw = &adapter->hw;
4861
4862 if (vid)
4863 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
4864 else
4865 wr32(E1000_VMVIR(vf), 0);
4866}
4867
4868static int igb_ndo_set_vf_vlan(struct net_device *netdev,
4869 int vf, u16 vlan, u8 qos)
4870{
4871 int err = 0;
4872 struct igb_adapter *adapter = netdev_priv(netdev);
4873
4874 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
4875 return -EINVAL;
4876 if (vlan || qos) {
4877 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
4878 if (err)
4879 goto out;
4880 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
4881 igb_set_vmolr(adapter, vf, !vlan);
4882 adapter->vf_data[vf].pf_vlan = vlan;
4883 adapter->vf_data[vf].pf_qos = qos;
4884 dev_info(&adapter->pdev->dev,
4885 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
4886 if (test_bit(__IGB_DOWN, &adapter->state)) {
4887 dev_warn(&adapter->pdev->dev,
4888 "The VF VLAN has been set,"
4889 " but the PF device is not up.\n");
4890 dev_warn(&adapter->pdev->dev,
4891 "Bring the PF device up before"
4892 " attempting to use the VF device.\n");
4893 }
4894 } else {
4895 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
4896 false, vf);
4897 igb_set_vmvir(adapter, vlan, vf);
4898 igb_set_vmolr(adapter, vf, true);
4899 adapter->vf_data[vf].pf_vlan = 0;
4900 adapter->vf_data[vf].pf_qos = 0;
4901 }
4902out:
4903 return err;
4ae196df
AD		 4904}
4905
4906static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
4907{
4908 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
4909 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
4910
4911 return igb_vlvf_set(adapter, vid, add, vf);
4912}
4913
f2ca0dbe 4914static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
4ae196df 4915{
8151d294
WM		 4916 /* clear flags */
4917 adapter->vf_data[vf].flags &= ~(IGB_VF_FLAG_PF_SET_MAC);
f2ca0dbe 4918 adapter->vf_data[vf].last_nack = jiffies;
4ae196df
AD		 4919
4920 /* reset offloads to defaults */
8151d294 4921 igb_set_vmolr(adapter, vf, true);
4ae196df
AD		 4922
4923 /* reset vlans for device */
4924 igb_clear_vf_vfta(adapter, vf);
8151d294
WM		 4925 if (adapter->vf_data[vf].pf_vlan)
4926 igb_ndo_set_vf_vlan(adapter->netdev, vf,
4927 adapter->vf_data[vf].pf_vlan,
4928 adapter->vf_data[vf].pf_qos);
4929 else
4930 igb_clear_vf_vfta(adapter, vf);
4ae196df
AD		 4931
4932 /* reset multicast table array for vf */
4933 adapter->vf_data[vf].num_vf_mc_hashes = 0;
4934
4935 /* Flush and reset the mta with the new values */
ff41f8dc 4936 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 4937}
4938
f2ca0dbe
AD		 4939static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
4940{
4941 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
4942
4943 /* generate a new mac address as we were hotplug removed/added */
8151d294
WM		 4944 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
4945 random_ether_addr(vf_mac);
f2ca0dbe
AD		 4946
4947 /* process remaining reset events */
4948 igb_vf_reset(adapter, vf);
4949}
4950
4951static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4ae196df
AD		 4952{
4953 struct e1000_hw *hw = &adapter->hw;
4954 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 4955 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 4956 u32 reg, msgbuf[3];
4957 u8 *addr = (u8 *)(&msgbuf[1]);
4958
4959 /* process all the same items cleared in a function level reset */
f2ca0dbe 4960 igb_vf_reset(adapter, vf);
4ae196df
AD		 4961
4962 /* set vf mac address */
26ad9178 4963 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4ae196df
AD		 4964
4965 /* enable transmit and receive for vf */
4966 reg = rd32(E1000_VFTE);
4967 wr32(E1000_VFTE, reg | (1 << vf));
4968 reg = rd32(E1000_VFRE);
4969 wr32(E1000_VFRE, reg | (1 << vf));
4970
f2ca0dbe 4971 adapter->vf_data[vf].flags = IGB_VF_FLAG_CTS;
4ae196df
AD		 4972
4973 /* reply to reset with ack and vf mac address */
4974 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
4975 memcpy(addr, vf_mac, 6);
4976 igb_write_mbx(hw, msgbuf, 3, vf);
4977}
4978
4979static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
4980{
f2ca0dbe
AD		 4981 unsigned char *addr = (char *)&msg[1];
4982 int err = -1;
4ae196df 4983
f2ca0dbe
AD		 4984 if (is_valid_ether_addr(addr))
4985 err = igb_set_vf_mac(adapter, vf, addr);
4ae196df 4986
f2ca0dbe 4987 return err;
4ae196df
AD		 4988}
4989
4990static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
4991{
4992 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 4993 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 4994 u32 msg = E1000_VT_MSGTYPE_NACK;
4995
4996 /* if device isn't clear to send it shouldn't be reading either */
f2ca0dbe
AD		 4997 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
4998 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
4ae196df 4999 igb_write_mbx(hw, &msg, 1, vf);
f2ca0dbe 5000 vf_data->last_nack = jiffies;
4ae196df
AD		 5001 }
5002}
5003
f2ca0dbe 5004static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4ae196df 5005{
f2ca0dbe
AD		 5006 struct pci_dev *pdev = adapter->pdev;
5007 u32 msgbuf[E1000_VFMAILBOX_SIZE];
4ae196df 5008 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 5009 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 5010 s32 retval;
5011
f2ca0dbe 5012 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
4ae196df 5013
fef45f4c
AD		 5014 if (retval) {
5015 /* if receive failed revoke VF CTS stats and restart init */
f2ca0dbe 5016 dev_err(&pdev->dev, "Error receiving message from VF\n");
fef45f4c
AD		 5017 vf_data->flags &= ~IGB_VF_FLAG_CTS;
5018 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5019 return;
5020 goto out;
5021 }
4ae196df
AD		 5022
5023 /* this is a message we already processed, do nothing */
5024 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
f2ca0dbe 5025 return;
4ae196df
AD		 5026
5027 /*
5028 * until the vf completes a reset it should not be
5029 * allowed to start any configuration.
5030 */
5031
5032 if (msgbuf[0] == E1000_VF_RESET) {
5033 igb_vf_reset_msg(adapter, vf);
f2ca0dbe 5034 return;
4ae196df
AD		 5035 }
5036
f2ca0dbe 5037 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
fef45f4c
AD		 5038 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5039 return;
5040 retval = -1;
5041 goto out;
4ae196df
AD		 5042 }
5043
5044 switch ((msgbuf[0] & 0xFFFF)) {
5045 case E1000_VF_SET_MAC_ADDR:
5046 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
5047 break;
7d5753f0
AD		 5048 case E1000_VF_SET_PROMISC:
5049 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
5050 break;
4ae196df
AD		 5051 case E1000_VF_SET_MULTICAST:
5052 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
5053 break;
5054 case E1000_VF_SET_LPE:
5055 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
5056 break;
5057 case E1000_VF_SET_VLAN:
8151d294
WM		 5058 if (adapter->vf_data[vf].pf_vlan)
5059 retval = -1;
5060 else
5061 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4ae196df
AD		 5062 break;
5063 default:
090b1795 5064 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4ae196df
AD		 5065 retval = -1;
5066 break;
5067 }
5068
fef45f4c
AD		 5069 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
5070out:
4ae196df
AD		 5071 /* notify the VF of the results of what it sent us */
5072 if (retval)
5073 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
5074 else
5075 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
5076
4ae196df 5077 igb_write_mbx(hw, msgbuf, 1, vf);
f2ca0dbe 5078}
4ae196df 5079
f2ca0dbe
AD		 5080static void igb_msg_task(struct igb_adapter *adapter)
5081{
5082 struct e1000_hw *hw = &adapter->hw;
5083 u32 vf;
5084
5085 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
5086 /* process any reset requests */
5087 if (!igb_check_for_rst(hw, vf))
5088 igb_vf_reset_event(adapter, vf);
5089
5090 /* process any messages pending */
5091 if (!igb_check_for_msg(hw, vf))
5092 igb_rcv_msg_from_vf(adapter, vf);
5093
5094 /* process any acks */
5095 if (!igb_check_for_ack(hw, vf))
5096 igb_rcv_ack_from_vf(adapter, vf);
5097 }
4ae196df
AD		 5098}
5099
68d480c4
AD		 5100/**
5101 * igb_set_uta - Set unicast filter table address
5102 * @adapter: board private structure
5103 *
5104 * The unicast table address is a register array of 32-bit registers.
5105 * The table is meant to be used in a way similar to how the MTA is used
5106 * however due to certain limitations in the hardware it is necessary to
5107 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscous
5108 * enable bit to allow vlan tag stripping when promiscous mode is enabled
5109 **/
5110static void igb_set_uta(struct igb_adapter *adapter)
5111{
5112 struct e1000_hw *hw = &adapter->hw;
5113 int i;
5114
5115 /* The UTA table only exists on 82576 hardware and newer */
5116 if (hw->mac.type < e1000_82576)
5117 return;
5118
5119 /* we only need to do this if VMDq is enabled */
5120 if (!adapter->vfs_allocated_count)
5121 return;
5122
5123 for (i = 0; i < hw->mac.uta_reg_count; i++)
5124 array_wr32(E1000_UTA, i, ~0);
5125}
5126
9d5c8243
AK		 5127/**
5128 * igb_intr_msi - Interrupt Handler
5129 * @irq: interrupt number
5130 * @data: pointer to a network interface device structure
5131 **/
5132static irqreturn_t igb_intr_msi(int irq, void *data)
5133{
047e0030
AD		 5134 struct igb_adapter *adapter = data;
5135 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 5136 struct e1000_hw *hw = &adapter->hw;
5137 /* read ICR disables interrupts using IAM */
5138 u32 icr = rd32(E1000_ICR);
5139
047e0030 5140 igb_write_itr(q_vector);
9d5c8243 5141
7f081d40
AD		 5142 if (icr & E1000_ICR_DRSTA)
5143 schedule_work(&adapter->reset_task);
5144
047e0030 5145 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5146 /* HW is reporting DMA is out of sync */
5147 adapter->stats.doosync++;
5148 }
5149
9d5c8243
AK		 5150 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5151 hw->mac.get_link_status = 1;
5152 if (!test_bit(__IGB_DOWN, &adapter->state))
5153 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5154 }
5155
047e0030 5156 napi_schedule(&q_vector->napi);
9d5c8243
AK		 5157
5158 return IRQ_HANDLED;
5159}
5160
5161/**
4a3c6433 5162 * igb_intr - Legacy Interrupt Handler
9d5c8243
AK		 5163 * @irq: interrupt number
5164 * @data: pointer to a network interface device structure
5165 **/
5166static irqreturn_t igb_intr(int irq, void *data)
5167{
047e0030
AD		 5168 struct igb_adapter *adapter = data;
5169 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 5170 struct e1000_hw *hw = &adapter->hw;
5171 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
5172 * need for the IMC write */
5173 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 5174 if (!icr)
5175 return IRQ_NONE; /* Not our interrupt */
5176
047e0030 5177 igb_write_itr(q_vector);
9d5c8243
AK		 5178
5179 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
5180 * not set, then the adapter didn't send an interrupt */
5181 if (!(icr & E1000_ICR_INT_ASSERTED))
5182 return IRQ_NONE;
5183
7f081d40
AD		 5184 if (icr & E1000_ICR_DRSTA)
5185 schedule_work(&adapter->reset_task);
5186
047e0030 5187 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5188 /* HW is reporting DMA is out of sync */
5189 adapter->stats.doosync++;
5190 }
5191
9d5c8243
AK		 5192 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5193 hw->mac.get_link_status = 1;
5194 /* guard against interrupt when we're going down */
5195 if (!test_bit(__IGB_DOWN, &adapter->state))
5196 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5197 }
5198
047e0030 5199 napi_schedule(&q_vector->napi);
9d5c8243
AK		 5200
5201 return IRQ_HANDLED;
5202}
5203
047e0030 5204static inline void igb_ring_irq_enable(struct igb_q_vector *q_vector)
9d5c8243 5205{
047e0030 5206 struct igb_adapter *adapter = q_vector->adapter;
46544258 5207 struct e1000_hw *hw = &adapter->hw;
9d5c8243 5208
4fc82adf
AD		 5209 if ((q_vector->rx_ring && (adapter->rx_itr_setting & 3)) ||
5210 (!q_vector->rx_ring && (adapter->tx_itr_setting & 3))) {
047e0030 5211 if (!adapter->msix_entries)
6eb5a7f1 5212 igb_set_itr(adapter);
46544258 5213 else
047e0030 5214 igb_update_ring_itr(q_vector);
9d5c8243
AK		 5215 }
5216
46544258
AD		 5217 if (!test_bit(__IGB_DOWN, &adapter->state)) {
5218 if (adapter->msix_entries)
047e0030 5219 wr32(E1000_EIMS, q_vector->eims_value);
46544258
AD		 5220 else
5221 igb_irq_enable(adapter);
5222 }
9d5c8243
AK		 5223}
5224
46544258
AD		 5225/**
5226 * igb_poll - NAPI Rx polling callback
5227 * @napi: napi polling structure
5228 * @budget: count of how many packets we should handle
5229 **/
5230static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 5231{
047e0030
AD		 5232 struct igb_q_vector *q_vector = container_of(napi,
5233 struct igb_q_vector,
5234 napi);
5235 int tx_clean_complete = 1, work_done = 0;
9d5c8243 5236
421e02f0 5237#ifdef CONFIG_IGB_DCA
047e0030
AD		 5238 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
5239 igb_update_dca(q_vector);
fe4506b6 5240#endif
047e0030
AD		 5241 if (q_vector->tx_ring)
5242 tx_clean_complete = igb_clean_tx_irq(q_vector);
9d5c8243 5243
047e0030
AD		 5244 if (q_vector->rx_ring)
5245 igb_clean_rx_irq_adv(q_vector, &work_done, budget);
5246
5247 if (!tx_clean_complete)
5248 work_done = budget;
46544258 5249
9d5c8243 5250 /* If not enough Rx work done, exit the polling mode */
5e6d5b17 5251 if (work_done < budget) {
288379f0 5252 napi_complete(napi);
047e0030 5253 igb_ring_irq_enable(q_vector);
9d5c8243
AK		 5254 }
5255
46544258 5256 return work_done;
9d5c8243 5257}
6d8126f9 5258
33af6bcc 5259/**
c5b9bd5e 5260 * igb_systim_to_hwtstamp - convert system time value to hw timestamp
33af6bcc 5261 * @adapter: board private structure
c5b9bd5e
AD		 5262 * @shhwtstamps: timestamp structure to update
5263 * @regval: unsigned 64bit system time value.
5264 *
5265 * We need to convert the system time value stored in the RX/TXSTMP registers
5266 * into a hwtstamp which can be used by the upper level timestamping functions
5267 */
5268static void igb_systim_to_hwtstamp(struct igb_adapter *adapter,
5269 struct skb_shared_hwtstamps *shhwtstamps,
5270 u64 regval)
5271{
5272 u64 ns;
5273
55cac248
AD		 5274 /*
5275 * The 82580 starts with 1ns at bit 0 in RX/TXSTMPL, shift this up to
5276 * 24 to match clock shift we setup earlier.
5277 */
5278 if (adapter->hw.mac.type == e1000_82580)
5279 regval <<= IGB_82580_TSYNC_SHIFT;
5280
c5b9bd5e
AD		 5281 ns = timecounter_cyc2time(&adapter->clock, regval);
5282 timecompare_update(&adapter->compare, ns);
5283 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps));
5284 shhwtstamps->hwtstamp = ns_to_ktime(ns);
5285 shhwtstamps->syststamp = timecompare_transform(&adapter->compare, ns);
5286}
5287
5288/**
5289 * igb_tx_hwtstamp - utility function which checks for TX time stamp
5290 * @q_vector: pointer to q_vector containing needed info
33af6bcc
PO		 5291 * @skb: packet that was just sent
5292 *
5293 * If we were asked to do hardware stamping and such a time stamp is
5294 * available, then it must have been for this skb here because we only
5295 * allow only one such packet into the queue.
5296 */
c5b9bd5e 5297static void igb_tx_hwtstamp(struct igb_q_vector *q_vector, struct sk_buff *skb)
33af6bcc 5298{
c5b9bd5e 5299 struct igb_adapter *adapter = q_vector->adapter;
33af6bcc
PO		 5300 union skb_shared_tx *shtx = skb_tx(skb);
5301 struct e1000_hw *hw = &adapter->hw;
c5b9bd5e
AD		 5302 struct skb_shared_hwtstamps shhwtstamps;
5303 u64 regval;
33af6bcc 5304
c5b9bd5e
AD		 5305 /* if skb does not support hw timestamp or TX stamp not valid exit */
5306 if (likely(!shtx->hardware) ||
5307 !(rd32(E1000_TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID))
5308 return;
5309
5310 regval = rd32(E1000_TXSTMPL);
5311 regval |= (u64)rd32(E1000_TXSTMPH) << 32;
5312
5313 igb_systim_to_hwtstamp(adapter, &shhwtstamps, regval);
5314 skb_tstamp_tx(skb, &shhwtstamps);
33af6bcc
PO		 5315}
5316
9d5c8243
AK		 5317/**
5318 * igb_clean_tx_irq - Reclaim resources after transmit completes
047e0030 5319 * @q_vector: pointer to q_vector containing needed info
9d5c8243
AK		 5320 * returns true if ring is completely cleaned
5321 **/
047e0030 5322static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
9d5c8243 5323{
047e0030
AD		 5324 struct igb_adapter *adapter = q_vector->adapter;
5325 struct igb_ring *tx_ring = q_vector->tx_ring;
e694e964 5326 struct net_device *netdev = tx_ring->netdev;
0e014cb1 5327 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 5328 struct igb_buffer *buffer_info;
5329 struct sk_buff *skb;
0e014cb1 5330 union e1000_adv_tx_desc *tx_desc, *eop_desc;
9d5c8243 5331 unsigned int total_bytes = 0, total_packets = 0;
0e014cb1
AD		 5332 unsigned int i, eop, count = 0;
5333 bool cleaned = false;
9d5c8243 5334
9d5c8243 5335 i = tx_ring->next_to_clean;
0e014cb1
AD		 5336 eop = tx_ring->buffer_info[i].next_to_watch;
5337 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
5338
5339 while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) &&
5340 (count < tx_ring->count)) {
5341 for (cleaned = false; !cleaned; count++) {
5342 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
9d5c8243 5343 buffer_info = &tx_ring->buffer_info[i];
0e014cb1 5344 cleaned = (i == eop);
9d5c8243
AK		 5345 skb = buffer_info->skb;
5346
5347 if (skb) {
5348 unsigned int segs, bytecount;
5349 /* gso_segs is currently only valid for tcp */
40e90c26 5350 segs = buffer_info->gso_segs;
9d5c8243
AK		 5351 /* multiply data chunks by size of headers */
5352 bytecount = ((segs - 1) * skb_headlen(skb)) +
5353 skb->len;
5354 total_packets += segs;
5355 total_bytes += bytecount;
33af6bcc 5356
c5b9bd5e 5357 igb_tx_hwtstamp(q_vector, skb);
9d5c8243
AK		 5358 }
5359
80785298 5360 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
0e014cb1 5361 tx_desc->wb.status = 0;
9d5c8243
AK		 5362
5363 i++;
5364 if (i == tx_ring->count)
5365 i = 0;
9d5c8243 5366 }
0e014cb1
AD		 5367 eop = tx_ring->buffer_info[i].next_to_watch;
5368 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
5369 }
5370
9d5c8243
AK		 5371 tx_ring->next_to_clean = i;
5372
fc7d345d 5373 if (unlikely(count &&
9d5c8243 5374 netif_carrier_ok(netdev) &&
c493ea45 5375 igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
9d5c8243
AK		 5376 /* Make sure that anybody stopping the queue after this
5377 * sees the new next_to_clean.
5378 */
5379 smp_mb();
661086df
PWJ		 5380 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
5381 !(test_bit(__IGB_DOWN, &adapter->state))) {
5382 netif_wake_subqueue(netdev, tx_ring->queue_index);
04a5fcaa 5383 tx_ring->tx_stats.restart_queue++;
661086df 5384 }
9d5c8243
AK		 5385 }
5386
5387 if (tx_ring->detect_tx_hung) {
5388 /* Detect a transmit hang in hardware, this serializes the
5389 * check with the clearing of time_stamp and movement of i */
5390 tx_ring->detect_tx_hung = false;
5391 if (tx_ring->buffer_info[i].time_stamp &&
5392 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
8e95a202
JP		 5393 (adapter->tx_timeout_factor * HZ)) &&
5394 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
9d5c8243 5395
9d5c8243 5396 /* detected Tx unit hang */
59d71989 5397 dev_err(tx_ring->dev,
9d5c8243 5398 "Detected Tx Unit Hang\n"
2d064c06 5399 " Tx Queue <%d>\n"
9d5c8243
AK		 5400 " TDH <%x>\n"
5401 " TDT <%x>\n"
5402 " next_to_use <%x>\n"
5403 " next_to_clean <%x>\n"
9d5c8243
AK		 5404 "buffer_info[next_to_clean]\n"
5405 " time_stamp <%lx>\n"
0e014cb1 5406 " next_to_watch <%x>\n"
9d5c8243
AK		 5407 " jiffies <%lx>\n"
5408 " desc.status <%x>\n",
2d064c06 5409 tx_ring->queue_index,
fce99e34
AD		 5410 readl(tx_ring->head),
5411 readl(tx_ring->tail),
9d5c8243
AK		 5412 tx_ring->next_to_use,
5413 tx_ring->next_to_clean,
f7ba205e 5414 tx_ring->buffer_info[eop].time_stamp,
0e014cb1 5415 eop,
9d5c8243 5416 jiffies,
0e014cb1 5417 eop_desc->wb.status);
661086df 5418 netif_stop_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 5419 }
5420 }
5421 tx_ring->total_bytes += total_bytes;
5422 tx_ring->total_packets += total_packets;
e21ed353
AD		 5423 tx_ring->tx_stats.bytes += total_bytes;
5424 tx_ring->tx_stats.packets += total_packets;
0e014cb1 5425 return (count < tx_ring->count);
9d5c8243
AK		 5426}
5427
9d5c8243
AK		 5428/**
5429 * igb_receive_skb - helper function to handle rx indications
047e0030
AD		 5430 * @q_vector: structure containing interrupt and ring information
5431 * @skb: packet to send up
5432 * @vlan_tag: vlan tag for packet
9d5c8243 5433 **/
047e0030
AD		 5434static void igb_receive_skb(struct igb_q_vector *q_vector,
5435 struct sk_buff *skb,
5436 u16 vlan_tag)
5437{
5438 struct igb_adapter *adapter = q_vector->adapter;
5439
31b24b95 5440 if (vlan_tag && adapter->vlgrp)
047e0030
AD		 5441 vlan_gro_receive(&q_vector->napi, adapter->vlgrp,
5442 vlan_tag, skb);
182ff8df 5443 else
047e0030 5444 napi_gro_receive(&q_vector->napi, skb);
9d5c8243
AK		 5445}
5446
04a5fcaa 5447static inline void igb_rx_checksum_adv(struct igb_ring *ring,
9d5c8243
AK		 5448 u32 status_err, struct sk_buff *skb)
5449{
5450 skb->ip_summed = CHECKSUM_NONE;
5451
5452 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
85ad76b2
AD		 5453 if (!(ring->flags & IGB_RING_FLAG_RX_CSUM) ||
5454 (status_err & E1000_RXD_STAT_IXSM))
9d5c8243 5455 return;
85ad76b2 5456
9d5c8243
AK		 5457 /* TCP/UDP checksum error bit is set */
5458 if (status_err &
5459 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
b9473560
JB		 5460 /*
5461 * work around errata with sctp packets where the TCPE aka
5462 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
5463 * packets, (aka let the stack check the crc32c)
5464 */
85ad76b2
AD		 5465 if ((skb->len == 60) &&
5466 (ring->flags & IGB_RING_FLAG_RX_SCTP_CSUM))
04a5fcaa 5467 ring->rx_stats.csum_err++;
85ad76b2 5468
9d5c8243 5469 /* let the stack verify checksum errors */
9d5c8243
AK		 5470 return;
5471 }
5472 /* It must be a TCP or UDP packet with a valid checksum */
5473 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
5474 skb->ip_summed = CHECKSUM_UNNECESSARY;
5475
59d71989 5476 dev_dbg(ring->dev, "cksum success: bits %08X\n", status_err);
9d5c8243
AK		 5477}
5478
757b77e2 5479static void igb_rx_hwtstamp(struct igb_q_vector *q_vector, u32 staterr,
c5b9bd5e
AD		 5480 struct sk_buff *skb)
5481{
5482 struct igb_adapter *adapter = q_vector->adapter;
5483 struct e1000_hw *hw = &adapter->hw;
5484 u64 regval;
5485
5486 /*
5487 * If this bit is set, then the RX registers contain the time stamp. No
5488 * other packet will be time stamped until we read these registers, so
5489 * read the registers to make them available again. Because only one
5490 * packet can be time stamped at a time, we know that the register
5491 * values must belong to this one here and therefore we don't need to
5492 * compare any of the additional attributes stored for it.
5493 *
5494 * If nothing went wrong, then it should have a skb_shared_tx that we
5495 * can turn into a skb_shared_hwtstamps.
5496 */
757b77e2
NN		 5497 if (staterr & E1000_RXDADV_STAT_TSIP) {
5498 u32 *stamp = (u32 *)skb->data;
5499 regval = le32_to_cpu(*(stamp + 2));
5500 regval |= (u64)le32_to_cpu(*(stamp + 3)) << 32;
5501 skb_pull(skb, IGB_TS_HDR_LEN);
5502 } else {
5503 if(!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
5504 return;
c5b9bd5e 5505
757b77e2
NN		 5506 regval = rd32(E1000_RXSTMPL);
5507 regval |= (u64)rd32(E1000_RXSTMPH) << 32;
5508 }
c5b9bd5e
AD		 5509
5510 igb_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval);
5511}
4c844851 5512static inline u16 igb_get_hlen(struct igb_ring *rx_ring,
2d94d8ab
AD		 5513 union e1000_adv_rx_desc *rx_desc)
5514{
5515 /* HW will not DMA in data larger than the given buffer, even if it
5516 * parses the (NFS, of course) header to be larger. In that case, it
5517 * fills the header buffer and spills the rest into the page.
5518 */
5519 u16 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
5520 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
4c844851
AD		 5521 if (hlen > rx_ring->rx_buffer_len)
5522 hlen = rx_ring->rx_buffer_len;
2d94d8ab
AD		 5523 return hlen;
5524}
5525
047e0030
AD		 5526static bool igb_clean_rx_irq_adv(struct igb_q_vector *q_vector,
5527 int *work_done, int budget)
9d5c8243 5528{
047e0030 5529 struct igb_ring *rx_ring = q_vector->rx_ring;
e694e964 5530 struct net_device *netdev = rx_ring->netdev;
59d71989 5531 struct device *dev = rx_ring->dev;
9d5c8243
AK		 5532 union e1000_adv_rx_desc *rx_desc , *next_rxd;
5533 struct igb_buffer *buffer_info , *next_buffer;
5534 struct sk_buff *skb;
9d5c8243
AK		 5535 bool cleaned = false;
5536 int cleaned_count = 0;
d1eff350 5537 int current_node = numa_node_id();
9d5c8243 5538 unsigned int total_bytes = 0, total_packets = 0;
73cd78f1 5539 unsigned int i;
2d94d8ab
AD		 5540 u32 staterr;
5541 u16 length;
047e0030 5542 u16 vlan_tag;
9d5c8243
AK		 5543
5544 i = rx_ring->next_to_clean;
69d3ca53 5545 buffer_info = &rx_ring->buffer_info[i];
9d5c8243
AK		 5546 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
5547 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
5548
5549 while (staterr & E1000_RXD_STAT_DD) {
5550 if (*work_done >= budget)
5551 break;
5552 (*work_done)++;
9d5c8243 5553
69d3ca53
AD		 5554 skb = buffer_info->skb;
5555 prefetch(skb->data - NET_IP_ALIGN);
5556 buffer_info->skb = NULL;
5557
5558 i++;
5559 if (i == rx_ring->count)
5560 i = 0;
42d0781a 5561
69d3ca53
AD		 5562 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
5563 prefetch(next_rxd);
5564 next_buffer = &rx_ring->buffer_info[i];
9d5c8243
AK		 5565
5566 length = le16_to_cpu(rx_desc->wb.upper.length);
5567 cleaned = true;
5568 cleaned_count++;
5569
2d94d8ab 5570 if (buffer_info->dma) {
59d71989 5571 dma_unmap_single(dev, buffer_info->dma,
4c844851 5572 rx_ring->rx_buffer_len,
59d71989 5573 DMA_FROM_DEVICE);
91615f76 5574 buffer_info->dma = 0;
4c844851 5575 if (rx_ring->rx_buffer_len >= IGB_RXBUFFER_1024) {
6ec43fe6
AD		 5576 skb_put(skb, length);
5577 goto send_up;
5578 }
4c844851 5579 skb_put(skb, igb_get_hlen(rx_ring, rx_desc));
bf36c1a0
AD		 5580 }
5581
5582 if (length) {
59d71989
AD		 5583 dma_unmap_page(dev, buffer_info->page_dma,
5584 PAGE_SIZE / 2, DMA_FROM_DEVICE);
9d5c8243 5585 buffer_info->page_dma = 0;
bf36c1a0 5586
aa913403 5587 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
bf36c1a0
AD		 5588 buffer_info->page,
5589 buffer_info->page_offset,
5590 length);
5591
d1eff350
AD		 5592 if ((page_count(buffer_info->page) != 1) ||
5593 (page_to_nid(buffer_info->page) != current_node))
bf36c1a0
AD		 5594 buffer_info->page = NULL;
5595 else
5596 get_page(buffer_info->page);
9d5c8243
AK		 5597
5598 skb->len += length;
5599 skb->data_len += length;
bf36c1a0 5600 skb->truesize += length;
9d5c8243 5601 }
9d5c8243 5602
bf36c1a0 5603 if (!(staterr & E1000_RXD_STAT_EOP)) {
b2d56536
AD		 5604 buffer_info->skb = next_buffer->skb;
5605 buffer_info->dma = next_buffer->dma;
5606 next_buffer->skb = skb;
5607 next_buffer->dma = 0;
bf36c1a0
AD		 5608 goto next_desc;
5609 }
69d3ca53 5610send_up:
9d5c8243
AK		 5611 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
5612 dev_kfree_skb_irq(skb);
5613 goto next_desc;
5614 }
9d5c8243 5615
757b77e2
NN		 5616 if (staterr & (E1000_RXDADV_STAT_TSIP | E1000_RXDADV_STAT_TS))
5617 igb_rx_hwtstamp(q_vector, staterr, skb);
9d5c8243
AK		 5618 total_bytes += skb->len;
5619 total_packets++;
5620
85ad76b2 5621 igb_rx_checksum_adv(rx_ring, staterr, skb);
9d5c8243
AK		 5622
5623 skb->protocol = eth_type_trans(skb, netdev);
047e0030
AD		 5624 skb_record_rx_queue(skb, rx_ring->queue_index);
5625
5626 vlan_tag = ((staterr & E1000_RXD_STAT_VP) ?
5627 le16_to_cpu(rx_desc->wb.upper.vlan) : 0);
9d5c8243 5628
047e0030 5629 igb_receive_skb(q_vector, skb, vlan_tag);
9d5c8243 5630
9d5c8243
AK		 5631next_desc:
5632 rx_desc->wb.upper.status_error = 0;
5633
5634 /* return some buffers to hardware, one at a time is too slow */
5635 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
3b644cf6 5636 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 5637 cleaned_count = 0;
5638 }
5639
5640 /* use prefetched values */
5641 rx_desc = next_rxd;
5642 buffer_info = next_buffer;
9d5c8243
AK		 5643 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
5644 }
bf36c1a0 5645
9d5c8243 5646 rx_ring->next_to_clean = i;
c493ea45 5647 cleaned_count = igb_desc_unused(rx_ring);
9d5c8243
AK		 5648
5649 if (cleaned_count)
3b644cf6 5650 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 5651
5652 rx_ring->total_packets += total_packets;
5653 rx_ring->total_bytes += total_bytes;
5654 rx_ring->rx_stats.packets += total_packets;
5655 rx_ring->rx_stats.bytes += total_bytes;
9d5c8243
AK		 5656 return cleaned;
5657}
5658
9d5c8243
AK		 5659/**
5660 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
5661 * @adapter: address of board private structure
5662 **/
d7ee5b3a 5663void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring, int cleaned_count)
9d5c8243 5664{
e694e964 5665 struct net_device *netdev = rx_ring->netdev;
9d5c8243
AK		 5666 union e1000_adv_rx_desc *rx_desc;
5667 struct igb_buffer *buffer_info;
5668 struct sk_buff *skb;
5669 unsigned int i;
db761762 5670 int bufsz;
9d5c8243
AK		 5671
5672 i = rx_ring->next_to_use;
5673 buffer_info = &rx_ring->buffer_info[i];
5674
4c844851 5675 bufsz = rx_ring->rx_buffer_len;
db761762 5676
9d5c8243
AK		 5677 while (cleaned_count--) {
5678 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
5679
6ec43fe6 5680 if ((bufsz < IGB_RXBUFFER_1024) && !buffer_info->page_dma) {
9d5c8243 5681 if (!buffer_info->page) {
42d0781a 5682 buffer_info->page = netdev_alloc_page(netdev);
bf36c1a0 5683 if (!buffer_info->page) {
04a5fcaa 5684 rx_ring->rx_stats.alloc_failed++;
bf36c1a0
AD		 5685 goto no_buffers;
5686 }
5687 buffer_info->page_offset = 0;
5688 } else {
5689 buffer_info->page_offset ^= PAGE_SIZE / 2;
9d5c8243
AK		 5690 }
5691 buffer_info->page_dma =
59d71989 5692 dma_map_page(rx_ring->dev, buffer_info->page,
bf36c1a0
AD		 5693 buffer_info->page_offset,
5694 PAGE_SIZE / 2,
59d71989
AD		 5695 DMA_FROM_DEVICE);
5696 if (dma_mapping_error(rx_ring->dev,
5697 buffer_info->page_dma)) {
42d0781a
AD		 5698 buffer_info->page_dma = 0;
5699 rx_ring->rx_stats.alloc_failed++;
5700 goto no_buffers;
5701 }
9d5c8243
AK		 5702 }
5703
42d0781a
AD		 5704 skb = buffer_info->skb;
5705 if (!skb) {
89d71a66 5706 skb = netdev_alloc_skb_ip_align(netdev, bufsz);
9d5c8243 5707 if (!skb) {
04a5fcaa 5708 rx_ring->rx_stats.alloc_failed++;
9d5c8243
AK		 5709 goto no_buffers;
5710 }
5711
9d5c8243 5712 buffer_info->skb = skb;
42d0781a
AD		 5713 }
5714 if (!buffer_info->dma) {
59d71989 5715 buffer_info->dma = dma_map_single(rx_ring->dev,
80785298 5716 skb->data,
9d5c8243 5717 bufsz,
59d71989
AD		 5718 DMA_FROM_DEVICE);
5719 if (dma_mapping_error(rx_ring->dev,
5720 buffer_info->dma)) {
42d0781a
AD		 5721 buffer_info->dma = 0;
5722 rx_ring->rx_stats.alloc_failed++;
5723 goto no_buffers;
5724 }
9d5c8243
AK		 5725 }
5726 /* Refresh the desc even if buffer_addrs didn't change because
5727 * each write-back erases this info. */
6ec43fe6 5728 if (bufsz < IGB_RXBUFFER_1024) {
9d5c8243
AK		 5729 rx_desc->read.pkt_addr =
5730 cpu_to_le64(buffer_info->page_dma);
5731 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
5732 } else {
42d0781a 5733 rx_desc->read.pkt_addr = cpu_to_le64(buffer_info->dma);
9d5c8243
AK		 5734 rx_desc->read.hdr_addr = 0;
5735 }
5736
5737 i++;
5738 if (i == rx_ring->count)
5739 i = 0;
5740 buffer_info = &rx_ring->buffer_info[i];
5741 }
5742
5743no_buffers:
5744 if (rx_ring->next_to_use != i) {
5745 rx_ring->next_to_use = i;
5746 if (i == 0)
5747 i = (rx_ring->count - 1);
5748 else
5749 i--;
5750
5751 /* Force memory writes to complete before letting h/w
5752 * know there are new descriptors to fetch. (Only
5753 * applicable for weak-ordered memory model archs,
5754 * such as IA-64). */
5755 wmb();
fce99e34 5756 writel(i, rx_ring->tail);
9d5c8243
AK		 5757 }
5758}
5759
5760/**
5761 * igb_mii_ioctl -
5762 * @netdev:
5763 * @ifreq:
5764 * @cmd:
5765 **/
5766static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5767{
5768 struct igb_adapter *adapter = netdev_priv(netdev);
5769 struct mii_ioctl_data *data = if_mii(ifr);
5770
5771 if (adapter->hw.phy.media_type != e1000_media_type_copper)
5772 return -EOPNOTSUPP;
5773
5774 switch (cmd) {
5775 case SIOCGMIIPHY:
5776 data->phy_id = adapter->hw.phy.addr;
5777 break;
5778 case SIOCGMIIREG:
f5f4cf08
AD		 5779 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
5780 &data->val_out))
9d5c8243
AK		 5781 return -EIO;
5782 break;
5783 case SIOCSMIIREG:
5784 default:
5785 return -EOPNOTSUPP;
5786 }
5787 return 0;
5788}
5789
c6cb090b
PO		 5790/**
5791 * igb_hwtstamp_ioctl - control hardware time stamping
5792 * @netdev:
5793 * @ifreq:
5794 * @cmd:
5795 *
33af6bcc
PO		 5796 * Outgoing time stamping can be enabled and disabled. Play nice and
5797 * disable it when requested, although it shouldn't case any overhead
5798 * when no packet needs it. At most one packet in the queue may be
5799 * marked for time stamping, otherwise it would be impossible to tell
5800 * for sure to which packet the hardware time stamp belongs.
5801 *
5802 * Incoming time stamping has to be configured via the hardware
5803 * filters. Not all combinations are supported, in particular event
5804 * type has to be specified. Matching the kind of event packet is
5805 * not supported, with the exception of "all V2 events regardless of
5806 * level 2 or 4".
5807 *
c6cb090b
PO		 5808 **/
5809static int igb_hwtstamp_ioctl(struct net_device *netdev,
5810 struct ifreq *ifr, int cmd)
5811{
33af6bcc
PO		 5812 struct igb_adapter *adapter = netdev_priv(netdev);
5813 struct e1000_hw *hw = &adapter->hw;
c6cb090b 5814 struct hwtstamp_config config;
c5b9bd5e
AD		 5815 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
5816 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
33af6bcc 5817 u32 tsync_rx_cfg = 0;
c5b9bd5e
AD		 5818 bool is_l4 = false;
5819 bool is_l2 = false;
33af6bcc 5820 u32 regval;
c6cb090b
PO		 5821
5822 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
5823 return -EFAULT;
5824
5825 /* reserved for future extensions */
5826 if (config.flags)
5827 return -EINVAL;
5828
33af6bcc
PO		 5829 switch (config.tx_type) {
5830 case HWTSTAMP_TX_OFF:
c5b9bd5e 5831 tsync_tx_ctl = 0;
33af6bcc 5832 case HWTSTAMP_TX_ON:
33af6bcc
PO		 5833 break;
5834 default:
5835 return -ERANGE;
5836 }
5837
5838 switch (config.rx_filter) {
5839 case HWTSTAMP_FILTER_NONE:
c5b9bd5e 5840 tsync_rx_ctl = 0;
33af6bcc
PO		 5841 break;
5842 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
5843 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
5844 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
5845 case HWTSTAMP_FILTER_ALL:
5846 /*
5847 * register TSYNCRXCFG must be set, therefore it is not
5848 * possible to time stamp both Sync and Delay_Req messages
5849 * => fall back to time stamping all packets
5850 */
c5b9bd5e 5851 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
33af6bcc
PO		 5852 config.rx_filter = HWTSTAMP_FILTER_ALL;
5853 break;
5854 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
c5b9bd5e 5855 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
33af6bcc 5856 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
c5b9bd5e 5857 is_l4 = true;
33af6bcc
PO		 5858 break;
5859 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
c5b9bd5e 5860 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
33af6bcc 5861 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
c5b9bd5e 5862 is_l4 = true;
33af6bcc
PO		 5863 break;
5864 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
5865 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
c5b9bd5e 5866 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
33af6bcc 5867 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE;
c5b9bd5e
AD		 5868 is_l2 = true;
5869 is_l4 = true;
33af6bcc
PO		 5870 config.rx_filter = HWTSTAMP_FILTER_SOME;
5871 break;
5872 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
5873 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
c5b9bd5e 5874 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
33af6bcc 5875 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE;
c5b9bd5e
AD		 5876 is_l2 = true;
5877 is_l4 = true;
33af6bcc
PO		 5878 config.rx_filter = HWTSTAMP_FILTER_SOME;
5879 break;
5880 case HWTSTAMP_FILTER_PTP_V2_EVENT:
5881 case HWTSTAMP_FILTER_PTP_V2_SYNC:
5882 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
c5b9bd5e 5883 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
33af6bcc 5884 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
c5b9bd5e 5885 is_l2 = true;
33af6bcc
PO		 5886 break;
5887 default:
5888 return -ERANGE;
5889 }
5890
c5b9bd5e
AD		 5891 if (hw->mac.type == e1000_82575) {
5892 if (tsync_rx_ctl | tsync_tx_ctl)
5893 return -EINVAL;
5894 return 0;
5895 }
5896
757b77e2
NN		 5897 /*
5898 * Per-packet timestamping only works if all packets are
5899 * timestamped, so enable timestamping in all packets as
5900 * long as one rx filter was configured.
5901 */
5902 if ((hw->mac.type == e1000_82580) && tsync_rx_ctl) {
5903 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
5904 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
5905 }
5906
33af6bcc
PO		 5907 /* enable/disable TX */
5908 regval = rd32(E1000_TSYNCTXCTL);
c5b9bd5e
AD		 5909 regval &= ~E1000_TSYNCTXCTL_ENABLED;
5910 regval |= tsync_tx_ctl;
33af6bcc
PO		 5911 wr32(E1000_TSYNCTXCTL, regval);
5912
c5b9bd5e 5913 /* enable/disable RX */
33af6bcc 5914 regval = rd32(E1000_TSYNCRXCTL);
c5b9bd5e
AD		 5915 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
5916 regval |= tsync_rx_ctl;
33af6bcc 5917 wr32(E1000_TSYNCRXCTL, regval);
33af6bcc 5918
c5b9bd5e
AD		 5919 /* define which PTP packets are time stamped */
5920 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
33af6bcc 5921
c5b9bd5e
AD		 5922 /* define ethertype filter for timestamped packets */
5923 if (is_l2)
5924 wr32(E1000_ETQF(3),
5925 (E1000_ETQF_FILTER_ENABLE | /* enable filter */
5926 E1000_ETQF_1588 | /* enable timestamping */
5927 ETH_P_1588)); /* 1588 eth protocol type */
5928 else
5929 wr32(E1000_ETQF(3), 0);
5930
5931#define PTP_PORT 319
5932 /* L4 Queue Filter[3]: filter by destination port and protocol */
5933 if (is_l4) {
5934 u32 ftqf = (IPPROTO_UDP /* UDP */
5935 | E1000_FTQF_VF_BP /* VF not compared */
5936 | E1000_FTQF_1588_TIME_STAMP /* Enable Timestamping */
5937 | E1000_FTQF_MASK); /* mask all inputs */
5938 ftqf &= ~E1000_FTQF_MASK_PROTO_BP; /* enable protocol check */
5939
5940 wr32(E1000_IMIR(3), htons(PTP_PORT));
5941 wr32(E1000_IMIREXT(3),
5942 (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP));
5943 if (hw->mac.type == e1000_82576) {
5944 /* enable source port check */
5945 wr32(E1000_SPQF(3), htons(PTP_PORT));
5946 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
5947 }
5948 wr32(E1000_FTQF(3), ftqf);
5949 } else {
5950 wr32(E1000_FTQF(3), E1000_FTQF_MASK);
5951 }
33af6bcc
PO		 5952 wrfl();
5953
5954 adapter->hwtstamp_config = config;
5955
5956 /* clear TX/RX time stamp registers, just to be sure */
5957 regval = rd32(E1000_TXSTMPH);
5958 regval = rd32(E1000_RXSTMPH);
c6cb090b 5959
33af6bcc
PO		 5960 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
5961 -EFAULT : 0;
c6cb090b
PO		 5962}
5963
9d5c8243
AK		 5964/**
5965 * igb_ioctl -
5966 * @netdev:
5967 * @ifreq:
5968 * @cmd:
5969 **/
5970static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5971{
5972 switch (cmd) {
5973 case SIOCGMIIPHY:
5974 case SIOCGMIIREG:
5975 case SIOCSMIIREG:
5976 return igb_mii_ioctl(netdev, ifr, cmd);
c6cb090b
PO		 5977 case SIOCSHWTSTAMP:
5978 return igb_hwtstamp_ioctl(netdev, ifr, cmd);
9d5c8243
AK		 5979 default:
5980 return -EOPNOTSUPP;
5981 }
5982}
5983
009bc06e
AD		 5984s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
5985{
5986 struct igb_adapter *adapter = hw->back;
5987 u16 cap_offset;
5988
5989 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
5990 if (!cap_offset)
5991 return -E1000_ERR_CONFIG;
5992
5993 pci_read_config_word(adapter->pdev, cap_offset + reg, value);
5994
5995 return 0;
5996}
5997
5998s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
5999{
6000 struct igb_adapter *adapter = hw->back;
6001 u16 cap_offset;
6002
6003 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
6004 if (!cap_offset)
6005 return -E1000_ERR_CONFIG;
6006
6007 pci_write_config_word(adapter->pdev, cap_offset + reg, *value);
6008
6009 return 0;
6010}
6011
9d5c8243
AK		 6012static void igb_vlan_rx_register(struct net_device *netdev,
6013 struct vlan_group *grp)
6014{
6015 struct igb_adapter *adapter = netdev_priv(netdev);
6016 struct e1000_hw *hw = &adapter->hw;
6017 u32 ctrl, rctl;
6018
6019 igb_irq_disable(adapter);
6020 adapter->vlgrp = grp;
6021
6022 if (grp) {
6023 /* enable VLAN tag insert/strip */
6024 ctrl = rd32(E1000_CTRL);
6025 ctrl |= E1000_CTRL_VME;
6026 wr32(E1000_CTRL, ctrl);
6027
51466239 6028 /* Disable CFI check */
9d5c8243 6029 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 6030 rctl &= ~E1000_RCTL_CFIEN;
6031 wr32(E1000_RCTL, rctl);
9d5c8243
AK		 6032 } else {
6033 /* disable VLAN tag insert/strip */
6034 ctrl = rd32(E1000_CTRL);
6035 ctrl &= ~E1000_CTRL_VME;
6036 wr32(E1000_CTRL, ctrl);
9d5c8243
AK		 6037 }
6038
e1739522
AD		 6039 igb_rlpml_set(adapter);
6040
9d5c8243
AK		 6041 if (!test_bit(__IGB_DOWN, &adapter->state))
6042 igb_irq_enable(adapter);
6043}
6044
6045static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
6046{
6047 struct igb_adapter *adapter = netdev_priv(netdev);
6048 struct e1000_hw *hw = &adapter->hw;
4ae196df 6049 int pf_id = adapter->vfs_allocated_count;
9d5c8243 6050
51466239
AD		 6051 /* attempt to add filter to vlvf array */
6052 igb_vlvf_set(adapter, vid, true, pf_id);
4ae196df 6053
51466239
AD		 6054 /* add the filter since PF can receive vlans w/o entry in vlvf */
6055 igb_vfta_set(hw, vid, true);
9d5c8243
AK		 6056}
6057
6058static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
6059{
6060 struct igb_adapter *adapter = netdev_priv(netdev);
6061 struct e1000_hw *hw = &adapter->hw;
4ae196df 6062 int pf_id = adapter->vfs_allocated_count;
51466239 6063 s32 err;
9d5c8243
AK		 6064
6065 igb_irq_disable(adapter);
6066 vlan_group_set_device(adapter->vlgrp, vid, NULL);
6067
6068 if (!test_bit(__IGB_DOWN, &adapter->state))
6069 igb_irq_enable(adapter);
6070
51466239
AD		 6071 /* remove vlan from VLVF table array */
6072 err = igb_vlvf_set(adapter, vid, false, pf_id);
9d5c8243 6073
51466239
AD		 6074 /* if vid was not present in VLVF just remove it from table */
6075 if (err)
4ae196df 6076 igb_vfta_set(hw, vid, false);
9d5c8243
AK		 6077}
6078
6079static void igb_restore_vlan(struct igb_adapter *adapter)
6080{
6081 igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
6082
6083 if (adapter->vlgrp) {
6084 u16 vid;
6085 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
6086 if (!vlan_group_get_device(adapter->vlgrp, vid))
6087 continue;
6088 igb_vlan_rx_add_vid(adapter->netdev, vid);
6089 }
6090 }
6091}
6092
6093int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
6094{
090b1795 6095 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 6096 struct e1000_mac_info *mac = &adapter->hw.mac;
6097
6098 mac->autoneg = 0;
6099
9d5c8243
AK		 6100 switch (spddplx) {
6101 case SPEED_10 + DUPLEX_HALF:
6102 mac->forced_speed_duplex = ADVERTISE_10_HALF;
6103 break;
6104 case SPEED_10 + DUPLEX_FULL:
6105 mac->forced_speed_duplex = ADVERTISE_10_FULL;
6106 break;
6107 case SPEED_100 + DUPLEX_HALF:
6108 mac->forced_speed_duplex = ADVERTISE_100_HALF;
6109 break;
6110 case SPEED_100 + DUPLEX_FULL:
6111 mac->forced_speed_duplex = ADVERTISE_100_FULL;
6112 break;
6113 case SPEED_1000 + DUPLEX_FULL:
6114 mac->autoneg = 1;
6115 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
6116 break;
6117 case SPEED_1000 + DUPLEX_HALF: /* not supported */
6118 default:
090b1795 6119 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
9d5c8243
AK		 6120 return -EINVAL;
6121 }
6122 return 0;
6123}
6124
3fe7c4c9 6125static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake)
9d5c8243
AK		 6126{
6127 struct net_device *netdev = pci_get_drvdata(pdev);
6128 struct igb_adapter *adapter = netdev_priv(netdev);
6129 struct e1000_hw *hw = &adapter->hw;
2d064c06 6130 u32 ctrl, rctl, status;
9d5c8243
AK		 6131 u32 wufc = adapter->wol;
6132#ifdef CONFIG_PM
6133 int retval = 0;
6134#endif
6135
6136 netif_device_detach(netdev);
6137
a88f10ec
AD		 6138 if (netif_running(netdev))
6139 igb_close(netdev);
6140
047e0030 6141 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 6142
6143#ifdef CONFIG_PM
6144 retval = pci_save_state(pdev);
6145 if (retval)
6146 return retval;
6147#endif
6148
6149 status = rd32(E1000_STATUS);
6150 if (status & E1000_STATUS_LU)
6151 wufc &= ~E1000_WUFC_LNKC;
6152
6153 if (wufc) {
6154 igb_setup_rctl(adapter);
ff41f8dc 6155 igb_set_rx_mode(netdev);
9d5c8243
AK		 6156
6157 /* turn on all-multi mode if wake on multicast is enabled */
6158 if (wufc & E1000_WUFC_MC) {
6159 rctl = rd32(E1000_RCTL);
6160 rctl |= E1000_RCTL_MPE;
6161 wr32(E1000_RCTL, rctl);
6162 }
6163
6164 ctrl = rd32(E1000_CTRL);
6165 /* advertise wake from D3Cold */
6166 #define E1000_CTRL_ADVD3WUC 0x00100000
6167 /* phy power management enable */
6168 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
6169 ctrl |= E1000_CTRL_ADVD3WUC;
6170 wr32(E1000_CTRL, ctrl);
6171
9d5c8243 6172 /* Allow time for pending master requests to run */
330a6d6a 6173 igb_disable_pcie_master(hw);
9d5c8243
AK		 6174
6175 wr32(E1000_WUC, E1000_WUC_PME_EN);
6176 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 6177 } else {
6178 wr32(E1000_WUC, 0);
6179 wr32(E1000_WUFC, 0);
9d5c8243
AK		 6180 }
6181
3fe7c4c9
RW		 6182 *enable_wake = wufc || adapter->en_mng_pt;
6183 if (!*enable_wake)
88a268c1
NN		 6184 igb_power_down_link(adapter);
6185 else
6186 igb_power_up_link(adapter);
9d5c8243
AK		 6187
6188 /* Release control of h/w to f/w. If f/w is AMT enabled, this
6189 * would have already happened in close and is redundant. */
6190 igb_release_hw_control(adapter);
6191
6192 pci_disable_device(pdev);
6193
9d5c8243
AK		 6194 return 0;
6195}
6196
6197#ifdef CONFIG_PM
3fe7c4c9
RW		 6198static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
6199{
6200 int retval;
6201 bool wake;
6202
6203 retval = __igb_shutdown(pdev, &wake);
6204 if (retval)
6205 return retval;
6206
6207 if (wake) {
6208 pci_prepare_to_sleep(pdev);
6209 } else {
6210 pci_wake_from_d3(pdev, false);
6211 pci_set_power_state(pdev, PCI_D3hot);
6212 }
6213
6214 return 0;
6215}
6216
9d5c8243
AK		 6217static int igb_resume(struct pci_dev *pdev)
6218{
6219 struct net_device *netdev = pci_get_drvdata(pdev);
6220 struct igb_adapter *adapter = netdev_priv(netdev);
6221 struct e1000_hw *hw = &adapter->hw;
6222 u32 err;
6223
6224 pci_set_power_state(pdev, PCI_D0);
6225 pci_restore_state(pdev);
b94f2d77 6226 pci_save_state(pdev);
42bfd33a 6227
aed5dec3 6228 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 6229 if (err) {
6230 dev_err(&pdev->dev,
6231 "igb: Cannot enable PCI device from suspend\n");
6232 return err;
6233 }
6234 pci_set_master(pdev);
6235
6236 pci_enable_wake(pdev, PCI_D3hot, 0);
6237 pci_enable_wake(pdev, PCI_D3cold, 0);
6238
047e0030 6239 if (igb_init_interrupt_scheme(adapter)) {
a88f10ec
AD		 6240 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
6241 return -ENOMEM;
9d5c8243
AK		 6242 }
6243
9d5c8243 6244 igb_reset(adapter);
a8564f03
AD		 6245
6246 /* let the f/w know that the h/w is now under the control of the
6247 * driver. */
6248 igb_get_hw_control(adapter);
6249
9d5c8243
AK		 6250 wr32(E1000_WUS, ~0);
6251
a88f10ec
AD		 6252 if (netif_running(netdev)) {
6253 err = igb_open(netdev);
6254 if (err)
6255 return err;
6256 }
9d5c8243
AK		 6257
6258 netif_device_attach(netdev);
6259
9d5c8243
AK		 6260 return 0;
6261}
6262#endif
6263
6264static void igb_shutdown(struct pci_dev *pdev)
6265{
3fe7c4c9
RW		 6266 bool wake;
6267
6268 __igb_shutdown(pdev, &wake);
6269
6270 if (system_state == SYSTEM_POWER_OFF) {
6271 pci_wake_from_d3(pdev, wake);
6272 pci_set_power_state(pdev, PCI_D3hot);
6273 }
9d5c8243
AK		 6274}
6275
6276#ifdef CONFIG_NET_POLL_CONTROLLER
6277/*
6278 * Polling 'interrupt' - used by things like netconsole to send skbs
6279 * without having to re-enable interrupts. It's not called while
6280 * the interrupt routine is executing.
6281 */
6282static void igb_netpoll(struct net_device *netdev)
6283{
6284 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 6285 struct e1000_hw *hw = &adapter->hw;
9d5c8243 6286 int i;
9d5c8243 6287
eebbbdba 6288 if (!adapter->msix_entries) {
047e0030 6289 struct igb_q_vector *q_vector = adapter->q_vector[0];
eebbbdba 6290 igb_irq_disable(adapter);
047e0030 6291 napi_schedule(&q_vector->napi);
eebbbdba
AD		 6292 return;
6293 }
9d5c8243 6294
047e0030
AD		 6295 for (i = 0; i < adapter->num_q_vectors; i++) {
6296 struct igb_q_vector *q_vector = adapter->q_vector[i];
6297 wr32(E1000_EIMC, q_vector->eims_value);
6298 napi_schedule(&q_vector->napi);
eebbbdba 6299 }
9d5c8243
AK		 6300}
6301#endif /* CONFIG_NET_POLL_CONTROLLER */
6302
6303/**
6304 * igb_io_error_detected - called when PCI error is detected
6305 * @pdev: Pointer to PCI device
6306 * @state: The current pci connection state
6307 *
6308 * This function is called after a PCI bus error affecting
6309 * this device has been detected.
6310 */
6311static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
6312 pci_channel_state_t state)
6313{
6314 struct net_device *netdev = pci_get_drvdata(pdev);
6315 struct igb_adapter *adapter = netdev_priv(netdev);
6316
6317 netif_device_detach(netdev);
6318
59ed6eec
AD		 6319 if (state == pci_channel_io_perm_failure)
6320 return PCI_ERS_RESULT_DISCONNECT;
6321
9d5c8243
AK		 6322 if (netif_running(netdev))
6323 igb_down(adapter);
6324 pci_disable_device(pdev);
6325
6326 /* Request a slot slot reset. */
6327 return PCI_ERS_RESULT_NEED_RESET;
6328}
6329
6330/**
6331 * igb_io_slot_reset - called after the pci bus has been reset.
6332 * @pdev: Pointer to PCI device
6333 *
6334 * Restart the card from scratch, as if from a cold-boot. Implementation
6335 * resembles the first-half of the igb_resume routine.
6336 */
6337static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
6338{
6339 struct net_device *netdev = pci_get_drvdata(pdev);
6340 struct igb_adapter *adapter = netdev_priv(netdev);
6341 struct e1000_hw *hw = &adapter->hw;
40a914fa 6342 pci_ers_result_t result;
42bfd33a 6343 int err;
9d5c8243 6344
aed5dec3 6345 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 6346 dev_err(&pdev->dev,
6347 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 6348 result = PCI_ERS_RESULT_DISCONNECT;
6349 } else {
6350 pci_set_master(pdev);
6351 pci_restore_state(pdev);
b94f2d77 6352 pci_save_state(pdev);
9d5c8243 6353
40a914fa
AD		 6354 pci_enable_wake(pdev, PCI_D3hot, 0);
6355 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 6356
40a914fa
AD		 6357 igb_reset(adapter);
6358 wr32(E1000_WUS, ~0);
6359 result = PCI_ERS_RESULT_RECOVERED;
6360 }
9d5c8243 6361
ea943d41
JK		 6362 err = pci_cleanup_aer_uncorrect_error_status(pdev);
6363 if (err) {
6364 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
6365 "failed 0x%0x\n", err);
6366 /* non-fatal, continue */
6367 }
40a914fa
AD		 6368
6369 return result;
9d5c8243
AK		 6370}
6371
6372/**
6373 * igb_io_resume - called when traffic can start flowing again.
6374 * @pdev: Pointer to PCI device
6375 *
6376 * This callback is called when the error recovery driver tells us that
6377 * its OK to resume normal operation. Implementation resembles the
6378 * second-half of the igb_resume routine.
6379 */
6380static void igb_io_resume(struct pci_dev *pdev)
6381{
6382 struct net_device *netdev = pci_get_drvdata(pdev);
6383 struct igb_adapter *adapter = netdev_priv(netdev);
6384
9d5c8243
AK		 6385 if (netif_running(netdev)) {
6386 if (igb_up(adapter)) {
6387 dev_err(&pdev->dev, "igb_up failed after reset\n");
6388 return;
6389 }
6390 }
6391
6392 netif_device_attach(netdev);
6393
6394 /* let the f/w know that the h/w is now under the control of the
6395 * driver. */
6396 igb_get_hw_control(adapter);
9d5c8243
AK		 6397}
6398
26ad9178
AD		 6399static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
6400 u8 qsel)
6401{
6402 u32 rar_low, rar_high;
6403 struct e1000_hw *hw = &adapter->hw;
6404
6405 /* HW expects these in little endian so we reverse the byte order
6406 * from network order (big endian) to little endian
6407 */
6408 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
6409 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
6410 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
6411
6412 /* Indicate to hardware the Address is Valid. */
6413 rar_high |= E1000_RAH_AV;
6414
6415 if (hw->mac.type == e1000_82575)
6416 rar_high |= E1000_RAH_POOL_1 * qsel;
6417 else
6418 rar_high |= E1000_RAH_POOL_1 << qsel;
6419
6420 wr32(E1000_RAL(index), rar_low);
6421 wrfl();
6422 wr32(E1000_RAH(index), rar_high);
6423 wrfl();
6424}
6425
4ae196df
AD		 6426static int igb_set_vf_mac(struct igb_adapter *adapter,
6427 int vf, unsigned char *mac_addr)
6428{
6429 struct e1000_hw *hw = &adapter->hw;
ff41f8dc
AD		 6430 /* VF MAC addresses start at end of receive addresses and moves
6431 * torwards the first, as a result a collision should not be possible */
6432 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 6433
37680117 6434 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 6435
26ad9178 6436 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
4ae196df
AD		 6437
6438 return 0;
6439}
6440
8151d294
WM		 6441static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
6442{
6443 struct igb_adapter *adapter = netdev_priv(netdev);
6444 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
6445 return -EINVAL;
6446 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
6447 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
6448 dev_info(&adapter->pdev->dev, "Reload the VF driver to make this"
6449 " change effective.");
6450 if (test_bit(__IGB_DOWN, &adapter->state)) {
6451 dev_warn(&adapter->pdev->dev, "The VF MAC address has been set,"
6452 " but the PF device is not up.\n");
6453 dev_warn(&adapter->pdev->dev, "Bring the PF device up before"
6454 " attempting to use the VF device.\n");
6455 }
6456 return igb_set_vf_mac(adapter, vf, mac);
6457}
6458
6459static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate)
6460{
6461 return -EOPNOTSUPP;
6462}
6463
6464static int igb_ndo_get_vf_config(struct net_device *netdev,
6465 int vf, struct ifla_vf_info *ivi)
6466{
6467 struct igb_adapter *adapter = netdev_priv(netdev);
6468 if (vf >= adapter->vfs_allocated_count)
6469 return -EINVAL;
6470 ivi->vf = vf;
6471 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
6472 ivi->tx_rate = 0;
6473 ivi->vlan = adapter->vf_data[vf].pf_vlan;
6474 ivi->qos = adapter->vf_data[vf].pf_qos;
6475 return 0;
6476}
6477
4ae196df
AD		 6478static void igb_vmm_control(struct igb_adapter *adapter)
6479{
6480 struct e1000_hw *hw = &adapter->hw;
10d8e907 6481 u32 reg;
4ae196df 6482
52a1dd4d
AD		 6483 switch (hw->mac.type) {
6484 case e1000_82575:
6485 default:
6486 /* replication is not supported for 82575 */
4ae196df 6487 return;
52a1dd4d
AD		 6488 case e1000_82576:
6489 /* notify HW that the MAC is adding vlan tags */
6490 reg = rd32(E1000_DTXCTL);
6491 reg |= E1000_DTXCTL_VLAN_ADDED;
6492 wr32(E1000_DTXCTL, reg);
6493 case e1000_82580:
6494 /* enable replication vlan tag stripping */
6495 reg = rd32(E1000_RPLOLR);
6496 reg |= E1000_RPLOLR_STRVLAN;
6497 wr32(E1000_RPLOLR, reg);
d2ba2ed8
AD		 6498 case e1000_i350:
6499 /* none of the above registers are supported by i350 */
52a1dd4d
AD		 6500 break;
6501 }
10d8e907 6502
d4960307
AD		 6503 if (adapter->vfs_allocated_count) {
6504 igb_vmdq_set_loopback_pf(hw, true);
6505 igb_vmdq_set_replication_pf(hw, true);
6506 } else {
6507 igb_vmdq_set_loopback_pf(hw, false);
6508 igb_vmdq_set_replication_pf(hw, false);
6509 }
4ae196df
AD		 6510}
6511
9d5c8243 6512/* igb_main.c */
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