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igb: cap interrupts at 20K per queue when in itr mode 3
[mirror_ubuntu-artful-kernel.git] / drivers / net / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
86d5d38f 4 Copyright(c) 2007-2009 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/module.h>
29#include <linux/types.h>
30#include <linux/init.h>
31#include <linux/vmalloc.h>
32#include <linux/pagemap.h>
33#include <linux/netdevice.h>
9d5c8243
AK		 34#include <linux/ipv6.h>
35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
c6cb090b 37#include <linux/net_tstamp.h>
9d5c8243
AK		 38#include <linux/mii.h>
39#include <linux/ethtool.h>
40#include <linux/if_vlan.h>
41#include <linux/pci.h>
c54106bb 42#include <linux/pci-aspm.h>
9d5c8243
AK		 43#include <linux/delay.h>
44#include <linux/interrupt.h>
45#include <linux/if_ether.h>
40a914fa 46#include <linux/aer.h>
421e02f0 47#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 48#include <linux/dca.h>
49#endif
9d5c8243
AK		 50#include "igb.h"
51
55cac248 52#define DRV_VERSION "2.1.0-k2"
9d5c8243
AK		 53char igb_driver_name[] = "igb";
54char igb_driver_version[] = DRV_VERSION;
55static const char igb_driver_string[] =
56 "Intel(R) Gigabit Ethernet Network Driver";
86d5d38f 57static const char igb_copyright[] = "Copyright (c) 2007-2009 Intel Corporation.";
9d5c8243 58
9d5c8243
AK		 59static const struct e1000_info *igb_info_tbl[] = {
60 [board_82575] = &e1000_82575_info,
61};
62
a3aa1884 63static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = {
55cac248
AD		 64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
2d064c06 69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 70 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
747d49ba 71 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
2d064c06
AD		 72 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
73 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 74 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
c8ea5ea9 75 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
79 /* required last entry */
80 {0, }
81};
82
83MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
84
85void igb_reset(struct igb_adapter *);
86static int igb_setup_all_tx_resources(struct igb_adapter *);
87static int igb_setup_all_rx_resources(struct igb_adapter *);
88static void igb_free_all_tx_resources(struct igb_adapter *);
89static void igb_free_all_rx_resources(struct igb_adapter *);
06cf2666 90static void igb_setup_mrqc(struct igb_adapter *);
9d5c8243
AK		 91void igb_update_stats(struct igb_adapter *);
92static int igb_probe(struct pci_dev *, const struct pci_device_id *);
93static void __devexit igb_remove(struct pci_dev *pdev);
94static int igb_sw_init(struct igb_adapter *);
95static int igb_open(struct net_device *);
96static int igb_close(struct net_device *);
97static void igb_configure_tx(struct igb_adapter *);
98static void igb_configure_rx(struct igb_adapter *);
9d5c8243
AK		 99static void igb_clean_all_tx_rings(struct igb_adapter *);
100static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 101static void igb_clean_tx_ring(struct igb_ring *);
102static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 103static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 104static void igb_update_phy_info(unsigned long);
105static void igb_watchdog(unsigned long);
106static void igb_watchdog_task(struct work_struct *);
b1a436c3 107static netdev_tx_t igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
9d5c8243
AK		 108static struct net_device_stats *igb_get_stats(struct net_device *);
109static int igb_change_mtu(struct net_device *, int);
110static int igb_set_mac(struct net_device *, void *);
68d480c4 111static void igb_set_uta(struct igb_adapter *adapter);
9d5c8243
AK		 112static irqreturn_t igb_intr(int irq, void *);
113static irqreturn_t igb_intr_msi(int irq, void *);
114static irqreturn_t igb_msix_other(int irq, void *);
047e0030 115static irqreturn_t igb_msix_ring(int irq, void *);
421e02f0 116#ifdef CONFIG_IGB_DCA
047e0030 117static void igb_update_dca(struct igb_q_vector *);
fe4506b6 118static void igb_setup_dca(struct igb_adapter *);
421e02f0 119#endif /* CONFIG_IGB_DCA */
047e0030 120static bool igb_clean_tx_irq(struct igb_q_vector *);
661086df 121static int igb_poll(struct napi_struct *, int);
047e0030 122static bool igb_clean_rx_irq_adv(struct igb_q_vector *, int *, int);
9d5c8243
AK		 123static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
124static void igb_tx_timeout(struct net_device *);
125static void igb_reset_task(struct work_struct *);
126static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
127static void igb_vlan_rx_add_vid(struct net_device *, u16);
128static void igb_vlan_rx_kill_vid(struct net_device *, u16);
129static void igb_restore_vlan(struct igb_adapter *);
26ad9178 130static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
4ae196df
AD		 131static void igb_ping_all_vfs(struct igb_adapter *);
132static void igb_msg_task(struct igb_adapter *);
4ae196df 133static void igb_vmm_control(struct igb_adapter *);
f2ca0dbe 134static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
4ae196df 135static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
8151d294
WM		 136static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
137static int igb_ndo_set_vf_vlan(struct net_device *netdev,
138 int vf, u16 vlan, u8 qos);
139static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate);
140static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
141 struct ifla_vf_info *ivi);
9d5c8243 142
9d5c8243 143#ifdef CONFIG_PM
3fe7c4c9 144static int igb_suspend(struct pci_dev *, pm_message_t);
9d5c8243
AK		 145static int igb_resume(struct pci_dev *);
146#endif
147static void igb_shutdown(struct pci_dev *);
421e02f0 148#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 149static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
150static struct notifier_block dca_notifier = {
151 .notifier_call = igb_notify_dca,
152 .next = NULL,
153 .priority = 0
154};
155#endif
9d5c8243
AK		 156#ifdef CONFIG_NET_POLL_CONTROLLER
157/* for netdump / net console */
158static void igb_netpoll(struct net_device *);
159#endif
37680117 160#ifdef CONFIG_PCI_IOV
2a3abf6d
AD		 161static unsigned int max_vfs = 0;
162module_param(max_vfs, uint, 0);
163MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
164 "per physical function");
165#endif /* CONFIG_PCI_IOV */
166
9d5c8243
AK		 167static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
168 pci_channel_state_t);
169static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
170static void igb_io_resume(struct pci_dev *);
171
172static struct pci_error_handlers igb_err_handler = {
173 .error_detected = igb_io_error_detected,
174 .slot_reset = igb_io_slot_reset,
175 .resume = igb_io_resume,
176};
177
178
179static struct pci_driver igb_driver = {
180 .name = igb_driver_name,
181 .id_table = igb_pci_tbl,
182 .probe = igb_probe,
183 .remove = __devexit_p(igb_remove),
184#ifdef CONFIG_PM
185 /* Power Managment Hooks */
186 .suspend = igb_suspend,
187 .resume = igb_resume,
188#endif
189 .shutdown = igb_shutdown,
190 .err_handler = &igb_err_handler
191};
192
193MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
194MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
195MODULE_LICENSE("GPL");
196MODULE_VERSION(DRV_VERSION);
197
38c845c7
PO		 198/**
199 * igb_read_clock - read raw cycle counter (to be used by time counter)
200 */
201static cycle_t igb_read_clock(const struct cyclecounter *tc)
202{
203 struct igb_adapter *adapter =
204 container_of(tc, struct igb_adapter, cycles);
205 struct e1000_hw *hw = &adapter->hw;
c5b9bd5e
AD		 206 u64 stamp = 0;
207 int shift = 0;
38c845c7 208
55cac248
AD		 209 /*
210 * The timestamp latches on lowest register read. For the 82580
211 * the lowest register is SYSTIMR instead of SYSTIML. However we never
212 * adjusted TIMINCA so SYSTIMR will just read as all 0s so ignore it.
213 */
214 if (hw->mac.type == e1000_82580) {
215 stamp = rd32(E1000_SYSTIMR) >> 8;
216 shift = IGB_82580_TSYNC_SHIFT;
217 }
218
c5b9bd5e
AD		 219 stamp |= (u64)rd32(E1000_SYSTIML) << shift;
220 stamp |= (u64)rd32(E1000_SYSTIMH) << (shift + 32);
38c845c7
PO		 221 return stamp;
222}
223
9d5c8243
AK		 224#ifdef DEBUG
225/**
226 * igb_get_hw_dev_name - return device name string
227 * used by hardware layer to print debugging information
228 **/
229char *igb_get_hw_dev_name(struct e1000_hw *hw)
230{
231 struct igb_adapter *adapter = hw->back;
232 return adapter->netdev->name;
233}
38c845c7
PO		 234
235/**
236 * igb_get_time_str - format current NIC and system time as string
237 */
238static char *igb_get_time_str(struct igb_adapter *adapter,
239 char buffer[160])
240{
241 cycle_t hw = adapter->cycles.read(&adapter->cycles);
242 struct timespec nic = ns_to_timespec(timecounter_read(&adapter->clock));
243 struct timespec sys;
244 struct timespec delta;
245 getnstimeofday(&sys);
246
247 delta = timespec_sub(nic, sys);
248
249 sprintf(buffer,
33af6bcc
PO		 250 "HW %llu, NIC %ld.%09lus, SYS %ld.%09lus, NIC-SYS %lds + %09luns",
251 hw,
38c845c7
PO		 252 (long)nic.tv_sec, nic.tv_nsec,
253 (long)sys.tv_sec, sys.tv_nsec,
254 (long)delta.tv_sec, delta.tv_nsec);
255
256 return buffer;
257}
9d5c8243
AK		 258#endif
259
260/**
261 * igb_init_module - Driver Registration Routine
262 *
263 * igb_init_module is the first routine called when the driver is
264 * loaded. All it does is register with the PCI subsystem.
265 **/
266static int __init igb_init_module(void)
267{
268 int ret;
269 printk(KERN_INFO "%s - version %s\n",
270 igb_driver_string, igb_driver_version);
271
272 printk(KERN_INFO "%s\n", igb_copyright);
273
421e02f0 274#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 275 dca_register_notify(&dca_notifier);
276#endif
bbd98fe4 277 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 278 return ret;
279}
280
281module_init(igb_init_module);
282
283/**
284 * igb_exit_module - Driver Exit Cleanup Routine
285 *
286 * igb_exit_module is called just before the driver is removed
287 * from memory.
288 **/
289static void __exit igb_exit_module(void)
290{
421e02f0 291#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 292 dca_unregister_notify(&dca_notifier);
293#endif
9d5c8243
AK		 294 pci_unregister_driver(&igb_driver);
295}
296
297module_exit(igb_exit_module);
298
26bc19ec
AD		 299#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
300/**
301 * igb_cache_ring_register - Descriptor ring to register mapping
302 * @adapter: board private structure to initialize
303 *
304 * Once we know the feature-set enabled for the device, we'll cache
305 * the register offset the descriptor ring is assigned to.
306 **/
307static void igb_cache_ring_register(struct igb_adapter *adapter)
308{
ee1b9f06 309 int i = 0, j = 0;
047e0030 310 u32 rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 311
312 switch (adapter->hw.mac.type) {
313 case e1000_82576:
314 /* The queues are allocated for virtualization such that VF 0
315 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
316 * In order to avoid collision we start at the first free queue
317 * and continue consuming queues in the same sequence
318 */
ee1b9f06 319 if (adapter->vfs_allocated_count) {
a99955fc 320 for (; i < adapter->rss_queues; i++)
3025a446
AD		 321 adapter->rx_ring[i]->reg_idx = rbase_offset +
322 Q_IDX_82576(i);
a99955fc 323 for (; j < adapter->rss_queues; j++)
3025a446
AD		 324 adapter->tx_ring[j]->reg_idx = rbase_offset +
325 Q_IDX_82576(j);
ee1b9f06 326 }
26bc19ec 327 case e1000_82575:
55cac248 328 case e1000_82580:
26bc19ec 329 default:
ee1b9f06 330 for (; i < adapter->num_rx_queues; i++)
3025a446 331 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
ee1b9f06 332 for (; j < adapter->num_tx_queues; j++)
3025a446 333 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
26bc19ec
AD		 334 break;
335 }
336}
337
047e0030
AD		 338static void igb_free_queues(struct igb_adapter *adapter)
339{
3025a446 340 int i;
047e0030 341
3025a446
AD		 342 for (i = 0; i < adapter->num_tx_queues; i++) {
343 kfree(adapter->tx_ring[i]);
344 adapter->tx_ring[i] = NULL;
345 }
346 for (i = 0; i < adapter->num_rx_queues; i++) {
347 kfree(adapter->rx_ring[i]);
348 adapter->rx_ring[i] = NULL;
349 }
047e0030
AD		 350 adapter->num_rx_queues = 0;
351 adapter->num_tx_queues = 0;
352}
353
9d5c8243
AK		 354/**
355 * igb_alloc_queues - Allocate memory for all rings
356 * @adapter: board private structure to initialize
357 *
358 * We allocate one ring per queue at run-time since we don't know the
359 * number of queues at compile-time.
360 **/
361static int igb_alloc_queues(struct igb_adapter *adapter)
362{
3025a446 363 struct igb_ring *ring;
9d5c8243
AK		 364 int i;
365
661086df 366 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446
AD		 367 ring = kzalloc(sizeof(struct igb_ring), GFP_KERNEL);
368 if (!ring)
369 goto err;
68fd9910 370 ring->count = adapter->tx_ring_count;
661086df 371 ring->queue_index = i;
80785298 372 ring->pdev = adapter->pdev;
e694e964 373 ring->netdev = adapter->netdev;
85ad76b2
AD		 374 /* For 82575, context index must be unique per ring. */
375 if (adapter->hw.mac.type == e1000_82575)
376 ring->flags = IGB_RING_FLAG_TX_CTX_IDX;
3025a446 377 adapter->tx_ring[i] = ring;
661086df 378 }
85ad76b2 379
9d5c8243 380 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446
AD		 381 ring = kzalloc(sizeof(struct igb_ring), GFP_KERNEL);
382 if (!ring)
383 goto err;
68fd9910 384 ring->count = adapter->rx_ring_count;
844290e5 385 ring->queue_index = i;
80785298 386 ring->pdev = adapter->pdev;
e694e964 387 ring->netdev = adapter->netdev;
4c844851 388 ring->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
85ad76b2
AD		 389 ring->flags = IGB_RING_FLAG_RX_CSUM; /* enable rx checksum */
390 /* set flag indicating ring supports SCTP checksum offload */
391 if (adapter->hw.mac.type >= e1000_82576)
392 ring->flags |= IGB_RING_FLAG_RX_SCTP_CSUM;
3025a446 393 adapter->rx_ring[i] = ring;
9d5c8243 394 }
26bc19ec
AD		 395
396 igb_cache_ring_register(adapter);
9d5c8243 397
047e0030 398 return 0;
a88f10ec 399
047e0030
AD		 400err:
401 igb_free_queues(adapter);
d1a8c9e1 402
047e0030 403 return -ENOMEM;
a88f10ec
AD		 404}
405
9d5c8243 406#define IGB_N0_QUEUE -1
047e0030 407static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
9d5c8243
AK		 408{
409 u32 msixbm = 0;
047e0030 410 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 411 struct e1000_hw *hw = &adapter->hw;
2d064c06 412 u32 ivar, index;
047e0030
AD		 413 int rx_queue = IGB_N0_QUEUE;
414 int tx_queue = IGB_N0_QUEUE;
415
416 if (q_vector->rx_ring)
417 rx_queue = q_vector->rx_ring->reg_idx;
418 if (q_vector->tx_ring)
419 tx_queue = q_vector->tx_ring->reg_idx;
2d064c06
AD		 420
421 switch (hw->mac.type) {
422 case e1000_82575:
9d5c8243
AK		 423 /* The 82575 assigns vectors using a bitmask, which matches the
424 bitmask for the EICR/EIMS/EIMC registers. To assign one
425 or more queues to a vector, we write the appropriate bits
426 into the MSIXBM register for that vector. */
047e0030 427 if (rx_queue > IGB_N0_QUEUE)
9d5c8243 428 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
047e0030 429 if (tx_queue > IGB_N0_QUEUE)
9d5c8243 430 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
feeb2721
AD		 431 if (!adapter->msix_entries && msix_vector == 0)
432 msixbm |= E1000_EIMS_OTHER;
9d5c8243 433 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
047e0030 434 q_vector->eims_value = msixbm;
2d064c06
AD		 435 break;
436 case e1000_82576:
26bc19ec 437 /* 82576 uses a table-based method for assigning vectors.
2d064c06
AD		 438 Each queue has a single entry in the table to which we write
439 a vector number along with a "valid" bit. Sadly, the layout
440 of the table is somewhat counterintuitive. */
441 if (rx_queue > IGB_N0_QUEUE) {
047e0030 442 index = (rx_queue & 0x7);
2d064c06 443 ivar = array_rd32(E1000_IVAR0, index);
047e0030 444 if (rx_queue < 8) {
26bc19ec
AD		 445 /* vector goes into low byte of register */
446 ivar = ivar & 0xFFFFFF00;
447 ivar |= msix_vector | E1000_IVAR_VALID;
047e0030
AD		 448 } else {
449 /* vector goes into third byte of register */
450 ivar = ivar & 0xFF00FFFF;
451 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
2d064c06 452 }
2d064c06
AD		 453 array_wr32(E1000_IVAR0, index, ivar);
454 }
455 if (tx_queue > IGB_N0_QUEUE) {
047e0030 456 index = (tx_queue & 0x7);
2d064c06 457 ivar = array_rd32(E1000_IVAR0, index);
047e0030 458 if (tx_queue < 8) {
26bc19ec
AD		 459 /* vector goes into second byte of register */
460 ivar = ivar & 0xFFFF00FF;
461 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
047e0030
AD		 462 } else {
463 /* vector goes into high byte of register */
464 ivar = ivar & 0x00FFFFFF;
465 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
2d064c06 466 }
2d064c06
AD		 467 array_wr32(E1000_IVAR0, index, ivar);
468 }
047e0030 469 q_vector->eims_value = 1 << msix_vector;
2d064c06 470 break;
55cac248
AD		 471 case e1000_82580:
472 /* 82580 uses the same table-based approach as 82576 but has fewer
473 entries as a result we carry over for queues greater than 4. */
474 if (rx_queue > IGB_N0_QUEUE) {
475 index = (rx_queue >> 1);
476 ivar = array_rd32(E1000_IVAR0, index);
477 if (rx_queue & 0x1) {
478 /* vector goes into third byte of register */
479 ivar = ivar & 0xFF00FFFF;
480 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
481 } else {
482 /* vector goes into low byte of register */
483 ivar = ivar & 0xFFFFFF00;
484 ivar |= msix_vector | E1000_IVAR_VALID;
485 }
486 array_wr32(E1000_IVAR0, index, ivar);
487 }
488 if (tx_queue > IGB_N0_QUEUE) {
489 index = (tx_queue >> 1);
490 ivar = array_rd32(E1000_IVAR0, index);
491 if (tx_queue & 0x1) {
492 /* vector goes into high byte of register */
493 ivar = ivar & 0x00FFFFFF;
494 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
495 } else {
496 /* vector goes into second byte of register */
497 ivar = ivar & 0xFFFF00FF;
498 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
499 }
500 array_wr32(E1000_IVAR0, index, ivar);
501 }
502 q_vector->eims_value = 1 << msix_vector;
503 break;
2d064c06
AD		 504 default:
505 BUG();
506 break;
507 }
26b39276
AD		 508
509 /* add q_vector eims value to global eims_enable_mask */
510 adapter->eims_enable_mask |= q_vector->eims_value;
511
512 /* configure q_vector to set itr on first interrupt */
513 q_vector->set_itr = 1;
9d5c8243
AK		 514}
515
516/**
517 * igb_configure_msix - Configure MSI-X hardware
518 *
519 * igb_configure_msix sets up the hardware to properly
520 * generate MSI-X interrupts.
521 **/
522static void igb_configure_msix(struct igb_adapter *adapter)
523{
524 u32 tmp;
525 int i, vector = 0;
526 struct e1000_hw *hw = &adapter->hw;
527
528 adapter->eims_enable_mask = 0;
9d5c8243
AK		 529
530 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 531 switch (hw->mac.type) {
532 case e1000_82575:
9d5c8243
AK		 533 tmp = rd32(E1000_CTRL_EXT);
534 /* enable MSI-X PBA support*/
535 tmp |= E1000_CTRL_EXT_PBA_CLR;
536
537 /* Auto-Mask interrupts upon ICR read. */
538 tmp |= E1000_CTRL_EXT_EIAME;
539 tmp |= E1000_CTRL_EXT_IRCA;
540
541 wr32(E1000_CTRL_EXT, tmp);
047e0030
AD		 542
543 /* enable msix_other interrupt */
544 array_wr32(E1000_MSIXBM(0), vector++,
545 E1000_EIMS_OTHER);
844290e5 546 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 547
2d064c06
AD		 548 break;
549
550 case e1000_82576:
55cac248 551 case e1000_82580:
047e0030
AD		 552 /* Turn on MSI-X capability first, or our settings
553 * won't stick. And it will take days to debug. */
554 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
555 E1000_GPIE_PBA | E1000_GPIE_EIAME |
556 E1000_GPIE_NSICR);
557
558 /* enable msix_other interrupt */
559 adapter->eims_other = 1 << vector;
2d064c06 560 tmp = (vector++ | E1000_IVAR_VALID) << 8;
2d064c06 561
047e0030 562 wr32(E1000_IVAR_MISC, tmp);
2d064c06
AD		 563 break;
564 default:
565 /* do nothing, since nothing else supports MSI-X */
566 break;
567 } /* switch (hw->mac.type) */
047e0030
AD		 568
569 adapter->eims_enable_mask |= adapter->eims_other;
570
26b39276
AD		 571 for (i = 0; i < adapter->num_q_vectors; i++)
572 igb_assign_vector(adapter->q_vector[i], vector++);
047e0030 573
9d5c8243
AK		 574 wrfl();
575}
576
577/**
578 * igb_request_msix - Initialize MSI-X interrupts
579 *
580 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
581 * kernel.
582 **/
583static int igb_request_msix(struct igb_adapter *adapter)
584{
585 struct net_device *netdev = adapter->netdev;
047e0030 586 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 587 int i, err = 0, vector = 0;
588
047e0030 589 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 590 igb_msix_other, 0, netdev->name, adapter);
047e0030
AD		 591 if (err)
592 goto out;
593 vector++;
594
595 for (i = 0; i < adapter->num_q_vectors; i++) {
596 struct igb_q_vector *q_vector = adapter->q_vector[i];
597
598 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
599
600 if (q_vector->rx_ring && q_vector->tx_ring)
601 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
602 q_vector->rx_ring->queue_index);
603 else if (q_vector->tx_ring)
604 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
605 q_vector->tx_ring->queue_index);
606 else if (q_vector->rx_ring)
607 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
608 q_vector->rx_ring->queue_index);
9d5c8243 609 else
047e0030
AD		 610 sprintf(q_vector->name, "%s-unused", netdev->name);
611
9d5c8243 612 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 613 igb_msix_ring, 0, q_vector->name,
047e0030 614 q_vector);
9d5c8243
AK		 615 if (err)
616 goto out;
9d5c8243
AK		 617 vector++;
618 }
619
9d5c8243
AK		 620 igb_configure_msix(adapter);
621 return 0;
622out:
623 return err;
624}
625
626static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
627{
628 if (adapter->msix_entries) {
629 pci_disable_msix(adapter->pdev);
630 kfree(adapter->msix_entries);
631 adapter->msix_entries = NULL;
047e0030 632 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243 633 pci_disable_msi(adapter->pdev);
047e0030 634 }
9d5c8243
AK		 635}
636
047e0030
AD		 637/**
638 * igb_free_q_vectors - Free memory allocated for interrupt vectors
639 * @adapter: board private structure to initialize
640 *
641 * This function frees the memory allocated to the q_vectors. In addition if
642 * NAPI is enabled it will delete any references to the NAPI struct prior
643 * to freeing the q_vector.
644 **/
645static void igb_free_q_vectors(struct igb_adapter *adapter)
646{
647 int v_idx;
648
649 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
650 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
651 adapter->q_vector[v_idx] = NULL;
652 netif_napi_del(&q_vector->napi);
653 kfree(q_vector);
654 }
655 adapter->num_q_vectors = 0;
656}
657
658/**
659 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
660 *
661 * This function resets the device so that it has 0 rx queues, tx queues, and
662 * MSI-X interrupts allocated.
663 */
664static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
665{
666 igb_free_queues(adapter);
667 igb_free_q_vectors(adapter);
668 igb_reset_interrupt_capability(adapter);
669}
9d5c8243
AK		 670
671/**
672 * igb_set_interrupt_capability - set MSI or MSI-X if supported
673 *
674 * Attempt to configure interrupts using the best available
675 * capabilities of the hardware and kernel.
676 **/
677static void igb_set_interrupt_capability(struct igb_adapter *adapter)
678{
679 int err;
680 int numvecs, i;
681
83b7180d 682 /* Number of supported queues. */
a99955fc
AD		 683 adapter->num_rx_queues = adapter->rss_queues;
684 adapter->num_tx_queues = adapter->rss_queues;
83b7180d 685
047e0030
AD		 686 /* start with one vector for every rx queue */
687 numvecs = adapter->num_rx_queues;
688
689 /* if tx handler is seperate add 1 for every tx queue */
a99955fc
AD		 690 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
691 numvecs += adapter->num_tx_queues;
047e0030
AD		 692
693 /* store the number of vectors reserved for queues */
694 adapter->num_q_vectors = numvecs;
695
696 /* add 1 vector for link status interrupts */
697 numvecs++;
9d5c8243
AK		 698 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
699 GFP_KERNEL);
700 if (!adapter->msix_entries)
701 goto msi_only;
702
703 for (i = 0; i < numvecs; i++)
704 adapter->msix_entries[i].entry = i;
705
706 err = pci_enable_msix(adapter->pdev,
707 adapter->msix_entries,
708 numvecs);
709 if (err == 0)
34a20e89 710 goto out;
9d5c8243
AK		 711
712 igb_reset_interrupt_capability(adapter);
713
714 /* If we can't do MSI-X, try MSI */
715msi_only:
2a3abf6d
AD		 716#ifdef CONFIG_PCI_IOV
717 /* disable SR-IOV for non MSI-X configurations */
718 if (adapter->vf_data) {
719 struct e1000_hw *hw = &adapter->hw;
720 /* disable iov and allow time for transactions to clear */
721 pci_disable_sriov(adapter->pdev);
722 msleep(500);
723
724 kfree(adapter->vf_data);
725 adapter->vf_data = NULL;
726 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
727 msleep(100);
728 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
729 }
730#endif
4fc82adf 731 adapter->vfs_allocated_count = 0;
a99955fc 732 adapter->rss_queues = 1;
4fc82adf 733 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
9d5c8243 734 adapter->num_rx_queues = 1;
661086df 735 adapter->num_tx_queues = 1;
047e0030 736 adapter->num_q_vectors = 1;
9d5c8243 737 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 738 adapter->flags |= IGB_FLAG_HAS_MSI;
34a20e89 739out:
661086df 740 /* Notify the stack of the (possibly) reduced Tx Queue count. */
fd2ea0a7 741 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
9d5c8243
AK		 742 return;
743}
744
047e0030
AD		 745/**
746 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
747 * @adapter: board private structure to initialize
748 *
749 * We allocate one q_vector per queue interrupt. If allocation fails we
750 * return -ENOMEM.
751 **/
752static int igb_alloc_q_vectors(struct igb_adapter *adapter)
753{
754 struct igb_q_vector *q_vector;
755 struct e1000_hw *hw = &adapter->hw;
756 int v_idx;
757
758 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
759 q_vector = kzalloc(sizeof(struct igb_q_vector), GFP_KERNEL);
760 if (!q_vector)
761 goto err_out;
762 q_vector->adapter = adapter;
047e0030
AD		 763 q_vector->itr_register = hw->hw_addr + E1000_EITR(0);
764 q_vector->itr_val = IGB_START_ITR;
047e0030
AD		 765 netif_napi_add(adapter->netdev, &q_vector->napi, igb_poll, 64);
766 adapter->q_vector[v_idx] = q_vector;
767 }
768 return 0;
769
770err_out:
771 while (v_idx) {
772 v_idx--;
773 q_vector = adapter->q_vector[v_idx];
774 netif_napi_del(&q_vector->napi);
775 kfree(q_vector);
776 adapter->q_vector[v_idx] = NULL;
777 }
778 return -ENOMEM;
779}
780
781static void igb_map_rx_ring_to_vector(struct igb_adapter *adapter,
782 int ring_idx, int v_idx)
783{
3025a446 784 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
047e0030 785
3025a446 786 q_vector->rx_ring = adapter->rx_ring[ring_idx];
047e0030 787 q_vector->rx_ring->q_vector = q_vector;
4fc82adf
AD		 788 q_vector->itr_val = adapter->rx_itr_setting;
789 if (q_vector->itr_val && q_vector->itr_val <= 3)
790 q_vector->itr_val = IGB_START_ITR;
047e0030
AD		 791}
792
793static void igb_map_tx_ring_to_vector(struct igb_adapter *adapter,
794 int ring_idx, int v_idx)
795{
3025a446 796 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
047e0030 797
3025a446 798 q_vector->tx_ring = adapter->tx_ring[ring_idx];
047e0030 799 q_vector->tx_ring->q_vector = q_vector;
4fc82adf
AD		 800 q_vector->itr_val = adapter->tx_itr_setting;
801 if (q_vector->itr_val && q_vector->itr_val <= 3)
802 q_vector->itr_val = IGB_START_ITR;
047e0030
AD		 803}
804
805/**
806 * igb_map_ring_to_vector - maps allocated queues to vectors
807 *
808 * This function maps the recently allocated queues to vectors.
809 **/
810static int igb_map_ring_to_vector(struct igb_adapter *adapter)
811{
812 int i;
813 int v_idx = 0;
814
815 if ((adapter->num_q_vectors < adapter->num_rx_queues) ||
816 (adapter->num_q_vectors < adapter->num_tx_queues))
817 return -ENOMEM;
818
819 if (adapter->num_q_vectors >=
820 (adapter->num_rx_queues + adapter->num_tx_queues)) {
821 for (i = 0; i < adapter->num_rx_queues; i++)
822 igb_map_rx_ring_to_vector(adapter, i, v_idx++);
823 for (i = 0; i < adapter->num_tx_queues; i++)
824 igb_map_tx_ring_to_vector(adapter, i, v_idx++);
825 } else {
826 for (i = 0; i < adapter->num_rx_queues; i++) {
827 if (i < adapter->num_tx_queues)
828 igb_map_tx_ring_to_vector(adapter, i, v_idx);
829 igb_map_rx_ring_to_vector(adapter, i, v_idx++);
830 }
831 for (; i < adapter->num_tx_queues; i++)
832 igb_map_tx_ring_to_vector(adapter, i, v_idx++);
833 }
834 return 0;
835}
836
837/**
838 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
839 *
840 * This function initializes the interrupts and allocates all of the queues.
841 **/
842static int igb_init_interrupt_scheme(struct igb_adapter *adapter)
843{
844 struct pci_dev *pdev = adapter->pdev;
845 int err;
846
847 igb_set_interrupt_capability(adapter);
848
849 err = igb_alloc_q_vectors(adapter);
850 if (err) {
851 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
852 goto err_alloc_q_vectors;
853 }
854
855 err = igb_alloc_queues(adapter);
856 if (err) {
857 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
858 goto err_alloc_queues;
859 }
860
861 err = igb_map_ring_to_vector(adapter);
862 if (err) {
863 dev_err(&pdev->dev, "Invalid q_vector to ring mapping\n");
864 goto err_map_queues;
865 }
866
867
868 return 0;
869err_map_queues:
870 igb_free_queues(adapter);
871err_alloc_queues:
872 igb_free_q_vectors(adapter);
873err_alloc_q_vectors:
874 igb_reset_interrupt_capability(adapter);
875 return err;
876}
877
9d5c8243
AK		 878/**
879 * igb_request_irq - initialize interrupts
880 *
881 * Attempts to configure interrupts using the best available
882 * capabilities of the hardware and kernel.
883 **/
884static int igb_request_irq(struct igb_adapter *adapter)
885{
886 struct net_device *netdev = adapter->netdev;
047e0030 887 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 888 int err = 0;
889
890 if (adapter->msix_entries) {
891 err = igb_request_msix(adapter);
844290e5 892 if (!err)
9d5c8243 893 goto request_done;
9d5c8243 894 /* fall back to MSI */
047e0030 895 igb_clear_interrupt_scheme(adapter);
9d5c8243 896 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 897 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 898 igb_free_all_tx_resources(adapter);
899 igb_free_all_rx_resources(adapter);
047e0030 900 adapter->num_tx_queues = 1;
9d5c8243 901 adapter->num_rx_queues = 1;
047e0030
AD		 902 adapter->num_q_vectors = 1;
903 err = igb_alloc_q_vectors(adapter);
904 if (err) {
905 dev_err(&pdev->dev,
906 "Unable to allocate memory for vectors\n");
907 goto request_done;
908 }
909 err = igb_alloc_queues(adapter);
910 if (err) {
911 dev_err(&pdev->dev,
912 "Unable to allocate memory for queues\n");
913 igb_free_q_vectors(adapter);
914 goto request_done;
915 }
916 igb_setup_all_tx_resources(adapter);
917 igb_setup_all_rx_resources(adapter);
844290e5 918 } else {
feeb2721 919 igb_assign_vector(adapter->q_vector[0], 0);
9d5c8243 920 }
844290e5 921
7dfc16fa 922 if (adapter->flags & IGB_FLAG_HAS_MSI) {
a0607fd3 923 err = request_irq(adapter->pdev->irq, igb_intr_msi, 0,
047e0030 924 netdev->name, adapter);
9d5c8243
AK		 925 if (!err)
926 goto request_done;
047e0030 927
9d5c8243
AK		 928 /* fall back to legacy interrupts */
929 igb_reset_interrupt_capability(adapter);
7dfc16fa 930 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 931 }
932
a0607fd3 933 err = request_irq(adapter->pdev->irq, igb_intr, IRQF_SHARED,
047e0030 934 netdev->name, adapter);
9d5c8243 935
6cb5e577 936 if (err)
9d5c8243
AK		 937 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
938 err);
9d5c8243
AK		 939
940request_done:
941 return err;
942}
943
944static void igb_free_irq(struct igb_adapter *adapter)
945{
9d5c8243
AK		 946 if (adapter->msix_entries) {
947 int vector = 0, i;
948
047e0030 949 free_irq(adapter->msix_entries[vector++].vector, adapter);
9d5c8243 950
047e0030
AD		 951 for (i = 0; i < adapter->num_q_vectors; i++) {
952 struct igb_q_vector *q_vector = adapter->q_vector[i];
953 free_irq(adapter->msix_entries[vector++].vector,
954 q_vector);
955 }
956 } else {
957 free_irq(adapter->pdev->irq, adapter);
9d5c8243 958 }
9d5c8243
AK		 959}
960
961/**
962 * igb_irq_disable - Mask off interrupt generation on the NIC
963 * @adapter: board private structure
964 **/
965static void igb_irq_disable(struct igb_adapter *adapter)
966{
967 struct e1000_hw *hw = &adapter->hw;
968
25568a53
AD		 969 /*
970 * we need to be careful when disabling interrupts. The VFs are also
971 * mapped into these registers and so clearing the bits can cause
972 * issues on the VF drivers so we only need to clear what we set
973 */
9d5c8243 974 if (adapter->msix_entries) {
2dfd1212
AD		 975 u32 regval = rd32(E1000_EIAM);
976 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
977 wr32(E1000_EIMC, adapter->eims_enable_mask);
978 regval = rd32(E1000_EIAC);
979 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 980 }
844290e5
PW		 981
982 wr32(E1000_IAM, 0);
9d5c8243
AK		 983 wr32(E1000_IMC, ~0);
984 wrfl();
985 synchronize_irq(adapter->pdev->irq);
986}
987
988/**
989 * igb_irq_enable - Enable default interrupt generation settings
990 * @adapter: board private structure
991 **/
992static void igb_irq_enable(struct igb_adapter *adapter)
993{
994 struct e1000_hw *hw = &adapter->hw;
995
996 if (adapter->msix_entries) {
25568a53 997 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC;
2dfd1212
AD		 998 u32 regval = rd32(E1000_EIAC);
999 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1000 regval = rd32(E1000_EIAM);
1001 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 1002 wr32(E1000_EIMS, adapter->eims_enable_mask);
25568a53 1003 if (adapter->vfs_allocated_count) {
4ae196df 1004 wr32(E1000_MBVFIMR, 0xFF);
25568a53
AD		 1005 ims |= E1000_IMS_VMMB;
1006 }
55cac248
AD		 1007 if (adapter->hw.mac.type == e1000_82580)
1008 ims |= E1000_IMS_DRSTA;
1009
25568a53 1010 wr32(E1000_IMS, ims);
844290e5 1011 } else {
55cac248
AD		 1012 wr32(E1000_IMS, IMS_ENABLE_MASK |
1013 E1000_IMS_DRSTA);
1014 wr32(E1000_IAM, IMS_ENABLE_MASK |
1015 E1000_IMS_DRSTA);
844290e5 1016 }
9d5c8243
AK		 1017}
1018
1019static void igb_update_mng_vlan(struct igb_adapter *adapter)
1020{
51466239 1021 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1022 u16 vid = adapter->hw.mng_cookie.vlan_id;
1023 u16 old_vid = adapter->mng_vlan_id;
51466239
AD		 1024
1025 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1026 /* add VID to filter table */
1027 igb_vfta_set(hw, vid, true);
1028 adapter->mng_vlan_id = vid;
1029 } else {
1030 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1031 }
1032
1033 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1034 (vid != old_vid) &&
1035 !vlan_group_get_device(adapter->vlgrp, old_vid)) {
1036 /* remove VID from filter table */
1037 igb_vfta_set(hw, old_vid, false);
9d5c8243
AK		 1038 }
1039}
1040
1041/**
1042 * igb_release_hw_control - release control of the h/w to f/w
1043 * @adapter: address of board private structure
1044 *
1045 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1046 * For ASF and Pass Through versions of f/w this means that the
1047 * driver is no longer loaded.
1048 *
1049 **/
1050static void igb_release_hw_control(struct igb_adapter *adapter)
1051{
1052 struct e1000_hw *hw = &adapter->hw;
1053 u32 ctrl_ext;
1054
1055 /* Let firmware take over control of h/w */
1056 ctrl_ext = rd32(E1000_CTRL_EXT);
1057 wr32(E1000_CTRL_EXT,
1058 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1059}
1060
9d5c8243
AK		 1061/**
1062 * igb_get_hw_control - get control of the h/w from f/w
1063 * @adapter: address of board private structure
1064 *
1065 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1066 * For ASF and Pass Through versions of f/w this means that
1067 * the driver is loaded.
1068 *
1069 **/
1070static void igb_get_hw_control(struct igb_adapter *adapter)
1071{
1072 struct e1000_hw *hw = &adapter->hw;
1073 u32 ctrl_ext;
1074
1075 /* Let firmware know the driver has taken over */
1076 ctrl_ext = rd32(E1000_CTRL_EXT);
1077 wr32(E1000_CTRL_EXT,
1078 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1079}
1080
9d5c8243
AK		 1081/**
1082 * igb_configure - configure the hardware for RX and TX
1083 * @adapter: private board structure
1084 **/
1085static void igb_configure(struct igb_adapter *adapter)
1086{
1087 struct net_device *netdev = adapter->netdev;
1088 int i;
1089
1090 igb_get_hw_control(adapter);
ff41f8dc 1091 igb_set_rx_mode(netdev);
9d5c8243
AK		 1092
1093 igb_restore_vlan(adapter);
9d5c8243 1094
85b430b4 1095 igb_setup_tctl(adapter);
06cf2666 1096 igb_setup_mrqc(adapter);
9d5c8243 1097 igb_setup_rctl(adapter);
85b430b4
AD		 1098
1099 igb_configure_tx(adapter);
9d5c8243 1100 igb_configure_rx(adapter);
662d7205
AD		 1101
1102 igb_rx_fifo_flush_82575(&adapter->hw);
1103
c493ea45 1104 /* call igb_desc_unused which always leaves
9d5c8243
AK		 1105 * at least 1 descriptor unused to make sure
1106 * next_to_use != next_to_clean */
1107 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 1108 struct igb_ring *ring = adapter->rx_ring[i];
c493ea45 1109 igb_alloc_rx_buffers_adv(ring, igb_desc_unused(ring));
9d5c8243
AK		 1110 }
1111
1112
1113 adapter->tx_queue_len = netdev->tx_queue_len;
1114}
1115
88a268c1
NN		 1116/**
1117 * igb_power_up_link - Power up the phy/serdes link
1118 * @adapter: address of board private structure
1119 **/
1120void igb_power_up_link(struct igb_adapter *adapter)
1121{
1122 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1123 igb_power_up_phy_copper(&adapter->hw);
1124 else
1125 igb_power_up_serdes_link_82575(&adapter->hw);
1126}
1127
1128/**
1129 * igb_power_down_link - Power down the phy/serdes link
1130 * @adapter: address of board private structure
1131 */
1132static void igb_power_down_link(struct igb_adapter *adapter)
1133{
1134 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1135 igb_power_down_phy_copper_82575(&adapter->hw);
1136 else
1137 igb_shutdown_serdes_link_82575(&adapter->hw);
1138}
9d5c8243
AK		 1139
1140/**
1141 * igb_up - Open the interface and prepare it to handle traffic
1142 * @adapter: board private structure
1143 **/
9d5c8243
AK		 1144int igb_up(struct igb_adapter *adapter)
1145{
1146 struct e1000_hw *hw = &adapter->hw;
1147 int i;
1148
1149 /* hardware has been reset, we need to reload some things */
1150 igb_configure(adapter);
1151
1152 clear_bit(__IGB_DOWN, &adapter->state);
1153
047e0030
AD		 1154 for (i = 0; i < adapter->num_q_vectors; i++) {
1155 struct igb_q_vector *q_vector = adapter->q_vector[i];
1156 napi_enable(&q_vector->napi);
1157 }
844290e5 1158 if (adapter->msix_entries)
9d5c8243 1159 igb_configure_msix(adapter);
feeb2721
AD		 1160 else
1161 igb_assign_vector(adapter->q_vector[0], 0);
9d5c8243
AK		 1162
1163 /* Clear any pending interrupts. */
1164 rd32(E1000_ICR);
1165 igb_irq_enable(adapter);
1166
d4960307
AD		 1167 /* notify VFs that reset has been completed */
1168 if (adapter->vfs_allocated_count) {
1169 u32 reg_data = rd32(E1000_CTRL_EXT);
1170 reg_data |= E1000_CTRL_EXT_PFRSTD;
1171 wr32(E1000_CTRL_EXT, reg_data);
1172 }
1173
4cb9be7a
JB		 1174 netif_tx_start_all_queues(adapter->netdev);
1175
25568a53
AD		 1176 /* start the watchdog. */
1177 hw->mac.get_link_status = 1;
1178 schedule_work(&adapter->watchdog_task);
1179
9d5c8243
AK		 1180 return 0;
1181}
1182
1183void igb_down(struct igb_adapter *adapter)
1184{
9d5c8243 1185 struct net_device *netdev = adapter->netdev;
330a6d6a 1186 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1187 u32 tctl, rctl;
1188 int i;
1189
1190 /* signal that we're down so the interrupt handler does not
1191 * reschedule our watchdog timer */
1192 set_bit(__IGB_DOWN, &adapter->state);
1193
1194 /* disable receives in the hardware */
1195 rctl = rd32(E1000_RCTL);
1196 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1197 /* flush and sleep below */
1198
fd2ea0a7 1199 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1200
1201 /* disable transmits in the hardware */
1202 tctl = rd32(E1000_TCTL);
1203 tctl &= ~E1000_TCTL_EN;
1204 wr32(E1000_TCTL, tctl);
1205 /* flush both disables and wait for them to finish */
1206 wrfl();
1207 msleep(10);
1208
047e0030
AD		 1209 for (i = 0; i < adapter->num_q_vectors; i++) {
1210 struct igb_q_vector *q_vector = adapter->q_vector[i];
1211 napi_disable(&q_vector->napi);
1212 }
9d5c8243 1213
9d5c8243
AK		 1214 igb_irq_disable(adapter);
1215
1216 del_timer_sync(&adapter->watchdog_timer);
1217 del_timer_sync(&adapter->phy_info_timer);
1218
1219 netdev->tx_queue_len = adapter->tx_queue_len;
1220 netif_carrier_off(netdev);
04fe6358
AD		 1221
1222 /* record the stats before reset*/
1223 igb_update_stats(adapter);
1224
9d5c8243
AK		 1225 adapter->link_speed = 0;
1226 adapter->link_duplex = 0;
1227
3023682e
JK		 1228 if (!pci_channel_offline(adapter->pdev))
1229 igb_reset(adapter);
9d5c8243
AK		 1230 igb_clean_all_tx_rings(adapter);
1231 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1232#ifdef CONFIG_IGB_DCA
1233
1234 /* since we reset the hardware DCA settings were cleared */
1235 igb_setup_dca(adapter);
1236#endif
9d5c8243
AK		 1237}
1238
1239void igb_reinit_locked(struct igb_adapter *adapter)
1240{
1241 WARN_ON(in_interrupt());
1242 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1243 msleep(1);
1244 igb_down(adapter);
1245 igb_up(adapter);
1246 clear_bit(__IGB_RESETTING, &adapter->state);
1247}
1248
1249void igb_reset(struct igb_adapter *adapter)
1250{
090b1795 1251 struct pci_dev *pdev = adapter->pdev;
9d5c8243 1252 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1253 struct e1000_mac_info *mac = &hw->mac;
1254 struct e1000_fc_info *fc = &hw->fc;
9d5c8243
AK		 1255 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
1256 u16 hwm;
1257
1258 /* Repartition Pba for greater than 9k mtu
1259 * To take effect CTRL.RST is required.
1260 */
fa4dfae0 1261 switch (mac->type) {
55cac248
AD		 1262 case e1000_82580:
1263 pba = rd32(E1000_RXPBS);
1264 pba = igb_rxpbs_adjust_82580(pba);
1265 break;
fa4dfae0 1266 case e1000_82576:
d249be54
AD		 1267 pba = rd32(E1000_RXPBS);
1268 pba &= E1000_RXPBS_SIZE_MASK_82576;
fa4dfae0
AD		 1269 break;
1270 case e1000_82575:
1271 default:
1272 pba = E1000_PBA_34K;
1273 break;
2d064c06 1274 }
9d5c8243 1275
2d064c06
AD		 1276 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1277 (mac->type < e1000_82576)) {
9d5c8243
AK		 1278 /* adjust PBA for jumbo frames */
1279 wr32(E1000_PBA, pba);
1280
1281 /* To maintain wire speed transmits, the Tx FIFO should be
1282 * large enough to accommodate two full transmit packets,
1283 * rounded up to the next 1KB and expressed in KB. Likewise,
1284 * the Rx FIFO should be large enough to accommodate at least
1285 * one full receive packet and is similarly rounded up and
1286 * expressed in KB. */
1287 pba = rd32(E1000_PBA);
1288 /* upper 16 bits has Tx packet buffer allocation size in KB */
1289 tx_space = pba >> 16;
1290 /* lower 16 bits has Rx packet buffer allocation size in KB */
1291 pba &= 0xffff;
1292 /* the tx fifo also stores 16 bytes of information about the tx
1293 * but don't include ethernet FCS because hardware appends it */
1294 min_tx_space = (adapter->max_frame_size +
85e8d004 1295 sizeof(union e1000_adv_tx_desc) -
9d5c8243
AK		 1296 ETH_FCS_LEN) * 2;
1297 min_tx_space = ALIGN(min_tx_space, 1024);
1298 min_tx_space >>= 10;
1299 /* software strips receive CRC, so leave room for it */
1300 min_rx_space = adapter->max_frame_size;
1301 min_rx_space = ALIGN(min_rx_space, 1024);
1302 min_rx_space >>= 10;
1303
1304 /* If current Tx allocation is less than the min Tx FIFO size,
1305 * and the min Tx FIFO size is less than the current Rx FIFO
1306 * allocation, take space away from current Rx allocation */
1307 if (tx_space < min_tx_space &&
1308 ((min_tx_space - tx_space) < pba)) {
1309 pba = pba - (min_tx_space - tx_space);
1310
1311 /* if short on rx space, rx wins and must trump tx
1312 * adjustment */
1313 if (pba < min_rx_space)
1314 pba = min_rx_space;
1315 }
2d064c06 1316 wr32(E1000_PBA, pba);
9d5c8243 1317 }
9d5c8243
AK		 1318
1319 /* flow control settings */
1320 /* The high water mark must be low enough to fit one full frame
1321 * (or the size used for early receive) above it in the Rx FIFO.
1322 * Set it to the lower of:
1323 * - 90% of the Rx FIFO size, or
1324 * - the full Rx FIFO size minus one full frame */
1325 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1326 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1327
d405ea3e
AD		 1328 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1329 fc->low_water = fc->high_water - 16;
9d5c8243
AK		 1330 fc->pause_time = 0xFFFF;
1331 fc->send_xon = 1;
0cce119a 1332 fc->current_mode = fc->requested_mode;
9d5c8243 1333
4ae196df
AD		 1334 /* disable receive for all VFs and wait one second */
1335 if (adapter->vfs_allocated_count) {
1336 int i;
1337 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
f2ca0dbe 1338 adapter->vf_data[i].flags = 0;
4ae196df
AD		 1339
1340 /* ping all the active vfs to let them know we are going down */
f2ca0dbe 1341 igb_ping_all_vfs(adapter);
4ae196df
AD		 1342
1343 /* disable transmits and receives */
1344 wr32(E1000_VFRE, 0);
1345 wr32(E1000_VFTE, 0);
1346 }
1347
9d5c8243 1348 /* Allow time for pending master requests to run */
330a6d6a 1349 hw->mac.ops.reset_hw(hw);
9d5c8243
AK		 1350 wr32(E1000_WUC, 0);
1351
330a6d6a 1352 if (hw->mac.ops.init_hw(hw))
090b1795 1353 dev_err(&pdev->dev, "Hardware Error\n");
9d5c8243 1354
55cac248
AD		 1355 if (hw->mac.type == e1000_82580) {
1356 u32 reg = rd32(E1000_PCIEMISC);
1357 wr32(E1000_PCIEMISC,
1358 reg & ~E1000_PCIEMISC_LX_DECISION);
1359 }
88a268c1
NN		 1360 if (!netif_running(adapter->netdev))
1361 igb_power_down_link(adapter);
1362
9d5c8243
AK		 1363 igb_update_mng_vlan(adapter);
1364
1365 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1366 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1367
330a6d6a 1368 igb_get_phy_info(hw);
9d5c8243
AK		 1369}
1370
2e5c6922 1371static const struct net_device_ops igb_netdev_ops = {
559e9c49 1372 .ndo_open = igb_open,
2e5c6922 1373 .ndo_stop = igb_close,
00829823 1374 .ndo_start_xmit = igb_xmit_frame_adv,
2e5c6922 1375 .ndo_get_stats = igb_get_stats,
ff41f8dc
AD		 1376 .ndo_set_rx_mode = igb_set_rx_mode,
1377 .ndo_set_multicast_list = igb_set_rx_mode,
2e5c6922
SH		 1378 .ndo_set_mac_address = igb_set_mac,
1379 .ndo_change_mtu = igb_change_mtu,
1380 .ndo_do_ioctl = igb_ioctl,
1381 .ndo_tx_timeout = igb_tx_timeout,
1382 .ndo_validate_addr = eth_validate_addr,
1383 .ndo_vlan_rx_register = igb_vlan_rx_register,
1384 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1385 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
8151d294
WM		 1386 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
1387 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
1388 .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw,
1389 .ndo_get_vf_config = igb_ndo_get_vf_config,
2e5c6922
SH		 1390#ifdef CONFIG_NET_POLL_CONTROLLER
1391 .ndo_poll_controller = igb_netpoll,
1392#endif
1393};
1394
9d5c8243
AK		 1395/**
1396 * igb_probe - Device Initialization Routine
1397 * @pdev: PCI device information struct
1398 * @ent: entry in igb_pci_tbl
1399 *
1400 * Returns 0 on success, negative on failure
1401 *
1402 * igb_probe initializes an adapter identified by a pci_dev structure.
1403 * The OS initialization, configuring of the adapter private structure,
1404 * and a hardware reset occur.
1405 **/
1406static int __devinit igb_probe(struct pci_dev *pdev,
1407 const struct pci_device_id *ent)
1408{
1409 struct net_device *netdev;
1410 struct igb_adapter *adapter;
1411 struct e1000_hw *hw;
4337e993
AD		 1412 u16 eeprom_data = 0;
1413 static int global_quad_port_a; /* global quad port a indication */
9d5c8243
AK		 1414 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1415 unsigned long mmio_start, mmio_len;
2d6a5e95 1416 int err, pci_using_dac;
9d5c8243
AK		 1417 u16 eeprom_apme_mask = IGB_EEPROM_APME;
1418 u32 part_num;
1419
aed5dec3 1420 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 1421 if (err)
1422 return err;
1423
1424 pci_using_dac = 0;
6a35528a 1425 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
9d5c8243 1426 if (!err) {
6a35528a 1427 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
9d5c8243
AK		 1428 if (!err)
1429 pci_using_dac = 1;
1430 } else {
284901a9 1431 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
9d5c8243 1432 if (err) {
284901a9 1433 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
9d5c8243
AK		 1434 if (err) {
1435 dev_err(&pdev->dev, "No usable DMA "
1436 "configuration, aborting\n");
1437 goto err_dma;
1438 }
1439 }
1440 }
1441
aed5dec3
AD		 1442 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1443 IORESOURCE_MEM),
1444 igb_driver_name);
9d5c8243
AK		 1445 if (err)
1446 goto err_pci_reg;
1447
19d5afd4 1448 pci_enable_pcie_error_reporting(pdev);
40a914fa 1449
9d5c8243 1450 pci_set_master(pdev);
c682fc23 1451 pci_save_state(pdev);
9d5c8243
AK		 1452
1453 err = -ENOMEM;
1bfaf07b
AD		 1454 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1455 IGB_ABS_MAX_TX_QUEUES);
9d5c8243
AK		 1456 if (!netdev)
1457 goto err_alloc_etherdev;
1458
1459 SET_NETDEV_DEV(netdev, &pdev->dev);
1460
1461 pci_set_drvdata(pdev, netdev);
1462 adapter = netdev_priv(netdev);
1463 adapter->netdev = netdev;
1464 adapter->pdev = pdev;
1465 hw = &adapter->hw;
1466 hw->back = adapter;
1467 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
1468
1469 mmio_start = pci_resource_start(pdev, 0);
1470 mmio_len = pci_resource_len(pdev, 0);
1471
1472 err = -EIO;
28b0759c
AD		 1473 hw->hw_addr = ioremap(mmio_start, mmio_len);
1474 if (!hw->hw_addr)
9d5c8243
AK		 1475 goto err_ioremap;
1476
2e5c6922 1477 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 1478 igb_set_ethtool_ops(netdev);
9d5c8243 1479 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 1480
1481 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1482
1483 netdev->mem_start = mmio_start;
1484 netdev->mem_end = mmio_start + mmio_len;
1485
9d5c8243
AK		 1486 /* PCI config space info */
1487 hw->vendor_id = pdev->vendor;
1488 hw->device_id = pdev->device;
1489 hw->revision_id = pdev->revision;
1490 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1491 hw->subsystem_device_id = pdev->subsystem_device;
1492
9d5c8243
AK		 1493 /* Copy the default MAC, PHY and NVM function pointers */
1494 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1495 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1496 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1497 /* Initialize skew-specific constants */
1498 err = ei->get_invariants(hw);
1499 if (err)
450c87c8 1500 goto err_sw_init;
9d5c8243 1501
450c87c8 1502 /* setup the private structure */
9d5c8243
AK		 1503 err = igb_sw_init(adapter);
1504 if (err)
1505 goto err_sw_init;
1506
1507 igb_get_bus_info_pcie(hw);
1508
1509 hw->phy.autoneg_wait_to_complete = false;
9d5c8243
AK		 1510
1511 /* Copper options */
1512 if (hw->phy.media_type == e1000_media_type_copper) {
1513 hw->phy.mdix = AUTO_ALL_MODES;
1514 hw->phy.disable_polarity_correction = false;
1515 hw->phy.ms_type = e1000_ms_hw_default;
1516 }
1517
1518 if (igb_check_reset_block(hw))
1519 dev_info(&pdev->dev,
1520 "PHY reset is blocked due to SOL/IDER session.\n");
1521
1522 netdev->features = NETIF_F_SG |
7d8eb29e 1523 NETIF_F_IP_CSUM |
9d5c8243
AK		 1524 NETIF_F_HW_VLAN_TX |
1525 NETIF_F_HW_VLAN_RX |
1526 NETIF_F_HW_VLAN_FILTER;
1527
7d8eb29e 1528 netdev->features |= NETIF_F_IPV6_CSUM;
9d5c8243 1529 netdev->features |= NETIF_F_TSO;
9d5c8243 1530 netdev->features |= NETIF_F_TSO6;
5c0999b7 1531 netdev->features |= NETIF_F_GRO;
d3352520 1532
48f29ffc
JK		 1533 netdev->vlan_features |= NETIF_F_TSO;
1534 netdev->vlan_features |= NETIF_F_TSO6;
7d8eb29e 1535 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 1536 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
48f29ffc
JK		 1537 netdev->vlan_features |= NETIF_F_SG;
1538
9d5c8243
AK		 1539 if (pci_using_dac)
1540 netdev->features |= NETIF_F_HIGHDMA;
1541
5b043fb0 1542 if (hw->mac.type >= e1000_82576)
b9473560
JB		 1543 netdev->features |= NETIF_F_SCTP_CSUM;
1544
330a6d6a 1545 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
9d5c8243
AK		 1546
1547 /* before reading the NVM, reset the controller to put the device in a
1548 * known good starting state */
1549 hw->mac.ops.reset_hw(hw);
1550
1551 /* make sure the NVM is good */
1552 if (igb_validate_nvm_checksum(hw) < 0) {
1553 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1554 err = -EIO;
1555 goto err_eeprom;
1556 }
1557
1558 /* copy the MAC address out of the NVM */
1559 if (hw->mac.ops.read_mac_addr(hw))
1560 dev_err(&pdev->dev, "NVM Read Error\n");
1561
1562 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1563 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1564
1565 if (!is_valid_ether_addr(netdev->perm_addr)) {
1566 dev_err(&pdev->dev, "Invalid MAC Address\n");
1567 err = -EIO;
1568 goto err_eeprom;
1569 }
1570
0e340485
AD		 1571 setup_timer(&adapter->watchdog_timer, &igb_watchdog,
1572 (unsigned long) adapter);
1573 setup_timer(&adapter->phy_info_timer, &igb_update_phy_info,
1574 (unsigned long) adapter);
9d5c8243
AK		 1575
1576 INIT_WORK(&adapter->reset_task, igb_reset_task);
1577 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1578
450c87c8 1579 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 1580 adapter->fc_autoneg = true;
1581 hw->mac.autoneg = true;
1582 hw->phy.autoneg_advertised = 0x2f;
1583
0cce119a
AD		 1584 hw->fc.requested_mode = e1000_fc_default;
1585 hw->fc.current_mode = e1000_fc_default;
9d5c8243 1586
9d5c8243
AK		 1587 igb_validate_mdi_setting(hw);
1588
9d5c8243
AK		 1589 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1590 * enable the ACPI Magic Packet filter
1591 */
1592
a2cf8b6c 1593 if (hw->bus.func == 0)
312c75ae 1594 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
55cac248
AD		 1595 else if (hw->mac.type == e1000_82580)
1596 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
1597 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
1598 &eeprom_data);
a2cf8b6c
AD		 1599 else if (hw->bus.func == 1)
1600 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243
AK		 1601
1602 if (eeprom_data & eeprom_apme_mask)
1603 adapter->eeprom_wol |= E1000_WUFC_MAG;
1604
1605 /* now that we have the eeprom settings, apply the special cases where
1606 * the eeprom may be wrong or the board simply won't support wake on
1607 * lan on a particular port */
1608 switch (pdev->device) {
1609 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1610 adapter->eeprom_wol = 0;
1611 break;
1612 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 1613 case E1000_DEV_ID_82576_FIBER:
1614 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 1615 /* Wake events only supported on port A for dual fiber
1616 * regardless of eeprom setting */
1617 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1618 adapter->eeprom_wol = 0;
1619 break;
c8ea5ea9
AD		 1620 case E1000_DEV_ID_82576_QUAD_COPPER:
1621 /* if quad port adapter, disable WoL on all but port A */
1622 if (global_quad_port_a != 0)
1623 adapter->eeprom_wol = 0;
1624 else
1625 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
1626 /* Reset for multiple quad port adapters */
1627 if (++global_quad_port_a == 4)
1628 global_quad_port_a = 0;
1629 break;
9d5c8243
AK		 1630 }
1631
1632 /* initialize the wol settings based on the eeprom settings */
1633 adapter->wol = adapter->eeprom_wol;
e1b86d84 1634 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
9d5c8243
AK		 1635
1636 /* reset the hardware with the new settings */
1637 igb_reset(adapter);
1638
1639 /* let the f/w know that the h/w is now under the control of the
1640 * driver. */
1641 igb_get_hw_control(adapter);
1642
9d5c8243
AK		 1643 strcpy(netdev->name, "eth%d");
1644 err = register_netdev(netdev);
1645 if (err)
1646 goto err_register;
1647
b168dfc5
JB		 1648 /* carrier off reporting is important to ethtool even BEFORE open */
1649 netif_carrier_off(netdev);
1650
421e02f0 1651#ifdef CONFIG_IGB_DCA
bbd98fe4 1652 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 1653 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 1654 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 1655 igb_setup_dca(adapter);
1656 }
fe4506b6 1657
38c845c7 1658#endif
9d5c8243
AK		 1659 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1660 /* print bus type/speed/width info */
7c510e4b 1661 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
9d5c8243 1662 netdev->name,
559e9c49
AD		 1663 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
1664 "unknown"),
59c3de89
AD		 1665 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
1666 (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :
1667 (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" :
1668 "unknown"),
7c510e4b 1669 netdev->dev_addr);
9d5c8243
AK		 1670
1671 igb_read_part_num(hw, &part_num);
1672 dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1673 (part_num >> 8), (part_num & 0xff));
1674
1675 dev_info(&pdev->dev,
1676 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1677 adapter->msix_entries ? "MSI-X" :
7dfc16fa 1678 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243
AK		 1679 adapter->num_rx_queues, adapter->num_tx_queues);
1680
9d5c8243
AK		 1681 return 0;
1682
1683err_register:
1684 igb_release_hw_control(adapter);
1685err_eeprom:
1686 if (!igb_check_reset_block(hw))
f5f4cf08 1687 igb_reset_phy(hw);
9d5c8243
AK		 1688
1689 if (hw->flash_address)
1690 iounmap(hw->flash_address);
9d5c8243 1691err_sw_init:
047e0030 1692 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 1693 iounmap(hw->hw_addr);
1694err_ioremap:
1695 free_netdev(netdev);
1696err_alloc_etherdev:
559e9c49
AD		 1697 pci_release_selected_regions(pdev,
1698 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243
AK		 1699err_pci_reg:
1700err_dma:
1701 pci_disable_device(pdev);
1702 return err;
1703}
1704
1705/**
1706 * igb_remove - Device Removal Routine
1707 * @pdev: PCI device information struct
1708 *
1709 * igb_remove is called by the PCI subsystem to alert the driver
1710 * that it should release a PCI device. The could be caused by a
1711 * Hot-Plug event, or because the driver is going to be removed from
1712 * memory.
1713 **/
1714static void __devexit igb_remove(struct pci_dev *pdev)
1715{
1716 struct net_device *netdev = pci_get_drvdata(pdev);
1717 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 1718 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1719
1720 /* flush_scheduled work may reschedule our watchdog task, so
1721 * explicitly disable watchdog tasks from being rescheduled */
1722 set_bit(__IGB_DOWN, &adapter->state);
1723 del_timer_sync(&adapter->watchdog_timer);
1724 del_timer_sync(&adapter->phy_info_timer);
1725
1726 flush_scheduled_work();
1727
421e02f0 1728#ifdef CONFIG_IGB_DCA
7dfc16fa 1729 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 1730 dev_info(&pdev->dev, "DCA disabled\n");
1731 dca_remove_requester(&pdev->dev);
7dfc16fa 1732 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 1733 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 1734 }
1735#endif
1736
9d5c8243
AK		 1737 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1738 * would have already happened in close and is redundant. */
1739 igb_release_hw_control(adapter);
1740
1741 unregister_netdev(netdev);
1742
047e0030 1743 igb_clear_interrupt_scheme(adapter);
9d5c8243 1744
37680117
AD		 1745#ifdef CONFIG_PCI_IOV
1746 /* reclaim resources allocated to VFs */
1747 if (adapter->vf_data) {
1748 /* disable iov and allow time for transactions to clear */
1749 pci_disable_sriov(pdev);
1750 msleep(500);
1751
1752 kfree(adapter->vf_data);
1753 adapter->vf_data = NULL;
1754 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1755 msleep(100);
1756 dev_info(&pdev->dev, "IOV Disabled\n");
1757 }
1758#endif
559e9c49 1759
28b0759c
AD		 1760 iounmap(hw->hw_addr);
1761 if (hw->flash_address)
1762 iounmap(hw->flash_address);
559e9c49
AD		 1763 pci_release_selected_regions(pdev,
1764 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243
AK		 1765
1766 free_netdev(netdev);
1767
19d5afd4 1768 pci_disable_pcie_error_reporting(pdev);
40a914fa 1769
9d5c8243
AK		 1770 pci_disable_device(pdev);
1771}
1772
a6b623e0
AD		 1773/**
1774 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
1775 * @adapter: board private structure to initialize
1776 *
1777 * This function initializes the vf specific data storage and then attempts to
1778 * allocate the VFs. The reason for ordering it this way is because it is much
1779 * mor expensive time wise to disable SR-IOV than it is to allocate and free
1780 * the memory for the VFs.
1781 **/
1782static void __devinit igb_probe_vfs(struct igb_adapter * adapter)
1783{
1784#ifdef CONFIG_PCI_IOV
1785 struct pci_dev *pdev = adapter->pdev;
1786
1787 if (adapter->vfs_allocated_count > 7)
1788 adapter->vfs_allocated_count = 7;
1789
1790 if (adapter->vfs_allocated_count) {
1791 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
1792 sizeof(struct vf_data_storage),
1793 GFP_KERNEL);
1794 /* if allocation failed then we do not support SR-IOV */
1795 if (!adapter->vf_data) {
1796 adapter->vfs_allocated_count = 0;
1797 dev_err(&pdev->dev, "Unable to allocate memory for VF "
1798 "Data Storage\n");
1799 }
1800 }
1801
1802 if (pci_enable_sriov(pdev, adapter->vfs_allocated_count)) {
1803 kfree(adapter->vf_data);
1804 adapter->vf_data = NULL;
1805#endif /* CONFIG_PCI_IOV */
1806 adapter->vfs_allocated_count = 0;
1807#ifdef CONFIG_PCI_IOV
1808 } else {
1809 unsigned char mac_addr[ETH_ALEN];
1810 int i;
1811 dev_info(&pdev->dev, "%d vfs allocated\n",
1812 adapter->vfs_allocated_count);
1813 for (i = 0; i < adapter->vfs_allocated_count; i++) {
1814 random_ether_addr(mac_addr);
1815 igb_set_vf_mac(adapter, i, mac_addr);
1816 }
1817 }
1818#endif /* CONFIG_PCI_IOV */
1819}
1820
115f459a
AD		 1821
1822/**
1823 * igb_init_hw_timer - Initialize hardware timer used with IEEE 1588 timestamp
1824 * @adapter: board private structure to initialize
1825 *
1826 * igb_init_hw_timer initializes the function pointer and values for the hw
1827 * timer found in hardware.
1828 **/
1829static void igb_init_hw_timer(struct igb_adapter *adapter)
1830{
1831 struct e1000_hw *hw = &adapter->hw;
1832
1833 switch (hw->mac.type) {
55cac248
AD		 1834 case e1000_82580:
1835 memset(&adapter->cycles, 0, sizeof(adapter->cycles));
1836 adapter->cycles.read = igb_read_clock;
1837 adapter->cycles.mask = CLOCKSOURCE_MASK(64);
1838 adapter->cycles.mult = 1;
1839 /*
1840 * The 82580 timesync updates the system timer every 8ns by 8ns
1841 * and the value cannot be shifted. Instead we need to shift
1842 * the registers to generate a 64bit timer value. As a result
1843 * SYSTIMR/L/H, TXSTMPL/H, RXSTMPL/H all have to be shifted by
1844 * 24 in order to generate a larger value for synchronization.
1845 */
1846 adapter->cycles.shift = IGB_82580_TSYNC_SHIFT;
1847 /* disable system timer temporarily by setting bit 31 */
1848 wr32(E1000_TSAUXC, 0x80000000);
1849 wrfl();
1850
1851 /* Set registers so that rollover occurs soon to test this. */
1852 wr32(E1000_SYSTIMR, 0x00000000);
1853 wr32(E1000_SYSTIML, 0x80000000);
1854 wr32(E1000_SYSTIMH, 0x000000FF);
1855 wrfl();
1856
1857 /* enable system timer by clearing bit 31 */
1858 wr32(E1000_TSAUXC, 0x0);
1859 wrfl();
1860
1861 timecounter_init(&adapter->clock,
1862 &adapter->cycles,
1863 ktime_to_ns(ktime_get_real()));
1864 /*
1865 * Synchronize our NIC clock against system wall clock. NIC
1866 * time stamp reading requires ~3us per sample, each sample
1867 * was pretty stable even under load => only require 10
1868 * samples for each offset comparison.
1869 */
1870 memset(&adapter->compare, 0, sizeof(adapter->compare));
1871 adapter->compare.source = &adapter->clock;
1872 adapter->compare.target = ktime_get_real;
1873 adapter->compare.num_samples = 10;
1874 timecompare_update(&adapter->compare, 0);
1875 break;
115f459a
AD		 1876 case e1000_82576:
1877 /*
1878 * Initialize hardware timer: we keep it running just in case
1879 * that some program needs it later on.
1880 */
1881 memset(&adapter->cycles, 0, sizeof(adapter->cycles));
1882 adapter->cycles.read = igb_read_clock;
1883 adapter->cycles.mask = CLOCKSOURCE_MASK(64);
1884 adapter->cycles.mult = 1;
1885 /**
1886 * Scale the NIC clock cycle by a large factor so that
1887 * relatively small clock corrections can be added or
1888 * substracted at each clock tick. The drawbacks of a large
1889 * factor are a) that the clock register overflows more quickly
1890 * (not such a big deal) and b) that the increment per tick has
1891 * to fit into 24 bits. As a result we need to use a shift of
1892 * 19 so we can fit a value of 16 into the TIMINCA register.
1893 */
1894 adapter->cycles.shift = IGB_82576_TSYNC_SHIFT;
1895 wr32(E1000_TIMINCA,
1896 (1 << E1000_TIMINCA_16NS_SHIFT) |
1897 (16 << IGB_82576_TSYNC_SHIFT));
1898
1899 /* Set registers so that rollover occurs soon to test this. */
1900 wr32(E1000_SYSTIML, 0x00000000);
1901 wr32(E1000_SYSTIMH, 0xFF800000);
1902 wrfl();
1903
1904 timecounter_init(&adapter->clock,
1905 &adapter->cycles,
1906 ktime_to_ns(ktime_get_real()));
1907 /*
1908 * Synchronize our NIC clock against system wall clock. NIC
1909 * time stamp reading requires ~3us per sample, each sample
1910 * was pretty stable even under load => only require 10
1911 * samples for each offset comparison.
1912 */
1913 memset(&adapter->compare, 0, sizeof(adapter->compare));
1914 adapter->compare.source = &adapter->clock;
1915 adapter->compare.target = ktime_get_real;
1916 adapter->compare.num_samples = 10;
1917 timecompare_update(&adapter->compare, 0);
1918 break;
1919 case e1000_82575:
1920 /* 82575 does not support timesync */
1921 default:
1922 break;
1923 }
1924
1925}
1926
9d5c8243
AK		 1927/**
1928 * igb_sw_init - Initialize general software structures (struct igb_adapter)
1929 * @adapter: board private structure to initialize
1930 *
1931 * igb_sw_init initializes the Adapter private data structure.
1932 * Fields are initialized based on PCI device information and
1933 * OS network device settings (MTU size).
1934 **/
1935static int __devinit igb_sw_init(struct igb_adapter *adapter)
1936{
1937 struct e1000_hw *hw = &adapter->hw;
1938 struct net_device *netdev = adapter->netdev;
1939 struct pci_dev *pdev = adapter->pdev;
1940
1941 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1942
68fd9910
AD		 1943 adapter->tx_ring_count = IGB_DEFAULT_TXD;
1944 adapter->rx_ring_count = IGB_DEFAULT_RXD;
4fc82adf
AD		 1945 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
1946 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
1947
9d5c8243
AK		 1948 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1949 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1950
a6b623e0
AD		 1951#ifdef CONFIG_PCI_IOV
1952 if (hw->mac.type == e1000_82576)
1953 adapter->vfs_allocated_count = max_vfs;
1954
1955#endif /* CONFIG_PCI_IOV */
a99955fc
AD		 1956 adapter->rss_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
1957
1958 /*
1959 * if rss_queues > 4 or vfs are going to be allocated with rss_queues
1960 * then we should combine the queues into a queue pair in order to
1961 * conserve interrupts due to limited supply
1962 */
1963 if ((adapter->rss_queues > 4) ||
1964 ((adapter->rss_queues > 1) && (adapter->vfs_allocated_count > 6)))
1965 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
1966
a6b623e0 1967 /* This call may decrease the number of queues */
047e0030 1968 if (igb_init_interrupt_scheme(adapter)) {
9d5c8243
AK		 1969 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1970 return -ENOMEM;
1971 }
1972
115f459a 1973 igb_init_hw_timer(adapter);
a6b623e0
AD		 1974 igb_probe_vfs(adapter);
1975
9d5c8243
AK		 1976 /* Explicitly disable IRQ since the NIC can be in any state. */
1977 igb_irq_disable(adapter);
1978
1979 set_bit(__IGB_DOWN, &adapter->state);
1980 return 0;
1981}
1982
1983/**
1984 * igb_open - Called when a network interface is made active
1985 * @netdev: network interface device structure
1986 *
1987 * Returns 0 on success, negative value on failure
1988 *
1989 * The open entry point is called when a network interface is made
1990 * active by the system (IFF_UP). At this point all resources needed
1991 * for transmit and receive operations are allocated, the interrupt
1992 * handler is registered with the OS, the watchdog timer is started,
1993 * and the stack is notified that the interface is ready.
1994 **/
1995static int igb_open(struct net_device *netdev)
1996{
1997 struct igb_adapter *adapter = netdev_priv(netdev);
1998 struct e1000_hw *hw = &adapter->hw;
1999 int err;
2000 int i;
2001
2002 /* disallow open during test */
2003 if (test_bit(__IGB_TESTING, &adapter->state))
2004 return -EBUSY;
2005
b168dfc5
JB		 2006 netif_carrier_off(netdev);
2007
9d5c8243
AK		 2008 /* allocate transmit descriptors */
2009 err = igb_setup_all_tx_resources(adapter);
2010 if (err)
2011 goto err_setup_tx;
2012
2013 /* allocate receive descriptors */
2014 err = igb_setup_all_rx_resources(adapter);
2015 if (err)
2016 goto err_setup_rx;
2017
88a268c1 2018 igb_power_up_link(adapter);
9d5c8243 2019
9d5c8243
AK		 2020 /* before we allocate an interrupt, we must be ready to handle it.
2021 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
2022 * as soon as we call pci_request_irq, so we have to setup our
2023 * clean_rx handler before we do so. */
2024 igb_configure(adapter);
2025
2026 err = igb_request_irq(adapter);
2027 if (err)
2028 goto err_req_irq;
2029
2030 /* From here on the code is the same as igb_up() */
2031 clear_bit(__IGB_DOWN, &adapter->state);
2032
047e0030
AD		 2033 for (i = 0; i < adapter->num_q_vectors; i++) {
2034 struct igb_q_vector *q_vector = adapter->q_vector[i];
2035 napi_enable(&q_vector->napi);
2036 }
9d5c8243
AK		 2037
2038 /* Clear any pending interrupts. */
2039 rd32(E1000_ICR);
844290e5
PW		 2040
2041 igb_irq_enable(adapter);
2042
d4960307
AD		 2043 /* notify VFs that reset has been completed */
2044 if (adapter->vfs_allocated_count) {
2045 u32 reg_data = rd32(E1000_CTRL_EXT);
2046 reg_data |= E1000_CTRL_EXT_PFRSTD;
2047 wr32(E1000_CTRL_EXT, reg_data);
2048 }
2049
d55b53ff
JK		 2050 netif_tx_start_all_queues(netdev);
2051
25568a53
AD		 2052 /* start the watchdog. */
2053 hw->mac.get_link_status = 1;
2054 schedule_work(&adapter->watchdog_task);
9d5c8243
AK		 2055
2056 return 0;
2057
2058err_req_irq:
2059 igb_release_hw_control(adapter);
88a268c1 2060 igb_power_down_link(adapter);
9d5c8243
AK		 2061 igb_free_all_rx_resources(adapter);
2062err_setup_rx:
2063 igb_free_all_tx_resources(adapter);
2064err_setup_tx:
2065 igb_reset(adapter);
2066
2067 return err;
2068}
2069
2070/**
2071 * igb_close - Disables a network interface
2072 * @netdev: network interface device structure
2073 *
2074 * Returns 0, this is not allowed to fail
2075 *
2076 * The close entry point is called when an interface is de-activated
2077 * by the OS. The hardware is still under the driver's control, but
2078 * needs to be disabled. A global MAC reset is issued to stop the
2079 * hardware, and all transmit and receive resources are freed.
2080 **/
2081static int igb_close(struct net_device *netdev)
2082{
2083 struct igb_adapter *adapter = netdev_priv(netdev);
2084
2085 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
2086 igb_down(adapter);
2087
2088 igb_free_irq(adapter);
2089
2090 igb_free_all_tx_resources(adapter);
2091 igb_free_all_rx_resources(adapter);
2092
9d5c8243
AK		 2093 return 0;
2094}
2095
2096/**
2097 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
9d5c8243
AK		 2098 * @tx_ring: tx descriptor ring (for a specific queue) to setup
2099 *
2100 * Return 0 on success, negative on failure
2101 **/
80785298 2102int igb_setup_tx_resources(struct igb_ring *tx_ring)
9d5c8243 2103{
80785298 2104 struct pci_dev *pdev = tx_ring->pdev;
9d5c8243
AK		 2105 int size;
2106
2107 size = sizeof(struct igb_buffer) * tx_ring->count;
2108 tx_ring->buffer_info = vmalloc(size);
2109 if (!tx_ring->buffer_info)
2110 goto err;
2111 memset(tx_ring->buffer_info, 0, size);
2112
2113 /* round up to nearest 4K */
85e8d004 2114 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 2115 tx_ring->size = ALIGN(tx_ring->size, 4096);
2116
439705e1
AD		 2117 tx_ring->desc = pci_alloc_consistent(pdev,
2118 tx_ring->size,
9d5c8243
AK		 2119 &tx_ring->dma);
2120
2121 if (!tx_ring->desc)
2122 goto err;
2123
9d5c8243
AK		 2124 tx_ring->next_to_use = 0;
2125 tx_ring->next_to_clean = 0;
9d5c8243
AK		 2126 return 0;
2127
2128err:
2129 vfree(tx_ring->buffer_info);
047e0030 2130 dev_err(&pdev->dev,
9d5c8243
AK		 2131 "Unable to allocate memory for the transmit descriptor ring\n");
2132 return -ENOMEM;
2133}
2134
2135/**
2136 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
2137 * (Descriptors) for all queues
2138 * @adapter: board private structure
2139 *
2140 * Return 0 on success, negative on failure
2141 **/
2142static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
2143{
439705e1 2144 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2145 int i, err = 0;
2146
2147 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 2148 err = igb_setup_tx_resources(adapter->tx_ring[i]);
9d5c8243 2149 if (err) {
439705e1 2150 dev_err(&pdev->dev,
9d5c8243
AK		 2151 "Allocation for Tx Queue %u failed\n", i);
2152 for (i--; i >= 0; i--)
3025a446 2153 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 2154 break;
2155 }
2156 }
2157
a99955fc 2158 for (i = 0; i < IGB_ABS_MAX_TX_QUEUES; i++) {
439705e1 2159 int r_idx = i % adapter->num_tx_queues;
3025a446 2160 adapter->multi_tx_table[i] = adapter->tx_ring[r_idx];
eebbbdba 2161 }
9d5c8243
AK		 2162 return err;
2163}
2164
2165/**
85b430b4
AD		 2166 * igb_setup_tctl - configure the transmit control registers
2167 * @adapter: Board private structure
9d5c8243 2168 **/
d7ee5b3a 2169void igb_setup_tctl(struct igb_adapter *adapter)
9d5c8243 2170{
9d5c8243
AK		 2171 struct e1000_hw *hw = &adapter->hw;
2172 u32 tctl;
9d5c8243 2173
85b430b4
AD		 2174 /* disable queue 0 which is enabled by default on 82575 and 82576 */
2175 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 2176
2177 /* Program the Transmit Control Register */
9d5c8243
AK		 2178 tctl = rd32(E1000_TCTL);
2179 tctl &= ~E1000_TCTL_CT;
2180 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2181 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2182
2183 igb_config_collision_dist(hw);
2184
9d5c8243
AK		 2185 /* Enable transmits */
2186 tctl |= E1000_TCTL_EN;
2187
2188 wr32(E1000_TCTL, tctl);
2189}
2190
85b430b4
AD		 2191/**
2192 * igb_configure_tx_ring - Configure transmit ring after Reset
2193 * @adapter: board private structure
2194 * @ring: tx ring to configure
2195 *
2196 * Configure a transmit ring after a reset.
2197 **/
d7ee5b3a
AD		 2198void igb_configure_tx_ring(struct igb_adapter *adapter,
2199 struct igb_ring *ring)
85b430b4
AD		 2200{
2201 struct e1000_hw *hw = &adapter->hw;
2202 u32 txdctl;
2203 u64 tdba = ring->dma;
2204 int reg_idx = ring->reg_idx;
2205
2206 /* disable the queue */
2207 txdctl = rd32(E1000_TXDCTL(reg_idx));
2208 wr32(E1000_TXDCTL(reg_idx),
2209 txdctl & ~E1000_TXDCTL_QUEUE_ENABLE);
2210 wrfl();
2211 mdelay(10);
2212
2213 wr32(E1000_TDLEN(reg_idx),
2214 ring->count * sizeof(union e1000_adv_tx_desc));
2215 wr32(E1000_TDBAL(reg_idx),
2216 tdba & 0x00000000ffffffffULL);
2217 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
2218
fce99e34
AD		 2219 ring->head = hw->hw_addr + E1000_TDH(reg_idx);
2220 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
2221 writel(0, ring->head);
2222 writel(0, ring->tail);
85b430b4
AD		 2223
2224 txdctl |= IGB_TX_PTHRESH;
2225 txdctl |= IGB_TX_HTHRESH << 8;
2226 txdctl |= IGB_TX_WTHRESH << 16;
2227
2228 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
2229 wr32(E1000_TXDCTL(reg_idx), txdctl);
2230}
2231
2232/**
2233 * igb_configure_tx - Configure transmit Unit after Reset
2234 * @adapter: board private structure
2235 *
2236 * Configure the Tx unit of the MAC after a reset.
2237 **/
2238static void igb_configure_tx(struct igb_adapter *adapter)
2239{
2240 int i;
2241
2242 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 2243 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
85b430b4
AD		 2244}
2245
9d5c8243
AK		 2246/**
2247 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
9d5c8243
AK		 2248 * @rx_ring: rx descriptor ring (for a specific queue) to setup
2249 *
2250 * Returns 0 on success, negative on failure
2251 **/
80785298 2252int igb_setup_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2253{
80785298 2254 struct pci_dev *pdev = rx_ring->pdev;
9d5c8243
AK		 2255 int size, desc_len;
2256
2257 size = sizeof(struct igb_buffer) * rx_ring->count;
2258 rx_ring->buffer_info = vmalloc(size);
2259 if (!rx_ring->buffer_info)
2260 goto err;
2261 memset(rx_ring->buffer_info, 0, size);
2262
2263 desc_len = sizeof(union e1000_adv_rx_desc);
2264
2265 /* Round up to nearest 4K */
2266 rx_ring->size = rx_ring->count * desc_len;
2267 rx_ring->size = ALIGN(rx_ring->size, 4096);
2268
2269 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
2270 &rx_ring->dma);
2271
2272 if (!rx_ring->desc)
2273 goto err;
2274
2275 rx_ring->next_to_clean = 0;
2276 rx_ring->next_to_use = 0;
9d5c8243 2277
9d5c8243
AK		 2278 return 0;
2279
2280err:
2281 vfree(rx_ring->buffer_info);
439705e1 2282 rx_ring->buffer_info = NULL;
80785298 2283 dev_err(&pdev->dev, "Unable to allocate memory for "
9d5c8243
AK		 2284 "the receive descriptor ring\n");
2285 return -ENOMEM;
2286}
2287
2288/**
2289 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
2290 * (Descriptors) for all queues
2291 * @adapter: board private structure
2292 *
2293 * Return 0 on success, negative on failure
2294 **/
2295static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
2296{
439705e1 2297 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2298 int i, err = 0;
2299
2300 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 2301 err = igb_setup_rx_resources(adapter->rx_ring[i]);
9d5c8243 2302 if (err) {
439705e1 2303 dev_err(&pdev->dev,
9d5c8243
AK		 2304 "Allocation for Rx Queue %u failed\n", i);
2305 for (i--; i >= 0; i--)
3025a446 2306 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 2307 break;
2308 }
2309 }
2310
2311 return err;
2312}
2313
06cf2666
AD		 2314/**
2315 * igb_setup_mrqc - configure the multiple receive queue control registers
2316 * @adapter: Board private structure
2317 **/
2318static void igb_setup_mrqc(struct igb_adapter *adapter)
2319{
2320 struct e1000_hw *hw = &adapter->hw;
2321 u32 mrqc, rxcsum;
2322 u32 j, num_rx_queues, shift = 0, shift2 = 0;
2323 union e1000_reta {
2324 u32 dword;
2325 u8 bytes[4];
2326 } reta;
2327 static const u8 rsshash[40] = {
2328 0x6d, 0x5a, 0x56, 0xda, 0x25, 0x5b, 0x0e, 0xc2, 0x41, 0x67,
2329 0x25, 0x3d, 0x43, 0xa3, 0x8f, 0xb0, 0xd0, 0xca, 0x2b, 0xcb,
2330 0xae, 0x7b, 0x30, 0xb4, 0x77, 0xcb, 0x2d, 0xa3, 0x80, 0x30,
2331 0xf2, 0x0c, 0x6a, 0x42, 0xb7, 0x3b, 0xbe, 0xac, 0x01, 0xfa };
2332
2333 /* Fill out hash function seeds */
2334 for (j = 0; j < 10; j++) {
2335 u32 rsskey = rsshash[(j * 4)];
2336 rsskey |= rsshash[(j * 4) + 1] << 8;
2337 rsskey |= rsshash[(j * 4) + 2] << 16;
2338 rsskey |= rsshash[(j * 4) + 3] << 24;
2339 array_wr32(E1000_RSSRK(0), j, rsskey);
2340 }
2341
a99955fc 2342 num_rx_queues = adapter->rss_queues;
06cf2666
AD		 2343
2344 if (adapter->vfs_allocated_count) {
2345 /* 82575 and 82576 supports 2 RSS queues for VMDq */
2346 switch (hw->mac.type) {
55cac248
AD		 2347 case e1000_82580:
2348 num_rx_queues = 1;
2349 shift = 0;
2350 break;
06cf2666
AD		 2351 case e1000_82576:
2352 shift = 3;
2353 num_rx_queues = 2;
2354 break;
2355 case e1000_82575:
2356 shift = 2;
2357 shift2 = 6;
2358 default:
2359 break;
2360 }
2361 } else {
2362 if (hw->mac.type == e1000_82575)
2363 shift = 6;
2364 }
2365
2366 for (j = 0; j < (32 * 4); j++) {
2367 reta.bytes[j & 3] = (j % num_rx_queues) << shift;
2368 if (shift2)
2369 reta.bytes[j & 3] |= num_rx_queues << shift2;
2370 if ((j & 3) == 3)
2371 wr32(E1000_RETA(j >> 2), reta.dword);
2372 }
2373
2374 /*
2375 * Disable raw packet checksumming so that RSS hash is placed in
2376 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
2377 * offloads as they are enabled by default
2378 */
2379 rxcsum = rd32(E1000_RXCSUM);
2380 rxcsum |= E1000_RXCSUM_PCSD;
2381
2382 if (adapter->hw.mac.type >= e1000_82576)
2383 /* Enable Receive Checksum Offload for SCTP */
2384 rxcsum |= E1000_RXCSUM_CRCOFL;
2385
2386 /* Don't need to set TUOFL or IPOFL, they default to 1 */
2387 wr32(E1000_RXCSUM, rxcsum);
2388
2389 /* If VMDq is enabled then we set the appropriate mode for that, else
2390 * we default to RSS so that an RSS hash is calculated per packet even
2391 * if we are only using one queue */
2392 if (adapter->vfs_allocated_count) {
2393 if (hw->mac.type > e1000_82575) {
2394 /* Set the default pool for the PF's first queue */
2395 u32 vtctl = rd32(E1000_VT_CTL);
2396 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
2397 E1000_VT_CTL_DISABLE_DEF_POOL);
2398 vtctl |= adapter->vfs_allocated_count <<
2399 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
2400 wr32(E1000_VT_CTL, vtctl);
2401 }
a99955fc 2402 if (adapter->rss_queues > 1)
06cf2666
AD		 2403 mrqc = E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
2404 else
2405 mrqc = E1000_MRQC_ENABLE_VMDQ;
2406 } else {
2407 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
2408 }
2409 igb_vmm_control(adapter);
2410
2411 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2412 E1000_MRQC_RSS_FIELD_IPV4_TCP);
2413 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2414 E1000_MRQC_RSS_FIELD_IPV6_TCP);
2415 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
2416 E1000_MRQC_RSS_FIELD_IPV6_UDP);
2417 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2418 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2419
2420 wr32(E1000_MRQC, mrqc);
2421}
2422
9d5c8243
AK		 2423/**
2424 * igb_setup_rctl - configure the receive control registers
2425 * @adapter: Board private structure
2426 **/
d7ee5b3a 2427void igb_setup_rctl(struct igb_adapter *adapter)
9d5c8243
AK		 2428{
2429 struct e1000_hw *hw = &adapter->hw;
2430 u32 rctl;
9d5c8243
AK		 2431
2432 rctl = rd32(E1000_RCTL);
2433
2434 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 2435 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 2436
69d728ba 2437 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 2438 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 2439
87cb7e8c
AK		 2440 /*
2441 * enable stripping of CRC. It's unlikely this will break BMC
2442 * redirection as it did with e1000. Newer features require
2443 * that the HW strips the CRC.
73cd78f1 2444 */
87cb7e8c 2445 rctl |= E1000_RCTL_SECRC;
9d5c8243 2446
559e9c49 2447 /* disable store bad packets and clear size bits. */
ec54d7d6 2448 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 2449
6ec43fe6
AD		 2450 /* enable LPE to prevent packets larger than max_frame_size */
2451 rctl |= E1000_RCTL_LPE;
9d5c8243 2452
952f72a8
AD		 2453 /* disable queue 0 to prevent tail write w/o re-config */
2454 wr32(E1000_RXDCTL(0), 0);
9d5c8243 2455
e1739522
AD		 2456 /* Attention!!! For SR-IOV PF driver operations you must enable
2457 * queue drop for all VF and PF queues to prevent head of line blocking
2458 * if an un-trusted VF does not provide descriptors to hardware.
2459 */
2460 if (adapter->vfs_allocated_count) {
e1739522
AD		 2461 /* set all queue drop enable bits */
2462 wr32(E1000_QDE, ALL_QUEUES);
e1739522
AD		 2463 }
2464
9d5c8243
AK		 2465 wr32(E1000_RCTL, rctl);
2466}
2467
7d5753f0
AD		 2468static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
2469 int vfn)
2470{
2471 struct e1000_hw *hw = &adapter->hw;
2472 u32 vmolr;
2473
2474 /* if it isn't the PF check to see if VFs are enabled and
2475 * increase the size to support vlan tags */
2476 if (vfn < adapter->vfs_allocated_count &&
2477 adapter->vf_data[vfn].vlans_enabled)
2478 size += VLAN_TAG_SIZE;
2479
2480 vmolr = rd32(E1000_VMOLR(vfn));
2481 vmolr &= ~E1000_VMOLR_RLPML_MASK;
2482 vmolr |= size | E1000_VMOLR_LPE;
2483 wr32(E1000_VMOLR(vfn), vmolr);
2484
2485 return 0;
2486}
2487
e1739522
AD		 2488/**
2489 * igb_rlpml_set - set maximum receive packet size
2490 * @adapter: board private structure
2491 *
2492 * Configure maximum receivable packet size.
2493 **/
2494static void igb_rlpml_set(struct igb_adapter *adapter)
2495{
2496 u32 max_frame_size = adapter->max_frame_size;
2497 struct e1000_hw *hw = &adapter->hw;
2498 u16 pf_id = adapter->vfs_allocated_count;
2499
2500 if (adapter->vlgrp)
2501 max_frame_size += VLAN_TAG_SIZE;
2502
2503 /* if vfs are enabled we set RLPML to the largest possible request
2504 * size and set the VMOLR RLPML to the size we need */
2505 if (pf_id) {
2506 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
7d5753f0 2507 max_frame_size = MAX_JUMBO_FRAME_SIZE;
e1739522
AD		 2508 }
2509
2510 wr32(E1000_RLPML, max_frame_size);
2511}
2512
8151d294
WM		 2513static inline void igb_set_vmolr(struct igb_adapter *adapter,
2514 int vfn, bool aupe)
7d5753f0
AD		 2515{
2516 struct e1000_hw *hw = &adapter->hw;
2517 u32 vmolr;
2518
2519 /*
2520 * This register exists only on 82576 and newer so if we are older then
2521 * we should exit and do nothing
2522 */
2523 if (hw->mac.type < e1000_82576)
2524 return;
2525
2526 vmolr = rd32(E1000_VMOLR(vfn));
8151d294
WM		 2527 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
2528 if (aupe)
2529 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
2530 else
2531 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
7d5753f0
AD		 2532
2533 /* clear all bits that might not be set */
2534 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
2535
a99955fc 2536 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
7d5753f0
AD		 2537 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
2538 /*
2539 * for VMDq only allow the VFs and pool 0 to accept broadcast and
2540 * multicast packets
2541 */
2542 if (vfn <= adapter->vfs_allocated_count)
2543 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
2544
2545 wr32(E1000_VMOLR(vfn), vmolr);
2546}
2547
85b430b4
AD		 2548/**
2549 * igb_configure_rx_ring - Configure a receive ring after Reset
2550 * @adapter: board private structure
2551 * @ring: receive ring to be configured
2552 *
2553 * Configure the Rx unit of the MAC after a reset.
2554 **/
d7ee5b3a
AD		 2555void igb_configure_rx_ring(struct igb_adapter *adapter,
2556 struct igb_ring *ring)
85b430b4
AD		 2557{
2558 struct e1000_hw *hw = &adapter->hw;
2559 u64 rdba = ring->dma;
2560 int reg_idx = ring->reg_idx;
952f72a8 2561 u32 srrctl, rxdctl;
85b430b4
AD		 2562
2563 /* disable the queue */
2564 rxdctl = rd32(E1000_RXDCTL(reg_idx));
2565 wr32(E1000_RXDCTL(reg_idx),
2566 rxdctl & ~E1000_RXDCTL_QUEUE_ENABLE);
2567
2568 /* Set DMA base address registers */
2569 wr32(E1000_RDBAL(reg_idx),
2570 rdba & 0x00000000ffffffffULL);
2571 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
2572 wr32(E1000_RDLEN(reg_idx),
2573 ring->count * sizeof(union e1000_adv_rx_desc));
2574
2575 /* initialize head and tail */
fce99e34
AD		 2576 ring->head = hw->hw_addr + E1000_RDH(reg_idx);
2577 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
2578 writel(0, ring->head);
2579 writel(0, ring->tail);
85b430b4 2580
952f72a8 2581 /* set descriptor configuration */
4c844851
AD		 2582 if (ring->rx_buffer_len < IGB_RXBUFFER_1024) {
2583 srrctl = ALIGN(ring->rx_buffer_len, 64) <<
952f72a8
AD		 2584 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2585#if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
2586 srrctl |= IGB_RXBUFFER_16384 >>
2587 E1000_SRRCTL_BSIZEPKT_SHIFT;
2588#else
2589 srrctl |= (PAGE_SIZE / 2) >>
2590 E1000_SRRCTL_BSIZEPKT_SHIFT;
2591#endif
2592 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2593 } else {
4c844851 2594 srrctl = ALIGN(ring->rx_buffer_len, 1024) >>
952f72a8
AD		 2595 E1000_SRRCTL_BSIZEPKT_SHIFT;
2596 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2597 }
2598
2599 wr32(E1000_SRRCTL(reg_idx), srrctl);
2600
7d5753f0 2601 /* set filtering for VMDQ pools */
8151d294 2602 igb_set_vmolr(adapter, reg_idx & 0x7, true);
7d5753f0 2603
85b430b4
AD		 2604 /* enable receive descriptor fetching */
2605 rxdctl = rd32(E1000_RXDCTL(reg_idx));
2606 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2607 rxdctl &= 0xFFF00000;
2608 rxdctl |= IGB_RX_PTHRESH;
2609 rxdctl |= IGB_RX_HTHRESH << 8;
2610 rxdctl |= IGB_RX_WTHRESH << 16;
2611 wr32(E1000_RXDCTL(reg_idx), rxdctl);
2612}
2613
9d5c8243
AK		 2614/**
2615 * igb_configure_rx - Configure receive Unit after Reset
2616 * @adapter: board private structure
2617 *
2618 * Configure the Rx unit of the MAC after a reset.
2619 **/
2620static void igb_configure_rx(struct igb_adapter *adapter)
2621{
9107584e 2622 int i;
9d5c8243 2623
68d480c4
AD		 2624 /* set UTA to appropriate mode */
2625 igb_set_uta(adapter);
2626
26ad9178
AD		 2627 /* set the correct pool for the PF default MAC address in entry 0 */
2628 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
2629 adapter->vfs_allocated_count);
2630
06cf2666
AD		 2631 /* Setup the HW Rx Head and Tail Descriptor Pointers and
2632 * the Base and Length of the Rx Descriptor Ring */
2633 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 2634 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
9d5c8243
AK		 2635}
2636
2637/**
2638 * igb_free_tx_resources - Free Tx Resources per Queue
9d5c8243
AK		 2639 * @tx_ring: Tx descriptor ring for a specific queue
2640 *
2641 * Free all transmit software resources
2642 **/
68fd9910 2643void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 2644{
3b644cf6 2645 igb_clean_tx_ring(tx_ring);
9d5c8243
AK		 2646
2647 vfree(tx_ring->buffer_info);
2648 tx_ring->buffer_info = NULL;
2649
439705e1
AD		 2650 /* if not set, then don't free */
2651 if (!tx_ring->desc)
2652 return;
2653
80785298
AD		 2654 pci_free_consistent(tx_ring->pdev, tx_ring->size,
2655 tx_ring->desc, tx_ring->dma);
9d5c8243
AK		 2656
2657 tx_ring->desc = NULL;
2658}
2659
2660/**
2661 * igb_free_all_tx_resources - Free Tx Resources for All Queues
2662 * @adapter: board private structure
2663 *
2664 * Free all transmit software resources
2665 **/
2666static void igb_free_all_tx_resources(struct igb_adapter *adapter)
2667{
2668 int i;
2669
2670 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 2671 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 2672}
2673
b1a436c3
AD		 2674void igb_unmap_and_free_tx_resource(struct igb_ring *tx_ring,
2675 struct igb_buffer *buffer_info)
9d5c8243 2676{
6366ad33
AD		 2677 if (buffer_info->dma) {
2678 if (buffer_info->mapped_as_page)
2679 pci_unmap_page(tx_ring->pdev,
2680 buffer_info->dma,
2681 buffer_info->length,
2682 PCI_DMA_TODEVICE);
2683 else
2684 pci_unmap_single(tx_ring->pdev,
2685 buffer_info->dma,
2686 buffer_info->length,
2687 PCI_DMA_TODEVICE);
2688 buffer_info->dma = 0;
2689 }
9d5c8243
AK		 2690 if (buffer_info->skb) {
2691 dev_kfree_skb_any(buffer_info->skb);
2692 buffer_info->skb = NULL;
2693 }
2694 buffer_info->time_stamp = 0;
6366ad33
AD		 2695 buffer_info->length = 0;
2696 buffer_info->next_to_watch = 0;
2697 buffer_info->mapped_as_page = false;
9d5c8243
AK		 2698}
2699
2700/**
2701 * igb_clean_tx_ring - Free Tx Buffers
9d5c8243
AK		 2702 * @tx_ring: ring to be cleaned
2703 **/
3b644cf6 2704static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243
AK		 2705{
2706 struct igb_buffer *buffer_info;
2707 unsigned long size;
2708 unsigned int i;
2709
2710 if (!tx_ring->buffer_info)
2711 return;
2712 /* Free all the Tx ring sk_buffs */
2713
2714 for (i = 0; i < tx_ring->count; i++) {
2715 buffer_info = &tx_ring->buffer_info[i];
80785298 2716 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
9d5c8243
AK		 2717 }
2718
2719 size = sizeof(struct igb_buffer) * tx_ring->count;
2720 memset(tx_ring->buffer_info, 0, size);
2721
2722 /* Zero out the descriptor ring */
9d5c8243
AK		 2723 memset(tx_ring->desc, 0, tx_ring->size);
2724
2725 tx_ring->next_to_use = 0;
2726 tx_ring->next_to_clean = 0;
9d5c8243
AK		 2727}
2728
2729/**
2730 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2731 * @adapter: board private structure
2732 **/
2733static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2734{
2735 int i;
2736
2737 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 2738 igb_clean_tx_ring(adapter->tx_ring[i]);
9d5c8243
AK		 2739}
2740
2741/**
2742 * igb_free_rx_resources - Free Rx Resources
9d5c8243
AK		 2743 * @rx_ring: ring to clean the resources from
2744 *
2745 * Free all receive software resources
2746 **/
68fd9910 2747void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2748{
3b644cf6 2749 igb_clean_rx_ring(rx_ring);
9d5c8243
AK		 2750
2751 vfree(rx_ring->buffer_info);
2752 rx_ring->buffer_info = NULL;
2753
439705e1
AD		 2754 /* if not set, then don't free */
2755 if (!rx_ring->desc)
2756 return;
2757
80785298
AD		 2758 pci_free_consistent(rx_ring->pdev, rx_ring->size,
2759 rx_ring->desc, rx_ring->dma);
9d5c8243
AK		 2760
2761 rx_ring->desc = NULL;
2762}
2763
2764/**
2765 * igb_free_all_rx_resources - Free Rx Resources for All Queues
2766 * @adapter: board private structure
2767 *
2768 * Free all receive software resources
2769 **/
2770static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2771{
2772 int i;
2773
2774 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 2775 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 2776}
2777
2778/**
2779 * igb_clean_rx_ring - Free Rx Buffers per Queue
9d5c8243
AK		 2780 * @rx_ring: ring to free buffers from
2781 **/
3b644cf6 2782static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243
AK		 2783{
2784 struct igb_buffer *buffer_info;
9d5c8243
AK		 2785 unsigned long size;
2786 unsigned int i;
2787
2788 if (!rx_ring->buffer_info)
2789 return;
439705e1 2790
9d5c8243
AK		 2791 /* Free all the Rx ring sk_buffs */
2792 for (i = 0; i < rx_ring->count; i++) {
2793 buffer_info = &rx_ring->buffer_info[i];
2794 if (buffer_info->dma) {
80785298
AD		 2795 pci_unmap_single(rx_ring->pdev,
2796 buffer_info->dma,
4c844851 2797 rx_ring->rx_buffer_len,
6ec43fe6 2798 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 2799 buffer_info->dma = 0;
2800 }
2801
2802 if (buffer_info->skb) {
2803 dev_kfree_skb(buffer_info->skb);
2804 buffer_info->skb = NULL;
2805 }
6ec43fe6 2806 if (buffer_info->page_dma) {
80785298
AD		 2807 pci_unmap_page(rx_ring->pdev,
2808 buffer_info->page_dma,
6ec43fe6
AD		 2809 PAGE_SIZE / 2,
2810 PCI_DMA_FROMDEVICE);
2811 buffer_info->page_dma = 0;
2812 }
9d5c8243 2813 if (buffer_info->page) {
9d5c8243
AK		 2814 put_page(buffer_info->page);
2815 buffer_info->page = NULL;
bf36c1a0 2816 buffer_info->page_offset = 0;
9d5c8243
AK		 2817 }
2818 }
2819
9d5c8243
AK		 2820 size = sizeof(struct igb_buffer) * rx_ring->count;
2821 memset(rx_ring->buffer_info, 0, size);
2822
2823 /* Zero out the descriptor ring */
2824 memset(rx_ring->desc, 0, rx_ring->size);
2825
2826 rx_ring->next_to_clean = 0;
2827 rx_ring->next_to_use = 0;
9d5c8243
AK		 2828}
2829
2830/**
2831 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2832 * @adapter: board private structure
2833 **/
2834static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2835{
2836 int i;
2837
2838 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 2839 igb_clean_rx_ring(adapter->rx_ring[i]);
9d5c8243
AK		 2840}
2841
2842/**
2843 * igb_set_mac - Change the Ethernet Address of the NIC
2844 * @netdev: network interface device structure
2845 * @p: pointer to an address structure
2846 *
2847 * Returns 0 on success, negative on failure
2848 **/
2849static int igb_set_mac(struct net_device *netdev, void *p)
2850{
2851 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 2852 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 2853 struct sockaddr *addr = p;
2854
2855 if (!is_valid_ether_addr(addr->sa_data))
2856 return -EADDRNOTAVAIL;
2857
2858 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 2859 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 2860
26ad9178
AD		 2861 /* set the correct pool for the new PF MAC address in entry 0 */
2862 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
2863 adapter->vfs_allocated_count);
e1739522 2864
9d5c8243
AK		 2865 return 0;
2866}
2867
2868/**
68d480c4 2869 * igb_write_mc_addr_list - write multicast addresses to MTA
9d5c8243
AK		 2870 * @netdev: network interface device structure
2871 *
68d480c4
AD		 2872 * Writes multicast address list to the MTA hash table.
2873 * Returns: -ENOMEM on failure
2874 * 0 on no addresses written
2875 * X on writing X addresses to MTA
9d5c8243 2876 **/
68d480c4 2877static int igb_write_mc_addr_list(struct net_device *netdev)
9d5c8243
AK		 2878{
2879 struct igb_adapter *adapter = netdev_priv(netdev);
2880 struct e1000_hw *hw = &adapter->hw;
ff41f8dc 2881 struct dev_mc_list *mc_ptr = netdev->mc_list;
68d480c4
AD		 2882 u8 *mta_list;
2883 u32 vmolr = 0;
9d5c8243
AK		 2884 int i;
2885
4cd24eaf 2886 if (netdev_mc_empty(netdev)) {
68d480c4
AD		 2887 /* nothing to program, so clear mc list */
2888 igb_update_mc_addr_list(hw, NULL, 0);
2889 igb_restore_vf_multicasts(adapter);
2890 return 0;
2891 }
9d5c8243 2892
4cd24eaf 2893 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
68d480c4
AD		 2894 if (!mta_list)
2895 return -ENOMEM;
ff41f8dc 2896
68d480c4
AD		 2897 /* set vmolr receive overflow multicast bit */
2898 vmolr |= E1000_VMOLR_ROMPE;
2899
2900 /* The shared function expects a packed array of only addresses. */
2901 mc_ptr = netdev->mc_list;
2902
4cd24eaf 2903 for (i = 0; i < netdev_mc_count(netdev); i++) {
68d480c4
AD		 2904 if (!mc_ptr)
2905 break;
2906 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2907 mc_ptr = mc_ptr->next;
746b9f02 2908 }
68d480c4
AD		 2909 igb_update_mc_addr_list(hw, mta_list, i);
2910 kfree(mta_list);
2911
4cd24eaf 2912 return netdev_mc_count(netdev);
68d480c4
AD		 2913}
2914
2915/**
2916 * igb_write_uc_addr_list - write unicast addresses to RAR table
2917 * @netdev: network interface device structure
2918 *
2919 * Writes unicast address list to the RAR table.
2920 * Returns: -ENOMEM on failure/insufficient address space
2921 * 0 on no addresses written
2922 * X on writing X addresses to the RAR table
2923 **/
2924static int igb_write_uc_addr_list(struct net_device *netdev)
2925{
2926 struct igb_adapter *adapter = netdev_priv(netdev);
2927 struct e1000_hw *hw = &adapter->hw;
2928 unsigned int vfn = adapter->vfs_allocated_count;
2929 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
2930 int count = 0;
2931
2932 /* return ENOMEM indicating insufficient memory for addresses */
32e7bfc4 2933 if (netdev_uc_count(netdev) > rar_entries)
68d480c4 2934 return -ENOMEM;
9d5c8243 2935
32e7bfc4 2936 if (!netdev_uc_empty(netdev) && rar_entries) {
ff41f8dc 2937 struct netdev_hw_addr *ha;
32e7bfc4
JP		 2938
2939 netdev_for_each_uc_addr(ha, netdev) {
ff41f8dc
AD		 2940 if (!rar_entries)
2941 break;
26ad9178
AD		 2942 igb_rar_set_qsel(adapter, ha->addr,
2943 rar_entries--,
68d480c4
AD		 2944 vfn);
2945 count++;
ff41f8dc
AD		 2946 }
2947 }
2948 /* write the addresses in reverse order to avoid write combining */
2949 for (; rar_entries > 0 ; rar_entries--) {
2950 wr32(E1000_RAH(rar_entries), 0);
2951 wr32(E1000_RAL(rar_entries), 0);
2952 }
2953 wrfl();
2954
68d480c4
AD		 2955 return count;
2956}
2957
2958/**
2959 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
2960 * @netdev: network interface device structure
2961 *
2962 * The set_rx_mode entry point is called whenever the unicast or multicast
2963 * address lists or the network interface flags are updated. This routine is
2964 * responsible for configuring the hardware for proper unicast, multicast,
2965 * promiscuous mode, and all-multi behavior.
2966 **/
2967static void igb_set_rx_mode(struct net_device *netdev)
2968{
2969 struct igb_adapter *adapter = netdev_priv(netdev);
2970 struct e1000_hw *hw = &adapter->hw;
2971 unsigned int vfn = adapter->vfs_allocated_count;
2972 u32 rctl, vmolr = 0;
2973 int count;
2974
2975 /* Check for Promiscuous and All Multicast modes */
2976 rctl = rd32(E1000_RCTL);
2977
2978 /* clear the effected bits */
2979 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
2980
2981 if (netdev->flags & IFF_PROMISC) {
2982 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2983 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
2984 } else {
2985 if (netdev->flags & IFF_ALLMULTI) {
2986 rctl |= E1000_RCTL_MPE;
2987 vmolr |= E1000_VMOLR_MPME;
2988 } else {
2989 /*
2990 * Write addresses to the MTA, if the attempt fails
2991 * then we should just turn on promiscous mode so
2992 * that we can at least receive multicast traffic
2993 */
2994 count = igb_write_mc_addr_list(netdev);
2995 if (count < 0) {
2996 rctl |= E1000_RCTL_MPE;
2997 vmolr |= E1000_VMOLR_MPME;
2998 } else if (count) {
2999 vmolr |= E1000_VMOLR_ROMPE;
3000 }
3001 }
3002 /*
3003 * Write addresses to available RAR registers, if there is not
3004 * sufficient space to store all the addresses then enable
3005 * unicast promiscous mode
3006 */
3007 count = igb_write_uc_addr_list(netdev);
3008 if (count < 0) {
3009 rctl |= E1000_RCTL_UPE;
3010 vmolr |= E1000_VMOLR_ROPE;
3011 }
3012 rctl |= E1000_RCTL_VFE;
28fc06f5 3013 }
68d480c4 3014 wr32(E1000_RCTL, rctl);
28fc06f5 3015
68d480c4
AD		 3016 /*
3017 * In order to support SR-IOV and eventually VMDq it is necessary to set
3018 * the VMOLR to enable the appropriate modes. Without this workaround
3019 * we will have issues with VLAN tag stripping not being done for frames
3020 * that are only arriving because we are the default pool
3021 */
3022 if (hw->mac.type < e1000_82576)
28fc06f5 3023 return;
9d5c8243 3024
68d480c4
AD		 3025 vmolr |= rd32(E1000_VMOLR(vfn)) &
3026 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
3027 wr32(E1000_VMOLR(vfn), vmolr);
28fc06f5 3028 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 3029}
3030
3031/* Need to wait a few seconds after link up to get diagnostic information from
3032 * the phy */
3033static void igb_update_phy_info(unsigned long data)
3034{
3035 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 3036 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 3037}
3038
4d6b725e
AD		 3039/**
3040 * igb_has_link - check shared code for link and determine up/down
3041 * @adapter: pointer to driver private info
3042 **/
3145535a 3043bool igb_has_link(struct igb_adapter *adapter)
4d6b725e
AD		 3044{
3045 struct e1000_hw *hw = &adapter->hw;
3046 bool link_active = false;
3047 s32 ret_val = 0;
3048
3049 /* get_link_status is set on LSC (link status) interrupt or
3050 * rx sequence error interrupt. get_link_status will stay
3051 * false until the e1000_check_for_link establishes link
3052 * for copper adapters ONLY
3053 */
3054 switch (hw->phy.media_type) {
3055 case e1000_media_type_copper:
3056 if (hw->mac.get_link_status) {
3057 ret_val = hw->mac.ops.check_for_link(hw);
3058 link_active = !hw->mac.get_link_status;
3059 } else {
3060 link_active = true;
3061 }
3062 break;
4d6b725e
AD		 3063 case e1000_media_type_internal_serdes:
3064 ret_val = hw->mac.ops.check_for_link(hw);
3065 link_active = hw->mac.serdes_has_link;
3066 break;
3067 default:
3068 case e1000_media_type_unknown:
3069 break;
3070 }
3071
3072 return link_active;
3073}
3074
9d5c8243
AK		 3075/**
3076 * igb_watchdog - Timer Call-back
3077 * @data: pointer to adapter cast into an unsigned long
3078 **/
3079static void igb_watchdog(unsigned long data)
3080{
3081 struct igb_adapter *adapter = (struct igb_adapter *)data;
3082 /* Do the rest outside of interrupt context */
3083 schedule_work(&adapter->watchdog_task);
3084}
3085
3086static void igb_watchdog_task(struct work_struct *work)
3087{
3088 struct igb_adapter *adapter = container_of(work,
559e9c49
AD		 3089 struct igb_adapter,
3090 watchdog_task);
9d5c8243 3091 struct e1000_hw *hw = &adapter->hw;
9d5c8243 3092 struct net_device *netdev = adapter->netdev;
9d5c8243 3093 u32 link;
7a6ea550 3094 int i;
9d5c8243 3095
4d6b725e 3096 link = igb_has_link(adapter);
9d5c8243
AK		 3097 if (link) {
3098 if (!netif_carrier_ok(netdev)) {
3099 u32 ctrl;
330a6d6a
AD		 3100 hw->mac.ops.get_speed_and_duplex(hw,
3101 &adapter->link_speed,
3102 &adapter->link_duplex);
9d5c8243
AK		 3103
3104 ctrl = rd32(E1000_CTRL);
527d47c1
AD		 3105 /* Links status message must follow this format */
3106 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
9d5c8243 3107 "Flow Control: %s\n",
559e9c49
AD		 3108 netdev->name,
3109 adapter->link_speed,
3110 adapter->link_duplex == FULL_DUPLEX ?
9d5c8243 3111 "Full Duplex" : "Half Duplex",
559e9c49
AD		 3112 ((ctrl & E1000_CTRL_TFCE) &&
3113 (ctrl & E1000_CTRL_RFCE)) ? "RX/TX" :
3114 ((ctrl & E1000_CTRL_RFCE) ? "RX" :
3115 ((ctrl & E1000_CTRL_TFCE) ? "TX" : "None")));
9d5c8243
AK		 3116
3117 /* tweak tx_queue_len according to speed/duplex and
3118 * adjust the timeout factor */
3119 netdev->tx_queue_len = adapter->tx_queue_len;
3120 adapter->tx_timeout_factor = 1;
3121 switch (adapter->link_speed) {
3122 case SPEED_10:
3123 netdev->tx_queue_len = 10;
3124 adapter->tx_timeout_factor = 14;
3125 break;
3126 case SPEED_100:
3127 netdev->tx_queue_len = 100;
3128 /* maybe add some timeout factor ? */
3129 break;
3130 }
3131
3132 netif_carrier_on(netdev);
9d5c8243 3133
4ae196df
AD		 3134 igb_ping_all_vfs(adapter);
3135
4b1a9877 3136 /* link state has changed, schedule phy info update */
9d5c8243
AK		 3137 if (!test_bit(__IGB_DOWN, &adapter->state))
3138 mod_timer(&adapter->phy_info_timer,
3139 round_jiffies(jiffies + 2 * HZ));
3140 }
3141 } else {
3142 if (netif_carrier_ok(netdev)) {
3143 adapter->link_speed = 0;
3144 adapter->link_duplex = 0;
527d47c1
AD		 3145 /* Links status message must follow this format */
3146 printk(KERN_INFO "igb: %s NIC Link is Down\n",
3147 netdev->name);
9d5c8243 3148 netif_carrier_off(netdev);
4b1a9877 3149
4ae196df
AD		 3150 igb_ping_all_vfs(adapter);
3151
4b1a9877 3152 /* link state has changed, schedule phy info update */
9d5c8243
AK		 3153 if (!test_bit(__IGB_DOWN, &adapter->state))
3154 mod_timer(&adapter->phy_info_timer,
3155 round_jiffies(jiffies + 2 * HZ));
3156 }
3157 }
3158
9d5c8243 3159 igb_update_stats(adapter);
9d5c8243 3160
dbabb065 3161 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 3162 struct igb_ring *tx_ring = adapter->tx_ring[i];
dbabb065 3163 if (!netif_carrier_ok(netdev)) {
9d5c8243
AK		 3164 /* We've lost link, so the controller stops DMA,
3165 * but we've got queued Tx work that's never going
3166 * to get done, so reset controller to flush Tx.
3167 * (Do the reset outside of interrupt context). */
dbabb065
AD		 3168 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
3169 adapter->tx_timeout_count++;
3170 schedule_work(&adapter->reset_task);
3171 /* return immediately since reset is imminent */
3172 return;
3173 }
9d5c8243 3174 }
9d5c8243 3175
dbabb065
AD		 3176 /* Force detection of hung controller every watchdog period */
3177 tx_ring->detect_tx_hung = true;
3178 }
f7ba205e 3179
9d5c8243 3180 /* Cause software interrupt to ensure rx ring is cleaned */
7a6ea550 3181 if (adapter->msix_entries) {
047e0030
AD		 3182 u32 eics = 0;
3183 for (i = 0; i < adapter->num_q_vectors; i++) {
3184 struct igb_q_vector *q_vector = adapter->q_vector[i];
3185 eics |= q_vector->eims_value;
3186 }
7a6ea550
AD		 3187 wr32(E1000_EICS, eics);
3188 } else {
3189 wr32(E1000_ICS, E1000_ICS_RXDMT0);
3190 }
9d5c8243 3191
9d5c8243
AK		 3192 /* Reset the timer */
3193 if (!test_bit(__IGB_DOWN, &adapter->state))
3194 mod_timer(&adapter->watchdog_timer,
3195 round_jiffies(jiffies + 2 * HZ));
3196}
3197
3198enum latency_range {
3199 lowest_latency = 0,
3200 low_latency = 1,
3201 bulk_latency = 2,
3202 latency_invalid = 255
3203};
3204
6eb5a7f1
AD		 3205/**
3206 * igb_update_ring_itr - update the dynamic ITR value based on packet size
3207 *
3208 * Stores a new ITR value based on strictly on packet size. This
3209 * algorithm is less sophisticated than that used in igb_update_itr,
3210 * due to the difficulty of synchronizing statistics across multiple
3211 * receive rings. The divisors and thresholds used by this fuction
3212 * were determined based on theoretical maximum wire speed and testing
3213 * data, in order to minimize response time while increasing bulk
3214 * throughput.
3215 * This functionality is controlled by the InterruptThrottleRate module
3216 * parameter (see igb_param.c)
3217 * NOTE: This function is called only when operating in a multiqueue
3218 * receive environment.
047e0030 3219 * @q_vector: pointer to q_vector
6eb5a7f1 3220 **/
047e0030 3221static void igb_update_ring_itr(struct igb_q_vector *q_vector)
9d5c8243 3222{
047e0030 3223 int new_val = q_vector->itr_val;
6eb5a7f1 3224 int avg_wire_size = 0;
047e0030 3225 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 3226
6eb5a7f1
AD		 3227 /* For non-gigabit speeds, just fix the interrupt rate at 4000
3228 * ints/sec - ITR timer value of 120 ticks.
3229 */
3230 if (adapter->link_speed != SPEED_1000) {
047e0030 3231 new_val = 976;
6eb5a7f1 3232 goto set_itr_val;
9d5c8243 3233 }
047e0030
AD		 3234
3235 if (q_vector->rx_ring && q_vector->rx_ring->total_packets) {
3236 struct igb_ring *ring = q_vector->rx_ring;
3237 avg_wire_size = ring->total_bytes / ring->total_packets;
3238 }
3239
3240 if (q_vector->tx_ring && q_vector->tx_ring->total_packets) {
3241 struct igb_ring *ring = q_vector->tx_ring;
3242 avg_wire_size = max_t(u32, avg_wire_size,
3243 (ring->total_bytes /
3244 ring->total_packets));
3245 }
3246
3247 /* if avg_wire_size isn't set no work was done */
3248 if (!avg_wire_size)
3249 goto clear_counts;
9d5c8243 3250
6eb5a7f1
AD		 3251 /* Add 24 bytes to size to account for CRC, preamble, and gap */
3252 avg_wire_size += 24;
3253
3254 /* Don't starve jumbo frames */
3255 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 3256
6eb5a7f1
AD		 3257 /* Give a little boost to mid-size frames */
3258 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
3259 new_val = avg_wire_size / 3;
3260 else
3261 new_val = avg_wire_size / 2;
9d5c8243 3262
abe1c363
NN		 3263 /* when in itr mode 3 do not exceed 20K ints/sec */
3264 if (adapter->rx_itr_setting == 3 && new_val < 196)
3265 new_val = 196;
3266
6eb5a7f1 3267set_itr_val:
047e0030
AD		 3268 if (new_val != q_vector->itr_val) {
3269 q_vector->itr_val = new_val;
3270 q_vector->set_itr = 1;
9d5c8243 3271 }
6eb5a7f1 3272clear_counts:
047e0030
AD		 3273 if (q_vector->rx_ring) {
3274 q_vector->rx_ring->total_bytes = 0;
3275 q_vector->rx_ring->total_packets = 0;
3276 }
3277 if (q_vector->tx_ring) {
3278 q_vector->tx_ring->total_bytes = 0;
3279 q_vector->tx_ring->total_packets = 0;
3280 }
9d5c8243
AK		 3281}
3282
3283/**
3284 * igb_update_itr - update the dynamic ITR value based on statistics
3285 * Stores a new ITR value based on packets and byte
3286 * counts during the last interrupt. The advantage of per interrupt
3287 * computation is faster updates and more accurate ITR for the current
3288 * traffic pattern. Constants in this function were computed
3289 * based on theoretical maximum wire speed and thresholds were set based
3290 * on testing data as well as attempting to minimize response time
3291 * while increasing bulk throughput.
3292 * this functionality is controlled by the InterruptThrottleRate module
3293 * parameter (see igb_param.c)
3294 * NOTE: These calculations are only valid when operating in a single-
3295 * queue environment.
3296 * @adapter: pointer to adapter
047e0030 3297 * @itr_setting: current q_vector->itr_val
9d5c8243
AK		 3298 * @packets: the number of packets during this measurement interval
3299 * @bytes: the number of bytes during this measurement interval
3300 **/
3301static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
3302 int packets, int bytes)
3303{
3304 unsigned int retval = itr_setting;
3305
3306 if (packets == 0)
3307 goto update_itr_done;
3308
3309 switch (itr_setting) {
3310 case lowest_latency:
3311 /* handle TSO and jumbo frames */
3312 if (bytes/packets > 8000)
3313 retval = bulk_latency;
3314 else if ((packets < 5) && (bytes > 512))
3315 retval = low_latency;
3316 break;
3317 case low_latency: /* 50 usec aka 20000 ints/s */
3318 if (bytes > 10000) {
3319 /* this if handles the TSO accounting */
3320 if (bytes/packets > 8000) {
3321 retval = bulk_latency;
3322 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
3323 retval = bulk_latency;
3324 } else if ((packets > 35)) {
3325 retval = lowest_latency;
3326 }
3327 } else if (bytes/packets > 2000) {
3328 retval = bulk_latency;
3329 } else if (packets <= 2 && bytes < 512) {
3330 retval = lowest_latency;
3331 }
3332 break;
3333 case bulk_latency: /* 250 usec aka 4000 ints/s */
3334 if (bytes > 25000) {
3335 if (packets > 35)
3336 retval = low_latency;
1e5c3d21 3337 } else if (bytes < 1500) {
9d5c8243
AK		 3338 retval = low_latency;
3339 }
3340 break;
3341 }
3342
3343update_itr_done:
3344 return retval;
3345}
3346
6eb5a7f1 3347static void igb_set_itr(struct igb_adapter *adapter)
9d5c8243 3348{
047e0030 3349 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243 3350 u16 current_itr;
047e0030 3351 u32 new_itr = q_vector->itr_val;
9d5c8243
AK		 3352
3353 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
3354 if (adapter->link_speed != SPEED_1000) {
3355 current_itr = 0;
3356 new_itr = 4000;
3357 goto set_itr_now;
3358 }
3359
3360 adapter->rx_itr = igb_update_itr(adapter,
3361 adapter->rx_itr,
3025a446
AD		 3362 q_vector->rx_ring->total_packets,
3363 q_vector->rx_ring->total_bytes);
9d5c8243 3364
047e0030
AD		 3365 adapter->tx_itr = igb_update_itr(adapter,
3366 adapter->tx_itr,
3025a446
AD		 3367 q_vector->tx_ring->total_packets,
3368 q_vector->tx_ring->total_bytes);
047e0030 3369 current_itr = max(adapter->rx_itr, adapter->tx_itr);
9d5c8243 3370
6eb5a7f1 3371 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4fc82adf 3372 if (adapter->rx_itr_setting == 3 && current_itr == lowest_latency)
6eb5a7f1
AD		 3373 current_itr = low_latency;
3374
9d5c8243
AK		 3375 switch (current_itr) {
3376 /* counts and packets in update_itr are dependent on these numbers */
3377 case lowest_latency:
78b1f607 3378 new_itr = 56; /* aka 70,000 ints/sec */
9d5c8243
AK		 3379 break;
3380 case low_latency:
78b1f607 3381 new_itr = 196; /* aka 20,000 ints/sec */
9d5c8243
AK		 3382 break;
3383 case bulk_latency:
78b1f607 3384 new_itr = 980; /* aka 4,000 ints/sec */
9d5c8243
AK		 3385 break;
3386 default:
3387 break;
3388 }
3389
3390set_itr_now:
3025a446
AD		 3391 q_vector->rx_ring->total_bytes = 0;
3392 q_vector->rx_ring->total_packets = 0;
3393 q_vector->tx_ring->total_bytes = 0;
3394 q_vector->tx_ring->total_packets = 0;
6eb5a7f1 3395
047e0030 3396 if (new_itr != q_vector->itr_val) {
9d5c8243
AK		 3397 /* this attempts to bias the interrupt rate towards Bulk
3398 * by adding intermediate steps when interrupt rate is
3399 * increasing */
047e0030
AD		 3400 new_itr = new_itr > q_vector->itr_val ?
3401 max((new_itr * q_vector->itr_val) /
3402 (new_itr + (q_vector->itr_val >> 2)),
3403 new_itr) :
9d5c8243
AK		 3404 new_itr;
3405 /* Don't write the value here; it resets the adapter's
3406 * internal timer, and causes us to delay far longer than
3407 * we should between interrupts. Instead, we write the ITR
3408 * value at the beginning of the next interrupt so the timing
3409 * ends up being correct.
3410 */
047e0030
AD		 3411 q_vector->itr_val = new_itr;
3412 q_vector->set_itr = 1;
9d5c8243
AK		 3413 }
3414
3415 return;
3416}
3417
9d5c8243
AK		 3418#define IGB_TX_FLAGS_CSUM 0x00000001
3419#define IGB_TX_FLAGS_VLAN 0x00000002
3420#define IGB_TX_FLAGS_TSO 0x00000004
3421#define IGB_TX_FLAGS_IPV4 0x00000008
cdfd01fc
AD		 3422#define IGB_TX_FLAGS_TSTAMP 0x00000010
3423#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
3424#define IGB_TX_FLAGS_VLAN_SHIFT 16
9d5c8243 3425
85ad76b2 3426static inline int igb_tso_adv(struct igb_ring *tx_ring,
9d5c8243
AK		 3427 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
3428{
3429 struct e1000_adv_tx_context_desc *context_desc;
3430 unsigned int i;
3431 int err;
3432 struct igb_buffer *buffer_info;
3433 u32 info = 0, tu_cmd = 0;
3434 u32 mss_l4len_idx, l4len;
3435 *hdr_len = 0;
3436
3437 if (skb_header_cloned(skb)) {
3438 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
3439 if (err)
3440 return err;
3441 }
3442
3443 l4len = tcp_hdrlen(skb);
3444 *hdr_len += l4len;
3445
3446 if (skb->protocol == htons(ETH_P_IP)) {
3447 struct iphdr *iph = ip_hdr(skb);
3448 iph->tot_len = 0;
3449 iph->check = 0;
3450 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
3451 iph->daddr, 0,
3452 IPPROTO_TCP,
3453 0);
8e1e8a47 3454 } else if (skb_is_gso_v6(skb)) {
9d5c8243
AK		 3455 ipv6_hdr(skb)->payload_len = 0;
3456 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
3457 &ipv6_hdr(skb)->daddr,
3458 0, IPPROTO_TCP, 0);
3459 }
3460
3461 i = tx_ring->next_to_use;
3462
3463 buffer_info = &tx_ring->buffer_info[i];
3464 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3465 /* VLAN MACLEN IPLEN */
3466 if (tx_flags & IGB_TX_FLAGS_VLAN)
3467 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
3468 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3469 *hdr_len += skb_network_offset(skb);
3470 info |= skb_network_header_len(skb);
3471 *hdr_len += skb_network_header_len(skb);
3472 context_desc->vlan_macip_lens = cpu_to_le32(info);
3473
3474 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
3475 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3476
3477 if (skb->protocol == htons(ETH_P_IP))
3478 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
3479 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3480
3481 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3482
3483 /* MSS L4LEN IDX */
3484 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
3485 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
3486
73cd78f1 3487 /* For 82575, context index must be unique per ring. */
85ad76b2
AD		 3488 if (tx_ring->flags & IGB_RING_FLAG_TX_CTX_IDX)
3489 mss_l4len_idx |= tx_ring->reg_idx << 4;
9d5c8243
AK		 3490
3491 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
3492 context_desc->seqnum_seed = 0;
3493
3494 buffer_info->time_stamp = jiffies;
0e014cb1 3495 buffer_info->next_to_watch = i;
9d5c8243
AK		 3496 buffer_info->dma = 0;
3497 i++;
3498 if (i == tx_ring->count)
3499 i = 0;
3500
3501 tx_ring->next_to_use = i;
3502
3503 return true;
3504}
3505
85ad76b2
AD		 3506static inline bool igb_tx_csum_adv(struct igb_ring *tx_ring,
3507 struct sk_buff *skb, u32 tx_flags)
9d5c8243
AK		 3508{
3509 struct e1000_adv_tx_context_desc *context_desc;
80785298 3510 struct pci_dev *pdev = tx_ring->pdev;
9d5c8243
AK		 3511 struct igb_buffer *buffer_info;
3512 u32 info = 0, tu_cmd = 0;
80785298 3513 unsigned int i;
9d5c8243
AK		 3514
3515 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
3516 (tx_flags & IGB_TX_FLAGS_VLAN)) {
3517 i = tx_ring->next_to_use;
3518 buffer_info = &tx_ring->buffer_info[i];
3519 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3520
3521 if (tx_flags & IGB_TX_FLAGS_VLAN)
3522 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
cdfd01fc 3523
9d5c8243
AK		 3524 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3525 if (skb->ip_summed == CHECKSUM_PARTIAL)
3526 info |= skb_network_header_len(skb);
3527
3528 context_desc->vlan_macip_lens = cpu_to_le32(info);
3529
3530 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3531
3532 if (skb->ip_summed == CHECKSUM_PARTIAL) {
fa4a7ef3
AJ		 3533 __be16 protocol;
3534
3535 if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
3536 const struct vlan_ethhdr *vhdr =
3537 (const struct vlan_ethhdr*)skb->data;
3538
3539 protocol = vhdr->h_vlan_encapsulated_proto;
3540 } else {
3541 protocol = skb->protocol;
3542 }
3543
3544 switch (protocol) {
09640e63 3545 case cpu_to_be16(ETH_P_IP):
9d5c8243 3546 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
44b0cda3
MW		 3547 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
3548 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
b9473560
JB		 3549 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
3550 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
44b0cda3 3551 break;
09640e63 3552 case cpu_to_be16(ETH_P_IPV6):
44b0cda3
MW		 3553 /* XXX what about other V6 headers?? */
3554 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
3555 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
b9473560
JB		 3556 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
3557 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
44b0cda3
MW		 3558 break;
3559 default:
3560 if (unlikely(net_ratelimit()))
80785298 3561 dev_warn(&pdev->dev,
44b0cda3
MW		 3562 "partial checksum but proto=%x!\n",
3563 skb->protocol);
3564 break;
3565 }
9d5c8243
AK		 3566 }
3567
3568 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3569 context_desc->seqnum_seed = 0;
85ad76b2 3570 if (tx_ring->flags & IGB_RING_FLAG_TX_CTX_IDX)
7dfc16fa 3571 context_desc->mss_l4len_idx =
85ad76b2 3572 cpu_to_le32(tx_ring->reg_idx << 4);
9d5c8243
AK		 3573
3574 buffer_info->time_stamp = jiffies;
0e014cb1 3575 buffer_info->next_to_watch = i;
9d5c8243
AK		 3576 buffer_info->dma = 0;
3577
3578 i++;
3579 if (i == tx_ring->count)
3580 i = 0;
3581 tx_ring->next_to_use = i;
3582
3583 return true;
3584 }
9d5c8243
AK		 3585 return false;
3586}
3587
3588#define IGB_MAX_TXD_PWR 16
3589#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
3590
80785298 3591static inline int igb_tx_map_adv(struct igb_ring *tx_ring, struct sk_buff *skb,
0e014cb1 3592 unsigned int first)
9d5c8243
AK		 3593{
3594 struct igb_buffer *buffer_info;
80785298 3595 struct pci_dev *pdev = tx_ring->pdev;
9d5c8243
AK		 3596 unsigned int len = skb_headlen(skb);
3597 unsigned int count = 0, i;
3598 unsigned int f;
3599
3600 i = tx_ring->next_to_use;
3601
3602 buffer_info = &tx_ring->buffer_info[i];
3603 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3604 buffer_info->length = len;
3605 /* set time_stamp *before* dma to help avoid a possible race */
3606 buffer_info->time_stamp = jiffies;
0e014cb1 3607 buffer_info->next_to_watch = i;
6366ad33
AD		 3608 buffer_info->dma = pci_map_single(pdev, skb->data, len,
3609 PCI_DMA_TODEVICE);
3610 if (pci_dma_mapping_error(pdev, buffer_info->dma))
3611 goto dma_error;
9d5c8243
AK		 3612
3613 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
3614 struct skb_frag_struct *frag;
3615
8581145f 3616 count++;
65689fef
AD		 3617 i++;
3618 if (i == tx_ring->count)
3619 i = 0;
3620
9d5c8243
AK		 3621 frag = &skb_shinfo(skb)->frags[f];
3622 len = frag->size;
3623
3624 buffer_info = &tx_ring->buffer_info[i];
3625 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3626 buffer_info->length = len;
3627 buffer_info->time_stamp = jiffies;
0e014cb1 3628 buffer_info->next_to_watch = i;
6366ad33
AD		 3629 buffer_info->mapped_as_page = true;
3630 buffer_info->dma = pci_map_page(pdev,
3631 frag->page,
3632 frag->page_offset,
3633 len,
3634 PCI_DMA_TODEVICE);
3635 if (pci_dma_mapping_error(pdev, buffer_info->dma))
3636 goto dma_error;
3637
9d5c8243
AK		 3638 }
3639
9d5c8243 3640 tx_ring->buffer_info[i].skb = skb;
0e014cb1 3641 tx_ring->buffer_info[first].next_to_watch = i;
9d5c8243 3642
cdfd01fc 3643 return ++count;
6366ad33
AD		 3644
3645dma_error:
3646 dev_err(&pdev->dev, "TX DMA map failed\n");
3647
3648 /* clear timestamp and dma mappings for failed buffer_info mapping */
3649 buffer_info->dma = 0;
3650 buffer_info->time_stamp = 0;
3651 buffer_info->length = 0;
3652 buffer_info->next_to_watch = 0;
3653 buffer_info->mapped_as_page = false;
3654 count--;
3655
3656 /* clear timestamp and dma mappings for remaining portion of packet */
3657 while (count >= 0) {
3658 count--;
3659 i--;
3660 if (i < 0)
3661 i += tx_ring->count;
3662 buffer_info = &tx_ring->buffer_info[i];
3663 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
3664 }
3665
3666 return 0;
9d5c8243
AK		 3667}
3668
85ad76b2 3669static inline void igb_tx_queue_adv(struct igb_ring *tx_ring,
9d5c8243
AK		 3670 int tx_flags, int count, u32 paylen,
3671 u8 hdr_len)
3672{
cdfd01fc 3673 union e1000_adv_tx_desc *tx_desc;
9d5c8243
AK		 3674 struct igb_buffer *buffer_info;
3675 u32 olinfo_status = 0, cmd_type_len;
cdfd01fc 3676 unsigned int i = tx_ring->next_to_use;
9d5c8243
AK		 3677
3678 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
3679 E1000_ADVTXD_DCMD_DEXT);
3680
3681 if (tx_flags & IGB_TX_FLAGS_VLAN)
3682 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3683
33af6bcc
PO		 3684 if (tx_flags & IGB_TX_FLAGS_TSTAMP)
3685 cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP;
3686
9d5c8243
AK		 3687 if (tx_flags & IGB_TX_FLAGS_TSO) {
3688 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3689
3690 /* insert tcp checksum */
3691 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3692
3693 /* insert ip checksum */
3694 if (tx_flags & IGB_TX_FLAGS_IPV4)
3695 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3696
3697 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
3698 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3699 }
3700
85ad76b2
AD		 3701 if ((tx_ring->flags & IGB_RING_FLAG_TX_CTX_IDX) &&
3702 (tx_flags & (IGB_TX_FLAGS_CSUM |
3703 IGB_TX_FLAGS_TSO |
7dfc16fa 3704 IGB_TX_FLAGS_VLAN)))
85ad76b2 3705 olinfo_status |= tx_ring->reg_idx << 4;
9d5c8243
AK		 3706
3707 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
3708
cdfd01fc 3709 do {
9d5c8243
AK		 3710 buffer_info = &tx_ring->buffer_info[i];
3711 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
3712 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
3713 tx_desc->read.cmd_type_len =
3714 cpu_to_le32(cmd_type_len | buffer_info->length);
3715 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
cdfd01fc 3716 count--;
9d5c8243
AK		 3717 i++;
3718 if (i == tx_ring->count)
3719 i = 0;
cdfd01fc 3720 } while (count > 0);
9d5c8243 3721
85ad76b2 3722 tx_desc->read.cmd_type_len |= cpu_to_le32(IGB_ADVTXD_DCMD);
9d5c8243
AK		 3723 /* Force memory writes to complete before letting h/w
3724 * know there are new descriptors to fetch. (Only
3725 * applicable for weak-ordered memory model archs,
3726 * such as IA-64). */
3727 wmb();
3728
3729 tx_ring->next_to_use = i;
fce99e34 3730 writel(i, tx_ring->tail);
9d5c8243
AK		 3731 /* we need this if more than one processor can write to our tail
3732 * at a time, it syncronizes IO on IA64/Altix systems */
3733 mmiowb();
3734}
3735
e694e964 3736static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, int size)
9d5c8243 3737{
e694e964
AD		 3738 struct net_device *netdev = tx_ring->netdev;
3739
661086df 3740 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 3741
9d5c8243
AK		 3742 /* Herbert's original patch had:
3743 * smp_mb__after_netif_stop_queue();
3744 * but since that doesn't exist yet, just open code it. */
3745 smp_mb();
3746
3747 /* We need to check again in a case another CPU has just
3748 * made room available. */
c493ea45 3749 if (igb_desc_unused(tx_ring) < size)
9d5c8243
AK		 3750 return -EBUSY;
3751
3752 /* A reprieve! */
661086df 3753 netif_wake_subqueue(netdev, tx_ring->queue_index);
04a5fcaa 3754 tx_ring->tx_stats.restart_queue++;
9d5c8243
AK		 3755 return 0;
3756}
3757
e694e964 3758static int igb_maybe_stop_tx(struct igb_ring *tx_ring, int size)
9d5c8243 3759{
c493ea45 3760 if (igb_desc_unused(tx_ring) >= size)
9d5c8243 3761 return 0;
e694e964 3762 return __igb_maybe_stop_tx(tx_ring, size);
9d5c8243
AK		 3763}
3764
b1a436c3
AD		 3765netdev_tx_t igb_xmit_frame_ring_adv(struct sk_buff *skb,
3766 struct igb_ring *tx_ring)
9d5c8243 3767{
e694e964 3768 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
0e014cb1 3769 unsigned int first;
9d5c8243 3770 unsigned int tx_flags = 0;
9d5c8243 3771 u8 hdr_len = 0;
cdfd01fc 3772 int tso = 0, count;
c5b9bd5e 3773 union skb_shared_tx *shtx = skb_tx(skb);
9d5c8243 3774
9d5c8243
AK		 3775 /* need: 1 descriptor per page,
3776 * + 2 desc gap to keep tail from touching head,
3777 * + 1 desc for skb->data,
3778 * + 1 desc for context descriptor,
3779 * otherwise try next time */
e694e964 3780 if (igb_maybe_stop_tx(tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
9d5c8243 3781 /* this is a hard error */
9d5c8243
AK		 3782 return NETDEV_TX_BUSY;
3783 }
33af6bcc 3784
33af6bcc
PO		 3785 if (unlikely(shtx->hardware)) {
3786 shtx->in_progress = 1;
3787 tx_flags |= IGB_TX_FLAGS_TSTAMP;
33af6bcc 3788 }
9d5c8243 3789
cdfd01fc 3790 if (vlan_tx_tag_present(skb) && adapter->vlgrp) {
9d5c8243
AK		 3791 tx_flags |= IGB_TX_FLAGS_VLAN;
3792 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
3793 }
3794
661086df
PWJ		 3795 if (skb->protocol == htons(ETH_P_IP))
3796 tx_flags |= IGB_TX_FLAGS_IPV4;
3797
0e014cb1 3798 first = tx_ring->next_to_use;
85ad76b2
AD		 3799 if (skb_is_gso(skb)) {
3800 tso = igb_tso_adv(tx_ring, skb, tx_flags, &hdr_len);
cdfd01fc 3801
85ad76b2
AD		 3802 if (tso < 0) {
3803 dev_kfree_skb_any(skb);
3804 return NETDEV_TX_OK;
3805 }
9d5c8243
AK		 3806 }
3807
3808 if (tso)
3809 tx_flags |= IGB_TX_FLAGS_TSO;
85ad76b2 3810 else if (igb_tx_csum_adv(tx_ring, skb, tx_flags) &&
bc1cbd34
AD		 3811 (skb->ip_summed == CHECKSUM_PARTIAL))
3812 tx_flags |= IGB_TX_FLAGS_CSUM;
9d5c8243 3813
65689fef 3814 /*
cdfd01fc 3815 * count reflects descriptors mapped, if 0 or less then mapping error
65689fef
AD		 3816 * has occured and we need to rewind the descriptor queue
3817 */
80785298 3818 count = igb_tx_map_adv(tx_ring, skb, first);
6366ad33 3819 if (!count) {
65689fef
AD		 3820 dev_kfree_skb_any(skb);
3821 tx_ring->buffer_info[first].time_stamp = 0;
3822 tx_ring->next_to_use = first;
85ad76b2 3823 return NETDEV_TX_OK;
65689fef 3824 }
9d5c8243 3825
85ad76b2
AD		 3826 igb_tx_queue_adv(tx_ring, tx_flags, count, skb->len, hdr_len);
3827
3828 /* Make sure there is space in the ring for the next send. */
e694e964 3829 igb_maybe_stop_tx(tx_ring, MAX_SKB_FRAGS + 4);
85ad76b2 3830
9d5c8243
AK		 3831 return NETDEV_TX_OK;
3832}
3833
3b29a56d
SH		 3834static netdev_tx_t igb_xmit_frame_adv(struct sk_buff *skb,
3835 struct net_device *netdev)
9d5c8243
AK		 3836{
3837 struct igb_adapter *adapter = netdev_priv(netdev);
661086df 3838 struct igb_ring *tx_ring;
661086df 3839 int r_idx = 0;
b1a436c3
AD		 3840
3841 if (test_bit(__IGB_DOWN, &adapter->state)) {
3842 dev_kfree_skb_any(skb);
3843 return NETDEV_TX_OK;
3844 }
3845
3846 if (skb->len <= 0) {
3847 dev_kfree_skb_any(skb);
3848 return NETDEV_TX_OK;
3849 }
3850
1bfaf07b 3851 r_idx = skb->queue_mapping & (IGB_ABS_MAX_TX_QUEUES - 1);
661086df 3852 tx_ring = adapter->multi_tx_table[r_idx];
9d5c8243
AK		 3853
3854 /* This goes back to the question of how to logically map a tx queue
3855 * to a flow. Right now, performance is impacted slightly negatively
3856 * if using multiple tx queues. If the stack breaks away from a
3857 * single qdisc implementation, we can look at this again. */
e694e964 3858 return igb_xmit_frame_ring_adv(skb, tx_ring);
9d5c8243
AK		 3859}
3860
3861/**
3862 * igb_tx_timeout - Respond to a Tx Hang
3863 * @netdev: network interface device structure
3864 **/
3865static void igb_tx_timeout(struct net_device *netdev)
3866{
3867 struct igb_adapter *adapter = netdev_priv(netdev);
3868 struct e1000_hw *hw = &adapter->hw;
3869
3870 /* Do the reset outside of interrupt context */
3871 adapter->tx_timeout_count++;
f7ba205e 3872
55cac248
AD		 3873 if (hw->mac.type == e1000_82580)
3874 hw->dev_spec._82575.global_device_reset = true;
3875
9d5c8243 3876 schedule_work(&adapter->reset_task);
265de409
AD		 3877 wr32(E1000_EICS,
3878 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 3879}
3880
3881static void igb_reset_task(struct work_struct *work)
3882{
3883 struct igb_adapter *adapter;
3884 adapter = container_of(work, struct igb_adapter, reset_task);
3885
3886 igb_reinit_locked(adapter);
3887}
3888
3889/**
3890 * igb_get_stats - Get System Network Statistics
3891 * @netdev: network interface device structure
3892 *
3893 * Returns the address of the device statistics structure.
3894 * The statistics are actually updated from the timer callback.
3895 **/
73cd78f1 3896static struct net_device_stats *igb_get_stats(struct net_device *netdev)
9d5c8243 3897{
9d5c8243 3898 /* only return the current stats */
8d24e933 3899 return &netdev->stats;
9d5c8243
AK		 3900}
3901
3902/**
3903 * igb_change_mtu - Change the Maximum Transfer Unit
3904 * @netdev: network interface device structure
3905 * @new_mtu: new value for maximum frame size
3906 *
3907 * Returns 0 on success, negative on failure
3908 **/
3909static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3910{
3911 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 3912 struct pci_dev *pdev = adapter->pdev;
9d5c8243 3913 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4c844851 3914 u32 rx_buffer_len, i;
9d5c8243 3915
c809d227 3916 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
090b1795 3917 dev_err(&pdev->dev, "Invalid MTU setting\n");
9d5c8243
AK		 3918 return -EINVAL;
3919 }
3920
9d5c8243 3921 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
090b1795 3922 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
9d5c8243
AK		 3923 return -EINVAL;
3924 }
3925
3926 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3927 msleep(1);
73cd78f1 3928
9d5c8243
AK		 3929 /* igb_down has a dependency on max_frame_size */
3930 adapter->max_frame_size = max_frame;
559e9c49 3931
9d5c8243
AK		 3932 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3933 * means we reserve 2 more, this pushes us to allocate from the next
3934 * larger slab size.
3935 * i.e. RXBUFFER_2048 --> size-4096 slab
3936 */
3937
7d95b717 3938 if (max_frame <= IGB_RXBUFFER_1024)
4c844851 3939 rx_buffer_len = IGB_RXBUFFER_1024;
6ec43fe6 3940 else if (max_frame <= MAXIMUM_ETHERNET_VLAN_SIZE)
4c844851 3941 rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
6ec43fe6 3942 else
4c844851
AD		 3943 rx_buffer_len = IGB_RXBUFFER_128;
3944
3945 if (netif_running(netdev))
3946 igb_down(adapter);
9d5c8243 3947
090b1795 3948 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
9d5c8243
AK		 3949 netdev->mtu, new_mtu);
3950 netdev->mtu = new_mtu;
3951
4c844851 3952 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3953 adapter->rx_ring[i]->rx_buffer_len = rx_buffer_len;
4c844851 3954
9d5c8243
AK		 3955 if (netif_running(netdev))
3956 igb_up(adapter);
3957 else
3958 igb_reset(adapter);
3959
3960 clear_bit(__IGB_RESETTING, &adapter->state);
3961
3962 return 0;
3963}
3964
3965/**
3966 * igb_update_stats - Update the board statistics counters
3967 * @adapter: board private structure
3968 **/
3969
3970void igb_update_stats(struct igb_adapter *adapter)
3971{
128e45eb 3972 struct net_device_stats *net_stats = igb_get_stats(adapter->netdev);
9d5c8243
AK		 3973 struct e1000_hw *hw = &adapter->hw;
3974 struct pci_dev *pdev = adapter->pdev;
3f9c0164 3975 u32 rnbc;
9d5c8243 3976 u16 phy_tmp;
3f9c0164
AD		 3977 int i;
3978 u64 bytes, packets;
9d5c8243
AK		 3979
3980#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3981
3982 /*
3983 * Prevent stats update while adapter is being reset, or if the pci
3984 * connection is down.
3985 */
3986 if (adapter->link_speed == 0)
3987 return;
3988 if (pci_channel_offline(pdev))
3989 return;
3990
3f9c0164
AD		 3991 bytes = 0;
3992 packets = 0;
3993 for (i = 0; i < adapter->num_rx_queues; i++) {
3994 u32 rqdpc_tmp = rd32(E1000_RQDPC(i)) & 0x0FFF;
3025a446
AD		 3995 struct igb_ring *ring = adapter->rx_ring[i];
3996 ring->rx_stats.drops += rqdpc_tmp;
128e45eb 3997 net_stats->rx_fifo_errors += rqdpc_tmp;
3025a446
AD		 3998 bytes += ring->rx_stats.bytes;
3999 packets += ring->rx_stats.packets;
3f9c0164
AD		 4000 }
4001
128e45eb
AD		 4002 net_stats->rx_bytes = bytes;
4003 net_stats->rx_packets = packets;
3f9c0164
AD		 4004
4005 bytes = 0;
4006 packets = 0;
4007 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446
AD		 4008 struct igb_ring *ring = adapter->tx_ring[i];
4009 bytes += ring->tx_stats.bytes;
4010 packets += ring->tx_stats.packets;
3f9c0164 4011 }
128e45eb
AD		 4012 net_stats->tx_bytes = bytes;
4013 net_stats->tx_packets = packets;
3f9c0164
AD		 4014
4015 /* read stats registers */
9d5c8243
AK		 4016 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
4017 adapter->stats.gprc += rd32(E1000_GPRC);
4018 adapter->stats.gorc += rd32(E1000_GORCL);
4019 rd32(E1000_GORCH); /* clear GORCL */
4020 adapter->stats.bprc += rd32(E1000_BPRC);
4021 adapter->stats.mprc += rd32(E1000_MPRC);
4022 adapter->stats.roc += rd32(E1000_ROC);
4023
4024 adapter->stats.prc64 += rd32(E1000_PRC64);
4025 adapter->stats.prc127 += rd32(E1000_PRC127);
4026 adapter->stats.prc255 += rd32(E1000_PRC255);
4027 adapter->stats.prc511 += rd32(E1000_PRC511);
4028 adapter->stats.prc1023 += rd32(E1000_PRC1023);
4029 adapter->stats.prc1522 += rd32(E1000_PRC1522);
4030 adapter->stats.symerrs += rd32(E1000_SYMERRS);
4031 adapter->stats.sec += rd32(E1000_SEC);
4032
4033 adapter->stats.mpc += rd32(E1000_MPC);
4034 adapter->stats.scc += rd32(E1000_SCC);
4035 adapter->stats.ecol += rd32(E1000_ECOL);
4036 adapter->stats.mcc += rd32(E1000_MCC);
4037 adapter->stats.latecol += rd32(E1000_LATECOL);
4038 adapter->stats.dc += rd32(E1000_DC);
4039 adapter->stats.rlec += rd32(E1000_RLEC);
4040 adapter->stats.xonrxc += rd32(E1000_XONRXC);
4041 adapter->stats.xontxc += rd32(E1000_XONTXC);
4042 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
4043 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
4044 adapter->stats.fcruc += rd32(E1000_FCRUC);
4045 adapter->stats.gptc += rd32(E1000_GPTC);
4046 adapter->stats.gotc += rd32(E1000_GOTCL);
4047 rd32(E1000_GOTCH); /* clear GOTCL */
3f9c0164
AD		 4048 rnbc = rd32(E1000_RNBC);
4049 adapter->stats.rnbc += rnbc;
128e45eb 4050 net_stats->rx_fifo_errors += rnbc;
9d5c8243
AK		 4051 adapter->stats.ruc += rd32(E1000_RUC);
4052 adapter->stats.rfc += rd32(E1000_RFC);
4053 adapter->stats.rjc += rd32(E1000_RJC);
4054 adapter->stats.tor += rd32(E1000_TORH);
4055 adapter->stats.tot += rd32(E1000_TOTH);
4056 adapter->stats.tpr += rd32(E1000_TPR);
4057
4058 adapter->stats.ptc64 += rd32(E1000_PTC64);
4059 adapter->stats.ptc127 += rd32(E1000_PTC127);
4060 adapter->stats.ptc255 += rd32(E1000_PTC255);
4061 adapter->stats.ptc511 += rd32(E1000_PTC511);
4062 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
4063 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
4064
4065 adapter->stats.mptc += rd32(E1000_MPTC);
4066 adapter->stats.bptc += rd32(E1000_BPTC);
4067
2d0b0f69
NN		 4068 adapter->stats.tpt += rd32(E1000_TPT);
4069 adapter->stats.colc += rd32(E1000_COLC);
9d5c8243
AK		 4070
4071 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
4072 adapter->stats.rxerrc += rd32(E1000_RXERRC);
4073 adapter->stats.tncrs += rd32(E1000_TNCRS);
4074 adapter->stats.tsctc += rd32(E1000_TSCTC);
4075 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
4076
4077 adapter->stats.iac += rd32(E1000_IAC);
4078 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
4079 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
4080 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
4081 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
4082 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
4083 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
4084 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
4085 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
4086
4087 /* Fill out the OS statistics structure */
128e45eb
AD		 4088 net_stats->multicast = adapter->stats.mprc;
4089 net_stats->collisions = adapter->stats.colc;
9d5c8243
AK		 4090
4091 /* Rx Errors */
4092
4093 /* RLEC on some newer hardware can be incorrect so build
8c0ab70a 4094 * our own version based on RUC and ROC */
128e45eb 4095 net_stats->rx_errors = adapter->stats.rxerrc +
9d5c8243
AK		 4096 adapter->stats.crcerrs + adapter->stats.algnerrc +
4097 adapter->stats.ruc + adapter->stats.roc +
4098 adapter->stats.cexterr;
128e45eb
AD		 4099 net_stats->rx_length_errors = adapter->stats.ruc +
4100 adapter->stats.roc;
4101 net_stats->rx_crc_errors = adapter->stats.crcerrs;
4102 net_stats->rx_frame_errors = adapter->stats.algnerrc;
4103 net_stats->rx_missed_errors = adapter->stats.mpc;
9d5c8243
AK		 4104
4105 /* Tx Errors */
128e45eb
AD		 4106 net_stats->tx_errors = adapter->stats.ecol +
4107 adapter->stats.latecol;
4108 net_stats->tx_aborted_errors = adapter->stats.ecol;
4109 net_stats->tx_window_errors = adapter->stats.latecol;
4110 net_stats->tx_carrier_errors = adapter->stats.tncrs;
9d5c8243
AK		 4111
4112 /* Tx Dropped needs to be maintained elsewhere */
4113
4114 /* Phy Stats */
4115 if (hw->phy.media_type == e1000_media_type_copper) {
4116 if ((adapter->link_speed == SPEED_1000) &&
73cd78f1 4117 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
9d5c8243
AK		 4118 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
4119 adapter->phy_stats.idle_errors += phy_tmp;
4120 }
4121 }
4122
4123 /* Management Stats */
4124 adapter->stats.mgptc += rd32(E1000_MGTPTC);
4125 adapter->stats.mgprc += rd32(E1000_MGTPRC);
4126 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
4127}
4128
9d5c8243
AK		 4129static irqreturn_t igb_msix_other(int irq, void *data)
4130{
047e0030 4131 struct igb_adapter *adapter = data;
9d5c8243 4132 struct e1000_hw *hw = &adapter->hw;
844290e5 4133 u32 icr = rd32(E1000_ICR);
844290e5 4134 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083 4135
7f081d40
AD		 4136 if (icr & E1000_ICR_DRSTA)
4137 schedule_work(&adapter->reset_task);
4138
047e0030 4139 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 4140 /* HW is reporting DMA is out of sync */
4141 adapter->stats.doosync++;
4142 }
eebbbdba 4143
4ae196df
AD		 4144 /* Check for a mailbox event */
4145 if (icr & E1000_ICR_VMMB)
4146 igb_msg_task(adapter);
4147
4148 if (icr & E1000_ICR_LSC) {
4149 hw->mac.get_link_status = 1;
4150 /* guard against interrupt when we're going down */
4151 if (!test_bit(__IGB_DOWN, &adapter->state))
4152 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4153 }
4154
25568a53
AD		 4155 if (adapter->vfs_allocated_count)
4156 wr32(E1000_IMS, E1000_IMS_LSC |
4157 E1000_IMS_VMMB |
4158 E1000_IMS_DOUTSYNC);
4159 else
4160 wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC);
844290e5 4161 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 4162
4163 return IRQ_HANDLED;
4164}
4165
047e0030 4166static void igb_write_itr(struct igb_q_vector *q_vector)
9d5c8243 4167{
26b39276 4168 struct igb_adapter *adapter = q_vector->adapter;
047e0030 4169 u32 itr_val = q_vector->itr_val & 0x7FFC;
9d5c8243 4170
047e0030
AD		 4171 if (!q_vector->set_itr)
4172 return;
73cd78f1 4173
047e0030
AD		 4174 if (!itr_val)
4175 itr_val = 0x4;
661086df 4176
26b39276
AD		 4177 if (adapter->hw.mac.type == e1000_82575)
4178 itr_val |= itr_val << 16;
661086df 4179 else
047e0030 4180 itr_val |= 0x8000000;
661086df 4181
047e0030
AD		 4182 writel(itr_val, q_vector->itr_register);
4183 q_vector->set_itr = 0;
6eb5a7f1
AD		 4184}
4185
047e0030 4186static irqreturn_t igb_msix_ring(int irq, void *data)
9d5c8243 4187{
047e0030 4188 struct igb_q_vector *q_vector = data;
9d5c8243 4189
047e0030
AD		 4190 /* Write the ITR value calculated from the previous interrupt. */
4191 igb_write_itr(q_vector);
9d5c8243 4192
047e0030 4193 napi_schedule(&q_vector->napi);
844290e5 4194
047e0030 4195 return IRQ_HANDLED;
fe4506b6
JC		 4196}
4197
421e02f0 4198#ifdef CONFIG_IGB_DCA
047e0030 4199static void igb_update_dca(struct igb_q_vector *q_vector)
fe4506b6 4200{
047e0030 4201 struct igb_adapter *adapter = q_vector->adapter;
fe4506b6
JC		 4202 struct e1000_hw *hw = &adapter->hw;
4203 int cpu = get_cpu();
fe4506b6 4204
047e0030
AD		 4205 if (q_vector->cpu == cpu)
4206 goto out_no_update;
4207
4208 if (q_vector->tx_ring) {
4209 int q = q_vector->tx_ring->reg_idx;
4210 u32 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
4211 if (hw->mac.type == e1000_82575) {
4212 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
4213 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
2d064c06 4214 } else {
047e0030
AD		 4215 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
4216 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
4217 E1000_DCA_TXCTRL_CPUID_SHIFT;
4218 }
4219 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
4220 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
4221 }
4222 if (q_vector->rx_ring) {
4223 int q = q_vector->rx_ring->reg_idx;
4224 u32 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
4225 if (hw->mac.type == e1000_82575) {
2d064c06 4226 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
92be7917 4227 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
047e0030
AD		 4228 } else {
4229 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
4230 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
4231 E1000_DCA_RXCTRL_CPUID_SHIFT;
2d064c06 4232 }
fe4506b6
JC		 4233 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
4234 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
4235 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
4236 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
fe4506b6 4237 }
047e0030
AD		 4238 q_vector->cpu = cpu;
4239out_no_update:
fe4506b6
JC		 4240 put_cpu();
4241}
4242
4243static void igb_setup_dca(struct igb_adapter *adapter)
4244{
7e0e99ef 4245 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 4246 int i;
4247
7dfc16fa 4248 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 4249 return;
4250
7e0e99ef
AD		 4251 /* Always use CB2 mode, difference is masked in the CB driver. */
4252 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
4253
047e0030 4254 for (i = 0; i < adapter->num_q_vectors; i++) {
26b39276
AD		 4255 adapter->q_vector[i]->cpu = -1;
4256 igb_update_dca(adapter->q_vector[i]);
fe4506b6
JC		 4257 }
4258}
4259
4260static int __igb_notify_dca(struct device *dev, void *data)
4261{
4262 struct net_device *netdev = dev_get_drvdata(dev);
4263 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 4264 struct pci_dev *pdev = adapter->pdev;
fe4506b6
JC		 4265 struct e1000_hw *hw = &adapter->hw;
4266 unsigned long event = *(unsigned long *)data;
4267
4268 switch (event) {
4269 case DCA_PROVIDER_ADD:
4270 /* if already enabled, don't do it again */
7dfc16fa 4271 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 4272 break;
fe4506b6 4273 if (dca_add_requester(dev) == 0) {
bbd98fe4 4274 adapter->flags |= IGB_FLAG_DCA_ENABLED;
090b1795 4275 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 4276 igb_setup_dca(adapter);
4277 break;
4278 }
4279 /* Fall Through since DCA is disabled. */
4280 case DCA_PROVIDER_REMOVE:
7dfc16fa 4281 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6 4282 /* without this a class_device is left
047e0030 4283 * hanging around in the sysfs model */
fe4506b6 4284 dca_remove_requester(dev);
090b1795 4285 dev_info(&pdev->dev, "DCA disabled\n");
7dfc16fa 4286 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 4287 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 4288 }
4289 break;
4290 }
bbd98fe4 4291
fe4506b6 4292 return 0;
9d5c8243
AK		 4293}
4294
fe4506b6
JC		 4295static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
4296 void *p)
4297{
4298 int ret_val;
4299
4300 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
4301 __igb_notify_dca);
4302
4303 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
4304}
421e02f0 4305#endif /* CONFIG_IGB_DCA */
9d5c8243 4306
4ae196df
AD		 4307static void igb_ping_all_vfs(struct igb_adapter *adapter)
4308{
4309 struct e1000_hw *hw = &adapter->hw;
4310 u32 ping;
4311 int i;
4312
4313 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
4314 ping = E1000_PF_CONTROL_MSG;
f2ca0dbe 4315 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
4ae196df
AD		 4316 ping |= E1000_VT_MSGTYPE_CTS;
4317 igb_write_mbx(hw, &ping, 1, i);
4318 }
4319}
4320
7d5753f0
AD		 4321static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
4322{
4323 struct e1000_hw *hw = &adapter->hw;
4324 u32 vmolr = rd32(E1000_VMOLR(vf));
4325 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4326
4327 vf_data->flags |= ~(IGB_VF_FLAG_UNI_PROMISC |
4328 IGB_VF_FLAG_MULTI_PROMISC);
4329 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
4330
4331 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
4332 vmolr |= E1000_VMOLR_MPME;
4333 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
4334 } else {
4335 /*
4336 * if we have hashes and we are clearing a multicast promisc
4337 * flag we need to write the hashes to the MTA as this step
4338 * was previously skipped
4339 */
4340 if (vf_data->num_vf_mc_hashes > 30) {
4341 vmolr |= E1000_VMOLR_MPME;
4342 } else if (vf_data->num_vf_mc_hashes) {
4343 int j;
4344 vmolr |= E1000_VMOLR_ROMPE;
4345 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
4346 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
4347 }
4348 }
4349
4350 wr32(E1000_VMOLR(vf), vmolr);
4351
4352 /* there are flags left unprocessed, likely not supported */
4353 if (*msgbuf & E1000_VT_MSGINFO_MASK)
4354 return -EINVAL;
4355
4356 return 0;
4357
4358}
4359
4ae196df
AD		 4360static int igb_set_vf_multicasts(struct igb_adapter *adapter,
4361 u32 *msgbuf, u32 vf)
4362{
4363 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
4364 u16 *hash_list = (u16 *)&msgbuf[1];
4365 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4366 int i;
4367
7d5753f0 4368 /* salt away the number of multicast addresses assigned
4ae196df
AD		 4369 * to this VF for later use to restore when the PF multi cast
4370 * list changes
4371 */
4372 vf_data->num_vf_mc_hashes = n;
4373
7d5753f0
AD		 4374 /* only up to 30 hash values supported */
4375 if (n > 30)
4376 n = 30;
4377
4378 /* store the hashes for later use */
4ae196df 4379 for (i = 0; i < n; i++)
a419aef8 4380 vf_data->vf_mc_hashes[i] = hash_list[i];
4ae196df
AD		 4381
4382 /* Flush and reset the mta with the new values */
ff41f8dc 4383 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 4384
4385 return 0;
4386}
4387
4388static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
4389{
4390 struct e1000_hw *hw = &adapter->hw;
4391 struct vf_data_storage *vf_data;
4392 int i, j;
4393
4394 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7d5753f0
AD		 4395 u32 vmolr = rd32(E1000_VMOLR(i));
4396 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
4397
4ae196df 4398 vf_data = &adapter->vf_data[i];
7d5753f0
AD		 4399
4400 if ((vf_data->num_vf_mc_hashes > 30) ||
4401 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
4402 vmolr |= E1000_VMOLR_MPME;
4403 } else if (vf_data->num_vf_mc_hashes) {
4404 vmolr |= E1000_VMOLR_ROMPE;
4405 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
4406 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
4407 }
4408 wr32(E1000_VMOLR(i), vmolr);
4ae196df
AD		 4409 }
4410}
4411
4412static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
4413{
4414 struct e1000_hw *hw = &adapter->hw;
4415 u32 pool_mask, reg, vid;
4416 int i;
4417
4418 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
4419
4420 /* Find the vlan filter for this id */
4421 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4422 reg = rd32(E1000_VLVF(i));
4423
4424 /* remove the vf from the pool */
4425 reg &= ~pool_mask;
4426
4427 /* if pool is empty then remove entry from vfta */
4428 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
4429 (reg & E1000_VLVF_VLANID_ENABLE)) {
4430 reg = 0;
4431 vid = reg & E1000_VLVF_VLANID_MASK;
4432 igb_vfta_set(hw, vid, false);
4433 }
4434
4435 wr32(E1000_VLVF(i), reg);
4436 }
ae641bdc
AD		 4437
4438 adapter->vf_data[vf].vlans_enabled = 0;
4ae196df
AD		 4439}
4440
4441static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
4442{
4443 struct e1000_hw *hw = &adapter->hw;
4444 u32 reg, i;
4445
51466239
AD		 4446 /* The vlvf table only exists on 82576 hardware and newer */
4447 if (hw->mac.type < e1000_82576)
4448 return -1;
4449
4450 /* we only need to do this if VMDq is enabled */
4ae196df
AD		 4451 if (!adapter->vfs_allocated_count)
4452 return -1;
4453
4454 /* Find the vlan filter for this id */
4455 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4456 reg = rd32(E1000_VLVF(i));
4457 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
4458 vid == (reg & E1000_VLVF_VLANID_MASK))
4459 break;
4460 }
4461
4462 if (add) {
4463 if (i == E1000_VLVF_ARRAY_SIZE) {
4464 /* Did not find a matching VLAN ID entry that was
4465 * enabled. Search for a free filter entry, i.e.
4466 * one without the enable bit set
4467 */
4468 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4469 reg = rd32(E1000_VLVF(i));
4470 if (!(reg & E1000_VLVF_VLANID_ENABLE))
4471 break;
4472 }
4473 }
4474 if (i < E1000_VLVF_ARRAY_SIZE) {
4475 /* Found an enabled/available entry */
4476 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
4477
4478 /* if !enabled we need to set this up in vfta */
4479 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
51466239
AD		 4480 /* add VID to filter table */
4481 igb_vfta_set(hw, vid, true);
4ae196df
AD		 4482 reg |= E1000_VLVF_VLANID_ENABLE;
4483 }
cad6d05f
AD		 4484 reg &= ~E1000_VLVF_VLANID_MASK;
4485 reg |= vid;
4ae196df 4486 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 4487
4488 /* do not modify RLPML for PF devices */
4489 if (vf >= adapter->vfs_allocated_count)
4490 return 0;
4491
4492 if (!adapter->vf_data[vf].vlans_enabled) {
4493 u32 size;
4494 reg = rd32(E1000_VMOLR(vf));
4495 size = reg & E1000_VMOLR_RLPML_MASK;
4496 size += 4;
4497 reg &= ~E1000_VMOLR_RLPML_MASK;
4498 reg |= size;
4499 wr32(E1000_VMOLR(vf), reg);
4500 }
ae641bdc 4501
51466239 4502 adapter->vf_data[vf].vlans_enabled++;
4ae196df
AD		 4503 return 0;
4504 }
4505 } else {
4506 if (i < E1000_VLVF_ARRAY_SIZE) {
4507 /* remove vf from the pool */
4508 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
4509 /* if pool is empty then remove entry from vfta */
4510 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
4511 reg = 0;
4512 igb_vfta_set(hw, vid, false);
4513 }
4514 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 4515
4516 /* do not modify RLPML for PF devices */
4517 if (vf >= adapter->vfs_allocated_count)
4518 return 0;
4519
4520 adapter->vf_data[vf].vlans_enabled--;
4521 if (!adapter->vf_data[vf].vlans_enabled) {
4522 u32 size;
4523 reg = rd32(E1000_VMOLR(vf));
4524 size = reg & E1000_VMOLR_RLPML_MASK;
4525 size -= 4;
4526 reg &= ~E1000_VMOLR_RLPML_MASK;
4527 reg |= size;
4528 wr32(E1000_VMOLR(vf), reg);
4529 }
4ae196df
AD		 4530 }
4531 }
8151d294
WM		 4532 return 0;
4533}
4534
4535static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
4536{
4537 struct e1000_hw *hw = &adapter->hw;
4538
4539 if (vid)
4540 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
4541 else
4542 wr32(E1000_VMVIR(vf), 0);
4543}
4544
4545static int igb_ndo_set_vf_vlan(struct net_device *netdev,
4546 int vf, u16 vlan, u8 qos)
4547{
4548 int err = 0;
4549 struct igb_adapter *adapter = netdev_priv(netdev);
4550
4551 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
4552 return -EINVAL;
4553 if (vlan || qos) {
4554 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
4555 if (err)
4556 goto out;
4557 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
4558 igb_set_vmolr(adapter, vf, !vlan);
4559 adapter->vf_data[vf].pf_vlan = vlan;
4560 adapter->vf_data[vf].pf_qos = qos;
4561 dev_info(&adapter->pdev->dev,
4562 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
4563 if (test_bit(__IGB_DOWN, &adapter->state)) {
4564 dev_warn(&adapter->pdev->dev,
4565 "The VF VLAN has been set,"
4566 " but the PF device is not up.\n");
4567 dev_warn(&adapter->pdev->dev,
4568 "Bring the PF device up before"
4569 " attempting to use the VF device.\n");
4570 }
4571 } else {
4572 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
4573 false, vf);
4574 igb_set_vmvir(adapter, vlan, vf);
4575 igb_set_vmolr(adapter, vf, true);
4576 adapter->vf_data[vf].pf_vlan = 0;
4577 adapter->vf_data[vf].pf_qos = 0;
4578 }
4579out:
4580 return err;
4ae196df
AD		 4581}
4582
4583static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
4584{
4585 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
4586 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
4587
4588 return igb_vlvf_set(adapter, vid, add, vf);
4589}
4590
f2ca0dbe 4591static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
4ae196df 4592{
8151d294
WM		 4593 /* clear flags */
4594 adapter->vf_data[vf].flags &= ~(IGB_VF_FLAG_PF_SET_MAC);
f2ca0dbe 4595 adapter->vf_data[vf].last_nack = jiffies;
4ae196df
AD		 4596
4597 /* reset offloads to defaults */
8151d294 4598 igb_set_vmolr(adapter, vf, true);
4ae196df
AD		 4599
4600 /* reset vlans for device */
4601 igb_clear_vf_vfta(adapter, vf);
8151d294
WM		 4602 if (adapter->vf_data[vf].pf_vlan)
4603 igb_ndo_set_vf_vlan(adapter->netdev, vf,
4604 adapter->vf_data[vf].pf_vlan,
4605 adapter->vf_data[vf].pf_qos);
4606 else
4607 igb_clear_vf_vfta(adapter, vf);
4ae196df
AD		 4608
4609 /* reset multicast table array for vf */
4610 adapter->vf_data[vf].num_vf_mc_hashes = 0;
4611
4612 /* Flush and reset the mta with the new values */
ff41f8dc 4613 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 4614}
4615
f2ca0dbe
AD		 4616static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
4617{
4618 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
4619
4620 /* generate a new mac address as we were hotplug removed/added */
8151d294
WM		 4621 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
4622 random_ether_addr(vf_mac);
f2ca0dbe
AD		 4623
4624 /* process remaining reset events */
4625 igb_vf_reset(adapter, vf);
4626}
4627
4628static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4ae196df
AD		 4629{
4630 struct e1000_hw *hw = &adapter->hw;
4631 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 4632 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 4633 u32 reg, msgbuf[3];
4634 u8 *addr = (u8 *)(&msgbuf[1]);
4635
4636 /* process all the same items cleared in a function level reset */
f2ca0dbe 4637 igb_vf_reset(adapter, vf);
4ae196df
AD		 4638
4639 /* set vf mac address */
26ad9178 4640 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4ae196df
AD		 4641
4642 /* enable transmit and receive for vf */
4643 reg = rd32(E1000_VFTE);
4644 wr32(E1000_VFTE, reg | (1 << vf));
4645 reg = rd32(E1000_VFRE);
4646 wr32(E1000_VFRE, reg | (1 << vf));
4647
f2ca0dbe 4648 adapter->vf_data[vf].flags = IGB_VF_FLAG_CTS;
4ae196df
AD		 4649
4650 /* reply to reset with ack and vf mac address */
4651 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
4652 memcpy(addr, vf_mac, 6);
4653 igb_write_mbx(hw, msgbuf, 3, vf);
4654}
4655
4656static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
4657{
f2ca0dbe
AD		 4658 unsigned char *addr = (char *)&msg[1];
4659 int err = -1;
4ae196df 4660
f2ca0dbe
AD		 4661 if (is_valid_ether_addr(addr))
4662 err = igb_set_vf_mac(adapter, vf, addr);
4ae196df 4663
f2ca0dbe 4664 return err;
4ae196df
AD		 4665}
4666
4667static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
4668{
4669 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 4670 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 4671 u32 msg = E1000_VT_MSGTYPE_NACK;
4672
4673 /* if device isn't clear to send it shouldn't be reading either */
f2ca0dbe
AD		 4674 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
4675 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
4ae196df 4676 igb_write_mbx(hw, &msg, 1, vf);
f2ca0dbe 4677 vf_data->last_nack = jiffies;
4ae196df
AD		 4678 }
4679}
4680
f2ca0dbe 4681static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4ae196df 4682{
f2ca0dbe
AD		 4683 struct pci_dev *pdev = adapter->pdev;
4684 u32 msgbuf[E1000_VFMAILBOX_SIZE];
4ae196df 4685 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 4686 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 4687 s32 retval;
4688
f2ca0dbe 4689 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
4ae196df 4690
fef45f4c
AD		 4691 if (retval) {
4692 /* if receive failed revoke VF CTS stats and restart init */
f2ca0dbe 4693 dev_err(&pdev->dev, "Error receiving message from VF\n");
fef45f4c
AD		 4694 vf_data->flags &= ~IGB_VF_FLAG_CTS;
4695 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
4696 return;
4697 goto out;
4698 }
4ae196df
AD		 4699
4700 /* this is a message we already processed, do nothing */
4701 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
f2ca0dbe 4702 return;
4ae196df
AD		 4703
4704 /*
4705 * until the vf completes a reset it should not be
4706 * allowed to start any configuration.
4707 */
4708
4709 if (msgbuf[0] == E1000_VF_RESET) {
4710 igb_vf_reset_msg(adapter, vf);
f2ca0dbe 4711 return;
4ae196df
AD		 4712 }
4713
f2ca0dbe 4714 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
fef45f4c
AD		 4715 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
4716 return;
4717 retval = -1;
4718 goto out;
4ae196df
AD		 4719 }
4720
4721 switch ((msgbuf[0] & 0xFFFF)) {
4722 case E1000_VF_SET_MAC_ADDR:
4723 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
4724 break;
7d5753f0
AD		 4725 case E1000_VF_SET_PROMISC:
4726 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
4727 break;
4ae196df
AD		 4728 case E1000_VF_SET_MULTICAST:
4729 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
4730 break;
4731 case E1000_VF_SET_LPE:
4732 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
4733 break;
4734 case E1000_VF_SET_VLAN:
8151d294
WM		 4735 if (adapter->vf_data[vf].pf_vlan)
4736 retval = -1;
4737 else
4738 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4ae196df
AD		 4739 break;
4740 default:
090b1795 4741 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4ae196df
AD		 4742 retval = -1;
4743 break;
4744 }
4745
fef45f4c
AD		 4746 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
4747out:
4ae196df
AD		 4748 /* notify the VF of the results of what it sent us */
4749 if (retval)
4750 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4751 else
4752 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
4753
4ae196df 4754 igb_write_mbx(hw, msgbuf, 1, vf);
f2ca0dbe 4755}
4ae196df 4756
f2ca0dbe
AD		 4757static void igb_msg_task(struct igb_adapter *adapter)
4758{
4759 struct e1000_hw *hw = &adapter->hw;
4760 u32 vf;
4761
4762 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
4763 /* process any reset requests */
4764 if (!igb_check_for_rst(hw, vf))
4765 igb_vf_reset_event(adapter, vf);
4766
4767 /* process any messages pending */
4768 if (!igb_check_for_msg(hw, vf))
4769 igb_rcv_msg_from_vf(adapter, vf);
4770
4771 /* process any acks */
4772 if (!igb_check_for_ack(hw, vf))
4773 igb_rcv_ack_from_vf(adapter, vf);
4774 }
4ae196df
AD		 4775}
4776
68d480c4
AD		 4777/**
4778 * igb_set_uta - Set unicast filter table address
4779 * @adapter: board private structure
4780 *
4781 * The unicast table address is a register array of 32-bit registers.
4782 * The table is meant to be used in a way similar to how the MTA is used
4783 * however due to certain limitations in the hardware it is necessary to
4784 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscous
4785 * enable bit to allow vlan tag stripping when promiscous mode is enabled
4786 **/
4787static void igb_set_uta(struct igb_adapter *adapter)
4788{
4789 struct e1000_hw *hw = &adapter->hw;
4790 int i;
4791
4792 /* The UTA table only exists on 82576 hardware and newer */
4793 if (hw->mac.type < e1000_82576)
4794 return;
4795
4796 /* we only need to do this if VMDq is enabled */
4797 if (!adapter->vfs_allocated_count)
4798 return;
4799
4800 for (i = 0; i < hw->mac.uta_reg_count; i++)
4801 array_wr32(E1000_UTA, i, ~0);
4802}
4803
9d5c8243
AK		 4804/**
4805 * igb_intr_msi - Interrupt Handler
4806 * @irq: interrupt number
4807 * @data: pointer to a network interface device structure
4808 **/
4809static irqreturn_t igb_intr_msi(int irq, void *data)
4810{
047e0030
AD		 4811 struct igb_adapter *adapter = data;
4812 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 4813 struct e1000_hw *hw = &adapter->hw;
4814 /* read ICR disables interrupts using IAM */
4815 u32 icr = rd32(E1000_ICR);
4816
047e0030 4817 igb_write_itr(q_vector);
9d5c8243 4818
7f081d40
AD		 4819 if (icr & E1000_ICR_DRSTA)
4820 schedule_work(&adapter->reset_task);
4821
047e0030 4822 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 4823 /* HW is reporting DMA is out of sync */
4824 adapter->stats.doosync++;
4825 }
4826
9d5c8243
AK		 4827 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4828 hw->mac.get_link_status = 1;
4829 if (!test_bit(__IGB_DOWN, &adapter->state))
4830 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4831 }
4832
047e0030 4833 napi_schedule(&q_vector->napi);
9d5c8243
AK		 4834
4835 return IRQ_HANDLED;
4836}
4837
4838/**
4a3c6433 4839 * igb_intr - Legacy Interrupt Handler
9d5c8243
AK		 4840 * @irq: interrupt number
4841 * @data: pointer to a network interface device structure
4842 **/
4843static irqreturn_t igb_intr(int irq, void *data)
4844{
047e0030
AD		 4845 struct igb_adapter *adapter = data;
4846 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 4847 struct e1000_hw *hw = &adapter->hw;
4848 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
4849 * need for the IMC write */
4850 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 4851 if (!icr)
4852 return IRQ_NONE; /* Not our interrupt */
4853
047e0030 4854 igb_write_itr(q_vector);
9d5c8243
AK		 4855
4856 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
4857 * not set, then the adapter didn't send an interrupt */
4858 if (!(icr & E1000_ICR_INT_ASSERTED))
4859 return IRQ_NONE;
4860
7f081d40
AD		 4861 if (icr & E1000_ICR_DRSTA)
4862 schedule_work(&adapter->reset_task);
4863
047e0030 4864 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 4865 /* HW is reporting DMA is out of sync */
4866 adapter->stats.doosync++;
4867 }
4868
9d5c8243
AK		 4869 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4870 hw->mac.get_link_status = 1;
4871 /* guard against interrupt when we're going down */
4872 if (!test_bit(__IGB_DOWN, &adapter->state))
4873 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4874 }
4875
047e0030 4876 napi_schedule(&q_vector->napi);
9d5c8243
AK		 4877
4878 return IRQ_HANDLED;
4879}
4880
047e0030 4881static inline void igb_ring_irq_enable(struct igb_q_vector *q_vector)
9d5c8243 4882{
047e0030 4883 struct igb_adapter *adapter = q_vector->adapter;
46544258 4884 struct e1000_hw *hw = &adapter->hw;
9d5c8243 4885
4fc82adf
AD		 4886 if ((q_vector->rx_ring && (adapter->rx_itr_setting & 3)) ||
4887 (!q_vector->rx_ring && (adapter->tx_itr_setting & 3))) {
047e0030 4888 if (!adapter->msix_entries)
6eb5a7f1 4889 igb_set_itr(adapter);
46544258 4890 else
047e0030 4891 igb_update_ring_itr(q_vector);
9d5c8243
AK		 4892 }
4893
46544258
AD		 4894 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4895 if (adapter->msix_entries)
047e0030 4896 wr32(E1000_EIMS, q_vector->eims_value);
46544258
AD		 4897 else
4898 igb_irq_enable(adapter);
4899 }
9d5c8243
AK		 4900}
4901
46544258
AD		 4902/**
4903 * igb_poll - NAPI Rx polling callback
4904 * @napi: napi polling structure
4905 * @budget: count of how many packets we should handle
4906 **/
4907static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 4908{
047e0030
AD		 4909 struct igb_q_vector *q_vector = container_of(napi,
4910 struct igb_q_vector,
4911 napi);
4912 int tx_clean_complete = 1, work_done = 0;
9d5c8243 4913
421e02f0 4914#ifdef CONFIG_IGB_DCA
047e0030
AD		 4915 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
4916 igb_update_dca(q_vector);
fe4506b6 4917#endif
047e0030
AD		 4918 if (q_vector->tx_ring)
4919 tx_clean_complete = igb_clean_tx_irq(q_vector);
9d5c8243 4920
047e0030
AD		 4921 if (q_vector->rx_ring)
4922 igb_clean_rx_irq_adv(q_vector, &work_done, budget);
4923
4924 if (!tx_clean_complete)
4925 work_done = budget;
46544258 4926
9d5c8243 4927 /* If not enough Rx work done, exit the polling mode */
5e6d5b17 4928 if (work_done < budget) {
288379f0 4929 napi_complete(napi);
047e0030 4930 igb_ring_irq_enable(q_vector);
9d5c8243
AK		 4931 }
4932
46544258 4933 return work_done;
9d5c8243 4934}
6d8126f9 4935
33af6bcc 4936/**
c5b9bd5e 4937 * igb_systim_to_hwtstamp - convert system time value to hw timestamp
33af6bcc 4938 * @adapter: board private structure
c5b9bd5e
AD		 4939 * @shhwtstamps: timestamp structure to update
4940 * @regval: unsigned 64bit system time value.
4941 *
4942 * We need to convert the system time value stored in the RX/TXSTMP registers
4943 * into a hwtstamp which can be used by the upper level timestamping functions
4944 */
4945static void igb_systim_to_hwtstamp(struct igb_adapter *adapter,
4946 struct skb_shared_hwtstamps *shhwtstamps,
4947 u64 regval)
4948{
4949 u64 ns;
4950
55cac248
AD		 4951 /*
4952 * The 82580 starts with 1ns at bit 0 in RX/TXSTMPL, shift this up to
4953 * 24 to match clock shift we setup earlier.
4954 */
4955 if (adapter->hw.mac.type == e1000_82580)
4956 regval <<= IGB_82580_TSYNC_SHIFT;
4957
c5b9bd5e
AD		 4958 ns = timecounter_cyc2time(&adapter->clock, regval);
4959 timecompare_update(&adapter->compare, ns);
4960 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps));
4961 shhwtstamps->hwtstamp = ns_to_ktime(ns);
4962 shhwtstamps->syststamp = timecompare_transform(&adapter->compare, ns);
4963}
4964
4965/**
4966 * igb_tx_hwtstamp - utility function which checks for TX time stamp
4967 * @q_vector: pointer to q_vector containing needed info
33af6bcc
PO		 4968 * @skb: packet that was just sent
4969 *
4970 * If we were asked to do hardware stamping and such a time stamp is
4971 * available, then it must have been for this skb here because we only
4972 * allow only one such packet into the queue.
4973 */
c5b9bd5e 4974static void igb_tx_hwtstamp(struct igb_q_vector *q_vector, struct sk_buff *skb)
33af6bcc 4975{
c5b9bd5e 4976 struct igb_adapter *adapter = q_vector->adapter;
33af6bcc
PO		 4977 union skb_shared_tx *shtx = skb_tx(skb);
4978 struct e1000_hw *hw = &adapter->hw;
c5b9bd5e
AD		 4979 struct skb_shared_hwtstamps shhwtstamps;
4980 u64 regval;
33af6bcc 4981
c5b9bd5e
AD		 4982 /* if skb does not support hw timestamp or TX stamp not valid exit */
4983 if (likely(!shtx->hardware) ||
4984 !(rd32(E1000_TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID))
4985 return;
4986
4987 regval = rd32(E1000_TXSTMPL);
4988 regval |= (u64)rd32(E1000_TXSTMPH) << 32;
4989
4990 igb_systim_to_hwtstamp(adapter, &shhwtstamps, regval);
4991 skb_tstamp_tx(skb, &shhwtstamps);
33af6bcc
PO		 4992}
4993
9d5c8243
AK		 4994/**
4995 * igb_clean_tx_irq - Reclaim resources after transmit completes
047e0030 4996 * @q_vector: pointer to q_vector containing needed info
9d5c8243
AK		 4997 * returns true if ring is completely cleaned
4998 **/
047e0030 4999static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
9d5c8243 5000{
047e0030
AD		 5001 struct igb_adapter *adapter = q_vector->adapter;
5002 struct igb_ring *tx_ring = q_vector->tx_ring;
e694e964 5003 struct net_device *netdev = tx_ring->netdev;
0e014cb1 5004 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 5005 struct igb_buffer *buffer_info;
5006 struct sk_buff *skb;
0e014cb1 5007 union e1000_adv_tx_desc *tx_desc, *eop_desc;
9d5c8243 5008 unsigned int total_bytes = 0, total_packets = 0;
0e014cb1
AD		 5009 unsigned int i, eop, count = 0;
5010 bool cleaned = false;
9d5c8243 5011
9d5c8243 5012 i = tx_ring->next_to_clean;
0e014cb1
AD		 5013 eop = tx_ring->buffer_info[i].next_to_watch;
5014 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
5015
5016 while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) &&
5017 (count < tx_ring->count)) {
5018 for (cleaned = false; !cleaned; count++) {
5019 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
9d5c8243 5020 buffer_info = &tx_ring->buffer_info[i];
0e014cb1 5021 cleaned = (i == eop);
9d5c8243
AK		 5022 skb = buffer_info->skb;
5023
5024 if (skb) {
5025 unsigned int segs, bytecount;
5026 /* gso_segs is currently only valid for tcp */
5027 segs = skb_shinfo(skb)->gso_segs ?: 1;
5028 /* multiply data chunks by size of headers */
5029 bytecount = ((segs - 1) * skb_headlen(skb)) +
5030 skb->len;
5031 total_packets += segs;
5032 total_bytes += bytecount;
33af6bcc 5033
c5b9bd5e 5034 igb_tx_hwtstamp(q_vector, skb);
9d5c8243
AK		 5035 }
5036
80785298 5037 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
0e014cb1 5038 tx_desc->wb.status = 0;
9d5c8243
AK		 5039
5040 i++;
5041 if (i == tx_ring->count)
5042 i = 0;
9d5c8243 5043 }
0e014cb1
AD		 5044 eop = tx_ring->buffer_info[i].next_to_watch;
5045 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
5046 }
5047
9d5c8243
AK		 5048 tx_ring->next_to_clean = i;
5049
fc7d345d 5050 if (unlikely(count &&
9d5c8243 5051 netif_carrier_ok(netdev) &&
c493ea45 5052 igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
9d5c8243
AK		 5053 /* Make sure that anybody stopping the queue after this
5054 * sees the new next_to_clean.
5055 */
5056 smp_mb();
661086df
PWJ		 5057 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
5058 !(test_bit(__IGB_DOWN, &adapter->state))) {
5059 netif_wake_subqueue(netdev, tx_ring->queue_index);
04a5fcaa 5060 tx_ring->tx_stats.restart_queue++;
661086df 5061 }
9d5c8243
AK		 5062 }
5063
5064 if (tx_ring->detect_tx_hung) {
5065 /* Detect a transmit hang in hardware, this serializes the
5066 * check with the clearing of time_stamp and movement of i */
5067 tx_ring->detect_tx_hung = false;
5068 if (tx_ring->buffer_info[i].time_stamp &&
5069 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
8e95a202
JP		 5070 (adapter->tx_timeout_factor * HZ)) &&
5071 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
9d5c8243 5072
9d5c8243 5073 /* detected Tx unit hang */
80785298 5074 dev_err(&tx_ring->pdev->dev,
9d5c8243 5075 "Detected Tx Unit Hang\n"
2d064c06 5076 " Tx Queue <%d>\n"
9d5c8243
AK		 5077 " TDH <%x>\n"
5078 " TDT <%x>\n"
5079 " next_to_use <%x>\n"
5080 " next_to_clean <%x>\n"
9d5c8243
AK		 5081 "buffer_info[next_to_clean]\n"
5082 " time_stamp <%lx>\n"
0e014cb1 5083 " next_to_watch <%x>\n"
9d5c8243
AK		 5084 " jiffies <%lx>\n"
5085 " desc.status <%x>\n",
2d064c06 5086 tx_ring->queue_index,
fce99e34
AD		 5087 readl(tx_ring->head),
5088 readl(tx_ring->tail),
9d5c8243
AK		 5089 tx_ring->next_to_use,
5090 tx_ring->next_to_clean,
f7ba205e 5091 tx_ring->buffer_info[eop].time_stamp,
0e014cb1 5092 eop,
9d5c8243 5093 jiffies,
0e014cb1 5094 eop_desc->wb.status);
661086df 5095 netif_stop_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 5096 }
5097 }
5098 tx_ring->total_bytes += total_bytes;
5099 tx_ring->total_packets += total_packets;
e21ed353
AD		 5100 tx_ring->tx_stats.bytes += total_bytes;
5101 tx_ring->tx_stats.packets += total_packets;
0e014cb1 5102 return (count < tx_ring->count);
9d5c8243
AK		 5103}
5104
9d5c8243
AK		 5105/**
5106 * igb_receive_skb - helper function to handle rx indications
047e0030
AD		 5107 * @q_vector: structure containing interrupt and ring information
5108 * @skb: packet to send up
5109 * @vlan_tag: vlan tag for packet
9d5c8243 5110 **/
047e0030
AD		 5111static void igb_receive_skb(struct igb_q_vector *q_vector,
5112 struct sk_buff *skb,
5113 u16 vlan_tag)
5114{
5115 struct igb_adapter *adapter = q_vector->adapter;
5116
5117 if (vlan_tag)
5118 vlan_gro_receive(&q_vector->napi, adapter->vlgrp,
5119 vlan_tag, skb);
182ff8df 5120 else
047e0030 5121 napi_gro_receive(&q_vector->napi, skb);
9d5c8243
AK		 5122}
5123
04a5fcaa 5124static inline void igb_rx_checksum_adv(struct igb_ring *ring,
9d5c8243
AK		 5125 u32 status_err, struct sk_buff *skb)
5126{
5127 skb->ip_summed = CHECKSUM_NONE;
5128
5129 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
85ad76b2
AD		 5130 if (!(ring->flags & IGB_RING_FLAG_RX_CSUM) ||
5131 (status_err & E1000_RXD_STAT_IXSM))
9d5c8243 5132 return;
85ad76b2 5133
9d5c8243
AK		 5134 /* TCP/UDP checksum error bit is set */
5135 if (status_err &
5136 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
b9473560
JB		 5137 /*
5138 * work around errata with sctp packets where the TCPE aka
5139 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
5140 * packets, (aka let the stack check the crc32c)
5141 */
85ad76b2
AD		 5142 if ((skb->len == 60) &&
5143 (ring->flags & IGB_RING_FLAG_RX_SCTP_CSUM))
04a5fcaa 5144 ring->rx_stats.csum_err++;
85ad76b2 5145
9d5c8243 5146 /* let the stack verify checksum errors */
9d5c8243
AK		 5147 return;
5148 }
5149 /* It must be a TCP or UDP packet with a valid checksum */
5150 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
5151 skb->ip_summed = CHECKSUM_UNNECESSARY;
5152
85ad76b2 5153 dev_dbg(&ring->pdev->dev, "cksum success: bits %08X\n", status_err);
9d5c8243
AK		 5154}
5155
c5b9bd5e
AD		 5156static inline void igb_rx_hwtstamp(struct igb_q_vector *q_vector, u32 staterr,
5157 struct sk_buff *skb)
5158{
5159 struct igb_adapter *adapter = q_vector->adapter;
5160 struct e1000_hw *hw = &adapter->hw;
5161 u64 regval;
5162
5163 /*
5164 * If this bit is set, then the RX registers contain the time stamp. No
5165 * other packet will be time stamped until we read these registers, so
5166 * read the registers to make them available again. Because only one
5167 * packet can be time stamped at a time, we know that the register
5168 * values must belong to this one here and therefore we don't need to
5169 * compare any of the additional attributes stored for it.
5170 *
5171 * If nothing went wrong, then it should have a skb_shared_tx that we
5172 * can turn into a skb_shared_hwtstamps.
5173 */
5174 if (likely(!(staterr & E1000_RXDADV_STAT_TS)))
5175 return;
5176 if (!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
5177 return;
5178
5179 regval = rd32(E1000_RXSTMPL);
5180 regval |= (u64)rd32(E1000_RXSTMPH) << 32;
5181
5182 igb_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval);
5183}
4c844851 5184static inline u16 igb_get_hlen(struct igb_ring *rx_ring,
2d94d8ab
AD		 5185 union e1000_adv_rx_desc *rx_desc)
5186{
5187 /* HW will not DMA in data larger than the given buffer, even if it
5188 * parses the (NFS, of course) header to be larger. In that case, it
5189 * fills the header buffer and spills the rest into the page.
5190 */
5191 u16 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
5192 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
4c844851
AD		 5193 if (hlen > rx_ring->rx_buffer_len)
5194 hlen = rx_ring->rx_buffer_len;
2d94d8ab
AD		 5195 return hlen;
5196}
5197
047e0030
AD		 5198static bool igb_clean_rx_irq_adv(struct igb_q_vector *q_vector,
5199 int *work_done, int budget)
9d5c8243 5200{
047e0030 5201 struct igb_ring *rx_ring = q_vector->rx_ring;
e694e964 5202 struct net_device *netdev = rx_ring->netdev;
80785298 5203 struct pci_dev *pdev = rx_ring->pdev;
9d5c8243
AK		 5204 union e1000_adv_rx_desc *rx_desc , *next_rxd;
5205 struct igb_buffer *buffer_info , *next_buffer;
5206 struct sk_buff *skb;
9d5c8243
AK		 5207 bool cleaned = false;
5208 int cleaned_count = 0;
d1eff350 5209 int current_node = numa_node_id();
9d5c8243 5210 unsigned int total_bytes = 0, total_packets = 0;
73cd78f1 5211 unsigned int i;
2d94d8ab
AD		 5212 u32 staterr;
5213 u16 length;
047e0030 5214 u16 vlan_tag;
9d5c8243
AK		 5215
5216 i = rx_ring->next_to_clean;
69d3ca53 5217 buffer_info = &rx_ring->buffer_info[i];
9d5c8243
AK		 5218 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
5219 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
5220
5221 while (staterr & E1000_RXD_STAT_DD) {
5222 if (*work_done >= budget)
5223 break;
5224 (*work_done)++;
9d5c8243 5225
69d3ca53
AD		 5226 skb = buffer_info->skb;
5227 prefetch(skb->data - NET_IP_ALIGN);
5228 buffer_info->skb = NULL;
5229
5230 i++;
5231 if (i == rx_ring->count)
5232 i = 0;
42d0781a 5233
69d3ca53
AD		 5234 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
5235 prefetch(next_rxd);
5236 next_buffer = &rx_ring->buffer_info[i];
9d5c8243
AK		 5237
5238 length = le16_to_cpu(rx_desc->wb.upper.length);
5239 cleaned = true;
5240 cleaned_count++;
5241
2d94d8ab 5242 if (buffer_info->dma) {
bf36c1a0 5243 pci_unmap_single(pdev, buffer_info->dma,
4c844851 5244 rx_ring->rx_buffer_len,
bf36c1a0 5245 PCI_DMA_FROMDEVICE);
91615f76 5246 buffer_info->dma = 0;
4c844851 5247 if (rx_ring->rx_buffer_len >= IGB_RXBUFFER_1024) {
6ec43fe6
AD		 5248 skb_put(skb, length);
5249 goto send_up;
5250 }
4c844851 5251 skb_put(skb, igb_get_hlen(rx_ring, rx_desc));
bf36c1a0
AD		 5252 }
5253
5254 if (length) {
9d5c8243 5255 pci_unmap_page(pdev, buffer_info->page_dma,
bf36c1a0 5256 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9d5c8243 5257 buffer_info->page_dma = 0;
bf36c1a0
AD		 5258
5259 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
5260 buffer_info->page,
5261 buffer_info->page_offset,
5262 length);
5263
d1eff350
AD		 5264 if ((page_count(buffer_info->page) != 1) ||
5265 (page_to_nid(buffer_info->page) != current_node))
bf36c1a0
AD		 5266 buffer_info->page = NULL;
5267 else
5268 get_page(buffer_info->page);
9d5c8243
AK		 5269
5270 skb->len += length;
5271 skb->data_len += length;
bf36c1a0 5272 skb->truesize += length;
9d5c8243 5273 }
9d5c8243 5274
bf36c1a0 5275 if (!(staterr & E1000_RXD_STAT_EOP)) {
b2d56536
AD		 5276 buffer_info->skb = next_buffer->skb;
5277 buffer_info->dma = next_buffer->dma;
5278 next_buffer->skb = skb;
5279 next_buffer->dma = 0;
bf36c1a0
AD		 5280 goto next_desc;
5281 }
69d3ca53 5282send_up:
9d5c8243
AK		 5283 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
5284 dev_kfree_skb_irq(skb);
5285 goto next_desc;
5286 }
9d5c8243 5287
c5b9bd5e 5288 igb_rx_hwtstamp(q_vector, staterr, skb);
9d5c8243
AK		 5289 total_bytes += skb->len;
5290 total_packets++;
5291
85ad76b2 5292 igb_rx_checksum_adv(rx_ring, staterr, skb);
9d5c8243
AK		 5293
5294 skb->protocol = eth_type_trans(skb, netdev);
047e0030
AD		 5295 skb_record_rx_queue(skb, rx_ring->queue_index);
5296
5297 vlan_tag = ((staterr & E1000_RXD_STAT_VP) ?
5298 le16_to_cpu(rx_desc->wb.upper.vlan) : 0);
9d5c8243 5299
047e0030 5300 igb_receive_skb(q_vector, skb, vlan_tag);
9d5c8243 5301
9d5c8243
AK		 5302next_desc:
5303 rx_desc->wb.upper.status_error = 0;
5304
5305 /* return some buffers to hardware, one at a time is too slow */
5306 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
3b644cf6 5307 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 5308 cleaned_count = 0;
5309 }
5310
5311 /* use prefetched values */
5312 rx_desc = next_rxd;
5313 buffer_info = next_buffer;
9d5c8243
AK		 5314 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
5315 }
bf36c1a0 5316
9d5c8243 5317 rx_ring->next_to_clean = i;
c493ea45 5318 cleaned_count = igb_desc_unused(rx_ring);
9d5c8243
AK		 5319
5320 if (cleaned_count)
3b644cf6 5321 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 5322
5323 rx_ring->total_packets += total_packets;
5324 rx_ring->total_bytes += total_bytes;
5325 rx_ring->rx_stats.packets += total_packets;
5326 rx_ring->rx_stats.bytes += total_bytes;
9d5c8243
AK		 5327 return cleaned;
5328}
5329
9d5c8243
AK		 5330/**
5331 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
5332 * @adapter: address of board private structure
5333 **/
d7ee5b3a 5334void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring, int cleaned_count)
9d5c8243 5335{
e694e964 5336 struct net_device *netdev = rx_ring->netdev;
9d5c8243
AK		 5337 union e1000_adv_rx_desc *rx_desc;
5338 struct igb_buffer *buffer_info;
5339 struct sk_buff *skb;
5340 unsigned int i;
db761762 5341 int bufsz;
9d5c8243
AK		 5342
5343 i = rx_ring->next_to_use;
5344 buffer_info = &rx_ring->buffer_info[i];
5345
4c844851 5346 bufsz = rx_ring->rx_buffer_len;
db761762 5347
9d5c8243
AK		 5348 while (cleaned_count--) {
5349 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
5350
6ec43fe6 5351 if ((bufsz < IGB_RXBUFFER_1024) && !buffer_info->page_dma) {
9d5c8243 5352 if (!buffer_info->page) {
42d0781a 5353 buffer_info->page = netdev_alloc_page(netdev);
bf36c1a0 5354 if (!buffer_info->page) {
04a5fcaa 5355 rx_ring->rx_stats.alloc_failed++;
bf36c1a0
AD		 5356 goto no_buffers;
5357 }
5358 buffer_info->page_offset = 0;
5359 } else {
5360 buffer_info->page_offset ^= PAGE_SIZE / 2;
9d5c8243
AK		 5361 }
5362 buffer_info->page_dma =
80785298 5363 pci_map_page(rx_ring->pdev, buffer_info->page,
bf36c1a0
AD		 5364 buffer_info->page_offset,
5365 PAGE_SIZE / 2,
9d5c8243 5366 PCI_DMA_FROMDEVICE);
42d0781a
AD		 5367 if (pci_dma_mapping_error(rx_ring->pdev,
5368 buffer_info->page_dma)) {
5369 buffer_info->page_dma = 0;
5370 rx_ring->rx_stats.alloc_failed++;
5371 goto no_buffers;
5372 }
9d5c8243
AK		 5373 }
5374
42d0781a
AD		 5375 skb = buffer_info->skb;
5376 if (!skb) {
89d71a66 5377 skb = netdev_alloc_skb_ip_align(netdev, bufsz);
9d5c8243 5378 if (!skb) {
04a5fcaa 5379 rx_ring->rx_stats.alloc_failed++;
9d5c8243
AK		 5380 goto no_buffers;
5381 }
5382
9d5c8243 5383 buffer_info->skb = skb;
42d0781a
AD		 5384 }
5385 if (!buffer_info->dma) {
80785298
AD		 5386 buffer_info->dma = pci_map_single(rx_ring->pdev,
5387 skb->data,
9d5c8243
AK		 5388 bufsz,
5389 PCI_DMA_FROMDEVICE);
42d0781a
AD		 5390 if (pci_dma_mapping_error(rx_ring->pdev,
5391 buffer_info->dma)) {
5392 buffer_info->dma = 0;
5393 rx_ring->rx_stats.alloc_failed++;
5394 goto no_buffers;
5395 }
9d5c8243
AK		 5396 }
5397 /* Refresh the desc even if buffer_addrs didn't change because
5398 * each write-back erases this info. */
6ec43fe6 5399 if (bufsz < IGB_RXBUFFER_1024) {
9d5c8243
AK		 5400 rx_desc->read.pkt_addr =
5401 cpu_to_le64(buffer_info->page_dma);
5402 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
5403 } else {
42d0781a 5404 rx_desc->read.pkt_addr = cpu_to_le64(buffer_info->dma);
9d5c8243
AK		 5405 rx_desc->read.hdr_addr = 0;
5406 }
5407
5408 i++;
5409 if (i == rx_ring->count)
5410 i = 0;
5411 buffer_info = &rx_ring->buffer_info[i];
5412 }
5413
5414no_buffers:
5415 if (rx_ring->next_to_use != i) {
5416 rx_ring->next_to_use = i;
5417 if (i == 0)
5418 i = (rx_ring->count - 1);
5419 else
5420 i--;
5421
5422 /* Force memory writes to complete before letting h/w
5423 * know there are new descriptors to fetch. (Only
5424 * applicable for weak-ordered memory model archs,
5425 * such as IA-64). */
5426 wmb();
fce99e34 5427 writel(i, rx_ring->tail);
9d5c8243
AK		 5428 }
5429}
5430
5431/**
5432 * igb_mii_ioctl -
5433 * @netdev:
5434 * @ifreq:
5435 * @cmd:
5436 **/
5437static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5438{
5439 struct igb_adapter *adapter = netdev_priv(netdev);
5440 struct mii_ioctl_data *data = if_mii(ifr);
5441
5442 if (adapter->hw.phy.media_type != e1000_media_type_copper)
5443 return -EOPNOTSUPP;
5444
5445 switch (cmd) {
5446 case SIOCGMIIPHY:
5447 data->phy_id = adapter->hw.phy.addr;
5448 break;
5449 case SIOCGMIIREG:
f5f4cf08
AD		 5450 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
5451 &data->val_out))
9d5c8243
AK		 5452 return -EIO;
5453 break;
5454 case SIOCSMIIREG:
5455 default:
5456 return -EOPNOTSUPP;
5457 }
5458 return 0;
5459}
5460
c6cb090b
PO		 5461/**
5462 * igb_hwtstamp_ioctl - control hardware time stamping
5463 * @netdev:
5464 * @ifreq:
5465 * @cmd:
5466 *
33af6bcc
PO		 5467 * Outgoing time stamping can be enabled and disabled. Play nice and
5468 * disable it when requested, although it shouldn't case any overhead
5469 * when no packet needs it. At most one packet in the queue may be
5470 * marked for time stamping, otherwise it would be impossible to tell
5471 * for sure to which packet the hardware time stamp belongs.
5472 *
5473 * Incoming time stamping has to be configured via the hardware
5474 * filters. Not all combinations are supported, in particular event
5475 * type has to be specified. Matching the kind of event packet is
5476 * not supported, with the exception of "all V2 events regardless of
5477 * level 2 or 4".
5478 *
c6cb090b
PO		 5479 **/
5480static int igb_hwtstamp_ioctl(struct net_device *netdev,
5481 struct ifreq *ifr, int cmd)
5482{
33af6bcc
PO		 5483 struct igb_adapter *adapter = netdev_priv(netdev);
5484 struct e1000_hw *hw = &adapter->hw;
c6cb090b 5485 struct hwtstamp_config config;
c5b9bd5e
AD		 5486 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
5487 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
33af6bcc 5488 u32 tsync_rx_cfg = 0;
c5b9bd5e
AD		 5489 bool is_l4 = false;
5490 bool is_l2 = false;
33af6bcc 5491 u32 regval;
c6cb090b
PO		 5492
5493 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
5494 return -EFAULT;
5495
5496 /* reserved for future extensions */
5497 if (config.flags)
5498 return -EINVAL;
5499
33af6bcc
PO		 5500 switch (config.tx_type) {
5501 case HWTSTAMP_TX_OFF:
c5b9bd5e 5502 tsync_tx_ctl = 0;
33af6bcc 5503 case HWTSTAMP_TX_ON:
33af6bcc
PO		 5504 break;
5505 default:
5506 return -ERANGE;
5507 }
5508
5509 switch (config.rx_filter) {
5510 case HWTSTAMP_FILTER_NONE:
c5b9bd5e 5511 tsync_rx_ctl = 0;
33af6bcc
PO		 5512 break;
5513 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
5514 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
5515 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
5516 case HWTSTAMP_FILTER_ALL:
5517 /*
5518 * register TSYNCRXCFG must be set, therefore it is not
5519 * possible to time stamp both Sync and Delay_Req messages
5520 * => fall back to time stamping all packets
5521 */
c5b9bd5e 5522 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
33af6bcc
PO		 5523 config.rx_filter = HWTSTAMP_FILTER_ALL;
5524 break;
5525 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
c5b9bd5e 5526 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
33af6bcc 5527 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
c5b9bd5e 5528 is_l4 = true;
33af6bcc
PO		 5529 break;
5530 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
c5b9bd5e 5531 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
33af6bcc 5532 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
c5b9bd5e 5533 is_l4 = true;
33af6bcc
PO		 5534 break;
5535 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
5536 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
c5b9bd5e 5537 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
33af6bcc 5538 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE;
c5b9bd5e
AD		 5539 is_l2 = true;
5540 is_l4 = true;
33af6bcc
PO		 5541 config.rx_filter = HWTSTAMP_FILTER_SOME;
5542 break;
5543 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
5544 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
c5b9bd5e 5545 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
33af6bcc 5546 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE;
c5b9bd5e
AD		 5547 is_l2 = true;
5548 is_l4 = true;
33af6bcc
PO		 5549 config.rx_filter = HWTSTAMP_FILTER_SOME;
5550 break;
5551 case HWTSTAMP_FILTER_PTP_V2_EVENT:
5552 case HWTSTAMP_FILTER_PTP_V2_SYNC:
5553 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
c5b9bd5e 5554 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
33af6bcc 5555 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
c5b9bd5e 5556 is_l2 = true;
33af6bcc
PO		 5557 break;
5558 default:
5559 return -ERANGE;
5560 }
5561
c5b9bd5e
AD		 5562 if (hw->mac.type == e1000_82575) {
5563 if (tsync_rx_ctl | tsync_tx_ctl)
5564 return -EINVAL;
5565 return 0;
5566 }
5567
33af6bcc
PO		 5568 /* enable/disable TX */
5569 regval = rd32(E1000_TSYNCTXCTL);
c5b9bd5e
AD		 5570 regval &= ~E1000_TSYNCTXCTL_ENABLED;
5571 regval |= tsync_tx_ctl;
33af6bcc
PO		 5572 wr32(E1000_TSYNCTXCTL, regval);
5573
c5b9bd5e 5574 /* enable/disable RX */
33af6bcc 5575 regval = rd32(E1000_TSYNCRXCTL);
c5b9bd5e
AD		 5576 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
5577 regval |= tsync_rx_ctl;
33af6bcc 5578 wr32(E1000_TSYNCRXCTL, regval);
33af6bcc 5579
c5b9bd5e
AD		 5580 /* define which PTP packets are time stamped */
5581 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
33af6bcc 5582
c5b9bd5e
AD		 5583 /* define ethertype filter for timestamped packets */
5584 if (is_l2)
5585 wr32(E1000_ETQF(3),
5586 (E1000_ETQF_FILTER_ENABLE | /* enable filter */
5587 E1000_ETQF_1588 | /* enable timestamping */
5588 ETH_P_1588)); /* 1588 eth protocol type */
5589 else
5590 wr32(E1000_ETQF(3), 0);
5591
5592#define PTP_PORT 319
5593 /* L4 Queue Filter[3]: filter by destination port and protocol */
5594 if (is_l4) {
5595 u32 ftqf = (IPPROTO_UDP /* UDP */
5596 | E1000_FTQF_VF_BP /* VF not compared */
5597 | E1000_FTQF_1588_TIME_STAMP /* Enable Timestamping */
5598 | E1000_FTQF_MASK); /* mask all inputs */
5599 ftqf &= ~E1000_FTQF_MASK_PROTO_BP; /* enable protocol check */
5600
5601 wr32(E1000_IMIR(3), htons(PTP_PORT));
5602 wr32(E1000_IMIREXT(3),
5603 (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP));
5604 if (hw->mac.type == e1000_82576) {
5605 /* enable source port check */
5606 wr32(E1000_SPQF(3), htons(PTP_PORT));
5607 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
5608 }
5609 wr32(E1000_FTQF(3), ftqf);
5610 } else {
5611 wr32(E1000_FTQF(3), E1000_FTQF_MASK);
5612 }
33af6bcc
PO		 5613 wrfl();
5614
5615 adapter->hwtstamp_config = config;
5616
5617 /* clear TX/RX time stamp registers, just to be sure */
5618 regval = rd32(E1000_TXSTMPH);
5619 regval = rd32(E1000_RXSTMPH);
c6cb090b 5620
33af6bcc
PO		 5621 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
5622 -EFAULT : 0;
c6cb090b
PO		 5623}
5624
9d5c8243
AK		 5625/**
5626 * igb_ioctl -
5627 * @netdev:
5628 * @ifreq:
5629 * @cmd:
5630 **/
5631static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5632{
5633 switch (cmd) {
5634 case SIOCGMIIPHY:
5635 case SIOCGMIIREG:
5636 case SIOCSMIIREG:
5637 return igb_mii_ioctl(netdev, ifr, cmd);
c6cb090b
PO		 5638 case SIOCSHWTSTAMP:
5639 return igb_hwtstamp_ioctl(netdev, ifr, cmd);
9d5c8243
AK		 5640 default:
5641 return -EOPNOTSUPP;
5642 }
5643}
5644
009bc06e
AD		 5645s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
5646{
5647 struct igb_adapter *adapter = hw->back;
5648 u16 cap_offset;
5649
5650 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
5651 if (!cap_offset)
5652 return -E1000_ERR_CONFIG;
5653
5654 pci_read_config_word(adapter->pdev, cap_offset + reg, value);
5655
5656 return 0;
5657}
5658
5659s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
5660{
5661 struct igb_adapter *adapter = hw->back;
5662 u16 cap_offset;
5663
5664 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
5665 if (!cap_offset)
5666 return -E1000_ERR_CONFIG;
5667
5668 pci_write_config_word(adapter->pdev, cap_offset + reg, *value);
5669
5670 return 0;
5671}
5672
9d5c8243
AK		 5673static void igb_vlan_rx_register(struct net_device *netdev,
5674 struct vlan_group *grp)
5675{
5676 struct igb_adapter *adapter = netdev_priv(netdev);
5677 struct e1000_hw *hw = &adapter->hw;
5678 u32 ctrl, rctl;
5679
5680 igb_irq_disable(adapter);
5681 adapter->vlgrp = grp;
5682
5683 if (grp) {
5684 /* enable VLAN tag insert/strip */
5685 ctrl = rd32(E1000_CTRL);
5686 ctrl |= E1000_CTRL_VME;
5687 wr32(E1000_CTRL, ctrl);
5688
51466239 5689 /* Disable CFI check */
9d5c8243 5690 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 5691 rctl &= ~E1000_RCTL_CFIEN;
5692 wr32(E1000_RCTL, rctl);
9d5c8243
AK		 5693 } else {
5694 /* disable VLAN tag insert/strip */
5695 ctrl = rd32(E1000_CTRL);
5696 ctrl &= ~E1000_CTRL_VME;
5697 wr32(E1000_CTRL, ctrl);
9d5c8243
AK		 5698 }
5699
e1739522
AD		 5700 igb_rlpml_set(adapter);
5701
9d5c8243
AK		 5702 if (!test_bit(__IGB_DOWN, &adapter->state))
5703 igb_irq_enable(adapter);
5704}
5705
5706static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
5707{
5708 struct igb_adapter *adapter = netdev_priv(netdev);
5709 struct e1000_hw *hw = &adapter->hw;
4ae196df 5710 int pf_id = adapter->vfs_allocated_count;
9d5c8243 5711
51466239
AD		 5712 /* attempt to add filter to vlvf array */
5713 igb_vlvf_set(adapter, vid, true, pf_id);
4ae196df 5714
51466239
AD		 5715 /* add the filter since PF can receive vlans w/o entry in vlvf */
5716 igb_vfta_set(hw, vid, true);
9d5c8243
AK		 5717}
5718
5719static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
5720{
5721 struct igb_adapter *adapter = netdev_priv(netdev);
5722 struct e1000_hw *hw = &adapter->hw;
4ae196df 5723 int pf_id = adapter->vfs_allocated_count;
51466239 5724 s32 err;
9d5c8243
AK		 5725
5726 igb_irq_disable(adapter);
5727 vlan_group_set_device(adapter->vlgrp, vid, NULL);
5728
5729 if (!test_bit(__IGB_DOWN, &adapter->state))
5730 igb_irq_enable(adapter);
5731
51466239
AD		 5732 /* remove vlan from VLVF table array */
5733 err = igb_vlvf_set(adapter, vid, false, pf_id);
9d5c8243 5734
51466239
AD		 5735 /* if vid was not present in VLVF just remove it from table */
5736 if (err)
4ae196df 5737 igb_vfta_set(hw, vid, false);
9d5c8243
AK		 5738}
5739
5740static void igb_restore_vlan(struct igb_adapter *adapter)
5741{
5742 igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
5743
5744 if (adapter->vlgrp) {
5745 u16 vid;
5746 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
5747 if (!vlan_group_get_device(adapter->vlgrp, vid))
5748 continue;
5749 igb_vlan_rx_add_vid(adapter->netdev, vid);
5750 }
5751 }
5752}
5753
5754int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
5755{
090b1795 5756 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 5757 struct e1000_mac_info *mac = &adapter->hw.mac;
5758
5759 mac->autoneg = 0;
5760
9d5c8243
AK		 5761 switch (spddplx) {
5762 case SPEED_10 + DUPLEX_HALF:
5763 mac->forced_speed_duplex = ADVERTISE_10_HALF;
5764 break;
5765 case SPEED_10 + DUPLEX_FULL:
5766 mac->forced_speed_duplex = ADVERTISE_10_FULL;
5767 break;
5768 case SPEED_100 + DUPLEX_HALF:
5769 mac->forced_speed_duplex = ADVERTISE_100_HALF;
5770 break;
5771 case SPEED_100 + DUPLEX_FULL:
5772 mac->forced_speed_duplex = ADVERTISE_100_FULL;
5773 break;
5774 case SPEED_1000 + DUPLEX_FULL:
5775 mac->autoneg = 1;
5776 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
5777 break;
5778 case SPEED_1000 + DUPLEX_HALF: /* not supported */
5779 default:
090b1795 5780 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
9d5c8243
AK		 5781 return -EINVAL;
5782 }
5783 return 0;
5784}
5785
3fe7c4c9 5786static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake)
9d5c8243
AK		 5787{
5788 struct net_device *netdev = pci_get_drvdata(pdev);
5789 struct igb_adapter *adapter = netdev_priv(netdev);
5790 struct e1000_hw *hw = &adapter->hw;
2d064c06 5791 u32 ctrl, rctl, status;
9d5c8243
AK		 5792 u32 wufc = adapter->wol;
5793#ifdef CONFIG_PM
5794 int retval = 0;
5795#endif
5796
5797 netif_device_detach(netdev);
5798
a88f10ec
AD		 5799 if (netif_running(netdev))
5800 igb_close(netdev);
5801
047e0030 5802 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 5803
5804#ifdef CONFIG_PM
5805 retval = pci_save_state(pdev);
5806 if (retval)
5807 return retval;
5808#endif
5809
5810 status = rd32(E1000_STATUS);
5811 if (status & E1000_STATUS_LU)
5812 wufc &= ~E1000_WUFC_LNKC;
5813
5814 if (wufc) {
5815 igb_setup_rctl(adapter);
ff41f8dc 5816 igb_set_rx_mode(netdev);
9d5c8243
AK		 5817
5818 /* turn on all-multi mode if wake on multicast is enabled */
5819 if (wufc & E1000_WUFC_MC) {
5820 rctl = rd32(E1000_RCTL);
5821 rctl |= E1000_RCTL_MPE;
5822 wr32(E1000_RCTL, rctl);
5823 }
5824
5825 ctrl = rd32(E1000_CTRL);
5826 /* advertise wake from D3Cold */
5827 #define E1000_CTRL_ADVD3WUC 0x00100000
5828 /* phy power management enable */
5829 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
5830 ctrl |= E1000_CTRL_ADVD3WUC;
5831 wr32(E1000_CTRL, ctrl);
5832
9d5c8243 5833 /* Allow time for pending master requests to run */
330a6d6a 5834 igb_disable_pcie_master(hw);
9d5c8243
AK		 5835
5836 wr32(E1000_WUC, E1000_WUC_PME_EN);
5837 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 5838 } else {
5839 wr32(E1000_WUC, 0);
5840 wr32(E1000_WUFC, 0);
9d5c8243
AK		 5841 }
5842
3fe7c4c9
RW		 5843 *enable_wake = wufc || adapter->en_mng_pt;
5844 if (!*enable_wake)
88a268c1
NN		 5845 igb_power_down_link(adapter);
5846 else
5847 igb_power_up_link(adapter);
9d5c8243
AK		 5848
5849 /* Release control of h/w to f/w. If f/w is AMT enabled, this
5850 * would have already happened in close and is redundant. */
5851 igb_release_hw_control(adapter);
5852
5853 pci_disable_device(pdev);
5854
9d5c8243
AK		 5855 return 0;
5856}
5857
5858#ifdef CONFIG_PM
3fe7c4c9
RW		 5859static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
5860{
5861 int retval;
5862 bool wake;
5863
5864 retval = __igb_shutdown(pdev, &wake);
5865 if (retval)
5866 return retval;
5867
5868 if (wake) {
5869 pci_prepare_to_sleep(pdev);
5870 } else {
5871 pci_wake_from_d3(pdev, false);
5872 pci_set_power_state(pdev, PCI_D3hot);
5873 }
5874
5875 return 0;
5876}
5877
9d5c8243
AK		 5878static int igb_resume(struct pci_dev *pdev)
5879{
5880 struct net_device *netdev = pci_get_drvdata(pdev);
5881 struct igb_adapter *adapter = netdev_priv(netdev);
5882 struct e1000_hw *hw = &adapter->hw;
5883 u32 err;
5884
5885 pci_set_power_state(pdev, PCI_D0);
5886 pci_restore_state(pdev);
b94f2d77 5887 pci_save_state(pdev);
42bfd33a 5888
aed5dec3 5889 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 5890 if (err) {
5891 dev_err(&pdev->dev,
5892 "igb: Cannot enable PCI device from suspend\n");
5893 return err;
5894 }
5895 pci_set_master(pdev);
5896
5897 pci_enable_wake(pdev, PCI_D3hot, 0);
5898 pci_enable_wake(pdev, PCI_D3cold, 0);
5899
047e0030 5900 if (igb_init_interrupt_scheme(adapter)) {
a88f10ec
AD		 5901 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
5902 return -ENOMEM;
9d5c8243
AK		 5903 }
5904
9d5c8243 5905 igb_reset(adapter);
a8564f03
AD		 5906
5907 /* let the f/w know that the h/w is now under the control of the
5908 * driver. */
5909 igb_get_hw_control(adapter);
5910
9d5c8243
AK		 5911 wr32(E1000_WUS, ~0);
5912
a88f10ec
AD		 5913 if (netif_running(netdev)) {
5914 err = igb_open(netdev);
5915 if (err)
5916 return err;
5917 }
9d5c8243
AK		 5918
5919 netif_device_attach(netdev);
5920
9d5c8243
AK		 5921 return 0;
5922}
5923#endif
5924
5925static void igb_shutdown(struct pci_dev *pdev)
5926{
3fe7c4c9
RW		 5927 bool wake;
5928
5929 __igb_shutdown(pdev, &wake);
5930
5931 if (system_state == SYSTEM_POWER_OFF) {
5932 pci_wake_from_d3(pdev, wake);
5933 pci_set_power_state(pdev, PCI_D3hot);
5934 }
9d5c8243
AK		 5935}
5936
5937#ifdef CONFIG_NET_POLL_CONTROLLER
5938/*
5939 * Polling 'interrupt' - used by things like netconsole to send skbs
5940 * without having to re-enable interrupts. It's not called while
5941 * the interrupt routine is executing.
5942 */
5943static void igb_netpoll(struct net_device *netdev)
5944{
5945 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 5946 struct e1000_hw *hw = &adapter->hw;
9d5c8243 5947 int i;
9d5c8243 5948
eebbbdba 5949 if (!adapter->msix_entries) {
047e0030 5950 struct igb_q_vector *q_vector = adapter->q_vector[0];
eebbbdba 5951 igb_irq_disable(adapter);
047e0030 5952 napi_schedule(&q_vector->napi);
eebbbdba
AD		 5953 return;
5954 }
9d5c8243 5955
047e0030
AD		 5956 for (i = 0; i < adapter->num_q_vectors; i++) {
5957 struct igb_q_vector *q_vector = adapter->q_vector[i];
5958 wr32(E1000_EIMC, q_vector->eims_value);
5959 napi_schedule(&q_vector->napi);
eebbbdba 5960 }
9d5c8243
AK		 5961}
5962#endif /* CONFIG_NET_POLL_CONTROLLER */
5963
5964/**
5965 * igb_io_error_detected - called when PCI error is detected
5966 * @pdev: Pointer to PCI device
5967 * @state: The current pci connection state
5968 *
5969 * This function is called after a PCI bus error affecting
5970 * this device has been detected.
5971 */
5972static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
5973 pci_channel_state_t state)
5974{
5975 struct net_device *netdev = pci_get_drvdata(pdev);
5976 struct igb_adapter *adapter = netdev_priv(netdev);
5977
5978 netif_device_detach(netdev);
5979
59ed6eec
AD		 5980 if (state == pci_channel_io_perm_failure)
5981 return PCI_ERS_RESULT_DISCONNECT;
5982
9d5c8243
AK		 5983 if (netif_running(netdev))
5984 igb_down(adapter);
5985 pci_disable_device(pdev);
5986
5987 /* Request a slot slot reset. */
5988 return PCI_ERS_RESULT_NEED_RESET;
5989}
5990
5991/**
5992 * igb_io_slot_reset - called after the pci bus has been reset.
5993 * @pdev: Pointer to PCI device
5994 *
5995 * Restart the card from scratch, as if from a cold-boot. Implementation
5996 * resembles the first-half of the igb_resume routine.
5997 */
5998static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
5999{
6000 struct net_device *netdev = pci_get_drvdata(pdev);
6001 struct igb_adapter *adapter = netdev_priv(netdev);
6002 struct e1000_hw *hw = &adapter->hw;
40a914fa 6003 pci_ers_result_t result;
42bfd33a 6004 int err;
9d5c8243 6005
aed5dec3 6006 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 6007 dev_err(&pdev->dev,
6008 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 6009 result = PCI_ERS_RESULT_DISCONNECT;
6010 } else {
6011 pci_set_master(pdev);
6012 pci_restore_state(pdev);
b94f2d77 6013 pci_save_state(pdev);
9d5c8243 6014
40a914fa
AD		 6015 pci_enable_wake(pdev, PCI_D3hot, 0);
6016 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 6017
40a914fa
AD		 6018 igb_reset(adapter);
6019 wr32(E1000_WUS, ~0);
6020 result = PCI_ERS_RESULT_RECOVERED;
6021 }
9d5c8243 6022
ea943d41
JK		 6023 err = pci_cleanup_aer_uncorrect_error_status(pdev);
6024 if (err) {
6025 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
6026 "failed 0x%0x\n", err);
6027 /* non-fatal, continue */
6028 }
40a914fa
AD		 6029
6030 return result;
9d5c8243
AK		 6031}
6032
6033/**
6034 * igb_io_resume - called when traffic can start flowing again.
6035 * @pdev: Pointer to PCI device
6036 *
6037 * This callback is called when the error recovery driver tells us that
6038 * its OK to resume normal operation. Implementation resembles the
6039 * second-half of the igb_resume routine.
6040 */
6041static void igb_io_resume(struct pci_dev *pdev)
6042{
6043 struct net_device *netdev = pci_get_drvdata(pdev);
6044 struct igb_adapter *adapter = netdev_priv(netdev);
6045
9d5c8243
AK		 6046 if (netif_running(netdev)) {
6047 if (igb_up(adapter)) {
6048 dev_err(&pdev->dev, "igb_up failed after reset\n");
6049 return;
6050 }
6051 }
6052
6053 netif_device_attach(netdev);
6054
6055 /* let the f/w know that the h/w is now under the control of the
6056 * driver. */
6057 igb_get_hw_control(adapter);
9d5c8243
AK		 6058}
6059
26ad9178
AD		 6060static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
6061 u8 qsel)
6062{
6063 u32 rar_low, rar_high;
6064 struct e1000_hw *hw = &adapter->hw;
6065
6066 /* HW expects these in little endian so we reverse the byte order
6067 * from network order (big endian) to little endian
6068 */
6069 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
6070 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
6071 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
6072
6073 /* Indicate to hardware the Address is Valid. */
6074 rar_high |= E1000_RAH_AV;
6075
6076 if (hw->mac.type == e1000_82575)
6077 rar_high |= E1000_RAH_POOL_1 * qsel;
6078 else
6079 rar_high |= E1000_RAH_POOL_1 << qsel;
6080
6081 wr32(E1000_RAL(index), rar_low);
6082 wrfl();
6083 wr32(E1000_RAH(index), rar_high);
6084 wrfl();
6085}
6086
4ae196df
AD		 6087static int igb_set_vf_mac(struct igb_adapter *adapter,
6088 int vf, unsigned char *mac_addr)
6089{
6090 struct e1000_hw *hw = &adapter->hw;
ff41f8dc
AD		 6091 /* VF MAC addresses start at end of receive addresses and moves
6092 * torwards the first, as a result a collision should not be possible */
6093 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 6094
37680117 6095 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 6096
26ad9178 6097 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
4ae196df
AD		 6098
6099 return 0;
6100}
6101
8151d294
WM		 6102static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
6103{
6104 struct igb_adapter *adapter = netdev_priv(netdev);
6105 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
6106 return -EINVAL;
6107 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
6108 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
6109 dev_info(&adapter->pdev->dev, "Reload the VF driver to make this"
6110 " change effective.");
6111 if (test_bit(__IGB_DOWN, &adapter->state)) {
6112 dev_warn(&adapter->pdev->dev, "The VF MAC address has been set,"
6113 " but the PF device is not up.\n");
6114 dev_warn(&adapter->pdev->dev, "Bring the PF device up before"
6115 " attempting to use the VF device.\n");
6116 }
6117 return igb_set_vf_mac(adapter, vf, mac);
6118}
6119
6120static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate)
6121{
6122 return -EOPNOTSUPP;
6123}
6124
6125static int igb_ndo_get_vf_config(struct net_device *netdev,
6126 int vf, struct ifla_vf_info *ivi)
6127{
6128 struct igb_adapter *adapter = netdev_priv(netdev);
6129 if (vf >= adapter->vfs_allocated_count)
6130 return -EINVAL;
6131 ivi->vf = vf;
6132 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
6133 ivi->tx_rate = 0;
6134 ivi->vlan = adapter->vf_data[vf].pf_vlan;
6135 ivi->qos = adapter->vf_data[vf].pf_qos;
6136 return 0;
6137}
6138
4ae196df
AD		 6139static void igb_vmm_control(struct igb_adapter *adapter)
6140{
6141 struct e1000_hw *hw = &adapter->hw;
10d8e907 6142 u32 reg;
4ae196df 6143
d4960307
AD		 6144 /* replication is not supported for 82575 */
6145 if (hw->mac.type == e1000_82575)
4ae196df
AD		 6146 return;
6147
10d8e907
AD		 6148 /* enable replication vlan tag stripping */
6149 reg = rd32(E1000_RPLOLR);
6150 reg |= E1000_RPLOLR_STRVLAN;
6151 wr32(E1000_RPLOLR, reg);
6152
6153 /* notify HW that the MAC is adding vlan tags */
6154 reg = rd32(E1000_DTXCTL);
6155 reg |= E1000_DTXCTL_VLAN_ADDED;
6156 wr32(E1000_DTXCTL, reg);
6157
d4960307
AD		 6158 if (adapter->vfs_allocated_count) {
6159 igb_vmdq_set_loopback_pf(hw, true);
6160 igb_vmdq_set_replication_pf(hw, true);
6161 } else {
6162 igb_vmdq_set_loopback_pf(hw, false);
6163 igb_vmdq_set_replication_pf(hw, false);
6164 }
4ae196df
AD		 6165}
6166
9d5c8243 6167/* igb_main.c */
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