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igb: remove check for needing an io port
[mirror_ubuntu-zesty-kernel.git] / drivers / net / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/module.h>
29#include <linux/types.h>
30#include <linux/init.h>
31#include <linux/vmalloc.h>
32#include <linux/pagemap.h>
33#include <linux/netdevice.h>
9d5c8243
AK		 34#include <linux/ipv6.h>
35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
37#include <linux/mii.h>
38#include <linux/ethtool.h>
39#include <linux/if_vlan.h>
40#include <linux/pci.h>
c54106bb 41#include <linux/pci-aspm.h>
9d5c8243
AK		 42#include <linux/delay.h>
43#include <linux/interrupt.h>
44#include <linux/if_ether.h>
40a914fa 45#include <linux/aer.h>
421e02f0 46#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 47#include <linux/dca.h>
48#endif
9d5c8243
AK		 49#include "igb.h"
50
0024fd00 51#define DRV_VERSION "1.2.45-k2"
9d5c8243
AK		 52char igb_driver_name[] = "igb";
53char igb_driver_version[] = DRV_VERSION;
54static const char igb_driver_string[] =
55 "Intel(R) Gigabit Ethernet Network Driver";
2d064c06 56static const char igb_copyright[] = "Copyright (c) 2008 Intel Corporation.";
9d5c8243 57
9d5c8243
AK		 58static const struct e1000_info *igb_info_tbl[] = {
59 [board_82575] = &e1000_82575_info,
60};
61
62static struct pci_device_id igb_pci_tbl[] = {
2d064c06
AD		 63 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
9d5c8243
AK		 66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
69 /* required last entry */
70 {0, }
71};
72
73MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
74
75void igb_reset(struct igb_adapter *);
76static int igb_setup_all_tx_resources(struct igb_adapter *);
77static int igb_setup_all_rx_resources(struct igb_adapter *);
78static void igb_free_all_tx_resources(struct igb_adapter *);
79static void igb_free_all_rx_resources(struct igb_adapter *);
9d5c8243
AK		 80void igb_update_stats(struct igb_adapter *);
81static int igb_probe(struct pci_dev *, const struct pci_device_id *);
82static void __devexit igb_remove(struct pci_dev *pdev);
83static int igb_sw_init(struct igb_adapter *);
84static int igb_open(struct net_device *);
85static int igb_close(struct net_device *);
86static void igb_configure_tx(struct igb_adapter *);
87static void igb_configure_rx(struct igb_adapter *);
88static void igb_setup_rctl(struct igb_adapter *);
89static void igb_clean_all_tx_rings(struct igb_adapter *);
90static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 91static void igb_clean_tx_ring(struct igb_ring *);
92static void igb_clean_rx_ring(struct igb_ring *);
9d5c8243
AK		 93static void igb_set_multi(struct net_device *);
94static void igb_update_phy_info(unsigned long);
95static void igb_watchdog(unsigned long);
96static void igb_watchdog_task(struct work_struct *);
97static int igb_xmit_frame_ring_adv(struct sk_buff *, struct net_device *,
98 struct igb_ring *);
99static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
100static struct net_device_stats *igb_get_stats(struct net_device *);
101static int igb_change_mtu(struct net_device *, int);
102static int igb_set_mac(struct net_device *, void *);
103static irqreturn_t igb_intr(int irq, void *);
104static irqreturn_t igb_intr_msi(int irq, void *);
105static irqreturn_t igb_msix_other(int irq, void *);
106static irqreturn_t igb_msix_rx(int irq, void *);
107static irqreturn_t igb_msix_tx(int irq, void *);
108static int igb_clean_rx_ring_msix(struct napi_struct *, int);
421e02f0 109#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 110static void igb_update_rx_dca(struct igb_ring *);
111static void igb_update_tx_dca(struct igb_ring *);
112static void igb_setup_dca(struct igb_adapter *);
421e02f0 113#endif /* CONFIG_IGB_DCA */
3b644cf6 114static bool igb_clean_tx_irq(struct igb_ring *);
661086df 115static int igb_poll(struct napi_struct *, int);
3b644cf6
MW		 116static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int);
117static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
9d5c8243
AK		 118static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
119static void igb_tx_timeout(struct net_device *);
120static void igb_reset_task(struct work_struct *);
121static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
122static void igb_vlan_rx_add_vid(struct net_device *, u16);
123static void igb_vlan_rx_kill_vid(struct net_device *, u16);
124static void igb_restore_vlan(struct igb_adapter *);
125
126static int igb_suspend(struct pci_dev *, pm_message_t);
127#ifdef CONFIG_PM
128static int igb_resume(struct pci_dev *);
129#endif
130static void igb_shutdown(struct pci_dev *);
421e02f0 131#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 132static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
133static struct notifier_block dca_notifier = {
134 .notifier_call = igb_notify_dca,
135 .next = NULL,
136 .priority = 0
137};
138#endif
9d5c8243
AK		 139
140#ifdef CONFIG_NET_POLL_CONTROLLER
141/* for netdump / net console */
142static void igb_netpoll(struct net_device *);
143#endif
144
145static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
146 pci_channel_state_t);
147static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
148static void igb_io_resume(struct pci_dev *);
149
150static struct pci_error_handlers igb_err_handler = {
151 .error_detected = igb_io_error_detected,
152 .slot_reset = igb_io_slot_reset,
153 .resume = igb_io_resume,
154};
155
156
157static struct pci_driver igb_driver = {
158 .name = igb_driver_name,
159 .id_table = igb_pci_tbl,
160 .probe = igb_probe,
161 .remove = __devexit_p(igb_remove),
162#ifdef CONFIG_PM
163 /* Power Managment Hooks */
164 .suspend = igb_suspend,
165 .resume = igb_resume,
166#endif
167 .shutdown = igb_shutdown,
168 .err_handler = &igb_err_handler
169};
170
7dfc16fa
AD		 171static int global_quad_port_a; /* global quad port a indication */
172
9d5c8243
AK		 173MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
174MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
175MODULE_LICENSE("GPL");
176MODULE_VERSION(DRV_VERSION);
177
178#ifdef DEBUG
179/**
180 * igb_get_hw_dev_name - return device name string
181 * used by hardware layer to print debugging information
182 **/
183char *igb_get_hw_dev_name(struct e1000_hw *hw)
184{
185 struct igb_adapter *adapter = hw->back;
186 return adapter->netdev->name;
187}
188#endif
189
190/**
191 * igb_init_module - Driver Registration Routine
192 *
193 * igb_init_module is the first routine called when the driver is
194 * loaded. All it does is register with the PCI subsystem.
195 **/
196static int __init igb_init_module(void)
197{
198 int ret;
199 printk(KERN_INFO "%s - version %s\n",
200 igb_driver_string, igb_driver_version);
201
202 printk(KERN_INFO "%s\n", igb_copyright);
203
7dfc16fa
AD		 204 global_quad_port_a = 0;
205
421e02f0 206#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 207 dca_register_notify(&dca_notifier);
208#endif
bbd98fe4
AD		 209
210 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 211 return ret;
212}
213
214module_init(igb_init_module);
215
216/**
217 * igb_exit_module - Driver Exit Cleanup Routine
218 *
219 * igb_exit_module is called just before the driver is removed
220 * from memory.
221 **/
222static void __exit igb_exit_module(void)
223{
421e02f0 224#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 225 dca_unregister_notify(&dca_notifier);
226#endif
9d5c8243
AK		 227 pci_unregister_driver(&igb_driver);
228}
229
230module_exit(igb_exit_module);
231
26bc19ec
AD		 232#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
233/**
234 * igb_cache_ring_register - Descriptor ring to register mapping
235 * @adapter: board private structure to initialize
236 *
237 * Once we know the feature-set enabled for the device, we'll cache
238 * the register offset the descriptor ring is assigned to.
239 **/
240static void igb_cache_ring_register(struct igb_adapter *adapter)
241{
242 int i;
243
244 switch (adapter->hw.mac.type) {
245 case e1000_82576:
246 /* The queues are allocated for virtualization such that VF 0
247 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
248 * In order to avoid collision we start at the first free queue
249 * and continue consuming queues in the same sequence
250 */
251 for (i = 0; i < adapter->num_rx_queues; i++)
252 adapter->rx_ring[i].reg_idx = Q_IDX_82576(i);
253 for (i = 0; i < adapter->num_tx_queues; i++)
254 adapter->tx_ring[i].reg_idx = Q_IDX_82576(i);
255 break;
256 case e1000_82575:
257 default:
258 for (i = 0; i < adapter->num_rx_queues; i++)
259 adapter->rx_ring[i].reg_idx = i;
260 for (i = 0; i < adapter->num_tx_queues; i++)
261 adapter->tx_ring[i].reg_idx = i;
262 break;
263 }
264}
265
9d5c8243
AK		 266/**
267 * igb_alloc_queues - Allocate memory for all rings
268 * @adapter: board private structure to initialize
269 *
270 * We allocate one ring per queue at run-time since we don't know the
271 * number of queues at compile-time.
272 **/
273static int igb_alloc_queues(struct igb_adapter *adapter)
274{
275 int i;
276
277 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
278 sizeof(struct igb_ring), GFP_KERNEL);
279 if (!adapter->tx_ring)
280 return -ENOMEM;
281
282 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
283 sizeof(struct igb_ring), GFP_KERNEL);
284 if (!adapter->rx_ring) {
285 kfree(adapter->tx_ring);
286 return -ENOMEM;
287 }
288
6eb5a7f1
AD		 289 adapter->rx_ring->buddy = adapter->tx_ring;
290
661086df
PWJ		 291 for (i = 0; i < adapter->num_tx_queues; i++) {
292 struct igb_ring *ring = &(adapter->tx_ring[i]);
68fd9910 293 ring->count = adapter->tx_ring_count;
661086df
PWJ		 294 ring->adapter = adapter;
295 ring->queue_index = i;
296 }
9d5c8243
AK		 297 for (i = 0; i < adapter->num_rx_queues; i++) {
298 struct igb_ring *ring = &(adapter->rx_ring[i]);
68fd9910 299 ring->count = adapter->rx_ring_count;
9d5c8243 300 ring->adapter = adapter;
844290e5 301 ring->queue_index = i;
9d5c8243
AK		 302 ring->itr_register = E1000_ITR;
303
844290e5 304 /* set a default napi handler for each rx_ring */
661086df 305 netif_napi_add(adapter->netdev, &ring->napi, igb_poll, 64);
9d5c8243 306 }
26bc19ec
AD		 307
308 igb_cache_ring_register(adapter);
9d5c8243
AK		 309 return 0;
310}
311
a88f10ec
AD		 312static void igb_free_queues(struct igb_adapter *adapter)
313{
314 int i;
315
316 for (i = 0; i < adapter->num_rx_queues; i++)
317 netif_napi_del(&adapter->rx_ring[i].napi);
318
319 kfree(adapter->tx_ring);
320 kfree(adapter->rx_ring);
321}
322
9d5c8243
AK		 323#define IGB_N0_QUEUE -1
324static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
325 int tx_queue, int msix_vector)
326{
327 u32 msixbm = 0;
328 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 329 u32 ivar, index;
330
331 switch (hw->mac.type) {
332 case e1000_82575:
9d5c8243
AK		 333 /* The 82575 assigns vectors using a bitmask, which matches the
334 bitmask for the EICR/EIMS/EIMC registers. To assign one
335 or more queues to a vector, we write the appropriate bits
336 into the MSIXBM register for that vector. */
337 if (rx_queue > IGB_N0_QUEUE) {
338 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
339 adapter->rx_ring[rx_queue].eims_value = msixbm;
340 }
341 if (tx_queue > IGB_N0_QUEUE) {
342 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
343 adapter->tx_ring[tx_queue].eims_value =
344 E1000_EICR_TX_QUEUE0 << tx_queue;
345 }
346 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
2d064c06
AD		 347 break;
348 case e1000_82576:
26bc19ec 349 /* 82576 uses a table-based method for assigning vectors.
2d064c06
AD		 350 Each queue has a single entry in the table to which we write
351 a vector number along with a "valid" bit. Sadly, the layout
352 of the table is somewhat counterintuitive. */
353 if (rx_queue > IGB_N0_QUEUE) {
26bc19ec 354 index = (rx_queue >> 1);
2d064c06 355 ivar = array_rd32(E1000_IVAR0, index);
26bc19ec 356 if (rx_queue & 0x1) {
2d064c06
AD		 357 /* vector goes into third byte of register */
358 ivar = ivar & 0xFF00FFFF;
359 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
26bc19ec
AD		 360 } else {
361 /* vector goes into low byte of register */
362 ivar = ivar & 0xFFFFFF00;
363 ivar |= msix_vector | E1000_IVAR_VALID;
2d064c06
AD		 364 }
365 adapter->rx_ring[rx_queue].eims_value= 1 << msix_vector;
366 array_wr32(E1000_IVAR0, index, ivar);
367 }
368 if (tx_queue > IGB_N0_QUEUE) {
26bc19ec 369 index = (tx_queue >> 1);
2d064c06 370 ivar = array_rd32(E1000_IVAR0, index);
26bc19ec 371 if (tx_queue & 0x1) {
2d064c06
AD		 372 /* vector goes into high byte of register */
373 ivar = ivar & 0x00FFFFFF;
374 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
26bc19ec
AD		 375 } else {
376 /* vector goes into second byte of register */
377 ivar = ivar & 0xFFFF00FF;
378 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
2d064c06
AD		 379 }
380 adapter->tx_ring[tx_queue].eims_value= 1 << msix_vector;
381 array_wr32(E1000_IVAR0, index, ivar);
382 }
383 break;
384 default:
385 BUG();
386 break;
387 }
9d5c8243
AK		 388}
389
390/**
391 * igb_configure_msix - Configure MSI-X hardware
392 *
393 * igb_configure_msix sets up the hardware to properly
394 * generate MSI-X interrupts.
395 **/
396static void igb_configure_msix(struct igb_adapter *adapter)
397{
398 u32 tmp;
399 int i, vector = 0;
400 struct e1000_hw *hw = &adapter->hw;
401
402 adapter->eims_enable_mask = 0;
2d064c06
AD		 403 if (hw->mac.type == e1000_82576)
404 /* Turn on MSI-X capability first, or our settings
405 * won't stick. And it will take days to debug. */
406 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
407 E1000_GPIE_PBA | E1000_GPIE_EIAME |
408 E1000_GPIE_NSICR);
9d5c8243
AK		 409
410 for (i = 0; i < adapter->num_tx_queues; i++) {
411 struct igb_ring *tx_ring = &adapter->tx_ring[i];
412 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
413 adapter->eims_enable_mask |= tx_ring->eims_value;
414 if (tx_ring->itr_val)
6eb5a7f1 415 writel(tx_ring->itr_val,
9d5c8243
AK		 416 hw->hw_addr + tx_ring->itr_register);
417 else
418 writel(1, hw->hw_addr + tx_ring->itr_register);
419 }
420
421 for (i = 0; i < adapter->num_rx_queues; i++) {
422 struct igb_ring *rx_ring = &adapter->rx_ring[i];
25ac3c24 423 rx_ring->buddy = NULL;
9d5c8243
AK		 424 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
425 adapter->eims_enable_mask |= rx_ring->eims_value;
426 if (rx_ring->itr_val)
6eb5a7f1 427 writel(rx_ring->itr_val,
9d5c8243
AK		 428 hw->hw_addr + rx_ring->itr_register);
429 else
430 writel(1, hw->hw_addr + rx_ring->itr_register);
431 }
432
433
434 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 435 switch (hw->mac.type) {
436 case e1000_82575:
9d5c8243
AK		 437 array_wr32(E1000_MSIXBM(0), vector++,
438 E1000_EIMS_OTHER);
439
9d5c8243
AK		 440 tmp = rd32(E1000_CTRL_EXT);
441 /* enable MSI-X PBA support*/
442 tmp |= E1000_CTRL_EXT_PBA_CLR;
443
444 /* Auto-Mask interrupts upon ICR read. */
445 tmp |= E1000_CTRL_EXT_EIAME;
446 tmp |= E1000_CTRL_EXT_IRCA;
447
448 wr32(E1000_CTRL_EXT, tmp);
449 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
844290e5 450 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 451
2d064c06
AD		 452 break;
453
454 case e1000_82576:
455 tmp = (vector++ | E1000_IVAR_VALID) << 8;
456 wr32(E1000_IVAR_MISC, tmp);
457
458 adapter->eims_enable_mask = (1 << (vector)) - 1;
459 adapter->eims_other = 1 << (vector - 1);
460 break;
461 default:
462 /* do nothing, since nothing else supports MSI-X */
463 break;
464 } /* switch (hw->mac.type) */
9d5c8243
AK		 465 wrfl();
466}
467
468/**
469 * igb_request_msix - Initialize MSI-X interrupts
470 *
471 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
472 * kernel.
473 **/
474static int igb_request_msix(struct igb_adapter *adapter)
475{
476 struct net_device *netdev = adapter->netdev;
477 int i, err = 0, vector = 0;
478
479 vector = 0;
480
481 for (i = 0; i < adapter->num_tx_queues; i++) {
482 struct igb_ring *ring = &(adapter->tx_ring[i]);
cb7b48f6 483 sprintf(ring->name, "%s-tx-%d", netdev->name, i);
9d5c8243
AK		 484 err = request_irq(adapter->msix_entries[vector].vector,
485 &igb_msix_tx, 0, ring->name,
486 &(adapter->tx_ring[i]));
487 if (err)
488 goto out;
489 ring->itr_register = E1000_EITR(0) + (vector << 2);
6eb5a7f1 490 ring->itr_val = 976; /* ~4000 ints/sec */
9d5c8243
AK		 491 vector++;
492 }
493 for (i = 0; i < adapter->num_rx_queues; i++) {
494 struct igb_ring *ring = &(adapter->rx_ring[i]);
495 if (strlen(netdev->name) < (IFNAMSIZ - 5))
cb7b48f6 496 sprintf(ring->name, "%s-rx-%d", netdev->name, i);
9d5c8243
AK		 497 else
498 memcpy(ring->name, netdev->name, IFNAMSIZ);
499 err = request_irq(adapter->msix_entries[vector].vector,
500 &igb_msix_rx, 0, ring->name,
501 &(adapter->rx_ring[i]));
502 if (err)
503 goto out;
504 ring->itr_register = E1000_EITR(0) + (vector << 2);
505 ring->itr_val = adapter->itr;
844290e5
PW		 506 /* overwrite the poll routine for MSIX, we've already done
507 * netif_napi_add */
508 ring->napi.poll = &igb_clean_rx_ring_msix;
9d5c8243
AK		 509 vector++;
510 }
511
512 err = request_irq(adapter->msix_entries[vector].vector,
513 &igb_msix_other, 0, netdev->name, netdev);
514 if (err)
515 goto out;
516
9d5c8243
AK		 517 igb_configure_msix(adapter);
518 return 0;
519out:
520 return err;
521}
522
523static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
524{
525 if (adapter->msix_entries) {
526 pci_disable_msix(adapter->pdev);
527 kfree(adapter->msix_entries);
528 adapter->msix_entries = NULL;
7dfc16fa 529 } else if (adapter->flags & IGB_FLAG_HAS_MSI)
9d5c8243
AK		 530 pci_disable_msi(adapter->pdev);
531 return;
532}
533
534
535/**
536 * igb_set_interrupt_capability - set MSI or MSI-X if supported
537 *
538 * Attempt to configure interrupts using the best available
539 * capabilities of the hardware and kernel.
540 **/
541static void igb_set_interrupt_capability(struct igb_adapter *adapter)
542{
543 int err;
544 int numvecs, i;
545
83b7180d
AD		 546 /* Number of supported queues. */
547 /* Having more queues than CPUs doesn't make sense. */
548 adapter->num_rx_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
549 adapter->num_tx_queues = min_t(u32, IGB_MAX_TX_QUEUES, num_online_cpus());
550
9d5c8243
AK		 551 numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1;
552 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
553 GFP_KERNEL);
554 if (!adapter->msix_entries)
555 goto msi_only;
556
557 for (i = 0; i < numvecs; i++)
558 adapter->msix_entries[i].entry = i;
559
560 err = pci_enable_msix(adapter->pdev,
561 adapter->msix_entries,
562 numvecs);
563 if (err == 0)
34a20e89 564 goto out;
9d5c8243
AK		 565
566 igb_reset_interrupt_capability(adapter);
567
568 /* If we can't do MSI-X, try MSI */
569msi_only:
570 adapter->num_rx_queues = 1;
661086df 571 adapter->num_tx_queues = 1;
9d5c8243 572 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 573 adapter->flags |= IGB_FLAG_HAS_MSI;
34a20e89 574out:
661086df 575 /* Notify the stack of the (possibly) reduced Tx Queue count. */
fd2ea0a7 576 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
9d5c8243
AK		 577 return;
578}
579
580/**
581 * igb_request_irq - initialize interrupts
582 *
583 * Attempts to configure interrupts using the best available
584 * capabilities of the hardware and kernel.
585 **/
586static int igb_request_irq(struct igb_adapter *adapter)
587{
588 struct net_device *netdev = adapter->netdev;
589 struct e1000_hw *hw = &adapter->hw;
590 int err = 0;
591
592 if (adapter->msix_entries) {
593 err = igb_request_msix(adapter);
844290e5 594 if (!err)
9d5c8243 595 goto request_done;
9d5c8243
AK		 596 /* fall back to MSI */
597 igb_reset_interrupt_capability(adapter);
598 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 599 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 600 igb_free_all_tx_resources(adapter);
601 igb_free_all_rx_resources(adapter);
602 adapter->num_rx_queues = 1;
603 igb_alloc_queues(adapter);
844290e5 604 } else {
2d064c06
AD		 605 switch (hw->mac.type) {
606 case e1000_82575:
607 wr32(E1000_MSIXBM(0),
608 (E1000_EICR_RX_QUEUE0 | E1000_EIMS_OTHER));
609 break;
610 case e1000_82576:
611 wr32(E1000_IVAR0, E1000_IVAR_VALID);
612 break;
613 default:
614 break;
615 }
9d5c8243 616 }
844290e5 617
7dfc16fa 618 if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243
AK		 619 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
620 netdev->name, netdev);
621 if (!err)
622 goto request_done;
623 /* fall back to legacy interrupts */
624 igb_reset_interrupt_capability(adapter);
7dfc16fa 625 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 626 }
627
628 err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
629 netdev->name, netdev);
630
6cb5e577 631 if (err)
9d5c8243
AK		 632 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
633 err);
9d5c8243
AK		 634
635request_done:
636 return err;
637}
638
639static void igb_free_irq(struct igb_adapter *adapter)
640{
641 struct net_device *netdev = adapter->netdev;
642
643 if (adapter->msix_entries) {
644 int vector = 0, i;
645
646 for (i = 0; i < adapter->num_tx_queues; i++)
647 free_irq(adapter->msix_entries[vector++].vector,
648 &(adapter->tx_ring[i]));
649 for (i = 0; i < adapter->num_rx_queues; i++)
650 free_irq(adapter->msix_entries[vector++].vector,
651 &(adapter->rx_ring[i]));
652
653 free_irq(adapter->msix_entries[vector++].vector, netdev);
654 return;
655 }
656
657 free_irq(adapter->pdev->irq, netdev);
658}
659
660/**
661 * igb_irq_disable - Mask off interrupt generation on the NIC
662 * @adapter: board private structure
663 **/
664static void igb_irq_disable(struct igb_adapter *adapter)
665{
666 struct e1000_hw *hw = &adapter->hw;
667
668 if (adapter->msix_entries) {
844290e5 669 wr32(E1000_EIAM, 0);
9d5c8243
AK		 670 wr32(E1000_EIMC, ~0);
671 wr32(E1000_EIAC, 0);
672 }
844290e5
PW		 673
674 wr32(E1000_IAM, 0);
9d5c8243
AK		 675 wr32(E1000_IMC, ~0);
676 wrfl();
677 synchronize_irq(adapter->pdev->irq);
678}
679
680/**
681 * igb_irq_enable - Enable default interrupt generation settings
682 * @adapter: board private structure
683 **/
684static void igb_irq_enable(struct igb_adapter *adapter)
685{
686 struct e1000_hw *hw = &adapter->hw;
687
688 if (adapter->msix_entries) {
844290e5
PW		 689 wr32(E1000_EIAC, adapter->eims_enable_mask);
690 wr32(E1000_EIAM, adapter->eims_enable_mask);
691 wr32(E1000_EIMS, adapter->eims_enable_mask);
9d5c8243 692 wr32(E1000_IMS, E1000_IMS_LSC);
844290e5
PW		 693 } else {
694 wr32(E1000_IMS, IMS_ENABLE_MASK);
695 wr32(E1000_IAM, IMS_ENABLE_MASK);
696 }
9d5c8243
AK		 697}
698
699static void igb_update_mng_vlan(struct igb_adapter *adapter)
700{
701 struct net_device *netdev = adapter->netdev;
702 u16 vid = adapter->hw.mng_cookie.vlan_id;
703 u16 old_vid = adapter->mng_vlan_id;
704 if (adapter->vlgrp) {
705 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
706 if (adapter->hw.mng_cookie.status &
707 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
708 igb_vlan_rx_add_vid(netdev, vid);
709 adapter->mng_vlan_id = vid;
710 } else
711 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
712
713 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
714 (vid != old_vid) &&
715 !vlan_group_get_device(adapter->vlgrp, old_vid))
716 igb_vlan_rx_kill_vid(netdev, old_vid);
717 } else
718 adapter->mng_vlan_id = vid;
719 }
720}
721
722/**
723 * igb_release_hw_control - release control of the h/w to f/w
724 * @adapter: address of board private structure
725 *
726 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
727 * For ASF and Pass Through versions of f/w this means that the
728 * driver is no longer loaded.
729 *
730 **/
731static void igb_release_hw_control(struct igb_adapter *adapter)
732{
733 struct e1000_hw *hw = &adapter->hw;
734 u32 ctrl_ext;
735
736 /* Let firmware take over control of h/w */
737 ctrl_ext = rd32(E1000_CTRL_EXT);
738 wr32(E1000_CTRL_EXT,
739 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
740}
741
742
743/**
744 * igb_get_hw_control - get control of the h/w from f/w
745 * @adapter: address of board private structure
746 *
747 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
748 * For ASF and Pass Through versions of f/w this means that
749 * the driver is loaded.
750 *
751 **/
752static void igb_get_hw_control(struct igb_adapter *adapter)
753{
754 struct e1000_hw *hw = &adapter->hw;
755 u32 ctrl_ext;
756
757 /* Let firmware know the driver has taken over */
758 ctrl_ext = rd32(E1000_CTRL_EXT);
759 wr32(E1000_CTRL_EXT,
760 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
761}
762
9d5c8243
AK		 763/**
764 * igb_configure - configure the hardware for RX and TX
765 * @adapter: private board structure
766 **/
767static void igb_configure(struct igb_adapter *adapter)
768{
769 struct net_device *netdev = adapter->netdev;
770 int i;
771
772 igb_get_hw_control(adapter);
773 igb_set_multi(netdev);
774
775 igb_restore_vlan(adapter);
9d5c8243
AK		 776
777 igb_configure_tx(adapter);
778 igb_setup_rctl(adapter);
779 igb_configure_rx(adapter);
662d7205
AD		 780
781 igb_rx_fifo_flush_82575(&adapter->hw);
782
9d5c8243
AK		 783 /* call IGB_DESC_UNUSED which always leaves
784 * at least 1 descriptor unused to make sure
785 * next_to_use != next_to_clean */
786 for (i = 0; i < adapter->num_rx_queues; i++) {
787 struct igb_ring *ring = &adapter->rx_ring[i];
3b644cf6 788 igb_alloc_rx_buffers_adv(ring, IGB_DESC_UNUSED(ring));
9d5c8243
AK		 789 }
790
791
792 adapter->tx_queue_len = netdev->tx_queue_len;
793}
794
795
796/**
797 * igb_up - Open the interface and prepare it to handle traffic
798 * @adapter: board private structure
799 **/
800
801int igb_up(struct igb_adapter *adapter)
802{
803 struct e1000_hw *hw = &adapter->hw;
804 int i;
805
806 /* hardware has been reset, we need to reload some things */
807 igb_configure(adapter);
808
809 clear_bit(__IGB_DOWN, &adapter->state);
810
844290e5
PW		 811 for (i = 0; i < adapter->num_rx_queues; i++)
812 napi_enable(&adapter->rx_ring[i].napi);
813 if (adapter->msix_entries)
9d5c8243 814 igb_configure_msix(adapter);
9d5c8243
AK		 815
816 /* Clear any pending interrupts. */
817 rd32(E1000_ICR);
818 igb_irq_enable(adapter);
819
820 /* Fire a link change interrupt to start the watchdog. */
821 wr32(E1000_ICS, E1000_ICS_LSC);
822 return 0;
823}
824
825void igb_down(struct igb_adapter *adapter)
826{
827 struct e1000_hw *hw = &adapter->hw;
828 struct net_device *netdev = adapter->netdev;
829 u32 tctl, rctl;
830 int i;
831
832 /* signal that we're down so the interrupt handler does not
833 * reschedule our watchdog timer */
834 set_bit(__IGB_DOWN, &adapter->state);
835
836 /* disable receives in the hardware */
837 rctl = rd32(E1000_RCTL);
838 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
839 /* flush and sleep below */
840
fd2ea0a7 841 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 842
843 /* disable transmits in the hardware */
844 tctl = rd32(E1000_TCTL);
845 tctl &= ~E1000_TCTL_EN;
846 wr32(E1000_TCTL, tctl);
847 /* flush both disables and wait for them to finish */
848 wrfl();
849 msleep(10);
850
844290e5
PW		 851 for (i = 0; i < adapter->num_rx_queues; i++)
852 napi_disable(&adapter->rx_ring[i].napi);
9d5c8243 853
9d5c8243
AK		 854 igb_irq_disable(adapter);
855
856 del_timer_sync(&adapter->watchdog_timer);
857 del_timer_sync(&adapter->phy_info_timer);
858
859 netdev->tx_queue_len = adapter->tx_queue_len;
860 netif_carrier_off(netdev);
861 adapter->link_speed = 0;
862 adapter->link_duplex = 0;
863
3023682e
JK		 864 if (!pci_channel_offline(adapter->pdev))
865 igb_reset(adapter);
9d5c8243
AK		 866 igb_clean_all_tx_rings(adapter);
867 igb_clean_all_rx_rings(adapter);
868}
869
870void igb_reinit_locked(struct igb_adapter *adapter)
871{
872 WARN_ON(in_interrupt());
873 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
874 msleep(1);
875 igb_down(adapter);
876 igb_up(adapter);
877 clear_bit(__IGB_RESETTING, &adapter->state);
878}
879
880void igb_reset(struct igb_adapter *adapter)
881{
882 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 883 struct e1000_mac_info *mac = &hw->mac;
884 struct e1000_fc_info *fc = &hw->fc;
9d5c8243
AK		 885 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
886 u16 hwm;
887
888 /* Repartition Pba for greater than 9k mtu
889 * To take effect CTRL.RST is required.
890 */
2d064c06 891 if (mac->type != e1000_82576) {
9d5c8243 892 pba = E1000_PBA_34K;
2d064c06
AD		 893 }
894 else {
895 pba = E1000_PBA_64K;
896 }
9d5c8243 897
2d064c06
AD		 898 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
899 (mac->type < e1000_82576)) {
9d5c8243
AK		 900 /* adjust PBA for jumbo frames */
901 wr32(E1000_PBA, pba);
902
903 /* To maintain wire speed transmits, the Tx FIFO should be
904 * large enough to accommodate two full transmit packets,
905 * rounded up to the next 1KB and expressed in KB. Likewise,
906 * the Rx FIFO should be large enough to accommodate at least
907 * one full receive packet and is similarly rounded up and
908 * expressed in KB. */
909 pba = rd32(E1000_PBA);
910 /* upper 16 bits has Tx packet buffer allocation size in KB */
911 tx_space = pba >> 16;
912 /* lower 16 bits has Rx packet buffer allocation size in KB */
913 pba &= 0xffff;
914 /* the tx fifo also stores 16 bytes of information about the tx
915 * but don't include ethernet FCS because hardware appends it */
916 min_tx_space = (adapter->max_frame_size +
917 sizeof(struct e1000_tx_desc) -
918 ETH_FCS_LEN) * 2;
919 min_tx_space = ALIGN(min_tx_space, 1024);
920 min_tx_space >>= 10;
921 /* software strips receive CRC, so leave room for it */
922 min_rx_space = adapter->max_frame_size;
923 min_rx_space = ALIGN(min_rx_space, 1024);
924 min_rx_space >>= 10;
925
926 /* If current Tx allocation is less than the min Tx FIFO size,
927 * and the min Tx FIFO size is less than the current Rx FIFO
928 * allocation, take space away from current Rx allocation */
929 if (tx_space < min_tx_space &&
930 ((min_tx_space - tx_space) < pba)) {
931 pba = pba - (min_tx_space - tx_space);
932
933 /* if short on rx space, rx wins and must trump tx
934 * adjustment */
935 if (pba < min_rx_space)
936 pba = min_rx_space;
937 }
2d064c06 938 wr32(E1000_PBA, pba);
9d5c8243 939 }
9d5c8243
AK		 940
941 /* flow control settings */
942 /* The high water mark must be low enough to fit one full frame
943 * (or the size used for early receive) above it in the Rx FIFO.
944 * Set it to the lower of:
945 * - 90% of the Rx FIFO size, or
946 * - the full Rx FIFO size minus one full frame */
947 hwm = min(((pba << 10) * 9 / 10),
2d064c06 948 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 949
2d064c06
AD		 950 if (mac->type < e1000_82576) {
951 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
952 fc->low_water = fc->high_water - 8;
953 } else {
954 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
955 fc->low_water = fc->high_water - 16;
956 }
9d5c8243
AK		 957 fc->pause_time = 0xFFFF;
958 fc->send_xon = 1;
959 fc->type = fc->original_type;
960
961 /* Allow time for pending master requests to run */
962 adapter->hw.mac.ops.reset_hw(&adapter->hw);
963 wr32(E1000_WUC, 0);
964
965 if (adapter->hw.mac.ops.init_hw(&adapter->hw))
966 dev_err(&adapter->pdev->dev, "Hardware Error\n");
967
968 igb_update_mng_vlan(adapter);
969
970 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
971 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
972
973 igb_reset_adaptive(&adapter->hw);
f5f4cf08 974 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 975}
976
2e5c6922
SH		 977static const struct net_device_ops igb_netdev_ops = {
978 .ndo_open = igb_open,
979 .ndo_stop = igb_close,
00829823 980 .ndo_start_xmit = igb_xmit_frame_adv,
2e5c6922
SH		 981 .ndo_get_stats = igb_get_stats,
982 .ndo_set_multicast_list = igb_set_multi,
983 .ndo_set_mac_address = igb_set_mac,
984 .ndo_change_mtu = igb_change_mtu,
985 .ndo_do_ioctl = igb_ioctl,
986 .ndo_tx_timeout = igb_tx_timeout,
987 .ndo_validate_addr = eth_validate_addr,
988 .ndo_vlan_rx_register = igb_vlan_rx_register,
989 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
990 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
991#ifdef CONFIG_NET_POLL_CONTROLLER
992 .ndo_poll_controller = igb_netpoll,
993#endif
994};
995
9d5c8243
AK		 996/**
997 * igb_probe - Device Initialization Routine
998 * @pdev: PCI device information struct
999 * @ent: entry in igb_pci_tbl
1000 *
1001 * Returns 0 on success, negative on failure
1002 *
1003 * igb_probe initializes an adapter identified by a pci_dev structure.
1004 * The OS initialization, configuring of the adapter private structure,
1005 * and a hardware reset occur.
1006 **/
1007static int __devinit igb_probe(struct pci_dev *pdev,
1008 const struct pci_device_id *ent)
1009{
1010 struct net_device *netdev;
1011 struct igb_adapter *adapter;
1012 struct e1000_hw *hw;
c54106bb 1013 struct pci_dev *us_dev;
9d5c8243
AK		 1014 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1015 unsigned long mmio_start, mmio_len;
c54106bb
AD		 1016 int i, err, pci_using_dac, pos;
1017 u16 eeprom_data = 0, state = 0;
9d5c8243
AK		 1018 u16 eeprom_apme_mask = IGB_EEPROM_APME;
1019 u32 part_num;
1020
aed5dec3 1021 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 1022 if (err)
1023 return err;
1024
1025 pci_using_dac = 0;
1026 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
1027 if (!err) {
1028 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1029 if (!err)
1030 pci_using_dac = 1;
1031 } else {
1032 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1033 if (err) {
1034 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1035 if (err) {
1036 dev_err(&pdev->dev, "No usable DMA "
1037 "configuration, aborting\n");
1038 goto err_dma;
1039 }
1040 }
1041 }
1042
c54106bb
AD		 1043 /* 82575 requires that the pci-e link partner disable the L0s state */
1044 switch (pdev->device) {
1045 case E1000_DEV_ID_82575EB_COPPER:
1046 case E1000_DEV_ID_82575EB_FIBER_SERDES:
1047 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1048 us_dev = pdev->bus->self;
1049 pos = pci_find_capability(us_dev, PCI_CAP_ID_EXP);
1050 if (pos) {
1051 pci_read_config_word(us_dev, pos + PCI_EXP_LNKCTL,
1052 &state);
1053 state &= ~PCIE_LINK_STATE_L0S;
1054 pci_write_config_word(us_dev, pos + PCI_EXP_LNKCTL,
1055 state);
ac450208
BH		 1056 dev_info(&pdev->dev,
1057 "Disabling ASPM L0s upstream switch port %s\n",
1058 pci_name(us_dev));
c54106bb
AD		 1059 }
1060 default:
1061 break;
1062 }
1063
aed5dec3
AD		 1064 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1065 IORESOURCE_MEM),
1066 igb_driver_name);
9d5c8243
AK		 1067 if (err)
1068 goto err_pci_reg;
1069
ea943d41
JK		 1070 err = pci_enable_pcie_error_reporting(pdev);
1071 if (err) {
1072 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
1073 "0x%x\n", err);
1074 /* non-fatal, continue */
1075 }
40a914fa 1076
9d5c8243 1077 pci_set_master(pdev);
c682fc23 1078 pci_save_state(pdev);
9d5c8243
AK		 1079
1080 err = -ENOMEM;
661086df 1081 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), IGB_MAX_TX_QUEUES);
9d5c8243
AK		 1082 if (!netdev)
1083 goto err_alloc_etherdev;
1084
1085 SET_NETDEV_DEV(netdev, &pdev->dev);
1086
1087 pci_set_drvdata(pdev, netdev);
1088 adapter = netdev_priv(netdev);
1089 adapter->netdev = netdev;
1090 adapter->pdev = pdev;
1091 hw = &adapter->hw;
1092 hw->back = adapter;
1093 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
1094
1095 mmio_start = pci_resource_start(pdev, 0);
1096 mmio_len = pci_resource_len(pdev, 0);
1097
1098 err = -EIO;
1099 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
1100 if (!adapter->hw.hw_addr)
1101 goto err_ioremap;
1102
2e5c6922 1103 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 1104 igb_set_ethtool_ops(netdev);
9d5c8243 1105 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 1106
1107 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1108
1109 netdev->mem_start = mmio_start;
1110 netdev->mem_end = mmio_start + mmio_len;
1111
9d5c8243
AK		 1112 /* PCI config space info */
1113 hw->vendor_id = pdev->vendor;
1114 hw->device_id = pdev->device;
1115 hw->revision_id = pdev->revision;
1116 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1117 hw->subsystem_device_id = pdev->subsystem_device;
1118
1119 /* setup the private structure */
1120 hw->back = adapter;
1121 /* Copy the default MAC, PHY and NVM function pointers */
1122 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1123 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1124 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1125 /* Initialize skew-specific constants */
1126 err = ei->get_invariants(hw);
1127 if (err)
1128 goto err_hw_init;
1129
1130 err = igb_sw_init(adapter);
1131 if (err)
1132 goto err_sw_init;
1133
1134 igb_get_bus_info_pcie(hw);
1135
7dfc16fa
AD		 1136 /* set flags */
1137 switch (hw->mac.type) {
7dfc16fa 1138 case e1000_82575:
7dfc16fa
AD		 1139 adapter->flags |= IGB_FLAG_NEED_CTX_IDX;
1140 break;
bbd98fe4 1141 case e1000_82576:
7dfc16fa
AD		 1142 default:
1143 break;
1144 }
1145
9d5c8243
AK		 1146 hw->phy.autoneg_wait_to_complete = false;
1147 hw->mac.adaptive_ifs = true;
1148
1149 /* Copper options */
1150 if (hw->phy.media_type == e1000_media_type_copper) {
1151 hw->phy.mdix = AUTO_ALL_MODES;
1152 hw->phy.disable_polarity_correction = false;
1153 hw->phy.ms_type = e1000_ms_hw_default;
1154 }
1155
1156 if (igb_check_reset_block(hw))
1157 dev_info(&pdev->dev,
1158 "PHY reset is blocked due to SOL/IDER session.\n");
1159
1160 netdev->features = NETIF_F_SG |
1161 NETIF_F_HW_CSUM |
1162 NETIF_F_HW_VLAN_TX |
1163 NETIF_F_HW_VLAN_RX |
1164 NETIF_F_HW_VLAN_FILTER;
1165
1166 netdev->features |= NETIF_F_TSO;
9d5c8243 1167 netdev->features |= NETIF_F_TSO6;
48f29ffc 1168
d3352520 1169#ifdef CONFIG_IGB_LRO
5c0999b7 1170 netdev->features |= NETIF_F_GRO;
d3352520
AD		 1171#endif
1172
48f29ffc
JK		 1173 netdev->vlan_features |= NETIF_F_TSO;
1174 netdev->vlan_features |= NETIF_F_TSO6;
1175 netdev->vlan_features |= NETIF_F_HW_CSUM;
1176 netdev->vlan_features |= NETIF_F_SG;
1177
9d5c8243
AK		 1178 if (pci_using_dac)
1179 netdev->features |= NETIF_F_HIGHDMA;
1180
9d5c8243
AK		 1181 adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1182
1183 /* before reading the NVM, reset the controller to put the device in a
1184 * known good starting state */
1185 hw->mac.ops.reset_hw(hw);
1186
1187 /* make sure the NVM is good */
1188 if (igb_validate_nvm_checksum(hw) < 0) {
1189 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1190 err = -EIO;
1191 goto err_eeprom;
1192 }
1193
1194 /* copy the MAC address out of the NVM */
1195 if (hw->mac.ops.read_mac_addr(hw))
1196 dev_err(&pdev->dev, "NVM Read Error\n");
1197
1198 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1199 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1200
1201 if (!is_valid_ether_addr(netdev->perm_addr)) {
1202 dev_err(&pdev->dev, "Invalid MAC Address\n");
1203 err = -EIO;
1204 goto err_eeprom;
1205 }
1206
1207 init_timer(&adapter->watchdog_timer);
1208 adapter->watchdog_timer.function = &igb_watchdog;
1209 adapter->watchdog_timer.data = (unsigned long) adapter;
1210
1211 init_timer(&adapter->phy_info_timer);
1212 adapter->phy_info_timer.function = &igb_update_phy_info;
1213 adapter->phy_info_timer.data = (unsigned long) adapter;
1214
1215 INIT_WORK(&adapter->reset_task, igb_reset_task);
1216 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1217
1218 /* Initialize link & ring properties that are user-changeable */
1219 adapter->tx_ring->count = 256;
1220 for (i = 0; i < adapter->num_tx_queues; i++)
1221 adapter->tx_ring[i].count = adapter->tx_ring->count;
1222 adapter->rx_ring->count = 256;
1223 for (i = 0; i < adapter->num_rx_queues; i++)
1224 adapter->rx_ring[i].count = adapter->rx_ring->count;
1225
1226 adapter->fc_autoneg = true;
1227 hw->mac.autoneg = true;
1228 hw->phy.autoneg_advertised = 0x2f;
1229
1230 hw->fc.original_type = e1000_fc_default;
1231 hw->fc.type = e1000_fc_default;
1232
1233 adapter->itr_setting = 3;
1234 adapter->itr = IGB_START_ITR;
1235
1236 igb_validate_mdi_setting(hw);
1237
1238 adapter->rx_csum = 1;
1239
1240 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1241 * enable the ACPI Magic Packet filter
1242 */
1243
1244 if (hw->bus.func == 0 ||
1245 hw->device_id == E1000_DEV_ID_82575EB_COPPER)
1246 hw->nvm.ops.read_nvm(hw, NVM_INIT_CONTROL3_PORT_A, 1,
1247 &eeprom_data);
1248
1249 if (eeprom_data & eeprom_apme_mask)
1250 adapter->eeprom_wol |= E1000_WUFC_MAG;
1251
1252 /* now that we have the eeprom settings, apply the special cases where
1253 * the eeprom may be wrong or the board simply won't support wake on
1254 * lan on a particular port */
1255 switch (pdev->device) {
1256 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1257 adapter->eeprom_wol = 0;
1258 break;
1259 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 1260 case E1000_DEV_ID_82576_FIBER:
1261 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 1262 /* Wake events only supported on port A for dual fiber
1263 * regardless of eeprom setting */
1264 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1265 adapter->eeprom_wol = 0;
1266 break;
1267 }
1268
1269 /* initialize the wol settings based on the eeprom settings */
1270 adapter->wol = adapter->eeprom_wol;
e1b86d84 1271 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
9d5c8243
AK		 1272
1273 /* reset the hardware with the new settings */
1274 igb_reset(adapter);
1275
1276 /* let the f/w know that the h/w is now under the control of the
1277 * driver. */
1278 igb_get_hw_control(adapter);
1279
1280 /* tell the stack to leave us alone until igb_open() is called */
1281 netif_carrier_off(netdev);
fd2ea0a7 1282 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1283
1284 strcpy(netdev->name, "eth%d");
1285 err = register_netdev(netdev);
1286 if (err)
1287 goto err_register;
1288
421e02f0 1289#ifdef CONFIG_IGB_DCA
bbd98fe4 1290 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 1291 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 1292 dev_info(&pdev->dev, "DCA enabled\n");
1293 /* Always use CB2 mode, difference is masked
1294 * in the CB driver. */
1295 wr32(E1000_DCA_CTRL, 2);
1296 igb_setup_dca(adapter);
1297 }
1298#endif
1299
9d5c8243
AK		 1300 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1301 /* print bus type/speed/width info */
7c510e4b 1302 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
9d5c8243
AK		 1303 netdev->name,
1304 ((hw->bus.speed == e1000_bus_speed_2500)
1305 ? "2.5Gb/s" : "unknown"),
1306 ((hw->bus.width == e1000_bus_width_pcie_x4)
1307 ? "Width x4" : (hw->bus.width == e1000_bus_width_pcie_x1)
1308 ? "Width x1" : "unknown"),
7c510e4b 1309 netdev->dev_addr);
9d5c8243
AK		 1310
1311 igb_read_part_num(hw, &part_num);
1312 dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1313 (part_num >> 8), (part_num & 0xff));
1314
1315 dev_info(&pdev->dev,
1316 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1317 adapter->msix_entries ? "MSI-X" :
7dfc16fa 1318 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243
AK		 1319 adapter->num_rx_queues, adapter->num_tx_queues);
1320
9d5c8243
AK		 1321 return 0;
1322
1323err_register:
1324 igb_release_hw_control(adapter);
1325err_eeprom:
1326 if (!igb_check_reset_block(hw))
f5f4cf08 1327 igb_reset_phy(hw);
9d5c8243
AK		 1328
1329 if (hw->flash_address)
1330 iounmap(hw->flash_address);
1331
1332 igb_remove_device(hw);
a88f10ec 1333 igb_free_queues(adapter);
9d5c8243
AK		 1334err_sw_init:
1335err_hw_init:
1336 iounmap(hw->hw_addr);
1337err_ioremap:
1338 free_netdev(netdev);
1339err_alloc_etherdev:
aed5dec3
AD		 1340 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1341 IORESOURCE_MEM));
9d5c8243
AK		 1342err_pci_reg:
1343err_dma:
1344 pci_disable_device(pdev);
1345 return err;
1346}
1347
1348/**
1349 * igb_remove - Device Removal Routine
1350 * @pdev: PCI device information struct
1351 *
1352 * igb_remove is called by the PCI subsystem to alert the driver
1353 * that it should release a PCI device. The could be caused by a
1354 * Hot-Plug event, or because the driver is going to be removed from
1355 * memory.
1356 **/
1357static void __devexit igb_remove(struct pci_dev *pdev)
1358{
1359 struct net_device *netdev = pci_get_drvdata(pdev);
1360 struct igb_adapter *adapter = netdev_priv(netdev);
421e02f0 1361#ifdef CONFIG_IGB_DCA
fe4506b6 1362 struct e1000_hw *hw = &adapter->hw;
9280fa52 1363#endif
ea943d41 1364 int err;
9d5c8243
AK		 1365
1366 /* flush_scheduled work may reschedule our watchdog task, so
1367 * explicitly disable watchdog tasks from being rescheduled */
1368 set_bit(__IGB_DOWN, &adapter->state);
1369 del_timer_sync(&adapter->watchdog_timer);
1370 del_timer_sync(&adapter->phy_info_timer);
1371
1372 flush_scheduled_work();
1373
421e02f0 1374#ifdef CONFIG_IGB_DCA
7dfc16fa 1375 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 1376 dev_info(&pdev->dev, "DCA disabled\n");
1377 dca_remove_requester(&pdev->dev);
7dfc16fa 1378 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 1379 wr32(E1000_DCA_CTRL, 1);
1380 }
1381#endif
1382
9d5c8243
AK		 1383 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1384 * would have already happened in close and is redundant. */
1385 igb_release_hw_control(adapter);
1386
1387 unregister_netdev(netdev);
1388
f5f4cf08
AD		 1389 if (!igb_check_reset_block(&adapter->hw))
1390 igb_reset_phy(&adapter->hw);
9d5c8243
AK		 1391
1392 igb_remove_device(&adapter->hw);
1393 igb_reset_interrupt_capability(adapter);
1394
a88f10ec 1395 igb_free_queues(adapter);
9d5c8243
AK		 1396
1397 iounmap(adapter->hw.hw_addr);
1398 if (adapter->hw.flash_address)
1399 iounmap(adapter->hw.flash_address);
aed5dec3
AD		 1400 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1401 IORESOURCE_MEM));
9d5c8243
AK		 1402
1403 free_netdev(netdev);
1404
ea943d41
JK		 1405 err = pci_disable_pcie_error_reporting(pdev);
1406 if (err)
1407 dev_err(&pdev->dev,
1408 "pci_disable_pcie_error_reporting failed 0x%x\n", err);
40a914fa 1409
9d5c8243
AK		 1410 pci_disable_device(pdev);
1411}
1412
1413/**
1414 * igb_sw_init - Initialize general software structures (struct igb_adapter)
1415 * @adapter: board private structure to initialize
1416 *
1417 * igb_sw_init initializes the Adapter private data structure.
1418 * Fields are initialized based on PCI device information and
1419 * OS network device settings (MTU size).
1420 **/
1421static int __devinit igb_sw_init(struct igb_adapter *adapter)
1422{
1423 struct e1000_hw *hw = &adapter->hw;
1424 struct net_device *netdev = adapter->netdev;
1425 struct pci_dev *pdev = adapter->pdev;
1426
1427 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1428
68fd9910
AD		 1429 adapter->tx_ring_count = IGB_DEFAULT_TXD;
1430 adapter->rx_ring_count = IGB_DEFAULT_RXD;
9d5c8243
AK		 1431 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1432 adapter->rx_ps_hdr_size = 0; /* disable packet split */
1433 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1434 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1435
661086df
PWJ		 1436 /* This call may decrease the number of queues depending on
1437 * interrupt mode. */
9d5c8243
AK		 1438 igb_set_interrupt_capability(adapter);
1439
1440 if (igb_alloc_queues(adapter)) {
1441 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1442 return -ENOMEM;
1443 }
1444
1445 /* Explicitly disable IRQ since the NIC can be in any state. */
1446 igb_irq_disable(adapter);
1447
1448 set_bit(__IGB_DOWN, &adapter->state);
1449 return 0;
1450}
1451
1452/**
1453 * igb_open - Called when a network interface is made active
1454 * @netdev: network interface device structure
1455 *
1456 * Returns 0 on success, negative value on failure
1457 *
1458 * The open entry point is called when a network interface is made
1459 * active by the system (IFF_UP). At this point all resources needed
1460 * for transmit and receive operations are allocated, the interrupt
1461 * handler is registered with the OS, the watchdog timer is started,
1462 * and the stack is notified that the interface is ready.
1463 **/
1464static int igb_open(struct net_device *netdev)
1465{
1466 struct igb_adapter *adapter = netdev_priv(netdev);
1467 struct e1000_hw *hw = &adapter->hw;
1468 int err;
1469 int i;
1470
1471 /* disallow open during test */
1472 if (test_bit(__IGB_TESTING, &adapter->state))
1473 return -EBUSY;
1474
1475 /* allocate transmit descriptors */
1476 err = igb_setup_all_tx_resources(adapter);
1477 if (err)
1478 goto err_setup_tx;
1479
1480 /* allocate receive descriptors */
1481 err = igb_setup_all_rx_resources(adapter);
1482 if (err)
1483 goto err_setup_rx;
1484
1485 /* e1000_power_up_phy(adapter); */
1486
1487 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1488 if ((adapter->hw.mng_cookie.status &
1489 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1490 igb_update_mng_vlan(adapter);
1491
1492 /* before we allocate an interrupt, we must be ready to handle it.
1493 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1494 * as soon as we call pci_request_irq, so we have to setup our
1495 * clean_rx handler before we do so. */
1496 igb_configure(adapter);
1497
1498 err = igb_request_irq(adapter);
1499 if (err)
1500 goto err_req_irq;
1501
1502 /* From here on the code is the same as igb_up() */
1503 clear_bit(__IGB_DOWN, &adapter->state);
1504
844290e5
PW		 1505 for (i = 0; i < adapter->num_rx_queues; i++)
1506 napi_enable(&adapter->rx_ring[i].napi);
9d5c8243
AK		 1507
1508 /* Clear any pending interrupts. */
1509 rd32(E1000_ICR);
844290e5
PW		 1510
1511 igb_irq_enable(adapter);
1512
d55b53ff
JK		 1513 netif_tx_start_all_queues(netdev);
1514
9d5c8243
AK		 1515 /* Fire a link status change interrupt to start the watchdog. */
1516 wr32(E1000_ICS, E1000_ICS_LSC);
1517
1518 return 0;
1519
1520err_req_irq:
1521 igb_release_hw_control(adapter);
1522 /* e1000_power_down_phy(adapter); */
1523 igb_free_all_rx_resources(adapter);
1524err_setup_rx:
1525 igb_free_all_tx_resources(adapter);
1526err_setup_tx:
1527 igb_reset(adapter);
1528
1529 return err;
1530}
1531
1532/**
1533 * igb_close - Disables a network interface
1534 * @netdev: network interface device structure
1535 *
1536 * Returns 0, this is not allowed to fail
1537 *
1538 * The close entry point is called when an interface is de-activated
1539 * by the OS. The hardware is still under the driver's control, but
1540 * needs to be disabled. A global MAC reset is issued to stop the
1541 * hardware, and all transmit and receive resources are freed.
1542 **/
1543static int igb_close(struct net_device *netdev)
1544{
1545 struct igb_adapter *adapter = netdev_priv(netdev);
1546
1547 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1548 igb_down(adapter);
1549
1550 igb_free_irq(adapter);
1551
1552 igb_free_all_tx_resources(adapter);
1553 igb_free_all_rx_resources(adapter);
1554
1555 /* kill manageability vlan ID if supported, but not if a vlan with
1556 * the same ID is registered on the host OS (let 8021q kill it) */
1557 if ((adapter->hw.mng_cookie.status &
1558 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1559 !(adapter->vlgrp &&
1560 vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1561 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1562
1563 return 0;
1564}
1565
1566/**
1567 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
1568 * @adapter: board private structure
1569 * @tx_ring: tx descriptor ring (for a specific queue) to setup
1570 *
1571 * Return 0 on success, negative on failure
1572 **/
1573
1574int igb_setup_tx_resources(struct igb_adapter *adapter,
1575 struct igb_ring *tx_ring)
1576{
1577 struct pci_dev *pdev = adapter->pdev;
1578 int size;
1579
1580 size = sizeof(struct igb_buffer) * tx_ring->count;
1581 tx_ring->buffer_info = vmalloc(size);
1582 if (!tx_ring->buffer_info)
1583 goto err;
1584 memset(tx_ring->buffer_info, 0, size);
1585
1586 /* round up to nearest 4K */
0e014cb1 1587 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
9d5c8243
AK		 1588 tx_ring->size = ALIGN(tx_ring->size, 4096);
1589
1590 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1591 &tx_ring->dma);
1592
1593 if (!tx_ring->desc)
1594 goto err;
1595
1596 tx_ring->adapter = adapter;
1597 tx_ring->next_to_use = 0;
1598 tx_ring->next_to_clean = 0;
9d5c8243
AK		 1599 return 0;
1600
1601err:
1602 vfree(tx_ring->buffer_info);
1603 dev_err(&adapter->pdev->dev,
1604 "Unable to allocate memory for the transmit descriptor ring\n");
1605 return -ENOMEM;
1606}
1607
1608/**
1609 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1610 * (Descriptors) for all queues
1611 * @adapter: board private structure
1612 *
1613 * Return 0 on success, negative on failure
1614 **/
1615static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1616{
1617 int i, err = 0;
661086df 1618 int r_idx;
9d5c8243
AK		 1619
1620 for (i = 0; i < adapter->num_tx_queues; i++) {
1621 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1622 if (err) {
1623 dev_err(&adapter->pdev->dev,
1624 "Allocation for Tx Queue %u failed\n", i);
1625 for (i--; i >= 0; i--)
3b644cf6 1626 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 1627 break;
1628 }
1629 }
1630
661086df
PWJ		 1631 for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
1632 r_idx = i % adapter->num_tx_queues;
1633 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
1634 }
9d5c8243
AK		 1635 return err;
1636}
1637
1638/**
1639 * igb_configure_tx - Configure transmit Unit after Reset
1640 * @adapter: board private structure
1641 *
1642 * Configure the Tx unit of the MAC after a reset.
1643 **/
1644static void igb_configure_tx(struct igb_adapter *adapter)
1645{
0e014cb1 1646 u64 tdba;
9d5c8243
AK		 1647 struct e1000_hw *hw = &adapter->hw;
1648 u32 tctl;
1649 u32 txdctl, txctrl;
26bc19ec 1650 int i, j;
9d5c8243
AK		 1651
1652 for (i = 0; i < adapter->num_tx_queues; i++) {
1653 struct igb_ring *ring = &(adapter->tx_ring[i]);
26bc19ec
AD		 1654 j = ring->reg_idx;
1655 wr32(E1000_TDLEN(j),
9d5c8243
AK		 1656 ring->count * sizeof(struct e1000_tx_desc));
1657 tdba = ring->dma;
26bc19ec 1658 wr32(E1000_TDBAL(j),
9d5c8243 1659 tdba & 0x00000000ffffffffULL);
26bc19ec 1660 wr32(E1000_TDBAH(j), tdba >> 32);
9d5c8243 1661
26bc19ec
AD		 1662 ring->head = E1000_TDH(j);
1663 ring->tail = E1000_TDT(j);
9d5c8243
AK		 1664 writel(0, hw->hw_addr + ring->tail);
1665 writel(0, hw->hw_addr + ring->head);
26bc19ec 1666 txdctl = rd32(E1000_TXDCTL(j));
9d5c8243 1667 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
26bc19ec 1668 wr32(E1000_TXDCTL(j), txdctl);
9d5c8243
AK		 1669
1670 /* Turn off Relaxed Ordering on head write-backs. The
1671 * writebacks MUST be delivered in order or it will
1672 * completely screw up our bookeeping.
1673 */
26bc19ec 1674 txctrl = rd32(E1000_DCA_TXCTRL(j));
9d5c8243 1675 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
26bc19ec 1676 wr32(E1000_DCA_TXCTRL(j), txctrl);
9d5c8243
AK		 1677 }
1678
1679
1680
1681 /* Use the default values for the Tx Inter Packet Gap (IPG) timer */
1682
1683 /* Program the Transmit Control Register */
1684
1685 tctl = rd32(E1000_TCTL);
1686 tctl &= ~E1000_TCTL_CT;
1687 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1688 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1689
1690 igb_config_collision_dist(hw);
1691
1692 /* Setup Transmit Descriptor Settings for eop descriptor */
1693 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
1694
1695 /* Enable transmits */
1696 tctl |= E1000_TCTL_EN;
1697
1698 wr32(E1000_TCTL, tctl);
1699}
1700
1701/**
1702 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
1703 * @adapter: board private structure
1704 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1705 *
1706 * Returns 0 on success, negative on failure
1707 **/
1708
1709int igb_setup_rx_resources(struct igb_adapter *adapter,
1710 struct igb_ring *rx_ring)
1711{
1712 struct pci_dev *pdev = adapter->pdev;
1713 int size, desc_len;
1714
1715 size = sizeof(struct igb_buffer) * rx_ring->count;
1716 rx_ring->buffer_info = vmalloc(size);
1717 if (!rx_ring->buffer_info)
1718 goto err;
1719 memset(rx_ring->buffer_info, 0, size);
1720
1721 desc_len = sizeof(union e1000_adv_rx_desc);
1722
1723 /* Round up to nearest 4K */
1724 rx_ring->size = rx_ring->count * desc_len;
1725 rx_ring->size = ALIGN(rx_ring->size, 4096);
1726
1727 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1728 &rx_ring->dma);
1729
1730 if (!rx_ring->desc)
1731 goto err;
1732
1733 rx_ring->next_to_clean = 0;
1734 rx_ring->next_to_use = 0;
9d5c8243
AK		 1735
1736 rx_ring->adapter = adapter;
9d5c8243
AK		 1737
1738 return 0;
1739
1740err:
1741 vfree(rx_ring->buffer_info);
1742 dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
1743 "the receive descriptor ring\n");
1744 return -ENOMEM;
1745}
1746
1747/**
1748 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
1749 * (Descriptors) for all queues
1750 * @adapter: board private structure
1751 *
1752 * Return 0 on success, negative on failure
1753 **/
1754static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
1755{
1756 int i, err = 0;
1757
1758 for (i = 0; i < adapter->num_rx_queues; i++) {
1759 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1760 if (err) {
1761 dev_err(&adapter->pdev->dev,
1762 "Allocation for Rx Queue %u failed\n", i);
1763 for (i--; i >= 0; i--)
3b644cf6 1764 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 1765 break;
1766 }
1767 }
1768
1769 return err;
1770}
1771
1772/**
1773 * igb_setup_rctl - configure the receive control registers
1774 * @adapter: Board private structure
1775 **/
1776static void igb_setup_rctl(struct igb_adapter *adapter)
1777{
1778 struct e1000_hw *hw = &adapter->hw;
1779 u32 rctl;
1780 u32 srrctl = 0;
26bc19ec 1781 int i, j;
9d5c8243
AK		 1782
1783 rctl = rd32(E1000_RCTL);
1784
1785 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 1786 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 1787
69d728ba 1788 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
9d5c8243
AK		 1789 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
1790
87cb7e8c
AK		 1791 /*
1792 * enable stripping of CRC. It's unlikely this will break BMC
1793 * redirection as it did with e1000. Newer features require
1794 * that the HW strips the CRC.
9d5c8243 1795 */
87cb7e8c 1796 rctl |= E1000_RCTL_SECRC;
9d5c8243 1797
9b07f3d3 1798 /*
ec54d7d6 1799 * disable store bad packets and clear size bits.
9b07f3d3 1800 */
ec54d7d6 1801 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 1802
ec54d7d6 1803 /* enable LPE when to prevent packets larger than max_frame_size */
9b07f3d3 1804 rctl |= E1000_RCTL_LPE;
b4557be2
AD		 1805
1806 /* Setup buffer sizes */
1807 switch (adapter->rx_buffer_len) {
1808 case IGB_RXBUFFER_256:
1809 rctl |= E1000_RCTL_SZ_256;
1810 break;
1811 case IGB_RXBUFFER_512:
1812 rctl |= E1000_RCTL_SZ_512;
1813 break;
1814 default:
1815 srrctl = ALIGN(adapter->rx_buffer_len, 1024)
1816 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1817 break;
9d5c8243
AK		 1818 }
1819
1820 /* 82575 and greater support packet-split where the protocol
1821 * header is placed in skb->data and the packet data is
1822 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
1823 * In the case of a non-split, skb->data is linearly filled,
1824 * followed by the page buffers. Therefore, skb->data is
1825 * sized to hold the largest protocol header.
1826 */
1827 /* allocations using alloc_page take too long for regular MTU
1828 * so only enable packet split for jumbo frames */
ec54d7d6 1829 if (adapter->netdev->mtu > ETH_DATA_LEN) {
9d5c8243 1830 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
bf36c1a0 1831 srrctl |= adapter->rx_ps_hdr_size <<
9d5c8243 1832 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
9d5c8243
AK		 1833 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1834 } else {
1835 adapter->rx_ps_hdr_size = 0;
1836 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
1837 }
1838
26bc19ec
AD		 1839 for (i = 0; i < adapter->num_rx_queues; i++) {
1840 j = adapter->rx_ring[i].reg_idx;
1841 wr32(E1000_SRRCTL(j), srrctl);
1842 }
9d5c8243
AK		 1843
1844 wr32(E1000_RCTL, rctl);
1845}
1846
1847/**
1848 * igb_configure_rx - Configure receive Unit after Reset
1849 * @adapter: board private structure
1850 *
1851 * Configure the Rx unit of the MAC after a reset.
1852 **/
1853static void igb_configure_rx(struct igb_adapter *adapter)
1854{
1855 u64 rdba;
1856 struct e1000_hw *hw = &adapter->hw;
1857 u32 rctl, rxcsum;
1858 u32 rxdctl;
26bc19ec 1859 int i, j;
9d5c8243
AK		 1860
1861 /* disable receives while setting up the descriptors */
1862 rctl = rd32(E1000_RCTL);
1863 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1864 wrfl();
1865 mdelay(10);
1866
1867 if (adapter->itr_setting > 3)
6eb5a7f1 1868 wr32(E1000_ITR, adapter->itr);
9d5c8243
AK		 1869
1870 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1871 * the Base and Length of the Rx Descriptor Ring */
1872 for (i = 0; i < adapter->num_rx_queues; i++) {
1873 struct igb_ring *ring = &(adapter->rx_ring[i]);
26bc19ec 1874 j = ring->reg_idx;
9d5c8243 1875 rdba = ring->dma;
26bc19ec 1876 wr32(E1000_RDBAL(j),
9d5c8243 1877 rdba & 0x00000000ffffffffULL);
26bc19ec
AD		 1878 wr32(E1000_RDBAH(j), rdba >> 32);
1879 wr32(E1000_RDLEN(j),
9d5c8243
AK		 1880 ring->count * sizeof(union e1000_adv_rx_desc));
1881
26bc19ec
AD		 1882 ring->head = E1000_RDH(j);
1883 ring->tail = E1000_RDT(j);
9d5c8243
AK		 1884 writel(0, hw->hw_addr + ring->tail);
1885 writel(0, hw->hw_addr + ring->head);
1886
26bc19ec 1887 rxdctl = rd32(E1000_RXDCTL(j));
9d5c8243
AK		 1888 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
1889 rxdctl &= 0xFFF00000;
1890 rxdctl |= IGB_RX_PTHRESH;
1891 rxdctl |= IGB_RX_HTHRESH << 8;
1892 rxdctl |= IGB_RX_WTHRESH << 16;
26bc19ec 1893 wr32(E1000_RXDCTL(j), rxdctl);
9d5c8243
AK		 1894 }
1895
1896 if (adapter->num_rx_queues > 1) {
1897 u32 random[10];
1898 u32 mrqc;
1899 u32 j, shift;
1900 union e1000_reta {
1901 u32 dword;
1902 u8 bytes[4];
1903 } reta;
1904
1905 get_random_bytes(&random[0], 40);
1906
2d064c06
AD		 1907 if (hw->mac.type >= e1000_82576)
1908 shift = 0;
1909 else
1910 shift = 6;
9d5c8243
AK		 1911 for (j = 0; j < (32 * 4); j++) {
1912 reta.bytes[j & 3] =
26bc19ec 1913 adapter->rx_ring[(j % adapter->num_rx_queues)].reg_idx << shift;
9d5c8243
AK		 1914 if ((j & 3) == 3)
1915 writel(reta.dword,
1916 hw->hw_addr + E1000_RETA(0) + (j & ~3));
1917 }
1918 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
1919
1920 /* Fill out hash function seeds */
1921 for (j = 0; j < 10; j++)
1922 array_wr32(E1000_RSSRK(0), j, random[j]);
1923
1924 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
1925 E1000_MRQC_RSS_FIELD_IPV4_TCP);
1926 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
1927 E1000_MRQC_RSS_FIELD_IPV6_TCP);
1928 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
1929 E1000_MRQC_RSS_FIELD_IPV6_UDP);
1930 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
1931 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
1932
1933
1934 wr32(E1000_MRQC, mrqc);
1935
1936 /* Multiqueue and raw packet checksumming are mutually
1937 * exclusive. Note that this not the same as TCP/IP
1938 * checksumming, which works fine. */
1939 rxcsum = rd32(E1000_RXCSUM);
1940 rxcsum |= E1000_RXCSUM_PCSD;
1941 wr32(E1000_RXCSUM, rxcsum);
1942 } else {
1943 /* Enable Receive Checksum Offload for TCP and UDP */
1944 rxcsum = rd32(E1000_RXCSUM);
1945 if (adapter->rx_csum) {
1946 rxcsum |= E1000_RXCSUM_TUOFL;
1947
1948 /* Enable IPv4 payload checksum for UDP fragments
1949 * Must be used in conjunction with packet-split. */
1950 if (adapter->rx_ps_hdr_size)
1951 rxcsum |= E1000_RXCSUM_IPPCSE;
1952 } else {
1953 rxcsum &= ~E1000_RXCSUM_TUOFL;
1954 /* don't need to clear IPPCSE as it defaults to 0 */
1955 }
1956 wr32(E1000_RXCSUM, rxcsum);
1957 }
1958
1959 if (adapter->vlgrp)
1960 wr32(E1000_RLPML,
1961 adapter->max_frame_size + VLAN_TAG_SIZE);
1962 else
1963 wr32(E1000_RLPML, adapter->max_frame_size);
1964
1965 /* Enable Receives */
1966 wr32(E1000_RCTL, rctl);
1967}
1968
1969/**
1970 * igb_free_tx_resources - Free Tx Resources per Queue
9d5c8243
AK		 1971 * @tx_ring: Tx descriptor ring for a specific queue
1972 *
1973 * Free all transmit software resources
1974 **/
68fd9910 1975void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 1976{
3b644cf6 1977 struct pci_dev *pdev = tx_ring->adapter->pdev;
9d5c8243 1978
3b644cf6 1979 igb_clean_tx_ring(tx_ring);
9d5c8243
AK		 1980
1981 vfree(tx_ring->buffer_info);
1982 tx_ring->buffer_info = NULL;
1983
1984 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1985
1986 tx_ring->desc = NULL;
1987}
1988
1989/**
1990 * igb_free_all_tx_resources - Free Tx Resources for All Queues
1991 * @adapter: board private structure
1992 *
1993 * Free all transmit software resources
1994 **/
1995static void igb_free_all_tx_resources(struct igb_adapter *adapter)
1996{
1997 int i;
1998
1999 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2000 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 2001}
2002
2003static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
2004 struct igb_buffer *buffer_info)
2005{
2006 if (buffer_info->dma) {
2007 pci_unmap_page(adapter->pdev,
2008 buffer_info->dma,
2009 buffer_info->length,
2010 PCI_DMA_TODEVICE);
2011 buffer_info->dma = 0;
2012 }
2013 if (buffer_info->skb) {
2014 dev_kfree_skb_any(buffer_info->skb);
2015 buffer_info->skb = NULL;
2016 }
2017 buffer_info->time_stamp = 0;
2018 /* buffer_info must be completely set up in the transmit path */
2019}
2020
2021/**
2022 * igb_clean_tx_ring - Free Tx Buffers
9d5c8243
AK		 2023 * @tx_ring: ring to be cleaned
2024 **/
3b644cf6 2025static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 2026{
3b644cf6 2027 struct igb_adapter *adapter = tx_ring->adapter;
9d5c8243
AK		 2028 struct igb_buffer *buffer_info;
2029 unsigned long size;
2030 unsigned int i;
2031
2032 if (!tx_ring->buffer_info)
2033 return;
2034 /* Free all the Tx ring sk_buffs */
2035
2036 for (i = 0; i < tx_ring->count; i++) {
2037 buffer_info = &tx_ring->buffer_info[i];
2038 igb_unmap_and_free_tx_resource(adapter, buffer_info);
2039 }
2040
2041 size = sizeof(struct igb_buffer) * tx_ring->count;
2042 memset(tx_ring->buffer_info, 0, size);
2043
2044 /* Zero out the descriptor ring */
2045
2046 memset(tx_ring->desc, 0, tx_ring->size);
2047
2048 tx_ring->next_to_use = 0;
2049 tx_ring->next_to_clean = 0;
2050
2051 writel(0, adapter->hw.hw_addr + tx_ring->head);
2052 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2053}
2054
2055/**
2056 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2057 * @adapter: board private structure
2058 **/
2059static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2060{
2061 int i;
2062
2063 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2064 igb_clean_tx_ring(&adapter->tx_ring[i]);
9d5c8243
AK		 2065}
2066
2067/**
2068 * igb_free_rx_resources - Free Rx Resources
9d5c8243
AK		 2069 * @rx_ring: ring to clean the resources from
2070 *
2071 * Free all receive software resources
2072 **/
68fd9910 2073void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2074{
3b644cf6 2075 struct pci_dev *pdev = rx_ring->adapter->pdev;
9d5c8243 2076
3b644cf6 2077 igb_clean_rx_ring(rx_ring);
9d5c8243
AK		 2078
2079 vfree(rx_ring->buffer_info);
2080 rx_ring->buffer_info = NULL;
2081
2082 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2083
2084 rx_ring->desc = NULL;
2085}
2086
2087/**
2088 * igb_free_all_rx_resources - Free Rx Resources for All Queues
2089 * @adapter: board private structure
2090 *
2091 * Free all receive software resources
2092 **/
2093static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2094{
2095 int i;
2096
2097 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2098 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 2099}
2100
2101/**
2102 * igb_clean_rx_ring - Free Rx Buffers per Queue
9d5c8243
AK		 2103 * @rx_ring: ring to free buffers from
2104 **/
3b644cf6 2105static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 2106{
3b644cf6 2107 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 2108 struct igb_buffer *buffer_info;
2109 struct pci_dev *pdev = adapter->pdev;
2110 unsigned long size;
2111 unsigned int i;
2112
2113 if (!rx_ring->buffer_info)
2114 return;
2115 /* Free all the Rx ring sk_buffs */
2116 for (i = 0; i < rx_ring->count; i++) {
2117 buffer_info = &rx_ring->buffer_info[i];
2118 if (buffer_info->dma) {
2119 if (adapter->rx_ps_hdr_size)
2120 pci_unmap_single(pdev, buffer_info->dma,
2121 adapter->rx_ps_hdr_size,
2122 PCI_DMA_FROMDEVICE);
2123 else
2124 pci_unmap_single(pdev, buffer_info->dma,
2125 adapter->rx_buffer_len,
2126 PCI_DMA_FROMDEVICE);
2127 buffer_info->dma = 0;
2128 }
2129
2130 if (buffer_info->skb) {
2131 dev_kfree_skb(buffer_info->skb);
2132 buffer_info->skb = NULL;
2133 }
2134 if (buffer_info->page) {
bf36c1a0
AD		 2135 if (buffer_info->page_dma)
2136 pci_unmap_page(pdev, buffer_info->page_dma,
2137 PAGE_SIZE / 2,
2138 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 2139 put_page(buffer_info->page);
2140 buffer_info->page = NULL;
2141 buffer_info->page_dma = 0;
bf36c1a0 2142 buffer_info->page_offset = 0;
9d5c8243
AK		 2143 }
2144 }
2145
9d5c8243
AK		 2146 size = sizeof(struct igb_buffer) * rx_ring->count;
2147 memset(rx_ring->buffer_info, 0, size);
2148
2149 /* Zero out the descriptor ring */
2150 memset(rx_ring->desc, 0, rx_ring->size);
2151
2152 rx_ring->next_to_clean = 0;
2153 rx_ring->next_to_use = 0;
2154
2155 writel(0, adapter->hw.hw_addr + rx_ring->head);
2156 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2157}
2158
2159/**
2160 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2161 * @adapter: board private structure
2162 **/
2163static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2164{
2165 int i;
2166
2167 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2168 igb_clean_rx_ring(&adapter->rx_ring[i]);
9d5c8243
AK		 2169}
2170
2171/**
2172 * igb_set_mac - Change the Ethernet Address of the NIC
2173 * @netdev: network interface device structure
2174 * @p: pointer to an address structure
2175 *
2176 * Returns 0 on success, negative on failure
2177 **/
2178static int igb_set_mac(struct net_device *netdev, void *p)
2179{
2180 struct igb_adapter *adapter = netdev_priv(netdev);
2181 struct sockaddr *addr = p;
2182
2183 if (!is_valid_ether_addr(addr->sa_data))
2184 return -EADDRNOTAVAIL;
2185
2186 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2187 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
2188
2189 adapter->hw.mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
2190
2191 return 0;
2192}
2193
2194/**
2195 * igb_set_multi - Multicast and Promiscuous mode set
2196 * @netdev: network interface device structure
2197 *
2198 * The set_multi entry point is called whenever the multicast address
2199 * list or the network interface flags are updated. This routine is
2200 * responsible for configuring the hardware for proper multicast,
2201 * promiscuous mode, and all-multi behavior.
2202 **/
2203static void igb_set_multi(struct net_device *netdev)
2204{
2205 struct igb_adapter *adapter = netdev_priv(netdev);
2206 struct e1000_hw *hw = &adapter->hw;
2207 struct e1000_mac_info *mac = &hw->mac;
2208 struct dev_mc_list *mc_ptr;
2209 u8 *mta_list;
2210 u32 rctl;
2211 int i;
2212
2213 /* Check for Promiscuous and All Multicast modes */
2214
2215 rctl = rd32(E1000_RCTL);
2216
746b9f02 2217 if (netdev->flags & IFF_PROMISC) {
9d5c8243 2218 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
746b9f02
PM		 2219 rctl &= ~E1000_RCTL_VFE;
2220 } else {
2221 if (netdev->flags & IFF_ALLMULTI) {
2222 rctl |= E1000_RCTL_MPE;
2223 rctl &= ~E1000_RCTL_UPE;
2224 } else
2225 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
78ed11a5 2226 rctl |= E1000_RCTL_VFE;
746b9f02 2227 }
9d5c8243
AK		 2228 wr32(E1000_RCTL, rctl);
2229
2230 if (!netdev->mc_count) {
2231 /* nothing to program, so clear mc list */
2d064c06 2232 igb_update_mc_addr_list_82575(hw, NULL, 0, 1,
9d5c8243
AK		 2233 mac->rar_entry_count);
2234 return;
2235 }
2236
2237 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2238 if (!mta_list)
2239 return;
2240
2241 /* The shared function expects a packed array of only addresses. */
2242 mc_ptr = netdev->mc_list;
2243
2244 for (i = 0; i < netdev->mc_count; i++) {
2245 if (!mc_ptr)
2246 break;
2247 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2248 mc_ptr = mc_ptr->next;
2249 }
2d064c06
AD		 2250 igb_update_mc_addr_list_82575(hw, mta_list, i, 1,
2251 mac->rar_entry_count);
9d5c8243
AK		 2252 kfree(mta_list);
2253}
2254
2255/* Need to wait a few seconds after link up to get diagnostic information from
2256 * the phy */
2257static void igb_update_phy_info(unsigned long data)
2258{
2259 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 2260 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 2261}
2262
2263/**
2264 * igb_watchdog - Timer Call-back
2265 * @data: pointer to adapter cast into an unsigned long
2266 **/
2267static void igb_watchdog(unsigned long data)
2268{
2269 struct igb_adapter *adapter = (struct igb_adapter *)data;
2270 /* Do the rest outside of interrupt context */
2271 schedule_work(&adapter->watchdog_task);
2272}
2273
2274static void igb_watchdog_task(struct work_struct *work)
2275{
2276 struct igb_adapter *adapter = container_of(work,
2277 struct igb_adapter, watchdog_task);
2278 struct e1000_hw *hw = &adapter->hw;
2279
2280 struct net_device *netdev = adapter->netdev;
2281 struct igb_ring *tx_ring = adapter->tx_ring;
2282 struct e1000_mac_info *mac = &adapter->hw.mac;
2283 u32 link;
7a6ea550 2284 u32 eics = 0;
9d5c8243 2285 s32 ret_val;
7a6ea550 2286 int i;
9d5c8243
AK		 2287
2288 if ((netif_carrier_ok(netdev)) &&
2289 (rd32(E1000_STATUS) & E1000_STATUS_LU))
2290 goto link_up;
2291
2292 ret_val = hw->mac.ops.check_for_link(&adapter->hw);
2293 if ((ret_val == E1000_ERR_PHY) &&
2294 (hw->phy.type == e1000_phy_igp_3) &&
2295 (rd32(E1000_CTRL) &
2296 E1000_PHY_CTRL_GBE_DISABLE))
2297 dev_info(&adapter->pdev->dev,
2298 "Gigabit has been disabled, downgrading speed\n");
2299
2300 if ((hw->phy.media_type == e1000_media_type_internal_serdes) &&
2301 !(rd32(E1000_TXCW) & E1000_TXCW_ANE))
2302 link = mac->serdes_has_link;
2303 else
2304 link = rd32(E1000_STATUS) &
2305 E1000_STATUS_LU;
2306
2307 if (link) {
2308 if (!netif_carrier_ok(netdev)) {
2309 u32 ctrl;
2310 hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2311 &adapter->link_speed,
2312 &adapter->link_duplex);
2313
2314 ctrl = rd32(E1000_CTRL);
527d47c1
AD		 2315 /* Links status message must follow this format */
2316 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
9d5c8243 2317 "Flow Control: %s\n",
527d47c1 2318 netdev->name,
9d5c8243
AK		 2319 adapter->link_speed,
2320 adapter->link_duplex == FULL_DUPLEX ?
2321 "Full Duplex" : "Half Duplex",
2322 ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2323 E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2324 E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2325 E1000_CTRL_TFCE) ? "TX" : "None")));
2326
2327 /* tweak tx_queue_len according to speed/duplex and
2328 * adjust the timeout factor */
2329 netdev->tx_queue_len = adapter->tx_queue_len;
2330 adapter->tx_timeout_factor = 1;
2331 switch (adapter->link_speed) {
2332 case SPEED_10:
2333 netdev->tx_queue_len = 10;
2334 adapter->tx_timeout_factor = 14;
2335 break;
2336 case SPEED_100:
2337 netdev->tx_queue_len = 100;
2338 /* maybe add some timeout factor ? */
2339 break;
2340 }
2341
2342 netif_carrier_on(netdev);
fd2ea0a7 2343 netif_tx_wake_all_queues(netdev);
9d5c8243
AK		 2344
2345 if (!test_bit(__IGB_DOWN, &adapter->state))
2346 mod_timer(&adapter->phy_info_timer,
2347 round_jiffies(jiffies + 2 * HZ));
2348 }
2349 } else {
2350 if (netif_carrier_ok(netdev)) {
2351 adapter->link_speed = 0;
2352 adapter->link_duplex = 0;
527d47c1
AD		 2353 /* Links status message must follow this format */
2354 printk(KERN_INFO "igb: %s NIC Link is Down\n",
2355 netdev->name);
9d5c8243 2356 netif_carrier_off(netdev);
fd2ea0a7 2357 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 2358 if (!test_bit(__IGB_DOWN, &adapter->state))
2359 mod_timer(&adapter->phy_info_timer,
2360 round_jiffies(jiffies + 2 * HZ));
2361 }
2362 }
2363
2364link_up:
2365 igb_update_stats(adapter);
2366
2367 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2368 adapter->tpt_old = adapter->stats.tpt;
2369 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
2370 adapter->colc_old = adapter->stats.colc;
2371
2372 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2373 adapter->gorc_old = adapter->stats.gorc;
2374 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2375 adapter->gotc_old = adapter->stats.gotc;
2376
2377 igb_update_adaptive(&adapter->hw);
2378
2379 if (!netif_carrier_ok(netdev)) {
2380 if (IGB_DESC_UNUSED(tx_ring) + 1 < tx_ring->count) {
2381 /* We've lost link, so the controller stops DMA,
2382 * but we've got queued Tx work that's never going
2383 * to get done, so reset controller to flush Tx.
2384 * (Do the reset outside of interrupt context). */
2385 adapter->tx_timeout_count++;
2386 schedule_work(&adapter->reset_task);
2387 }
2388 }
2389
2390 /* Cause software interrupt to ensure rx ring is cleaned */
7a6ea550
AD		 2391 if (adapter->msix_entries) {
2392 for (i = 0; i < adapter->num_rx_queues; i++)
2393 eics |= adapter->rx_ring[i].eims_value;
2394 wr32(E1000_EICS, eics);
2395 } else {
2396 wr32(E1000_ICS, E1000_ICS_RXDMT0);
2397 }
9d5c8243
AK		 2398
2399 /* Force detection of hung controller every watchdog period */
2400 tx_ring->detect_tx_hung = true;
2401
2402 /* Reset the timer */
2403 if (!test_bit(__IGB_DOWN, &adapter->state))
2404 mod_timer(&adapter->watchdog_timer,
2405 round_jiffies(jiffies + 2 * HZ));
2406}
2407
2408enum latency_range {
2409 lowest_latency = 0,
2410 low_latency = 1,
2411 bulk_latency = 2,
2412 latency_invalid = 255
2413};
2414
2415
6eb5a7f1
AD		 2416/**
2417 * igb_update_ring_itr - update the dynamic ITR value based on packet size
2418 *
2419 * Stores a new ITR value based on strictly on packet size. This
2420 * algorithm is less sophisticated than that used in igb_update_itr,
2421 * due to the difficulty of synchronizing statistics across multiple
2422 * receive rings. The divisors and thresholds used by this fuction
2423 * were determined based on theoretical maximum wire speed and testing
2424 * data, in order to minimize response time while increasing bulk
2425 * throughput.
2426 * This functionality is controlled by the InterruptThrottleRate module
2427 * parameter (see igb_param.c)
2428 * NOTE: This function is called only when operating in a multiqueue
2429 * receive environment.
2430 * @rx_ring: pointer to ring
2431 **/
2432static void igb_update_ring_itr(struct igb_ring *rx_ring)
9d5c8243 2433{
6eb5a7f1
AD		 2434 int new_val = rx_ring->itr_val;
2435 int avg_wire_size = 0;
2436 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 2437
6eb5a7f1
AD		 2438 if (!rx_ring->total_packets)
2439 goto clear_counts; /* no packets, so don't do anything */
9d5c8243 2440
6eb5a7f1
AD		 2441 /* For non-gigabit speeds, just fix the interrupt rate at 4000
2442 * ints/sec - ITR timer value of 120 ticks.
2443 */
2444 if (adapter->link_speed != SPEED_1000) {
2445 new_val = 120;
2446 goto set_itr_val;
9d5c8243 2447 }
6eb5a7f1 2448 avg_wire_size = rx_ring->total_bytes / rx_ring->total_packets;
9d5c8243 2449
6eb5a7f1
AD		 2450 /* Add 24 bytes to size to account for CRC, preamble, and gap */
2451 avg_wire_size += 24;
2452
2453 /* Don't starve jumbo frames */
2454 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 2455
6eb5a7f1
AD		 2456 /* Give a little boost to mid-size frames */
2457 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
2458 new_val = avg_wire_size / 3;
2459 else
2460 new_val = avg_wire_size / 2;
9d5c8243 2461
6eb5a7f1 2462set_itr_val:
9d5c8243
AK		 2463 if (new_val != rx_ring->itr_val) {
2464 rx_ring->itr_val = new_val;
6eb5a7f1 2465 rx_ring->set_itr = 1;
9d5c8243 2466 }
6eb5a7f1
AD		 2467clear_counts:
2468 rx_ring->total_bytes = 0;
2469 rx_ring->total_packets = 0;
9d5c8243
AK		 2470}
2471
2472/**
2473 * igb_update_itr - update the dynamic ITR value based on statistics
2474 * Stores a new ITR value based on packets and byte
2475 * counts during the last interrupt. The advantage of per interrupt
2476 * computation is faster updates and more accurate ITR for the current
2477 * traffic pattern. Constants in this function were computed
2478 * based on theoretical maximum wire speed and thresholds were set based
2479 * on testing data as well as attempting to minimize response time
2480 * while increasing bulk throughput.
2481 * this functionality is controlled by the InterruptThrottleRate module
2482 * parameter (see igb_param.c)
2483 * NOTE: These calculations are only valid when operating in a single-
2484 * queue environment.
2485 * @adapter: pointer to adapter
2486 * @itr_setting: current adapter->itr
2487 * @packets: the number of packets during this measurement interval
2488 * @bytes: the number of bytes during this measurement interval
2489 **/
2490static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
2491 int packets, int bytes)
2492{
2493 unsigned int retval = itr_setting;
2494
2495 if (packets == 0)
2496 goto update_itr_done;
2497
2498 switch (itr_setting) {
2499 case lowest_latency:
2500 /* handle TSO and jumbo frames */
2501 if (bytes/packets > 8000)
2502 retval = bulk_latency;
2503 else if ((packets < 5) && (bytes > 512))
2504 retval = low_latency;
2505 break;
2506 case low_latency: /* 50 usec aka 20000 ints/s */
2507 if (bytes > 10000) {
2508 /* this if handles the TSO accounting */
2509 if (bytes/packets > 8000) {
2510 retval = bulk_latency;
2511 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
2512 retval = bulk_latency;
2513 } else if ((packets > 35)) {
2514 retval = lowest_latency;
2515 }
2516 } else if (bytes/packets > 2000) {
2517 retval = bulk_latency;
2518 } else if (packets <= 2 && bytes < 512) {
2519 retval = lowest_latency;
2520 }
2521 break;
2522 case bulk_latency: /* 250 usec aka 4000 ints/s */
2523 if (bytes > 25000) {
2524 if (packets > 35)
2525 retval = low_latency;
2526 } else if (bytes < 6000) {
2527 retval = low_latency;
2528 }
2529 break;
2530 }
2531
2532update_itr_done:
2533 return retval;
2534}
2535
6eb5a7f1 2536static void igb_set_itr(struct igb_adapter *adapter)
9d5c8243
AK		 2537{
2538 u16 current_itr;
2539 u32 new_itr = adapter->itr;
2540
2541 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2542 if (adapter->link_speed != SPEED_1000) {
2543 current_itr = 0;
2544 new_itr = 4000;
2545 goto set_itr_now;
2546 }
2547
2548 adapter->rx_itr = igb_update_itr(adapter,
2549 adapter->rx_itr,
2550 adapter->rx_ring->total_packets,
2551 adapter->rx_ring->total_bytes);
9d5c8243 2552
6eb5a7f1 2553 if (adapter->rx_ring->buddy) {
9d5c8243
AK		 2554 adapter->tx_itr = igb_update_itr(adapter,
2555 adapter->tx_itr,
2556 adapter->tx_ring->total_packets,
2557 adapter->tx_ring->total_bytes);
9d5c8243
AK		 2558
2559 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2560 } else {
2561 current_itr = adapter->rx_itr;
2562 }
2563
6eb5a7f1
AD		 2564 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2565 if (adapter->itr_setting == 3 &&
2566 current_itr == lowest_latency)
2567 current_itr = low_latency;
2568
9d5c8243
AK		 2569 switch (current_itr) {
2570 /* counts and packets in update_itr are dependent on these numbers */
2571 case lowest_latency:
2572 new_itr = 70000;
2573 break;
2574 case low_latency:
2575 new_itr = 20000; /* aka hwitr = ~200 */
2576 break;
2577 case bulk_latency:
2578 new_itr = 4000;
2579 break;
2580 default:
2581 break;
2582 }
2583
2584set_itr_now:
6eb5a7f1
AD		 2585 adapter->rx_ring->total_bytes = 0;
2586 adapter->rx_ring->total_packets = 0;
2587 if (adapter->rx_ring->buddy) {
2588 adapter->rx_ring->buddy->total_bytes = 0;
2589 adapter->rx_ring->buddy->total_packets = 0;
2590 }
2591
9d5c8243
AK		 2592 if (new_itr != adapter->itr) {
2593 /* this attempts to bias the interrupt rate towards Bulk
2594 * by adding intermediate steps when interrupt rate is
2595 * increasing */
2596 new_itr = new_itr > adapter->itr ?
2597 min(adapter->itr + (new_itr >> 2), new_itr) :
2598 new_itr;
2599 /* Don't write the value here; it resets the adapter's
2600 * internal timer, and causes us to delay far longer than
2601 * we should between interrupts. Instead, we write the ITR
2602 * value at the beginning of the next interrupt so the timing
2603 * ends up being correct.
2604 */
2605 adapter->itr = new_itr;
6eb5a7f1
AD		 2606 adapter->rx_ring->itr_val = 1000000000 / (new_itr * 256);
2607 adapter->rx_ring->set_itr = 1;
9d5c8243
AK		 2608 }
2609
2610 return;
2611}
2612
2613
2614#define IGB_TX_FLAGS_CSUM 0x00000001
2615#define IGB_TX_FLAGS_VLAN 0x00000002
2616#define IGB_TX_FLAGS_TSO 0x00000004
2617#define IGB_TX_FLAGS_IPV4 0x00000008
2618#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
2619#define IGB_TX_FLAGS_VLAN_SHIFT 16
2620
2621static inline int igb_tso_adv(struct igb_adapter *adapter,
2622 struct igb_ring *tx_ring,
2623 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
2624{
2625 struct e1000_adv_tx_context_desc *context_desc;
2626 unsigned int i;
2627 int err;
2628 struct igb_buffer *buffer_info;
2629 u32 info = 0, tu_cmd = 0;
2630 u32 mss_l4len_idx, l4len;
2631 *hdr_len = 0;
2632
2633 if (skb_header_cloned(skb)) {
2634 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2635 if (err)
2636 return err;
2637 }
2638
2639 l4len = tcp_hdrlen(skb);
2640 *hdr_len += l4len;
2641
2642 if (skb->protocol == htons(ETH_P_IP)) {
2643 struct iphdr *iph = ip_hdr(skb);
2644 iph->tot_len = 0;
2645 iph->check = 0;
2646 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2647 iph->daddr, 0,
2648 IPPROTO_TCP,
2649 0);
2650 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
2651 ipv6_hdr(skb)->payload_len = 0;
2652 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2653 &ipv6_hdr(skb)->daddr,
2654 0, IPPROTO_TCP, 0);
2655 }
2656
2657 i = tx_ring->next_to_use;
2658
2659 buffer_info = &tx_ring->buffer_info[i];
2660 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2661 /* VLAN MACLEN IPLEN */
2662 if (tx_flags & IGB_TX_FLAGS_VLAN)
2663 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2664 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2665 *hdr_len += skb_network_offset(skb);
2666 info |= skb_network_header_len(skb);
2667 *hdr_len += skb_network_header_len(skb);
2668 context_desc->vlan_macip_lens = cpu_to_le32(info);
2669
2670 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
2671 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2672
2673 if (skb->protocol == htons(ETH_P_IP))
2674 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
2675 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2676
2677 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2678
2679 /* MSS L4LEN IDX */
2680 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
2681 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
2682
7dfc16fa
AD		 2683 /* Context index must be unique per ring. */
2684 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2685 mss_l4len_idx |= tx_ring->queue_index << 4;
9d5c8243
AK		 2686
2687 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
2688 context_desc->seqnum_seed = 0;
2689
2690 buffer_info->time_stamp = jiffies;
0e014cb1 2691 buffer_info->next_to_watch = i;
9d5c8243
AK		 2692 buffer_info->dma = 0;
2693 i++;
2694 if (i == tx_ring->count)
2695 i = 0;
2696
2697 tx_ring->next_to_use = i;
2698
2699 return true;
2700}
2701
2702static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
2703 struct igb_ring *tx_ring,
2704 struct sk_buff *skb, u32 tx_flags)
2705{
2706 struct e1000_adv_tx_context_desc *context_desc;
2707 unsigned int i;
2708 struct igb_buffer *buffer_info;
2709 u32 info = 0, tu_cmd = 0;
2710
2711 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
2712 (tx_flags & IGB_TX_FLAGS_VLAN)) {
2713 i = tx_ring->next_to_use;
2714 buffer_info = &tx_ring->buffer_info[i];
2715 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2716
2717 if (tx_flags & IGB_TX_FLAGS_VLAN)
2718 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2719 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2720 if (skb->ip_summed == CHECKSUM_PARTIAL)
2721 info |= skb_network_header_len(skb);
2722
2723 context_desc->vlan_macip_lens = cpu_to_le32(info);
2724
2725 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2726
2727 if (skb->ip_summed == CHECKSUM_PARTIAL) {
44b0cda3 2728 switch (skb->protocol) {
09640e63 2729 case cpu_to_be16(ETH_P_IP):
9d5c8243 2730 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
44b0cda3
MW		 2731 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
2732 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2733 break;
09640e63 2734 case cpu_to_be16(ETH_P_IPV6):
44b0cda3
MW		 2735 /* XXX what about other V6 headers?? */
2736 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
2737 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2738 break;
2739 default:
2740 if (unlikely(net_ratelimit()))
2741 dev_warn(&adapter->pdev->dev,
2742 "partial checksum but proto=%x!\n",
2743 skb->protocol);
2744 break;
2745 }
9d5c8243
AK		 2746 }
2747
2748 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2749 context_desc->seqnum_seed = 0;
7dfc16fa
AD		 2750 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2751 context_desc->mss_l4len_idx =
2752 cpu_to_le32(tx_ring->queue_index << 4);
9d5c8243
AK		 2753
2754 buffer_info->time_stamp = jiffies;
0e014cb1 2755 buffer_info->next_to_watch = i;
9d5c8243
AK		 2756 buffer_info->dma = 0;
2757
2758 i++;
2759 if (i == tx_ring->count)
2760 i = 0;
2761 tx_ring->next_to_use = i;
2762
2763 return true;
2764 }
2765
2766
2767 return false;
2768}
2769
2770#define IGB_MAX_TXD_PWR 16
2771#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
2772
2773static inline int igb_tx_map_adv(struct igb_adapter *adapter,
0e014cb1
AD		 2774 struct igb_ring *tx_ring, struct sk_buff *skb,
2775 unsigned int first)
9d5c8243
AK		 2776{
2777 struct igb_buffer *buffer_info;
2778 unsigned int len = skb_headlen(skb);
2779 unsigned int count = 0, i;
2780 unsigned int f;
2781
2782 i = tx_ring->next_to_use;
2783
2784 buffer_info = &tx_ring->buffer_info[i];
2785 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2786 buffer_info->length = len;
2787 /* set time_stamp *before* dma to help avoid a possible race */
2788 buffer_info->time_stamp = jiffies;
0e014cb1 2789 buffer_info->next_to_watch = i;
9d5c8243
AK		 2790 buffer_info->dma = pci_map_single(adapter->pdev, skb->data, len,
2791 PCI_DMA_TODEVICE);
2792 count++;
2793 i++;
2794 if (i == tx_ring->count)
2795 i = 0;
2796
2797 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
2798 struct skb_frag_struct *frag;
2799
2800 frag = &skb_shinfo(skb)->frags[f];
2801 len = frag->size;
2802
2803 buffer_info = &tx_ring->buffer_info[i];
2804 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2805 buffer_info->length = len;
2806 buffer_info->time_stamp = jiffies;
0e014cb1 2807 buffer_info->next_to_watch = i;
9d5c8243
AK		 2808 buffer_info->dma = pci_map_page(adapter->pdev,
2809 frag->page,
2810 frag->page_offset,
2811 len,
2812 PCI_DMA_TODEVICE);
2813
2814 count++;
2815 i++;
2816 if (i == tx_ring->count)
2817 i = 0;
2818 }
2819
0e014cb1 2820 i = ((i == 0) ? tx_ring->count - 1 : i - 1);
9d5c8243 2821 tx_ring->buffer_info[i].skb = skb;
0e014cb1 2822 tx_ring->buffer_info[first].next_to_watch = i;
9d5c8243
AK		 2823
2824 return count;
2825}
2826
2827static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
2828 struct igb_ring *tx_ring,
2829 int tx_flags, int count, u32 paylen,
2830 u8 hdr_len)
2831{
2832 union e1000_adv_tx_desc *tx_desc = NULL;
2833 struct igb_buffer *buffer_info;
2834 u32 olinfo_status = 0, cmd_type_len;
2835 unsigned int i;
2836
2837 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
2838 E1000_ADVTXD_DCMD_DEXT);
2839
2840 if (tx_flags & IGB_TX_FLAGS_VLAN)
2841 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
2842
2843 if (tx_flags & IGB_TX_FLAGS_TSO) {
2844 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
2845
2846 /* insert tcp checksum */
2847 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2848
2849 /* insert ip checksum */
2850 if (tx_flags & IGB_TX_FLAGS_IPV4)
2851 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
2852
2853 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
2854 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2855 }
2856
7dfc16fa
AD		 2857 if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) &&
2858 (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
2859 IGB_TX_FLAGS_VLAN)))
661086df 2860 olinfo_status |= tx_ring->queue_index << 4;
9d5c8243
AK		 2861
2862 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
2863
2864 i = tx_ring->next_to_use;
2865 while (count--) {
2866 buffer_info = &tx_ring->buffer_info[i];
2867 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
2868 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
2869 tx_desc->read.cmd_type_len =
2870 cpu_to_le32(cmd_type_len | buffer_info->length);
2871 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
2872 i++;
2873 if (i == tx_ring->count)
2874 i = 0;
2875 }
2876
2877 tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
2878 /* Force memory writes to complete before letting h/w
2879 * know there are new descriptors to fetch. (Only
2880 * applicable for weak-ordered memory model archs,
2881 * such as IA-64). */
2882 wmb();
2883
2884 tx_ring->next_to_use = i;
2885 writel(i, adapter->hw.hw_addr + tx_ring->tail);
2886 /* we need this if more than one processor can write to our tail
2887 * at a time, it syncronizes IO on IA64/Altix systems */
2888 mmiowb();
2889}
2890
2891static int __igb_maybe_stop_tx(struct net_device *netdev,
2892 struct igb_ring *tx_ring, int size)
2893{
2894 struct igb_adapter *adapter = netdev_priv(netdev);
2895
661086df 2896 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 2897
9d5c8243
AK		 2898 /* Herbert's original patch had:
2899 * smp_mb__after_netif_stop_queue();
2900 * but since that doesn't exist yet, just open code it. */
2901 smp_mb();
2902
2903 /* We need to check again in a case another CPU has just
2904 * made room available. */
2905 if (IGB_DESC_UNUSED(tx_ring) < size)
2906 return -EBUSY;
2907
2908 /* A reprieve! */
661086df 2909 netif_wake_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 2910 ++adapter->restart_queue;
2911 return 0;
2912}
2913
2914static int igb_maybe_stop_tx(struct net_device *netdev,
2915 struct igb_ring *tx_ring, int size)
2916{
2917 if (IGB_DESC_UNUSED(tx_ring) >= size)
2918 return 0;
2919 return __igb_maybe_stop_tx(netdev, tx_ring, size);
2920}
2921
2922#define TXD_USE_COUNT(S) (((S) >> (IGB_MAX_TXD_PWR)) + 1)
2923
2924static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
2925 struct net_device *netdev,
2926 struct igb_ring *tx_ring)
2927{
2928 struct igb_adapter *adapter = netdev_priv(netdev);
0e014cb1 2929 unsigned int first;
9d5c8243
AK		 2930 unsigned int tx_flags = 0;
2931 unsigned int len;
9d5c8243
AK		 2932 u8 hdr_len = 0;
2933 int tso = 0;
2934
2935 len = skb_headlen(skb);
2936
2937 if (test_bit(__IGB_DOWN, &adapter->state)) {
2938 dev_kfree_skb_any(skb);
2939 return NETDEV_TX_OK;
2940 }
2941
2942 if (skb->len <= 0) {
2943 dev_kfree_skb_any(skb);
2944 return NETDEV_TX_OK;
2945 }
2946
9d5c8243
AK		 2947 /* need: 1 descriptor per page,
2948 * + 2 desc gap to keep tail from touching head,
2949 * + 1 desc for skb->data,
2950 * + 1 desc for context descriptor,
2951 * otherwise try next time */
2952 if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
2953 /* this is a hard error */
9d5c8243
AK		 2954 return NETDEV_TX_BUSY;
2955 }
6eb5a7f1 2956 skb_orphan(skb);
9d5c8243
AK		 2957
2958 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
2959 tx_flags |= IGB_TX_FLAGS_VLAN;
2960 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
2961 }
2962
661086df
PWJ		 2963 if (skb->protocol == htons(ETH_P_IP))
2964 tx_flags |= IGB_TX_FLAGS_IPV4;
2965
0e014cb1
AD		 2966 first = tx_ring->next_to_use;
2967
9d5c8243
AK		 2968 tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
2969 &hdr_len) : 0;
2970
2971 if (tso < 0) {
2972 dev_kfree_skb_any(skb);
9d5c8243
AK		 2973 return NETDEV_TX_OK;
2974 }
2975
2976 if (tso)
2977 tx_flags |= IGB_TX_FLAGS_TSO;
2978 else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags))
2979 if (skb->ip_summed == CHECKSUM_PARTIAL)
2980 tx_flags |= IGB_TX_FLAGS_CSUM;
2981
9d5c8243 2982 igb_tx_queue_adv(adapter, tx_ring, tx_flags,
0e014cb1 2983 igb_tx_map_adv(adapter, tx_ring, skb, first),
9d5c8243
AK		 2984 skb->len, hdr_len);
2985
2986 netdev->trans_start = jiffies;
2987
2988 /* Make sure there is space in the ring for the next send. */
2989 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
2990
9d5c8243
AK		 2991 return NETDEV_TX_OK;
2992}
2993
2994static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *netdev)
2995{
2996 struct igb_adapter *adapter = netdev_priv(netdev);
661086df
PWJ		 2997 struct igb_ring *tx_ring;
2998
661086df
PWJ		 2999 int r_idx = 0;
3000 r_idx = skb->queue_mapping & (IGB_MAX_TX_QUEUES - 1);
3001 tx_ring = adapter->multi_tx_table[r_idx];
9d5c8243
AK		 3002
3003 /* This goes back to the question of how to logically map a tx queue
3004 * to a flow. Right now, performance is impacted slightly negatively
3005 * if using multiple tx queues. If the stack breaks away from a
3006 * single qdisc implementation, we can look at this again. */
3007 return (igb_xmit_frame_ring_adv(skb, netdev, tx_ring));
3008}
3009
3010/**
3011 * igb_tx_timeout - Respond to a Tx Hang
3012 * @netdev: network interface device structure
3013 **/
3014static void igb_tx_timeout(struct net_device *netdev)
3015{
3016 struct igb_adapter *adapter = netdev_priv(netdev);
3017 struct e1000_hw *hw = &adapter->hw;
3018
3019 /* Do the reset outside of interrupt context */
3020 adapter->tx_timeout_count++;
3021 schedule_work(&adapter->reset_task);
3022 wr32(E1000_EICS, adapter->eims_enable_mask &
3023 ~(E1000_EIMS_TCP_TIMER | E1000_EIMS_OTHER));
3024}
3025
3026static void igb_reset_task(struct work_struct *work)
3027{
3028 struct igb_adapter *adapter;
3029 adapter = container_of(work, struct igb_adapter, reset_task);
3030
3031 igb_reinit_locked(adapter);
3032}
3033
3034/**
3035 * igb_get_stats - Get System Network Statistics
3036 * @netdev: network interface device structure
3037 *
3038 * Returns the address of the device statistics structure.
3039 * The statistics are actually updated from the timer callback.
3040 **/
3041static struct net_device_stats *
3042igb_get_stats(struct net_device *netdev)
3043{
3044 struct igb_adapter *adapter = netdev_priv(netdev);
3045
3046 /* only return the current stats */
3047 return &adapter->net_stats;
3048}
3049
3050/**
3051 * igb_change_mtu - Change the Maximum Transfer Unit
3052 * @netdev: network interface device structure
3053 * @new_mtu: new value for maximum frame size
3054 *
3055 * Returns 0 on success, negative on failure
3056 **/
3057static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3058{
3059 struct igb_adapter *adapter = netdev_priv(netdev);
3060 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3061
3062 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
3063 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3064 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
3065 return -EINVAL;
3066 }
3067
3068#define MAX_STD_JUMBO_FRAME_SIZE 9234
3069 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3070 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
3071 return -EINVAL;
3072 }
3073
3074 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3075 msleep(1);
3076 /* igb_down has a dependency on max_frame_size */
3077 adapter->max_frame_size = max_frame;
3078 if (netif_running(netdev))
3079 igb_down(adapter);
3080
3081 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3082 * means we reserve 2 more, this pushes us to allocate from the next
3083 * larger slab size.
3084 * i.e. RXBUFFER_2048 --> size-4096 slab
3085 */
3086
3087 if (max_frame <= IGB_RXBUFFER_256)
3088 adapter->rx_buffer_len = IGB_RXBUFFER_256;
3089 else if (max_frame <= IGB_RXBUFFER_512)
3090 adapter->rx_buffer_len = IGB_RXBUFFER_512;
3091 else if (max_frame <= IGB_RXBUFFER_1024)
3092 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3093 else if (max_frame <= IGB_RXBUFFER_2048)
3094 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
3095 else
bf36c1a0
AD		 3096#if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
3097 adapter->rx_buffer_len = IGB_RXBUFFER_16384;
3098#else
3099 adapter->rx_buffer_len = PAGE_SIZE / 2;
3100#endif
9d5c8243
AK		 3101 /* adjust allocation if LPE protects us, and we aren't using SBP */
3102 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
3103 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
3104 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3105
3106 dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
3107 netdev->mtu, new_mtu);
3108 netdev->mtu = new_mtu;
3109
3110 if (netif_running(netdev))
3111 igb_up(adapter);
3112 else
3113 igb_reset(adapter);
3114
3115 clear_bit(__IGB_RESETTING, &adapter->state);
3116
3117 return 0;
3118}
3119
3120/**
3121 * igb_update_stats - Update the board statistics counters
3122 * @adapter: board private structure
3123 **/
3124
3125void igb_update_stats(struct igb_adapter *adapter)
3126{
3127 struct e1000_hw *hw = &adapter->hw;
3128 struct pci_dev *pdev = adapter->pdev;
3129 u16 phy_tmp;
3130
3131#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3132
3133 /*
3134 * Prevent stats update while adapter is being reset, or if the pci
3135 * connection is down.
3136 */
3137 if (adapter->link_speed == 0)
3138 return;
3139 if (pci_channel_offline(pdev))
3140 return;
3141
3142 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3143 adapter->stats.gprc += rd32(E1000_GPRC);
3144 adapter->stats.gorc += rd32(E1000_GORCL);
3145 rd32(E1000_GORCH); /* clear GORCL */
3146 adapter->stats.bprc += rd32(E1000_BPRC);
3147 adapter->stats.mprc += rd32(E1000_MPRC);
3148 adapter->stats.roc += rd32(E1000_ROC);
3149
3150 adapter->stats.prc64 += rd32(E1000_PRC64);
3151 adapter->stats.prc127 += rd32(E1000_PRC127);
3152 adapter->stats.prc255 += rd32(E1000_PRC255);
3153 adapter->stats.prc511 += rd32(E1000_PRC511);
3154 adapter->stats.prc1023 += rd32(E1000_PRC1023);
3155 adapter->stats.prc1522 += rd32(E1000_PRC1522);
3156 adapter->stats.symerrs += rd32(E1000_SYMERRS);
3157 adapter->stats.sec += rd32(E1000_SEC);
3158
3159 adapter->stats.mpc += rd32(E1000_MPC);
3160 adapter->stats.scc += rd32(E1000_SCC);
3161 adapter->stats.ecol += rd32(E1000_ECOL);
3162 adapter->stats.mcc += rd32(E1000_MCC);
3163 adapter->stats.latecol += rd32(E1000_LATECOL);
3164 adapter->stats.dc += rd32(E1000_DC);
3165 adapter->stats.rlec += rd32(E1000_RLEC);
3166 adapter->stats.xonrxc += rd32(E1000_XONRXC);
3167 adapter->stats.xontxc += rd32(E1000_XONTXC);
3168 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
3169 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
3170 adapter->stats.fcruc += rd32(E1000_FCRUC);
3171 adapter->stats.gptc += rd32(E1000_GPTC);
3172 adapter->stats.gotc += rd32(E1000_GOTCL);
3173 rd32(E1000_GOTCH); /* clear GOTCL */
3174 adapter->stats.rnbc += rd32(E1000_RNBC);
3175 adapter->stats.ruc += rd32(E1000_RUC);
3176 adapter->stats.rfc += rd32(E1000_RFC);
3177 adapter->stats.rjc += rd32(E1000_RJC);
3178 adapter->stats.tor += rd32(E1000_TORH);
3179 adapter->stats.tot += rd32(E1000_TOTH);
3180 adapter->stats.tpr += rd32(E1000_TPR);
3181
3182 adapter->stats.ptc64 += rd32(E1000_PTC64);
3183 adapter->stats.ptc127 += rd32(E1000_PTC127);
3184 adapter->stats.ptc255 += rd32(E1000_PTC255);
3185 adapter->stats.ptc511 += rd32(E1000_PTC511);
3186 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
3187 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
3188
3189 adapter->stats.mptc += rd32(E1000_MPTC);
3190 adapter->stats.bptc += rd32(E1000_BPTC);
3191
3192 /* used for adaptive IFS */
3193
3194 hw->mac.tx_packet_delta = rd32(E1000_TPT);
3195 adapter->stats.tpt += hw->mac.tx_packet_delta;
3196 hw->mac.collision_delta = rd32(E1000_COLC);
3197 adapter->stats.colc += hw->mac.collision_delta;
3198
3199 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
3200 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3201 adapter->stats.tncrs += rd32(E1000_TNCRS);
3202 adapter->stats.tsctc += rd32(E1000_TSCTC);
3203 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
3204
3205 adapter->stats.iac += rd32(E1000_IAC);
3206 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
3207 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
3208 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
3209 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
3210 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
3211 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
3212 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
3213 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
3214
3215 /* Fill out the OS statistics structure */
3216 adapter->net_stats.multicast = adapter->stats.mprc;
3217 adapter->net_stats.collisions = adapter->stats.colc;
3218
3219 /* Rx Errors */
3220
3221 /* RLEC on some newer hardware can be incorrect so build
3222 * our own version based on RUC and ROC */
3223 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3224 adapter->stats.crcerrs + adapter->stats.algnerrc +
3225 adapter->stats.ruc + adapter->stats.roc +
3226 adapter->stats.cexterr;
3227 adapter->net_stats.rx_length_errors = adapter->stats.ruc +
3228 adapter->stats.roc;
3229 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3230 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
3231 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3232
3233 /* Tx Errors */
3234 adapter->net_stats.tx_errors = adapter->stats.ecol +
3235 adapter->stats.latecol;
3236 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3237 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3238 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3239
3240 /* Tx Dropped needs to be maintained elsewhere */
3241
3242 /* Phy Stats */
3243 if (hw->phy.media_type == e1000_media_type_copper) {
3244 if ((adapter->link_speed == SPEED_1000) &&
f5f4cf08 3245 (!igb_read_phy_reg(hw, PHY_1000T_STATUS,
9d5c8243
AK		 3246 &phy_tmp))) {
3247 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3248 adapter->phy_stats.idle_errors += phy_tmp;
3249 }
3250 }
3251
3252 /* Management Stats */
3253 adapter->stats.mgptc += rd32(E1000_MGTPTC);
3254 adapter->stats.mgprc += rd32(E1000_MGTPRC);
3255 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3256}
3257
3258
3259static irqreturn_t igb_msix_other(int irq, void *data)
3260{
3261 struct net_device *netdev = data;
3262 struct igb_adapter *adapter = netdev_priv(netdev);
3263 struct e1000_hw *hw = &adapter->hw;
844290e5 3264 u32 icr = rd32(E1000_ICR);
9d5c8243 3265
844290e5
PW		 3266 /* reading ICR causes bit 31 of EICR to be cleared */
3267 if (!(icr & E1000_ICR_LSC))
3268 goto no_link_interrupt;
3269 hw->mac.get_link_status = 1;
3270 /* guard against interrupt when we're going down */
3271 if (!test_bit(__IGB_DOWN, &adapter->state))
3272 mod_timer(&adapter->watchdog_timer, jiffies + 1);
661086df 3273
9d5c8243
AK		 3274no_link_interrupt:
3275 wr32(E1000_IMS, E1000_IMS_LSC);
844290e5 3276 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 3277
3278 return IRQ_HANDLED;
3279}
3280
3281static irqreturn_t igb_msix_tx(int irq, void *data)
3282{
3283 struct igb_ring *tx_ring = data;
3284 struct igb_adapter *adapter = tx_ring->adapter;
3285 struct e1000_hw *hw = &adapter->hw;
3286
421e02f0 3287#ifdef CONFIG_IGB_DCA
7dfc16fa 3288 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3289 igb_update_tx_dca(tx_ring);
3290#endif
9d5c8243
AK		 3291 tx_ring->total_bytes = 0;
3292 tx_ring->total_packets = 0;
661086df
PWJ		 3293
3294 /* auto mask will automatically reenable the interrupt when we write
3295 * EICS */
3b644cf6 3296 if (!igb_clean_tx_irq(tx_ring))
9d5c8243
AK		 3297 /* Ring was not completely cleaned, so fire another interrupt */
3298 wr32(E1000_EICS, tx_ring->eims_value);
661086df 3299 else
9d5c8243 3300 wr32(E1000_EIMS, tx_ring->eims_value);
661086df 3301
9d5c8243
AK		 3302 return IRQ_HANDLED;
3303}
3304
6eb5a7f1
AD		 3305static void igb_write_itr(struct igb_ring *ring)
3306{
3307 struct e1000_hw *hw = &ring->adapter->hw;
3308 if ((ring->adapter->itr_setting & 3) && ring->set_itr) {
3309 switch (hw->mac.type) {
3310 case e1000_82576:
3311 wr32(ring->itr_register,
3312 ring->itr_val |
3313 0x80000000);
3314 break;
3315 default:
3316 wr32(ring->itr_register,
3317 ring->itr_val |
3318 (ring->itr_val << 16));
3319 break;
3320 }
3321 ring->set_itr = 0;
3322 }
3323}
3324
9d5c8243
AK		 3325static irqreturn_t igb_msix_rx(int irq, void *data)
3326{
3327 struct igb_ring *rx_ring = data;
9d5c8243 3328
844290e5
PW		 3329 /* Write the ITR value calculated at the end of the
3330 * previous interrupt.
3331 */
9d5c8243 3332
6eb5a7f1 3333 igb_write_itr(rx_ring);
9d5c8243 3334
288379f0
BH		 3335 if (napi_schedule_prep(&rx_ring->napi))
3336 __napi_schedule(&rx_ring->napi);
844290e5 3337
421e02f0 3338#ifdef CONFIG_IGB_DCA
8d253320 3339 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3340 igb_update_rx_dca(rx_ring);
3341#endif
3342 return IRQ_HANDLED;
3343}
3344
421e02f0 3345#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 3346static void igb_update_rx_dca(struct igb_ring *rx_ring)
3347{
3348 u32 dca_rxctrl;
3349 struct igb_adapter *adapter = rx_ring->adapter;
3350 struct e1000_hw *hw = &adapter->hw;
3351 int cpu = get_cpu();
26bc19ec 3352 int q = rx_ring->reg_idx;
fe4506b6
JC		 3353
3354 if (rx_ring->cpu != cpu) {
3355 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
2d064c06
AD		 3356 if (hw->mac.type == e1000_82576) {
3357 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
3358 dca_rxctrl |= dca_get_tag(cpu) <<
3359 E1000_DCA_RXCTRL_CPUID_SHIFT;
3360 } else {
3361 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
3362 dca_rxctrl |= dca_get_tag(cpu);
3363 }
fe4506b6
JC		 3364 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
3365 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
3366 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
3367 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
3368 rx_ring->cpu = cpu;
3369 }
3370 put_cpu();
3371}
3372
3373static void igb_update_tx_dca(struct igb_ring *tx_ring)
3374{
3375 u32 dca_txctrl;
3376 struct igb_adapter *adapter = tx_ring->adapter;
3377 struct e1000_hw *hw = &adapter->hw;
3378 int cpu = get_cpu();
26bc19ec 3379 int q = tx_ring->reg_idx;
fe4506b6
JC		 3380
3381 if (tx_ring->cpu != cpu) {
3382 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
2d064c06
AD		 3383 if (hw->mac.type == e1000_82576) {
3384 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
3385 dca_txctrl |= dca_get_tag(cpu) <<
3386 E1000_DCA_TXCTRL_CPUID_SHIFT;
3387 } else {
3388 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
3389 dca_txctrl |= dca_get_tag(cpu);
3390 }
fe4506b6
JC		 3391 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
3392 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
3393 tx_ring->cpu = cpu;
3394 }
3395 put_cpu();
3396}
3397
3398static void igb_setup_dca(struct igb_adapter *adapter)
3399{
3400 int i;
3401
7dfc16fa 3402 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 3403 return;
3404
3405 for (i = 0; i < adapter->num_tx_queues; i++) {
3406 adapter->tx_ring[i].cpu = -1;
3407 igb_update_tx_dca(&adapter->tx_ring[i]);
3408 }
3409 for (i = 0; i < adapter->num_rx_queues; i++) {
3410 adapter->rx_ring[i].cpu = -1;
3411 igb_update_rx_dca(&adapter->rx_ring[i]);
3412 }
3413}
3414
3415static int __igb_notify_dca(struct device *dev, void *data)
3416{
3417 struct net_device *netdev = dev_get_drvdata(dev);
3418 struct igb_adapter *adapter = netdev_priv(netdev);
3419 struct e1000_hw *hw = &adapter->hw;
3420 unsigned long event = *(unsigned long *)data;
3421
3422 switch (event) {
3423 case DCA_PROVIDER_ADD:
3424 /* if already enabled, don't do it again */
7dfc16fa 3425 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 3426 break;
fe4506b6
JC		 3427 /* Always use CB2 mode, difference is masked
3428 * in the CB driver. */
3429 wr32(E1000_DCA_CTRL, 2);
3430 if (dca_add_requester(dev) == 0) {
bbd98fe4 3431 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 3432 dev_info(&adapter->pdev->dev, "DCA enabled\n");
3433 igb_setup_dca(adapter);
3434 break;
3435 }
3436 /* Fall Through since DCA is disabled. */
3437 case DCA_PROVIDER_REMOVE:
7dfc16fa 3438 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 3439 /* without this a class_device is left
3440 * hanging around in the sysfs model */
3441 dca_remove_requester(dev);
3442 dev_info(&adapter->pdev->dev, "DCA disabled\n");
7dfc16fa 3443 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 3444 wr32(E1000_DCA_CTRL, 1);
3445 }
3446 break;
3447 }
bbd98fe4 3448
fe4506b6 3449 return 0;
9d5c8243
AK		 3450}
3451
fe4506b6
JC		 3452static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
3453 void *p)
3454{
3455 int ret_val;
3456
3457 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
3458 __igb_notify_dca);
3459
3460 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
3461}
421e02f0 3462#endif /* CONFIG_IGB_DCA */
9d5c8243
AK		 3463
3464/**
3465 * igb_intr_msi - Interrupt Handler
3466 * @irq: interrupt number
3467 * @data: pointer to a network interface device structure
3468 **/
3469static irqreturn_t igb_intr_msi(int irq, void *data)
3470{
3471 struct net_device *netdev = data;
3472 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 3473 struct e1000_hw *hw = &adapter->hw;
3474 /* read ICR disables interrupts using IAM */
3475 u32 icr = rd32(E1000_ICR);
3476
6eb5a7f1 3477 igb_write_itr(adapter->rx_ring);
9d5c8243 3478
9d5c8243
AK		 3479 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3480 hw->mac.get_link_status = 1;
3481 if (!test_bit(__IGB_DOWN, &adapter->state))
3482 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3483 }
3484
288379f0 3485 napi_schedule(&adapter->rx_ring[0].napi);
9d5c8243
AK		 3486
3487 return IRQ_HANDLED;
3488}
3489
3490/**
3491 * igb_intr - Interrupt Handler
3492 * @irq: interrupt number
3493 * @data: pointer to a network interface device structure
3494 **/
3495static irqreturn_t igb_intr(int irq, void *data)
3496{
3497 struct net_device *netdev = data;
3498 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 3499 struct e1000_hw *hw = &adapter->hw;
3500 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
3501 * need for the IMC write */
3502 u32 icr = rd32(E1000_ICR);
3503 u32 eicr = 0;
3504 if (!icr)
3505 return IRQ_NONE; /* Not our interrupt */
3506
6eb5a7f1 3507 igb_write_itr(adapter->rx_ring);
9d5c8243
AK		 3508
3509 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
3510 * not set, then the adapter didn't send an interrupt */
3511 if (!(icr & E1000_ICR_INT_ASSERTED))
3512 return IRQ_NONE;
3513
3514 eicr = rd32(E1000_EICR);
3515
3516 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3517 hw->mac.get_link_status = 1;
3518 /* guard against interrupt when we're going down */
3519 if (!test_bit(__IGB_DOWN, &adapter->state))
3520 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3521 }
3522
288379f0 3523 napi_schedule(&adapter->rx_ring[0].napi);
9d5c8243
AK		 3524
3525 return IRQ_HANDLED;
3526}
3527
3528/**
661086df
PWJ		 3529 * igb_poll - NAPI Rx polling callback
3530 * @napi: napi polling structure
3531 * @budget: count of how many packets we should handle
9d5c8243 3532 **/
661086df 3533static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 3534{
661086df
PWJ		 3535 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3536 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 3537 struct net_device *netdev = adapter->netdev;
661086df 3538 int tx_clean_complete, work_done = 0;
9d5c8243 3539
661086df 3540 /* this poll routine only supports one tx and one rx queue */
421e02f0 3541#ifdef CONFIG_IGB_DCA
7dfc16fa 3542 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3543 igb_update_tx_dca(&adapter->tx_ring[0]);
3544#endif
661086df 3545 tx_clean_complete = igb_clean_tx_irq(&adapter->tx_ring[0]);
fe4506b6 3546
421e02f0 3547#ifdef CONFIG_IGB_DCA
7dfc16fa 3548 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3549 igb_update_rx_dca(&adapter->rx_ring[0]);
3550#endif
661086df 3551 igb_clean_rx_irq_adv(&adapter->rx_ring[0], &work_done, budget);
9d5c8243
AK		 3552
3553 /* If no Tx and not enough Rx work done, exit the polling mode */
3554 if ((tx_clean_complete && (work_done < budget)) ||
3555 !netif_running(netdev)) {
9d5c8243 3556 if (adapter->itr_setting & 3)
6eb5a7f1 3557 igb_set_itr(adapter);
288379f0 3558 napi_complete(napi);
9d5c8243
AK		 3559 if (!test_bit(__IGB_DOWN, &adapter->state))
3560 igb_irq_enable(adapter);
3561 return 0;
3562 }
3563
3564 return 1;
3565}
3566
3567static int igb_clean_rx_ring_msix(struct napi_struct *napi, int budget)
3568{
3569 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3570 struct igb_adapter *adapter = rx_ring->adapter;
3571 struct e1000_hw *hw = &adapter->hw;
3572 struct net_device *netdev = adapter->netdev;
3573 int work_done = 0;
3574
421e02f0 3575#ifdef CONFIG_IGB_DCA
7dfc16fa 3576 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3577 igb_update_rx_dca(rx_ring);
3578#endif
3b644cf6 3579 igb_clean_rx_irq_adv(rx_ring, &work_done, budget);
9d5c8243
AK		 3580
3581
3582 /* If not enough Rx work done, exit the polling mode */
3583 if ((work_done == 0) || !netif_running(netdev)) {
288379f0 3584 napi_complete(napi);
9d5c8243 3585
6eb5a7f1
AD		 3586 if (adapter->itr_setting & 3) {
3587 if (adapter->num_rx_queues == 1)
3588 igb_set_itr(adapter);
3589 else
3590 igb_update_ring_itr(rx_ring);
9d5c8243 3591 }
844290e5
PW		 3592
3593 if (!test_bit(__IGB_DOWN, &adapter->state))
3594 wr32(E1000_EIMS, rx_ring->eims_value);
3595
9d5c8243
AK		 3596 return 0;
3597 }
3598
3599 return 1;
3600}
6d8126f9 3601
9d5c8243
AK		 3602/**
3603 * igb_clean_tx_irq - Reclaim resources after transmit completes
3604 * @adapter: board private structure
3605 * returns true if ring is completely cleaned
3606 **/
3b644cf6 3607static bool igb_clean_tx_irq(struct igb_ring *tx_ring)
9d5c8243 3608{
3b644cf6 3609 struct igb_adapter *adapter = tx_ring->adapter;
3b644cf6 3610 struct net_device *netdev = adapter->netdev;
0e014cb1 3611 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 3612 struct igb_buffer *buffer_info;
3613 struct sk_buff *skb;
0e014cb1 3614 union e1000_adv_tx_desc *tx_desc, *eop_desc;
9d5c8243 3615 unsigned int total_bytes = 0, total_packets = 0;
0e014cb1
AD		 3616 unsigned int i, eop, count = 0;
3617 bool cleaned = false;
9d5c8243 3618
9d5c8243 3619 i = tx_ring->next_to_clean;
0e014cb1
AD		 3620 eop = tx_ring->buffer_info[i].next_to_watch;
3621 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
3622
3623 while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) &&
3624 (count < tx_ring->count)) {
3625 for (cleaned = false; !cleaned; count++) {
3626 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
9d5c8243 3627 buffer_info = &tx_ring->buffer_info[i];
0e014cb1 3628 cleaned = (i == eop);
9d5c8243
AK		 3629 skb = buffer_info->skb;
3630
3631 if (skb) {
3632 unsigned int segs, bytecount;
3633 /* gso_segs is currently only valid for tcp */
3634 segs = skb_shinfo(skb)->gso_segs ?: 1;
3635 /* multiply data chunks by size of headers */
3636 bytecount = ((segs - 1) * skb_headlen(skb)) +
3637 skb->len;
3638 total_packets += segs;
3639 total_bytes += bytecount;
3640 }
3641
3642 igb_unmap_and_free_tx_resource(adapter, buffer_info);
0e014cb1 3643 tx_desc->wb.status = 0;
9d5c8243
AK		 3644
3645 i++;
3646 if (i == tx_ring->count)
3647 i = 0;
9d5c8243 3648 }
0e014cb1
AD		 3649
3650 eop = tx_ring->buffer_info[i].next_to_watch;
3651 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
3652 }
3653
9d5c8243
AK		 3654 tx_ring->next_to_clean = i;
3655
fc7d345d 3656 if (unlikely(count &&
9d5c8243
AK		 3657 netif_carrier_ok(netdev) &&
3658 IGB_DESC_UNUSED(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
3659 /* Make sure that anybody stopping the queue after this
3660 * sees the new next_to_clean.
3661 */
3662 smp_mb();
661086df
PWJ		 3663 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
3664 !(test_bit(__IGB_DOWN, &adapter->state))) {
3665 netif_wake_subqueue(netdev, tx_ring->queue_index);
3666 ++adapter->restart_queue;
3667 }
9d5c8243
AK		 3668 }
3669
3670 if (tx_ring->detect_tx_hung) {
3671 /* Detect a transmit hang in hardware, this serializes the
3672 * check with the clearing of time_stamp and movement of i */
3673 tx_ring->detect_tx_hung = false;
3674 if (tx_ring->buffer_info[i].time_stamp &&
3675 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
3676 (adapter->tx_timeout_factor * HZ))
3677 && !(rd32(E1000_STATUS) &
3678 E1000_STATUS_TXOFF)) {
3679
9d5c8243
AK		 3680 /* detected Tx unit hang */
3681 dev_err(&adapter->pdev->dev,
3682 "Detected Tx Unit Hang\n"
2d064c06 3683 " Tx Queue <%d>\n"
9d5c8243
AK		 3684 " TDH <%x>\n"
3685 " TDT <%x>\n"
3686 " next_to_use <%x>\n"
3687 " next_to_clean <%x>\n"
9d5c8243
AK		 3688 "buffer_info[next_to_clean]\n"
3689 " time_stamp <%lx>\n"
0e014cb1 3690 " next_to_watch <%x>\n"
9d5c8243
AK		 3691 " jiffies <%lx>\n"
3692 " desc.status <%x>\n",
2d064c06 3693 tx_ring->queue_index,
9d5c8243
AK		 3694 readl(adapter->hw.hw_addr + tx_ring->head),
3695 readl(adapter->hw.hw_addr + tx_ring->tail),
3696 tx_ring->next_to_use,
3697 tx_ring->next_to_clean,
9d5c8243 3698 tx_ring->buffer_info[i].time_stamp,
0e014cb1 3699 eop,
9d5c8243 3700 jiffies,
0e014cb1 3701 eop_desc->wb.status);
661086df 3702 netif_stop_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 3703 }
3704 }
3705 tx_ring->total_bytes += total_bytes;
3706 tx_ring->total_packets += total_packets;
e21ed353
AD		 3707 tx_ring->tx_stats.bytes += total_bytes;
3708 tx_ring->tx_stats.packets += total_packets;
9d5c8243
AK		 3709 adapter->net_stats.tx_bytes += total_bytes;
3710 adapter->net_stats.tx_packets += total_packets;
0e014cb1 3711 return (count < tx_ring->count);
9d5c8243
AK		 3712}
3713
9d5c8243
AK		 3714/**
3715 * igb_receive_skb - helper function to handle rx indications
d3352520 3716 * @ring: pointer to receive ring receving this packet
9d5c8243
AK		 3717 * @status: descriptor status field as written by hardware
3718 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
3719 * @skb: pointer to sk_buff to be indicated to stack
3720 **/
d3352520
AD		 3721static void igb_receive_skb(struct igb_ring *ring, u8 status,
3722 union e1000_adv_rx_desc * rx_desc,
3723 struct sk_buff *skb)
3724{
3725 struct igb_adapter * adapter = ring->adapter;
3726 bool vlan_extracted = (adapter->vlgrp && (status & E1000_RXD_STAT_VP));
3727
0c8dfc83 3728 skb_record_rx_queue(skb, ring->queue_index);
5c0999b7 3729 if (skb->ip_summed == CHECKSUM_UNNECESSARY) {
d3352520 3730 if (vlan_extracted)
5c0999b7
HX		 3731 vlan_gro_receive(&ring->napi, adapter->vlgrp,
3732 le16_to_cpu(rx_desc->wb.upper.vlan),
3733 skb);
d3352520 3734 else
5c0999b7 3735 napi_gro_receive(&ring->napi, skb);
d3352520 3736 } else {
d3352520
AD		 3737 if (vlan_extracted)
3738 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
3739 le16_to_cpu(rx_desc->wb.upper.vlan));
3740 else
d3352520 3741 netif_receive_skb(skb);
d3352520 3742 }
9d5c8243
AK		 3743}
3744
3745
3746static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
3747 u32 status_err, struct sk_buff *skb)
3748{
3749 skb->ip_summed = CHECKSUM_NONE;
3750
3751 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
3752 if ((status_err & E1000_RXD_STAT_IXSM) || !adapter->rx_csum)
3753 return;
3754 /* TCP/UDP checksum error bit is set */
3755 if (status_err &
3756 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
3757 /* let the stack verify checksum errors */
3758 adapter->hw_csum_err++;
3759 return;
3760 }
3761 /* It must be a TCP or UDP packet with a valid checksum */
3762 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
3763 skb->ip_summed = CHECKSUM_UNNECESSARY;
3764
3765 adapter->hw_csum_good++;
3766}
3767
3b644cf6
MW		 3768static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring,
3769 int *work_done, int budget)
9d5c8243 3770{
3b644cf6 3771 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 3772 struct net_device *netdev = adapter->netdev;
3773 struct pci_dev *pdev = adapter->pdev;
3774 union e1000_adv_rx_desc *rx_desc , *next_rxd;
3775 struct igb_buffer *buffer_info , *next_buffer;
3776 struct sk_buff *skb;
bf36c1a0 3777 unsigned int i;
9d5c8243
AK		 3778 u32 length, hlen, staterr;
3779 bool cleaned = false;
3780 int cleaned_count = 0;
3781 unsigned int total_bytes = 0, total_packets = 0;
3782
3783 i = rx_ring->next_to_clean;
69d3ca53 3784 buffer_info = &rx_ring->buffer_info[i];
9d5c8243
AK		 3785 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3786 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3787
3788 while (staterr & E1000_RXD_STAT_DD) {
3789 if (*work_done >= budget)
3790 break;
3791 (*work_done)++;
9d5c8243 3792
69d3ca53
AD		 3793 skb = buffer_info->skb;
3794 prefetch(skb->data - NET_IP_ALIGN);
3795 buffer_info->skb = NULL;
3796
3797 i++;
3798 if (i == rx_ring->count)
3799 i = 0;
3800 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
3801 prefetch(next_rxd);
3802 next_buffer = &rx_ring->buffer_info[i];
9d5c8243
AK		 3803
3804 length = le16_to_cpu(rx_desc->wb.upper.length);
3805 cleaned = true;
3806 cleaned_count++;
3807
bf36c1a0
AD		 3808 if (!adapter->rx_ps_hdr_size) {
3809 pci_unmap_single(pdev, buffer_info->dma,
3810 adapter->rx_buffer_len +
3811 NET_IP_ALIGN,
3812 PCI_DMA_FROMDEVICE);
3813 skb_put(skb, length);
3814 goto send_up;
9d5c8243
AK		 3815 }
3816
69d3ca53
AD		 3817 /* HW will not DMA in data larger than the given buffer, even
3818 * if it parses the (NFS, of course) header to be larger. In
3819 * that case, it fills the header buffer and spills the rest
3820 * into the page.
3821 */
3822 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
3823 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
3824 if (hlen > adapter->rx_ps_hdr_size)
3825 hlen = adapter->rx_ps_hdr_size;
3826
bf36c1a0
AD		 3827 if (!skb_shinfo(skb)->nr_frags) {
3828 pci_unmap_single(pdev, buffer_info->dma,
3829 adapter->rx_ps_hdr_size +
3830 NET_IP_ALIGN,
3831 PCI_DMA_FROMDEVICE);
3832 skb_put(skb, hlen);
3833 }
3834
3835 if (length) {
9d5c8243 3836 pci_unmap_page(pdev, buffer_info->page_dma,
bf36c1a0 3837 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9d5c8243 3838 buffer_info->page_dma = 0;
bf36c1a0
AD		 3839
3840 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
3841 buffer_info->page,
3842 buffer_info->page_offset,
3843 length);
3844
3845 if ((adapter->rx_buffer_len > (PAGE_SIZE / 2)) ||
3846 (page_count(buffer_info->page) != 1))
3847 buffer_info->page = NULL;
3848 else
3849 get_page(buffer_info->page);
9d5c8243
AK		 3850
3851 skb->len += length;
3852 skb->data_len += length;
9d5c8243 3853
bf36c1a0 3854 skb->truesize += length;
9d5c8243 3855 }
9d5c8243 3856
bf36c1a0 3857 if (!(staterr & E1000_RXD_STAT_EOP)) {
b2d56536
AD		 3858 buffer_info->skb = next_buffer->skb;
3859 buffer_info->dma = next_buffer->dma;
3860 next_buffer->skb = skb;
3861 next_buffer->dma = 0;
bf36c1a0
AD		 3862 goto next_desc;
3863 }
69d3ca53 3864send_up:
9d5c8243
AK		 3865 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
3866 dev_kfree_skb_irq(skb);
3867 goto next_desc;
3868 }
9d5c8243
AK		 3869
3870 total_bytes += skb->len;
3871 total_packets++;
3872
3873 igb_rx_checksum_adv(adapter, staterr, skb);
3874
3875 skb->protocol = eth_type_trans(skb, netdev);
3876
d3352520 3877 igb_receive_skb(rx_ring, staterr, rx_desc, skb);
9d5c8243 3878
9d5c8243
AK		 3879next_desc:
3880 rx_desc->wb.upper.status_error = 0;
3881
3882 /* return some buffers to hardware, one at a time is too slow */
3883 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
3b644cf6 3884 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 3885 cleaned_count = 0;
3886 }
3887
3888 /* use prefetched values */
3889 rx_desc = next_rxd;
3890 buffer_info = next_buffer;
9d5c8243
AK		 3891 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3892 }
bf36c1a0 3893
9d5c8243
AK		 3894 rx_ring->next_to_clean = i;
3895 cleaned_count = IGB_DESC_UNUSED(rx_ring);
3896
3897 if (cleaned_count)
3b644cf6 3898 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 3899
3900 rx_ring->total_packets += total_packets;
3901 rx_ring->total_bytes += total_bytes;
3902 rx_ring->rx_stats.packets += total_packets;
3903 rx_ring->rx_stats.bytes += total_bytes;
3904 adapter->net_stats.rx_bytes += total_bytes;
3905 adapter->net_stats.rx_packets += total_packets;
3906 return cleaned;
3907}
3908
3909
3910/**
3911 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
3912 * @adapter: address of board private structure
3913 **/
3b644cf6 3914static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
9d5c8243
AK		 3915 int cleaned_count)
3916{
3b644cf6 3917 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 3918 struct net_device *netdev = adapter->netdev;
3919 struct pci_dev *pdev = adapter->pdev;
3920 union e1000_adv_rx_desc *rx_desc;
3921 struct igb_buffer *buffer_info;
3922 struct sk_buff *skb;
3923 unsigned int i;
db761762 3924 int bufsz;
9d5c8243
AK		 3925
3926 i = rx_ring->next_to_use;
3927 buffer_info = &rx_ring->buffer_info[i];
3928
db761762
AD		 3929 if (adapter->rx_ps_hdr_size)
3930 bufsz = adapter->rx_ps_hdr_size;
3931 else
3932 bufsz = adapter->rx_buffer_len;
3933 bufsz += NET_IP_ALIGN;
3934
9d5c8243
AK		 3935 while (cleaned_count--) {
3936 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3937
bf36c1a0 3938 if (adapter->rx_ps_hdr_size && !buffer_info->page_dma) {
9d5c8243 3939 if (!buffer_info->page) {
bf36c1a0
AD		 3940 buffer_info->page = alloc_page(GFP_ATOMIC);
3941 if (!buffer_info->page) {
3942 adapter->alloc_rx_buff_failed++;
3943 goto no_buffers;
3944 }
3945 buffer_info->page_offset = 0;
3946 } else {
3947 buffer_info->page_offset ^= PAGE_SIZE / 2;
9d5c8243
AK		 3948 }
3949 buffer_info->page_dma =
db761762 3950 pci_map_page(pdev, buffer_info->page,
bf36c1a0
AD		 3951 buffer_info->page_offset,
3952 PAGE_SIZE / 2,
9d5c8243
AK		 3953 PCI_DMA_FROMDEVICE);
3954 }
3955
3956 if (!buffer_info->skb) {
9d5c8243 3957 skb = netdev_alloc_skb(netdev, bufsz);
9d5c8243
AK		 3958 if (!skb) {
3959 adapter->alloc_rx_buff_failed++;
3960 goto no_buffers;
3961 }
3962
3963 /* Make buffer alignment 2 beyond a 16 byte boundary
3964 * this will result in a 16 byte aligned IP header after
3965 * the 14 byte MAC header is removed
3966 */
3967 skb_reserve(skb, NET_IP_ALIGN);
3968
3969 buffer_info->skb = skb;
3970 buffer_info->dma = pci_map_single(pdev, skb->data,
3971 bufsz,
3972 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 3973 }
3974 /* Refresh the desc even if buffer_addrs didn't change because
3975 * each write-back erases this info. */
3976 if (adapter->rx_ps_hdr_size) {
3977 rx_desc->read.pkt_addr =
3978 cpu_to_le64(buffer_info->page_dma);
3979 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
3980 } else {
3981 rx_desc->read.pkt_addr =
3982 cpu_to_le64(buffer_info->dma);
3983 rx_desc->read.hdr_addr = 0;
3984 }
3985
3986 i++;
3987 if (i == rx_ring->count)
3988 i = 0;
3989 buffer_info = &rx_ring->buffer_info[i];
3990 }
3991
3992no_buffers:
3993 if (rx_ring->next_to_use != i) {
3994 rx_ring->next_to_use = i;
3995 if (i == 0)
3996 i = (rx_ring->count - 1);
3997 else
3998 i--;
3999
4000 /* Force memory writes to complete before letting h/w
4001 * know there are new descriptors to fetch. (Only
4002 * applicable for weak-ordered memory model archs,
4003 * such as IA-64). */
4004 wmb();
4005 writel(i, adapter->hw.hw_addr + rx_ring->tail);
4006 }
4007}
4008
4009/**
4010 * igb_mii_ioctl -
4011 * @netdev:
4012 * @ifreq:
4013 * @cmd:
4014 **/
4015static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4016{
4017 struct igb_adapter *adapter = netdev_priv(netdev);
4018 struct mii_ioctl_data *data = if_mii(ifr);
4019
4020 if (adapter->hw.phy.media_type != e1000_media_type_copper)
4021 return -EOPNOTSUPP;
4022
4023 switch (cmd) {
4024 case SIOCGMIIPHY:
4025 data->phy_id = adapter->hw.phy.addr;
4026 break;
4027 case SIOCGMIIREG:
4028 if (!capable(CAP_NET_ADMIN))
4029 return -EPERM;
f5f4cf08
AD		 4030 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
4031 &data->val_out))
9d5c8243
AK		 4032 return -EIO;
4033 break;
4034 case SIOCSMIIREG:
4035 default:
4036 return -EOPNOTSUPP;
4037 }
4038 return 0;
4039}
4040
4041/**
4042 * igb_ioctl -
4043 * @netdev:
4044 * @ifreq:
4045 * @cmd:
4046 **/
4047static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4048{
4049 switch (cmd) {
4050 case SIOCGMIIPHY:
4051 case SIOCGMIIREG:
4052 case SIOCSMIIREG:
4053 return igb_mii_ioctl(netdev, ifr, cmd);
4054 default:
4055 return -EOPNOTSUPP;
4056 }
4057}
4058
4059static void igb_vlan_rx_register(struct net_device *netdev,
4060 struct vlan_group *grp)
4061{
4062 struct igb_adapter *adapter = netdev_priv(netdev);
4063 struct e1000_hw *hw = &adapter->hw;
4064 u32 ctrl, rctl;
4065
4066 igb_irq_disable(adapter);
4067 adapter->vlgrp = grp;
4068
4069 if (grp) {
4070 /* enable VLAN tag insert/strip */
4071 ctrl = rd32(E1000_CTRL);
4072 ctrl |= E1000_CTRL_VME;
4073 wr32(E1000_CTRL, ctrl);
4074
4075 /* enable VLAN receive filtering */
4076 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 4077 rctl &= ~E1000_RCTL_CFIEN;
4078 wr32(E1000_RCTL, rctl);
4079 igb_update_mng_vlan(adapter);
4080 wr32(E1000_RLPML,
4081 adapter->max_frame_size + VLAN_TAG_SIZE);
4082 } else {
4083 /* disable VLAN tag insert/strip */
4084 ctrl = rd32(E1000_CTRL);
4085 ctrl &= ~E1000_CTRL_VME;
4086 wr32(E1000_CTRL, ctrl);
4087
9d5c8243
AK		 4088 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
4089 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4090 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
4091 }
4092 wr32(E1000_RLPML,
4093 adapter->max_frame_size);
4094 }
4095
4096 if (!test_bit(__IGB_DOWN, &adapter->state))
4097 igb_irq_enable(adapter);
4098}
4099
4100static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
4101{
4102 struct igb_adapter *adapter = netdev_priv(netdev);
4103 struct e1000_hw *hw = &adapter->hw;
4104 u32 vfta, index;
4105
4106 if ((adapter->hw.mng_cookie.status &
4107 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4108 (vid == adapter->mng_vlan_id))
4109 return;
4110 /* add VID to filter table */
4111 index = (vid >> 5) & 0x7F;
4112 vfta = array_rd32(E1000_VFTA, index);
4113 vfta |= (1 << (vid & 0x1F));
4114 igb_write_vfta(&adapter->hw, index, vfta);
4115}
4116
4117static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
4118{
4119 struct igb_adapter *adapter = netdev_priv(netdev);
4120 struct e1000_hw *hw = &adapter->hw;
4121 u32 vfta, index;
4122
4123 igb_irq_disable(adapter);
4124 vlan_group_set_device(adapter->vlgrp, vid, NULL);
4125
4126 if (!test_bit(__IGB_DOWN, &adapter->state))
4127 igb_irq_enable(adapter);
4128
4129 if ((adapter->hw.mng_cookie.status &
4130 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4131 (vid == adapter->mng_vlan_id)) {
4132 /* release control to f/w */
4133 igb_release_hw_control(adapter);
4134 return;
4135 }
4136
4137 /* remove VID from filter table */
4138 index = (vid >> 5) & 0x7F;
4139 vfta = array_rd32(E1000_VFTA, index);
4140 vfta &= ~(1 << (vid & 0x1F));
4141 igb_write_vfta(&adapter->hw, index, vfta);
4142}
4143
4144static void igb_restore_vlan(struct igb_adapter *adapter)
4145{
4146 igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
4147
4148 if (adapter->vlgrp) {
4149 u16 vid;
4150 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
4151 if (!vlan_group_get_device(adapter->vlgrp, vid))
4152 continue;
4153 igb_vlan_rx_add_vid(adapter->netdev, vid);
4154 }
4155 }
4156}
4157
4158int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
4159{
4160 struct e1000_mac_info *mac = &adapter->hw.mac;
4161
4162 mac->autoneg = 0;
4163
4164 /* Fiber NICs only allow 1000 gbps Full duplex */
4165 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) &&
4166 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
4167 dev_err(&adapter->pdev->dev,
4168 "Unsupported Speed/Duplex configuration\n");
4169 return -EINVAL;
4170 }
4171
4172 switch (spddplx) {
4173 case SPEED_10 + DUPLEX_HALF:
4174 mac->forced_speed_duplex = ADVERTISE_10_HALF;
4175 break;
4176 case SPEED_10 + DUPLEX_FULL:
4177 mac->forced_speed_duplex = ADVERTISE_10_FULL;
4178 break;
4179 case SPEED_100 + DUPLEX_HALF:
4180 mac->forced_speed_duplex = ADVERTISE_100_HALF;
4181 break;
4182 case SPEED_100 + DUPLEX_FULL:
4183 mac->forced_speed_duplex = ADVERTISE_100_FULL;
4184 break;
4185 case SPEED_1000 + DUPLEX_FULL:
4186 mac->autoneg = 1;
4187 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
4188 break;
4189 case SPEED_1000 + DUPLEX_HALF: /* not supported */
4190 default:
4191 dev_err(&adapter->pdev->dev,
4192 "Unsupported Speed/Duplex configuration\n");
4193 return -EINVAL;
4194 }
4195 return 0;
4196}
4197
4198
4199static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
4200{
4201 struct net_device *netdev = pci_get_drvdata(pdev);
4202 struct igb_adapter *adapter = netdev_priv(netdev);
4203 struct e1000_hw *hw = &adapter->hw;
2d064c06 4204 u32 ctrl, rctl, status;
9d5c8243
AK		 4205 u32 wufc = adapter->wol;
4206#ifdef CONFIG_PM
4207 int retval = 0;
4208#endif
4209
4210 netif_device_detach(netdev);
4211
a88f10ec
AD		 4212 if (netif_running(netdev))
4213 igb_close(netdev);
4214
4215 igb_reset_interrupt_capability(adapter);
4216
4217 igb_free_queues(adapter);
9d5c8243
AK		 4218
4219#ifdef CONFIG_PM
4220 retval = pci_save_state(pdev);
4221 if (retval)
4222 return retval;
4223#endif
4224
4225 status = rd32(E1000_STATUS);
4226 if (status & E1000_STATUS_LU)
4227 wufc &= ~E1000_WUFC_LNKC;
4228
4229 if (wufc) {
4230 igb_setup_rctl(adapter);
4231 igb_set_multi(netdev);
4232
4233 /* turn on all-multi mode if wake on multicast is enabled */
4234 if (wufc & E1000_WUFC_MC) {
4235 rctl = rd32(E1000_RCTL);
4236 rctl |= E1000_RCTL_MPE;
4237 wr32(E1000_RCTL, rctl);
4238 }
4239
4240 ctrl = rd32(E1000_CTRL);
4241 /* advertise wake from D3Cold */
4242 #define E1000_CTRL_ADVD3WUC 0x00100000
4243 /* phy power management enable */
4244 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
4245 ctrl |= E1000_CTRL_ADVD3WUC;
4246 wr32(E1000_CTRL, ctrl);
4247
9d5c8243
AK		 4248 /* Allow time for pending master requests to run */
4249 igb_disable_pcie_master(&adapter->hw);
4250
4251 wr32(E1000_WUC, E1000_WUC_PME_EN);
4252 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 4253 } else {
4254 wr32(E1000_WUC, 0);
4255 wr32(E1000_WUFC, 0);
9d5c8243
AK		 4256 }
4257
2d064c06
AD		 4258 /* make sure adapter isn't asleep if manageability/wol is enabled */
4259 if (wufc || adapter->en_mng_pt) {
9d5c8243
AK		 4260 pci_enable_wake(pdev, PCI_D3hot, 1);
4261 pci_enable_wake(pdev, PCI_D3cold, 1);
2d064c06
AD		 4262 } else {
4263 igb_shutdown_fiber_serdes_link_82575(hw);
4264 pci_enable_wake(pdev, PCI_D3hot, 0);
4265 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243
AK		 4266 }
4267
4268 /* Release control of h/w to f/w. If f/w is AMT enabled, this
4269 * would have already happened in close and is redundant. */
4270 igb_release_hw_control(adapter);
4271
4272 pci_disable_device(pdev);
4273
4274 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4275
4276 return 0;
4277}
4278
4279#ifdef CONFIG_PM
4280static int igb_resume(struct pci_dev *pdev)
4281{
4282 struct net_device *netdev = pci_get_drvdata(pdev);
4283 struct igb_adapter *adapter = netdev_priv(netdev);
4284 struct e1000_hw *hw = &adapter->hw;
4285 u32 err;
4286
4287 pci_set_power_state(pdev, PCI_D0);
4288 pci_restore_state(pdev);
42bfd33a 4289
aed5dec3 4290 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 4291 if (err) {
4292 dev_err(&pdev->dev,
4293 "igb: Cannot enable PCI device from suspend\n");
4294 return err;
4295 }
4296 pci_set_master(pdev);
4297
4298 pci_enable_wake(pdev, PCI_D3hot, 0);
4299 pci_enable_wake(pdev, PCI_D3cold, 0);
4300
a88f10ec
AD		 4301 igb_set_interrupt_capability(adapter);
4302
4303 if (igb_alloc_queues(adapter)) {
4304 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
4305 return -ENOMEM;
9d5c8243
AK		 4306 }
4307
4308 /* e1000_power_up_phy(adapter); */
4309
4310 igb_reset(adapter);
4311 wr32(E1000_WUS, ~0);
4312
a88f10ec
AD		 4313 if (netif_running(netdev)) {
4314 err = igb_open(netdev);
4315 if (err)
4316 return err;
4317 }
9d5c8243
AK		 4318
4319 netif_device_attach(netdev);
4320
4321 /* let the f/w know that the h/w is now under the control of the
4322 * driver. */
4323 igb_get_hw_control(adapter);
4324
4325 return 0;
4326}
4327#endif
4328
4329static void igb_shutdown(struct pci_dev *pdev)
4330{
4331 igb_suspend(pdev, PMSG_SUSPEND);
4332}
4333
4334#ifdef CONFIG_NET_POLL_CONTROLLER
4335/*
4336 * Polling 'interrupt' - used by things like netconsole to send skbs
4337 * without having to re-enable interrupts. It's not called while
4338 * the interrupt routine is executing.
4339 */
4340static void igb_netpoll(struct net_device *netdev)
4341{
4342 struct igb_adapter *adapter = netdev_priv(netdev);
4343 int i;
4344 int work_done = 0;
4345
4346 igb_irq_disable(adapter);
7dfc16fa
AD		 4347 adapter->flags |= IGB_FLAG_IN_NETPOLL;
4348
9d5c8243 4349 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 4350 igb_clean_tx_irq(&adapter->tx_ring[i]);
9d5c8243
AK		 4351
4352 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 4353 igb_clean_rx_irq_adv(&adapter->rx_ring[i],
9d5c8243
AK		 4354 &work_done,
4355 adapter->rx_ring[i].napi.weight);
4356
7dfc16fa 4357 adapter->flags &= ~IGB_FLAG_IN_NETPOLL;
9d5c8243
AK		 4358 igb_irq_enable(adapter);
4359}
4360#endif /* CONFIG_NET_POLL_CONTROLLER */
4361
4362/**
4363 * igb_io_error_detected - called when PCI error is detected
4364 * @pdev: Pointer to PCI device
4365 * @state: The current pci connection state
4366 *
4367 * This function is called after a PCI bus error affecting
4368 * this device has been detected.
4369 */
4370static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
4371 pci_channel_state_t state)
4372{
4373 struct net_device *netdev = pci_get_drvdata(pdev);
4374 struct igb_adapter *adapter = netdev_priv(netdev);
4375
4376 netif_device_detach(netdev);
4377
4378 if (netif_running(netdev))
4379 igb_down(adapter);
4380 pci_disable_device(pdev);
4381
4382 /* Request a slot slot reset. */
4383 return PCI_ERS_RESULT_NEED_RESET;
4384}
4385
4386/**
4387 * igb_io_slot_reset - called after the pci bus has been reset.
4388 * @pdev: Pointer to PCI device
4389 *
4390 * Restart the card from scratch, as if from a cold-boot. Implementation
4391 * resembles the first-half of the igb_resume routine.
4392 */
4393static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
4394{
4395 struct net_device *netdev = pci_get_drvdata(pdev);
4396 struct igb_adapter *adapter = netdev_priv(netdev);
4397 struct e1000_hw *hw = &adapter->hw;
40a914fa 4398 pci_ers_result_t result;
42bfd33a 4399 int err;
9d5c8243 4400
aed5dec3 4401 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 4402 dev_err(&pdev->dev,
4403 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 4404 result = PCI_ERS_RESULT_DISCONNECT;
4405 } else {
4406 pci_set_master(pdev);
4407 pci_restore_state(pdev);
9d5c8243 4408
40a914fa
AD		 4409 pci_enable_wake(pdev, PCI_D3hot, 0);
4410 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 4411
40a914fa
AD		 4412 igb_reset(adapter);
4413 wr32(E1000_WUS, ~0);
4414 result = PCI_ERS_RESULT_RECOVERED;
4415 }
9d5c8243 4416
ea943d41
JK		 4417 err = pci_cleanup_aer_uncorrect_error_status(pdev);
4418 if (err) {
4419 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
4420 "failed 0x%0x\n", err);
4421 /* non-fatal, continue */
4422 }
40a914fa
AD		 4423
4424 return result;
9d5c8243
AK		 4425}
4426
4427/**
4428 * igb_io_resume - called when traffic can start flowing again.
4429 * @pdev: Pointer to PCI device
4430 *
4431 * This callback is called when the error recovery driver tells us that
4432 * its OK to resume normal operation. Implementation resembles the
4433 * second-half of the igb_resume routine.
4434 */
4435static void igb_io_resume(struct pci_dev *pdev)
4436{
4437 struct net_device *netdev = pci_get_drvdata(pdev);
4438 struct igb_adapter *adapter = netdev_priv(netdev);
4439
9d5c8243
AK		 4440 if (netif_running(netdev)) {
4441 if (igb_up(adapter)) {
4442 dev_err(&pdev->dev, "igb_up failed after reset\n");
4443 return;
4444 }
4445 }
4446
4447 netif_device_attach(netdev);
4448
4449 /* let the f/w know that the h/w is now under the control of the
4450 * driver. */
4451 igb_get_hw_control(adapter);
9d5c8243
AK		 4452}
4453
4454/* igb_main.c */
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