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9d5c8243 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel(R) Gigabit Ethernet Linux driver | |
86d5d38f | 4 | Copyright(c) 2007-2009 Intel Corporation. |
9d5c8243 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #include <linux/module.h> | |
29 | #include <linux/types.h> | |
30 | #include <linux/init.h> | |
31 | #include <linux/vmalloc.h> | |
32 | #include <linux/pagemap.h> | |
33 | #include <linux/netdevice.h> | |
9d5c8243 AK |
34 | #include <linux/ipv6.h> |
35 | #include <net/checksum.h> | |
36 | #include <net/ip6_checksum.h> | |
c6cb090b | 37 | #include <linux/net_tstamp.h> |
9d5c8243 AK |
38 | #include <linux/mii.h> |
39 | #include <linux/ethtool.h> | |
40 | #include <linux/if_vlan.h> | |
41 | #include <linux/pci.h> | |
c54106bb | 42 | #include <linux/pci-aspm.h> |
9d5c8243 AK |
43 | #include <linux/delay.h> |
44 | #include <linux/interrupt.h> | |
45 | #include <linux/if_ether.h> | |
40a914fa | 46 | #include <linux/aer.h> |
421e02f0 | 47 | #ifdef CONFIG_IGB_DCA |
fe4506b6 JC |
48 | #include <linux/dca.h> |
49 | #endif | |
9d5c8243 AK |
50 | #include "igb.h" |
51 | ||
86d5d38f | 52 | #define DRV_VERSION "1.3.16-k2" |
9d5c8243 AK |
53 | char igb_driver_name[] = "igb"; |
54 | char igb_driver_version[] = DRV_VERSION; | |
55 | static const char igb_driver_string[] = | |
56 | "Intel(R) Gigabit Ethernet Network Driver"; | |
86d5d38f | 57 | static const char igb_copyright[] = "Copyright (c) 2007-2009 Intel Corporation."; |
9d5c8243 | 58 | |
9d5c8243 AK |
59 | static const struct e1000_info *igb_info_tbl[] = { |
60 | [board_82575] = &e1000_82575_info, | |
61 | }; | |
62 | ||
63 | static struct pci_device_id igb_pci_tbl[] = { | |
2d064c06 | 64 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, |
9eb2341d | 65 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, |
2d064c06 AD |
66 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, |
67 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, | |
c8ea5ea9 | 68 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, |
9d5c8243 AK |
69 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, |
70 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, | |
71 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, | |
72 | /* required last entry */ | |
73 | {0, } | |
74 | }; | |
75 | ||
76 | MODULE_DEVICE_TABLE(pci, igb_pci_tbl); | |
77 | ||
78 | void igb_reset(struct igb_adapter *); | |
79 | static int igb_setup_all_tx_resources(struct igb_adapter *); | |
80 | static int igb_setup_all_rx_resources(struct igb_adapter *); | |
81 | static void igb_free_all_tx_resources(struct igb_adapter *); | |
82 | static void igb_free_all_rx_resources(struct igb_adapter *); | |
9d5c8243 AK |
83 | void igb_update_stats(struct igb_adapter *); |
84 | static int igb_probe(struct pci_dev *, const struct pci_device_id *); | |
85 | static void __devexit igb_remove(struct pci_dev *pdev); | |
86 | static int igb_sw_init(struct igb_adapter *); | |
87 | static int igb_open(struct net_device *); | |
88 | static int igb_close(struct net_device *); | |
89 | static void igb_configure_tx(struct igb_adapter *); | |
90 | static void igb_configure_rx(struct igb_adapter *); | |
91 | static void igb_setup_rctl(struct igb_adapter *); | |
92 | static void igb_clean_all_tx_rings(struct igb_adapter *); | |
93 | static void igb_clean_all_rx_rings(struct igb_adapter *); | |
3b644cf6 MW |
94 | static void igb_clean_tx_ring(struct igb_ring *); |
95 | static void igb_clean_rx_ring(struct igb_ring *); | |
9d5c8243 AK |
96 | static void igb_set_multi(struct net_device *); |
97 | static void igb_update_phy_info(unsigned long); | |
98 | static void igb_watchdog(unsigned long); | |
99 | static void igb_watchdog_task(struct work_struct *); | |
100 | static int igb_xmit_frame_ring_adv(struct sk_buff *, struct net_device *, | |
101 | struct igb_ring *); | |
102 | static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *); | |
103 | static struct net_device_stats *igb_get_stats(struct net_device *); | |
104 | static int igb_change_mtu(struct net_device *, int); | |
105 | static int igb_set_mac(struct net_device *, void *); | |
106 | static irqreturn_t igb_intr(int irq, void *); | |
107 | static irqreturn_t igb_intr_msi(int irq, void *); | |
108 | static irqreturn_t igb_msix_other(int irq, void *); | |
109 | static irqreturn_t igb_msix_rx(int irq, void *); | |
110 | static irqreturn_t igb_msix_tx(int irq, void *); | |
421e02f0 | 111 | #ifdef CONFIG_IGB_DCA |
fe4506b6 JC |
112 | static void igb_update_rx_dca(struct igb_ring *); |
113 | static void igb_update_tx_dca(struct igb_ring *); | |
114 | static void igb_setup_dca(struct igb_adapter *); | |
421e02f0 | 115 | #endif /* CONFIG_IGB_DCA */ |
3b644cf6 | 116 | static bool igb_clean_tx_irq(struct igb_ring *); |
661086df | 117 | static int igb_poll(struct napi_struct *, int); |
3b644cf6 MW |
118 | static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int); |
119 | static void igb_alloc_rx_buffers_adv(struct igb_ring *, int); | |
9d5c8243 AK |
120 | static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); |
121 | static void igb_tx_timeout(struct net_device *); | |
122 | static void igb_reset_task(struct work_struct *); | |
123 | static void igb_vlan_rx_register(struct net_device *, struct vlan_group *); | |
124 | static void igb_vlan_rx_add_vid(struct net_device *, u16); | |
125 | static void igb_vlan_rx_kill_vid(struct net_device *, u16); | |
126 | static void igb_restore_vlan(struct igb_adapter *); | |
4ae196df AD |
127 | static void igb_ping_all_vfs(struct igb_adapter *); |
128 | static void igb_msg_task(struct igb_adapter *); | |
129 | static int igb_rcv_msg_from_vf(struct igb_adapter *, u32); | |
e1739522 AD |
130 | static inline void igb_set_rah_pool(struct e1000_hw *, int , int); |
131 | static void igb_set_mc_list_pools(struct igb_adapter *, int, u16); | |
4ae196df | 132 | static void igb_vmm_control(struct igb_adapter *); |
e1739522 | 133 | static inline void igb_set_vmolr(struct e1000_hw *, int); |
4ae196df AD |
134 | static inline int igb_set_vf_rlpml(struct igb_adapter *, int, int); |
135 | static int igb_set_vf_mac(struct igb_adapter *adapter, int, unsigned char *); | |
136 | static void igb_restore_vf_multicasts(struct igb_adapter *adapter); | |
9d5c8243 AK |
137 | |
138 | static int igb_suspend(struct pci_dev *, pm_message_t); | |
139 | #ifdef CONFIG_PM | |
140 | static int igb_resume(struct pci_dev *); | |
141 | #endif | |
142 | static void igb_shutdown(struct pci_dev *); | |
421e02f0 | 143 | #ifdef CONFIG_IGB_DCA |
fe4506b6 JC |
144 | static int igb_notify_dca(struct notifier_block *, unsigned long, void *); |
145 | static struct notifier_block dca_notifier = { | |
146 | .notifier_call = igb_notify_dca, | |
147 | .next = NULL, | |
148 | .priority = 0 | |
149 | }; | |
150 | #endif | |
9d5c8243 AK |
151 | #ifdef CONFIG_NET_POLL_CONTROLLER |
152 | /* for netdump / net console */ | |
153 | static void igb_netpoll(struct net_device *); | |
154 | #endif | |
155 | ||
37680117 AD |
156 | #ifdef CONFIG_PCI_IOV |
157 | static ssize_t igb_set_num_vfs(struct device *, struct device_attribute *, | |
158 | const char *, size_t); | |
159 | static ssize_t igb_show_num_vfs(struct device *, struct device_attribute *, | |
160 | char *); | |
161 | DEVICE_ATTR(num_vfs, S_IRUGO | S_IWUSR, igb_show_num_vfs, igb_set_num_vfs); | |
162 | #endif | |
9d5c8243 AK |
163 | static pci_ers_result_t igb_io_error_detected(struct pci_dev *, |
164 | pci_channel_state_t); | |
165 | static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); | |
166 | static void igb_io_resume(struct pci_dev *); | |
167 | ||
168 | static struct pci_error_handlers igb_err_handler = { | |
169 | .error_detected = igb_io_error_detected, | |
170 | .slot_reset = igb_io_slot_reset, | |
171 | .resume = igb_io_resume, | |
172 | }; | |
173 | ||
174 | ||
175 | static struct pci_driver igb_driver = { | |
176 | .name = igb_driver_name, | |
177 | .id_table = igb_pci_tbl, | |
178 | .probe = igb_probe, | |
179 | .remove = __devexit_p(igb_remove), | |
180 | #ifdef CONFIG_PM | |
181 | /* Power Managment Hooks */ | |
182 | .suspend = igb_suspend, | |
183 | .resume = igb_resume, | |
184 | #endif | |
185 | .shutdown = igb_shutdown, | |
186 | .err_handler = &igb_err_handler | |
187 | }; | |
188 | ||
7dfc16fa AD |
189 | static int global_quad_port_a; /* global quad port a indication */ |
190 | ||
9d5c8243 AK |
191 | MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); |
192 | MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); | |
193 | MODULE_LICENSE("GPL"); | |
194 | MODULE_VERSION(DRV_VERSION); | |
195 | ||
38c845c7 PO |
196 | /** |
197 | * Scale the NIC clock cycle by a large factor so that | |
198 | * relatively small clock corrections can be added or | |
199 | * substracted at each clock tick. The drawbacks of a | |
200 | * large factor are a) that the clock register overflows | |
201 | * more quickly (not such a big deal) and b) that the | |
202 | * increment per tick has to fit into 24 bits. | |
203 | * | |
204 | * Note that | |
205 | * TIMINCA = IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS * | |
206 | * IGB_TSYNC_SCALE | |
207 | * TIMINCA += TIMINCA * adjustment [ppm] / 1e9 | |
208 | * | |
209 | * The base scale factor is intentionally a power of two | |
210 | * so that the division in %struct timecounter can be done with | |
211 | * a shift. | |
212 | */ | |
213 | #define IGB_TSYNC_SHIFT (19) | |
214 | #define IGB_TSYNC_SCALE (1<<IGB_TSYNC_SHIFT) | |
215 | ||
216 | /** | |
217 | * The duration of one clock cycle of the NIC. | |
218 | * | |
219 | * @todo This hard-coded value is part of the specification and might change | |
220 | * in future hardware revisions. Add revision check. | |
221 | */ | |
222 | #define IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS 16 | |
223 | ||
224 | #if (IGB_TSYNC_SCALE * IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS) >= (1<<24) | |
225 | # error IGB_TSYNC_SCALE and/or IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS are too large to fit into TIMINCA | |
226 | #endif | |
227 | ||
228 | /** | |
229 | * igb_read_clock - read raw cycle counter (to be used by time counter) | |
230 | */ | |
231 | static cycle_t igb_read_clock(const struct cyclecounter *tc) | |
232 | { | |
233 | struct igb_adapter *adapter = | |
234 | container_of(tc, struct igb_adapter, cycles); | |
235 | struct e1000_hw *hw = &adapter->hw; | |
236 | u64 stamp; | |
237 | ||
238 | stamp = rd32(E1000_SYSTIML); | |
239 | stamp |= (u64)rd32(E1000_SYSTIMH) << 32ULL; | |
240 | ||
241 | return stamp; | |
242 | } | |
243 | ||
9d5c8243 AK |
244 | #ifdef DEBUG |
245 | /** | |
246 | * igb_get_hw_dev_name - return device name string | |
247 | * used by hardware layer to print debugging information | |
248 | **/ | |
249 | char *igb_get_hw_dev_name(struct e1000_hw *hw) | |
250 | { | |
251 | struct igb_adapter *adapter = hw->back; | |
252 | return adapter->netdev->name; | |
253 | } | |
38c845c7 PO |
254 | |
255 | /** | |
256 | * igb_get_time_str - format current NIC and system time as string | |
257 | */ | |
258 | static char *igb_get_time_str(struct igb_adapter *adapter, | |
259 | char buffer[160]) | |
260 | { | |
261 | cycle_t hw = adapter->cycles.read(&adapter->cycles); | |
262 | struct timespec nic = ns_to_timespec(timecounter_read(&adapter->clock)); | |
263 | struct timespec sys; | |
264 | struct timespec delta; | |
265 | getnstimeofday(&sys); | |
266 | ||
267 | delta = timespec_sub(nic, sys); | |
268 | ||
269 | sprintf(buffer, | |
33af6bcc PO |
270 | "HW %llu, NIC %ld.%09lus, SYS %ld.%09lus, NIC-SYS %lds + %09luns", |
271 | hw, | |
38c845c7 PO |
272 | (long)nic.tv_sec, nic.tv_nsec, |
273 | (long)sys.tv_sec, sys.tv_nsec, | |
274 | (long)delta.tv_sec, delta.tv_nsec); | |
275 | ||
276 | return buffer; | |
277 | } | |
9d5c8243 AK |
278 | #endif |
279 | ||
c493ea45 AD |
280 | /** |
281 | * igb_desc_unused - calculate if we have unused descriptors | |
282 | **/ | |
283 | static int igb_desc_unused(struct igb_ring *ring) | |
284 | { | |
285 | if (ring->next_to_clean > ring->next_to_use) | |
286 | return ring->next_to_clean - ring->next_to_use - 1; | |
287 | ||
288 | return ring->count + ring->next_to_clean - ring->next_to_use - 1; | |
289 | } | |
290 | ||
9d5c8243 AK |
291 | /** |
292 | * igb_init_module - Driver Registration Routine | |
293 | * | |
294 | * igb_init_module is the first routine called when the driver is | |
295 | * loaded. All it does is register with the PCI subsystem. | |
296 | **/ | |
297 | static int __init igb_init_module(void) | |
298 | { | |
299 | int ret; | |
300 | printk(KERN_INFO "%s - version %s\n", | |
301 | igb_driver_string, igb_driver_version); | |
302 | ||
303 | printk(KERN_INFO "%s\n", igb_copyright); | |
304 | ||
7dfc16fa AD |
305 | global_quad_port_a = 0; |
306 | ||
421e02f0 | 307 | #ifdef CONFIG_IGB_DCA |
fe4506b6 JC |
308 | dca_register_notify(&dca_notifier); |
309 | #endif | |
bbd98fe4 AD |
310 | |
311 | ret = pci_register_driver(&igb_driver); | |
9d5c8243 AK |
312 | return ret; |
313 | } | |
314 | ||
315 | module_init(igb_init_module); | |
316 | ||
317 | /** | |
318 | * igb_exit_module - Driver Exit Cleanup Routine | |
319 | * | |
320 | * igb_exit_module is called just before the driver is removed | |
321 | * from memory. | |
322 | **/ | |
323 | static void __exit igb_exit_module(void) | |
324 | { | |
421e02f0 | 325 | #ifdef CONFIG_IGB_DCA |
fe4506b6 JC |
326 | dca_unregister_notify(&dca_notifier); |
327 | #endif | |
9d5c8243 AK |
328 | pci_unregister_driver(&igb_driver); |
329 | } | |
330 | ||
331 | module_exit(igb_exit_module); | |
332 | ||
26bc19ec AD |
333 | #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) |
334 | /** | |
335 | * igb_cache_ring_register - Descriptor ring to register mapping | |
336 | * @adapter: board private structure to initialize | |
337 | * | |
338 | * Once we know the feature-set enabled for the device, we'll cache | |
339 | * the register offset the descriptor ring is assigned to. | |
340 | **/ | |
341 | static void igb_cache_ring_register(struct igb_adapter *adapter) | |
342 | { | |
343 | int i; | |
1bfaf07b | 344 | unsigned int rbase_offset = adapter->vfs_allocated_count; |
26bc19ec AD |
345 | |
346 | switch (adapter->hw.mac.type) { | |
347 | case e1000_82576: | |
348 | /* The queues are allocated for virtualization such that VF 0 | |
349 | * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. | |
350 | * In order to avoid collision we start at the first free queue | |
351 | * and continue consuming queues in the same sequence | |
352 | */ | |
353 | for (i = 0; i < adapter->num_rx_queues; i++) | |
1bfaf07b AD |
354 | adapter->rx_ring[i].reg_idx = rbase_offset + |
355 | Q_IDX_82576(i); | |
26bc19ec | 356 | for (i = 0; i < adapter->num_tx_queues; i++) |
1bfaf07b AD |
357 | adapter->tx_ring[i].reg_idx = rbase_offset + |
358 | Q_IDX_82576(i); | |
26bc19ec AD |
359 | break; |
360 | case e1000_82575: | |
361 | default: | |
362 | for (i = 0; i < adapter->num_rx_queues; i++) | |
363 | adapter->rx_ring[i].reg_idx = i; | |
364 | for (i = 0; i < adapter->num_tx_queues; i++) | |
365 | adapter->tx_ring[i].reg_idx = i; | |
366 | break; | |
367 | } | |
368 | } | |
369 | ||
9d5c8243 AK |
370 | /** |
371 | * igb_alloc_queues - Allocate memory for all rings | |
372 | * @adapter: board private structure to initialize | |
373 | * | |
374 | * We allocate one ring per queue at run-time since we don't know the | |
375 | * number of queues at compile-time. | |
376 | **/ | |
377 | static int igb_alloc_queues(struct igb_adapter *adapter) | |
378 | { | |
379 | int i; | |
380 | ||
381 | adapter->tx_ring = kcalloc(adapter->num_tx_queues, | |
382 | sizeof(struct igb_ring), GFP_KERNEL); | |
383 | if (!adapter->tx_ring) | |
384 | return -ENOMEM; | |
385 | ||
386 | adapter->rx_ring = kcalloc(adapter->num_rx_queues, | |
387 | sizeof(struct igb_ring), GFP_KERNEL); | |
388 | if (!adapter->rx_ring) { | |
389 | kfree(adapter->tx_ring); | |
390 | return -ENOMEM; | |
391 | } | |
392 | ||
6eb5a7f1 AD |
393 | adapter->rx_ring->buddy = adapter->tx_ring; |
394 | ||
661086df PWJ |
395 | for (i = 0; i < adapter->num_tx_queues; i++) { |
396 | struct igb_ring *ring = &(adapter->tx_ring[i]); | |
68fd9910 | 397 | ring->count = adapter->tx_ring_count; |
661086df PWJ |
398 | ring->adapter = adapter; |
399 | ring->queue_index = i; | |
400 | } | |
9d5c8243 AK |
401 | for (i = 0; i < adapter->num_rx_queues; i++) { |
402 | struct igb_ring *ring = &(adapter->rx_ring[i]); | |
68fd9910 | 403 | ring->count = adapter->rx_ring_count; |
9d5c8243 | 404 | ring->adapter = adapter; |
844290e5 | 405 | ring->queue_index = i; |
9d5c8243 AK |
406 | ring->itr_register = E1000_ITR; |
407 | ||
844290e5 | 408 | /* set a default napi handler for each rx_ring */ |
661086df | 409 | netif_napi_add(adapter->netdev, &ring->napi, igb_poll, 64); |
9d5c8243 | 410 | } |
26bc19ec AD |
411 | |
412 | igb_cache_ring_register(adapter); | |
9d5c8243 AK |
413 | return 0; |
414 | } | |
415 | ||
a88f10ec AD |
416 | static void igb_free_queues(struct igb_adapter *adapter) |
417 | { | |
418 | int i; | |
419 | ||
420 | for (i = 0; i < adapter->num_rx_queues; i++) | |
421 | netif_napi_del(&adapter->rx_ring[i].napi); | |
422 | ||
423 | kfree(adapter->tx_ring); | |
424 | kfree(adapter->rx_ring); | |
425 | } | |
426 | ||
9d5c8243 AK |
427 | #define IGB_N0_QUEUE -1 |
428 | static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue, | |
429 | int tx_queue, int msix_vector) | |
430 | { | |
431 | u32 msixbm = 0; | |
432 | struct e1000_hw *hw = &adapter->hw; | |
2d064c06 AD |
433 | u32 ivar, index; |
434 | ||
435 | switch (hw->mac.type) { | |
436 | case e1000_82575: | |
9d5c8243 AK |
437 | /* The 82575 assigns vectors using a bitmask, which matches the |
438 | bitmask for the EICR/EIMS/EIMC registers. To assign one | |
439 | or more queues to a vector, we write the appropriate bits | |
440 | into the MSIXBM register for that vector. */ | |
441 | if (rx_queue > IGB_N0_QUEUE) { | |
442 | msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; | |
443 | adapter->rx_ring[rx_queue].eims_value = msixbm; | |
444 | } | |
445 | if (tx_queue > IGB_N0_QUEUE) { | |
446 | msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; | |
447 | adapter->tx_ring[tx_queue].eims_value = | |
448 | E1000_EICR_TX_QUEUE0 << tx_queue; | |
449 | } | |
450 | array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); | |
2d064c06 AD |
451 | break; |
452 | case e1000_82576: | |
26bc19ec | 453 | /* 82576 uses a table-based method for assigning vectors. |
2d064c06 AD |
454 | Each queue has a single entry in the table to which we write |
455 | a vector number along with a "valid" bit. Sadly, the layout | |
456 | of the table is somewhat counterintuitive. */ | |
457 | if (rx_queue > IGB_N0_QUEUE) { | |
1bfaf07b | 458 | index = (rx_queue >> 1) + adapter->vfs_allocated_count; |
2d064c06 | 459 | ivar = array_rd32(E1000_IVAR0, index); |
26bc19ec | 460 | if (rx_queue & 0x1) { |
2d064c06 AD |
461 | /* vector goes into third byte of register */ |
462 | ivar = ivar & 0xFF00FFFF; | |
463 | ivar |= (msix_vector | E1000_IVAR_VALID) << 16; | |
26bc19ec AD |
464 | } else { |
465 | /* vector goes into low byte of register */ | |
466 | ivar = ivar & 0xFFFFFF00; | |
467 | ivar |= msix_vector | E1000_IVAR_VALID; | |
2d064c06 AD |
468 | } |
469 | adapter->rx_ring[rx_queue].eims_value= 1 << msix_vector; | |
470 | array_wr32(E1000_IVAR0, index, ivar); | |
471 | } | |
472 | if (tx_queue > IGB_N0_QUEUE) { | |
1bfaf07b | 473 | index = (tx_queue >> 1) + adapter->vfs_allocated_count; |
2d064c06 | 474 | ivar = array_rd32(E1000_IVAR0, index); |
26bc19ec | 475 | if (tx_queue & 0x1) { |
2d064c06 AD |
476 | /* vector goes into high byte of register */ |
477 | ivar = ivar & 0x00FFFFFF; | |
478 | ivar |= (msix_vector | E1000_IVAR_VALID) << 24; | |
26bc19ec AD |
479 | } else { |
480 | /* vector goes into second byte of register */ | |
481 | ivar = ivar & 0xFFFF00FF; | |
482 | ivar |= (msix_vector | E1000_IVAR_VALID) << 8; | |
2d064c06 AD |
483 | } |
484 | adapter->tx_ring[tx_queue].eims_value= 1 << msix_vector; | |
485 | array_wr32(E1000_IVAR0, index, ivar); | |
486 | } | |
487 | break; | |
488 | default: | |
489 | BUG(); | |
490 | break; | |
491 | } | |
9d5c8243 AK |
492 | } |
493 | ||
494 | /** | |
495 | * igb_configure_msix - Configure MSI-X hardware | |
496 | * | |
497 | * igb_configure_msix sets up the hardware to properly | |
498 | * generate MSI-X interrupts. | |
499 | **/ | |
500 | static void igb_configure_msix(struct igb_adapter *adapter) | |
501 | { | |
502 | u32 tmp; | |
503 | int i, vector = 0; | |
504 | struct e1000_hw *hw = &adapter->hw; | |
505 | ||
506 | adapter->eims_enable_mask = 0; | |
2d064c06 AD |
507 | if (hw->mac.type == e1000_82576) |
508 | /* Turn on MSI-X capability first, or our settings | |
509 | * won't stick. And it will take days to debug. */ | |
510 | wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | | |
eebbbdba | 511 | E1000_GPIE_PBA | E1000_GPIE_EIAME | |
2d064c06 | 512 | E1000_GPIE_NSICR); |
9d5c8243 AK |
513 | |
514 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
515 | struct igb_ring *tx_ring = &adapter->tx_ring[i]; | |
516 | igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++); | |
517 | adapter->eims_enable_mask |= tx_ring->eims_value; | |
518 | if (tx_ring->itr_val) | |
6eb5a7f1 | 519 | writel(tx_ring->itr_val, |
9d5c8243 AK |
520 | hw->hw_addr + tx_ring->itr_register); |
521 | else | |
522 | writel(1, hw->hw_addr + tx_ring->itr_register); | |
523 | } | |
524 | ||
525 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
526 | struct igb_ring *rx_ring = &adapter->rx_ring[i]; | |
25ac3c24 | 527 | rx_ring->buddy = NULL; |
9d5c8243 AK |
528 | igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++); |
529 | adapter->eims_enable_mask |= rx_ring->eims_value; | |
530 | if (rx_ring->itr_val) | |
6eb5a7f1 | 531 | writel(rx_ring->itr_val, |
9d5c8243 AK |
532 | hw->hw_addr + rx_ring->itr_register); |
533 | else | |
534 | writel(1, hw->hw_addr + rx_ring->itr_register); | |
535 | } | |
536 | ||
537 | ||
538 | /* set vector for other causes, i.e. link changes */ | |
2d064c06 AD |
539 | switch (hw->mac.type) { |
540 | case e1000_82575: | |
9d5c8243 AK |
541 | array_wr32(E1000_MSIXBM(0), vector++, |
542 | E1000_EIMS_OTHER); | |
543 | ||
9d5c8243 AK |
544 | tmp = rd32(E1000_CTRL_EXT); |
545 | /* enable MSI-X PBA support*/ | |
546 | tmp |= E1000_CTRL_EXT_PBA_CLR; | |
547 | ||
548 | /* Auto-Mask interrupts upon ICR read. */ | |
549 | tmp |= E1000_CTRL_EXT_EIAME; | |
550 | tmp |= E1000_CTRL_EXT_IRCA; | |
551 | ||
552 | wr32(E1000_CTRL_EXT, tmp); | |
553 | adapter->eims_enable_mask |= E1000_EIMS_OTHER; | |
844290e5 | 554 | adapter->eims_other = E1000_EIMS_OTHER; |
9d5c8243 | 555 | |
2d064c06 AD |
556 | break; |
557 | ||
558 | case e1000_82576: | |
559 | tmp = (vector++ | E1000_IVAR_VALID) << 8; | |
560 | wr32(E1000_IVAR_MISC, tmp); | |
561 | ||
562 | adapter->eims_enable_mask = (1 << (vector)) - 1; | |
563 | adapter->eims_other = 1 << (vector - 1); | |
564 | break; | |
565 | default: | |
566 | /* do nothing, since nothing else supports MSI-X */ | |
567 | break; | |
568 | } /* switch (hw->mac.type) */ | |
9d5c8243 AK |
569 | wrfl(); |
570 | } | |
571 | ||
572 | /** | |
573 | * igb_request_msix - Initialize MSI-X interrupts | |
574 | * | |
575 | * igb_request_msix allocates MSI-X vectors and requests interrupts from the | |
576 | * kernel. | |
577 | **/ | |
578 | static int igb_request_msix(struct igb_adapter *adapter) | |
579 | { | |
580 | struct net_device *netdev = adapter->netdev; | |
581 | int i, err = 0, vector = 0; | |
582 | ||
583 | vector = 0; | |
584 | ||
585 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
586 | struct igb_ring *ring = &(adapter->tx_ring[i]); | |
cb7b48f6 | 587 | sprintf(ring->name, "%s-tx-%d", netdev->name, i); |
9d5c8243 AK |
588 | err = request_irq(adapter->msix_entries[vector].vector, |
589 | &igb_msix_tx, 0, ring->name, | |
590 | &(adapter->tx_ring[i])); | |
591 | if (err) | |
592 | goto out; | |
593 | ring->itr_register = E1000_EITR(0) + (vector << 2); | |
6eb5a7f1 | 594 | ring->itr_val = 976; /* ~4000 ints/sec */ |
9d5c8243 AK |
595 | vector++; |
596 | } | |
597 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
598 | struct igb_ring *ring = &(adapter->rx_ring[i]); | |
599 | if (strlen(netdev->name) < (IFNAMSIZ - 5)) | |
cb7b48f6 | 600 | sprintf(ring->name, "%s-rx-%d", netdev->name, i); |
9d5c8243 AK |
601 | else |
602 | memcpy(ring->name, netdev->name, IFNAMSIZ); | |
603 | err = request_irq(adapter->msix_entries[vector].vector, | |
604 | &igb_msix_rx, 0, ring->name, | |
605 | &(adapter->rx_ring[i])); | |
606 | if (err) | |
607 | goto out; | |
608 | ring->itr_register = E1000_EITR(0) + (vector << 2); | |
609 | ring->itr_val = adapter->itr; | |
610 | vector++; | |
611 | } | |
612 | ||
613 | err = request_irq(adapter->msix_entries[vector].vector, | |
614 | &igb_msix_other, 0, netdev->name, netdev); | |
615 | if (err) | |
616 | goto out; | |
617 | ||
9d5c8243 AK |
618 | igb_configure_msix(adapter); |
619 | return 0; | |
620 | out: | |
621 | return err; | |
622 | } | |
623 | ||
624 | static void igb_reset_interrupt_capability(struct igb_adapter *adapter) | |
625 | { | |
626 | if (adapter->msix_entries) { | |
627 | pci_disable_msix(adapter->pdev); | |
628 | kfree(adapter->msix_entries); | |
629 | adapter->msix_entries = NULL; | |
7dfc16fa | 630 | } else if (adapter->flags & IGB_FLAG_HAS_MSI) |
9d5c8243 AK |
631 | pci_disable_msi(adapter->pdev); |
632 | return; | |
633 | } | |
634 | ||
635 | ||
636 | /** | |
637 | * igb_set_interrupt_capability - set MSI or MSI-X if supported | |
638 | * | |
639 | * Attempt to configure interrupts using the best available | |
640 | * capabilities of the hardware and kernel. | |
641 | **/ | |
642 | static void igb_set_interrupt_capability(struct igb_adapter *adapter) | |
643 | { | |
644 | int err; | |
645 | int numvecs, i; | |
646 | ||
83b7180d AD |
647 | /* Number of supported queues. */ |
648 | /* Having more queues than CPUs doesn't make sense. */ | |
649 | adapter->num_rx_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus()); | |
650 | adapter->num_tx_queues = min_t(u32, IGB_MAX_TX_QUEUES, num_online_cpus()); | |
651 | ||
9d5c8243 AK |
652 | numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1; |
653 | adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry), | |
654 | GFP_KERNEL); | |
655 | if (!adapter->msix_entries) | |
656 | goto msi_only; | |
657 | ||
658 | for (i = 0; i < numvecs; i++) | |
659 | adapter->msix_entries[i].entry = i; | |
660 | ||
661 | err = pci_enable_msix(adapter->pdev, | |
662 | adapter->msix_entries, | |
663 | numvecs); | |
664 | if (err == 0) | |
34a20e89 | 665 | goto out; |
9d5c8243 AK |
666 | |
667 | igb_reset_interrupt_capability(adapter); | |
668 | ||
669 | /* If we can't do MSI-X, try MSI */ | |
670 | msi_only: | |
671 | adapter->num_rx_queues = 1; | |
661086df | 672 | adapter->num_tx_queues = 1; |
9d5c8243 | 673 | if (!pci_enable_msi(adapter->pdev)) |
7dfc16fa | 674 | adapter->flags |= IGB_FLAG_HAS_MSI; |
34a20e89 | 675 | out: |
661086df | 676 | /* Notify the stack of the (possibly) reduced Tx Queue count. */ |
fd2ea0a7 | 677 | adapter->netdev->real_num_tx_queues = adapter->num_tx_queues; |
9d5c8243 AK |
678 | return; |
679 | } | |
680 | ||
681 | /** | |
682 | * igb_request_irq - initialize interrupts | |
683 | * | |
684 | * Attempts to configure interrupts using the best available | |
685 | * capabilities of the hardware and kernel. | |
686 | **/ | |
687 | static int igb_request_irq(struct igb_adapter *adapter) | |
688 | { | |
689 | struct net_device *netdev = adapter->netdev; | |
690 | struct e1000_hw *hw = &adapter->hw; | |
691 | int err = 0; | |
692 | ||
693 | if (adapter->msix_entries) { | |
694 | err = igb_request_msix(adapter); | |
844290e5 | 695 | if (!err) |
9d5c8243 | 696 | goto request_done; |
9d5c8243 AK |
697 | /* fall back to MSI */ |
698 | igb_reset_interrupt_capability(adapter); | |
699 | if (!pci_enable_msi(adapter->pdev)) | |
7dfc16fa | 700 | adapter->flags |= IGB_FLAG_HAS_MSI; |
9d5c8243 AK |
701 | igb_free_all_tx_resources(adapter); |
702 | igb_free_all_rx_resources(adapter); | |
703 | adapter->num_rx_queues = 1; | |
704 | igb_alloc_queues(adapter); | |
844290e5 | 705 | } else { |
2d064c06 AD |
706 | switch (hw->mac.type) { |
707 | case e1000_82575: | |
708 | wr32(E1000_MSIXBM(0), | |
709 | (E1000_EICR_RX_QUEUE0 | E1000_EIMS_OTHER)); | |
710 | break; | |
711 | case e1000_82576: | |
712 | wr32(E1000_IVAR0, E1000_IVAR_VALID); | |
713 | break; | |
714 | default: | |
715 | break; | |
716 | } | |
9d5c8243 | 717 | } |
844290e5 | 718 | |
7dfc16fa | 719 | if (adapter->flags & IGB_FLAG_HAS_MSI) { |
9d5c8243 AK |
720 | err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0, |
721 | netdev->name, netdev); | |
722 | if (!err) | |
723 | goto request_done; | |
724 | /* fall back to legacy interrupts */ | |
725 | igb_reset_interrupt_capability(adapter); | |
7dfc16fa | 726 | adapter->flags &= ~IGB_FLAG_HAS_MSI; |
9d5c8243 AK |
727 | } |
728 | ||
729 | err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED, | |
730 | netdev->name, netdev); | |
731 | ||
6cb5e577 | 732 | if (err) |
9d5c8243 AK |
733 | dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n", |
734 | err); | |
9d5c8243 AK |
735 | |
736 | request_done: | |
737 | return err; | |
738 | } | |
739 | ||
740 | static void igb_free_irq(struct igb_adapter *adapter) | |
741 | { | |
742 | struct net_device *netdev = adapter->netdev; | |
743 | ||
744 | if (adapter->msix_entries) { | |
745 | int vector = 0, i; | |
746 | ||
747 | for (i = 0; i < adapter->num_tx_queues; i++) | |
748 | free_irq(adapter->msix_entries[vector++].vector, | |
749 | &(adapter->tx_ring[i])); | |
750 | for (i = 0; i < adapter->num_rx_queues; i++) | |
751 | free_irq(adapter->msix_entries[vector++].vector, | |
752 | &(adapter->rx_ring[i])); | |
753 | ||
754 | free_irq(adapter->msix_entries[vector++].vector, netdev); | |
755 | return; | |
756 | } | |
757 | ||
758 | free_irq(adapter->pdev->irq, netdev); | |
759 | } | |
760 | ||
761 | /** | |
762 | * igb_irq_disable - Mask off interrupt generation on the NIC | |
763 | * @adapter: board private structure | |
764 | **/ | |
765 | static void igb_irq_disable(struct igb_adapter *adapter) | |
766 | { | |
767 | struct e1000_hw *hw = &adapter->hw; | |
768 | ||
769 | if (adapter->msix_entries) { | |
844290e5 | 770 | wr32(E1000_EIAM, 0); |
9d5c8243 AK |
771 | wr32(E1000_EIMC, ~0); |
772 | wr32(E1000_EIAC, 0); | |
773 | } | |
844290e5 PW |
774 | |
775 | wr32(E1000_IAM, 0); | |
9d5c8243 AK |
776 | wr32(E1000_IMC, ~0); |
777 | wrfl(); | |
778 | synchronize_irq(adapter->pdev->irq); | |
779 | } | |
780 | ||
781 | /** | |
782 | * igb_irq_enable - Enable default interrupt generation settings | |
783 | * @adapter: board private structure | |
784 | **/ | |
785 | static void igb_irq_enable(struct igb_adapter *adapter) | |
786 | { | |
787 | struct e1000_hw *hw = &adapter->hw; | |
788 | ||
789 | if (adapter->msix_entries) { | |
844290e5 PW |
790 | wr32(E1000_EIAC, adapter->eims_enable_mask); |
791 | wr32(E1000_EIAM, adapter->eims_enable_mask); | |
792 | wr32(E1000_EIMS, adapter->eims_enable_mask); | |
4ae196df AD |
793 | if (adapter->vfs_allocated_count) |
794 | wr32(E1000_MBVFIMR, 0xFF); | |
795 | wr32(E1000_IMS, (E1000_IMS_LSC | E1000_IMS_VMMB | | |
796 | E1000_IMS_DOUTSYNC)); | |
844290e5 PW |
797 | } else { |
798 | wr32(E1000_IMS, IMS_ENABLE_MASK); | |
799 | wr32(E1000_IAM, IMS_ENABLE_MASK); | |
800 | } | |
9d5c8243 AK |
801 | } |
802 | ||
803 | static void igb_update_mng_vlan(struct igb_adapter *adapter) | |
804 | { | |
805 | struct net_device *netdev = adapter->netdev; | |
806 | u16 vid = adapter->hw.mng_cookie.vlan_id; | |
807 | u16 old_vid = adapter->mng_vlan_id; | |
808 | if (adapter->vlgrp) { | |
809 | if (!vlan_group_get_device(adapter->vlgrp, vid)) { | |
810 | if (adapter->hw.mng_cookie.status & | |
811 | E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { | |
812 | igb_vlan_rx_add_vid(netdev, vid); | |
813 | adapter->mng_vlan_id = vid; | |
814 | } else | |
815 | adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; | |
816 | ||
817 | if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && | |
818 | (vid != old_vid) && | |
819 | !vlan_group_get_device(adapter->vlgrp, old_vid)) | |
820 | igb_vlan_rx_kill_vid(netdev, old_vid); | |
821 | } else | |
822 | adapter->mng_vlan_id = vid; | |
823 | } | |
824 | } | |
825 | ||
826 | /** | |
827 | * igb_release_hw_control - release control of the h/w to f/w | |
828 | * @adapter: address of board private structure | |
829 | * | |
830 | * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. | |
831 | * For ASF and Pass Through versions of f/w this means that the | |
832 | * driver is no longer loaded. | |
833 | * | |
834 | **/ | |
835 | static void igb_release_hw_control(struct igb_adapter *adapter) | |
836 | { | |
837 | struct e1000_hw *hw = &adapter->hw; | |
838 | u32 ctrl_ext; | |
839 | ||
840 | /* Let firmware take over control of h/w */ | |
841 | ctrl_ext = rd32(E1000_CTRL_EXT); | |
842 | wr32(E1000_CTRL_EXT, | |
843 | ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); | |
844 | } | |
845 | ||
846 | ||
847 | /** | |
848 | * igb_get_hw_control - get control of the h/w from f/w | |
849 | * @adapter: address of board private structure | |
850 | * | |
851 | * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. | |
852 | * For ASF and Pass Through versions of f/w this means that | |
853 | * the driver is loaded. | |
854 | * | |
855 | **/ | |
856 | static void igb_get_hw_control(struct igb_adapter *adapter) | |
857 | { | |
858 | struct e1000_hw *hw = &adapter->hw; | |
859 | u32 ctrl_ext; | |
860 | ||
861 | /* Let firmware know the driver has taken over */ | |
862 | ctrl_ext = rd32(E1000_CTRL_EXT); | |
863 | wr32(E1000_CTRL_EXT, | |
864 | ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); | |
865 | } | |
866 | ||
9d5c8243 AK |
867 | /** |
868 | * igb_configure - configure the hardware for RX and TX | |
869 | * @adapter: private board structure | |
870 | **/ | |
871 | static void igb_configure(struct igb_adapter *adapter) | |
872 | { | |
873 | struct net_device *netdev = adapter->netdev; | |
874 | int i; | |
875 | ||
876 | igb_get_hw_control(adapter); | |
877 | igb_set_multi(netdev); | |
878 | ||
879 | igb_restore_vlan(adapter); | |
9d5c8243 AK |
880 | |
881 | igb_configure_tx(adapter); | |
882 | igb_setup_rctl(adapter); | |
883 | igb_configure_rx(adapter); | |
662d7205 AD |
884 | |
885 | igb_rx_fifo_flush_82575(&adapter->hw); | |
886 | ||
c493ea45 | 887 | /* call igb_desc_unused which always leaves |
9d5c8243 AK |
888 | * at least 1 descriptor unused to make sure |
889 | * next_to_use != next_to_clean */ | |
890 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
891 | struct igb_ring *ring = &adapter->rx_ring[i]; | |
c493ea45 | 892 | igb_alloc_rx_buffers_adv(ring, igb_desc_unused(ring)); |
9d5c8243 AK |
893 | } |
894 | ||
895 | ||
896 | adapter->tx_queue_len = netdev->tx_queue_len; | |
897 | } | |
898 | ||
899 | ||
900 | /** | |
901 | * igb_up - Open the interface and prepare it to handle traffic | |
902 | * @adapter: board private structure | |
903 | **/ | |
904 | ||
905 | int igb_up(struct igb_adapter *adapter) | |
906 | { | |
907 | struct e1000_hw *hw = &adapter->hw; | |
908 | int i; | |
909 | ||
910 | /* hardware has been reset, we need to reload some things */ | |
911 | igb_configure(adapter); | |
912 | ||
913 | clear_bit(__IGB_DOWN, &adapter->state); | |
914 | ||
844290e5 PW |
915 | for (i = 0; i < adapter->num_rx_queues; i++) |
916 | napi_enable(&adapter->rx_ring[i].napi); | |
917 | if (adapter->msix_entries) | |
9d5c8243 | 918 | igb_configure_msix(adapter); |
9d5c8243 | 919 | |
4ae196df | 920 | igb_vmm_control(adapter); |
e1739522 AD |
921 | igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0); |
922 | igb_set_vmolr(hw, adapter->vfs_allocated_count); | |
923 | ||
9d5c8243 AK |
924 | /* Clear any pending interrupts. */ |
925 | rd32(E1000_ICR); | |
926 | igb_irq_enable(adapter); | |
927 | ||
928 | /* Fire a link change interrupt to start the watchdog. */ | |
929 | wr32(E1000_ICS, E1000_ICS_LSC); | |
930 | return 0; | |
931 | } | |
932 | ||
933 | void igb_down(struct igb_adapter *adapter) | |
934 | { | |
935 | struct e1000_hw *hw = &adapter->hw; | |
936 | struct net_device *netdev = adapter->netdev; | |
937 | u32 tctl, rctl; | |
938 | int i; | |
939 | ||
940 | /* signal that we're down so the interrupt handler does not | |
941 | * reschedule our watchdog timer */ | |
942 | set_bit(__IGB_DOWN, &adapter->state); | |
943 | ||
944 | /* disable receives in the hardware */ | |
945 | rctl = rd32(E1000_RCTL); | |
946 | wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); | |
947 | /* flush and sleep below */ | |
948 | ||
fd2ea0a7 | 949 | netif_tx_stop_all_queues(netdev); |
9d5c8243 AK |
950 | |
951 | /* disable transmits in the hardware */ | |
952 | tctl = rd32(E1000_TCTL); | |
953 | tctl &= ~E1000_TCTL_EN; | |
954 | wr32(E1000_TCTL, tctl); | |
955 | /* flush both disables and wait for them to finish */ | |
956 | wrfl(); | |
957 | msleep(10); | |
958 | ||
844290e5 PW |
959 | for (i = 0; i < adapter->num_rx_queues; i++) |
960 | napi_disable(&adapter->rx_ring[i].napi); | |
9d5c8243 | 961 | |
9d5c8243 AK |
962 | igb_irq_disable(adapter); |
963 | ||
964 | del_timer_sync(&adapter->watchdog_timer); | |
965 | del_timer_sync(&adapter->phy_info_timer); | |
966 | ||
967 | netdev->tx_queue_len = adapter->tx_queue_len; | |
968 | netif_carrier_off(netdev); | |
04fe6358 AD |
969 | |
970 | /* record the stats before reset*/ | |
971 | igb_update_stats(adapter); | |
972 | ||
9d5c8243 AK |
973 | adapter->link_speed = 0; |
974 | adapter->link_duplex = 0; | |
975 | ||
3023682e JK |
976 | if (!pci_channel_offline(adapter->pdev)) |
977 | igb_reset(adapter); | |
9d5c8243 AK |
978 | igb_clean_all_tx_rings(adapter); |
979 | igb_clean_all_rx_rings(adapter); | |
980 | } | |
981 | ||
982 | void igb_reinit_locked(struct igb_adapter *adapter) | |
983 | { | |
984 | WARN_ON(in_interrupt()); | |
985 | while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) | |
986 | msleep(1); | |
987 | igb_down(adapter); | |
988 | igb_up(adapter); | |
989 | clear_bit(__IGB_RESETTING, &adapter->state); | |
990 | } | |
991 | ||
992 | void igb_reset(struct igb_adapter *adapter) | |
993 | { | |
994 | struct e1000_hw *hw = &adapter->hw; | |
2d064c06 AD |
995 | struct e1000_mac_info *mac = &hw->mac; |
996 | struct e1000_fc_info *fc = &hw->fc; | |
9d5c8243 AK |
997 | u32 pba = 0, tx_space, min_tx_space, min_rx_space; |
998 | u16 hwm; | |
999 | ||
1000 | /* Repartition Pba for greater than 9k mtu | |
1001 | * To take effect CTRL.RST is required. | |
1002 | */ | |
fa4dfae0 AD |
1003 | switch (mac->type) { |
1004 | case e1000_82576: | |
2d064c06 | 1005 | pba = E1000_PBA_64K; |
fa4dfae0 AD |
1006 | break; |
1007 | case e1000_82575: | |
1008 | default: | |
1009 | pba = E1000_PBA_34K; | |
1010 | break; | |
2d064c06 | 1011 | } |
9d5c8243 | 1012 | |
2d064c06 AD |
1013 | if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) && |
1014 | (mac->type < e1000_82576)) { | |
9d5c8243 AK |
1015 | /* adjust PBA for jumbo frames */ |
1016 | wr32(E1000_PBA, pba); | |
1017 | ||
1018 | /* To maintain wire speed transmits, the Tx FIFO should be | |
1019 | * large enough to accommodate two full transmit packets, | |
1020 | * rounded up to the next 1KB and expressed in KB. Likewise, | |
1021 | * the Rx FIFO should be large enough to accommodate at least | |
1022 | * one full receive packet and is similarly rounded up and | |
1023 | * expressed in KB. */ | |
1024 | pba = rd32(E1000_PBA); | |
1025 | /* upper 16 bits has Tx packet buffer allocation size in KB */ | |
1026 | tx_space = pba >> 16; | |
1027 | /* lower 16 bits has Rx packet buffer allocation size in KB */ | |
1028 | pba &= 0xffff; | |
1029 | /* the tx fifo also stores 16 bytes of information about the tx | |
1030 | * but don't include ethernet FCS because hardware appends it */ | |
1031 | min_tx_space = (adapter->max_frame_size + | |
85e8d004 | 1032 | sizeof(union e1000_adv_tx_desc) - |
9d5c8243 AK |
1033 | ETH_FCS_LEN) * 2; |
1034 | min_tx_space = ALIGN(min_tx_space, 1024); | |
1035 | min_tx_space >>= 10; | |
1036 | /* software strips receive CRC, so leave room for it */ | |
1037 | min_rx_space = adapter->max_frame_size; | |
1038 | min_rx_space = ALIGN(min_rx_space, 1024); | |
1039 | min_rx_space >>= 10; | |
1040 | ||
1041 | /* If current Tx allocation is less than the min Tx FIFO size, | |
1042 | * and the min Tx FIFO size is less than the current Rx FIFO | |
1043 | * allocation, take space away from current Rx allocation */ | |
1044 | if (tx_space < min_tx_space && | |
1045 | ((min_tx_space - tx_space) < pba)) { | |
1046 | pba = pba - (min_tx_space - tx_space); | |
1047 | ||
1048 | /* if short on rx space, rx wins and must trump tx | |
1049 | * adjustment */ | |
1050 | if (pba < min_rx_space) | |
1051 | pba = min_rx_space; | |
1052 | } | |
2d064c06 | 1053 | wr32(E1000_PBA, pba); |
9d5c8243 | 1054 | } |
9d5c8243 AK |
1055 | |
1056 | /* flow control settings */ | |
1057 | /* The high water mark must be low enough to fit one full frame | |
1058 | * (or the size used for early receive) above it in the Rx FIFO. | |
1059 | * Set it to the lower of: | |
1060 | * - 90% of the Rx FIFO size, or | |
1061 | * - the full Rx FIFO size minus one full frame */ | |
1062 | hwm = min(((pba << 10) * 9 / 10), | |
2d064c06 | 1063 | ((pba << 10) - 2 * adapter->max_frame_size)); |
9d5c8243 | 1064 | |
2d064c06 AD |
1065 | if (mac->type < e1000_82576) { |
1066 | fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */ | |
1067 | fc->low_water = fc->high_water - 8; | |
1068 | } else { | |
1069 | fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */ | |
1070 | fc->low_water = fc->high_water - 16; | |
1071 | } | |
9d5c8243 AK |
1072 | fc->pause_time = 0xFFFF; |
1073 | fc->send_xon = 1; | |
1074 | fc->type = fc->original_type; | |
1075 | ||
4ae196df AD |
1076 | /* disable receive for all VFs and wait one second */ |
1077 | if (adapter->vfs_allocated_count) { | |
1078 | int i; | |
1079 | for (i = 0 ; i < adapter->vfs_allocated_count; i++) | |
1080 | adapter->vf_data[i].clear_to_send = false; | |
1081 | ||
1082 | /* ping all the active vfs to let them know we are going down */ | |
1083 | igb_ping_all_vfs(adapter); | |
1084 | ||
1085 | /* disable transmits and receives */ | |
1086 | wr32(E1000_VFRE, 0); | |
1087 | wr32(E1000_VFTE, 0); | |
1088 | } | |
1089 | ||
9d5c8243 AK |
1090 | /* Allow time for pending master requests to run */ |
1091 | adapter->hw.mac.ops.reset_hw(&adapter->hw); | |
1092 | wr32(E1000_WUC, 0); | |
1093 | ||
1094 | if (adapter->hw.mac.ops.init_hw(&adapter->hw)) | |
1095 | dev_err(&adapter->pdev->dev, "Hardware Error\n"); | |
1096 | ||
1097 | igb_update_mng_vlan(adapter); | |
1098 | ||
1099 | /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ | |
1100 | wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); | |
1101 | ||
1102 | igb_reset_adaptive(&adapter->hw); | |
f5f4cf08 | 1103 | igb_get_phy_info(&adapter->hw); |
9d5c8243 AK |
1104 | } |
1105 | ||
2e5c6922 SH |
1106 | static const struct net_device_ops igb_netdev_ops = { |
1107 | .ndo_open = igb_open, | |
1108 | .ndo_stop = igb_close, | |
00829823 | 1109 | .ndo_start_xmit = igb_xmit_frame_adv, |
2e5c6922 SH |
1110 | .ndo_get_stats = igb_get_stats, |
1111 | .ndo_set_multicast_list = igb_set_multi, | |
1112 | .ndo_set_mac_address = igb_set_mac, | |
1113 | .ndo_change_mtu = igb_change_mtu, | |
1114 | .ndo_do_ioctl = igb_ioctl, | |
1115 | .ndo_tx_timeout = igb_tx_timeout, | |
1116 | .ndo_validate_addr = eth_validate_addr, | |
1117 | .ndo_vlan_rx_register = igb_vlan_rx_register, | |
1118 | .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, | |
1119 | .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, | |
1120 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1121 | .ndo_poll_controller = igb_netpoll, | |
1122 | #endif | |
1123 | }; | |
1124 | ||
9d5c8243 AK |
1125 | /** |
1126 | * igb_probe - Device Initialization Routine | |
1127 | * @pdev: PCI device information struct | |
1128 | * @ent: entry in igb_pci_tbl | |
1129 | * | |
1130 | * Returns 0 on success, negative on failure | |
1131 | * | |
1132 | * igb_probe initializes an adapter identified by a pci_dev structure. | |
1133 | * The OS initialization, configuring of the adapter private structure, | |
1134 | * and a hardware reset occur. | |
1135 | **/ | |
1136 | static int __devinit igb_probe(struct pci_dev *pdev, | |
1137 | const struct pci_device_id *ent) | |
1138 | { | |
1139 | struct net_device *netdev; | |
1140 | struct igb_adapter *adapter; | |
1141 | struct e1000_hw *hw; | |
1142 | const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; | |
1143 | unsigned long mmio_start, mmio_len; | |
2d6a5e95 | 1144 | int err, pci_using_dac; |
682337fe | 1145 | u16 eeprom_data = 0; |
9d5c8243 AK |
1146 | u16 eeprom_apme_mask = IGB_EEPROM_APME; |
1147 | u32 part_num; | |
1148 | ||
aed5dec3 | 1149 | err = pci_enable_device_mem(pdev); |
9d5c8243 AK |
1150 | if (err) |
1151 | return err; | |
1152 | ||
1153 | pci_using_dac = 0; | |
1154 | err = pci_set_dma_mask(pdev, DMA_64BIT_MASK); | |
1155 | if (!err) { | |
1156 | err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); | |
1157 | if (!err) | |
1158 | pci_using_dac = 1; | |
1159 | } else { | |
1160 | err = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
1161 | if (err) { | |
1162 | err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
1163 | if (err) { | |
1164 | dev_err(&pdev->dev, "No usable DMA " | |
1165 | "configuration, aborting\n"); | |
1166 | goto err_dma; | |
1167 | } | |
1168 | } | |
1169 | } | |
1170 | ||
aed5dec3 AD |
1171 | err = pci_request_selected_regions(pdev, pci_select_bars(pdev, |
1172 | IORESOURCE_MEM), | |
1173 | igb_driver_name); | |
9d5c8243 AK |
1174 | if (err) |
1175 | goto err_pci_reg; | |
1176 | ||
ea943d41 JK |
1177 | err = pci_enable_pcie_error_reporting(pdev); |
1178 | if (err) { | |
1179 | dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed " | |
1180 | "0x%x\n", err); | |
1181 | /* non-fatal, continue */ | |
1182 | } | |
40a914fa | 1183 | |
9d5c8243 | 1184 | pci_set_master(pdev); |
c682fc23 | 1185 | pci_save_state(pdev); |
9d5c8243 AK |
1186 | |
1187 | err = -ENOMEM; | |
1bfaf07b AD |
1188 | netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), |
1189 | IGB_ABS_MAX_TX_QUEUES); | |
9d5c8243 AK |
1190 | if (!netdev) |
1191 | goto err_alloc_etherdev; | |
1192 | ||
1193 | SET_NETDEV_DEV(netdev, &pdev->dev); | |
1194 | ||
1195 | pci_set_drvdata(pdev, netdev); | |
1196 | adapter = netdev_priv(netdev); | |
1197 | adapter->netdev = netdev; | |
1198 | adapter->pdev = pdev; | |
1199 | hw = &adapter->hw; | |
1200 | hw->back = adapter; | |
1201 | adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE; | |
1202 | ||
1203 | mmio_start = pci_resource_start(pdev, 0); | |
1204 | mmio_len = pci_resource_len(pdev, 0); | |
1205 | ||
1206 | err = -EIO; | |
28b0759c AD |
1207 | hw->hw_addr = ioremap(mmio_start, mmio_len); |
1208 | if (!hw->hw_addr) | |
9d5c8243 AK |
1209 | goto err_ioremap; |
1210 | ||
2e5c6922 | 1211 | netdev->netdev_ops = &igb_netdev_ops; |
9d5c8243 | 1212 | igb_set_ethtool_ops(netdev); |
9d5c8243 | 1213 | netdev->watchdog_timeo = 5 * HZ; |
9d5c8243 AK |
1214 | |
1215 | strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); | |
1216 | ||
1217 | netdev->mem_start = mmio_start; | |
1218 | netdev->mem_end = mmio_start + mmio_len; | |
1219 | ||
9d5c8243 AK |
1220 | /* PCI config space info */ |
1221 | hw->vendor_id = pdev->vendor; | |
1222 | hw->device_id = pdev->device; | |
1223 | hw->revision_id = pdev->revision; | |
1224 | hw->subsystem_vendor_id = pdev->subsystem_vendor; | |
1225 | hw->subsystem_device_id = pdev->subsystem_device; | |
1226 | ||
1227 | /* setup the private structure */ | |
1228 | hw->back = adapter; | |
1229 | /* Copy the default MAC, PHY and NVM function pointers */ | |
1230 | memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); | |
1231 | memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); | |
1232 | memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); | |
1233 | /* Initialize skew-specific constants */ | |
1234 | err = ei->get_invariants(hw); | |
1235 | if (err) | |
450c87c8 | 1236 | goto err_sw_init; |
9d5c8243 | 1237 | |
450c87c8 | 1238 | /* setup the private structure */ |
9d5c8243 AK |
1239 | err = igb_sw_init(adapter); |
1240 | if (err) | |
1241 | goto err_sw_init; | |
1242 | ||
1243 | igb_get_bus_info_pcie(hw); | |
1244 | ||
7dfc16fa AD |
1245 | /* set flags */ |
1246 | switch (hw->mac.type) { | |
7dfc16fa | 1247 | case e1000_82575: |
7dfc16fa AD |
1248 | adapter->flags |= IGB_FLAG_NEED_CTX_IDX; |
1249 | break; | |
bbd98fe4 | 1250 | case e1000_82576: |
7dfc16fa AD |
1251 | default: |
1252 | break; | |
1253 | } | |
1254 | ||
9d5c8243 AK |
1255 | hw->phy.autoneg_wait_to_complete = false; |
1256 | hw->mac.adaptive_ifs = true; | |
1257 | ||
1258 | /* Copper options */ | |
1259 | if (hw->phy.media_type == e1000_media_type_copper) { | |
1260 | hw->phy.mdix = AUTO_ALL_MODES; | |
1261 | hw->phy.disable_polarity_correction = false; | |
1262 | hw->phy.ms_type = e1000_ms_hw_default; | |
1263 | } | |
1264 | ||
1265 | if (igb_check_reset_block(hw)) | |
1266 | dev_info(&pdev->dev, | |
1267 | "PHY reset is blocked due to SOL/IDER session.\n"); | |
1268 | ||
1269 | netdev->features = NETIF_F_SG | | |
7d8eb29e | 1270 | NETIF_F_IP_CSUM | |
9d5c8243 AK |
1271 | NETIF_F_HW_VLAN_TX | |
1272 | NETIF_F_HW_VLAN_RX | | |
1273 | NETIF_F_HW_VLAN_FILTER; | |
1274 | ||
7d8eb29e | 1275 | netdev->features |= NETIF_F_IPV6_CSUM; |
9d5c8243 | 1276 | netdev->features |= NETIF_F_TSO; |
9d5c8243 | 1277 | netdev->features |= NETIF_F_TSO6; |
48f29ffc | 1278 | |
5c0999b7 | 1279 | netdev->features |= NETIF_F_GRO; |
d3352520 | 1280 | |
48f29ffc JK |
1281 | netdev->vlan_features |= NETIF_F_TSO; |
1282 | netdev->vlan_features |= NETIF_F_TSO6; | |
7d8eb29e | 1283 | netdev->vlan_features |= NETIF_F_IP_CSUM; |
48f29ffc JK |
1284 | netdev->vlan_features |= NETIF_F_SG; |
1285 | ||
9d5c8243 AK |
1286 | if (pci_using_dac) |
1287 | netdev->features |= NETIF_F_HIGHDMA; | |
1288 | ||
9d5c8243 AK |
1289 | adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw); |
1290 | ||
1291 | /* before reading the NVM, reset the controller to put the device in a | |
1292 | * known good starting state */ | |
1293 | hw->mac.ops.reset_hw(hw); | |
1294 | ||
1295 | /* make sure the NVM is good */ | |
1296 | if (igb_validate_nvm_checksum(hw) < 0) { | |
1297 | dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); | |
1298 | err = -EIO; | |
1299 | goto err_eeprom; | |
1300 | } | |
1301 | ||
1302 | /* copy the MAC address out of the NVM */ | |
1303 | if (hw->mac.ops.read_mac_addr(hw)) | |
1304 | dev_err(&pdev->dev, "NVM Read Error\n"); | |
1305 | ||
1306 | memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len); | |
1307 | memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len); | |
1308 | ||
1309 | if (!is_valid_ether_addr(netdev->perm_addr)) { | |
1310 | dev_err(&pdev->dev, "Invalid MAC Address\n"); | |
1311 | err = -EIO; | |
1312 | goto err_eeprom; | |
1313 | } | |
1314 | ||
0e340485 AD |
1315 | setup_timer(&adapter->watchdog_timer, &igb_watchdog, |
1316 | (unsigned long) adapter); | |
1317 | setup_timer(&adapter->phy_info_timer, &igb_update_phy_info, | |
1318 | (unsigned long) adapter); | |
9d5c8243 AK |
1319 | |
1320 | INIT_WORK(&adapter->reset_task, igb_reset_task); | |
1321 | INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); | |
1322 | ||
450c87c8 | 1323 | /* Initialize link properties that are user-changeable */ |
9d5c8243 AK |
1324 | adapter->fc_autoneg = true; |
1325 | hw->mac.autoneg = true; | |
1326 | hw->phy.autoneg_advertised = 0x2f; | |
1327 | ||
1328 | hw->fc.original_type = e1000_fc_default; | |
1329 | hw->fc.type = e1000_fc_default; | |
1330 | ||
cbd347ad | 1331 | adapter->itr_setting = IGB_DEFAULT_ITR; |
9d5c8243 AK |
1332 | adapter->itr = IGB_START_ITR; |
1333 | ||
1334 | igb_validate_mdi_setting(hw); | |
1335 | ||
1336 | adapter->rx_csum = 1; | |
1337 | ||
1338 | /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM, | |
1339 | * enable the ACPI Magic Packet filter | |
1340 | */ | |
1341 | ||
a2cf8b6c | 1342 | if (hw->bus.func == 0) |
312c75ae | 1343 | hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); |
a2cf8b6c AD |
1344 | else if (hw->bus.func == 1) |
1345 | hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); | |
9d5c8243 AK |
1346 | |
1347 | if (eeprom_data & eeprom_apme_mask) | |
1348 | adapter->eeprom_wol |= E1000_WUFC_MAG; | |
1349 | ||
1350 | /* now that we have the eeprom settings, apply the special cases where | |
1351 | * the eeprom may be wrong or the board simply won't support wake on | |
1352 | * lan on a particular port */ | |
1353 | switch (pdev->device) { | |
1354 | case E1000_DEV_ID_82575GB_QUAD_COPPER: | |
1355 | adapter->eeprom_wol = 0; | |
1356 | break; | |
1357 | case E1000_DEV_ID_82575EB_FIBER_SERDES: | |
2d064c06 AD |
1358 | case E1000_DEV_ID_82576_FIBER: |
1359 | case E1000_DEV_ID_82576_SERDES: | |
9d5c8243 AK |
1360 | /* Wake events only supported on port A for dual fiber |
1361 | * regardless of eeprom setting */ | |
1362 | if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) | |
1363 | adapter->eeprom_wol = 0; | |
1364 | break; | |
c8ea5ea9 AD |
1365 | case E1000_DEV_ID_82576_QUAD_COPPER: |
1366 | /* if quad port adapter, disable WoL on all but port A */ | |
1367 | if (global_quad_port_a != 0) | |
1368 | adapter->eeprom_wol = 0; | |
1369 | else | |
1370 | adapter->flags |= IGB_FLAG_QUAD_PORT_A; | |
1371 | /* Reset for multiple quad port adapters */ | |
1372 | if (++global_quad_port_a == 4) | |
1373 | global_quad_port_a = 0; | |
1374 | break; | |
9d5c8243 AK |
1375 | } |
1376 | ||
1377 | /* initialize the wol settings based on the eeprom settings */ | |
1378 | adapter->wol = adapter->eeprom_wol; | |
e1b86d84 | 1379 | device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); |
9d5c8243 AK |
1380 | |
1381 | /* reset the hardware with the new settings */ | |
1382 | igb_reset(adapter); | |
1383 | ||
1384 | /* let the f/w know that the h/w is now under the control of the | |
1385 | * driver. */ | |
1386 | igb_get_hw_control(adapter); | |
1387 | ||
1388 | /* tell the stack to leave us alone until igb_open() is called */ | |
1389 | netif_carrier_off(netdev); | |
fd2ea0a7 | 1390 | netif_tx_stop_all_queues(netdev); |
9d5c8243 AK |
1391 | |
1392 | strcpy(netdev->name, "eth%d"); | |
1393 | err = register_netdev(netdev); | |
1394 | if (err) | |
1395 | goto err_register; | |
1396 | ||
37680117 AD |
1397 | #ifdef CONFIG_PCI_IOV |
1398 | /* since iov functionality isn't critical to base device function we | |
1399 | * can accept failure. If it fails we don't allow iov to be enabled */ | |
1400 | if (hw->mac.type == e1000_82576) { | |
1401 | err = pci_enable_sriov(pdev, 0); | |
1402 | if (!err) | |
1403 | err = device_create_file(&netdev->dev, | |
1404 | &dev_attr_num_vfs); | |
1405 | if (err) | |
1406 | dev_err(&pdev->dev, "Failed to initialize IOV\n"); | |
1407 | } | |
1408 | ||
1409 | #endif | |
421e02f0 | 1410 | #ifdef CONFIG_IGB_DCA |
bbd98fe4 | 1411 | if (dca_add_requester(&pdev->dev) == 0) { |
7dfc16fa | 1412 | adapter->flags |= IGB_FLAG_DCA_ENABLED; |
fe4506b6 JC |
1413 | dev_info(&pdev->dev, "DCA enabled\n"); |
1414 | /* Always use CB2 mode, difference is masked | |
1415 | * in the CB driver. */ | |
cbd347ad | 1416 | wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); |
fe4506b6 JC |
1417 | igb_setup_dca(adapter); |
1418 | } | |
1419 | #endif | |
1420 | ||
38c845c7 PO |
1421 | /* |
1422 | * Initialize hardware timer: we keep it running just in case | |
1423 | * that some program needs it later on. | |
1424 | */ | |
1425 | memset(&adapter->cycles, 0, sizeof(adapter->cycles)); | |
1426 | adapter->cycles.read = igb_read_clock; | |
1427 | adapter->cycles.mask = CLOCKSOURCE_MASK(64); | |
1428 | adapter->cycles.mult = 1; | |
1429 | adapter->cycles.shift = IGB_TSYNC_SHIFT; | |
1430 | wr32(E1000_TIMINCA, | |
1431 | (1<<24) | | |
1432 | IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS * IGB_TSYNC_SCALE); | |
1433 | #if 0 | |
1434 | /* | |
1435 | * Avoid rollover while we initialize by resetting the time counter. | |
1436 | */ | |
1437 | wr32(E1000_SYSTIML, 0x00000000); | |
1438 | wr32(E1000_SYSTIMH, 0x00000000); | |
1439 | #else | |
1440 | /* | |
1441 | * Set registers so that rollover occurs soon to test this. | |
1442 | */ | |
1443 | wr32(E1000_SYSTIML, 0x00000000); | |
1444 | wr32(E1000_SYSTIMH, 0xFF800000); | |
1445 | #endif | |
1446 | wrfl(); | |
1447 | timecounter_init(&adapter->clock, | |
1448 | &adapter->cycles, | |
1449 | ktime_to_ns(ktime_get_real())); | |
1450 | ||
33af6bcc PO |
1451 | /* |
1452 | * Synchronize our NIC clock against system wall clock. NIC | |
1453 | * time stamp reading requires ~3us per sample, each sample | |
1454 | * was pretty stable even under load => only require 10 | |
1455 | * samples for each offset comparison. | |
1456 | */ | |
1457 | memset(&adapter->compare, 0, sizeof(adapter->compare)); | |
1458 | adapter->compare.source = &adapter->clock; | |
1459 | adapter->compare.target = ktime_get_real; | |
1460 | adapter->compare.num_samples = 10; | |
1461 | timecompare_update(&adapter->compare, 0); | |
1462 | ||
38c845c7 PO |
1463 | #ifdef DEBUG |
1464 | { | |
1465 | char buffer[160]; | |
1466 | printk(KERN_DEBUG | |
1467 | "igb: %s: hw %p initialized timer\n", | |
1468 | igb_get_time_str(adapter, buffer), | |
1469 | &adapter->hw); | |
1470 | } | |
1471 | #endif | |
1472 | ||
9d5c8243 AK |
1473 | dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); |
1474 | /* print bus type/speed/width info */ | |
7c510e4b | 1475 | dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", |
9d5c8243 AK |
1476 | netdev->name, |
1477 | ((hw->bus.speed == e1000_bus_speed_2500) | |
1478 | ? "2.5Gb/s" : "unknown"), | |
1479 | ((hw->bus.width == e1000_bus_width_pcie_x4) | |
1480 | ? "Width x4" : (hw->bus.width == e1000_bus_width_pcie_x1) | |
1481 | ? "Width x1" : "unknown"), | |
7c510e4b | 1482 | netdev->dev_addr); |
9d5c8243 AK |
1483 | |
1484 | igb_read_part_num(hw, &part_num); | |
1485 | dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name, | |
1486 | (part_num >> 8), (part_num & 0xff)); | |
1487 | ||
1488 | dev_info(&pdev->dev, | |
1489 | "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", | |
1490 | adapter->msix_entries ? "MSI-X" : | |
7dfc16fa | 1491 | (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", |
9d5c8243 AK |
1492 | adapter->num_rx_queues, adapter->num_tx_queues); |
1493 | ||
9d5c8243 AK |
1494 | return 0; |
1495 | ||
1496 | err_register: | |
1497 | igb_release_hw_control(adapter); | |
1498 | err_eeprom: | |
1499 | if (!igb_check_reset_block(hw)) | |
f5f4cf08 | 1500 | igb_reset_phy(hw); |
9d5c8243 AK |
1501 | |
1502 | if (hw->flash_address) | |
1503 | iounmap(hw->flash_address); | |
1504 | ||
a88f10ec | 1505 | igb_free_queues(adapter); |
9d5c8243 | 1506 | err_sw_init: |
9d5c8243 AK |
1507 | iounmap(hw->hw_addr); |
1508 | err_ioremap: | |
1509 | free_netdev(netdev); | |
1510 | err_alloc_etherdev: | |
aed5dec3 AD |
1511 | pci_release_selected_regions(pdev, pci_select_bars(pdev, |
1512 | IORESOURCE_MEM)); | |
9d5c8243 AK |
1513 | err_pci_reg: |
1514 | err_dma: | |
1515 | pci_disable_device(pdev); | |
1516 | return err; | |
1517 | } | |
1518 | ||
1519 | /** | |
1520 | * igb_remove - Device Removal Routine | |
1521 | * @pdev: PCI device information struct | |
1522 | * | |
1523 | * igb_remove is called by the PCI subsystem to alert the driver | |
1524 | * that it should release a PCI device. The could be caused by a | |
1525 | * Hot-Plug event, or because the driver is going to be removed from | |
1526 | * memory. | |
1527 | **/ | |
1528 | static void __devexit igb_remove(struct pci_dev *pdev) | |
1529 | { | |
1530 | struct net_device *netdev = pci_get_drvdata(pdev); | |
1531 | struct igb_adapter *adapter = netdev_priv(netdev); | |
fe4506b6 | 1532 | struct e1000_hw *hw = &adapter->hw; |
ea943d41 | 1533 | int err; |
9d5c8243 AK |
1534 | |
1535 | /* flush_scheduled work may reschedule our watchdog task, so | |
1536 | * explicitly disable watchdog tasks from being rescheduled */ | |
1537 | set_bit(__IGB_DOWN, &adapter->state); | |
1538 | del_timer_sync(&adapter->watchdog_timer); | |
1539 | del_timer_sync(&adapter->phy_info_timer); | |
1540 | ||
1541 | flush_scheduled_work(); | |
1542 | ||
421e02f0 | 1543 | #ifdef CONFIG_IGB_DCA |
7dfc16fa | 1544 | if (adapter->flags & IGB_FLAG_DCA_ENABLED) { |
fe4506b6 JC |
1545 | dev_info(&pdev->dev, "DCA disabled\n"); |
1546 | dca_remove_requester(&pdev->dev); | |
7dfc16fa | 1547 | adapter->flags &= ~IGB_FLAG_DCA_ENABLED; |
cbd347ad | 1548 | wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); |
fe4506b6 JC |
1549 | } |
1550 | #endif | |
1551 | ||
9d5c8243 AK |
1552 | /* Release control of h/w to f/w. If f/w is AMT enabled, this |
1553 | * would have already happened in close and is redundant. */ | |
1554 | igb_release_hw_control(adapter); | |
1555 | ||
1556 | unregister_netdev(netdev); | |
1557 | ||
f5f4cf08 AD |
1558 | if (!igb_check_reset_block(&adapter->hw)) |
1559 | igb_reset_phy(&adapter->hw); | |
9d5c8243 | 1560 | |
9d5c8243 AK |
1561 | igb_reset_interrupt_capability(adapter); |
1562 | ||
a88f10ec | 1563 | igb_free_queues(adapter); |
9d5c8243 | 1564 | |
37680117 AD |
1565 | #ifdef CONFIG_PCI_IOV |
1566 | /* reclaim resources allocated to VFs */ | |
1567 | if (adapter->vf_data) { | |
1568 | /* disable iov and allow time for transactions to clear */ | |
1569 | pci_disable_sriov(pdev); | |
1570 | msleep(500); | |
1571 | ||
1572 | kfree(adapter->vf_data); | |
1573 | adapter->vf_data = NULL; | |
1574 | wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); | |
1575 | msleep(100); | |
1576 | dev_info(&pdev->dev, "IOV Disabled\n"); | |
1577 | } | |
1578 | #endif | |
28b0759c AD |
1579 | iounmap(hw->hw_addr); |
1580 | if (hw->flash_address) | |
1581 | iounmap(hw->flash_address); | |
aed5dec3 AD |
1582 | pci_release_selected_regions(pdev, pci_select_bars(pdev, |
1583 | IORESOURCE_MEM)); | |
9d5c8243 AK |
1584 | |
1585 | free_netdev(netdev); | |
1586 | ||
ea943d41 JK |
1587 | err = pci_disable_pcie_error_reporting(pdev); |
1588 | if (err) | |
1589 | dev_err(&pdev->dev, | |
1590 | "pci_disable_pcie_error_reporting failed 0x%x\n", err); | |
40a914fa | 1591 | |
9d5c8243 AK |
1592 | pci_disable_device(pdev); |
1593 | } | |
1594 | ||
1595 | /** | |
1596 | * igb_sw_init - Initialize general software structures (struct igb_adapter) | |
1597 | * @adapter: board private structure to initialize | |
1598 | * | |
1599 | * igb_sw_init initializes the Adapter private data structure. | |
1600 | * Fields are initialized based on PCI device information and | |
1601 | * OS network device settings (MTU size). | |
1602 | **/ | |
1603 | static int __devinit igb_sw_init(struct igb_adapter *adapter) | |
1604 | { | |
1605 | struct e1000_hw *hw = &adapter->hw; | |
1606 | struct net_device *netdev = adapter->netdev; | |
1607 | struct pci_dev *pdev = adapter->pdev; | |
1608 | ||
1609 | pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); | |
1610 | ||
68fd9910 AD |
1611 | adapter->tx_ring_count = IGB_DEFAULT_TXD; |
1612 | adapter->rx_ring_count = IGB_DEFAULT_RXD; | |
9d5c8243 AK |
1613 | adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE; |
1614 | adapter->rx_ps_hdr_size = 0; /* disable packet split */ | |
1615 | adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; | |
1616 | adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; | |
1617 | ||
661086df PWJ |
1618 | /* This call may decrease the number of queues depending on |
1619 | * interrupt mode. */ | |
9d5c8243 AK |
1620 | igb_set_interrupt_capability(adapter); |
1621 | ||
1622 | if (igb_alloc_queues(adapter)) { | |
1623 | dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); | |
1624 | return -ENOMEM; | |
1625 | } | |
1626 | ||
1627 | /* Explicitly disable IRQ since the NIC can be in any state. */ | |
1628 | igb_irq_disable(adapter); | |
1629 | ||
1630 | set_bit(__IGB_DOWN, &adapter->state); | |
1631 | return 0; | |
1632 | } | |
1633 | ||
1634 | /** | |
1635 | * igb_open - Called when a network interface is made active | |
1636 | * @netdev: network interface device structure | |
1637 | * | |
1638 | * Returns 0 on success, negative value on failure | |
1639 | * | |
1640 | * The open entry point is called when a network interface is made | |
1641 | * active by the system (IFF_UP). At this point all resources needed | |
1642 | * for transmit and receive operations are allocated, the interrupt | |
1643 | * handler is registered with the OS, the watchdog timer is started, | |
1644 | * and the stack is notified that the interface is ready. | |
1645 | **/ | |
1646 | static int igb_open(struct net_device *netdev) | |
1647 | { | |
1648 | struct igb_adapter *adapter = netdev_priv(netdev); | |
1649 | struct e1000_hw *hw = &adapter->hw; | |
1650 | int err; | |
1651 | int i; | |
1652 | ||
1653 | /* disallow open during test */ | |
1654 | if (test_bit(__IGB_TESTING, &adapter->state)) | |
1655 | return -EBUSY; | |
1656 | ||
1657 | /* allocate transmit descriptors */ | |
1658 | err = igb_setup_all_tx_resources(adapter); | |
1659 | if (err) | |
1660 | goto err_setup_tx; | |
1661 | ||
1662 | /* allocate receive descriptors */ | |
1663 | err = igb_setup_all_rx_resources(adapter); | |
1664 | if (err) | |
1665 | goto err_setup_rx; | |
1666 | ||
1667 | /* e1000_power_up_phy(adapter); */ | |
1668 | ||
1669 | adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; | |
1670 | if ((adapter->hw.mng_cookie.status & | |
1671 | E1000_MNG_DHCP_COOKIE_STATUS_VLAN)) | |
1672 | igb_update_mng_vlan(adapter); | |
1673 | ||
1674 | /* before we allocate an interrupt, we must be ready to handle it. | |
1675 | * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt | |
1676 | * as soon as we call pci_request_irq, so we have to setup our | |
1677 | * clean_rx handler before we do so. */ | |
1678 | igb_configure(adapter); | |
1679 | ||
4ae196df | 1680 | igb_vmm_control(adapter); |
e1739522 AD |
1681 | igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0); |
1682 | igb_set_vmolr(hw, adapter->vfs_allocated_count); | |
1683 | ||
9d5c8243 AK |
1684 | err = igb_request_irq(adapter); |
1685 | if (err) | |
1686 | goto err_req_irq; | |
1687 | ||
1688 | /* From here on the code is the same as igb_up() */ | |
1689 | clear_bit(__IGB_DOWN, &adapter->state); | |
1690 | ||
844290e5 PW |
1691 | for (i = 0; i < adapter->num_rx_queues; i++) |
1692 | napi_enable(&adapter->rx_ring[i].napi); | |
9d5c8243 AK |
1693 | |
1694 | /* Clear any pending interrupts. */ | |
1695 | rd32(E1000_ICR); | |
844290e5 PW |
1696 | |
1697 | igb_irq_enable(adapter); | |
1698 | ||
d55b53ff JK |
1699 | netif_tx_start_all_queues(netdev); |
1700 | ||
9d5c8243 AK |
1701 | /* Fire a link status change interrupt to start the watchdog. */ |
1702 | wr32(E1000_ICS, E1000_ICS_LSC); | |
1703 | ||
1704 | return 0; | |
1705 | ||
1706 | err_req_irq: | |
1707 | igb_release_hw_control(adapter); | |
1708 | /* e1000_power_down_phy(adapter); */ | |
1709 | igb_free_all_rx_resources(adapter); | |
1710 | err_setup_rx: | |
1711 | igb_free_all_tx_resources(adapter); | |
1712 | err_setup_tx: | |
1713 | igb_reset(adapter); | |
1714 | ||
1715 | return err; | |
1716 | } | |
1717 | ||
1718 | /** | |
1719 | * igb_close - Disables a network interface | |
1720 | * @netdev: network interface device structure | |
1721 | * | |
1722 | * Returns 0, this is not allowed to fail | |
1723 | * | |
1724 | * The close entry point is called when an interface is de-activated | |
1725 | * by the OS. The hardware is still under the driver's control, but | |
1726 | * needs to be disabled. A global MAC reset is issued to stop the | |
1727 | * hardware, and all transmit and receive resources are freed. | |
1728 | **/ | |
1729 | static int igb_close(struct net_device *netdev) | |
1730 | { | |
1731 | struct igb_adapter *adapter = netdev_priv(netdev); | |
1732 | ||
1733 | WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); | |
1734 | igb_down(adapter); | |
1735 | ||
1736 | igb_free_irq(adapter); | |
1737 | ||
1738 | igb_free_all_tx_resources(adapter); | |
1739 | igb_free_all_rx_resources(adapter); | |
1740 | ||
1741 | /* kill manageability vlan ID if supported, but not if a vlan with | |
1742 | * the same ID is registered on the host OS (let 8021q kill it) */ | |
1743 | if ((adapter->hw.mng_cookie.status & | |
1744 | E1000_MNG_DHCP_COOKIE_STATUS_VLAN) && | |
1745 | !(adapter->vlgrp && | |
1746 | vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id))) | |
1747 | igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id); | |
1748 | ||
1749 | return 0; | |
1750 | } | |
1751 | ||
1752 | /** | |
1753 | * igb_setup_tx_resources - allocate Tx resources (Descriptors) | |
1754 | * @adapter: board private structure | |
1755 | * @tx_ring: tx descriptor ring (for a specific queue) to setup | |
1756 | * | |
1757 | * Return 0 on success, negative on failure | |
1758 | **/ | |
9d5c8243 AK |
1759 | int igb_setup_tx_resources(struct igb_adapter *adapter, |
1760 | struct igb_ring *tx_ring) | |
1761 | { | |
1762 | struct pci_dev *pdev = adapter->pdev; | |
1763 | int size; | |
1764 | ||
1765 | size = sizeof(struct igb_buffer) * tx_ring->count; | |
1766 | tx_ring->buffer_info = vmalloc(size); | |
1767 | if (!tx_ring->buffer_info) | |
1768 | goto err; | |
1769 | memset(tx_ring->buffer_info, 0, size); | |
1770 | ||
1771 | /* round up to nearest 4K */ | |
85e8d004 | 1772 | tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); |
9d5c8243 AK |
1773 | tx_ring->size = ALIGN(tx_ring->size, 4096); |
1774 | ||
1775 | tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size, | |
1776 | &tx_ring->dma); | |
1777 | ||
1778 | if (!tx_ring->desc) | |
1779 | goto err; | |
1780 | ||
1781 | tx_ring->adapter = adapter; | |
1782 | tx_ring->next_to_use = 0; | |
1783 | tx_ring->next_to_clean = 0; | |
9d5c8243 AK |
1784 | return 0; |
1785 | ||
1786 | err: | |
1787 | vfree(tx_ring->buffer_info); | |
1788 | dev_err(&adapter->pdev->dev, | |
1789 | "Unable to allocate memory for the transmit descriptor ring\n"); | |
1790 | return -ENOMEM; | |
1791 | } | |
1792 | ||
1793 | /** | |
1794 | * igb_setup_all_tx_resources - wrapper to allocate Tx resources | |
1795 | * (Descriptors) for all queues | |
1796 | * @adapter: board private structure | |
1797 | * | |
1798 | * Return 0 on success, negative on failure | |
1799 | **/ | |
1800 | static int igb_setup_all_tx_resources(struct igb_adapter *adapter) | |
1801 | { | |
1802 | int i, err = 0; | |
661086df | 1803 | int r_idx; |
9d5c8243 AK |
1804 | |
1805 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
1806 | err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]); | |
1807 | if (err) { | |
1808 | dev_err(&adapter->pdev->dev, | |
1809 | "Allocation for Tx Queue %u failed\n", i); | |
1810 | for (i--; i >= 0; i--) | |
3b644cf6 | 1811 | igb_free_tx_resources(&adapter->tx_ring[i]); |
9d5c8243 AK |
1812 | break; |
1813 | } | |
1814 | } | |
1815 | ||
661086df PWJ |
1816 | for (i = 0; i < IGB_MAX_TX_QUEUES; i++) { |
1817 | r_idx = i % adapter->num_tx_queues; | |
1818 | adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx]; | |
eebbbdba | 1819 | } |
9d5c8243 AK |
1820 | return err; |
1821 | } | |
1822 | ||
1823 | /** | |
1824 | * igb_configure_tx - Configure transmit Unit after Reset | |
1825 | * @adapter: board private structure | |
1826 | * | |
1827 | * Configure the Tx unit of the MAC after a reset. | |
1828 | **/ | |
1829 | static void igb_configure_tx(struct igb_adapter *adapter) | |
1830 | { | |
0e014cb1 | 1831 | u64 tdba; |
9d5c8243 AK |
1832 | struct e1000_hw *hw = &adapter->hw; |
1833 | u32 tctl; | |
1834 | u32 txdctl, txctrl; | |
26bc19ec | 1835 | int i, j; |
9d5c8243 AK |
1836 | |
1837 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
73cd78f1 | 1838 | struct igb_ring *ring = &adapter->tx_ring[i]; |
26bc19ec AD |
1839 | j = ring->reg_idx; |
1840 | wr32(E1000_TDLEN(j), | |
85e8d004 | 1841 | ring->count * sizeof(union e1000_adv_tx_desc)); |
9d5c8243 | 1842 | tdba = ring->dma; |
26bc19ec | 1843 | wr32(E1000_TDBAL(j), |
73cd78f1 | 1844 | tdba & 0x00000000ffffffffULL); |
26bc19ec | 1845 | wr32(E1000_TDBAH(j), tdba >> 32); |
9d5c8243 | 1846 | |
26bc19ec AD |
1847 | ring->head = E1000_TDH(j); |
1848 | ring->tail = E1000_TDT(j); | |
9d5c8243 AK |
1849 | writel(0, hw->hw_addr + ring->tail); |
1850 | writel(0, hw->hw_addr + ring->head); | |
26bc19ec | 1851 | txdctl = rd32(E1000_TXDCTL(j)); |
9d5c8243 | 1852 | txdctl |= E1000_TXDCTL_QUEUE_ENABLE; |
26bc19ec | 1853 | wr32(E1000_TXDCTL(j), txdctl); |
9d5c8243 AK |
1854 | |
1855 | /* Turn off Relaxed Ordering on head write-backs. The | |
1856 | * writebacks MUST be delivered in order or it will | |
1857 | * completely screw up our bookeeping. | |
1858 | */ | |
26bc19ec | 1859 | txctrl = rd32(E1000_DCA_TXCTRL(j)); |
9d5c8243 | 1860 | txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN; |
26bc19ec | 1861 | wr32(E1000_DCA_TXCTRL(j), txctrl); |
9d5c8243 AK |
1862 | } |
1863 | ||
e1739522 AD |
1864 | /* disable queue 0 to prevent tail bump w/o re-configuration */ |
1865 | if (adapter->vfs_allocated_count) | |
1866 | wr32(E1000_TXDCTL(0), 0); | |
9d5c8243 AK |
1867 | |
1868 | /* Program the Transmit Control Register */ | |
9d5c8243 AK |
1869 | tctl = rd32(E1000_TCTL); |
1870 | tctl &= ~E1000_TCTL_CT; | |
1871 | tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | | |
1872 | (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); | |
1873 | ||
1874 | igb_config_collision_dist(hw); | |
1875 | ||
1876 | /* Setup Transmit Descriptor Settings for eop descriptor */ | |
1877 | adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS; | |
1878 | ||
1879 | /* Enable transmits */ | |
1880 | tctl |= E1000_TCTL_EN; | |
1881 | ||
1882 | wr32(E1000_TCTL, tctl); | |
1883 | } | |
1884 | ||
1885 | /** | |
1886 | * igb_setup_rx_resources - allocate Rx resources (Descriptors) | |
1887 | * @adapter: board private structure | |
1888 | * @rx_ring: rx descriptor ring (for a specific queue) to setup | |
1889 | * | |
1890 | * Returns 0 on success, negative on failure | |
1891 | **/ | |
9d5c8243 AK |
1892 | int igb_setup_rx_resources(struct igb_adapter *adapter, |
1893 | struct igb_ring *rx_ring) | |
1894 | { | |
1895 | struct pci_dev *pdev = adapter->pdev; | |
1896 | int size, desc_len; | |
1897 | ||
1898 | size = sizeof(struct igb_buffer) * rx_ring->count; | |
1899 | rx_ring->buffer_info = vmalloc(size); | |
1900 | if (!rx_ring->buffer_info) | |
1901 | goto err; | |
1902 | memset(rx_ring->buffer_info, 0, size); | |
1903 | ||
1904 | desc_len = sizeof(union e1000_adv_rx_desc); | |
1905 | ||
1906 | /* Round up to nearest 4K */ | |
1907 | rx_ring->size = rx_ring->count * desc_len; | |
1908 | rx_ring->size = ALIGN(rx_ring->size, 4096); | |
1909 | ||
1910 | rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, | |
1911 | &rx_ring->dma); | |
1912 | ||
1913 | if (!rx_ring->desc) | |
1914 | goto err; | |
1915 | ||
1916 | rx_ring->next_to_clean = 0; | |
1917 | rx_ring->next_to_use = 0; | |
9d5c8243 AK |
1918 | |
1919 | rx_ring->adapter = adapter; | |
9d5c8243 AK |
1920 | |
1921 | return 0; | |
1922 | ||
1923 | err: | |
1924 | vfree(rx_ring->buffer_info); | |
1925 | dev_err(&adapter->pdev->dev, "Unable to allocate memory for " | |
1926 | "the receive descriptor ring\n"); | |
1927 | return -ENOMEM; | |
1928 | } | |
1929 | ||
1930 | /** | |
1931 | * igb_setup_all_rx_resources - wrapper to allocate Rx resources | |
1932 | * (Descriptors) for all queues | |
1933 | * @adapter: board private structure | |
1934 | * | |
1935 | * Return 0 on success, negative on failure | |
1936 | **/ | |
1937 | static int igb_setup_all_rx_resources(struct igb_adapter *adapter) | |
1938 | { | |
1939 | int i, err = 0; | |
1940 | ||
1941 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
1942 | err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]); | |
1943 | if (err) { | |
1944 | dev_err(&adapter->pdev->dev, | |
1945 | "Allocation for Rx Queue %u failed\n", i); | |
1946 | for (i--; i >= 0; i--) | |
3b644cf6 | 1947 | igb_free_rx_resources(&adapter->rx_ring[i]); |
9d5c8243 AK |
1948 | break; |
1949 | } | |
1950 | } | |
1951 | ||
1952 | return err; | |
1953 | } | |
1954 | ||
1955 | /** | |
1956 | * igb_setup_rctl - configure the receive control registers | |
1957 | * @adapter: Board private structure | |
1958 | **/ | |
1959 | static void igb_setup_rctl(struct igb_adapter *adapter) | |
1960 | { | |
1961 | struct e1000_hw *hw = &adapter->hw; | |
1962 | u32 rctl; | |
1963 | u32 srrctl = 0; | |
26bc19ec | 1964 | int i, j; |
9d5c8243 AK |
1965 | |
1966 | rctl = rd32(E1000_RCTL); | |
1967 | ||
1968 | rctl &= ~(3 << E1000_RCTL_MO_SHIFT); | |
69d728ba | 1969 | rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); |
9d5c8243 | 1970 | |
69d728ba | 1971 | rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | |
28b0759c | 1972 | (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); |
9d5c8243 | 1973 | |
87cb7e8c AK |
1974 | /* |
1975 | * enable stripping of CRC. It's unlikely this will break BMC | |
1976 | * redirection as it did with e1000. Newer features require | |
1977 | * that the HW strips the CRC. | |
73cd78f1 | 1978 | */ |
87cb7e8c | 1979 | rctl |= E1000_RCTL_SECRC; |
9d5c8243 | 1980 | |
9b07f3d3 | 1981 | /* |
ec54d7d6 | 1982 | * disable store bad packets and clear size bits. |
9b07f3d3 | 1983 | */ |
ec54d7d6 | 1984 | rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); |
9d5c8243 | 1985 | |
ec54d7d6 | 1986 | /* enable LPE when to prevent packets larger than max_frame_size */ |
9b07f3d3 | 1987 | rctl |= E1000_RCTL_LPE; |
b4557be2 AD |
1988 | |
1989 | /* Setup buffer sizes */ | |
1990 | switch (adapter->rx_buffer_len) { | |
1991 | case IGB_RXBUFFER_256: | |
1992 | rctl |= E1000_RCTL_SZ_256; | |
1993 | break; | |
1994 | case IGB_RXBUFFER_512: | |
1995 | rctl |= E1000_RCTL_SZ_512; | |
1996 | break; | |
1997 | default: | |
1998 | srrctl = ALIGN(adapter->rx_buffer_len, 1024) | |
1999 | >> E1000_SRRCTL_BSIZEPKT_SHIFT; | |
2000 | break; | |
9d5c8243 AK |
2001 | } |
2002 | ||
2003 | /* 82575 and greater support packet-split where the protocol | |
2004 | * header is placed in skb->data and the packet data is | |
2005 | * placed in pages hanging off of skb_shinfo(skb)->nr_frags. | |
2006 | * In the case of a non-split, skb->data is linearly filled, | |
2007 | * followed by the page buffers. Therefore, skb->data is | |
2008 | * sized to hold the largest protocol header. | |
2009 | */ | |
2010 | /* allocations using alloc_page take too long for regular MTU | |
2011 | * so only enable packet split for jumbo frames */ | |
ec54d7d6 | 2012 | if (adapter->netdev->mtu > ETH_DATA_LEN) { |
9d5c8243 | 2013 | adapter->rx_ps_hdr_size = IGB_RXBUFFER_128; |
bf36c1a0 | 2014 | srrctl |= adapter->rx_ps_hdr_size << |
9d5c8243 | 2015 | E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; |
9d5c8243 AK |
2016 | srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS; |
2017 | } else { | |
2018 | adapter->rx_ps_hdr_size = 0; | |
2019 | srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; | |
2020 | } | |
2021 | ||
e1739522 AD |
2022 | /* Attention!!! For SR-IOV PF driver operations you must enable |
2023 | * queue drop for all VF and PF queues to prevent head of line blocking | |
2024 | * if an un-trusted VF does not provide descriptors to hardware. | |
2025 | */ | |
2026 | if (adapter->vfs_allocated_count) { | |
2027 | u32 vmolr; | |
2028 | ||
2029 | j = adapter->rx_ring[0].reg_idx; | |
2030 | ||
2031 | /* set all queue drop enable bits */ | |
2032 | wr32(E1000_QDE, ALL_QUEUES); | |
2033 | srrctl |= E1000_SRRCTL_DROP_EN; | |
2034 | ||
2035 | /* disable queue 0 to prevent tail write w/o re-config */ | |
2036 | wr32(E1000_RXDCTL(0), 0); | |
2037 | ||
2038 | vmolr = rd32(E1000_VMOLR(j)); | |
2039 | if (rctl & E1000_RCTL_LPE) | |
2040 | vmolr |= E1000_VMOLR_LPE; | |
2041 | if (adapter->num_rx_queues > 0) | |
2042 | vmolr |= E1000_VMOLR_RSSE; | |
2043 | wr32(E1000_VMOLR(j), vmolr); | |
2044 | } | |
2045 | ||
26bc19ec AD |
2046 | for (i = 0; i < adapter->num_rx_queues; i++) { |
2047 | j = adapter->rx_ring[i].reg_idx; | |
2048 | wr32(E1000_SRRCTL(j), srrctl); | |
2049 | } | |
9d5c8243 AK |
2050 | |
2051 | wr32(E1000_RCTL, rctl); | |
2052 | } | |
2053 | ||
e1739522 AD |
2054 | /** |
2055 | * igb_rlpml_set - set maximum receive packet size | |
2056 | * @adapter: board private structure | |
2057 | * | |
2058 | * Configure maximum receivable packet size. | |
2059 | **/ | |
2060 | static void igb_rlpml_set(struct igb_adapter *adapter) | |
2061 | { | |
2062 | u32 max_frame_size = adapter->max_frame_size; | |
2063 | struct e1000_hw *hw = &adapter->hw; | |
2064 | u16 pf_id = adapter->vfs_allocated_count; | |
2065 | ||
2066 | if (adapter->vlgrp) | |
2067 | max_frame_size += VLAN_TAG_SIZE; | |
2068 | ||
2069 | /* if vfs are enabled we set RLPML to the largest possible request | |
2070 | * size and set the VMOLR RLPML to the size we need */ | |
2071 | if (pf_id) { | |
2072 | igb_set_vf_rlpml(adapter, max_frame_size, pf_id); | |
2073 | max_frame_size = MAX_STD_JUMBO_FRAME_SIZE + VLAN_TAG_SIZE; | |
2074 | } | |
2075 | ||
2076 | wr32(E1000_RLPML, max_frame_size); | |
2077 | } | |
2078 | ||
2079 | /** | |
2080 | * igb_configure_vt_default_pool - Configure VT default pool | |
2081 | * @adapter: board private structure | |
2082 | * | |
2083 | * Configure the default pool | |
2084 | **/ | |
2085 | static void igb_configure_vt_default_pool(struct igb_adapter *adapter) | |
2086 | { | |
2087 | struct e1000_hw *hw = &adapter->hw; | |
2088 | u16 pf_id = adapter->vfs_allocated_count; | |
2089 | u32 vtctl; | |
2090 | ||
2091 | /* not in sr-iov mode - do nothing */ | |
2092 | if (!pf_id) | |
2093 | return; | |
2094 | ||
2095 | vtctl = rd32(E1000_VT_CTL); | |
2096 | vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | | |
2097 | E1000_VT_CTL_DISABLE_DEF_POOL); | |
2098 | vtctl |= pf_id << E1000_VT_CTL_DEFAULT_POOL_SHIFT; | |
2099 | wr32(E1000_VT_CTL, vtctl); | |
2100 | } | |
2101 | ||
9d5c8243 AK |
2102 | /** |
2103 | * igb_configure_rx - Configure receive Unit after Reset | |
2104 | * @adapter: board private structure | |
2105 | * | |
2106 | * Configure the Rx unit of the MAC after a reset. | |
2107 | **/ | |
2108 | static void igb_configure_rx(struct igb_adapter *adapter) | |
2109 | { | |
2110 | u64 rdba; | |
2111 | struct e1000_hw *hw = &adapter->hw; | |
2112 | u32 rctl, rxcsum; | |
2113 | u32 rxdctl; | |
9107584e | 2114 | int i; |
9d5c8243 AK |
2115 | |
2116 | /* disable receives while setting up the descriptors */ | |
2117 | rctl = rd32(E1000_RCTL); | |
2118 | wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); | |
2119 | wrfl(); | |
2120 | mdelay(10); | |
2121 | ||
2122 | if (adapter->itr_setting > 3) | |
6eb5a7f1 | 2123 | wr32(E1000_ITR, adapter->itr); |
9d5c8243 AK |
2124 | |
2125 | /* Setup the HW Rx Head and Tail Descriptor Pointers and | |
2126 | * the Base and Length of the Rx Descriptor Ring */ | |
2127 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
73cd78f1 | 2128 | struct igb_ring *ring = &adapter->rx_ring[i]; |
9107584e | 2129 | int j = ring->reg_idx; |
9d5c8243 | 2130 | rdba = ring->dma; |
26bc19ec | 2131 | wr32(E1000_RDBAL(j), |
73cd78f1 | 2132 | rdba & 0x00000000ffffffffULL); |
26bc19ec AD |
2133 | wr32(E1000_RDBAH(j), rdba >> 32); |
2134 | wr32(E1000_RDLEN(j), | |
73cd78f1 | 2135 | ring->count * sizeof(union e1000_adv_rx_desc)); |
9d5c8243 | 2136 | |
26bc19ec AD |
2137 | ring->head = E1000_RDH(j); |
2138 | ring->tail = E1000_RDT(j); | |
9d5c8243 AK |
2139 | writel(0, hw->hw_addr + ring->tail); |
2140 | writel(0, hw->hw_addr + ring->head); | |
2141 | ||
26bc19ec | 2142 | rxdctl = rd32(E1000_RXDCTL(j)); |
9d5c8243 AK |
2143 | rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; |
2144 | rxdctl &= 0xFFF00000; | |
2145 | rxdctl |= IGB_RX_PTHRESH; | |
2146 | rxdctl |= IGB_RX_HTHRESH << 8; | |
2147 | rxdctl |= IGB_RX_WTHRESH << 16; | |
26bc19ec | 2148 | wr32(E1000_RXDCTL(j), rxdctl); |
9d5c8243 AK |
2149 | } |
2150 | ||
2151 | if (adapter->num_rx_queues > 1) { | |
2152 | u32 random[10]; | |
2153 | u32 mrqc; | |
2154 | u32 j, shift; | |
2155 | union e1000_reta { | |
2156 | u32 dword; | |
2157 | u8 bytes[4]; | |
2158 | } reta; | |
2159 | ||
2160 | get_random_bytes(&random[0], 40); | |
2161 | ||
2d064c06 AD |
2162 | if (hw->mac.type >= e1000_82576) |
2163 | shift = 0; | |
2164 | else | |
2165 | shift = 6; | |
9d5c8243 AK |
2166 | for (j = 0; j < (32 * 4); j++) { |
2167 | reta.bytes[j & 3] = | |
26bc19ec | 2168 | adapter->rx_ring[(j % adapter->num_rx_queues)].reg_idx << shift; |
9d5c8243 AK |
2169 | if ((j & 3) == 3) |
2170 | writel(reta.dword, | |
2171 | hw->hw_addr + E1000_RETA(0) + (j & ~3)); | |
2172 | } | |
e1739522 AD |
2173 | if (adapter->vfs_allocated_count) |
2174 | mrqc = E1000_MRQC_ENABLE_VMDQ_RSS_2Q; | |
2175 | else | |
2176 | mrqc = E1000_MRQC_ENABLE_RSS_4Q; | |
9d5c8243 AK |
2177 | |
2178 | /* Fill out hash function seeds */ | |
2179 | for (j = 0; j < 10; j++) | |
2180 | array_wr32(E1000_RSSRK(0), j, random[j]); | |
2181 | ||
2182 | mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | | |
2183 | E1000_MRQC_RSS_FIELD_IPV4_TCP); | |
2184 | mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 | | |
2185 | E1000_MRQC_RSS_FIELD_IPV6_TCP); | |
2186 | mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP | | |
2187 | E1000_MRQC_RSS_FIELD_IPV6_UDP); | |
2188 | mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | | |
2189 | E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); | |
2190 | ||
2191 | ||
2192 | wr32(E1000_MRQC, mrqc); | |
2193 | ||
2194 | /* Multiqueue and raw packet checksumming are mutually | |
2195 | * exclusive. Note that this not the same as TCP/IP | |
2196 | * checksumming, which works fine. */ | |
2197 | rxcsum = rd32(E1000_RXCSUM); | |
2198 | rxcsum |= E1000_RXCSUM_PCSD; | |
2199 | wr32(E1000_RXCSUM, rxcsum); | |
2200 | } else { | |
e1739522 AD |
2201 | /* Enable multi-queue for sr-iov */ |
2202 | if (adapter->vfs_allocated_count) | |
2203 | wr32(E1000_MRQC, E1000_MRQC_ENABLE_VMDQ); | |
9d5c8243 AK |
2204 | /* Enable Receive Checksum Offload for TCP and UDP */ |
2205 | rxcsum = rd32(E1000_RXCSUM); | |
56fbbb4e AD |
2206 | if (adapter->rx_csum) |
2207 | rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPPCSE; | |
2208 | else | |
2209 | rxcsum &= ~(E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPPCSE); | |
2210 | ||
9d5c8243 AK |
2211 | wr32(E1000_RXCSUM, rxcsum); |
2212 | } | |
2213 | ||
e1739522 AD |
2214 | /* Set the default pool for the PF's first queue */ |
2215 | igb_configure_vt_default_pool(adapter); | |
2216 | ||
2217 | igb_rlpml_set(adapter); | |
9d5c8243 AK |
2218 | |
2219 | /* Enable Receives */ | |
2220 | wr32(E1000_RCTL, rctl); | |
2221 | } | |
2222 | ||
2223 | /** | |
2224 | * igb_free_tx_resources - Free Tx Resources per Queue | |
9d5c8243 AK |
2225 | * @tx_ring: Tx descriptor ring for a specific queue |
2226 | * | |
2227 | * Free all transmit software resources | |
2228 | **/ | |
68fd9910 | 2229 | void igb_free_tx_resources(struct igb_ring *tx_ring) |
9d5c8243 | 2230 | { |
3b644cf6 | 2231 | struct pci_dev *pdev = tx_ring->adapter->pdev; |
9d5c8243 | 2232 | |
3b644cf6 | 2233 | igb_clean_tx_ring(tx_ring); |
9d5c8243 AK |
2234 | |
2235 | vfree(tx_ring->buffer_info); | |
2236 | tx_ring->buffer_info = NULL; | |
2237 | ||
2238 | pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma); | |
2239 | ||
2240 | tx_ring->desc = NULL; | |
2241 | } | |
2242 | ||
2243 | /** | |
2244 | * igb_free_all_tx_resources - Free Tx Resources for All Queues | |
2245 | * @adapter: board private structure | |
2246 | * | |
2247 | * Free all transmit software resources | |
2248 | **/ | |
2249 | static void igb_free_all_tx_resources(struct igb_adapter *adapter) | |
2250 | { | |
2251 | int i; | |
2252 | ||
2253 | for (i = 0; i < adapter->num_tx_queues; i++) | |
3b644cf6 | 2254 | igb_free_tx_resources(&adapter->tx_ring[i]); |
9d5c8243 AK |
2255 | } |
2256 | ||
2257 | static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter, | |
2258 | struct igb_buffer *buffer_info) | |
2259 | { | |
2260 | if (buffer_info->dma) { | |
2261 | pci_unmap_page(adapter->pdev, | |
2262 | buffer_info->dma, | |
2263 | buffer_info->length, | |
2264 | PCI_DMA_TODEVICE); | |
2265 | buffer_info->dma = 0; | |
2266 | } | |
2267 | if (buffer_info->skb) { | |
2268 | dev_kfree_skb_any(buffer_info->skb); | |
2269 | buffer_info->skb = NULL; | |
2270 | } | |
2271 | buffer_info->time_stamp = 0; | |
73cd78f1 | 2272 | buffer_info->next_to_watch = 0; |
9d5c8243 AK |
2273 | /* buffer_info must be completely set up in the transmit path */ |
2274 | } | |
2275 | ||
2276 | /** | |
2277 | * igb_clean_tx_ring - Free Tx Buffers | |
9d5c8243 AK |
2278 | * @tx_ring: ring to be cleaned |
2279 | **/ | |
3b644cf6 | 2280 | static void igb_clean_tx_ring(struct igb_ring *tx_ring) |
9d5c8243 | 2281 | { |
3b644cf6 | 2282 | struct igb_adapter *adapter = tx_ring->adapter; |
9d5c8243 AK |
2283 | struct igb_buffer *buffer_info; |
2284 | unsigned long size; | |
2285 | unsigned int i; | |
2286 | ||
2287 | if (!tx_ring->buffer_info) | |
2288 | return; | |
2289 | /* Free all the Tx ring sk_buffs */ | |
2290 | ||
2291 | for (i = 0; i < tx_ring->count; i++) { | |
2292 | buffer_info = &tx_ring->buffer_info[i]; | |
2293 | igb_unmap_and_free_tx_resource(adapter, buffer_info); | |
2294 | } | |
2295 | ||
2296 | size = sizeof(struct igb_buffer) * tx_ring->count; | |
2297 | memset(tx_ring->buffer_info, 0, size); | |
2298 | ||
2299 | /* Zero out the descriptor ring */ | |
2300 | ||
2301 | memset(tx_ring->desc, 0, tx_ring->size); | |
2302 | ||
2303 | tx_ring->next_to_use = 0; | |
2304 | tx_ring->next_to_clean = 0; | |
2305 | ||
2306 | writel(0, adapter->hw.hw_addr + tx_ring->head); | |
2307 | writel(0, adapter->hw.hw_addr + tx_ring->tail); | |
2308 | } | |
2309 | ||
2310 | /** | |
2311 | * igb_clean_all_tx_rings - Free Tx Buffers for all queues | |
2312 | * @adapter: board private structure | |
2313 | **/ | |
2314 | static void igb_clean_all_tx_rings(struct igb_adapter *adapter) | |
2315 | { | |
2316 | int i; | |
2317 | ||
2318 | for (i = 0; i < adapter->num_tx_queues; i++) | |
3b644cf6 | 2319 | igb_clean_tx_ring(&adapter->tx_ring[i]); |
9d5c8243 AK |
2320 | } |
2321 | ||
2322 | /** | |
2323 | * igb_free_rx_resources - Free Rx Resources | |
9d5c8243 AK |
2324 | * @rx_ring: ring to clean the resources from |
2325 | * | |
2326 | * Free all receive software resources | |
2327 | **/ | |
68fd9910 | 2328 | void igb_free_rx_resources(struct igb_ring *rx_ring) |
9d5c8243 | 2329 | { |
3b644cf6 | 2330 | struct pci_dev *pdev = rx_ring->adapter->pdev; |
9d5c8243 | 2331 | |
3b644cf6 | 2332 | igb_clean_rx_ring(rx_ring); |
9d5c8243 AK |
2333 | |
2334 | vfree(rx_ring->buffer_info); | |
2335 | rx_ring->buffer_info = NULL; | |
2336 | ||
2337 | pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma); | |
2338 | ||
2339 | rx_ring->desc = NULL; | |
2340 | } | |
2341 | ||
2342 | /** | |
2343 | * igb_free_all_rx_resources - Free Rx Resources for All Queues | |
2344 | * @adapter: board private structure | |
2345 | * | |
2346 | * Free all receive software resources | |
2347 | **/ | |
2348 | static void igb_free_all_rx_resources(struct igb_adapter *adapter) | |
2349 | { | |
2350 | int i; | |
2351 | ||
2352 | for (i = 0; i < adapter->num_rx_queues; i++) | |
3b644cf6 | 2353 | igb_free_rx_resources(&adapter->rx_ring[i]); |
9d5c8243 AK |
2354 | } |
2355 | ||
2356 | /** | |
2357 | * igb_clean_rx_ring - Free Rx Buffers per Queue | |
9d5c8243 AK |
2358 | * @rx_ring: ring to free buffers from |
2359 | **/ | |
3b644cf6 | 2360 | static void igb_clean_rx_ring(struct igb_ring *rx_ring) |
9d5c8243 | 2361 | { |
3b644cf6 | 2362 | struct igb_adapter *adapter = rx_ring->adapter; |
9d5c8243 AK |
2363 | struct igb_buffer *buffer_info; |
2364 | struct pci_dev *pdev = adapter->pdev; | |
2365 | unsigned long size; | |
2366 | unsigned int i; | |
2367 | ||
2368 | if (!rx_ring->buffer_info) | |
2369 | return; | |
2370 | /* Free all the Rx ring sk_buffs */ | |
2371 | for (i = 0; i < rx_ring->count; i++) { | |
2372 | buffer_info = &rx_ring->buffer_info[i]; | |
2373 | if (buffer_info->dma) { | |
2374 | if (adapter->rx_ps_hdr_size) | |
2375 | pci_unmap_single(pdev, buffer_info->dma, | |
2376 | adapter->rx_ps_hdr_size, | |
2377 | PCI_DMA_FROMDEVICE); | |
2378 | else | |
2379 | pci_unmap_single(pdev, buffer_info->dma, | |
2380 | adapter->rx_buffer_len, | |
2381 | PCI_DMA_FROMDEVICE); | |
2382 | buffer_info->dma = 0; | |
2383 | } | |
2384 | ||
2385 | if (buffer_info->skb) { | |
2386 | dev_kfree_skb(buffer_info->skb); | |
2387 | buffer_info->skb = NULL; | |
2388 | } | |
2389 | if (buffer_info->page) { | |
bf36c1a0 AD |
2390 | if (buffer_info->page_dma) |
2391 | pci_unmap_page(pdev, buffer_info->page_dma, | |
2392 | PAGE_SIZE / 2, | |
2393 | PCI_DMA_FROMDEVICE); | |
9d5c8243 AK |
2394 | put_page(buffer_info->page); |
2395 | buffer_info->page = NULL; | |
2396 | buffer_info->page_dma = 0; | |
bf36c1a0 | 2397 | buffer_info->page_offset = 0; |
9d5c8243 AK |
2398 | } |
2399 | } | |
2400 | ||
9d5c8243 AK |
2401 | size = sizeof(struct igb_buffer) * rx_ring->count; |
2402 | memset(rx_ring->buffer_info, 0, size); | |
2403 | ||
2404 | /* Zero out the descriptor ring */ | |
2405 | memset(rx_ring->desc, 0, rx_ring->size); | |
2406 | ||
2407 | rx_ring->next_to_clean = 0; | |
2408 | rx_ring->next_to_use = 0; | |
2409 | ||
2410 | writel(0, adapter->hw.hw_addr + rx_ring->head); | |
2411 | writel(0, adapter->hw.hw_addr + rx_ring->tail); | |
2412 | } | |
2413 | ||
2414 | /** | |
2415 | * igb_clean_all_rx_rings - Free Rx Buffers for all queues | |
2416 | * @adapter: board private structure | |
2417 | **/ | |
2418 | static void igb_clean_all_rx_rings(struct igb_adapter *adapter) | |
2419 | { | |
2420 | int i; | |
2421 | ||
2422 | for (i = 0; i < adapter->num_rx_queues; i++) | |
3b644cf6 | 2423 | igb_clean_rx_ring(&adapter->rx_ring[i]); |
9d5c8243 AK |
2424 | } |
2425 | ||
2426 | /** | |
2427 | * igb_set_mac - Change the Ethernet Address of the NIC | |
2428 | * @netdev: network interface device structure | |
2429 | * @p: pointer to an address structure | |
2430 | * | |
2431 | * Returns 0 on success, negative on failure | |
2432 | **/ | |
2433 | static int igb_set_mac(struct net_device *netdev, void *p) | |
2434 | { | |
2435 | struct igb_adapter *adapter = netdev_priv(netdev); | |
28b0759c | 2436 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 AK |
2437 | struct sockaddr *addr = p; |
2438 | ||
2439 | if (!is_valid_ether_addr(addr->sa_data)) | |
2440 | return -EADDRNOTAVAIL; | |
2441 | ||
2442 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | |
28b0759c | 2443 | memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); |
9d5c8243 | 2444 | |
28b0759c | 2445 | hw->mac.ops.rar_set(hw, hw->mac.addr, 0); |
9d5c8243 | 2446 | |
e1739522 AD |
2447 | igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0); |
2448 | ||
9d5c8243 AK |
2449 | return 0; |
2450 | } | |
2451 | ||
2452 | /** | |
2453 | * igb_set_multi - Multicast and Promiscuous mode set | |
2454 | * @netdev: network interface device structure | |
2455 | * | |
2456 | * The set_multi entry point is called whenever the multicast address | |
2457 | * list or the network interface flags are updated. This routine is | |
2458 | * responsible for configuring the hardware for proper multicast, | |
2459 | * promiscuous mode, and all-multi behavior. | |
2460 | **/ | |
2461 | static void igb_set_multi(struct net_device *netdev) | |
2462 | { | |
2463 | struct igb_adapter *adapter = netdev_priv(netdev); | |
2464 | struct e1000_hw *hw = &adapter->hw; | |
2465 | struct e1000_mac_info *mac = &hw->mac; | |
2466 | struct dev_mc_list *mc_ptr; | |
c5cd11e3 | 2467 | u8 *mta_list = NULL; |
9d5c8243 AK |
2468 | u32 rctl; |
2469 | int i; | |
2470 | ||
2471 | /* Check for Promiscuous and All Multicast modes */ | |
2472 | ||
2473 | rctl = rd32(E1000_RCTL); | |
2474 | ||
746b9f02 | 2475 | if (netdev->flags & IFF_PROMISC) { |
9d5c8243 | 2476 | rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); |
746b9f02 PM |
2477 | rctl &= ~E1000_RCTL_VFE; |
2478 | } else { | |
2479 | if (netdev->flags & IFF_ALLMULTI) { | |
2480 | rctl |= E1000_RCTL_MPE; | |
2481 | rctl &= ~E1000_RCTL_UPE; | |
2482 | } else | |
2483 | rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE); | |
78ed11a5 | 2484 | rctl |= E1000_RCTL_VFE; |
746b9f02 | 2485 | } |
9d5c8243 AK |
2486 | wr32(E1000_RCTL, rctl); |
2487 | ||
c5cd11e3 AD |
2488 | if (netdev->mc_count) { |
2489 | mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC); | |
2490 | if (!mta_list) { | |
2491 | dev_err(&adapter->pdev->dev, | |
2492 | "failed to allocate multicast filter list\n"); | |
2493 | return; | |
2494 | } | |
9d5c8243 AK |
2495 | } |
2496 | ||
9d5c8243 AK |
2497 | /* The shared function expects a packed array of only addresses. */ |
2498 | mc_ptr = netdev->mc_list; | |
2499 | ||
2500 | for (i = 0; i < netdev->mc_count; i++) { | |
2501 | if (!mc_ptr) | |
2502 | break; | |
2503 | memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN); | |
2504 | mc_ptr = mc_ptr->next; | |
2505 | } | |
e1739522 AD |
2506 | igb_update_mc_addr_list(hw, mta_list, i, |
2507 | adapter->vfs_allocated_count + 1, | |
2508 | mac->rar_entry_count); | |
2509 | ||
2510 | igb_set_mc_list_pools(adapter, i, mac->rar_entry_count); | |
4ae196df AD |
2511 | igb_restore_vf_multicasts(adapter); |
2512 | ||
9d5c8243 AK |
2513 | kfree(mta_list); |
2514 | } | |
2515 | ||
2516 | /* Need to wait a few seconds after link up to get diagnostic information from | |
2517 | * the phy */ | |
2518 | static void igb_update_phy_info(unsigned long data) | |
2519 | { | |
2520 | struct igb_adapter *adapter = (struct igb_adapter *) data; | |
f5f4cf08 | 2521 | igb_get_phy_info(&adapter->hw); |
9d5c8243 AK |
2522 | } |
2523 | ||
4d6b725e AD |
2524 | /** |
2525 | * igb_has_link - check shared code for link and determine up/down | |
2526 | * @adapter: pointer to driver private info | |
2527 | **/ | |
2528 | static bool igb_has_link(struct igb_adapter *adapter) | |
2529 | { | |
2530 | struct e1000_hw *hw = &adapter->hw; | |
2531 | bool link_active = false; | |
2532 | s32 ret_val = 0; | |
2533 | ||
2534 | /* get_link_status is set on LSC (link status) interrupt or | |
2535 | * rx sequence error interrupt. get_link_status will stay | |
2536 | * false until the e1000_check_for_link establishes link | |
2537 | * for copper adapters ONLY | |
2538 | */ | |
2539 | switch (hw->phy.media_type) { | |
2540 | case e1000_media_type_copper: | |
2541 | if (hw->mac.get_link_status) { | |
2542 | ret_val = hw->mac.ops.check_for_link(hw); | |
2543 | link_active = !hw->mac.get_link_status; | |
2544 | } else { | |
2545 | link_active = true; | |
2546 | } | |
2547 | break; | |
2548 | case e1000_media_type_fiber: | |
2549 | ret_val = hw->mac.ops.check_for_link(hw); | |
2550 | link_active = !!(rd32(E1000_STATUS) & E1000_STATUS_LU); | |
2551 | break; | |
2552 | case e1000_media_type_internal_serdes: | |
2553 | ret_val = hw->mac.ops.check_for_link(hw); | |
2554 | link_active = hw->mac.serdes_has_link; | |
2555 | break; | |
2556 | default: | |
2557 | case e1000_media_type_unknown: | |
2558 | break; | |
2559 | } | |
2560 | ||
2561 | return link_active; | |
2562 | } | |
2563 | ||
9d5c8243 AK |
2564 | /** |
2565 | * igb_watchdog - Timer Call-back | |
2566 | * @data: pointer to adapter cast into an unsigned long | |
2567 | **/ | |
2568 | static void igb_watchdog(unsigned long data) | |
2569 | { | |
2570 | struct igb_adapter *adapter = (struct igb_adapter *)data; | |
2571 | /* Do the rest outside of interrupt context */ | |
2572 | schedule_work(&adapter->watchdog_task); | |
2573 | } | |
2574 | ||
2575 | static void igb_watchdog_task(struct work_struct *work) | |
2576 | { | |
2577 | struct igb_adapter *adapter = container_of(work, | |
2578 | struct igb_adapter, watchdog_task); | |
2579 | struct e1000_hw *hw = &adapter->hw; | |
9d5c8243 AK |
2580 | struct net_device *netdev = adapter->netdev; |
2581 | struct igb_ring *tx_ring = adapter->tx_ring; | |
9d5c8243 | 2582 | u32 link; |
7a6ea550 | 2583 | u32 eics = 0; |
7a6ea550 | 2584 | int i; |
9d5c8243 | 2585 | |
4d6b725e AD |
2586 | link = igb_has_link(adapter); |
2587 | if ((netif_carrier_ok(netdev)) && link) | |
9d5c8243 AK |
2588 | goto link_up; |
2589 | ||
9d5c8243 AK |
2590 | if (link) { |
2591 | if (!netif_carrier_ok(netdev)) { | |
2592 | u32 ctrl; | |
2593 | hw->mac.ops.get_speed_and_duplex(&adapter->hw, | |
2594 | &adapter->link_speed, | |
2595 | &adapter->link_duplex); | |
2596 | ||
2597 | ctrl = rd32(E1000_CTRL); | |
527d47c1 AD |
2598 | /* Links status message must follow this format */ |
2599 | printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, " | |
9d5c8243 | 2600 | "Flow Control: %s\n", |
527d47c1 | 2601 | netdev->name, |
9d5c8243 AK |
2602 | adapter->link_speed, |
2603 | adapter->link_duplex == FULL_DUPLEX ? | |
2604 | "Full Duplex" : "Half Duplex", | |
2605 | ((ctrl & E1000_CTRL_TFCE) && (ctrl & | |
2606 | E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl & | |
2607 | E1000_CTRL_RFCE) ? "RX" : ((ctrl & | |
2608 | E1000_CTRL_TFCE) ? "TX" : "None"))); | |
2609 | ||
2610 | /* tweak tx_queue_len according to speed/duplex and | |
2611 | * adjust the timeout factor */ | |
2612 | netdev->tx_queue_len = adapter->tx_queue_len; | |
2613 | adapter->tx_timeout_factor = 1; | |
2614 | switch (adapter->link_speed) { | |
2615 | case SPEED_10: | |
2616 | netdev->tx_queue_len = 10; | |
2617 | adapter->tx_timeout_factor = 14; | |
2618 | break; | |
2619 | case SPEED_100: | |
2620 | netdev->tx_queue_len = 100; | |
2621 | /* maybe add some timeout factor ? */ | |
2622 | break; | |
2623 | } | |
2624 | ||
2625 | netif_carrier_on(netdev); | |
fd2ea0a7 | 2626 | netif_tx_wake_all_queues(netdev); |
9d5c8243 | 2627 | |
4ae196df AD |
2628 | igb_ping_all_vfs(adapter); |
2629 | ||
4b1a9877 | 2630 | /* link state has changed, schedule phy info update */ |
9d5c8243 AK |
2631 | if (!test_bit(__IGB_DOWN, &adapter->state)) |
2632 | mod_timer(&adapter->phy_info_timer, | |
2633 | round_jiffies(jiffies + 2 * HZ)); | |
2634 | } | |
2635 | } else { | |
2636 | if (netif_carrier_ok(netdev)) { | |
2637 | adapter->link_speed = 0; | |
2638 | adapter->link_duplex = 0; | |
527d47c1 AD |
2639 | /* Links status message must follow this format */ |
2640 | printk(KERN_INFO "igb: %s NIC Link is Down\n", | |
2641 | netdev->name); | |
9d5c8243 | 2642 | netif_carrier_off(netdev); |
fd2ea0a7 | 2643 | netif_tx_stop_all_queues(netdev); |
4b1a9877 | 2644 | |
4ae196df AD |
2645 | igb_ping_all_vfs(adapter); |
2646 | ||
4b1a9877 | 2647 | /* link state has changed, schedule phy info update */ |
9d5c8243 AK |
2648 | if (!test_bit(__IGB_DOWN, &adapter->state)) |
2649 | mod_timer(&adapter->phy_info_timer, | |
2650 | round_jiffies(jiffies + 2 * HZ)); | |
2651 | } | |
2652 | } | |
2653 | ||
2654 | link_up: | |
2655 | igb_update_stats(adapter); | |
2656 | ||
4b1a9877 | 2657 | hw->mac.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old; |
9d5c8243 | 2658 | adapter->tpt_old = adapter->stats.tpt; |
4b1a9877 | 2659 | hw->mac.collision_delta = adapter->stats.colc - adapter->colc_old; |
9d5c8243 AK |
2660 | adapter->colc_old = adapter->stats.colc; |
2661 | ||
2662 | adapter->gorc = adapter->stats.gorc - adapter->gorc_old; | |
2663 | adapter->gorc_old = adapter->stats.gorc; | |
2664 | adapter->gotc = adapter->stats.gotc - adapter->gotc_old; | |
2665 | adapter->gotc_old = adapter->stats.gotc; | |
2666 | ||
2667 | igb_update_adaptive(&adapter->hw); | |
2668 | ||
2669 | if (!netif_carrier_ok(netdev)) { | |
c493ea45 | 2670 | if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { |
9d5c8243 AK |
2671 | /* We've lost link, so the controller stops DMA, |
2672 | * but we've got queued Tx work that's never going | |
2673 | * to get done, so reset controller to flush Tx. | |
2674 | * (Do the reset outside of interrupt context). */ | |
2675 | adapter->tx_timeout_count++; | |
2676 | schedule_work(&adapter->reset_task); | |
2677 | } | |
2678 | } | |
2679 | ||
2680 | /* Cause software interrupt to ensure rx ring is cleaned */ | |
7a6ea550 AD |
2681 | if (adapter->msix_entries) { |
2682 | for (i = 0; i < adapter->num_rx_queues; i++) | |
2683 | eics |= adapter->rx_ring[i].eims_value; | |
2684 | wr32(E1000_EICS, eics); | |
2685 | } else { | |
2686 | wr32(E1000_ICS, E1000_ICS_RXDMT0); | |
2687 | } | |
9d5c8243 AK |
2688 | |
2689 | /* Force detection of hung controller every watchdog period */ | |
2690 | tx_ring->detect_tx_hung = true; | |
2691 | ||
2692 | /* Reset the timer */ | |
2693 | if (!test_bit(__IGB_DOWN, &adapter->state)) | |
2694 | mod_timer(&adapter->watchdog_timer, | |
2695 | round_jiffies(jiffies + 2 * HZ)); | |
2696 | } | |
2697 | ||
2698 | enum latency_range { | |
2699 | lowest_latency = 0, | |
2700 | low_latency = 1, | |
2701 | bulk_latency = 2, | |
2702 | latency_invalid = 255 | |
2703 | }; | |
2704 | ||
2705 | ||
6eb5a7f1 AD |
2706 | /** |
2707 | * igb_update_ring_itr - update the dynamic ITR value based on packet size | |
2708 | * | |
2709 | * Stores a new ITR value based on strictly on packet size. This | |
2710 | * algorithm is less sophisticated than that used in igb_update_itr, | |
2711 | * due to the difficulty of synchronizing statistics across multiple | |
2712 | * receive rings. The divisors and thresholds used by this fuction | |
2713 | * were determined based on theoretical maximum wire speed and testing | |
2714 | * data, in order to minimize response time while increasing bulk | |
2715 | * throughput. | |
2716 | * This functionality is controlled by the InterruptThrottleRate module | |
2717 | * parameter (see igb_param.c) | |
2718 | * NOTE: This function is called only when operating in a multiqueue | |
2719 | * receive environment. | |
2720 | * @rx_ring: pointer to ring | |
2721 | **/ | |
2722 | static void igb_update_ring_itr(struct igb_ring *rx_ring) | |
9d5c8243 | 2723 | { |
6eb5a7f1 AD |
2724 | int new_val = rx_ring->itr_val; |
2725 | int avg_wire_size = 0; | |
2726 | struct igb_adapter *adapter = rx_ring->adapter; | |
9d5c8243 | 2727 | |
6eb5a7f1 AD |
2728 | if (!rx_ring->total_packets) |
2729 | goto clear_counts; /* no packets, so don't do anything */ | |
9d5c8243 | 2730 | |
6eb5a7f1 AD |
2731 | /* For non-gigabit speeds, just fix the interrupt rate at 4000 |
2732 | * ints/sec - ITR timer value of 120 ticks. | |
2733 | */ | |
2734 | if (adapter->link_speed != SPEED_1000) { | |
2735 | new_val = 120; | |
2736 | goto set_itr_val; | |
9d5c8243 | 2737 | } |
6eb5a7f1 | 2738 | avg_wire_size = rx_ring->total_bytes / rx_ring->total_packets; |
9d5c8243 | 2739 | |
6eb5a7f1 AD |
2740 | /* Add 24 bytes to size to account for CRC, preamble, and gap */ |
2741 | avg_wire_size += 24; | |
2742 | ||
2743 | /* Don't starve jumbo frames */ | |
2744 | avg_wire_size = min(avg_wire_size, 3000); | |
9d5c8243 | 2745 | |
6eb5a7f1 AD |
2746 | /* Give a little boost to mid-size frames */ |
2747 | if ((avg_wire_size > 300) && (avg_wire_size < 1200)) | |
2748 | new_val = avg_wire_size / 3; | |
2749 | else | |
2750 | new_val = avg_wire_size / 2; | |
9d5c8243 | 2751 | |
6eb5a7f1 | 2752 | set_itr_val: |
9d5c8243 AK |
2753 | if (new_val != rx_ring->itr_val) { |
2754 | rx_ring->itr_val = new_val; | |
6eb5a7f1 | 2755 | rx_ring->set_itr = 1; |
9d5c8243 | 2756 | } |
6eb5a7f1 AD |
2757 | clear_counts: |
2758 | rx_ring->total_bytes = 0; | |
2759 | rx_ring->total_packets = 0; | |
9d5c8243 AK |
2760 | } |
2761 | ||
2762 | /** | |
2763 | * igb_update_itr - update the dynamic ITR value based on statistics | |
2764 | * Stores a new ITR value based on packets and byte | |
2765 | * counts during the last interrupt. The advantage of per interrupt | |
2766 | * computation is faster updates and more accurate ITR for the current | |
2767 | * traffic pattern. Constants in this function were computed | |
2768 | * based on theoretical maximum wire speed and thresholds were set based | |
2769 | * on testing data as well as attempting to minimize response time | |
2770 | * while increasing bulk throughput. | |
2771 | * this functionality is controlled by the InterruptThrottleRate module | |
2772 | * parameter (see igb_param.c) | |
2773 | * NOTE: These calculations are only valid when operating in a single- | |
2774 | * queue environment. | |
2775 | * @adapter: pointer to adapter | |
2776 | * @itr_setting: current adapter->itr | |
2777 | * @packets: the number of packets during this measurement interval | |
2778 | * @bytes: the number of bytes during this measurement interval | |
2779 | **/ | |
2780 | static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting, | |
2781 | int packets, int bytes) | |
2782 | { | |
2783 | unsigned int retval = itr_setting; | |
2784 | ||
2785 | if (packets == 0) | |
2786 | goto update_itr_done; | |
2787 | ||
2788 | switch (itr_setting) { | |
2789 | case lowest_latency: | |
2790 | /* handle TSO and jumbo frames */ | |
2791 | if (bytes/packets > 8000) | |
2792 | retval = bulk_latency; | |
2793 | else if ((packets < 5) && (bytes > 512)) | |
2794 | retval = low_latency; | |
2795 | break; | |
2796 | case low_latency: /* 50 usec aka 20000 ints/s */ | |
2797 | if (bytes > 10000) { | |
2798 | /* this if handles the TSO accounting */ | |
2799 | if (bytes/packets > 8000) { | |
2800 | retval = bulk_latency; | |
2801 | } else if ((packets < 10) || ((bytes/packets) > 1200)) { | |
2802 | retval = bulk_latency; | |
2803 | } else if ((packets > 35)) { | |
2804 | retval = lowest_latency; | |
2805 | } | |
2806 | } else if (bytes/packets > 2000) { | |
2807 | retval = bulk_latency; | |
2808 | } else if (packets <= 2 && bytes < 512) { | |
2809 | retval = lowest_latency; | |
2810 | } | |
2811 | break; | |
2812 | case bulk_latency: /* 250 usec aka 4000 ints/s */ | |
2813 | if (bytes > 25000) { | |
2814 | if (packets > 35) | |
2815 | retval = low_latency; | |
1e5c3d21 | 2816 | } else if (bytes < 1500) { |
9d5c8243 AK |
2817 | retval = low_latency; |
2818 | } | |
2819 | break; | |
2820 | } | |
2821 | ||
2822 | update_itr_done: | |
2823 | return retval; | |
2824 | } | |
2825 | ||
6eb5a7f1 | 2826 | static void igb_set_itr(struct igb_adapter *adapter) |
9d5c8243 AK |
2827 | { |
2828 | u16 current_itr; | |
2829 | u32 new_itr = adapter->itr; | |
2830 | ||
2831 | /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ | |
2832 | if (adapter->link_speed != SPEED_1000) { | |
2833 | current_itr = 0; | |
2834 | new_itr = 4000; | |
2835 | goto set_itr_now; | |
2836 | } | |
2837 | ||
2838 | adapter->rx_itr = igb_update_itr(adapter, | |
2839 | adapter->rx_itr, | |
2840 | adapter->rx_ring->total_packets, | |
2841 | adapter->rx_ring->total_bytes); | |
9d5c8243 | 2842 | |
6eb5a7f1 | 2843 | if (adapter->rx_ring->buddy) { |
9d5c8243 AK |
2844 | adapter->tx_itr = igb_update_itr(adapter, |
2845 | adapter->tx_itr, | |
2846 | adapter->tx_ring->total_packets, | |
2847 | adapter->tx_ring->total_bytes); | |
9d5c8243 AK |
2848 | current_itr = max(adapter->rx_itr, adapter->tx_itr); |
2849 | } else { | |
2850 | current_itr = adapter->rx_itr; | |
2851 | } | |
2852 | ||
6eb5a7f1 | 2853 | /* conservative mode (itr 3) eliminates the lowest_latency setting */ |
73cd78f1 | 2854 | if (adapter->itr_setting == 3 && current_itr == lowest_latency) |
6eb5a7f1 AD |
2855 | current_itr = low_latency; |
2856 | ||
9d5c8243 AK |
2857 | switch (current_itr) { |
2858 | /* counts and packets in update_itr are dependent on these numbers */ | |
2859 | case lowest_latency: | |
2860 | new_itr = 70000; | |
2861 | break; | |
2862 | case low_latency: | |
2863 | new_itr = 20000; /* aka hwitr = ~200 */ | |
2864 | break; | |
2865 | case bulk_latency: | |
2866 | new_itr = 4000; | |
2867 | break; | |
2868 | default: | |
2869 | break; | |
2870 | } | |
2871 | ||
2872 | set_itr_now: | |
6eb5a7f1 AD |
2873 | adapter->rx_ring->total_bytes = 0; |
2874 | adapter->rx_ring->total_packets = 0; | |
2875 | if (adapter->rx_ring->buddy) { | |
2876 | adapter->rx_ring->buddy->total_bytes = 0; | |
2877 | adapter->rx_ring->buddy->total_packets = 0; | |
2878 | } | |
2879 | ||
9d5c8243 AK |
2880 | if (new_itr != adapter->itr) { |
2881 | /* this attempts to bias the interrupt rate towards Bulk | |
2882 | * by adding intermediate steps when interrupt rate is | |
2883 | * increasing */ | |
2884 | new_itr = new_itr > adapter->itr ? | |
2885 | min(adapter->itr + (new_itr >> 2), new_itr) : | |
2886 | new_itr; | |
2887 | /* Don't write the value here; it resets the adapter's | |
2888 | * internal timer, and causes us to delay far longer than | |
2889 | * we should between interrupts. Instead, we write the ITR | |
2890 | * value at the beginning of the next interrupt so the timing | |
2891 | * ends up being correct. | |
2892 | */ | |
2893 | adapter->itr = new_itr; | |
6eb5a7f1 AD |
2894 | adapter->rx_ring->itr_val = 1000000000 / (new_itr * 256); |
2895 | adapter->rx_ring->set_itr = 1; | |
9d5c8243 AK |
2896 | } |
2897 | ||
2898 | return; | |
2899 | } | |
2900 | ||
2901 | ||
2902 | #define IGB_TX_FLAGS_CSUM 0x00000001 | |
2903 | #define IGB_TX_FLAGS_VLAN 0x00000002 | |
2904 | #define IGB_TX_FLAGS_TSO 0x00000004 | |
2905 | #define IGB_TX_FLAGS_IPV4 0x00000008 | |
33af6bcc | 2906 | #define IGB_TX_FLAGS_TSTAMP 0x00000010 |
9d5c8243 AK |
2907 | #define IGB_TX_FLAGS_VLAN_MASK 0xffff0000 |
2908 | #define IGB_TX_FLAGS_VLAN_SHIFT 16 | |
2909 | ||
2910 | static inline int igb_tso_adv(struct igb_adapter *adapter, | |
2911 | struct igb_ring *tx_ring, | |
2912 | struct sk_buff *skb, u32 tx_flags, u8 *hdr_len) | |
2913 | { | |
2914 | struct e1000_adv_tx_context_desc *context_desc; | |
2915 | unsigned int i; | |
2916 | int err; | |
2917 | struct igb_buffer *buffer_info; | |
2918 | u32 info = 0, tu_cmd = 0; | |
2919 | u32 mss_l4len_idx, l4len; | |
2920 | *hdr_len = 0; | |
2921 | ||
2922 | if (skb_header_cloned(skb)) { | |
2923 | err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); | |
2924 | if (err) | |
2925 | return err; | |
2926 | } | |
2927 | ||
2928 | l4len = tcp_hdrlen(skb); | |
2929 | *hdr_len += l4len; | |
2930 | ||
2931 | if (skb->protocol == htons(ETH_P_IP)) { | |
2932 | struct iphdr *iph = ip_hdr(skb); | |
2933 | iph->tot_len = 0; | |
2934 | iph->check = 0; | |
2935 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, | |
2936 | iph->daddr, 0, | |
2937 | IPPROTO_TCP, | |
2938 | 0); | |
2939 | } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) { | |
2940 | ipv6_hdr(skb)->payload_len = 0; | |
2941 | tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, | |
2942 | &ipv6_hdr(skb)->daddr, | |
2943 | 0, IPPROTO_TCP, 0); | |
2944 | } | |
2945 | ||
2946 | i = tx_ring->next_to_use; | |
2947 | ||
2948 | buffer_info = &tx_ring->buffer_info[i]; | |
2949 | context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i); | |
2950 | /* VLAN MACLEN IPLEN */ | |
2951 | if (tx_flags & IGB_TX_FLAGS_VLAN) | |
2952 | info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK); | |
2953 | info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT); | |
2954 | *hdr_len += skb_network_offset(skb); | |
2955 | info |= skb_network_header_len(skb); | |
2956 | *hdr_len += skb_network_header_len(skb); | |
2957 | context_desc->vlan_macip_lens = cpu_to_le32(info); | |
2958 | ||
2959 | /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ | |
2960 | tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT); | |
2961 | ||
2962 | if (skb->protocol == htons(ETH_P_IP)) | |
2963 | tu_cmd |= E1000_ADVTXD_TUCMD_IPV4; | |
2964 | tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP; | |
2965 | ||
2966 | context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd); | |
2967 | ||
2968 | /* MSS L4LEN IDX */ | |
2969 | mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT); | |
2970 | mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT); | |
2971 | ||
73cd78f1 | 2972 | /* For 82575, context index must be unique per ring. */ |
7dfc16fa AD |
2973 | if (adapter->flags & IGB_FLAG_NEED_CTX_IDX) |
2974 | mss_l4len_idx |= tx_ring->queue_index << 4; | |
9d5c8243 AK |
2975 | |
2976 | context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); | |
2977 | context_desc->seqnum_seed = 0; | |
2978 | ||
2979 | buffer_info->time_stamp = jiffies; | |
0e014cb1 | 2980 | buffer_info->next_to_watch = i; |
9d5c8243 AK |
2981 | buffer_info->dma = 0; |
2982 | i++; | |
2983 | if (i == tx_ring->count) | |
2984 | i = 0; | |
2985 | ||
2986 | tx_ring->next_to_use = i; | |
2987 | ||
2988 | return true; | |
2989 | } | |
2990 | ||
2991 | static inline bool igb_tx_csum_adv(struct igb_adapter *adapter, | |
2992 | struct igb_ring *tx_ring, | |
2993 | struct sk_buff *skb, u32 tx_flags) | |
2994 | { | |
2995 | struct e1000_adv_tx_context_desc *context_desc; | |
2996 | unsigned int i; | |
2997 | struct igb_buffer *buffer_info; | |
2998 | u32 info = 0, tu_cmd = 0; | |
2999 | ||
3000 | if ((skb->ip_summed == CHECKSUM_PARTIAL) || | |
3001 | (tx_flags & IGB_TX_FLAGS_VLAN)) { | |
3002 | i = tx_ring->next_to_use; | |
3003 | buffer_info = &tx_ring->buffer_info[i]; | |
3004 | context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i); | |
3005 | ||
3006 | if (tx_flags & IGB_TX_FLAGS_VLAN) | |
3007 | info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK); | |
3008 | info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT); | |
3009 | if (skb->ip_summed == CHECKSUM_PARTIAL) | |
3010 | info |= skb_network_header_len(skb); | |
3011 | ||
3012 | context_desc->vlan_macip_lens = cpu_to_le32(info); | |
3013 | ||
3014 | tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT); | |
3015 | ||
3016 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
fa4a7ef3 AJ |
3017 | __be16 protocol; |
3018 | ||
3019 | if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) { | |
3020 | const struct vlan_ethhdr *vhdr = | |
3021 | (const struct vlan_ethhdr*)skb->data; | |
3022 | ||
3023 | protocol = vhdr->h_vlan_encapsulated_proto; | |
3024 | } else { | |
3025 | protocol = skb->protocol; | |
3026 | } | |
3027 | ||
3028 | switch (protocol) { | |
09640e63 | 3029 | case cpu_to_be16(ETH_P_IP): |
9d5c8243 | 3030 | tu_cmd |= E1000_ADVTXD_TUCMD_IPV4; |
44b0cda3 MW |
3031 | if (ip_hdr(skb)->protocol == IPPROTO_TCP) |
3032 | tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP; | |
3033 | break; | |
09640e63 | 3034 | case cpu_to_be16(ETH_P_IPV6): |
44b0cda3 MW |
3035 | /* XXX what about other V6 headers?? */ |
3036 | if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP) | |
3037 | tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP; | |
3038 | break; | |
3039 | default: | |
3040 | if (unlikely(net_ratelimit())) | |
3041 | dev_warn(&adapter->pdev->dev, | |
3042 | "partial checksum but proto=%x!\n", | |
3043 | skb->protocol); | |
3044 | break; | |
3045 | } | |
9d5c8243 AK |
3046 | } |
3047 | ||
3048 | context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd); | |
3049 | context_desc->seqnum_seed = 0; | |
7dfc16fa AD |
3050 | if (adapter->flags & IGB_FLAG_NEED_CTX_IDX) |
3051 | context_desc->mss_l4len_idx = | |
3052 | cpu_to_le32(tx_ring->queue_index << 4); | |
265de409 AD |
3053 | else |
3054 | context_desc->mss_l4len_idx = 0; | |
9d5c8243 AK |
3055 | |
3056 | buffer_info->time_stamp = jiffies; | |
0e014cb1 | 3057 | buffer_info->next_to_watch = i; |
9d5c8243 AK |
3058 | buffer_info->dma = 0; |
3059 | ||
3060 | i++; | |
3061 | if (i == tx_ring->count) | |
3062 | i = 0; | |
3063 | tx_ring->next_to_use = i; | |
3064 | ||
3065 | return true; | |
3066 | } | |
9d5c8243 AK |
3067 | return false; |
3068 | } | |
3069 | ||
3070 | #define IGB_MAX_TXD_PWR 16 | |
3071 | #define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR) | |
3072 | ||
3073 | static inline int igb_tx_map_adv(struct igb_adapter *adapter, | |
0e014cb1 AD |
3074 | struct igb_ring *tx_ring, struct sk_buff *skb, |
3075 | unsigned int first) | |
9d5c8243 AK |
3076 | { |
3077 | struct igb_buffer *buffer_info; | |
3078 | unsigned int len = skb_headlen(skb); | |
3079 | unsigned int count = 0, i; | |
3080 | unsigned int f; | |
3081 | ||
3082 | i = tx_ring->next_to_use; | |
3083 | ||
3084 | buffer_info = &tx_ring->buffer_info[i]; | |
3085 | BUG_ON(len >= IGB_MAX_DATA_PER_TXD); | |
3086 | buffer_info->length = len; | |
3087 | /* set time_stamp *before* dma to help avoid a possible race */ | |
3088 | buffer_info->time_stamp = jiffies; | |
0e014cb1 | 3089 | buffer_info->next_to_watch = i; |
9d5c8243 AK |
3090 | buffer_info->dma = pci_map_single(adapter->pdev, skb->data, len, |
3091 | PCI_DMA_TODEVICE); | |
3092 | count++; | |
3093 | i++; | |
3094 | if (i == tx_ring->count) | |
3095 | i = 0; | |
3096 | ||
3097 | for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) { | |
3098 | struct skb_frag_struct *frag; | |
3099 | ||
3100 | frag = &skb_shinfo(skb)->frags[f]; | |
3101 | len = frag->size; | |
3102 | ||
3103 | buffer_info = &tx_ring->buffer_info[i]; | |
3104 | BUG_ON(len >= IGB_MAX_DATA_PER_TXD); | |
3105 | buffer_info->length = len; | |
3106 | buffer_info->time_stamp = jiffies; | |
0e014cb1 | 3107 | buffer_info->next_to_watch = i; |
9d5c8243 AK |
3108 | buffer_info->dma = pci_map_page(adapter->pdev, |
3109 | frag->page, | |
3110 | frag->page_offset, | |
3111 | len, | |
3112 | PCI_DMA_TODEVICE); | |
3113 | ||
3114 | count++; | |
3115 | i++; | |
3116 | if (i == tx_ring->count) | |
3117 | i = 0; | |
3118 | } | |
3119 | ||
0e014cb1 | 3120 | i = ((i == 0) ? tx_ring->count - 1 : i - 1); |
9d5c8243 | 3121 | tx_ring->buffer_info[i].skb = skb; |
0e014cb1 | 3122 | tx_ring->buffer_info[first].next_to_watch = i; |
9d5c8243 AK |
3123 | |
3124 | return count; | |
3125 | } | |
3126 | ||
3127 | static inline void igb_tx_queue_adv(struct igb_adapter *adapter, | |
3128 | struct igb_ring *tx_ring, | |
3129 | int tx_flags, int count, u32 paylen, | |
3130 | u8 hdr_len) | |
3131 | { | |
3132 | union e1000_adv_tx_desc *tx_desc = NULL; | |
3133 | struct igb_buffer *buffer_info; | |
3134 | u32 olinfo_status = 0, cmd_type_len; | |
3135 | unsigned int i; | |
3136 | ||
3137 | cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS | | |
3138 | E1000_ADVTXD_DCMD_DEXT); | |
3139 | ||
3140 | if (tx_flags & IGB_TX_FLAGS_VLAN) | |
3141 | cmd_type_len |= E1000_ADVTXD_DCMD_VLE; | |
3142 | ||
33af6bcc PO |
3143 | if (tx_flags & IGB_TX_FLAGS_TSTAMP) |
3144 | cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP; | |
3145 | ||
9d5c8243 AK |
3146 | if (tx_flags & IGB_TX_FLAGS_TSO) { |
3147 | cmd_type_len |= E1000_ADVTXD_DCMD_TSE; | |
3148 | ||
3149 | /* insert tcp checksum */ | |
3150 | olinfo_status |= E1000_TXD_POPTS_TXSM << 8; | |
3151 | ||
3152 | /* insert ip checksum */ | |
3153 | if (tx_flags & IGB_TX_FLAGS_IPV4) | |
3154 | olinfo_status |= E1000_TXD_POPTS_IXSM << 8; | |
3155 | ||
3156 | } else if (tx_flags & IGB_TX_FLAGS_CSUM) { | |
3157 | olinfo_status |= E1000_TXD_POPTS_TXSM << 8; | |
3158 | } | |
3159 | ||
7dfc16fa AD |
3160 | if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) && |
3161 | (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO | | |
3162 | IGB_TX_FLAGS_VLAN))) | |
661086df | 3163 | olinfo_status |= tx_ring->queue_index << 4; |
9d5c8243 AK |
3164 | |
3165 | olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT); | |
3166 | ||
3167 | i = tx_ring->next_to_use; | |
3168 | while (count--) { | |
3169 | buffer_info = &tx_ring->buffer_info[i]; | |
3170 | tx_desc = E1000_TX_DESC_ADV(*tx_ring, i); | |
3171 | tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma); | |
3172 | tx_desc->read.cmd_type_len = | |
3173 | cpu_to_le32(cmd_type_len | buffer_info->length); | |
3174 | tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); | |
3175 | i++; | |
3176 | if (i == tx_ring->count) | |
3177 | i = 0; | |
3178 | } | |
3179 | ||
3180 | tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd); | |
3181 | /* Force memory writes to complete before letting h/w | |
3182 | * know there are new descriptors to fetch. (Only | |
3183 | * applicable for weak-ordered memory model archs, | |
3184 | * such as IA-64). */ | |
3185 | wmb(); | |
3186 | ||
3187 | tx_ring->next_to_use = i; | |
3188 | writel(i, adapter->hw.hw_addr + tx_ring->tail); | |
3189 | /* we need this if more than one processor can write to our tail | |
3190 | * at a time, it syncronizes IO on IA64/Altix systems */ | |
3191 | mmiowb(); | |
3192 | } | |
3193 | ||
3194 | static int __igb_maybe_stop_tx(struct net_device *netdev, | |
3195 | struct igb_ring *tx_ring, int size) | |
3196 | { | |
3197 | struct igb_adapter *adapter = netdev_priv(netdev); | |
3198 | ||
661086df | 3199 | netif_stop_subqueue(netdev, tx_ring->queue_index); |
661086df | 3200 | |
9d5c8243 AK |
3201 | /* Herbert's original patch had: |
3202 | * smp_mb__after_netif_stop_queue(); | |
3203 | * but since that doesn't exist yet, just open code it. */ | |
3204 | smp_mb(); | |
3205 | ||
3206 | /* We need to check again in a case another CPU has just | |
3207 | * made room available. */ | |
c493ea45 | 3208 | if (igb_desc_unused(tx_ring) < size) |
9d5c8243 AK |
3209 | return -EBUSY; |
3210 | ||
3211 | /* A reprieve! */ | |
661086df | 3212 | netif_wake_subqueue(netdev, tx_ring->queue_index); |
9d5c8243 AK |
3213 | ++adapter->restart_queue; |
3214 | return 0; | |
3215 | } | |
3216 | ||
3217 | static int igb_maybe_stop_tx(struct net_device *netdev, | |
3218 | struct igb_ring *tx_ring, int size) | |
3219 | { | |
c493ea45 | 3220 | if (igb_desc_unused(tx_ring) >= size) |
9d5c8243 AK |
3221 | return 0; |
3222 | return __igb_maybe_stop_tx(netdev, tx_ring, size); | |
3223 | } | |
3224 | ||
9d5c8243 AK |
3225 | static int igb_xmit_frame_ring_adv(struct sk_buff *skb, |
3226 | struct net_device *netdev, | |
3227 | struct igb_ring *tx_ring) | |
3228 | { | |
3229 | struct igb_adapter *adapter = netdev_priv(netdev); | |
0e014cb1 | 3230 | unsigned int first; |
9d5c8243 | 3231 | unsigned int tx_flags = 0; |
9d5c8243 AK |
3232 | u8 hdr_len = 0; |
3233 | int tso = 0; | |
33af6bcc | 3234 | union skb_shared_tx *shtx; |
9d5c8243 | 3235 | |
9d5c8243 AK |
3236 | if (test_bit(__IGB_DOWN, &adapter->state)) { |
3237 | dev_kfree_skb_any(skb); | |
3238 | return NETDEV_TX_OK; | |
3239 | } | |
3240 | ||
3241 | if (skb->len <= 0) { | |
3242 | dev_kfree_skb_any(skb); | |
3243 | return NETDEV_TX_OK; | |
3244 | } | |
3245 | ||
9d5c8243 AK |
3246 | /* need: 1 descriptor per page, |
3247 | * + 2 desc gap to keep tail from touching head, | |
3248 | * + 1 desc for skb->data, | |
3249 | * + 1 desc for context descriptor, | |
3250 | * otherwise try next time */ | |
3251 | if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) { | |
3252 | /* this is a hard error */ | |
9d5c8243 AK |
3253 | return NETDEV_TX_BUSY; |
3254 | } | |
33af6bcc PO |
3255 | |
3256 | /* | |
3257 | * TODO: check that there currently is no other packet with | |
3258 | * time stamping in the queue | |
3259 | * | |
3260 | * When doing time stamping, keep the connection to the socket | |
3261 | * a while longer: it is still needed by skb_hwtstamp_tx(), | |
3262 | * called either in igb_tx_hwtstamp() or by our caller when | |
3263 | * doing software time stamping. | |
3264 | */ | |
3265 | shtx = skb_tx(skb); | |
3266 | if (unlikely(shtx->hardware)) { | |
3267 | shtx->in_progress = 1; | |
3268 | tx_flags |= IGB_TX_FLAGS_TSTAMP; | |
33af6bcc | 3269 | } |
9d5c8243 AK |
3270 | |
3271 | if (adapter->vlgrp && vlan_tx_tag_present(skb)) { | |
3272 | tx_flags |= IGB_TX_FLAGS_VLAN; | |
3273 | tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); | |
3274 | } | |
3275 | ||
661086df PWJ |
3276 | if (skb->protocol == htons(ETH_P_IP)) |
3277 | tx_flags |= IGB_TX_FLAGS_IPV4; | |
3278 | ||
0e014cb1 | 3279 | first = tx_ring->next_to_use; |
9d5c8243 AK |
3280 | tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags, |
3281 | &hdr_len) : 0; | |
3282 | ||
3283 | if (tso < 0) { | |
3284 | dev_kfree_skb_any(skb); | |
9d5c8243 AK |
3285 | return NETDEV_TX_OK; |
3286 | } | |
3287 | ||
3288 | if (tso) | |
3289 | tx_flags |= IGB_TX_FLAGS_TSO; | |
bc1cbd34 AD |
3290 | else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags) && |
3291 | (skb->ip_summed == CHECKSUM_PARTIAL)) | |
3292 | tx_flags |= IGB_TX_FLAGS_CSUM; | |
9d5c8243 | 3293 | |
9d5c8243 | 3294 | igb_tx_queue_adv(adapter, tx_ring, tx_flags, |
0e014cb1 | 3295 | igb_tx_map_adv(adapter, tx_ring, skb, first), |
9d5c8243 AK |
3296 | skb->len, hdr_len); |
3297 | ||
3298 | netdev->trans_start = jiffies; | |
3299 | ||
3300 | /* Make sure there is space in the ring for the next send. */ | |
3301 | igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4); | |
3302 | ||
9d5c8243 AK |
3303 | return NETDEV_TX_OK; |
3304 | } | |
3305 | ||
3306 | static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *netdev) | |
3307 | { | |
3308 | struct igb_adapter *adapter = netdev_priv(netdev); | |
661086df PWJ |
3309 | struct igb_ring *tx_ring; |
3310 | ||
661086df | 3311 | int r_idx = 0; |
1bfaf07b | 3312 | r_idx = skb->queue_mapping & (IGB_ABS_MAX_TX_QUEUES - 1); |
661086df | 3313 | tx_ring = adapter->multi_tx_table[r_idx]; |
9d5c8243 AK |
3314 | |
3315 | /* This goes back to the question of how to logically map a tx queue | |
3316 | * to a flow. Right now, performance is impacted slightly negatively | |
3317 | * if using multiple tx queues. If the stack breaks away from a | |
3318 | * single qdisc implementation, we can look at this again. */ | |
3319 | return (igb_xmit_frame_ring_adv(skb, netdev, tx_ring)); | |
3320 | } | |
3321 | ||
3322 | /** | |
3323 | * igb_tx_timeout - Respond to a Tx Hang | |
3324 | * @netdev: network interface device structure | |
3325 | **/ | |
3326 | static void igb_tx_timeout(struct net_device *netdev) | |
3327 | { | |
3328 | struct igb_adapter *adapter = netdev_priv(netdev); | |
3329 | struct e1000_hw *hw = &adapter->hw; | |
3330 | ||
3331 | /* Do the reset outside of interrupt context */ | |
3332 | adapter->tx_timeout_count++; | |
3333 | schedule_work(&adapter->reset_task); | |
265de409 AD |
3334 | wr32(E1000_EICS, |
3335 | (adapter->eims_enable_mask & ~adapter->eims_other)); | |
9d5c8243 AK |
3336 | } |
3337 | ||
3338 | static void igb_reset_task(struct work_struct *work) | |
3339 | { | |
3340 | struct igb_adapter *adapter; | |
3341 | adapter = container_of(work, struct igb_adapter, reset_task); | |
3342 | ||
3343 | igb_reinit_locked(adapter); | |
3344 | } | |
3345 | ||
3346 | /** | |
3347 | * igb_get_stats - Get System Network Statistics | |
3348 | * @netdev: network interface device structure | |
3349 | * | |
3350 | * Returns the address of the device statistics structure. | |
3351 | * The statistics are actually updated from the timer callback. | |
3352 | **/ | |
73cd78f1 | 3353 | static struct net_device_stats *igb_get_stats(struct net_device *netdev) |
9d5c8243 AK |
3354 | { |
3355 | struct igb_adapter *adapter = netdev_priv(netdev); | |
3356 | ||
3357 | /* only return the current stats */ | |
3358 | return &adapter->net_stats; | |
3359 | } | |
3360 | ||
3361 | /** | |
3362 | * igb_change_mtu - Change the Maximum Transfer Unit | |
3363 | * @netdev: network interface device structure | |
3364 | * @new_mtu: new value for maximum frame size | |
3365 | * | |
3366 | * Returns 0 on success, negative on failure | |
3367 | **/ | |
3368 | static int igb_change_mtu(struct net_device *netdev, int new_mtu) | |
3369 | { | |
3370 | struct igb_adapter *adapter = netdev_priv(netdev); | |
3371 | int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; | |
3372 | ||
3373 | if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) || | |
3374 | (max_frame > MAX_JUMBO_FRAME_SIZE)) { | |
3375 | dev_err(&adapter->pdev->dev, "Invalid MTU setting\n"); | |
3376 | return -EINVAL; | |
3377 | } | |
3378 | ||
9d5c8243 AK |
3379 | if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) { |
3380 | dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n"); | |
3381 | return -EINVAL; | |
3382 | } | |
3383 | ||
3384 | while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) | |
3385 | msleep(1); | |
73cd78f1 | 3386 | |
9d5c8243 AK |
3387 | /* igb_down has a dependency on max_frame_size */ |
3388 | adapter->max_frame_size = max_frame; | |
3389 | if (netif_running(netdev)) | |
3390 | igb_down(adapter); | |
3391 | ||
3392 | /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN | |
3393 | * means we reserve 2 more, this pushes us to allocate from the next | |
3394 | * larger slab size. | |
3395 | * i.e. RXBUFFER_2048 --> size-4096 slab | |
3396 | */ | |
3397 | ||
3398 | if (max_frame <= IGB_RXBUFFER_256) | |
3399 | adapter->rx_buffer_len = IGB_RXBUFFER_256; | |
3400 | else if (max_frame <= IGB_RXBUFFER_512) | |
3401 | adapter->rx_buffer_len = IGB_RXBUFFER_512; | |
3402 | else if (max_frame <= IGB_RXBUFFER_1024) | |
3403 | adapter->rx_buffer_len = IGB_RXBUFFER_1024; | |
3404 | else if (max_frame <= IGB_RXBUFFER_2048) | |
3405 | adapter->rx_buffer_len = IGB_RXBUFFER_2048; | |
3406 | else | |
bf36c1a0 AD |
3407 | #if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384 |
3408 | adapter->rx_buffer_len = IGB_RXBUFFER_16384; | |
3409 | #else | |
3410 | adapter->rx_buffer_len = PAGE_SIZE / 2; | |
3411 | #endif | |
e1739522 AD |
3412 | |
3413 | /* if sr-iov is enabled we need to force buffer size to 1K or larger */ | |
3414 | if (adapter->vfs_allocated_count && | |
3415 | (adapter->rx_buffer_len < IGB_RXBUFFER_1024)) | |
3416 | adapter->rx_buffer_len = IGB_RXBUFFER_1024; | |
3417 | ||
9d5c8243 AK |
3418 | /* adjust allocation if LPE protects us, and we aren't using SBP */ |
3419 | if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) || | |
3420 | (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE)) | |
3421 | adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE; | |
3422 | ||
3423 | dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n", | |
3424 | netdev->mtu, new_mtu); | |
3425 | netdev->mtu = new_mtu; | |
3426 | ||
3427 | if (netif_running(netdev)) | |
3428 | igb_up(adapter); | |
3429 | else | |
3430 | igb_reset(adapter); | |
3431 | ||
3432 | clear_bit(__IGB_RESETTING, &adapter->state); | |
3433 | ||
3434 | return 0; | |
3435 | } | |
3436 | ||
3437 | /** | |
3438 | * igb_update_stats - Update the board statistics counters | |
3439 | * @adapter: board private structure | |
3440 | **/ | |
3441 | ||
3442 | void igb_update_stats(struct igb_adapter *adapter) | |
3443 | { | |
3444 | struct e1000_hw *hw = &adapter->hw; | |
3445 | struct pci_dev *pdev = adapter->pdev; | |
3446 | u16 phy_tmp; | |
3447 | ||
3448 | #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF | |
3449 | ||
3450 | /* | |
3451 | * Prevent stats update while adapter is being reset, or if the pci | |
3452 | * connection is down. | |
3453 | */ | |
3454 | if (adapter->link_speed == 0) | |
3455 | return; | |
3456 | if (pci_channel_offline(pdev)) | |
3457 | return; | |
3458 | ||
3459 | adapter->stats.crcerrs += rd32(E1000_CRCERRS); | |
3460 | adapter->stats.gprc += rd32(E1000_GPRC); | |
3461 | adapter->stats.gorc += rd32(E1000_GORCL); | |
3462 | rd32(E1000_GORCH); /* clear GORCL */ | |
3463 | adapter->stats.bprc += rd32(E1000_BPRC); | |
3464 | adapter->stats.mprc += rd32(E1000_MPRC); | |
3465 | adapter->stats.roc += rd32(E1000_ROC); | |
3466 | ||
3467 | adapter->stats.prc64 += rd32(E1000_PRC64); | |
3468 | adapter->stats.prc127 += rd32(E1000_PRC127); | |
3469 | adapter->stats.prc255 += rd32(E1000_PRC255); | |
3470 | adapter->stats.prc511 += rd32(E1000_PRC511); | |
3471 | adapter->stats.prc1023 += rd32(E1000_PRC1023); | |
3472 | adapter->stats.prc1522 += rd32(E1000_PRC1522); | |
3473 | adapter->stats.symerrs += rd32(E1000_SYMERRS); | |
3474 | adapter->stats.sec += rd32(E1000_SEC); | |
3475 | ||
3476 | adapter->stats.mpc += rd32(E1000_MPC); | |
3477 | adapter->stats.scc += rd32(E1000_SCC); | |
3478 | adapter->stats.ecol += rd32(E1000_ECOL); | |
3479 | adapter->stats.mcc += rd32(E1000_MCC); | |
3480 | adapter->stats.latecol += rd32(E1000_LATECOL); | |
3481 | adapter->stats.dc += rd32(E1000_DC); | |
3482 | adapter->stats.rlec += rd32(E1000_RLEC); | |
3483 | adapter->stats.xonrxc += rd32(E1000_XONRXC); | |
3484 | adapter->stats.xontxc += rd32(E1000_XONTXC); | |
3485 | adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); | |
3486 | adapter->stats.xofftxc += rd32(E1000_XOFFTXC); | |
3487 | adapter->stats.fcruc += rd32(E1000_FCRUC); | |
3488 | adapter->stats.gptc += rd32(E1000_GPTC); | |
3489 | adapter->stats.gotc += rd32(E1000_GOTCL); | |
3490 | rd32(E1000_GOTCH); /* clear GOTCL */ | |
3491 | adapter->stats.rnbc += rd32(E1000_RNBC); | |
3492 | adapter->stats.ruc += rd32(E1000_RUC); | |
3493 | adapter->stats.rfc += rd32(E1000_RFC); | |
3494 | adapter->stats.rjc += rd32(E1000_RJC); | |
3495 | adapter->stats.tor += rd32(E1000_TORH); | |
3496 | adapter->stats.tot += rd32(E1000_TOTH); | |
3497 | adapter->stats.tpr += rd32(E1000_TPR); | |
3498 | ||
3499 | adapter->stats.ptc64 += rd32(E1000_PTC64); | |
3500 | adapter->stats.ptc127 += rd32(E1000_PTC127); | |
3501 | adapter->stats.ptc255 += rd32(E1000_PTC255); | |
3502 | adapter->stats.ptc511 += rd32(E1000_PTC511); | |
3503 | adapter->stats.ptc1023 += rd32(E1000_PTC1023); | |
3504 | adapter->stats.ptc1522 += rd32(E1000_PTC1522); | |
3505 | ||
3506 | adapter->stats.mptc += rd32(E1000_MPTC); | |
3507 | adapter->stats.bptc += rd32(E1000_BPTC); | |
3508 | ||
3509 | /* used for adaptive IFS */ | |
3510 | ||
3511 | hw->mac.tx_packet_delta = rd32(E1000_TPT); | |
3512 | adapter->stats.tpt += hw->mac.tx_packet_delta; | |
3513 | hw->mac.collision_delta = rd32(E1000_COLC); | |
3514 | adapter->stats.colc += hw->mac.collision_delta; | |
3515 | ||
3516 | adapter->stats.algnerrc += rd32(E1000_ALGNERRC); | |
3517 | adapter->stats.rxerrc += rd32(E1000_RXERRC); | |
3518 | adapter->stats.tncrs += rd32(E1000_TNCRS); | |
3519 | adapter->stats.tsctc += rd32(E1000_TSCTC); | |
3520 | adapter->stats.tsctfc += rd32(E1000_TSCTFC); | |
3521 | ||
3522 | adapter->stats.iac += rd32(E1000_IAC); | |
3523 | adapter->stats.icrxoc += rd32(E1000_ICRXOC); | |
3524 | adapter->stats.icrxptc += rd32(E1000_ICRXPTC); | |
3525 | adapter->stats.icrxatc += rd32(E1000_ICRXATC); | |
3526 | adapter->stats.ictxptc += rd32(E1000_ICTXPTC); | |
3527 | adapter->stats.ictxatc += rd32(E1000_ICTXATC); | |
3528 | adapter->stats.ictxqec += rd32(E1000_ICTXQEC); | |
3529 | adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); | |
3530 | adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); | |
3531 | ||
3532 | /* Fill out the OS statistics structure */ | |
3533 | adapter->net_stats.multicast = adapter->stats.mprc; | |
3534 | adapter->net_stats.collisions = adapter->stats.colc; | |
3535 | ||
3536 | /* Rx Errors */ | |
3537 | ||
3538 | /* RLEC on some newer hardware can be incorrect so build | |
3539 | * our own version based on RUC and ROC */ | |
3540 | adapter->net_stats.rx_errors = adapter->stats.rxerrc + | |
3541 | adapter->stats.crcerrs + adapter->stats.algnerrc + | |
3542 | adapter->stats.ruc + adapter->stats.roc + | |
3543 | adapter->stats.cexterr; | |
3544 | adapter->net_stats.rx_length_errors = adapter->stats.ruc + | |
3545 | adapter->stats.roc; | |
3546 | adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs; | |
3547 | adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc; | |
3548 | adapter->net_stats.rx_missed_errors = adapter->stats.mpc; | |
3549 | ||
3550 | /* Tx Errors */ | |
3551 | adapter->net_stats.tx_errors = adapter->stats.ecol + | |
3552 | adapter->stats.latecol; | |
3553 | adapter->net_stats.tx_aborted_errors = adapter->stats.ecol; | |
3554 | adapter->net_stats.tx_window_errors = adapter->stats.latecol; | |
3555 | adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs; | |
3556 | ||
3557 | /* Tx Dropped needs to be maintained elsewhere */ | |
3558 | ||
3559 | /* Phy Stats */ | |
3560 | if (hw->phy.media_type == e1000_media_type_copper) { | |
3561 | if ((adapter->link_speed == SPEED_1000) && | |
73cd78f1 | 3562 | (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) { |
9d5c8243 AK |
3563 | phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK; |
3564 | adapter->phy_stats.idle_errors += phy_tmp; | |
3565 | } | |
3566 | } | |
3567 | ||
3568 | /* Management Stats */ | |
3569 | adapter->stats.mgptc += rd32(E1000_MGTPTC); | |
3570 | adapter->stats.mgprc += rd32(E1000_MGTPRC); | |
3571 | adapter->stats.mgpdc += rd32(E1000_MGTPDC); | |
3572 | } | |
3573 | ||
9d5c8243 AK |
3574 | static irqreturn_t igb_msix_other(int irq, void *data) |
3575 | { | |
3576 | struct net_device *netdev = data; | |
3577 | struct igb_adapter *adapter = netdev_priv(netdev); | |
3578 | struct e1000_hw *hw = &adapter->hw; | |
844290e5 | 3579 | u32 icr = rd32(E1000_ICR); |
9d5c8243 | 3580 | |
844290e5 | 3581 | /* reading ICR causes bit 31 of EICR to be cleared */ |
dda0e083 AD |
3582 | |
3583 | if(icr & E1000_ICR_DOUTSYNC) { | |
3584 | /* HW is reporting DMA is out of sync */ | |
3585 | adapter->stats.doosync++; | |
3586 | } | |
eebbbdba | 3587 | |
4ae196df AD |
3588 | /* Check for a mailbox event */ |
3589 | if (icr & E1000_ICR_VMMB) | |
3590 | igb_msg_task(adapter); | |
3591 | ||
3592 | if (icr & E1000_ICR_LSC) { | |
3593 | hw->mac.get_link_status = 1; | |
3594 | /* guard against interrupt when we're going down */ | |
3595 | if (!test_bit(__IGB_DOWN, &adapter->state)) | |
3596 | mod_timer(&adapter->watchdog_timer, jiffies + 1); | |
3597 | } | |
3598 | ||
3599 | wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_VMMB); | |
844290e5 | 3600 | wr32(E1000_EIMS, adapter->eims_other); |
9d5c8243 AK |
3601 | |
3602 | return IRQ_HANDLED; | |
3603 | } | |
3604 | ||
3605 | static irqreturn_t igb_msix_tx(int irq, void *data) | |
3606 | { | |
3607 | struct igb_ring *tx_ring = data; | |
3608 | struct igb_adapter *adapter = tx_ring->adapter; | |
3609 | struct e1000_hw *hw = &adapter->hw; | |
3610 | ||
421e02f0 | 3611 | #ifdef CONFIG_IGB_DCA |
7dfc16fa | 3612 | if (adapter->flags & IGB_FLAG_DCA_ENABLED) |
fe4506b6 JC |
3613 | igb_update_tx_dca(tx_ring); |
3614 | #endif | |
73cd78f1 | 3615 | |
9d5c8243 AK |
3616 | tx_ring->total_bytes = 0; |
3617 | tx_ring->total_packets = 0; | |
661086df PWJ |
3618 | |
3619 | /* auto mask will automatically reenable the interrupt when we write | |
3620 | * EICS */ | |
3b644cf6 | 3621 | if (!igb_clean_tx_irq(tx_ring)) |
9d5c8243 AK |
3622 | /* Ring was not completely cleaned, so fire another interrupt */ |
3623 | wr32(E1000_EICS, tx_ring->eims_value); | |
661086df | 3624 | else |
9d5c8243 | 3625 | wr32(E1000_EIMS, tx_ring->eims_value); |
661086df | 3626 | |
9d5c8243 AK |
3627 | return IRQ_HANDLED; |
3628 | } | |
3629 | ||
6eb5a7f1 AD |
3630 | static void igb_write_itr(struct igb_ring *ring) |
3631 | { | |
3632 | struct e1000_hw *hw = &ring->adapter->hw; | |
3633 | if ((ring->adapter->itr_setting & 3) && ring->set_itr) { | |
3634 | switch (hw->mac.type) { | |
3635 | case e1000_82576: | |
73cd78f1 | 3636 | wr32(ring->itr_register, ring->itr_val | |
6eb5a7f1 AD |
3637 | 0x80000000); |
3638 | break; | |
3639 | default: | |
73cd78f1 | 3640 | wr32(ring->itr_register, ring->itr_val | |
6eb5a7f1 AD |
3641 | (ring->itr_val << 16)); |
3642 | break; | |
3643 | } | |
3644 | ring->set_itr = 0; | |
3645 | } | |
3646 | } | |
3647 | ||
9d5c8243 AK |
3648 | static irqreturn_t igb_msix_rx(int irq, void *data) |
3649 | { | |
3650 | struct igb_ring *rx_ring = data; | |
9d5c8243 | 3651 | |
844290e5 PW |
3652 | /* Write the ITR value calculated at the end of the |
3653 | * previous interrupt. | |
3654 | */ | |
9d5c8243 | 3655 | |
6eb5a7f1 | 3656 | igb_write_itr(rx_ring); |
9d5c8243 | 3657 | |
288379f0 BH |
3658 | if (napi_schedule_prep(&rx_ring->napi)) |
3659 | __napi_schedule(&rx_ring->napi); | |
844290e5 | 3660 | |
421e02f0 | 3661 | #ifdef CONFIG_IGB_DCA |
8d253320 | 3662 | if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED) |
fe4506b6 JC |
3663 | igb_update_rx_dca(rx_ring); |
3664 | #endif | |
3665 | return IRQ_HANDLED; | |
3666 | } | |
3667 | ||
421e02f0 | 3668 | #ifdef CONFIG_IGB_DCA |
fe4506b6 JC |
3669 | static void igb_update_rx_dca(struct igb_ring *rx_ring) |
3670 | { | |
3671 | u32 dca_rxctrl; | |
3672 | struct igb_adapter *adapter = rx_ring->adapter; | |
3673 | struct e1000_hw *hw = &adapter->hw; | |
3674 | int cpu = get_cpu(); | |
26bc19ec | 3675 | int q = rx_ring->reg_idx; |
fe4506b6 JC |
3676 | |
3677 | if (rx_ring->cpu != cpu) { | |
3678 | dca_rxctrl = rd32(E1000_DCA_RXCTRL(q)); | |
2d064c06 AD |
3679 | if (hw->mac.type == e1000_82576) { |
3680 | dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576; | |
92be7917 | 3681 | dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) << |
2d064c06 AD |
3682 | E1000_DCA_RXCTRL_CPUID_SHIFT; |
3683 | } else { | |
3684 | dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK; | |
92be7917 | 3685 | dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu); |
2d064c06 | 3686 | } |
fe4506b6 JC |
3687 | dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN; |
3688 | dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN; | |
3689 | dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN; | |
3690 | wr32(E1000_DCA_RXCTRL(q), dca_rxctrl); | |
3691 | rx_ring->cpu = cpu; | |
3692 | } | |
3693 | put_cpu(); | |
3694 | } | |
3695 | ||
3696 | static void igb_update_tx_dca(struct igb_ring *tx_ring) | |
3697 | { | |
3698 | u32 dca_txctrl; | |
3699 | struct igb_adapter *adapter = tx_ring->adapter; | |
3700 | struct e1000_hw *hw = &adapter->hw; | |
3701 | int cpu = get_cpu(); | |
26bc19ec | 3702 | int q = tx_ring->reg_idx; |
fe4506b6 JC |
3703 | |
3704 | if (tx_ring->cpu != cpu) { | |
3705 | dca_txctrl = rd32(E1000_DCA_TXCTRL(q)); | |
2d064c06 AD |
3706 | if (hw->mac.type == e1000_82576) { |
3707 | dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576; | |
92be7917 | 3708 | dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) << |
2d064c06 AD |
3709 | E1000_DCA_TXCTRL_CPUID_SHIFT; |
3710 | } else { | |
3711 | dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK; | |
92be7917 | 3712 | dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu); |
2d064c06 | 3713 | } |
fe4506b6 JC |
3714 | dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN; |
3715 | wr32(E1000_DCA_TXCTRL(q), dca_txctrl); | |
3716 | tx_ring->cpu = cpu; | |
3717 | } | |
3718 | put_cpu(); | |
3719 | } | |
3720 | ||
3721 | static void igb_setup_dca(struct igb_adapter *adapter) | |
3722 | { | |
3723 | int i; | |
3724 | ||
7dfc16fa | 3725 | if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) |
fe4506b6 JC |
3726 | return; |
3727 | ||
3728 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
3729 | adapter->tx_ring[i].cpu = -1; | |
3730 | igb_update_tx_dca(&adapter->tx_ring[i]); | |
3731 | } | |
3732 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
3733 | adapter->rx_ring[i].cpu = -1; | |
3734 | igb_update_rx_dca(&adapter->rx_ring[i]); | |
3735 | } | |
3736 | } | |
3737 | ||
3738 | static int __igb_notify_dca(struct device *dev, void *data) | |
3739 | { | |
3740 | struct net_device *netdev = dev_get_drvdata(dev); | |
3741 | struct igb_adapter *adapter = netdev_priv(netdev); | |
3742 | struct e1000_hw *hw = &adapter->hw; | |
3743 | unsigned long event = *(unsigned long *)data; | |
3744 | ||
3745 | switch (event) { | |
3746 | case DCA_PROVIDER_ADD: | |
3747 | /* if already enabled, don't do it again */ | |
7dfc16fa | 3748 | if (adapter->flags & IGB_FLAG_DCA_ENABLED) |
fe4506b6 | 3749 | break; |
fe4506b6 JC |
3750 | /* Always use CB2 mode, difference is masked |
3751 | * in the CB driver. */ | |
cbd347ad | 3752 | wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); |
fe4506b6 | 3753 | if (dca_add_requester(dev) == 0) { |
bbd98fe4 | 3754 | adapter->flags |= IGB_FLAG_DCA_ENABLED; |
fe4506b6 JC |
3755 | dev_info(&adapter->pdev->dev, "DCA enabled\n"); |
3756 | igb_setup_dca(adapter); | |
3757 | break; | |
3758 | } | |
3759 | /* Fall Through since DCA is disabled. */ | |
3760 | case DCA_PROVIDER_REMOVE: | |
7dfc16fa | 3761 | if (adapter->flags & IGB_FLAG_DCA_ENABLED) { |
fe4506b6 JC |
3762 | /* without this a class_device is left |
3763 | * hanging around in the sysfs model */ | |
3764 | dca_remove_requester(dev); | |
3765 | dev_info(&adapter->pdev->dev, "DCA disabled\n"); | |
7dfc16fa | 3766 | adapter->flags &= ~IGB_FLAG_DCA_ENABLED; |
cbd347ad | 3767 | wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); |
fe4506b6 JC |
3768 | } |
3769 | break; | |
3770 | } | |
bbd98fe4 | 3771 | |
fe4506b6 | 3772 | return 0; |
9d5c8243 AK |
3773 | } |
3774 | ||
fe4506b6 JC |
3775 | static int igb_notify_dca(struct notifier_block *nb, unsigned long event, |
3776 | void *p) | |
3777 | { | |
3778 | int ret_val; | |
3779 | ||
3780 | ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, | |
3781 | __igb_notify_dca); | |
3782 | ||
3783 | return ret_val ? NOTIFY_BAD : NOTIFY_DONE; | |
3784 | } | |
421e02f0 | 3785 | #endif /* CONFIG_IGB_DCA */ |
9d5c8243 | 3786 | |
4ae196df AD |
3787 | static void igb_ping_all_vfs(struct igb_adapter *adapter) |
3788 | { | |
3789 | struct e1000_hw *hw = &adapter->hw; | |
3790 | u32 ping; | |
3791 | int i; | |
3792 | ||
3793 | for (i = 0 ; i < adapter->vfs_allocated_count; i++) { | |
3794 | ping = E1000_PF_CONTROL_MSG; | |
3795 | if (adapter->vf_data[i].clear_to_send) | |
3796 | ping |= E1000_VT_MSGTYPE_CTS; | |
3797 | igb_write_mbx(hw, &ping, 1, i); | |
3798 | } | |
3799 | } | |
3800 | ||
3801 | static int igb_set_vf_multicasts(struct igb_adapter *adapter, | |
3802 | u32 *msgbuf, u32 vf) | |
3803 | { | |
3804 | int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; | |
3805 | u16 *hash_list = (u16 *)&msgbuf[1]; | |
3806 | struct vf_data_storage *vf_data = &adapter->vf_data[vf]; | |
3807 | int i; | |
3808 | ||
3809 | /* only up to 30 hash values supported */ | |
3810 | if (n > 30) | |
3811 | n = 30; | |
3812 | ||
3813 | /* salt away the number of multi cast addresses assigned | |
3814 | * to this VF for later use to restore when the PF multi cast | |
3815 | * list changes | |
3816 | */ | |
3817 | vf_data->num_vf_mc_hashes = n; | |
3818 | ||
3819 | /* VFs are limited to using the MTA hash table for their multicast | |
3820 | * addresses */ | |
3821 | for (i = 0; i < n; i++) | |
3822 | vf_data->vf_mc_hashes[i] = hash_list[i];; | |
3823 | ||
3824 | /* Flush and reset the mta with the new values */ | |
3825 | igb_set_multi(adapter->netdev); | |
3826 | ||
3827 | return 0; | |
3828 | } | |
3829 | ||
3830 | static void igb_restore_vf_multicasts(struct igb_adapter *adapter) | |
3831 | { | |
3832 | struct e1000_hw *hw = &adapter->hw; | |
3833 | struct vf_data_storage *vf_data; | |
3834 | int i, j; | |
3835 | ||
3836 | for (i = 0; i < adapter->vfs_allocated_count; i++) { | |
3837 | vf_data = &adapter->vf_data[i]; | |
75f4f382 | 3838 | for (j = 0; j < vf_data->num_vf_mc_hashes; j++) |
4ae196df AD |
3839 | igb_mta_set(hw, vf_data->vf_mc_hashes[j]); |
3840 | } | |
3841 | } | |
3842 | ||
3843 | static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf) | |
3844 | { | |
3845 | struct e1000_hw *hw = &adapter->hw; | |
3846 | u32 pool_mask, reg, vid; | |
3847 | int i; | |
3848 | ||
3849 | pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf); | |
3850 | ||
3851 | /* Find the vlan filter for this id */ | |
3852 | for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { | |
3853 | reg = rd32(E1000_VLVF(i)); | |
3854 | ||
3855 | /* remove the vf from the pool */ | |
3856 | reg &= ~pool_mask; | |
3857 | ||
3858 | /* if pool is empty then remove entry from vfta */ | |
3859 | if (!(reg & E1000_VLVF_POOLSEL_MASK) && | |
3860 | (reg & E1000_VLVF_VLANID_ENABLE)) { | |
3861 | reg = 0; | |
3862 | vid = reg & E1000_VLVF_VLANID_MASK; | |
3863 | igb_vfta_set(hw, vid, false); | |
3864 | } | |
3865 | ||
3866 | wr32(E1000_VLVF(i), reg); | |
3867 | } | |
3868 | } | |
3869 | ||
3870 | static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf) | |
3871 | { | |
3872 | struct e1000_hw *hw = &adapter->hw; | |
3873 | u32 reg, i; | |
3874 | ||
3875 | /* It is an error to call this function when VFs are not enabled */ | |
3876 | if (!adapter->vfs_allocated_count) | |
3877 | return -1; | |
3878 | ||
3879 | /* Find the vlan filter for this id */ | |
3880 | for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { | |
3881 | reg = rd32(E1000_VLVF(i)); | |
3882 | if ((reg & E1000_VLVF_VLANID_ENABLE) && | |
3883 | vid == (reg & E1000_VLVF_VLANID_MASK)) | |
3884 | break; | |
3885 | } | |
3886 | ||
3887 | if (add) { | |
3888 | if (i == E1000_VLVF_ARRAY_SIZE) { | |
3889 | /* Did not find a matching VLAN ID entry that was | |
3890 | * enabled. Search for a free filter entry, i.e. | |
3891 | * one without the enable bit set | |
3892 | */ | |
3893 | for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { | |
3894 | reg = rd32(E1000_VLVF(i)); | |
3895 | if (!(reg & E1000_VLVF_VLANID_ENABLE)) | |
3896 | break; | |
3897 | } | |
3898 | } | |
3899 | if (i < E1000_VLVF_ARRAY_SIZE) { | |
3900 | /* Found an enabled/available entry */ | |
3901 | reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf); | |
3902 | ||
3903 | /* if !enabled we need to set this up in vfta */ | |
3904 | if (!(reg & E1000_VLVF_VLANID_ENABLE)) { | |
cad6d05f AD |
3905 | /* add VID to filter table, if bit already set |
3906 | * PF must have added it outside of table */ | |
3907 | if (igb_vfta_set(hw, vid, true)) | |
3908 | reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + | |
3909 | adapter->vfs_allocated_count); | |
4ae196df AD |
3910 | reg |= E1000_VLVF_VLANID_ENABLE; |
3911 | } | |
cad6d05f AD |
3912 | reg &= ~E1000_VLVF_VLANID_MASK; |
3913 | reg |= vid; | |
4ae196df AD |
3914 | |
3915 | wr32(E1000_VLVF(i), reg); | |
3916 | return 0; | |
3917 | } | |
3918 | } else { | |
3919 | if (i < E1000_VLVF_ARRAY_SIZE) { | |
3920 | /* remove vf from the pool */ | |
3921 | reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf)); | |
3922 | /* if pool is empty then remove entry from vfta */ | |
3923 | if (!(reg & E1000_VLVF_POOLSEL_MASK)) { | |
3924 | reg = 0; | |
3925 | igb_vfta_set(hw, vid, false); | |
3926 | } | |
3927 | wr32(E1000_VLVF(i), reg); | |
3928 | return 0; | |
3929 | } | |
3930 | } | |
3931 | return -1; | |
3932 | } | |
3933 | ||
3934 | static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) | |
3935 | { | |
3936 | int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; | |
3937 | int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); | |
3938 | ||
3939 | return igb_vlvf_set(adapter, vid, add, vf); | |
3940 | } | |
3941 | ||
3942 | static inline void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) | |
3943 | { | |
3944 | struct e1000_hw *hw = &adapter->hw; | |
3945 | ||
3946 | /* disable mailbox functionality for vf */ | |
3947 | adapter->vf_data[vf].clear_to_send = false; | |
3948 | ||
3949 | /* reset offloads to defaults */ | |
3950 | igb_set_vmolr(hw, vf); | |
3951 | ||
3952 | /* reset vlans for device */ | |
3953 | igb_clear_vf_vfta(adapter, vf); | |
3954 | ||
3955 | /* reset multicast table array for vf */ | |
3956 | adapter->vf_data[vf].num_vf_mc_hashes = 0; | |
3957 | ||
3958 | /* Flush and reset the mta with the new values */ | |
3959 | igb_set_multi(adapter->netdev); | |
3960 | } | |
3961 | ||
3962 | static inline void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) | |
3963 | { | |
3964 | struct e1000_hw *hw = &adapter->hw; | |
3965 | unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; | |
3966 | u32 reg, msgbuf[3]; | |
3967 | u8 *addr = (u8 *)(&msgbuf[1]); | |
3968 | ||
3969 | /* process all the same items cleared in a function level reset */ | |
3970 | igb_vf_reset_event(adapter, vf); | |
3971 | ||
3972 | /* set vf mac address */ | |
3973 | igb_rar_set(hw, vf_mac, vf + 1); | |
3974 | igb_set_rah_pool(hw, vf, vf + 1); | |
3975 | ||
3976 | /* enable transmit and receive for vf */ | |
3977 | reg = rd32(E1000_VFTE); | |
3978 | wr32(E1000_VFTE, reg | (1 << vf)); | |
3979 | reg = rd32(E1000_VFRE); | |
3980 | wr32(E1000_VFRE, reg | (1 << vf)); | |
3981 | ||
3982 | /* enable mailbox functionality for vf */ | |
3983 | adapter->vf_data[vf].clear_to_send = true; | |
3984 | ||
3985 | /* reply to reset with ack and vf mac address */ | |
3986 | msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; | |
3987 | memcpy(addr, vf_mac, 6); | |
3988 | igb_write_mbx(hw, msgbuf, 3, vf); | |
3989 | } | |
3990 | ||
3991 | static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) | |
3992 | { | |
3993 | unsigned char *addr = (char *)&msg[1]; | |
3994 | int err = -1; | |
3995 | ||
3996 | if (is_valid_ether_addr(addr)) | |
3997 | err = igb_set_vf_mac(adapter, vf, addr); | |
3998 | ||
3999 | return err; | |
4000 | ||
4001 | } | |
4002 | ||
4003 | static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) | |
4004 | { | |
4005 | struct e1000_hw *hw = &adapter->hw; | |
4006 | u32 msg = E1000_VT_MSGTYPE_NACK; | |
4007 | ||
4008 | /* if device isn't clear to send it shouldn't be reading either */ | |
4009 | if (!adapter->vf_data[vf].clear_to_send) | |
4010 | igb_write_mbx(hw, &msg, 1, vf); | |
4011 | } | |
4012 | ||
4013 | ||
4014 | static void igb_msg_task(struct igb_adapter *adapter) | |
4015 | { | |
4016 | struct e1000_hw *hw = &adapter->hw; | |
4017 | u32 vf; | |
4018 | ||
4019 | for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { | |
4020 | /* process any reset requests */ | |
4021 | if (!igb_check_for_rst(hw, vf)) { | |
4022 | adapter->vf_data[vf].clear_to_send = false; | |
4023 | igb_vf_reset_event(adapter, vf); | |
4024 | } | |
4025 | ||
4026 | /* process any messages pending */ | |
4027 | if (!igb_check_for_msg(hw, vf)) | |
4028 | igb_rcv_msg_from_vf(adapter, vf); | |
4029 | ||
4030 | /* process any acks */ | |
4031 | if (!igb_check_for_ack(hw, vf)) | |
4032 | igb_rcv_ack_from_vf(adapter, vf); | |
4033 | ||
4034 | } | |
4035 | } | |
4036 | ||
4037 | static int igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) | |
4038 | { | |
4039 | u32 mbx_size = E1000_VFMAILBOX_SIZE; | |
4040 | u32 msgbuf[mbx_size]; | |
4041 | struct e1000_hw *hw = &adapter->hw; | |
4042 | s32 retval; | |
4043 | ||
4044 | retval = igb_read_mbx(hw, msgbuf, mbx_size, vf); | |
4045 | ||
4046 | if (retval) | |
4047 | dev_err(&adapter->pdev->dev, | |
4048 | "Error receiving message from VF\n"); | |
4049 | ||
4050 | /* this is a message we already processed, do nothing */ | |
4051 | if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) | |
4052 | return retval; | |
4053 | ||
4054 | /* | |
4055 | * until the vf completes a reset it should not be | |
4056 | * allowed to start any configuration. | |
4057 | */ | |
4058 | ||
4059 | if (msgbuf[0] == E1000_VF_RESET) { | |
4060 | igb_vf_reset_msg(adapter, vf); | |
4061 | ||
4062 | return retval; | |
4063 | } | |
4064 | ||
4065 | if (!adapter->vf_data[vf].clear_to_send) { | |
4066 | msgbuf[0] |= E1000_VT_MSGTYPE_NACK; | |
4067 | igb_write_mbx(hw, msgbuf, 1, vf); | |
4068 | return retval; | |
4069 | } | |
4070 | ||
4071 | switch ((msgbuf[0] & 0xFFFF)) { | |
4072 | case E1000_VF_SET_MAC_ADDR: | |
4073 | retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); | |
4074 | break; | |
4075 | case E1000_VF_SET_MULTICAST: | |
4076 | retval = igb_set_vf_multicasts(adapter, msgbuf, vf); | |
4077 | break; | |
4078 | case E1000_VF_SET_LPE: | |
4079 | retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); | |
4080 | break; | |
4081 | case E1000_VF_SET_VLAN: | |
4082 | retval = igb_set_vf_vlan(adapter, msgbuf, vf); | |
4083 | break; | |
4084 | default: | |
4085 | dev_err(&adapter->pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); | |
4086 | retval = -1; | |
4087 | break; | |
4088 | } | |
4089 | ||
4090 | /* notify the VF of the results of what it sent us */ | |
4091 | if (retval) | |
4092 | msgbuf[0] |= E1000_VT_MSGTYPE_NACK; | |
4093 | else | |
4094 | msgbuf[0] |= E1000_VT_MSGTYPE_ACK; | |
4095 | ||
4096 | msgbuf[0] |= E1000_VT_MSGTYPE_CTS; | |
4097 | ||
4098 | igb_write_mbx(hw, msgbuf, 1, vf); | |
4099 | ||
4100 | return retval; | |
4101 | } | |
4102 | ||
9d5c8243 AK |
4103 | /** |
4104 | * igb_intr_msi - Interrupt Handler | |
4105 | * @irq: interrupt number | |
4106 | * @data: pointer to a network interface device structure | |
4107 | **/ | |
4108 | static irqreturn_t igb_intr_msi(int irq, void *data) | |
4109 | { | |
4110 | struct net_device *netdev = data; | |
4111 | struct igb_adapter *adapter = netdev_priv(netdev); | |
9d5c8243 AK |
4112 | struct e1000_hw *hw = &adapter->hw; |
4113 | /* read ICR disables interrupts using IAM */ | |
4114 | u32 icr = rd32(E1000_ICR); | |
4115 | ||
6eb5a7f1 | 4116 | igb_write_itr(adapter->rx_ring); |
9d5c8243 | 4117 | |
dda0e083 AD |
4118 | if(icr & E1000_ICR_DOUTSYNC) { |
4119 | /* HW is reporting DMA is out of sync */ | |
4120 | adapter->stats.doosync++; | |
4121 | } | |
4122 | ||
9d5c8243 AK |
4123 | if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { |
4124 | hw->mac.get_link_status = 1; | |
4125 | if (!test_bit(__IGB_DOWN, &adapter->state)) | |
4126 | mod_timer(&adapter->watchdog_timer, jiffies + 1); | |
4127 | } | |
4128 | ||
288379f0 | 4129 | napi_schedule(&adapter->rx_ring[0].napi); |
9d5c8243 AK |
4130 | |
4131 | return IRQ_HANDLED; | |
4132 | } | |
4133 | ||
4134 | /** | |
4a3c6433 | 4135 | * igb_intr - Legacy Interrupt Handler |
9d5c8243 AK |
4136 | * @irq: interrupt number |
4137 | * @data: pointer to a network interface device structure | |
4138 | **/ | |
4139 | static irqreturn_t igb_intr(int irq, void *data) | |
4140 | { | |
4141 | struct net_device *netdev = data; | |
4142 | struct igb_adapter *adapter = netdev_priv(netdev); | |
9d5c8243 AK |
4143 | struct e1000_hw *hw = &adapter->hw; |
4144 | /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No | |
4145 | * need for the IMC write */ | |
4146 | u32 icr = rd32(E1000_ICR); | |
9d5c8243 AK |
4147 | if (!icr) |
4148 | return IRQ_NONE; /* Not our interrupt */ | |
4149 | ||
6eb5a7f1 | 4150 | igb_write_itr(adapter->rx_ring); |
9d5c8243 AK |
4151 | |
4152 | /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is | |
4153 | * not set, then the adapter didn't send an interrupt */ | |
4154 | if (!(icr & E1000_ICR_INT_ASSERTED)) | |
4155 | return IRQ_NONE; | |
4156 | ||
dda0e083 AD |
4157 | if(icr & E1000_ICR_DOUTSYNC) { |
4158 | /* HW is reporting DMA is out of sync */ | |
4159 | adapter->stats.doosync++; | |
4160 | } | |
4161 | ||
9d5c8243 AK |
4162 | if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { |
4163 | hw->mac.get_link_status = 1; | |
4164 | /* guard against interrupt when we're going down */ | |
4165 | if (!test_bit(__IGB_DOWN, &adapter->state)) | |
4166 | mod_timer(&adapter->watchdog_timer, jiffies + 1); | |
4167 | } | |
4168 | ||
288379f0 | 4169 | napi_schedule(&adapter->rx_ring[0].napi); |
9d5c8243 AK |
4170 | |
4171 | return IRQ_HANDLED; | |
4172 | } | |
4173 | ||
46544258 | 4174 | static inline void igb_rx_irq_enable(struct igb_ring *rx_ring) |
9d5c8243 | 4175 | { |
661086df | 4176 | struct igb_adapter *adapter = rx_ring->adapter; |
46544258 | 4177 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 | 4178 | |
46544258 AD |
4179 | if (adapter->itr_setting & 3) { |
4180 | if (adapter->num_rx_queues == 1) | |
6eb5a7f1 | 4181 | igb_set_itr(adapter); |
46544258 AD |
4182 | else |
4183 | igb_update_ring_itr(rx_ring); | |
9d5c8243 AK |
4184 | } |
4185 | ||
46544258 AD |
4186 | if (!test_bit(__IGB_DOWN, &adapter->state)) { |
4187 | if (adapter->msix_entries) | |
4188 | wr32(E1000_EIMS, rx_ring->eims_value); | |
4189 | else | |
4190 | igb_irq_enable(adapter); | |
4191 | } | |
9d5c8243 AK |
4192 | } |
4193 | ||
46544258 AD |
4194 | /** |
4195 | * igb_poll - NAPI Rx polling callback | |
4196 | * @napi: napi polling structure | |
4197 | * @budget: count of how many packets we should handle | |
4198 | **/ | |
4199 | static int igb_poll(struct napi_struct *napi, int budget) | |
9d5c8243 AK |
4200 | { |
4201 | struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi); | |
9d5c8243 AK |
4202 | int work_done = 0; |
4203 | ||
421e02f0 | 4204 | #ifdef CONFIG_IGB_DCA |
bd38e5d1 | 4205 | if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED) |
fe4506b6 JC |
4206 | igb_update_rx_dca(rx_ring); |
4207 | #endif | |
3b644cf6 | 4208 | igb_clean_rx_irq_adv(rx_ring, &work_done, budget); |
9d5c8243 | 4209 | |
46544258 AD |
4210 | if (rx_ring->buddy) { |
4211 | #ifdef CONFIG_IGB_DCA | |
bd38e5d1 | 4212 | if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED) |
46544258 AD |
4213 | igb_update_tx_dca(rx_ring->buddy); |
4214 | #endif | |
4215 | if (!igb_clean_tx_irq(rx_ring->buddy)) | |
4216 | work_done = budget; | |
4217 | } | |
4218 | ||
9d5c8243 | 4219 | /* If not enough Rx work done, exit the polling mode */ |
5e6d5b17 | 4220 | if (work_done < budget) { |
288379f0 | 4221 | napi_complete(napi); |
46544258 | 4222 | igb_rx_irq_enable(rx_ring); |
9d5c8243 AK |
4223 | } |
4224 | ||
46544258 | 4225 | return work_done; |
9d5c8243 | 4226 | } |
6d8126f9 | 4227 | |
33af6bcc PO |
4228 | /** |
4229 | * igb_hwtstamp - utility function which checks for TX time stamp | |
4230 | * @adapter: board private structure | |
4231 | * @skb: packet that was just sent | |
4232 | * | |
4233 | * If we were asked to do hardware stamping and such a time stamp is | |
4234 | * available, then it must have been for this skb here because we only | |
4235 | * allow only one such packet into the queue. | |
4236 | */ | |
4237 | static void igb_tx_hwtstamp(struct igb_adapter *adapter, struct sk_buff *skb) | |
4238 | { | |
4239 | union skb_shared_tx *shtx = skb_tx(skb); | |
4240 | struct e1000_hw *hw = &adapter->hw; | |
4241 | ||
4242 | if (unlikely(shtx->hardware)) { | |
4243 | u32 valid = rd32(E1000_TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID; | |
4244 | if (valid) { | |
4245 | u64 regval = rd32(E1000_TXSTMPL); | |
4246 | u64 ns; | |
4247 | struct skb_shared_hwtstamps shhwtstamps; | |
4248 | ||
4249 | memset(&shhwtstamps, 0, sizeof(shhwtstamps)); | |
4250 | regval |= (u64)rd32(E1000_TXSTMPH) << 32; | |
4251 | ns = timecounter_cyc2time(&adapter->clock, | |
4252 | regval); | |
4253 | timecompare_update(&adapter->compare, ns); | |
4254 | shhwtstamps.hwtstamp = ns_to_ktime(ns); | |
4255 | shhwtstamps.syststamp = | |
4256 | timecompare_transform(&adapter->compare, ns); | |
4257 | skb_tstamp_tx(skb, &shhwtstamps); | |
4258 | } | |
33af6bcc PO |
4259 | } |
4260 | } | |
4261 | ||
9d5c8243 AK |
4262 | /** |
4263 | * igb_clean_tx_irq - Reclaim resources after transmit completes | |
4264 | * @adapter: board private structure | |
4265 | * returns true if ring is completely cleaned | |
4266 | **/ | |
3b644cf6 | 4267 | static bool igb_clean_tx_irq(struct igb_ring *tx_ring) |
9d5c8243 | 4268 | { |
3b644cf6 | 4269 | struct igb_adapter *adapter = tx_ring->adapter; |
3b644cf6 | 4270 | struct net_device *netdev = adapter->netdev; |
0e014cb1 | 4271 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 AK |
4272 | struct igb_buffer *buffer_info; |
4273 | struct sk_buff *skb; | |
0e014cb1 | 4274 | union e1000_adv_tx_desc *tx_desc, *eop_desc; |
9d5c8243 | 4275 | unsigned int total_bytes = 0, total_packets = 0; |
0e014cb1 AD |
4276 | unsigned int i, eop, count = 0; |
4277 | bool cleaned = false; | |
9d5c8243 | 4278 | |
9d5c8243 | 4279 | i = tx_ring->next_to_clean; |
0e014cb1 AD |
4280 | eop = tx_ring->buffer_info[i].next_to_watch; |
4281 | eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop); | |
4282 | ||
4283 | while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) && | |
4284 | (count < tx_ring->count)) { | |
4285 | for (cleaned = false; !cleaned; count++) { | |
4286 | tx_desc = E1000_TX_DESC_ADV(*tx_ring, i); | |
9d5c8243 | 4287 | buffer_info = &tx_ring->buffer_info[i]; |
0e014cb1 | 4288 | cleaned = (i == eop); |
9d5c8243 AK |
4289 | skb = buffer_info->skb; |
4290 | ||
4291 | if (skb) { | |
4292 | unsigned int segs, bytecount; | |
4293 | /* gso_segs is currently only valid for tcp */ | |
4294 | segs = skb_shinfo(skb)->gso_segs ?: 1; | |
4295 | /* multiply data chunks by size of headers */ | |
4296 | bytecount = ((segs - 1) * skb_headlen(skb)) + | |
4297 | skb->len; | |
4298 | total_packets += segs; | |
4299 | total_bytes += bytecount; | |
33af6bcc PO |
4300 | |
4301 | igb_tx_hwtstamp(adapter, skb); | |
9d5c8243 AK |
4302 | } |
4303 | ||
4304 | igb_unmap_and_free_tx_resource(adapter, buffer_info); | |
0e014cb1 | 4305 | tx_desc->wb.status = 0; |
9d5c8243 AK |
4306 | |
4307 | i++; | |
4308 | if (i == tx_ring->count) | |
4309 | i = 0; | |
9d5c8243 | 4310 | } |
0e014cb1 AD |
4311 | eop = tx_ring->buffer_info[i].next_to_watch; |
4312 | eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop); | |
4313 | } | |
4314 | ||
9d5c8243 AK |
4315 | tx_ring->next_to_clean = i; |
4316 | ||
fc7d345d | 4317 | if (unlikely(count && |
9d5c8243 | 4318 | netif_carrier_ok(netdev) && |
c493ea45 | 4319 | igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) { |
9d5c8243 AK |
4320 | /* Make sure that anybody stopping the queue after this |
4321 | * sees the new next_to_clean. | |
4322 | */ | |
4323 | smp_mb(); | |
661086df PWJ |
4324 | if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) && |
4325 | !(test_bit(__IGB_DOWN, &adapter->state))) { | |
4326 | netif_wake_subqueue(netdev, tx_ring->queue_index); | |
4327 | ++adapter->restart_queue; | |
4328 | } | |
9d5c8243 AK |
4329 | } |
4330 | ||
4331 | if (tx_ring->detect_tx_hung) { | |
4332 | /* Detect a transmit hang in hardware, this serializes the | |
4333 | * check with the clearing of time_stamp and movement of i */ | |
4334 | tx_ring->detect_tx_hung = false; | |
4335 | if (tx_ring->buffer_info[i].time_stamp && | |
4336 | time_after(jiffies, tx_ring->buffer_info[i].time_stamp + | |
4337 | (adapter->tx_timeout_factor * HZ)) | |
4338 | && !(rd32(E1000_STATUS) & | |
4339 | E1000_STATUS_TXOFF)) { | |
4340 | ||
9d5c8243 AK |
4341 | /* detected Tx unit hang */ |
4342 | dev_err(&adapter->pdev->dev, | |
4343 | "Detected Tx Unit Hang\n" | |
2d064c06 | 4344 | " Tx Queue <%d>\n" |
9d5c8243 AK |
4345 | " TDH <%x>\n" |
4346 | " TDT <%x>\n" | |
4347 | " next_to_use <%x>\n" | |
4348 | " next_to_clean <%x>\n" | |
9d5c8243 AK |
4349 | "buffer_info[next_to_clean]\n" |
4350 | " time_stamp <%lx>\n" | |
0e014cb1 | 4351 | " next_to_watch <%x>\n" |
9d5c8243 AK |
4352 | " jiffies <%lx>\n" |
4353 | " desc.status <%x>\n", | |
2d064c06 | 4354 | tx_ring->queue_index, |
9d5c8243 AK |
4355 | readl(adapter->hw.hw_addr + tx_ring->head), |
4356 | readl(adapter->hw.hw_addr + tx_ring->tail), | |
4357 | tx_ring->next_to_use, | |
4358 | tx_ring->next_to_clean, | |
9d5c8243 | 4359 | tx_ring->buffer_info[i].time_stamp, |
0e014cb1 | 4360 | eop, |
9d5c8243 | 4361 | jiffies, |
0e014cb1 | 4362 | eop_desc->wb.status); |
661086df | 4363 | netif_stop_subqueue(netdev, tx_ring->queue_index); |
9d5c8243 AK |
4364 | } |
4365 | } | |
4366 | tx_ring->total_bytes += total_bytes; | |
4367 | tx_ring->total_packets += total_packets; | |
e21ed353 AD |
4368 | tx_ring->tx_stats.bytes += total_bytes; |
4369 | tx_ring->tx_stats.packets += total_packets; | |
9d5c8243 AK |
4370 | adapter->net_stats.tx_bytes += total_bytes; |
4371 | adapter->net_stats.tx_packets += total_packets; | |
0e014cb1 | 4372 | return (count < tx_ring->count); |
9d5c8243 AK |
4373 | } |
4374 | ||
9d5c8243 AK |
4375 | /** |
4376 | * igb_receive_skb - helper function to handle rx indications | |
eebbbdba | 4377 | * @ring: pointer to receive ring receving this packet |
9d5c8243 | 4378 | * @status: descriptor status field as written by hardware |
73cd78f1 | 4379 | * @rx_desc: receive descriptor containing vlan and type information. |
9d5c8243 AK |
4380 | * @skb: pointer to sk_buff to be indicated to stack |
4381 | **/ | |
d3352520 AD |
4382 | static void igb_receive_skb(struct igb_ring *ring, u8 status, |
4383 | union e1000_adv_rx_desc * rx_desc, | |
4384 | struct sk_buff *skb) | |
4385 | { | |
4386 | struct igb_adapter * adapter = ring->adapter; | |
4387 | bool vlan_extracted = (adapter->vlgrp && (status & E1000_RXD_STAT_VP)); | |
4388 | ||
0c8dfc83 | 4389 | skb_record_rx_queue(skb, ring->queue_index); |
5c0999b7 | 4390 | if (skb->ip_summed == CHECKSUM_UNNECESSARY) { |
d3352520 | 4391 | if (vlan_extracted) |
5c0999b7 HX |
4392 | vlan_gro_receive(&ring->napi, adapter->vlgrp, |
4393 | le16_to_cpu(rx_desc->wb.upper.vlan), | |
4394 | skb); | |
d3352520 | 4395 | else |
5c0999b7 | 4396 | napi_gro_receive(&ring->napi, skb); |
d3352520 | 4397 | } else { |
d3352520 AD |
4398 | if (vlan_extracted) |
4399 | vlan_hwaccel_receive_skb(skb, adapter->vlgrp, | |
4400 | le16_to_cpu(rx_desc->wb.upper.vlan)); | |
4401 | else | |
d3352520 | 4402 | netif_receive_skb(skb); |
d3352520 | 4403 | } |
9d5c8243 AK |
4404 | } |
4405 | ||
9d5c8243 AK |
4406 | static inline void igb_rx_checksum_adv(struct igb_adapter *adapter, |
4407 | u32 status_err, struct sk_buff *skb) | |
4408 | { | |
4409 | skb->ip_summed = CHECKSUM_NONE; | |
4410 | ||
4411 | /* Ignore Checksum bit is set or checksum is disabled through ethtool */ | |
4412 | if ((status_err & E1000_RXD_STAT_IXSM) || !adapter->rx_csum) | |
4413 | return; | |
4414 | /* TCP/UDP checksum error bit is set */ | |
4415 | if (status_err & | |
4416 | (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) { | |
4417 | /* let the stack verify checksum errors */ | |
4418 | adapter->hw_csum_err++; | |
4419 | return; | |
4420 | } | |
4421 | /* It must be a TCP or UDP packet with a valid checksum */ | |
4422 | if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)) | |
4423 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
4424 | ||
4425 | adapter->hw_csum_good++; | |
4426 | } | |
4427 | ||
3b644cf6 MW |
4428 | static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring, |
4429 | int *work_done, int budget) | |
9d5c8243 | 4430 | { |
3b644cf6 | 4431 | struct igb_adapter *adapter = rx_ring->adapter; |
9d5c8243 | 4432 | struct net_device *netdev = adapter->netdev; |
33af6bcc | 4433 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 AK |
4434 | struct pci_dev *pdev = adapter->pdev; |
4435 | union e1000_adv_rx_desc *rx_desc , *next_rxd; | |
4436 | struct igb_buffer *buffer_info , *next_buffer; | |
4437 | struct sk_buff *skb; | |
9d5c8243 AK |
4438 | bool cleaned = false; |
4439 | int cleaned_count = 0; | |
4440 | unsigned int total_bytes = 0, total_packets = 0; | |
73cd78f1 AD |
4441 | unsigned int i; |
4442 | u32 length, hlen, staterr; | |
9d5c8243 AK |
4443 | |
4444 | i = rx_ring->next_to_clean; | |
69d3ca53 | 4445 | buffer_info = &rx_ring->buffer_info[i]; |
9d5c8243 AK |
4446 | rx_desc = E1000_RX_DESC_ADV(*rx_ring, i); |
4447 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
4448 | ||
4449 | while (staterr & E1000_RXD_STAT_DD) { | |
4450 | if (*work_done >= budget) | |
4451 | break; | |
4452 | (*work_done)++; | |
9d5c8243 | 4453 | |
69d3ca53 AD |
4454 | skb = buffer_info->skb; |
4455 | prefetch(skb->data - NET_IP_ALIGN); | |
4456 | buffer_info->skb = NULL; | |
4457 | ||
4458 | i++; | |
4459 | if (i == rx_ring->count) | |
4460 | i = 0; | |
4461 | next_rxd = E1000_RX_DESC_ADV(*rx_ring, i); | |
4462 | prefetch(next_rxd); | |
4463 | next_buffer = &rx_ring->buffer_info[i]; | |
9d5c8243 AK |
4464 | |
4465 | length = le16_to_cpu(rx_desc->wb.upper.length); | |
4466 | cleaned = true; | |
4467 | cleaned_count++; | |
4468 | ||
bf36c1a0 AD |
4469 | if (!adapter->rx_ps_hdr_size) { |
4470 | pci_unmap_single(pdev, buffer_info->dma, | |
4471 | adapter->rx_buffer_len + | |
4472 | NET_IP_ALIGN, | |
4473 | PCI_DMA_FROMDEVICE); | |
4474 | skb_put(skb, length); | |
4475 | goto send_up; | |
9d5c8243 AK |
4476 | } |
4477 | ||
69d3ca53 AD |
4478 | /* HW will not DMA in data larger than the given buffer, even |
4479 | * if it parses the (NFS, of course) header to be larger. In | |
4480 | * that case, it fills the header buffer and spills the rest | |
4481 | * into the page. | |
4482 | */ | |
4483 | hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) & | |
4484 | E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT; | |
4485 | if (hlen > adapter->rx_ps_hdr_size) | |
4486 | hlen = adapter->rx_ps_hdr_size; | |
4487 | ||
bf36c1a0 AD |
4488 | if (!skb_shinfo(skb)->nr_frags) { |
4489 | pci_unmap_single(pdev, buffer_info->dma, | |
73cd78f1 | 4490 | adapter->rx_ps_hdr_size + NET_IP_ALIGN, |
bf36c1a0 AD |
4491 | PCI_DMA_FROMDEVICE); |
4492 | skb_put(skb, hlen); | |
4493 | } | |
4494 | ||
4495 | if (length) { | |
9d5c8243 | 4496 | pci_unmap_page(pdev, buffer_info->page_dma, |
bf36c1a0 | 4497 | PAGE_SIZE / 2, PCI_DMA_FROMDEVICE); |
9d5c8243 | 4498 | buffer_info->page_dma = 0; |
bf36c1a0 AD |
4499 | |
4500 | skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++, | |
4501 | buffer_info->page, | |
4502 | buffer_info->page_offset, | |
4503 | length); | |
4504 | ||
4505 | if ((adapter->rx_buffer_len > (PAGE_SIZE / 2)) || | |
4506 | (page_count(buffer_info->page) != 1)) | |
4507 | buffer_info->page = NULL; | |
4508 | else | |
4509 | get_page(buffer_info->page); | |
9d5c8243 AK |
4510 | |
4511 | skb->len += length; | |
4512 | skb->data_len += length; | |
9d5c8243 | 4513 | |
bf36c1a0 | 4514 | skb->truesize += length; |
9d5c8243 | 4515 | } |
9d5c8243 | 4516 | |
bf36c1a0 | 4517 | if (!(staterr & E1000_RXD_STAT_EOP)) { |
b2d56536 AD |
4518 | buffer_info->skb = next_buffer->skb; |
4519 | buffer_info->dma = next_buffer->dma; | |
4520 | next_buffer->skb = skb; | |
4521 | next_buffer->dma = 0; | |
bf36c1a0 AD |
4522 | goto next_desc; |
4523 | } | |
69d3ca53 | 4524 | send_up: |
33af6bcc PO |
4525 | /* |
4526 | * If this bit is set, then the RX registers contain | |
4527 | * the time stamp. No other packet will be time | |
4528 | * stamped until we read these registers, so read the | |
4529 | * registers to make them available again. Because | |
4530 | * only one packet can be time stamped at a time, we | |
4531 | * know that the register values must belong to this | |
4532 | * one here and therefore we don't need to compare | |
4533 | * any of the additional attributes stored for it. | |
4534 | * | |
4535 | * If nothing went wrong, then it should have a | |
4536 | * skb_shared_tx that we can turn into a | |
4537 | * skb_shared_hwtstamps. | |
4538 | * | |
4539 | * TODO: can time stamping be triggered (thus locking | |
4540 | * the registers) without the packet reaching this point | |
4541 | * here? In that case RX time stamping would get stuck. | |
4542 | * | |
4543 | * TODO: in "time stamp all packets" mode this bit is | |
4544 | * not set. Need a global flag for this mode and then | |
4545 | * always read the registers. Cannot be done without | |
4546 | * a race condition. | |
4547 | */ | |
4548 | if (unlikely(staterr & E1000_RXD_STAT_TS)) { | |
4549 | u64 regval; | |
4550 | u64 ns; | |
4551 | struct skb_shared_hwtstamps *shhwtstamps = | |
4552 | skb_hwtstamps(skb); | |
4553 | ||
4554 | WARN(!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID), | |
4555 | "igb: no RX time stamp available for time stamped packet"); | |
4556 | regval = rd32(E1000_RXSTMPL); | |
4557 | regval |= (u64)rd32(E1000_RXSTMPH) << 32; | |
4558 | ns = timecounter_cyc2time(&adapter->clock, regval); | |
4559 | timecompare_update(&adapter->compare, ns); | |
4560 | memset(shhwtstamps, 0, sizeof(*shhwtstamps)); | |
4561 | shhwtstamps->hwtstamp = ns_to_ktime(ns); | |
4562 | shhwtstamps->syststamp = | |
4563 | timecompare_transform(&adapter->compare, ns); | |
4564 | } | |
4565 | ||
9d5c8243 AK |
4566 | if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) { |
4567 | dev_kfree_skb_irq(skb); | |
4568 | goto next_desc; | |
4569 | } | |
9d5c8243 AK |
4570 | |
4571 | total_bytes += skb->len; | |
4572 | total_packets++; | |
4573 | ||
4574 | igb_rx_checksum_adv(adapter, staterr, skb); | |
4575 | ||
4576 | skb->protocol = eth_type_trans(skb, netdev); | |
4577 | ||
d3352520 | 4578 | igb_receive_skb(rx_ring, staterr, rx_desc, skb); |
9d5c8243 | 4579 | |
9d5c8243 AK |
4580 | next_desc: |
4581 | rx_desc->wb.upper.status_error = 0; | |
4582 | ||
4583 | /* return some buffers to hardware, one at a time is too slow */ | |
4584 | if (cleaned_count >= IGB_RX_BUFFER_WRITE) { | |
3b644cf6 | 4585 | igb_alloc_rx_buffers_adv(rx_ring, cleaned_count); |
9d5c8243 AK |
4586 | cleaned_count = 0; |
4587 | } | |
4588 | ||
4589 | /* use prefetched values */ | |
4590 | rx_desc = next_rxd; | |
4591 | buffer_info = next_buffer; | |
9d5c8243 AK |
4592 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); |
4593 | } | |
bf36c1a0 | 4594 | |
9d5c8243 | 4595 | rx_ring->next_to_clean = i; |
c493ea45 | 4596 | cleaned_count = igb_desc_unused(rx_ring); |
9d5c8243 AK |
4597 | |
4598 | if (cleaned_count) | |
3b644cf6 | 4599 | igb_alloc_rx_buffers_adv(rx_ring, cleaned_count); |
9d5c8243 AK |
4600 | |
4601 | rx_ring->total_packets += total_packets; | |
4602 | rx_ring->total_bytes += total_bytes; | |
4603 | rx_ring->rx_stats.packets += total_packets; | |
4604 | rx_ring->rx_stats.bytes += total_bytes; | |
4605 | adapter->net_stats.rx_bytes += total_bytes; | |
4606 | adapter->net_stats.rx_packets += total_packets; | |
4607 | return cleaned; | |
4608 | } | |
4609 | ||
9d5c8243 AK |
4610 | /** |
4611 | * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split | |
4612 | * @adapter: address of board private structure | |
4613 | **/ | |
3b644cf6 | 4614 | static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring, |
9d5c8243 AK |
4615 | int cleaned_count) |
4616 | { | |
3b644cf6 | 4617 | struct igb_adapter *adapter = rx_ring->adapter; |
9d5c8243 AK |
4618 | struct net_device *netdev = adapter->netdev; |
4619 | struct pci_dev *pdev = adapter->pdev; | |
4620 | union e1000_adv_rx_desc *rx_desc; | |
4621 | struct igb_buffer *buffer_info; | |
4622 | struct sk_buff *skb; | |
4623 | unsigned int i; | |
db761762 | 4624 | int bufsz; |
9d5c8243 AK |
4625 | |
4626 | i = rx_ring->next_to_use; | |
4627 | buffer_info = &rx_ring->buffer_info[i]; | |
4628 | ||
db761762 AD |
4629 | if (adapter->rx_ps_hdr_size) |
4630 | bufsz = adapter->rx_ps_hdr_size; | |
4631 | else | |
4632 | bufsz = adapter->rx_buffer_len; | |
4633 | bufsz += NET_IP_ALIGN; | |
4634 | ||
9d5c8243 AK |
4635 | while (cleaned_count--) { |
4636 | rx_desc = E1000_RX_DESC_ADV(*rx_ring, i); | |
4637 | ||
bf36c1a0 | 4638 | if (adapter->rx_ps_hdr_size && !buffer_info->page_dma) { |
9d5c8243 | 4639 | if (!buffer_info->page) { |
bf36c1a0 AD |
4640 | buffer_info->page = alloc_page(GFP_ATOMIC); |
4641 | if (!buffer_info->page) { | |
4642 | adapter->alloc_rx_buff_failed++; | |
4643 | goto no_buffers; | |
4644 | } | |
4645 | buffer_info->page_offset = 0; | |
4646 | } else { | |
4647 | buffer_info->page_offset ^= PAGE_SIZE / 2; | |
9d5c8243 AK |
4648 | } |
4649 | buffer_info->page_dma = | |
db761762 | 4650 | pci_map_page(pdev, buffer_info->page, |
bf36c1a0 AD |
4651 | buffer_info->page_offset, |
4652 | PAGE_SIZE / 2, | |
9d5c8243 AK |
4653 | PCI_DMA_FROMDEVICE); |
4654 | } | |
4655 | ||
4656 | if (!buffer_info->skb) { | |
9d5c8243 | 4657 | skb = netdev_alloc_skb(netdev, bufsz); |
9d5c8243 AK |
4658 | if (!skb) { |
4659 | adapter->alloc_rx_buff_failed++; | |
4660 | goto no_buffers; | |
4661 | } | |
4662 | ||
4663 | /* Make buffer alignment 2 beyond a 16 byte boundary | |
4664 | * this will result in a 16 byte aligned IP header after | |
4665 | * the 14 byte MAC header is removed | |
4666 | */ | |
4667 | skb_reserve(skb, NET_IP_ALIGN); | |
4668 | ||
4669 | buffer_info->skb = skb; | |
4670 | buffer_info->dma = pci_map_single(pdev, skb->data, | |
4671 | bufsz, | |
4672 | PCI_DMA_FROMDEVICE); | |
9d5c8243 AK |
4673 | } |
4674 | /* Refresh the desc even if buffer_addrs didn't change because | |
4675 | * each write-back erases this info. */ | |
4676 | if (adapter->rx_ps_hdr_size) { | |
4677 | rx_desc->read.pkt_addr = | |
4678 | cpu_to_le64(buffer_info->page_dma); | |
4679 | rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma); | |
4680 | } else { | |
4681 | rx_desc->read.pkt_addr = | |
4682 | cpu_to_le64(buffer_info->dma); | |
4683 | rx_desc->read.hdr_addr = 0; | |
4684 | } | |
4685 | ||
4686 | i++; | |
4687 | if (i == rx_ring->count) | |
4688 | i = 0; | |
4689 | buffer_info = &rx_ring->buffer_info[i]; | |
4690 | } | |
4691 | ||
4692 | no_buffers: | |
4693 | if (rx_ring->next_to_use != i) { | |
4694 | rx_ring->next_to_use = i; | |
4695 | if (i == 0) | |
4696 | i = (rx_ring->count - 1); | |
4697 | else | |
4698 | i--; | |
4699 | ||
4700 | /* Force memory writes to complete before letting h/w | |
4701 | * know there are new descriptors to fetch. (Only | |
4702 | * applicable for weak-ordered memory model archs, | |
4703 | * such as IA-64). */ | |
4704 | wmb(); | |
4705 | writel(i, adapter->hw.hw_addr + rx_ring->tail); | |
4706 | } | |
4707 | } | |
4708 | ||
4709 | /** | |
4710 | * igb_mii_ioctl - | |
4711 | * @netdev: | |
4712 | * @ifreq: | |
4713 | * @cmd: | |
4714 | **/ | |
4715 | static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) | |
4716 | { | |
4717 | struct igb_adapter *adapter = netdev_priv(netdev); | |
4718 | struct mii_ioctl_data *data = if_mii(ifr); | |
4719 | ||
4720 | if (adapter->hw.phy.media_type != e1000_media_type_copper) | |
4721 | return -EOPNOTSUPP; | |
4722 | ||
4723 | switch (cmd) { | |
4724 | case SIOCGMIIPHY: | |
4725 | data->phy_id = adapter->hw.phy.addr; | |
4726 | break; | |
4727 | case SIOCGMIIREG: | |
4728 | if (!capable(CAP_NET_ADMIN)) | |
4729 | return -EPERM; | |
f5f4cf08 AD |
4730 | if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, |
4731 | &data->val_out)) | |
9d5c8243 AK |
4732 | return -EIO; |
4733 | break; | |
4734 | case SIOCSMIIREG: | |
4735 | default: | |
4736 | return -EOPNOTSUPP; | |
4737 | } | |
4738 | return 0; | |
4739 | } | |
4740 | ||
c6cb090b PO |
4741 | /** |
4742 | * igb_hwtstamp_ioctl - control hardware time stamping | |
4743 | * @netdev: | |
4744 | * @ifreq: | |
4745 | * @cmd: | |
4746 | * | |
33af6bcc PO |
4747 | * Outgoing time stamping can be enabled and disabled. Play nice and |
4748 | * disable it when requested, although it shouldn't case any overhead | |
4749 | * when no packet needs it. At most one packet in the queue may be | |
4750 | * marked for time stamping, otherwise it would be impossible to tell | |
4751 | * for sure to which packet the hardware time stamp belongs. | |
4752 | * | |
4753 | * Incoming time stamping has to be configured via the hardware | |
4754 | * filters. Not all combinations are supported, in particular event | |
4755 | * type has to be specified. Matching the kind of event packet is | |
4756 | * not supported, with the exception of "all V2 events regardless of | |
4757 | * level 2 or 4". | |
4758 | * | |
c6cb090b PO |
4759 | **/ |
4760 | static int igb_hwtstamp_ioctl(struct net_device *netdev, | |
4761 | struct ifreq *ifr, int cmd) | |
4762 | { | |
33af6bcc PO |
4763 | struct igb_adapter *adapter = netdev_priv(netdev); |
4764 | struct e1000_hw *hw = &adapter->hw; | |
c6cb090b | 4765 | struct hwtstamp_config config; |
33af6bcc PO |
4766 | u32 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED; |
4767 | u32 tsync_rx_ctl_bit = E1000_TSYNCRXCTL_ENABLED; | |
4768 | u32 tsync_rx_ctl_type = 0; | |
4769 | u32 tsync_rx_cfg = 0; | |
4770 | int is_l4 = 0; | |
4771 | int is_l2 = 0; | |
4772 | short port = 319; /* PTP */ | |
4773 | u32 regval; | |
c6cb090b PO |
4774 | |
4775 | if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) | |
4776 | return -EFAULT; | |
4777 | ||
4778 | /* reserved for future extensions */ | |
4779 | if (config.flags) | |
4780 | return -EINVAL; | |
4781 | ||
33af6bcc PO |
4782 | switch (config.tx_type) { |
4783 | case HWTSTAMP_TX_OFF: | |
4784 | tsync_tx_ctl_bit = 0; | |
4785 | break; | |
4786 | case HWTSTAMP_TX_ON: | |
4787 | tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED; | |
4788 | break; | |
4789 | default: | |
4790 | return -ERANGE; | |
4791 | } | |
4792 | ||
4793 | switch (config.rx_filter) { | |
4794 | case HWTSTAMP_FILTER_NONE: | |
4795 | tsync_rx_ctl_bit = 0; | |
4796 | break; | |
4797 | case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: | |
4798 | case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: | |
4799 | case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: | |
4800 | case HWTSTAMP_FILTER_ALL: | |
4801 | /* | |
4802 | * register TSYNCRXCFG must be set, therefore it is not | |
4803 | * possible to time stamp both Sync and Delay_Req messages | |
4804 | * => fall back to time stamping all packets | |
4805 | */ | |
4806 | tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_ALL; | |
4807 | config.rx_filter = HWTSTAMP_FILTER_ALL; | |
4808 | break; | |
4809 | case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: | |
4810 | tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1; | |
4811 | tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE; | |
4812 | is_l4 = 1; | |
4813 | break; | |
4814 | case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: | |
4815 | tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1; | |
4816 | tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE; | |
4817 | is_l4 = 1; | |
4818 | break; | |
4819 | case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: | |
4820 | case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: | |
4821 | tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2; | |
4822 | tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE; | |
4823 | is_l2 = 1; | |
4824 | is_l4 = 1; | |
4825 | config.rx_filter = HWTSTAMP_FILTER_SOME; | |
4826 | break; | |
4827 | case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: | |
4828 | case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: | |
4829 | tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2; | |
4830 | tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE; | |
4831 | is_l2 = 1; | |
4832 | is_l4 = 1; | |
4833 | config.rx_filter = HWTSTAMP_FILTER_SOME; | |
4834 | break; | |
4835 | case HWTSTAMP_FILTER_PTP_V2_EVENT: | |
4836 | case HWTSTAMP_FILTER_PTP_V2_SYNC: | |
4837 | case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: | |
4838 | tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_EVENT_V2; | |
4839 | config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; | |
4840 | is_l2 = 1; | |
4841 | break; | |
4842 | default: | |
4843 | return -ERANGE; | |
4844 | } | |
4845 | ||
4846 | /* enable/disable TX */ | |
4847 | regval = rd32(E1000_TSYNCTXCTL); | |
4848 | regval = (regval & ~E1000_TSYNCTXCTL_ENABLED) | tsync_tx_ctl_bit; | |
4849 | wr32(E1000_TSYNCTXCTL, regval); | |
4850 | ||
4851 | /* enable/disable RX, define which PTP packets are time stamped */ | |
4852 | regval = rd32(E1000_TSYNCRXCTL); | |
4853 | regval = (regval & ~E1000_TSYNCRXCTL_ENABLED) | tsync_rx_ctl_bit; | |
4854 | regval = (regval & ~0xE) | tsync_rx_ctl_type; | |
4855 | wr32(E1000_TSYNCRXCTL, regval); | |
4856 | wr32(E1000_TSYNCRXCFG, tsync_rx_cfg); | |
4857 | ||
4858 | /* | |
4859 | * Ethertype Filter Queue Filter[0][15:0] = 0x88F7 | |
4860 | * (Ethertype to filter on) | |
4861 | * Ethertype Filter Queue Filter[0][26] = 0x1 (Enable filter) | |
4862 | * Ethertype Filter Queue Filter[0][30] = 0x1 (Enable Timestamping) | |
4863 | */ | |
4864 | wr32(E1000_ETQF0, is_l2 ? 0x440088f7 : 0); | |
4865 | ||
4866 | /* L4 Queue Filter[0]: only filter by source and destination port */ | |
4867 | wr32(E1000_SPQF0, htons(port)); | |
4868 | wr32(E1000_IMIREXT(0), is_l4 ? | |
4869 | ((1<<12) | (1<<19) /* bypass size and control flags */) : 0); | |
4870 | wr32(E1000_IMIR(0), is_l4 ? | |
4871 | (htons(port) | |
4872 | | (0<<16) /* immediate interrupt disabled */ | |
4873 | | 0 /* (1<<17) bit cleared: do not bypass | |
4874 | destination port check */) | |
4875 | : 0); | |
4876 | wr32(E1000_FTQF0, is_l4 ? | |
4877 | (0x11 /* UDP */ | |
4878 | | (1<<15) /* VF not compared */ | |
4879 | | (1<<27) /* Enable Timestamping */ | |
4880 | | (7<<28) /* only source port filter enabled, | |
4881 | source/target address and protocol | |
4882 | masked */) | |
4883 | : ((1<<15) | (15<<28) /* all mask bits set = filter not | |
4884 | enabled */)); | |
4885 | ||
4886 | wrfl(); | |
4887 | ||
4888 | adapter->hwtstamp_config = config; | |
4889 | ||
4890 | /* clear TX/RX time stamp registers, just to be sure */ | |
4891 | regval = rd32(E1000_TXSTMPH); | |
4892 | regval = rd32(E1000_RXSTMPH); | |
c6cb090b | 4893 | |
33af6bcc PO |
4894 | return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? |
4895 | -EFAULT : 0; | |
c6cb090b PO |
4896 | } |
4897 | ||
9d5c8243 AK |
4898 | /** |
4899 | * igb_ioctl - | |
4900 | * @netdev: | |
4901 | * @ifreq: | |
4902 | * @cmd: | |
4903 | **/ | |
4904 | static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) | |
4905 | { | |
4906 | switch (cmd) { | |
4907 | case SIOCGMIIPHY: | |
4908 | case SIOCGMIIREG: | |
4909 | case SIOCSMIIREG: | |
4910 | return igb_mii_ioctl(netdev, ifr, cmd); | |
c6cb090b PO |
4911 | case SIOCSHWTSTAMP: |
4912 | return igb_hwtstamp_ioctl(netdev, ifr, cmd); | |
9d5c8243 AK |
4913 | default: |
4914 | return -EOPNOTSUPP; | |
4915 | } | |
4916 | } | |
4917 | ||
4918 | static void igb_vlan_rx_register(struct net_device *netdev, | |
4919 | struct vlan_group *grp) | |
4920 | { | |
4921 | struct igb_adapter *adapter = netdev_priv(netdev); | |
4922 | struct e1000_hw *hw = &adapter->hw; | |
4923 | u32 ctrl, rctl; | |
4924 | ||
4925 | igb_irq_disable(adapter); | |
4926 | adapter->vlgrp = grp; | |
4927 | ||
4928 | if (grp) { | |
4929 | /* enable VLAN tag insert/strip */ | |
4930 | ctrl = rd32(E1000_CTRL); | |
4931 | ctrl |= E1000_CTRL_VME; | |
4932 | wr32(E1000_CTRL, ctrl); | |
4933 | ||
4934 | /* enable VLAN receive filtering */ | |
4935 | rctl = rd32(E1000_RCTL); | |
9d5c8243 AK |
4936 | rctl &= ~E1000_RCTL_CFIEN; |
4937 | wr32(E1000_RCTL, rctl); | |
4938 | igb_update_mng_vlan(adapter); | |
9d5c8243 AK |
4939 | } else { |
4940 | /* disable VLAN tag insert/strip */ | |
4941 | ctrl = rd32(E1000_CTRL); | |
4942 | ctrl &= ~E1000_CTRL_VME; | |
4943 | wr32(E1000_CTRL, ctrl); | |
4944 | ||
9d5c8243 AK |
4945 | if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) { |
4946 | igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id); | |
4947 | adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; | |
4948 | } | |
9d5c8243 AK |
4949 | } |
4950 | ||
e1739522 AD |
4951 | igb_rlpml_set(adapter); |
4952 | ||
9d5c8243 AK |
4953 | if (!test_bit(__IGB_DOWN, &adapter->state)) |
4954 | igb_irq_enable(adapter); | |
4955 | } | |
4956 | ||
4957 | static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid) | |
4958 | { | |
4959 | struct igb_adapter *adapter = netdev_priv(netdev); | |
4960 | struct e1000_hw *hw = &adapter->hw; | |
4ae196df | 4961 | int pf_id = adapter->vfs_allocated_count; |
9d5c8243 | 4962 | |
28b0759c | 4963 | if ((hw->mng_cookie.status & |
9d5c8243 AK |
4964 | E1000_MNG_DHCP_COOKIE_STATUS_VLAN) && |
4965 | (vid == adapter->mng_vlan_id)) | |
4966 | return; | |
4ae196df AD |
4967 | |
4968 | /* add vid to vlvf if sr-iov is enabled, | |
4969 | * if that fails add directly to filter table */ | |
4970 | if (igb_vlvf_set(adapter, vid, true, pf_id)) | |
4971 | igb_vfta_set(hw, vid, true); | |
4972 | ||
9d5c8243 AK |
4973 | } |
4974 | ||
4975 | static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) | |
4976 | { | |
4977 | struct igb_adapter *adapter = netdev_priv(netdev); | |
4978 | struct e1000_hw *hw = &adapter->hw; | |
4ae196df | 4979 | int pf_id = adapter->vfs_allocated_count; |
9d5c8243 AK |
4980 | |
4981 | igb_irq_disable(adapter); | |
4982 | vlan_group_set_device(adapter->vlgrp, vid, NULL); | |
4983 | ||
4984 | if (!test_bit(__IGB_DOWN, &adapter->state)) | |
4985 | igb_irq_enable(adapter); | |
4986 | ||
4987 | if ((adapter->hw.mng_cookie.status & | |
4988 | E1000_MNG_DHCP_COOKIE_STATUS_VLAN) && | |
4989 | (vid == adapter->mng_vlan_id)) { | |
4990 | /* release control to f/w */ | |
4991 | igb_release_hw_control(adapter); | |
4992 | return; | |
4993 | } | |
4994 | ||
4ae196df AD |
4995 | /* remove vid from vlvf if sr-iov is enabled, |
4996 | * if not in vlvf remove from vfta */ | |
4997 | if (igb_vlvf_set(adapter, vid, false, pf_id)) | |
4998 | igb_vfta_set(hw, vid, false); | |
9d5c8243 AK |
4999 | } |
5000 | ||
5001 | static void igb_restore_vlan(struct igb_adapter *adapter) | |
5002 | { | |
5003 | igb_vlan_rx_register(adapter->netdev, adapter->vlgrp); | |
5004 | ||
5005 | if (adapter->vlgrp) { | |
5006 | u16 vid; | |
5007 | for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) { | |
5008 | if (!vlan_group_get_device(adapter->vlgrp, vid)) | |
5009 | continue; | |
5010 | igb_vlan_rx_add_vid(adapter->netdev, vid); | |
5011 | } | |
5012 | } | |
5013 | } | |
5014 | ||
5015 | int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx) | |
5016 | { | |
5017 | struct e1000_mac_info *mac = &adapter->hw.mac; | |
5018 | ||
5019 | mac->autoneg = 0; | |
5020 | ||
5021 | /* Fiber NICs only allow 1000 gbps Full duplex */ | |
5022 | if ((adapter->hw.phy.media_type == e1000_media_type_fiber) && | |
5023 | spddplx != (SPEED_1000 + DUPLEX_FULL)) { | |
5024 | dev_err(&adapter->pdev->dev, | |
5025 | "Unsupported Speed/Duplex configuration\n"); | |
5026 | return -EINVAL; | |
5027 | } | |
5028 | ||
5029 | switch (spddplx) { | |
5030 | case SPEED_10 + DUPLEX_HALF: | |
5031 | mac->forced_speed_duplex = ADVERTISE_10_HALF; | |
5032 | break; | |
5033 | case SPEED_10 + DUPLEX_FULL: | |
5034 | mac->forced_speed_duplex = ADVERTISE_10_FULL; | |
5035 | break; | |
5036 | case SPEED_100 + DUPLEX_HALF: | |
5037 | mac->forced_speed_duplex = ADVERTISE_100_HALF; | |
5038 | break; | |
5039 | case SPEED_100 + DUPLEX_FULL: | |
5040 | mac->forced_speed_duplex = ADVERTISE_100_FULL; | |
5041 | break; | |
5042 | case SPEED_1000 + DUPLEX_FULL: | |
5043 | mac->autoneg = 1; | |
5044 | adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; | |
5045 | break; | |
5046 | case SPEED_1000 + DUPLEX_HALF: /* not supported */ | |
5047 | default: | |
5048 | dev_err(&adapter->pdev->dev, | |
5049 | "Unsupported Speed/Duplex configuration\n"); | |
5050 | return -EINVAL; | |
5051 | } | |
5052 | return 0; | |
5053 | } | |
5054 | ||
9d5c8243 AK |
5055 | static int igb_suspend(struct pci_dev *pdev, pm_message_t state) |
5056 | { | |
5057 | struct net_device *netdev = pci_get_drvdata(pdev); | |
5058 | struct igb_adapter *adapter = netdev_priv(netdev); | |
5059 | struct e1000_hw *hw = &adapter->hw; | |
2d064c06 | 5060 | u32 ctrl, rctl, status; |
9d5c8243 AK |
5061 | u32 wufc = adapter->wol; |
5062 | #ifdef CONFIG_PM | |
5063 | int retval = 0; | |
5064 | #endif | |
5065 | ||
5066 | netif_device_detach(netdev); | |
5067 | ||
a88f10ec AD |
5068 | if (netif_running(netdev)) |
5069 | igb_close(netdev); | |
5070 | ||
5071 | igb_reset_interrupt_capability(adapter); | |
5072 | ||
5073 | igb_free_queues(adapter); | |
9d5c8243 AK |
5074 | |
5075 | #ifdef CONFIG_PM | |
5076 | retval = pci_save_state(pdev); | |
5077 | if (retval) | |
5078 | return retval; | |
5079 | #endif | |
5080 | ||
5081 | status = rd32(E1000_STATUS); | |
5082 | if (status & E1000_STATUS_LU) | |
5083 | wufc &= ~E1000_WUFC_LNKC; | |
5084 | ||
5085 | if (wufc) { | |
5086 | igb_setup_rctl(adapter); | |
5087 | igb_set_multi(netdev); | |
5088 | ||
5089 | /* turn on all-multi mode if wake on multicast is enabled */ | |
5090 | if (wufc & E1000_WUFC_MC) { | |
5091 | rctl = rd32(E1000_RCTL); | |
5092 | rctl |= E1000_RCTL_MPE; | |
5093 | wr32(E1000_RCTL, rctl); | |
5094 | } | |
5095 | ||
5096 | ctrl = rd32(E1000_CTRL); | |
5097 | /* advertise wake from D3Cold */ | |
5098 | #define E1000_CTRL_ADVD3WUC 0x00100000 | |
5099 | /* phy power management enable */ | |
5100 | #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 | |
5101 | ctrl |= E1000_CTRL_ADVD3WUC; | |
5102 | wr32(E1000_CTRL, ctrl); | |
5103 | ||
9d5c8243 AK |
5104 | /* Allow time for pending master requests to run */ |
5105 | igb_disable_pcie_master(&adapter->hw); | |
5106 | ||
5107 | wr32(E1000_WUC, E1000_WUC_PME_EN); | |
5108 | wr32(E1000_WUFC, wufc); | |
9d5c8243 AK |
5109 | } else { |
5110 | wr32(E1000_WUC, 0); | |
5111 | wr32(E1000_WUFC, 0); | |
9d5c8243 AK |
5112 | } |
5113 | ||
2d064c06 AD |
5114 | /* make sure adapter isn't asleep if manageability/wol is enabled */ |
5115 | if (wufc || adapter->en_mng_pt) { | |
9d5c8243 AK |
5116 | pci_enable_wake(pdev, PCI_D3hot, 1); |
5117 | pci_enable_wake(pdev, PCI_D3cold, 1); | |
2d064c06 AD |
5118 | } else { |
5119 | igb_shutdown_fiber_serdes_link_82575(hw); | |
5120 | pci_enable_wake(pdev, PCI_D3hot, 0); | |
5121 | pci_enable_wake(pdev, PCI_D3cold, 0); | |
9d5c8243 AK |
5122 | } |
5123 | ||
5124 | /* Release control of h/w to f/w. If f/w is AMT enabled, this | |
5125 | * would have already happened in close and is redundant. */ | |
5126 | igb_release_hw_control(adapter); | |
5127 | ||
5128 | pci_disable_device(pdev); | |
5129 | ||
5130 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); | |
5131 | ||
5132 | return 0; | |
5133 | } | |
5134 | ||
5135 | #ifdef CONFIG_PM | |
5136 | static int igb_resume(struct pci_dev *pdev) | |
5137 | { | |
5138 | struct net_device *netdev = pci_get_drvdata(pdev); | |
5139 | struct igb_adapter *adapter = netdev_priv(netdev); | |
5140 | struct e1000_hw *hw = &adapter->hw; | |
5141 | u32 err; | |
5142 | ||
5143 | pci_set_power_state(pdev, PCI_D0); | |
5144 | pci_restore_state(pdev); | |
42bfd33a | 5145 | |
aed5dec3 | 5146 | err = pci_enable_device_mem(pdev); |
9d5c8243 AK |
5147 | if (err) { |
5148 | dev_err(&pdev->dev, | |
5149 | "igb: Cannot enable PCI device from suspend\n"); | |
5150 | return err; | |
5151 | } | |
5152 | pci_set_master(pdev); | |
5153 | ||
5154 | pci_enable_wake(pdev, PCI_D3hot, 0); | |
5155 | pci_enable_wake(pdev, PCI_D3cold, 0); | |
5156 | ||
a88f10ec AD |
5157 | igb_set_interrupt_capability(adapter); |
5158 | ||
5159 | if (igb_alloc_queues(adapter)) { | |
5160 | dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); | |
5161 | return -ENOMEM; | |
9d5c8243 AK |
5162 | } |
5163 | ||
5164 | /* e1000_power_up_phy(adapter); */ | |
5165 | ||
5166 | igb_reset(adapter); | |
a8564f03 AD |
5167 | |
5168 | /* let the f/w know that the h/w is now under the control of the | |
5169 | * driver. */ | |
5170 | igb_get_hw_control(adapter); | |
5171 | ||
9d5c8243 AK |
5172 | wr32(E1000_WUS, ~0); |
5173 | ||
a88f10ec AD |
5174 | if (netif_running(netdev)) { |
5175 | err = igb_open(netdev); | |
5176 | if (err) | |
5177 | return err; | |
5178 | } | |
9d5c8243 AK |
5179 | |
5180 | netif_device_attach(netdev); | |
5181 | ||
9d5c8243 AK |
5182 | return 0; |
5183 | } | |
5184 | #endif | |
5185 | ||
5186 | static void igb_shutdown(struct pci_dev *pdev) | |
5187 | { | |
5188 | igb_suspend(pdev, PMSG_SUSPEND); | |
5189 | } | |
5190 | ||
5191 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
5192 | /* | |
5193 | * Polling 'interrupt' - used by things like netconsole to send skbs | |
5194 | * without having to re-enable interrupts. It's not called while | |
5195 | * the interrupt routine is executing. | |
5196 | */ | |
5197 | static void igb_netpoll(struct net_device *netdev) | |
5198 | { | |
5199 | struct igb_adapter *adapter = netdev_priv(netdev); | |
eebbbdba | 5200 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 | 5201 | int i; |
9d5c8243 | 5202 | |
eebbbdba AD |
5203 | if (!adapter->msix_entries) { |
5204 | igb_irq_disable(adapter); | |
5205 | napi_schedule(&adapter->rx_ring[0].napi); | |
5206 | return; | |
5207 | } | |
9d5c8243 | 5208 | |
eebbbdba AD |
5209 | for (i = 0; i < adapter->num_tx_queues; i++) { |
5210 | struct igb_ring *tx_ring = &adapter->tx_ring[i]; | |
5211 | wr32(E1000_EIMC, tx_ring->eims_value); | |
5212 | igb_clean_tx_irq(tx_ring); | |
5213 | wr32(E1000_EIMS, tx_ring->eims_value); | |
5214 | } | |
9d5c8243 | 5215 | |
eebbbdba AD |
5216 | for (i = 0; i < adapter->num_rx_queues; i++) { |
5217 | struct igb_ring *rx_ring = &adapter->rx_ring[i]; | |
5218 | wr32(E1000_EIMC, rx_ring->eims_value); | |
5219 | napi_schedule(&rx_ring->napi); | |
5220 | } | |
9d5c8243 AK |
5221 | } |
5222 | #endif /* CONFIG_NET_POLL_CONTROLLER */ | |
5223 | ||
5224 | /** | |
5225 | * igb_io_error_detected - called when PCI error is detected | |
5226 | * @pdev: Pointer to PCI device | |
5227 | * @state: The current pci connection state | |
5228 | * | |
5229 | * This function is called after a PCI bus error affecting | |
5230 | * this device has been detected. | |
5231 | */ | |
5232 | static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, | |
5233 | pci_channel_state_t state) | |
5234 | { | |
5235 | struct net_device *netdev = pci_get_drvdata(pdev); | |
5236 | struct igb_adapter *adapter = netdev_priv(netdev); | |
5237 | ||
5238 | netif_device_detach(netdev); | |
5239 | ||
5240 | if (netif_running(netdev)) | |
5241 | igb_down(adapter); | |
5242 | pci_disable_device(pdev); | |
5243 | ||
5244 | /* Request a slot slot reset. */ | |
5245 | return PCI_ERS_RESULT_NEED_RESET; | |
5246 | } | |
5247 | ||
5248 | /** | |
5249 | * igb_io_slot_reset - called after the pci bus has been reset. | |
5250 | * @pdev: Pointer to PCI device | |
5251 | * | |
5252 | * Restart the card from scratch, as if from a cold-boot. Implementation | |
5253 | * resembles the first-half of the igb_resume routine. | |
5254 | */ | |
5255 | static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) | |
5256 | { | |
5257 | struct net_device *netdev = pci_get_drvdata(pdev); | |
5258 | struct igb_adapter *adapter = netdev_priv(netdev); | |
5259 | struct e1000_hw *hw = &adapter->hw; | |
40a914fa | 5260 | pci_ers_result_t result; |
42bfd33a | 5261 | int err; |
9d5c8243 | 5262 | |
aed5dec3 | 5263 | if (pci_enable_device_mem(pdev)) { |
9d5c8243 AK |
5264 | dev_err(&pdev->dev, |
5265 | "Cannot re-enable PCI device after reset.\n"); | |
40a914fa AD |
5266 | result = PCI_ERS_RESULT_DISCONNECT; |
5267 | } else { | |
5268 | pci_set_master(pdev); | |
5269 | pci_restore_state(pdev); | |
9d5c8243 | 5270 | |
40a914fa AD |
5271 | pci_enable_wake(pdev, PCI_D3hot, 0); |
5272 | pci_enable_wake(pdev, PCI_D3cold, 0); | |
9d5c8243 | 5273 | |
40a914fa AD |
5274 | igb_reset(adapter); |
5275 | wr32(E1000_WUS, ~0); | |
5276 | result = PCI_ERS_RESULT_RECOVERED; | |
5277 | } | |
9d5c8243 | 5278 | |
ea943d41 JK |
5279 | err = pci_cleanup_aer_uncorrect_error_status(pdev); |
5280 | if (err) { | |
5281 | dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status " | |
5282 | "failed 0x%0x\n", err); | |
5283 | /* non-fatal, continue */ | |
5284 | } | |
40a914fa AD |
5285 | |
5286 | return result; | |
9d5c8243 AK |
5287 | } |
5288 | ||
5289 | /** | |
5290 | * igb_io_resume - called when traffic can start flowing again. | |
5291 | * @pdev: Pointer to PCI device | |
5292 | * | |
5293 | * This callback is called when the error recovery driver tells us that | |
5294 | * its OK to resume normal operation. Implementation resembles the | |
5295 | * second-half of the igb_resume routine. | |
5296 | */ | |
5297 | static void igb_io_resume(struct pci_dev *pdev) | |
5298 | { | |
5299 | struct net_device *netdev = pci_get_drvdata(pdev); | |
5300 | struct igb_adapter *adapter = netdev_priv(netdev); | |
5301 | ||
9d5c8243 AK |
5302 | if (netif_running(netdev)) { |
5303 | if (igb_up(adapter)) { | |
5304 | dev_err(&pdev->dev, "igb_up failed after reset\n"); | |
5305 | return; | |
5306 | } | |
5307 | } | |
5308 | ||
5309 | netif_device_attach(netdev); | |
5310 | ||
5311 | /* let the f/w know that the h/w is now under the control of the | |
5312 | * driver. */ | |
5313 | igb_get_hw_control(adapter); | |
9d5c8243 AK |
5314 | } |
5315 | ||
e1739522 AD |
5316 | static inline void igb_set_vmolr(struct e1000_hw *hw, int vfn) |
5317 | { | |
5318 | u32 reg_data; | |
5319 | ||
5320 | reg_data = rd32(E1000_VMOLR(vfn)); | |
5321 | reg_data |= E1000_VMOLR_BAM | /* Accept broadcast */ | |
5322 | E1000_VMOLR_ROPE | /* Accept packets matched in UTA */ | |
5323 | E1000_VMOLR_ROMPE | /* Accept packets matched in MTA */ | |
5324 | E1000_VMOLR_AUPE | /* Accept untagged packets */ | |
5325 | E1000_VMOLR_STRVLAN; /* Strip vlan tags */ | |
5326 | wr32(E1000_VMOLR(vfn), reg_data); | |
5327 | } | |
5328 | ||
4ae196df AD |
5329 | static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, |
5330 | int vfn) | |
e1739522 AD |
5331 | { |
5332 | struct e1000_hw *hw = &adapter->hw; | |
5333 | u32 vmolr; | |
5334 | ||
5335 | vmolr = rd32(E1000_VMOLR(vfn)); | |
5336 | vmolr &= ~E1000_VMOLR_RLPML_MASK; | |
5337 | vmolr |= size | E1000_VMOLR_LPE; | |
5338 | wr32(E1000_VMOLR(vfn), vmolr); | |
4ae196df AD |
5339 | |
5340 | return 0; | |
e1739522 AD |
5341 | } |
5342 | ||
5343 | static inline void igb_set_rah_pool(struct e1000_hw *hw, int pool, int entry) | |
5344 | { | |
5345 | u32 reg_data; | |
5346 | ||
5347 | reg_data = rd32(E1000_RAH(entry)); | |
5348 | reg_data &= ~E1000_RAH_POOL_MASK; | |
5349 | reg_data |= E1000_RAH_POOL_1 << pool;; | |
5350 | wr32(E1000_RAH(entry), reg_data); | |
5351 | } | |
5352 | ||
5353 | static void igb_set_mc_list_pools(struct igb_adapter *adapter, | |
5354 | int entry_count, u16 total_rar_filters) | |
5355 | { | |
5356 | struct e1000_hw *hw = &adapter->hw; | |
5357 | int i = adapter->vfs_allocated_count + 1; | |
5358 | ||
5359 | if ((i + entry_count) < total_rar_filters) | |
5360 | total_rar_filters = i + entry_count; | |
5361 | ||
5362 | for (; i < total_rar_filters; i++) | |
5363 | igb_set_rah_pool(hw, adapter->vfs_allocated_count, i); | |
5364 | } | |
5365 | ||
4ae196df AD |
5366 | static int igb_set_vf_mac(struct igb_adapter *adapter, |
5367 | int vf, unsigned char *mac_addr) | |
5368 | { | |
5369 | struct e1000_hw *hw = &adapter->hw; | |
5370 | int rar_entry = vf + 1; /* VF MAC addresses start at entry 1 */ | |
5371 | ||
5372 | igb_rar_set(hw, mac_addr, rar_entry); | |
5373 | ||
37680117 | 5374 | memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN); |
4ae196df AD |
5375 | |
5376 | igb_set_rah_pool(hw, vf, rar_entry); | |
5377 | ||
5378 | return 0; | |
5379 | } | |
5380 | ||
5381 | static void igb_vmm_control(struct igb_adapter *adapter) | |
5382 | { | |
5383 | struct e1000_hw *hw = &adapter->hw; | |
5384 | u32 reg_data; | |
5385 | ||
5386 | if (!adapter->vfs_allocated_count) | |
5387 | return; | |
5388 | ||
5389 | /* VF's need PF reset indication before they | |
5390 | * can send/receive mail */ | |
5391 | reg_data = rd32(E1000_CTRL_EXT); | |
5392 | reg_data |= E1000_CTRL_EXT_PFRSTD; | |
5393 | wr32(E1000_CTRL_EXT, reg_data); | |
5394 | ||
5395 | igb_vmdq_set_loopback_pf(hw, true); | |
5396 | igb_vmdq_set_replication_pf(hw, true); | |
5397 | } | |
5398 | ||
37680117 AD |
5399 | #ifdef CONFIG_PCI_IOV |
5400 | static ssize_t igb_show_num_vfs(struct device *dev, | |
5401 | struct device_attribute *attr, char *buf) | |
5402 | { | |
5403 | struct igb_adapter *adapter = netdev_priv(to_net_dev(dev)); | |
5404 | ||
5405 | return sprintf(buf, "%d\n", adapter->vfs_allocated_count); | |
5406 | } | |
5407 | ||
5408 | static ssize_t igb_set_num_vfs(struct device *dev, | |
5409 | struct device_attribute *attr, | |
5410 | const char *buf, size_t count) | |
5411 | { | |
5412 | struct net_device *netdev = to_net_dev(dev); | |
5413 | struct igb_adapter *adapter = netdev_priv(netdev); | |
5414 | struct e1000_hw *hw = &adapter->hw; | |
5415 | struct pci_dev *pdev = adapter->pdev; | |
5416 | unsigned int num_vfs, i; | |
5417 | unsigned char mac_addr[ETH_ALEN]; | |
5418 | int err; | |
5419 | ||
5420 | sscanf(buf, "%u", &num_vfs); | |
5421 | ||
5422 | if (num_vfs > 7) | |
5423 | num_vfs = 7; | |
5424 | ||
5425 | /* value unchanged do nothing */ | |
5426 | if (num_vfs == adapter->vfs_allocated_count) | |
5427 | return count; | |
5428 | ||
5429 | if (netdev->flags & IFF_UP) | |
5430 | igb_close(netdev); | |
5431 | ||
5432 | igb_reset_interrupt_capability(adapter); | |
5433 | igb_free_queues(adapter); | |
5434 | adapter->tx_ring = NULL; | |
5435 | adapter->rx_ring = NULL; | |
5436 | adapter->vfs_allocated_count = 0; | |
5437 | ||
5438 | /* reclaim resources allocated to VFs since we are changing count */ | |
5439 | if (adapter->vf_data) { | |
5440 | /* disable iov and allow time for transactions to clear */ | |
5441 | pci_disable_sriov(pdev); | |
5442 | msleep(500); | |
5443 | ||
5444 | kfree(adapter->vf_data); | |
5445 | adapter->vf_data = NULL; | |
5446 | wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); | |
5447 | msleep(100); | |
5448 | dev_info(&pdev->dev, "IOV Disabled\n"); | |
5449 | } | |
5450 | ||
5451 | if (num_vfs) { | |
5452 | adapter->vf_data = kcalloc(num_vfs, | |
5453 | sizeof(struct vf_data_storage), | |
5454 | GFP_KERNEL); | |
5455 | if (!adapter->vf_data) { | |
5456 | dev_err(&pdev->dev, "Could not allocate VF private " | |
5457 | "data - IOV enable failed\n"); | |
5458 | } else { | |
5459 | err = pci_enable_sriov(pdev, num_vfs); | |
5460 | if (!err) { | |
5461 | adapter->vfs_allocated_count = num_vfs; | |
5462 | dev_info(&pdev->dev, "%d vfs allocated\n", num_vfs); | |
5463 | for (i = 0; i < adapter->vfs_allocated_count; i++) { | |
5464 | random_ether_addr(mac_addr); | |
5465 | igb_set_vf_mac(adapter, i, mac_addr); | |
5466 | } | |
5467 | } else { | |
5468 | kfree(adapter->vf_data); | |
5469 | adapter->vf_data = NULL; | |
5470 | } | |
5471 | } | |
5472 | } | |
5473 | ||
5474 | igb_set_interrupt_capability(adapter); | |
5475 | igb_alloc_queues(adapter); | |
5476 | igb_reset(adapter); | |
5477 | ||
5478 | if (netdev->flags & IFF_UP) | |
5479 | igb_open(netdev); | |
5480 | ||
5481 | return count; | |
5482 | } | |
5483 | #endif /* CONFIG_PCI_IOV */ | |
9d5c8243 | 5484 | /* igb_main.c */ |