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9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
86d5d38f 4 Copyright(c) 2007-2009 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/module.h>
29#include <linux/types.h>
30#include <linux/init.h>
31#include <linux/vmalloc.h>
32#include <linux/pagemap.h>
33#include <linux/netdevice.h>
9d5c8243
AK		 34#include <linux/ipv6.h>
35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
c6cb090b 37#include <linux/net_tstamp.h>
9d5c8243
AK		 38#include <linux/mii.h>
39#include <linux/ethtool.h>
40#include <linux/if_vlan.h>
41#include <linux/pci.h>
c54106bb 42#include <linux/pci-aspm.h>
9d5c8243
AK		 43#include <linux/delay.h>
44#include <linux/interrupt.h>
45#include <linux/if_ether.h>
40a914fa 46#include <linux/aer.h>
421e02f0 47#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 48#include <linux/dca.h>
49#endif
9d5c8243
AK		 50#include "igb.h"
51
86d5d38f 52#define DRV_VERSION "1.3.16-k2"
9d5c8243
AK		 53char igb_driver_name[] = "igb";
54char igb_driver_version[] = DRV_VERSION;
55static const char igb_driver_string[] =
56 "Intel(R) Gigabit Ethernet Network Driver";
86d5d38f 57static const char igb_copyright[] = "Copyright (c) 2007-2009 Intel Corporation.";
9d5c8243 58
9d5c8243
AK		 59static const struct e1000_info *igb_info_tbl[] = {
60 [board_82575] = &e1000_82575_info,
61};
62
63static struct pci_device_id igb_pci_tbl[] = {
2d064c06 64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
747d49ba 66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
2d064c06
AD		 67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
c8ea5ea9 70 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 71 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
72 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
73 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
74 /* required last entry */
75 {0, }
76};
77
78MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
79
80void igb_reset(struct igb_adapter *);
81static int igb_setup_all_tx_resources(struct igb_adapter *);
82static int igb_setup_all_rx_resources(struct igb_adapter *);
83static void igb_free_all_tx_resources(struct igb_adapter *);
84static void igb_free_all_rx_resources(struct igb_adapter *);
9d5c8243
AK		 85void igb_update_stats(struct igb_adapter *);
86static int igb_probe(struct pci_dev *, const struct pci_device_id *);
87static void __devexit igb_remove(struct pci_dev *pdev);
88static int igb_sw_init(struct igb_adapter *);
89static int igb_open(struct net_device *);
90static int igb_close(struct net_device *);
91static void igb_configure_tx(struct igb_adapter *);
92static void igb_configure_rx(struct igb_adapter *);
85b430b4 93static void igb_setup_tctl(struct igb_adapter *);
9d5c8243
AK		 94static void igb_setup_rctl(struct igb_adapter *);
95static void igb_clean_all_tx_rings(struct igb_adapter *);
96static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 97static void igb_clean_tx_ring(struct igb_ring *);
98static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 99static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 100static void igb_update_phy_info(unsigned long);
101static void igb_watchdog(unsigned long);
102static void igb_watchdog_task(struct work_struct *);
3b29a56d
SH		 103static netdev_tx_t igb_xmit_frame_ring_adv(struct sk_buff *,
104 struct net_device *,
105 struct igb_ring *);
106static netdev_tx_t igb_xmit_frame_adv(struct sk_buff *skb,
107 struct net_device *);
9d5c8243
AK		 108static struct net_device_stats *igb_get_stats(struct net_device *);
109static int igb_change_mtu(struct net_device *, int);
110static int igb_set_mac(struct net_device *, void *);
68d480c4 111static void igb_set_uta(struct igb_adapter *adapter);
9d5c8243
AK		 112static irqreturn_t igb_intr(int irq, void *);
113static irqreturn_t igb_intr_msi(int irq, void *);
114static irqreturn_t igb_msix_other(int irq, void *);
047e0030 115static irqreturn_t igb_msix_ring(int irq, void *);
421e02f0 116#ifdef CONFIG_IGB_DCA
047e0030 117static void igb_update_dca(struct igb_q_vector *);
fe4506b6 118static void igb_setup_dca(struct igb_adapter *);
421e02f0 119#endif /* CONFIG_IGB_DCA */
047e0030 120static bool igb_clean_tx_irq(struct igb_q_vector *);
661086df 121static int igb_poll(struct napi_struct *, int);
047e0030 122static bool igb_clean_rx_irq_adv(struct igb_q_vector *, int *, int);
3b644cf6 123static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
9d5c8243
AK		 124static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
125static void igb_tx_timeout(struct net_device *);
126static void igb_reset_task(struct work_struct *);
127static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
128static void igb_vlan_rx_add_vid(struct net_device *, u16);
129static void igb_vlan_rx_kill_vid(struct net_device *, u16);
130static void igb_restore_vlan(struct igb_adapter *);
26ad9178 131static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
4ae196df
AD		 132static void igb_ping_all_vfs(struct igb_adapter *);
133static void igb_msg_task(struct igb_adapter *);
134static int igb_rcv_msg_from_vf(struct igb_adapter *, u32);
4ae196df 135static void igb_vmm_control(struct igb_adapter *);
4ae196df
AD		 136static int igb_set_vf_mac(struct igb_adapter *adapter, int, unsigned char *);
137static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
9d5c8243 138
c8159b2d
ED		 139static inline void igb_set_vmolr(struct e1000_hw *hw, int vfn)
140{
141 u32 reg_data;
142
143 reg_data = rd32(E1000_VMOLR(vfn));
144 reg_data |= E1000_VMOLR_BAM | /* Accept broadcast */
c8159b2d
ED		 145 E1000_VMOLR_ROMPE | /* Accept packets matched in MTA */
146 E1000_VMOLR_AUPE | /* Accept untagged packets */
147 E1000_VMOLR_STRVLAN; /* Strip vlan tags */
148 wr32(E1000_VMOLR(vfn), reg_data);
149}
150
151static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
152 int vfn)
153{
154 struct e1000_hw *hw = &adapter->hw;
155 u32 vmolr;
156
ae641bdc
AD		 157 /* if it isn't the PF check to see if VFs are enabled and
158 * increase the size to support vlan tags */
159 if (vfn < adapter->vfs_allocated_count &&
160 adapter->vf_data[vfn].vlans_enabled)
161 size += VLAN_TAG_SIZE;
162
c8159b2d
ED		 163 vmolr = rd32(E1000_VMOLR(vfn));
164 vmolr &= ~E1000_VMOLR_RLPML_MASK;
165 vmolr |= size | E1000_VMOLR_LPE;
166 wr32(E1000_VMOLR(vfn), vmolr);
167
168 return 0;
169}
170
9d5c8243 171#ifdef CONFIG_PM
3fe7c4c9 172static int igb_suspend(struct pci_dev *, pm_message_t);
9d5c8243
AK		 173static int igb_resume(struct pci_dev *);
174#endif
175static void igb_shutdown(struct pci_dev *);
421e02f0 176#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 177static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
178static struct notifier_block dca_notifier = {
179 .notifier_call = igb_notify_dca,
180 .next = NULL,
181 .priority = 0
182};
183#endif
9d5c8243
AK		 184#ifdef CONFIG_NET_POLL_CONTROLLER
185/* for netdump / net console */
186static void igb_netpoll(struct net_device *);
187#endif
37680117 188#ifdef CONFIG_PCI_IOV
2a3abf6d
AD		 189static unsigned int max_vfs = 0;
190module_param(max_vfs, uint, 0);
191MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
192 "per physical function");
193#endif /* CONFIG_PCI_IOV */
194
9d5c8243
AK		 195static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
196 pci_channel_state_t);
197static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
198static void igb_io_resume(struct pci_dev *);
199
200static struct pci_error_handlers igb_err_handler = {
201 .error_detected = igb_io_error_detected,
202 .slot_reset = igb_io_slot_reset,
203 .resume = igb_io_resume,
204};
205
206
207static struct pci_driver igb_driver = {
208 .name = igb_driver_name,
209 .id_table = igb_pci_tbl,
210 .probe = igb_probe,
211 .remove = __devexit_p(igb_remove),
212#ifdef CONFIG_PM
213 /* Power Managment Hooks */
214 .suspend = igb_suspend,
215 .resume = igb_resume,
216#endif
217 .shutdown = igb_shutdown,
218 .err_handler = &igb_err_handler
219};
220
7dfc16fa
AD		 221static int global_quad_port_a; /* global quad port a indication */
222
9d5c8243
AK		 223MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
224MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
225MODULE_LICENSE("GPL");
226MODULE_VERSION(DRV_VERSION);
227
38c845c7
PO		 228/**
229 * Scale the NIC clock cycle by a large factor so that
230 * relatively small clock corrections can be added or
231 * substracted at each clock tick. The drawbacks of a
232 * large factor are a) that the clock register overflows
233 * more quickly (not such a big deal) and b) that the
234 * increment per tick has to fit into 24 bits.
235 *
236 * Note that
237 * TIMINCA = IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS *
238 * IGB_TSYNC_SCALE
239 * TIMINCA += TIMINCA * adjustment [ppm] / 1e9
240 *
241 * The base scale factor is intentionally a power of two
242 * so that the division in %struct timecounter can be done with
243 * a shift.
244 */
245#define IGB_TSYNC_SHIFT (19)
246#define IGB_TSYNC_SCALE (1<<IGB_TSYNC_SHIFT)
247
248/**
249 * The duration of one clock cycle of the NIC.
250 *
251 * @todo This hard-coded value is part of the specification and might change
252 * in future hardware revisions. Add revision check.
253 */
254#define IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS 16
255
256#if (IGB_TSYNC_SCALE * IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS) >= (1<<24)
257# error IGB_TSYNC_SCALE and/or IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS are too large to fit into TIMINCA
258#endif
259
260/**
261 * igb_read_clock - read raw cycle counter (to be used by time counter)
262 */
263static cycle_t igb_read_clock(const struct cyclecounter *tc)
264{
265 struct igb_adapter *adapter =
266 container_of(tc, struct igb_adapter, cycles);
267 struct e1000_hw *hw = &adapter->hw;
268 u64 stamp;
269
270 stamp = rd32(E1000_SYSTIML);
271 stamp |= (u64)rd32(E1000_SYSTIMH) << 32ULL;
272
273 return stamp;
274}
275
9d5c8243
AK		 276#ifdef DEBUG
277/**
278 * igb_get_hw_dev_name - return device name string
279 * used by hardware layer to print debugging information
280 **/
281char *igb_get_hw_dev_name(struct e1000_hw *hw)
282{
283 struct igb_adapter *adapter = hw->back;
284 return adapter->netdev->name;
285}
38c845c7
PO		 286
287/**
288 * igb_get_time_str - format current NIC and system time as string
289 */
290static char *igb_get_time_str(struct igb_adapter *adapter,
291 char buffer[160])
292{
293 cycle_t hw = adapter->cycles.read(&adapter->cycles);
294 struct timespec nic = ns_to_timespec(timecounter_read(&adapter->clock));
295 struct timespec sys;
296 struct timespec delta;
297 getnstimeofday(&sys);
298
299 delta = timespec_sub(nic, sys);
300
301 sprintf(buffer,
33af6bcc
PO		 302 "HW %llu, NIC %ld.%09lus, SYS %ld.%09lus, NIC-SYS %lds + %09luns",
303 hw,
38c845c7
PO		 304 (long)nic.tv_sec, nic.tv_nsec,
305 (long)sys.tv_sec, sys.tv_nsec,
306 (long)delta.tv_sec, delta.tv_nsec);
307
308 return buffer;
309}
9d5c8243
AK		 310#endif
311
c493ea45
AD		 312/**
313 * igb_desc_unused - calculate if we have unused descriptors
314 **/
315static int igb_desc_unused(struct igb_ring *ring)
316{
317 if (ring->next_to_clean > ring->next_to_use)
318 return ring->next_to_clean - ring->next_to_use - 1;
319
320 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
321}
322
9d5c8243
AK		 323/**
324 * igb_init_module - Driver Registration Routine
325 *
326 * igb_init_module is the first routine called when the driver is
327 * loaded. All it does is register with the PCI subsystem.
328 **/
329static int __init igb_init_module(void)
330{
331 int ret;
332 printk(KERN_INFO "%s - version %s\n",
333 igb_driver_string, igb_driver_version);
334
335 printk(KERN_INFO "%s\n", igb_copyright);
336
7dfc16fa
AD		 337 global_quad_port_a = 0;
338
421e02f0 339#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 340 dca_register_notify(&dca_notifier);
341#endif
bbd98fe4
AD		 342
343 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 344 return ret;
345}
346
347module_init(igb_init_module);
348
349/**
350 * igb_exit_module - Driver Exit Cleanup Routine
351 *
352 * igb_exit_module is called just before the driver is removed
353 * from memory.
354 **/
355static void __exit igb_exit_module(void)
356{
421e02f0 357#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 358 dca_unregister_notify(&dca_notifier);
359#endif
9d5c8243
AK		 360 pci_unregister_driver(&igb_driver);
361}
362
363module_exit(igb_exit_module);
364
26bc19ec
AD		 365#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
366/**
367 * igb_cache_ring_register - Descriptor ring to register mapping
368 * @adapter: board private structure to initialize
369 *
370 * Once we know the feature-set enabled for the device, we'll cache
371 * the register offset the descriptor ring is assigned to.
372 **/
373static void igb_cache_ring_register(struct igb_adapter *adapter)
374{
375 int i;
047e0030 376 u32 rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 377
378 switch (adapter->hw.mac.type) {
379 case e1000_82576:
380 /* The queues are allocated for virtualization such that VF 0
381 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
382 * In order to avoid collision we start at the first free queue
383 * and continue consuming queues in the same sequence
384 */
385 for (i = 0; i < adapter->num_rx_queues; i++)
1bfaf07b
AD		 386 adapter->rx_ring[i].reg_idx = rbase_offset +
387 Q_IDX_82576(i);
26bc19ec 388 for (i = 0; i < adapter->num_tx_queues; i++)
1bfaf07b
AD		 389 adapter->tx_ring[i].reg_idx = rbase_offset +
390 Q_IDX_82576(i);
26bc19ec
AD		 391 break;
392 case e1000_82575:
393 default:
394 for (i = 0; i < adapter->num_rx_queues; i++)
395 adapter->rx_ring[i].reg_idx = i;
396 for (i = 0; i < adapter->num_tx_queues; i++)
397 adapter->tx_ring[i].reg_idx = i;
398 break;
399 }
400}
401
047e0030
AD		 402static void igb_free_queues(struct igb_adapter *adapter)
403{
404 kfree(adapter->tx_ring);
405 kfree(adapter->rx_ring);
406
407 adapter->tx_ring = NULL;
408 adapter->rx_ring = NULL;
409
410 adapter->num_rx_queues = 0;
411 adapter->num_tx_queues = 0;
412}
413
9d5c8243
AK		 414/**
415 * igb_alloc_queues - Allocate memory for all rings
416 * @adapter: board private structure to initialize
417 *
418 * We allocate one ring per queue at run-time since we don't know the
419 * number of queues at compile-time.
420 **/
421static int igb_alloc_queues(struct igb_adapter *adapter)
422{
423 int i;
424
425 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
426 sizeof(struct igb_ring), GFP_KERNEL);
427 if (!adapter->tx_ring)
047e0030 428 goto err;
9d5c8243
AK		 429
430 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
431 sizeof(struct igb_ring), GFP_KERNEL);
047e0030
AD		 432 if (!adapter->rx_ring)
433 goto err;
6eb5a7f1 434
661086df
PWJ		 435 for (i = 0; i < adapter->num_tx_queues; i++) {
436 struct igb_ring *ring = &(adapter->tx_ring[i]);
68fd9910 437 ring->count = adapter->tx_ring_count;
661086df
PWJ		 438 ring->queue_index = i;
439 }
9d5c8243
AK		 440 for (i = 0; i < adapter->num_rx_queues; i++) {
441 struct igb_ring *ring = &(adapter->rx_ring[i]);
68fd9910 442 ring->count = adapter->rx_ring_count;
844290e5 443 ring->queue_index = i;
9d5c8243 444 }
26bc19ec
AD		 445
446 igb_cache_ring_register(adapter);
9d5c8243 447
047e0030 448 return 0;
a88f10ec 449
047e0030
AD		 450err:
451 igb_free_queues(adapter);
d1a8c9e1 452
047e0030 453 return -ENOMEM;
a88f10ec
AD		 454}
455
9d5c8243 456#define IGB_N0_QUEUE -1
047e0030 457static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
9d5c8243
AK		 458{
459 u32 msixbm = 0;
047e0030 460 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 461 struct e1000_hw *hw = &adapter->hw;
2d064c06 462 u32 ivar, index;
047e0030
AD		 463 int rx_queue = IGB_N0_QUEUE;
464 int tx_queue = IGB_N0_QUEUE;
465
466 if (q_vector->rx_ring)
467 rx_queue = q_vector->rx_ring->reg_idx;
468 if (q_vector->tx_ring)
469 tx_queue = q_vector->tx_ring->reg_idx;
2d064c06
AD		 470
471 switch (hw->mac.type) {
472 case e1000_82575:
9d5c8243
AK		 473 /* The 82575 assigns vectors using a bitmask, which matches the
474 bitmask for the EICR/EIMS/EIMC registers. To assign one
475 or more queues to a vector, we write the appropriate bits
476 into the MSIXBM register for that vector. */
047e0030 477 if (rx_queue > IGB_N0_QUEUE)
9d5c8243 478 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
047e0030 479 if (tx_queue > IGB_N0_QUEUE)
9d5c8243 480 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
9d5c8243 481 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
047e0030 482 q_vector->eims_value = msixbm;
2d064c06
AD		 483 break;
484 case e1000_82576:
26bc19ec 485 /* 82576 uses a table-based method for assigning vectors.
2d064c06
AD		 486 Each queue has a single entry in the table to which we write
487 a vector number along with a "valid" bit. Sadly, the layout
488 of the table is somewhat counterintuitive. */
489 if (rx_queue > IGB_N0_QUEUE) {
047e0030 490 index = (rx_queue & 0x7);
2d064c06 491 ivar = array_rd32(E1000_IVAR0, index);
047e0030 492 if (rx_queue < 8) {
26bc19ec
AD		 493 /* vector goes into low byte of register */
494 ivar = ivar & 0xFFFFFF00;
495 ivar |= msix_vector | E1000_IVAR_VALID;
047e0030
AD		 496 } else {
497 /* vector goes into third byte of register */
498 ivar = ivar & 0xFF00FFFF;
499 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
2d064c06 500 }
2d064c06
AD		 501 array_wr32(E1000_IVAR0, index, ivar);
502 }
503 if (tx_queue > IGB_N0_QUEUE) {
047e0030 504 index = (tx_queue & 0x7);
2d064c06 505 ivar = array_rd32(E1000_IVAR0, index);
047e0030 506 if (tx_queue < 8) {
26bc19ec
AD		 507 /* vector goes into second byte of register */
508 ivar = ivar & 0xFFFF00FF;
509 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
047e0030
AD		 510 } else {
511 /* vector goes into high byte of register */
512 ivar = ivar & 0x00FFFFFF;
513 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
2d064c06 514 }
2d064c06
AD		 515 array_wr32(E1000_IVAR0, index, ivar);
516 }
047e0030 517 q_vector->eims_value = 1 << msix_vector;
2d064c06
AD		 518 break;
519 default:
520 BUG();
521 break;
522 }
9d5c8243
AK		 523}
524
525/**
526 * igb_configure_msix - Configure MSI-X hardware
527 *
528 * igb_configure_msix sets up the hardware to properly
529 * generate MSI-X interrupts.
530 **/
531static void igb_configure_msix(struct igb_adapter *adapter)
532{
533 u32 tmp;
534 int i, vector = 0;
535 struct e1000_hw *hw = &adapter->hw;
536
537 adapter->eims_enable_mask = 0;
9d5c8243
AK		 538
539 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 540 switch (hw->mac.type) {
541 case e1000_82575:
9d5c8243
AK		 542 tmp = rd32(E1000_CTRL_EXT);
543 /* enable MSI-X PBA support*/
544 tmp |= E1000_CTRL_EXT_PBA_CLR;
545
546 /* Auto-Mask interrupts upon ICR read. */
547 tmp |= E1000_CTRL_EXT_EIAME;
548 tmp |= E1000_CTRL_EXT_IRCA;
549
550 wr32(E1000_CTRL_EXT, tmp);
047e0030
AD		 551
552 /* enable msix_other interrupt */
553 array_wr32(E1000_MSIXBM(0), vector++,
554 E1000_EIMS_OTHER);
844290e5 555 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 556
2d064c06
AD		 557 break;
558
559 case e1000_82576:
047e0030
AD		 560 /* Turn on MSI-X capability first, or our settings
561 * won't stick. And it will take days to debug. */
562 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
563 E1000_GPIE_PBA | E1000_GPIE_EIAME |
564 E1000_GPIE_NSICR);
565
566 /* enable msix_other interrupt */
567 adapter->eims_other = 1 << vector;
2d064c06 568 tmp = (vector++ | E1000_IVAR_VALID) << 8;
2d064c06 569
047e0030 570 wr32(E1000_IVAR_MISC, tmp);
2d064c06
AD		 571 break;
572 default:
573 /* do nothing, since nothing else supports MSI-X */
574 break;
575 } /* switch (hw->mac.type) */
047e0030
AD		 576
577 adapter->eims_enable_mask |= adapter->eims_other;
578
579 for (i = 0; i < adapter->num_q_vectors; i++) {
580 struct igb_q_vector *q_vector = adapter->q_vector[i];
581 igb_assign_vector(q_vector, vector++);
582 adapter->eims_enable_mask |= q_vector->eims_value;
583 }
584
9d5c8243
AK		 585 wrfl();
586}
587
588/**
589 * igb_request_msix - Initialize MSI-X interrupts
590 *
591 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
592 * kernel.
593 **/
594static int igb_request_msix(struct igb_adapter *adapter)
595{
596 struct net_device *netdev = adapter->netdev;
047e0030 597 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 598 int i, err = 0, vector = 0;
599
047e0030
AD		 600 err = request_irq(adapter->msix_entries[vector].vector,
601 &igb_msix_other, 0, netdev->name, adapter);
602 if (err)
603 goto out;
604 vector++;
605
606 for (i = 0; i < adapter->num_q_vectors; i++) {
607 struct igb_q_vector *q_vector = adapter->q_vector[i];
608
609 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
610
611 if (q_vector->rx_ring && q_vector->tx_ring)
612 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
613 q_vector->rx_ring->queue_index);
614 else if (q_vector->tx_ring)
615 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
616 q_vector->tx_ring->queue_index);
617 else if (q_vector->rx_ring)
618 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
619 q_vector->rx_ring->queue_index);
9d5c8243 620 else
047e0030
AD		 621 sprintf(q_vector->name, "%s-unused", netdev->name);
622
9d5c8243 623 err = request_irq(adapter->msix_entries[vector].vector,
047e0030
AD		 624 &igb_msix_ring, 0, q_vector->name,
625 q_vector);
9d5c8243
AK		 626 if (err)
627 goto out;
9d5c8243
AK		 628 vector++;
629 }
630
9d5c8243
AK		 631 igb_configure_msix(adapter);
632 return 0;
633out:
634 return err;
635}
636
637static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
638{
639 if (adapter->msix_entries) {
640 pci_disable_msix(adapter->pdev);
641 kfree(adapter->msix_entries);
642 adapter->msix_entries = NULL;
047e0030 643 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243 644 pci_disable_msi(adapter->pdev);
047e0030 645 }
9d5c8243
AK		 646}
647
047e0030
AD		 648/**
649 * igb_free_q_vectors - Free memory allocated for interrupt vectors
650 * @adapter: board private structure to initialize
651 *
652 * This function frees the memory allocated to the q_vectors. In addition if
653 * NAPI is enabled it will delete any references to the NAPI struct prior
654 * to freeing the q_vector.
655 **/
656static void igb_free_q_vectors(struct igb_adapter *adapter)
657{
658 int v_idx;
659
660 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
661 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
662 adapter->q_vector[v_idx] = NULL;
663 netif_napi_del(&q_vector->napi);
664 kfree(q_vector);
665 }
666 adapter->num_q_vectors = 0;
667}
668
669/**
670 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
671 *
672 * This function resets the device so that it has 0 rx queues, tx queues, and
673 * MSI-X interrupts allocated.
674 */
675static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
676{
677 igb_free_queues(adapter);
678 igb_free_q_vectors(adapter);
679 igb_reset_interrupt_capability(adapter);
680}
9d5c8243
AK		 681
682/**
683 * igb_set_interrupt_capability - set MSI or MSI-X if supported
684 *
685 * Attempt to configure interrupts using the best available
686 * capabilities of the hardware and kernel.
687 **/
688static void igb_set_interrupt_capability(struct igb_adapter *adapter)
689{
690 int err;
691 int numvecs, i;
692
83b7180d 693 /* Number of supported queues. */
83b7180d
AD		 694 adapter->num_rx_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
695 adapter->num_tx_queues = min_t(u32, IGB_MAX_TX_QUEUES, num_online_cpus());
696
047e0030
AD		 697 /* start with one vector for every rx queue */
698 numvecs = adapter->num_rx_queues;
699
700 /* if tx handler is seperate add 1 for every tx queue */
701 numvecs += adapter->num_tx_queues;
702
703 /* store the number of vectors reserved for queues */
704 adapter->num_q_vectors = numvecs;
705
706 /* add 1 vector for link status interrupts */
707 numvecs++;
9d5c8243
AK		 708 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
709 GFP_KERNEL);
710 if (!adapter->msix_entries)
711 goto msi_only;
712
713 for (i = 0; i < numvecs; i++)
714 adapter->msix_entries[i].entry = i;
715
716 err = pci_enable_msix(adapter->pdev,
717 adapter->msix_entries,
718 numvecs);
719 if (err == 0)
34a20e89 720 goto out;
9d5c8243
AK		 721
722 igb_reset_interrupt_capability(adapter);
723
724 /* If we can't do MSI-X, try MSI */
725msi_only:
2a3abf6d
AD		 726#ifdef CONFIG_PCI_IOV
727 /* disable SR-IOV for non MSI-X configurations */
728 if (adapter->vf_data) {
729 struct e1000_hw *hw = &adapter->hw;
730 /* disable iov and allow time for transactions to clear */
731 pci_disable_sriov(adapter->pdev);
732 msleep(500);
733
734 kfree(adapter->vf_data);
735 adapter->vf_data = NULL;
736 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
737 msleep(100);
738 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
739 }
740#endif
9d5c8243 741 adapter->num_rx_queues = 1;
661086df 742 adapter->num_tx_queues = 1;
047e0030 743 adapter->num_q_vectors = 1;
9d5c8243 744 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 745 adapter->flags |= IGB_FLAG_HAS_MSI;
34a20e89 746out:
661086df 747 /* Notify the stack of the (possibly) reduced Tx Queue count. */
fd2ea0a7 748 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
9d5c8243
AK		 749 return;
750}
751
047e0030
AD		 752/**
753 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
754 * @adapter: board private structure to initialize
755 *
756 * We allocate one q_vector per queue interrupt. If allocation fails we
757 * return -ENOMEM.
758 **/
759static int igb_alloc_q_vectors(struct igb_adapter *adapter)
760{
761 struct igb_q_vector *q_vector;
762 struct e1000_hw *hw = &adapter->hw;
763 int v_idx;
764
765 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
766 q_vector = kzalloc(sizeof(struct igb_q_vector), GFP_KERNEL);
767 if (!q_vector)
768 goto err_out;
769 q_vector->adapter = adapter;
770 q_vector->itr_shift = (hw->mac.type == e1000_82575) ? 16 : 0;
771 q_vector->itr_register = hw->hw_addr + E1000_EITR(0);
772 q_vector->itr_val = IGB_START_ITR;
773 q_vector->set_itr = 1;
774 netif_napi_add(adapter->netdev, &q_vector->napi, igb_poll, 64);
775 adapter->q_vector[v_idx] = q_vector;
776 }
777 return 0;
778
779err_out:
780 while (v_idx) {
781 v_idx--;
782 q_vector = adapter->q_vector[v_idx];
783 netif_napi_del(&q_vector->napi);
784 kfree(q_vector);
785 adapter->q_vector[v_idx] = NULL;
786 }
787 return -ENOMEM;
788}
789
790static void igb_map_rx_ring_to_vector(struct igb_adapter *adapter,
791 int ring_idx, int v_idx)
792{
793 struct igb_q_vector *q_vector;
794
795 q_vector = adapter->q_vector[v_idx];
796 q_vector->rx_ring = &adapter->rx_ring[ring_idx];
797 q_vector->rx_ring->q_vector = q_vector;
798 q_vector->itr_val = adapter->itr;
799}
800
801static void igb_map_tx_ring_to_vector(struct igb_adapter *adapter,
802 int ring_idx, int v_idx)
803{
804 struct igb_q_vector *q_vector;
805
806 q_vector = adapter->q_vector[v_idx];
807 q_vector->tx_ring = &adapter->tx_ring[ring_idx];
808 q_vector->tx_ring->q_vector = q_vector;
809 q_vector->itr_val = adapter->itr;
810}
811
812/**
813 * igb_map_ring_to_vector - maps allocated queues to vectors
814 *
815 * This function maps the recently allocated queues to vectors.
816 **/
817static int igb_map_ring_to_vector(struct igb_adapter *adapter)
818{
819 int i;
820 int v_idx = 0;
821
822 if ((adapter->num_q_vectors < adapter->num_rx_queues) ||
823 (adapter->num_q_vectors < adapter->num_tx_queues))
824 return -ENOMEM;
825
826 if (adapter->num_q_vectors >=
827 (adapter->num_rx_queues + adapter->num_tx_queues)) {
828 for (i = 0; i < adapter->num_rx_queues; i++)
829 igb_map_rx_ring_to_vector(adapter, i, v_idx++);
830 for (i = 0; i < adapter->num_tx_queues; i++)
831 igb_map_tx_ring_to_vector(adapter, i, v_idx++);
832 } else {
833 for (i = 0; i < adapter->num_rx_queues; i++) {
834 if (i < adapter->num_tx_queues)
835 igb_map_tx_ring_to_vector(adapter, i, v_idx);
836 igb_map_rx_ring_to_vector(adapter, i, v_idx++);
837 }
838 for (; i < adapter->num_tx_queues; i++)
839 igb_map_tx_ring_to_vector(adapter, i, v_idx++);
840 }
841 return 0;
842}
843
844/**
845 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
846 *
847 * This function initializes the interrupts and allocates all of the queues.
848 **/
849static int igb_init_interrupt_scheme(struct igb_adapter *adapter)
850{
851 struct pci_dev *pdev = adapter->pdev;
852 int err;
853
854 igb_set_interrupt_capability(adapter);
855
856 err = igb_alloc_q_vectors(adapter);
857 if (err) {
858 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
859 goto err_alloc_q_vectors;
860 }
861
862 err = igb_alloc_queues(adapter);
863 if (err) {
864 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
865 goto err_alloc_queues;
866 }
867
868 err = igb_map_ring_to_vector(adapter);
869 if (err) {
870 dev_err(&pdev->dev, "Invalid q_vector to ring mapping\n");
871 goto err_map_queues;
872 }
873
874
875 return 0;
876err_map_queues:
877 igb_free_queues(adapter);
878err_alloc_queues:
879 igb_free_q_vectors(adapter);
880err_alloc_q_vectors:
881 igb_reset_interrupt_capability(adapter);
882 return err;
883}
884
9d5c8243
AK		 885/**
886 * igb_request_irq - initialize interrupts
887 *
888 * Attempts to configure interrupts using the best available
889 * capabilities of the hardware and kernel.
890 **/
891static int igb_request_irq(struct igb_adapter *adapter)
892{
893 struct net_device *netdev = adapter->netdev;
047e0030 894 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 895 struct e1000_hw *hw = &adapter->hw;
896 int err = 0;
897
898 if (adapter->msix_entries) {
899 err = igb_request_msix(adapter);
844290e5 900 if (!err)
9d5c8243 901 goto request_done;
9d5c8243 902 /* fall back to MSI */
047e0030 903 igb_clear_interrupt_scheme(adapter);
9d5c8243 904 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 905 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 906 igb_free_all_tx_resources(adapter);
907 igb_free_all_rx_resources(adapter);
047e0030 908 adapter->num_tx_queues = 1;
9d5c8243 909 adapter->num_rx_queues = 1;
047e0030
AD		 910 adapter->num_q_vectors = 1;
911 err = igb_alloc_q_vectors(adapter);
912 if (err) {
913 dev_err(&pdev->dev,
914 "Unable to allocate memory for vectors\n");
915 goto request_done;
916 }
917 err = igb_alloc_queues(adapter);
918 if (err) {
919 dev_err(&pdev->dev,
920 "Unable to allocate memory for queues\n");
921 igb_free_q_vectors(adapter);
922 goto request_done;
923 }
924 igb_setup_all_tx_resources(adapter);
925 igb_setup_all_rx_resources(adapter);
844290e5 926 } else {
2d064c06
AD		 927 switch (hw->mac.type) {
928 case e1000_82575:
929 wr32(E1000_MSIXBM(0),
047e0030
AD		 930 (E1000_EICR_RX_QUEUE0 |
931 E1000_EICR_TX_QUEUE0 |
932 E1000_EIMS_OTHER));
2d064c06
AD		 933 break;
934 case e1000_82576:
935 wr32(E1000_IVAR0, E1000_IVAR_VALID);
936 break;
937 default:
938 break;
939 }
9d5c8243 940 }
844290e5 941
7dfc16fa 942 if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243 943 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
047e0030 944 netdev->name, adapter);
9d5c8243
AK		 945 if (!err)
946 goto request_done;
047e0030 947
9d5c8243
AK		 948 /* fall back to legacy interrupts */
949 igb_reset_interrupt_capability(adapter);
7dfc16fa 950 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 951 }
952
953 err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
047e0030 954 netdev->name, adapter);
9d5c8243 955
6cb5e577 956 if (err)
9d5c8243
AK		 957 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
958 err);
9d5c8243
AK		 959
960request_done:
961 return err;
962}
963
964static void igb_free_irq(struct igb_adapter *adapter)
965{
9d5c8243
AK		 966 if (adapter->msix_entries) {
967 int vector = 0, i;
968
047e0030 969 free_irq(adapter->msix_entries[vector++].vector, adapter);
9d5c8243 970
047e0030
AD		 971 for (i = 0; i < adapter->num_q_vectors; i++) {
972 struct igb_q_vector *q_vector = adapter->q_vector[i];
973 free_irq(adapter->msix_entries[vector++].vector,
974 q_vector);
975 }
976 } else {
977 free_irq(adapter->pdev->irq, adapter);
9d5c8243 978 }
9d5c8243
AK		 979}
980
981/**
982 * igb_irq_disable - Mask off interrupt generation on the NIC
983 * @adapter: board private structure
984 **/
985static void igb_irq_disable(struct igb_adapter *adapter)
986{
987 struct e1000_hw *hw = &adapter->hw;
988
989 if (adapter->msix_entries) {
2dfd1212
AD		 990 u32 regval = rd32(E1000_EIAM);
991 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
992 wr32(E1000_EIMC, adapter->eims_enable_mask);
993 regval = rd32(E1000_EIAC);
994 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 995 }
844290e5
PW		 996
997 wr32(E1000_IAM, 0);
9d5c8243
AK		 998 wr32(E1000_IMC, ~0);
999 wrfl();
1000 synchronize_irq(adapter->pdev->irq);
1001}
1002
1003/**
1004 * igb_irq_enable - Enable default interrupt generation settings
1005 * @adapter: board private structure
1006 **/
1007static void igb_irq_enable(struct igb_adapter *adapter)
1008{
1009 struct e1000_hw *hw = &adapter->hw;
1010
1011 if (adapter->msix_entries) {
2dfd1212
AD		 1012 u32 regval = rd32(E1000_EIAC);
1013 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1014 regval = rd32(E1000_EIAM);
1015 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 1016 wr32(E1000_EIMS, adapter->eims_enable_mask);
4ae196df
AD		 1017 if (adapter->vfs_allocated_count)
1018 wr32(E1000_MBVFIMR, 0xFF);
1019 wr32(E1000_IMS, (E1000_IMS_LSC | E1000_IMS_VMMB |
1020 E1000_IMS_DOUTSYNC));
844290e5
PW		 1021 } else {
1022 wr32(E1000_IMS, IMS_ENABLE_MASK);
1023 wr32(E1000_IAM, IMS_ENABLE_MASK);
1024 }
9d5c8243
AK		 1025}
1026
1027static void igb_update_mng_vlan(struct igb_adapter *adapter)
1028{
1029 struct net_device *netdev = adapter->netdev;
1030 u16 vid = adapter->hw.mng_cookie.vlan_id;
1031 u16 old_vid = adapter->mng_vlan_id;
1032 if (adapter->vlgrp) {
1033 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
1034 if (adapter->hw.mng_cookie.status &
1035 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1036 igb_vlan_rx_add_vid(netdev, vid);
1037 adapter->mng_vlan_id = vid;
1038 } else
1039 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1040
1041 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1042 (vid != old_vid) &&
1043 !vlan_group_get_device(adapter->vlgrp, old_vid))
1044 igb_vlan_rx_kill_vid(netdev, old_vid);
1045 } else
1046 adapter->mng_vlan_id = vid;
1047 }
1048}
1049
1050/**
1051 * igb_release_hw_control - release control of the h/w to f/w
1052 * @adapter: address of board private structure
1053 *
1054 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1055 * For ASF and Pass Through versions of f/w this means that the
1056 * driver is no longer loaded.
1057 *
1058 **/
1059static void igb_release_hw_control(struct igb_adapter *adapter)
1060{
1061 struct e1000_hw *hw = &adapter->hw;
1062 u32 ctrl_ext;
1063
1064 /* Let firmware take over control of h/w */
1065 ctrl_ext = rd32(E1000_CTRL_EXT);
1066 wr32(E1000_CTRL_EXT,
1067 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1068}
1069
1070
1071/**
1072 * igb_get_hw_control - get control of the h/w from f/w
1073 * @adapter: address of board private structure
1074 *
1075 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1076 * For ASF and Pass Through versions of f/w this means that
1077 * the driver is loaded.
1078 *
1079 **/
1080static void igb_get_hw_control(struct igb_adapter *adapter)
1081{
1082 struct e1000_hw *hw = &adapter->hw;
1083 u32 ctrl_ext;
1084
1085 /* Let firmware know the driver has taken over */
1086 ctrl_ext = rd32(E1000_CTRL_EXT);
1087 wr32(E1000_CTRL_EXT,
1088 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1089}
1090
9d5c8243
AK		 1091/**
1092 * igb_configure - configure the hardware for RX and TX
1093 * @adapter: private board structure
1094 **/
1095static void igb_configure(struct igb_adapter *adapter)
1096{
1097 struct net_device *netdev = adapter->netdev;
1098 int i;
1099
1100 igb_get_hw_control(adapter);
ff41f8dc 1101 igb_set_rx_mode(netdev);
9d5c8243
AK		 1102
1103 igb_restore_vlan(adapter);
9d5c8243 1104
85b430b4 1105 igb_setup_tctl(adapter);
9d5c8243 1106 igb_setup_rctl(adapter);
85b430b4
AD		 1107
1108 igb_configure_tx(adapter);
9d5c8243 1109 igb_configure_rx(adapter);
662d7205
AD		 1110
1111 igb_rx_fifo_flush_82575(&adapter->hw);
1112
c493ea45 1113 /* call igb_desc_unused which always leaves
9d5c8243
AK		 1114 * at least 1 descriptor unused to make sure
1115 * next_to_use != next_to_clean */
1116 for (i = 0; i < adapter->num_rx_queues; i++) {
1117 struct igb_ring *ring = &adapter->rx_ring[i];
c493ea45 1118 igb_alloc_rx_buffers_adv(ring, igb_desc_unused(ring));
9d5c8243
AK		 1119 }
1120
1121
1122 adapter->tx_queue_len = netdev->tx_queue_len;
1123}
1124
1125
1126/**
1127 * igb_up - Open the interface and prepare it to handle traffic
1128 * @adapter: board private structure
1129 **/
1130
1131int igb_up(struct igb_adapter *adapter)
1132{
1133 struct e1000_hw *hw = &adapter->hw;
1134 int i;
1135
1136 /* hardware has been reset, we need to reload some things */
1137 igb_configure(adapter);
1138
1139 clear_bit(__IGB_DOWN, &adapter->state);
1140
047e0030
AD		 1141 for (i = 0; i < adapter->num_q_vectors; i++) {
1142 struct igb_q_vector *q_vector = adapter->q_vector[i];
1143 napi_enable(&q_vector->napi);
1144 }
844290e5 1145 if (adapter->msix_entries)
9d5c8243 1146 igb_configure_msix(adapter);
9d5c8243 1147
4ae196df 1148 igb_vmm_control(adapter);
e1739522
AD		 1149 igb_set_vmolr(hw, adapter->vfs_allocated_count);
1150
9d5c8243
AK		 1151 /* Clear any pending interrupts. */
1152 rd32(E1000_ICR);
1153 igb_irq_enable(adapter);
1154
4cb9be7a
JB		 1155 netif_tx_start_all_queues(adapter->netdev);
1156
9d5c8243
AK		 1157 /* Fire a link change interrupt to start the watchdog. */
1158 wr32(E1000_ICS, E1000_ICS_LSC);
1159 return 0;
1160}
1161
1162void igb_down(struct igb_adapter *adapter)
1163{
1164 struct e1000_hw *hw = &adapter->hw;
1165 struct net_device *netdev = adapter->netdev;
1166 u32 tctl, rctl;
1167 int i;
1168
1169 /* signal that we're down so the interrupt handler does not
1170 * reschedule our watchdog timer */
1171 set_bit(__IGB_DOWN, &adapter->state);
1172
1173 /* disable receives in the hardware */
1174 rctl = rd32(E1000_RCTL);
1175 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1176 /* flush and sleep below */
1177
fd2ea0a7 1178 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1179
1180 /* disable transmits in the hardware */
1181 tctl = rd32(E1000_TCTL);
1182 tctl &= ~E1000_TCTL_EN;
1183 wr32(E1000_TCTL, tctl);
1184 /* flush both disables and wait for them to finish */
1185 wrfl();
1186 msleep(10);
1187
047e0030
AD		 1188 for (i = 0; i < adapter->num_q_vectors; i++) {
1189 struct igb_q_vector *q_vector = adapter->q_vector[i];
1190 napi_disable(&q_vector->napi);
1191 }
9d5c8243 1192
9d5c8243
AK		 1193 igb_irq_disable(adapter);
1194
1195 del_timer_sync(&adapter->watchdog_timer);
1196 del_timer_sync(&adapter->phy_info_timer);
1197
1198 netdev->tx_queue_len = adapter->tx_queue_len;
1199 netif_carrier_off(netdev);
04fe6358
AD		 1200
1201 /* record the stats before reset*/
1202 igb_update_stats(adapter);
1203
9d5c8243
AK		 1204 adapter->link_speed = 0;
1205 adapter->link_duplex = 0;
1206
3023682e
JK		 1207 if (!pci_channel_offline(adapter->pdev))
1208 igb_reset(adapter);
9d5c8243
AK		 1209 igb_clean_all_tx_rings(adapter);
1210 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1211#ifdef CONFIG_IGB_DCA
1212
1213 /* since we reset the hardware DCA settings were cleared */
1214 igb_setup_dca(adapter);
1215#endif
9d5c8243
AK		 1216}
1217
1218void igb_reinit_locked(struct igb_adapter *adapter)
1219{
1220 WARN_ON(in_interrupt());
1221 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1222 msleep(1);
1223 igb_down(adapter);
1224 igb_up(adapter);
1225 clear_bit(__IGB_RESETTING, &adapter->state);
1226}
1227
1228void igb_reset(struct igb_adapter *adapter)
1229{
1230 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1231 struct e1000_mac_info *mac = &hw->mac;
1232 struct e1000_fc_info *fc = &hw->fc;
9d5c8243
AK		 1233 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
1234 u16 hwm;
1235
1236 /* Repartition Pba for greater than 9k mtu
1237 * To take effect CTRL.RST is required.
1238 */
fa4dfae0
AD		 1239 switch (mac->type) {
1240 case e1000_82576:
2d064c06 1241 pba = E1000_PBA_64K;
fa4dfae0
AD		 1242 break;
1243 case e1000_82575:
1244 default:
1245 pba = E1000_PBA_34K;
1246 break;
2d064c06 1247 }
9d5c8243 1248
2d064c06
AD		 1249 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1250 (mac->type < e1000_82576)) {
9d5c8243
AK		 1251 /* adjust PBA for jumbo frames */
1252 wr32(E1000_PBA, pba);
1253
1254 /* To maintain wire speed transmits, the Tx FIFO should be
1255 * large enough to accommodate two full transmit packets,
1256 * rounded up to the next 1KB and expressed in KB. Likewise,
1257 * the Rx FIFO should be large enough to accommodate at least
1258 * one full receive packet and is similarly rounded up and
1259 * expressed in KB. */
1260 pba = rd32(E1000_PBA);
1261 /* upper 16 bits has Tx packet buffer allocation size in KB */
1262 tx_space = pba >> 16;
1263 /* lower 16 bits has Rx packet buffer allocation size in KB */
1264 pba &= 0xffff;
1265 /* the tx fifo also stores 16 bytes of information about the tx
1266 * but don't include ethernet FCS because hardware appends it */
1267 min_tx_space = (adapter->max_frame_size +
85e8d004 1268 sizeof(union e1000_adv_tx_desc) -
9d5c8243
AK		 1269 ETH_FCS_LEN) * 2;
1270 min_tx_space = ALIGN(min_tx_space, 1024);
1271 min_tx_space >>= 10;
1272 /* software strips receive CRC, so leave room for it */
1273 min_rx_space = adapter->max_frame_size;
1274 min_rx_space = ALIGN(min_rx_space, 1024);
1275 min_rx_space >>= 10;
1276
1277 /* If current Tx allocation is less than the min Tx FIFO size,
1278 * and the min Tx FIFO size is less than the current Rx FIFO
1279 * allocation, take space away from current Rx allocation */
1280 if (tx_space < min_tx_space &&
1281 ((min_tx_space - tx_space) < pba)) {
1282 pba = pba - (min_tx_space - tx_space);
1283
1284 /* if short on rx space, rx wins and must trump tx
1285 * adjustment */
1286 if (pba < min_rx_space)
1287 pba = min_rx_space;
1288 }
2d064c06 1289 wr32(E1000_PBA, pba);
9d5c8243 1290 }
9d5c8243
AK		 1291
1292 /* flow control settings */
1293 /* The high water mark must be low enough to fit one full frame
1294 * (or the size used for early receive) above it in the Rx FIFO.
1295 * Set it to the lower of:
1296 * - 90% of the Rx FIFO size, or
1297 * - the full Rx FIFO size minus one full frame */
1298 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1299 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1300
2d064c06
AD		 1301 if (mac->type < e1000_82576) {
1302 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
1303 fc->low_water = fc->high_water - 8;
1304 } else {
1305 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1306 fc->low_water = fc->high_water - 16;
1307 }
9d5c8243
AK		 1308 fc->pause_time = 0xFFFF;
1309 fc->send_xon = 1;
0cce119a 1310 fc->current_mode = fc->requested_mode;
9d5c8243 1311
4ae196df
AD		 1312 /* disable receive for all VFs and wait one second */
1313 if (adapter->vfs_allocated_count) {
1314 int i;
1315 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
1316 adapter->vf_data[i].clear_to_send = false;
1317
1318 /* ping all the active vfs to let them know we are going down */
1319 igb_ping_all_vfs(adapter);
1320
1321 /* disable transmits and receives */
1322 wr32(E1000_VFRE, 0);
1323 wr32(E1000_VFTE, 0);
1324 }
1325
9d5c8243
AK		 1326 /* Allow time for pending master requests to run */
1327 adapter->hw.mac.ops.reset_hw(&adapter->hw);
1328 wr32(E1000_WUC, 0);
1329
1330 if (adapter->hw.mac.ops.init_hw(&adapter->hw))
1331 dev_err(&adapter->pdev->dev, "Hardware Error\n");
1332
1333 igb_update_mng_vlan(adapter);
1334
1335 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1336 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1337
1338 igb_reset_adaptive(&adapter->hw);
f5f4cf08 1339 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 1340}
1341
2e5c6922
SH		 1342static const struct net_device_ops igb_netdev_ops = {
1343 .ndo_open = igb_open,
1344 .ndo_stop = igb_close,
00829823 1345 .ndo_start_xmit = igb_xmit_frame_adv,
2e5c6922 1346 .ndo_get_stats = igb_get_stats,
ff41f8dc
AD		 1347 .ndo_set_rx_mode = igb_set_rx_mode,
1348 .ndo_set_multicast_list = igb_set_rx_mode,
2e5c6922
SH		 1349 .ndo_set_mac_address = igb_set_mac,
1350 .ndo_change_mtu = igb_change_mtu,
1351 .ndo_do_ioctl = igb_ioctl,
1352 .ndo_tx_timeout = igb_tx_timeout,
1353 .ndo_validate_addr = eth_validate_addr,
1354 .ndo_vlan_rx_register = igb_vlan_rx_register,
1355 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1356 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
1357#ifdef CONFIG_NET_POLL_CONTROLLER
1358 .ndo_poll_controller = igb_netpoll,
1359#endif
1360};
1361
9d5c8243
AK		 1362/**
1363 * igb_probe - Device Initialization Routine
1364 * @pdev: PCI device information struct
1365 * @ent: entry in igb_pci_tbl
1366 *
1367 * Returns 0 on success, negative on failure
1368 *
1369 * igb_probe initializes an adapter identified by a pci_dev structure.
1370 * The OS initialization, configuring of the adapter private structure,
1371 * and a hardware reset occur.
1372 **/
1373static int __devinit igb_probe(struct pci_dev *pdev,
1374 const struct pci_device_id *ent)
1375{
1376 struct net_device *netdev;
1377 struct igb_adapter *adapter;
1378 struct e1000_hw *hw;
1379 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1380 unsigned long mmio_start, mmio_len;
2d6a5e95 1381 int err, pci_using_dac;
682337fe 1382 u16 eeprom_data = 0;
9d5c8243
AK		 1383 u16 eeprom_apme_mask = IGB_EEPROM_APME;
1384 u32 part_num;
1385
aed5dec3 1386 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 1387 if (err)
1388 return err;
1389
1390 pci_using_dac = 0;
6a35528a 1391 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
9d5c8243 1392 if (!err) {
6a35528a 1393 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
9d5c8243
AK		 1394 if (!err)
1395 pci_using_dac = 1;
1396 } else {
284901a9 1397 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
9d5c8243 1398 if (err) {
284901a9 1399 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
9d5c8243
AK		 1400 if (err) {
1401 dev_err(&pdev->dev, "No usable DMA "
1402 "configuration, aborting\n");
1403 goto err_dma;
1404 }
1405 }
1406 }
1407
aed5dec3
AD		 1408 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1409 IORESOURCE_MEM),
1410 igb_driver_name);
9d5c8243
AK		 1411 if (err)
1412 goto err_pci_reg;
1413
19d5afd4 1414 pci_enable_pcie_error_reporting(pdev);
40a914fa 1415
9d5c8243 1416 pci_set_master(pdev);
c682fc23 1417 pci_save_state(pdev);
9d5c8243
AK		 1418
1419 err = -ENOMEM;
1bfaf07b
AD		 1420 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1421 IGB_ABS_MAX_TX_QUEUES);
9d5c8243
AK		 1422 if (!netdev)
1423 goto err_alloc_etherdev;
1424
1425 SET_NETDEV_DEV(netdev, &pdev->dev);
1426
1427 pci_set_drvdata(pdev, netdev);
1428 adapter = netdev_priv(netdev);
1429 adapter->netdev = netdev;
1430 adapter->pdev = pdev;
1431 hw = &adapter->hw;
1432 hw->back = adapter;
1433 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
1434
1435 mmio_start = pci_resource_start(pdev, 0);
1436 mmio_len = pci_resource_len(pdev, 0);
1437
1438 err = -EIO;
28b0759c
AD		 1439 hw->hw_addr = ioremap(mmio_start, mmio_len);
1440 if (!hw->hw_addr)
9d5c8243
AK		 1441 goto err_ioremap;
1442
2e5c6922 1443 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 1444 igb_set_ethtool_ops(netdev);
9d5c8243 1445 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 1446
1447 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1448
1449 netdev->mem_start = mmio_start;
1450 netdev->mem_end = mmio_start + mmio_len;
1451
9d5c8243
AK		 1452 /* PCI config space info */
1453 hw->vendor_id = pdev->vendor;
1454 hw->device_id = pdev->device;
1455 hw->revision_id = pdev->revision;
1456 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1457 hw->subsystem_device_id = pdev->subsystem_device;
1458
1459 /* setup the private structure */
1460 hw->back = adapter;
1461 /* Copy the default MAC, PHY and NVM function pointers */
1462 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1463 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1464 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1465 /* Initialize skew-specific constants */
1466 err = ei->get_invariants(hw);
1467 if (err)
450c87c8 1468 goto err_sw_init;
9d5c8243 1469
2a3abf6d
AD		 1470#ifdef CONFIG_PCI_IOV
1471 /* since iov functionality isn't critical to base device function we
1472 * can accept failure. If it fails we don't allow iov to be enabled */
1473 if (hw->mac.type == e1000_82576) {
1474 /* 82576 supports a maximum of 7 VFs in addition to the PF */
1475 unsigned int num_vfs = (max_vfs > 7) ? 7 : max_vfs;
1476 int i;
1477 unsigned char mac_addr[ETH_ALEN];
1478
9ca046d5 1479 if (num_vfs) {
2a3abf6d
AD		 1480 adapter->vf_data = kcalloc(num_vfs,
1481 sizeof(struct vf_data_storage),
1482 GFP_KERNEL);
9ca046d5
AD		 1483 if (!adapter->vf_data) {
1484 dev_err(&pdev->dev,
1485 "Could not allocate VF private data - "
1486 "IOV enable failed\n");
2a3abf6d 1487 } else {
9ca046d5
AD		 1488 err = pci_enable_sriov(pdev, num_vfs);
1489 if (!err) {
1490 adapter->vfs_allocated_count = num_vfs;
1491 dev_info(&pdev->dev,
1492 "%d vfs allocated\n",
1493 num_vfs);
1494 for (i = 0;
1495 i < adapter->vfs_allocated_count;
1496 i++) {
1497 random_ether_addr(mac_addr);
1498 igb_set_vf_mac(adapter, i,
1499 mac_addr);
1500 }
1501 } else {
1502 kfree(adapter->vf_data);
1503 adapter->vf_data = NULL;
1504 }
2a3abf6d
AD		 1505 }
1506 }
1507 }
1508
1509#endif
450c87c8 1510 /* setup the private structure */
9d5c8243
AK		 1511 err = igb_sw_init(adapter);
1512 if (err)
1513 goto err_sw_init;
1514
1515 igb_get_bus_info_pcie(hw);
1516
7dfc16fa
AD		 1517 /* set flags */
1518 switch (hw->mac.type) {
7dfc16fa 1519 case e1000_82575:
7dfc16fa
AD		 1520 adapter->flags |= IGB_FLAG_NEED_CTX_IDX;
1521 break;
bbd98fe4 1522 case e1000_82576:
7dfc16fa
AD		 1523 default:
1524 break;
1525 }
1526
9d5c8243
AK		 1527 hw->phy.autoneg_wait_to_complete = false;
1528 hw->mac.adaptive_ifs = true;
1529
1530 /* Copper options */
1531 if (hw->phy.media_type == e1000_media_type_copper) {
1532 hw->phy.mdix = AUTO_ALL_MODES;
1533 hw->phy.disable_polarity_correction = false;
1534 hw->phy.ms_type = e1000_ms_hw_default;
1535 }
1536
1537 if (igb_check_reset_block(hw))
1538 dev_info(&pdev->dev,
1539 "PHY reset is blocked due to SOL/IDER session.\n");
1540
1541 netdev->features = NETIF_F_SG |
7d8eb29e 1542 NETIF_F_IP_CSUM |
9d5c8243
AK		 1543 NETIF_F_HW_VLAN_TX |
1544 NETIF_F_HW_VLAN_RX |
1545 NETIF_F_HW_VLAN_FILTER;
1546
7d8eb29e 1547 netdev->features |= NETIF_F_IPV6_CSUM;
9d5c8243 1548 netdev->features |= NETIF_F_TSO;
9d5c8243 1549 netdev->features |= NETIF_F_TSO6;
48f29ffc 1550
5c0999b7 1551 netdev->features |= NETIF_F_GRO;
d3352520 1552
48f29ffc
JK		 1553 netdev->vlan_features |= NETIF_F_TSO;
1554 netdev->vlan_features |= NETIF_F_TSO6;
7d8eb29e 1555 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 1556 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
48f29ffc
JK		 1557 netdev->vlan_features |= NETIF_F_SG;
1558
9d5c8243
AK		 1559 if (pci_using_dac)
1560 netdev->features |= NETIF_F_HIGHDMA;
1561
b9473560
JB		 1562 if (adapter->hw.mac.type == e1000_82576)
1563 netdev->features |= NETIF_F_SCTP_CSUM;
1564
9d5c8243
AK		 1565 adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1566
1567 /* before reading the NVM, reset the controller to put the device in a
1568 * known good starting state */
1569 hw->mac.ops.reset_hw(hw);
1570
1571 /* make sure the NVM is good */
1572 if (igb_validate_nvm_checksum(hw) < 0) {
1573 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1574 err = -EIO;
1575 goto err_eeprom;
1576 }
1577
1578 /* copy the MAC address out of the NVM */
1579 if (hw->mac.ops.read_mac_addr(hw))
1580 dev_err(&pdev->dev, "NVM Read Error\n");
1581
1582 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1583 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1584
1585 if (!is_valid_ether_addr(netdev->perm_addr)) {
1586 dev_err(&pdev->dev, "Invalid MAC Address\n");
1587 err = -EIO;
1588 goto err_eeprom;
1589 }
1590
0e340485
AD		 1591 setup_timer(&adapter->watchdog_timer, &igb_watchdog,
1592 (unsigned long) adapter);
1593 setup_timer(&adapter->phy_info_timer, &igb_update_phy_info,
1594 (unsigned long) adapter);
9d5c8243
AK		 1595
1596 INIT_WORK(&adapter->reset_task, igb_reset_task);
1597 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1598
450c87c8 1599 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 1600 adapter->fc_autoneg = true;
1601 hw->mac.autoneg = true;
1602 hw->phy.autoneg_advertised = 0x2f;
1603
0cce119a
AD		 1604 hw->fc.requested_mode = e1000_fc_default;
1605 hw->fc.current_mode = e1000_fc_default;
9d5c8243 1606
cbd347ad 1607 adapter->itr_setting = IGB_DEFAULT_ITR;
9d5c8243
AK		 1608 adapter->itr = IGB_START_ITR;
1609
1610 igb_validate_mdi_setting(hw);
1611
9d5c8243
AK		 1612 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1613 * enable the ACPI Magic Packet filter
1614 */
1615
a2cf8b6c 1616 if (hw->bus.func == 0)
312c75ae 1617 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
a2cf8b6c
AD		 1618 else if (hw->bus.func == 1)
1619 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243
AK		 1620
1621 if (eeprom_data & eeprom_apme_mask)
1622 adapter->eeprom_wol |= E1000_WUFC_MAG;
1623
1624 /* now that we have the eeprom settings, apply the special cases where
1625 * the eeprom may be wrong or the board simply won't support wake on
1626 * lan on a particular port */
1627 switch (pdev->device) {
1628 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1629 adapter->eeprom_wol = 0;
1630 break;
1631 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 1632 case E1000_DEV_ID_82576_FIBER:
1633 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 1634 /* Wake events only supported on port A for dual fiber
1635 * regardless of eeprom setting */
1636 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1637 adapter->eeprom_wol = 0;
1638 break;
c8ea5ea9
AD		 1639 case E1000_DEV_ID_82576_QUAD_COPPER:
1640 /* if quad port adapter, disable WoL on all but port A */
1641 if (global_quad_port_a != 0)
1642 adapter->eeprom_wol = 0;
1643 else
1644 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
1645 /* Reset for multiple quad port adapters */
1646 if (++global_quad_port_a == 4)
1647 global_quad_port_a = 0;
1648 break;
9d5c8243
AK		 1649 }
1650
1651 /* initialize the wol settings based on the eeprom settings */
1652 adapter->wol = adapter->eeprom_wol;
e1b86d84 1653 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
9d5c8243
AK		 1654
1655 /* reset the hardware with the new settings */
1656 igb_reset(adapter);
1657
1658 /* let the f/w know that the h/w is now under the control of the
1659 * driver. */
1660 igb_get_hw_control(adapter);
1661
9d5c8243
AK		 1662 strcpy(netdev->name, "eth%d");
1663 err = register_netdev(netdev);
1664 if (err)
1665 goto err_register;
1666
b168dfc5
JB		 1667 /* carrier off reporting is important to ethtool even BEFORE open */
1668 netif_carrier_off(netdev);
1669
421e02f0 1670#ifdef CONFIG_IGB_DCA
bbd98fe4 1671 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 1672 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 1673 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 1674 igb_setup_dca(adapter);
1675 }
1676#endif
1677
38c845c7
PO		 1678 /*
1679 * Initialize hardware timer: we keep it running just in case
1680 * that some program needs it later on.
1681 */
1682 memset(&adapter->cycles, 0, sizeof(adapter->cycles));
1683 adapter->cycles.read = igb_read_clock;
1684 adapter->cycles.mask = CLOCKSOURCE_MASK(64);
1685 adapter->cycles.mult = 1;
1686 adapter->cycles.shift = IGB_TSYNC_SHIFT;
1687 wr32(E1000_TIMINCA,
1688 (1<<24) |
1689 IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS * IGB_TSYNC_SCALE);
1690#if 0
1691 /*
1692 * Avoid rollover while we initialize by resetting the time counter.
1693 */
1694 wr32(E1000_SYSTIML, 0x00000000);
1695 wr32(E1000_SYSTIMH, 0x00000000);
1696#else
1697 /*
1698 * Set registers so that rollover occurs soon to test this.
1699 */
1700 wr32(E1000_SYSTIML, 0x00000000);
1701 wr32(E1000_SYSTIMH, 0xFF800000);
1702#endif
1703 wrfl();
1704 timecounter_init(&adapter->clock,
1705 &adapter->cycles,
1706 ktime_to_ns(ktime_get_real()));
1707
33af6bcc
PO		 1708 /*
1709 * Synchronize our NIC clock against system wall clock. NIC
1710 * time stamp reading requires ~3us per sample, each sample
1711 * was pretty stable even under load => only require 10
1712 * samples for each offset comparison.
1713 */
1714 memset(&adapter->compare, 0, sizeof(adapter->compare));
1715 adapter->compare.source = &adapter->clock;
1716 adapter->compare.target = ktime_get_real;
1717 adapter->compare.num_samples = 10;
1718 timecompare_update(&adapter->compare, 0);
1719
38c845c7
PO		 1720#ifdef DEBUG
1721 {
1722 char buffer[160];
1723 printk(KERN_DEBUG
1724 "igb: %s: hw %p initialized timer\n",
1725 igb_get_time_str(adapter, buffer),
1726 &adapter->hw);
1727 }
1728#endif
1729
9d5c8243
AK		 1730 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1731 /* print bus type/speed/width info */
7c510e4b 1732 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
9d5c8243
AK		 1733 netdev->name,
1734 ((hw->bus.speed == e1000_bus_speed_2500)
1735 ? "2.5Gb/s" : "unknown"),
59c3de89
AD		 1736 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
1737 (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :
1738 (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" :
1739 "unknown"),
7c510e4b 1740 netdev->dev_addr);
9d5c8243
AK		 1741
1742 igb_read_part_num(hw, &part_num);
1743 dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1744 (part_num >> 8), (part_num & 0xff));
1745
1746 dev_info(&pdev->dev,
1747 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1748 adapter->msix_entries ? "MSI-X" :
7dfc16fa 1749 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243
AK		 1750 adapter->num_rx_queues, adapter->num_tx_queues);
1751
9d5c8243
AK		 1752 return 0;
1753
1754err_register:
1755 igb_release_hw_control(adapter);
1756err_eeprom:
1757 if (!igb_check_reset_block(hw))
f5f4cf08 1758 igb_reset_phy(hw);
9d5c8243
AK		 1759
1760 if (hw->flash_address)
1761 iounmap(hw->flash_address);
9d5c8243 1762err_sw_init:
047e0030 1763 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 1764 iounmap(hw->hw_addr);
1765err_ioremap:
1766 free_netdev(netdev);
1767err_alloc_etherdev:
aed5dec3
AD		 1768 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1769 IORESOURCE_MEM));
9d5c8243
AK		 1770err_pci_reg:
1771err_dma:
1772 pci_disable_device(pdev);
1773 return err;
1774}
1775
1776/**
1777 * igb_remove - Device Removal Routine
1778 * @pdev: PCI device information struct
1779 *
1780 * igb_remove is called by the PCI subsystem to alert the driver
1781 * that it should release a PCI device. The could be caused by a
1782 * Hot-Plug event, or because the driver is going to be removed from
1783 * memory.
1784 **/
1785static void __devexit igb_remove(struct pci_dev *pdev)
1786{
1787 struct net_device *netdev = pci_get_drvdata(pdev);
1788 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 1789 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1790
1791 /* flush_scheduled work may reschedule our watchdog task, so
1792 * explicitly disable watchdog tasks from being rescheduled */
1793 set_bit(__IGB_DOWN, &adapter->state);
1794 del_timer_sync(&adapter->watchdog_timer);
1795 del_timer_sync(&adapter->phy_info_timer);
1796
1797 flush_scheduled_work();
1798
421e02f0 1799#ifdef CONFIG_IGB_DCA
7dfc16fa 1800 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 1801 dev_info(&pdev->dev, "DCA disabled\n");
1802 dca_remove_requester(&pdev->dev);
7dfc16fa 1803 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 1804 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 1805 }
1806#endif
1807
9d5c8243
AK		 1808 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1809 * would have already happened in close and is redundant. */
1810 igb_release_hw_control(adapter);
1811
1812 unregister_netdev(netdev);
1813
f5f4cf08
AD		 1814 if (!igb_check_reset_block(&adapter->hw))
1815 igb_reset_phy(&adapter->hw);
9d5c8243 1816
047e0030 1817 igb_clear_interrupt_scheme(adapter);
9d5c8243 1818
37680117
AD		 1819#ifdef CONFIG_PCI_IOV
1820 /* reclaim resources allocated to VFs */
1821 if (adapter->vf_data) {
1822 /* disable iov and allow time for transactions to clear */
1823 pci_disable_sriov(pdev);
1824 msleep(500);
1825
1826 kfree(adapter->vf_data);
1827 adapter->vf_data = NULL;
1828 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1829 msleep(100);
1830 dev_info(&pdev->dev, "IOV Disabled\n");
1831 }
1832#endif
28b0759c
AD		 1833 iounmap(hw->hw_addr);
1834 if (hw->flash_address)
1835 iounmap(hw->flash_address);
aed5dec3
AD		 1836 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1837 IORESOURCE_MEM));
9d5c8243
AK		 1838
1839 free_netdev(netdev);
1840
19d5afd4 1841 pci_disable_pcie_error_reporting(pdev);
40a914fa 1842
9d5c8243
AK		 1843 pci_disable_device(pdev);
1844}
1845
1846/**
1847 * igb_sw_init - Initialize general software structures (struct igb_adapter)
1848 * @adapter: board private structure to initialize
1849 *
1850 * igb_sw_init initializes the Adapter private data structure.
1851 * Fields are initialized based on PCI device information and
1852 * OS network device settings (MTU size).
1853 **/
1854static int __devinit igb_sw_init(struct igb_adapter *adapter)
1855{
1856 struct e1000_hw *hw = &adapter->hw;
1857 struct net_device *netdev = adapter->netdev;
1858 struct pci_dev *pdev = adapter->pdev;
1859
1860 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1861
68fd9910
AD		 1862 adapter->tx_ring_count = IGB_DEFAULT_TXD;
1863 adapter->rx_ring_count = IGB_DEFAULT_RXD;
9d5c8243 1864 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9d5c8243
AK		 1865 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1866 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1867
661086df
PWJ		 1868 /* This call may decrease the number of queues depending on
1869 * interrupt mode. */
047e0030 1870 if (igb_init_interrupt_scheme(adapter)) {
9d5c8243
AK		 1871 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1872 return -ENOMEM;
1873 }
1874
1875 /* Explicitly disable IRQ since the NIC can be in any state. */
1876 igb_irq_disable(adapter);
1877
1878 set_bit(__IGB_DOWN, &adapter->state);
1879 return 0;
1880}
1881
1882/**
1883 * igb_open - Called when a network interface is made active
1884 * @netdev: network interface device structure
1885 *
1886 * Returns 0 on success, negative value on failure
1887 *
1888 * The open entry point is called when a network interface is made
1889 * active by the system (IFF_UP). At this point all resources needed
1890 * for transmit and receive operations are allocated, the interrupt
1891 * handler is registered with the OS, the watchdog timer is started,
1892 * and the stack is notified that the interface is ready.
1893 **/
1894static int igb_open(struct net_device *netdev)
1895{
1896 struct igb_adapter *adapter = netdev_priv(netdev);
1897 struct e1000_hw *hw = &adapter->hw;
1898 int err;
1899 int i;
1900
1901 /* disallow open during test */
1902 if (test_bit(__IGB_TESTING, &adapter->state))
1903 return -EBUSY;
1904
b168dfc5
JB		 1905 netif_carrier_off(netdev);
1906
9d5c8243
AK		 1907 /* allocate transmit descriptors */
1908 err = igb_setup_all_tx_resources(adapter);
1909 if (err)
1910 goto err_setup_tx;
1911
1912 /* allocate receive descriptors */
1913 err = igb_setup_all_rx_resources(adapter);
1914 if (err)
1915 goto err_setup_rx;
1916
1917 /* e1000_power_up_phy(adapter); */
1918
1919 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1920 if ((adapter->hw.mng_cookie.status &
1921 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1922 igb_update_mng_vlan(adapter);
1923
1924 /* before we allocate an interrupt, we must be ready to handle it.
1925 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1926 * as soon as we call pci_request_irq, so we have to setup our
1927 * clean_rx handler before we do so. */
1928 igb_configure(adapter);
1929
4ae196df 1930 igb_vmm_control(adapter);
e1739522
AD		 1931 igb_set_vmolr(hw, adapter->vfs_allocated_count);
1932
9d5c8243
AK		 1933 err = igb_request_irq(adapter);
1934 if (err)
1935 goto err_req_irq;
1936
1937 /* From here on the code is the same as igb_up() */
1938 clear_bit(__IGB_DOWN, &adapter->state);
1939
047e0030
AD		 1940 for (i = 0; i < adapter->num_q_vectors; i++) {
1941 struct igb_q_vector *q_vector = adapter->q_vector[i];
1942 napi_enable(&q_vector->napi);
1943 }
9d5c8243
AK		 1944
1945 /* Clear any pending interrupts. */
1946 rd32(E1000_ICR);
844290e5
PW		 1947
1948 igb_irq_enable(adapter);
1949
d55b53ff
JK		 1950 netif_tx_start_all_queues(netdev);
1951
9d5c8243
AK		 1952 /* Fire a link status change interrupt to start the watchdog. */
1953 wr32(E1000_ICS, E1000_ICS_LSC);
1954
1955 return 0;
1956
1957err_req_irq:
1958 igb_release_hw_control(adapter);
1959 /* e1000_power_down_phy(adapter); */
1960 igb_free_all_rx_resources(adapter);
1961err_setup_rx:
1962 igb_free_all_tx_resources(adapter);
1963err_setup_tx:
1964 igb_reset(adapter);
1965
1966 return err;
1967}
1968
1969/**
1970 * igb_close - Disables a network interface
1971 * @netdev: network interface device structure
1972 *
1973 * Returns 0, this is not allowed to fail
1974 *
1975 * The close entry point is called when an interface is de-activated
1976 * by the OS. The hardware is still under the driver's control, but
1977 * needs to be disabled. A global MAC reset is issued to stop the
1978 * hardware, and all transmit and receive resources are freed.
1979 **/
1980static int igb_close(struct net_device *netdev)
1981{
1982 struct igb_adapter *adapter = netdev_priv(netdev);
1983
1984 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1985 igb_down(adapter);
1986
1987 igb_free_irq(adapter);
1988
1989 igb_free_all_tx_resources(adapter);
1990 igb_free_all_rx_resources(adapter);
1991
1992 /* kill manageability vlan ID if supported, but not if a vlan with
1993 * the same ID is registered on the host OS (let 8021q kill it) */
1994 if ((adapter->hw.mng_cookie.status &
1995 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1996 !(adapter->vlgrp &&
1997 vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1998 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1999
2000 return 0;
2001}
2002
2003/**
2004 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
2005 * @adapter: board private structure
2006 * @tx_ring: tx descriptor ring (for a specific queue) to setup
2007 *
2008 * Return 0 on success, negative on failure
2009 **/
9d5c8243
AK		 2010int igb_setup_tx_resources(struct igb_adapter *adapter,
2011 struct igb_ring *tx_ring)
2012{
2013 struct pci_dev *pdev = adapter->pdev;
2014 int size;
2015
2016 size = sizeof(struct igb_buffer) * tx_ring->count;
2017 tx_ring->buffer_info = vmalloc(size);
2018 if (!tx_ring->buffer_info)
2019 goto err;
2020 memset(tx_ring->buffer_info, 0, size);
2021
2022 /* round up to nearest 4K */
85e8d004 2023 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 2024 tx_ring->size = ALIGN(tx_ring->size, 4096);
2025
2026 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
2027 &tx_ring->dma);
2028
2029 if (!tx_ring->desc)
2030 goto err;
2031
9d5c8243
AK		 2032 tx_ring->next_to_use = 0;
2033 tx_ring->next_to_clean = 0;
9d5c8243
AK		 2034 return 0;
2035
2036err:
2037 vfree(tx_ring->buffer_info);
047e0030 2038 dev_err(&pdev->dev,
9d5c8243
AK		 2039 "Unable to allocate memory for the transmit descriptor ring\n");
2040 return -ENOMEM;
2041}
2042
2043/**
2044 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
2045 * (Descriptors) for all queues
2046 * @adapter: board private structure
2047 *
2048 * Return 0 on success, negative on failure
2049 **/
2050static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
2051{
2052 int i, err = 0;
661086df 2053 int r_idx;
9d5c8243
AK		 2054
2055 for (i = 0; i < adapter->num_tx_queues; i++) {
2056 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
2057 if (err) {
2058 dev_err(&adapter->pdev->dev,
2059 "Allocation for Tx Queue %u failed\n", i);
2060 for (i--; i >= 0; i--)
3b644cf6 2061 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 2062 break;
2063 }
2064 }
2065
661086df
PWJ		 2066 for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
2067 r_idx = i % adapter->num_tx_queues;
2068 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
eebbbdba 2069 }
9d5c8243
AK		 2070 return err;
2071}
2072
2073/**
85b430b4
AD		 2074 * igb_setup_tctl - configure the transmit control registers
2075 * @adapter: Board private structure
9d5c8243 2076 **/
85b430b4 2077static void igb_setup_tctl(struct igb_adapter *adapter)
9d5c8243 2078{
9d5c8243
AK		 2079 struct e1000_hw *hw = &adapter->hw;
2080 u32 tctl;
9d5c8243 2081
85b430b4
AD		 2082 /* disable queue 0 which is enabled by default on 82575 and 82576 */
2083 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 2084
2085 /* Program the Transmit Control Register */
9d5c8243
AK		 2086 tctl = rd32(E1000_TCTL);
2087 tctl &= ~E1000_TCTL_CT;
2088 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2089 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2090
2091 igb_config_collision_dist(hw);
2092
9d5c8243
AK		 2093 /* Enable transmits */
2094 tctl |= E1000_TCTL_EN;
2095
2096 wr32(E1000_TCTL, tctl);
2097}
2098
85b430b4
AD		 2099/**
2100 * igb_configure_tx_ring - Configure transmit ring after Reset
2101 * @adapter: board private structure
2102 * @ring: tx ring to configure
2103 *
2104 * Configure a transmit ring after a reset.
2105 **/
2106static void igb_configure_tx_ring(struct igb_adapter *adapter,
2107 struct igb_ring *ring)
2108{
2109 struct e1000_hw *hw = &adapter->hw;
2110 u32 txdctl;
2111 u64 tdba = ring->dma;
2112 int reg_idx = ring->reg_idx;
2113
2114 /* disable the queue */
2115 txdctl = rd32(E1000_TXDCTL(reg_idx));
2116 wr32(E1000_TXDCTL(reg_idx),
2117 txdctl & ~E1000_TXDCTL_QUEUE_ENABLE);
2118 wrfl();
2119 mdelay(10);
2120
2121 wr32(E1000_TDLEN(reg_idx),
2122 ring->count * sizeof(union e1000_adv_tx_desc));
2123 wr32(E1000_TDBAL(reg_idx),
2124 tdba & 0x00000000ffffffffULL);
2125 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
2126
fce99e34
AD		 2127 ring->head = hw->hw_addr + E1000_TDH(reg_idx);
2128 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
2129 writel(0, ring->head);
2130 writel(0, ring->tail);
85b430b4
AD		 2131
2132 txdctl |= IGB_TX_PTHRESH;
2133 txdctl |= IGB_TX_HTHRESH << 8;
2134 txdctl |= IGB_TX_WTHRESH << 16;
2135
2136 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
2137 wr32(E1000_TXDCTL(reg_idx), txdctl);
2138}
2139
2140/**
2141 * igb_configure_tx - Configure transmit Unit after Reset
2142 * @adapter: board private structure
2143 *
2144 * Configure the Tx unit of the MAC after a reset.
2145 **/
2146static void igb_configure_tx(struct igb_adapter *adapter)
2147{
2148 int i;
2149
2150 for (i = 0; i < adapter->num_tx_queues; i++)
2151 igb_configure_tx_ring(adapter, &adapter->tx_ring[i]);
2152
2153 /* Setup Transmit Descriptor Settings for eop descriptor */
2154 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
2155}
2156
9d5c8243
AK		 2157/**
2158 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
2159 * @adapter: board private structure
2160 * @rx_ring: rx descriptor ring (for a specific queue) to setup
2161 *
2162 * Returns 0 on success, negative on failure
2163 **/
9d5c8243
AK		 2164int igb_setup_rx_resources(struct igb_adapter *adapter,
2165 struct igb_ring *rx_ring)
2166{
2167 struct pci_dev *pdev = adapter->pdev;
2168 int size, desc_len;
2169
2170 size = sizeof(struct igb_buffer) * rx_ring->count;
2171 rx_ring->buffer_info = vmalloc(size);
2172 if (!rx_ring->buffer_info)
2173 goto err;
2174 memset(rx_ring->buffer_info, 0, size);
2175
2176 desc_len = sizeof(union e1000_adv_rx_desc);
2177
2178 /* Round up to nearest 4K */
2179 rx_ring->size = rx_ring->count * desc_len;
2180 rx_ring->size = ALIGN(rx_ring->size, 4096);
2181
2182 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
2183 &rx_ring->dma);
2184
2185 if (!rx_ring->desc)
2186 goto err;
2187
2188 rx_ring->next_to_clean = 0;
2189 rx_ring->next_to_use = 0;
9d5c8243 2190
9d5c8243
AK		 2191 return 0;
2192
2193err:
2194 vfree(rx_ring->buffer_info);
2195 dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
2196 "the receive descriptor ring\n");
2197 return -ENOMEM;
2198}
2199
2200/**
2201 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
2202 * (Descriptors) for all queues
2203 * @adapter: board private structure
2204 *
2205 * Return 0 on success, negative on failure
2206 **/
2207static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
2208{
2209 int i, err = 0;
2210
2211 for (i = 0; i < adapter->num_rx_queues; i++) {
2212 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
2213 if (err) {
2214 dev_err(&adapter->pdev->dev,
2215 "Allocation for Rx Queue %u failed\n", i);
2216 for (i--; i >= 0; i--)
3b644cf6 2217 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 2218 break;
2219 }
2220 }
2221
2222 return err;
2223}
2224
2225/**
2226 * igb_setup_rctl - configure the receive control registers
2227 * @adapter: Board private structure
2228 **/
2229static void igb_setup_rctl(struct igb_adapter *adapter)
2230{
2231 struct e1000_hw *hw = &adapter->hw;
2232 u32 rctl;
9d5c8243
AK		 2233
2234 rctl = rd32(E1000_RCTL);
2235
2236 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 2237 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 2238
69d728ba 2239 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 2240 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 2241
87cb7e8c
AK		 2242 /*
2243 * enable stripping of CRC. It's unlikely this will break BMC
2244 * redirection as it did with e1000. Newer features require
2245 * that the HW strips the CRC.
73cd78f1 2246 */
87cb7e8c 2247 rctl |= E1000_RCTL_SECRC;
9d5c8243 2248
9b07f3d3 2249 /*
ec54d7d6 2250 * disable store bad packets and clear size bits.
9b07f3d3 2251 */
ec54d7d6 2252 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 2253
6ec43fe6
AD		 2254 /* enable LPE to prevent packets larger than max_frame_size */
2255 rctl |= E1000_RCTL_LPE;
9d5c8243 2256
952f72a8
AD		 2257 /* disable queue 0 to prevent tail write w/o re-config */
2258 wr32(E1000_RXDCTL(0), 0);
9d5c8243 2259
e1739522
AD		 2260 /* Attention!!! For SR-IOV PF driver operations you must enable
2261 * queue drop for all VF and PF queues to prevent head of line blocking
2262 * if an un-trusted VF does not provide descriptors to hardware.
2263 */
2264 if (adapter->vfs_allocated_count) {
2265 u32 vmolr;
2266
e1739522
AD		 2267 /* set all queue drop enable bits */
2268 wr32(E1000_QDE, ALL_QUEUES);
e1739522 2269
77a22941 2270 vmolr = rd32(E1000_VMOLR(adapter->vfs_allocated_count));
e1739522
AD		 2271 if (rctl & E1000_RCTL_LPE)
2272 vmolr |= E1000_VMOLR_LPE;
77a22941 2273 if (adapter->num_rx_queues > 1)
e1739522 2274 vmolr |= E1000_VMOLR_RSSE;
77a22941 2275 wr32(E1000_VMOLR(adapter->vfs_allocated_count), vmolr);
e1739522
AD		 2276 }
2277
9d5c8243
AK		 2278 wr32(E1000_RCTL, rctl);
2279}
2280
e1739522
AD		 2281/**
2282 * igb_rlpml_set - set maximum receive packet size
2283 * @adapter: board private structure
2284 *
2285 * Configure maximum receivable packet size.
2286 **/
2287static void igb_rlpml_set(struct igb_adapter *adapter)
2288{
2289 u32 max_frame_size = adapter->max_frame_size;
2290 struct e1000_hw *hw = &adapter->hw;
2291 u16 pf_id = adapter->vfs_allocated_count;
2292
2293 if (adapter->vlgrp)
2294 max_frame_size += VLAN_TAG_SIZE;
2295
2296 /* if vfs are enabled we set RLPML to the largest possible request
2297 * size and set the VMOLR RLPML to the size we need */
2298 if (pf_id) {
2299 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
2300 max_frame_size = MAX_STD_JUMBO_FRAME_SIZE + VLAN_TAG_SIZE;
2301 }
2302
2303 wr32(E1000_RLPML, max_frame_size);
2304}
2305
2306/**
2307 * igb_configure_vt_default_pool - Configure VT default pool
2308 * @adapter: board private structure
2309 *
2310 * Configure the default pool
2311 **/
2312static void igb_configure_vt_default_pool(struct igb_adapter *adapter)
2313{
2314 struct e1000_hw *hw = &adapter->hw;
2315 u16 pf_id = adapter->vfs_allocated_count;
2316 u32 vtctl;
2317
2318 /* not in sr-iov mode - do nothing */
2319 if (!pf_id)
2320 return;
2321
2322 vtctl = rd32(E1000_VT_CTL);
2323 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
2324 E1000_VT_CTL_DISABLE_DEF_POOL);
2325 vtctl |= pf_id << E1000_VT_CTL_DEFAULT_POOL_SHIFT;
2326 wr32(E1000_VT_CTL, vtctl);
2327}
2328
85b430b4
AD		 2329/**
2330 * igb_configure_rx_ring - Configure a receive ring after Reset
2331 * @adapter: board private structure
2332 * @ring: receive ring to be configured
2333 *
2334 * Configure the Rx unit of the MAC after a reset.
2335 **/
2336static void igb_configure_rx_ring(struct igb_adapter *adapter,
2337 struct igb_ring *ring)
2338{
2339 struct e1000_hw *hw = &adapter->hw;
2340 u64 rdba = ring->dma;
2341 int reg_idx = ring->reg_idx;
952f72a8 2342 u32 srrctl, rxdctl;
85b430b4
AD		 2343
2344 /* disable the queue */
2345 rxdctl = rd32(E1000_RXDCTL(reg_idx));
2346 wr32(E1000_RXDCTL(reg_idx),
2347 rxdctl & ~E1000_RXDCTL_QUEUE_ENABLE);
2348
2349 /* Set DMA base address registers */
2350 wr32(E1000_RDBAL(reg_idx),
2351 rdba & 0x00000000ffffffffULL);
2352 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
2353 wr32(E1000_RDLEN(reg_idx),
2354 ring->count * sizeof(union e1000_adv_rx_desc));
2355
2356 /* initialize head and tail */
fce99e34
AD		 2357 ring->head = hw->hw_addr + E1000_RDH(reg_idx);
2358 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
2359 writel(0, ring->head);
2360 writel(0, ring->tail);
85b430b4 2361
952f72a8
AD		 2362 /* set descriptor configuration */
2363 if (adapter->rx_buffer_len < IGB_RXBUFFER_1024) {
2364 srrctl = ALIGN(adapter->rx_buffer_len, 64) <<
2365 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2366#if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
2367 srrctl |= IGB_RXBUFFER_16384 >>
2368 E1000_SRRCTL_BSIZEPKT_SHIFT;
2369#else
2370 srrctl |= (PAGE_SIZE / 2) >>
2371 E1000_SRRCTL_BSIZEPKT_SHIFT;
2372#endif
2373 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2374 } else {
2375 srrctl = ALIGN(adapter->rx_buffer_len, 1024) >>
2376 E1000_SRRCTL_BSIZEPKT_SHIFT;
2377 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2378 }
2379
2380 wr32(E1000_SRRCTL(reg_idx), srrctl);
2381
85b430b4
AD		 2382 /* enable receive descriptor fetching */
2383 rxdctl = rd32(E1000_RXDCTL(reg_idx));
2384 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2385 rxdctl &= 0xFFF00000;
2386 rxdctl |= IGB_RX_PTHRESH;
2387 rxdctl |= IGB_RX_HTHRESH << 8;
2388 rxdctl |= IGB_RX_WTHRESH << 16;
2389 wr32(E1000_RXDCTL(reg_idx), rxdctl);
2390}
2391
9d5c8243
AK		 2392/**
2393 * igb_configure_rx - Configure receive Unit after Reset
2394 * @adapter: board private structure
2395 *
2396 * Configure the Rx unit of the MAC after a reset.
2397 **/
2398static void igb_configure_rx(struct igb_adapter *adapter)
2399{
9d5c8243
AK		 2400 struct e1000_hw *hw = &adapter->hw;
2401 u32 rctl, rxcsum;
9107584e 2402 int i;
9d5c8243
AK		 2403
2404 /* disable receives while setting up the descriptors */
2405 rctl = rd32(E1000_RCTL);
2406 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
2407 wrfl();
2408 mdelay(10);
2409
2410 if (adapter->itr_setting > 3)
6eb5a7f1 2411 wr32(E1000_ITR, adapter->itr);
9d5c8243
AK		 2412
2413 /* Setup the HW Rx Head and Tail Descriptor Pointers and
2414 * the Base and Length of the Rx Descriptor Ring */
85b430b4
AD		 2415 for (i = 0; i < adapter->num_rx_queues; i++)
2416 igb_configure_rx_ring(adapter, &adapter->rx_ring[i]);
9d5c8243
AK		 2417
2418 if (adapter->num_rx_queues > 1) {
2419 u32 random[10];
2420 u32 mrqc;
2421 u32 j, shift;
2422 union e1000_reta {
2423 u32 dword;
2424 u8 bytes[4];
2425 } reta;
2426
2427 get_random_bytes(&random[0], 40);
2428
2d064c06
AD		 2429 if (hw->mac.type >= e1000_82576)
2430 shift = 0;
2431 else
2432 shift = 6;
9d5c8243
AK		 2433 for (j = 0; j < (32 * 4); j++) {
2434 reta.bytes[j & 3] =
26bc19ec 2435 adapter->rx_ring[(j % adapter->num_rx_queues)].reg_idx << shift;
9d5c8243
AK		 2436 if ((j & 3) == 3)
2437 writel(reta.dword,
2438 hw->hw_addr + E1000_RETA(0) + (j & ~3));
2439 }
e1739522
AD		 2440 if (adapter->vfs_allocated_count)
2441 mrqc = E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
2442 else
2443 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
9d5c8243
AK		 2444
2445 /* Fill out hash function seeds */
2446 for (j = 0; j < 10; j++)
2447 array_wr32(E1000_RSSRK(0), j, random[j]);
2448
2449 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2450 E1000_MRQC_RSS_FIELD_IPV4_TCP);
2451 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2452 E1000_MRQC_RSS_FIELD_IPV6_TCP);
2453 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
2454 E1000_MRQC_RSS_FIELD_IPV6_UDP);
2455 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2456 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2457
9d5c8243 2458 wr32(E1000_MRQC, mrqc);
2844f797 2459 } else if (adapter->vfs_allocated_count) {
e1739522 2460 /* Enable multi-queue for sr-iov */
2844f797 2461 wr32(E1000_MRQC, E1000_MRQC_ENABLE_VMDQ);
9d5c8243
AK		 2462 }
2463
2844f797
AD		 2464 /* Enable Receive Checksum Offload for TCP and UDP */
2465 rxcsum = rd32(E1000_RXCSUM);
2466 /* Disable raw packet checksumming */
2467 rxcsum |= E1000_RXCSUM_PCSD;
7beb0146
AD		 2468
2469 if (adapter->hw.mac.type == e1000_82576)
b9473560
JB		 2470 /* Enable Receive Checksum Offload for SCTP */
2471 rxcsum |= E1000_RXCSUM_CRCOFL;
2472
7beb0146 2473 /* Don't need to set TUOFL or IPOFL, they default to 1 */
2844f797
AD		 2474 wr32(E1000_RXCSUM, rxcsum);
2475
e1739522
AD		 2476 /* Set the default pool for the PF's first queue */
2477 igb_configure_vt_default_pool(adapter);
2478
68d480c4
AD		 2479 /* set UTA to appropriate mode */
2480 igb_set_uta(adapter);
2481
26ad9178
AD		 2482 /* set the correct pool for the PF default MAC address in entry 0 */
2483 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
2484 adapter->vfs_allocated_count);
2485
e1739522 2486 igb_rlpml_set(adapter);
9d5c8243
AK		 2487
2488 /* Enable Receives */
2489 wr32(E1000_RCTL, rctl);
2490}
2491
2492/**
2493 * igb_free_tx_resources - Free Tx Resources per Queue
9d5c8243
AK		 2494 * @tx_ring: Tx descriptor ring for a specific queue
2495 *
2496 * Free all transmit software resources
2497 **/
68fd9910 2498void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 2499{
047e0030 2500 struct pci_dev *pdev = tx_ring->q_vector->adapter->pdev;
9d5c8243 2501
3b644cf6 2502 igb_clean_tx_ring(tx_ring);
9d5c8243
AK		 2503
2504 vfree(tx_ring->buffer_info);
2505 tx_ring->buffer_info = NULL;
2506
2507 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
2508
2509 tx_ring->desc = NULL;
2510}
2511
2512/**
2513 * igb_free_all_tx_resources - Free Tx Resources for All Queues
2514 * @adapter: board private structure
2515 *
2516 * Free all transmit software resources
2517 **/
2518static void igb_free_all_tx_resources(struct igb_adapter *adapter)
2519{
2520 int i;
2521
2522 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2523 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 2524}
2525
2526static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
2527 struct igb_buffer *buffer_info)
2528{
65689fef 2529 buffer_info->dma = 0;
9d5c8243 2530 if (buffer_info->skb) {
65689fef
AD		 2531 skb_dma_unmap(&adapter->pdev->dev, buffer_info->skb,
2532 DMA_TO_DEVICE);
9d5c8243
AK		 2533 dev_kfree_skb_any(buffer_info->skb);
2534 buffer_info->skb = NULL;
2535 }
2536 buffer_info->time_stamp = 0;
2537 /* buffer_info must be completely set up in the transmit path */
2538}
2539
2540/**
2541 * igb_clean_tx_ring - Free Tx Buffers
9d5c8243
AK		 2542 * @tx_ring: ring to be cleaned
2543 **/
3b644cf6 2544static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 2545{
047e0030 2546 struct igb_adapter *adapter = tx_ring->q_vector->adapter;
9d5c8243
AK		 2547 struct igb_buffer *buffer_info;
2548 unsigned long size;
2549 unsigned int i;
2550
2551 if (!tx_ring->buffer_info)
2552 return;
2553 /* Free all the Tx ring sk_buffs */
2554
2555 for (i = 0; i < tx_ring->count; i++) {
2556 buffer_info = &tx_ring->buffer_info[i];
2557 igb_unmap_and_free_tx_resource(adapter, buffer_info);
2558 }
2559
2560 size = sizeof(struct igb_buffer) * tx_ring->count;
2561 memset(tx_ring->buffer_info, 0, size);
2562
2563 /* Zero out the descriptor ring */
2564
2565 memset(tx_ring->desc, 0, tx_ring->size);
2566
2567 tx_ring->next_to_use = 0;
2568 tx_ring->next_to_clean = 0;
2569
fce99e34
AD		 2570 writel(0, tx_ring->head);
2571 writel(0, tx_ring->tail);
9d5c8243
AK		 2572}
2573
2574/**
2575 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2576 * @adapter: board private structure
2577 **/
2578static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2579{
2580 int i;
2581
2582 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2583 igb_clean_tx_ring(&adapter->tx_ring[i]);
9d5c8243
AK		 2584}
2585
2586/**
2587 * igb_free_rx_resources - Free Rx Resources
9d5c8243
AK		 2588 * @rx_ring: ring to clean the resources from
2589 *
2590 * Free all receive software resources
2591 **/
68fd9910 2592void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2593{
047e0030 2594 struct pci_dev *pdev = rx_ring->q_vector->adapter->pdev;
9d5c8243 2595
3b644cf6 2596 igb_clean_rx_ring(rx_ring);
9d5c8243
AK		 2597
2598 vfree(rx_ring->buffer_info);
2599 rx_ring->buffer_info = NULL;
2600
2601 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2602
2603 rx_ring->desc = NULL;
2604}
2605
2606/**
2607 * igb_free_all_rx_resources - Free Rx Resources for All Queues
2608 * @adapter: board private structure
2609 *
2610 * Free all receive software resources
2611 **/
2612static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2613{
2614 int i;
2615
2616 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2617 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 2618}
2619
2620/**
2621 * igb_clean_rx_ring - Free Rx Buffers per Queue
9d5c8243
AK		 2622 * @rx_ring: ring to free buffers from
2623 **/
3b644cf6 2624static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 2625{
047e0030 2626 struct igb_adapter *adapter = rx_ring->q_vector->adapter;
9d5c8243
AK		 2627 struct igb_buffer *buffer_info;
2628 struct pci_dev *pdev = adapter->pdev;
2629 unsigned long size;
2630 unsigned int i;
2631
2632 if (!rx_ring->buffer_info)
2633 return;
2634 /* Free all the Rx ring sk_buffs */
2635 for (i = 0; i < rx_ring->count; i++) {
2636 buffer_info = &rx_ring->buffer_info[i];
2637 if (buffer_info->dma) {
6ec43fe6
AD		 2638 pci_unmap_single(pdev, buffer_info->dma,
2639 adapter->rx_buffer_len,
2640 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 2641 buffer_info->dma = 0;
2642 }
2643
2644 if (buffer_info->skb) {
2645 dev_kfree_skb(buffer_info->skb);
2646 buffer_info->skb = NULL;
2647 }
6ec43fe6
AD		 2648 if (buffer_info->page_dma) {
2649 pci_unmap_page(pdev, buffer_info->page_dma,
2650 PAGE_SIZE / 2,
2651 PCI_DMA_FROMDEVICE);
2652 buffer_info->page_dma = 0;
2653 }
9d5c8243 2654 if (buffer_info->page) {
9d5c8243
AK		 2655 put_page(buffer_info->page);
2656 buffer_info->page = NULL;
bf36c1a0 2657 buffer_info->page_offset = 0;
9d5c8243
AK		 2658 }
2659 }
2660
9d5c8243
AK		 2661 size = sizeof(struct igb_buffer) * rx_ring->count;
2662 memset(rx_ring->buffer_info, 0, size);
2663
2664 /* Zero out the descriptor ring */
2665 memset(rx_ring->desc, 0, rx_ring->size);
2666
2667 rx_ring->next_to_clean = 0;
2668 rx_ring->next_to_use = 0;
2669
fce99e34
AD		 2670 writel(0, rx_ring->head);
2671 writel(0, rx_ring->tail);
9d5c8243
AK		 2672}
2673
2674/**
2675 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2676 * @adapter: board private structure
2677 **/
2678static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2679{
2680 int i;
2681
2682 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2683 igb_clean_rx_ring(&adapter->rx_ring[i]);
9d5c8243
AK		 2684}
2685
2686/**
2687 * igb_set_mac - Change the Ethernet Address of the NIC
2688 * @netdev: network interface device structure
2689 * @p: pointer to an address structure
2690 *
2691 * Returns 0 on success, negative on failure
2692 **/
2693static int igb_set_mac(struct net_device *netdev, void *p)
2694{
2695 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 2696 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 2697 struct sockaddr *addr = p;
2698
2699 if (!is_valid_ether_addr(addr->sa_data))
2700 return -EADDRNOTAVAIL;
2701
2702 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 2703 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 2704
26ad9178
AD		 2705 /* set the correct pool for the new PF MAC address in entry 0 */
2706 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
2707 adapter->vfs_allocated_count);
e1739522 2708
9d5c8243
AK		 2709 return 0;
2710}
2711
2712/**
68d480c4 2713 * igb_write_mc_addr_list - write multicast addresses to MTA
9d5c8243
AK		 2714 * @netdev: network interface device structure
2715 *
68d480c4
AD		 2716 * Writes multicast address list to the MTA hash table.
2717 * Returns: -ENOMEM on failure
2718 * 0 on no addresses written
2719 * X on writing X addresses to MTA
9d5c8243 2720 **/
68d480c4 2721static int igb_write_mc_addr_list(struct net_device *netdev)
9d5c8243
AK		 2722{
2723 struct igb_adapter *adapter = netdev_priv(netdev);
2724 struct e1000_hw *hw = &adapter->hw;
ff41f8dc 2725 struct dev_mc_list *mc_ptr = netdev->mc_list;
68d480c4
AD		 2726 u8 *mta_list;
2727 u32 vmolr = 0;
9d5c8243
AK		 2728 int i;
2729
68d480c4
AD		 2730 if (!netdev->mc_count) {
2731 /* nothing to program, so clear mc list */
2732 igb_update_mc_addr_list(hw, NULL, 0);
2733 igb_restore_vf_multicasts(adapter);
2734 return 0;
2735 }
9d5c8243 2736
68d480c4
AD		 2737 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2738 if (!mta_list)
2739 return -ENOMEM;
ff41f8dc 2740
68d480c4
AD		 2741 /* set vmolr receive overflow multicast bit */
2742 vmolr |= E1000_VMOLR_ROMPE;
2743
2744 /* The shared function expects a packed array of only addresses. */
2745 mc_ptr = netdev->mc_list;
2746
2747 for (i = 0; i < netdev->mc_count; i++) {
2748 if (!mc_ptr)
2749 break;
2750 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2751 mc_ptr = mc_ptr->next;
746b9f02 2752 }
68d480c4
AD		 2753 igb_update_mc_addr_list(hw, mta_list, i);
2754 kfree(mta_list);
2755
2756 return netdev->mc_count;
2757}
2758
2759/**
2760 * igb_write_uc_addr_list - write unicast addresses to RAR table
2761 * @netdev: network interface device structure
2762 *
2763 * Writes unicast address list to the RAR table.
2764 * Returns: -ENOMEM on failure/insufficient address space
2765 * 0 on no addresses written
2766 * X on writing X addresses to the RAR table
2767 **/
2768static int igb_write_uc_addr_list(struct net_device *netdev)
2769{
2770 struct igb_adapter *adapter = netdev_priv(netdev);
2771 struct e1000_hw *hw = &adapter->hw;
2772 unsigned int vfn = adapter->vfs_allocated_count;
2773 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
2774 int count = 0;
2775
2776 /* return ENOMEM indicating insufficient memory for addresses */
2777 if (netdev->uc.count > rar_entries)
2778 return -ENOMEM;
9d5c8243 2779
ff41f8dc
AD		 2780 if (netdev->uc.count && rar_entries) {
2781 struct netdev_hw_addr *ha;
2782 list_for_each_entry(ha, &netdev->uc.list, list) {
2783 if (!rar_entries)
2784 break;
26ad9178
AD		 2785 igb_rar_set_qsel(adapter, ha->addr,
2786 rar_entries--,
68d480c4
AD		 2787 vfn);
2788 count++;
ff41f8dc
AD		 2789 }
2790 }
2791 /* write the addresses in reverse order to avoid write combining */
2792 for (; rar_entries > 0 ; rar_entries--) {
2793 wr32(E1000_RAH(rar_entries), 0);
2794 wr32(E1000_RAL(rar_entries), 0);
2795 }
2796 wrfl();
2797
68d480c4
AD		 2798 return count;
2799}
2800
2801/**
2802 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
2803 * @netdev: network interface device structure
2804 *
2805 * The set_rx_mode entry point is called whenever the unicast or multicast
2806 * address lists or the network interface flags are updated. This routine is
2807 * responsible for configuring the hardware for proper unicast, multicast,
2808 * promiscuous mode, and all-multi behavior.
2809 **/
2810static void igb_set_rx_mode(struct net_device *netdev)
2811{
2812 struct igb_adapter *adapter = netdev_priv(netdev);
2813 struct e1000_hw *hw = &adapter->hw;
2814 unsigned int vfn = adapter->vfs_allocated_count;
2815 u32 rctl, vmolr = 0;
2816 int count;
2817
2818 /* Check for Promiscuous and All Multicast modes */
2819 rctl = rd32(E1000_RCTL);
2820
2821 /* clear the effected bits */
2822 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
2823
2824 if (netdev->flags & IFF_PROMISC) {
2825 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2826 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
2827 } else {
2828 if (netdev->flags & IFF_ALLMULTI) {
2829 rctl |= E1000_RCTL_MPE;
2830 vmolr |= E1000_VMOLR_MPME;
2831 } else {
2832 /*
2833 * Write addresses to the MTA, if the attempt fails
2834 * then we should just turn on promiscous mode so
2835 * that we can at least receive multicast traffic
2836 */
2837 count = igb_write_mc_addr_list(netdev);
2838 if (count < 0) {
2839 rctl |= E1000_RCTL_MPE;
2840 vmolr |= E1000_VMOLR_MPME;
2841 } else if (count) {
2842 vmolr |= E1000_VMOLR_ROMPE;
2843 }
2844 }
2845 /*
2846 * Write addresses to available RAR registers, if there is not
2847 * sufficient space to store all the addresses then enable
2848 * unicast promiscous mode
2849 */
2850 count = igb_write_uc_addr_list(netdev);
2851 if (count < 0) {
2852 rctl |= E1000_RCTL_UPE;
2853 vmolr |= E1000_VMOLR_ROPE;
2854 }
2855 rctl |= E1000_RCTL_VFE;
28fc06f5 2856 }
68d480c4 2857 wr32(E1000_RCTL, rctl);
28fc06f5 2858
68d480c4
AD		 2859 /*
2860 * In order to support SR-IOV and eventually VMDq it is necessary to set
2861 * the VMOLR to enable the appropriate modes. Without this workaround
2862 * we will have issues with VLAN tag stripping not being done for frames
2863 * that are only arriving because we are the default pool
2864 */
2865 if (hw->mac.type < e1000_82576)
28fc06f5 2866 return;
9d5c8243 2867
68d480c4
AD		 2868 vmolr |= rd32(E1000_VMOLR(vfn)) &
2869 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
2870 wr32(E1000_VMOLR(vfn), vmolr);
28fc06f5 2871 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 2872}
2873
2874/* Need to wait a few seconds after link up to get diagnostic information from
2875 * the phy */
2876static void igb_update_phy_info(unsigned long data)
2877{
2878 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 2879 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 2880}
2881
4d6b725e
AD		 2882/**
2883 * igb_has_link - check shared code for link and determine up/down
2884 * @adapter: pointer to driver private info
2885 **/
2886static bool igb_has_link(struct igb_adapter *adapter)
2887{
2888 struct e1000_hw *hw = &adapter->hw;
2889 bool link_active = false;
2890 s32 ret_val = 0;
2891
2892 /* get_link_status is set on LSC (link status) interrupt or
2893 * rx sequence error interrupt. get_link_status will stay
2894 * false until the e1000_check_for_link establishes link
2895 * for copper adapters ONLY
2896 */
2897 switch (hw->phy.media_type) {
2898 case e1000_media_type_copper:
2899 if (hw->mac.get_link_status) {
2900 ret_val = hw->mac.ops.check_for_link(hw);
2901 link_active = !hw->mac.get_link_status;
2902 } else {
2903 link_active = true;
2904 }
2905 break;
4d6b725e
AD		 2906 case e1000_media_type_internal_serdes:
2907 ret_val = hw->mac.ops.check_for_link(hw);
2908 link_active = hw->mac.serdes_has_link;
2909 break;
2910 default:
2911 case e1000_media_type_unknown:
2912 break;
2913 }
2914
2915 return link_active;
2916}
2917
9d5c8243
AK		 2918/**
2919 * igb_watchdog - Timer Call-back
2920 * @data: pointer to adapter cast into an unsigned long
2921 **/
2922static void igb_watchdog(unsigned long data)
2923{
2924 struct igb_adapter *adapter = (struct igb_adapter *)data;
2925 /* Do the rest outside of interrupt context */
2926 schedule_work(&adapter->watchdog_task);
2927}
2928
2929static void igb_watchdog_task(struct work_struct *work)
2930{
2931 struct igb_adapter *adapter = container_of(work,
2932 struct igb_adapter, watchdog_task);
2933 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 2934 struct net_device *netdev = adapter->netdev;
2935 struct igb_ring *tx_ring = adapter->tx_ring;
9d5c8243 2936 u32 link;
7a6ea550 2937 int i;
9d5c8243 2938
4d6b725e
AD		 2939 link = igb_has_link(adapter);
2940 if ((netif_carrier_ok(netdev)) && link)
9d5c8243
AK		 2941 goto link_up;
2942
9d5c8243
AK		 2943 if (link) {
2944 if (!netif_carrier_ok(netdev)) {
2945 u32 ctrl;
2946 hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2947 &adapter->link_speed,
2948 &adapter->link_duplex);
2949
2950 ctrl = rd32(E1000_CTRL);
527d47c1
AD		 2951 /* Links status message must follow this format */
2952 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
9d5c8243 2953 "Flow Control: %s\n",
527d47c1 2954 netdev->name,
9d5c8243
AK		 2955 adapter->link_speed,
2956 adapter->link_duplex == FULL_DUPLEX ?
2957 "Full Duplex" : "Half Duplex",
2958 ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2959 E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2960 E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2961 E1000_CTRL_TFCE) ? "TX" : "None")));
2962
2963 /* tweak tx_queue_len according to speed/duplex and
2964 * adjust the timeout factor */
2965 netdev->tx_queue_len = adapter->tx_queue_len;
2966 adapter->tx_timeout_factor = 1;
2967 switch (adapter->link_speed) {
2968 case SPEED_10:
2969 netdev->tx_queue_len = 10;
2970 adapter->tx_timeout_factor = 14;
2971 break;
2972 case SPEED_100:
2973 netdev->tx_queue_len = 100;
2974 /* maybe add some timeout factor ? */
2975 break;
2976 }
2977
2978 netif_carrier_on(netdev);
9d5c8243 2979
4ae196df
AD		 2980 igb_ping_all_vfs(adapter);
2981
4b1a9877 2982 /* link state has changed, schedule phy info update */
9d5c8243
AK		 2983 if (!test_bit(__IGB_DOWN, &adapter->state))
2984 mod_timer(&adapter->phy_info_timer,
2985 round_jiffies(jiffies + 2 * HZ));
2986 }
2987 } else {
2988 if (netif_carrier_ok(netdev)) {
2989 adapter->link_speed = 0;
2990 adapter->link_duplex = 0;
527d47c1
AD		 2991 /* Links status message must follow this format */
2992 printk(KERN_INFO "igb: %s NIC Link is Down\n",
2993 netdev->name);
9d5c8243 2994 netif_carrier_off(netdev);
4b1a9877 2995
4ae196df
AD		 2996 igb_ping_all_vfs(adapter);
2997
4b1a9877 2998 /* link state has changed, schedule phy info update */
9d5c8243
AK		 2999 if (!test_bit(__IGB_DOWN, &adapter->state))
3000 mod_timer(&adapter->phy_info_timer,
3001 round_jiffies(jiffies + 2 * HZ));
3002 }
3003 }
3004
3005link_up:
3006 igb_update_stats(adapter);
3007
4b1a9877 3008 hw->mac.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
9d5c8243 3009 adapter->tpt_old = adapter->stats.tpt;
4b1a9877 3010 hw->mac.collision_delta = adapter->stats.colc - adapter->colc_old;
9d5c8243
AK		 3011 adapter->colc_old = adapter->stats.colc;
3012
3013 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
3014 adapter->gorc_old = adapter->stats.gorc;
3015 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
3016 adapter->gotc_old = adapter->stats.gotc;
3017
3018 igb_update_adaptive(&adapter->hw);
3019
3020 if (!netif_carrier_ok(netdev)) {
c493ea45 3021 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
9d5c8243
AK		 3022 /* We've lost link, so the controller stops DMA,
3023 * but we've got queued Tx work that's never going
3024 * to get done, so reset controller to flush Tx.
3025 * (Do the reset outside of interrupt context). */
3026 adapter->tx_timeout_count++;
3027 schedule_work(&adapter->reset_task);
c2d5ab49
JB		 3028 /* return immediately since reset is imminent */
3029 return;
9d5c8243
AK		 3030 }
3031 }
3032
3033 /* Cause software interrupt to ensure rx ring is cleaned */
7a6ea550 3034 if (adapter->msix_entries) {
047e0030
AD		 3035 u32 eics = 0;
3036 for (i = 0; i < adapter->num_q_vectors; i++) {
3037 struct igb_q_vector *q_vector = adapter->q_vector[i];
3038 eics |= q_vector->eims_value;
3039 }
7a6ea550
AD		 3040 wr32(E1000_EICS, eics);
3041 } else {
3042 wr32(E1000_ICS, E1000_ICS_RXDMT0);
3043 }
9d5c8243
AK		 3044
3045 /* Force detection of hung controller every watchdog period */
3046 tx_ring->detect_tx_hung = true;
3047
3048 /* Reset the timer */
3049 if (!test_bit(__IGB_DOWN, &adapter->state))
3050 mod_timer(&adapter->watchdog_timer,
3051 round_jiffies(jiffies + 2 * HZ));
3052}
3053
3054enum latency_range {
3055 lowest_latency = 0,
3056 low_latency = 1,
3057 bulk_latency = 2,
3058 latency_invalid = 255
3059};
3060
3061
6eb5a7f1
AD		 3062/**
3063 * igb_update_ring_itr - update the dynamic ITR value based on packet size
3064 *
3065 * Stores a new ITR value based on strictly on packet size. This
3066 * algorithm is less sophisticated than that used in igb_update_itr,
3067 * due to the difficulty of synchronizing statistics across multiple
3068 * receive rings. The divisors and thresholds used by this fuction
3069 * were determined based on theoretical maximum wire speed and testing
3070 * data, in order to minimize response time while increasing bulk
3071 * throughput.
3072 * This functionality is controlled by the InterruptThrottleRate module
3073 * parameter (see igb_param.c)
3074 * NOTE: This function is called only when operating in a multiqueue
3075 * receive environment.
047e0030 3076 * @q_vector: pointer to q_vector
6eb5a7f1 3077 **/
047e0030 3078static void igb_update_ring_itr(struct igb_q_vector *q_vector)
9d5c8243 3079{
047e0030 3080 int new_val = q_vector->itr_val;
6eb5a7f1 3081 int avg_wire_size = 0;
047e0030 3082 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 3083
6eb5a7f1
AD		 3084 /* For non-gigabit speeds, just fix the interrupt rate at 4000
3085 * ints/sec - ITR timer value of 120 ticks.
3086 */
3087 if (adapter->link_speed != SPEED_1000) {
047e0030 3088 new_val = 976;
6eb5a7f1 3089 goto set_itr_val;
9d5c8243 3090 }
047e0030
AD		 3091
3092 if (q_vector->rx_ring && q_vector->rx_ring->total_packets) {
3093 struct igb_ring *ring = q_vector->rx_ring;
3094 avg_wire_size = ring->total_bytes / ring->total_packets;
3095 }
3096
3097 if (q_vector->tx_ring && q_vector->tx_ring->total_packets) {
3098 struct igb_ring *ring = q_vector->tx_ring;
3099 avg_wire_size = max_t(u32, avg_wire_size,
3100 (ring->total_bytes /
3101 ring->total_packets));
3102 }
3103
3104 /* if avg_wire_size isn't set no work was done */
3105 if (!avg_wire_size)
3106 goto clear_counts;
9d5c8243 3107
6eb5a7f1
AD		 3108 /* Add 24 bytes to size to account for CRC, preamble, and gap */
3109 avg_wire_size += 24;
3110
3111 /* Don't starve jumbo frames */
3112 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 3113
6eb5a7f1
AD		 3114 /* Give a little boost to mid-size frames */
3115 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
3116 new_val = avg_wire_size / 3;
3117 else
3118 new_val = avg_wire_size / 2;
9d5c8243 3119
6eb5a7f1 3120set_itr_val:
047e0030
AD		 3121 if (new_val != q_vector->itr_val) {
3122 q_vector->itr_val = new_val;
3123 q_vector->set_itr = 1;
9d5c8243 3124 }
6eb5a7f1 3125clear_counts:
047e0030
AD		 3126 if (q_vector->rx_ring) {
3127 q_vector->rx_ring->total_bytes = 0;
3128 q_vector->rx_ring->total_packets = 0;
3129 }
3130 if (q_vector->tx_ring) {
3131 q_vector->tx_ring->total_bytes = 0;
3132 q_vector->tx_ring->total_packets = 0;
3133 }
9d5c8243
AK		 3134}
3135
3136/**
3137 * igb_update_itr - update the dynamic ITR value based on statistics
3138 * Stores a new ITR value based on packets and byte
3139 * counts during the last interrupt. The advantage of per interrupt
3140 * computation is faster updates and more accurate ITR for the current
3141 * traffic pattern. Constants in this function were computed
3142 * based on theoretical maximum wire speed and thresholds were set based
3143 * on testing data as well as attempting to minimize response time
3144 * while increasing bulk throughput.
3145 * this functionality is controlled by the InterruptThrottleRate module
3146 * parameter (see igb_param.c)
3147 * NOTE: These calculations are only valid when operating in a single-
3148 * queue environment.
3149 * @adapter: pointer to adapter
047e0030 3150 * @itr_setting: current q_vector->itr_val
9d5c8243
AK		 3151 * @packets: the number of packets during this measurement interval
3152 * @bytes: the number of bytes during this measurement interval
3153 **/
3154static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
3155 int packets, int bytes)
3156{
3157 unsigned int retval = itr_setting;
3158
3159 if (packets == 0)
3160 goto update_itr_done;
3161
3162 switch (itr_setting) {
3163 case lowest_latency:
3164 /* handle TSO and jumbo frames */
3165 if (bytes/packets > 8000)
3166 retval = bulk_latency;
3167 else if ((packets < 5) && (bytes > 512))
3168 retval = low_latency;
3169 break;
3170 case low_latency: /* 50 usec aka 20000 ints/s */
3171 if (bytes > 10000) {
3172 /* this if handles the TSO accounting */
3173 if (bytes/packets > 8000) {
3174 retval = bulk_latency;
3175 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
3176 retval = bulk_latency;
3177 } else if ((packets > 35)) {
3178 retval = lowest_latency;
3179 }
3180 } else if (bytes/packets > 2000) {
3181 retval = bulk_latency;
3182 } else if (packets <= 2 && bytes < 512) {
3183 retval = lowest_latency;
3184 }
3185 break;
3186 case bulk_latency: /* 250 usec aka 4000 ints/s */
3187 if (bytes > 25000) {
3188 if (packets > 35)
3189 retval = low_latency;
1e5c3d21 3190 } else if (bytes < 1500) {
9d5c8243
AK		 3191 retval = low_latency;
3192 }
3193 break;
3194 }
3195
3196update_itr_done:
3197 return retval;
3198}
3199
6eb5a7f1 3200static void igb_set_itr(struct igb_adapter *adapter)
9d5c8243 3201{
047e0030 3202 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243 3203 u16 current_itr;
047e0030 3204 u32 new_itr = q_vector->itr_val;
9d5c8243
AK		 3205
3206 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
3207 if (adapter->link_speed != SPEED_1000) {
3208 current_itr = 0;
3209 new_itr = 4000;
3210 goto set_itr_now;
3211 }
3212
3213 adapter->rx_itr = igb_update_itr(adapter,
3214 adapter->rx_itr,
3215 adapter->rx_ring->total_packets,
3216 adapter->rx_ring->total_bytes);
9d5c8243 3217
047e0030
AD		 3218 adapter->tx_itr = igb_update_itr(adapter,
3219 adapter->tx_itr,
3220 adapter->tx_ring->total_packets,
3221 adapter->tx_ring->total_bytes);
3222 current_itr = max(adapter->rx_itr, adapter->tx_itr);
9d5c8243 3223
6eb5a7f1 3224 /* conservative mode (itr 3) eliminates the lowest_latency setting */
73cd78f1 3225 if (adapter->itr_setting == 3 && current_itr == lowest_latency)
6eb5a7f1
AD		 3226 current_itr = low_latency;
3227
9d5c8243
AK		 3228 switch (current_itr) {
3229 /* counts and packets in update_itr are dependent on these numbers */
3230 case lowest_latency:
78b1f607 3231 new_itr = 56; /* aka 70,000 ints/sec */
9d5c8243
AK		 3232 break;
3233 case low_latency:
78b1f607 3234 new_itr = 196; /* aka 20,000 ints/sec */
9d5c8243
AK		 3235 break;
3236 case bulk_latency:
78b1f607 3237 new_itr = 980; /* aka 4,000 ints/sec */
9d5c8243
AK		 3238 break;
3239 default:
3240 break;
3241 }
3242
3243set_itr_now:
6eb5a7f1
AD		 3244 adapter->rx_ring->total_bytes = 0;
3245 adapter->rx_ring->total_packets = 0;
047e0030
AD		 3246 adapter->tx_ring->total_bytes = 0;
3247 adapter->tx_ring->total_packets = 0;
6eb5a7f1 3248
047e0030 3249 if (new_itr != q_vector->itr_val) {
9d5c8243
AK		 3250 /* this attempts to bias the interrupt rate towards Bulk
3251 * by adding intermediate steps when interrupt rate is
3252 * increasing */
047e0030
AD		 3253 new_itr = new_itr > q_vector->itr_val ?
3254 max((new_itr * q_vector->itr_val) /
3255 (new_itr + (q_vector->itr_val >> 2)),
3256 new_itr) :
9d5c8243
AK		 3257 new_itr;
3258 /* Don't write the value here; it resets the adapter's
3259 * internal timer, and causes us to delay far longer than
3260 * we should between interrupts. Instead, we write the ITR
3261 * value at the beginning of the next interrupt so the timing
3262 * ends up being correct.
3263 */
047e0030
AD		 3264 q_vector->itr_val = new_itr;
3265 q_vector->set_itr = 1;
9d5c8243
AK		 3266 }
3267
3268 return;
3269}
3270
9d5c8243
AK		 3271#define IGB_TX_FLAGS_CSUM 0x00000001
3272#define IGB_TX_FLAGS_VLAN 0x00000002
3273#define IGB_TX_FLAGS_TSO 0x00000004
3274#define IGB_TX_FLAGS_IPV4 0x00000008
33af6bcc 3275#define IGB_TX_FLAGS_TSTAMP 0x00000010
9d5c8243
AK		 3276#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
3277#define IGB_TX_FLAGS_VLAN_SHIFT 16
3278
3279static inline int igb_tso_adv(struct igb_adapter *adapter,
3280 struct igb_ring *tx_ring,
3281 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
3282{
3283 struct e1000_adv_tx_context_desc *context_desc;
3284 unsigned int i;
3285 int err;
3286 struct igb_buffer *buffer_info;
3287 u32 info = 0, tu_cmd = 0;
3288 u32 mss_l4len_idx, l4len;
3289 *hdr_len = 0;
3290
3291 if (skb_header_cloned(skb)) {
3292 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
3293 if (err)
3294 return err;
3295 }
3296
3297 l4len = tcp_hdrlen(skb);
3298 *hdr_len += l4len;
3299
3300 if (skb->protocol == htons(ETH_P_IP)) {
3301 struct iphdr *iph = ip_hdr(skb);
3302 iph->tot_len = 0;
3303 iph->check = 0;
3304 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
3305 iph->daddr, 0,
3306 IPPROTO_TCP,
3307 0);
3308 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
3309 ipv6_hdr(skb)->payload_len = 0;
3310 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
3311 &ipv6_hdr(skb)->daddr,
3312 0, IPPROTO_TCP, 0);
3313 }
3314
3315 i = tx_ring->next_to_use;
3316
3317 buffer_info = &tx_ring->buffer_info[i];
3318 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3319 /* VLAN MACLEN IPLEN */
3320 if (tx_flags & IGB_TX_FLAGS_VLAN)
3321 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
3322 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3323 *hdr_len += skb_network_offset(skb);
3324 info |= skb_network_header_len(skb);
3325 *hdr_len += skb_network_header_len(skb);
3326 context_desc->vlan_macip_lens = cpu_to_le32(info);
3327
3328 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
3329 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3330
3331 if (skb->protocol == htons(ETH_P_IP))
3332 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
3333 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3334
3335 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3336
3337 /* MSS L4LEN IDX */
3338 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
3339 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
3340
73cd78f1 3341 /* For 82575, context index must be unique per ring. */
7dfc16fa
AD		 3342 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
3343 mss_l4len_idx |= tx_ring->queue_index << 4;
9d5c8243
AK		 3344
3345 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
3346 context_desc->seqnum_seed = 0;
3347
3348 buffer_info->time_stamp = jiffies;
0e014cb1 3349 buffer_info->next_to_watch = i;
9d5c8243
AK		 3350 buffer_info->dma = 0;
3351 i++;
3352 if (i == tx_ring->count)
3353 i = 0;
3354
3355 tx_ring->next_to_use = i;
3356
3357 return true;
3358}
3359
3360static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
3361 struct igb_ring *tx_ring,
3362 struct sk_buff *skb, u32 tx_flags)
3363{
3364 struct e1000_adv_tx_context_desc *context_desc;
3365 unsigned int i;
3366 struct igb_buffer *buffer_info;
3367 u32 info = 0, tu_cmd = 0;
3368
3369 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
3370 (tx_flags & IGB_TX_FLAGS_VLAN)) {
3371 i = tx_ring->next_to_use;
3372 buffer_info = &tx_ring->buffer_info[i];
3373 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3374
3375 if (tx_flags & IGB_TX_FLAGS_VLAN)
3376 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
3377 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3378 if (skb->ip_summed == CHECKSUM_PARTIAL)
3379 info |= skb_network_header_len(skb);
3380
3381 context_desc->vlan_macip_lens = cpu_to_le32(info);
3382
3383 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3384
3385 if (skb->ip_summed == CHECKSUM_PARTIAL) {
fa4a7ef3
AJ		 3386 __be16 protocol;
3387
3388 if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
3389 const struct vlan_ethhdr *vhdr =
3390 (const struct vlan_ethhdr*)skb->data;
3391
3392 protocol = vhdr->h_vlan_encapsulated_proto;
3393 } else {
3394 protocol = skb->protocol;
3395 }
3396
3397 switch (protocol) {
09640e63 3398 case cpu_to_be16(ETH_P_IP):
9d5c8243 3399 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
44b0cda3
MW		 3400 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
3401 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
b9473560
JB		 3402 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
3403 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
44b0cda3 3404 break;
09640e63 3405 case cpu_to_be16(ETH_P_IPV6):
44b0cda3
MW		 3406 /* XXX what about other V6 headers?? */
3407 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
3408 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
b9473560
JB		 3409 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
3410 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
44b0cda3
MW		 3411 break;
3412 default:
3413 if (unlikely(net_ratelimit()))
3414 dev_warn(&adapter->pdev->dev,
3415 "partial checksum but proto=%x!\n",
3416 skb->protocol);
3417 break;
3418 }
9d5c8243
AK		 3419 }
3420
3421 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3422 context_desc->seqnum_seed = 0;
7dfc16fa
AD		 3423 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
3424 context_desc->mss_l4len_idx =
3425 cpu_to_le32(tx_ring->queue_index << 4);
265de409
AD		 3426 else
3427 context_desc->mss_l4len_idx = 0;
9d5c8243
AK		 3428
3429 buffer_info->time_stamp = jiffies;
0e014cb1 3430 buffer_info->next_to_watch = i;
9d5c8243
AK		 3431 buffer_info->dma = 0;
3432
3433 i++;
3434 if (i == tx_ring->count)
3435 i = 0;
3436 tx_ring->next_to_use = i;
3437
3438 return true;
3439 }
9d5c8243
AK		 3440 return false;
3441}
3442
3443#define IGB_MAX_TXD_PWR 16
3444#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
3445
3446static inline int igb_tx_map_adv(struct igb_adapter *adapter,
0e014cb1
AD		 3447 struct igb_ring *tx_ring, struct sk_buff *skb,
3448 unsigned int first)
9d5c8243
AK		 3449{
3450 struct igb_buffer *buffer_info;
3451 unsigned int len = skb_headlen(skb);
3452 unsigned int count = 0, i;
3453 unsigned int f;
65689fef 3454 dma_addr_t *map;
9d5c8243
AK		 3455
3456 i = tx_ring->next_to_use;
3457
65689fef
AD		 3458 if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
3459 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
3460 return 0;
3461 }
3462
3463 map = skb_shinfo(skb)->dma_maps;
3464
9d5c8243
AK		 3465 buffer_info = &tx_ring->buffer_info[i];
3466 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3467 buffer_info->length = len;
3468 /* set time_stamp *before* dma to help avoid a possible race */
3469 buffer_info->time_stamp = jiffies;
0e014cb1 3470 buffer_info->next_to_watch = i;
042a53a9 3471 buffer_info->dma = skb_shinfo(skb)->dma_head;
9d5c8243
AK		 3472
3473 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
3474 struct skb_frag_struct *frag;
3475
65689fef
AD		 3476 i++;
3477 if (i == tx_ring->count)
3478 i = 0;
3479
9d5c8243
AK		 3480 frag = &skb_shinfo(skb)->frags[f];
3481 len = frag->size;
3482
3483 buffer_info = &tx_ring->buffer_info[i];
3484 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3485 buffer_info->length = len;
3486 buffer_info->time_stamp = jiffies;
0e014cb1 3487 buffer_info->next_to_watch = i;
65689fef 3488 buffer_info->dma = map[count];
9d5c8243 3489 count++;
9d5c8243
AK		 3490 }
3491
9d5c8243 3492 tx_ring->buffer_info[i].skb = skb;
0e014cb1 3493 tx_ring->buffer_info[first].next_to_watch = i;
9d5c8243 3494
042a53a9 3495 return count + 1;
9d5c8243
AK		 3496}
3497
3498static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
3499 struct igb_ring *tx_ring,
3500 int tx_flags, int count, u32 paylen,
3501 u8 hdr_len)
3502{
3503 union e1000_adv_tx_desc *tx_desc = NULL;
3504 struct igb_buffer *buffer_info;
3505 u32 olinfo_status = 0, cmd_type_len;
3506 unsigned int i;
3507
3508 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
3509 E1000_ADVTXD_DCMD_DEXT);
3510
3511 if (tx_flags & IGB_TX_FLAGS_VLAN)
3512 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3513
33af6bcc
PO		 3514 if (tx_flags & IGB_TX_FLAGS_TSTAMP)
3515 cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP;
3516
9d5c8243
AK		 3517 if (tx_flags & IGB_TX_FLAGS_TSO) {
3518 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3519
3520 /* insert tcp checksum */
3521 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3522
3523 /* insert ip checksum */
3524 if (tx_flags & IGB_TX_FLAGS_IPV4)
3525 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3526
3527 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
3528 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3529 }
3530
7dfc16fa
AD		 3531 if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) &&
3532 (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
3533 IGB_TX_FLAGS_VLAN)))
661086df 3534 olinfo_status |= tx_ring->queue_index << 4;
9d5c8243
AK		 3535
3536 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
3537
3538 i = tx_ring->next_to_use;
3539 while (count--) {
3540 buffer_info = &tx_ring->buffer_info[i];
3541 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
3542 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
3543 tx_desc->read.cmd_type_len =
3544 cpu_to_le32(cmd_type_len | buffer_info->length);
3545 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
3546 i++;
3547 if (i == tx_ring->count)
3548 i = 0;
3549 }
3550
3551 tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
3552 /* Force memory writes to complete before letting h/w
3553 * know there are new descriptors to fetch. (Only
3554 * applicable for weak-ordered memory model archs,
3555 * such as IA-64). */
3556 wmb();
3557
3558 tx_ring->next_to_use = i;
fce99e34 3559 writel(i, tx_ring->tail);
9d5c8243
AK		 3560 /* we need this if more than one processor can write to our tail
3561 * at a time, it syncronizes IO on IA64/Altix systems */
3562 mmiowb();
3563}
3564
3565static int __igb_maybe_stop_tx(struct net_device *netdev,
3566 struct igb_ring *tx_ring, int size)
3567{
3568 struct igb_adapter *adapter = netdev_priv(netdev);
3569
661086df 3570 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 3571
9d5c8243
AK		 3572 /* Herbert's original patch had:
3573 * smp_mb__after_netif_stop_queue();
3574 * but since that doesn't exist yet, just open code it. */
3575 smp_mb();
3576
3577 /* We need to check again in a case another CPU has just
3578 * made room available. */
c493ea45 3579 if (igb_desc_unused(tx_ring) < size)
9d5c8243
AK		 3580 return -EBUSY;
3581
3582 /* A reprieve! */
661086df 3583 netif_wake_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 3584 ++adapter->restart_queue;
3585 return 0;
3586}
3587
3588static int igb_maybe_stop_tx(struct net_device *netdev,
3589 struct igb_ring *tx_ring, int size)
3590{
c493ea45 3591 if (igb_desc_unused(tx_ring) >= size)
9d5c8243
AK		 3592 return 0;
3593 return __igb_maybe_stop_tx(netdev, tx_ring, size);
3594}
3595
3b29a56d
SH		 3596static netdev_tx_t igb_xmit_frame_ring_adv(struct sk_buff *skb,
3597 struct net_device *netdev,
3598 struct igb_ring *tx_ring)
9d5c8243
AK		 3599{
3600 struct igb_adapter *adapter = netdev_priv(netdev);
0e014cb1 3601 unsigned int first;
9d5c8243 3602 unsigned int tx_flags = 0;
9d5c8243 3603 u8 hdr_len = 0;
65689fef 3604 int count = 0;
9d5c8243 3605 int tso = 0;
33af6bcc 3606 union skb_shared_tx *shtx;
9d5c8243 3607
9d5c8243
AK		 3608 if (test_bit(__IGB_DOWN, &adapter->state)) {
3609 dev_kfree_skb_any(skb);
3610 return NETDEV_TX_OK;
3611 }
3612
3613 if (skb->len <= 0) {
3614 dev_kfree_skb_any(skb);
3615 return NETDEV_TX_OK;
3616 }
3617
9d5c8243
AK		 3618 /* need: 1 descriptor per page,
3619 * + 2 desc gap to keep tail from touching head,
3620 * + 1 desc for skb->data,
3621 * + 1 desc for context descriptor,
3622 * otherwise try next time */
3623 if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
3624 /* this is a hard error */
9d5c8243
AK		 3625 return NETDEV_TX_BUSY;
3626 }
33af6bcc
PO		 3627
3628 /*
3629 * TODO: check that there currently is no other packet with
3630 * time stamping in the queue
3631 *
3632 * When doing time stamping, keep the connection to the socket
3633 * a while longer: it is still needed by skb_hwtstamp_tx(),
3634 * called either in igb_tx_hwtstamp() or by our caller when
3635 * doing software time stamping.
3636 */
3637 shtx = skb_tx(skb);
3638 if (unlikely(shtx->hardware)) {
3639 shtx->in_progress = 1;
3640 tx_flags |= IGB_TX_FLAGS_TSTAMP;
33af6bcc 3641 }
9d5c8243
AK		 3642
3643 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
3644 tx_flags |= IGB_TX_FLAGS_VLAN;
3645 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
3646 }
3647
661086df
PWJ		 3648 if (skb->protocol == htons(ETH_P_IP))
3649 tx_flags |= IGB_TX_FLAGS_IPV4;
3650
0e014cb1 3651 first = tx_ring->next_to_use;
9d5c8243
AK		 3652 tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
3653 &hdr_len) : 0;
3654
3655 if (tso < 0) {
3656 dev_kfree_skb_any(skb);
9d5c8243
AK		 3657 return NETDEV_TX_OK;
3658 }
3659
3660 if (tso)
3661 tx_flags |= IGB_TX_FLAGS_TSO;
bc1cbd34
AD		 3662 else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags) &&
3663 (skb->ip_summed == CHECKSUM_PARTIAL))
3664 tx_flags |= IGB_TX_FLAGS_CSUM;
9d5c8243 3665
65689fef
AD		 3666 /*
3667 * count reflects descriptors mapped, if 0 then mapping error
3668 * has occured and we need to rewind the descriptor queue
3669 */
3670 count = igb_tx_map_adv(adapter, tx_ring, skb, first);
3671
3672 if (count) {
3673 igb_tx_queue_adv(adapter, tx_ring, tx_flags, count,
3674 skb->len, hdr_len);
65689fef
AD		 3675 /* Make sure there is space in the ring for the next send. */
3676 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
3677 } else {
3678 dev_kfree_skb_any(skb);
3679 tx_ring->buffer_info[first].time_stamp = 0;
3680 tx_ring->next_to_use = first;
3681 }
9d5c8243 3682
9d5c8243
AK		 3683 return NETDEV_TX_OK;
3684}
3685
3b29a56d
SH		 3686static netdev_tx_t igb_xmit_frame_adv(struct sk_buff *skb,
3687 struct net_device *netdev)
9d5c8243
AK		 3688{
3689 struct igb_adapter *adapter = netdev_priv(netdev);
661086df
PWJ		 3690 struct igb_ring *tx_ring;
3691
661086df 3692 int r_idx = 0;
1bfaf07b 3693 r_idx = skb->queue_mapping & (IGB_ABS_MAX_TX_QUEUES - 1);
661086df 3694 tx_ring = adapter->multi_tx_table[r_idx];
9d5c8243
AK		 3695
3696 /* This goes back to the question of how to logically map a tx queue
3697 * to a flow. Right now, performance is impacted slightly negatively
3698 * if using multiple tx queues. If the stack breaks away from a
3699 * single qdisc implementation, we can look at this again. */
3b29a56d 3700 return igb_xmit_frame_ring_adv(skb, netdev, tx_ring);
9d5c8243
AK		 3701}
3702
3703/**
3704 * igb_tx_timeout - Respond to a Tx Hang
3705 * @netdev: network interface device structure
3706 **/
3707static void igb_tx_timeout(struct net_device *netdev)
3708{
3709 struct igb_adapter *adapter = netdev_priv(netdev);
3710 struct e1000_hw *hw = &adapter->hw;
3711
3712 /* Do the reset outside of interrupt context */
3713 adapter->tx_timeout_count++;
3714 schedule_work(&adapter->reset_task);
265de409
AD		 3715 wr32(E1000_EICS,
3716 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 3717}
3718
3719static void igb_reset_task(struct work_struct *work)
3720{
3721 struct igb_adapter *adapter;
3722 adapter = container_of(work, struct igb_adapter, reset_task);
3723
3724 igb_reinit_locked(adapter);
3725}
3726
3727/**
3728 * igb_get_stats - Get System Network Statistics
3729 * @netdev: network interface device structure
3730 *
3731 * Returns the address of the device statistics structure.
3732 * The statistics are actually updated from the timer callback.
3733 **/
73cd78f1 3734static struct net_device_stats *igb_get_stats(struct net_device *netdev)
9d5c8243 3735{
9d5c8243 3736 /* only return the current stats */
8d24e933 3737 return &netdev->stats;
9d5c8243
AK		 3738}
3739
3740/**
3741 * igb_change_mtu - Change the Maximum Transfer Unit
3742 * @netdev: network interface device structure
3743 * @new_mtu: new value for maximum frame size
3744 *
3745 * Returns 0 on success, negative on failure
3746 **/
3747static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3748{
3749 struct igb_adapter *adapter = netdev_priv(netdev);
3750 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3751
3752 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
3753 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3754 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
3755 return -EINVAL;
3756 }
3757
9d5c8243
AK		 3758 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3759 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
3760 return -EINVAL;
3761 }
3762
3763 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3764 msleep(1);
73cd78f1 3765
9d5c8243
AK		 3766 /* igb_down has a dependency on max_frame_size */
3767 adapter->max_frame_size = max_frame;
3768 if (netif_running(netdev))
3769 igb_down(adapter);
3770
3771 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3772 * means we reserve 2 more, this pushes us to allocate from the next
3773 * larger slab size.
3774 * i.e. RXBUFFER_2048 --> size-4096 slab
3775 */
3776
7d95b717 3777 if (max_frame <= IGB_RXBUFFER_1024)
9d5c8243 3778 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
6ec43fe6 3779 else if (max_frame <= MAXIMUM_ETHERNET_VLAN_SIZE)
9d5c8243 3780 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
6ec43fe6
AD		 3781 else
3782 adapter->rx_buffer_len = IGB_RXBUFFER_128;
9d5c8243
AK		 3783
3784 dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
3785 netdev->mtu, new_mtu);
3786 netdev->mtu = new_mtu;
3787
3788 if (netif_running(netdev))
3789 igb_up(adapter);
3790 else
3791 igb_reset(adapter);
3792
3793 clear_bit(__IGB_RESETTING, &adapter->state);
3794
3795 return 0;
3796}
3797
3798/**
3799 * igb_update_stats - Update the board statistics counters
3800 * @adapter: board private structure
3801 **/
3802
3803void igb_update_stats(struct igb_adapter *adapter)
3804{
8d24e933 3805 struct net_device *netdev = adapter->netdev;
9d5c8243
AK		 3806 struct e1000_hw *hw = &adapter->hw;
3807 struct pci_dev *pdev = adapter->pdev;
3808 u16 phy_tmp;
3809
3810#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3811
3812 /*
3813 * Prevent stats update while adapter is being reset, or if the pci
3814 * connection is down.
3815 */
3816 if (adapter->link_speed == 0)
3817 return;
3818 if (pci_channel_offline(pdev))
3819 return;
3820
3821 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3822 adapter->stats.gprc += rd32(E1000_GPRC);
3823 adapter->stats.gorc += rd32(E1000_GORCL);
3824 rd32(E1000_GORCH); /* clear GORCL */
3825 adapter->stats.bprc += rd32(E1000_BPRC);
3826 adapter->stats.mprc += rd32(E1000_MPRC);
3827 adapter->stats.roc += rd32(E1000_ROC);
3828
3829 adapter->stats.prc64 += rd32(E1000_PRC64);
3830 adapter->stats.prc127 += rd32(E1000_PRC127);
3831 adapter->stats.prc255 += rd32(E1000_PRC255);
3832 adapter->stats.prc511 += rd32(E1000_PRC511);
3833 adapter->stats.prc1023 += rd32(E1000_PRC1023);
3834 adapter->stats.prc1522 += rd32(E1000_PRC1522);
3835 adapter->stats.symerrs += rd32(E1000_SYMERRS);
3836 adapter->stats.sec += rd32(E1000_SEC);
3837
3838 adapter->stats.mpc += rd32(E1000_MPC);
3839 adapter->stats.scc += rd32(E1000_SCC);
3840 adapter->stats.ecol += rd32(E1000_ECOL);
3841 adapter->stats.mcc += rd32(E1000_MCC);
3842 adapter->stats.latecol += rd32(E1000_LATECOL);
3843 adapter->stats.dc += rd32(E1000_DC);
3844 adapter->stats.rlec += rd32(E1000_RLEC);
3845 adapter->stats.xonrxc += rd32(E1000_XONRXC);
3846 adapter->stats.xontxc += rd32(E1000_XONTXC);
3847 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
3848 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
3849 adapter->stats.fcruc += rd32(E1000_FCRUC);
3850 adapter->stats.gptc += rd32(E1000_GPTC);
3851 adapter->stats.gotc += rd32(E1000_GOTCL);
3852 rd32(E1000_GOTCH); /* clear GOTCL */
3853 adapter->stats.rnbc += rd32(E1000_RNBC);
3854 adapter->stats.ruc += rd32(E1000_RUC);
3855 adapter->stats.rfc += rd32(E1000_RFC);
3856 adapter->stats.rjc += rd32(E1000_RJC);
3857 adapter->stats.tor += rd32(E1000_TORH);
3858 adapter->stats.tot += rd32(E1000_TOTH);
3859 adapter->stats.tpr += rd32(E1000_TPR);
3860
3861 adapter->stats.ptc64 += rd32(E1000_PTC64);
3862 adapter->stats.ptc127 += rd32(E1000_PTC127);
3863 adapter->stats.ptc255 += rd32(E1000_PTC255);
3864 adapter->stats.ptc511 += rd32(E1000_PTC511);
3865 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
3866 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
3867
3868 adapter->stats.mptc += rd32(E1000_MPTC);
3869 adapter->stats.bptc += rd32(E1000_BPTC);
3870
3871 /* used for adaptive IFS */
3872
3873 hw->mac.tx_packet_delta = rd32(E1000_TPT);
3874 adapter->stats.tpt += hw->mac.tx_packet_delta;
3875 hw->mac.collision_delta = rd32(E1000_COLC);
3876 adapter->stats.colc += hw->mac.collision_delta;
3877
3878 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
3879 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3880 adapter->stats.tncrs += rd32(E1000_TNCRS);
3881 adapter->stats.tsctc += rd32(E1000_TSCTC);
3882 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
3883
3884 adapter->stats.iac += rd32(E1000_IAC);
3885 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
3886 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
3887 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
3888 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
3889 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
3890 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
3891 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
3892 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
3893
3894 /* Fill out the OS statistics structure */
8d24e933
AK		 3895 netdev->stats.multicast = adapter->stats.mprc;
3896 netdev->stats.collisions = adapter->stats.colc;
9d5c8243
AK		 3897
3898 /* Rx Errors */
3899
8c0ab70a
JDB		 3900 if (hw->mac.type != e1000_82575) {
3901 u32 rqdpc_tmp;
3ea73afa 3902 u64 rqdpc_total = 0;
8c0ab70a
JDB		 3903 int i;
3904 /* Read out drops stats per RX queue. Notice RQDPC (Receive
3905 * Queue Drop Packet Count) stats only gets incremented, if
3906 * the DROP_EN but it set (in the SRRCTL register for that
3907 * queue). If DROP_EN bit is NOT set, then the some what
3908 * equivalent count is stored in RNBC (not per queue basis).
3909 * Also note the drop count is due to lack of available
3910 * descriptors.
3911 */
3912 for (i = 0; i < adapter->num_rx_queues; i++) {
3913 rqdpc_tmp = rd32(E1000_RQDPC(i)) & 0xFFF;
3914 adapter->rx_ring[i].rx_stats.drops += rqdpc_tmp;
3ea73afa 3915 rqdpc_total += adapter->rx_ring[i].rx_stats.drops;
8c0ab70a 3916 }
8d24e933 3917 netdev->stats.rx_fifo_errors = rqdpc_total;
8c0ab70a
JDB		 3918 }
3919
3ea73afa
JDB		 3920 /* Note RNBC (Receive No Buffers Count) is an not an exact
3921 * drop count as the hardware FIFO might save the day. Thats
3922 * one of the reason for saving it in rx_fifo_errors, as its
3923 * potentially not a true drop.
3924 */
8d24e933 3925 netdev->stats.rx_fifo_errors += adapter->stats.rnbc;
3ea73afa 3926
9d5c8243 3927 /* RLEC on some newer hardware can be incorrect so build
8c0ab70a 3928 * our own version based on RUC and ROC */
8d24e933 3929 netdev->stats.rx_errors = adapter->stats.rxerrc +
9d5c8243
AK		 3930 adapter->stats.crcerrs + adapter->stats.algnerrc +
3931 adapter->stats.ruc + adapter->stats.roc +
3932 adapter->stats.cexterr;
8d24e933 3933 netdev->stats.rx_length_errors = adapter->stats.ruc +
9d5c8243 3934 adapter->stats.roc;
8d24e933
AK		 3935 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
3936 netdev->stats.rx_frame_errors = adapter->stats.algnerrc;
3937 netdev->stats.rx_missed_errors = adapter->stats.mpc;
9d5c8243
AK		 3938
3939 /* Tx Errors */
8d24e933 3940 netdev->stats.tx_errors = adapter->stats.ecol +
9d5c8243 3941 adapter->stats.latecol;
8d24e933
AK		 3942 netdev->stats.tx_aborted_errors = adapter->stats.ecol;
3943 netdev->stats.tx_window_errors = adapter->stats.latecol;
3944 netdev->stats.tx_carrier_errors = adapter->stats.tncrs;
9d5c8243
AK		 3945
3946 /* Tx Dropped needs to be maintained elsewhere */
3947
3948 /* Phy Stats */
3949 if (hw->phy.media_type == e1000_media_type_copper) {
3950 if ((adapter->link_speed == SPEED_1000) &&
73cd78f1 3951 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
9d5c8243
AK		 3952 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3953 adapter->phy_stats.idle_errors += phy_tmp;
3954 }
3955 }
3956
3957 /* Management Stats */
3958 adapter->stats.mgptc += rd32(E1000_MGTPTC);
3959 adapter->stats.mgprc += rd32(E1000_MGTPRC);
3960 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3961}
3962
9d5c8243
AK		 3963static irqreturn_t igb_msix_other(int irq, void *data)
3964{
047e0030 3965 struct igb_adapter *adapter = data;
9d5c8243 3966 struct e1000_hw *hw = &adapter->hw;
844290e5 3967 u32 icr = rd32(E1000_ICR);
844290e5 3968 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083 3969
047e0030 3970 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 3971 /* HW is reporting DMA is out of sync */
3972 adapter->stats.doosync++;
3973 }
eebbbdba 3974
4ae196df
AD		 3975 /* Check for a mailbox event */
3976 if (icr & E1000_ICR_VMMB)
3977 igb_msg_task(adapter);
3978
3979 if (icr & E1000_ICR_LSC) {
3980 hw->mac.get_link_status = 1;
3981 /* guard against interrupt when we're going down */
3982 if (!test_bit(__IGB_DOWN, &adapter->state))
3983 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3984 }
3985
3986 wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_VMMB);
844290e5 3987 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 3988
3989 return IRQ_HANDLED;
3990}
3991
047e0030 3992static void igb_write_itr(struct igb_q_vector *q_vector)
9d5c8243 3993{
047e0030 3994 u32 itr_val = q_vector->itr_val & 0x7FFC;
9d5c8243 3995
047e0030
AD		 3996 if (!q_vector->set_itr)
3997 return;
73cd78f1 3998
047e0030
AD		 3999 if (!itr_val)
4000 itr_val = 0x4;
661086df 4001
047e0030
AD		 4002 if (q_vector->itr_shift)
4003 itr_val |= itr_val << q_vector->itr_shift;
661086df 4004 else
047e0030 4005 itr_val |= 0x8000000;
661086df 4006
047e0030
AD		 4007 writel(itr_val, q_vector->itr_register);
4008 q_vector->set_itr = 0;
6eb5a7f1
AD		 4009}
4010
047e0030 4011static irqreturn_t igb_msix_ring(int irq, void *data)
9d5c8243 4012{
047e0030 4013 struct igb_q_vector *q_vector = data;
9d5c8243 4014
047e0030
AD		 4015 /* Write the ITR value calculated from the previous interrupt. */
4016 igb_write_itr(q_vector);
9d5c8243 4017
047e0030 4018 napi_schedule(&q_vector->napi);
844290e5 4019
047e0030 4020 return IRQ_HANDLED;
fe4506b6
JC		 4021}
4022
421e02f0 4023#ifdef CONFIG_IGB_DCA
047e0030 4024static void igb_update_dca(struct igb_q_vector *q_vector)
fe4506b6 4025{
047e0030 4026 struct igb_adapter *adapter = q_vector->adapter;
fe4506b6
JC		 4027 struct e1000_hw *hw = &adapter->hw;
4028 int cpu = get_cpu();
fe4506b6 4029
047e0030
AD		 4030 if (q_vector->cpu == cpu)
4031 goto out_no_update;
4032
4033 if (q_vector->tx_ring) {
4034 int q = q_vector->tx_ring->reg_idx;
4035 u32 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
4036 if (hw->mac.type == e1000_82575) {
4037 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
4038 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
2d064c06 4039 } else {
047e0030
AD		 4040 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
4041 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
4042 E1000_DCA_TXCTRL_CPUID_SHIFT;
4043 }
4044 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
4045 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
4046 }
4047 if (q_vector->rx_ring) {
4048 int q = q_vector->rx_ring->reg_idx;
4049 u32 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
4050 if (hw->mac.type == e1000_82575) {
2d064c06 4051 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
92be7917 4052 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
047e0030
AD		 4053 } else {
4054 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
4055 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
4056 E1000_DCA_RXCTRL_CPUID_SHIFT;
2d064c06 4057 }
fe4506b6
JC		 4058 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
4059 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
4060 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
4061 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
fe4506b6 4062 }
047e0030
AD		 4063 q_vector->cpu = cpu;
4064out_no_update:
fe4506b6
JC		 4065 put_cpu();
4066}
4067
4068static void igb_setup_dca(struct igb_adapter *adapter)
4069{
7e0e99ef 4070 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 4071 int i;
4072
7dfc16fa 4073 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 4074 return;
4075
7e0e99ef
AD		 4076 /* Always use CB2 mode, difference is masked in the CB driver. */
4077 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
4078
047e0030
AD		 4079 for (i = 0; i < adapter->num_q_vectors; i++) {
4080 struct igb_q_vector *q_vector = adapter->q_vector[i];
4081 q_vector->cpu = -1;
4082 igb_update_dca(q_vector);
fe4506b6
JC		 4083 }
4084}
4085
4086static int __igb_notify_dca(struct device *dev, void *data)
4087{
4088 struct net_device *netdev = dev_get_drvdata(dev);
4089 struct igb_adapter *adapter = netdev_priv(netdev);
4090 struct e1000_hw *hw = &adapter->hw;
4091 unsigned long event = *(unsigned long *)data;
4092
4093 switch (event) {
4094 case DCA_PROVIDER_ADD:
4095 /* if already enabled, don't do it again */
7dfc16fa 4096 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 4097 break;
fe4506b6
JC		 4098 /* Always use CB2 mode, difference is masked
4099 * in the CB driver. */
cbd347ad 4100 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
fe4506b6 4101 if (dca_add_requester(dev) == 0) {
bbd98fe4 4102 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 4103 dev_info(&adapter->pdev->dev, "DCA enabled\n");
4104 igb_setup_dca(adapter);
4105 break;
4106 }
4107 /* Fall Through since DCA is disabled. */
4108 case DCA_PROVIDER_REMOVE:
7dfc16fa 4109 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6 4110 /* without this a class_device is left
047e0030 4111 * hanging around in the sysfs model */
fe4506b6
JC		 4112 dca_remove_requester(dev);
4113 dev_info(&adapter->pdev->dev, "DCA disabled\n");
7dfc16fa 4114 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 4115 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 4116 }
4117 break;
4118 }
bbd98fe4 4119
fe4506b6 4120 return 0;
9d5c8243
AK		 4121}
4122
fe4506b6
JC		 4123static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
4124 void *p)
4125{
4126 int ret_val;
4127
4128 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
4129 __igb_notify_dca);
4130
4131 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
4132}
421e02f0 4133#endif /* CONFIG_IGB_DCA */
9d5c8243 4134
4ae196df
AD		 4135static void igb_ping_all_vfs(struct igb_adapter *adapter)
4136{
4137 struct e1000_hw *hw = &adapter->hw;
4138 u32 ping;
4139 int i;
4140
4141 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
4142 ping = E1000_PF_CONTROL_MSG;
4143 if (adapter->vf_data[i].clear_to_send)
4144 ping |= E1000_VT_MSGTYPE_CTS;
4145 igb_write_mbx(hw, &ping, 1, i);
4146 }
4147}
4148
4149static int igb_set_vf_multicasts(struct igb_adapter *adapter,
4150 u32 *msgbuf, u32 vf)
4151{
4152 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
4153 u16 *hash_list = (u16 *)&msgbuf[1];
4154 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4155 int i;
4156
4157 /* only up to 30 hash values supported */
4158 if (n > 30)
4159 n = 30;
4160
4161 /* salt away the number of multi cast addresses assigned
4162 * to this VF for later use to restore when the PF multi cast
4163 * list changes
4164 */
4165 vf_data->num_vf_mc_hashes = n;
4166
4167 /* VFs are limited to using the MTA hash table for their multicast
4168 * addresses */
4169 for (i = 0; i < n; i++)
a419aef8 4170 vf_data->vf_mc_hashes[i] = hash_list[i];
4ae196df
AD		 4171
4172 /* Flush and reset the mta with the new values */
ff41f8dc 4173 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 4174
4175 return 0;
4176}
4177
4178static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
4179{
4180 struct e1000_hw *hw = &adapter->hw;
4181 struct vf_data_storage *vf_data;
4182 int i, j;
4183
4184 for (i = 0; i < adapter->vfs_allocated_count; i++) {
4185 vf_data = &adapter->vf_data[i];
75f4f382 4186 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
4ae196df
AD		 4187 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
4188 }
4189}
4190
4191static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
4192{
4193 struct e1000_hw *hw = &adapter->hw;
4194 u32 pool_mask, reg, vid;
4195 int i;
4196
4197 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
4198
4199 /* Find the vlan filter for this id */
4200 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4201 reg = rd32(E1000_VLVF(i));
4202
4203 /* remove the vf from the pool */
4204 reg &= ~pool_mask;
4205
4206 /* if pool is empty then remove entry from vfta */
4207 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
4208 (reg & E1000_VLVF_VLANID_ENABLE)) {
4209 reg = 0;
4210 vid = reg & E1000_VLVF_VLANID_MASK;
4211 igb_vfta_set(hw, vid, false);
4212 }
4213
4214 wr32(E1000_VLVF(i), reg);
4215 }
ae641bdc
AD		 4216
4217 adapter->vf_data[vf].vlans_enabled = 0;
4ae196df
AD		 4218}
4219
4220static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
4221{
4222 struct e1000_hw *hw = &adapter->hw;
4223 u32 reg, i;
4224
4225 /* It is an error to call this function when VFs are not enabled */
4226 if (!adapter->vfs_allocated_count)
4227 return -1;
4228
4229 /* Find the vlan filter for this id */
4230 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4231 reg = rd32(E1000_VLVF(i));
4232 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
4233 vid == (reg & E1000_VLVF_VLANID_MASK))
4234 break;
4235 }
4236
4237 if (add) {
4238 if (i == E1000_VLVF_ARRAY_SIZE) {
4239 /* Did not find a matching VLAN ID entry that was
4240 * enabled. Search for a free filter entry, i.e.
4241 * one without the enable bit set
4242 */
4243 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4244 reg = rd32(E1000_VLVF(i));
4245 if (!(reg & E1000_VLVF_VLANID_ENABLE))
4246 break;
4247 }
4248 }
4249 if (i < E1000_VLVF_ARRAY_SIZE) {
4250 /* Found an enabled/available entry */
4251 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
4252
4253 /* if !enabled we need to set this up in vfta */
4254 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
cad6d05f
AD		 4255 /* add VID to filter table, if bit already set
4256 * PF must have added it outside of table */
4257 if (igb_vfta_set(hw, vid, true))
4258 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT +
4259 adapter->vfs_allocated_count);
4ae196df
AD		 4260 reg |= E1000_VLVF_VLANID_ENABLE;
4261 }
cad6d05f
AD		 4262 reg &= ~E1000_VLVF_VLANID_MASK;
4263 reg |= vid;
4ae196df
AD		 4264
4265 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 4266
4267 /* do not modify RLPML for PF devices */
4268 if (vf >= adapter->vfs_allocated_count)
4269 return 0;
4270
4271 if (!adapter->vf_data[vf].vlans_enabled) {
4272 u32 size;
4273 reg = rd32(E1000_VMOLR(vf));
4274 size = reg & E1000_VMOLR_RLPML_MASK;
4275 size += 4;
4276 reg &= ~E1000_VMOLR_RLPML_MASK;
4277 reg |= size;
4278 wr32(E1000_VMOLR(vf), reg);
4279 }
4280 adapter->vf_data[vf].vlans_enabled++;
4281
4ae196df
AD		 4282 return 0;
4283 }
4284 } else {
4285 if (i < E1000_VLVF_ARRAY_SIZE) {
4286 /* remove vf from the pool */
4287 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
4288 /* if pool is empty then remove entry from vfta */
4289 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
4290 reg = 0;
4291 igb_vfta_set(hw, vid, false);
4292 }
4293 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 4294
4295 /* do not modify RLPML for PF devices */
4296 if (vf >= adapter->vfs_allocated_count)
4297 return 0;
4298
4299 adapter->vf_data[vf].vlans_enabled--;
4300 if (!adapter->vf_data[vf].vlans_enabled) {
4301 u32 size;
4302 reg = rd32(E1000_VMOLR(vf));
4303 size = reg & E1000_VMOLR_RLPML_MASK;
4304 size -= 4;
4305 reg &= ~E1000_VMOLR_RLPML_MASK;
4306 reg |= size;
4307 wr32(E1000_VMOLR(vf), reg);
4308 }
4ae196df
AD		 4309 return 0;
4310 }
4311 }
4312 return -1;
4313}
4314
4315static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
4316{
4317 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
4318 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
4319
4320 return igb_vlvf_set(adapter, vid, add, vf);
4321}
4322
4323static inline void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
4324{
4325 struct e1000_hw *hw = &adapter->hw;
4326
4327 /* disable mailbox functionality for vf */
4328 adapter->vf_data[vf].clear_to_send = false;
4329
4330 /* reset offloads to defaults */
4331 igb_set_vmolr(hw, vf);
4332
4333 /* reset vlans for device */
4334 igb_clear_vf_vfta(adapter, vf);
4335
4336 /* reset multicast table array for vf */
4337 adapter->vf_data[vf].num_vf_mc_hashes = 0;
4338
4339 /* Flush and reset the mta with the new values */
ff41f8dc 4340 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 4341}
4342
4343static inline void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4344{
4345 struct e1000_hw *hw = &adapter->hw;
4346 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 4347 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 4348 u32 reg, msgbuf[3];
4349 u8 *addr = (u8 *)(&msgbuf[1]);
4350
4351 /* process all the same items cleared in a function level reset */
4352 igb_vf_reset_event(adapter, vf);
4353
4354 /* set vf mac address */
26ad9178 4355 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4ae196df
AD		 4356
4357 /* enable transmit and receive for vf */
4358 reg = rd32(E1000_VFTE);
4359 wr32(E1000_VFTE, reg | (1 << vf));
4360 reg = rd32(E1000_VFRE);
4361 wr32(E1000_VFRE, reg | (1 << vf));
4362
4363 /* enable mailbox functionality for vf */
4364 adapter->vf_data[vf].clear_to_send = true;
4365
4366 /* reply to reset with ack and vf mac address */
4367 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
4368 memcpy(addr, vf_mac, 6);
4369 igb_write_mbx(hw, msgbuf, 3, vf);
4370}
4371
4372static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
4373{
4374 unsigned char *addr = (char *)&msg[1];
4375 int err = -1;
4376
4377 if (is_valid_ether_addr(addr))
4378 err = igb_set_vf_mac(adapter, vf, addr);
4379
4380 return err;
4381
4382}
4383
4384static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
4385{
4386 struct e1000_hw *hw = &adapter->hw;
4387 u32 msg = E1000_VT_MSGTYPE_NACK;
4388
4389 /* if device isn't clear to send it shouldn't be reading either */
4390 if (!adapter->vf_data[vf].clear_to_send)
4391 igb_write_mbx(hw, &msg, 1, vf);
4392}
4393
4394
4395static void igb_msg_task(struct igb_adapter *adapter)
4396{
4397 struct e1000_hw *hw = &adapter->hw;
4398 u32 vf;
4399
4400 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
4401 /* process any reset requests */
4402 if (!igb_check_for_rst(hw, vf)) {
4403 adapter->vf_data[vf].clear_to_send = false;
4404 igb_vf_reset_event(adapter, vf);
4405 }
4406
4407 /* process any messages pending */
4408 if (!igb_check_for_msg(hw, vf))
4409 igb_rcv_msg_from_vf(adapter, vf);
4410
4411 /* process any acks */
4412 if (!igb_check_for_ack(hw, vf))
4413 igb_rcv_ack_from_vf(adapter, vf);
4414
4415 }
4416}
4417
4418static int igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4419{
4420 u32 mbx_size = E1000_VFMAILBOX_SIZE;
4421 u32 msgbuf[mbx_size];
4422 struct e1000_hw *hw = &adapter->hw;
4423 s32 retval;
4424
4425 retval = igb_read_mbx(hw, msgbuf, mbx_size, vf);
4426
4427 if (retval)
4428 dev_err(&adapter->pdev->dev,
4429 "Error receiving message from VF\n");
4430
4431 /* this is a message we already processed, do nothing */
4432 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
4433 return retval;
4434
4435 /*
4436 * until the vf completes a reset it should not be
4437 * allowed to start any configuration.
4438 */
4439
4440 if (msgbuf[0] == E1000_VF_RESET) {
4441 igb_vf_reset_msg(adapter, vf);
4442
4443 return retval;
4444 }
4445
4446 if (!adapter->vf_data[vf].clear_to_send) {
4447 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4448 igb_write_mbx(hw, msgbuf, 1, vf);
4449 return retval;
4450 }
4451
4452 switch ((msgbuf[0] & 0xFFFF)) {
4453 case E1000_VF_SET_MAC_ADDR:
4454 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
4455 break;
4456 case E1000_VF_SET_MULTICAST:
4457 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
4458 break;
4459 case E1000_VF_SET_LPE:
4460 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
4461 break;
4462 case E1000_VF_SET_VLAN:
4463 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4464 break;
4465 default:
4466 dev_err(&adapter->pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4467 retval = -1;
4468 break;
4469 }
4470
4471 /* notify the VF of the results of what it sent us */
4472 if (retval)
4473 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4474 else
4475 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
4476
4477 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
4478
4479 igb_write_mbx(hw, msgbuf, 1, vf);
4480
4481 return retval;
4482}
4483
68d480c4
AD		 4484/**
4485 * igb_set_uta - Set unicast filter table address
4486 * @adapter: board private structure
4487 *
4488 * The unicast table address is a register array of 32-bit registers.
4489 * The table is meant to be used in a way similar to how the MTA is used
4490 * however due to certain limitations in the hardware it is necessary to
4491 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscous
4492 * enable bit to allow vlan tag stripping when promiscous mode is enabled
4493 **/
4494static void igb_set_uta(struct igb_adapter *adapter)
4495{
4496 struct e1000_hw *hw = &adapter->hw;
4497 int i;
4498
4499 /* The UTA table only exists on 82576 hardware and newer */
4500 if (hw->mac.type < e1000_82576)
4501 return;
4502
4503 /* we only need to do this if VMDq is enabled */
4504 if (!adapter->vfs_allocated_count)
4505 return;
4506
4507 for (i = 0; i < hw->mac.uta_reg_count; i++)
4508 array_wr32(E1000_UTA, i, ~0);
4509}
4510
9d5c8243
AK		 4511/**
4512 * igb_intr_msi - Interrupt Handler
4513 * @irq: interrupt number
4514 * @data: pointer to a network interface device structure
4515 **/
4516static irqreturn_t igb_intr_msi(int irq, void *data)
4517{
047e0030
AD		 4518 struct igb_adapter *adapter = data;
4519 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 4520 struct e1000_hw *hw = &adapter->hw;
4521 /* read ICR disables interrupts using IAM */
4522 u32 icr = rd32(E1000_ICR);
4523
047e0030 4524 igb_write_itr(q_vector);
9d5c8243 4525
047e0030 4526 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 4527 /* HW is reporting DMA is out of sync */
4528 adapter->stats.doosync++;
4529 }
4530
9d5c8243
AK		 4531 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4532 hw->mac.get_link_status = 1;
4533 if (!test_bit(__IGB_DOWN, &adapter->state))
4534 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4535 }
4536
047e0030 4537 napi_schedule(&q_vector->napi);
9d5c8243
AK		 4538
4539 return IRQ_HANDLED;
4540}
4541
4542/**
4a3c6433 4543 * igb_intr - Legacy Interrupt Handler
9d5c8243
AK		 4544 * @irq: interrupt number
4545 * @data: pointer to a network interface device structure
4546 **/
4547static irqreturn_t igb_intr(int irq, void *data)
4548{
047e0030
AD		 4549 struct igb_adapter *adapter = data;
4550 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 4551 struct e1000_hw *hw = &adapter->hw;
4552 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
4553 * need for the IMC write */
4554 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 4555 if (!icr)
4556 return IRQ_NONE; /* Not our interrupt */
4557
047e0030 4558 igb_write_itr(q_vector);
9d5c8243
AK		 4559
4560 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
4561 * not set, then the adapter didn't send an interrupt */
4562 if (!(icr & E1000_ICR_INT_ASSERTED))
4563 return IRQ_NONE;
4564
047e0030 4565 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 4566 /* HW is reporting DMA is out of sync */
4567 adapter->stats.doosync++;
4568 }
4569
9d5c8243
AK		 4570 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4571 hw->mac.get_link_status = 1;
4572 /* guard against interrupt when we're going down */
4573 if (!test_bit(__IGB_DOWN, &adapter->state))
4574 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4575 }
4576
047e0030 4577 napi_schedule(&q_vector->napi);
9d5c8243
AK		 4578
4579 return IRQ_HANDLED;
4580}
4581
047e0030 4582static inline void igb_ring_irq_enable(struct igb_q_vector *q_vector)
9d5c8243 4583{
047e0030 4584 struct igb_adapter *adapter = q_vector->adapter;
46544258 4585 struct e1000_hw *hw = &adapter->hw;
9d5c8243 4586
46544258 4587 if (adapter->itr_setting & 3) {
047e0030 4588 if (!adapter->msix_entries)
6eb5a7f1 4589 igb_set_itr(adapter);
46544258 4590 else
047e0030 4591 igb_update_ring_itr(q_vector);
9d5c8243
AK		 4592 }
4593
46544258
AD		 4594 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4595 if (adapter->msix_entries)
047e0030 4596 wr32(E1000_EIMS, q_vector->eims_value);
46544258
AD		 4597 else
4598 igb_irq_enable(adapter);
4599 }
9d5c8243
AK		 4600}
4601
46544258
AD		 4602/**
4603 * igb_poll - NAPI Rx polling callback
4604 * @napi: napi polling structure
4605 * @budget: count of how many packets we should handle
4606 **/
4607static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 4608{
047e0030
AD		 4609 struct igb_q_vector *q_vector = container_of(napi,
4610 struct igb_q_vector,
4611 napi);
4612 int tx_clean_complete = 1, work_done = 0;
9d5c8243 4613
421e02f0 4614#ifdef CONFIG_IGB_DCA
047e0030
AD		 4615 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
4616 igb_update_dca(q_vector);
fe4506b6 4617#endif
047e0030
AD		 4618 if (q_vector->tx_ring)
4619 tx_clean_complete = igb_clean_tx_irq(q_vector);
9d5c8243 4620
047e0030
AD		 4621 if (q_vector->rx_ring)
4622 igb_clean_rx_irq_adv(q_vector, &work_done, budget);
4623
4624 if (!tx_clean_complete)
4625 work_done = budget;
46544258 4626
9d5c8243 4627 /* If not enough Rx work done, exit the polling mode */
5e6d5b17 4628 if (work_done < budget) {
288379f0 4629 napi_complete(napi);
047e0030 4630 igb_ring_irq_enable(q_vector);
9d5c8243
AK		 4631 }
4632
46544258 4633 return work_done;
9d5c8243 4634}
6d8126f9 4635
33af6bcc
PO		 4636/**
4637 * igb_hwtstamp - utility function which checks for TX time stamp
4638 * @adapter: board private structure
4639 * @skb: packet that was just sent
4640 *
4641 * If we were asked to do hardware stamping and such a time stamp is
4642 * available, then it must have been for this skb here because we only
4643 * allow only one such packet into the queue.
4644 */
4645static void igb_tx_hwtstamp(struct igb_adapter *adapter, struct sk_buff *skb)
4646{
4647 union skb_shared_tx *shtx = skb_tx(skb);
4648 struct e1000_hw *hw = &adapter->hw;
4649
4650 if (unlikely(shtx->hardware)) {
4651 u32 valid = rd32(E1000_TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID;
4652 if (valid) {
4653 u64 regval = rd32(E1000_TXSTMPL);
4654 u64 ns;
4655 struct skb_shared_hwtstamps shhwtstamps;
4656
4657 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
4658 regval |= (u64)rd32(E1000_TXSTMPH) << 32;
4659 ns = timecounter_cyc2time(&adapter->clock,
4660 regval);
4661 timecompare_update(&adapter->compare, ns);
4662 shhwtstamps.hwtstamp = ns_to_ktime(ns);
4663 shhwtstamps.syststamp =
4664 timecompare_transform(&adapter->compare, ns);
4665 skb_tstamp_tx(skb, &shhwtstamps);
4666 }
33af6bcc
PO		 4667 }
4668}
4669
9d5c8243
AK		 4670/**
4671 * igb_clean_tx_irq - Reclaim resources after transmit completes
047e0030 4672 * @q_vector: pointer to q_vector containing needed info
9d5c8243
AK		 4673 * returns true if ring is completely cleaned
4674 **/
047e0030 4675static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
9d5c8243 4676{
047e0030
AD		 4677 struct igb_adapter *adapter = q_vector->adapter;
4678 struct igb_ring *tx_ring = q_vector->tx_ring;
3b644cf6 4679 struct net_device *netdev = adapter->netdev;
0e014cb1 4680 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 4681 struct igb_buffer *buffer_info;
4682 struct sk_buff *skb;
0e014cb1 4683 union e1000_adv_tx_desc *tx_desc, *eop_desc;
9d5c8243 4684 unsigned int total_bytes = 0, total_packets = 0;
0e014cb1
AD		 4685 unsigned int i, eop, count = 0;
4686 bool cleaned = false;
9d5c8243 4687
9d5c8243 4688 i = tx_ring->next_to_clean;
0e014cb1
AD		 4689 eop = tx_ring->buffer_info[i].next_to_watch;
4690 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4691
4692 while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) &&
4693 (count < tx_ring->count)) {
4694 for (cleaned = false; !cleaned; count++) {
4695 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
9d5c8243 4696 buffer_info = &tx_ring->buffer_info[i];
0e014cb1 4697 cleaned = (i == eop);
9d5c8243
AK		 4698 skb = buffer_info->skb;
4699
4700 if (skb) {
4701 unsigned int segs, bytecount;
4702 /* gso_segs is currently only valid for tcp */
4703 segs = skb_shinfo(skb)->gso_segs ?: 1;
4704 /* multiply data chunks by size of headers */
4705 bytecount = ((segs - 1) * skb_headlen(skb)) +
4706 skb->len;
4707 total_packets += segs;
4708 total_bytes += bytecount;
33af6bcc
PO		 4709
4710 igb_tx_hwtstamp(adapter, skb);
9d5c8243
AK		 4711 }
4712
4713 igb_unmap_and_free_tx_resource(adapter, buffer_info);
0e014cb1 4714 tx_desc->wb.status = 0;
9d5c8243
AK		 4715
4716 i++;
4717 if (i == tx_ring->count)
4718 i = 0;
9d5c8243 4719 }
0e014cb1
AD		 4720 eop = tx_ring->buffer_info[i].next_to_watch;
4721 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4722 }
4723
9d5c8243
AK		 4724 tx_ring->next_to_clean = i;
4725
fc7d345d 4726 if (unlikely(count &&
9d5c8243 4727 netif_carrier_ok(netdev) &&
c493ea45 4728 igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
9d5c8243
AK		 4729 /* Make sure that anybody stopping the queue after this
4730 * sees the new next_to_clean.
4731 */
4732 smp_mb();
661086df
PWJ		 4733 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
4734 !(test_bit(__IGB_DOWN, &adapter->state))) {
4735 netif_wake_subqueue(netdev, tx_ring->queue_index);
4736 ++adapter->restart_queue;
4737 }
9d5c8243
AK		 4738 }
4739
4740 if (tx_ring->detect_tx_hung) {
4741 /* Detect a transmit hang in hardware, this serializes the
4742 * check with the clearing of time_stamp and movement of i */
4743 tx_ring->detect_tx_hung = false;
4744 if (tx_ring->buffer_info[i].time_stamp &&
4745 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
4746 (adapter->tx_timeout_factor * HZ))
4747 && !(rd32(E1000_STATUS) &
4748 E1000_STATUS_TXOFF)) {
4749
9d5c8243
AK		 4750 /* detected Tx unit hang */
4751 dev_err(&adapter->pdev->dev,
4752 "Detected Tx Unit Hang\n"
2d064c06 4753 " Tx Queue <%d>\n"
9d5c8243
AK		 4754 " TDH <%x>\n"
4755 " TDT <%x>\n"
4756 " next_to_use <%x>\n"
4757 " next_to_clean <%x>\n"
9d5c8243
AK		 4758 "buffer_info[next_to_clean]\n"
4759 " time_stamp <%lx>\n"
0e014cb1 4760 " next_to_watch <%x>\n"
9d5c8243
AK		 4761 " jiffies <%lx>\n"
4762 " desc.status <%x>\n",
2d064c06 4763 tx_ring->queue_index,
fce99e34
AD		 4764 readl(tx_ring->head),
4765 readl(tx_ring->tail),
9d5c8243
AK		 4766 tx_ring->next_to_use,
4767 tx_ring->next_to_clean,
9d5c8243 4768 tx_ring->buffer_info[i].time_stamp,
0e014cb1 4769 eop,
9d5c8243 4770 jiffies,
0e014cb1 4771 eop_desc->wb.status);
661086df 4772 netif_stop_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 4773 }
4774 }
4775 tx_ring->total_bytes += total_bytes;
4776 tx_ring->total_packets += total_packets;
e21ed353
AD		 4777 tx_ring->tx_stats.bytes += total_bytes;
4778 tx_ring->tx_stats.packets += total_packets;
8d24e933
AK		 4779 netdev->stats.tx_bytes += total_bytes;
4780 netdev->stats.tx_packets += total_packets;
0e014cb1 4781 return (count < tx_ring->count);
9d5c8243
AK		 4782}
4783
9d5c8243
AK		 4784/**
4785 * igb_receive_skb - helper function to handle rx indications
047e0030
AD		 4786 * @q_vector: structure containing interrupt and ring information
4787 * @skb: packet to send up
4788 * @vlan_tag: vlan tag for packet
9d5c8243 4789 **/
047e0030
AD		 4790static void igb_receive_skb(struct igb_q_vector *q_vector,
4791 struct sk_buff *skb,
4792 u16 vlan_tag)
4793{
4794 struct igb_adapter *adapter = q_vector->adapter;
4795
4796 if (vlan_tag)
4797 vlan_gro_receive(&q_vector->napi, adapter->vlgrp,
4798 vlan_tag, skb);
182ff8df 4799 else
047e0030 4800 napi_gro_receive(&q_vector->napi, skb);
9d5c8243
AK		 4801}
4802
9d5c8243
AK		 4803static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
4804 u32 status_err, struct sk_buff *skb)
4805{
4806 skb->ip_summed = CHECKSUM_NONE;
4807
4808 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
7beb0146
AD		 4809 if ((status_err & E1000_RXD_STAT_IXSM) ||
4810 (adapter->flags & IGB_FLAG_RX_CSUM_DISABLED))
9d5c8243
AK		 4811 return;
4812 /* TCP/UDP checksum error bit is set */
4813 if (status_err &
4814 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
b9473560
JB		 4815 /*
4816 * work around errata with sctp packets where the TCPE aka
4817 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
4818 * packets, (aka let the stack check the crc32c)
4819 */
4820 if (!((adapter->hw.mac.type == e1000_82576) &&
4821 (skb->len == 60)))
4822 adapter->hw_csum_err++;
9d5c8243 4823 /* let the stack verify checksum errors */
9d5c8243
AK		 4824 return;
4825 }
4826 /* It must be a TCP or UDP packet with a valid checksum */
4827 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
4828 skb->ip_summed = CHECKSUM_UNNECESSARY;
4829
b9473560 4830 dev_dbg(&adapter->pdev->dev, "cksum success: bits %08X\n", status_err);
9d5c8243
AK		 4831}
4832
2d94d8ab
AD		 4833static inline u16 igb_get_hlen(struct igb_adapter *adapter,
4834 union e1000_adv_rx_desc *rx_desc)
4835{
4836 /* HW will not DMA in data larger than the given buffer, even if it
4837 * parses the (NFS, of course) header to be larger. In that case, it
4838 * fills the header buffer and spills the rest into the page.
4839 */
4840 u16 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
4841 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
6ec43fe6
AD		 4842 if (hlen > adapter->rx_buffer_len)
4843 hlen = adapter->rx_buffer_len;
2d94d8ab
AD		 4844 return hlen;
4845}
4846
047e0030
AD		 4847static bool igb_clean_rx_irq_adv(struct igb_q_vector *q_vector,
4848 int *work_done, int budget)
9d5c8243 4849{
047e0030 4850 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 4851 struct net_device *netdev = adapter->netdev;
047e0030 4852 struct igb_ring *rx_ring = q_vector->rx_ring;
33af6bcc 4853 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 4854 struct pci_dev *pdev = adapter->pdev;
4855 union e1000_adv_rx_desc *rx_desc , *next_rxd;
4856 struct igb_buffer *buffer_info , *next_buffer;
4857 struct sk_buff *skb;
9d5c8243
AK		 4858 bool cleaned = false;
4859 int cleaned_count = 0;
4860 unsigned int total_bytes = 0, total_packets = 0;
73cd78f1 4861 unsigned int i;
2d94d8ab
AD		 4862 u32 staterr;
4863 u16 length;
047e0030 4864 u16 vlan_tag;
9d5c8243
AK		 4865
4866 i = rx_ring->next_to_clean;
69d3ca53 4867 buffer_info = &rx_ring->buffer_info[i];
9d5c8243
AK		 4868 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4869 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4870
4871 while (staterr & E1000_RXD_STAT_DD) {
4872 if (*work_done >= budget)
4873 break;
4874 (*work_done)++;
9d5c8243 4875
69d3ca53
AD		 4876 skb = buffer_info->skb;
4877 prefetch(skb->data - NET_IP_ALIGN);
4878 buffer_info->skb = NULL;
4879
4880 i++;
4881 if (i == rx_ring->count)
4882 i = 0;
4883 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
4884 prefetch(next_rxd);
4885 next_buffer = &rx_ring->buffer_info[i];
9d5c8243
AK		 4886
4887 length = le16_to_cpu(rx_desc->wb.upper.length);
4888 cleaned = true;
4889 cleaned_count++;
4890
2d94d8ab 4891 if (buffer_info->dma) {
bf36c1a0 4892 pci_unmap_single(pdev, buffer_info->dma,
6ec43fe6 4893 adapter->rx_buffer_len,
bf36c1a0 4894 PCI_DMA_FROMDEVICE);
91615f76 4895 buffer_info->dma = 0;
6ec43fe6
AD		 4896 if (adapter->rx_buffer_len >= IGB_RXBUFFER_1024) {
4897 skb_put(skb, length);
4898 goto send_up;
4899 }
4900 skb_put(skb, igb_get_hlen(adapter, rx_desc));
bf36c1a0
AD		 4901 }
4902
4903 if (length) {
9d5c8243 4904 pci_unmap_page(pdev, buffer_info->page_dma,
bf36c1a0 4905 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9d5c8243 4906 buffer_info->page_dma = 0;
bf36c1a0
AD		 4907
4908 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
4909 buffer_info->page,
4910 buffer_info->page_offset,
4911 length);
4912
6ec43fe6 4913 if (page_count(buffer_info->page) != 1)
bf36c1a0
AD		 4914 buffer_info->page = NULL;
4915 else
4916 get_page(buffer_info->page);
9d5c8243
AK		 4917
4918 skb->len += length;
4919 skb->data_len += length;
9d5c8243 4920
bf36c1a0 4921 skb->truesize += length;
9d5c8243 4922 }
9d5c8243 4923
bf36c1a0 4924 if (!(staterr & E1000_RXD_STAT_EOP)) {
b2d56536
AD		 4925 buffer_info->skb = next_buffer->skb;
4926 buffer_info->dma = next_buffer->dma;
4927 next_buffer->skb = skb;
4928 next_buffer->dma = 0;
bf36c1a0
AD		 4929 goto next_desc;
4930 }
69d3ca53 4931send_up:
33af6bcc
PO		 4932 /*
4933 * If this bit is set, then the RX registers contain
4934 * the time stamp. No other packet will be time
4935 * stamped until we read these registers, so read the
4936 * registers to make them available again. Because
4937 * only one packet can be time stamped at a time, we
4938 * know that the register values must belong to this
4939 * one here and therefore we don't need to compare
4940 * any of the additional attributes stored for it.
4941 *
4942 * If nothing went wrong, then it should have a
4943 * skb_shared_tx that we can turn into a
4944 * skb_shared_hwtstamps.
4945 *
4946 * TODO: can time stamping be triggered (thus locking
4947 * the registers) without the packet reaching this point
4948 * here? In that case RX time stamping would get stuck.
4949 *
4950 * TODO: in "time stamp all packets" mode this bit is
4951 * not set. Need a global flag for this mode and then
4952 * always read the registers. Cannot be done without
4953 * a race condition.
4954 */
4955 if (unlikely(staterr & E1000_RXD_STAT_TS)) {
4956 u64 regval;
4957 u64 ns;
4958 struct skb_shared_hwtstamps *shhwtstamps =
4959 skb_hwtstamps(skb);
4960
4961 WARN(!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID),
4962 "igb: no RX time stamp available for time stamped packet");
4963 regval = rd32(E1000_RXSTMPL);
4964 regval |= (u64)rd32(E1000_RXSTMPH) << 32;
4965 ns = timecounter_cyc2time(&adapter->clock, regval);
4966 timecompare_update(&adapter->compare, ns);
4967 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
4968 shhwtstamps->hwtstamp = ns_to_ktime(ns);
4969 shhwtstamps->syststamp =
4970 timecompare_transform(&adapter->compare, ns);
4971 }
4972
9d5c8243
AK		 4973 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
4974 dev_kfree_skb_irq(skb);
4975 goto next_desc;
4976 }
9d5c8243
AK		 4977
4978 total_bytes += skb->len;
4979 total_packets++;
4980
4981 igb_rx_checksum_adv(adapter, staterr, skb);
4982
4983 skb->protocol = eth_type_trans(skb, netdev);
047e0030
AD		 4984 skb_record_rx_queue(skb, rx_ring->queue_index);
4985
4986 vlan_tag = ((staterr & E1000_RXD_STAT_VP) ?
4987 le16_to_cpu(rx_desc->wb.upper.vlan) : 0);
9d5c8243 4988
047e0030 4989 igb_receive_skb(q_vector, skb, vlan_tag);
9d5c8243 4990
9d5c8243
AK		 4991next_desc:
4992 rx_desc->wb.upper.status_error = 0;
4993
4994 /* return some buffers to hardware, one at a time is too slow */
4995 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
3b644cf6 4996 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 4997 cleaned_count = 0;
4998 }
4999
5000 /* use prefetched values */
5001 rx_desc = next_rxd;
5002 buffer_info = next_buffer;
9d5c8243
AK		 5003 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
5004 }
bf36c1a0 5005
9d5c8243 5006 rx_ring->next_to_clean = i;
c493ea45 5007 cleaned_count = igb_desc_unused(rx_ring);
9d5c8243
AK		 5008
5009 if (cleaned_count)
3b644cf6 5010 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 5011
5012 rx_ring->total_packets += total_packets;
5013 rx_ring->total_bytes += total_bytes;
5014 rx_ring->rx_stats.packets += total_packets;
5015 rx_ring->rx_stats.bytes += total_bytes;
8d24e933
AK		 5016 netdev->stats.rx_bytes += total_bytes;
5017 netdev->stats.rx_packets += total_packets;
9d5c8243
AK		 5018 return cleaned;
5019}
5020
9d5c8243
AK		 5021/**
5022 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
5023 * @adapter: address of board private structure
5024 **/
3b644cf6 5025static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
9d5c8243
AK		 5026 int cleaned_count)
5027{
047e0030 5028 struct igb_adapter *adapter = rx_ring->q_vector->adapter;
9d5c8243
AK		 5029 struct net_device *netdev = adapter->netdev;
5030 struct pci_dev *pdev = adapter->pdev;
5031 union e1000_adv_rx_desc *rx_desc;
5032 struct igb_buffer *buffer_info;
5033 struct sk_buff *skb;
5034 unsigned int i;
db761762 5035 int bufsz;
9d5c8243
AK		 5036
5037 i = rx_ring->next_to_use;
5038 buffer_info = &rx_ring->buffer_info[i];
5039
6ec43fe6 5040 bufsz = adapter->rx_buffer_len;
db761762 5041
9d5c8243
AK		 5042 while (cleaned_count--) {
5043 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
5044
6ec43fe6 5045 if ((bufsz < IGB_RXBUFFER_1024) && !buffer_info->page_dma) {
9d5c8243 5046 if (!buffer_info->page) {
bf36c1a0
AD		 5047 buffer_info->page = alloc_page(GFP_ATOMIC);
5048 if (!buffer_info->page) {
5049 adapter->alloc_rx_buff_failed++;
5050 goto no_buffers;
5051 }
5052 buffer_info->page_offset = 0;
5053 } else {
5054 buffer_info->page_offset ^= PAGE_SIZE / 2;
9d5c8243
AK		 5055 }
5056 buffer_info->page_dma =
db761762 5057 pci_map_page(pdev, buffer_info->page,
bf36c1a0
AD		 5058 buffer_info->page_offset,
5059 PAGE_SIZE / 2,
9d5c8243
AK		 5060 PCI_DMA_FROMDEVICE);
5061 }
5062
5063 if (!buffer_info->skb) {
89d71a66 5064 skb = netdev_alloc_skb_ip_align(netdev, bufsz);
9d5c8243
AK		 5065 if (!skb) {
5066 adapter->alloc_rx_buff_failed++;
5067 goto no_buffers;
5068 }
5069
9d5c8243
AK		 5070 buffer_info->skb = skb;
5071 buffer_info->dma = pci_map_single(pdev, skb->data,
5072 bufsz,
5073 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 5074 }
5075 /* Refresh the desc even if buffer_addrs didn't change because
5076 * each write-back erases this info. */
6ec43fe6 5077 if (bufsz < IGB_RXBUFFER_1024) {
9d5c8243
AK		 5078 rx_desc->read.pkt_addr =
5079 cpu_to_le64(buffer_info->page_dma);
5080 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
5081 } else {
5082 rx_desc->read.pkt_addr =
5083 cpu_to_le64(buffer_info->dma);
5084 rx_desc->read.hdr_addr = 0;
5085 }
5086
5087 i++;
5088 if (i == rx_ring->count)
5089 i = 0;
5090 buffer_info = &rx_ring->buffer_info[i];
5091 }
5092
5093no_buffers:
5094 if (rx_ring->next_to_use != i) {
5095 rx_ring->next_to_use = i;
5096 if (i == 0)
5097 i = (rx_ring->count - 1);
5098 else
5099 i--;
5100
5101 /* Force memory writes to complete before letting h/w
5102 * know there are new descriptors to fetch. (Only
5103 * applicable for weak-ordered memory model archs,
5104 * such as IA-64). */
5105 wmb();
fce99e34 5106 writel(i, rx_ring->tail);
9d5c8243
AK		 5107 }
5108}
5109
5110/**
5111 * igb_mii_ioctl -
5112 * @netdev:
5113 * @ifreq:
5114 * @cmd:
5115 **/
5116static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5117{
5118 struct igb_adapter *adapter = netdev_priv(netdev);
5119 struct mii_ioctl_data *data = if_mii(ifr);
5120
5121 if (adapter->hw.phy.media_type != e1000_media_type_copper)
5122 return -EOPNOTSUPP;
5123
5124 switch (cmd) {
5125 case SIOCGMIIPHY:
5126 data->phy_id = adapter->hw.phy.addr;
5127 break;
5128 case SIOCGMIIREG:
f5f4cf08
AD		 5129 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
5130 &data->val_out))
9d5c8243
AK		 5131 return -EIO;
5132 break;
5133 case SIOCSMIIREG:
5134 default:
5135 return -EOPNOTSUPP;
5136 }
5137 return 0;
5138}
5139
c6cb090b
PO		 5140/**
5141 * igb_hwtstamp_ioctl - control hardware time stamping
5142 * @netdev:
5143 * @ifreq:
5144 * @cmd:
5145 *
33af6bcc
PO		 5146 * Outgoing time stamping can be enabled and disabled. Play nice and
5147 * disable it when requested, although it shouldn't case any overhead
5148 * when no packet needs it. At most one packet in the queue may be
5149 * marked for time stamping, otherwise it would be impossible to tell
5150 * for sure to which packet the hardware time stamp belongs.
5151 *
5152 * Incoming time stamping has to be configured via the hardware
5153 * filters. Not all combinations are supported, in particular event
5154 * type has to be specified. Matching the kind of event packet is
5155 * not supported, with the exception of "all V2 events regardless of
5156 * level 2 or 4".
5157 *
c6cb090b
PO		 5158 **/
5159static int igb_hwtstamp_ioctl(struct net_device *netdev,
5160 struct ifreq *ifr, int cmd)
5161{
33af6bcc
PO		 5162 struct igb_adapter *adapter = netdev_priv(netdev);
5163 struct e1000_hw *hw = &adapter->hw;
c6cb090b 5164 struct hwtstamp_config config;
33af6bcc
PO		 5165 u32 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
5166 u32 tsync_rx_ctl_bit = E1000_TSYNCRXCTL_ENABLED;
5167 u32 tsync_rx_ctl_type = 0;
5168 u32 tsync_rx_cfg = 0;
5169 int is_l4 = 0;
5170 int is_l2 = 0;
5171 short port = 319; /* PTP */
5172 u32 regval;
c6cb090b
PO		 5173
5174 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
5175 return -EFAULT;
5176
5177 /* reserved for future extensions */
5178 if (config.flags)
5179 return -EINVAL;
5180
33af6bcc
PO		 5181 switch (config.tx_type) {
5182 case HWTSTAMP_TX_OFF:
5183 tsync_tx_ctl_bit = 0;
5184 break;
5185 case HWTSTAMP_TX_ON:
5186 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
5187 break;
5188 default:
5189 return -ERANGE;
5190 }
5191
5192 switch (config.rx_filter) {
5193 case HWTSTAMP_FILTER_NONE:
5194 tsync_rx_ctl_bit = 0;
5195 break;
5196 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
5197 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
5198 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
5199 case HWTSTAMP_FILTER_ALL:
5200 /*
5201 * register TSYNCRXCFG must be set, therefore it is not
5202 * possible to time stamp both Sync and Delay_Req messages
5203 * => fall back to time stamping all packets
5204 */
5205 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_ALL;
5206 config.rx_filter = HWTSTAMP_FILTER_ALL;
5207 break;
5208 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
5209 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
5210 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
5211 is_l4 = 1;
5212 break;
5213 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
5214 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
5215 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
5216 is_l4 = 1;
5217 break;
5218 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
5219 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
5220 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
5221 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE;
5222 is_l2 = 1;
5223 is_l4 = 1;
5224 config.rx_filter = HWTSTAMP_FILTER_SOME;
5225 break;
5226 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
5227 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
5228 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
5229 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE;
5230 is_l2 = 1;
5231 is_l4 = 1;
5232 config.rx_filter = HWTSTAMP_FILTER_SOME;
5233 break;
5234 case HWTSTAMP_FILTER_PTP_V2_EVENT:
5235 case HWTSTAMP_FILTER_PTP_V2_SYNC:
5236 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
5237 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_EVENT_V2;
5238 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
5239 is_l2 = 1;
5240 break;
5241 default:
5242 return -ERANGE;
5243 }
5244
5245 /* enable/disable TX */
5246 regval = rd32(E1000_TSYNCTXCTL);
5247 regval = (regval & ~E1000_TSYNCTXCTL_ENABLED) | tsync_tx_ctl_bit;
5248 wr32(E1000_TSYNCTXCTL, regval);
5249
5250 /* enable/disable RX, define which PTP packets are time stamped */
5251 regval = rd32(E1000_TSYNCRXCTL);
5252 regval = (regval & ~E1000_TSYNCRXCTL_ENABLED) | tsync_rx_ctl_bit;
5253 regval = (regval & ~0xE) | tsync_rx_ctl_type;
5254 wr32(E1000_TSYNCRXCTL, regval);
5255 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
5256
5257 /*
5258 * Ethertype Filter Queue Filter[0][15:0] = 0x88F7
5259 * (Ethertype to filter on)
5260 * Ethertype Filter Queue Filter[0][26] = 0x1 (Enable filter)
5261 * Ethertype Filter Queue Filter[0][30] = 0x1 (Enable Timestamping)
5262 */
5263 wr32(E1000_ETQF0, is_l2 ? 0x440088f7 : 0);
5264
5265 /* L4 Queue Filter[0]: only filter by source and destination port */
5266 wr32(E1000_SPQF0, htons(port));
5267 wr32(E1000_IMIREXT(0), is_l4 ?
5268 ((1<<12) | (1<<19) /* bypass size and control flags */) : 0);
5269 wr32(E1000_IMIR(0), is_l4 ?
5270 (htons(port)
5271 | (0<<16) /* immediate interrupt disabled */
5272 | 0 /* (1<<17) bit cleared: do not bypass
5273 destination port check */)
5274 : 0);
5275 wr32(E1000_FTQF0, is_l4 ?
5276 (0x11 /* UDP */
5277 | (1<<15) /* VF not compared */
5278 | (1<<27) /* Enable Timestamping */
5279 | (7<<28) /* only source port filter enabled,
5280 source/target address and protocol
5281 masked */)
5282 : ((1<<15) | (15<<28) /* all mask bits set = filter not
5283 enabled */));
5284
5285 wrfl();
5286
5287 adapter->hwtstamp_config = config;
5288
5289 /* clear TX/RX time stamp registers, just to be sure */
5290 regval = rd32(E1000_TXSTMPH);
5291 regval = rd32(E1000_RXSTMPH);
c6cb090b 5292
33af6bcc
PO		 5293 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
5294 -EFAULT : 0;
c6cb090b
PO		 5295}
5296
9d5c8243
AK		 5297/**
5298 * igb_ioctl -
5299 * @netdev:
5300 * @ifreq:
5301 * @cmd:
5302 **/
5303static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5304{
5305 switch (cmd) {
5306 case SIOCGMIIPHY:
5307 case SIOCGMIIREG:
5308 case SIOCSMIIREG:
5309 return igb_mii_ioctl(netdev, ifr, cmd);
c6cb090b
PO		 5310 case SIOCSHWTSTAMP:
5311 return igb_hwtstamp_ioctl(netdev, ifr, cmd);
9d5c8243
AK		 5312 default:
5313 return -EOPNOTSUPP;
5314 }
5315}
5316
009bc06e
AD		 5317s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
5318{
5319 struct igb_adapter *adapter = hw->back;
5320 u16 cap_offset;
5321
5322 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
5323 if (!cap_offset)
5324 return -E1000_ERR_CONFIG;
5325
5326 pci_read_config_word(adapter->pdev, cap_offset + reg, value);
5327
5328 return 0;
5329}
5330
5331s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
5332{
5333 struct igb_adapter *adapter = hw->back;
5334 u16 cap_offset;
5335
5336 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
5337 if (!cap_offset)
5338 return -E1000_ERR_CONFIG;
5339
5340 pci_write_config_word(adapter->pdev, cap_offset + reg, *value);
5341
5342 return 0;
5343}
5344
9d5c8243
AK		 5345static void igb_vlan_rx_register(struct net_device *netdev,
5346 struct vlan_group *grp)
5347{
5348 struct igb_adapter *adapter = netdev_priv(netdev);
5349 struct e1000_hw *hw = &adapter->hw;
5350 u32 ctrl, rctl;
5351
5352 igb_irq_disable(adapter);
5353 adapter->vlgrp = grp;
5354
5355 if (grp) {
5356 /* enable VLAN tag insert/strip */
5357 ctrl = rd32(E1000_CTRL);
5358 ctrl |= E1000_CTRL_VME;
5359 wr32(E1000_CTRL, ctrl);
5360
5361 /* enable VLAN receive filtering */
5362 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 5363 rctl &= ~E1000_RCTL_CFIEN;
5364 wr32(E1000_RCTL, rctl);
5365 igb_update_mng_vlan(adapter);
9d5c8243
AK		 5366 } else {
5367 /* disable VLAN tag insert/strip */
5368 ctrl = rd32(E1000_CTRL);
5369 ctrl &= ~E1000_CTRL_VME;
5370 wr32(E1000_CTRL, ctrl);
5371
9d5c8243
AK		 5372 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
5373 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
5374 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
5375 }
9d5c8243
AK		 5376 }
5377
e1739522
AD		 5378 igb_rlpml_set(adapter);
5379
9d5c8243
AK		 5380 if (!test_bit(__IGB_DOWN, &adapter->state))
5381 igb_irq_enable(adapter);
5382}
5383
5384static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
5385{
5386 struct igb_adapter *adapter = netdev_priv(netdev);
5387 struct e1000_hw *hw = &adapter->hw;
4ae196df 5388 int pf_id = adapter->vfs_allocated_count;
9d5c8243 5389
28b0759c 5390 if ((hw->mng_cookie.status &
9d5c8243
AK		 5391 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
5392 (vid == adapter->mng_vlan_id))
5393 return;
4ae196df
AD		 5394
5395 /* add vid to vlvf if sr-iov is enabled,
5396 * if that fails add directly to filter table */
5397 if (igb_vlvf_set(adapter, vid, true, pf_id))
5398 igb_vfta_set(hw, vid, true);
5399
9d5c8243
AK		 5400}
5401
5402static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
5403{
5404 struct igb_adapter *adapter = netdev_priv(netdev);
5405 struct e1000_hw *hw = &adapter->hw;
4ae196df 5406 int pf_id = adapter->vfs_allocated_count;
9d5c8243
AK		 5407
5408 igb_irq_disable(adapter);
5409 vlan_group_set_device(adapter->vlgrp, vid, NULL);
5410
5411 if (!test_bit(__IGB_DOWN, &adapter->state))
5412 igb_irq_enable(adapter);
5413
5414 if ((adapter->hw.mng_cookie.status &
5415 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
5416 (vid == adapter->mng_vlan_id)) {
5417 /* release control to f/w */
5418 igb_release_hw_control(adapter);
5419 return;
5420 }
5421
4ae196df
AD		 5422 /* remove vid from vlvf if sr-iov is enabled,
5423 * if not in vlvf remove from vfta */
5424 if (igb_vlvf_set(adapter, vid, false, pf_id))
5425 igb_vfta_set(hw, vid, false);
9d5c8243
AK		 5426}
5427
5428static void igb_restore_vlan(struct igb_adapter *adapter)
5429{
5430 igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
5431
5432 if (adapter->vlgrp) {
5433 u16 vid;
5434 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
5435 if (!vlan_group_get_device(adapter->vlgrp, vid))
5436 continue;
5437 igb_vlan_rx_add_vid(adapter->netdev, vid);
5438 }
5439 }
5440}
5441
5442int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
5443{
5444 struct e1000_mac_info *mac = &adapter->hw.mac;
5445
5446 mac->autoneg = 0;
5447
9d5c8243
AK		 5448 switch (spddplx) {
5449 case SPEED_10 + DUPLEX_HALF:
5450 mac->forced_speed_duplex = ADVERTISE_10_HALF;
5451 break;
5452 case SPEED_10 + DUPLEX_FULL:
5453 mac->forced_speed_duplex = ADVERTISE_10_FULL;
5454 break;
5455 case SPEED_100 + DUPLEX_HALF:
5456 mac->forced_speed_duplex = ADVERTISE_100_HALF;
5457 break;
5458 case SPEED_100 + DUPLEX_FULL:
5459 mac->forced_speed_duplex = ADVERTISE_100_FULL;
5460 break;
5461 case SPEED_1000 + DUPLEX_FULL:
5462 mac->autoneg = 1;
5463 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
5464 break;
5465 case SPEED_1000 + DUPLEX_HALF: /* not supported */
5466 default:
5467 dev_err(&adapter->pdev->dev,
5468 "Unsupported Speed/Duplex configuration\n");
5469 return -EINVAL;
5470 }
5471 return 0;
5472}
5473
3fe7c4c9 5474static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake)
9d5c8243
AK		 5475{
5476 struct net_device *netdev = pci_get_drvdata(pdev);
5477 struct igb_adapter *adapter = netdev_priv(netdev);
5478 struct e1000_hw *hw = &adapter->hw;
2d064c06 5479 u32 ctrl, rctl, status;
9d5c8243
AK		 5480 u32 wufc = adapter->wol;
5481#ifdef CONFIG_PM
5482 int retval = 0;
5483#endif
5484
5485 netif_device_detach(netdev);
5486
a88f10ec
AD		 5487 if (netif_running(netdev))
5488 igb_close(netdev);
5489
047e0030 5490 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 5491
5492#ifdef CONFIG_PM
5493 retval = pci_save_state(pdev);
5494 if (retval)
5495 return retval;
5496#endif
5497
5498 status = rd32(E1000_STATUS);
5499 if (status & E1000_STATUS_LU)
5500 wufc &= ~E1000_WUFC_LNKC;
5501
5502 if (wufc) {
5503 igb_setup_rctl(adapter);
ff41f8dc 5504 igb_set_rx_mode(netdev);
9d5c8243
AK		 5505
5506 /* turn on all-multi mode if wake on multicast is enabled */
5507 if (wufc & E1000_WUFC_MC) {
5508 rctl = rd32(E1000_RCTL);
5509 rctl |= E1000_RCTL_MPE;
5510 wr32(E1000_RCTL, rctl);
5511 }
5512
5513 ctrl = rd32(E1000_CTRL);
5514 /* advertise wake from D3Cold */
5515 #define E1000_CTRL_ADVD3WUC 0x00100000
5516 /* phy power management enable */
5517 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
5518 ctrl |= E1000_CTRL_ADVD3WUC;
5519 wr32(E1000_CTRL, ctrl);
5520
9d5c8243
AK		 5521 /* Allow time for pending master requests to run */
5522 igb_disable_pcie_master(&adapter->hw);
5523
5524 wr32(E1000_WUC, E1000_WUC_PME_EN);
5525 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 5526 } else {
5527 wr32(E1000_WUC, 0);
5528 wr32(E1000_WUFC, 0);
9d5c8243
AK		 5529 }
5530
3fe7c4c9
RW		 5531 *enable_wake = wufc || adapter->en_mng_pt;
5532 if (!*enable_wake)
2fb02a26 5533 igb_shutdown_serdes_link_82575(hw);
9d5c8243
AK		 5534
5535 /* Release control of h/w to f/w. If f/w is AMT enabled, this
5536 * would have already happened in close and is redundant. */
5537 igb_release_hw_control(adapter);
5538
5539 pci_disable_device(pdev);
5540
9d5c8243
AK		 5541 return 0;
5542}
5543
5544#ifdef CONFIG_PM
3fe7c4c9
RW		 5545static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
5546{
5547 int retval;
5548 bool wake;
5549
5550 retval = __igb_shutdown(pdev, &wake);
5551 if (retval)
5552 return retval;
5553
5554 if (wake) {
5555 pci_prepare_to_sleep(pdev);
5556 } else {
5557 pci_wake_from_d3(pdev, false);
5558 pci_set_power_state(pdev, PCI_D3hot);
5559 }
5560
5561 return 0;
5562}
5563
9d5c8243
AK		 5564static int igb_resume(struct pci_dev *pdev)
5565{
5566 struct net_device *netdev = pci_get_drvdata(pdev);
5567 struct igb_adapter *adapter = netdev_priv(netdev);
5568 struct e1000_hw *hw = &adapter->hw;
5569 u32 err;
5570
5571 pci_set_power_state(pdev, PCI_D0);
5572 pci_restore_state(pdev);
42bfd33a 5573
aed5dec3 5574 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 5575 if (err) {
5576 dev_err(&pdev->dev,
5577 "igb: Cannot enable PCI device from suspend\n");
5578 return err;
5579 }
5580 pci_set_master(pdev);
5581
5582 pci_enable_wake(pdev, PCI_D3hot, 0);
5583 pci_enable_wake(pdev, PCI_D3cold, 0);
5584
047e0030 5585 if (igb_init_interrupt_scheme(adapter)) {
a88f10ec
AD		 5586 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
5587 return -ENOMEM;
9d5c8243
AK		 5588 }
5589
5590 /* e1000_power_up_phy(adapter); */
5591
5592 igb_reset(adapter);
a8564f03
AD		 5593
5594 /* let the f/w know that the h/w is now under the control of the
5595 * driver. */
5596 igb_get_hw_control(adapter);
5597
9d5c8243
AK		 5598 wr32(E1000_WUS, ~0);
5599
a88f10ec
AD		 5600 if (netif_running(netdev)) {
5601 err = igb_open(netdev);
5602 if (err)
5603 return err;
5604 }
9d5c8243
AK		 5605
5606 netif_device_attach(netdev);
5607
9d5c8243
AK		 5608 return 0;
5609}
5610#endif
5611
5612static void igb_shutdown(struct pci_dev *pdev)
5613{
3fe7c4c9
RW		 5614 bool wake;
5615
5616 __igb_shutdown(pdev, &wake);
5617
5618 if (system_state == SYSTEM_POWER_OFF) {
5619 pci_wake_from_d3(pdev, wake);
5620 pci_set_power_state(pdev, PCI_D3hot);
5621 }
9d5c8243
AK		 5622}
5623
5624#ifdef CONFIG_NET_POLL_CONTROLLER
5625/*
5626 * Polling 'interrupt' - used by things like netconsole to send skbs
5627 * without having to re-enable interrupts. It's not called while
5628 * the interrupt routine is executing.
5629 */
5630static void igb_netpoll(struct net_device *netdev)
5631{
5632 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 5633 struct e1000_hw *hw = &adapter->hw;
9d5c8243 5634 int i;
9d5c8243 5635
eebbbdba 5636 if (!adapter->msix_entries) {
047e0030 5637 struct igb_q_vector *q_vector = adapter->q_vector[0];
eebbbdba 5638 igb_irq_disable(adapter);
047e0030 5639 napi_schedule(&q_vector->napi);
eebbbdba
AD		 5640 return;
5641 }
9d5c8243 5642
047e0030
AD		 5643 for (i = 0; i < adapter->num_q_vectors; i++) {
5644 struct igb_q_vector *q_vector = adapter->q_vector[i];
5645 wr32(E1000_EIMC, q_vector->eims_value);
5646 napi_schedule(&q_vector->napi);
eebbbdba 5647 }
9d5c8243
AK		 5648}
5649#endif /* CONFIG_NET_POLL_CONTROLLER */
5650
5651/**
5652 * igb_io_error_detected - called when PCI error is detected
5653 * @pdev: Pointer to PCI device
5654 * @state: The current pci connection state
5655 *
5656 * This function is called after a PCI bus error affecting
5657 * this device has been detected.
5658 */
5659static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
5660 pci_channel_state_t state)
5661{
5662 struct net_device *netdev = pci_get_drvdata(pdev);
5663 struct igb_adapter *adapter = netdev_priv(netdev);
5664
5665 netif_device_detach(netdev);
5666
59ed6eec
AD		 5667 if (state == pci_channel_io_perm_failure)
5668 return PCI_ERS_RESULT_DISCONNECT;
5669
9d5c8243
AK		 5670 if (netif_running(netdev))
5671 igb_down(adapter);
5672 pci_disable_device(pdev);
5673
5674 /* Request a slot slot reset. */
5675 return PCI_ERS_RESULT_NEED_RESET;
5676}
5677
5678/**
5679 * igb_io_slot_reset - called after the pci bus has been reset.
5680 * @pdev: Pointer to PCI device
5681 *
5682 * Restart the card from scratch, as if from a cold-boot. Implementation
5683 * resembles the first-half of the igb_resume routine.
5684 */
5685static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
5686{
5687 struct net_device *netdev = pci_get_drvdata(pdev);
5688 struct igb_adapter *adapter = netdev_priv(netdev);
5689 struct e1000_hw *hw = &adapter->hw;
40a914fa 5690 pci_ers_result_t result;
42bfd33a 5691 int err;
9d5c8243 5692
aed5dec3 5693 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 5694 dev_err(&pdev->dev,
5695 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 5696 result = PCI_ERS_RESULT_DISCONNECT;
5697 } else {
5698 pci_set_master(pdev);
5699 pci_restore_state(pdev);
9d5c8243 5700
40a914fa
AD		 5701 pci_enable_wake(pdev, PCI_D3hot, 0);
5702 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 5703
40a914fa
AD		 5704 igb_reset(adapter);
5705 wr32(E1000_WUS, ~0);
5706 result = PCI_ERS_RESULT_RECOVERED;
5707 }
9d5c8243 5708
ea943d41
JK		 5709 err = pci_cleanup_aer_uncorrect_error_status(pdev);
5710 if (err) {
5711 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
5712 "failed 0x%0x\n", err);
5713 /* non-fatal, continue */
5714 }
40a914fa
AD		 5715
5716 return result;
9d5c8243
AK		 5717}
5718
5719/**
5720 * igb_io_resume - called when traffic can start flowing again.
5721 * @pdev: Pointer to PCI device
5722 *
5723 * This callback is called when the error recovery driver tells us that
5724 * its OK to resume normal operation. Implementation resembles the
5725 * second-half of the igb_resume routine.
5726 */
5727static void igb_io_resume(struct pci_dev *pdev)
5728{
5729 struct net_device *netdev = pci_get_drvdata(pdev);
5730 struct igb_adapter *adapter = netdev_priv(netdev);
5731
9d5c8243
AK		 5732 if (netif_running(netdev)) {
5733 if (igb_up(adapter)) {
5734 dev_err(&pdev->dev, "igb_up failed after reset\n");
5735 return;
5736 }
5737 }
5738
5739 netif_device_attach(netdev);
5740
5741 /* let the f/w know that the h/w is now under the control of the
5742 * driver. */
5743 igb_get_hw_control(adapter);
9d5c8243
AK		 5744}
5745
26ad9178
AD		 5746static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
5747 u8 qsel)
5748{
5749 u32 rar_low, rar_high;
5750 struct e1000_hw *hw = &adapter->hw;
5751
5752 /* HW expects these in little endian so we reverse the byte order
5753 * from network order (big endian) to little endian
5754 */
5755 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
5756 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
5757 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
5758
5759 /* Indicate to hardware the Address is Valid. */
5760 rar_high |= E1000_RAH_AV;
5761
5762 if (hw->mac.type == e1000_82575)
5763 rar_high |= E1000_RAH_POOL_1 * qsel;
5764 else
5765 rar_high |= E1000_RAH_POOL_1 << qsel;
5766
5767 wr32(E1000_RAL(index), rar_low);
5768 wrfl();
5769 wr32(E1000_RAH(index), rar_high);
5770 wrfl();
5771}
5772
4ae196df
AD		 5773static int igb_set_vf_mac(struct igb_adapter *adapter,
5774 int vf, unsigned char *mac_addr)
5775{
5776 struct e1000_hw *hw = &adapter->hw;
ff41f8dc
AD		 5777 /* VF MAC addresses start at end of receive addresses and moves
5778 * torwards the first, as a result a collision should not be possible */
5779 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 5780
37680117 5781 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 5782
26ad9178 5783 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
4ae196df
AD		 5784
5785 return 0;
5786}
5787
5788static void igb_vmm_control(struct igb_adapter *adapter)
5789{
5790 struct e1000_hw *hw = &adapter->hw;
5791 u32 reg_data;
5792
5793 if (!adapter->vfs_allocated_count)
5794 return;
5795
5796 /* VF's need PF reset indication before they
5797 * can send/receive mail */
5798 reg_data = rd32(E1000_CTRL_EXT);
5799 reg_data |= E1000_CTRL_EXT_PFRSTD;
5800 wr32(E1000_CTRL_EXT, reg_data);
5801
5802 igb_vmdq_set_loopback_pf(hw, true);
5803 igb_vmdq_set_replication_pf(hw, true);
5804}
5805
9d5c8243 5806/* igb_main.c */
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