[mirror_ubuntu-hirsute-kernel.git] / drivers / net / ipa / gsi_reg.h

/* SPDX-License-Identifier: GPL-2.0 */

/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
 * Copyright (C) 2018-2020 Linaro Ltd.
 */
#ifndef _GSI_REG_H_
#define _GSI_REG_H_

/* === Only "gsi.c" should include this file === */

#include <linux/bits.h>

/**
 * DOC: GSI Registers
 *
 * GSI registers are located within the "gsi" address space defined by Device
 * Tree.  The offset of each register within that space is specified by
 * symbols defined below.  The GSI address space is mapped to virtual memory
 * space in gsi_init().  All GSI registers are 32 bits wide.
 *
 * Each register type is duplicated for a number of instances of something.
 * For example, each GSI channel has its own set of registers defining its
 * configuration.  The offset to a channel's set of registers is computed
 * based on a "base" offset plus an additional "stride" amount computed
 * from the channel's ID.  For such registers, the offset is computed by a
 * function-like macro that takes a parameter used in the computation.
 *
 * The offset of a register dependent on execution environment is computed
 * by a macro that is supplied a parameter "ee".  The "ee" value is a member
 * of the gsi_ee_id enumerated type.
 *
 * The offset of a channel register is computed by a macro that is supplied a
 * parameter "ch".  The "ch" value is a channel id whose maximum value is 30
 * (though the actual limit is hardware-dependent).
 *
 * The offset of an event register is computed by a macro that is supplied a
 * parameter "ev".  The "ev" value is an event id whose maximum value is 15
 * (though the actual limit is hardware-dependent).
 */

/* GSI EE registers as a group are shifted downward by a fixed
 * constant amount for IPA versions 4.5 and beyond.  This applies
 * to all GSI registers we use *except* the ones that disable
 * inter-EE interrupts for channels and event channels.
 *
 * We handle this by adjusting the pointer to the mapped GSI memory
 * region downward.  Then in the one place we use them (gsi_irq_setup())
 * we undo that adjustment for the inter-EE interrupt registers.
 */
#define GSI_EE_REG_ADJUST			0x0000d000	/* IPA v4.5+ */

#define GSI_INTER_EE_SRC_CH_IRQ_OFFSET \
			GSI_INTER_EE_N_SRC_CH_IRQ_OFFSET(GSI_EE_AP)
#define GSI_INTER_EE_N_SRC_CH_IRQ_OFFSET(ee) \
			(0x0000c018 + 0x1000 * (ee))

#define GSI_INTER_EE_SRC_EV_CH_IRQ_OFFSET \
			GSI_INTER_EE_N_SRC_EV_CH_IRQ_OFFSET(GSI_EE_AP)
#define GSI_INTER_EE_N_SRC_EV_CH_IRQ_OFFSET(ee) \
			(0x0000c01c + 0x1000 * (ee))

#define GSI_CH_C_CNTXT_0_OFFSET(ch) \
		GSI_EE_N_CH_C_CNTXT_0_OFFSET((ch), GSI_EE_AP)
#define GSI_EE_N_CH_C_CNTXT_0_OFFSET(ch, ee) \
		(0x0001c000 + 0x4000 * (ee) + 0x80 * (ch))
#define CHTYPE_PROTOCOL_FMASK		GENMASK(2, 0)
#define CHTYPE_DIR_FMASK		GENMASK(3, 3)
#define EE_FMASK			GENMASK(7, 4)
#define CHID_FMASK			GENMASK(12, 8)
/* The next field is present for IPA v4.5 and above */
#define CHTYPE_PROTOCOL_MSB_FMASK	GENMASK(13, 13)
#define ERINDEX_FMASK			GENMASK(18, 14)
#define CHSTATE_FMASK			GENMASK(23, 20)
#define ELEMENT_SIZE_FMASK		GENMASK(31, 24)

/** enum gsi_channel_type - CHTYPE_PROTOCOL field values in CH_C_CNTXT_0 */
enum gsi_channel_type {
	GSI_CHANNEL_TYPE_MHI			= 0x0,
	GSI_CHANNEL_TYPE_XHCI			= 0x1,
	GSI_CHANNEL_TYPE_GPI			= 0x2,
	GSI_CHANNEL_TYPE_XDCI			= 0x3,
};

#define GSI_CH_C_CNTXT_1_OFFSET(ch) \
		GSI_EE_N_CH_C_CNTXT_1_OFFSET((ch), GSI_EE_AP)
#define GSI_EE_N_CH_C_CNTXT_1_OFFSET(ch, ee) \
		(0x0001c004 + 0x4000 * (ee) + 0x80 * (ch))
#define R_LENGTH_FMASK			GENMASK(15, 0)

#define GSI_CH_C_CNTXT_2_OFFSET(ch) \
		GSI_EE_N_CH_C_CNTXT_2_OFFSET((ch), GSI_EE_AP)
#define GSI_EE_N_CH_C_CNTXT_2_OFFSET(ch, ee) \
		(0x0001c008 + 0x4000 * (ee) + 0x80 * (ch))

#define GSI_CH_C_CNTXT_3_OFFSET(ch) \
		GSI_EE_N_CH_C_CNTXT_3_OFFSET((ch), GSI_EE_AP)
#define GSI_EE_N_CH_C_CNTXT_3_OFFSET(ch, ee) \
		(0x0001c00c + 0x4000 * (ee) + 0x80 * (ch))

#define GSI_CH_C_QOS_OFFSET(ch) \
		GSI_EE_N_CH_C_QOS_OFFSET((ch), GSI_EE_AP)
#define GSI_EE_N_CH_C_QOS_OFFSET(ch, ee) \
		(0x0001c05c + 0x4000 * (ee) + 0x80 * (ch))
#define WRR_WEIGHT_FMASK		GENMASK(3, 0)
#define MAX_PREFETCH_FMASK		GENMASK(8, 8)
#define USE_DB_ENG_FMASK		GENMASK(9, 9)
/* The next field is only present for IPA v4.0, v4.1, and v4.2 */
#define USE_ESCAPE_BUF_ONLY_FMASK	GENMASK(10, 10)
/* The next two fields are present for IPA v4.5 and above */
#define PREFETCH_MODE_FMASK		GENMASK(13, 10)
#define EMPTY_LVL_THRSHOLD_FMASK	GENMASK(23, 16)
/** enum gsi_prefetch_mode - PREFETCH_MODE field in CH_C_QOS */
enum gsi_prefetch_mode {
	GSI_USE_PREFETCH_BUFS			= 0x0,
	GSI_ESCAPE_BUF_ONLY			= 0x1,
	GSI_SMART_PREFETCH			= 0x2,
	GSI_FREE_PREFETCH			= 0x3,
};

#define GSI_CH_C_SCRATCH_0_OFFSET(ch) \
		GSI_EE_N_CH_C_SCRATCH_0_OFFSET((ch), GSI_EE_AP)
#define GSI_EE_N_CH_C_SCRATCH_0_OFFSET(ch, ee) \
		(0x0001c060 + 0x4000 * (ee) + 0x80 * (ch))

#define GSI_CH_C_SCRATCH_1_OFFSET(ch) \
		GSI_EE_N_CH_C_SCRATCH_1_OFFSET((ch), GSI_EE_AP)
#define GSI_EE_N_CH_C_SCRATCH_1_OFFSET(ch, ee) \
		(0x0001c064 + 0x4000 * (ee) + 0x80 * (ch))

#define GSI_CH_C_SCRATCH_2_OFFSET(ch) \
		GSI_EE_N_CH_C_SCRATCH_2_OFFSET((ch), GSI_EE_AP)
#define GSI_EE_N_CH_C_SCRATCH_2_OFFSET(ch, ee) \
		(0x0001c068 + 0x4000 * (ee) + 0x80 * (ch))

#define GSI_CH_C_SCRATCH_3_OFFSET(ch) \
		GSI_EE_N_CH_C_SCRATCH_3_OFFSET((ch), GSI_EE_AP)
#define GSI_EE_N_CH_C_SCRATCH_3_OFFSET(ch, ee) \
		(0x0001c06c + 0x4000 * (ee) + 0x80 * (ch))

#define GSI_EV_CH_E_CNTXT_0_OFFSET(ev) \
		GSI_EE_N_EV_CH_E_CNTXT_0_OFFSET((ev), GSI_EE_AP)
#define GSI_EE_N_EV_CH_E_CNTXT_0_OFFSET(ev, ee) \
		(0x0001d000 + 0x4000 * (ee) + 0x80 * (ev))
#define EV_CHTYPE_FMASK			GENMASK(3, 0)
#define EV_EE_FMASK			GENMASK(7, 4)
#define EV_EVCHID_FMASK			GENMASK(15, 8)
#define EV_INTYPE_FMASK			GENMASK(16, 16)
#define EV_CHSTATE_FMASK		GENMASK(23, 20)
#define EV_ELEMENT_SIZE_FMASK		GENMASK(31, 24)
/* enum gsi_channel_type defines EV_CHTYPE field values in EV_CH_E_CNTXT_0 */

#define GSI_EV_CH_E_CNTXT_1_OFFSET(ev) \
		GSI_EE_N_EV_CH_E_CNTXT_1_OFFSET((ev), GSI_EE_AP)
#define GSI_EE_N_EV_CH_E_CNTXT_1_OFFSET(ev, ee) \
		(0x0001d004 + 0x4000 * (ee) + 0x80 * (ev))
#define EV_R_LENGTH_FMASK		GENMASK(15, 0)

#define GSI_EV_CH_E_CNTXT_2_OFFSET(ev) \
		GSI_EE_N_EV_CH_E_CNTXT_2_OFFSET((ev), GSI_EE_AP)
#define GSI_EE_N_EV_CH_E_CNTXT_2_OFFSET(ev, ee) \
		(0x0001d008 + 0x4000 * (ee) + 0x80 * (ev))

#define GSI_EV_CH_E_CNTXT_3_OFFSET(ev) \
		GSI_EE_N_EV_CH_E_CNTXT_3_OFFSET((ev), GSI_EE_AP)
#define GSI_EE_N_EV_CH_E_CNTXT_3_OFFSET(ev, ee) \
		(0x0001d00c + 0x4000 * (ee) + 0x80 * (ev))

#define GSI_EV_CH_E_CNTXT_4_OFFSET(ev) \
		GSI_EE_N_EV_CH_E_CNTXT_4_OFFSET((ev), GSI_EE_AP)
#define GSI_EE_N_EV_CH_E_CNTXT_4_OFFSET(ev, ee) \
		(0x0001d010 + 0x4000 * (ee) + 0x80 * (ev))

#define GSI_EV_CH_E_CNTXT_8_OFFSET(ev) \
		GSI_EE_N_EV_CH_E_CNTXT_8_OFFSET((ev), GSI_EE_AP)
#define GSI_EE_N_EV_CH_E_CNTXT_8_OFFSET(ev, ee) \
		(0x0001d020 + 0x4000 * (ee) + 0x80 * (ev))
#define MODT_FMASK			GENMASK(15, 0)
#define MODC_FMASK			GENMASK(23, 16)
#define MOD_CNT_FMASK			GENMASK(31, 24)

#define GSI_EV_CH_E_CNTXT_9_OFFSET(ev) \
		GSI_EE_N_EV_CH_E_CNTXT_9_OFFSET((ev), GSI_EE_AP)
#define GSI_EE_N_EV_CH_E_CNTXT_9_OFFSET(ev, ee) \
		(0x0001d024 + 0x4000 * (ee) + 0x80 * (ev))

#define GSI_EV_CH_E_CNTXT_10_OFFSET(ev) \
		GSI_EE_N_EV_CH_E_CNTXT_10_OFFSET((ev), GSI_EE_AP)
#define GSI_EE_N_EV_CH_E_CNTXT_10_OFFSET(ev, ee) \
		(0x0001d028 + 0x4000 * (ee) + 0x80 * (ev))

#define GSI_EV_CH_E_CNTXT_11_OFFSET(ev) \
		GSI_EE_N_EV_CH_E_CNTXT_11_OFFSET((ev), GSI_EE_AP)
#define GSI_EE_N_EV_CH_E_CNTXT_11_OFFSET(ev, ee) \
		(0x0001d02c + 0x4000 * (ee) + 0x80 * (ev))

#define GSI_EV_CH_E_CNTXT_12_OFFSET(ev) \
		GSI_EE_N_EV_CH_E_CNTXT_12_OFFSET((ev), GSI_EE_AP)
#define GSI_EE_N_EV_CH_E_CNTXT_12_OFFSET(ev, ee) \
		(0x0001d030 + 0x4000 * (ee) + 0x80 * (ev))

#define GSI_EV_CH_E_CNTXT_13_OFFSET(ev) \
		GSI_EE_N_EV_CH_E_CNTXT_13_OFFSET((ev), GSI_EE_AP)
#define GSI_EE_N_EV_CH_E_CNTXT_13_OFFSET(ev, ee) \
		(0x0001d034 + 0x4000 * (ee) + 0x80 * (ev))

#define GSI_EV_CH_E_SCRATCH_0_OFFSET(ev) \
		GSI_EE_N_EV_CH_E_SCRATCH_0_OFFSET((ev), GSI_EE_AP)
#define GSI_EE_N_EV_CH_E_SCRATCH_0_OFFSET(ev, ee) \
		(0x0001d048 + 0x4000 * (ee) + 0x80 * (ev))

#define GSI_EV_CH_E_SCRATCH_1_OFFSET(ev) \
		GSI_EE_N_EV_CH_E_SCRATCH_1_OFFSET((ev), GSI_EE_AP)
#define GSI_EE_N_EV_CH_E_SCRATCH_1_OFFSET(ev, ee) \
		(0x0001d04c + 0x4000 * (ee) + 0x80 * (ev))

#define GSI_CH_C_DOORBELL_0_OFFSET(ch) \
		GSI_EE_N_CH_C_DOORBELL_0_OFFSET((ch), GSI_EE_AP)
#define GSI_EE_N_CH_C_DOORBELL_0_OFFSET(ch, ee) \
			(0x0001e000 + 0x4000 * (ee) + 0x08 * (ch))

#define GSI_EV_CH_E_DOORBELL_0_OFFSET(ev) \
			GSI_EE_N_EV_CH_E_DOORBELL_0_OFFSET((ev), GSI_EE_AP)
#define GSI_EE_N_EV_CH_E_DOORBELL_0_OFFSET(ev, ee) \
			(0x0001e100 + 0x4000 * (ee) + 0x08 * (ev))

#define GSI_GSI_STATUS_OFFSET \
			GSI_EE_N_GSI_STATUS_OFFSET(GSI_EE_AP)
#define GSI_EE_N_GSI_STATUS_OFFSET(ee) \
			(0x0001f000 + 0x4000 * (ee))
#define ENABLED_FMASK			GENMASK(0, 0)

#define GSI_CH_CMD_OFFSET \
			GSI_EE_N_CH_CMD_OFFSET(GSI_EE_AP)
#define GSI_EE_N_CH_CMD_OFFSET(ee) \
			(0x0001f008 + 0x4000 * (ee))
#define CH_CHID_FMASK			GENMASK(7, 0)
#define CH_OPCODE_FMASK			GENMASK(31, 24)

/** enum gsi_ch_cmd_opcode - CH_OPCODE field values in CH_CMD */
enum gsi_ch_cmd_opcode {
	GSI_CH_ALLOCATE				= 0x0,
	GSI_CH_START				= 0x1,
	GSI_CH_STOP				= 0x2,
	GSI_CH_RESET				= 0x9,
	GSI_CH_DE_ALLOC				= 0xa,
};

#define GSI_EV_CH_CMD_OFFSET \
			GSI_EE_N_EV_CH_CMD_OFFSET(GSI_EE_AP)
#define GSI_EE_N_EV_CH_CMD_OFFSET(ee) \
			(0x0001f010 + 0x4000 * (ee))
#define EV_CHID_FMASK			GENMASK(7, 0)
#define EV_OPCODE_FMASK			GENMASK(31, 24)

/** enum gsi_evt_cmd_opcode - EV_OPCODE field values in EV_CH_CMD */
enum gsi_evt_cmd_opcode {
	GSI_EVT_ALLOCATE			= 0x0,
	GSI_EVT_RESET				= 0x9,
	GSI_EVT_DE_ALLOC			= 0xa,
};

#define GSI_GENERIC_CMD_OFFSET \
			GSI_EE_N_GENERIC_CMD_OFFSET(GSI_EE_AP)
#define GSI_EE_N_GENERIC_CMD_OFFSET(ee) \
			(0x0001f018 + 0x4000 * (ee))
#define GENERIC_OPCODE_FMASK		GENMASK(4, 0)
#define GENERIC_CHID_FMASK		GENMASK(9, 5)
#define GENERIC_EE_FMASK		GENMASK(13, 10)

/** enum gsi_generic_cmd_opcode - GENERIC_OPCODE field values in GENERIC_CMD */
enum gsi_generic_cmd_opcode {
	GSI_GENERIC_HALT_CHANNEL		= 0x1,
	GSI_GENERIC_ALLOCATE_CHANNEL		= 0x2,
};

#define GSI_GSI_HW_PARAM_2_OFFSET \
			GSI_EE_N_GSI_HW_PARAM_2_OFFSET(GSI_EE_AP)
#define GSI_EE_N_GSI_HW_PARAM_2_OFFSET(ee) \
			(0x0001f040 + 0x4000 * (ee))
#define IRAM_SIZE_FMASK			GENMASK(2, 0)
#define NUM_CH_PER_EE_FMASK		GENMASK(7, 3)
#define NUM_EV_PER_EE_FMASK		GENMASK(12, 8)
#define GSI_CH_PEND_TRANSLATE_FMASK	GENMASK(13, 13)
#define GSI_CH_FULL_LOGIC_FMASK		GENMASK(14, 14)
/* Fields below are present for IPA v4.0 and above */
#define GSI_USE_SDMA_FMASK		GENMASK(15, 15)
#define GSI_SDMA_N_INT_FMASK		GENMASK(18, 16)
#define GSI_SDMA_MAX_BURST_FMASK	GENMASK(26, 19)
#define GSI_SDMA_N_IOVEC_FMASK		GENMASK(29, 27)
/* Fields below are present for IPA v4.2 and above */
#define GSI_USE_RD_WR_ENG_FMASK		GENMASK(30, 30)
#define GSI_USE_INTER_EE_FMASK		GENMASK(31, 31)

/** enum gsi_iram_size - IRAM_SIZE field values in HW_PARAM_2 */
enum gsi_iram_size {
	IRAM_SIZE_ONE_KB			= 0x0,
	IRAM_SIZE_TWO_KB			= 0x1,
/* The next two values are available for IPA v4.0 and above */
	IRAM_SIZE_TWO_N_HALF_KB			= 0x2,
	IRAM_SIZE_THREE_KB			= 0x3,
	/* The next two values are available for IPA v4.5 and above */
	IRAM_SIZE_THREE_N_HALF_KB		= 0x4,
	IRAM_SIZE_FOUR_KB			= 0x5,
};

/* IRQ condition for each type is cleared by writing type-specific register */
#define GSI_CNTXT_TYPE_IRQ_OFFSET \
			GSI_EE_N_CNTXT_TYPE_IRQ_OFFSET(GSI_EE_AP)
#define GSI_EE_N_CNTXT_TYPE_IRQ_OFFSET(ee) \
			(0x0001f080 + 0x4000 * (ee))
#define GSI_CNTXT_TYPE_IRQ_MSK_OFFSET \
			GSI_EE_N_CNTXT_TYPE_IRQ_MSK_OFFSET(GSI_EE_AP)
#define GSI_EE_N_CNTXT_TYPE_IRQ_MSK_OFFSET(ee) \
			(0x0001f088 + 0x4000 * (ee))

/* Values here are bit positions in the TYPE_IRQ and TYPE_IRQ_MSK registers */
enum gsi_irq_type_id {
	GSI_CH_CTRL		= 0x0,	/* channel allocation, etc.  */
	GSI_EV_CTRL		= 0x1,	/* event ring allocation, etc. */
	GSI_GLOB_EE		= 0x2,	/* global/general event */
	GSI_IEOB		= 0x3,	/* TRE completion */
	GSI_INTER_EE_CH_CTRL	= 0x4,	/* remote-issued stop/reset (unused) */
	GSI_INTER_EE_EV_CTRL	= 0x5,	/* remote-issued event reset (unused) */
	GSI_GENERAL		= 0x6,	/* general-purpose event */
};

#define GSI_CNTXT_SRC_CH_IRQ_OFFSET \
			GSI_EE_N_CNTXT_SRC_CH_IRQ_OFFSET(GSI_EE_AP)
#define GSI_EE_N_CNTXT_SRC_CH_IRQ_OFFSET(ee) \
			(0x0001f090 + 0x4000 * (ee))

#define GSI_CNTXT_SRC_EV_CH_IRQ_OFFSET \
			GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_OFFSET(GSI_EE_AP)
#define GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_OFFSET(ee) \
			(0x0001f094 + 0x4000 * (ee))

#define GSI_CNTXT_SRC_CH_IRQ_MSK_OFFSET \
			GSI_EE_N_CNTXT_SRC_CH_IRQ_MSK_OFFSET(GSI_EE_AP)
#define GSI_EE_N_CNTXT_SRC_CH_IRQ_MSK_OFFSET(ee) \
			(0x0001f098 + 0x4000 * (ee))

#define GSI_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET \
			GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET(GSI_EE_AP)
#define GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET(ee) \
			(0x0001f09c + 0x4000 * (ee))

#define GSI_CNTXT_SRC_CH_IRQ_CLR_OFFSET \
			GSI_EE_N_CNTXT_SRC_CH_IRQ_CLR_OFFSET(GSI_EE_AP)
#define GSI_EE_N_CNTXT_SRC_CH_IRQ_CLR_OFFSET(ee) \
			(0x0001f0a0 + 0x4000 * (ee))

#define GSI_CNTXT_SRC_EV_CH_IRQ_CLR_OFFSET \
			GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_CLR_OFFSET(GSI_EE_AP)
#define GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_CLR_OFFSET(ee) \
			(0x0001f0a4 + 0x4000 * (ee))

#define GSI_CNTXT_SRC_IEOB_IRQ_OFFSET \
			GSI_EE_N_CNTXT_SRC_IEOB_IRQ_OFFSET(GSI_EE_AP)
#define GSI_EE_N_CNTXT_SRC_IEOB_IRQ_OFFSET(ee) \
			(0x0001f0b0 + 0x4000 * (ee))

#define GSI_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET \
			GSI_EE_N_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET(GSI_EE_AP)
#define GSI_EE_N_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET(ee) \
			(0x0001f0b8 + 0x4000 * (ee))

#define GSI_CNTXT_SRC_IEOB_IRQ_CLR_OFFSET \
			GSI_EE_N_CNTXT_SRC_IEOB_IRQ_CLR_OFFSET(GSI_EE_AP)
#define GSI_EE_N_CNTXT_SRC_IEOB_IRQ_CLR_OFFSET(ee) \
			(0x0001f0c0 + 0x4000 * (ee))

#define GSI_CNTXT_GLOB_IRQ_STTS_OFFSET \
			GSI_EE_N_CNTXT_GLOB_IRQ_STTS_OFFSET(GSI_EE_AP)
#define GSI_EE_N_CNTXT_GLOB_IRQ_STTS_OFFSET(ee) \
			(0x0001f100 + 0x4000 * (ee))
#define GSI_CNTXT_GLOB_IRQ_EN_OFFSET \
			GSI_EE_N_CNTXT_GLOB_IRQ_EN_OFFSET(GSI_EE_AP)
#define GSI_EE_N_CNTXT_GLOB_IRQ_EN_OFFSET(ee) \
			(0x0001f108 + 0x4000 * (ee))
#define GSI_CNTXT_GLOB_IRQ_CLR_OFFSET \
			GSI_EE_N_CNTXT_GLOB_IRQ_CLR_OFFSET(GSI_EE_AP)
#define GSI_EE_N_CNTXT_GLOB_IRQ_CLR_OFFSET(ee) \
			(0x0001f110 + 0x4000 * (ee))
/* Values here are bit positions in the GLOB_IRQ_* registers */
enum gsi_global_irq_id {
	ERROR_INT				= 0x0,
	GP_INT1					= 0x1,
	GP_INT2					= 0x2,
	GP_INT3					= 0x3,
};

#define GSI_CNTXT_GSI_IRQ_STTS_OFFSET \
			GSI_EE_N_CNTXT_GSI_IRQ_STTS_OFFSET(GSI_EE_AP)
#define GSI_EE_N_CNTXT_GSI_IRQ_STTS_OFFSET(ee) \
			(0x0001f118 + 0x4000 * (ee))
#define GSI_CNTXT_GSI_IRQ_EN_OFFSET \
			GSI_EE_N_CNTXT_GSI_IRQ_EN_OFFSET(GSI_EE_AP)
#define GSI_EE_N_CNTXT_GSI_IRQ_EN_OFFSET(ee) \
			(0x0001f120 + 0x4000 * (ee))
#define GSI_CNTXT_GSI_IRQ_CLR_OFFSET \
			GSI_EE_N_CNTXT_GSI_IRQ_CLR_OFFSET(GSI_EE_AP)
#define GSI_EE_N_CNTXT_GSI_IRQ_CLR_OFFSET(ee) \
			(0x0001f128 + 0x4000 * (ee))
/* Values here are bit positions in the (general) GSI_IRQ_* registers */
enum gsi_general_id {
	BREAK_POINT				= 0x0,
	BUS_ERROR				= 0x1,
	CMD_FIFO_OVRFLOW			= 0x2,
	MCS_STACK_OVRFLOW			= 0x3,
};

#define GSI_CNTXT_INTSET_OFFSET \
			GSI_EE_N_CNTXT_INTSET_OFFSET(GSI_EE_AP)
#define GSI_EE_N_CNTXT_INTSET_OFFSET(ee) \
			(0x0001f180 + 0x4000 * (ee))
#define INTYPE_FMASK			GENMASK(0, 0)

#define GSI_ERROR_LOG_OFFSET \
			GSI_EE_N_ERROR_LOG_OFFSET(GSI_EE_AP)
#define GSI_EE_N_ERROR_LOG_OFFSET(ee) \
			(0x0001f200 + 0x4000 * (ee))
#define ERR_ARG3_FMASK			GENMASK(3, 0)
#define ERR_ARG2_FMASK			GENMASK(7, 4)
#define ERR_ARG1_FMASK			GENMASK(11, 8)
#define ERR_CODE_FMASK			GENMASK(15, 12)
#define ERR_VIRT_IDX_FMASK		GENMASK(23, 19)
#define ERR_TYPE_FMASK			GENMASK(27, 24)
#define ERR_EE_FMASK			GENMASK(31, 28)

/** enum gsi_err_code - ERR_CODE field values in EE_ERR_LOG */
enum gsi_err_code {
	GSI_INVALID_TRE				= 0x1,
	GSI_OUT_OF_BUFFERS			= 0x2,
	GSI_OUT_OF_RESOURCES			= 0x3,
	GSI_UNSUPPORTED_INTER_EE_OP		= 0x4,
	GSI_EVT_RING_EMPTY			= 0x5,
	GSI_NON_ALLOCATED_EVT_ACCESS		= 0x6,
	/* 7 is not assigned */
	GSI_HWO_1				= 0x8,
};

/** enum gsi_err_type - ERR_TYPE field values in EE_ERR_LOG */
enum gsi_err_type {
	GSI_ERR_TYPE_GLOB			= 0x1,
	GSI_ERR_TYPE_CHAN			= 0x2,
	GSI_ERR_TYPE_EVT			= 0x3,
};

#define GSI_ERROR_LOG_CLR_OFFSET \
			GSI_EE_N_ERROR_LOG_CLR_OFFSET(GSI_EE_AP)
#define GSI_EE_N_ERROR_LOG_CLR_OFFSET(ee) \
			(0x0001f210 + 0x4000 * (ee))

#define GSI_CNTXT_SCRATCH_0_OFFSET \
			GSI_EE_N_CNTXT_SCRATCH_0_OFFSET(GSI_EE_AP)
#define GSI_EE_N_CNTXT_SCRATCH_0_OFFSET(ee) \
			(0x0001f400 + 0x4000 * (ee))
#define INTER_EE_RESULT_FMASK		GENMASK(2, 0)
#define GENERIC_EE_RESULT_FMASK		GENMASK(7, 5)

/** enum gsi_generic_ee_result - GENERIC_EE_RESULT field values in SCRATCH_0 */
enum gsi_generic_ee_result {
	GENERIC_EE_SUCCESS			= 0x1,
	GENERIC_EE_CHANNEL_NOT_RUNNING		= 0x2,
	GENERIC_EE_INCORRECT_DIRECTION		= 0x3,
	GENERIC_EE_INCORRECT_CHANNEL_TYPE	= 0x4,
	GENERIC_EE_INCORRECT_CHANNEL		= 0x5,
	GENERIC_EE_RETRY			= 0x6,
	GENERIC_EE_NO_RESOURCES			= 0x7,
};

#define USB_MAX_PACKET_FMASK		GENMASK(15, 15)	/* 0: HS; 1: SS */
#define MHI_BASE_CHANNEL_FMASK		GENMASK(31, 24)

#endif	/* _GSI_REG_H_ */
Commit	Line	Data
ca48b27b AE	1	/* SPDX-License-Identifier: GPL-2.0 */
	2
	3	/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
	4	* Copyright (C) 2018-2020 Linaro Ltd.
	5	*/
	6	#ifndef _GSI_REG_H_
	7	#define _GSI_REG_H_
	8
	9	/* === Only "gsi.c" should include this file === */
	10
	11	#include <linux/bits.h>
	12
	13	/**
	14	* DOC: GSI Registers
	15	*
	16	* GSI registers are located within the "gsi" address space defined by Device
	17	* Tree. The offset of each register within that space is specified by
	18	* symbols defined below. The GSI address space is mapped to virtual memory
	19	* space in gsi_init(). All GSI registers are 32 bits wide.
	20	*
	21	* Each register type is duplicated for a number of instances of something.
	22	* For example, each GSI channel has its own set of registers defining its
	23	* configuration. The offset to a channel's set of registers is computed
	24	* based on a "base" offset plus an additional "stride" amount computed
	25	* from the channel's ID. For such registers, the offset is computed by a
	26	* function-like macro that takes a parameter used in the computation.
	27	*
	28	* The offset of a register dependent on execution environment is computed
	29	* by a macro that is supplied a parameter "ee". The "ee" value is a member
	30	* of the gsi_ee_id enumerated type.
	31	*
	32	* The offset of a channel register is computed by a macro that is supplied a
	33	* parameter "ch". The "ch" value is a channel id whose maximum value is 30
	34	* (though the actual limit is hardware-dependent).
	35	*
	36	* The offset of an event register is computed by a macro that is supplied a
	37	* parameter "ev". The "ev" value is an event id whose maximum value is 15
	38	* (though the actual limit is hardware-dependent).
	39	*/
	40
cdeee49f AE	41	/* GSI EE registers as a group are shifted downward by a fixed
	42	* constant amount for IPA versions 4.5 and beyond. This applies
	43	* to all GSI registers we use except the ones that disable
	44	* inter-EE interrupts for channels and event channels.
	45	*
	46	* We handle this by adjusting the pointer to the mapped GSI memory
	47	* region downward. Then in the one place we use them (gsi_irq_setup())
	48	* we undo that adjustment for the inter-EE interrupt registers.
	49	*/
	50	#define GSI_EE_REG_ADJUST 0x0000d000 /* IPA v4.5+ */
	51
ca48b27b AE	52	#define GSI_INTER_EE_SRC_CH_IRQ_OFFSET \
	53	GSI_INTER_EE_N_SRC_CH_IRQ_OFFSET(GSI_EE_AP)
	54	#define GSI_INTER_EE_N_SRC_CH_IRQ_OFFSET(ee) \
	55	(0x0000c018 + 0x1000 * (ee))
	56
	57	#define GSI_INTER_EE_SRC_EV_CH_IRQ_OFFSET \
	58	GSI_INTER_EE_N_SRC_EV_CH_IRQ_OFFSET(GSI_EE_AP)
	59	#define GSI_INTER_EE_N_SRC_EV_CH_IRQ_OFFSET(ee) \
	60	(0x0000c01c + 0x1000 * (ee))
	61
ca48b27b AE	62	#define GSI_CH_C_CNTXT_0_OFFSET(ch) \
	63	GSI_EE_N_CH_C_CNTXT_0_OFFSET((ch), GSI_EE_AP)
	64	#define GSI_EE_N_CH_C_CNTXT_0_OFFSET(ch, ee) \
	65	(0x0001c000 + 0x4000 * (ee) + 0x80 * (ch))
	66	#define CHTYPE_PROTOCOL_FMASK GENMASK(2, 0)
	67	#define CHTYPE_DIR_FMASK GENMASK(3, 3)
	68	#define EE_FMASK GENMASK(7, 4)
	69	#define CHID_FMASK GENMASK(12, 8)
4a04d65c	70	/* The next field is present for IPA v4.5 and above */
ca48b27b AE	71	#define CHTYPE_PROTOCOL_MSB_FMASK GENMASK(13, 13)
	72	#define ERINDEX_FMASK GENMASK(18, 14)
	73	#define CHSTATE_FMASK GENMASK(23, 20)
	74	#define ELEMENT_SIZE_FMASK GENMASK(31, 24)
8701cb00	75
9ed8c2a9 AE	76	/** enum gsi_channel_type - CHTYPE_PROTOCOL field values in CH_C_CNTXT_0 */
	77	enum gsi_channel_type {
	78	GSI_CHANNEL_TYPE_MHI = 0x0,
	79	GSI_CHANNEL_TYPE_XHCI = 0x1,
	80	GSI_CHANNEL_TYPE_GPI = 0x2,
	81	GSI_CHANNEL_TYPE_XDCI = 0x3,
	82	};
ca48b27b AE	83
	84	#define GSI_CH_C_CNTXT_1_OFFSET(ch) \
	85	GSI_EE_N_CH_C_CNTXT_1_OFFSET((ch), GSI_EE_AP)
	86	#define GSI_EE_N_CH_C_CNTXT_1_OFFSET(ch, ee) \
	87	(0x0001c004 + 0x4000 * (ee) + 0x80 * (ch))
	88	#define R_LENGTH_FMASK GENMASK(15, 0)
	89
	90	#define GSI_CH_C_CNTXT_2_OFFSET(ch) \
	91	GSI_EE_N_CH_C_CNTXT_2_OFFSET((ch), GSI_EE_AP)
	92	#define GSI_EE_N_CH_C_CNTXT_2_OFFSET(ch, ee) \
	93	(0x0001c008 + 0x4000 * (ee) + 0x80 * (ch))
	94
	95	#define GSI_CH_C_CNTXT_3_OFFSET(ch) \
	96	GSI_EE_N_CH_C_CNTXT_3_OFFSET((ch), GSI_EE_AP)
	97	#define GSI_EE_N_CH_C_CNTXT_3_OFFSET(ch, ee) \
	98	(0x0001c00c + 0x4000 * (ee) + 0x80 * (ch))
	99
	100	#define GSI_CH_C_QOS_OFFSET(ch) \
	101	GSI_EE_N_CH_C_QOS_OFFSET((ch), GSI_EE_AP)
	102	#define GSI_EE_N_CH_C_QOS_OFFSET(ch, ee) \
	103	(0x0001c05c + 0x4000 * (ee) + 0x80 * (ch))
	104	#define WRR_WEIGHT_FMASK GENMASK(3, 0)
	105	#define MAX_PREFETCH_FMASK GENMASK(8, 8)
	106	#define USE_DB_ENG_FMASK GENMASK(9, 9)
4a04d65c	107	/* The next field is only present for IPA v4.0, v4.1, and v4.2 */
ca48b27b	108	#define USE_ESCAPE_BUF_ONLY_FMASK GENMASK(10, 10)
b0b6f0dd AE	109	/* The next two fields are present for IPA v4.5 and above */
	110	#define PREFETCH_MODE_FMASK GENMASK(13, 10)
	111	#define EMPTY_LVL_THRSHOLD_FMASK GENMASK(23, 16)
	112	/** enum gsi_prefetch_mode - PREFETCH_MODE field in CH_C_QOS */
	113	enum gsi_prefetch_mode {
	114	GSI_USE_PREFETCH_BUFS = 0x0,
	115	GSI_ESCAPE_BUF_ONLY = 0x1,
	116	GSI_SMART_PREFETCH = 0x2,
	117	GSI_FREE_PREFETCH = 0x3,
	118	};
ca48b27b AE	119
	120	#define GSI_CH_C_SCRATCH_0_OFFSET(ch) \
	121	GSI_EE_N_CH_C_SCRATCH_0_OFFSET((ch), GSI_EE_AP)
	122	#define GSI_EE_N_CH_C_SCRATCH_0_OFFSET(ch, ee) \
	123	(0x0001c060 + 0x4000 * (ee) + 0x80 * (ch))
	124
	125	#define GSI_CH_C_SCRATCH_1_OFFSET(ch) \
	126	GSI_EE_N_CH_C_SCRATCH_1_OFFSET((ch), GSI_EE_AP)
	127	#define GSI_EE_N_CH_C_SCRATCH_1_OFFSET(ch, ee) \
	128	(0x0001c064 + 0x4000 * (ee) + 0x80 * (ch))
	129
	130	#define GSI_CH_C_SCRATCH_2_OFFSET(ch) \
	131	GSI_EE_N_CH_C_SCRATCH_2_OFFSET((ch), GSI_EE_AP)
	132	#define GSI_EE_N_CH_C_SCRATCH_2_OFFSET(ch, ee) \
	133	(0x0001c068 + 0x4000 * (ee) + 0x80 * (ch))
	134
	135	#define GSI_CH_C_SCRATCH_3_OFFSET(ch) \
	136	GSI_EE_N_CH_C_SCRATCH_3_OFFSET((ch), GSI_EE_AP)
	137	#define GSI_EE_N_CH_C_SCRATCH_3_OFFSET(ch, ee) \
	138	(0x0001c06c + 0x4000 * (ee) + 0x80 * (ch))
	139
	140	#define GSI_EV_CH_E_CNTXT_0_OFFSET(ev) \
	141	GSI_EE_N_EV_CH_E_CNTXT_0_OFFSET((ev), GSI_EE_AP)
	142	#define GSI_EE_N_EV_CH_E_CNTXT_0_OFFSET(ev, ee) \
	143	(0x0001d000 + 0x4000 * (ee) + 0x80 * (ev))
	144	#define EV_CHTYPE_FMASK GENMASK(3, 0)
	145	#define EV_EE_FMASK GENMASK(7, 4)
	146	#define EV_EVCHID_FMASK GENMASK(15, 8)
	147	#define EV_INTYPE_FMASK GENMASK(16, 16)
	148	#define EV_CHSTATE_FMASK GENMASK(23, 20)
	149	#define EV_ELEMENT_SIZE_FMASK GENMASK(31, 24)
9ed8c2a9	150	/* enum gsi_channel_type defines EV_CHTYPE field values in EV_CH_E_CNTXT_0 */
ca48b27b AE	151
	152	#define GSI_EV_CH_E_CNTXT_1_OFFSET(ev) \
	153	GSI_EE_N_EV_CH_E_CNTXT_1_OFFSET((ev), GSI_EE_AP)
	154	#define GSI_EE_N_EV_CH_E_CNTXT_1_OFFSET(ev, ee) \
	155	(0x0001d004 + 0x4000 * (ee) + 0x80 * (ev))
	156	#define EV_R_LENGTH_FMASK GENMASK(15, 0)
	157
	158	#define GSI_EV_CH_E_CNTXT_2_OFFSET(ev) \
	159	GSI_EE_N_EV_CH_E_CNTXT_2_OFFSET((ev), GSI_EE_AP)
	160	#define GSI_EE_N_EV_CH_E_CNTXT_2_OFFSET(ev, ee) \
	161	(0x0001d008 + 0x4000 * (ee) + 0x80 * (ev))
	162
	163	#define GSI_EV_CH_E_CNTXT_3_OFFSET(ev) \
	164	GSI_EE_N_EV_CH_E_CNTXT_3_OFFSET((ev), GSI_EE_AP)
	165	#define GSI_EE_N_EV_CH_E_CNTXT_3_OFFSET(ev, ee) \
	166	(0x0001d00c + 0x4000 * (ee) + 0x80 * (ev))
	167
	168	#define GSI_EV_CH_E_CNTXT_4_OFFSET(ev) \
	169	GSI_EE_N_EV_CH_E_CNTXT_4_OFFSET((ev), GSI_EE_AP)
	170	#define GSI_EE_N_EV_CH_E_CNTXT_4_OFFSET(ev, ee) \
	171	(0x0001d010 + 0x4000 * (ee) + 0x80 * (ev))
	172
	173	#define GSI_EV_CH_E_CNTXT_8_OFFSET(ev) \
	174	GSI_EE_N_EV_CH_E_CNTXT_8_OFFSET((ev), GSI_EE_AP)
	175	#define GSI_EE_N_EV_CH_E_CNTXT_8_OFFSET(ev, ee) \
	176	(0x0001d020 + 0x4000 * (ee) + 0x80 * (ev))
	177	#define MODT_FMASK GENMASK(15, 0)
	178	#define MODC_FMASK GENMASK(23, 16)
	179	#define MOD_CNT_FMASK GENMASK(31, 24)
	180
	181	#define GSI_EV_CH_E_CNTXT_9_OFFSET(ev) \
	182	GSI_EE_N_EV_CH_E_CNTXT_9_OFFSET((ev), GSI_EE_AP)
	183	#define GSI_EE_N_EV_CH_E_CNTXT_9_OFFSET(ev, ee) \
	184	(0x0001d024 + 0x4000 * (ee) + 0x80 * (ev))
	185
	186	#define GSI_EV_CH_E_CNTXT_10_OFFSET(ev) \
	187	GSI_EE_N_EV_CH_E_CNTXT_10_OFFSET((ev), GSI_EE_AP)
	188	#define GSI_EE_N_EV_CH_E_CNTXT_10_OFFSET(ev, ee) \
	189	(0x0001d028 + 0x4000 * (ee) + 0x80 * (ev))
	190
	191	#define GSI_EV_CH_E_CNTXT_11_OFFSET(ev) \
	192	GSI_EE_N_EV_CH_E_CNTXT_11_OFFSET((ev), GSI_EE_AP)
	193	#define GSI_EE_N_EV_CH_E_CNTXT_11_OFFSET(ev, ee) \
	194	(0x0001d02c + 0x4000 * (ee) + 0x80 * (ev))
	195
	196	#define GSI_EV_CH_E_CNTXT_12_OFFSET(ev) \
	197	GSI_EE_N_EV_CH_E_CNTXT_12_OFFSET((ev), GSI_EE_AP)
	198	#define GSI_EE_N_EV_CH_E_CNTXT_12_OFFSET(ev, ee) \
	199	(0x0001d030 + 0x4000 * (ee) + 0x80 * (ev))
	200
	201	#define GSI_EV_CH_E_CNTXT_13_OFFSET(ev) \
	202	GSI_EE_N_EV_CH_E_CNTXT_13_OFFSET((ev), GSI_EE_AP)
	203	#define GSI_EE_N_EV_CH_E_CNTXT_13_OFFSET(ev, ee) \
	204	(0x0001d034 + 0x4000 * (ee) + 0x80 * (ev))
	205
	206	#define GSI_EV_CH_E_SCRATCH_0_OFFSET(ev) \
	207	GSI_EE_N_EV_CH_E_SCRATCH_0_OFFSET((ev), GSI_EE_AP)
	208	#define GSI_EE_N_EV_CH_E_SCRATCH_0_OFFSET(ev, ee) \
	209	(0x0001d048 + 0x4000 * (ee) + 0x80 * (ev))
	210
	211	#define GSI_EV_CH_E_SCRATCH_1_OFFSET(ev) \
	212	GSI_EE_N_EV_CH_E_SCRATCH_1_OFFSET((ev), GSI_EE_AP)
	213	#define GSI_EE_N_EV_CH_E_SCRATCH_1_OFFSET(ev, ee) \
	214	(0x0001d04c + 0x4000 * (ee) + 0x80 * (ev))
215
216	#define GSI_CH_C_DOORBELL_0_OFFSET(ch) \
217	GSI_EE_N_CH_C_DOORBELL_0_OFFSET((ch), GSI_EE_AP)
218	#define GSI_EE_N_CH_C_DOORBELL_0_OFFSET(ch, ee) \
219	(0x0001e000 + 0x4000 * (ee) + 0x08 * (ch))
220
221	#define GSI_EV_CH_E_DOORBELL_0_OFFSET(ev) \
222	GSI_EE_N_EV_CH_E_DOORBELL_0_OFFSET((ev), GSI_EE_AP)
223	#define GSI_EE_N_EV_CH_E_DOORBELL_0_OFFSET(ev, ee) \
224	(0x0001e100 + 0x4000 * (ee) + 0x08 * (ev))
225
226	#define GSI_GSI_STATUS_OFFSET \
227	GSI_EE_N_GSI_STATUS_OFFSET(GSI_EE_AP)
228	#define GSI_EE_N_GSI_STATUS_OFFSET(ee) \
229	(0x0001f000 + 0x4000 * (ee))
230	#define ENABLED_FMASK GENMASK(0, 0)
231
232	#define GSI_CH_CMD_OFFSET \
233	GSI_EE_N_CH_CMD_OFFSET(GSI_EE_AP)
234	#define GSI_EE_N_CH_CMD_OFFSET(ee) \
235	(0x0001f008 + 0x4000 * (ee))
236	#define CH_CHID_FMASK GENMASK(7, 0)
237	#define CH_OPCODE_FMASK GENMASK(31, 24)
8701cb00	238
cec2076e AE	239	/** enum gsi_ch_cmd_opcode - CH_OPCODE field values in CH_CMD */
	240	enum gsi_ch_cmd_opcode {
	241	GSI_CH_ALLOCATE = 0x0,
	242	GSI_CH_START = 0x1,
	243	GSI_CH_STOP = 0x2,
	244	GSI_CH_RESET = 0x9,
	245	GSI_CH_DE_ALLOC = 0xa,
	246	};
ca48b27b AE	247
	248	#define GSI_EV_CH_CMD_OFFSET \
	249	GSI_EE_N_EV_CH_CMD_OFFSET(GSI_EE_AP)
	250	#define GSI_EE_N_EV_CH_CMD_OFFSET(ee) \
	251	(0x0001f010 + 0x4000 * (ee))
	252	#define EV_CHID_FMASK GENMASK(7, 0)
	253	#define EV_OPCODE_FMASK GENMASK(31, 24)
8701cb00	254
cec2076e AE	255	/** enum gsi_evt_cmd_opcode - EV_OPCODE field values in EV_CH_CMD */
	256	enum gsi_evt_cmd_opcode {
	257	GSI_EVT_ALLOCATE = 0x0,
	258	GSI_EVT_RESET = 0x9,
	259	GSI_EVT_DE_ALLOC = 0xa,
	260	};
ca48b27b AE	261
	262	#define GSI_GENERIC_CMD_OFFSET \
	263	GSI_EE_N_GENERIC_CMD_OFFSET(GSI_EE_AP)
	264	#define GSI_EE_N_GENERIC_CMD_OFFSET(ee) \
	265	(0x0001f018 + 0x4000 * (ee))
	266	#define GENERIC_OPCODE_FMASK GENMASK(4, 0)
	267	#define GENERIC_CHID_FMASK GENMASK(9, 5)
	268	#define GENERIC_EE_FMASK GENMASK(13, 10)
8701cb00	269
cec2076e AE	270	/** enum gsi_generic_cmd_opcode - GENERIC_OPCODE field values in GENERIC_CMD */
	271	enum gsi_generic_cmd_opcode {
	272	GSI_GENERIC_HALT_CHANNEL = 0x1,
	273	GSI_GENERIC_ALLOCATE_CHANNEL = 0x2,
	274	};
ca48b27b AE	275
	276	#define GSI_GSI_HW_PARAM_2_OFFSET \
	277	GSI_EE_N_GSI_HW_PARAM_2_OFFSET(GSI_EE_AP)
	278	#define GSI_EE_N_GSI_HW_PARAM_2_OFFSET(ee) \
	279	(0x0001f040 + 0x4000 * (ee))
	280	#define IRAM_SIZE_FMASK GENMASK(2, 0)
ca48b27b AE	281	#define NUM_CH_PER_EE_FMASK GENMASK(7, 3)
	282	#define NUM_EV_PER_EE_FMASK GENMASK(12, 8)
	283	#define GSI_CH_PEND_TRANSLATE_FMASK GENMASK(13, 13)
	284	#define GSI_CH_FULL_LOGIC_FMASK GENMASK(14, 14)
4a04d65c	285	/* Fields below are present for IPA v4.0 and above */
ca48b27b AE	286	#define GSI_USE_SDMA_FMASK GENMASK(15, 15)
	287	#define GSI_SDMA_N_INT_FMASK GENMASK(18, 16)
	288	#define GSI_SDMA_MAX_BURST_FMASK GENMASK(26, 19)
	289	#define GSI_SDMA_N_IOVEC_FMASK GENMASK(29, 27)
4a04d65c	290	/* Fields below are present for IPA v4.2 and above */
ca48b27b AE	291	#define GSI_USE_RD_WR_ENG_FMASK GENMASK(30, 30)
ca48b27b AE	292	#define GSI_USE_INTER_EE_FMASK GENMASK(31, 31)
8701cb00	293
4730ab1c AE	294	/** enum gsi_iram_size - IRAM_SIZE field values in HW_PARAM_2 */
	295	enum gsi_iram_size {
	296	IRAM_SIZE_ONE_KB = 0x0,
	297	IRAM_SIZE_TWO_KB = 0x1,
	298	/* The next two values are available for IPA v4.0 and above */
	299	IRAM_SIZE_TWO_N_HALF_KB = 0x2,
	300	IRAM_SIZE_THREE_KB = 0x3,
b0b6f0dd AE	301	/* The next two values are available for IPA v4.5 and above */
	302	IRAM_SIZE_THREE_N_HALF_KB = 0x4,
	303	IRAM_SIZE_FOUR_KB = 0x5,
4730ab1c	304	};
ca48b27b	305
6c6358cc	306	/* IRQ condition for each type is cleared by writing type-specific register */
ca48b27b AE	307	#define GSI_CNTXT_TYPE_IRQ_OFFSET \
	308	GSI_EE_N_CNTXT_TYPE_IRQ_OFFSET(GSI_EE_AP)
	309	#define GSI_EE_N_CNTXT_TYPE_IRQ_OFFSET(ee) \
	310	(0x0001f080 + 0x4000 * (ee))
e6580d0e AE	311	#define GSI_CNTXT_TYPE_IRQ_MSK_OFFSET \
	312	GSI_EE_N_CNTXT_TYPE_IRQ_MSK_OFFSET(GSI_EE_AP)
	313	#define GSI_EE_N_CNTXT_TYPE_IRQ_MSK_OFFSET(ee) \
	314	(0x0001f088 + 0x4000 * (ee))
8701cb00	315
f9b28804 AE	316	/* Values here are bit positions in the TYPE_IRQ and TYPE_IRQ_MSK registers */
f9b28804 AE	317	enum gsi_irq_type_id {
8701cb00 AE	318	GSI_CH_CTRL = 0x0, /* channel allocation, etc. */
	319	GSI_EV_CTRL = 0x1, /* event ring allocation, etc. */
	320	GSI_GLOB_EE = 0x2, /* global/general event */
	321	GSI_IEOB = 0x3, /* TRE completion */
	322	GSI_INTER_EE_CH_CTRL = 0x4, /* remote-issued stop/reset (unused) */
	323	GSI_INTER_EE_EV_CTRL = 0x5, /* remote-issued event reset (unused) */
	324	GSI_GENERAL = 0x6, /* general-purpose event */
f9b28804	325	};
ca48b27b AE	326
	327	#define GSI_CNTXT_SRC_CH_IRQ_OFFSET \
	328	GSI_EE_N_CNTXT_SRC_CH_IRQ_OFFSET(GSI_EE_AP)
	329	#define GSI_EE_N_CNTXT_SRC_CH_IRQ_OFFSET(ee) \
	330	(0x0001f090 + 0x4000 * (ee))
	331
	332	#define GSI_CNTXT_SRC_EV_CH_IRQ_OFFSET \
	333	GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_OFFSET(GSI_EE_AP)
	334	#define GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_OFFSET(ee) \
	335	(0x0001f094 + 0x4000 * (ee))
	336
	337	#define GSI_CNTXT_SRC_CH_IRQ_MSK_OFFSET \
	338	GSI_EE_N_CNTXT_SRC_CH_IRQ_MSK_OFFSET(GSI_EE_AP)
	339	#define GSI_EE_N_CNTXT_SRC_CH_IRQ_MSK_OFFSET(ee) \
	340	(0x0001f098 + 0x4000 * (ee))
	341
	342	#define GSI_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET \
	343	GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET(GSI_EE_AP)
	344	#define GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET(ee) \
	345	(0x0001f09c + 0x4000 * (ee))
	346
	347	#define GSI_CNTXT_SRC_CH_IRQ_CLR_OFFSET \
	348	GSI_EE_N_CNTXT_SRC_CH_IRQ_CLR_OFFSET(GSI_EE_AP)
	349	#define GSI_EE_N_CNTXT_SRC_CH_IRQ_CLR_OFFSET(ee) \
	350	(0x0001f0a0 + 0x4000 * (ee))
	351
	352	#define GSI_CNTXT_SRC_EV_CH_IRQ_CLR_OFFSET \
	353	GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_CLR_OFFSET(GSI_EE_AP)
	354	#define GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_CLR_OFFSET(ee) \
	355	(0x0001f0a4 + 0x4000 * (ee))
	356
	357	#define GSI_CNTXT_SRC_IEOB_IRQ_OFFSET \
	358	GSI_EE_N_CNTXT_SRC_IEOB_IRQ_OFFSET(GSI_EE_AP)
	359	#define GSI_EE_N_CNTXT_SRC_IEOB_IRQ_OFFSET(ee) \
	360	(0x0001f0b0 + 0x4000 * (ee))
	361
	362	#define GSI_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET \
	363	GSI_EE_N_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET(GSI_EE_AP)
	364	#define GSI_EE_N_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET(ee) \
	365	(0x0001f0b8 + 0x4000 * (ee))
	366
	367	#define GSI_CNTXT_SRC_IEOB_IRQ_CLR_OFFSET \
	368	GSI_EE_N_CNTXT_SRC_IEOB_IRQ_CLR_OFFSET(GSI_EE_AP)
	369	#define GSI_EE_N_CNTXT_SRC_IEOB_IRQ_CLR_OFFSET(ee) \
	370	(0x0001f0c0 + 0x4000 * (ee))
	371
	372	#define GSI_CNTXT_GLOB_IRQ_STTS_OFFSET \
	373	GSI_EE_N_CNTXT_GLOB_IRQ_STTS_OFFSET(GSI_EE_AP)
	374	#define GSI_EE_N_CNTXT_GLOB_IRQ_STTS_OFFSET(ee) \
	375	(0x0001f100 + 0x4000 * (ee))
ca48b27b AE	376	#define GSI_CNTXT_GLOB_IRQ_EN_OFFSET \
	377	GSI_EE_N_CNTXT_GLOB_IRQ_EN_OFFSET(GSI_EE_AP)
	378	#define GSI_EE_N_CNTXT_GLOB_IRQ_EN_OFFSET(ee) \
	379	(0x0001f108 + 0x4000 * (ee))
ca48b27b AE	380	#define GSI_CNTXT_GLOB_IRQ_CLR_OFFSET \
	381	GSI_EE_N_CNTXT_GLOB_IRQ_CLR_OFFSET(GSI_EE_AP)
	382	#define GSI_EE_N_CNTXT_GLOB_IRQ_CLR_OFFSET(ee) \
	383	(0x0001f110 + 0x4000 * (ee))
6c6358cc AE	384	/* Values here are bit positions in the GLOB_IRQ_* registers */
	385	enum gsi_global_irq_id {
	386	ERROR_INT = 0x0,
	387	GP_INT1 = 0x1,
	388	GP_INT2 = 0x2,
	389	GP_INT3 = 0x3,
	390	};
ca48b27b AE	391
	392	#define GSI_CNTXT_GSI_IRQ_STTS_OFFSET \
	393	GSI_EE_N_CNTXT_GSI_IRQ_STTS_OFFSET(GSI_EE_AP)
	394	#define GSI_EE_N_CNTXT_GSI_IRQ_STTS_OFFSET(ee) \
	395	(0x0001f118 + 0x4000 * (ee))
ca48b27b AE	396	#define GSI_CNTXT_GSI_IRQ_EN_OFFSET \
	397	GSI_EE_N_CNTXT_GSI_IRQ_EN_OFFSET(GSI_EE_AP)
	398	#define GSI_EE_N_CNTXT_GSI_IRQ_EN_OFFSET(ee) \
	399	(0x0001f120 + 0x4000 * (ee))
ca48b27b AE	400	#define GSI_CNTXT_GSI_IRQ_CLR_OFFSET \
	401	GSI_EE_N_CNTXT_GSI_IRQ_CLR_OFFSET(GSI_EE_AP)
	402	#define GSI_EE_N_CNTXT_GSI_IRQ_CLR_OFFSET(ee) \
	403	(0x0001f128 + 0x4000 * (ee))
6c6358cc AE	404	/* Values here are bit positions in the (general) GSI_IRQ_* registers */
	405	enum gsi_general_id {
	406	BREAK_POINT = 0x0,
	407	BUS_ERROR = 0x1,
	408	CMD_FIFO_OVRFLOW = 0x2,
	409	MCS_STACK_OVRFLOW = 0x3,
	410	};
ca48b27b AE	411
	412	#define GSI_CNTXT_INTSET_OFFSET \
	413	GSI_EE_N_CNTXT_INTSET_OFFSET(GSI_EE_AP)
	414	#define GSI_EE_N_CNTXT_INTSET_OFFSET(ee) \
	415	(0x0001f180 + 0x4000 * (ee))
	416	#define INTYPE_FMASK GENMASK(0, 0)
	417
	418	#define GSI_ERROR_LOG_OFFSET \
	419	GSI_EE_N_ERROR_LOG_OFFSET(GSI_EE_AP)
	420	#define GSI_EE_N_ERROR_LOG_OFFSET(ee) \
	421	(0x0001f200 + 0x4000 * (ee))
	422	#define ERR_ARG3_FMASK GENMASK(3, 0)
	423	#define ERR_ARG2_FMASK GENMASK(7, 4)
	424	#define ERR_ARG1_FMASK GENMASK(11, 8)
	425	#define ERR_CODE_FMASK GENMASK(15, 12)
	426	#define ERR_VIRT_IDX_FMASK GENMASK(23, 19)
	427	#define ERR_TYPE_FMASK GENMASK(27, 24)
	428	#define ERR_EE_FMASK GENMASK(31, 28)
8701cb00	429
7b0ac8f6 AE	430	/** enum gsi_err_code - ERR_CODE field values in EE_ERR_LOG */
	431	enum gsi_err_code {
	432	GSI_INVALID_TRE = 0x1,
	433	GSI_OUT_OF_BUFFERS = 0x2,
	434	GSI_OUT_OF_RESOURCES = 0x3,
	435	GSI_UNSUPPORTED_INTER_EE_OP = 0x4,
	436	GSI_EVT_RING_EMPTY = 0x5,
	437	GSI_NON_ALLOCATED_EVT_ACCESS = 0x6,
	438	/* 7 is not assigned */
	439	GSI_HWO_1 = 0x8,
	440	};
8701cb00	441
7b0ac8f6 AE	442	/** enum gsi_err_type - ERR_TYPE field values in EE_ERR_LOG */
	443	enum gsi_err_type {
	444	GSI_ERR_TYPE_GLOB = 0x1,
	445	GSI_ERR_TYPE_CHAN = 0x2,
	446	GSI_ERR_TYPE_EVT = 0x3,
	447	};
ca48b27b AE	448
	449	#define GSI_ERROR_LOG_CLR_OFFSET \
	450	GSI_EE_N_ERROR_LOG_CLR_OFFSET(GSI_EE_AP)
	451	#define GSI_EE_N_ERROR_LOG_CLR_OFFSET(ee) \
	452	(0x0001f210 + 0x4000 * (ee))
	453
	454	#define GSI_CNTXT_SCRATCH_0_OFFSET \
	455	GSI_EE_N_CNTXT_SCRATCH_0_OFFSET(GSI_EE_AP)
	456	#define GSI_EE_N_CNTXT_SCRATCH_0_OFFSET(ee) \
	457	(0x0001f400 + 0x4000 * (ee))
	458	#define INTER_EE_RESULT_FMASK GENMASK(2, 0)
	459	#define GENERIC_EE_RESULT_FMASK GENMASK(7, 5)
8701cb00 AE	460
8701cb00 AE	461	/** enum gsi_generic_ee_result - GENERIC_EE_RESULT field values in SCRATCH_0 */
4730ab1c AE	462	enum gsi_generic_ee_result {
	463	GENERIC_EE_SUCCESS = 0x1,
	464	GENERIC_EE_CHANNEL_NOT_RUNNING = 0x2,
	465	GENERIC_EE_INCORRECT_DIRECTION = 0x3,
	466	GENERIC_EE_INCORRECT_CHANNEL_TYPE = 0x4,
	467	GENERIC_EE_INCORRECT_CHANNEL = 0x5,
	468	GENERIC_EE_RETRY = 0x6,
	469	GENERIC_EE_NO_RESOURCES = 0x7,
	470	};
8701cb00	471
ca48b27b AE	472	#define USB_MAX_PACKET_FMASK GENMASK(15, 15) /* 0: HS; 1: SS */
	473	#define MHI_BASE_CHANNEL_FMASK GENMASK(31, 24)
	474
	475	#endif /* _GSI_REG_H_ */