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1da177e4 LT |
1 | /* |
2 | * Alchemy Semi Au1000 IrDA driver | |
3 | * | |
4 | * Copyright 2001 MontaVista Software Inc. | |
5 | * Author: MontaVista Software, Inc. | |
6 | * ppopov@mvista.com or source@mvista.com | |
7 | * | |
8 | * This program is free software; you can distribute it and/or modify it | |
9 | * under the terms of the GNU General Public License (Version 2) as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | * for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along | |
18 | * with this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. | |
20 | */ | |
1da177e4 LT |
21 | #include <linux/module.h> |
22 | #include <linux/types.h> | |
23 | #include <linux/init.h> | |
24 | #include <linux/errno.h> | |
25 | #include <linux/netdevice.h> | |
f6a26293 | 26 | #include <linux/etherdevice.h> |
1da177e4 LT |
27 | #include <linux/slab.h> |
28 | #include <linux/rtnetlink.h> | |
29 | #include <linux/interrupt.h> | |
30 | #include <linux/pm.h> | |
31 | #include <linux/bitops.h> | |
32 | ||
33 | #include <asm/irq.h> | |
34 | #include <asm/io.h> | |
35 | #include <asm/au1000.h> | |
36 | #if defined(CONFIG_MIPS_PB1000) || defined(CONFIG_MIPS_PB1100) | |
37 | #include <asm/pb1000.h> | |
38 | #elif defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) | |
39 | #include <asm/db1x00.h> | |
40 | #else | |
41 | #error au1k_ir: unsupported board | |
42 | #endif | |
43 | ||
44 | #include <net/irda/irda.h> | |
45 | #include <net/irda/irmod.h> | |
46 | #include <net/irda/wrapper.h> | |
47 | #include <net/irda/irda_device.h> | |
48 | #include "au1000_ircc.h" | |
49 | ||
50 | static int au1k_irda_net_init(struct net_device *); | |
51 | static int au1k_irda_start(struct net_device *); | |
52 | static int au1k_irda_stop(struct net_device *dev); | |
53 | static int au1k_irda_hard_xmit(struct sk_buff *, struct net_device *); | |
54 | static int au1k_irda_rx(struct net_device *); | |
7d12e780 | 55 | static void au1k_irda_interrupt(int, void *); |
1da177e4 | 56 | static void au1k_tx_timeout(struct net_device *); |
1da177e4 LT |
57 | static int au1k_irda_ioctl(struct net_device *, struct ifreq *, int); |
58 | static int au1k_irda_set_speed(struct net_device *dev, int speed); | |
59 | ||
60 | static void *dma_alloc(size_t, dma_addr_t *); | |
61 | static void dma_free(void *, size_t); | |
62 | ||
63 | static int qos_mtt_bits = 0x07; /* 1 ms or more */ | |
64 | static struct net_device *ir_devs[NUM_IR_IFF]; | |
65 | static char version[] __devinitdata = | |
66 | "au1k_ircc:1.2 ppopov@mvista.com\n"; | |
67 | ||
68 | #define RUN_AT(x) (jiffies + (x)) | |
69 | ||
70 | #if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) | |
71 | static BCSR * const bcsr = (BCSR *)0xAE000000; | |
72 | #endif | |
73 | ||
74 | static DEFINE_SPINLOCK(ir_lock); | |
75 | ||
76 | /* | |
77 | * IrDA peripheral bug. You have to read the register | |
78 | * twice to get the right value. | |
79 | */ | |
80 | u32 read_ir_reg(u32 addr) | |
81 | { | |
82 | readl(addr); | |
83 | return readl(addr); | |
84 | } | |
85 | ||
86 | ||
87 | /* | |
88 | * Buffer allocation/deallocation routines. The buffer descriptor returned | |
89 | * has the virtual and dma address of a buffer suitable for | |
90 | * both, receive and transmit operations. | |
91 | */ | |
92 | static db_dest_t *GetFreeDB(struct au1k_private *aup) | |
93 | { | |
94 | db_dest_t *pDB; | |
95 | pDB = aup->pDBfree; | |
96 | ||
97 | if (pDB) { | |
98 | aup->pDBfree = pDB->pnext; | |
99 | } | |
100 | return pDB; | |
101 | } | |
102 | ||
103 | static void ReleaseDB(struct au1k_private *aup, db_dest_t *pDB) | |
104 | { | |
105 | db_dest_t *pDBfree = aup->pDBfree; | |
106 | if (pDBfree) | |
107 | pDBfree->pnext = pDB; | |
108 | aup->pDBfree = pDB; | |
109 | } | |
110 | ||
111 | ||
112 | /* | |
113 | DMA memory allocation, derived from pci_alloc_consistent. | |
114 | However, the Au1000 data cache is coherent (when programmed | |
115 | so), therefore we return KSEG0 address, not KSEG1. | |
116 | */ | |
117 | static void *dma_alloc(size_t size, dma_addr_t * dma_handle) | |
118 | { | |
119 | void *ret; | |
120 | int gfp = GFP_ATOMIC | GFP_DMA; | |
121 | ||
122 | ret = (void *) __get_free_pages(gfp, get_order(size)); | |
123 | ||
124 | if (ret != NULL) { | |
125 | memset(ret, 0, size); | |
126 | *dma_handle = virt_to_bus(ret); | |
127 | ret = (void *)KSEG0ADDR(ret); | |
128 | } | |
129 | return ret; | |
130 | } | |
131 | ||
132 | ||
133 | static void dma_free(void *vaddr, size_t size) | |
134 | { | |
135 | vaddr = (void *)KSEG0ADDR(vaddr); | |
136 | free_pages((unsigned long) vaddr, get_order(size)); | |
137 | } | |
138 | ||
139 | ||
140 | static void | |
141 | setup_hw_rings(struct au1k_private *aup, u32 rx_base, u32 tx_base) | |
142 | { | |
143 | int i; | |
144 | for (i=0; i<NUM_IR_DESC; i++) { | |
145 | aup->rx_ring[i] = (volatile ring_dest_t *) | |
146 | (rx_base + sizeof(ring_dest_t)*i); | |
147 | } | |
148 | for (i=0; i<NUM_IR_DESC; i++) { | |
149 | aup->tx_ring[i] = (volatile ring_dest_t *) | |
150 | (tx_base + sizeof(ring_dest_t)*i); | |
151 | } | |
152 | } | |
153 | ||
154 | static int au1k_irda_init(void) | |
155 | { | |
156 | static unsigned version_printed = 0; | |
157 | struct au1k_private *aup; | |
158 | struct net_device *dev; | |
159 | int err; | |
160 | ||
161 | if (version_printed++ == 0) printk(version); | |
162 | ||
163 | dev = alloc_irdadev(sizeof(struct au1k_private)); | |
164 | if (!dev) | |
165 | return -ENOMEM; | |
166 | ||
167 | dev->irq = AU1000_IRDA_RX_INT; /* TX has its own interrupt */ | |
168 | err = au1k_irda_net_init(dev); | |
169 | if (err) | |
170 | goto out; | |
171 | err = register_netdev(dev); | |
172 | if (err) | |
173 | goto out1; | |
174 | ir_devs[0] = dev; | |
175 | printk(KERN_INFO "IrDA: Registered device %s\n", dev->name); | |
176 | return 0; | |
177 | ||
178 | out1: | |
179 | aup = netdev_priv(dev); | |
180 | dma_free((void *)aup->db[0].vaddr, | |
181 | MAX_BUF_SIZE * 2*NUM_IR_DESC); | |
182 | dma_free((void *)aup->rx_ring[0], | |
183 | 2 * MAX_NUM_IR_DESC*(sizeof(ring_dest_t))); | |
184 | kfree(aup->rx_buff.head); | |
185 | out: | |
186 | free_netdev(dev); | |
187 | return err; | |
188 | } | |
189 | ||
190 | static int au1k_irda_init_iobuf(iobuff_t *io, int size) | |
191 | { | |
192 | io->head = kmalloc(size, GFP_KERNEL); | |
193 | if (io->head != NULL) { | |
194 | io->truesize = size; | |
195 | io->in_frame = FALSE; | |
196 | io->state = OUTSIDE_FRAME; | |
197 | io->data = io->head; | |
198 | } | |
199 | return io->head ? 0 : -ENOMEM; | |
200 | } | |
201 | ||
602355a0 AB |
202 | static const struct net_device_ops au1k_irda_netdev_ops = { |
203 | .ndo_open = au1k_irda_start, | |
204 | .ndo_stop = au1k_irda_stop, | |
205 | .ndo_start_xmit = au1k_irda_hard_xmit, | |
206 | .ndo_tx_timeout = au1k_tx_timeout, | |
207 | .ndo_do_ioctl = au1k_irda_ioctl, | |
208 | .ndo_change_mtu = eth_change_mtu, | |
209 | .ndo_validate_addr = eth_validate_addr, | |
210 | .ndo_set_mac_address = eth_mac_addr, | |
211 | }; | |
212 | ||
1da177e4 LT |
213 | static int au1k_irda_net_init(struct net_device *dev) |
214 | { | |
215 | struct au1k_private *aup = netdev_priv(dev); | |
216 | int i, retval = 0, err; | |
217 | db_dest_t *pDB, *pDBfree; | |
218 | dma_addr_t temp; | |
219 | ||
220 | err = au1k_irda_init_iobuf(&aup->rx_buff, 14384); | |
221 | if (err) | |
222 | goto out1; | |
223 | ||
602355a0 | 224 | dev->netdev_ops = &au1k_irda_netdev_ops; |
1da177e4 LT |
225 | |
226 | irda_init_max_qos_capabilies(&aup->qos); | |
227 | ||
228 | /* The only value we must override it the baudrate */ | |
229 | aup->qos.baud_rate.bits = IR_9600|IR_19200|IR_38400|IR_57600| | |
230 | IR_115200|IR_576000 |(IR_4000000 << 8); | |
231 | ||
232 | aup->qos.min_turn_time.bits = qos_mtt_bits; | |
233 | irda_qos_bits_to_value(&aup->qos); | |
234 | ||
235 | retval = -ENOMEM; | |
236 | ||
237 | /* Tx ring follows rx ring + 512 bytes */ | |
238 | /* we need a 1k aligned buffer */ | |
239 | aup->rx_ring[0] = (ring_dest_t *) | |
240 | dma_alloc(2*MAX_NUM_IR_DESC*(sizeof(ring_dest_t)), &temp); | |
241 | if (!aup->rx_ring[0]) | |
242 | goto out2; | |
243 | ||
244 | /* allocate the data buffers */ | |
245 | aup->db[0].vaddr = | |
246 | (void *)dma_alloc(MAX_BUF_SIZE * 2*NUM_IR_DESC, &temp); | |
247 | if (!aup->db[0].vaddr) | |
248 | goto out3; | |
249 | ||
250 | setup_hw_rings(aup, (u32)aup->rx_ring[0], (u32)aup->rx_ring[0] + 512); | |
251 | ||
252 | pDBfree = NULL; | |
253 | pDB = aup->db; | |
254 | for (i=0; i<(2*NUM_IR_DESC); i++) { | |
255 | pDB->pnext = pDBfree; | |
256 | pDBfree = pDB; | |
257 | pDB->vaddr = | |
258 | (u32 *)((unsigned)aup->db[0].vaddr + MAX_BUF_SIZE*i); | |
259 | pDB->dma_addr = (dma_addr_t)virt_to_bus(pDB->vaddr); | |
260 | pDB++; | |
261 | } | |
262 | aup->pDBfree = pDBfree; | |
263 | ||
264 | /* attach a data buffer to each descriptor */ | |
265 | for (i=0; i<NUM_IR_DESC; i++) { | |
266 | pDB = GetFreeDB(aup); | |
267 | if (!pDB) goto out; | |
268 | aup->rx_ring[i]->addr_0 = (u8)(pDB->dma_addr & 0xff); | |
269 | aup->rx_ring[i]->addr_1 = (u8)((pDB->dma_addr>>8) & 0xff); | |
270 | aup->rx_ring[i]->addr_2 = (u8)((pDB->dma_addr>>16) & 0xff); | |
271 | aup->rx_ring[i]->addr_3 = (u8)((pDB->dma_addr>>24) & 0xff); | |
272 | aup->rx_db_inuse[i] = pDB; | |
273 | } | |
274 | for (i=0; i<NUM_IR_DESC; i++) { | |
275 | pDB = GetFreeDB(aup); | |
276 | if (!pDB) goto out; | |
277 | aup->tx_ring[i]->addr_0 = (u8)(pDB->dma_addr & 0xff); | |
278 | aup->tx_ring[i]->addr_1 = (u8)((pDB->dma_addr>>8) & 0xff); | |
279 | aup->tx_ring[i]->addr_2 = (u8)((pDB->dma_addr>>16) & 0xff); | |
280 | aup->tx_ring[i]->addr_3 = (u8)((pDB->dma_addr>>24) & 0xff); | |
281 | aup->tx_ring[i]->count_0 = 0; | |
282 | aup->tx_ring[i]->count_1 = 0; | |
283 | aup->tx_ring[i]->flags = 0; | |
284 | aup->tx_db_inuse[i] = pDB; | |
285 | } | |
286 | ||
287 | #if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) | |
288 | /* power on */ | |
289 | bcsr->resets &= ~BCSR_RESETS_IRDA_MODE_MASK; | |
290 | bcsr->resets |= BCSR_RESETS_IRDA_MODE_FULL; | |
291 | au_sync(); | |
292 | #endif | |
293 | ||
294 | return 0; | |
295 | ||
296 | out3: | |
297 | dma_free((void *)aup->rx_ring[0], | |
298 | 2 * MAX_NUM_IR_DESC*(sizeof(ring_dest_t))); | |
299 | out2: | |
300 | kfree(aup->rx_buff.head); | |
301 | out1: | |
302 | printk(KERN_ERR "au1k_init_module failed. Returns %d\n", retval); | |
303 | return retval; | |
304 | } | |
305 | ||
306 | ||
307 | static int au1k_init(struct net_device *dev) | |
308 | { | |
309 | struct au1k_private *aup = netdev_priv(dev); | |
310 | int i; | |
311 | u32 control; | |
312 | u32 ring_address; | |
313 | ||
314 | /* bring the device out of reset */ | |
315 | control = 0xe; /* coherent, clock enable, one half system clock */ | |
316 | ||
317 | #ifndef CONFIG_CPU_LITTLE_ENDIAN | |
318 | control |= 1; | |
319 | #endif | |
320 | aup->tx_head = 0; | |
321 | aup->tx_tail = 0; | |
322 | aup->rx_head = 0; | |
323 | ||
324 | for (i=0; i<NUM_IR_DESC; i++) { | |
325 | aup->rx_ring[i]->flags = AU_OWN; | |
326 | } | |
327 | ||
328 | writel(control, IR_INTERFACE_CONFIG); | |
329 | au_sync_delay(10); | |
330 | ||
331 | writel(read_ir_reg(IR_ENABLE) & ~0x8000, IR_ENABLE); /* disable PHY */ | |
332 | au_sync_delay(1); | |
333 | ||
334 | writel(MAX_BUF_SIZE, IR_MAX_PKT_LEN); | |
335 | ||
336 | ring_address = (u32)virt_to_phys((void *)aup->rx_ring[0]); | |
337 | writel(ring_address >> 26, IR_RING_BASE_ADDR_H); | |
338 | writel((ring_address >> 10) & 0xffff, IR_RING_BASE_ADDR_L); | |
339 | ||
340 | writel(RING_SIZE_64<<8 | RING_SIZE_64<<12, IR_RING_SIZE); | |
341 | ||
342 | writel(1<<2 | IR_ONE_PIN, IR_CONFIG_2); /* 48MHz */ | |
343 | writel(0, IR_RING_ADDR_CMPR); | |
344 | ||
345 | au1k_irda_set_speed(dev, 9600); | |
346 | return 0; | |
347 | } | |
348 | ||
349 | static int au1k_irda_start(struct net_device *dev) | |
350 | { | |
351 | int retval; | |
352 | char hwname[32]; | |
353 | struct au1k_private *aup = netdev_priv(dev); | |
354 | ||
355 | if ((retval = au1k_init(dev))) { | |
356 | printk(KERN_ERR "%s: error in au1k_init\n", dev->name); | |
357 | return retval; | |
358 | } | |
359 | ||
360 | if ((retval = request_irq(AU1000_IRDA_TX_INT, &au1k_irda_interrupt, | |
361 | 0, dev->name, dev))) { | |
362 | printk(KERN_ERR "%s: unable to get IRQ %d\n", | |
363 | dev->name, dev->irq); | |
364 | return retval; | |
365 | } | |
366 | if ((retval = request_irq(AU1000_IRDA_RX_INT, &au1k_irda_interrupt, | |
367 | 0, dev->name, dev))) { | |
368 | free_irq(AU1000_IRDA_TX_INT, dev); | |
369 | printk(KERN_ERR "%s: unable to get IRQ %d\n", | |
370 | dev->name, dev->irq); | |
371 | return retval; | |
372 | } | |
373 | ||
374 | /* Give self a hardware name */ | |
375 | sprintf(hwname, "Au1000 SIR/FIR"); | |
376 | aup->irlap = irlap_open(dev, &aup->qos, hwname); | |
377 | netif_start_queue(dev); | |
378 | ||
379 | writel(read_ir_reg(IR_CONFIG_2) | 1<<8, IR_CONFIG_2); /* int enable */ | |
380 | ||
381 | aup->timer.expires = RUN_AT((3*HZ)); | |
382 | aup->timer.data = (unsigned long)dev; | |
383 | return 0; | |
384 | } | |
385 | ||
386 | static int au1k_irda_stop(struct net_device *dev) | |
387 | { | |
388 | struct au1k_private *aup = netdev_priv(dev); | |
389 | ||
390 | /* disable interrupts */ | |
391 | writel(read_ir_reg(IR_CONFIG_2) & ~(1<<8), IR_CONFIG_2); | |
392 | writel(0, IR_CONFIG_1); | |
393 | writel(0, IR_INTERFACE_CONFIG); /* disable clock */ | |
394 | au_sync(); | |
395 | ||
396 | if (aup->irlap) { | |
397 | irlap_close(aup->irlap); | |
398 | aup->irlap = NULL; | |
399 | } | |
400 | ||
401 | netif_stop_queue(dev); | |
402 | del_timer(&aup->timer); | |
403 | ||
404 | /* disable the interrupt */ | |
405 | free_irq(AU1000_IRDA_TX_INT, dev); | |
406 | free_irq(AU1000_IRDA_RX_INT, dev); | |
407 | return 0; | |
408 | } | |
409 | ||
410 | static void __exit au1k_irda_exit(void) | |
411 | { | |
412 | struct net_device *dev = ir_devs[0]; | |
413 | struct au1k_private *aup = netdev_priv(dev); | |
414 | ||
415 | unregister_netdev(dev); | |
416 | ||
417 | dma_free((void *)aup->db[0].vaddr, | |
418 | MAX_BUF_SIZE * 2*NUM_IR_DESC); | |
419 | dma_free((void *)aup->rx_ring[0], | |
420 | 2 * MAX_NUM_IR_DESC*(sizeof(ring_dest_t))); | |
421 | kfree(aup->rx_buff.head); | |
422 | free_netdev(dev); | |
423 | } | |
424 | ||
425 | ||
426 | static inline void | |
427 | update_tx_stats(struct net_device *dev, u32 status, u32 pkt_len) | |
428 | { | |
429 | struct au1k_private *aup = netdev_priv(dev); | |
430 | struct net_device_stats *ps = &aup->stats; | |
431 | ||
432 | ps->tx_packets++; | |
433 | ps->tx_bytes += pkt_len; | |
434 | ||
435 | if (status & IR_TX_ERROR) { | |
436 | ps->tx_errors++; | |
437 | ps->tx_aborted_errors++; | |
438 | } | |
439 | } | |
440 | ||
441 | ||
442 | static void au1k_tx_ack(struct net_device *dev) | |
443 | { | |
444 | struct au1k_private *aup = netdev_priv(dev); | |
445 | volatile ring_dest_t *ptxd; | |
446 | ||
447 | ptxd = aup->tx_ring[aup->tx_tail]; | |
448 | while (!(ptxd->flags & AU_OWN) && (aup->tx_tail != aup->tx_head)) { | |
449 | update_tx_stats(dev, ptxd->flags, | |
450 | ptxd->count_1<<8 | ptxd->count_0); | |
451 | ptxd->count_0 = 0; | |
452 | ptxd->count_1 = 0; | |
453 | au_sync(); | |
454 | ||
455 | aup->tx_tail = (aup->tx_tail + 1) & (NUM_IR_DESC - 1); | |
456 | ptxd = aup->tx_ring[aup->tx_tail]; | |
457 | ||
458 | if (aup->tx_full) { | |
459 | aup->tx_full = 0; | |
460 | netif_wake_queue(dev); | |
461 | } | |
462 | } | |
463 | ||
464 | if (aup->tx_tail == aup->tx_head) { | |
465 | if (aup->newspeed) { | |
466 | au1k_irda_set_speed(dev, aup->newspeed); | |
467 | aup->newspeed = 0; | |
468 | } | |
469 | else { | |
470 | writel(read_ir_reg(IR_CONFIG_1) & ~IR_TX_ENABLE, | |
471 | IR_CONFIG_1); | |
472 | au_sync(); | |
473 | writel(read_ir_reg(IR_CONFIG_1) | IR_RX_ENABLE, | |
474 | IR_CONFIG_1); | |
475 | writel(0, IR_RING_PROMPT); | |
476 | au_sync(); | |
477 | } | |
478 | } | |
479 | } | |
480 | ||
481 | ||
482 | /* | |
483 | * Au1000 transmit routine. | |
484 | */ | |
485 | static int au1k_irda_hard_xmit(struct sk_buff *skb, struct net_device *dev) | |
486 | { | |
487 | struct au1k_private *aup = netdev_priv(dev); | |
488 | int speed = irda_get_next_speed(skb); | |
489 | volatile ring_dest_t *ptxd; | |
490 | u32 len; | |
491 | ||
492 | u32 flags; | |
493 | db_dest_t *pDB; | |
494 | ||
495 | if (speed != aup->speed && speed != -1) { | |
496 | aup->newspeed = speed; | |
497 | } | |
498 | ||
499 | if ((skb->len == 0) && (aup->newspeed)) { | |
500 | if (aup->tx_tail == aup->tx_head) { | |
501 | au1k_irda_set_speed(dev, speed); | |
502 | aup->newspeed = 0; | |
503 | } | |
504 | dev_kfree_skb(skb); | |
6ed10654 | 505 | return NETDEV_TX_OK; |
1da177e4 LT |
506 | } |
507 | ||
508 | ptxd = aup->tx_ring[aup->tx_head]; | |
509 | flags = ptxd->flags; | |
510 | ||
511 | if (flags & AU_OWN) { | |
512 | printk(KERN_DEBUG "%s: tx_full\n", dev->name); | |
513 | netif_stop_queue(dev); | |
514 | aup->tx_full = 1; | |
5b548140 | 515 | return NETDEV_TX_BUSY; |
1da177e4 LT |
516 | } |
517 | else if (((aup->tx_head + 1) & (NUM_IR_DESC - 1)) == aup->tx_tail) { | |
518 | printk(KERN_DEBUG "%s: tx_full\n", dev->name); | |
519 | netif_stop_queue(dev); | |
520 | aup->tx_full = 1; | |
5b548140 | 521 | return NETDEV_TX_BUSY; |
1da177e4 LT |
522 | } |
523 | ||
524 | pDB = aup->tx_db_inuse[aup->tx_head]; | |
525 | ||
526 | #if 0 | |
527 | if (read_ir_reg(IR_RX_BYTE_CNT) != 0) { | |
528 | printk("tx warning: rx byte cnt %x\n", | |
529 | read_ir_reg(IR_RX_BYTE_CNT)); | |
530 | } | |
531 | #endif | |
532 | ||
533 | if (aup->speed == 4000000) { | |
534 | /* FIR */ | |
d626f62b | 535 | skb_copy_from_linear_data(skb, pDB->vaddr, skb->len); |
1da177e4 LT |
536 | ptxd->count_0 = skb->len & 0xff; |
537 | ptxd->count_1 = (skb->len >> 8) & 0xff; | |
538 | ||
539 | } | |
540 | else { | |
541 | /* SIR */ | |
542 | len = async_wrap_skb(skb, (u8 *)pDB->vaddr, MAX_BUF_SIZE); | |
543 | ptxd->count_0 = len & 0xff; | |
544 | ptxd->count_1 = (len >> 8) & 0xff; | |
545 | ptxd->flags |= IR_DIS_CRC; | |
546 | au_writel(au_readl(0xae00000c) & ~(1<<13), 0xae00000c); | |
547 | } | |
548 | ptxd->flags |= AU_OWN; | |
549 | au_sync(); | |
550 | ||
551 | writel(read_ir_reg(IR_CONFIG_1) | IR_TX_ENABLE, IR_CONFIG_1); | |
552 | writel(0, IR_RING_PROMPT); | |
553 | au_sync(); | |
554 | ||
555 | dev_kfree_skb(skb); | |
556 | aup->tx_head = (aup->tx_head + 1) & (NUM_IR_DESC - 1); | |
557 | dev->trans_start = jiffies; | |
6ed10654 | 558 | return NETDEV_TX_OK; |
1da177e4 LT |
559 | } |
560 | ||
561 | ||
562 | static inline void | |
563 | update_rx_stats(struct net_device *dev, u32 status, u32 count) | |
564 | { | |
565 | struct au1k_private *aup = netdev_priv(dev); | |
566 | struct net_device_stats *ps = &aup->stats; | |
567 | ||
568 | ps->rx_packets++; | |
569 | ||
570 | if (status & IR_RX_ERROR) { | |
571 | ps->rx_errors++; | |
572 | if (status & (IR_PHY_ERROR|IR_FIFO_OVER)) | |
573 | ps->rx_missed_errors++; | |
574 | if (status & IR_MAX_LEN) | |
575 | ps->rx_length_errors++; | |
576 | if (status & IR_CRC_ERROR) | |
577 | ps->rx_crc_errors++; | |
578 | } | |
579 | else | |
580 | ps->rx_bytes += count; | |
581 | } | |
582 | ||
583 | /* | |
584 | * Au1000 receive routine. | |
585 | */ | |
586 | static int au1k_irda_rx(struct net_device *dev) | |
587 | { | |
588 | struct au1k_private *aup = netdev_priv(dev); | |
589 | struct sk_buff *skb; | |
590 | volatile ring_dest_t *prxd; | |
591 | u32 flags, count; | |
592 | db_dest_t *pDB; | |
593 | ||
594 | prxd = aup->rx_ring[aup->rx_head]; | |
595 | flags = prxd->flags; | |
596 | ||
597 | while (!(flags & AU_OWN)) { | |
598 | pDB = aup->rx_db_inuse[aup->rx_head]; | |
599 | count = prxd->count_1<<8 | prxd->count_0; | |
600 | if (!(flags & IR_RX_ERROR)) { | |
601 | /* good frame */ | |
602 | update_rx_stats(dev, flags, count); | |
603 | skb=alloc_skb(count+1,GFP_ATOMIC); | |
604 | if (skb == NULL) { | |
216c32d4 | 605 | aup->netdev->stats.rx_dropped++; |
1da177e4 LT |
606 | continue; |
607 | } | |
608 | skb_reserve(skb, 1); | |
609 | if (aup->speed == 4000000) | |
610 | skb_put(skb, count); | |
611 | else | |
612 | skb_put(skb, count-2); | |
27d7ff46 | 613 | skb_copy_to_linear_data(skb, pDB->vaddr, count - 2); |
1da177e4 | 614 | skb->dev = dev; |
459a98ed | 615 | skb_reset_mac_header(skb); |
1da177e4 LT |
616 | skb->protocol = htons(ETH_P_IRDA); |
617 | netif_rx(skb); | |
618 | prxd->count_0 = 0; | |
619 | prxd->count_1 = 0; | |
620 | } | |
621 | prxd->flags |= AU_OWN; | |
622 | aup->rx_head = (aup->rx_head + 1) & (NUM_IR_DESC - 1); | |
623 | writel(0, IR_RING_PROMPT); | |
624 | au_sync(); | |
625 | ||
626 | /* next descriptor */ | |
627 | prxd = aup->rx_ring[aup->rx_head]; | |
628 | flags = prxd->flags; | |
1da177e4 LT |
629 | |
630 | } | |
631 | return 0; | |
632 | } | |
633 | ||
634 | ||
e38c2c65 | 635 | static irqreturn_t au1k_irda_interrupt(int dummy, void *dev_id) |
1da177e4 | 636 | { |
e38c2c65 | 637 | struct net_device *dev = dev_id; |
1da177e4 LT |
638 | |
639 | writel(0, IR_INT_CLEAR); /* ack irda interrupts */ | |
640 | ||
641 | au1k_irda_rx(dev); | |
642 | au1k_tx_ack(dev); | |
e38c2c65 JG |
643 | |
644 | return IRQ_HANDLED; | |
1da177e4 LT |
645 | } |
646 | ||
647 | ||
648 | /* | |
649 | * The Tx ring has been full longer than the watchdog timeout | |
650 | * value. The transmitter must be hung? | |
651 | */ | |
652 | static void au1k_tx_timeout(struct net_device *dev) | |
653 | { | |
654 | u32 speed; | |
655 | struct au1k_private *aup = netdev_priv(dev); | |
656 | ||
657 | printk(KERN_ERR "%s: tx timeout\n", dev->name); | |
658 | speed = aup->speed; | |
659 | aup->speed = 0; | |
660 | au1k_irda_set_speed(dev, speed); | |
661 | aup->tx_full = 0; | |
662 | netif_wake_queue(dev); | |
663 | } | |
664 | ||
665 | ||
666 | /* | |
667 | * Set the IrDA communications speed. | |
668 | */ | |
669 | static int | |
670 | au1k_irda_set_speed(struct net_device *dev, int speed) | |
671 | { | |
672 | unsigned long flags; | |
673 | struct au1k_private *aup = netdev_priv(dev); | |
674 | u32 control; | |
675 | int ret = 0, timeout = 10, i; | |
676 | volatile ring_dest_t *ptxd; | |
677 | #if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) | |
678 | unsigned long irda_resets; | |
679 | #endif | |
680 | ||
681 | if (speed == aup->speed) | |
682 | return ret; | |
683 | ||
684 | spin_lock_irqsave(&ir_lock, flags); | |
685 | ||
686 | /* disable PHY first */ | |
687 | writel(read_ir_reg(IR_ENABLE) & ~0x8000, IR_ENABLE); | |
688 | ||
689 | /* disable RX/TX */ | |
690 | writel(read_ir_reg(IR_CONFIG_1) & ~(IR_RX_ENABLE|IR_TX_ENABLE), | |
691 | IR_CONFIG_1); | |
692 | au_sync_delay(1); | |
693 | while (read_ir_reg(IR_ENABLE) & (IR_RX_STATUS | IR_TX_STATUS)) { | |
694 | mdelay(1); | |
695 | if (!timeout--) { | |
696 | printk(KERN_ERR "%s: rx/tx disable timeout\n", | |
697 | dev->name); | |
698 | break; | |
699 | } | |
700 | } | |
701 | ||
702 | /* disable DMA */ | |
703 | writel(read_ir_reg(IR_CONFIG_1) & ~IR_DMA_ENABLE, IR_CONFIG_1); | |
704 | au_sync_delay(1); | |
705 | ||
706 | /* | |
707 | * After we disable tx/rx. the index pointers | |
708 | * go back to zero. | |
709 | */ | |
710 | aup->tx_head = aup->tx_tail = aup->rx_head = 0; | |
711 | for (i=0; i<NUM_IR_DESC; i++) { | |
712 | ptxd = aup->tx_ring[i]; | |
713 | ptxd->flags = 0; | |
714 | ptxd->count_0 = 0; | |
715 | ptxd->count_1 = 0; | |
716 | } | |
717 | ||
718 | for (i=0; i<NUM_IR_DESC; i++) { | |
719 | ptxd = aup->rx_ring[i]; | |
720 | ptxd->count_0 = 0; | |
721 | ptxd->count_1 = 0; | |
722 | ptxd->flags = AU_OWN; | |
723 | } | |
724 | ||
725 | if (speed == 4000000) { | |
726 | #if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) | |
727 | bcsr->resets |= BCSR_RESETS_FIR_SEL; | |
728 | #else /* Pb1000 and Pb1100 */ | |
729 | writel(1<<13, CPLD_AUX1); | |
730 | #endif | |
731 | } | |
732 | else { | |
733 | #if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) | |
734 | bcsr->resets &= ~BCSR_RESETS_FIR_SEL; | |
735 | #else /* Pb1000 and Pb1100 */ | |
736 | writel(readl(CPLD_AUX1) & ~(1<<13), CPLD_AUX1); | |
737 | #endif | |
738 | } | |
739 | ||
740 | switch (speed) { | |
741 | case 9600: | |
742 | writel(11<<10 | 12<<5, IR_WRITE_PHY_CONFIG); | |
743 | writel(IR_SIR_MODE, IR_CONFIG_1); | |
744 | break; | |
745 | case 19200: | |
746 | writel(5<<10 | 12<<5, IR_WRITE_PHY_CONFIG); | |
747 | writel(IR_SIR_MODE, IR_CONFIG_1); | |
748 | break; | |
749 | case 38400: | |
750 | writel(2<<10 | 12<<5, IR_WRITE_PHY_CONFIG); | |
751 | writel(IR_SIR_MODE, IR_CONFIG_1); | |
752 | break; | |
753 | case 57600: | |
754 | writel(1<<10 | 12<<5, IR_WRITE_PHY_CONFIG); | |
755 | writel(IR_SIR_MODE, IR_CONFIG_1); | |
756 | break; | |
757 | case 115200: | |
758 | writel(12<<5, IR_WRITE_PHY_CONFIG); | |
759 | writel(IR_SIR_MODE, IR_CONFIG_1); | |
760 | break; | |
761 | case 4000000: | |
762 | writel(0xF, IR_WRITE_PHY_CONFIG); | |
763 | writel(IR_FIR|IR_DMA_ENABLE|IR_RX_ENABLE, IR_CONFIG_1); | |
764 | break; | |
765 | default: | |
766 | printk(KERN_ERR "%s unsupported speed %x\n", dev->name, speed); | |
767 | ret = -EINVAL; | |
768 | break; | |
769 | } | |
770 | ||
771 | aup->speed = speed; | |
772 | writel(read_ir_reg(IR_ENABLE) | 0x8000, IR_ENABLE); | |
773 | au_sync(); | |
774 | ||
775 | control = read_ir_reg(IR_ENABLE); | |
776 | writel(0, IR_RING_PROMPT); | |
777 | au_sync(); | |
778 | ||
779 | if (control & (1<<14)) { | |
780 | printk(KERN_ERR "%s: configuration error\n", dev->name); | |
781 | } | |
782 | else { | |
783 | if (control & (1<<11)) | |
784 | printk(KERN_DEBUG "%s Valid SIR config\n", dev->name); | |
785 | if (control & (1<<12)) | |
786 | printk(KERN_DEBUG "%s Valid MIR config\n", dev->name); | |
787 | if (control & (1<<13)) | |
788 | printk(KERN_DEBUG "%s Valid FIR config\n", dev->name); | |
789 | if (control & (1<<10)) | |
790 | printk(KERN_DEBUG "%s TX enabled\n", dev->name); | |
791 | if (control & (1<<9)) | |
792 | printk(KERN_DEBUG "%s RX enabled\n", dev->name); | |
793 | } | |
794 | ||
795 | spin_unlock_irqrestore(&ir_lock, flags); | |
796 | return ret; | |
797 | } | |
798 | ||
799 | static int | |
800 | au1k_irda_ioctl(struct net_device *dev, struct ifreq *ifreq, int cmd) | |
801 | { | |
802 | struct if_irda_req *rq = (struct if_irda_req *)ifreq; | |
803 | struct au1k_private *aup = netdev_priv(dev); | |
804 | int ret = -EOPNOTSUPP; | |
805 | ||
806 | switch (cmd) { | |
807 | case SIOCSBANDWIDTH: | |
808 | if (capable(CAP_NET_ADMIN)) { | |
809 | /* | |
810 | * We are unable to set the speed if the | |
811 | * device is not running. | |
812 | */ | |
813 | if (aup->open) | |
814 | ret = au1k_irda_set_speed(dev, | |
815 | rq->ifr_baudrate); | |
816 | else { | |
817 | printk(KERN_ERR "%s ioctl: !netif_running\n", | |
818 | dev->name); | |
819 | ret = 0; | |
820 | } | |
821 | } | |
822 | break; | |
823 | ||
824 | case SIOCSMEDIABUSY: | |
825 | ret = -EPERM; | |
826 | if (capable(CAP_NET_ADMIN)) { | |
827 | irda_device_set_media_busy(dev, TRUE); | |
828 | ret = 0; | |
829 | } | |
830 | break; | |
831 | ||
832 | case SIOCGRECEIVING: | |
833 | rq->ifr_receiving = 0; | |
834 | break; | |
835 | default: | |
836 | break; | |
837 | } | |
838 | return ret; | |
839 | } | |
840 | ||
1da177e4 LT |
841 | MODULE_AUTHOR("Pete Popov <ppopov@mvista.com>"); |
842 | MODULE_DESCRIPTION("Au1000 IrDA Device Driver"); | |
843 | ||
844 | module_init(au1k_irda_init); | |
845 | module_exit(au1k_irda_exit); |