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1da177e4 LT |
1 | /********************************************************************* |
2 | * | |
3 | * Filename: toshoboe.h | |
4 | * Version: 2.16 | |
5 | * Description: Driver for the Toshiba OBOE (or type-O or 701) | |
6 | * FIR Chipset, also supports the DONAUOBOE (type-DO | |
7 | * or d01) FIR chipset which as far as I know is | |
8 | * register compatible. | |
9 | * Status: Experimental. | |
10 | * Author: James McKenzie <james@fishsoup.dhs.org> | |
11 | * Created at: Sat May 8 12:35:27 1999 | |
12 | * Modified: 2.16 Martin Lucina <mato@kotelna.sk> | |
13 | * Modified: 2.16 Sat Jun 22 18:54:29 2002 (sync headers) | |
14 | * Modified: 2.17 Christian Gennerat <christian.gennerat@polytechnique.org> | |
15 | * Modified: 2.17 jeu sep 12 08:50:20 2002 (add lock to be used by spinlocks) | |
16 | * | |
17 | * Copyright (c) 1999 James McKenzie, All Rights Reserved. | |
18 | * | |
19 | * This program is free software; you can redistribute it and/or | |
20 | * modify it under the terms of the GNU General Public License as | |
21 | * published by the Free Software Foundation; either version 2 of | |
22 | * the License, or (at your option) any later version. | |
23 | * | |
24 | * Neither James McKenzie nor Cambridge University admit liability nor | |
25 | * provide warranty for any of this software. This material is | |
26 | * provided "AS-IS" and at no charge. | |
27 | * | |
28 | * Applicable Models : Libretto 100/110CT and many more. | |
29 | * Toshiba refers to this chip as the type-O IR port, | |
30 | * or the type-DO IR port. | |
31 | * | |
32 | * IrDA chip set list from Toshiba Computer Engineering Corp. | |
33 | * model method maker controler Version | |
34 | * Portege 320CT FIR,SIR Toshiba Oboe(Triangle) | |
35 | * Portege 3010CT FIR,SIR Toshiba Oboe(Sydney) | |
36 | * Portege 3015CT FIR,SIR Toshiba Oboe(Sydney) | |
37 | * Portege 3020CT FIR,SIR Toshiba Oboe(Sydney) | |
38 | * Portege 7020CT FIR,SIR ? ? | |
39 | * | |
40 | * Satell. 4090XCDT FIR,SIR ? ? | |
41 | * | |
42 | * Libretto 100CT FIR,SIR Toshiba Oboe | |
43 | * Libretto 1000CT FIR,SIR Toshiba Oboe | |
44 | * | |
45 | * TECRA750DVD FIR,SIR Toshiba Oboe(Triangle) REV ID=14h | |
46 | * TECRA780 FIR,SIR Toshiba Oboe(Sandlot) REV ID=32h,33h | |
47 | * TECRA750CDT FIR,SIR Toshiba Oboe(Triangle) REV ID=13h,14h | |
48 | * TECRA8000 FIR,SIR Toshiba Oboe(ISKUR) REV ID=23h | |
49 | * | |
50 | ********************************************************************/ | |
51 | ||
52 | /* The documentation for this chip is allegedly released */ | |
53 | /* However I have not seen it, not have I managed to contact */ | |
54 | /* anyone who has. HOWEVER the chip bears a striking resemblence */ | |
55 | /* to the IrDA controller in the Toshiba RISC TMPR3922 chip */ | |
56 | /* the documentation for this is freely available at */ | |
57 | /* http://www.toshiba.com/taec/components/Generic/TMPR3922.shtml */ | |
58 | /* The mapping between the registers in that document and the */ | |
59 | /* Registers in the 701 oboe chip are as follows */ | |
60 | ||
61 | ||
62 | /* 3922 reg 701 regs, by bit numbers */ | |
63 | /* 7- 0 15- 8 24-16 31-25 */ | |
64 | /* $28 0x0 0x1 */ | |
65 | /* $2c SEE NOTE 1 */ | |
66 | /* $30 0x6 0x7 */ | |
67 | /* $34 0x8 0x9 SEE NOTE 2 */ | |
68 | /* $38 0x10 0x11 */ | |
69 | /* $3C 0xe SEE NOTE 3 */ | |
70 | /* $40 0x12 0x13 */ | |
71 | /* $44 0x14 0x15 */ | |
72 | /* $48 0x16 0x17 */ | |
73 | /* $4c 0x18 0x19 */ | |
74 | /* $50 0x1a 0x1b */ | |
75 | ||
76 | /* FIXME: could be 0x1b 0x1a here */ | |
77 | ||
78 | /* $54 0x1d 0x1c */ | |
79 | /* $5C 0xf SEE NOTE 4 */ | |
80 | /* $130 SEE NOTE 5 */ | |
81 | /* $134 SEE NOTE 6 */ | |
82 | /* */ | |
83 | /* NOTES: */ | |
84 | /* 1. The pointer to ring is packed in most unceremoniusly */ | |
85 | /* 701 Register Address bits (A9-A0 must be zero) */ | |
86 | /* 0x4: A17 A16 A15 A14 A13 A12 A11 A10 */ | |
87 | /* 0x5: A25 A24 A23 A22 A21 A20 A19 A18 */ | |
88 | /* 0x2: 0 0 A31 A30 A29 A28 A27 A26 */ | |
89 | /* */ | |
90 | /* 2. The M$ drivers do a write 0x1 to 0x9, however the 3922 */ | |
91 | /* documentation would suggest that a write of 0x1 to 0x8 */ | |
92 | /* would be more appropriate. */ | |
93 | /* */ | |
94 | /* 3. This assignment is tenuous at best, register 0xe seems to */ | |
95 | /* have bits arranged 0 0 0 R/W R/W R/W R/W R/W */ | |
96 | /* if either of the lower two bits are set the chip seems to */ | |
97 | /* switch off */ | |
98 | /* */ | |
99 | /* 4. Bits 7-4 seem to be different 4 seems just to be generic */ | |
100 | /* receiver busy flag */ | |
101 | /* */ | |
102 | /* 5. and 6. The IER and ISR have a different bit assignment */ | |
103 | /* The lower three bits of both read back as ones */ | |
104 | /* ISR is register 0xc, IER is register 0xd */ | |
105 | /* 7 6 5 4 3 2 1 0 */ | |
106 | /* 0xc: TxDone RxDone TxUndr RxOver SipRcv 1 1 1 */ | |
107 | /* 0xd: TxDone RxDone TxUndr RxOver SipRcv 1 1 1 */ | |
108 | /* TxDone xmitt done (generated only if generate interrupt bit */ | |
109 | /* is set in the ring) */ | |
110 | /* RxDone recv completed (or other recv condition if you set it */ | |
111 | /* up */ | |
112 | /* TxUnder underflow in Transmit FIFO */ | |
113 | /* RxOver overflow in Recv FIFO */ | |
114 | /* SipRcv received serial gap (or other condition you set) */ | |
115 | /* Interrupts are enabled by writing a one to the IER register */ | |
beb7dd86 | 116 | /* Interrupts are cleared by writing a one to the ISR register */ |
1da177e4 LT |
117 | /* */ |
118 | /* 6. The remaining registers: 0x6 and 0x3 appear to be */ | |
119 | /* reserved parts of 16 or 32 bit registersthe remainder */ | |
120 | /* 0xa 0xb 0x1e 0x1f could possibly be (by their behaviour) */ | |
121 | /* the Unicast Filter register at $58. */ | |
122 | /* */ | |
123 | /* 7. While the core obviously expects 32 bit accesses all the */ | |
124 | /* M$ drivers do 8 bit accesses, infact the Miniport ones */ | |
125 | /* write and read back the byte serveral times (why?) */ | |
126 | ||
127 | ||
128 | #ifndef TOSHOBOE_H | |
129 | #define TOSHOBOE_H | |
130 | ||
131 | /* Registers */ | |
132 | ||
133 | #define OBOE_IO_EXTENT 0x1f | |
134 | ||
135 | /*Receive and transmit slot pointers */ | |
136 | #define OBOE_REG(i) (i+(self->base)) | |
137 | #define OBOE_RXSLOT OBOE_REG(0x0) | |
138 | #define OBOE_TXSLOT OBOE_REG(0x1) | |
139 | #define OBOE_SLOT_MASK 0x3f | |
140 | ||
141 | #define OBOE_TXRING_OFFSET 0x200 | |
142 | #define OBOE_TXRING_OFFSET_IN_SLOTS 0x40 | |
143 | ||
144 | /*pointer to the ring */ | |
145 | #define OBOE_RING_BASE0 OBOE_REG(0x4) | |
146 | #define OBOE_RING_BASE1 OBOE_REG(0x5) | |
147 | #define OBOE_RING_BASE2 OBOE_REG(0x2) | |
148 | #define OBOE_RING_BASE3 OBOE_REG(0x3) | |
149 | ||
150 | /*Number of slots in the ring */ | |
151 | #define OBOE_RING_SIZE OBOE_REG(0x7) | |
152 | #define OBOE_RING_SIZE_RX4 0x00 | |
153 | #define OBOE_RING_SIZE_RX8 0x01 | |
154 | #define OBOE_RING_SIZE_RX16 0x03 | |
155 | #define OBOE_RING_SIZE_RX32 0x07 | |
156 | #define OBOE_RING_SIZE_RX64 0x0f | |
157 | #define OBOE_RING_SIZE_TX4 0x00 | |
158 | #define OBOE_RING_SIZE_TX8 0x10 | |
159 | #define OBOE_RING_SIZE_TX16 0x30 | |
160 | #define OBOE_RING_SIZE_TX32 0x70 | |
161 | #define OBOE_RING_SIZE_TX64 0xf0 | |
162 | ||
163 | #define OBOE_RING_MAX_SIZE 64 | |
164 | ||
165 | /*Causes the gubbins to re-examine the ring */ | |
166 | #define OBOE_PROMPT OBOE_REG(0x9) | |
167 | #define OBOE_PROMPT_BIT 0x1 | |
168 | ||
169 | /* Interrupt Status Register */ | |
170 | #define OBOE_ISR OBOE_REG(0xc) | |
171 | /* Interrupt Enable Register */ | |
172 | #define OBOE_IER OBOE_REG(0xd) | |
173 | /* Interrupt bits for IER and ISR */ | |
174 | #define OBOE_INT_TXDONE 0x80 | |
175 | #define OBOE_INT_RXDONE 0x40 | |
176 | #define OBOE_INT_TXUNDER 0x20 | |
177 | #define OBOE_INT_RXOVER 0x10 | |
178 | #define OBOE_INT_SIP 0x08 | |
179 | #define OBOE_INT_MASK 0xf8 | |
180 | ||
181 | /*Reset Register */ | |
182 | #define OBOE_CONFIG1 OBOE_REG(0xe) | |
183 | #define OBOE_CONFIG1_RST 0x01 | |
184 | #define OBOE_CONFIG1_DISABLE 0x02 | |
185 | #define OBOE_CONFIG1_4 0x08 | |
186 | #define OBOE_CONFIG1_8 0x08 | |
187 | ||
188 | #define OBOE_CONFIG1_ON 0x8 | |
189 | #define OBOE_CONFIG1_RESET 0xf | |
190 | #define OBOE_CONFIG1_OFF 0xe | |
191 | ||
192 | #define OBOE_STATUS OBOE_REG(0xf) | |
193 | #define OBOE_STATUS_RXBUSY 0x10 | |
194 | #define OBOE_STATUS_FIRRX 0x04 | |
195 | #define OBOE_STATUS_MIRRX 0x02 | |
196 | #define OBOE_STATUS_SIRRX 0x01 | |
197 | ||
198 | ||
199 | /*Speed control registers */ | |
200 | #define OBOE_CONFIG0L OBOE_REG(0x10) | |
201 | #define OBOE_CONFIG0H OBOE_REG(0x11) | |
202 | ||
203 | #define OBOE_CONFIG0H_TXONLOOP 0x80 /*Transmit when looping (dangerous) */ | |
204 | #define OBOE_CONFIG0H_LOOP 0x40 /*Loopback Tx->Rx */ | |
205 | #define OBOE_CONFIG0H_ENTX 0x10 /*Enable Tx */ | |
206 | #define OBOE_CONFIG0H_ENRX 0x08 /*Enable Rx */ | |
207 | #define OBOE_CONFIG0H_ENDMAC 0x04 /*Enable/reset* the DMA controller */ | |
208 | #define OBOE_CONFIG0H_RCVANY 0x02 /*DMA mode 1=bytes, 0=dwords */ | |
209 | ||
210 | #define OBOE_CONFIG0L_CRC16 0x80 /*CRC 1=16 bit 0=32 bit */ | |
211 | #define OBOE_CONFIG0L_ENFIR 0x40 /*Enable FIR */ | |
212 | #define OBOE_CONFIG0L_ENMIR 0x20 /*Enable MIR */ | |
213 | #define OBOE_CONFIG0L_ENSIR 0x10 /*Enable SIR */ | |
214 | #define OBOE_CONFIG0L_ENSIRF 0x08 /*Enable SIR framer */ | |
215 | #define OBOE_CONFIG0L_SIRTEST 0x04 /*Enable SIR framer in MIR and FIR */ | |
216 | #define OBOE_CONFIG0L_INVERTTX 0x02 /*Invert Tx Line */ | |
217 | #define OBOE_CONFIG0L_INVERTRX 0x01 /*Invert Rx Line */ | |
218 | ||
219 | #define OBOE_BOF OBOE_REG(0x12) | |
220 | #define OBOE_EOF OBOE_REG(0x13) | |
221 | ||
222 | #define OBOE_ENABLEL OBOE_REG(0x14) | |
223 | #define OBOE_ENABLEH OBOE_REG(0x15) | |
224 | ||
225 | #define OBOE_ENABLEH_PHYANDCLOCK 0x80 /*Toggle low to copy config in */ | |
226 | #define OBOE_ENABLEH_CONFIGERR 0x40 | |
227 | #define OBOE_ENABLEH_FIRON 0x20 | |
228 | #define OBOE_ENABLEH_MIRON 0x10 | |
229 | #define OBOE_ENABLEH_SIRON 0x08 | |
230 | #define OBOE_ENABLEH_ENTX 0x04 | |
231 | #define OBOE_ENABLEH_ENRX 0x02 | |
232 | #define OBOE_ENABLEH_CRC16 0x01 | |
233 | ||
234 | #define OBOE_ENABLEL_BROADCAST 0x01 | |
235 | ||
236 | #define OBOE_CURR_PCONFIGL OBOE_REG(0x16) /*Current config */ | |
237 | #define OBOE_CURR_PCONFIGH OBOE_REG(0x17) | |
238 | ||
239 | #define OBOE_NEW_PCONFIGL OBOE_REG(0x18) | |
240 | #define OBOE_NEW_PCONFIGH OBOE_REG(0x19) | |
241 | ||
242 | #define OBOE_PCONFIGH_BAUDMASK 0xfc | |
243 | #define OBOE_PCONFIGH_WIDTHMASK 0x04 | |
244 | #define OBOE_PCONFIGL_WIDTHMASK 0xe0 | |
245 | #define OBOE_PCONFIGL_PREAMBLEMASK 0x1f | |
246 | ||
247 | #define OBOE_PCONFIG_BAUDMASK 0xfc00 | |
248 | #define OBOE_PCONFIG_BAUDSHIFT 10 | |
249 | #define OBOE_PCONFIG_WIDTHMASK 0x04e0 | |
250 | #define OBOE_PCONFIG_WIDTHSHIFT 5 | |
251 | #define OBOE_PCONFIG_PREAMBLEMASK 0x001f | |
252 | #define OBOE_PCONFIG_PREAMBLESHIFT 0 | |
253 | ||
254 | #define OBOE_MAXLENL OBOE_REG(0x1a) | |
255 | #define OBOE_MAXLENH OBOE_REG(0x1b) | |
256 | ||
257 | #define OBOE_RXCOUNTH OBOE_REG(0x1c) /*Reset on recipt */ | |
258 | #define OBOE_RXCOUNTL OBOE_REG(0x1d) /*of whole packet */ | |
259 | ||
260 | /* The PCI ID of the OBOE chip */ | |
261 | #ifndef PCI_DEVICE_ID_FIR701 | |
262 | #define PCI_DEVICE_ID_FIR701 0x0701 | |
263 | #endif | |
264 | ||
265 | #ifndef PCI_DEVICE_ID_FIRD01 | |
266 | #define PCI_DEVICE_ID_FIRD01 0x0d01 | |
267 | #endif | |
268 | ||
269 | struct OboeSlot | |
270 | { | |
271 | __u16 len; /*Tweleve bits of packet length */ | |
272 | __u8 unused; | |
273 | __u8 control; /*Slot control/status see below */ | |
274 | __u32 address; /*Slot buffer address */ | |
275 | } | |
276 | __attribute__ ((packed)); | |
277 | ||
278 | #define OBOE_NTASKS OBOE_TXRING_OFFSET_IN_SLOTS | |
279 | ||
280 | struct OboeRing | |
281 | { | |
282 | struct OboeSlot rx[OBOE_NTASKS]; | |
283 | struct OboeSlot tx[OBOE_NTASKS]; | |
284 | }; | |
285 | ||
286 | #define OBOE_RING_LEN (sizeof(struct OboeRing)) | |
287 | ||
288 | ||
289 | #define OBOE_CTL_TX_HW_OWNS 0x80 /*W/R This slot owned by the hardware */ | |
290 | #define OBOE_CTL_TX_DISTX_CRC 0x40 /*W Disable CRC generation for [FM]IR */ | |
291 | #define OBOE_CTL_TX_BAD_CRC 0x20 /*W Generate bad CRC */ | |
292 | #define OBOE_CTL_TX_SIP 0x10 /*W Generate an SIP after xmittion */ | |
293 | #define OBOE_CTL_TX_MKUNDER 0x08 /*W Generate an underrun error */ | |
294 | #define OBOE_CTL_TX_RTCENTX 0x04 /*W Enable receiver and generate TXdone */ | |
295 | /* After this slot is processed */ | |
296 | #define OBOE_CTL_TX_UNDER 0x01 /*R Set by hardware to indicate underrun */ | |
297 | ||
298 | ||
299 | #define OBOE_CTL_RX_HW_OWNS 0x80 /*W/R This slot owned by hardware */ | |
300 | #define OBOE_CTL_RX_PHYERR 0x40 /*R Decoder error on receiption */ | |
301 | #define OBOE_CTL_RX_CRCERR 0x20 /*R CRC error only set for [FM]IR */ | |
302 | #define OBOE_CTL_RX_LENGTH 0x10 /*R Packet > max Rx length */ | |
303 | #define OBOE_CTL_RX_OVER 0x08 /*R set to indicate an overflow */ | |
304 | #define OBOE_CTL_RX_SIRBAD 0x04 /*R SIR had BOF in packet or ABORT sequence */ | |
305 | #define OBOE_CTL_RX_RXEOF 0x02 /*R Finished receiving on this slot */ | |
306 | ||
307 | ||
308 | struct toshoboe_cb | |
309 | { | |
310 | struct net_device *netdev; /* Yes! we are some kind of netdevice */ | |
311 | struct net_device_stats stats; | |
312 | struct tty_driver ttydev; | |
313 | ||
314 | struct irlap_cb *irlap; /* The link layer we are binded to */ | |
315 | ||
316 | chipio_t io; /* IrDA controller information */ | |
317 | struct qos_info qos; /* QoS capabilities for this device */ | |
318 | ||
319 | __u32 flags; /* Interface flags */ | |
320 | ||
321 | struct pci_dev *pdev; /*PCI device */ | |
322 | int base; /*IO base */ | |
323 | ||
324 | ||
325 | int txpending; /*how many tx's are pending */ | |
326 | int txs, rxs; /*Which slots are we at */ | |
327 | ||
328 | int irdad; /*Driver under control of netdev end */ | |
329 | int async; /*Driver under control of async end */ | |
330 | ||
331 | ||
332 | int stopped; /*Stopped by some or other APM stuff */ | |
333 | ||
334 | int filter; /*In SIR mode do we want to receive | |
335 | frames or byte ranges */ | |
336 | ||
337 | void *ringbuf; /*The ring buffer */ | |
338 | struct OboeRing *ring; /*The ring */ | |
339 | ||
340 | void *tx_bufs[OBOE_RING_MAX_SIZE]; /*The buffers */ | |
341 | void *rx_bufs[OBOE_RING_MAX_SIZE]; | |
342 | ||
343 | ||
344 | int speed; /*Current setting of the speed */ | |
345 | int new_speed; /*Set to request a speed change */ | |
346 | ||
347 | /* The spinlock protect critical parts of the driver. | |
348 | * Locking is done like this : | |
349 | * spin_lock_irqsave(&self->spinlock, flags); | |
350 | * Releasing the lock : | |
351 | * spin_unlock_irqrestore(&self->spinlock, flags); | |
352 | */ | |
353 | spinlock_t spinlock; | |
354 | /* Used for the probe and diagnostics code */ | |
355 | int int_rx; | |
356 | int int_tx; | |
357 | int int_txunder; | |
358 | int int_rxover; | |
359 | int int_sip; | |
360 | }; | |
361 | ||
362 | ||
363 | #endif |