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[mirror_ubuntu-hirsute-kernel.git] / drivers / net / irda / smsc-ircc2.c
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1da177e4 1/*********************************************************************
1da177e4
LT		 2 *
3 * Description: Driver for the SMC Infrared Communications Controller
4 * Status: Experimental.
5 * Author: Daniele Peri (peri@csai.unipa.it)
527b6af4
DT		 6 * Created at:
7 * Modified at:
8 * Modified by:
9 *
1da177e4
LT		 10 * Copyright (c) 2002 Daniele Peri
11 * All Rights Reserved.
12 * Copyright (c) 2002 Jean Tourrilhes
c1e14a6e 13 * Copyright (c) 2006 Linus Walleij
1da177e4
LT		 14 *
15 *
16 * Based on smc-ircc.c:
17 *
18 * Copyright (c) 2001 Stefani Seibold
19 * Copyright (c) 1999-2001 Dag Brattli
527b6af4 20 * Copyright (c) 1998-1999 Thomas Davis,
1da177e4
LT		 21 *
22 * and irport.c:
23 *
24 * Copyright (c) 1997, 1998, 1999-2000 Dag Brattli, All Rights Reserved.
25 *
527b6af4
DT		 26 *
27 * This program is free software; you can redistribute it and/or
28 * modify it under the terms of the GNU General Public License as
29 * published by the Free Software Foundation; either version 2 of
1da177e4 30 * the License, or (at your option) any later version.
527b6af4 31 *
1da177e4
LT		 32 * This program is distributed in the hope that it will be useful,
33 * but WITHOUT ANY WARRANTY; without even the implied warranty of
34 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
35 * GNU General Public License for more details.
527b6af4
DT		 36 *
37 * You should have received a copy of the GNU General Public License
38 * along with this program; if not, write to the Free Software
39 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
1da177e4
LT		 40 * MA 02111-1307 USA
41 *
42 ********************************************************************/
43
44#include <linux/module.h>
45#include <linux/kernel.h>
46#include <linux/types.h>
47#include <linux/skbuff.h>
48#include <linux/netdevice.h>
49#include <linux/ioport.h>
50#include <linux/delay.h>
1da177e4 51#include <linux/init.h>
a6b7a407 52#include <linux/interrupt.h>
1da177e4
LT		 53#include <linux/rtnetlink.h>
54#include <linux/serial_reg.h>
55#include <linux/dma-mapping.h>
d94c77b9 56#include <linux/pnp.h>
d052d1be 57#include <linux/platform_device.h>
5a0e3ad6 58#include <linux/gfp.h>
1da177e4
LT		 59
60#include <asm/io.h>
61#include <asm/dma.h>
62#include <asm/byteorder.h>
63
64#include <linux/spinlock.h>
65#include <linux/pm.h>
c1e14a6e
LW		 66#ifdef CONFIG_PCI
67#include <linux/pci.h>
68#endif
1da177e4
LT		 69
70#include <net/irda/wrapper.h>
71#include <net/irda/irda.h>
72#include <net/irda/irda_device.h>
73
74#include "smsc-ircc2.h"
75#include "smsc-sio.h"
76
98b77773
DT		 77
78MODULE_AUTHOR("Daniele Peri <peri@csai.unipa.it>");
79MODULE_DESCRIPTION("SMC IrCC SIR/FIR controller driver");
80MODULE_LICENSE("GPL");
81
cbcdd772 82static int smsc_nopnp = 1;
d0d4f69b 83module_param_named(nopnp, smsc_nopnp, bool, 0);
32db9276 84MODULE_PARM_DESC(nopnp, "Do not use PNP to detect controller settings, defaults to true");
d0d4f69b 85
916f11c7
BH		 86#define DMA_INVAL 255
87static int ircc_dma = DMA_INVAL;
98b77773
DT		 88module_param(ircc_dma, int, 0);
89MODULE_PARM_DESC(ircc_dma, "DMA channel");
90
916f11c7
BH		 91#define IRQ_INVAL 255
92static int ircc_irq = IRQ_INVAL;
98b77773
DT		 93module_param(ircc_irq, int, 0);
94MODULE_PARM_DESC(ircc_irq, "IRQ line");
95
96static int ircc_fir;
97module_param(ircc_fir, int, 0);
98MODULE_PARM_DESC(ircc_fir, "FIR Base Address");
99
100static int ircc_sir;
101module_param(ircc_sir, int, 0);
102MODULE_PARM_DESC(ircc_sir, "SIR Base Address");
103
104static int ircc_cfg;
105module_param(ircc_cfg, int, 0);
106MODULE_PARM_DESC(ircc_cfg, "Configuration register base address");
107
108static int ircc_transceiver;
109module_param(ircc_transceiver, int, 0);
110MODULE_PARM_DESC(ircc_transceiver, "Transceiver type");
111
1da177e4
LT		 112/* Types */
113
c1e14a6e
LW		 114#ifdef CONFIG_PCI
115struct smsc_ircc_subsystem_configuration {
116 unsigned short vendor; /* PCI vendor ID */
117 unsigned short device; /* PCI vendor ID */
118 unsigned short subvendor; /* PCI subsystem vendor ID */
83cf0a9b 119 unsigned short subdevice; /* PCI subsystem device ID */
c1e14a6e
LW		 120 unsigned short sir_io; /* I/O port for SIR */
121 unsigned short fir_io; /* I/O port for FIR */
122 unsigned char fir_irq; /* FIR IRQ */
123 unsigned char fir_dma; /* FIR DMA */
124 unsigned short cfg_base; /* I/O port for chip configuration */
125 int (*preconfigure)(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf); /* Preconfig function */
126 const char *name; /* name shown as info */
127};
128#endif
129
1da177e4
LT		 130struct smsc_transceiver {
131 char *name;
527b6af4 132 void (*set_for_speed)(int fir_base, u32 speed);
1da177e4
LT		 133 int (*probe)(int fir_base);
134};
1da177e4
LT		 135
136struct smsc_chip {
137 char *name;
138 #if 0
139 u8 type;
140 #endif
141 u16 flags;
142 u8 devid;
143 u8 rev;
144};
1da177e4
LT		 145
146struct smsc_chip_address {
147 unsigned int cfg_base;
148 unsigned int type;
149};
1da177e4
LT		 150
151/* Private data for each instance */
152struct smsc_ircc_cb {
153 struct net_device *netdev; /* Yes! we are some kind of netdevice */
1da177e4 154 struct irlap_cb *irlap; /* The link layer we are binded to */
527b6af4 155
1da177e4
LT		 156 chipio_t io; /* IrDA controller information */
157 iobuff_t tx_buff; /* Transmit buffer */
158 iobuff_t rx_buff; /* Receive buffer */
159 dma_addr_t tx_buff_dma;
160 dma_addr_t rx_buff_dma;
161
162 struct qos_info qos; /* QoS capabilities for this device */
163
164 spinlock_t lock; /* For serializing operations */
527b6af4 165
1da177e4
LT		 166 __u32 new_speed;
167 __u32 flags; /* Interface flags */
168
169 int tx_buff_offsets[10]; /* Offsets between frames in tx_buff */
170 int tx_len; /* Number of frames in tx_buff */
171
172 int transceiver;
6bb3b2cd 173 struct platform_device *pldev;
1da177e4
LT		 174};
175
176/* Constants */
177
6bb3b2cd
DT		 178#define SMSC_IRCC2_DRIVER_NAME "smsc-ircc2"
179
1da177e4
LT		 180#define SMSC_IRCC2_C_IRDA_FALLBACK_SPEED 9600
181#define SMSC_IRCC2_C_DEFAULT_TRANSCEIVER 1
98b77773 182#define SMSC_IRCC2_C_NET_TIMEOUT 0
1da177e4
LT		 183#define SMSC_IRCC2_C_SIR_STOP 0
184
6bb3b2cd
DT		 185static const char *driver_name = SMSC_IRCC2_DRIVER_NAME;
186
1da177e4
LT		 187/* Prototypes */
188
189static int smsc_ircc_open(unsigned int firbase, unsigned int sirbase, u8 dma, u8 irq);
190static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base);
191static void smsc_ircc_setup_io(struct smsc_ircc_cb *self, unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq);
192static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self);
193static void smsc_ircc_init_chip(struct smsc_ircc_cb *self);
194static int __exit smsc_ircc_close(struct smsc_ircc_cb *self);
80a90589
DT		 195static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self);
196static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self);
1da177e4 197static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self);
6518bbb8
SH		 198static netdev_tx_t smsc_ircc_hard_xmit_sir(struct sk_buff *skb,
199 struct net_device *dev);
200static netdev_tx_t smsc_ircc_hard_xmit_fir(struct sk_buff *skb,
201 struct net_device *dev);
80a90589
DT		 202static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int bofs);
203static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self);
0fa2f491
DT		 204static void smsc_ircc_change_speed(struct smsc_ircc_cb *self, u32 speed);
205static void smsc_ircc_set_sir_speed(struct smsc_ircc_cb *self, u32 speed);
7d12e780 206static irqreturn_t smsc_ircc_interrupt(int irq, void *dev_id);
1da177e4
LT		 207static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev);
208static void smsc_ircc_sir_start(struct smsc_ircc_cb *self);
209#if SMSC_IRCC2_C_SIR_STOP
210static void smsc_ircc_sir_stop(struct smsc_ircc_cb *self);
211#endif
212static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self);
213static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len);
214static int smsc_ircc_net_open(struct net_device *dev);
215static int smsc_ircc_net_close(struct net_device *dev);
216static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
217#if SMSC_IRCC2_C_NET_TIMEOUT
218static void smsc_ircc_timeout(struct net_device *dev);
219#endif
1da177e4
LT		 220static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self);
221static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self);
222static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed);
223static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self);
224
225/* Probing */
948252cb
DM		 226static int __init smsc_ircc_look_for_chips(void);
227static const struct smsc_chip * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const struct smsc_chip *chip, char *type);
228static int __init smsc_superio_flat(const struct smsc_chip *chips, unsigned short cfg_base, char *type);
229static int __init smsc_superio_paged(const struct smsc_chip *chips, unsigned short cfg_base, char *type);
230static int __init smsc_superio_fdc(unsigned short cfg_base);
231static int __init smsc_superio_lpc(unsigned short cfg_base);
c1e14a6e 232#ifdef CONFIG_PCI
948252cb
DM		 233static int __init preconfigure_smsc_chip(struct smsc_ircc_subsystem_configuration *conf);
234static int __init preconfigure_through_82801(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf);
235static void __init preconfigure_ali_port(struct pci_dev *dev,
08d09997 236 unsigned short port);
948252cb
DM		 237static int __init preconfigure_through_ali(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf);
238static int __init smsc_ircc_preconfigure_subsystems(unsigned short ircc_cfg,
c1e14a6e
LW		 239 unsigned short ircc_fir,
240 unsigned short ircc_sir,
241 unsigned char ircc_dma,
242 unsigned char ircc_irq);
243#endif
1da177e4
LT		 244
245/* Transceivers specific functions */
246
247static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed);
248static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base);
249static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed);
250static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base);
251static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed);
252static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base);
253
254/* Power Management */
255
3ae5eaec
RK		 256static int smsc_ircc_suspend(struct platform_device *dev, pm_message_t state);
257static int smsc_ircc_resume(struct platform_device *dev);
1da177e4 258
3ae5eaec 259static struct platform_driver smsc_ircc_driver = {
6bb3b2cd
DT		 260 .suspend = smsc_ircc_suspend,
261 .resume = smsc_ircc_resume,
3ae5eaec
RK		 262 .driver = {
263 .name = SMSC_IRCC2_DRIVER_NAME,
264 },
6bb3b2cd 265};
1da177e4
LT		 266
267/* Transceivers for SMSC-ircc */
268
b6158d23 269static struct smsc_transceiver smsc_transceivers[] =
1da177e4 270{
98b77773
DT		 271 { "Toshiba Satellite 1800 (GP data pin select)", smsc_ircc_set_transceiver_toshiba_sat1800, smsc_ircc_probe_transceiver_toshiba_sat1800 },
272 { "Fast pin select", smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select, smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select },
273 { "ATC IRMode", smsc_ircc_set_transceiver_smsc_ircc_atc, smsc_ircc_probe_transceiver_smsc_ircc_atc },
274 { NULL, NULL }
1da177e4 275};
a956f4ca 276#define SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS (ARRAY_SIZE(smsc_transceivers) - 1)
1da177e4
LT		 277
278/* SMC SuperIO chipsets definitions */
279
280#define KEY55_1 0 /* SuperIO Configuration mode with Key <0x55> */
281#define KEY55_2 1 /* SuperIO Configuration mode with Key <0x55,0x55> */
282#define NoIRDA 2 /* SuperIO Chip has no IRDA Port */
283#define SIR 0 /* SuperIO Chip has only slow IRDA */
284#define FIR 4 /* SuperIO Chip has fast IRDA */
285#define SERx4 8 /* SuperIO Chip supports 115,2 KBaud * 4=460,8 KBaud */
286
b6158d23 287static struct smsc_chip __initdata fdc_chips_flat[] =
1da177e4
LT		 288{
289 /* Base address 0x3f0 or 0x370 */
290 { "37C44", KEY55_1|NoIRDA, 0x00, 0x00 }, /* This chip cannot be detected */
291 { "37C665GT", KEY55_2|NoIRDA, 0x65, 0x01 },
292 { "37C665GT", KEY55_2|NoIRDA, 0x66, 0x01 },
293 { "37C669", KEY55_2|SIR|SERx4, 0x03, 0x02 },
294 { "37C669", KEY55_2|SIR|SERx4, 0x04, 0x02 }, /* ID? */
295 { "37C78", KEY55_2|NoIRDA, 0x78, 0x00 },
296 { "37N769", KEY55_1|FIR|SERx4, 0x28, 0x00 },
297 { "37N869", KEY55_1|FIR|SERx4, 0x29, 0x00 },
298 { NULL }
299};
300
b6158d23 301static struct smsc_chip __initdata fdc_chips_paged[] =
1da177e4
LT		 302{
303 /* Base address 0x3f0 or 0x370 */
304 { "37B72X", KEY55_1|SIR|SERx4, 0x4c, 0x00 },
305 { "37B77X", KEY55_1|SIR|SERx4, 0x43, 0x00 },
306 { "37B78X", KEY55_1|SIR|SERx4, 0x44, 0x00 },
307 { "37B80X", KEY55_1|SIR|SERx4, 0x42, 0x00 },
308 { "37C67X", KEY55_1|FIR|SERx4, 0x40, 0x00 },
309 { "37C93X", KEY55_2|SIR|SERx4, 0x02, 0x01 },
310 { "37C93XAPM", KEY55_1|SIR|SERx4, 0x30, 0x01 },
311 { "37C93XFR", KEY55_2|FIR|SERx4, 0x03, 0x01 },
312 { "37M707", KEY55_1|SIR|SERx4, 0x42, 0x00 },
313 { "37M81X", KEY55_1|SIR|SERx4, 0x4d, 0x00 },
314 { "37N958FR", KEY55_1|FIR|SERx4, 0x09, 0x04 },
315 { "37N971", KEY55_1|FIR|SERx4, 0x0a, 0x00 },
316 { "37N972", KEY55_1|FIR|SERx4, 0x0b, 0x00 },
317 { NULL }
318};
319
b6158d23 320static struct smsc_chip __initdata lpc_chips_flat[] =
1da177e4
LT		 321{
322 /* Base address 0x2E or 0x4E */
323 { "47N227", KEY55_1|FIR|SERx4, 0x5a, 0x00 },
afdf27c9 324 { "47N227", KEY55_1|FIR|SERx4, 0x7a, 0x00 },
1da177e4
LT		 325 { "47N267", KEY55_1|FIR|SERx4, 0x5e, 0x00 },
326 { NULL }
327};
328
b6158d23 329static struct smsc_chip __initdata lpc_chips_paged[] =
1da177e4
LT		 330{
331 /* Base address 0x2E or 0x4E */
332 { "47B27X", KEY55_1|SIR|SERx4, 0x51, 0x00 },
333 { "47B37X", KEY55_1|SIR|SERx4, 0x52, 0x00 },
334 { "47M10X", KEY55_1|SIR|SERx4, 0x59, 0x00 },
335 { "47M120", KEY55_1|NoIRDA|SERx4, 0x5c, 0x00 },
336 { "47M13X", KEY55_1|SIR|SERx4, 0x59, 0x00 },
337 { "47M14X", KEY55_1|SIR|SERx4, 0x5f, 0x00 },
338 { "47N252", KEY55_1|FIR|SERx4, 0x0e, 0x00 },
339 { "47S42X", KEY55_1|SIR|SERx4, 0x57, 0x00 },
340 { NULL }
341};
342
343#define SMSCSIO_TYPE_FDC 1
344#define SMSCSIO_TYPE_LPC 2
345#define SMSCSIO_TYPE_FLAT 4
346#define SMSCSIO_TYPE_PAGED 8
347
b6158d23 348static struct smsc_chip_address __initdata possible_addresses[] =
1da177e4 349{
98b77773
DT		 350 { 0x3f0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
351 { 0x370, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
352 { 0xe0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
353 { 0x2e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
354 { 0x4e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
355 { 0, 0 }
1da177e4
LT		 356};
357
358/* Globals */
359
98b77773
DT		 360static struct smsc_ircc_cb *dev_self[] = { NULL, NULL };
361static unsigned short dev_count;
1da177e4
LT		 362
363static inline void register_bank(int iobase, int bank)
364{
98b77773
DT		 365 outb(((inb(iobase + IRCC_MASTER) & 0xf0) | (bank & 0x07)),
366 iobase + IRCC_MASTER);
1da177e4
LT		 367}
368
d94c77b9 369/* PNP hotplug support */
948252cb 370static const struct pnp_device_id smsc_ircc_pnp_table[] = {
d94c77b9
DB		 371 { .id = "SMCf010", .driver_data = 0 },
372 /* and presumably others */
373 { }
374};
375MODULE_DEVICE_TABLE(pnp, smsc_ircc_pnp_table);
d0d4f69b
BH		 376
377static int pnp_driver_registered;
378
7a1aa309 379#ifdef CONFIG_PNP
1170bed0 380static int __devinit smsc_ircc_pnp_probe(struct pnp_dev *dev,
d0d4f69b
BH		 381 const struct pnp_device_id *dev_id)
382{
383 unsigned int firbase, sirbase;
384 u8 dma, irq;
385
386 if (!(pnp_port_valid(dev, 0) && pnp_port_valid(dev, 1) &&
387 pnp_dma_valid(dev, 0) && pnp_irq_valid(dev, 0)))
388 return -EINVAL;
389
390 sirbase = pnp_port_start(dev, 0);
391 firbase = pnp_port_start(dev, 1);
392 dma = pnp_dma(dev, 0);
393 irq = pnp_irq(dev, 0);
394
395 if (smsc_ircc_open(firbase, sirbase, dma, irq))
396 return -ENODEV;
397
398 return 0;
399}
400
401static struct pnp_driver smsc_ircc_pnp_driver = {
402 .name = "smsc-ircc2",
403 .id_table = smsc_ircc_pnp_table,
404 .probe = smsc_ircc_pnp_probe,
405};
7a1aa309
IM		 406#else /* CONFIG_PNP */
407static struct pnp_driver smsc_ircc_pnp_driver;
408#endif
1da177e4
LT		 409
410/*******************************************************************************
411 *
412 *
413 * SMSC-ircc stuff
414 *
415 *
416 *******************************************************************************/
417
d0d4f69b
BH		 418static int __init smsc_ircc_legacy_probe(void)
419{
420 int ret = 0;
421
7c31d2f5
BH		 422#ifdef CONFIG_PCI
423 if (smsc_ircc_preconfigure_subsystems(ircc_cfg, ircc_fir, ircc_sir, ircc_dma, ircc_irq) < 0) {
424 /* Ignore errors from preconfiguration */
425 IRDA_ERROR("%s, Preconfiguration failed !\n", driver_name);
426 }
427#endif
428
d0d4f69b
BH		 429 if (ircc_fir > 0 && ircc_sir > 0) {
430 IRDA_MESSAGE(" Overriding FIR address 0x%04x\n", ircc_fir);
431 IRDA_MESSAGE(" Overriding SIR address 0x%04x\n", ircc_sir);
432
433 if (smsc_ircc_open(ircc_fir, ircc_sir, ircc_dma, ircc_irq))
434 ret = -ENODEV;
435 } else {
436 ret = -ENODEV;
437
438 /* try user provided configuration register base address */
439 if (ircc_cfg > 0) {
440 IRDA_MESSAGE(" Overriding configuration address "
441 "0x%04x\n", ircc_cfg);
442 if (!smsc_superio_fdc(ircc_cfg))
443 ret = 0;
444 if (!smsc_superio_lpc(ircc_cfg))
445 ret = 0;
446 }
447
448 if (smsc_ircc_look_for_chips() > 0)
449 ret = 0;
450 }
451 return ret;
452}
453
1da177e4
LT		 454/*
455 * Function smsc_ircc_init ()
456 *
457 * Initialize chip. Just try to find out how many chips we are dealing with
458 * and where they are
459 */
460static int __init smsc_ircc_init(void)
461{
6bb3b2cd 462 int ret;
1da177e4 463
a97a6f10 464 IRDA_DEBUG(1, "%s\n", __func__);
1da177e4 465
3ae5eaec 466 ret = platform_driver_register(&smsc_ircc_driver);
6bb3b2cd
DT		 467 if (ret) {
468 IRDA_ERROR("%s, Can't register driver!\n", driver_name);
469 return ret;
470 }
471
98b77773 472 dev_count = 0;
527b6af4 473
d0d4f69b
BH		 474 if (smsc_nopnp || !pnp_platform_devices ||
475 ircc_cfg || ircc_fir || ircc_sir ||
476 ircc_dma != DMA_INVAL || ircc_irq != IRQ_INVAL) {
477 ret = smsc_ircc_legacy_probe();
6bb3b2cd 478 } else {
d0d4f69b
BH		 479 if (pnp_register_driver(&smsc_ircc_pnp_driver) == 0)
480 pnp_driver_registered = 1;
1da177e4 481 }
527b6af4 482
d0d4f69b
BH		 483 if (ret) {
484 if (pnp_driver_registered)
485 pnp_unregister_driver(&smsc_ircc_pnp_driver);
3ae5eaec 486 platform_driver_unregister(&smsc_ircc_driver);
d0d4f69b 487 }
527b6af4 488
1da177e4
LT		 489 return ret;
490}
491
6518bbb8
SH		 492static netdev_tx_t smsc_ircc_net_xmit(struct sk_buff *skb,
493 struct net_device *dev)
02087be6
SH		 494{
495 struct smsc_ircc_cb *self = netdev_priv(dev);
496
497 if (self->io.speed > 115200)
498 return smsc_ircc_hard_xmit_fir(skb, dev);
499 else
500 return smsc_ircc_hard_xmit_sir(skb, dev);
501}
502
503static const struct net_device_ops smsc_ircc_netdev_ops = {
504 .ndo_open = smsc_ircc_net_open,
505 .ndo_stop = smsc_ircc_net_close,
506 .ndo_do_ioctl = smsc_ircc_net_ioctl,
507 .ndo_start_xmit = smsc_ircc_net_xmit,
508#if SMSC_IRCC2_C_NET_TIMEOUT
509 .ndo_tx_timeout = smsc_ircc_timeout,
510#endif
511};
512
1da177e4
LT		 513/*
514 * Function smsc_ircc_open (firbase, sirbase, dma, irq)
515 *
516 * Try to open driver instance
517 *
518 */
f470e5ae 519static int __devinit smsc_ircc_open(unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq)
1da177e4
LT		 520{
521 struct smsc_ircc_cb *self;
522 struct net_device *dev;
523 int err;
527b6af4 524
a97a6f10 525 IRDA_DEBUG(1, "%s\n", __func__);
1da177e4
LT		 526
527 err = smsc_ircc_present(fir_base, sir_base);
98b77773 528 if (err)
1da177e4 529 goto err_out;
527b6af4 530
1da177e4 531 err = -ENOMEM;
a956f4ca 532 if (dev_count >= ARRAY_SIZE(dev_self)) {
a97a6f10 533 IRDA_WARNING("%s(), too many devices!\n", __func__);
1da177e4
LT		 534 goto err_out1;
535 }
536
537 /*
538 * Allocate new instance of the driver
539 */
540 dev = alloc_irdadev(sizeof(struct smsc_ircc_cb));
541 if (!dev) {
a97a6f10 542 IRDA_WARNING("%s() can't allocate net device\n", __func__);
1da177e4
LT		 543 goto err_out1;
544 }
545
1da177e4 546#if SMSC_IRCC2_C_NET_TIMEOUT
98b77773 547 dev->watchdog_timeo = HZ * 2; /* Allow enough time for speed change */
1da177e4 548#endif
02087be6 549 dev->netdev_ops = &smsc_ircc_netdev_ops;
527b6af4 550
da0841a0 551 self = netdev_priv(dev);
1da177e4
LT		 552 self->netdev = dev;
553
554 /* Make ifconfig display some details */
555 dev->base_addr = self->io.fir_base = fir_base;
556 dev->irq = self->io.irq = irq;
557
558 /* Need to store self somewhere */
6bb3b2cd 559 dev_self[dev_count] = self;
1da177e4
LT		 560 spin_lock_init(&self->lock);
561
527b6af4 562 self->rx_buff.truesize = SMSC_IRCC2_RX_BUFF_TRUESIZE;
1da177e4
LT		 563 self->tx_buff.truesize = SMSC_IRCC2_TX_BUFF_TRUESIZE;
564
565 self->rx_buff.head =
566 dma_alloc_coherent(NULL, self->rx_buff.truesize,
567 &self->rx_buff_dma, GFP_KERNEL);
568 if (self->rx_buff.head == NULL) {
569 IRDA_ERROR("%s, Can't allocate memory for receive buffer!\n",
570 driver_name);
571 goto err_out2;
572 }
573
574 self->tx_buff.head =
575 dma_alloc_coherent(NULL, self->tx_buff.truesize,
576 &self->tx_buff_dma, GFP_KERNEL);
577 if (self->tx_buff.head == NULL) {
578 IRDA_ERROR("%s, Can't allocate memory for transmit buffer!\n",
579 driver_name);
580 goto err_out3;
581 }
582
583 memset(self->rx_buff.head, 0, self->rx_buff.truesize);
584 memset(self->tx_buff.head, 0, self->tx_buff.truesize);
585
586 self->rx_buff.in_frame = FALSE;
587 self->rx_buff.state = OUTSIDE_FRAME;
588 self->tx_buff.data = self->tx_buff.head;
589 self->rx_buff.data = self->rx_buff.head;
527b6af4 590
1da177e4 591 smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq);
1da177e4 592 smsc_ircc_setup_qos(self);
1da177e4 593 smsc_ircc_init_chip(self);
527b6af4 594
98b77773
DT		 595 if (ircc_transceiver > 0 &&
596 ircc_transceiver < SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS)
1da177e4
LT		 597 self->transceiver = ircc_transceiver;
598 else
599 smsc_ircc_probe_transceiver(self);
600
601 err = register_netdev(self->netdev);
98b77773 602 if (err) {
1da177e4
LT		 603 IRDA_ERROR("%s, Network device registration failed!\n",
604 driver_name);
605 goto err_out4;
606 }
607
6bb3b2cd
DT		 608 self->pldev = platform_device_register_simple(SMSC_IRCC2_DRIVER_NAME,
609 dev_count, NULL, 0);
610 if (IS_ERR(self->pldev)) {
611 err = PTR_ERR(self->pldev);
612 goto err_out5;
613 }
3ae5eaec 614 platform_set_drvdata(self->pldev, self);
1da177e4
LT		 615
616 IRDA_MESSAGE("IrDA: Registered device %s\n", dev->name);
6bb3b2cd 617 dev_count++;
1da177e4
LT		 618
619 return 0;
98b77773 620
6bb3b2cd
DT		 621 err_out5:
622 unregister_netdev(self->netdev);
623
1da177e4
LT		 624 err_out4:
625 dma_free_coherent(NULL, self->tx_buff.truesize,
626 self->tx_buff.head, self->tx_buff_dma);
627 err_out3:
628 dma_free_coherent(NULL, self->rx_buff.truesize,
629 self->rx_buff.head, self->rx_buff_dma);
630 err_out2:
631 free_netdev(self->netdev);
6bb3b2cd 632 dev_self[dev_count] = NULL;
1da177e4
LT		 633 err_out1:
634 release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT);
635 release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT);
636 err_out:
637 return err;
638}
639
640/*
641 * Function smsc_ircc_present(fir_base, sir_base)
642 *
643 * Check the smsc-ircc chip presence
644 *
645 */
646static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base)
647{
648 unsigned char low, high, chip, config, dma, irq, version;
649
650 if (!request_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT,
651 driver_name)) {
652 IRDA_WARNING("%s: can't get fir_base of 0x%03x\n",
a97a6f10 653 __func__, fir_base);
1da177e4
LT		 654 goto out1;
655 }
656
657 if (!request_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT,
658 driver_name)) {
659 IRDA_WARNING("%s: can't get sir_base of 0x%03x\n",
a97a6f10 660 __func__, sir_base);
1da177e4
LT		 661 goto out2;
662 }
663
664 register_bank(fir_base, 3);
665
98b77773
DT		 666 high = inb(fir_base + IRCC_ID_HIGH);
667 low = inb(fir_base + IRCC_ID_LOW);
668 chip = inb(fir_base + IRCC_CHIP_ID);
669 version = inb(fir_base + IRCC_VERSION);
670 config = inb(fir_base + IRCC_INTERFACE);
1da177e4
LT		 671 dma = config & IRCC_INTERFACE_DMA_MASK;
672 irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4;
673
527b6af4 674 if (high != 0x10 || low != 0xb8 || (chip != 0xf1 && chip != 0xf2)) {
98b77773 675 IRDA_WARNING("%s(), addr 0x%04x - no device found!\n",
a97a6f10 676 __func__, fir_base);
1da177e4
LT		 677 goto out3;
678 }
679 IRDA_MESSAGE("SMsC IrDA Controller found\n IrCC version %d.%d, "
680 "firport 0x%03x, sirport 0x%03x dma=%d, irq=%d\n",
681 chip & 0x0f, version, fir_base, sir_base, dma, irq);
682
683 return 0;
98b77773 684
1da177e4
LT		 685 out3:
686 release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT);
687 out2:
688 release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT);
689 out1:
690 return -ENODEV;
691}
692
693/*
694 * Function smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq)
695 *
696 * Setup I/O
697 *
698 */
527b6af4
DT		 699static void smsc_ircc_setup_io(struct smsc_ircc_cb *self,
700 unsigned int fir_base, unsigned int sir_base,
1da177e4
LT		 701 u8 dma, u8 irq)
702{
703 unsigned char config, chip_dma, chip_irq;
704
705 register_bank(fir_base, 3);
98b77773
DT		 706 config = inb(fir_base + IRCC_INTERFACE);
707 chip_dma = config & IRCC_INTERFACE_DMA_MASK;
708 chip_irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4;
1da177e4
LT		 709
710 self->io.fir_base = fir_base;
711 self->io.sir_base = sir_base;
712 self->io.fir_ext = SMSC_IRCC2_FIR_CHIP_IO_EXTENT;
713 self->io.sir_ext = SMSC_IRCC2_SIR_CHIP_IO_EXTENT;
714 self->io.fifo_size = SMSC_IRCC2_FIFO_SIZE;
715 self->io.speed = SMSC_IRCC2_C_IRDA_FALLBACK_SPEED;
716
916f11c7 717 if (irq != IRQ_INVAL) {
1da177e4
LT		 718 if (irq != chip_irq)
719 IRDA_MESSAGE("%s, Overriding IRQ - chip says %d, using %d\n",
720 driver_name, chip_irq, irq);
721 self->io.irq = irq;
98b77773 722 } else
1da177e4 723 self->io.irq = chip_irq;
527b6af4 724
916f11c7 725 if (dma != DMA_INVAL) {
1da177e4
LT		 726 if (dma != chip_dma)
727 IRDA_MESSAGE("%s, Overriding DMA - chip says %d, using %d\n",
728 driver_name, chip_dma, dma);
729 self->io.dma = dma;
98b77773 730 } else
1da177e4
LT		 731 self->io.dma = chip_dma;
732
733}
734
735/*
736 * Function smsc_ircc_setup_qos(self)
737 *
738 * Setup qos
739 *
740 */
741static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self)
742{
743 /* Initialize QoS for this device */
744 irda_init_max_qos_capabilies(&self->qos);
527b6af4 745
1da177e4
LT		 746 self->qos.baud_rate.bits = IR_9600|IR_19200|IR_38400|IR_57600|
747 IR_115200|IR_576000|IR_1152000|(IR_4000000 << 8);
748
749 self->qos.min_turn_time.bits = SMSC_IRCC2_MIN_TURN_TIME;
750 self->qos.window_size.bits = SMSC_IRCC2_WINDOW_SIZE;
751 irda_qos_bits_to_value(&self->qos);
752}
753
754/*
755 * Function smsc_ircc_init_chip(self)
756 *
757 * Init chip
758 *
759 */
760static void smsc_ircc_init_chip(struct smsc_ircc_cb *self)
761{
e812cb52 762 int iobase = self->io.fir_base;
1da177e4
LT		 763
764 register_bank(iobase, 0);
98b77773
DT		 765 outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER);
766 outb(0x00, iobase + IRCC_MASTER);
1da177e4
LT		 767
768 register_bank(iobase, 1);
e812cb52 769 outb(((inb(iobase + IRCC_SCE_CFGA) & 0x87) | IRCC_CFGA_IRDA_SIR_A),
98b77773 770 iobase + IRCC_SCE_CFGA);
1da177e4
LT		 771
772#ifdef smsc_669 /* Uses pin 88/89 for Rx/Tx */
98b77773
DT		 773 outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM),
774 iobase + IRCC_SCE_CFGB);
527b6af4 775#else
98b77773
DT		 776 outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR),
777 iobase + IRCC_SCE_CFGB);
527b6af4 778#endif
98b77773
DT		 779 (void) inb(iobase + IRCC_FIFO_THRESHOLD);
780 outb(SMSC_IRCC2_FIFO_THRESHOLD, iobase + IRCC_FIFO_THRESHOLD);
527b6af4 781
1da177e4 782 register_bank(iobase, 4);
e812cb52 783 outb((inb(iobase + IRCC_CONTROL) & 0x30), iobase + IRCC_CONTROL);
527b6af4 784
1da177e4 785 register_bank(iobase, 0);
e812cb52 786 outb(0, iobase + IRCC_LCR_A);
1da177e4
LT		 787
788 smsc_ircc_set_sir_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED);
527b6af4 789
1da177e4 790 /* Power on device */
98b77773 791 outb(0x00, iobase + IRCC_MASTER);
1da177e4
LT		 792}
793
794/*
795 * Function smsc_ircc_net_ioctl (dev, rq, cmd)
796 *
797 * Process IOCTL commands for this device
798 *
799 */
800static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
801{
802 struct if_irda_req *irq = (struct if_irda_req *) rq;
803 struct smsc_ircc_cb *self;
804 unsigned long flags;
805 int ret = 0;
806
807 IRDA_ASSERT(dev != NULL, return -1;);
808
da0841a0 809 self = netdev_priv(dev);
1da177e4
LT		 810
811 IRDA_ASSERT(self != NULL, return -1;);
812
a97a6f10 813 IRDA_DEBUG(2, "%s(), %s, (cmd=0x%X)\n", __func__, dev->name, cmd);
527b6af4 814
1da177e4
LT		 815 switch (cmd) {
816 case SIOCSBANDWIDTH: /* Set bandwidth */
817 if (!capable(CAP_NET_ADMIN))
818 ret = -EPERM;
819 else {
820 /* Make sure we are the only one touching
821 * self->io.speed and the hardware - Jean II */
822 spin_lock_irqsave(&self->lock, flags);
823 smsc_ircc_change_speed(self, irq->ifr_baudrate);
824 spin_unlock_irqrestore(&self->lock, flags);
825 }
826 break;
827 case SIOCSMEDIABUSY: /* Set media busy */
828 if (!capable(CAP_NET_ADMIN)) {
829 ret = -EPERM;
830 break;
831 }
832
833 irda_device_set_media_busy(self->netdev, TRUE);
834 break;
835 case SIOCGRECEIVING: /* Check if we are receiving right now */
836 irq->ifr_receiving = smsc_ircc_is_receiving(self);
837 break;
838 #if 0
839 case SIOCSDTRRTS:
840 if (!capable(CAP_NET_ADMIN)) {
841 ret = -EPERM;
842 break;
843 }
844 smsc_ircc_sir_set_dtr_rts(dev, irq->ifr_dtr, irq->ifr_rts);
845 break;
846 #endif
847 default:
848 ret = -EOPNOTSUPP;
849 }
527b6af4 850
1da177e4
LT		 851 return ret;
852}
853
1da177e4
LT		 854#if SMSC_IRCC2_C_NET_TIMEOUT
855/*
856 * Function smsc_ircc_timeout (struct net_device *dev)
857 *
858 * The networking timeout management.
859 *
860 */
861
862static void smsc_ircc_timeout(struct net_device *dev)
863{
da0841a0 864 struct smsc_ircc_cb *self = netdev_priv(dev);
1da177e4
LT		 865 unsigned long flags;
866
1da177e4
LT		 867 IRDA_WARNING("%s: transmit timed out, changing speed to: %d\n",
868 dev->name, self->io.speed);
869 spin_lock_irqsave(&self->lock, flags);
870 smsc_ircc_sir_start(self);
871 smsc_ircc_change_speed(self, self->io.speed);
1ae5dc34 872 dev->trans_start = jiffies; /* prevent tx timeout */
1da177e4
LT		 873 netif_wake_queue(dev);
874 spin_unlock_irqrestore(&self->lock, flags);
875}
876#endif
877
878/*
879 * Function smsc_ircc_hard_xmit_sir (struct sk_buff *skb, struct net_device *dev)
880 *
881 * Transmits the current frame until FIFO is full, then
882 * waits until the next transmit interrupt, and continues until the
883 * frame is transmitted.
884 */
6518bbb8
SH		 885static netdev_tx_t smsc_ircc_hard_xmit_sir(struct sk_buff *skb,
886 struct net_device *dev)
1da177e4
LT		 887{
888 struct smsc_ircc_cb *self;
889 unsigned long flags;
1da177e4
LT		 890 s32 speed;
891
a97a6f10 892 IRDA_DEBUG(1, "%s\n", __func__);
1da177e4 893
ec634fe3 894 IRDA_ASSERT(dev != NULL, return NETDEV_TX_OK;);
527b6af4 895
da0841a0 896 self = netdev_priv(dev);
ec634fe3 897 IRDA_ASSERT(self != NULL, return NETDEV_TX_OK;);
1da177e4 898
1da177e4 899 netif_stop_queue(dev);
527b6af4 900
1da177e4
LT		 901 /* Make sure test of self->io.speed & speed change are atomic */
902 spin_lock_irqsave(&self->lock, flags);
903
904 /* Check if we need to change the speed */
905 speed = irda_get_next_speed(skb);
98b77773 906 if (speed != self->io.speed && speed != -1) {
1da177e4
LT		 907 /* Check for empty frame */
908 if (!skb->len) {
909 /*
910 * We send frames one by one in SIR mode (no
911 * pipelining), so at this point, if we were sending
912 * a previous frame, we just received the interrupt
913 * telling us it is finished (UART_IIR_THRI).
914 * Therefore, waiting for the transmitter to really
915 * finish draining the fifo won't take too long.
916 * And the interrupt handler is not expected to run.
917 * - Jean II */
918 smsc_ircc_sir_wait_hw_transmitter_finish(self);
919 smsc_ircc_change_speed(self, speed);
920 spin_unlock_irqrestore(&self->lock, flags);
921 dev_kfree_skb(skb);
ec634fe3 922 return NETDEV_TX_OK;
1da177e4 923 }
98b77773 924 self->new_speed = speed;
1da177e4
LT		 925 }
926
927 /* Init tx buffer */
928 self->tx_buff.data = self->tx_buff.head;
929
930 /* Copy skb to tx_buff while wrapping, stuffing and making CRC */
527b6af4 931 self->tx_buff.len = async_wrap_skb(skb, self->tx_buff.data,
1da177e4 932 self->tx_buff.truesize);
527b6af4 933
af049081 934 dev->stats.tx_bytes += self->tx_buff.len;
1da177e4
LT		 935
936 /* Turn on transmit finished interrupt. Will fire immediately! */
80a90589 937 outb(UART_IER_THRI, self->io.sir_base + UART_IER);
1da177e4
LT		 938
939 spin_unlock_irqrestore(&self->lock, flags);
940
941 dev_kfree_skb(skb);
527b6af4 942
ec634fe3 943 return NETDEV_TX_OK;
1da177e4
LT		 944}
945
946/*
947 * Function smsc_ircc_set_fir_speed (self, baud)
948 *
949 * Change the speed of the device
950 *
951 */
952static void smsc_ircc_set_fir_speed(struct smsc_ircc_cb *self, u32 speed)
953{
954 int fir_base, ir_mode, ctrl, fast;
955
956 IRDA_ASSERT(self != NULL, return;);
957 fir_base = self->io.fir_base;
958
959 self->io.speed = speed;
960
98b77773 961 switch (speed) {
1da177e4 962 default:
527b6af4 963 case 576000:
1da177e4
LT		 964 ir_mode = IRCC_CFGA_IRDA_HDLC;
965 ctrl = IRCC_CRC;
966 fast = 0;
a97a6f10 967 IRDA_DEBUG(0, "%s(), handling baud of 576000\n", __func__);
1da177e4
LT		 968 break;
969 case 1152000:
970 ir_mode = IRCC_CFGA_IRDA_HDLC;
971 ctrl = IRCC_1152 | IRCC_CRC;
972 fast = IRCC_LCR_A_FAST | IRCC_LCR_A_GP_DATA;
973 IRDA_DEBUG(0, "%s(), handling baud of 1152000\n",
a97a6f10 974 __func__);
1da177e4
LT		 975 break;
976 case 4000000:
977 ir_mode = IRCC_CFGA_IRDA_4PPM;
978 ctrl = IRCC_CRC;
979 fast = IRCC_LCR_A_FAST;
980 IRDA_DEBUG(0, "%s(), handling baud of 4000000\n",
a97a6f10 981 __func__);
1da177e4
LT		 982 break;
983 }
984 #if 0
985 Now in tranceiver!
986 /* This causes an interrupt */
987 register_bank(fir_base, 0);
98b77773 988 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast, fir_base + IRCC_LCR_A);
1da177e4 989 #endif
527b6af4 990
1da177e4 991 register_bank(fir_base, 1);
98b77773 992 outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | ir_mode), fir_base + IRCC_SCE_CFGA);
527b6af4 993
1da177e4 994 register_bank(fir_base, 4);
98b77773 995 outb((inb(fir_base + IRCC_CONTROL) & 0x30) | ctrl, fir_base + IRCC_CONTROL);
1da177e4
LT		 996}
997
998/*
999 * Function smsc_ircc_fir_start(self)
1000 *
1001 * Change the speed of the device
1002 *
1003 */
1004static void smsc_ircc_fir_start(struct smsc_ircc_cb *self)
1005{
1006 struct net_device *dev;
1007 int fir_base;
1008
a97a6f10 1009 IRDA_DEBUG(1, "%s\n", __func__);
1da177e4
LT		 1010
1011 IRDA_ASSERT(self != NULL, return;);
1012 dev = self->netdev;
1013 IRDA_ASSERT(dev != NULL, return;);
1014
1015 fir_base = self->io.fir_base;
1016
1017 /* Reset everything */
1018
1da177e4 1019 /* Clear FIFO */
98b77773 1020 outb(inb(fir_base + IRCC_LCR_A) | IRCC_LCR_A_FIFO_RESET, fir_base + IRCC_LCR_A);
1da177e4
LT		 1021
1022 /* Enable interrupt */
98b77773 1023 /*outb(IRCC_IER_ACTIVE_FRAME|IRCC_IER_EOM, fir_base + IRCC_IER);*/
1da177e4
LT		 1024
1025 register_bank(fir_base, 1);
1026
527b6af4 1027 /* Select the TX/RX interface */
1da177e4 1028#ifdef SMSC_669 /* Uses pin 88/89 for Rx/Tx */
98b77773
DT		 1029 outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM),
1030 fir_base + IRCC_SCE_CFGB);
527b6af4 1031#else
98b77773
DT		 1032 outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR),
1033 fir_base + IRCC_SCE_CFGB);
527b6af4 1034#endif
98b77773 1035 (void) inb(fir_base + IRCC_FIFO_THRESHOLD);
1da177e4
LT		 1036
1037 /* Enable SCE interrupts */
98b77773 1038 outb(0, fir_base + IRCC_MASTER);
1da177e4 1039 register_bank(fir_base, 0);
98b77773
DT		 1040 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, fir_base + IRCC_IER);
1041 outb(IRCC_MASTER_INT_EN, fir_base + IRCC_MASTER);
1da177e4
LT		 1042}
1043
1044/*
1045 * Function smsc_ircc_fir_stop(self, baud)
1046 *
1047 * Change the speed of the device
1048 *
1049 */
1050static void smsc_ircc_fir_stop(struct smsc_ircc_cb *self)
1051{
1052 int fir_base;
1053
a97a6f10 1054 IRDA_DEBUG(1, "%s\n", __func__);
527b6af4 1055
1da177e4
LT		 1056 IRDA_ASSERT(self != NULL, return;);
1057
1058 fir_base = self->io.fir_base;
1059 register_bank(fir_base, 0);
98b77773
DT		 1060 /*outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER);*/
1061 outb(inb(fir_base + IRCC_LCR_B) & IRCC_LCR_B_SIP_ENABLE, fir_base + IRCC_LCR_B);
1da177e4
LT		 1062}
1063
1064
1065/*
1066 * Function smsc_ircc_change_speed(self, baud)
1067 *
1068 * Change the speed of the device
1069 *
1070 * This function *must* be called with spinlock held, because it may
1071 * be called from the irq handler. - Jean II
1072 */
0fa2f491 1073static void smsc_ircc_change_speed(struct smsc_ircc_cb *self, u32 speed)
1da177e4 1074{
1da177e4 1075 struct net_device *dev;
1da177e4 1076 int last_speed_was_sir;
527b6af4 1077
a97a6f10 1078 IRDA_DEBUG(0, "%s() changing speed to: %d\n", __func__, speed);
1da177e4
LT		 1079
1080 IRDA_ASSERT(self != NULL, return;);
1081 dev = self->netdev;
1da177e4
LT		 1082
1083 last_speed_was_sir = self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED;
1084
1085 #if 0
1086 /* Temp Hack */
1087 speed= 1152000;
1088 self->io.speed = speed;
1089 last_speed_was_sir = 0;
527b6af4 1090 smsc_ircc_fir_start(self);
1da177e4 1091 #endif
527b6af4 1092
98b77773 1093 if (self->io.speed == 0)
1da177e4
LT		 1094 smsc_ircc_sir_start(self);
1095
1096 #if 0
98b77773 1097 if (!last_speed_was_sir) speed = self->io.speed;
1da177e4
LT		 1098 #endif
1099
98b77773
DT		 1100 if (self->io.speed != speed)
1101 smsc_ircc_set_transceiver_for_speed(self, speed);
1da177e4
LT		 1102
1103 self->io.speed = speed;
527b6af4 1104
98b77773
DT		 1105 if (speed <= SMSC_IRCC2_MAX_SIR_SPEED) {
1106 if (!last_speed_was_sir) {
1da177e4
LT		 1107 smsc_ircc_fir_stop(self);
1108 smsc_ircc_sir_start(self);
1109 }
527b6af4 1110 smsc_ircc_set_sir_speed(self, speed);
98b77773
DT		 1111 } else {
1112 if (last_speed_was_sir) {
527b6af4 1113 #if SMSC_IRCC2_C_SIR_STOP
1da177e4
LT		 1114 smsc_ircc_sir_stop(self);
1115 #endif
1116 smsc_ircc_fir_start(self);
1117 }
1118 smsc_ircc_set_fir_speed(self, speed);
1119
1120 #if 0
1121 self->tx_buff.len = 10;
1122 self->tx_buff.data = self->tx_buff.head;
527b6af4 1123
80a90589 1124 smsc_ircc_dma_xmit(self, 4000);
1da177e4
LT		 1125 #endif
1126 /* Be ready for incoming frames */
80a90589 1127 smsc_ircc_dma_receive(self);
1da177e4 1128 }
527b6af4 1129
1da177e4
LT		 1130 netif_wake_queue(dev);
1131}
1132
1133/*
1134 * Function smsc_ircc_set_sir_speed (self, speed)
1135 *
1136 * Set speed of IrDA port to specified baudrate
1137 *
1138 */
0e49e645 1139static void smsc_ircc_set_sir_speed(struct smsc_ircc_cb *self, __u32 speed)
1da177e4 1140{
527b6af4 1141 int iobase;
1da177e4
LT		 1142 int fcr; /* FIFO control reg */
1143 int lcr; /* Line control reg */
1144 int divisor;
1145
a97a6f10 1146 IRDA_DEBUG(0, "%s(), Setting speed to: %d\n", __func__, speed);
1da177e4
LT		 1147
1148 IRDA_ASSERT(self != NULL, return;);
1149 iobase = self->io.sir_base;
527b6af4 1150
1da177e4
LT		 1151 /* Update accounting for new speed */
1152 self->io.speed = speed;
1153
1154 /* Turn off interrupts */
98b77773 1155 outb(0, iobase + UART_IER);
1da177e4 1156
98b77773 1157 divisor = SMSC_IRCC2_MAX_SIR_SPEED / speed;
527b6af4 1158
1da177e4
LT		 1159 fcr = UART_FCR_ENABLE_FIFO;
1160
527b6af4 1161 /*
1da177e4
LT		 1162 * Use trigger level 1 to avoid 3 ms. timeout delay at 9600 bps, and
1163 * almost 1,7 ms at 19200 bps. At speeds above that we can just forget
527b6af4 1164 * about this timeout since it will always be fast enough.
1da177e4 1165 */
98b77773
DT		 1166 fcr |= self->io.speed < 38400 ?
1167 UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14;
527b6af4 1168
1da177e4
LT		 1169 /* IrDA ports use 8N1 */
1170 lcr = UART_LCR_WLEN8;
527b6af4 1171
98b77773
DT		 1172 outb(UART_LCR_DLAB | lcr, iobase + UART_LCR); /* Set DLAB */
1173 outb(divisor & 0xff, iobase + UART_DLL); /* Set speed */
1174 outb(divisor >> 8, iobase + UART_DLM);
1175 outb(lcr, iobase + UART_LCR); /* Set 8N1 */
1176 outb(fcr, iobase + UART_FCR); /* Enable FIFO's */
1da177e4
LT		 1177
1178 /* Turn on interrups */
98b77773 1179 outb(UART_IER_RLSI | UART_IER_RDI | UART_IER_THRI, iobase + UART_IER);
1da177e4 1180
a97a6f10 1181 IRDA_DEBUG(2, "%s() speed changed to: %d\n", __func__, speed);
1da177e4
LT		 1182}
1183
1184
1185/*
1186 * Function smsc_ircc_hard_xmit_fir (skb, dev)
1187 *
1188 * Transmit the frame!
1189 *
1190 */
6518bbb8
SH		 1191static netdev_tx_t smsc_ircc_hard_xmit_fir(struct sk_buff *skb,
1192 struct net_device *dev)
1da177e4
LT		 1193{
1194 struct smsc_ircc_cb *self;
1195 unsigned long flags;
1196 s32 speed;
1da177e4
LT		 1197 int mtt;
1198
ec634fe3 1199 IRDA_ASSERT(dev != NULL, return NETDEV_TX_OK;);
da0841a0 1200 self = netdev_priv(dev);
ec634fe3 1201 IRDA_ASSERT(self != NULL, return NETDEV_TX_OK;);
1da177e4 1202
1da177e4
LT		 1203 netif_stop_queue(dev);
1204
1205 /* Make sure test of self->io.speed & speed change are atomic */
1206 spin_lock_irqsave(&self->lock, flags);
1207
1208 /* Check if we need to change the speed after this frame */
1209 speed = irda_get_next_speed(skb);
98b77773 1210 if (speed != self->io.speed && speed != -1) {
1da177e4
LT		 1211 /* Check for empty frame */
1212 if (!skb->len) {
1213 /* Note : you should make sure that speed changes
1214 * are not going to corrupt any outgoing frame.
1215 * Look at nsc-ircc for the gory details - Jean II */
527b6af4 1216 smsc_ircc_change_speed(self, speed);
1da177e4
LT		 1217 spin_unlock_irqrestore(&self->lock, flags);
1218 dev_kfree_skb(skb);
ec634fe3 1219 return NETDEV_TX_OK;
98b77773
DT		 1220 }
1221
1222 self->new_speed = speed;
1da177e4 1223 }
527b6af4 1224
d626f62b 1225 skb_copy_from_linear_data(skb, self->tx_buff.head, skb->len);
1da177e4
LT		 1226
1227 self->tx_buff.len = skb->len;
1228 self->tx_buff.data = self->tx_buff.head;
527b6af4
DT		 1229
1230 mtt = irda_get_mtt(skb);
1da177e4
LT		 1231 if (mtt) {
1232 int bofs;
1233
527b6af4 1234 /*
1da177e4
LT		 1235 * Compute how many BOFs (STA or PA's) we need to waste the
1236 * min turn time given the speed of the link.
1237 */
1238 bofs = mtt * (self->io.speed / 1000) / 8000;
1239 if (bofs > 4095)
1240 bofs = 4095;
1241
80a90589 1242 smsc_ircc_dma_xmit(self, bofs);
1da177e4
LT		 1243 } else {
1244 /* Transmit frame */
80a90589 1245 smsc_ircc_dma_xmit(self, 0);
1da177e4 1246 }
98b77773 1247
1da177e4
LT		 1248 spin_unlock_irqrestore(&self->lock, flags);
1249 dev_kfree_skb(skb);
1250
ec634fe3 1251 return NETDEV_TX_OK;
1da177e4
LT		 1252}
1253
1254/*
80a90589 1255 * Function smsc_ircc_dma_xmit (self, bofs)
1da177e4
LT		 1256 *
1257 * Transmit data using DMA
1258 *
1259 */
80a90589 1260static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int bofs)
1da177e4 1261{
80a90589 1262 int iobase = self->io.fir_base;
1da177e4
LT		 1263 u8 ctrl;
1264
a97a6f10 1265 IRDA_DEBUG(3, "%s\n", __func__);
1da177e4
LT		 1266#if 1
1267 /* Disable Rx */
1268 register_bank(iobase, 0);
98b77773 1269 outb(0x00, iobase + IRCC_LCR_B);
1da177e4
LT		 1270#endif
1271 register_bank(iobase, 1);
98b77773
DT		 1272 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1273 iobase + IRCC_SCE_CFGB);
1da177e4
LT		 1274
1275 self->io.direction = IO_XMIT;
1276
1277 /* Set BOF additional count for generating the min turn time */
1278 register_bank(iobase, 4);
98b77773
DT		 1279 outb(bofs & 0xff, iobase + IRCC_BOF_COUNT_LO);
1280 ctrl = inb(iobase + IRCC_CONTROL) & 0xf0;
1281 outb(ctrl | ((bofs >> 8) & 0x0f), iobase + IRCC_BOF_COUNT_HI);
1da177e4
LT		 1282
1283 /* Set max Tx frame size */
98b77773
DT		 1284 outb(self->tx_buff.len >> 8, iobase + IRCC_TX_SIZE_HI);
1285 outb(self->tx_buff.len & 0xff, iobase + IRCC_TX_SIZE_LO);
1da177e4
LT		 1286
1287 /*outb(UART_MCR_OUT2, self->io.sir_base + UART_MCR);*/
527b6af4 1288
1da177e4
LT		 1289 /* Enable burst mode chip Tx DMA */
1290 register_bank(iobase, 1);
98b77773
DT		 1291 outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |
1292 IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB);
1da177e4
LT		 1293
1294 /* Setup DMA controller (must be done after enabling chip DMA) */
1295 irda_setup_dma(self->io.dma, self->tx_buff_dma, self->tx_buff.len,
1296 DMA_TX_MODE);
1297
1298 /* Enable interrupt */
1299
1300 register_bank(iobase, 0);
98b77773
DT		 1301 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1302 outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER);
527b6af4 1303
1da177e4 1304 /* Enable transmit */
98b77773 1305 outb(IRCC_LCR_B_SCE_TRANSMIT | IRCC_LCR_B_SIP_ENABLE, iobase + IRCC_LCR_B);
1da177e4
LT		 1306}
1307
1308/*
1309 * Function smsc_ircc_dma_xmit_complete (self)
1310 *
527b6af4 1311 * The transfer of a frame in finished. This function will only be called
1da177e4
LT		 1312 * by the interrupt handler
1313 *
1314 */
80a90589 1315static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self)
1da177e4 1316{
80a90589
DT		 1317 int iobase = self->io.fir_base;
1318
a97a6f10 1319 IRDA_DEBUG(3, "%s\n", __func__);
1da177e4
LT		 1320#if 0
1321 /* Disable Tx */
1322 register_bank(iobase, 0);
98b77773 1323 outb(0x00, iobase + IRCC_LCR_B);
1da177e4 1324#endif
80a90589
DT		 1325 register_bank(iobase, 1);
1326 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1327 iobase + IRCC_SCE_CFGB);
1da177e4
LT		 1328
1329 /* Check for underrun! */
1330 register_bank(iobase, 0);
98b77773 1331 if (inb(iobase + IRCC_LSR) & IRCC_LSR_UNDERRUN) {
af049081
SH		 1332 self->netdev->stats.tx_errors++;
1333 self->netdev->stats.tx_fifo_errors++;
1da177e4
LT		 1334
1335 /* Reset error condition */
1336 register_bank(iobase, 0);
98b77773
DT		 1337 outb(IRCC_MASTER_ERROR_RESET, iobase + IRCC_MASTER);
1338 outb(0x00, iobase + IRCC_MASTER);
1da177e4 1339 } else {
af049081
SH		 1340 self->netdev->stats.tx_packets++;
1341 self->netdev->stats.tx_bytes += self->tx_buff.len;
1da177e4
LT		 1342 }
1343
1344 /* Check if it's time to change the speed */
1345 if (self->new_speed) {
527b6af4 1346 smsc_ircc_change_speed(self, self->new_speed);
1da177e4
LT		 1347 self->new_speed = 0;
1348 }
1349
1350 netif_wake_queue(self->netdev);
1351}
1352
1353/*
1354 * Function smsc_ircc_dma_receive(self)
1355 *
1356 * Get ready for receiving a frame. The device will initiate a DMA
1357 * if it starts to receive a frame.
1358 *
1359 */
80a90589 1360static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self)
1da177e4 1361{
80a90589 1362 int iobase = self->io.fir_base;
1da177e4
LT		 1363#if 0
1364 /* Turn off chip DMA */
1365 register_bank(iobase, 1);
98b77773
DT		 1366 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1367 iobase + IRCC_SCE_CFGB);
1da177e4 1368#endif
527b6af4 1369
1da177e4
LT		 1370 /* Disable Tx */
1371 register_bank(iobase, 0);
98b77773 1372 outb(0x00, iobase + IRCC_LCR_B);
1da177e4
LT		 1373
1374 /* Turn off chip DMA */
1375 register_bank(iobase, 1);
98b77773
DT		 1376 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1377 iobase + IRCC_SCE_CFGB);
1da177e4
LT		 1378
1379 self->io.direction = IO_RECV;
1380 self->rx_buff.data = self->rx_buff.head;
1381
1382 /* Set max Rx frame size */
1383 register_bank(iobase, 4);
98b77773
DT		 1384 outb((2050 >> 8) & 0x0f, iobase + IRCC_RX_SIZE_HI);
1385 outb(2050 & 0xff, iobase + IRCC_RX_SIZE_LO);
1da177e4
LT		 1386
1387 /* Setup DMA controller */
1388 irda_setup_dma(self->io.dma, self->rx_buff_dma, self->rx_buff.truesize,
1389 DMA_RX_MODE);
1390
1391 /* Enable burst mode chip Rx DMA */
1392 register_bank(iobase, 1);
98b77773
DT		 1393 outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |
1394 IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB);
1da177e4
LT		 1395
1396 /* Enable interrupt */
1397 register_bank(iobase, 0);
98b77773
DT		 1398 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1399 outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER);
1da177e4
LT		 1400
1401 /* Enable receiver */
1402 register_bank(iobase, 0);
527b6af4 1403 outb(IRCC_LCR_B_SCE_RECEIVE | IRCC_LCR_B_SIP_ENABLE,
98b77773 1404 iobase + IRCC_LCR_B);
527b6af4 1405
1da177e4
LT		 1406 return 0;
1407}
1408
1409/*
80a90589 1410 * Function smsc_ircc_dma_receive_complete(self)
1da177e4
LT		 1411 *
1412 * Finished with receiving frames
1413 *
1414 */
80a90589 1415static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self)
1da177e4
LT		 1416{
1417 struct sk_buff *skb;
1418 int len, msgcnt, lsr;
80a90589 1419 int iobase = self->io.fir_base;
527b6af4 1420
1da177e4 1421 register_bank(iobase, 0);
527b6af4 1422
a97a6f10 1423 IRDA_DEBUG(3, "%s\n", __func__);
1da177e4
LT		 1424#if 0
1425 /* Disable Rx */
1426 register_bank(iobase, 0);
98b77773 1427 outb(0x00, iobase + IRCC_LCR_B);
1da177e4
LT		 1428#endif
1429 register_bank(iobase, 0);
98b77773
DT		 1430 outb(inb(iobase + IRCC_LSAR) & ~IRCC_LSAR_ADDRESS_MASK, iobase + IRCC_LSAR);
1431 lsr= inb(iobase + IRCC_LSR);
1432 msgcnt = inb(iobase + IRCC_LCR_B) & 0x08;
1da177e4 1433
a97a6f10 1434 IRDA_DEBUG(2, "%s: dma count = %d\n", __func__,
1da177e4
LT		 1435 get_dma_residue(self->io.dma));
1436
1437 len = self->rx_buff.truesize - get_dma_residue(self->io.dma);
1438
98b77773
DT		 1439 /* Look for errors */
1440 if (lsr & (IRCC_LSR_FRAME_ERROR | IRCC_LSR_CRC_ERROR | IRCC_LSR_SIZE_ERROR)) {
af049081 1441 self->netdev->stats.rx_errors++;
98b77773 1442 if (lsr & IRCC_LSR_FRAME_ERROR)
af049081 1443 self->netdev->stats.rx_frame_errors++;
98b77773 1444 if (lsr & IRCC_LSR_CRC_ERROR)
af049081 1445 self->netdev->stats.rx_crc_errors++;
98b77773 1446 if (lsr & IRCC_LSR_SIZE_ERROR)
af049081 1447 self->netdev->stats.rx_length_errors++;
98b77773 1448 if (lsr & (IRCC_LSR_UNDERRUN | IRCC_LSR_OVERRUN))
af049081 1449 self->netdev->stats.rx_length_errors++;
1da177e4
LT		 1450 return;
1451 }
98b77773 1452
1da177e4 1453 /* Remove CRC */
98b77773 1454 len -= self->io.speed < 4000000 ? 2 : 4;
1da177e4 1455
98b77773 1456 if (len < 2 || len > 2050) {
a97a6f10 1457 IRDA_WARNING("%s(), bogus len=%d\n", __func__, len);
1da177e4
LT		 1458 return;
1459 }
a97a6f10 1460 IRDA_DEBUG(2, "%s: msgcnt = %d, len=%d\n", __func__, msgcnt, len);
1da177e4 1461
98b77773
DT		 1462 skb = dev_alloc_skb(len + 1);
1463 if (!skb) {
1da177e4 1464 IRDA_WARNING("%s(), memory squeeze, dropping frame.\n",
a97a6f10 1465 __func__);
1da177e4 1466 return;
527b6af4 1467 }
1da177e4 1468 /* Make sure IP header gets aligned */
527b6af4 1469 skb_reserve(skb, 1);
1da177e4
LT		 1470
1471 memcpy(skb_put(skb, len), self->rx_buff.data, len);
af049081
SH		 1472 self->netdev->stats.rx_packets++;
1473 self->netdev->stats.rx_bytes += len;
1da177e4
LT		 1474
1475 skb->dev = self->netdev;
459a98ed 1476 skb_reset_mac_header(skb);
1da177e4
LT		 1477 skb->protocol = htons(ETH_P_IRDA);
1478 netif_rx(skb);
1479}
1480
1481/*
1482 * Function smsc_ircc_sir_receive (self)
1483 *
1484 * Receive one frame from the infrared port
1485 *
1486 */
527b6af4 1487static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self)
1da177e4
LT		 1488{
1489 int boguscount = 0;
1490 int iobase;
1491
1492 IRDA_ASSERT(self != NULL, return;);
1493
1494 iobase = self->io.sir_base;
1495
527b6af4
DT		 1496 /*
1497 * Receive all characters in Rx FIFO, unwrap and unstuff them.
1498 * async_unwrap_char will deliver all found frames
1da177e4
LT		 1499 */
1500 do {
af049081 1501 async_unwrap_char(self->netdev, &self->netdev->stats, &self->rx_buff,
98b77773 1502 inb(iobase + UART_RX));
1da177e4
LT		 1503
1504 /* Make sure we don't stay here to long */
1505 if (boguscount++ > 32) {
a97a6f10 1506 IRDA_DEBUG(2, "%s(), breaking!\n", __func__);
1da177e4
LT		 1507 break;
1508 }
98b77773 1509 } while (inb(iobase + UART_LSR) & UART_LSR_DR);
1da177e4
LT		 1510}
1511
1512
1513/*
1514 * Function smsc_ircc_interrupt (irq, dev_id, regs)
1515 *
1516 * An interrupt from the chip has arrived. Time to do some work
1517 *
1518 */
28fc1f5a 1519static irqreturn_t smsc_ircc_interrupt(int dummy, void *dev_id)
1da177e4 1520{
28fc1f5a
JG		 1521 struct net_device *dev = dev_id;
1522 struct smsc_ircc_cb *self = netdev_priv(dev);
1da177e4
LT		 1523 int iobase, iir, lcra, lsr;
1524 irqreturn_t ret = IRQ_NONE;
1525
1da177e4 1526 /* Serialise the interrupt handler in various CPUs, stop Tx path */
527b6af4 1527 spin_lock(&self->lock);
1da177e4
LT		 1528
1529 /* Check if we should use the SIR interrupt handler */
98b77773 1530 if (self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED) {
1da177e4
LT		 1531 ret = smsc_ircc_interrupt_sir(dev);
1532 goto irq_ret_unlock;
1533 }
1534
1535 iobase = self->io.fir_base;
1536
1537 register_bank(iobase, 0);
98b77773 1538 iir = inb(iobase + IRCC_IIR);
527b6af4 1539 if (iir == 0)
1da177e4
LT		 1540 goto irq_ret_unlock;
1541 ret = IRQ_HANDLED;
1542
1543 /* Disable interrupts */
98b77773
DT		 1544 outb(0, iobase + IRCC_IER);
1545 lcra = inb(iobase + IRCC_LCR_A);
1546 lsr = inb(iobase + IRCC_LSR);
527b6af4 1547
a97a6f10 1548 IRDA_DEBUG(2, "%s(), iir = 0x%02x\n", __func__, iir);
1da177e4
LT		 1549
1550 if (iir & IRCC_IIR_EOM) {
1551 if (self->io.direction == IO_RECV)
80a90589 1552 smsc_ircc_dma_receive_complete(self);
1da177e4 1553 else
80a90589 1554 smsc_ircc_dma_xmit_complete(self);
527b6af4 1555
80a90589 1556 smsc_ircc_dma_receive(self);
1da177e4
LT		 1557 }
1558
1559 if (iir & IRCC_IIR_ACTIVE_FRAME) {
a97a6f10 1560 /*printk(KERN_WARNING "%s(): Active Frame\n", __func__);*/
1da177e4
LT		 1561 }
1562
1563 /* Enable interrupts again */
1564
1565 register_bank(iobase, 0);
98b77773 1566 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1da177e4
LT		 1567
1568 irq_ret_unlock:
1569 spin_unlock(&self->lock);
28fc1f5a 1570
1da177e4
LT		 1571 return ret;
1572}
1573
1574/*
7d12e780 1575 * Function irport_interrupt_sir (irq, dev_id)
1da177e4
LT		 1576 *
1577 * Interrupt handler for SIR modes
1578 */
1579static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev)
1580{
da0841a0 1581 struct smsc_ircc_cb *self = netdev_priv(dev);
1da177e4
LT		 1582 int boguscount = 0;
1583 int iobase;
1584 int iir, lsr;
1585
25985edc 1586 /* Already locked coming here in smsc_ircc_interrupt() */
1da177e4
LT		 1587 /*spin_lock(&self->lock);*/
1588
1589 iobase = self->io.sir_base;
1590
98b77773 1591 iir = inb(iobase + UART_IIR) & UART_IIR_ID;
1da177e4
LT		 1592 if (iir == 0)
1593 return IRQ_NONE;
1594 while (iir) {
1595 /* Clear interrupt */
98b77773 1596 lsr = inb(iobase + UART_LSR);
1da177e4 1597
527b6af4 1598 IRDA_DEBUG(4, "%s(), iir=%02x, lsr=%02x, iobase=%#x\n",
a97a6f10 1599 __func__, iir, lsr, iobase);
1da177e4
LT		 1600
1601 switch (iir) {
1602 case UART_IIR_RLSI:
a97a6f10 1603 IRDA_DEBUG(2, "%s(), RLSI\n", __func__);
1da177e4
LT		 1604 break;
1605 case UART_IIR_RDI:
1606 /* Receive interrupt */
1607 smsc_ircc_sir_receive(self);
1608 break;
1609 case UART_IIR_THRI:
1610 if (lsr & UART_LSR_THRE)
1611 /* Transmitter ready for data */
1612 smsc_ircc_sir_write_wakeup(self);
1613 break;
1614 default:
1615 IRDA_DEBUG(0, "%s(), unhandled IIR=%#x\n",
a97a6f10 1616 __func__, iir);
1da177e4 1617 break;
527b6af4
DT		 1618 }
1619
1da177e4
LT		 1620 /* Make sure we don't stay here to long */
1621 if (boguscount++ > 100)
1622 break;
1623
527b6af4 1624 iir = inb(iobase + UART_IIR) & UART_IIR_ID;
1da177e4
LT		 1625 }
1626 /*spin_unlock(&self->lock);*/
1627 return IRQ_HANDLED;
1628}
1629
1630
1631#if 0 /* unused */
1632/*
1633 * Function ircc_is_receiving (self)
1634 *
1635 * Return TRUE is we are currently receiving a frame
1636 *
1637 */
1638static int ircc_is_receiving(struct smsc_ircc_cb *self)
1639{
1640 int status = FALSE;
1641 /* int iobase; */
1642
a97a6f10 1643 IRDA_DEBUG(1, "%s\n", __func__);
1da177e4
LT		 1644
1645 IRDA_ASSERT(self != NULL, return FALSE;);
1646
a97a6f10 1647 IRDA_DEBUG(0, "%s: dma count = %d\n", __func__,
1da177e4
LT		 1648 get_dma_residue(self->io.dma));
1649
1650 status = (self->rx_buff.state != OUTSIDE_FRAME);
527b6af4 1651
1da177e4
LT		 1652 return status;
1653}
1654#endif /* unused */
1655
e812cb52
DT		 1656static int smsc_ircc_request_irq(struct smsc_ircc_cb *self)
1657{
1658 int error;
1659
1660 error = request_irq(self->io.irq, smsc_ircc_interrupt, 0,
1661 self->netdev->name, self->netdev);
1662 if (error)
1663 IRDA_DEBUG(0, "%s(), unable to allocate irq=%d, err=%d\n",
a97a6f10 1664 __func__, self->io.irq, error);
e812cb52
DT		 1665
1666 return error;
1667}
1668
1669static void smsc_ircc_start_interrupts(struct smsc_ircc_cb *self)
1670{
1671 unsigned long flags;
1672
1673 spin_lock_irqsave(&self->lock, flags);
1674
1675 self->io.speed = 0;
1676 smsc_ircc_change_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED);
1677
1678 spin_unlock_irqrestore(&self->lock, flags);
1679}
1680
1681static void smsc_ircc_stop_interrupts(struct smsc_ircc_cb *self)
1682{
1683 int iobase = self->io.fir_base;
1684 unsigned long flags;
1685
1686 spin_lock_irqsave(&self->lock, flags);
1687
1688 register_bank(iobase, 0);
1689 outb(0, iobase + IRCC_IER);
1690 outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER);
1691 outb(0x00, iobase + IRCC_MASTER);
1692
1693 spin_unlock_irqrestore(&self->lock, flags);
1694}
1695
1da177e4
LT		 1696
1697/*
1698 * Function smsc_ircc_net_open (dev)
1699 *
1700 * Start the device
1701 *
1702 */
1703static int smsc_ircc_net_open(struct net_device *dev)
1704{
1705 struct smsc_ircc_cb *self;
1da177e4 1706 char hwname[16];
1da177e4 1707
a97a6f10 1708 IRDA_DEBUG(1, "%s\n", __func__);
527b6af4 1709
1da177e4 1710 IRDA_ASSERT(dev != NULL, return -1;);
da0841a0 1711 self = netdev_priv(dev);
1da177e4 1712 IRDA_ASSERT(self != NULL, return 0;);
527b6af4 1713
e812cb52 1714 if (self->io.suspended) {
a97a6f10 1715 IRDA_DEBUG(0, "%s(), device is suspended\n", __func__);
e812cb52
DT		 1716 return -EAGAIN;
1717 }
1718
527b6af4 1719 if (request_irq(self->io.irq, smsc_ircc_interrupt, 0, dev->name,
1da177e4
LT		 1720 (void *) dev)) {
1721 IRDA_DEBUG(0, "%s(), unable to allocate irq=%d\n",
a97a6f10 1722 __func__, self->io.irq);
1da177e4
LT		 1723 return -EAGAIN;
1724 }
1725
e812cb52 1726 smsc_ircc_start_interrupts(self);
527b6af4 1727
1da177e4
LT		 1728 /* Give self a hardware name */
1729 /* It would be cool to offer the chip revision here - Jean II */
1730 sprintf(hwname, "SMSC @ 0x%03x", self->io.fir_base);
1731
527b6af4 1732 /*
1da177e4 1733 * Open new IrLAP layer instance, now that everything should be
527b6af4 1734 * initialized properly
1da177e4
LT		 1735 */
1736 self->irlap = irlap_open(dev, &self->qos, hwname);
1737
1738 /*
1739 * Always allocate the DMA channel after the IRQ,
1740 * and clean up on failure.
1741 */
1742 if (request_dma(self->io.dma, dev->name)) {
1743 smsc_ircc_net_close(dev);
1744
1745 IRDA_WARNING("%s(), unable to allocate DMA=%d\n",
a97a6f10 1746 __func__, self->io.dma);
1da177e4
LT		 1747 return -EAGAIN;
1748 }
527b6af4 1749
1da177e4
LT		 1750 netif_start_queue(dev);
1751
1752 return 0;
1753}
1754
1755/*
1756 * Function smsc_ircc_net_close (dev)
1757 *
1758 * Stop the device
1759 *
1760 */
1761static int smsc_ircc_net_close(struct net_device *dev)
1762{
1763 struct smsc_ircc_cb *self;
1da177e4 1764
a97a6f10 1765 IRDA_DEBUG(1, "%s\n", __func__);
527b6af4 1766
1da177e4 1767 IRDA_ASSERT(dev != NULL, return -1;);
da0841a0 1768 self = netdev_priv(dev);
1da177e4 1769 IRDA_ASSERT(self != NULL, return 0;);
527b6af4 1770
1da177e4
LT		 1771 /* Stop device */
1772 netif_stop_queue(dev);
527b6af4 1773
1da177e4
LT		 1774 /* Stop and remove instance of IrLAP */
1775 if (self->irlap)
1776 irlap_close(self->irlap);
1777 self->irlap = NULL;
1778
e812cb52
DT		 1779 smsc_ircc_stop_interrupts(self);
1780
1781 /* if we are called from smsc_ircc_resume we don't have IRQ reserved */
1782 if (!self->io.suspended)
1783 free_irq(self->io.irq, dev);
1784
1da177e4 1785 disable_dma(self->io.dma);
1da177e4
LT		 1786 free_dma(self->io.dma);
1787
1788 return 0;
1789}
1790
3ae5eaec 1791static int smsc_ircc_suspend(struct platform_device *dev, pm_message_t state)
1da177e4 1792{
3ae5eaec 1793 struct smsc_ircc_cb *self = platform_get_drvdata(dev);
6bb3b2cd 1794
9480e307 1795 if (!self->io.suspended) {
e812cb52
DT		 1796 IRDA_DEBUG(1, "%s, Suspending\n", driver_name);
1797
1798 rtnl_lock();
1799 if (netif_running(self->netdev)) {
1800 netif_device_detach(self->netdev);
1801 smsc_ircc_stop_interrupts(self);
1802 free_irq(self->io.irq, self->netdev);
1803 disable_dma(self->io.dma);
1804 }
98b77773 1805 self->io.suspended = 1;
e812cb52 1806 rtnl_unlock();
98b77773 1807 }
6bb3b2cd
DT		 1808
1809 return 0;
1da177e4
LT		 1810}
1811
3ae5eaec 1812static int smsc_ircc_resume(struct platform_device *dev)
1da177e4 1813{
3ae5eaec 1814 struct smsc_ircc_cb *self = platform_get_drvdata(dev);
1da177e4 1815
9480e307 1816 if (self->io.suspended) {
e812cb52
DT		 1817 IRDA_DEBUG(1, "%s, Waking up\n", driver_name);
1818
1819 rtnl_lock();
1820 smsc_ircc_init_chip(self);
1821 if (netif_running(self->netdev)) {
1822 if (smsc_ircc_request_irq(self)) {
1823 /*
1824 * Don't fail resume process, just kill this
1825 * network interface
1826 */
1827 unregister_netdevice(self->netdev);
1828 } else {
1829 enable_dma(self->io.dma);
1830 smsc_ircc_start_interrupts(self);
1831 netif_device_attach(self->netdev);
1832 }
1833 }
6bb3b2cd 1834 self->io.suspended = 0;
e812cb52 1835 rtnl_unlock();
6bb3b2cd 1836 }
1da177e4
LT		 1837 return 0;
1838}
1839
1840/*
1841 * Function smsc_ircc_close (self)
1842 *
1843 * Close driver instance
1844 *
1845 */
1846static int __exit smsc_ircc_close(struct smsc_ircc_cb *self)
1847{
a97a6f10 1848 IRDA_DEBUG(1, "%s\n", __func__);
1da177e4
LT		 1849
1850 IRDA_ASSERT(self != NULL, return -1;);
1851
6bb3b2cd 1852 platform_device_unregister(self->pldev);
1da177e4
LT		 1853
1854 /* Remove netdevice */
1855 unregister_netdev(self->netdev);
1856
e812cb52 1857 smsc_ircc_stop_interrupts(self);
1da177e4
LT		 1858
1859 /* Release the PORTS that this driver is using */
a97a6f10 1860 IRDA_DEBUG(0, "%s(), releasing 0x%03x\n", __func__,
1da177e4
LT		 1861 self->io.fir_base);
1862
1863 release_region(self->io.fir_base, self->io.fir_ext);
1864
a97a6f10 1865 IRDA_DEBUG(0, "%s(), releasing 0x%03x\n", __func__,
1da177e4
LT		 1866 self->io.sir_base);
1867
1868 release_region(self->io.sir_base, self->io.sir_ext);
1869
1870 if (self->tx_buff.head)
1871 dma_free_coherent(NULL, self->tx_buff.truesize,
1872 self->tx_buff.head, self->tx_buff_dma);
527b6af4 1873
1da177e4
LT		 1874 if (self->rx_buff.head)
1875 dma_free_coherent(NULL, self->rx_buff.truesize,
1876 self->rx_buff.head, self->rx_buff_dma);
1877
1878 free_netdev(self->netdev);
1879
1880 return 0;
1881}
1882
1883static void __exit smsc_ircc_cleanup(void)
1884{
1885 int i;
1886
a97a6f10 1887 IRDA_DEBUG(1, "%s\n", __func__);
1da177e4 1888
98b77773 1889 for (i = 0; i < 2; i++) {
1da177e4
LT		 1890 if (dev_self[i])
1891 smsc_ircc_close(dev_self[i]);
1892 }
6bb3b2cd 1893
d0d4f69b
BH		 1894 if (pnp_driver_registered)
1895 pnp_unregister_driver(&smsc_ircc_pnp_driver);
1896
3ae5eaec 1897 platform_driver_unregister(&smsc_ircc_driver);
1da177e4
LT		 1898}
1899
1900/*
1901 * Start SIR operations
1902 *
1903 * This function *must* be called with spinlock held, because it may
1904 * be called from the irq handler (via smsc_ircc_change_speed()). - Jean II
1905 */
0e49e645 1906static void smsc_ircc_sir_start(struct smsc_ircc_cb *self)
1da177e4
LT		 1907{
1908 struct net_device *dev;
1909 int fir_base, sir_base;
1910
a97a6f10 1911 IRDA_DEBUG(3, "%s\n", __func__);
1da177e4 1912
527b6af4 1913 IRDA_ASSERT(self != NULL, return;);
98b77773 1914 dev = self->netdev;
527b6af4 1915 IRDA_ASSERT(dev != NULL, return;);
1da177e4
LT		 1916
1917 fir_base = self->io.fir_base;
1918 sir_base = self->io.sir_base;
1919
1920 /* Reset everything */
98b77773 1921 outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER);
1da177e4
LT		 1922
1923 #if SMSC_IRCC2_C_SIR_STOP
1924 /*smsc_ircc_sir_stop(self);*/
1925 #endif
1926
1927 register_bank(fir_base, 1);
98b77773 1928 outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | IRCC_CFGA_IRDA_SIR_A), fir_base + IRCC_SCE_CFGA);
1da177e4
LT		 1929
1930 /* Initialize UART */
98b77773
DT		 1931 outb(UART_LCR_WLEN8, sir_base + UART_LCR); /* Reset DLAB */
1932 outb((UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2), sir_base + UART_MCR);
527b6af4 1933
1da177e4 1934 /* Turn on interrups */
98b77773 1935 outb(UART_IER_RLSI | UART_IER_RDI |UART_IER_THRI, sir_base + UART_IER);
1da177e4 1936
a97a6f10 1937 IRDA_DEBUG(3, "%s() - exit\n", __func__);
1da177e4 1938
98b77773 1939 outb(0x00, fir_base + IRCC_MASTER);
1da177e4
LT		 1940}
1941
1942#if SMSC_IRCC2_C_SIR_STOP
1943void smsc_ircc_sir_stop(struct smsc_ircc_cb *self)
1944{
1945 int iobase;
1946
a97a6f10 1947 IRDA_DEBUG(3, "%s\n", __func__);
1da177e4
LT		 1948 iobase = self->io.sir_base;
1949
1950 /* Reset UART */
98b77773 1951 outb(0, iobase + UART_MCR);
527b6af4 1952
1da177e4 1953 /* Turn off interrupts */
98b77773 1954 outb(0, iobase + UART_IER);
1da177e4
LT		 1955}
1956#endif
1957
1958/*
1959 * Function smsc_sir_write_wakeup (self)
1960 *
1961 * Called by the SIR interrupt handler when there's room for more data.
1962 * If we have more packets to send, we send them here.
1963 *
1964 */
1965static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self)
1966{
1967 int actual = 0;
1968 int iobase;
1969 int fcr;
1970
1971 IRDA_ASSERT(self != NULL, return;);
1972
a97a6f10 1973 IRDA_DEBUG(4, "%s\n", __func__);
1da177e4
LT		 1974
1975 iobase = self->io.sir_base;
1976
1977 /* Finished with frame? */
1978 if (self->tx_buff.len > 0) {
1979 /* Write data left in transmit buffer */
527b6af4 1980 actual = smsc_ircc_sir_write(iobase, self->io.fifo_size,
1da177e4
LT		 1981 self->tx_buff.data, self->tx_buff.len);
1982 self->tx_buff.data += actual;
1983 self->tx_buff.len -= actual;
1984 } else {
527b6af4 1985
1da177e4 1986 /*if (self->tx_buff.len ==0) {*/
527b6af4
DT		 1987
1988 /*
1989 * Now serial buffer is almost free & we can start
1da177e4
LT		 1990 * transmission of another packet. But first we must check
1991 * if we need to change the speed of the hardware
1992 */
1993 if (self->new_speed) {
1994 IRDA_DEBUG(5, "%s(), Changing speed to %d.\n",
a97a6f10 1995 __func__, self->new_speed);
1da177e4
LT		 1996 smsc_ircc_sir_wait_hw_transmitter_finish(self);
1997 smsc_ircc_change_speed(self, self->new_speed);
1998 self->new_speed = 0;
1999 } else {
2000 /* Tell network layer that we want more frames */
2001 netif_wake_queue(self->netdev);
2002 }
af049081 2003 self->netdev->stats.tx_packets++;
1da177e4 2004
98b77773
DT		 2005 if (self->io.speed <= 115200) {
2006 /*
2007 * Reset Rx FIFO to make sure that all reflected transmit data
2008 * is discarded. This is needed for half duplex operation
2009 */
2010 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR;
2011 fcr |= self->io.speed < 38400 ?
2012 UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14;
1da177e4 2013
98b77773 2014 outb(fcr, iobase + UART_FCR);
1da177e4 2015
98b77773
DT		 2016 /* Turn on receive interrupts */
2017 outb(UART_IER_RDI, iobase + UART_IER);
1da177e4
LT		 2018 }
2019 }
2020}
2021
2022/*
2023 * Function smsc_ircc_sir_write (iobase, fifo_size, buf, len)
2024 *
2025 * Fill Tx FIFO with transmit data
2026 *
2027 */
2028static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len)
2029{
2030 int actual = 0;
527b6af4 2031
1da177e4 2032 /* Tx FIFO should be empty! */
98b77773 2033 if (!(inb(iobase + UART_LSR) & UART_LSR_THRE)) {
a97a6f10 2034 IRDA_WARNING("%s(), failed, fifo not empty!\n", __func__);
1da177e4
LT		 2035 return 0;
2036 }
527b6af4 2037
1da177e4 2038 /* Fill FIFO with current frame */
98b77773 2039 while (fifo_size-- > 0 && actual < len) {
1da177e4 2040 /* Transmit next byte */
98b77773 2041 outb(buf[actual], iobase + UART_TX);
1da177e4
LT		 2042 actual++;
2043 }
2044 return actual;
2045}
2046
2047/*
2048 * Function smsc_ircc_is_receiving (self)
2049 *
2050 * Returns true is we are currently receiving data
2051 *
2052 */
2053static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self)
2054{
807540ba 2055 return self->rx_buff.state != OUTSIDE_FRAME;
1da177e4
LT		 2056}
2057
2058
2059/*
2060 * Function smsc_ircc_probe_transceiver(self)
2061 *
2062 * Tries to find the used Transceiver
2063 *
2064 */
2065static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self)
2066{
2067 unsigned int i;
527b6af4 2068
1da177e4 2069 IRDA_ASSERT(self != NULL, return;);
527b6af4 2070
98b77773
DT		 2071 for (i = 0; smsc_transceivers[i].name != NULL; i++)
2072 if (smsc_transceivers[i].probe(self->io.fir_base)) {
1da177e4
LT		 2073 IRDA_MESSAGE(" %s transceiver found\n",
2074 smsc_transceivers[i].name);
98b77773 2075 self->transceiver= i + 1;
1da177e4
LT		 2076 return;
2077 }
98b77773 2078
1da177e4
LT		 2079 IRDA_MESSAGE("No transceiver found. Defaulting to %s\n",
2080 smsc_transceivers[SMSC_IRCC2_C_DEFAULT_TRANSCEIVER].name);
527b6af4 2081
98b77773 2082 self->transceiver = SMSC_IRCC2_C_DEFAULT_TRANSCEIVER;
1da177e4
LT		 2083}
2084
2085
2086/*
2087 * Function smsc_ircc_set_transceiver_for_speed(self, speed)
2088 *
2089 * Set the transceiver according to the speed
2090 *
2091 */
2092static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed)
2093{
2094 unsigned int trx;
527b6af4 2095
1da177e4 2096 trx = self->transceiver;
98b77773
DT		 2097 if (trx > 0)
2098 smsc_transceivers[trx - 1].set_for_speed(self->io.fir_base, speed);
1da177e4
LT		 2099}
2100
2101/*
2102 * Function smsc_ircc_wait_hw_transmitter_finish ()
2103 *
2104 * Wait for the real end of HW transmission
2105 *
2106 * The UART is a strict FIFO, and we get called only when we have finished
2107 * pushing data to the FIFO, so the maximum amount of time we must wait
2108 * is only for the FIFO to drain out.
2109 *
2110 * We use a simple calibrated loop. We may need to adjust the loop
2111 * delay (udelay) to balance I/O traffic and latency. And we also need to
2112 * adjust the maximum timeout.
2113 * It would probably be better to wait for the proper interrupt,
2114 * but it doesn't seem to be available.
2115 *
2116 * We can't use jiffies or kernel timers because :
2117 * 1) We are called from the interrupt handler, which disable softirqs,
2118 * so jiffies won't be increased
2119 * 2) Jiffies granularity is usually very coarse (10ms), and we don't
2120 * want to wait that long to detect stuck hardware.
2121 * Jean II
2122 */
2123
2124static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self)
2125{
98b77773 2126 int iobase = self->io.sir_base;
1da177e4 2127 int count = SMSC_IRCC2_HW_TRANSMITTER_TIMEOUT_US;
527b6af4 2128
1da177e4 2129 /* Calibrated busy loop */
98b77773 2130 while (count-- > 0 && !(inb(iobase + UART_LSR) & UART_LSR_TEMT))
1da177e4
LT		 2131 udelay(1);
2132
adbf7f01 2133 if (count < 0)
a97a6f10 2134 IRDA_DEBUG(0, "%s(): stuck transmitter\n", __func__);
1da177e4
LT		 2135}
2136
2137
2138/* PROBING
2139 *
d94c77b9
DB		 2140 * REVISIT we can be told about the device by PNP, and should use that info
2141 * instead of probing hardware and creating a platform_device ...
1da177e4
LT		 2142 */
2143
2144static int __init smsc_ircc_look_for_chips(void)
2145{
b6158d23 2146 struct smsc_chip_address *address;
98b77773 2147 char *type;
1da177e4 2148 unsigned int cfg_base, found;
527b6af4 2149
1da177e4
LT		 2150 found = 0;
2151 address = possible_addresses;
527b6af4 2152
98b77773 2153 while (address->cfg_base) {
1da177e4 2154 cfg_base = address->cfg_base;
527b6af4 2155
a97a6f10 2156 /*printk(KERN_WARNING "%s(): probing: 0x%02x for: 0x%02x\n", __func__, cfg_base, address->type);*/
527b6af4 2157
98b77773 2158 if (address->type & SMSCSIO_TYPE_FDC) {
1da177e4 2159 type = "FDC";
98b77773
DT		 2160 if (address->type & SMSCSIO_TYPE_FLAT)
2161 if (!smsc_superio_flat(fdc_chips_flat, cfg_base, type))
2162 found++;
2163
2164 if (address->type & SMSCSIO_TYPE_PAGED)
2165 if (!smsc_superio_paged(fdc_chips_paged, cfg_base, type))
2166 found++;
1da177e4 2167 }
98b77773 2168 if (address->type & SMSCSIO_TYPE_LPC) {
1da177e4 2169 type = "LPC";
98b77773
DT		 2170 if (address->type & SMSCSIO_TYPE_FLAT)
2171 if (!smsc_superio_flat(lpc_chips_flat, cfg_base, type))
2172 found++;
2173
2174 if (address->type & SMSCSIO_TYPE_PAGED)
2175 if (!smsc_superio_paged(lpc_chips_paged, cfg_base, type))
2176 found++;
1da177e4
LT		 2177 }
2178 address++;
2179 }
2180 return found;
527b6af4 2181}
1da177e4
LT		 2182
2183/*
2184 * Function smsc_superio_flat (chip, base, type)
2185 *
2186 * Try to get configuration of a smc SuperIO chip with flat register model
2187 *
2188 */
b6158d23 2189static int __init smsc_superio_flat(const struct smsc_chip *chips, unsigned short cfgbase, char *type)
1da177e4
LT		 2190{
2191 unsigned short firbase, sirbase;
2192 u8 mode, dma, irq;
2193 int ret = -ENODEV;
2194
a97a6f10 2195 IRDA_DEBUG(1, "%s\n", __func__);
1da177e4 2196
98b77773 2197 if (smsc_ircc_probe(cfgbase, SMSCSIOFLAT_DEVICEID_REG, chips, type) == NULL)
1da177e4
LT		 2198 return ret;
2199
2200 outb(SMSCSIOFLAT_UARTMODE0C_REG, cfgbase);
98b77773 2201 mode = inb(cfgbase + 1);
527b6af4 2202
a97a6f10 2203 /*printk(KERN_WARNING "%s(): mode: 0x%02x\n", __func__, mode);*/
527b6af4 2204
98b77773 2205 if (!(mode & SMSCSIOFLAT_UART2MODE_VAL_IRDA))
a97a6f10 2206 IRDA_WARNING("%s(): IrDA not enabled\n", __func__);
1da177e4
LT		 2207
2208 outb(SMSCSIOFLAT_UART2BASEADDR_REG, cfgbase);
98b77773 2209 sirbase = inb(cfgbase + 1) << 2;
1da177e4 2210
527b6af4 2211 /* FIR iobase */
1da177e4 2212 outb(SMSCSIOFLAT_FIRBASEADDR_REG, cfgbase);
98b77773 2213 firbase = inb(cfgbase + 1) << 3;
1da177e4
LT		 2214
2215 /* DMA */
2216 outb(SMSCSIOFLAT_FIRDMASELECT_REG, cfgbase);
98b77773 2217 dma = inb(cfgbase + 1) & SMSCSIOFLAT_FIRDMASELECT_MASK;
527b6af4 2218
1da177e4
LT		 2219 /* IRQ */
2220 outb(SMSCSIOFLAT_UARTIRQSELECT_REG, cfgbase);
98b77773 2221 irq = inb(cfgbase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK;
1da177e4 2222
a97a6f10 2223 IRDA_MESSAGE("%s(): fir: 0x%02x, sir: 0x%02x, dma: %02d, irq: %d, mode: 0x%02x\n", __func__, firbase, sirbase, dma, irq, mode);
1da177e4 2224
98b77773
DT		 2225 if (firbase && smsc_ircc_open(firbase, sirbase, dma, irq) == 0)
2226 ret = 0;
527b6af4 2227
1da177e4
LT		 2228 /* Exit configuration */
2229 outb(SMSCSIO_CFGEXITKEY, cfgbase);
2230
2231 return ret;
2232}
2233
2234/*
2235 * Function smsc_superio_paged (chip, base, type)
2236 *
2237 * Try to get configuration of a smc SuperIO chip with paged register model
2238 *
2239 */
b6158d23 2240static int __init smsc_superio_paged(const struct smsc_chip *chips, unsigned short cfg_base, char *type)
1da177e4
LT		 2241{
2242 unsigned short fir_io, sir_io;
2243 int ret = -ENODEV;
527b6af4 2244
a97a6f10 2245 IRDA_DEBUG(1, "%s\n", __func__);
1da177e4 2246
98b77773 2247 if (smsc_ircc_probe(cfg_base, 0x20, chips, type) == NULL)
1da177e4 2248 return ret;
527b6af4 2249
1da177e4
LT		 2250 /* Select logical device (UART2) */
2251 outb(0x07, cfg_base);
2252 outb(0x05, cfg_base + 1);
527b6af4 2253
1da177e4
LT		 2254 /* SIR iobase */
2255 outb(0x60, cfg_base);
98b77773 2256 sir_io = inb(cfg_base + 1) << 8;
1da177e4
LT		 2257 outb(0x61, cfg_base);
2258 sir_io |= inb(cfg_base + 1);
527b6af4 2259
1da177e4
LT		 2260 /* Read FIR base */
2261 outb(0x62, cfg_base);
2262 fir_io = inb(cfg_base + 1) << 8;
2263 outb(0x63, cfg_base);
2264 fir_io |= inb(cfg_base + 1);
2265 outb(0x2b, cfg_base); /* ??? */
2266
98b77773
DT		 2267 if (fir_io && smsc_ircc_open(fir_io, sir_io, ircc_dma, ircc_irq) == 0)
2268 ret = 0;
527b6af4 2269
1da177e4
LT		 2270 /* Exit configuration */
2271 outb(SMSCSIO_CFGEXITKEY, cfg_base);
2272
2273 return ret;
2274}
2275
2276
948252cb 2277static int __init smsc_access(unsigned short cfg_base, unsigned char reg)
1da177e4 2278{
a97a6f10 2279 IRDA_DEBUG(1, "%s\n", __func__);
1da177e4
LT		 2280
2281 outb(reg, cfg_base);
98b77773 2282 return inb(cfg_base) != reg ? -1 : 0;
1da177e4
LT		 2283}
2284
948252cb 2285static const struct smsc_chip * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const struct smsc_chip *chip, char *type)
1da177e4 2286{
98b77773 2287 u8 devid, xdevid, rev;
1da177e4 2288
a97a6f10 2289 IRDA_DEBUG(1, "%s\n", __func__);
1da177e4
LT		 2290
2291 /* Leave configuration */
2292
2293 outb(SMSCSIO_CFGEXITKEY, cfg_base);
2294
2295 if (inb(cfg_base) == SMSCSIO_CFGEXITKEY) /* not a smc superio chip */
2296 return NULL;
2297
2298 outb(reg, cfg_base);
2299
98b77773 2300 xdevid = inb(cfg_base + 1);
1da177e4
LT		 2301
2302 /* Enter configuration */
2303
2304 outb(SMSCSIO_CFGACCESSKEY, cfg_base);
2305
2306 #if 0
2307 if (smsc_access(cfg_base,0x55)) /* send second key and check */
2308 return NULL;
2309 #endif
527b6af4 2310
1da177e4
LT		 2311 /* probe device ID */
2312
98b77773 2313 if (smsc_access(cfg_base, reg))
1da177e4
LT		 2314 return NULL;
2315
98b77773 2316 devid = inb(cfg_base + 1);
527b6af4 2317
98b77773 2318 if (devid == 0 || devid == 0xff) /* typical values for unused port */
1da177e4
LT		 2319 return NULL;
2320
2321 /* probe revision ID */
2322
98b77773 2323 if (smsc_access(cfg_base, reg + 1))
1da177e4
LT		 2324 return NULL;
2325
98b77773 2326 rev = inb(cfg_base + 1);
1da177e4 2327
98b77773 2328 if (rev >= 128) /* i think this will make no sense */
1da177e4
LT		 2329 return NULL;
2330
98b77773 2331 if (devid == xdevid) /* protection against false positives */
1da177e4
LT		 2332 return NULL;
2333
2334 /* Check for expected device ID; are there others? */
2335
98b77773 2336 while (chip->devid != devid) {
1da177e4
LT		 2337
2338 chip++;
2339
98b77773 2340 if (chip->name == NULL)
1da177e4
LT		 2341 return NULL;
2342 }
2343
98b77773
DT		 2344 IRDA_MESSAGE("found SMC SuperIO Chip (devid=0x%02x rev=%02X base=0x%04x): %s%s\n",
2345 devid, rev, cfg_base, type, chip->name);
1da177e4 2346
98b77773 2347 if (chip->rev > rev) {
527b6af4 2348 IRDA_MESSAGE("Revision higher than expected\n");
1da177e4
LT		 2349 return NULL;
2350 }
527b6af4 2351
98b77773 2352 if (chip->flags & NoIRDA)
1da177e4
LT		 2353 IRDA_MESSAGE("chipset does not support IRDA\n");
2354
2355 return chip;
2356}
2357
2358static int __init smsc_superio_fdc(unsigned short cfg_base)
2359{
2360 int ret = -1;
2361
2362 if (!request_region(cfg_base, 2, driver_name)) {
2363 IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n",
a97a6f10 2364 __func__, cfg_base);
1da177e4 2365 } else {
98b77773
DT		 2366 if (!smsc_superio_flat(fdc_chips_flat, cfg_base, "FDC") ||
2367 !smsc_superio_paged(fdc_chips_paged, cfg_base, "FDC"))
1da177e4
LT		 2368 ret = 0;
2369
2370 release_region(cfg_base, 2);
2371 }
2372
2373 return ret;
2374}
2375
2376static int __init smsc_superio_lpc(unsigned short cfg_base)
2377{
2378 int ret = -1;
2379
2380 if (!request_region(cfg_base, 2, driver_name)) {
2381 IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n",
a97a6f10 2382 __func__, cfg_base);
1da177e4 2383 } else {
98b77773
DT		 2384 if (!smsc_superio_flat(lpc_chips_flat, cfg_base, "LPC") ||
2385 !smsc_superio_paged(lpc_chips_paged, cfg_base, "LPC"))
1da177e4 2386 ret = 0;
98b77773 2387
1da177e4
LT		 2388 release_region(cfg_base, 2);
2389 }
2390 return ret;
2391}
2392
c1e14a6e
LW		 2393/*
2394 * Look for some specific subsystem setups that need
2395 * pre-configuration not properly done by the BIOS (especially laptops)
2396 * This code is based in part on smcinit.c, tosh1800-smcinit.c
2397 * and tosh2450-smcinit.c. The table lists the device entries
08d09997
LW		 2398 * for ISA bridges with an LPC (Low Pin Count) controller which
2399 * handles the communication with the SMSC device. After the LPC
2400 * controller is initialized through PCI, the SMSC device is initialized
2401 * through a dedicated port in the ISA port-mapped I/O area, this latter
2402 * area is used to configure the SMSC device with default
2403 * SIR and FIR I/O ports, DMA and IRQ. Different vendors have
2404 * used different sets of parameters and different control port
2405 * addresses making a subsystem device table necessary.
c1e14a6e
LW		 2406 */
2407#ifdef CONFIG_PCI
948252cb 2408static struct smsc_ircc_subsystem_configuration subsystem_configurations[] __initdata = {
895de090
LWLE		 2409 /*
2410 * Subsystems needing entries:
2411 * 0x10b9:0x1533 0x103c:0x0850 HP nx9010 family
2412 * 0x10b9:0x1533 0x0e11:0x005a Compaq nc4000 family
2413 * 0x8086:0x24cc 0x0e11:0x002a HP nx9000 family
2414 */
2415 {
2416 /* Guessed entry */
5ee5a07c 2417 .vendor = PCI_VENDOR_ID_INTEL, /* Intel 82801DBM LPC bridge */
895de090
LWLE		 2418 .device = 0x24cc,
2419 .subvendor = 0x103c,
2420 .subdevice = 0x08bc,
2421 .sir_io = 0x02f8,
2422 .fir_io = 0x0130,
2423 .fir_irq = 0x05,
2424 .fir_dma = 0x03,
2425 .cfg_base = 0x004e,
2426 .preconfigure = preconfigure_through_82801,
2427 .name = "HP nx5000 family",
2428 },
c1e14a6e 2429 {
5ee5a07c 2430 .vendor = PCI_VENDOR_ID_INTEL, /* Intel 82801DBM LPC bridge */
c1e14a6e
LW		 2431 .device = 0x24cc,
2432 .subvendor = 0x103c,
2433 .subdevice = 0x088c,
08d09997
LW		 2434 /* Quite certain these are the same for nc8000 as for nc6000 */
2435 .sir_io = 0x02f8,
c1e14a6e 2436 .fir_io = 0x0130,
08d09997 2437 .fir_irq = 0x05,
c1e14a6e
LW		 2438 .fir_dma = 0x03,
2439 .cfg_base = 0x004e,
2440 .preconfigure = preconfigure_through_82801,
895de090 2441 .name = "HP nc8000 family",
c1e14a6e
LW		 2442 },
2443 {
5ee5a07c 2444 .vendor = PCI_VENDOR_ID_INTEL, /* Intel 82801DBM LPC bridge */
c1e14a6e
LW		 2445 .device = 0x24cc,
2446 .subvendor = 0x103c,
2447 .subdevice = 0x0890,
2448 .sir_io = 0x02f8,
2449 .fir_io = 0x0130,
08d09997 2450 .fir_irq = 0x05,
c1e14a6e
LW		 2451 .fir_dma = 0x03,
2452 .cfg_base = 0x004e,
2453 .preconfigure = preconfigure_through_82801,
895de090
LWLE		 2454 .name = "HP nc6000 family",
2455 },
2456 {
5ee5a07c 2457 .vendor = PCI_VENDOR_ID_INTEL, /* Intel 82801DBM LPC bridge */
895de090
LWLE		 2458 .device = 0x24cc,
2459 .subvendor = 0x0e11,
2460 .subdevice = 0x0860,
2461 /* I assume these are the same for x1000 as for the others */
2462 .sir_io = 0x02e8,
2463 .fir_io = 0x02f8,
2464 .fir_irq = 0x07,
2465 .fir_dma = 0x03,
2466 .cfg_base = 0x002e,
2467 .preconfigure = preconfigure_through_82801,
2468 .name = "Compaq x1000 family",
c1e14a6e
LW		 2469 },
2470 {
08d09997 2471 /* Intel 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge */
5ee5a07c 2472 .vendor = PCI_VENDOR_ID_INTEL,
c1e14a6e
LW		 2473 .device = 0x24c0,
2474 .subvendor = 0x1179,
08d09997 2475 .subdevice = 0xffff, /* 0xffff is "any" */
c1e14a6e
LW		 2476 .sir_io = 0x03f8,
2477 .fir_io = 0x0130,
2478 .fir_irq = 0x07,
2479 .fir_dma = 0x01,
2480 .cfg_base = 0x002e,
2481 .preconfigure = preconfigure_through_82801,
08d09997 2482 .name = "Toshiba laptop with Intel 82801DB/DBL LPC bridge",
c1e14a6e
LW		 2483 },
2484 {
5ee5a07c 2485 .vendor = PCI_VENDOR_ID_INTEL, /* Intel 82801CAM ISA bridge */
08d09997 2486 .device = 0x248c,
c1e14a6e 2487 .subvendor = 0x1179,
08d09997 2488 .subdevice = 0xffff, /* 0xffff is "any" */
c1e14a6e
LW		 2489 .sir_io = 0x03f8,
2490 .fir_io = 0x0130,
2491 .fir_irq = 0x03,
2492 .fir_dma = 0x03,
2493 .cfg_base = 0x002e,
2494 .preconfigure = preconfigure_through_82801,
08d09997 2495 .name = "Toshiba laptop with Intel 82801CAM ISA bridge",
c1e14a6e
LW		 2496 },
2497 {
08d09997 2498 /* 82801DBM (ICH4-M) LPC Interface Bridge */
5ee5a07c 2499 .vendor = PCI_VENDOR_ID_INTEL,
08d09997
LW		 2500 .device = 0x24cc,
2501 .subvendor = 0x1179,
2502 .subdevice = 0xffff, /* 0xffff is "any" */
2503 .sir_io = 0x03f8,
2504 .fir_io = 0x0130,
2505 .fir_irq = 0x03,
2506 .fir_dma = 0x03,
2507 .cfg_base = 0x002e,
2508 .preconfigure = preconfigure_through_82801,
2509 .name = "Toshiba laptop with Intel 8281DBM LPC bridge",
2510 },
2511 {
2512 /* ALi M1533/M1535 PCI to ISA Bridge [Aladdin IV/V/V+] */
5ee5a07c 2513 .vendor = PCI_VENDOR_ID_AL,
c1e14a6e
LW		 2514 .device = 0x1533,
2515 .subvendor = 0x1179,
08d09997 2516 .subdevice = 0xffff, /* 0xffff is "any" */
c1e14a6e
LW		 2517 .sir_io = 0x02e8,
2518 .fir_io = 0x02f8,
2519 .fir_irq = 0x07,
2520 .fir_dma = 0x03,
2521 .cfg_base = 0x002e,
2522 .preconfigure = preconfigure_through_ali,
08d09997 2523 .name = "Toshiba laptop with ALi ISA bridge",
c1e14a6e
LW		 2524 },
2525 { } // Terminator
2526};
2527
2528
2529/*
08d09997
LW		 2530 * This sets up the basic SMSC parameters
2531 * (FIR port, SIR port, FIR DMA, FIR IRQ)
c1e14a6e
LW		 2532 * through the chip configuration port.
2533 */
948252cb 2534static int __init preconfigure_smsc_chip(struct
08d09997
LW		 2535 smsc_ircc_subsystem_configuration
2536 *conf)
c1e14a6e
LW		 2537{
2538 unsigned short iobase = conf->cfg_base;
2539 unsigned char tmpbyte;
2540
2541 outb(LPC47N227_CFGACCESSKEY, iobase); // enter configuration state
2542 outb(SMSCSIOFLAT_DEVICEID_REG, iobase); // set for device ID
2543 tmpbyte = inb(iobase +1); // Read device ID
08d09997
LW		 2544 IRDA_DEBUG(0,
2545 "Detected Chip id: 0x%02x, setting up registers...\n",
2546 tmpbyte);
c1e14a6e
LW		 2547
2548 /* Disable UART1 and set up SIR I/O port */
2549 outb(0x24, iobase); // select CR24 - UART1 base addr
2550 outb(0x00, iobase + 1); // disable UART1
2551 outb(SMSCSIOFLAT_UART2BASEADDR_REG, iobase); // select CR25 - UART2 base addr
2552 outb( (conf->sir_io >> 2), iobase + 1); // bits 2-9 of 0x3f8
2553 tmpbyte = inb(iobase + 1);
2554 if (tmpbyte != (conf->sir_io >> 2) ) {
2555 IRDA_WARNING("ERROR: could not configure SIR ioport.\n");
08d09997 2556 IRDA_WARNING("Try to supply ircc_cfg argument.\n");
c1e14a6e
LW		 2557 return -ENXIO;
2558 }
2559
2560 /* Set up FIR IRQ channel for UART2 */
2561 outb(SMSCSIOFLAT_UARTIRQSELECT_REG, iobase); // select CR28 - UART1,2 IRQ select
2562 tmpbyte = inb(iobase + 1);
2563 tmpbyte &= SMSCSIOFLAT_UART1IRQSELECT_MASK; // Do not touch the UART1 portion
2564 tmpbyte |= (conf->fir_irq & SMSCSIOFLAT_UART2IRQSELECT_MASK);
2565 outb(tmpbyte, iobase + 1);
2566 tmpbyte = inb(iobase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK;
2567 if (tmpbyte != conf->fir_irq) {
2568 IRDA_WARNING("ERROR: could not configure FIR IRQ channel.\n");
2569 return -ENXIO;
2570 }
2571
2572 /* Set up FIR I/O port */
2573 outb(SMSCSIOFLAT_FIRBASEADDR_REG, iobase); // CR2B - SCE (FIR) base addr
2574 outb((conf->fir_io >> 3), iobase + 1);
2575 tmpbyte = inb(iobase + 1);
2576 if (tmpbyte != (conf->fir_io >> 3) ) {
2577 IRDA_WARNING("ERROR: could not configure FIR I/O port.\n");
2578 return -ENXIO;
2579 }
2580
2581 /* Set up FIR DMA channel */
2582 outb(SMSCSIOFLAT_FIRDMASELECT_REG, iobase); // CR2C - SCE (FIR) DMA select
2583 outb((conf->fir_dma & LPC47N227_FIRDMASELECT_MASK), iobase + 1); // DMA
2584 tmpbyte = inb(iobase + 1) & LPC47N227_FIRDMASELECT_MASK;
2585 if (tmpbyte != (conf->fir_dma & LPC47N227_FIRDMASELECT_MASK)) {
2586 IRDA_WARNING("ERROR: could not configure FIR DMA channel.\n");
2587 return -ENXIO;
2588 }
2589
2590 outb(SMSCSIOFLAT_UARTMODE0C_REG, iobase); // CR0C - UART mode
2591 tmpbyte = inb(iobase + 1);
08d09997
LW		 2592 tmpbyte &= ~SMSCSIOFLAT_UART2MODE_MASK |
2593 SMSCSIOFLAT_UART2MODE_VAL_IRDA;
c1e14a6e
LW		 2594 outb(tmpbyte, iobase + 1); // enable IrDA (HPSIR) mode, high speed
2595
2596 outb(LPC47N227_APMBOOTDRIVE_REG, iobase); // CR07 - Auto Pwr Mgt/boot drive sel
2597 tmpbyte = inb(iobase + 1);
2598 outb(tmpbyte | LPC47N227_UART2AUTOPWRDOWN_MASK, iobase + 1); // enable UART2 autopower down
2599
2600 /* This one was not part of tosh1800 */
2601 outb(0x0a, iobase); // CR0a - ecp fifo / ir mux
2602 tmpbyte = inb(iobase + 1);
2603 outb(tmpbyte | 0x40, iobase + 1); // send active device to ir port
2604
2605 outb(LPC47N227_UART12POWER_REG, iobase); // CR02 - UART 1,2 power
2606 tmpbyte = inb(iobase + 1);
2607 outb(tmpbyte | LPC47N227_UART2POWERDOWN_MASK, iobase + 1); // UART2 power up mode, UART1 power down
2608
2609 outb(LPC47N227_FDCPOWERVALIDCONF_REG, iobase); // CR00 - FDC Power/valid config cycle
2610 tmpbyte = inb(iobase + 1);
2611 outb(tmpbyte | LPC47N227_VALID_MASK, iobase + 1); // valid config cycle done
2612
2613 outb(LPC47N227_CFGEXITKEY, iobase); // Exit configuration
2614
2615 return 0;
2616}
2617
08d09997 2618/* 82801CAM generic registers */
c1e14a6e
LW		 2619#define VID 0x00
2620#define DID 0x02
08d09997
LW		 2621#define PIRQ_A_D_ROUT 0x60
2622#define SIRQ_CNTL 0x64
2623#define PIRQ_E_H_ROUT 0x68
c1e14a6e 2624#define PCI_DMA_C 0x90
08d09997 2625/* LPC-specific registers */
c1e14a6e 2626#define COM_DEC 0xe0
08d09997 2627#define GEN1_DEC 0xe4
c1e14a6e
LW		 2628#define LPC_EN 0xe6
2629#define GEN2_DEC 0xec
2630/*
08d09997
LW		 2631 * Sets up the I/O range using the 82801CAM ISA bridge, 82801DBM LPC bridge
2632 * or Intel 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge.
2633 * They all work the same way!
c1e14a6e 2634 */
948252cb 2635static int __init preconfigure_through_82801(struct pci_dev *dev,
08d09997
LW		 2636 struct
2637 smsc_ircc_subsystem_configuration
2638 *conf)
c1e14a6e
LW		 2639{
2640 unsigned short tmpword;
08d09997 2641 unsigned char tmpbyte;
c1e14a6e 2642
08d09997
LW		 2643 IRDA_MESSAGE("Setting up Intel 82801 controller and SMSC device\n");
2644 /*
2645 * Select the range for the COMA COM port (SIR)
2646 * Register COM_DEC:
2647 * Bit 7: reserved
2648 * Bit 6-4, COMB decode range
2649 * Bit 3: reserved
2650 * Bit 2-0, COMA decode range
2651 *
2652 * Decode ranges:
2653 * 000 = 0x3f8-0x3ff (COM1)
2654 * 001 = 0x2f8-0x2ff (COM2)
2655 * 010 = 0x220-0x227
2656 * 011 = 0x228-0x22f
2657 * 100 = 0x238-0x23f
2658 * 101 = 0x2e8-0x2ef (COM4)
2659 * 110 = 0x338-0x33f
2660 * 111 = 0x3e8-0x3ef (COM3)
2661 */
2662 pci_read_config_byte(dev, COM_DEC, &tmpbyte);
2663 tmpbyte &= 0xf8; /* mask COMA bits */
2664 switch(conf->sir_io) {
2665 case 0x3f8:
2666 tmpbyte |= 0x00;
2667 break;
2668 case 0x2f8:
2669 tmpbyte |= 0x01;
2670 break;
2671 case 0x220:
2672 tmpbyte |= 0x02;
2673 break;
2674 case 0x228:
2675 tmpbyte |= 0x03;
2676 break;
2677 case 0x238:
2678 tmpbyte |= 0x04;
2679 break;
2680 case 0x2e8:
2681 tmpbyte |= 0x05;
2682 break;
2683 case 0x338:
2684 tmpbyte |= 0x06;
2685 break;
2686 case 0x3e8:
2687 tmpbyte |= 0x07;
2688 break;
2689 default:
2690 tmpbyte |= 0x01; /* COM2 default */
2691 }
2692 IRDA_DEBUG(1, "COM_DEC (write): 0x%02x\n", tmpbyte);
2693 pci_write_config_byte(dev, COM_DEC, tmpbyte);
c1e14a6e 2694
08d09997
LW		 2695 /* Enable Low Pin Count interface */
2696 pci_read_config_word(dev, LPC_EN, &tmpword);
2697 /* These seem to be set up at all times,
2698 * just make sure it is properly set.
2699 */
2700 switch(conf->cfg_base) {
2701 case 0x04e:
2702 tmpword |= 0x2000;
2703 break;
2704 case 0x02e:
2705 tmpword |= 0x1000;
2706 break;
2707 case 0x062:
2708 tmpword |= 0x0800;
2709 break;
2710 case 0x060:
2711 tmpword |= 0x0400;
2712 break;
2713 default:
2714 IRDA_WARNING("Uncommon I/O base address: 0x%04x\n",
2715 conf->cfg_base);
2716 break;
2717 }
2718 tmpword &= 0xfffd; /* disable LPC COMB */
2719 tmpword |= 0x0001; /* set bit 0 : enable LPC COMA addr range (GEN2) */
2720 IRDA_DEBUG(1, "LPC_EN (write): 0x%04x\n", tmpword);
c1e14a6e
LW		 2721 pci_write_config_word(dev, LPC_EN, tmpword);
2722
08d09997
LW		 2723 /*
2724 * Configure LPC DMA channel
2725 * PCI_DMA_C bits:
2726 * Bit 15-14: DMA channel 7 select
2727 * Bit 13-12: DMA channel 6 select
2728 * Bit 11-10: DMA channel 5 select
2729 * Bit 9-8: Reserved
2730 * Bit 7-6: DMA channel 3 select
2731 * Bit 5-4: DMA channel 2 select
2732 * Bit 3-2: DMA channel 1 select
2733 * Bit 1-0: DMA channel 0 select
2734 * 00 = Reserved value
2735 * 01 = PC/PCI DMA
2736 * 10 = Reserved value
2737 * 11 = LPC I/F DMA
2738 */
2739 pci_read_config_word(dev, PCI_DMA_C, &tmpword);
2740 switch(conf->fir_dma) {
2741 case 0x07:
2742 tmpword |= 0xc000;
2743 break;
2744 case 0x06:
2745 tmpword |= 0x3000;
2746 break;
2747 case 0x05:
2748 tmpword |= 0x0c00;
2749 break;
2750 case 0x03:
2751 tmpword |= 0x00c0;
2752 break;
2753 case 0x02:
2754 tmpword |= 0x0030;
2755 break;
2756 case 0x01:
2757 tmpword |= 0x000c;
2758 break;
2759 case 0x00:
2760 tmpword |= 0x0003;
2761 break;
2762 default:
2763 break; /* do not change settings */
2764 }
2765 IRDA_DEBUG(1, "PCI_DMA_C (write): 0x%04x\n", tmpword);
2766 pci_write_config_word(dev, PCI_DMA_C, tmpword);
2767
2768 /*
2769 * GEN2_DEC bits:
2770 * Bit 15-4: Generic I/O range
2771 * Bit 3-1: reserved (read as 0)
2772 * Bit 0: enable GEN2 range on LPC I/F
2773 */
2774 tmpword = conf->fir_io & 0xfff8;
2775 tmpword |= 0x0001;
2776 IRDA_DEBUG(1, "GEN2_DEC (write): 0x%04x\n", tmpword);
2777 pci_write_config_word(dev, GEN2_DEC, tmpword);
c1e14a6e
LW		 2778
2779 /* Pre-configure chip */
08d09997
LW		 2780 return preconfigure_smsc_chip(conf);
2781}
c1e14a6e 2782
08d09997
LW		 2783/*
2784 * Pre-configure a certain port on the ALi 1533 bridge.
2785 * This is based on reverse-engineering since ALi does not
2786 * provide any data sheet for the 1533 chip.
2787 */
948252cb 2788static void __init preconfigure_ali_port(struct pci_dev *dev,
08d09997
LW		 2789 unsigned short port)
2790{
2791 unsigned char reg;
2792 /* These bits obviously control the different ports */
2793 unsigned char mask;
2794 unsigned char tmpbyte;
2795
2796 switch(port) {
2797 case 0x0130:
2798 case 0x0178:
2799 reg = 0xb0;
2800 mask = 0x80;
2801 break;
2802 case 0x03f8:
2803 reg = 0xb4;
2804 mask = 0x80;
2805 break;
2806 case 0x02f8:
2807 reg = 0xb4;
2808 mask = 0x30;
2809 break;
2810 case 0x02e8:
2811 reg = 0xb4;
2812 mask = 0x08;
2813 break;
2814 default:
2815 IRDA_ERROR("Failed to configure unsupported port on ALi 1533 bridge: 0x%04x\n", port);
2816 return;
2817 }
2818
2819 pci_read_config_byte(dev, reg, &tmpbyte);
2820 /* Turn on the right bits */
2821 tmpbyte |= mask;
2822 pci_write_config_byte(dev, reg, tmpbyte);
2823 IRDA_MESSAGE("Activated ALi 1533 ISA bridge port 0x%04x.\n", port);
c1e14a6e
LW		 2824}
2825
948252cb 2826static int __init preconfigure_through_ali(struct pci_dev *dev,
08d09997
LW		 2827 struct
2828 smsc_ircc_subsystem_configuration
2829 *conf)
c1e14a6e 2830{
08d09997
LW		 2831 /* Configure the two ports on the ALi 1533 */
2832 preconfigure_ali_port(dev, conf->sir_io);
2833 preconfigure_ali_port(dev, conf->fir_io);
2834
2835 /* Pre-configure chip */
2836 return preconfigure_smsc_chip(conf);
c1e14a6e
LW		 2837}
2838
948252cb 2839static int __init smsc_ircc_preconfigure_subsystems(unsigned short ircc_cfg,
c1e14a6e
LW		 2840 unsigned short ircc_fir,
2841 unsigned short ircc_sir,
2842 unsigned char ircc_dma,
2843 unsigned char ircc_irq)
2844{
2845 struct pci_dev *dev = NULL;
2846 unsigned short ss_vendor = 0x0000;
2847 unsigned short ss_device = 0x0000;
2848 int ret = 0;
2849
2e4e7a97 2850 for_each_pci_dev(dev) {
948252cb 2851 struct smsc_ircc_subsystem_configuration *conf;
c1e14a6e
LW		 2852
2853 /*
08d09997
LW		 2854 * Cache the subsystem vendor/device:
2855 * some manufacturers fail to set this for all components,
2856 * so we save it in case there is just 0x0000 0x0000 on the
2857 * device we want to check.
c1e14a6e
LW		 2858 */
2859 if (dev->subsystem_vendor != 0x0000U) {
2860 ss_vendor = dev->subsystem_vendor;
2861 ss_device = dev->subsystem_device;
2862 }
2863 conf = subsystem_configurations;
2864 for( ; conf->subvendor; conf++) {
2865 if(conf->vendor == dev->vendor &&
2866 conf->device == dev->device &&
08d09997
LW		 2867 conf->subvendor == ss_vendor &&
2868 /* Sometimes these are cached values */
2869 (conf->subdevice == ss_device ||
2870 conf->subdevice == 0xffff)) {
2871 struct smsc_ircc_subsystem_configuration
2872 tmpconf;
c1e14a6e 2873
08d09997
LW		 2874 memcpy(&tmpconf, conf,
2875 sizeof(struct smsc_ircc_subsystem_configuration));
c1e14a6e 2876
08d09997
LW		 2877 /*
2878 * Override the default values with anything
2879 * passed in as parameter
2880 */
c1e14a6e
LW		 2881 if (ircc_cfg != 0)
2882 tmpconf.cfg_base = ircc_cfg;
2883 if (ircc_fir != 0)
2884 tmpconf.fir_io = ircc_fir;
2885 if (ircc_sir != 0)
2886 tmpconf.sir_io = ircc_sir;
916f11c7 2887 if (ircc_dma != DMA_INVAL)
c1e14a6e 2888 tmpconf.fir_dma = ircc_dma;
916f11c7 2889 if (ircc_irq != IRQ_INVAL)
c1e14a6e
LW		 2890 tmpconf.fir_irq = ircc_irq;
2891
2892 IRDA_MESSAGE("Detected unconfigured %s SMSC IrDA chip, pre-configuring device.\n", conf->name);
2893 if (conf->preconfigure)
2894 ret = conf->preconfigure(dev, &tmpconf);
2895 else
2896 ret = -ENODEV;
2897 }
2898 }
c1e14a6e
LW		 2899 }
2900
2901 return ret;
2902}
2903#endif // CONFIG_PCI
2904
1da177e4
LT		 2905/************************************************
2906 *
2907 * Transceivers specific functions
2908 *
2909 ************************************************/
2910
2911
2912/*
2913 * Function smsc_ircc_set_transceiver_smsc_ircc_atc(fir_base, speed)
2914 *
2915 * Program transceiver through smsc-ircc ATC circuitry
2916 *
2917 */
2918
2919static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed)
2920{
2921 unsigned long jiffies_now, jiffies_timeout;
98b77773 2922 u8 val;
527b6af4 2923
98b77773
DT		 2924 jiffies_now = jiffies;
2925 jiffies_timeout = jiffies + SMSC_IRCC2_ATC_PROGRAMMING_TIMEOUT_JIFFIES;
527b6af4 2926
1da177e4
LT		 2927 /* ATC */
2928 register_bank(fir_base, 4);
98b77773
DT		 2929 outb((inb(fir_base + IRCC_ATC) & IRCC_ATC_MASK) | IRCC_ATC_nPROGREADY|IRCC_ATC_ENABLE,
2930 fir_base + IRCC_ATC);
2931
2932 while ((val = (inb(fir_base + IRCC_ATC) & IRCC_ATC_nPROGREADY)) &&
2933 !time_after(jiffies, jiffies_timeout))
2934 /* empty */;
2935
2936 if (val)
a97a6f10 2937 IRDA_WARNING("%s(): ATC: 0x%02x\n", __func__,
98b77773 2938 inb(fir_base + IRCC_ATC));
1da177e4
LT		 2939}
2940
2941/*
2942 * Function smsc_ircc_probe_transceiver_smsc_ircc_atc(fir_base)
2943 *
2944 * Probe transceiver smsc-ircc ATC circuitry
2945 *
2946 */
2947
2948static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base)
2949{
2950 return 0;
2951}
2952
2953/*
2954 * Function smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(self, speed)
2955 *
527b6af4 2956 * Set transceiver
1da177e4
LT		 2957 *
2958 */
2959
2960static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed)
2961{
98b77773 2962 u8 fast_mode;
527b6af4 2963
98b77773
DT		 2964 switch (speed) {
2965 default:
2966 case 576000 :
527b6af4 2967 fast_mode = 0;
1da177e4 2968 break;
98b77773
DT		 2969 case 1152000 :
2970 case 4000000 :
1da177e4
LT		 2971 fast_mode = IRCC_LCR_A_FAST;
2972 break;
1da177e4
LT		 2973 }
2974 register_bank(fir_base, 0);
98b77773 2975 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A);
1da177e4
LT		 2976}
2977
2978/*
2979 * Function smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(fir_base)
2980 *
527b6af4 2981 * Probe transceiver
1da177e4
LT		 2982 *
2983 */
2984
2985static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base)
2986{
2987 return 0;
2988}
2989
2990/*
2991 * Function smsc_ircc_set_transceiver_toshiba_sat1800(fir_base, speed)
2992 *
527b6af4 2993 * Set transceiver
1da177e4
LT		 2994 *
2995 */
2996
2997static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed)
2998{
98b77773 2999 u8 fast_mode;
527b6af4 3000
98b77773
DT		 3001 switch (speed) {
3002 default:
3003 case 576000 :
527b6af4 3004 fast_mode = 0;
1da177e4 3005 break;
98b77773
DT		 3006 case 1152000 :
3007 case 4000000 :
1da177e4
LT		 3008 fast_mode = /*IRCC_LCR_A_FAST |*/ IRCC_LCR_A_GP_DATA;
3009 break;
527b6af4 3010
1da177e4
LT		 3011 }
3012 /* This causes an interrupt */
3013 register_bank(fir_base, 0);
98b77773 3014 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A);
1da177e4
LT		 3015}
3016
3017/*
3018 * Function smsc_ircc_probe_transceiver_toshiba_sat1800(fir_base)
3019 *
527b6af4 3020 * Probe transceiver
1da177e4
LT		 3021 *
3022 */
3023
3024static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base)
3025{
3026 return 0;
3027}
3028
3029
3030module_init(smsc_ircc_init);
3031module_exit(smsc_ircc_cleanup);
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