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Merge tag 'nfc-next-4.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sameo...
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / irda / smsc-ircc2.c
CommitLineData
1da177e4 1/*********************************************************************
1da177e4
LT		 2 *
3 * Description: Driver for the SMC Infrared Communications Controller
1da177e4 4 * Author: Daniele Peri (peri@csai.unipa.it)
527b6af4
DT		 5 * Created at:
6 * Modified at:
7 * Modified by:
8 *
1da177e4
LT		 9 * Copyright (c) 2002 Daniele Peri
10 * All Rights Reserved.
11 * Copyright (c) 2002 Jean Tourrilhes
c1e14a6e 12 * Copyright (c) 2006 Linus Walleij
1da177e4
LT		 13 *
14 *
15 * Based on smc-ircc.c:
16 *
17 * Copyright (c) 2001 Stefani Seibold
18 * Copyright (c) 1999-2001 Dag Brattli
527b6af4 19 * Copyright (c) 1998-1999 Thomas Davis,
1da177e4
LT		 20 *
21 * and irport.c:
22 *
23 * Copyright (c) 1997, 1998, 1999-2000 Dag Brattli, All Rights Reserved.
24 *
527b6af4
DT		 25 *
26 * This program is free software; you can redistribute it and/or
27 * modify it under the terms of the GNU General Public License as
28 * published by the Free Software Foundation; either version 2 of
1da177e4 29 * the License, or (at your option) any later version.
527b6af4 30 *
1da177e4
LT		 31 * This program is distributed in the hope that it will be useful,
32 * but WITHOUT ANY WARRANTY; without even the implied warranty of
33 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
34 * GNU General Public License for more details.
527b6af4
DT		 35 *
36 * You should have received a copy of the GNU General Public License
e8478de3 37 * along with this program; if not, see <http://www.gnu.org/licenses/>.
1da177e4
LT		 38 *
39 ********************************************************************/
40
41#include <linux/module.h>
42#include <linux/kernel.h>
43#include <linux/types.h>
44#include <linux/skbuff.h>
45#include <linux/netdevice.h>
46#include <linux/ioport.h>
47#include <linux/delay.h>
1da177e4 48#include <linux/init.h>
a6b7a407 49#include <linux/interrupt.h>
1da177e4
LT		 50#include <linux/rtnetlink.h>
51#include <linux/serial_reg.h>
52#include <linux/dma-mapping.h>
d94c77b9 53#include <linux/pnp.h>
d052d1be 54#include <linux/platform_device.h>
5a0e3ad6 55#include <linux/gfp.h>
1da177e4
LT		 56
57#include <asm/io.h>
58#include <asm/dma.h>
59#include <asm/byteorder.h>
60
61#include <linux/spinlock.h>
62#include <linux/pm.h>
c1e14a6e
LW		 63#ifdef CONFIG_PCI
64#include <linux/pci.h>
65#endif
1da177e4
LT		 66
67#include <net/irda/wrapper.h>
68#include <net/irda/irda.h>
69#include <net/irda/irda_device.h>
70
71#include "smsc-ircc2.h"
72#include "smsc-sio.h"
73
98b77773
DT		 74
75MODULE_AUTHOR("Daniele Peri <peri@csai.unipa.it>");
76MODULE_DESCRIPTION("SMC IrCC SIR/FIR controller driver");
77MODULE_LICENSE("GPL");
78
eb939922 79static bool smsc_nopnp = true;
d0d4f69b 80module_param_named(nopnp, smsc_nopnp, bool, 0);
32db9276 81MODULE_PARM_DESC(nopnp, "Do not use PNP to detect controller settings, defaults to true");
d0d4f69b 82
916f11c7
BH		 83#define DMA_INVAL 255
84static int ircc_dma = DMA_INVAL;
98b77773
DT		 85module_param(ircc_dma, int, 0);
86MODULE_PARM_DESC(ircc_dma, "DMA channel");
87
916f11c7
BH		 88#define IRQ_INVAL 255
89static int ircc_irq = IRQ_INVAL;
98b77773
DT		 90module_param(ircc_irq, int, 0);
91MODULE_PARM_DESC(ircc_irq, "IRQ line");
92
93static int ircc_fir;
94module_param(ircc_fir, int, 0);
95MODULE_PARM_DESC(ircc_fir, "FIR Base Address");
96
97static int ircc_sir;
98module_param(ircc_sir, int, 0);
99MODULE_PARM_DESC(ircc_sir, "SIR Base Address");
100
101static int ircc_cfg;
102module_param(ircc_cfg, int, 0);
103MODULE_PARM_DESC(ircc_cfg, "Configuration register base address");
104
105static int ircc_transceiver;
106module_param(ircc_transceiver, int, 0);
107MODULE_PARM_DESC(ircc_transceiver, "Transceiver type");
108
1da177e4
LT		 109/* Types */
110
c1e14a6e
LW		 111#ifdef CONFIG_PCI
112struct smsc_ircc_subsystem_configuration {
113 unsigned short vendor; /* PCI vendor ID */
114 unsigned short device; /* PCI vendor ID */
115 unsigned short subvendor; /* PCI subsystem vendor ID */
83cf0a9b 116 unsigned short subdevice; /* PCI subsystem device ID */
c1e14a6e
LW		 117 unsigned short sir_io; /* I/O port for SIR */
118 unsigned short fir_io; /* I/O port for FIR */
119 unsigned char fir_irq; /* FIR IRQ */
120 unsigned char fir_dma; /* FIR DMA */
121 unsigned short cfg_base; /* I/O port for chip configuration */
122 int (*preconfigure)(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf); /* Preconfig function */
123 const char *name; /* name shown as info */
124};
125#endif
126
1da177e4
LT		 127struct smsc_transceiver {
128 char *name;
527b6af4 129 void (*set_for_speed)(int fir_base, u32 speed);
1da177e4
LT		 130 int (*probe)(int fir_base);
131};
1da177e4
LT		 132
133struct smsc_chip {
134 char *name;
135 #if 0
136 u8 type;
137 #endif
138 u16 flags;
139 u8 devid;
140 u8 rev;
141};
1da177e4
LT		 142
143struct smsc_chip_address {
144 unsigned int cfg_base;
145 unsigned int type;
146};
1da177e4
LT		 147
148/* Private data for each instance */
149struct smsc_ircc_cb {
150 struct net_device *netdev; /* Yes! we are some kind of netdevice */
1da177e4 151 struct irlap_cb *irlap; /* The link layer we are binded to */
527b6af4 152
1da177e4
LT		 153 chipio_t io; /* IrDA controller information */
154 iobuff_t tx_buff; /* Transmit buffer */
155 iobuff_t rx_buff; /* Receive buffer */
156 dma_addr_t tx_buff_dma;
157 dma_addr_t rx_buff_dma;
158
159 struct qos_info qos; /* QoS capabilities for this device */
160
161 spinlock_t lock; /* For serializing operations */
527b6af4 162
1da177e4
LT		 163 __u32 new_speed;
164 __u32 flags; /* Interface flags */
165
166 int tx_buff_offsets[10]; /* Offsets between frames in tx_buff */
167 int tx_len; /* Number of frames in tx_buff */
168
169 int transceiver;
6bb3b2cd 170 struct platform_device *pldev;
1da177e4
LT		 171};
172
173/* Constants */
174
6bb3b2cd
DT		 175#define SMSC_IRCC2_DRIVER_NAME "smsc-ircc2"
176
1da177e4
LT		 177#define SMSC_IRCC2_C_IRDA_FALLBACK_SPEED 9600
178#define SMSC_IRCC2_C_DEFAULT_TRANSCEIVER 1
98b77773 179#define SMSC_IRCC2_C_NET_TIMEOUT 0
1da177e4
LT		 180#define SMSC_IRCC2_C_SIR_STOP 0
181
6bb3b2cd
DT		 182static const char *driver_name = SMSC_IRCC2_DRIVER_NAME;
183
1da177e4
LT		 184/* Prototypes */
185
186static int smsc_ircc_open(unsigned int firbase, unsigned int sirbase, u8 dma, u8 irq);
187static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base);
188static void smsc_ircc_setup_io(struct smsc_ircc_cb *self, unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq);
189static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self);
190static void smsc_ircc_init_chip(struct smsc_ircc_cb *self);
191static int __exit smsc_ircc_close(struct smsc_ircc_cb *self);
80a90589
DT		 192static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self);
193static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self);
1da177e4 194static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self);
6518bbb8
SH		 195static netdev_tx_t smsc_ircc_hard_xmit_sir(struct sk_buff *skb,
196 struct net_device *dev);
197static netdev_tx_t smsc_ircc_hard_xmit_fir(struct sk_buff *skb,
198 struct net_device *dev);
80a90589
DT		 199static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int bofs);
200static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self);
0fa2f491
DT		 201static void smsc_ircc_change_speed(struct smsc_ircc_cb *self, u32 speed);
202static void smsc_ircc_set_sir_speed(struct smsc_ircc_cb *self, u32 speed);
7d12e780 203static irqreturn_t smsc_ircc_interrupt(int irq, void *dev_id);
1da177e4
LT		 204static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev);
205static void smsc_ircc_sir_start(struct smsc_ircc_cb *self);
206#if SMSC_IRCC2_C_SIR_STOP
207static void smsc_ircc_sir_stop(struct smsc_ircc_cb *self);
208#endif
209static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self);
210static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len);
211static int smsc_ircc_net_open(struct net_device *dev);
212static int smsc_ircc_net_close(struct net_device *dev);
213static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
214#if SMSC_IRCC2_C_NET_TIMEOUT
215static void smsc_ircc_timeout(struct net_device *dev);
216#endif
1da177e4
LT		 217static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self);
218static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self);
219static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed);
220static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self);
221
222/* Probing */
948252cb
DM		 223static int __init smsc_ircc_look_for_chips(void);
224static const struct smsc_chip * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const struct smsc_chip *chip, char *type);
225static int __init smsc_superio_flat(const struct smsc_chip *chips, unsigned short cfg_base, char *type);
226static int __init smsc_superio_paged(const struct smsc_chip *chips, unsigned short cfg_base, char *type);
227static int __init smsc_superio_fdc(unsigned short cfg_base);
228static int __init smsc_superio_lpc(unsigned short cfg_base);
c1e14a6e 229#ifdef CONFIG_PCI
948252cb
DM		 230static int __init preconfigure_smsc_chip(struct smsc_ircc_subsystem_configuration *conf);
231static int __init preconfigure_through_82801(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf);
232static void __init preconfigure_ali_port(struct pci_dev *dev,
08d09997 233 unsigned short port);
948252cb
DM		 234static int __init preconfigure_through_ali(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf);
235static int __init smsc_ircc_preconfigure_subsystems(unsigned short ircc_cfg,
c1e14a6e
LW		 236 unsigned short ircc_fir,
237 unsigned short ircc_sir,
238 unsigned char ircc_dma,
239 unsigned char ircc_irq);
240#endif
1da177e4
LT		 241
242/* Transceivers specific functions */
243
244static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed);
245static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base);
246static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed);
247static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base);
248static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed);
249static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base);
250
251/* Power Management */
252
3ae5eaec
RK		 253static int smsc_ircc_suspend(struct platform_device *dev, pm_message_t state);
254static int smsc_ircc_resume(struct platform_device *dev);
1da177e4 255
3ae5eaec 256static struct platform_driver smsc_ircc_driver = {
6bb3b2cd
DT		 257 .suspend = smsc_ircc_suspend,
258 .resume = smsc_ircc_resume,
3ae5eaec
RK		 259 .driver = {
260 .name = SMSC_IRCC2_DRIVER_NAME,
261 },
6bb3b2cd 262};
1da177e4
LT		 263
264/* Transceivers for SMSC-ircc */
265
b6158d23 266static struct smsc_transceiver smsc_transceivers[] =
1da177e4 267{
98b77773
DT		 268 { "Toshiba Satellite 1800 (GP data pin select)", smsc_ircc_set_transceiver_toshiba_sat1800, smsc_ircc_probe_transceiver_toshiba_sat1800 },
269 { "Fast pin select", smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select, smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select },
270 { "ATC IRMode", smsc_ircc_set_transceiver_smsc_ircc_atc, smsc_ircc_probe_transceiver_smsc_ircc_atc },
271 { NULL, NULL }
1da177e4 272};
a956f4ca 273#define SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS (ARRAY_SIZE(smsc_transceivers) - 1)
1da177e4
LT		 274
275/* SMC SuperIO chipsets definitions */
276
277#define KEY55_1 0 /* SuperIO Configuration mode with Key <0x55> */
278#define KEY55_2 1 /* SuperIO Configuration mode with Key <0x55,0x55> */
279#define NoIRDA 2 /* SuperIO Chip has no IRDA Port */
280#define SIR 0 /* SuperIO Chip has only slow IRDA */
281#define FIR 4 /* SuperIO Chip has fast IRDA */
282#define SERx4 8 /* SuperIO Chip supports 115,2 KBaud * 4=460,8 KBaud */
283
b6158d23 284static struct smsc_chip __initdata fdc_chips_flat[] =
1da177e4
LT		 285{
286 /* Base address 0x3f0 or 0x370 */
287 { "37C44", KEY55_1|NoIRDA, 0x00, 0x00 }, /* This chip cannot be detected */
288 { "37C665GT", KEY55_2|NoIRDA, 0x65, 0x01 },
289 { "37C665GT", KEY55_2|NoIRDA, 0x66, 0x01 },
290 { "37C669", KEY55_2|SIR|SERx4, 0x03, 0x02 },
291 { "37C669", KEY55_2|SIR|SERx4, 0x04, 0x02 }, /* ID? */
292 { "37C78", KEY55_2|NoIRDA, 0x78, 0x00 },
293 { "37N769", KEY55_1|FIR|SERx4, 0x28, 0x00 },
294 { "37N869", KEY55_1|FIR|SERx4, 0x29, 0x00 },
295 { NULL }
296};
297
b6158d23 298static struct smsc_chip __initdata fdc_chips_paged[] =
1da177e4
LT		 299{
300 /* Base address 0x3f0 or 0x370 */
301 { "37B72X", KEY55_1|SIR|SERx4, 0x4c, 0x00 },
302 { "37B77X", KEY55_1|SIR|SERx4, 0x43, 0x00 },
303 { "37B78X", KEY55_1|SIR|SERx4, 0x44, 0x00 },
304 { "37B80X", KEY55_1|SIR|SERx4, 0x42, 0x00 },
305 { "37C67X", KEY55_1|FIR|SERx4, 0x40, 0x00 },
306 { "37C93X", KEY55_2|SIR|SERx4, 0x02, 0x01 },
307 { "37C93XAPM", KEY55_1|SIR|SERx4, 0x30, 0x01 },
308 { "37C93XFR", KEY55_2|FIR|SERx4, 0x03, 0x01 },
309 { "37M707", KEY55_1|SIR|SERx4, 0x42, 0x00 },
310 { "37M81X", KEY55_1|SIR|SERx4, 0x4d, 0x00 },
311 { "37N958FR", KEY55_1|FIR|SERx4, 0x09, 0x04 },
312 { "37N971", KEY55_1|FIR|SERx4, 0x0a, 0x00 },
313 { "37N972", KEY55_1|FIR|SERx4, 0x0b, 0x00 },
314 { NULL }
315};
316
b6158d23 317static struct smsc_chip __initdata lpc_chips_flat[] =
1da177e4
LT		 318{
319 /* Base address 0x2E or 0x4E */
320 { "47N227", KEY55_1|FIR|SERx4, 0x5a, 0x00 },
afdf27c9 321 { "47N227", KEY55_1|FIR|SERx4, 0x7a, 0x00 },
1da177e4
LT		 322 { "47N267", KEY55_1|FIR|SERx4, 0x5e, 0x00 },
323 { NULL }
324};
325
b6158d23 326static struct smsc_chip __initdata lpc_chips_paged[] =
1da177e4
LT		 327{
328 /* Base address 0x2E or 0x4E */
329 { "47B27X", KEY55_1|SIR|SERx4, 0x51, 0x00 },
330 { "47B37X", KEY55_1|SIR|SERx4, 0x52, 0x00 },
331 { "47M10X", KEY55_1|SIR|SERx4, 0x59, 0x00 },
332 { "47M120", KEY55_1|NoIRDA|SERx4, 0x5c, 0x00 },
333 { "47M13X", KEY55_1|SIR|SERx4, 0x59, 0x00 },
334 { "47M14X", KEY55_1|SIR|SERx4, 0x5f, 0x00 },
335 { "47N252", KEY55_1|FIR|SERx4, 0x0e, 0x00 },
336 { "47S42X", KEY55_1|SIR|SERx4, 0x57, 0x00 },
337 { NULL }
338};
339
340#define SMSCSIO_TYPE_FDC 1
341#define SMSCSIO_TYPE_LPC 2
342#define SMSCSIO_TYPE_FLAT 4
343#define SMSCSIO_TYPE_PAGED 8
344
b6158d23 345static struct smsc_chip_address __initdata possible_addresses[] =
1da177e4 346{
98b77773
DT		 347 { 0x3f0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
348 { 0x370, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
349 { 0xe0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
350 { 0x2e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
351 { 0x4e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
352 { 0, 0 }
1da177e4
LT		 353};
354
355/* Globals */
356
98b77773
DT		 357static struct smsc_ircc_cb *dev_self[] = { NULL, NULL };
358static unsigned short dev_count;
1da177e4
LT		 359
360static inline void register_bank(int iobase, int bank)
361{
98b77773
DT		 362 outb(((inb(iobase + IRCC_MASTER) & 0xf0) | (bank & 0x07)),
363 iobase + IRCC_MASTER);
1da177e4
LT		 364}
365
d94c77b9 366/* PNP hotplug support */
948252cb 367static const struct pnp_device_id smsc_ircc_pnp_table[] = {
d94c77b9
DB		 368 { .id = "SMCf010", .driver_data = 0 },
369 /* and presumably others */
370 { }
371};
372MODULE_DEVICE_TABLE(pnp, smsc_ircc_pnp_table);
d0d4f69b
BH		 373
374static int pnp_driver_registered;
375
7a1aa309 376#ifdef CONFIG_PNP
45ac936c 377static int smsc_ircc_pnp_probe(struct pnp_dev *dev,
1dd06ae8 378 const struct pnp_device_id *dev_id)
d0d4f69b
BH		 379{
380 unsigned int firbase, sirbase;
381 u8 dma, irq;
382
383 if (!(pnp_port_valid(dev, 0) && pnp_port_valid(dev, 1) &&
384 pnp_dma_valid(dev, 0) && pnp_irq_valid(dev, 0)))
385 return -EINVAL;
386
387 sirbase = pnp_port_start(dev, 0);
388 firbase = pnp_port_start(dev, 1);
389 dma = pnp_dma(dev, 0);
390 irq = pnp_irq(dev, 0);
391
392 if (smsc_ircc_open(firbase, sirbase, dma, irq))
393 return -ENODEV;
394
395 return 0;
396}
397
398static struct pnp_driver smsc_ircc_pnp_driver = {
399 .name = "smsc-ircc2",
400 .id_table = smsc_ircc_pnp_table,
401 .probe = smsc_ircc_pnp_probe,
402};
7a1aa309
IM		 403#else /* CONFIG_PNP */
404static struct pnp_driver smsc_ircc_pnp_driver;
405#endif
1da177e4
LT		 406
407/*******************************************************************************
408 *
409 *
410 * SMSC-ircc stuff
411 *
412 *
413 *******************************************************************************/
414
d0d4f69b
BH		 415static int __init smsc_ircc_legacy_probe(void)
416{
417 int ret = 0;
418
7c31d2f5
BH		 419#ifdef CONFIG_PCI
420 if (smsc_ircc_preconfigure_subsystems(ircc_cfg, ircc_fir, ircc_sir, ircc_dma, ircc_irq) < 0) {
421 /* Ignore errors from preconfiguration */
6c91023d
JP		 422 net_err_ratelimited("%s, Preconfiguration failed !\n",
423 driver_name);
7c31d2f5
BH		 424 }
425#endif
426
d0d4f69b 427 if (ircc_fir > 0 && ircc_sir > 0) {
6c91023d
JP		 428 net_info_ratelimited(" Overriding FIR address 0x%04x\n",
429 ircc_fir);
430 net_info_ratelimited(" Overriding SIR address 0x%04x\n",
431 ircc_sir);
d0d4f69b
BH		 432
433 if (smsc_ircc_open(ircc_fir, ircc_sir, ircc_dma, ircc_irq))
434 ret = -ENODEV;
435 } else {
436 ret = -ENODEV;
437
438 /* try user provided configuration register base address */
439 if (ircc_cfg > 0) {
6c91023d
JP		 440 net_info_ratelimited(" Overriding configuration address 0x%04x\n",
441 ircc_cfg);
d0d4f69b
BH		 442 if (!smsc_superio_fdc(ircc_cfg))
443 ret = 0;
444 if (!smsc_superio_lpc(ircc_cfg))
445 ret = 0;
446 }
447
448 if (smsc_ircc_look_for_chips() > 0)
449 ret = 0;
450 }
451 return ret;
452}
453
1da177e4
LT		 454/*
455 * Function smsc_ircc_init ()
456 *
457 * Initialize chip. Just try to find out how many chips we are dealing with
458 * and where they are
459 */
460static int __init smsc_ircc_init(void)
461{
6bb3b2cd 462 int ret;
1da177e4 463
955a9d20 464 pr_debug("%s\n", __func__);
1da177e4 465
3ae5eaec 466 ret = platform_driver_register(&smsc_ircc_driver);
6bb3b2cd 467 if (ret) {
6c91023d
JP		 468 net_err_ratelimited("%s, Can't register driver!\n",
469 driver_name);
6bb3b2cd
DT		 470 return ret;
471 }
472
98b77773 473 dev_count = 0;
527b6af4 474
d0d4f69b
BH		 475 if (smsc_nopnp || !pnp_platform_devices ||
476 ircc_cfg || ircc_fir || ircc_sir ||
477 ircc_dma != DMA_INVAL || ircc_irq != IRQ_INVAL) {
478 ret = smsc_ircc_legacy_probe();
6bb3b2cd 479 } else {
d0d4f69b
BH		 480 if (pnp_register_driver(&smsc_ircc_pnp_driver) == 0)
481 pnp_driver_registered = 1;
1da177e4 482 }
527b6af4 483
d0d4f69b
BH		 484 if (ret) {
485 if (pnp_driver_registered)
486 pnp_unregister_driver(&smsc_ircc_pnp_driver);
3ae5eaec 487 platform_driver_unregister(&smsc_ircc_driver);
d0d4f69b 488 }
527b6af4 489
1da177e4
LT		 490 return ret;
491}
492
6518bbb8
SH		 493static netdev_tx_t smsc_ircc_net_xmit(struct sk_buff *skb,
494 struct net_device *dev)
02087be6
SH		 495{
496 struct smsc_ircc_cb *self = netdev_priv(dev);
497
498 if (self->io.speed > 115200)
499 return smsc_ircc_hard_xmit_fir(skb, dev);
500 else
501 return smsc_ircc_hard_xmit_sir(skb, dev);
502}
503
504static const struct net_device_ops smsc_ircc_netdev_ops = {
505 .ndo_open = smsc_ircc_net_open,
506 .ndo_stop = smsc_ircc_net_close,
507 .ndo_do_ioctl = smsc_ircc_net_ioctl,
508 .ndo_start_xmit = smsc_ircc_net_xmit,
509#if SMSC_IRCC2_C_NET_TIMEOUT
510 .ndo_tx_timeout = smsc_ircc_timeout,
511#endif
512};
513
1da177e4
LT		 514/*
515 * Function smsc_ircc_open (firbase, sirbase, dma, irq)
516 *
517 * Try to open driver instance
518 *
519 */
45ac936c 520static int smsc_ircc_open(unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq)
1da177e4
LT		 521{
522 struct smsc_ircc_cb *self;
523 struct net_device *dev;
524 int err;
527b6af4 525
955a9d20 526 pr_debug("%s\n", __func__);
1da177e4
LT		 527
528 err = smsc_ircc_present(fir_base, sir_base);
98b77773 529 if (err)
1da177e4 530 goto err_out;
527b6af4 531
1da177e4 532 err = -ENOMEM;
a956f4ca 533 if (dev_count >= ARRAY_SIZE(dev_self)) {
6c91023d 534 net_warn_ratelimited("%s(), too many devices!\n", __func__);
1da177e4
LT		 535 goto err_out1;
536 }
537
538 /*
539 * Allocate new instance of the driver
540 */
541 dev = alloc_irdadev(sizeof(struct smsc_ircc_cb));
542 if (!dev) {
6c91023d
JP		 543 net_warn_ratelimited("%s() can't allocate net device\n",
544 __func__);
1da177e4
LT		 545 goto err_out1;
546 }
547
1da177e4 548#if SMSC_IRCC2_C_NET_TIMEOUT
98b77773 549 dev->watchdog_timeo = HZ * 2; /* Allow enough time for speed change */
1da177e4 550#endif
02087be6 551 dev->netdev_ops = &smsc_ircc_netdev_ops;
527b6af4 552
da0841a0 553 self = netdev_priv(dev);
1da177e4
LT		 554 self->netdev = dev;
555
556 /* Make ifconfig display some details */
557 dev->base_addr = self->io.fir_base = fir_base;
558 dev->irq = self->io.irq = irq;
559
560 /* Need to store self somewhere */
6bb3b2cd 561 dev_self[dev_count] = self;
1da177e4
LT		 562 spin_lock_init(&self->lock);
563
527b6af4 564 self->rx_buff.truesize = SMSC_IRCC2_RX_BUFF_TRUESIZE;
1da177e4
LT		 565 self->tx_buff.truesize = SMSC_IRCC2_TX_BUFF_TRUESIZE;
566
567 self->rx_buff.head =
ede23fa8
JP		 568 dma_zalloc_coherent(NULL, self->rx_buff.truesize,
569 &self->rx_buff_dma, GFP_KERNEL);
d0320f75 570 if (self->rx_buff.head == NULL)
1da177e4 571 goto err_out2;
1da177e4
LT		 572
573 self->tx_buff.head =
ede23fa8
JP		 574 dma_zalloc_coherent(NULL, self->tx_buff.truesize,
575 &self->tx_buff_dma, GFP_KERNEL);
d0320f75 576 if (self->tx_buff.head == NULL)
1da177e4 577 goto err_out3;
1da177e4 578
1da177e4
LT		 579 self->rx_buff.in_frame = FALSE;
580 self->rx_buff.state = OUTSIDE_FRAME;
581 self->tx_buff.data = self->tx_buff.head;
582 self->rx_buff.data = self->rx_buff.head;
527b6af4 583
1da177e4 584 smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq);
1da177e4 585 smsc_ircc_setup_qos(self);
1da177e4 586 smsc_ircc_init_chip(self);
527b6af4 587
98b77773
DT		 588 if (ircc_transceiver > 0 &&
589 ircc_transceiver < SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS)
1da177e4
LT		 590 self->transceiver = ircc_transceiver;
591 else
592 smsc_ircc_probe_transceiver(self);
593
594 err = register_netdev(self->netdev);
98b77773 595 if (err) {
6c91023d
JP		 596 net_err_ratelimited("%s, Network device registration failed!\n",
597 driver_name);
1da177e4
LT		 598 goto err_out4;
599 }
600
6bb3b2cd
DT		 601 self->pldev = platform_device_register_simple(SMSC_IRCC2_DRIVER_NAME,
602 dev_count, NULL, 0);
603 if (IS_ERR(self->pldev)) {
604 err = PTR_ERR(self->pldev);
605 goto err_out5;
606 }
3ae5eaec 607 platform_set_drvdata(self->pldev, self);
1da177e4 608
6c91023d 609 net_info_ratelimited("IrDA: Registered device %s\n", dev->name);
6bb3b2cd 610 dev_count++;
1da177e4
LT		 611
612 return 0;
98b77773 613
6bb3b2cd
DT		 614 err_out5:
615 unregister_netdev(self->netdev);
616
1da177e4
LT		 617 err_out4:
618 dma_free_coherent(NULL, self->tx_buff.truesize,
619 self->tx_buff.head, self->tx_buff_dma);
620 err_out3:
621 dma_free_coherent(NULL, self->rx_buff.truesize,
622 self->rx_buff.head, self->rx_buff_dma);
623 err_out2:
624 free_netdev(self->netdev);
6bb3b2cd 625 dev_self[dev_count] = NULL;
1da177e4
LT		 626 err_out1:
627 release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT);
628 release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT);
629 err_out:
630 return err;
631}
632
633/*
634 * Function smsc_ircc_present(fir_base, sir_base)
635 *
636 * Check the smsc-ircc chip presence
637 *
638 */
639static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base)
640{
641 unsigned char low, high, chip, config, dma, irq, version;
642
643 if (!request_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT,
644 driver_name)) {
6c91023d
JP		 645 net_warn_ratelimited("%s: can't get fir_base of 0x%03x\n",
646 __func__, fir_base);
1da177e4
LT		 647 goto out1;
648 }
649
650 if (!request_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT,
651 driver_name)) {
6c91023d
JP		 652 net_warn_ratelimited("%s: can't get sir_base of 0x%03x\n",
653 __func__, sir_base);
1da177e4
LT		 654 goto out2;
655 }
656
657 register_bank(fir_base, 3);
658
98b77773
DT		 659 high = inb(fir_base + IRCC_ID_HIGH);
660 low = inb(fir_base + IRCC_ID_LOW);
661 chip = inb(fir_base + IRCC_CHIP_ID);
662 version = inb(fir_base + IRCC_VERSION);
663 config = inb(fir_base + IRCC_INTERFACE);
1da177e4
LT		 664 dma = config & IRCC_INTERFACE_DMA_MASK;
665 irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4;
666
527b6af4 667 if (high != 0x10 || low != 0xb8 || (chip != 0xf1 && chip != 0xf2)) {
6c91023d
JP		 668 net_warn_ratelimited("%s(), addr 0x%04x - no device found!\n",
669 __func__, fir_base);
1da177e4
LT		 670 goto out3;
671 }
6c91023d
JP		 672 net_info_ratelimited("SMsC IrDA Controller found\n IrCC version %d.%d, firport 0x%03x, sirport 0x%03x dma=%d, irq=%d\n",
673 chip & 0x0f, version,
674 fir_base, sir_base, dma, irq);
1da177e4
LT		 675
676 return 0;
98b77773 677
1da177e4
LT		 678 out3:
679 release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT);
680 out2:
681 release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT);
682 out1:
683 return -ENODEV;
684}
685
686/*
687 * Function smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq)
688 *
689 * Setup I/O
690 *
691 */
527b6af4
DT		 692static void smsc_ircc_setup_io(struct smsc_ircc_cb *self,
693 unsigned int fir_base, unsigned int sir_base,
1da177e4
LT		 694 u8 dma, u8 irq)
695{
696 unsigned char config, chip_dma, chip_irq;
697
698 register_bank(fir_base, 3);
98b77773
DT		 699 config = inb(fir_base + IRCC_INTERFACE);
700 chip_dma = config & IRCC_INTERFACE_DMA_MASK;
701 chip_irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4;
1da177e4
LT		 702
703 self->io.fir_base = fir_base;
704 self->io.sir_base = sir_base;
705 self->io.fir_ext = SMSC_IRCC2_FIR_CHIP_IO_EXTENT;
706 self->io.sir_ext = SMSC_IRCC2_SIR_CHIP_IO_EXTENT;
707 self->io.fifo_size = SMSC_IRCC2_FIFO_SIZE;
708 self->io.speed = SMSC_IRCC2_C_IRDA_FALLBACK_SPEED;
709
916f11c7 710 if (irq != IRQ_INVAL) {
1da177e4 711 if (irq != chip_irq)
6c91023d
JP		 712 net_info_ratelimited("%s, Overriding IRQ - chip says %d, using %d\n",
713 driver_name, chip_irq, irq);
1da177e4 714 self->io.irq = irq;
98b77773 715 } else
1da177e4 716 self->io.irq = chip_irq;
527b6af4 717
916f11c7 718 if (dma != DMA_INVAL) {
1da177e4 719 if (dma != chip_dma)
6c91023d
JP		 720 net_info_ratelimited("%s, Overriding DMA - chip says %d, using %d\n",
721 driver_name, chip_dma, dma);
1da177e4 722 self->io.dma = dma;
98b77773 723 } else
1da177e4
LT		 724 self->io.dma = chip_dma;
725
726}
727
728/*
729 * Function smsc_ircc_setup_qos(self)
730 *
731 * Setup qos
732 *
733 */
734static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self)
735{
736 /* Initialize QoS for this device */
737 irda_init_max_qos_capabilies(&self->qos);
527b6af4 738
1da177e4
LT		 739 self->qos.baud_rate.bits = IR_9600|IR_19200|IR_38400|IR_57600|
740 IR_115200|IR_576000|IR_1152000|(IR_4000000 << 8);
741
742 self->qos.min_turn_time.bits = SMSC_IRCC2_MIN_TURN_TIME;
743 self->qos.window_size.bits = SMSC_IRCC2_WINDOW_SIZE;
744 irda_qos_bits_to_value(&self->qos);
745}
746
747/*
748 * Function smsc_ircc_init_chip(self)
749 *
750 * Init chip
751 *
752 */
753static void smsc_ircc_init_chip(struct smsc_ircc_cb *self)
754{
e812cb52 755 int iobase = self->io.fir_base;
1da177e4
LT		 756
757 register_bank(iobase, 0);
98b77773
DT		 758 outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER);
759 outb(0x00, iobase + IRCC_MASTER);
1da177e4
LT		 760
761 register_bank(iobase, 1);
e812cb52 762 outb(((inb(iobase + IRCC_SCE_CFGA) & 0x87) | IRCC_CFGA_IRDA_SIR_A),
98b77773 763 iobase + IRCC_SCE_CFGA);
1da177e4
LT		 764
765#ifdef smsc_669 /* Uses pin 88/89 for Rx/Tx */
98b77773
DT		 766 outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM),
767 iobase + IRCC_SCE_CFGB);
527b6af4 768#else
98b77773
DT		 769 outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR),
770 iobase + IRCC_SCE_CFGB);
527b6af4 771#endif
98b77773
DT		 772 (void) inb(iobase + IRCC_FIFO_THRESHOLD);
773 outb(SMSC_IRCC2_FIFO_THRESHOLD, iobase + IRCC_FIFO_THRESHOLD);
527b6af4 774
1da177e4 775 register_bank(iobase, 4);
e812cb52 776 outb((inb(iobase + IRCC_CONTROL) & 0x30), iobase + IRCC_CONTROL);
527b6af4 777
1da177e4 778 register_bank(iobase, 0);
e812cb52 779 outb(0, iobase + IRCC_LCR_A);
1da177e4
LT		 780
781 smsc_ircc_set_sir_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED);
527b6af4 782
1da177e4 783 /* Power on device */
98b77773 784 outb(0x00, iobase + IRCC_MASTER);
1da177e4
LT		 785}
786
787/*
788 * Function smsc_ircc_net_ioctl (dev, rq, cmd)
789 *
790 * Process IOCTL commands for this device
791 *
792 */
793static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
794{
795 struct if_irda_req *irq = (struct if_irda_req *) rq;
796 struct smsc_ircc_cb *self;
797 unsigned long flags;
798 int ret = 0;
799
800 IRDA_ASSERT(dev != NULL, return -1;);
801
da0841a0 802 self = netdev_priv(dev);
1da177e4
LT		 803
804 IRDA_ASSERT(self != NULL, return -1;);
805
955a9d20 806 pr_debug("%s(), %s, (cmd=0x%X)\n", __func__, dev->name, cmd);
527b6af4 807
1da177e4
LT		 808 switch (cmd) {
809 case SIOCSBANDWIDTH: /* Set bandwidth */
810 if (!capable(CAP_NET_ADMIN))
811 ret = -EPERM;
812 else {
813 /* Make sure we are the only one touching
814 * self->io.speed and the hardware - Jean II */
815 spin_lock_irqsave(&self->lock, flags);
816 smsc_ircc_change_speed(self, irq->ifr_baudrate);
817 spin_unlock_irqrestore(&self->lock, flags);
818 }
819 break;
820 case SIOCSMEDIABUSY: /* Set media busy */
821 if (!capable(CAP_NET_ADMIN)) {
822 ret = -EPERM;
823 break;
824 }
825
826 irda_device_set_media_busy(self->netdev, TRUE);
827 break;
828 case SIOCGRECEIVING: /* Check if we are receiving right now */
829 irq->ifr_receiving = smsc_ircc_is_receiving(self);
830 break;
831 #if 0
832 case SIOCSDTRRTS:
833 if (!capable(CAP_NET_ADMIN)) {
834 ret = -EPERM;
835 break;
836 }
837 smsc_ircc_sir_set_dtr_rts(dev, irq->ifr_dtr, irq->ifr_rts);
838 break;
839 #endif
840 default:
841 ret = -EOPNOTSUPP;
842 }
527b6af4 843
1da177e4
LT		 844 return ret;
845}
846
1da177e4
LT		 847#if SMSC_IRCC2_C_NET_TIMEOUT
848/*
849 * Function smsc_ircc_timeout (struct net_device *dev)
850 *
851 * The networking timeout management.
852 *
853 */
854
855static void smsc_ircc_timeout(struct net_device *dev)
856{
da0841a0 857 struct smsc_ircc_cb *self = netdev_priv(dev);
1da177e4
LT		 858 unsigned long flags;
859
6c91023d
JP		 860 net_warn_ratelimited("%s: transmit timed out, changing speed to: %d\n",
861 dev->name, self->io.speed);
1da177e4
LT		 862 spin_lock_irqsave(&self->lock, flags);
863 smsc_ircc_sir_start(self);
864 smsc_ircc_change_speed(self, self->io.speed);
860e9538 865 netif_trans_update(dev); /* prevent tx timeout */
1da177e4
LT		 866 netif_wake_queue(dev);
867 spin_unlock_irqrestore(&self->lock, flags);
868}
869#endif
870
871/*
872 * Function smsc_ircc_hard_xmit_sir (struct sk_buff *skb, struct net_device *dev)
873 *
874 * Transmits the current frame until FIFO is full, then
875 * waits until the next transmit interrupt, and continues until the
876 * frame is transmitted.
877 */
6518bbb8
SH		 878static netdev_tx_t smsc_ircc_hard_xmit_sir(struct sk_buff *skb,
879 struct net_device *dev)
1da177e4
LT		 880{
881 struct smsc_ircc_cb *self;
882 unsigned long flags;
1da177e4
LT		 883 s32 speed;
884
955a9d20 885 pr_debug("%s\n", __func__);
1da177e4 886
ec634fe3 887 IRDA_ASSERT(dev != NULL, return NETDEV_TX_OK;);
527b6af4 888
da0841a0 889 self = netdev_priv(dev);
ec634fe3 890 IRDA_ASSERT(self != NULL, return NETDEV_TX_OK;);
1da177e4 891
1da177e4 892 netif_stop_queue(dev);
527b6af4 893
1da177e4
LT		 894 /* Make sure test of self->io.speed & speed change are atomic */
895 spin_lock_irqsave(&self->lock, flags);
896
897 /* Check if we need to change the speed */
898 speed = irda_get_next_speed(skb);
98b77773 899 if (speed != self->io.speed && speed != -1) {
1da177e4
LT		 900 /* Check for empty frame */
901 if (!skb->len) {
902 /*
903 * We send frames one by one in SIR mode (no
904 * pipelining), so at this point, if we were sending
905 * a previous frame, we just received the interrupt
906 * telling us it is finished (UART_IIR_THRI).
907 * Therefore, waiting for the transmitter to really
908 * finish draining the fifo won't take too long.
909 * And the interrupt handler is not expected to run.
910 * - Jean II */
911 smsc_ircc_sir_wait_hw_transmitter_finish(self);
912 smsc_ircc_change_speed(self, speed);
913 spin_unlock_irqrestore(&self->lock, flags);
914 dev_kfree_skb(skb);
ec634fe3 915 return NETDEV_TX_OK;
1da177e4 916 }
98b77773 917 self->new_speed = speed;
1da177e4
LT		 918 }
919
920 /* Init tx buffer */
921 self->tx_buff.data = self->tx_buff.head;
922
923 /* Copy skb to tx_buff while wrapping, stuffing and making CRC */
527b6af4 924 self->tx_buff.len = async_wrap_skb(skb, self->tx_buff.data,
1da177e4 925 self->tx_buff.truesize);
527b6af4 926
af049081 927 dev->stats.tx_bytes += self->tx_buff.len;
1da177e4
LT		 928
929 /* Turn on transmit finished interrupt. Will fire immediately! */
80a90589 930 outb(UART_IER_THRI, self->io.sir_base + UART_IER);
1da177e4
LT		 931
932 spin_unlock_irqrestore(&self->lock, flags);
933
934 dev_kfree_skb(skb);
527b6af4 935
ec634fe3 936 return NETDEV_TX_OK;
1da177e4
LT		 937}
938
939/*
940 * Function smsc_ircc_set_fir_speed (self, baud)
941 *
942 * Change the speed of the device
943 *
944 */
945static void smsc_ircc_set_fir_speed(struct smsc_ircc_cb *self, u32 speed)
946{
947 int fir_base, ir_mode, ctrl, fast;
948
949 IRDA_ASSERT(self != NULL, return;);
950 fir_base = self->io.fir_base;
951
952 self->io.speed = speed;
953
98b77773 954 switch (speed) {
1da177e4 955 default:
527b6af4 956 case 576000:
1da177e4
LT		 957 ir_mode = IRCC_CFGA_IRDA_HDLC;
958 ctrl = IRCC_CRC;
959 fast = 0;
955a9d20 960 pr_debug("%s(), handling baud of 576000\n", __func__);
1da177e4
LT		 961 break;
962 case 1152000:
963 ir_mode = IRCC_CFGA_IRDA_HDLC;
964 ctrl = IRCC_1152 | IRCC_CRC;
965 fast = IRCC_LCR_A_FAST | IRCC_LCR_A_GP_DATA;
955a9d20
JP		 966 pr_debug("%s(), handling baud of 1152000\n",
967 __func__);
1da177e4
LT		 968 break;
969 case 4000000:
970 ir_mode = IRCC_CFGA_IRDA_4PPM;
971 ctrl = IRCC_CRC;
972 fast = IRCC_LCR_A_FAST;
955a9d20
JP		 973 pr_debug("%s(), handling baud of 4000000\n",
974 __func__);
1da177e4
LT		 975 break;
976 }
977 #if 0
978 Now in tranceiver!
979 /* This causes an interrupt */
980 register_bank(fir_base, 0);
98b77773 981 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast, fir_base + IRCC_LCR_A);
1da177e4 982 #endif
527b6af4 983
1da177e4 984 register_bank(fir_base, 1);
98b77773 985 outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | ir_mode), fir_base + IRCC_SCE_CFGA);
527b6af4 986
1da177e4 987 register_bank(fir_base, 4);
98b77773 988 outb((inb(fir_base + IRCC_CONTROL) & 0x30) | ctrl, fir_base + IRCC_CONTROL);
1da177e4
LT		 989}
990
991/*
992 * Function smsc_ircc_fir_start(self)
993 *
994 * Change the speed of the device
995 *
996 */
997static void smsc_ircc_fir_start(struct smsc_ircc_cb *self)
998{
999 struct net_device *dev;
1000 int fir_base;
1001
955a9d20 1002 pr_debug("%s\n", __func__);
1da177e4
LT		 1003
1004 IRDA_ASSERT(self != NULL, return;);
1005 dev = self->netdev;
1006 IRDA_ASSERT(dev != NULL, return;);
1007
1008 fir_base = self->io.fir_base;
1009
1010 /* Reset everything */
1011
1da177e4 1012 /* Clear FIFO */
98b77773 1013 outb(inb(fir_base + IRCC_LCR_A) | IRCC_LCR_A_FIFO_RESET, fir_base + IRCC_LCR_A);
1da177e4
LT		 1014
1015 /* Enable interrupt */
98b77773 1016 /*outb(IRCC_IER_ACTIVE_FRAME|IRCC_IER_EOM, fir_base + IRCC_IER);*/
1da177e4
LT		 1017
1018 register_bank(fir_base, 1);
1019
527b6af4 1020 /* Select the TX/RX interface */
1da177e4 1021#ifdef SMSC_669 /* Uses pin 88/89 for Rx/Tx */
98b77773
DT		 1022 outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM),
1023 fir_base + IRCC_SCE_CFGB);
527b6af4 1024#else
98b77773
DT		 1025 outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR),
1026 fir_base + IRCC_SCE_CFGB);
527b6af4 1027#endif
98b77773 1028 (void) inb(fir_base + IRCC_FIFO_THRESHOLD);
1da177e4
LT		 1029
1030 /* Enable SCE interrupts */
98b77773 1031 outb(0, fir_base + IRCC_MASTER);
1da177e4 1032 register_bank(fir_base, 0);
98b77773
DT		 1033 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, fir_base + IRCC_IER);
1034 outb(IRCC_MASTER_INT_EN, fir_base + IRCC_MASTER);
1da177e4
LT		 1035}
1036
1037/*
1038 * Function smsc_ircc_fir_stop(self, baud)
1039 *
1040 * Change the speed of the device
1041 *
1042 */
1043static void smsc_ircc_fir_stop(struct smsc_ircc_cb *self)
1044{
1045 int fir_base;
1046
955a9d20 1047 pr_debug("%s\n", __func__);
527b6af4 1048
1da177e4
LT		 1049 IRDA_ASSERT(self != NULL, return;);
1050
1051 fir_base = self->io.fir_base;
1052 register_bank(fir_base, 0);
98b77773
DT		 1053 /*outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER);*/
1054 outb(inb(fir_base + IRCC_LCR_B) & IRCC_LCR_B_SIP_ENABLE, fir_base + IRCC_LCR_B);
1da177e4
LT		 1055}
1056
1057
1058/*
1059 * Function smsc_ircc_change_speed(self, baud)
1060 *
1061 * Change the speed of the device
1062 *
1063 * This function *must* be called with spinlock held, because it may
1064 * be called from the irq handler. - Jean II
1065 */
0fa2f491 1066static void smsc_ircc_change_speed(struct smsc_ircc_cb *self, u32 speed)
1da177e4 1067{
1da177e4 1068 struct net_device *dev;
1da177e4 1069 int last_speed_was_sir;
527b6af4 1070
955a9d20 1071 pr_debug("%s() changing speed to: %d\n", __func__, speed);
1da177e4
LT		 1072
1073 IRDA_ASSERT(self != NULL, return;);
1074 dev = self->netdev;
1da177e4
LT		 1075
1076 last_speed_was_sir = self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED;
1077
1078 #if 0
1079 /* Temp Hack */
1080 speed= 1152000;
1081 self->io.speed = speed;
1082 last_speed_was_sir = 0;
527b6af4 1083 smsc_ircc_fir_start(self);
1da177e4 1084 #endif
527b6af4 1085
98b77773 1086 if (self->io.speed == 0)
1da177e4
LT		 1087 smsc_ircc_sir_start(self);
1088
1089 #if 0
98b77773 1090 if (!last_speed_was_sir) speed = self->io.speed;
1da177e4
LT		 1091 #endif
1092
98b77773
DT		 1093 if (self->io.speed != speed)
1094 smsc_ircc_set_transceiver_for_speed(self, speed);
1da177e4
LT		 1095
1096 self->io.speed = speed;
527b6af4 1097
98b77773
DT		 1098 if (speed <= SMSC_IRCC2_MAX_SIR_SPEED) {
1099 if (!last_speed_was_sir) {
1da177e4
LT		 1100 smsc_ircc_fir_stop(self);
1101 smsc_ircc_sir_start(self);
1102 }
527b6af4 1103 smsc_ircc_set_sir_speed(self, speed);
98b77773
DT		 1104 } else {
1105 if (last_speed_was_sir) {
527b6af4 1106 #if SMSC_IRCC2_C_SIR_STOP
1da177e4
LT		 1107 smsc_ircc_sir_stop(self);
1108 #endif
1109 smsc_ircc_fir_start(self);
1110 }
1111 smsc_ircc_set_fir_speed(self, speed);
1112
1113 #if 0
1114 self->tx_buff.len = 10;
1115 self->tx_buff.data = self->tx_buff.head;
527b6af4 1116
80a90589 1117 smsc_ircc_dma_xmit(self, 4000);
1da177e4
LT		 1118 #endif
1119 /* Be ready for incoming frames */
80a90589 1120 smsc_ircc_dma_receive(self);
1da177e4 1121 }
527b6af4 1122
1da177e4
LT		 1123 netif_wake_queue(dev);
1124}
1125
1126/*
1127 * Function smsc_ircc_set_sir_speed (self, speed)
1128 *
1129 * Set speed of IrDA port to specified baudrate
1130 *
1131 */
0e49e645 1132static void smsc_ircc_set_sir_speed(struct smsc_ircc_cb *self, __u32 speed)
1da177e4 1133{
527b6af4 1134 int iobase;
1da177e4
LT		 1135 int fcr; /* FIFO control reg */
1136 int lcr; /* Line control reg */
1137 int divisor;
1138
955a9d20 1139 pr_debug("%s(), Setting speed to: %d\n", __func__, speed);
1da177e4
LT		 1140
1141 IRDA_ASSERT(self != NULL, return;);
1142 iobase = self->io.sir_base;
527b6af4 1143
1da177e4
LT		 1144 /* Update accounting for new speed */
1145 self->io.speed = speed;
1146
1147 /* Turn off interrupts */
98b77773 1148 outb(0, iobase + UART_IER);
1da177e4 1149
98b77773 1150 divisor = SMSC_IRCC2_MAX_SIR_SPEED / speed;
527b6af4 1151
1da177e4
LT		 1152 fcr = UART_FCR_ENABLE_FIFO;
1153
527b6af4 1154 /*
1da177e4
LT		 1155 * Use trigger level 1 to avoid 3 ms. timeout delay at 9600 bps, and
1156 * almost 1,7 ms at 19200 bps. At speeds above that we can just forget
527b6af4 1157 * about this timeout since it will always be fast enough.
1da177e4 1158 */
98b77773
DT		 1159 fcr |= self->io.speed < 38400 ?
1160 UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14;
527b6af4 1161
1da177e4
LT		 1162 /* IrDA ports use 8N1 */
1163 lcr = UART_LCR_WLEN8;
527b6af4 1164
98b77773
DT		 1165 outb(UART_LCR_DLAB | lcr, iobase + UART_LCR); /* Set DLAB */
1166 outb(divisor & 0xff, iobase + UART_DLL); /* Set speed */
1167 outb(divisor >> 8, iobase + UART_DLM);
1168 outb(lcr, iobase + UART_LCR); /* Set 8N1 */
1169 outb(fcr, iobase + UART_FCR); /* Enable FIFO's */
1da177e4
LT		 1170
1171 /* Turn on interrups */
98b77773 1172 outb(UART_IER_RLSI | UART_IER_RDI | UART_IER_THRI, iobase + UART_IER);
1da177e4 1173
955a9d20 1174 pr_debug("%s() speed changed to: %d\n", __func__, speed);
1da177e4
LT		 1175}
1176
1177
1178/*
1179 * Function smsc_ircc_hard_xmit_fir (skb, dev)
1180 *
1181 * Transmit the frame!
1182 *
1183 */
6518bbb8
SH		 1184static netdev_tx_t smsc_ircc_hard_xmit_fir(struct sk_buff *skb,
1185 struct net_device *dev)
1da177e4
LT		 1186{
1187 struct smsc_ircc_cb *self;
1188 unsigned long flags;
1189 s32 speed;
1da177e4
LT		 1190 int mtt;
1191
ec634fe3 1192 IRDA_ASSERT(dev != NULL, return NETDEV_TX_OK;);
da0841a0 1193 self = netdev_priv(dev);
ec634fe3 1194 IRDA_ASSERT(self != NULL, return NETDEV_TX_OK;);
1da177e4 1195
1da177e4
LT		 1196 netif_stop_queue(dev);
1197
1198 /* Make sure test of self->io.speed & speed change are atomic */
1199 spin_lock_irqsave(&self->lock, flags);
1200
1201 /* Check if we need to change the speed after this frame */
1202 speed = irda_get_next_speed(skb);
98b77773 1203 if (speed != self->io.speed && speed != -1) {
1da177e4
LT		 1204 /* Check for empty frame */
1205 if (!skb->len) {
1206 /* Note : you should make sure that speed changes
1207 * are not going to corrupt any outgoing frame.
1208 * Look at nsc-ircc for the gory details - Jean II */
527b6af4 1209 smsc_ircc_change_speed(self, speed);
1da177e4
LT		 1210 spin_unlock_irqrestore(&self->lock, flags);
1211 dev_kfree_skb(skb);
ec634fe3 1212 return NETDEV_TX_OK;
98b77773
DT		 1213 }
1214
1215 self->new_speed = speed;
1da177e4 1216 }
527b6af4 1217
d626f62b 1218 skb_copy_from_linear_data(skb, self->tx_buff.head, skb->len);
1da177e4
LT		 1219
1220 self->tx_buff.len = skb->len;
1221 self->tx_buff.data = self->tx_buff.head;
527b6af4
DT		 1222
1223 mtt = irda_get_mtt(skb);
1da177e4
LT		 1224 if (mtt) {
1225 int bofs;
1226
527b6af4 1227 /*
1da177e4
LT		 1228 * Compute how many BOFs (STA or PA's) we need to waste the
1229 * min turn time given the speed of the link.
1230 */
1231 bofs = mtt * (self->io.speed / 1000) / 8000;
1232 if (bofs > 4095)
1233 bofs = 4095;
1234
80a90589 1235 smsc_ircc_dma_xmit(self, bofs);
1da177e4
LT		 1236 } else {
1237 /* Transmit frame */
80a90589 1238 smsc_ircc_dma_xmit(self, 0);
1da177e4 1239 }
98b77773 1240
1da177e4
LT		 1241 spin_unlock_irqrestore(&self->lock, flags);
1242 dev_kfree_skb(skb);
1243
ec634fe3 1244 return NETDEV_TX_OK;
1da177e4
LT		 1245}
1246
1247/*
80a90589 1248 * Function smsc_ircc_dma_xmit (self, bofs)
1da177e4
LT		 1249 *
1250 * Transmit data using DMA
1251 *
1252 */
80a90589 1253static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int bofs)
1da177e4 1254{
80a90589 1255 int iobase = self->io.fir_base;
1da177e4
LT		 1256 u8 ctrl;
1257
955a9d20 1258 pr_debug("%s\n", __func__);
1da177e4
LT		 1259#if 1
1260 /* Disable Rx */
1261 register_bank(iobase, 0);
98b77773 1262 outb(0x00, iobase + IRCC_LCR_B);
1da177e4
LT		 1263#endif
1264 register_bank(iobase, 1);
98b77773
DT		 1265 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1266 iobase + IRCC_SCE_CFGB);
1da177e4
LT		 1267
1268 self->io.direction = IO_XMIT;
1269
1270 /* Set BOF additional count for generating the min turn time */
1271 register_bank(iobase, 4);
98b77773
DT		 1272 outb(bofs & 0xff, iobase + IRCC_BOF_COUNT_LO);
1273 ctrl = inb(iobase + IRCC_CONTROL) & 0xf0;
1274 outb(ctrl | ((bofs >> 8) & 0x0f), iobase + IRCC_BOF_COUNT_HI);
1da177e4
LT		 1275
1276 /* Set max Tx frame size */
98b77773
DT		 1277 outb(self->tx_buff.len >> 8, iobase + IRCC_TX_SIZE_HI);
1278 outb(self->tx_buff.len & 0xff, iobase + IRCC_TX_SIZE_LO);
1da177e4
LT		 1279
1280 /*outb(UART_MCR_OUT2, self->io.sir_base + UART_MCR);*/
527b6af4 1281
1da177e4
LT		 1282 /* Enable burst mode chip Tx DMA */
1283 register_bank(iobase, 1);
98b77773
DT		 1284 outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |
1285 IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB);
1da177e4
LT		 1286
1287 /* Setup DMA controller (must be done after enabling chip DMA) */
1288 irda_setup_dma(self->io.dma, self->tx_buff_dma, self->tx_buff.len,
1289 DMA_TX_MODE);
1290
1291 /* Enable interrupt */
1292
1293 register_bank(iobase, 0);
98b77773
DT		 1294 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1295 outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER);
527b6af4 1296
1da177e4 1297 /* Enable transmit */
98b77773 1298 outb(IRCC_LCR_B_SCE_TRANSMIT | IRCC_LCR_B_SIP_ENABLE, iobase + IRCC_LCR_B);
1da177e4
LT		 1299}
1300
1301/*
1302 * Function smsc_ircc_dma_xmit_complete (self)
1303 *
527b6af4 1304 * The transfer of a frame in finished. This function will only be called
1da177e4
LT		 1305 * by the interrupt handler
1306 *
1307 */
80a90589 1308static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self)
1da177e4 1309{
80a90589
DT		 1310 int iobase = self->io.fir_base;
1311
955a9d20 1312 pr_debug("%s\n", __func__);
1da177e4
LT		 1313#if 0
1314 /* Disable Tx */
1315 register_bank(iobase, 0);
98b77773 1316 outb(0x00, iobase + IRCC_LCR_B);
1da177e4 1317#endif
80a90589
DT		 1318 register_bank(iobase, 1);
1319 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1320 iobase + IRCC_SCE_CFGB);
1da177e4
LT		 1321
1322 /* Check for underrun! */
1323 register_bank(iobase, 0);
98b77773 1324 if (inb(iobase + IRCC_LSR) & IRCC_LSR_UNDERRUN) {
af049081
SH		 1325 self->netdev->stats.tx_errors++;
1326 self->netdev->stats.tx_fifo_errors++;
1da177e4
LT		 1327
1328 /* Reset error condition */
1329 register_bank(iobase, 0);
98b77773
DT		 1330 outb(IRCC_MASTER_ERROR_RESET, iobase + IRCC_MASTER);
1331 outb(0x00, iobase + IRCC_MASTER);
1da177e4 1332 } else {
af049081
SH		 1333 self->netdev->stats.tx_packets++;
1334 self->netdev->stats.tx_bytes += self->tx_buff.len;
1da177e4
LT		 1335 }
1336
1337 /* Check if it's time to change the speed */
1338 if (self->new_speed) {
527b6af4 1339 smsc_ircc_change_speed(self, self->new_speed);
1da177e4
LT		 1340 self->new_speed = 0;
1341 }
1342
1343 netif_wake_queue(self->netdev);
1344}
1345
1346/*
1347 * Function smsc_ircc_dma_receive(self)
1348 *
1349 * Get ready for receiving a frame. The device will initiate a DMA
1350 * if it starts to receive a frame.
1351 *
1352 */
80a90589 1353static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self)
1da177e4 1354{
80a90589 1355 int iobase = self->io.fir_base;
1da177e4
LT		 1356#if 0
1357 /* Turn off chip DMA */
1358 register_bank(iobase, 1);
98b77773
DT		 1359 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1360 iobase + IRCC_SCE_CFGB);
1da177e4 1361#endif
527b6af4 1362
1da177e4
LT		 1363 /* Disable Tx */
1364 register_bank(iobase, 0);
98b77773 1365 outb(0x00, iobase + IRCC_LCR_B);
1da177e4
LT		 1366
1367 /* Turn off chip DMA */
1368 register_bank(iobase, 1);
98b77773
DT		 1369 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1370 iobase + IRCC_SCE_CFGB);
1da177e4
LT		 1371
1372 self->io.direction = IO_RECV;
1373 self->rx_buff.data = self->rx_buff.head;
1374
1375 /* Set max Rx frame size */
1376 register_bank(iobase, 4);
98b77773
DT		 1377 outb((2050 >> 8) & 0x0f, iobase + IRCC_RX_SIZE_HI);
1378 outb(2050 & 0xff, iobase + IRCC_RX_SIZE_LO);
1da177e4
LT		 1379
1380 /* Setup DMA controller */
1381 irda_setup_dma(self->io.dma, self->rx_buff_dma, self->rx_buff.truesize,
1382 DMA_RX_MODE);
1383
1384 /* Enable burst mode chip Rx DMA */
1385 register_bank(iobase, 1);
98b77773
DT		 1386 outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |
1387 IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB);
1da177e4
LT		 1388
1389 /* Enable interrupt */
1390 register_bank(iobase, 0);
98b77773
DT		 1391 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1392 outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER);
1da177e4
LT		 1393
1394 /* Enable receiver */
1395 register_bank(iobase, 0);
527b6af4 1396 outb(IRCC_LCR_B_SCE_RECEIVE | IRCC_LCR_B_SIP_ENABLE,
98b77773 1397 iobase + IRCC_LCR_B);
527b6af4 1398
1da177e4
LT		 1399 return 0;
1400}
1401
1402/*
80a90589 1403 * Function smsc_ircc_dma_receive_complete(self)
1da177e4
LT		 1404 *
1405 * Finished with receiving frames
1406 *
1407 */
80a90589 1408static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self)
1da177e4
LT		 1409{
1410 struct sk_buff *skb;
1411 int len, msgcnt, lsr;
80a90589 1412 int iobase = self->io.fir_base;
527b6af4 1413
1da177e4 1414 register_bank(iobase, 0);
527b6af4 1415
955a9d20 1416 pr_debug("%s\n", __func__);
1da177e4
LT		 1417#if 0
1418 /* Disable Rx */
1419 register_bank(iobase, 0);
98b77773 1420 outb(0x00, iobase + IRCC_LCR_B);
1da177e4
LT		 1421#endif
1422 register_bank(iobase, 0);
98b77773
DT		 1423 outb(inb(iobase + IRCC_LSAR) & ~IRCC_LSAR_ADDRESS_MASK, iobase + IRCC_LSAR);
1424 lsr= inb(iobase + IRCC_LSR);
1425 msgcnt = inb(iobase + IRCC_LCR_B) & 0x08;
1da177e4 1426
955a9d20
JP		 1427 pr_debug("%s: dma count = %d\n", __func__,
1428 get_dma_residue(self->io.dma));
1da177e4
LT		 1429
1430 len = self->rx_buff.truesize - get_dma_residue(self->io.dma);
1431
98b77773
DT		 1432 /* Look for errors */
1433 if (lsr & (IRCC_LSR_FRAME_ERROR | IRCC_LSR_CRC_ERROR | IRCC_LSR_SIZE_ERROR)) {
af049081 1434 self->netdev->stats.rx_errors++;
98b77773 1435 if (lsr & IRCC_LSR_FRAME_ERROR)
af049081 1436 self->netdev->stats.rx_frame_errors++;
98b77773 1437 if (lsr & IRCC_LSR_CRC_ERROR)
af049081 1438 self->netdev->stats.rx_crc_errors++;
98b77773 1439 if (lsr & IRCC_LSR_SIZE_ERROR)
af049081 1440 self->netdev->stats.rx_length_errors++;
98b77773 1441 if (lsr & (IRCC_LSR_UNDERRUN | IRCC_LSR_OVERRUN))
af049081 1442 self->netdev->stats.rx_length_errors++;
1da177e4
LT		 1443 return;
1444 }
98b77773 1445
1da177e4 1446 /* Remove CRC */
98b77773 1447 len -= self->io.speed < 4000000 ? 2 : 4;
1da177e4 1448
98b77773 1449 if (len < 2 || len > 2050) {
6c91023d 1450 net_warn_ratelimited("%s(), bogus len=%d\n", __func__, len);
1da177e4
LT		 1451 return;
1452 }
955a9d20 1453 pr_debug("%s: msgcnt = %d, len=%d\n", __func__, msgcnt, len);
1da177e4 1454
98b77773 1455 skb = dev_alloc_skb(len + 1);
6c91023d 1456 if (!skb)
1da177e4 1457 return;
6c91023d 1458
1da177e4 1459 /* Make sure IP header gets aligned */
527b6af4 1460 skb_reserve(skb, 1);
1da177e4
LT		 1461
1462 memcpy(skb_put(skb, len), self->rx_buff.data, len);
af049081
SH		 1463 self->netdev->stats.rx_packets++;
1464 self->netdev->stats.rx_bytes += len;
1da177e4
LT		 1465
1466 skb->dev = self->netdev;
459a98ed 1467 skb_reset_mac_header(skb);
1da177e4
LT		 1468 skb->protocol = htons(ETH_P_IRDA);
1469 netif_rx(skb);
1470}
1471
1472/*
1473 * Function smsc_ircc_sir_receive (self)
1474 *
1475 * Receive one frame from the infrared port
1476 *
1477 */
527b6af4 1478static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self)
1da177e4
LT		 1479{
1480 int boguscount = 0;
1481 int iobase;
1482
1483 IRDA_ASSERT(self != NULL, return;);
1484
1485 iobase = self->io.sir_base;
1486
527b6af4
DT		 1487 /*
1488 * Receive all characters in Rx FIFO, unwrap and unstuff them.
1489 * async_unwrap_char will deliver all found frames
1da177e4
LT		 1490 */
1491 do {
af049081 1492 async_unwrap_char(self->netdev, &self->netdev->stats, &self->rx_buff,
98b77773 1493 inb(iobase + UART_RX));
1da177e4
LT		 1494
1495 /* Make sure we don't stay here to long */
1496 if (boguscount++ > 32) {
955a9d20 1497 pr_debug("%s(), breaking!\n", __func__);
1da177e4
LT		 1498 break;
1499 }
98b77773 1500 } while (inb(iobase + UART_LSR) & UART_LSR_DR);
1da177e4
LT		 1501}
1502
1503
1504/*
1505 * Function smsc_ircc_interrupt (irq, dev_id, regs)
1506 *
1507 * An interrupt from the chip has arrived. Time to do some work
1508 *
1509 */
28fc1f5a 1510static irqreturn_t smsc_ircc_interrupt(int dummy, void *dev_id)
1da177e4 1511{
28fc1f5a
JG		 1512 struct net_device *dev = dev_id;
1513 struct smsc_ircc_cb *self = netdev_priv(dev);
1da177e4
LT		 1514 int iobase, iir, lcra, lsr;
1515 irqreturn_t ret = IRQ_NONE;
1516
1da177e4 1517 /* Serialise the interrupt handler in various CPUs, stop Tx path */
527b6af4 1518 spin_lock(&self->lock);
1da177e4
LT		 1519
1520 /* Check if we should use the SIR interrupt handler */
98b77773 1521 if (self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED) {
1da177e4
LT		 1522 ret = smsc_ircc_interrupt_sir(dev);
1523 goto irq_ret_unlock;
1524 }
1525
1526 iobase = self->io.fir_base;
1527
1528 register_bank(iobase, 0);
98b77773 1529 iir = inb(iobase + IRCC_IIR);
527b6af4 1530 if (iir == 0)
1da177e4
LT		 1531 goto irq_ret_unlock;
1532 ret = IRQ_HANDLED;
1533
1534 /* Disable interrupts */
98b77773
DT		 1535 outb(0, iobase + IRCC_IER);
1536 lcra = inb(iobase + IRCC_LCR_A);
1537 lsr = inb(iobase + IRCC_LSR);
527b6af4 1538
955a9d20 1539 pr_debug("%s(), iir = 0x%02x\n", __func__, iir);
1da177e4
LT		 1540
1541 if (iir & IRCC_IIR_EOM) {
1542 if (self->io.direction == IO_RECV)
80a90589 1543 smsc_ircc_dma_receive_complete(self);
1da177e4 1544 else
80a90589 1545 smsc_ircc_dma_xmit_complete(self);
527b6af4 1546
80a90589 1547 smsc_ircc_dma_receive(self);
1da177e4
LT		 1548 }
1549
1550 if (iir & IRCC_IIR_ACTIVE_FRAME) {
a97a6f10 1551 /*printk(KERN_WARNING "%s(): Active Frame\n", __func__);*/
1da177e4
LT		 1552 }
1553
1554 /* Enable interrupts again */
1555
1556 register_bank(iobase, 0);
98b77773 1557 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1da177e4
LT		 1558
1559 irq_ret_unlock:
1560 spin_unlock(&self->lock);
28fc1f5a 1561
1da177e4
LT		 1562 return ret;
1563}
1564
1565/*
7d12e780 1566 * Function irport_interrupt_sir (irq, dev_id)
1da177e4
LT		 1567 *
1568 * Interrupt handler for SIR modes
1569 */
1570static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev)
1571{
da0841a0 1572 struct smsc_ircc_cb *self = netdev_priv(dev);
1da177e4
LT		 1573 int boguscount = 0;
1574 int iobase;
1575 int iir, lsr;
1576
25985edc 1577 /* Already locked coming here in smsc_ircc_interrupt() */
1da177e4
LT		 1578 /*spin_lock(&self->lock);*/
1579
1580 iobase = self->io.sir_base;
1581
98b77773 1582 iir = inb(iobase + UART_IIR) & UART_IIR_ID;
1da177e4
LT		 1583 if (iir == 0)
1584 return IRQ_NONE;
1585 while (iir) {
1586 /* Clear interrupt */
98b77773 1587 lsr = inb(iobase + UART_LSR);
1da177e4 1588
955a9d20
JP		 1589 pr_debug("%s(), iir=%02x, lsr=%02x, iobase=%#x\n",
1590 __func__, iir, lsr, iobase);
1da177e4
LT		 1591
1592 switch (iir) {
1593 case UART_IIR_RLSI:
955a9d20 1594 pr_debug("%s(), RLSI\n", __func__);
1da177e4
LT		 1595 break;
1596 case UART_IIR_RDI:
1597 /* Receive interrupt */
1598 smsc_ircc_sir_receive(self);
1599 break;
1600 case UART_IIR_THRI:
1601 if (lsr & UART_LSR_THRE)
1602 /* Transmitter ready for data */
1603 smsc_ircc_sir_write_wakeup(self);
1604 break;
1605 default:
955a9d20
JP		 1606 pr_debug("%s(), unhandled IIR=%#x\n",
1607 __func__, iir);
1da177e4 1608 break;
527b6af4
DT		 1609 }
1610
1da177e4
LT		 1611 /* Make sure we don't stay here to long */
1612 if (boguscount++ > 100)
1613 break;
1614
527b6af4 1615 iir = inb(iobase + UART_IIR) & UART_IIR_ID;
1da177e4
LT		 1616 }
1617 /*spin_unlock(&self->lock);*/
1618 return IRQ_HANDLED;
1619}
1620
1621
1622#if 0 /* unused */
1623/*
1624 * Function ircc_is_receiving (self)
1625 *
1626 * Return TRUE is we are currently receiving a frame
1627 *
1628 */
1629static int ircc_is_receiving(struct smsc_ircc_cb *self)
1630{
1631 int status = FALSE;
1632 /* int iobase; */
1633
955a9d20 1634 pr_debug("%s\n", __func__);
1da177e4
LT		 1635
1636 IRDA_ASSERT(self != NULL, return FALSE;);
1637
955a9d20
JP		 1638 pr_debug("%s: dma count = %d\n", __func__,
1639 get_dma_residue(self->io.dma));
1da177e4
LT		 1640
1641 status = (self->rx_buff.state != OUTSIDE_FRAME);
527b6af4 1642
1da177e4
LT		 1643 return status;
1644}
1645#endif /* unused */
1646
e812cb52
DT		 1647static int smsc_ircc_request_irq(struct smsc_ircc_cb *self)
1648{
1649 int error;
1650
1651 error = request_irq(self->io.irq, smsc_ircc_interrupt, 0,
1652 self->netdev->name, self->netdev);
1653 if (error)
955a9d20
JP		 1654 pr_debug("%s(), unable to allocate irq=%d, err=%d\n",
1655 __func__, self->io.irq, error);
e812cb52
DT		 1656
1657 return error;
1658}
1659
1660static void smsc_ircc_start_interrupts(struct smsc_ircc_cb *self)
1661{
1662 unsigned long flags;
1663
1664 spin_lock_irqsave(&self->lock, flags);
1665
1666 self->io.speed = 0;
1667 smsc_ircc_change_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED);
1668
1669 spin_unlock_irqrestore(&self->lock, flags);
1670}
1671
1672static void smsc_ircc_stop_interrupts(struct smsc_ircc_cb *self)
1673{
1674 int iobase = self->io.fir_base;
1675 unsigned long flags;
1676
1677 spin_lock_irqsave(&self->lock, flags);
1678
1679 register_bank(iobase, 0);
1680 outb(0, iobase + IRCC_IER);
1681 outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER);
1682 outb(0x00, iobase + IRCC_MASTER);
1683
1684 spin_unlock_irqrestore(&self->lock, flags);
1685}
1686
1da177e4
LT		 1687
1688/*
1689 * Function smsc_ircc_net_open (dev)
1690 *
1691 * Start the device
1692 *
1693 */
1694static int smsc_ircc_net_open(struct net_device *dev)
1695{
1696 struct smsc_ircc_cb *self;
1da177e4 1697 char hwname[16];
1da177e4 1698
955a9d20 1699 pr_debug("%s\n", __func__);
527b6af4 1700
1da177e4 1701 IRDA_ASSERT(dev != NULL, return -1;);
da0841a0 1702 self = netdev_priv(dev);
1da177e4 1703 IRDA_ASSERT(self != NULL, return 0;);
527b6af4 1704
e812cb52 1705 if (self->io.suspended) {
955a9d20 1706 pr_debug("%s(), device is suspended\n", __func__);
e812cb52
DT		 1707 return -EAGAIN;
1708 }
1709
527b6af4 1710 if (request_irq(self->io.irq, smsc_ircc_interrupt, 0, dev->name,
1da177e4 1711 (void *) dev)) {
955a9d20
JP		 1712 pr_debug("%s(), unable to allocate irq=%d\n",
1713 __func__, self->io.irq);
1da177e4
LT		 1714 return -EAGAIN;
1715 }
1716
e812cb52 1717 smsc_ircc_start_interrupts(self);
527b6af4 1718
1da177e4
LT		 1719 /* Give self a hardware name */
1720 /* It would be cool to offer the chip revision here - Jean II */
1721 sprintf(hwname, "SMSC @ 0x%03x", self->io.fir_base);
1722
527b6af4 1723 /*
1da177e4 1724 * Open new IrLAP layer instance, now that everything should be
527b6af4 1725 * initialized properly
1da177e4
LT		 1726 */
1727 self->irlap = irlap_open(dev, &self->qos, hwname);
1728
1729 /*
1730 * Always allocate the DMA channel after the IRQ,
1731 * and clean up on failure.
1732 */
1733 if (request_dma(self->io.dma, dev->name)) {
1734 smsc_ircc_net_close(dev);
1735
6c91023d
JP		 1736 net_warn_ratelimited("%s(), unable to allocate DMA=%d\n",
1737 __func__, self->io.dma);
1da177e4
LT		 1738 return -EAGAIN;
1739 }
527b6af4 1740
1da177e4
LT		 1741 netif_start_queue(dev);
1742
1743 return 0;
1744}
1745
1746/*
1747 * Function smsc_ircc_net_close (dev)
1748 *
1749 * Stop the device
1750 *
1751 */
1752static int smsc_ircc_net_close(struct net_device *dev)
1753{
1754 struct smsc_ircc_cb *self;
1da177e4 1755
955a9d20 1756 pr_debug("%s\n", __func__);
527b6af4 1757
1da177e4 1758 IRDA_ASSERT(dev != NULL, return -1;);
da0841a0 1759 self = netdev_priv(dev);
1da177e4 1760 IRDA_ASSERT(self != NULL, return 0;);
527b6af4 1761
1da177e4
LT		 1762 /* Stop device */
1763 netif_stop_queue(dev);
527b6af4 1764
1da177e4
LT		 1765 /* Stop and remove instance of IrLAP */
1766 if (self->irlap)
1767 irlap_close(self->irlap);
1768 self->irlap = NULL;
1769
e812cb52
DT		 1770 smsc_ircc_stop_interrupts(self);
1771
1772 /* if we are called from smsc_ircc_resume we don't have IRQ reserved */
1773 if (!self->io.suspended)
1774 free_irq(self->io.irq, dev);
1775
1da177e4 1776 disable_dma(self->io.dma);
1da177e4
LT		 1777 free_dma(self->io.dma);
1778
1779 return 0;
1780}
1781
3ae5eaec 1782static int smsc_ircc_suspend(struct platform_device *dev, pm_message_t state)
1da177e4 1783{
3ae5eaec 1784 struct smsc_ircc_cb *self = platform_get_drvdata(dev);
6bb3b2cd 1785
9480e307 1786 if (!self->io.suspended) {
955a9d20 1787 pr_debug("%s, Suspending\n", driver_name);
e812cb52
DT		 1788
1789 rtnl_lock();
1790 if (netif_running(self->netdev)) {
1791 netif_device_detach(self->netdev);
1792 smsc_ircc_stop_interrupts(self);
1793 free_irq(self->io.irq, self->netdev);
1794 disable_dma(self->io.dma);
1795 }
98b77773 1796 self->io.suspended = 1;
e812cb52 1797 rtnl_unlock();
98b77773 1798 }
6bb3b2cd
DT		 1799
1800 return 0;
1da177e4
LT		 1801}
1802
3ae5eaec 1803static int smsc_ircc_resume(struct platform_device *dev)
1da177e4 1804{
3ae5eaec 1805 struct smsc_ircc_cb *self = platform_get_drvdata(dev);
1da177e4 1806
9480e307 1807 if (self->io.suspended) {
955a9d20 1808 pr_debug("%s, Waking up\n", driver_name);
e812cb52
DT		 1809
1810 rtnl_lock();
1811 smsc_ircc_init_chip(self);
1812 if (netif_running(self->netdev)) {
1813 if (smsc_ircc_request_irq(self)) {
1814 /*
1815 * Don't fail resume process, just kill this
1816 * network interface
1817 */
1818 unregister_netdevice(self->netdev);
1819 } else {
1820 enable_dma(self->io.dma);
1821 smsc_ircc_start_interrupts(self);
1822 netif_device_attach(self->netdev);
1823 }
1824 }
6bb3b2cd 1825 self->io.suspended = 0;
e812cb52 1826 rtnl_unlock();
6bb3b2cd 1827 }
1da177e4
LT		 1828 return 0;
1829}
1830
1831/*
1832 * Function smsc_ircc_close (self)
1833 *
1834 * Close driver instance
1835 *
1836 */
1837static int __exit smsc_ircc_close(struct smsc_ircc_cb *self)
1838{
955a9d20 1839 pr_debug("%s\n", __func__);
1da177e4
LT		 1840
1841 IRDA_ASSERT(self != NULL, return -1;);
1842
6bb3b2cd 1843 platform_device_unregister(self->pldev);
1da177e4
LT		 1844
1845 /* Remove netdevice */
1846 unregister_netdev(self->netdev);
1847
e812cb52 1848 smsc_ircc_stop_interrupts(self);
1da177e4
LT		 1849
1850 /* Release the PORTS that this driver is using */
955a9d20
JP		 1851 pr_debug("%s(), releasing 0x%03x\n", __func__,
1852 self->io.fir_base);
1da177e4
LT		 1853
1854 release_region(self->io.fir_base, self->io.fir_ext);
1855
955a9d20
JP		 1856 pr_debug("%s(), releasing 0x%03x\n", __func__,
1857 self->io.sir_base);
1da177e4
LT		 1858
1859 release_region(self->io.sir_base, self->io.sir_ext);
1860
1861 if (self->tx_buff.head)
1862 dma_free_coherent(NULL, self->tx_buff.truesize,
1863 self->tx_buff.head, self->tx_buff_dma);
527b6af4 1864
1da177e4
LT		 1865 if (self->rx_buff.head)
1866 dma_free_coherent(NULL, self->rx_buff.truesize,
1867 self->rx_buff.head, self->rx_buff_dma);
1868
1869 free_netdev(self->netdev);
1870
1871 return 0;
1872}
1873
1874static void __exit smsc_ircc_cleanup(void)
1875{
1876 int i;
1877
955a9d20 1878 pr_debug("%s\n", __func__);
1da177e4 1879
98b77773 1880 for (i = 0; i < 2; i++) {
1da177e4
LT		 1881 if (dev_self[i])
1882 smsc_ircc_close(dev_self[i]);
1883 }
6bb3b2cd 1884
d0d4f69b
BH		 1885 if (pnp_driver_registered)
1886 pnp_unregister_driver(&smsc_ircc_pnp_driver);
1887
3ae5eaec 1888 platform_driver_unregister(&smsc_ircc_driver);
1da177e4
LT		 1889}
1890
1891/*
1892 * Start SIR operations
1893 *
1894 * This function *must* be called with spinlock held, because it may
1895 * be called from the irq handler (via smsc_ircc_change_speed()). - Jean II
1896 */
0e49e645 1897static void smsc_ircc_sir_start(struct smsc_ircc_cb *self)
1da177e4
LT		 1898{
1899 struct net_device *dev;
1900 int fir_base, sir_base;
1901
955a9d20 1902 pr_debug("%s\n", __func__);
1da177e4 1903
527b6af4 1904 IRDA_ASSERT(self != NULL, return;);
98b77773 1905 dev = self->netdev;
527b6af4 1906 IRDA_ASSERT(dev != NULL, return;);
1da177e4
LT		 1907
1908 fir_base = self->io.fir_base;
1909 sir_base = self->io.sir_base;
1910
1911 /* Reset everything */
98b77773 1912 outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER);
1da177e4
LT		 1913
1914 #if SMSC_IRCC2_C_SIR_STOP
1915 /*smsc_ircc_sir_stop(self);*/
1916 #endif
1917
1918 register_bank(fir_base, 1);
98b77773 1919 outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | IRCC_CFGA_IRDA_SIR_A), fir_base + IRCC_SCE_CFGA);
1da177e4
LT		 1920
1921 /* Initialize UART */
98b77773
DT		 1922 outb(UART_LCR_WLEN8, sir_base + UART_LCR); /* Reset DLAB */
1923 outb((UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2), sir_base + UART_MCR);
527b6af4 1924
1da177e4 1925 /* Turn on interrups */
98b77773 1926 outb(UART_IER_RLSI | UART_IER_RDI |UART_IER_THRI, sir_base + UART_IER);
1da177e4 1927
955a9d20 1928 pr_debug("%s() - exit\n", __func__);
1da177e4 1929
98b77773 1930 outb(0x00, fir_base + IRCC_MASTER);
1da177e4
LT		 1931}
1932
1933#if SMSC_IRCC2_C_SIR_STOP
1934void smsc_ircc_sir_stop(struct smsc_ircc_cb *self)
1935{
1936 int iobase;
1937
955a9d20 1938 pr_debug("%s\n", __func__);
1da177e4
LT		 1939 iobase = self->io.sir_base;
1940
1941 /* Reset UART */
98b77773 1942 outb(0, iobase + UART_MCR);
527b6af4 1943
1da177e4 1944 /* Turn off interrupts */
98b77773 1945 outb(0, iobase + UART_IER);
1da177e4
LT		 1946}
1947#endif
1948
1949/*
1950 * Function smsc_sir_write_wakeup (self)
1951 *
1952 * Called by the SIR interrupt handler when there's room for more data.
1953 * If we have more packets to send, we send them here.
1954 *
1955 */
1956static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self)
1957{
1958 int actual = 0;
1959 int iobase;
1960 int fcr;
1961
1962 IRDA_ASSERT(self != NULL, return;);
1963
955a9d20 1964 pr_debug("%s\n", __func__);
1da177e4
LT		 1965
1966 iobase = self->io.sir_base;
1967
1968 /* Finished with frame? */
1969 if (self->tx_buff.len > 0) {
1970 /* Write data left in transmit buffer */
527b6af4 1971 actual = smsc_ircc_sir_write(iobase, self->io.fifo_size,
1da177e4
LT		 1972 self->tx_buff.data, self->tx_buff.len);
1973 self->tx_buff.data += actual;
1974 self->tx_buff.len -= actual;
1975 } else {
527b6af4 1976
1da177e4 1977 /*if (self->tx_buff.len ==0) {*/
527b6af4
DT		 1978
1979 /*
1980 * Now serial buffer is almost free & we can start
1da177e4
LT		 1981 * transmission of another packet. But first we must check
1982 * if we need to change the speed of the hardware
1983 */
1984 if (self->new_speed) {
955a9d20
JP		 1985 pr_debug("%s(), Changing speed to %d.\n",
1986 __func__, self->new_speed);
1da177e4
LT		 1987 smsc_ircc_sir_wait_hw_transmitter_finish(self);
1988 smsc_ircc_change_speed(self, self->new_speed);
1989 self->new_speed = 0;
1990 } else {
1991 /* Tell network layer that we want more frames */
1992 netif_wake_queue(self->netdev);
1993 }
af049081 1994 self->netdev->stats.tx_packets++;
1da177e4 1995
98b77773
DT		 1996 if (self->io.speed <= 115200) {
1997 /*
1998 * Reset Rx FIFO to make sure that all reflected transmit data
1999 * is discarded. This is needed for half duplex operation
2000 */
2001 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR;
2002 fcr |= self->io.speed < 38400 ?
2003 UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14;
1da177e4 2004
98b77773 2005 outb(fcr, iobase + UART_FCR);
1da177e4 2006
98b77773
DT		 2007 /* Turn on receive interrupts */
2008 outb(UART_IER_RDI, iobase + UART_IER);
1da177e4
LT		 2009 }
2010 }
2011}
2012
2013/*
2014 * Function smsc_ircc_sir_write (iobase, fifo_size, buf, len)
2015 *
2016 * Fill Tx FIFO with transmit data
2017 *
2018 */
2019static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len)
2020{
2021 int actual = 0;
527b6af4 2022
1da177e4 2023 /* Tx FIFO should be empty! */
98b77773 2024 if (!(inb(iobase + UART_LSR) & UART_LSR_THRE)) {
6c91023d
JP		 2025 net_warn_ratelimited("%s(), failed, fifo not empty!\n",
2026 __func__);
1da177e4
LT		 2027 return 0;
2028 }
527b6af4 2029
1da177e4 2030 /* Fill FIFO with current frame */
98b77773 2031 while (fifo_size-- > 0 && actual < len) {
1da177e4 2032 /* Transmit next byte */
98b77773 2033 outb(buf[actual], iobase + UART_TX);
1da177e4
LT		 2034 actual++;
2035 }
2036 return actual;
2037}
2038
2039/*
2040 * Function smsc_ircc_is_receiving (self)
2041 *
2042 * Returns true is we are currently receiving data
2043 *
2044 */
2045static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self)
2046{
807540ba 2047 return self->rx_buff.state != OUTSIDE_FRAME;
1da177e4
LT		 2048}
2049
2050
2051/*
2052 * Function smsc_ircc_probe_transceiver(self)
2053 *
2054 * Tries to find the used Transceiver
2055 *
2056 */
2057static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self)
2058{
2059 unsigned int i;
527b6af4 2060
1da177e4 2061 IRDA_ASSERT(self != NULL, return;);
527b6af4 2062
98b77773
DT		 2063 for (i = 0; smsc_transceivers[i].name != NULL; i++)
2064 if (smsc_transceivers[i].probe(self->io.fir_base)) {
6c91023d
JP		 2065 net_info_ratelimited(" %s transceiver found\n",
2066 smsc_transceivers[i].name);
98b77773 2067 self->transceiver= i + 1;
1da177e4
LT		 2068 return;
2069 }
98b77773 2070
6c91023d
JP		 2071 net_info_ratelimited("No transceiver found. Defaulting to %s\n",
2072 smsc_transceivers[SMSC_IRCC2_C_DEFAULT_TRANSCEIVER].name);
527b6af4 2073
98b77773 2074 self->transceiver = SMSC_IRCC2_C_DEFAULT_TRANSCEIVER;
1da177e4
LT		 2075}
2076
2077
2078/*
2079 * Function smsc_ircc_set_transceiver_for_speed(self, speed)
2080 *
2081 * Set the transceiver according to the speed
2082 *
2083 */
2084static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed)
2085{
2086 unsigned int trx;
527b6af4 2087
1da177e4 2088 trx = self->transceiver;
98b77773
DT		 2089 if (trx > 0)
2090 smsc_transceivers[trx - 1].set_for_speed(self->io.fir_base, speed);
1da177e4
LT		 2091}
2092
2093/*
2094 * Function smsc_ircc_wait_hw_transmitter_finish ()
2095 *
2096 * Wait for the real end of HW transmission
2097 *
2098 * The UART is a strict FIFO, and we get called only when we have finished
2099 * pushing data to the FIFO, so the maximum amount of time we must wait
2100 * is only for the FIFO to drain out.
2101 *
2102 * We use a simple calibrated loop. We may need to adjust the loop
2103 * delay (udelay) to balance I/O traffic and latency. And we also need to
2104 * adjust the maximum timeout.
2105 * It would probably be better to wait for the proper interrupt,
2106 * but it doesn't seem to be available.
2107 *
2108 * We can't use jiffies or kernel timers because :
2109 * 1) We are called from the interrupt handler, which disable softirqs,
2110 * so jiffies won't be increased
2111 * 2) Jiffies granularity is usually very coarse (10ms), and we don't
2112 * want to wait that long to detect stuck hardware.
2113 * Jean II
2114 */
2115
2116static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self)
2117{
98b77773 2118 int iobase = self->io.sir_base;
1da177e4 2119 int count = SMSC_IRCC2_HW_TRANSMITTER_TIMEOUT_US;
527b6af4 2120
1da177e4 2121 /* Calibrated busy loop */
98b77773 2122 while (count-- > 0 && !(inb(iobase + UART_LSR) & UART_LSR_TEMT))
1da177e4
LT		 2123 udelay(1);
2124
adbf7f01 2125 if (count < 0)
955a9d20 2126 pr_debug("%s(): stuck transmitter\n", __func__);
1da177e4
LT		 2127}
2128
2129
2130/* PROBING
2131 *
d94c77b9
DB		 2132 * REVISIT we can be told about the device by PNP, and should use that info
2133 * instead of probing hardware and creating a platform_device ...
1da177e4
LT		 2134 */
2135
2136static int __init smsc_ircc_look_for_chips(void)
2137{
b6158d23 2138 struct smsc_chip_address *address;
98b77773 2139 char *type;
1da177e4 2140 unsigned int cfg_base, found;
527b6af4 2141
1da177e4
LT		 2142 found = 0;
2143 address = possible_addresses;
527b6af4 2144
98b77773 2145 while (address->cfg_base) {
1da177e4 2146 cfg_base = address->cfg_base;
527b6af4 2147
a97a6f10 2148 /*printk(KERN_WARNING "%s(): probing: 0x%02x for: 0x%02x\n", __func__, cfg_base, address->type);*/
527b6af4 2149
98b77773 2150 if (address->type & SMSCSIO_TYPE_FDC) {
1da177e4 2151 type = "FDC";
98b77773
DT		 2152 if (address->type & SMSCSIO_TYPE_FLAT)
2153 if (!smsc_superio_flat(fdc_chips_flat, cfg_base, type))
2154 found++;
2155
2156 if (address->type & SMSCSIO_TYPE_PAGED)
2157 if (!smsc_superio_paged(fdc_chips_paged, cfg_base, type))
2158 found++;
1da177e4 2159 }
98b77773 2160 if (address->type & SMSCSIO_TYPE_LPC) {
1da177e4 2161 type = "LPC";
98b77773
DT		 2162 if (address->type & SMSCSIO_TYPE_FLAT)
2163 if (!smsc_superio_flat(lpc_chips_flat, cfg_base, type))
2164 found++;
2165
2166 if (address->type & SMSCSIO_TYPE_PAGED)
2167 if (!smsc_superio_paged(lpc_chips_paged, cfg_base, type))
2168 found++;
1da177e4
LT		 2169 }
2170 address++;
2171 }
2172 return found;
527b6af4 2173}
1da177e4
LT		 2174
2175/*
2176 * Function smsc_superio_flat (chip, base, type)
2177 *
2178 * Try to get configuration of a smc SuperIO chip with flat register model
2179 *
2180 */
b6158d23 2181static int __init smsc_superio_flat(const struct smsc_chip *chips, unsigned short cfgbase, char *type)
1da177e4
LT		 2182{
2183 unsigned short firbase, sirbase;
2184 u8 mode, dma, irq;
2185 int ret = -ENODEV;
2186
955a9d20 2187 pr_debug("%s\n", __func__);
1da177e4 2188
98b77773 2189 if (smsc_ircc_probe(cfgbase, SMSCSIOFLAT_DEVICEID_REG, chips, type) == NULL)
1da177e4
LT		 2190 return ret;
2191
2192 outb(SMSCSIOFLAT_UARTMODE0C_REG, cfgbase);
98b77773 2193 mode = inb(cfgbase + 1);
527b6af4 2194
a97a6f10 2195 /*printk(KERN_WARNING "%s(): mode: 0x%02x\n", __func__, mode);*/
527b6af4 2196
98b77773 2197 if (!(mode & SMSCSIOFLAT_UART2MODE_VAL_IRDA))
6c91023d 2198 net_warn_ratelimited("%s(): IrDA not enabled\n", __func__);
1da177e4
LT		 2199
2200 outb(SMSCSIOFLAT_UART2BASEADDR_REG, cfgbase);
98b77773 2201 sirbase = inb(cfgbase + 1) << 2;
1da177e4 2202
527b6af4 2203 /* FIR iobase */
1da177e4 2204 outb(SMSCSIOFLAT_FIRBASEADDR_REG, cfgbase);
98b77773 2205 firbase = inb(cfgbase + 1) << 3;
1da177e4
LT		 2206
2207 /* DMA */
2208 outb(SMSCSIOFLAT_FIRDMASELECT_REG, cfgbase);
98b77773 2209 dma = inb(cfgbase + 1) & SMSCSIOFLAT_FIRDMASELECT_MASK;
527b6af4 2210
1da177e4
LT		 2211 /* IRQ */
2212 outb(SMSCSIOFLAT_UARTIRQSELECT_REG, cfgbase);
98b77773 2213 irq = inb(cfgbase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK;
1da177e4 2214
6c91023d
JP		 2215 net_info_ratelimited("%s(): fir: 0x%02x, sir: 0x%02x, dma: %02d, irq: %d, mode: 0x%02x\n",
2216 __func__, firbase, sirbase, dma, irq, mode);
1da177e4 2217
98b77773
DT		 2218 if (firbase && smsc_ircc_open(firbase, sirbase, dma, irq) == 0)
2219 ret = 0;
527b6af4 2220
1da177e4
LT		 2221 /* Exit configuration */
2222 outb(SMSCSIO_CFGEXITKEY, cfgbase);
2223
2224 return ret;
2225}
2226
2227/*
2228 * Function smsc_superio_paged (chip, base, type)
2229 *
2230 * Try to get configuration of a smc SuperIO chip with paged register model
2231 *
2232 */
b6158d23 2233static int __init smsc_superio_paged(const struct smsc_chip *chips, unsigned short cfg_base, char *type)
1da177e4
LT		 2234{
2235 unsigned short fir_io, sir_io;
2236 int ret = -ENODEV;
527b6af4 2237
955a9d20 2238 pr_debug("%s\n", __func__);
1da177e4 2239
98b77773 2240 if (smsc_ircc_probe(cfg_base, 0x20, chips, type) == NULL)
1da177e4 2241 return ret;
527b6af4 2242
1da177e4
LT		 2243 /* Select logical device (UART2) */
2244 outb(0x07, cfg_base);
2245 outb(0x05, cfg_base + 1);
527b6af4 2246
1da177e4
LT		 2247 /* SIR iobase */
2248 outb(0x60, cfg_base);
98b77773 2249 sir_io = inb(cfg_base + 1) << 8;
1da177e4
LT		 2250 outb(0x61, cfg_base);
2251 sir_io |= inb(cfg_base + 1);
527b6af4 2252
1da177e4
LT		 2253 /* Read FIR base */
2254 outb(0x62, cfg_base);
2255 fir_io = inb(cfg_base + 1) << 8;
2256 outb(0x63, cfg_base);
2257 fir_io |= inb(cfg_base + 1);
2258 outb(0x2b, cfg_base); /* ??? */
2259
98b77773
DT		 2260 if (fir_io && smsc_ircc_open(fir_io, sir_io, ircc_dma, ircc_irq) == 0)
2261 ret = 0;
527b6af4 2262
1da177e4
LT		 2263 /* Exit configuration */
2264 outb(SMSCSIO_CFGEXITKEY, cfg_base);
2265
2266 return ret;
2267}
2268
2269
948252cb 2270static int __init smsc_access(unsigned short cfg_base, unsigned char reg)
1da177e4 2271{
955a9d20 2272 pr_debug("%s\n", __func__);
1da177e4
LT		 2273
2274 outb(reg, cfg_base);
98b77773 2275 return inb(cfg_base) != reg ? -1 : 0;
1da177e4
LT		 2276}
2277
948252cb 2278static const struct smsc_chip * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const struct smsc_chip *chip, char *type)
1da177e4 2279{
98b77773 2280 u8 devid, xdevid, rev;
1da177e4 2281
955a9d20 2282 pr_debug("%s\n", __func__);
1da177e4
LT		 2283
2284 /* Leave configuration */
2285
2286 outb(SMSCSIO_CFGEXITKEY, cfg_base);
2287
2288 if (inb(cfg_base) == SMSCSIO_CFGEXITKEY) /* not a smc superio chip */
2289 return NULL;
2290
2291 outb(reg, cfg_base);
2292
98b77773 2293 xdevid = inb(cfg_base + 1);
1da177e4
LT		 2294
2295 /* Enter configuration */
2296
2297 outb(SMSCSIO_CFGACCESSKEY, cfg_base);
2298
2299 #if 0
2300 if (smsc_access(cfg_base,0x55)) /* send second key and check */
2301 return NULL;
2302 #endif
527b6af4 2303
1da177e4
LT		 2304 /* probe device ID */
2305
98b77773 2306 if (smsc_access(cfg_base, reg))
1da177e4
LT		 2307 return NULL;
2308
98b77773 2309 devid = inb(cfg_base + 1);
527b6af4 2310
98b77773 2311 if (devid == 0 || devid == 0xff) /* typical values for unused port */
1da177e4
LT		 2312 return NULL;
2313
2314 /* probe revision ID */
2315
98b77773 2316 if (smsc_access(cfg_base, reg + 1))
1da177e4
LT		 2317 return NULL;
2318
98b77773 2319 rev = inb(cfg_base + 1);
1da177e4 2320
98b77773 2321 if (rev >= 128) /* i think this will make no sense */
1da177e4
LT		 2322 return NULL;
2323
98b77773 2324 if (devid == xdevid) /* protection against false positives */
1da177e4
LT		 2325 return NULL;
2326
2327 /* Check for expected device ID; are there others? */
2328
98b77773 2329 while (chip->devid != devid) {
1da177e4
LT		 2330
2331 chip++;
2332
98b77773 2333 if (chip->name == NULL)
1da177e4
LT		 2334 return NULL;
2335 }
2336
6c91023d
JP		 2337 net_info_ratelimited("found SMC SuperIO Chip (devid=0x%02x rev=%02X base=0x%04x): %s%s\n",
2338 devid, rev, cfg_base, type, chip->name);
1da177e4 2339
98b77773 2340 if (chip->rev > rev) {
6c91023d 2341 net_info_ratelimited("Revision higher than expected\n");
1da177e4
LT		 2342 return NULL;
2343 }
527b6af4 2344
98b77773 2345 if (chip->flags & NoIRDA)
6c91023d 2346 net_info_ratelimited("chipset does not support IRDA\n");
1da177e4
LT		 2347
2348 return chip;
2349}
2350
2351static int __init smsc_superio_fdc(unsigned short cfg_base)
2352{
2353 int ret = -1;
2354
2355 if (!request_region(cfg_base, 2, driver_name)) {
6c91023d
JP		 2356 net_warn_ratelimited("%s: can't get cfg_base of 0x%03x\n",
2357 __func__, cfg_base);
1da177e4 2358 } else {
98b77773
DT		 2359 if (!smsc_superio_flat(fdc_chips_flat, cfg_base, "FDC") ||
2360 !smsc_superio_paged(fdc_chips_paged, cfg_base, "FDC"))
1da177e4
LT		 2361 ret = 0;
2362
2363 release_region(cfg_base, 2);
2364 }
2365
2366 return ret;
2367}
2368
2369static int __init smsc_superio_lpc(unsigned short cfg_base)
2370{
2371 int ret = -1;
2372
2373 if (!request_region(cfg_base, 2, driver_name)) {
6c91023d
JP		 2374 net_warn_ratelimited("%s: can't get cfg_base of 0x%03x\n",
2375 __func__, cfg_base);
1da177e4 2376 } else {
98b77773
DT		 2377 if (!smsc_superio_flat(lpc_chips_flat, cfg_base, "LPC") ||
2378 !smsc_superio_paged(lpc_chips_paged, cfg_base, "LPC"))
1da177e4 2379 ret = 0;
98b77773 2380
1da177e4
LT		 2381 release_region(cfg_base, 2);
2382 }
2383 return ret;
2384}
2385
c1e14a6e
LW		 2386/*
2387 * Look for some specific subsystem setups that need
2388 * pre-configuration not properly done by the BIOS (especially laptops)
2389 * This code is based in part on smcinit.c, tosh1800-smcinit.c
2390 * and tosh2450-smcinit.c. The table lists the device entries
08d09997
LW		 2391 * for ISA bridges with an LPC (Low Pin Count) controller which
2392 * handles the communication with the SMSC device. After the LPC
2393 * controller is initialized through PCI, the SMSC device is initialized
2394 * through a dedicated port in the ISA port-mapped I/O area, this latter
2395 * area is used to configure the SMSC device with default
2396 * SIR and FIR I/O ports, DMA and IRQ. Different vendors have
2397 * used different sets of parameters and different control port
2398 * addresses making a subsystem device table necessary.
c1e14a6e
LW		 2399 */
2400#ifdef CONFIG_PCI
948252cb 2401static struct smsc_ircc_subsystem_configuration subsystem_configurations[] __initdata = {
895de090
LWLE		 2402 /*
2403 * Subsystems needing entries:
2404 * 0x10b9:0x1533 0x103c:0x0850 HP nx9010 family
2405 * 0x10b9:0x1533 0x0e11:0x005a Compaq nc4000 family
2406 * 0x8086:0x24cc 0x0e11:0x002a HP nx9000 family
2407 */
2408 {
2409 /* Guessed entry */
5ee5a07c 2410 .vendor = PCI_VENDOR_ID_INTEL, /* Intel 82801DBM LPC bridge */
895de090
LWLE		 2411 .device = 0x24cc,
2412 .subvendor = 0x103c,
2413 .subdevice = 0x08bc,
2414 .sir_io = 0x02f8,
2415 .fir_io = 0x0130,
2416 .fir_irq = 0x05,
2417 .fir_dma = 0x03,
2418 .cfg_base = 0x004e,
2419 .preconfigure = preconfigure_through_82801,
2420 .name = "HP nx5000 family",
2421 },
c1e14a6e 2422 {
5ee5a07c 2423 .vendor = PCI_VENDOR_ID_INTEL, /* Intel 82801DBM LPC bridge */
c1e14a6e
LW		 2424 .device = 0x24cc,
2425 .subvendor = 0x103c,
2426 .subdevice = 0x088c,
08d09997
LW		 2427 /* Quite certain these are the same for nc8000 as for nc6000 */
2428 .sir_io = 0x02f8,
c1e14a6e 2429 .fir_io = 0x0130,
08d09997 2430 .fir_irq = 0x05,
c1e14a6e
LW		 2431 .fir_dma = 0x03,
2432 .cfg_base = 0x004e,
2433 .preconfigure = preconfigure_through_82801,
895de090 2434 .name = "HP nc8000 family",
c1e14a6e
LW		 2435 },
2436 {
5ee5a07c 2437 .vendor = PCI_VENDOR_ID_INTEL, /* Intel 82801DBM LPC bridge */
c1e14a6e
LW		 2438 .device = 0x24cc,
2439 .subvendor = 0x103c,
2440 .subdevice = 0x0890,
2441 .sir_io = 0x02f8,
2442 .fir_io = 0x0130,
08d09997 2443 .fir_irq = 0x05,
c1e14a6e
LW		 2444 .fir_dma = 0x03,
2445 .cfg_base = 0x004e,
2446 .preconfigure = preconfigure_through_82801,
895de090
LWLE		 2447 .name = "HP nc6000 family",
2448 },
2449 {
5ee5a07c 2450 .vendor = PCI_VENDOR_ID_INTEL, /* Intel 82801DBM LPC bridge */
895de090
LWLE		 2451 .device = 0x24cc,
2452 .subvendor = 0x0e11,
2453 .subdevice = 0x0860,
2454 /* I assume these are the same for x1000 as for the others */
2455 .sir_io = 0x02e8,
2456 .fir_io = 0x02f8,
2457 .fir_irq = 0x07,
2458 .fir_dma = 0x03,
2459 .cfg_base = 0x002e,
2460 .preconfigure = preconfigure_through_82801,
2461 .name = "Compaq x1000 family",
c1e14a6e
LW		 2462 },
2463 {
08d09997 2464 /* Intel 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge */
5ee5a07c 2465 .vendor = PCI_VENDOR_ID_INTEL,
c1e14a6e
LW		 2466 .device = 0x24c0,
2467 .subvendor = 0x1179,
08d09997 2468 .subdevice = 0xffff, /* 0xffff is "any" */
c1e14a6e
LW		 2469 .sir_io = 0x03f8,
2470 .fir_io = 0x0130,
2471 .fir_irq = 0x07,
2472 .fir_dma = 0x01,
2473 .cfg_base = 0x002e,
2474 .preconfigure = preconfigure_through_82801,
08d09997 2475 .name = "Toshiba laptop with Intel 82801DB/DBL LPC bridge",
c1e14a6e
LW		 2476 },
2477 {
5ee5a07c 2478 .vendor = PCI_VENDOR_ID_INTEL, /* Intel 82801CAM ISA bridge */
08d09997 2479 .device = 0x248c,
c1e14a6e 2480 .subvendor = 0x1179,
08d09997 2481 .subdevice = 0xffff, /* 0xffff is "any" */
c1e14a6e
LW		 2482 .sir_io = 0x03f8,
2483 .fir_io = 0x0130,
2484 .fir_irq = 0x03,
2485 .fir_dma = 0x03,
2486 .cfg_base = 0x002e,
2487 .preconfigure = preconfigure_through_82801,
08d09997 2488 .name = "Toshiba laptop with Intel 82801CAM ISA bridge",
c1e14a6e
LW		 2489 },
2490 {
08d09997 2491 /* 82801DBM (ICH4-M) LPC Interface Bridge */
5ee5a07c 2492 .vendor = PCI_VENDOR_ID_INTEL,
08d09997
LW		 2493 .device = 0x24cc,
2494 .subvendor = 0x1179,
2495 .subdevice = 0xffff, /* 0xffff is "any" */
2496 .sir_io = 0x03f8,
2497 .fir_io = 0x0130,
2498 .fir_irq = 0x03,
2499 .fir_dma = 0x03,
2500 .cfg_base = 0x002e,
2501 .preconfigure = preconfigure_through_82801,
2502 .name = "Toshiba laptop with Intel 8281DBM LPC bridge",
2503 },
2504 {
2505 /* ALi M1533/M1535 PCI to ISA Bridge [Aladdin IV/V/V+] */
5ee5a07c 2506 .vendor = PCI_VENDOR_ID_AL,
c1e14a6e
LW		 2507 .device = 0x1533,
2508 .subvendor = 0x1179,
08d09997 2509 .subdevice = 0xffff, /* 0xffff is "any" */
c1e14a6e
LW		 2510 .sir_io = 0x02e8,
2511 .fir_io = 0x02f8,
2512 .fir_irq = 0x07,
2513 .fir_dma = 0x03,
2514 .cfg_base = 0x002e,
2515 .preconfigure = preconfigure_through_ali,
08d09997 2516 .name = "Toshiba laptop with ALi ISA bridge",
c1e14a6e
LW		 2517 },
2518 { } // Terminator
2519};
2520
2521
2522/*
08d09997
LW		 2523 * This sets up the basic SMSC parameters
2524 * (FIR port, SIR port, FIR DMA, FIR IRQ)
c1e14a6e
LW		 2525 * through the chip configuration port.
2526 */
948252cb 2527static int __init preconfigure_smsc_chip(struct
08d09997
LW		 2528 smsc_ircc_subsystem_configuration
2529 *conf)
c1e14a6e
LW		 2530{
2531 unsigned short iobase = conf->cfg_base;
2532 unsigned char tmpbyte;
2533
2534 outb(LPC47N227_CFGACCESSKEY, iobase); // enter configuration state
2535 outb(SMSCSIOFLAT_DEVICEID_REG, iobase); // set for device ID
2536 tmpbyte = inb(iobase +1); // Read device ID
955a9d20
JP		 2537 pr_debug("Detected Chip id: 0x%02x, setting up registers...\n",
2538 tmpbyte);
c1e14a6e
LW		 2539
2540 /* Disable UART1 and set up SIR I/O port */
2541 outb(0x24, iobase); // select CR24 - UART1 base addr
2542 outb(0x00, iobase + 1); // disable UART1
2543 outb(SMSCSIOFLAT_UART2BASEADDR_REG, iobase); // select CR25 - UART2 base addr
2544 outb( (conf->sir_io >> 2), iobase + 1); // bits 2-9 of 0x3f8
2545 tmpbyte = inb(iobase + 1);
2546 if (tmpbyte != (conf->sir_io >> 2) ) {
6c91023d
JP		 2547 net_warn_ratelimited("ERROR: could not configure SIR ioport\n");
2548 net_warn_ratelimited("Try to supply ircc_cfg argument\n");
c1e14a6e
LW		 2549 return -ENXIO;
2550 }
2551
2552 /* Set up FIR IRQ channel for UART2 */
2553 outb(SMSCSIOFLAT_UARTIRQSELECT_REG, iobase); // select CR28 - UART1,2 IRQ select
2554 tmpbyte = inb(iobase + 1);
2555 tmpbyte &= SMSCSIOFLAT_UART1IRQSELECT_MASK; // Do not touch the UART1 portion
2556 tmpbyte |= (conf->fir_irq & SMSCSIOFLAT_UART2IRQSELECT_MASK);
2557 outb(tmpbyte, iobase + 1);
2558 tmpbyte = inb(iobase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK;
2559 if (tmpbyte != conf->fir_irq) {
6c91023d 2560 net_warn_ratelimited("ERROR: could not configure FIR IRQ channel\n");
c1e14a6e
LW		 2561 return -ENXIO;
2562 }
2563
2564 /* Set up FIR I/O port */
2565 outb(SMSCSIOFLAT_FIRBASEADDR_REG, iobase); // CR2B - SCE (FIR) base addr
2566 outb((conf->fir_io >> 3), iobase + 1);
2567 tmpbyte = inb(iobase + 1);
2568 if (tmpbyte != (conf->fir_io >> 3) ) {
6c91023d 2569 net_warn_ratelimited("ERROR: could not configure FIR I/O port\n");
c1e14a6e
LW		 2570 return -ENXIO;
2571 }
2572
2573 /* Set up FIR DMA channel */
2574 outb(SMSCSIOFLAT_FIRDMASELECT_REG, iobase); // CR2C - SCE (FIR) DMA select
2575 outb((conf->fir_dma & LPC47N227_FIRDMASELECT_MASK), iobase + 1); // DMA
2576 tmpbyte = inb(iobase + 1) & LPC47N227_FIRDMASELECT_MASK;
2577 if (tmpbyte != (conf->fir_dma & LPC47N227_FIRDMASELECT_MASK)) {
6c91023d 2578 net_warn_ratelimited("ERROR: could not configure FIR DMA channel\n");
c1e14a6e
LW		 2579 return -ENXIO;
2580 }
2581
2582 outb(SMSCSIOFLAT_UARTMODE0C_REG, iobase); // CR0C - UART mode
2583 tmpbyte = inb(iobase + 1);
08d09997
LW		 2584 tmpbyte &= ~SMSCSIOFLAT_UART2MODE_MASK |
2585 SMSCSIOFLAT_UART2MODE_VAL_IRDA;
c1e14a6e
LW		 2586 outb(tmpbyte, iobase + 1); // enable IrDA (HPSIR) mode, high speed
2587
2588 outb(LPC47N227_APMBOOTDRIVE_REG, iobase); // CR07 - Auto Pwr Mgt/boot drive sel
2589 tmpbyte = inb(iobase + 1);
2590 outb(tmpbyte | LPC47N227_UART2AUTOPWRDOWN_MASK, iobase + 1); // enable UART2 autopower down
2591
2592 /* This one was not part of tosh1800 */
2593 outb(0x0a, iobase); // CR0a - ecp fifo / ir mux
2594 tmpbyte = inb(iobase + 1);
2595 outb(tmpbyte | 0x40, iobase + 1); // send active device to ir port
2596
2597 outb(LPC47N227_UART12POWER_REG, iobase); // CR02 - UART 1,2 power
2598 tmpbyte = inb(iobase + 1);
2599 outb(tmpbyte | LPC47N227_UART2POWERDOWN_MASK, iobase + 1); // UART2 power up mode, UART1 power down
2600
2601 outb(LPC47N227_FDCPOWERVALIDCONF_REG, iobase); // CR00 - FDC Power/valid config cycle
2602 tmpbyte = inb(iobase + 1);
2603 outb(tmpbyte | LPC47N227_VALID_MASK, iobase + 1); // valid config cycle done
2604
2605 outb(LPC47N227_CFGEXITKEY, iobase); // Exit configuration
2606
2607 return 0;
2608}
2609
08d09997 2610/* 82801CAM generic registers */
c1e14a6e
LW		 2611#define VID 0x00
2612#define DID 0x02
08d09997
LW		 2613#define PIRQ_A_D_ROUT 0x60
2614#define SIRQ_CNTL 0x64
2615#define PIRQ_E_H_ROUT 0x68
c1e14a6e 2616#define PCI_DMA_C 0x90
08d09997 2617/* LPC-specific registers */
c1e14a6e 2618#define COM_DEC 0xe0
08d09997 2619#define GEN1_DEC 0xe4
c1e14a6e
LW		 2620#define LPC_EN 0xe6
2621#define GEN2_DEC 0xec
2622/*
08d09997
LW		 2623 * Sets up the I/O range using the 82801CAM ISA bridge, 82801DBM LPC bridge
2624 * or Intel 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge.
2625 * They all work the same way!
c1e14a6e 2626 */
948252cb 2627static int __init preconfigure_through_82801(struct pci_dev *dev,
08d09997
LW		 2628 struct
2629 smsc_ircc_subsystem_configuration
2630 *conf)
c1e14a6e
LW		 2631{
2632 unsigned short tmpword;
08d09997 2633 unsigned char tmpbyte;
c1e14a6e 2634
6c91023d 2635 net_info_ratelimited("Setting up Intel 82801 controller and SMSC device\n");
08d09997
LW		 2636 /*
2637 * Select the range for the COMA COM port (SIR)
2638 * Register COM_DEC:
2639 * Bit 7: reserved
2640 * Bit 6-4, COMB decode range
2641 * Bit 3: reserved
2642 * Bit 2-0, COMA decode range
2643 *
2644 * Decode ranges:
2645 * 000 = 0x3f8-0x3ff (COM1)
2646 * 001 = 0x2f8-0x2ff (COM2)
2647 * 010 = 0x220-0x227
2648 * 011 = 0x228-0x22f
2649 * 100 = 0x238-0x23f
2650 * 101 = 0x2e8-0x2ef (COM4)
2651 * 110 = 0x338-0x33f
2652 * 111 = 0x3e8-0x3ef (COM3)
2653 */
2654 pci_read_config_byte(dev, COM_DEC, &tmpbyte);
2655 tmpbyte &= 0xf8; /* mask COMA bits */
2656 switch(conf->sir_io) {
2657 case 0x3f8:
2658 tmpbyte |= 0x00;
2659 break;
2660 case 0x2f8:
2661 tmpbyte |= 0x01;
2662 break;
2663 case 0x220:
2664 tmpbyte |= 0x02;
2665 break;
2666 case 0x228:
2667 tmpbyte |= 0x03;
2668 break;
2669 case 0x238:
2670 tmpbyte |= 0x04;
2671 break;
2672 case 0x2e8:
2673 tmpbyte |= 0x05;
2674 break;
2675 case 0x338:
2676 tmpbyte |= 0x06;
2677 break;
2678 case 0x3e8:
2679 tmpbyte |= 0x07;
2680 break;
2681 default:
2682 tmpbyte |= 0x01; /* COM2 default */
2683 }
955a9d20 2684 pr_debug("COM_DEC (write): 0x%02x\n", tmpbyte);
08d09997 2685 pci_write_config_byte(dev, COM_DEC, tmpbyte);
c1e14a6e 2686
08d09997
LW		 2687 /* Enable Low Pin Count interface */
2688 pci_read_config_word(dev, LPC_EN, &tmpword);
2689 /* These seem to be set up at all times,
2690 * just make sure it is properly set.
2691 */
2692 switch(conf->cfg_base) {
2693 case 0x04e:
2694 tmpword |= 0x2000;
2695 break;
2696 case 0x02e:
2697 tmpword |= 0x1000;
2698 break;
2699 case 0x062:
2700 tmpword |= 0x0800;
2701 break;
2702 case 0x060:
2703 tmpword |= 0x0400;
2704 break;
2705 default:
6c91023d
JP		 2706 net_warn_ratelimited("Uncommon I/O base address: 0x%04x\n",
2707 conf->cfg_base);
08d09997
LW		 2708 break;
2709 }
2710 tmpword &= 0xfffd; /* disable LPC COMB */
2711 tmpword |= 0x0001; /* set bit 0 : enable LPC COMA addr range (GEN2) */
955a9d20 2712 pr_debug("LPC_EN (write): 0x%04x\n", tmpword);
c1e14a6e
LW		 2713 pci_write_config_word(dev, LPC_EN, tmpword);
2714
08d09997
LW		 2715 /*
2716 * Configure LPC DMA channel
2717 * PCI_DMA_C bits:
2718 * Bit 15-14: DMA channel 7 select
2719 * Bit 13-12: DMA channel 6 select
2720 * Bit 11-10: DMA channel 5 select
2721 * Bit 9-8: Reserved
2722 * Bit 7-6: DMA channel 3 select
2723 * Bit 5-4: DMA channel 2 select
2724 * Bit 3-2: DMA channel 1 select
2725 * Bit 1-0: DMA channel 0 select
2726 * 00 = Reserved value
2727 * 01 = PC/PCI DMA
2728 * 10 = Reserved value
2729 * 11 = LPC I/F DMA
2730 */
2731 pci_read_config_word(dev, PCI_DMA_C, &tmpword);
2732 switch(conf->fir_dma) {
2733 case 0x07:
2734 tmpword |= 0xc000;
2735 break;
2736 case 0x06:
2737 tmpword |= 0x3000;
2738 break;
2739 case 0x05:
2740 tmpword |= 0x0c00;
2741 break;
2742 case 0x03:
2743 tmpword |= 0x00c0;
2744 break;
2745 case 0x02:
2746 tmpword |= 0x0030;
2747 break;
2748 case 0x01:
2749 tmpword |= 0x000c;
2750 break;
2751 case 0x00:
2752 tmpword |= 0x0003;
2753 break;
2754 default:
2755 break; /* do not change settings */
2756 }
955a9d20 2757 pr_debug("PCI_DMA_C (write): 0x%04x\n", tmpword);
08d09997
LW		 2758 pci_write_config_word(dev, PCI_DMA_C, tmpword);
2759
2760 /*
2761 * GEN2_DEC bits:
2762 * Bit 15-4: Generic I/O range
2763 * Bit 3-1: reserved (read as 0)
2764 * Bit 0: enable GEN2 range on LPC I/F
2765 */
2766 tmpword = conf->fir_io & 0xfff8;
2767 tmpword |= 0x0001;
955a9d20 2768 pr_debug("GEN2_DEC (write): 0x%04x\n", tmpword);
08d09997 2769 pci_write_config_word(dev, GEN2_DEC, tmpword);
c1e14a6e
LW		 2770
2771 /* Pre-configure chip */
08d09997
LW		 2772 return preconfigure_smsc_chip(conf);
2773}
c1e14a6e 2774
08d09997
LW		 2775/*
2776 * Pre-configure a certain port on the ALi 1533 bridge.
2777 * This is based on reverse-engineering since ALi does not
2778 * provide any data sheet for the 1533 chip.
2779 */
948252cb 2780static void __init preconfigure_ali_port(struct pci_dev *dev,
08d09997
LW		 2781 unsigned short port)
2782{
2783 unsigned char reg;
2784 /* These bits obviously control the different ports */
2785 unsigned char mask;
2786 unsigned char tmpbyte;
2787
2788 switch(port) {
2789 case 0x0130:
2790 case 0x0178:
2791 reg = 0xb0;
2792 mask = 0x80;
2793 break;
2794 case 0x03f8:
2795 reg = 0xb4;
2796 mask = 0x80;
2797 break;
2798 case 0x02f8:
2799 reg = 0xb4;
2800 mask = 0x30;
2801 break;
2802 case 0x02e8:
2803 reg = 0xb4;
2804 mask = 0x08;
2805 break;
2806 default:
6c91023d
JP		 2807 net_err_ratelimited("Failed to configure unsupported port on ALi 1533 bridge: 0x%04x\n",
2808 port);
08d09997
LW		 2809 return;
2810 }
2811
2812 pci_read_config_byte(dev, reg, &tmpbyte);
2813 /* Turn on the right bits */
2814 tmpbyte |= mask;
2815 pci_write_config_byte(dev, reg, tmpbyte);
6c91023d
JP		 2816 net_info_ratelimited("Activated ALi 1533 ISA bridge port 0x%04x\n",
2817 port);
c1e14a6e
LW		 2818}
2819
948252cb 2820static int __init preconfigure_through_ali(struct pci_dev *dev,
08d09997
LW		 2821 struct
2822 smsc_ircc_subsystem_configuration
2823 *conf)
c1e14a6e 2824{
08d09997
LW		 2825 /* Configure the two ports on the ALi 1533 */
2826 preconfigure_ali_port(dev, conf->sir_io);
2827 preconfigure_ali_port(dev, conf->fir_io);
2828
2829 /* Pre-configure chip */
2830 return preconfigure_smsc_chip(conf);
c1e14a6e
LW		 2831}
2832
948252cb 2833static int __init smsc_ircc_preconfigure_subsystems(unsigned short ircc_cfg,
c1e14a6e
LW		 2834 unsigned short ircc_fir,
2835 unsigned short ircc_sir,
2836 unsigned char ircc_dma,
2837 unsigned char ircc_irq)
2838{
2839 struct pci_dev *dev = NULL;
2840 unsigned short ss_vendor = 0x0000;
2841 unsigned short ss_device = 0x0000;
2842 int ret = 0;
2843
2e4e7a97 2844 for_each_pci_dev(dev) {
948252cb 2845 struct smsc_ircc_subsystem_configuration *conf;
c1e14a6e
LW		 2846
2847 /*
08d09997
LW		 2848 * Cache the subsystem vendor/device:
2849 * some manufacturers fail to set this for all components,
2850 * so we save it in case there is just 0x0000 0x0000 on the
2851 * device we want to check.
c1e14a6e
LW		 2852 */
2853 if (dev->subsystem_vendor != 0x0000U) {
2854 ss_vendor = dev->subsystem_vendor;
2855 ss_device = dev->subsystem_device;
2856 }
2857 conf = subsystem_configurations;
2858 for( ; conf->subvendor; conf++) {
2859 if(conf->vendor == dev->vendor &&
2860 conf->device == dev->device &&
08d09997
LW		 2861 conf->subvendor == ss_vendor &&
2862 /* Sometimes these are cached values */
2863 (conf->subdevice == ss_device ||
2864 conf->subdevice == 0xffff)) {
2865 struct smsc_ircc_subsystem_configuration
2866 tmpconf;
c1e14a6e 2867
08d09997
LW		 2868 memcpy(&tmpconf, conf,
2869 sizeof(struct smsc_ircc_subsystem_configuration));
c1e14a6e 2870
08d09997
LW		 2871 /*
2872 * Override the default values with anything
2873 * passed in as parameter
2874 */
c1e14a6e
LW		 2875 if (ircc_cfg != 0)
2876 tmpconf.cfg_base = ircc_cfg;
2877 if (ircc_fir != 0)
2878 tmpconf.fir_io = ircc_fir;
2879 if (ircc_sir != 0)
2880 tmpconf.sir_io = ircc_sir;
916f11c7 2881 if (ircc_dma != DMA_INVAL)
c1e14a6e 2882 tmpconf.fir_dma = ircc_dma;
916f11c7 2883 if (ircc_irq != IRQ_INVAL)
c1e14a6e
LW		 2884 tmpconf.fir_irq = ircc_irq;
2885
6c91023d
JP		 2886 net_info_ratelimited("Detected unconfigured %s SMSC IrDA chip, pre-configuring device\n",
2887 conf->name);
c1e14a6e
LW		 2888 if (conf->preconfigure)
2889 ret = conf->preconfigure(dev, &tmpconf);
2890 else
2891 ret = -ENODEV;
2892 }
2893 }
c1e14a6e
LW		 2894 }
2895
2896 return ret;
2897}
2898#endif // CONFIG_PCI
2899
1da177e4
LT		 2900/************************************************
2901 *
2902 * Transceivers specific functions
2903 *
2904 ************************************************/
2905
2906
2907/*
2908 * Function smsc_ircc_set_transceiver_smsc_ircc_atc(fir_base, speed)
2909 *
2910 * Program transceiver through smsc-ircc ATC circuitry
2911 *
2912 */
2913
2914static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed)
2915{
2916 unsigned long jiffies_now, jiffies_timeout;
98b77773 2917 u8 val;
527b6af4 2918
98b77773
DT		 2919 jiffies_now = jiffies;
2920 jiffies_timeout = jiffies + SMSC_IRCC2_ATC_PROGRAMMING_TIMEOUT_JIFFIES;
527b6af4 2921
1da177e4
LT		 2922 /* ATC */
2923 register_bank(fir_base, 4);
98b77773
DT		 2924 outb((inb(fir_base + IRCC_ATC) & IRCC_ATC_MASK) | IRCC_ATC_nPROGREADY|IRCC_ATC_ENABLE,
2925 fir_base + IRCC_ATC);
2926
2927 while ((val = (inb(fir_base + IRCC_ATC) & IRCC_ATC_nPROGREADY)) &&
2928 !time_after(jiffies, jiffies_timeout))
2929 /* empty */;
2930
2931 if (val)
6c91023d
JP		 2932 net_warn_ratelimited("%s(): ATC: 0x%02x\n",
2933 __func__, inb(fir_base + IRCC_ATC));
1da177e4
LT		 2934}
2935
2936/*
2937 * Function smsc_ircc_probe_transceiver_smsc_ircc_atc(fir_base)
2938 *
2939 * Probe transceiver smsc-ircc ATC circuitry
2940 *
2941 */
2942
2943static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base)
2944{
2945 return 0;
2946}
2947
2948/*
2949 * Function smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(self, speed)
2950 *
527b6af4 2951 * Set transceiver
1da177e4
LT		 2952 *
2953 */
2954
2955static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed)
2956{
98b77773 2957 u8 fast_mode;
527b6af4 2958
98b77773
DT		 2959 switch (speed) {
2960 default:
2961 case 576000 :
527b6af4 2962 fast_mode = 0;
1da177e4 2963 break;
98b77773
DT		 2964 case 1152000 :
2965 case 4000000 :
1da177e4
LT		 2966 fast_mode = IRCC_LCR_A_FAST;
2967 break;
1da177e4
LT		 2968 }
2969 register_bank(fir_base, 0);
98b77773 2970 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A);
1da177e4
LT		 2971}
2972
2973/*
2974 * Function smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(fir_base)
2975 *
527b6af4 2976 * Probe transceiver
1da177e4
LT		 2977 *
2978 */
2979
2980static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base)
2981{
2982 return 0;
2983}
2984
2985/*
2986 * Function smsc_ircc_set_transceiver_toshiba_sat1800(fir_base, speed)
2987 *
527b6af4 2988 * Set transceiver
1da177e4
LT		 2989 *
2990 */
2991
2992static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed)
2993{
98b77773 2994 u8 fast_mode;
527b6af4 2995
98b77773
DT		 2996 switch (speed) {
2997 default:
2998 case 576000 :
527b6af4 2999 fast_mode = 0;
1da177e4 3000 break;
98b77773
DT		 3001 case 1152000 :
3002 case 4000000 :
1da177e4
LT		 3003 fast_mode = /*IRCC_LCR_A_FAST |*/ IRCC_LCR_A_GP_DATA;
3004 break;
527b6af4 3005
1da177e4
LT		 3006 }
3007 /* This causes an interrupt */
3008 register_bank(fir_base, 0);
98b77773 3009 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A);
1da177e4
LT		 3010}
3011
3012/*
3013 * Function smsc_ircc_probe_transceiver_toshiba_sat1800(fir_base)
3014 *
527b6af4 3015 * Probe transceiver
1da177e4
LT		 3016 *
3017 */
3018
3019static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base)
3020{
3021 return 0;
3022}
3023
3024
3025module_init(smsc_ircc_init);
3026module_exit(smsc_ircc_cleanup);
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