]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | |
2 | /********************************************************************* | |
3 | * | |
4 | * vlsi_ir.h: VLSI82C147 PCI IrDA controller driver for Linux | |
5 | * | |
6 | * Version: 0.5 | |
7 | * | |
8 | * Copyright (c) 2001-2003 Martin Diehl | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of | |
13 | * the License, or (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
23 | * MA 02111-1307 USA | |
24 | * | |
25 | ********************************************************************/ | |
26 | ||
27 | #ifndef IRDA_VLSI_FIR_H | |
28 | #define IRDA_VLSI_FIR_H | |
29 | ||
30 | /* ================================================================ | |
31 | * compatibility stuff | |
32 | */ | |
33 | ||
34 | /* definitions not present in pci_ids.h */ | |
35 | ||
36 | #ifndef PCI_CLASS_WIRELESS_IRDA | |
37 | #define PCI_CLASS_WIRELESS_IRDA 0x0d00 | |
38 | #endif | |
39 | ||
40 | #ifndef PCI_CLASS_SUBCLASS_MASK | |
41 | #define PCI_CLASS_SUBCLASS_MASK 0xffff | |
42 | #endif | |
43 | ||
1da177e4 LT |
44 | /* ================================================================ */ |
45 | ||
46 | /* non-standard PCI registers */ | |
47 | ||
48 | enum vlsi_pci_regs { | |
49 | VLSI_PCI_CLKCTL = 0x40, /* chip clock input control */ | |
50 | VLSI_PCI_MSTRPAGE = 0x41, /* addr [31:24] for all busmaster cycles */ | |
51 | VLSI_PCI_IRMISC = 0x42 /* mainly legacy UART related */ | |
52 | }; | |
53 | ||
54 | /* ------------------------------------------ */ | |
55 | ||
56 | /* VLSI_PCI_CLKCTL: Clock Control Register (u8, rw) */ | |
57 | ||
58 | /* Three possible clock sources: either on-chip 48MHz PLL or | |
59 | * external clock applied to EXTCLK pin. External clock may | |
60 | * be either 48MHz or 40MHz, which is indicated by XCKSEL. | |
61 | * CLKSTP controls whether the selected clock source gets | |
62 | * connected to the IrDA block. | |
63 | * | |
64 | * On my HP OB-800 the BIOS sets external 40MHz clock as source | |
65 | * when IrDA enabled and I've never detected any PLL lock success. | |
66 | * Apparently the 14.3...MHz OSC input required for the PLL to work | |
67 | * is not connected and the 40MHz EXTCLK is provided externally. | |
68 | * At least this is what makes the driver working for me. | |
69 | */ | |
70 | ||
71 | enum vlsi_pci_clkctl { | |
72 | ||
73 | /* PLL control */ | |
74 | ||
75 | CLKCTL_PD_INV = 0x04, /* PD#: inverted power down signal, | |
76 | * i.e. PLL is powered, if PD_INV set */ | |
77 | CLKCTL_LOCK = 0x40, /* (ro) set, if PLL is locked */ | |
78 | ||
79 | /* clock source selection */ | |
80 | ||
81 | CLKCTL_EXTCLK = 0x20, /* set to select external clock input, not PLL */ | |
82 | CLKCTL_XCKSEL = 0x10, /* set to indicate EXTCLK is 40MHz, not 48MHz */ | |
83 | ||
84 | /* IrDA block control */ | |
85 | ||
86 | CLKCTL_CLKSTP = 0x80, /* set to disconnect from selected clock source */ | |
87 | CLKCTL_WAKE = 0x08 /* set to enable wakeup feature: whenever IR activity | |
88 | * is detected, PD_INV gets set(?) and CLKSTP cleared */ | |
89 | }; | |
90 | ||
91 | /* ------------------------------------------ */ | |
92 | ||
93 | /* VLSI_PCI_MSTRPAGE: Master Page Register (u8, rw) and busmastering stuff */ | |
94 | ||
95 | #define DMA_MASK_USED_BY_HW 0xffffffff | |
96 | #define DMA_MASK_MSTRPAGE 0x00ffffff | |
97 | #define MSTRPAGE_VALUE (DMA_MASK_MSTRPAGE >> 24) | |
98 | ||
99 | /* PCI busmastering is somewhat special for this guy - in short: | |
100 | * | |
101 | * We select to operate using fixed MSTRPAGE=0, use ISA DMA | |
102 | * address restrictions to make the PCI BM api aware of this, | |
103 | * but ensure the hardware is dealing with real 32bit access. | |
104 | * | |
105 | * In detail: | |
106 | * The chip executes normal 32bit busmaster cycles, i.e. | |
107 | * drives all 32 address lines. These addresses however are | |
108 | * composed of [0:23] taken from various busaddr-pointers | |
109 | * and [24:31] taken from the MSTRPAGE register in the VLSI82C147 | |
110 | * config space. Therefore _all_ busmastering must be | |
111 | * targeted to/from one single 16MB (busaddr-) superpage! | |
112 | * The point is to make sure all the allocations for memory | |
113 | * locations with busmaster access (ring descriptors, buffers) | |
114 | * are indeed bus-mappable to the same 16MB range (for x86 this | |
115 | * means they must reside in the same 16MB physical memory address | |
116 | * range). The only constraint we have which supports "several objects | |
117 | * mappable to common 16MB range" paradigma, is the old ISA DMA | |
118 | * restriction to the first 16MB of physical address range. | |
119 | * Hence the approach here is to enable PCI busmaster support using | |
120 | * the correct 32bit dma-mask used by the chip. Afterwards the device's | |
121 | * dma-mask gets restricted to 24bit, which must be honoured somehow by | |
122 | * all allocations for memory areas to be exposed to the chip ... | |
123 | * | |
124 | * Note: | |
125 | * Don't be surprised to get "Setting latency timer..." messages every | |
126 | * time when PCI busmastering is enabled for the chip. | |
127 | * The chip has its PCI latency timer RO fixed at 0 - which is not a | |
128 | * problem here, because it is never requesting _burst_ transactions. | |
129 | */ | |
130 | ||
131 | /* ------------------------------------------ */ | |
132 | ||
133 | /* VLSI_PCIIRMISC: IR Miscellaneous Register (u8, rw) */ | |
134 | ||
135 | /* legacy UART emulation - not used by this driver - would require: | |
136 | * (see below for some register-value definitions) | |
137 | * | |
138 | * - IRMISC_UARTEN must be set to enable UART address decoding | |
139 | * - IRMISC_UARTSEL configured | |
140 | * - IRCFG_MASTER must be cleared | |
141 | * - IRCFG_SIR must be set | |
142 | * - IRENABLE_PHYANDCLOCK must be asserted 0->1 (and hence IRENABLE_SIR_ON) | |
143 | */ | |
144 | ||
145 | enum vlsi_pci_irmisc { | |
146 | ||
147 | /* IR transceiver control */ | |
148 | ||
149 | IRMISC_IRRAIL = 0x40, /* (ro?) IR rail power indication (and control?) | |
150 | * 0=3.3V / 1=5V. Probably set during power-on? | |
151 | * unclear - not touched by driver */ | |
152 | IRMISC_IRPD = 0x08, /* transceiver power down, if set */ | |
153 | ||
154 | /* legacy UART control */ | |
155 | ||
156 | IRMISC_UARTTST = 0x80, /* UART test mode - "always write 0" */ | |
157 | IRMISC_UARTEN = 0x04, /* enable UART address decoding */ | |
158 | ||
159 | /* bits [1:0] IRMISC_UARTSEL to select legacy UART address */ | |
160 | ||
161 | IRMISC_UARTSEL_3f8 = 0x00, | |
162 | IRMISC_UARTSEL_2f8 = 0x01, | |
163 | IRMISC_UARTSEL_3e8 = 0x02, | |
164 | IRMISC_UARTSEL_2e8 = 0x03 | |
165 | }; | |
166 | ||
167 | /* ================================================================ */ | |
168 | ||
169 | /* registers mapped to 32 byte PCI IO space */ | |
170 | ||
171 | /* note: better access all registers at the indicated u8/u16 size | |
172 | * although some of them contain only 1 byte of information. | |
173 | * some of them (particaluarly PROMPT and IRCFG) ignore | |
174 | * access when using the wrong addressing mode! | |
175 | */ | |
176 | ||
177 | enum vlsi_pio_regs { | |
178 | VLSI_PIO_IRINTR = 0x00, /* interrupt enable/request (u8, rw) */ | |
179 | VLSI_PIO_RINGPTR = 0x02, /* rx/tx ring pointer (u16, ro) */ | |
180 | VLSI_PIO_RINGBASE = 0x04, /* [23:10] of ring address (u16, rw) */ | |
181 | VLSI_PIO_RINGSIZE = 0x06, /* rx/tx ring size (u16, rw) */ | |
182 | VLSI_PIO_PROMPT = 0x08, /* triggers ring processing (u16, wo) */ | |
183 | /* 0x0a-0x0f: reserved / duplicated UART regs */ | |
184 | VLSI_PIO_IRCFG = 0x10, /* configuration select (u16, rw) */ | |
185 | VLSI_PIO_SIRFLAG = 0x12, /* BOF/EOF for filtered SIR (u16, ro) */ | |
186 | VLSI_PIO_IRENABLE = 0x14, /* enable and status register (u16, rw/ro) */ | |
187 | VLSI_PIO_PHYCTL = 0x16, /* physical layer current status (u16, ro) */ | |
188 | VLSI_PIO_NPHYCTL = 0x18, /* next physical layer select (u16, rw) */ | |
189 | VLSI_PIO_MAXPKT = 0x1a, /* [11:0] max len for packet receive (u16, rw) */ | |
190 | VLSI_PIO_RCVBCNT = 0x1c /* current receive-FIFO byte count (u16, ro) */ | |
191 | /* 0x1e-0x1f: reserved / duplicated UART regs */ | |
192 | }; | |
193 | ||
194 | /* ------------------------------------------ */ | |
195 | ||
196 | /* VLSI_PIO_IRINTR: Interrupt Register (u8, rw) */ | |
197 | ||
198 | /* enable-bits: | |
199 | * 1 = enable / 0 = disable | |
200 | * interrupt condition bits: | |
201 | * set according to corresponding interrupt source | |
202 | * (regardless of the state of the enable bits) | |
203 | * enable bit status indicates whether interrupt gets raised | |
204 | * write-to-clear | |
205 | * note: RPKTINT and TPKTINT behave different in legacy UART mode (which we don't use :-) | |
206 | */ | |
207 | ||
208 | enum vlsi_pio_irintr { | |
209 | IRINTR_ACTEN = 0x80, /* activity interrupt enable */ | |
210 | IRINTR_ACTIVITY = 0x40, /* activity monitor (traffic detected) */ | |
211 | IRINTR_RPKTEN = 0x20, /* receive packet interrupt enable*/ | |
212 | IRINTR_RPKTINT = 0x10, /* rx-packet transfered from fifo to memory finished */ | |
213 | IRINTR_TPKTEN = 0x08, /* transmit packet interrupt enable */ | |
214 | IRINTR_TPKTINT = 0x04, /* last bit of tx-packet+crc shifted to ir-pulser */ | |
215 | IRINTR_OE_EN = 0x02, /* UART rx fifo overrun error interrupt enable */ | |
216 | IRINTR_OE_INT = 0x01 /* UART rx fifo overrun error (read LSR to clear) */ | |
217 | }; | |
218 | ||
219 | /* we use this mask to check whether the (shared PCI) interrupt is ours */ | |
220 | ||
221 | #define IRINTR_INT_MASK (IRINTR_ACTIVITY|IRINTR_RPKTINT|IRINTR_TPKTINT) | |
222 | ||
223 | /* ------------------------------------------ */ | |
224 | ||
225 | /* VLSI_PIO_RINGPTR: Ring Pointer Read-Back Register (u16, ro) */ | |
226 | ||
227 | /* _both_ ring pointers are indices relative to the _entire_ rx,tx-ring! | |
228 | * i.e. the referenced descriptor is located | |
229 | * at RINGBASE + PTR * sizeof(descr) for rx and tx | |
230 | * therefore, the tx-pointer has offset MAX_RING_DESCR | |
231 | */ | |
232 | ||
233 | #define MAX_RING_DESCR 64 /* tx, rx rings may contain up to 64 descr each */ | |
234 | ||
235 | #define RINGPTR_RX_MASK (MAX_RING_DESCR-1) | |
236 | #define RINGPTR_TX_MASK ((MAX_RING_DESCR-1)<<8) | |
237 | ||
238 | #define RINGPTR_GET_RX(p) ((p)&RINGPTR_RX_MASK) | |
239 | #define RINGPTR_GET_TX(p) (((p)&RINGPTR_TX_MASK)>>8) | |
240 | ||
241 | /* ------------------------------------------ */ | |
242 | ||
243 | /* VLSI_PIO_RINGBASE: Ring Pointer Base Address Register (u16, ro) */ | |
244 | ||
245 | /* Contains [23:10] part of the ring base (bus-) address | |
246 | * which must be 1k-alinged. [31:24] is taken from | |
247 | * VLSI_PCI_MSTRPAGE above. | |
248 | * The controller initiates non-burst PCI BM cycles to | |
249 | * fetch and update the descriptors in the ring. | |
250 | * Once fetched, the descriptor remains cached onchip | |
251 | * until it gets closed and updated due to the ring | |
252 | * processing state machine. | |
253 | * The entire ring area is split in rx and tx areas with each | |
254 | * area consisting of 64 descriptors of 8 bytes each. | |
255 | * The rx(tx) ring is located at ringbase+0 (ringbase+64*8). | |
256 | */ | |
257 | ||
258 | #define BUS_TO_RINGBASE(p) (((p)>>10)&0x3fff) | |
259 | ||
260 | /* ------------------------------------------ */ | |
261 | ||
262 | /* VLSI_PIO_RINGSIZE: Ring Size Register (u16, rw) */ | |
263 | ||
264 | /* bit mask to indicate the ring size to be used for rx and tx. | |
265 | * possible values encoded bits | |
266 | * 4 0000 | |
267 | * 8 0001 | |
268 | * 16 0011 | |
269 | * 32 0111 | |
270 | * 64 1111 | |
271 | * located at [15:12] for tx and [11:8] for rx ([7:0] unused) | |
272 | * | |
273 | * note: probably a good idea to have IRCFG_MSTR cleared when writing | |
274 | * this so the state machines are stopped and the RINGPTR is reset! | |
275 | */ | |
276 | ||
277 | #define SIZE_TO_BITS(num) ((((num)-1)>>2)&0x0f) | |
278 | #define TX_RX_TO_RINGSIZE(tx,rx) ((SIZE_TO_BITS(tx)<<12)|(SIZE_TO_BITS(rx)<<8)) | |
279 | #define RINGSIZE_TO_RXSIZE(rs) ((((rs)&0x0f00)>>6)+4) | |
280 | #define RINGSIZE_TO_TXSIZE(rs) ((((rs)&0xf000)>>10)+4) | |
281 | ||
282 | ||
283 | /* ------------------------------------------ */ | |
284 | ||
285 | /* VLSI_PIO_PROMPT: Ring Prompting Register (u16, write-to-start) */ | |
286 | ||
287 | /* writing any value kicks the ring processing state machines | |
288 | * for both tx, rx rings as follows: | |
289 | * - active rings (currently owning an active descriptor) | |
290 | * ignore the prompt and continue | |
291 | * - idle rings fetch the next descr from the ring and start | |
292 | * their processing | |
293 | */ | |
294 | ||
295 | /* ------------------------------------------ */ | |
296 | ||
297 | /* VLSI_PIO_IRCFG: IR Config Register (u16, rw) */ | |
298 | ||
299 | /* notes: | |
300 | * - not more than one SIR/MIR/FIR bit must be set at any time | |
301 | * - SIR, MIR, FIR and CRC16 select the configuration which will | |
302 | * be applied on next 0->1 transition of IRENABLE_PHYANDCLOCK (see below). | |
303 | * - besides allowing the PCI interface to execute busmaster cycles | |
304 | * and therefore the ring SM to operate, the MSTR bit has side-effects: | |
305 | * when MSTR is cleared, the RINGPTR's get reset and the legacy UART mode | |
306 | * (in contrast to busmaster access mode) gets enabled. | |
307 | * - clearing ENRX or setting ENTX while data is received may stall the | |
308 | * receive fifo until ENRX reenabled _and_ another packet arrives | |
309 | * - SIRFILT means the chip performs the required unwrapping of hardware | |
310 | * headers (XBOF's, BOF/EOF) and un-escaping in the _receive_ direction. | |
311 | * Only the resulting IrLAP payload is copied to the receive buffers - | |
312 | * but with the 16bit FCS still encluded. Question remains, whether it | |
313 | * was already checked or we should do it before passing the packet to IrLAP? | |
314 | */ | |
315 | ||
316 | enum vlsi_pio_ircfg { | |
317 | IRCFG_LOOP = 0x4000, /* enable loopback test mode */ | |
318 | IRCFG_ENTX = 0x1000, /* transmit enable */ | |
319 | IRCFG_ENRX = 0x0800, /* receive enable */ | |
320 | IRCFG_MSTR = 0x0400, /* master enable */ | |
321 | IRCFG_RXANY = 0x0200, /* receive any packet */ | |
322 | IRCFG_CRC16 = 0x0080, /* 16bit (not 32bit) CRC select for MIR/FIR */ | |
323 | IRCFG_FIR = 0x0040, /* FIR 4PPM encoding mode enable */ | |
324 | IRCFG_MIR = 0x0020, /* MIR HDLC encoding mode enable */ | |
325 | IRCFG_SIR = 0x0010, /* SIR encoding mode enable */ | |
326 | IRCFG_SIRFILT = 0x0008, /* enable SIR decode filter (receiver unwrapping) */ | |
327 | IRCFG_SIRTEST = 0x0004, /* allow SIR decode filter when not in SIR mode */ | |
328 | IRCFG_TXPOL = 0x0002, /* invert tx polarity when set */ | |
329 | IRCFG_RXPOL = 0x0001 /* invert rx polarity when set */ | |
330 | }; | |
331 | ||
332 | /* ------------------------------------------ */ | |
333 | ||
334 | /* VLSI_PIO_SIRFLAG: SIR Flag Register (u16, ro) */ | |
335 | ||
336 | /* register contains hardcoded BOF=0xc0 at [7:0] and EOF=0xc1 at [15:8] | |
337 | * which is used for unwrapping received frames in SIR decode-filter mode | |
338 | */ | |
339 | ||
340 | /* ------------------------------------------ */ | |
341 | ||
342 | /* VLSI_PIO_IRENABLE: IR Enable Register (u16, rw/ro) */ | |
343 | ||
344 | /* notes: | |
345 | * - IREN acts as gate for latching the configured IR mode information | |
346 | * from IRCFG and IRPHYCTL when IREN=reset and applying them when | |
347 | * IREN gets set afterwards. | |
348 | * - ENTXST reflects IRCFG_ENTX | |
349 | * - ENRXST = IRCFG_ENRX && (!IRCFG_ENTX || IRCFG_LOOP) | |
350 | */ | |
351 | ||
352 | enum vlsi_pio_irenable { | |
353 | IRENABLE_PHYANDCLOCK = 0x8000, /* enable IR phy and gate the mode config (rw) */ | |
354 | IRENABLE_CFGER = 0x4000, /* mode configuration error (ro) */ | |
355 | IRENABLE_FIR_ON = 0x2000, /* FIR on status (ro) */ | |
356 | IRENABLE_MIR_ON = 0x1000, /* MIR on status (ro) */ | |
357 | IRENABLE_SIR_ON = 0x0800, /* SIR on status (ro) */ | |
358 | IRENABLE_ENTXST = 0x0400, /* transmit enable status (ro) */ | |
359 | IRENABLE_ENRXST = 0x0200, /* Receive enable status (ro) */ | |
360 | IRENABLE_CRC16_ON = 0x0100 /* 16bit (not 32bit) CRC enabled status (ro) */ | |
361 | }; | |
362 | ||
363 | #define IRENABLE_MASK 0xff00 /* Read mask */ | |
364 | ||
365 | /* ------------------------------------------ */ | |
366 | ||
367 | /* VLSI_PIO_PHYCTL: IR Physical Layer Current Control Register (u16, ro) */ | |
368 | ||
369 | /* read-back of the currently applied physical layer status. | |
370 | * applied from VLSI_PIO_NPHYCTL at rising edge of IRENABLE_PHYANDCLOCK | |
371 | * contents identical to VLSI_PIO_NPHYCTL (see below) | |
372 | */ | |
373 | ||
374 | /* ------------------------------------------ */ | |
375 | ||
376 | /* VLSI_PIO_NPHYCTL: IR Physical Layer Next Control Register (u16, rw) */ | |
377 | ||
378 | /* latched during IRENABLE_PHYANDCLOCK=0 and applied at 0-1 transition | |
379 | * | |
380 | * consists of BAUD[15:10], PLSWID[9:5] and PREAMB[4:0] bits defined as follows: | |
381 | * | |
382 | * SIR-mode: BAUD = (115.2kHz / baudrate) - 1 | |
383 | * PLSWID = (pulsetime * freq / (BAUD+1)) - 1 | |
384 | * where pulsetime is the requested IrPHY pulse width | |
385 | * and freq is 8(16)MHz for 40(48)MHz primary input clock | |
386 | * PREAMB: don't care for SIR | |
387 | * | |
388 | * The nominal SIR pulse width is 3/16 bit time so we have PLSWID=12 | |
389 | * fixed for all SIR speeds at 40MHz input clock (PLSWID=24 at 48MHz). | |
390 | * IrPHY also allows shorter pulses down to the nominal pulse duration | |
391 | * at 115.2kbaud (minus some tolerance) which is 1.41 usec. | |
392 | * Using the expression PLSWID = 12/(BAUD+1)-1 (multiplied by two for 48MHz) | |
393 | * we get the minimum acceptable PLSWID values according to the VLSI | |
394 | * specification, which provides 1.5 usec pulse width for all speeds (except | |
395 | * for 2.4kbaud getting 6usec). This is fine with IrPHY v1.3 specs and | |
396 | * reduces the transceiver power which drains the battery. At 9.6kbaud for | |
397 | * example this amounts to more than 90% battery power saving! | |
398 | * | |
399 | * MIR-mode: BAUD = 0 | |
400 | * PLSWID = 9(10) for 40(48) MHz input clock | |
401 | * to get nominal MIR pulse width | |
402 | * PREAMB = 1 | |
403 | * | |
404 | * FIR-mode: BAUD = 0 | |
405 | * PLSWID: don't care | |
406 | * PREAMB = 15 | |
407 | */ | |
408 | ||
409 | #define PHYCTL_BAUD_SHIFT 10 | |
410 | #define PHYCTL_BAUD_MASK 0xfc00 | |
411 | #define PHYCTL_PLSWID_SHIFT 5 | |
412 | #define PHYCTL_PLSWID_MASK 0x03e0 | |
413 | #define PHYCTL_PREAMB_SHIFT 0 | |
414 | #define PHYCTL_PREAMB_MASK 0x001f | |
415 | ||
416 | #define PHYCTL_TO_BAUD(bwp) (((bwp)&PHYCTL_BAUD_MASK)>>PHYCTL_BAUD_SHIFT) | |
417 | #define PHYCTL_TO_PLSWID(bwp) (((bwp)&PHYCTL_PLSWID_MASK)>>PHYCTL_PLSWID_SHIFT) | |
418 | #define PHYCTL_TO_PREAMB(bwp) (((bwp)&PHYCTL_PREAMB_MASK)>>PHYCTL_PREAMB_SHIFT) | |
419 | ||
420 | #define BWP_TO_PHYCTL(b,w,p) ((((b)<<PHYCTL_BAUD_SHIFT)&PHYCTL_BAUD_MASK) \ | |
421 | | (((w)<<PHYCTL_PLSWID_SHIFT)&PHYCTL_PLSWID_MASK) \ | |
422 | | (((p)<<PHYCTL_PREAMB_SHIFT)&PHYCTL_PREAMB_MASK)) | |
423 | ||
424 | #define BAUD_BITS(br) ((115200/(br))-1) | |
425 | ||
426 | static inline unsigned | |
427 | calc_width_bits(unsigned baudrate, unsigned widthselect, unsigned clockselect) | |
428 | { | |
429 | unsigned tmp; | |
430 | ||
431 | if (widthselect) /* nominal 3/16 puls width */ | |
432 | return (clockselect) ? 12 : 24; | |
433 | ||
434 | tmp = ((clockselect) ? 12 : 24) / (BAUD_BITS(baudrate)+1); | |
435 | ||
436 | /* intermediate result of integer division needed here */ | |
437 | ||
438 | return (tmp>0) ? (tmp-1) : 0; | |
439 | } | |
440 | ||
441 | #define PHYCTL_SIR(br,ws,cs) BWP_TO_PHYCTL(BAUD_BITS(br),calc_width_bits((br),(ws),(cs)),0) | |
442 | #define PHYCTL_MIR(cs) BWP_TO_PHYCTL(0,((cs)?9:10),1) | |
443 | #define PHYCTL_FIR BWP_TO_PHYCTL(0,0,15) | |
444 | ||
445 | /* quite ugly, I know. But implementing these calculations here avoids | |
446 | * having magic numbers in the code and allows some playing with pulsewidths | |
447 | * without risk to violate the standards. | |
448 | * FWIW, here is the table for reference: | |
449 | * | |
450 | * baudrate BAUD min-PLSWID nom-PLSWID PREAMB | |
451 | * 2400 47 0(0) 12(24) 0 | |
452 | * 9600 11 0(0) 12(24) 0 | |
453 | * 19200 5 1(2) 12(24) 0 | |
454 | * 38400 2 3(6) 12(24) 0 | |
455 | * 57600 1 5(10) 12(24) 0 | |
456 | * 115200 0 11(22) 12(24) 0 | |
457 | * MIR 0 - 9(10) 1 | |
458 | * FIR 0 - 0 15 | |
459 | * | |
460 | * note: x(y) means x-value for 40MHz / y-value for 48MHz primary input clock | |
461 | */ | |
462 | ||
463 | /* ------------------------------------------ */ | |
464 | ||
465 | ||
466 | /* VLSI_PIO_MAXPKT: Maximum Packet Length register (u16, rw) */ | |
467 | ||
468 | /* maximum acceptable length for received packets */ | |
469 | ||
470 | /* hw imposed limitation - register uses only [11:0] */ | |
471 | #define MAX_PACKET_LENGTH 0x0fff | |
472 | ||
473 | /* IrLAP I-field (apparently not defined elsewhere) */ | |
474 | #define IRDA_MTU 2048 | |
475 | ||
476 | /* complete packet consists of A(1)+C(1)+I(<=IRDA_MTU) */ | |
477 | #define IRLAP_SKB_ALLOCSIZE (1+1+IRDA_MTU) | |
478 | ||
479 | /* the buffers we use to exchange frames with the hardware need to be | |
480 | * larger than IRLAP_SKB_ALLOCSIZE because we may have up to 4 bytes FCS | |
481 | * appended and, in SIR mode, a lot of frame wrapping bytes. The worst | |
482 | * case appears to be a SIR packet with I-size==IRDA_MTU and all bytes | |
483 | * requiring to be escaped to provide transparency. Furthermore, the peer | |
484 | * might ask for quite a number of additional XBOFs: | |
485 | * up to 115+48 XBOFS 163 | |
486 | * regular BOF 1 | |
487 | * A-field 1 | |
488 | * C-field 1 | |
489 | * I-field, IRDA_MTU, all escaped 4096 | |
490 | * FCS (16 bit at SIR, escaped) 4 | |
491 | * EOF 1 | |
492 | * AFAICS nothing in IrLAP guarantees A/C field not to need escaping | |
493 | * (f.e. 0xc0/0xc1 - i.e. BOF/EOF - are legal values there) so in the | |
494 | * worst case we have 4269 bytes total frame size. | |
495 | * However, the VLSI uses 12 bits only for all buffer length values, | |
496 | * which limits the maximum useable buffer size <= 4095. | |
497 | * Note this is not a limitation in the receive case because we use | |
498 | * the SIR filtering mode where the hw unwraps the frame and only the | |
499 | * bare packet+fcs is stored into the buffer - in contrast to the SIR | |
500 | * tx case where we have to pass frame-wrapped packets to the hw. | |
501 | * If this would ever become an issue in real life, the only workaround | |
502 | * I see would be using the legacy UART emulation in SIR mode. | |
503 | */ | |
504 | ||
505 | #define XFER_BUF_SIZE MAX_PACKET_LENGTH | |
506 | ||
507 | /* ------------------------------------------ */ | |
508 | ||
509 | /* VLSI_PIO_RCVBCNT: Receive Byte Count Register (u16, ro) */ | |
510 | ||
511 | /* receive packet counter gets incremented on every non-filtered | |
512 | * byte which was put in the receive fifo and reset for each | |
513 | * new packet. Used to decide whether we are just in the middle | |
514 | * of receiving | |
515 | */ | |
516 | ||
517 | /* better apply the [11:0] mask when reading, as some docs say the | |
518 | * reserved [15:12] would return 1 when reading - which is wrong AFAICS | |
519 | */ | |
520 | #define RCVBCNT_MASK 0x0fff | |
521 | ||
522 | /******************************************************************/ | |
523 | ||
524 | /* descriptors for rx/tx ring | |
525 | * | |
526 | * accessed by hardware - don't change! | |
527 | * | |
528 | * the descriptor is owned by hardware, when the ACTIVE status bit | |
529 | * is set and nothing (besides reading status to test the bit) | |
530 | * shall be done. The bit gets cleared by hw, when the descriptor | |
531 | * gets closed. Premature reaping of descriptors owned be the chip | |
532 | * can be achieved by disabling IRCFG_MSTR | |
533 | * | |
534 | * Attention: Writing addr overwrites status! | |
535 | * | |
536 | * ### FIXME: depends on endianess (but there ain't no non-i586 ob800 ;-) | |
537 | */ | |
538 | ||
539 | struct ring_descr_hw { | |
37e1370b AV |
540 | volatile __le16 rd_count; /* tx/rx count [11:0] */ |
541 | __le16 reserved; | |
1da177e4 | 542 | union { |
37e1370b | 543 | __le32 addr; /* [23:0] of the buffer's busaddress */ |
1da177e4 LT |
544 | struct { |
545 | u8 addr_res[3]; | |
546 | volatile u8 status; /* descriptor status */ | |
ba2d3587 ED |
547 | } __packed rd_s; |
548 | } __packed rd_u; | |
549 | } __packed; | |
1da177e4 LT |
550 | |
551 | #define rd_addr rd_u.addr | |
552 | #define rd_status rd_u.rd_s.status | |
553 | ||
554 | /* ring descriptor status bits */ | |
555 | ||
556 | #define RD_ACTIVE 0x80 /* descriptor owned by hw (both TX,RX) */ | |
557 | ||
558 | /* TX ring descriptor status */ | |
559 | ||
560 | #define RD_TX_DISCRC 0x40 /* do not send CRC (for SIR) */ | |
561 | #define RD_TX_BADCRC 0x20 /* force a bad CRC */ | |
562 | #define RD_TX_PULSE 0x10 /* send indication pulse after this frame (MIR/FIR) */ | |
563 | #define RD_TX_FRCEUND 0x08 /* force underrun */ | |
564 | #define RD_TX_CLRENTX 0x04 /* clear ENTX after this frame */ | |
565 | #define RD_TX_UNDRN 0x01 /* TX fifo underrun (probably PCI problem) */ | |
566 | ||
567 | /* RX ring descriptor status */ | |
568 | ||
569 | #define RD_RX_PHYERR 0x40 /* physical encoding error */ | |
570 | #define RD_RX_CRCERR 0x20 /* CRC error (MIR/FIR) */ | |
571 | #define RD_RX_LENGTH 0x10 /* frame exceeds buffer length */ | |
572 | #define RD_RX_OVER 0x08 /* RX fifo overrun (probably PCI problem) */ | |
573 | #define RD_RX_SIRBAD 0x04 /* EOF missing: BOF follows BOF (SIR, filtered) */ | |
574 | ||
575 | #define RD_RX_ERROR 0x7c /* any error in received frame */ | |
576 | ||
577 | /* the memory required to hold the 2 descriptor rings */ | |
578 | #define HW_RING_AREA_SIZE (2 * MAX_RING_DESCR * sizeof(struct ring_descr_hw)) | |
579 | ||
580 | /******************************************************************/ | |
581 | ||
582 | /* sw-ring descriptors consists of a bus-mapped transfer buffer with | |
583 | * associated skb and a pointer to the hw entry descriptor | |
584 | */ | |
585 | ||
586 | struct ring_descr { | |
587 | struct ring_descr_hw *hw; | |
588 | struct sk_buff *skb; | |
589 | void *buf; | |
590 | }; | |
591 | ||
592 | /* wrappers for operations on hw-exposed ring descriptors | |
593 | * access to the hw-part of the descriptors must use these. | |
594 | */ | |
595 | ||
596 | static inline int rd_is_active(struct ring_descr *rd) | |
597 | { | |
807540ba | 598 | return (rd->hw->rd_status & RD_ACTIVE) != 0; |
1da177e4 LT |
599 | } |
600 | ||
601 | static inline void rd_activate(struct ring_descr *rd) | |
602 | { | |
603 | rd->hw->rd_status |= RD_ACTIVE; | |
604 | } | |
605 | ||
606 | static inline void rd_set_status(struct ring_descr *rd, u8 s) | |
607 | { | |
608 | rd->hw->rd_status = s; /* may pass ownership to the hardware */ | |
609 | } | |
610 | ||
611 | static inline void rd_set_addr_status(struct ring_descr *rd, dma_addr_t a, u8 s) | |
612 | { | |
613 | /* order is important for two reasons: | |
614 | * - overlayed: writing addr overwrites status | |
615 | * - we want to write status last so we have valid address in | |
616 | * case status has RD_ACTIVE set | |
617 | */ | |
618 | ||
619 | if ((a & ~DMA_MASK_MSTRPAGE)>>24 != MSTRPAGE_VALUE) { | |
a97a6f10 | 620 | IRDA_ERROR("%s: pci busaddr inconsistency!\n", __func__); |
1da177e4 LT |
621 | dump_stack(); |
622 | return; | |
623 | } | |
624 | ||
625 | a &= DMA_MASK_MSTRPAGE; /* clear highbyte to make sure we won't write | |
626 | * to status - just in case MSTRPAGE_VALUE!=0 | |
627 | */ | |
628 | rd->hw->rd_addr = cpu_to_le32(a); | |
629 | wmb(); | |
630 | rd_set_status(rd, s); /* may pass ownership to the hardware */ | |
631 | } | |
632 | ||
633 | static inline void rd_set_count(struct ring_descr *rd, u16 c) | |
634 | { | |
635 | rd->hw->rd_count = cpu_to_le16(c); | |
636 | } | |
637 | ||
638 | static inline u8 rd_get_status(struct ring_descr *rd) | |
639 | { | |
640 | return rd->hw->rd_status; | |
641 | } | |
642 | ||
643 | static inline dma_addr_t rd_get_addr(struct ring_descr *rd) | |
644 | { | |
645 | dma_addr_t a; | |
646 | ||
647 | a = le32_to_cpu(rd->hw->rd_addr); | |
648 | return (a & DMA_MASK_MSTRPAGE) | (MSTRPAGE_VALUE << 24); | |
649 | } | |
650 | ||
651 | static inline u16 rd_get_count(struct ring_descr *rd) | |
652 | { | |
653 | return le16_to_cpu(rd->hw->rd_count); | |
654 | } | |
655 | ||
656 | /******************************************************************/ | |
657 | ||
658 | /* sw descriptor rings for rx, tx: | |
659 | * | |
660 | * operations follow producer-consumer paradigm, with the hw | |
661 | * in the middle doing the processing. | |
662 | * ring size must be power of two. | |
663 | * | |
664 | * producer advances r->tail after inserting for processing | |
665 | * consumer advances r->head after removing processed rd | |
666 | * ring is empty if head==tail / full if (tail+1)==head | |
667 | */ | |
668 | ||
669 | struct vlsi_ring { | |
670 | struct pci_dev *pdev; | |
671 | int dir; | |
672 | unsigned len; | |
673 | unsigned size; | |
674 | unsigned mask; | |
675 | atomic_t head, tail; | |
676 | struct ring_descr *rd; | |
677 | }; | |
678 | ||
679 | /* ring processing helpers */ | |
680 | ||
681 | static inline struct ring_descr *ring_last(struct vlsi_ring *r) | |
682 | { | |
683 | int t; | |
684 | ||
685 | t = atomic_read(&r->tail) & r->mask; | |
686 | return (((t+1) & r->mask) == (atomic_read(&r->head) & r->mask)) ? NULL : &r->rd[t]; | |
687 | } | |
688 | ||
689 | static inline struct ring_descr *ring_put(struct vlsi_ring *r) | |
690 | { | |
691 | atomic_inc(&r->tail); | |
692 | return ring_last(r); | |
693 | } | |
694 | ||
695 | static inline struct ring_descr *ring_first(struct vlsi_ring *r) | |
696 | { | |
697 | int h; | |
698 | ||
699 | h = atomic_read(&r->head) & r->mask; | |
700 | return (h == (atomic_read(&r->tail) & r->mask)) ? NULL : &r->rd[h]; | |
701 | } | |
702 | ||
703 | static inline struct ring_descr *ring_get(struct vlsi_ring *r) | |
704 | { | |
705 | atomic_inc(&r->head); | |
706 | return ring_first(r); | |
707 | } | |
708 | ||
709 | /******************************************************************/ | |
710 | ||
711 | /* our private compound VLSI-PCI-IRDA device information */ | |
712 | ||
713 | typedef struct vlsi_irda_dev { | |
714 | struct pci_dev *pdev; | |
1da177e4 LT |
715 | |
716 | struct irlap_cb *irlap; | |
717 | ||
718 | struct qos_info qos; | |
719 | ||
720 | unsigned mode; | |
721 | int baud, new_baud; | |
722 | ||
723 | dma_addr_t busaddr; | |
724 | void *virtaddr; | |
725 | struct vlsi_ring *tx_ring, *rx_ring; | |
726 | ||
727 | struct timeval last_rx; | |
728 | ||
729 | spinlock_t lock; | |
aa429110 | 730 | struct mutex mtx; |
1da177e4 LT |
731 | |
732 | u8 resume_ok; | |
733 | struct proc_dir_entry *proc_entry; | |
734 | ||
735 | } vlsi_irda_dev_t; | |
736 | ||
737 | /********************************************************/ | |
738 | ||
739 | /* the remapped error flags we use for returning from frame | |
740 | * post-processing in vlsi_process_tx/rx() after it was completed | |
741 | * by the hardware. These functions either return the >=0 number | |
742 | * of transfered bytes in case of success or the negative (-) | |
743 | * of the or'ed error flags. | |
744 | */ | |
745 | ||
746 | #define VLSI_TX_DROP 0x0001 | |
747 | #define VLSI_TX_FIFO 0x0002 | |
748 | ||
749 | #define VLSI_RX_DROP 0x0100 | |
750 | #define VLSI_RX_OVER 0x0200 | |
751 | #define VLSI_RX_LENGTH 0x0400 | |
752 | #define VLSI_RX_FRAME 0x0800 | |
753 | #define VLSI_RX_CRC 0x1000 | |
754 | ||
755 | /********************************************************/ | |
756 | ||
757 | #endif /* IRDA_VLSI_FIR_H */ | |
758 |