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1da177e4 LT |
1 | /******************************************************************************* |
2 | ||
0abb6eb1 AK |
3 | Intel PRO/10GbE Linux driver |
4 | Copyright(c) 1999 - 2006 Intel Corporation. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
1da177e4 | 13 | more details. |
0abb6eb1 | 14 | |
1da177e4 | 15 | You should have received a copy of the GNU General Public License along with |
0abb6eb1 AK |
16 | this program; if not, write to the Free Software Foundation, Inc., |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
1da177e4 LT |
22 | Contact Information: |
23 | Linux NICS <linux.nics@intel.com> | |
0abb6eb1 | 24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
1da177e4 LT |
25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
26 | ||
27 | *******************************************************************************/ | |
28 | ||
29 | /* glue for the OS independent part of ixgb | |
30 | * includes register access macros | |
31 | */ | |
32 | ||
33 | #ifndef _IXGB_OSDEP_H_ | |
34 | #define _IXGB_OSDEP_H_ | |
35 | ||
36 | #include <linux/types.h> | |
37 | #include <linux/pci.h> | |
38 | #include <linux/delay.h> | |
39 | #include <asm/io.h> | |
40 | #include <linux/interrupt.h> | |
41 | #include <linux/sched.h> | |
42 | ||
1da177e4 LT |
43 | typedef enum { |
44 | #undef FALSE | |
45 | FALSE = 0, | |
46 | #undef TRUE | |
47 | TRUE = 1 | |
48 | } boolean_t; | |
49 | ||
50 | #undef ASSERT | |
51 | #define ASSERT(x) if(!(x)) BUG() | |
52 | #define MSGOUT(S, A, B) printk(KERN_DEBUG S "\n", A, B) | |
53 | ||
54 | #ifdef DBG | |
55 | #define DEBUGOUT(S) printk(KERN_DEBUG S "\n") | |
56 | #define DEBUGOUT1(S, A...) printk(KERN_DEBUG S "\n", A) | |
57 | #else | |
58 | #define DEBUGOUT(S) | |
59 | #define DEBUGOUT1(S, A...) | |
60 | #endif | |
61 | ||
62 | #define DEBUGFUNC(F) DEBUGOUT(F) | |
63 | #define DEBUGOUT2 DEBUGOUT1 | |
64 | #define DEBUGOUT3 DEBUGOUT2 | |
65 | #define DEBUGOUT7 DEBUGOUT3 | |
66 | ||
67 | #define IXGB_WRITE_REG(a, reg, value) ( \ | |
68 | writel((value), ((a)->hw_addr + IXGB_##reg))) | |
69 | ||
70 | #define IXGB_READ_REG(a, reg) ( \ | |
71 | readl((a)->hw_addr + IXGB_##reg)) | |
72 | ||
73 | #define IXGB_WRITE_REG_ARRAY(a, reg, offset, value) ( \ | |
74 | writel((value), ((a)->hw_addr + IXGB_##reg + ((offset) << 2)))) | |
75 | ||
76 | #define IXGB_READ_REG_ARRAY(a, reg, offset) ( \ | |
77 | readl((a)->hw_addr + IXGB_##reg + ((offset) << 2))) | |
78 | ||
79 | #define IXGB_WRITE_FLUSH(a) IXGB_READ_REG(a, STATUS) | |
80 | ||
81 | #define IXGB_MEMCPY memcpy | |
82 | ||
83 | #endif /* _IXGB_OSDEP_H_ */ |