[mirror_ubuntu-artful-kernel.git] / drivers / net / ixgbe / ixgbe_common.h

/*******************************************************************************

  Intel 10 Gigabit PCI Express Linux driver
  Copyright(c) 1999 - 2011 Intel Corporation.

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Contact Information:
  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

*******************************************************************************/

#ifndef _IXGBE_COMMON_H_
#define _IXGBE_COMMON_H_

#include "ixgbe_type.h"
#include "ixgbe.h"

u32 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw);
s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw);
s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw);
s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw);
s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw);
s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw);
s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
                                  u32 pba_num_size);
s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr);
s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw);
void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw);
s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw);

s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index);
s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index);

s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw);
s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data);
s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
					       u16 words, u16 *data);
s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data);
s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
				   u16 words, u16 *data);
s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data);
s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
				    u16 words, u16 *data);
s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
                                       u16 *data);
s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
					      u16 words, u16 *data);
u16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw);
s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
                                           u16 *checksum_val);
s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw);

s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
                          u32 enable_addr);
s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index);
s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw);
s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw,
				      struct net_device *netdev);
s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw);
s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw);
s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval);
s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packtetbuf_num);
s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw);

s32 ixgbe_validate_mac_addr(u8 *mac_addr);
s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask);
void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask);
s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw);
s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr);
s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw);
s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan,
                           u32 vind, bool vlan_on);
s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw);
s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw,
                                 ixgbe_link_speed *speed,
                                 bool *link_up, bool link_up_wait_to_complete);
s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
                                 u16 *wwpn_prefix);
s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index);
s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index);
void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf);
void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf);
s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps);

#define IXGBE_WRITE_REG(a, reg, value) writel((value), ((a)->hw_addr + (reg)))

#ifndef writeq
#define writeq(val, addr) writel((u32) (val), addr); \
    writel((u32) (val >> 32), (addr + 4));
#endif

#define IXGBE_WRITE_REG64(a, reg, value) writeq((value), ((a)->hw_addr + (reg)))

#define IXGBE_READ_REG(a, reg) readl((a)->hw_addr + (reg))

#define IXGBE_WRITE_REG_ARRAY(a, reg, offset, value) (\
    writel((value), ((a)->hw_addr + (reg) + ((offset) << 2))))

#define IXGBE_READ_REG_ARRAY(a, reg, offset) (\
    readl((a)->hw_addr + (reg) + ((offset) << 2)))

#define IXGBE_WRITE_FLUSH(a) IXGBE_READ_REG(a, IXGBE_STATUS)

#define hw_dbg(hw, format, arg...) \
	netdev_dbg(((struct ixgbe_adapter *)(hw->back))->netdev, format, ##arg)
#define e_dev_info(format, arg...) \
	dev_info(&adapter->pdev->dev, format, ## arg)
#define e_dev_warn(format, arg...) \
	dev_warn(&adapter->pdev->dev, format, ## arg)
#define e_dev_err(format, arg...) \
	dev_err(&adapter->pdev->dev, format, ## arg)
#define e_dev_notice(format, arg...) \
	dev_notice(&adapter->pdev->dev, format, ## arg)
#define e_info(msglvl, format, arg...) \
	netif_info(adapter, msglvl, adapter->netdev, format, ## arg)
#define e_err(msglvl, format, arg...) \
	netif_err(adapter, msglvl, adapter->netdev, format, ## arg)
#define e_warn(msglvl, format, arg...) \
	netif_warn(adapter, msglvl, adapter->netdev, format, ## arg)
#define e_crit(msglvl, format, arg...) \
	netif_crit(adapter, msglvl, adapter->netdev, format, ## arg)
#endif /* IXGBE_COMMON */
Commit	Line	Data
9a799d71 AK	1	/*******************************************************************************
	2
	3	Intel 10 Gigabit PCI Express Linux driver
a52055e0	4	Copyright(c) 1999 - 2011 Intel Corporation.
9a799d71 AK	5
	6	This program is free software; you can redistribute it and/or modify it
	7	under the terms and conditions of the GNU General Public License,
	8	version 2, as published by the Free Software Foundation.
	9
	10	This program is distributed in the hope it will be useful, but WITHOUT
	11	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	more details.
	14
	15	You should have received a copy of the GNU General Public License along with
	16	this program; if not, write to the Free Software Foundation, Inc.,
	17	51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	18
	19	The full GNU General Public License is included in this distribution in
	20	the file called "COPYING".
	21
	22	Contact Information:
9a799d71 AK	23	e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
	24	Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	25
	26	*******************************************************************************/
	27
	28	#ifndef _IXGBE_COMMON_H_
	29	#define _IXGBE_COMMON_H_
	30
	31	#include "ixgbe_type.h"
32f75466	32	#include "ixgbe.h"
9a799d71	33
21ce849b	34	u32 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw);
c44ade9e JB	35	s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw);
	36	s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw);
	37	s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw);
7184b7cf	38	s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw);
c44ade9e	39	s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw);
289700db DS	40	s32 ixgbe_read_pba_string_generic(struct ixgbe_hw hw, u8 pba_num,
289700db DS	41	u32 pba_num_size);
c44ade9e JB	42	s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw hw, u8 mac_addr);
c44ade9e JB	43	s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw);
11afc1b1	44	void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw);
c44ade9e JB	45	s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw);
	46
	47	s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index);
	48	s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index);
	49
	50	s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw);
11afc1b1	51	s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data);
68c7005d ET	52	s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
68c7005d ET	53	u16 words, u16 *data);
21ce849b	54	s32 ixgbe_read_eerd_generic(struct ixgbe_hw hw, u16 offset, u16 data);
68c7005d ET	55	s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
68c7005d ET	56	u16 words, u16 *data);
eb9c3e3e	57	s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data);
68c7005d ET	58	s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
68c7005d ET	59	u16 words, u16 *data);
c44ade9e JB	60	s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
c44ade9e JB	61	u16 *data);
68c7005d ET	62	s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
68c7005d ET	63	u16 words, u16 *data);
a391f1d5	64	u16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw);
c44ade9e JB	65	s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
	66	u16 *checksum_val);
	67	s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw);
	68
	69	s32 ixgbe_set_rar_generic(struct ixgbe_hw hw, u32 index, u8 addr, u32 vmdq,
	70	u32 enable_addr);
	71	s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index);
	72	s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw);
2853eb89 JP	73	s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw,
2853eb89 JP	74	struct net_device *netdev);
c44ade9e JB	75	s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw);
c44ade9e JB	76	s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw);
11afc1b1	77	s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval);
620fa036	78	s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packtetbuf_num);
0ecc061d	79	s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw);
9a799d71	80
c44ade9e	81	s32 ixgbe_validate_mac_addr(u8 *mac_addr);
9a799d71 AK	82	s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask);
	83	void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask);
	84	s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw);
21ce849b MC	85	s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw hw, u8 san_mac_addr);
	86	s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
	87	s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
	88	s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw);
	89	s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan,
	90	u32 vind, bool vlan_on);
	91	s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw);
	92	s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw,
	93	ixgbe_link_speed *speed,
	94	bool *link_up, bool link_up_wait_to_complete);
a391f1d5 DS	95	s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw hw, u16 wwnn_prefix,
a391f1d5 DS	96	u16 *wwpn_prefix);
87c12017 PW	97	s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index);
87c12017 PW	98	s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index);
a985b6c3 GR	99	void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf);
a985b6c3 GR	100	void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf);
b776d104	101	s32 ixgbe_get_device_caps_generic(struct ixgbe_hw hw, u16 device_caps);
87c12017	102
9a799d71 AK	103	#define IXGBE_WRITE_REG(a, reg, value) writel((value), ((a)->hw_addr + (reg)))
9a799d71 AK	104
11afc1b1 PW	105	#ifndef writeq
	106	#define writeq(val, addr) writel((u32) (val), addr); \
	107	writel((u32) (val >> 32), (addr + 4));
	108	#endif
	109
	110	#define IXGBE_WRITE_REG64(a, reg, value) writeq((value), ((a)->hw_addr + (reg)))
	111
9a799d71 AK	112	#define IXGBE_READ_REG(a, reg) readl((a)->hw_addr + (reg))
	113
	114	#define IXGBE_WRITE_REG_ARRAY(a, reg, offset, value) (\
	115	writel((value), ((a)->hw_addr + (reg) + ((offset) << 2))))
	116
	117	#define IXGBE_READ_REG_ARRAY(a, reg, offset) (\
	118	readl((a)->hw_addr + (reg) + ((offset) << 2)))
	119
	120	#define IXGBE_WRITE_FLUSH(a) IXGBE_READ_REG(a, IXGBE_STATUS)
	121
9a799d71	122	#define hw_dbg(hw, format, arg...) \
32f75466	123	netdev_dbg(((struct ixgbe_adapter *)(hw->back))->netdev, format, ##arg)
849c4542 ET	124	#define e_dev_info(format, arg...) \
	125	dev_info(&adapter->pdev->dev, format, ## arg)
	126	#define e_dev_warn(format, arg...) \
	127	dev_warn(&adapter->pdev->dev, format, ## arg)
	128	#define e_dev_err(format, arg...) \
	129	dev_err(&adapter->pdev->dev, format, ## arg)
	130	#define e_dev_notice(format, arg...) \
	131	dev_notice(&adapter->pdev->dev, format, ## arg)
396e799c ET	132	#define e_info(msglvl, format, arg...) \
	133	netif_info(adapter, msglvl, adapter->netdev, format, ## arg)
	134	#define e_err(msglvl, format, arg...) \
	135	netif_err(adapter, msglvl, adapter->netdev, format, ## arg)
	136	#define e_warn(msglvl, format, arg...) \
	137	netif_warn(adapter, msglvl, adapter->netdev, format, ## arg)
	138	#define e_crit(msglvl, format, arg...) \
	139	netif_crit(adapter, msglvl, adapter->netdev, format, ## arg)
9a799d71	140	#endif /* IXGBE_COMMON */