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ixgbe: disable RSC when Rx checksum is off
[mirror_ubuntu-artful-kernel.git] / drivers / net / ixgbe / ixgbe_ethtool.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
a52055e0 4 Copyright(c) 1999 - 2011 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28/* ethtool support for ixgbe */
29
a6b7a407 30#include <linux/interrupt.h>
9a799d71
AK		 31#include <linux/types.h>
32#include <linux/module.h>
5a0e3ad6 33#include <linux/slab.h>
9a799d71
AK		 34#include <linux/pci.h>
35#include <linux/netdevice.h>
36#include <linux/ethtool.h>
37#include <linux/vmalloc.h>
38#include <linux/uaccess.h>
39
40#include "ixgbe.h"
41
42
43#define IXGBE_ALL_RAR_ENTRIES 16
44
29c3a050
AK		 45enum {NETDEV_STATS, IXGBE_STATS};
46
9a799d71
AK		 47struct ixgbe_stats {
48 char stat_string[ETH_GSTRING_LEN];
29c3a050 49 int type;
9a799d71
AK		 50 int sizeof_stat;
51 int stat_offset;
52};
53
29c3a050
AK		 54#define IXGBE_STAT(m) IXGBE_STATS, \
55 sizeof(((struct ixgbe_adapter *)0)->m), \
56 offsetof(struct ixgbe_adapter, m)
57#define IXGBE_NETDEV_STAT(m) NETDEV_STATS, \
55bad823
ED		 58 sizeof(((struct rtnl_link_stats64 *)0)->m), \
59 offsetof(struct rtnl_link_stats64, m)
29c3a050 60
9a799d71 61static struct ixgbe_stats ixgbe_gstrings_stats[] = {
55bad823
ED		 62 {"rx_packets", IXGBE_NETDEV_STAT(rx_packets)},
63 {"tx_packets", IXGBE_NETDEV_STAT(tx_packets)},
64 {"rx_bytes", IXGBE_NETDEV_STAT(rx_bytes)},
65 {"tx_bytes", IXGBE_NETDEV_STAT(tx_bytes)},
aad71918
BG		 66 {"rx_pkts_nic", IXGBE_STAT(stats.gprc)},
67 {"tx_pkts_nic", IXGBE_STAT(stats.gptc)},
68 {"rx_bytes_nic", IXGBE_STAT(stats.gorc)},
69 {"tx_bytes_nic", IXGBE_STAT(stats.gotc)},
9a799d71
AK		 70 {"lsc_int", IXGBE_STAT(lsc_int)},
71 {"tx_busy", IXGBE_STAT(tx_busy)},
72 {"non_eop_descs", IXGBE_STAT(non_eop_descs)},
55bad823
ED		 73 {"rx_errors", IXGBE_NETDEV_STAT(rx_errors)},
74 {"tx_errors", IXGBE_NETDEV_STAT(tx_errors)},
75 {"rx_dropped", IXGBE_NETDEV_STAT(rx_dropped)},
76 {"tx_dropped", IXGBE_NETDEV_STAT(tx_dropped)},
77 {"multicast", IXGBE_NETDEV_STAT(multicast)},
9a799d71
AK		 78 {"broadcast", IXGBE_STAT(stats.bprc)},
79 {"rx_no_buffer_count", IXGBE_STAT(stats.rnbc[0]) },
55bad823
ED		 80 {"collisions", IXGBE_NETDEV_STAT(collisions)},
81 {"rx_over_errors", IXGBE_NETDEV_STAT(rx_over_errors)},
82 {"rx_crc_errors", IXGBE_NETDEV_STAT(rx_crc_errors)},
83 {"rx_frame_errors", IXGBE_NETDEV_STAT(rx_frame_errors)},
94b982b2
MC		 84 {"hw_rsc_aggregated", IXGBE_STAT(rsc_total_count)},
85 {"hw_rsc_flushed", IXGBE_STAT(rsc_total_flush)},
c4cf55e5
PWJ		 86 {"fdir_match", IXGBE_STAT(stats.fdirmatch)},
87 {"fdir_miss", IXGBE_STAT(stats.fdirmiss)},
d034acf1 88 {"fdir_overflow", IXGBE_STAT(fdir_overflow)},
55bad823
ED		 89 {"rx_fifo_errors", IXGBE_NETDEV_STAT(rx_fifo_errors)},
90 {"rx_missed_errors", IXGBE_NETDEV_STAT(rx_missed_errors)},
91 {"tx_aborted_errors", IXGBE_NETDEV_STAT(tx_aborted_errors)},
92 {"tx_carrier_errors", IXGBE_NETDEV_STAT(tx_carrier_errors)},
93 {"tx_fifo_errors", IXGBE_NETDEV_STAT(tx_fifo_errors)},
94 {"tx_heartbeat_errors", IXGBE_NETDEV_STAT(tx_heartbeat_errors)},
9a799d71
AK		 95 {"tx_timeout_count", IXGBE_STAT(tx_timeout_count)},
96 {"tx_restart_queue", IXGBE_STAT(restart_queue)},
97 {"rx_long_length_errors", IXGBE_STAT(stats.roc)},
98 {"rx_short_length_errors", IXGBE_STAT(stats.ruc)},
9a799d71
AK		 99 {"tx_flow_control_xon", IXGBE_STAT(stats.lxontxc)},
100 {"rx_flow_control_xon", IXGBE_STAT(stats.lxonrxc)},
101 {"tx_flow_control_xoff", IXGBE_STAT(stats.lxofftxc)},
102 {"rx_flow_control_xoff", IXGBE_STAT(stats.lxoffrxc)},
9a799d71 103 {"rx_csum_offload_errors", IXGBE_STAT(hw_csum_rx_error)},
9a799d71
AK		 104 {"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)},
105 {"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)},
e8e26350 106 {"rx_no_dma_resources", IXGBE_STAT(hw_rx_no_dma_resources)},
58f6bcf9
ET		 107 {"os2bmc_rx_by_bmc", IXGBE_STAT(stats.o2bgptc)},
108 {"os2bmc_tx_by_bmc", IXGBE_STAT(stats.b2ospc)},
109 {"os2bmc_tx_by_host", IXGBE_STAT(stats.o2bspc)},
110 {"os2bmc_rx_by_host", IXGBE_STAT(stats.b2ogprc)},
6d45522c
YZ		 111#ifdef IXGBE_FCOE
112 {"fcoe_bad_fccrc", IXGBE_STAT(stats.fccrc)},
113 {"rx_fcoe_dropped", IXGBE_STAT(stats.fcoerpdc)},
114 {"rx_fcoe_packets", IXGBE_STAT(stats.fcoeprc)},
115 {"rx_fcoe_dwords", IXGBE_STAT(stats.fcoedwrc)},
116 {"tx_fcoe_packets", IXGBE_STAT(stats.fcoeptc)},
117 {"tx_fcoe_dwords", IXGBE_STAT(stats.fcoedwtc)},
118#endif /* IXGBE_FCOE */
9a799d71
AK		 119};
120
121#define IXGBE_QUEUE_STATS_LEN \
454d7c9b
WC		 122 ((((struct ixgbe_adapter *)netdev_priv(netdev))->num_tx_queues + \
123 ((struct ixgbe_adapter *)netdev_priv(netdev))->num_rx_queues) * \
124 (sizeof(struct ixgbe_queue_stats) / sizeof(u64)))
b4617240 125#define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats)
2f90b865 126#define IXGBE_PB_STATS_LEN ( \
9d2f4720 127 (((struct ixgbe_adapter *)netdev_priv(netdev))->flags & \
2f90b865
AD		 128 IXGBE_FLAG_DCB_ENABLED) ? \
129 (sizeof(((struct ixgbe_adapter *)0)->stats.pxonrxc) + \
130 sizeof(((struct ixgbe_adapter *)0)->stats.pxontxc) + \
131 sizeof(((struct ixgbe_adapter *)0)->stats.pxoffrxc) + \
132 sizeof(((struct ixgbe_adapter *)0)->stats.pxofftxc)) \
133 / sizeof(u64) : 0)
134#define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + \
135 IXGBE_PB_STATS_LEN + \
136 IXGBE_QUEUE_STATS_LEN)
9a799d71 137
da4dd0f7
PWJ		 138static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = {
139 "Register test (offline)", "Eeprom test (offline)",
140 "Interrupt test (offline)", "Loopback test (offline)",
141 "Link test (on/offline)"
142};
143#define IXGBE_TEST_LEN sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN
144
9a799d71 145static int ixgbe_get_settings(struct net_device *netdev,
b4617240 146 struct ethtool_cmd *ecmd)
9a799d71
AK		 147{
148 struct ixgbe_adapter *adapter = netdev_priv(netdev);
735441fb
AV		 149 struct ixgbe_hw *hw = &adapter->hw;
150 u32 link_speed = 0;
151 bool link_up;
9a799d71 152
735441fb
AV		 153 ecmd->supported = SUPPORTED_10000baseT_Full;
154 ecmd->autoneg = AUTONEG_ENABLE;
9a799d71 155 ecmd->transceiver = XCVR_EXTERNAL;
74766013 156 if ((hw->phy.media_type == ixgbe_media_type_copper) ||
a3801379 157 (hw->phy.multispeed_fiber)) {
735441fb 158 ecmd->supported |= (SUPPORTED_1000baseT_Full |
74766013 159 SUPPORTED_Autoneg);
735441fb 160
1b1c0a48
AS		 161 switch (hw->mac.type) {
162 case ixgbe_mac_X540:
163 ecmd->supported |= SUPPORTED_100baseT_Full;
164 break;
165 default:
166 break;
167 }
168
74766013 169 ecmd->advertising = ADVERTISED_Autoneg;
2b642ca5
ET		 170 if (hw->phy.autoneg_advertised) {
171 if (hw->phy.autoneg_advertised &
172 IXGBE_LINK_SPEED_100_FULL)
173 ecmd->advertising |= ADVERTISED_100baseT_Full;
174 if (hw->phy.autoneg_advertised &
175 IXGBE_LINK_SPEED_10GB_FULL)
176 ecmd->advertising |= ADVERTISED_10000baseT_Full;
177 if (hw->phy.autoneg_advertised &
178 IXGBE_LINK_SPEED_1GB_FULL)
179 ecmd->advertising |= ADVERTISED_1000baseT_Full;
180 } else {
181 /*
182 * Default advertised modes in case
183 * phy.autoneg_advertised isn't set.
184 */
7c5b8323
DS		 185 ecmd->advertising |= (ADVERTISED_10000baseT_Full |
186 ADVERTISED_1000baseT_Full);
2b642ca5
ET		 187 if (hw->mac.type == ixgbe_mac_X540)
188 ecmd->advertising |= ADVERTISED_100baseT_Full;
1b1c0a48
AS		 189 }
190
74766013
MC		 191 if (hw->phy.media_type == ixgbe_media_type_copper) {
192 ecmd->supported |= SUPPORTED_TP;
193 ecmd->advertising |= ADVERTISED_TP;
194 ecmd->port = PORT_TP;
195 } else {
196 ecmd->supported |= SUPPORTED_FIBRE;
197 ecmd->advertising |= ADVERTISED_FIBRE;
198 ecmd->port = PORT_FIBRE;
199 }
1e336d0f
DS		 200 } else if (hw->phy.media_type == ixgbe_media_type_backplane) {
201 /* Set as FIBRE until SERDES defined in kernel */
46a72b35 202 if (hw->device_id == IXGBE_DEV_ID_82598_BX) {
2f21bdd3
DS		 203 ecmd->supported = (SUPPORTED_1000baseT_Full |
204 SUPPORTED_FIBRE);
205 ecmd->advertising = (ADVERTISED_1000baseT_Full |
206 ADVERTISED_FIBRE);
207 ecmd->port = PORT_FIBRE;
208 ecmd->autoneg = AUTONEG_DISABLE;
50d6c681
AD		 209 } else if ((hw->device_id == IXGBE_DEV_ID_82599_COMBO_BACKPLANE) ||
210 (hw->device_id == IXGBE_DEV_ID_82599_KX4_MEZZ)) {
211 ecmd->supported |= (SUPPORTED_1000baseT_Full |
212 SUPPORTED_Autoneg |
213 SUPPORTED_FIBRE);
214 ecmd->advertising = (ADVERTISED_10000baseT_Full |
215 ADVERTISED_1000baseT_Full |
216 ADVERTISED_Autoneg |
217 ADVERTISED_FIBRE);
218 ecmd->port = PORT_FIBRE;
46a72b35
MC		 219 } else {
220 ecmd->supported |= (SUPPORTED_1000baseT_Full |
221 SUPPORTED_FIBRE);
222 ecmd->advertising = (ADVERTISED_10000baseT_Full |
223 ADVERTISED_1000baseT_Full |
224 ADVERTISED_FIBRE);
225 ecmd->port = PORT_FIBRE;
1e336d0f 226 }
735441fb
AV		 227 } else {
228 ecmd->supported |= SUPPORTED_FIBRE;
229 ecmd->advertising = (ADVERTISED_10000baseT_Full |
b4617240 230 ADVERTISED_FIBRE);
735441fb 231 ecmd->port = PORT_FIBRE;
c44ade9e 232 ecmd->autoneg = AUTONEG_DISABLE;
735441fb 233 }
9a799d71 234
3b8626ba
PW		 235 /* Get PHY type */
236 switch (adapter->hw.phy.type) {
237 case ixgbe_phy_tn:
fe15e8e1 238 case ixgbe_phy_aq:
3b8626ba
PW		 239 case ixgbe_phy_cu_unknown:
240 /* Copper 10G-BASET */
241 ecmd->port = PORT_TP;
242 break;
243 case ixgbe_phy_qt:
244 ecmd->port = PORT_FIBRE;
245 break;
246 case ixgbe_phy_nl:
ea0a04df
DS		 247 case ixgbe_phy_sfp_passive_tyco:
248 case ixgbe_phy_sfp_passive_unknown:
3b8626ba
PW		 249 case ixgbe_phy_sfp_ftl:
250 case ixgbe_phy_sfp_avago:
251 case ixgbe_phy_sfp_intel:
252 case ixgbe_phy_sfp_unknown:
253 switch (adapter->hw.phy.sfp_type) {
254 /* SFP+ devices, further checking needed */
255 case ixgbe_sfp_type_da_cu:
256 case ixgbe_sfp_type_da_cu_core0:
257 case ixgbe_sfp_type_da_cu_core1:
258 ecmd->port = PORT_DA;
259 break;
260 case ixgbe_sfp_type_sr:
261 case ixgbe_sfp_type_lr:
262 case ixgbe_sfp_type_srlr_core0:
263 case ixgbe_sfp_type_srlr_core1:
264 ecmd->port = PORT_FIBRE;
265 break;
266 case ixgbe_sfp_type_not_present:
267 ecmd->port = PORT_NONE;
268 break;
cb836a97
DS		 269 case ixgbe_sfp_type_1g_cu_core0:
270 case ixgbe_sfp_type_1g_cu_core1:
271 ecmd->port = PORT_TP;
272 ecmd->supported = SUPPORTED_TP;
273 ecmd->advertising = (ADVERTISED_1000baseT_Full |
274 ADVERTISED_TP);
275 break;
3b8626ba
PW		 276 case ixgbe_sfp_type_unknown:
277 default:
278 ecmd->port = PORT_OTHER;
279 break;
280 }
281 break;
282 case ixgbe_phy_xaui:
283 ecmd->port = PORT_NONE;
284 break;
285 case ixgbe_phy_unknown:
286 case ixgbe_phy_generic:
287 case ixgbe_phy_sfp_unsupported:
288 default:
289 ecmd->port = PORT_OTHER;
290 break;
291 }
292
c44ade9e 293 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
735441fb 294 if (link_up) {
1b1c0a48
AS		 295 switch (link_speed) {
296 case IXGBE_LINK_SPEED_10GB_FULL:
70739497 297 ethtool_cmd_speed_set(ecmd, SPEED_10000);
1b1c0a48
AS		 298 break;
299 case IXGBE_LINK_SPEED_1GB_FULL:
70739497 300 ethtool_cmd_speed_set(ecmd, SPEED_1000);
1b1c0a48
AS		 301 break;
302 case IXGBE_LINK_SPEED_100_FULL:
70739497 303 ethtool_cmd_speed_set(ecmd, SPEED_100);
1b1c0a48
AS		 304 break;
305 default:
306 break;
307 }
9a799d71
AK		 308 ecmd->duplex = DUPLEX_FULL;
309 } else {
70739497 310 ethtool_cmd_speed_set(ecmd, -1);
9a799d71
AK		 311 ecmd->duplex = -1;
312 }
313
9a799d71
AK		 314 return 0;
315}
316
317static int ixgbe_set_settings(struct net_device *netdev,
b4617240 318 struct ethtool_cmd *ecmd)
9a799d71
AK		 319{
320 struct ixgbe_adapter *adapter = netdev_priv(netdev);
735441fb 321 struct ixgbe_hw *hw = &adapter->hw;
0befdb3e 322 u32 advertised, old;
74766013 323 s32 err = 0;
9a799d71 324
74766013 325 if ((hw->phy.media_type == ixgbe_media_type_copper) ||
a3801379 326 (hw->phy.multispeed_fiber)) {
0befdb3e
JB		 327 /* 10000/copper and 1000/copper must autoneg
328 * this function does not support any duplex forcing, but can
329 * limit the advertising of the adapter to only 10000 or 1000 */
330 if (ecmd->autoneg == AUTONEG_DISABLE)
331 return -EINVAL;
332
333 old = hw->phy.autoneg_advertised;
334 advertised = 0;
335 if (ecmd->advertising & ADVERTISED_10000baseT_Full)
336 advertised |= IXGBE_LINK_SPEED_10GB_FULL;
337
338 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
339 advertised |= IXGBE_LINK_SPEED_1GB_FULL;
340
2b642ca5
ET		 341 if (ecmd->advertising & ADVERTISED_100baseT_Full)
342 advertised |= IXGBE_LINK_SPEED_100_FULL;
343
0befdb3e 344 if (old == advertised)
74766013 345 return err;
0befdb3e 346 /* this sets the link speed and restarts auto-neg */
74766013 347 hw->mac.autotry_restart = true;
8620a103 348 err = hw->mac.ops.setup_link(hw, advertised, true, true);
0befdb3e 349 if (err) {
396e799c 350 e_info(probe, "setup link failed with code %d\n", err);
8620a103 351 hw->mac.ops.setup_link(hw, old, true, true);
0befdb3e 352 }
74766013
MC		 353 } else {
354 /* in this case we currently only support 10Gb/FULL */
25db0338 355 u32 speed = ethtool_cmd_speed(ecmd);
74766013 356 if ((ecmd->autoneg == AUTONEG_ENABLE) ||
a3801379 357 (ecmd->advertising != ADVERTISED_10000baseT_Full) ||
25db0338 358 (speed + ecmd->duplex != SPEED_10000 + DUPLEX_FULL))
74766013 359 return -EINVAL;
9a799d71
AK		 360 }
361
74766013 362 return err;
9a799d71
AK		 363}
364
365static void ixgbe_get_pauseparam(struct net_device *netdev,
b4617240 366 struct ethtool_pauseparam *pause)
9a799d71
AK		 367{
368 struct ixgbe_adapter *adapter = netdev_priv(netdev);
369 struct ixgbe_hw *hw = &adapter->hw;
370
71fd570b
DS		 371 /*
372 * Flow Control Autoneg isn't on if
373 * - we didn't ask for it OR
374 * - it failed, we know this by tx & rx being off
375 */
376 if (hw->fc.disable_fc_autoneg ||
377 (hw->fc.current_mode == ixgbe_fc_none))
378 pause->autoneg = 0;
379 else
380 pause->autoneg = 1;
9a799d71 381
0ecc061d 382 if (hw->fc.current_mode == ixgbe_fc_rx_pause) {
9a799d71 383 pause->rx_pause = 1;
0ecc061d 384 } else if (hw->fc.current_mode == ixgbe_fc_tx_pause) {
9a799d71 385 pause->tx_pause = 1;
0ecc061d 386 } else if (hw->fc.current_mode == ixgbe_fc_full) {
9a799d71
AK		 387 pause->rx_pause = 1;
388 pause->tx_pause = 1;
673ac604
AD		 389#ifdef CONFIG_DCB
390 } else if (hw->fc.current_mode == ixgbe_fc_pfc) {
391 pause->rx_pause = 0;
392 pause->tx_pause = 0;
393#endif
9a799d71
AK		 394 }
395}
396
397static int ixgbe_set_pauseparam(struct net_device *netdev,
b4617240 398 struct ethtool_pauseparam *pause)
9a799d71
AK		 399{
400 struct ixgbe_adapter *adapter = netdev_priv(netdev);
401 struct ixgbe_hw *hw = &adapter->hw;
620fa036 402 struct ixgbe_fc_info fc;
9a799d71 403
264857b8
PWJ		 404#ifdef CONFIG_DCB
405 if (adapter->dcb_cfg.pfc_mode_enable ||
406 ((hw->mac.type == ixgbe_mac_82598EB) &&
407 (adapter->flags & IXGBE_FLAG_DCB_ENABLED)))
408 return -EINVAL;
409
410#endif
620fa036
MC		 411 fc = hw->fc;
412
71fd570b 413 if (pause->autoneg != AUTONEG_ENABLE)
620fa036 414 fc.disable_fc_autoneg = true;
71fd570b 415 else
620fa036 416 fc.disable_fc_autoneg = false;
71fd570b 417
1c4f0ef8 418 if ((pause->rx_pause && pause->tx_pause) || pause->autoneg)
620fa036 419 fc.requested_mode = ixgbe_fc_full;
9a799d71 420 else if (pause->rx_pause && !pause->tx_pause)
620fa036 421 fc.requested_mode = ixgbe_fc_rx_pause;
9a799d71 422 else if (!pause->rx_pause && pause->tx_pause)
620fa036 423 fc.requested_mode = ixgbe_fc_tx_pause;
9a799d71 424 else if (!pause->rx_pause && !pause->tx_pause)
620fa036 425 fc.requested_mode = ixgbe_fc_none;
9c83b070
AV		 426 else
427 return -EINVAL;
9a799d71 428
264857b8 429#ifdef CONFIG_DCB
620fa036 430 adapter->last_lfc_mode = fc.requested_mode;
264857b8 431#endif
620fa036
MC		 432
433 /* if the thing changed then we'll update and use new autoneg */
434 if (memcmp(&fc, &hw->fc, sizeof(struct ixgbe_fc_info))) {
435 hw->fc = fc;
436 if (netif_running(netdev))
437 ixgbe_reinit_locked(adapter);
438 else
439 ixgbe_reset(adapter);
440 }
9a799d71
AK		 441
442 return 0;
443}
444
c988ee82
ET		 445static void ixgbe_do_reset(struct net_device *netdev)
446{
447 struct ixgbe_adapter *adapter = netdev_priv(netdev);
448
449 if (netif_running(netdev))
450 ixgbe_reinit_locked(adapter);
451 else
452 ixgbe_reset(adapter);
453}
454
9a799d71
AK		 455static u32 ixgbe_get_rx_csum(struct net_device *netdev)
456{
457 struct ixgbe_adapter *adapter = netdev_priv(netdev);
807540ba 458 return adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED;
9a799d71
AK		 459}
460
3a289264
ET		 461static void ixgbe_set_rsc(struct ixgbe_adapter *adapter)
462{
463 int i;
464
465 for (i = 0; i < adapter->num_rx_queues; i++) {
466 struct ixgbe_ring *ring = adapter->rx_ring[i];
467 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
468 set_ring_rsc_enabled(ring);
469 ixgbe_configure_rscctl(adapter, ring);
470 } else {
471 ixgbe_clear_rscctl(adapter, ring);
472 }
473 }
474}
475
2ba279e2
ET		 476static int ixgbe_set_rx_csum(struct net_device *netdev, u32 data)
477{
478 struct ixgbe_adapter *adapter = netdev_priv(netdev);
479 bool need_reset = false;
480
481 if (data) {
482 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
483 } else {
484 adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED;
485
486 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) {
487 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
488 netdev->features &= ~NETIF_F_LRO;
489 }
490
491 switch (adapter->hw.mac.type) {
492 case ixgbe_mac_X540:
493 ixgbe_set_rsc(adapter);
494 break;
495 case ixgbe_mac_82599EB:
496 need_reset = true;
497 break;
498 default:
499 break;
500 }
501 }
502
503 if (need_reset)
504 ixgbe_do_reset(netdev);
505
506 return 0;
507}
508
9a799d71
AK		 509static u32 ixgbe_get_tx_csum(struct net_device *netdev)
510{
22f32b7a 511 return (netdev->features & NETIF_F_IP_CSUM) != 0;
9a799d71
AK		 512}
513
514static int ixgbe_set_tx_csum(struct net_device *netdev, u32 data)
515{
45a5ead0 516 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b93a2226 517 u32 feature_list;
45a5ead0 518
b93a2226
DS		 519 feature_list = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
520 switch (adapter->hw.mac.type) {
521 case ixgbe_mac_82599EB:
522 case ixgbe_mac_X540:
523 feature_list |= NETIF_F_SCTP_CSUM;
524 break;
525 default:
526 break;
45a5ead0 527 }
b93a2226
DS		 528 if (data)
529 netdev->features |= feature_list;
530 else
531 netdev->features &= ~feature_list;
9a799d71
AK		 532
533 return 0;
534}
535
536static int ixgbe_set_tso(struct net_device *netdev, u32 data)
537{
9a799d71
AK		 538 if (data) {
539 netdev->features |= NETIF_F_TSO;
540 netdev->features |= NETIF_F_TSO6;
541 } else {
542 netdev->features &= ~NETIF_F_TSO;
543 netdev->features &= ~NETIF_F_TSO6;
544 }
545 return 0;
546}
547
548static u32 ixgbe_get_msglevel(struct net_device *netdev)
549{
550 struct ixgbe_adapter *adapter = netdev_priv(netdev);
551 return adapter->msg_enable;
552}
553
554static void ixgbe_set_msglevel(struct net_device *netdev, u32 data)
555{
556 struct ixgbe_adapter *adapter = netdev_priv(netdev);
557 adapter->msg_enable = data;
558}
559
560static int ixgbe_get_regs_len(struct net_device *netdev)
561{
562#define IXGBE_REGS_LEN 1128
563 return IXGBE_REGS_LEN * sizeof(u32);
564}
565
566#define IXGBE_GET_STAT(_A_, _R_) _A_->stats._R_
567
568static void ixgbe_get_regs(struct net_device *netdev,
b4617240 569 struct ethtool_regs *regs, void *p)
9a799d71
AK		 570{
571 struct ixgbe_adapter *adapter = netdev_priv(netdev);
572 struct ixgbe_hw *hw = &adapter->hw;
573 u32 *regs_buff = p;
574 u8 i;
575
576 memset(p, 0, IXGBE_REGS_LEN * sizeof(u32));
577
578 regs->version = (1 << 24) | hw->revision_id << 16 | hw->device_id;
579
580 /* General Registers */
581 regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL);
582 regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS);
583 regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
584 regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP);
585 regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP);
586 regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
587 regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER);
588 regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER);
589
590 /* NVM Register */
591 regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC);
592 regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD);
593 regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA);
594 regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL);
595 regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA);
596 regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL);
597 regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA);
598 regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT);
599 regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP);
600 regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC);
601
602 /* Interrupt */
98c00a1c
JB		 603 /* don't read EICR because it can clear interrupt causes, instead
604 * read EICS which is a shadow but doesn't clear EICR */
605 regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICS);
9a799d71
AK		 606 regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS);
607 regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS);
608 regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC);
609 regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC);
610 regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM);
611 regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0));
612 regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0));
613 regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT);
614 regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA);
c44ade9e 615 regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL(0));
9a799d71
AK		 616 regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE);
617
618 /* Flow Control */
619 regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP);
620 regs_buff[31] = IXGBE_READ_REG(hw, IXGBE_FCTTV(0));
621 regs_buff[32] = IXGBE_READ_REG(hw, IXGBE_FCTTV(1));
622 regs_buff[33] = IXGBE_READ_REG(hw, IXGBE_FCTTV(2));
623 regs_buff[34] = IXGBE_READ_REG(hw, IXGBE_FCTTV(3));
bd508178
AD		 624 for (i = 0; i < 8; i++) {
625 switch (hw->mac.type) {
626 case ixgbe_mac_82598EB:
627 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i));
628 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i));
629 break;
630 case ixgbe_mac_82599EB:
631 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL_82599(i));
632 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
633 break;
634 default:
635 break;
636 }
637 }
9a799d71
AK		 638 regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV);
639 regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS);
640
641 /* Receive DMA */
642 for (i = 0; i < 64; i++)
643 regs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
644 for (i = 0; i < 64; i++)
645 regs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
646 for (i = 0; i < 64; i++)
647 regs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
648 for (i = 0; i < 64; i++)
649 regs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
650 for (i = 0; i < 64; i++)
651 regs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
652 for (i = 0; i < 64; i++)
653 regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
654 for (i = 0; i < 16; i++)
655 regs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
656 for (i = 0; i < 16; i++)
657 regs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
658 regs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
659 for (i = 0; i < 8; i++)
660 regs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
661 regs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
662 regs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN);
663
664 /* Receive */
665 regs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
666 regs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL);
667 for (i = 0; i < 16; i++)
668 regs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i));
669 for (i = 0; i < 16; i++)
670 regs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i));
c44ade9e 671 regs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0));
9a799d71
AK		 672 regs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL);
673 regs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
674 regs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL);
675 regs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC);
676 regs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
677 for (i = 0; i < 8; i++)
678 regs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i));
679 for (i = 0; i < 8; i++)
680 regs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i));
681 regs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP);
682
683 /* Transmit */
684 for (i = 0; i < 32; i++)
685 regs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
686 for (i = 0; i < 32; i++)
687 regs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
688 for (i = 0; i < 32; i++)
689 regs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
690 for (i = 0; i < 32; i++)
691 regs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
692 for (i = 0; i < 32; i++)
693 regs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
694 for (i = 0; i < 32; i++)
695 regs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
696 for (i = 0; i < 32; i++)
697 regs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i));
698 for (i = 0; i < 32; i++)
699 regs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i));
700 regs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
701 for (i = 0; i < 16; i++)
702 regs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
703 regs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG);
704 for (i = 0; i < 8; i++)
705 regs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i));
706 regs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP);
707
708 /* Wake Up */
709 regs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC);
710 regs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC);
711 regs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS);
712 regs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV);
713 regs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT);
714 regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT);
715 regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL);
716 regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM);
11afc1b1 717 regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0));
9a799d71 718
673ac604 719 /* DCB */
9a799d71
AK		 720 regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS);
721 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS);
722 regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS);
723 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR);
724 for (i = 0; i < 8; i++)
725 regs_buff[833 + i] = IXGBE_READ_REG(hw, IXGBE_RT2CR(i));
726 for (i = 0; i < 8; i++)
727 regs_buff[841 + i] = IXGBE_READ_REG(hw, IXGBE_RT2SR(i));
728 for (i = 0; i < 8; i++)
729 regs_buff[849 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i));
730 for (i = 0; i < 8; i++)
731 regs_buff[857 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i));
732 for (i = 0; i < 8; i++)
733 regs_buff[865 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i));
734 for (i = 0; i < 8; i++)
735 regs_buff[873 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i));
736
737 /* Statistics */
738 regs_buff[881] = IXGBE_GET_STAT(adapter, crcerrs);
739 regs_buff[882] = IXGBE_GET_STAT(adapter, illerrc);
740 regs_buff[883] = IXGBE_GET_STAT(adapter, errbc);
741 regs_buff[884] = IXGBE_GET_STAT(adapter, mspdc);
742 for (i = 0; i < 8; i++)
743 regs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]);
744 regs_buff[893] = IXGBE_GET_STAT(adapter, mlfc);
745 regs_buff[894] = IXGBE_GET_STAT(adapter, mrfc);
746 regs_buff[895] = IXGBE_GET_STAT(adapter, rlec);
747 regs_buff[896] = IXGBE_GET_STAT(adapter, lxontxc);
748 regs_buff[897] = IXGBE_GET_STAT(adapter, lxonrxc);
749 regs_buff[898] = IXGBE_GET_STAT(adapter, lxofftxc);
750 regs_buff[899] = IXGBE_GET_STAT(adapter, lxoffrxc);
751 for (i = 0; i < 8; i++)
752 regs_buff[900 + i] = IXGBE_GET_STAT(adapter, pxontxc[i]);
753 for (i = 0; i < 8; i++)
754 regs_buff[908 + i] = IXGBE_GET_STAT(adapter, pxonrxc[i]);
755 for (i = 0; i < 8; i++)
756 regs_buff[916 + i] = IXGBE_GET_STAT(adapter, pxofftxc[i]);
757 for (i = 0; i < 8; i++)
758 regs_buff[924 + i] = IXGBE_GET_STAT(adapter, pxoffrxc[i]);
759 regs_buff[932] = IXGBE_GET_STAT(adapter, prc64);
760 regs_buff[933] = IXGBE_GET_STAT(adapter, prc127);
761 regs_buff[934] = IXGBE_GET_STAT(adapter, prc255);
762 regs_buff[935] = IXGBE_GET_STAT(adapter, prc511);
763 regs_buff[936] = IXGBE_GET_STAT(adapter, prc1023);
764 regs_buff[937] = IXGBE_GET_STAT(adapter, prc1522);
765 regs_buff[938] = IXGBE_GET_STAT(adapter, gprc);
766 regs_buff[939] = IXGBE_GET_STAT(adapter, bprc);
767 regs_buff[940] = IXGBE_GET_STAT(adapter, mprc);
768 regs_buff[941] = IXGBE_GET_STAT(adapter, gptc);
769 regs_buff[942] = IXGBE_GET_STAT(adapter, gorc);
770 regs_buff[944] = IXGBE_GET_STAT(adapter, gotc);
771 for (i = 0; i < 8; i++)
772 regs_buff[946 + i] = IXGBE_GET_STAT(adapter, rnbc[i]);
773 regs_buff[954] = IXGBE_GET_STAT(adapter, ruc);
774 regs_buff[955] = IXGBE_GET_STAT(adapter, rfc);
775 regs_buff[956] = IXGBE_GET_STAT(adapter, roc);
776 regs_buff[957] = IXGBE_GET_STAT(adapter, rjc);
777 regs_buff[958] = IXGBE_GET_STAT(adapter, mngprc);
778 regs_buff[959] = IXGBE_GET_STAT(adapter, mngpdc);
779 regs_buff[960] = IXGBE_GET_STAT(adapter, mngptc);
780 regs_buff[961] = IXGBE_GET_STAT(adapter, tor);
781 regs_buff[963] = IXGBE_GET_STAT(adapter, tpr);
782 regs_buff[964] = IXGBE_GET_STAT(adapter, tpt);
783 regs_buff[965] = IXGBE_GET_STAT(adapter, ptc64);
784 regs_buff[966] = IXGBE_GET_STAT(adapter, ptc127);
785 regs_buff[967] = IXGBE_GET_STAT(adapter, ptc255);
786 regs_buff[968] = IXGBE_GET_STAT(adapter, ptc511);
787 regs_buff[969] = IXGBE_GET_STAT(adapter, ptc1023);
788 regs_buff[970] = IXGBE_GET_STAT(adapter, ptc1522);
789 regs_buff[971] = IXGBE_GET_STAT(adapter, mptc);
790 regs_buff[972] = IXGBE_GET_STAT(adapter, bptc);
791 regs_buff[973] = IXGBE_GET_STAT(adapter, xec);
792 for (i = 0; i < 16; i++)
793 regs_buff[974 + i] = IXGBE_GET_STAT(adapter, qprc[i]);
794 for (i = 0; i < 16; i++)
795 regs_buff[990 + i] = IXGBE_GET_STAT(adapter, qptc[i]);
796 for (i = 0; i < 16; i++)
797 regs_buff[1006 + i] = IXGBE_GET_STAT(adapter, qbrc[i]);
798 for (i = 0; i < 16; i++)
799 regs_buff[1022 + i] = IXGBE_GET_STAT(adapter, qbtc[i]);
800
801 /* MAC */
802 regs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG);
803 regs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
804 regs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
805 regs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0);
806 regs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1);
807 regs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
808 regs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
809 regs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP);
810 regs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP);
811 regs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0);
812 regs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1);
813 regs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP);
814 regs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA);
815 regs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE);
816 regs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD);
817 regs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS);
818 regs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA);
819 regs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD);
820 regs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD);
821 regs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD);
822 regs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG);
823 regs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1);
824 regs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2);
825 regs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS);
826 regs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC);
827 regs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS);
828 regs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC);
829 regs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS);
830 regs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
831 regs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3);
832 regs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1);
833 regs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2);
834 regs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
835
836 /* Diagnostic */
837 regs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL);
838 for (i = 0; i < 8; i++)
98c00a1c 839 regs_buff[1072 + i] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i));
9a799d71 840 regs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN);
98c00a1c
JB		 841 for (i = 0; i < 4; i++)
842 regs_buff[1081 + i] = IXGBE_READ_REG(hw, IXGBE_RIC_DW(i));
9a799d71
AK		 843 regs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE);
844 regs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL);
845 for (i = 0; i < 8; i++)
98c00a1c 846 regs_buff[1087 + i] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i));
9a799d71 847 regs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN);
98c00a1c
JB		 848 for (i = 0; i < 4; i++)
849 regs_buff[1096 + i] = IXGBE_READ_REG(hw, IXGBE_TIC_DW(i));
9a799d71
AK		 850 regs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE);
851 regs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL);
852 regs_buff[1102] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA0);
853 regs_buff[1103] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA1);
854 regs_buff[1104] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA2);
855 regs_buff[1105] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA3);
856 regs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL);
857 regs_buff[1107] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA0);
858 regs_buff[1108] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA1);
859 regs_buff[1109] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA2);
860 regs_buff[1110] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA3);
861 for (i = 0; i < 8; i++)
98c00a1c 862 regs_buff[1111 + i] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i));
9a799d71
AK		 863 regs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL);
864 regs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1);
865 regs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2);
866 regs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1);
867 regs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2);
868 regs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS);
869 regs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL);
870 regs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC);
871 regs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC);
872}
873
874static int ixgbe_get_eeprom_len(struct net_device *netdev)
875{
876 struct ixgbe_adapter *adapter = netdev_priv(netdev);
877 return adapter->hw.eeprom.word_size * 2;
878}
879
880static int ixgbe_get_eeprom(struct net_device *netdev,
b4617240 881 struct ethtool_eeprom *eeprom, u8 *bytes)
9a799d71
AK		 882{
883 struct ixgbe_adapter *adapter = netdev_priv(netdev);
884 struct ixgbe_hw *hw = &adapter->hw;
885 u16 *eeprom_buff;
886 int first_word, last_word, eeprom_len;
887 int ret_val = 0;
888 u16 i;
889
890 if (eeprom->len == 0)
891 return -EINVAL;
892
893 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
894
895 first_word = eeprom->offset >> 1;
896 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
897 eeprom_len = last_word - first_word + 1;
898
899 eeprom_buff = kmalloc(sizeof(u16) * eeprom_len, GFP_KERNEL);
900 if (!eeprom_buff)
901 return -ENOMEM;
902
68c7005d
ET		 903 ret_val = hw->eeprom.ops.read_buffer(hw, first_word, eeprom_len,
904 eeprom_buff);
9a799d71
AK		 905
906 /* Device's eeprom is always little-endian, word addressable */
907 for (i = 0; i < eeprom_len; i++)
908 le16_to_cpus(&eeprom_buff[i]);
909
910 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len);
911 kfree(eeprom_buff);
912
913 return ret_val;
914}
915
916static void ixgbe_get_drvinfo(struct net_device *netdev,
b4617240 917 struct ethtool_drvinfo *drvinfo)
9a799d71
AK		 918{
919 struct ixgbe_adapter *adapter = netdev_priv(netdev);
34b0368c 920 char firmware_version[32];
9a799d71 921
9fe93afd
DS		 922 strncpy(drvinfo->driver, ixgbe_driver_name,
923 sizeof(drvinfo->driver) - 1);
083fc582 924 strncpy(drvinfo->version, ixgbe_driver_version,
9fe93afd 925 sizeof(drvinfo->version) - 1);
083fc582
DS		 926
927 snprintf(firmware_version, sizeof(firmware_version), "%d.%d-%d",
928 (adapter->eeprom_version & 0xF000) >> 12,
929 (adapter->eeprom_version & 0x0FF0) >> 4,
930 adapter->eeprom_version & 0x000F);
931
932 strncpy(drvinfo->fw_version, firmware_version,
933 sizeof(drvinfo->fw_version));
934 strncpy(drvinfo->bus_info, pci_name(adapter->pdev),
935 sizeof(drvinfo->bus_info));
9a799d71 936 drvinfo->n_stats = IXGBE_STATS_LEN;
da4dd0f7 937 drvinfo->testinfo_len = IXGBE_TEST_LEN;
9a799d71
AK		 938 drvinfo->regdump_len = ixgbe_get_regs_len(netdev);
939}
940
941static void ixgbe_get_ringparam(struct net_device *netdev,
b4617240 942 struct ethtool_ringparam *ring)
9a799d71
AK		 943{
944 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4a0b9ca0
PW		 945 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
946 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
9a799d71
AK		 947
948 ring->rx_max_pending = IXGBE_MAX_RXD;
949 ring->tx_max_pending = IXGBE_MAX_TXD;
950 ring->rx_mini_max_pending = 0;
951 ring->rx_jumbo_max_pending = 0;
952 ring->rx_pending = rx_ring->count;
953 ring->tx_pending = tx_ring->count;
954 ring->rx_mini_pending = 0;
955 ring->rx_jumbo_pending = 0;
956}
957
958static int ixgbe_set_ringparam(struct net_device *netdev,
b4617240 959 struct ethtool_ringparam *ring)
9a799d71
AK		 960{
961 struct ixgbe_adapter *adapter = netdev_priv(netdev);
f9ed8854 962 struct ixgbe_ring *temp_tx_ring, *temp_rx_ring;
759884b4 963 int i, err = 0;
c431f97e 964 u32 new_rx_count, new_tx_count;
f9ed8854 965 bool need_update = false;
9a799d71
AK		 966
967 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
968 return -EINVAL;
969
970 new_rx_count = max(ring->rx_pending, (u32)IXGBE_MIN_RXD);
971 new_rx_count = min(new_rx_count, (u32)IXGBE_MAX_RXD);
972 new_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE);
973
974 new_tx_count = max(ring->tx_pending, (u32)IXGBE_MIN_TXD);
975 new_tx_count = min(new_tx_count, (u32)IXGBE_MAX_TXD);
976 new_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE);
977
4a0b9ca0
PW		 978 if ((new_tx_count == adapter->tx_ring[0]->count) &&
979 (new_rx_count == adapter->rx_ring[0]->count)) {
9a799d71
AK		 980 /* nothing to do */
981 return 0;
982 }
983
d4f80882 984 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 985 usleep_range(1000, 2000);
d4f80882 986
759884b4
AD		 987 if (!netif_running(adapter->netdev)) {
988 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 989 adapter->tx_ring[i]->count = new_tx_count;
759884b4 990 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 991 adapter->rx_ring[i]->count = new_rx_count;
759884b4
AD		 992 adapter->tx_ring_count = new_tx_count;
993 adapter->rx_ring_count = new_rx_count;
4a0b9ca0 994 goto clear_reset;
759884b4
AD		 995 }
996
4a0b9ca0 997 temp_tx_ring = vmalloc(adapter->num_tx_queues * sizeof(struct ixgbe_ring));
f9ed8854
MC		 998 if (!temp_tx_ring) {
999 err = -ENOMEM;
4a0b9ca0 1000 goto clear_reset;
f9ed8854
MC		 1001 }
1002
1003 if (new_tx_count != adapter->tx_ring_count) {
9a799d71 1004 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0
PW		 1005 memcpy(&temp_tx_ring[i], adapter->tx_ring[i],
1006 sizeof(struct ixgbe_ring));
f9ed8854 1007 temp_tx_ring[i].count = new_tx_count;
b6ec895e 1008 err = ixgbe_setup_tx_resources(&temp_tx_ring[i]);
9a799d71 1009 if (err) {
c431f97e
JB		 1010 while (i) {
1011 i--;
b6ec895e 1012 ixgbe_free_tx_resources(&temp_tx_ring[i]);
c431f97e 1013 }
4a0b9ca0 1014 goto clear_reset;
9a799d71 1015 }
9a799d71 1016 }
f9ed8854 1017 need_update = true;
9a799d71
AK		 1018 }
1019
4a0b9ca0
PW		 1020 temp_rx_ring = vmalloc(adapter->num_rx_queues * sizeof(struct ixgbe_ring));
1021 if (!temp_rx_ring) {
f9ed8854
MC		 1022 err = -ENOMEM;
1023 goto err_setup;
d3fa4721 1024 }
9a799d71 1025
f9ed8854 1026 if (new_rx_count != adapter->rx_ring_count) {
c431f97e 1027 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 1028 memcpy(&temp_rx_ring[i], adapter->rx_ring[i],
1029 sizeof(struct ixgbe_ring));
f9ed8854 1030 temp_rx_ring[i].count = new_rx_count;
b6ec895e 1031 err = ixgbe_setup_rx_resources(&temp_rx_ring[i]);
9a799d71 1032 if (err) {
c431f97e
JB		 1033 while (i) {
1034 i--;
b6ec895e 1035 ixgbe_free_rx_resources(&temp_rx_ring[i]);
c431f97e 1036 }
9a799d71
AK		 1037 goto err_setup;
1038 }
9a799d71 1039 }
f9ed8854
MC		 1040 need_update = true;
1041 }
1042
1043 /* if rings need to be updated, here's the place to do it in one shot */
1044 if (need_update) {
759884b4 1045 ixgbe_down(adapter);
f9ed8854
MC		 1046
1047 /* tx */
1048 if (new_tx_count != adapter->tx_ring_count) {
4a0b9ca0 1049 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 1050 ixgbe_free_tx_resources(adapter->tx_ring[i]);
4a0b9ca0
PW		 1051 memcpy(adapter->tx_ring[i], &temp_tx_ring[i],
1052 sizeof(struct ixgbe_ring));
1053 }
f9ed8854
MC		 1054 adapter->tx_ring_count = new_tx_count;
1055 }
1056
1057 /* rx */
1058 if (new_rx_count != adapter->rx_ring_count) {
4a0b9ca0 1059 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 1060 ixgbe_free_rx_resources(adapter->rx_ring[i]);
4a0b9ca0
PW		 1061 memcpy(adapter->rx_ring[i], &temp_rx_ring[i],
1062 sizeof(struct ixgbe_ring));
1063 }
f9ed8854
MC		 1064 adapter->rx_ring_count = new_rx_count;
1065 }
f9ed8854 1066 ixgbe_up(adapter);
759884b4 1067 }
4a0b9ca0
PW		 1068
1069 vfree(temp_rx_ring);
f9ed8854 1070err_setup:
4a0b9ca0
PW		 1071 vfree(temp_tx_ring);
1072clear_reset:
d4f80882 1073 clear_bit(__IXGBE_RESETTING, &adapter->state);
9a799d71
AK		 1074 return err;
1075}
1076
b9f2c044 1077static int ixgbe_get_sset_count(struct net_device *netdev, int sset)
9a799d71 1078{
b9f2c044 1079 switch (sset) {
da4dd0f7
PWJ		 1080 case ETH_SS_TEST:
1081 return IXGBE_TEST_LEN;
b9f2c044
JG		 1082 case ETH_SS_STATS:
1083 return IXGBE_STATS_LEN;
1084 default:
1085 return -EOPNOTSUPP;
1086 }
9a799d71
AK		 1087}
1088
1089static void ixgbe_get_ethtool_stats(struct net_device *netdev,
b4617240 1090 struct ethtool_stats *stats, u64 *data)
9a799d71
AK		 1091{
1092 struct ixgbe_adapter *adapter = netdev_priv(netdev);
28172739
ED		 1093 struct rtnl_link_stats64 temp;
1094 const struct rtnl_link_stats64 *net_stats;
de1036b1
ED		 1095 unsigned int start;
1096 struct ixgbe_ring *ring;
1097 int i, j;
29c3a050 1098 char *p = NULL;
9a799d71
AK		 1099
1100 ixgbe_update_stats(adapter);
28172739 1101 net_stats = dev_get_stats(netdev, &temp);
9a799d71 1102 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
29c3a050
AK		 1103 switch (ixgbe_gstrings_stats[i].type) {
1104 case NETDEV_STATS:
28172739 1105 p = (char *) net_stats +
29c3a050
AK		 1106 ixgbe_gstrings_stats[i].stat_offset;
1107 break;
1108 case IXGBE_STATS:
1109 p = (char *) adapter +
1110 ixgbe_gstrings_stats[i].stat_offset;
1111 break;
1112 }
1113
9a799d71 1114 data[i] = (ixgbe_gstrings_stats[i].sizeof_stat ==
b4617240 1115 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
9a799d71
AK		 1116 }
1117 for (j = 0; j < adapter->num_tx_queues; j++) {
de1036b1
ED		 1118 ring = adapter->tx_ring[j];
1119 do {
1120 start = u64_stats_fetch_begin_bh(&ring->syncp);
1121 data[i] = ring->stats.packets;
1122 data[i+1] = ring->stats.bytes;
1123 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
1124 i += 2;
9a799d71
AK		 1125 }
1126 for (j = 0; j < adapter->num_rx_queues; j++) {
de1036b1
ED		 1127 ring = adapter->rx_ring[j];
1128 do {
1129 start = u64_stats_fetch_begin_bh(&ring->syncp);
1130 data[i] = ring->stats.packets;
1131 data[i+1] = ring->stats.bytes;
1132 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
1133 i += 2;
9a799d71 1134 }
2f90b865
AD		 1135 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
1136 for (j = 0; j < MAX_TX_PACKET_BUFFERS; j++) {
1137 data[i++] = adapter->stats.pxontxc[j];
1138 data[i++] = adapter->stats.pxofftxc[j];
1139 }
1140 for (j = 0; j < MAX_RX_PACKET_BUFFERS; j++) {
1141 data[i++] = adapter->stats.pxonrxc[j];
1142 data[i++] = adapter->stats.pxoffrxc[j];
1143 }
1144 }
9a799d71
AK		 1145}
1146
1147static void ixgbe_get_strings(struct net_device *netdev, u32 stringset,
b4617240 1148 u8 *data)
9a799d71
AK		 1149{
1150 struct ixgbe_adapter *adapter = netdev_priv(netdev);
c44ade9e 1151 char *p = (char *)data;
9a799d71
AK		 1152 int i;
1153
1154 switch (stringset) {
da4dd0f7
PWJ		 1155 case ETH_SS_TEST:
1156 memcpy(data, *ixgbe_gstrings_test,
1157 IXGBE_TEST_LEN * ETH_GSTRING_LEN);
1158 break;
9a799d71
AK		 1159 case ETH_SS_STATS:
1160 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
1161 memcpy(p, ixgbe_gstrings_stats[i].stat_string,
1162 ETH_GSTRING_LEN);
1163 p += ETH_GSTRING_LEN;
1164 }
1165 for (i = 0; i < adapter->num_tx_queues; i++) {
1166 sprintf(p, "tx_queue_%u_packets", i);
1167 p += ETH_GSTRING_LEN;
1168 sprintf(p, "tx_queue_%u_bytes", i);
1169 p += ETH_GSTRING_LEN;
1170 }
1171 for (i = 0; i < adapter->num_rx_queues; i++) {
1172 sprintf(p, "rx_queue_%u_packets", i);
1173 p += ETH_GSTRING_LEN;
1174 sprintf(p, "rx_queue_%u_bytes", i);
1175 p += ETH_GSTRING_LEN;
1176 }
2f90b865
AD		 1177 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
1178 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
1179 sprintf(p, "tx_pb_%u_pxon", i);
bfb8cc31
DS		 1180 p += ETH_GSTRING_LEN;
1181 sprintf(p, "tx_pb_%u_pxoff", i);
1182 p += ETH_GSTRING_LEN;
2f90b865
AD		 1183 }
1184 for (i = 0; i < MAX_RX_PACKET_BUFFERS; i++) {
bfb8cc31
DS		 1185 sprintf(p, "rx_pb_%u_pxon", i);
1186 p += ETH_GSTRING_LEN;
1187 sprintf(p, "rx_pb_%u_pxoff", i);
1188 p += ETH_GSTRING_LEN;
2f90b865
AD		 1189 }
1190 }
b4617240 1191 /* BUG_ON(p - data != IXGBE_STATS_LEN * ETH_GSTRING_LEN); */
9a799d71
AK		 1192 break;
1193 }
1194}
1195
da4dd0f7
PWJ		 1196static int ixgbe_link_test(struct ixgbe_adapter *adapter, u64 *data)
1197{
1198 struct ixgbe_hw *hw = &adapter->hw;
1199 bool link_up;
1200 u32 link_speed = 0;
1201 *data = 0;
1202
1203 hw->mac.ops.check_link(hw, &link_speed, &link_up, true);
1204 if (link_up)
1205 return *data;
1206 else
1207 *data = 1;
1208 return *data;
1209}
1210
1211/* ethtool register test data */
1212struct ixgbe_reg_test {
1213 u16 reg;
1214 u8 array_len;
1215 u8 test_type;
1216 u32 mask;
1217 u32 write;
1218};
1219
1220/* In the hardware, registers are laid out either singly, in arrays
1221 * spaced 0x40 bytes apart, or in contiguous tables. We assume
1222 * most tests take place on arrays or single registers (handled
1223 * as a single-element array) and special-case the tables.
1224 * Table tests are always pattern tests.
1225 *
1226 * We also make provision for some required setup steps by specifying
1227 * registers to be written without any read-back testing.
1228 */
1229
1230#define PATTERN_TEST 1
1231#define SET_READ_TEST 2
1232#define WRITE_NO_TEST 3
1233#define TABLE32_TEST 4
1234#define TABLE64_TEST_LO 5
1235#define TABLE64_TEST_HI 6
1236
1237/* default 82599 register test */
66744500 1238static const struct ixgbe_reg_test reg_test_82599[] = {
da4dd0f7
PWJ		 1239 { IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1240 { IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1241 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1242 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1243 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 },
1244 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1245 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1246 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1247 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1248 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1249 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1250 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1251 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1252 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1253 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFF80 },
1254 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000001, 0x00000001 },
1255 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1256 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF },
1257 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1258 { 0, 0, 0, 0 }
1259};
1260
1261/* default 82598 register test */
66744500 1262static const struct ixgbe_reg_test reg_test_82598[] = {
da4dd0f7
PWJ		 1263 { IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1264 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1265 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1266 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1267 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1268 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1269 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1270 /* Enable all four RX queues before testing. */
1271 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1272 /* RDH is read-only for 82598, only test RDT. */
1273 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1274 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1275 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1276 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1277 { IXGBE_TIPG, 1, PATTERN_TEST, 0x000000FF, 0x000000FF },
1278 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1279 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1280 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1281 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000003, 0x00000003 },
1282 { IXGBE_DTXCTL, 1, SET_READ_TEST, 0x00000005, 0x00000005 },
1283 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1284 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x800CFFFF, 0x800CFFFF },
1285 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1286 { 0, 0, 0, 0 }
1287};
1288
95a46011
ET		 1289static bool reg_pattern_test(struct ixgbe_adapter *adapter, u64 *data, int reg,
1290 u32 mask, u32 write)
1291{
1292 u32 pat, val, before;
1293 static const u32 test_pattern[] = {
1294 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
1295
1296 for (pat = 0; pat < ARRAY_SIZE(test_pattern); pat++) {
1297 before = readl(adapter->hw.hw_addr + reg);
1298 writel((test_pattern[pat] & write),
1299 (adapter->hw.hw_addr + reg));
1300 val = readl(adapter->hw.hw_addr + reg);
1301 if (val != (test_pattern[pat] & write & mask)) {
1302 e_err(drv, "pattern test reg %04X failed: got "
1303 "0x%08X expected 0x%08X\n",
1304 reg, val, (test_pattern[pat] & write & mask));
1305 *data = reg;
1306 writel(before, adapter->hw.hw_addr + reg);
1307 return 1;
1308 }
1309 writel(before, adapter->hw.hw_addr + reg);
1310 }
1311 return 0;
da4dd0f7
PWJ		 1312}
1313
95a46011
ET		 1314static bool reg_set_and_check(struct ixgbe_adapter *adapter, u64 *data, int reg,
1315 u32 mask, u32 write)
1316{
1317 u32 val, before;
1318 before = readl(adapter->hw.hw_addr + reg);
1319 writel((write & mask), (adapter->hw.hw_addr + reg));
1320 val = readl(adapter->hw.hw_addr + reg);
1321 if ((write & mask) != (val & mask)) {
1322 e_err(drv, "set/check reg %04X test failed: got 0x%08X "
1323 "expected 0x%08X\n", reg, (val & mask), (write & mask));
1324 *data = reg;
1325 writel(before, (adapter->hw.hw_addr + reg));
1326 return 1;
1327 }
1328 writel(before, (adapter->hw.hw_addr + reg));
1329 return 0;
da4dd0f7
PWJ		 1330}
1331
95a46011
ET		 1332#define REG_PATTERN_TEST(reg, mask, write) \
1333 do { \
1334 if (reg_pattern_test(adapter, data, reg, mask, write)) \
1335 return 1; \
1336 } while (0) \
1337
1338
1339#define REG_SET_AND_CHECK(reg, mask, write) \
1340 do { \
1341 if (reg_set_and_check(adapter, data, reg, mask, write)) \
1342 return 1; \
1343 } while (0) \
1344
da4dd0f7
PWJ		 1345static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data)
1346{
66744500 1347 const struct ixgbe_reg_test *test;
da4dd0f7
PWJ		 1348 u32 value, before, after;
1349 u32 i, toggle;
1350
bd508178
AD		 1351 switch (adapter->hw.mac.type) {
1352 case ixgbe_mac_82598EB:
da4dd0f7
PWJ		 1353 toggle = 0x7FFFF3FF;
1354 test = reg_test_82598;
bd508178
AD		 1355 break;
1356 case ixgbe_mac_82599EB:
b93a2226 1357 case ixgbe_mac_X540:
bd508178
AD		 1358 toggle = 0x7FFFF30F;
1359 test = reg_test_82599;
1360 break;
1361 default:
1362 *data = 1;
1363 return 1;
1364 break;
da4dd0f7
PWJ		 1365 }
1366
1367 /*
1368 * Because the status register is such a special case,
1369 * we handle it separately from the rest of the register
1370 * tests. Some bits are read-only, some toggle, and some
1371 * are writeable on newer MACs.
1372 */
1373 before = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS);
1374 value = (IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle);
1375 IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, toggle);
1376 after = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle;
1377 if (value != after) {
396e799c
ET		 1378 e_err(drv, "failed STATUS register test got: 0x%08X "
1379 "expected: 0x%08X\n", after, value);
da4dd0f7
PWJ		 1380 *data = 1;
1381 return 1;
1382 }
1383 /* restore previous status */
1384 IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, before);
1385
1386 /*
1387 * Perform the remainder of the register test, looping through
1388 * the test table until we either fail or reach the null entry.
1389 */
1390 while (test->reg) {
1391 for (i = 0; i < test->array_len; i++) {
1392 switch (test->test_type) {
1393 case PATTERN_TEST:
1394 REG_PATTERN_TEST(test->reg + (i * 0x40),
95a46011
ET		 1395 test->mask,
1396 test->write);
da4dd0f7
PWJ		 1397 break;
1398 case SET_READ_TEST:
1399 REG_SET_AND_CHECK(test->reg + (i * 0x40),
95a46011
ET		 1400 test->mask,
1401 test->write);
da4dd0f7
PWJ		 1402 break;
1403 case WRITE_NO_TEST:
1404 writel(test->write,
1405 (adapter->hw.hw_addr + test->reg)
1406 + (i * 0x40));
1407 break;
1408 case TABLE32_TEST:
1409 REG_PATTERN_TEST(test->reg + (i * 4),
95a46011
ET		 1410 test->mask,
1411 test->write);
da4dd0f7
PWJ		 1412 break;
1413 case TABLE64_TEST_LO:
1414 REG_PATTERN_TEST(test->reg + (i * 8),
95a46011
ET		 1415 test->mask,
1416 test->write);
da4dd0f7
PWJ		 1417 break;
1418 case TABLE64_TEST_HI:
1419 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
95a46011
ET		 1420 test->mask,
1421 test->write);
da4dd0f7
PWJ		 1422 break;
1423 }
1424 }
1425 test++;
1426 }
1427
1428 *data = 0;
1429 return 0;
1430}
1431
1432static int ixgbe_eeprom_test(struct ixgbe_adapter *adapter, u64 *data)
1433{
1434 struct ixgbe_hw *hw = &adapter->hw;
1435 if (hw->eeprom.ops.validate_checksum(hw, NULL))
1436 *data = 1;
1437 else
1438 *data = 0;
1439 return *data;
1440}
1441
1442static irqreturn_t ixgbe_test_intr(int irq, void *data)
1443{
1444 struct net_device *netdev = (struct net_device *) data;
1445 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1446
1447 adapter->test_icr |= IXGBE_READ_REG(&adapter->hw, IXGBE_EICR);
1448
1449 return IRQ_HANDLED;
1450}
1451
1452static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
1453{
1454 struct net_device *netdev = adapter->netdev;
1455 u32 mask, i = 0, shared_int = true;
1456 u32 irq = adapter->pdev->irq;
1457
1458 *data = 0;
1459
1460 /* Hook up test interrupt handler just for this test */
1461 if (adapter->msix_entries) {
1462 /* NOTE: we don't test MSI-X interrupts here, yet */
1463 return 0;
1464 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1465 shared_int = false;
a0607fd3 1466 if (request_irq(irq, ixgbe_test_intr, 0, netdev->name,
da4dd0f7
PWJ		 1467 netdev)) {
1468 *data = 1;
1469 return -1;
1470 }
a0607fd3 1471 } else if (!request_irq(irq, ixgbe_test_intr, IRQF_PROBE_SHARED,
da4dd0f7
PWJ		 1472 netdev->name, netdev)) {
1473 shared_int = false;
a0607fd3 1474 } else if (request_irq(irq, ixgbe_test_intr, IRQF_SHARED,
da4dd0f7
PWJ		 1475 netdev->name, netdev)) {
1476 *data = 1;
1477 return -1;
1478 }
396e799c
ET		 1479 e_info(hw, "testing %s interrupt\n", shared_int ?
1480 "shared" : "unshared");
da4dd0f7
PWJ		 1481
1482 /* Disable all the interrupts */
1483 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
032b4325 1484 usleep_range(10000, 20000);
da4dd0f7
PWJ		 1485
1486 /* Test each interrupt */
1487 for (; i < 10; i++) {
1488 /* Interrupt to test */
1489 mask = 1 << i;
1490
1491 if (!shared_int) {
1492 /*
1493 * Disable the interrupts to be reported in
1494 * the cause register and then force the same
1495 * interrupt and see if one gets posted. If
1496 * an interrupt was posted to the bus, the
1497 * test failed.
1498 */
1499 adapter->test_icr = 0;
1500 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1501 ~mask & 0x00007FFF);
1502 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1503 ~mask & 0x00007FFF);
032b4325 1504 usleep_range(10000, 20000);
da4dd0f7
PWJ		 1505
1506 if (adapter->test_icr & mask) {
1507 *data = 3;
1508 break;
1509 }
1510 }
1511
1512 /*
1513 * Enable the interrupt to be reported in the cause
1514 * register and then force the same interrupt and see
1515 * if one gets posted. If an interrupt was not posted
1516 * to the bus, the test failed.
1517 */
1518 adapter->test_icr = 0;
1519 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1520 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
032b4325 1521 usleep_range(10000, 20000);
da4dd0f7
PWJ		 1522
1523 if (!(adapter->test_icr &mask)) {
1524 *data = 4;
1525 break;
1526 }
1527
1528 if (!shared_int) {
1529 /*
1530 * Disable the other interrupts to be reported in
1531 * the cause register and then force the other
1532 * interrupts and see if any get posted. If
1533 * an interrupt was posted to the bus, the
1534 * test failed.
1535 */
1536 adapter->test_icr = 0;
1537 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1538 ~mask & 0x00007FFF);
1539 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1540 ~mask & 0x00007FFF);
032b4325 1541 usleep_range(10000, 20000);
da4dd0f7
PWJ		 1542
1543 if (adapter->test_icr) {
1544 *data = 5;
1545 break;
1546 }
1547 }
1548 }
1549
1550 /* Disable all the interrupts */
1551 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
032b4325 1552 usleep_range(10000, 20000);
da4dd0f7
PWJ		 1553
1554 /* Unhook test interrupt handler */
1555 free_irq(irq, netdev);
1556
1557 return *data;
1558}
1559
1560static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter)
1561{
1562 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1563 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1564 struct ixgbe_hw *hw = &adapter->hw;
da4dd0f7 1565 u32 reg_ctl;
da4dd0f7
PWJ		 1566
1567 /* shut down the DMA engines now so they can be reinitialized later */
1568
1569 /* first Rx */
1570 reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1571 reg_ctl &= ~IXGBE_RXCTRL_RXEN;
1572 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_ctl);
2d39d576 1573 ixgbe_disable_rx_queue(adapter, rx_ring);
da4dd0f7
PWJ		 1574
1575 /* now Tx */
84418e3b 1576 reg_ctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx));
da4dd0f7 1577 reg_ctl &= ~IXGBE_TXDCTL_ENABLE;
84418e3b
AD		 1578 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx), reg_ctl);
1579
bd508178
AD		 1580 switch (hw->mac.type) {
1581 case ixgbe_mac_82599EB:
b93a2226 1582 case ixgbe_mac_X540:
da4dd0f7
PWJ		 1583 reg_ctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1584 reg_ctl &= ~IXGBE_DMATXCTL_TE;
1585 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg_ctl);
bd508178
AD		 1586 break;
1587 default:
1588 break;
da4dd0f7
PWJ		 1589 }
1590
1591 ixgbe_reset(adapter);
1592
b6ec895e
AD		 1593 ixgbe_free_tx_resources(&adapter->test_tx_ring);
1594 ixgbe_free_rx_resources(&adapter->test_rx_ring);
da4dd0f7
PWJ		 1595}
1596
1597static int ixgbe_setup_desc_rings(struct ixgbe_adapter *adapter)
1598{
1599 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1600 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
da4dd0f7 1601 u32 rctl, reg_data;
84418e3b
AD		 1602 int ret_val;
1603 int err;
da4dd0f7
PWJ		 1604
1605 /* Setup Tx descriptor ring and Tx buffers */
84418e3b
AD		 1606 tx_ring->count = IXGBE_DEFAULT_TXD;
1607 tx_ring->queue_index = 0;
b6ec895e 1608 tx_ring->dev = &adapter->pdev->dev;
fc77dc3c 1609 tx_ring->netdev = adapter->netdev;
84418e3b
AD		 1610 tx_ring->reg_idx = adapter->tx_ring[0]->reg_idx;
1611 tx_ring->numa_node = adapter->node;
da4dd0f7 1612
b6ec895e 1613 err = ixgbe_setup_tx_resources(tx_ring);
84418e3b
AD		 1614 if (err)
1615 return 1;
da4dd0f7 1616
bd508178
AD		 1617 switch (adapter->hw.mac.type) {
1618 case ixgbe_mac_82599EB:
b93a2226 1619 case ixgbe_mac_X540:
da4dd0f7
PWJ		 1620 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL);
1621 reg_data |= IXGBE_DMATXCTL_TE;
1622 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data);
bd508178
AD		 1623 break;
1624 default:
1625 break;
da4dd0f7 1626 }
f4ec443b 1627
84418e3b 1628 ixgbe_configure_tx_ring(adapter, tx_ring);
da4dd0f7
PWJ		 1629
1630 /* Setup Rx Descriptor ring and Rx buffers */
84418e3b
AD		 1631 rx_ring->count = IXGBE_DEFAULT_RXD;
1632 rx_ring->queue_index = 0;
b6ec895e 1633 rx_ring->dev = &adapter->pdev->dev;
fc77dc3c 1634 rx_ring->netdev = adapter->netdev;
84418e3b
AD		 1635 rx_ring->reg_idx = adapter->rx_ring[0]->reg_idx;
1636 rx_ring->rx_buf_len = IXGBE_RXBUFFER_2048;
1637 rx_ring->numa_node = adapter->node;
1638
b6ec895e 1639 err = ixgbe_setup_rx_resources(rx_ring);
84418e3b 1640 if (err) {
da4dd0f7
PWJ		 1641 ret_val = 4;
1642 goto err_nomem;
1643 }
1644
da4dd0f7
PWJ		 1645 rctl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL);
1646 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl & ~IXGBE_RXCTRL_RXEN);
da4dd0f7 1647
84418e3b 1648 ixgbe_configure_rx_ring(adapter, rx_ring);
da4dd0f7
PWJ		 1649
1650 rctl |= IXGBE_RXCTRL_RXEN | IXGBE_RXCTRL_DMBYPS;
1651 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl);
1652
da4dd0f7
PWJ		 1653 return 0;
1654
1655err_nomem:
1656 ixgbe_free_desc_rings(adapter);
1657 return ret_val;
1658}
1659
1660static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter)
1661{
1662 struct ixgbe_hw *hw = &adapter->hw;
1663 u32 reg_data;
1664
e7fd9253
DS		 1665 /* X540 needs to set the MACC.FLU bit to force link up */
1666 if (adapter->hw.mac.type == ixgbe_mac_X540) {
1667 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_MACC);
1668 reg_data |= IXGBE_MACC_FLU;
1669 IXGBE_WRITE_REG(&adapter->hw, IXGBE_MACC, reg_data);
1670 }
1671
da4dd0f7 1672 /* right now we only support MAC loopback in the driver */
da4dd0f7 1673 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
84418e3b 1674 /* Setup MAC loopback */
da4dd0f7
PWJ		 1675 reg_data |= IXGBE_HLREG0_LPBK;
1676 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1677
84418e3b
AD		 1678 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1679 reg_data |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_SBP | IXGBE_FCTRL_MPE;
1680 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, reg_data);
1681
da4dd0f7
PWJ		 1682 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_AUTOC);
1683 reg_data &= ~IXGBE_AUTOC_LMS_MASK;
1684 reg_data |= IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU;
1685 IXGBE_WRITE_REG(&adapter->hw, IXGBE_AUTOC, reg_data);
84418e3b 1686 IXGBE_WRITE_FLUSH(&adapter->hw);
032b4325 1687 usleep_range(10000, 20000);
da4dd0f7
PWJ		 1688
1689 /* Disable Atlas Tx lanes; re-enabled in reset path */
1690 if (hw->mac.type == ixgbe_mac_82598EB) {
1691 u8 atlas;
1692
1693 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &atlas);
1694 atlas |= IXGBE_ATLAS_PDN_TX_REG_EN;
1695 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, atlas);
1696
1697 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &atlas);
1698 atlas |= IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
1699 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, atlas);
1700
1701 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &atlas);
1702 atlas |= IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
1703 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, atlas);
1704
1705 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &atlas);
1706 atlas |= IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
1707 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, atlas);
1708 }
1709
1710 return 0;
1711}
1712
1713static void ixgbe_loopback_cleanup(struct ixgbe_adapter *adapter)
1714{
1715 u32 reg_data;
1716
1717 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1718 reg_data &= ~IXGBE_HLREG0_LPBK;
1719 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1720}
1721
1722static void ixgbe_create_lbtest_frame(struct sk_buff *skb,
1723 unsigned int frame_size)
1724{
1725 memset(skb->data, 0xFF, frame_size);
1726 frame_size &= ~1;
1727 memset(&skb->data[frame_size / 2], 0xAA, frame_size / 2 - 1);
1728 memset(&skb->data[frame_size / 2 + 10], 0xBE, 1);
1729 memset(&skb->data[frame_size / 2 + 12], 0xAF, 1);
1730}
1731
1732static int ixgbe_check_lbtest_frame(struct sk_buff *skb,
1733 unsigned int frame_size)
1734{
1735 frame_size &= ~1;
1736 if (*(skb->data + 3) == 0xFF) {
1737 if ((*(skb->data + frame_size / 2 + 10) == 0xBE) &&
1738 (*(skb->data + frame_size / 2 + 12) == 0xAF)) {
1739 return 0;
1740 }
1741 }
1742 return 13;
1743}
1744
fc77dc3c 1745static u16 ixgbe_clean_test_rings(struct ixgbe_ring *rx_ring,
84418e3b
AD		 1746 struct ixgbe_ring *tx_ring,
1747 unsigned int size)
1748{
1749 union ixgbe_adv_rx_desc *rx_desc;
1750 struct ixgbe_rx_buffer *rx_buffer_info;
1751 struct ixgbe_tx_buffer *tx_buffer_info;
1752 const int bufsz = rx_ring->rx_buf_len;
1753 u32 staterr;
1754 u16 rx_ntc, tx_ntc, count = 0;
1755
1756 /* initialize next to clean and descriptor values */
1757 rx_ntc = rx_ring->next_to_clean;
1758 tx_ntc = tx_ring->next_to_clean;
1759 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, rx_ntc);
1760 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1761
1762 while (staterr & IXGBE_RXD_STAT_DD) {
1763 /* check Rx buffer */
1764 rx_buffer_info = &rx_ring->rx_buffer_info[rx_ntc];
1765
1766 /* unmap Rx buffer, will be remapped by alloc_rx_buffers */
b6ec895e 1767 dma_unmap_single(rx_ring->dev,
84418e3b
AD		 1768 rx_buffer_info->dma,
1769 bufsz,
1770 DMA_FROM_DEVICE);
1771 rx_buffer_info->dma = 0;
1772
1773 /* verify contents of skb */
1774 if (!ixgbe_check_lbtest_frame(rx_buffer_info->skb, size))
1775 count++;
1776
1777 /* unmap buffer on Tx side */
1778 tx_buffer_info = &tx_ring->tx_buffer_info[tx_ntc];
b6ec895e 1779 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
84418e3b
AD		 1780
1781 /* increment Rx/Tx next to clean counters */
1782 rx_ntc++;
1783 if (rx_ntc == rx_ring->count)
1784 rx_ntc = 0;
1785 tx_ntc++;
1786 if (tx_ntc == tx_ring->count)
1787 tx_ntc = 0;
1788
1789 /* fetch next descriptor */
1790 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, rx_ntc);
1791 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1792 }
1793
1794 /* re-map buffers to ring, store next to clean values */
fc77dc3c 1795 ixgbe_alloc_rx_buffers(rx_ring, count);
84418e3b
AD		 1796 rx_ring->next_to_clean = rx_ntc;
1797 tx_ring->next_to_clean = tx_ntc;
1798
1799 return count;
1800}
1801
da4dd0f7
PWJ		 1802static int ixgbe_run_loopback_test(struct ixgbe_adapter *adapter)
1803{
1804 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1805 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
84418e3b
AD		 1806 int i, j, lc, good_cnt, ret_val = 0;
1807 unsigned int size = 1024;
1808 netdev_tx_t tx_ret_val;
1809 struct sk_buff *skb;
1810
1811 /* allocate test skb */
1812 skb = alloc_skb(size, GFP_KERNEL);
1813 if (!skb)
1814 return 11;
da4dd0f7 1815
84418e3b
AD		 1816 /* place data into test skb */
1817 ixgbe_create_lbtest_frame(skb, size);
1818 skb_put(skb, size);
da4dd0f7
PWJ		 1819
1820 /*
1821 * Calculate the loop count based on the largest descriptor ring
1822 * The idea is to wrap the largest ring a number of times using 64
1823 * send/receive pairs during each loop
1824 */
1825
1826 if (rx_ring->count <= tx_ring->count)
1827 lc = ((tx_ring->count / 64) * 2) + 1;
1828 else
1829 lc = ((rx_ring->count / 64) * 2) + 1;
1830
da4dd0f7 1831 for (j = 0; j <= lc; j++) {
84418e3b 1832 /* reset count of good packets */
da4dd0f7 1833 good_cnt = 0;
84418e3b
AD		 1834
1835 /* place 64 packets on the transmit queue*/
1836 for (i = 0; i < 64; i++) {
1837 skb_get(skb);
1838 tx_ret_val = ixgbe_xmit_frame_ring(skb,
84418e3b
AD		 1839 adapter,
1840 tx_ring);
1841 if (tx_ret_val == NETDEV_TX_OK)
da4dd0f7 1842 good_cnt++;
84418e3b
AD		 1843 }
1844
da4dd0f7 1845 if (good_cnt != 64) {
84418e3b 1846 ret_val = 12;
da4dd0f7
PWJ		 1847 break;
1848 }
84418e3b
AD		 1849
1850 /* allow 200 milliseconds for packets to go from Tx to Rx */
1851 msleep(200);
1852
fc77dc3c 1853 good_cnt = ixgbe_clean_test_rings(rx_ring, tx_ring, size);
84418e3b
AD		 1854 if (good_cnt != 64) {
1855 ret_val = 13;
da4dd0f7
PWJ		 1856 break;
1857 }
1858 }
1859
84418e3b
AD		 1860 /* free the original skb */
1861 kfree_skb(skb);
1862
da4dd0f7
PWJ		 1863 return ret_val;
1864}
1865
1866static int ixgbe_loopback_test(struct ixgbe_adapter *adapter, u64 *data)
1867{
1868 *data = ixgbe_setup_desc_rings(adapter);
1869 if (*data)
1870 goto out;
1871 *data = ixgbe_setup_loopback_test(adapter);
1872 if (*data)
1873 goto err_loopback;
1874 *data = ixgbe_run_loopback_test(adapter);
1875 ixgbe_loopback_cleanup(adapter);
1876
1877err_loopback:
1878 ixgbe_free_desc_rings(adapter);
1879out:
1880 return *data;
1881}
1882
1883static void ixgbe_diag_test(struct net_device *netdev,
1884 struct ethtool_test *eth_test, u64 *data)
1885{
1886 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1887 bool if_running = netif_running(netdev);
1888
1889 set_bit(__IXGBE_TESTING, &adapter->state);
1890 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1891 /* Offline tests */
1892
396e799c 1893 e_info(hw, "offline testing starting\n");
da4dd0f7
PWJ		 1894
1895 /* Link test performed before hardware reset so autoneg doesn't
1896 * interfere with test result */
1897 if (ixgbe_link_test(adapter, &data[4]))
1898 eth_test->flags |= ETH_TEST_FL_FAILED;
1899
e7d481a6
GR		 1900 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
1901 int i;
1902 for (i = 0; i < adapter->num_vfs; i++) {
1903 if (adapter->vfinfo[i].clear_to_send) {
1904 netdev_warn(netdev, "%s",
1905 "offline diagnostic is not "
1906 "supported when VFs are "
1907 "present\n");
1908 data[0] = 1;
1909 data[1] = 1;
1910 data[2] = 1;
1911 data[3] = 1;
1912 eth_test->flags |= ETH_TEST_FL_FAILED;
1913 clear_bit(__IXGBE_TESTING,
1914 &adapter->state);
1915 goto skip_ol_tests;
1916 }
1917 }
1918 }
1919
da4dd0f7
PWJ		 1920 if (if_running)
1921 /* indicate we're in test mode */
1922 dev_close(netdev);
1923 else
1924 ixgbe_reset(adapter);
1925
396e799c 1926 e_info(hw, "register testing starting\n");
da4dd0f7
PWJ		 1927 if (ixgbe_reg_test(adapter, &data[0]))
1928 eth_test->flags |= ETH_TEST_FL_FAILED;
1929
1930 ixgbe_reset(adapter);
396e799c 1931 e_info(hw, "eeprom testing starting\n");
da4dd0f7
PWJ		 1932 if (ixgbe_eeprom_test(adapter, &data[1]))
1933 eth_test->flags |= ETH_TEST_FL_FAILED;
1934
1935 ixgbe_reset(adapter);
396e799c 1936 e_info(hw, "interrupt testing starting\n");
da4dd0f7
PWJ		 1937 if (ixgbe_intr_test(adapter, &data[2]))
1938 eth_test->flags |= ETH_TEST_FL_FAILED;
1939
bdbec4b8
GR		 1940 /* If SRIOV or VMDq is enabled then skip MAC
1941 * loopback diagnostic. */
1942 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED |
1943 IXGBE_FLAG_VMDQ_ENABLED)) {
396e799c
ET		 1944 e_info(hw, "Skip MAC loopback diagnostic in VT "
1945 "mode\n");
bdbec4b8
GR		 1946 data[3] = 0;
1947 goto skip_loopback;
1948 }
1949
da4dd0f7 1950 ixgbe_reset(adapter);
396e799c 1951 e_info(hw, "loopback testing starting\n");
da4dd0f7
PWJ		 1952 if (ixgbe_loopback_test(adapter, &data[3]))
1953 eth_test->flags |= ETH_TEST_FL_FAILED;
1954
bdbec4b8 1955skip_loopback:
da4dd0f7
PWJ		 1956 ixgbe_reset(adapter);
1957
1958 clear_bit(__IXGBE_TESTING, &adapter->state);
1959 if (if_running)
1960 dev_open(netdev);
1961 } else {
396e799c 1962 e_info(hw, "online testing starting\n");
da4dd0f7
PWJ		 1963 /* Online tests */
1964 if (ixgbe_link_test(adapter, &data[4]))
1965 eth_test->flags |= ETH_TEST_FL_FAILED;
1966
1967 /* Online tests aren't run; pass by default */
1968 data[0] = 0;
1969 data[1] = 0;
1970 data[2] = 0;
1971 data[3] = 0;
1972
1973 clear_bit(__IXGBE_TESTING, &adapter->state);
1974 }
e7d481a6 1975skip_ol_tests:
da4dd0f7
PWJ		 1976 msleep_interruptible(4 * 1000);
1977}
9a799d71 1978
d6c519e1
AD		 1979static int ixgbe_wol_exclusion(struct ixgbe_adapter *adapter,
1980 struct ethtool_wolinfo *wol)
1981{
1982 struct ixgbe_hw *hw = &adapter->hw;
1983 int retval = 1;
1984
0b077fea 1985 /* WOL not supported except for the following */
d6c519e1 1986 switch(hw->device_id) {
0b077fea
DS		 1987 case IXGBE_DEV_ID_82599_SFP:
1988 /* Only this subdevice supports WOL */
1989 if (hw->subsystem_device_id != IXGBE_SUBDEV_ID_82599_SFP) {
1990 wol->supported = 0;
1991 break;
1992 }
1993 retval = 0;
1994 break;
50d6c681
AD		 1995 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
1996 /* All except this subdevice support WOL */
1997 if (hw->subsystem_device_id ==
1998 IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) {
1999 wol->supported = 0;
2000 break;
2001 }
0b077fea
DS		 2002 retval = 0;
2003 break;
d6c519e1
AD		 2004 case IXGBE_DEV_ID_82599_KX4:
2005 retval = 0;
2006 break;
2007 default:
2008 wol->supported = 0;
d6c519e1
AD		 2009 }
2010
2011 return retval;
2012}
2013
9a799d71 2014static void ixgbe_get_wol(struct net_device *netdev,
b4617240 2015 struct ethtool_wolinfo *wol)
9a799d71 2016{
e63d9762
PW		 2017 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2018
2019 wol->supported = WAKE_UCAST | WAKE_MCAST |
2020 WAKE_BCAST | WAKE_MAGIC;
9a799d71
AK		 2021 wol->wolopts = 0;
2022
d6c519e1
AD		 2023 if (ixgbe_wol_exclusion(adapter, wol) ||
2024 !device_can_wakeup(&adapter->pdev->dev))
e63d9762
PW		 2025 return;
2026
2027 if (adapter->wol & IXGBE_WUFC_EX)
2028 wol->wolopts |= WAKE_UCAST;
2029 if (adapter->wol & IXGBE_WUFC_MC)
2030 wol->wolopts |= WAKE_MCAST;
2031 if (adapter->wol & IXGBE_WUFC_BC)
2032 wol->wolopts |= WAKE_BCAST;
2033 if (adapter->wol & IXGBE_WUFC_MAG)
2034 wol->wolopts |= WAKE_MAGIC;
9a799d71
AK		 2035}
2036
e63d9762
PW		 2037static int ixgbe_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2038{
2039 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2040
2041 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
2042 return -EOPNOTSUPP;
2043
d6c519e1
AD		 2044 if (ixgbe_wol_exclusion(adapter, wol))
2045 return wol->wolopts ? -EOPNOTSUPP : 0;
2046
e63d9762
PW		 2047 adapter->wol = 0;
2048
2049 if (wol->wolopts & WAKE_UCAST)
2050 adapter->wol |= IXGBE_WUFC_EX;
2051 if (wol->wolopts & WAKE_MCAST)
2052 adapter->wol |= IXGBE_WUFC_MC;
2053 if (wol->wolopts & WAKE_BCAST)
2054 adapter->wol |= IXGBE_WUFC_BC;
2055 if (wol->wolopts & WAKE_MAGIC)
2056 adapter->wol |= IXGBE_WUFC_MAG;
2057
2058 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
2059
2060 return 0;
2061}
2062
9a799d71
AK		 2063static int ixgbe_nway_reset(struct net_device *netdev)
2064{
2065 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2066
d4f80882
AV		 2067 if (netif_running(netdev))
2068 ixgbe_reinit_locked(adapter);
9a799d71
AK		 2069
2070 return 0;
2071}
2072
66e6961c
ET		 2073static int ixgbe_set_phys_id(struct net_device *netdev,
2074 enum ethtool_phys_id_state state)
9a799d71
AK		 2075{
2076 struct ixgbe_adapter *adapter = netdev_priv(netdev);
c44ade9e 2077 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 2078
66e6961c
ET		 2079 switch (state) {
2080 case ETHTOOL_ID_ACTIVE:
2081 adapter->led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2082 return 2;
9a799d71 2083
66e6961c 2084 case ETHTOOL_ID_ON:
c44ade9e 2085 hw->mac.ops.led_on(hw, IXGBE_LED_ON);
66e6961c
ET		 2086 break;
2087
2088 case ETHTOOL_ID_OFF:
c44ade9e 2089 hw->mac.ops.led_off(hw, IXGBE_LED_ON);
66e6961c 2090 break;
9a799d71 2091
66e6961c
ET		 2092 case ETHTOOL_ID_INACTIVE:
2093 /* Restore LED settings */
2094 IXGBE_WRITE_REG(&adapter->hw, IXGBE_LEDCTL, adapter->led_reg);
2095 break;
2096 }
9a799d71
AK		 2097
2098 return 0;
2099}
2100
2101static int ixgbe_get_coalesce(struct net_device *netdev,
b4617240 2102 struct ethtool_coalesce *ec)
9a799d71
AK		 2103{
2104 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2105
4a0b9ca0 2106 ec->tx_max_coalesced_frames_irq = adapter->tx_ring[0]->work_limit;
30efa5a3
JB		 2107
2108 /* only valid if in constant ITR mode */
f7554a2b 2109 switch (adapter->rx_itr_setting) {
30efa5a3
JB		 2110 case 0:
2111 /* throttling disabled */
2112 ec->rx_coalesce_usecs = 0;
2113 break;
2114 case 1:
2115 /* dynamic ITR mode */
2116 ec->rx_coalesce_usecs = 1;
2117 break;
2118 default:
2119 /* fixed interrupt rate mode */
f7554a2b 2120 ec->rx_coalesce_usecs = 1000000/adapter->rx_eitr_param;
30efa5a3
JB		 2121 break;
2122 }
f7554a2b 2123
cfb3f91a
SN		 2124 /* if in mixed tx/rx queues per vector mode, report only rx settings */
2125 if (adapter->q_vector[0]->txr_count && adapter->q_vector[0]->rxr_count)
2126 return 0;
2127
f7554a2b
NS		 2128 /* only valid if in constant ITR mode */
2129 switch (adapter->tx_itr_setting) {
2130 case 0:
2131 /* throttling disabled */
2132 ec->tx_coalesce_usecs = 0;
2133 break;
2134 case 1:
2135 /* dynamic ITR mode */
2136 ec->tx_coalesce_usecs = 1;
2137 break;
2138 default:
2139 ec->tx_coalesce_usecs = 1000000/adapter->tx_eitr_param;
2140 break;
2141 }
2142
9a799d71
AK		 2143 return 0;
2144}
2145
80fba3f4
AD		 2146/*
2147 * this function must be called before setting the new value of
2148 * rx_itr_setting
2149 */
2150static bool ixgbe_update_rsc(struct ixgbe_adapter *adapter,
2151 struct ethtool_coalesce *ec)
2152{
2153 struct net_device *netdev = adapter->netdev;
2154
2155 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
2156 return false;
2157
2158 /* if interrupt rate is too high then disable RSC */
2159 if (ec->rx_coalesce_usecs != 1 &&
2160 ec->rx_coalesce_usecs <= 1000000/IXGBE_MAX_RSC_INT_RATE) {
2161 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2162 e_info(probe, "rx-usecs set too low, "
2163 "disabling RSC\n");
2164 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
2165 return true;
2166 }
2167 } else {
2168 /* check the feature flag value and enable RSC if necessary */
2169 if ((netdev->features & NETIF_F_LRO) &&
2170 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
2171 e_info(probe, "rx-usecs set to %d, "
2172 "re-enabling RSC\n",
2173 ec->rx_coalesce_usecs);
2174 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
2175 return true;
2176 }
2177 }
2178 return false;
2179}
2180
9a799d71 2181static int ixgbe_set_coalesce(struct net_device *netdev,
b4617240 2182 struct ethtool_coalesce *ec)
9a799d71
AK		 2183{
2184 struct ixgbe_adapter *adapter = netdev_priv(netdev);
237057ad 2185 struct ixgbe_q_vector *q_vector;
30efa5a3 2186 int i;
ef021194 2187 bool need_reset = false;
9a799d71 2188
cfb3f91a
SN		 2189 /* don't accept tx specific changes if we've got mixed RxTx vectors */
2190 if (adapter->q_vector[0]->txr_count && adapter->q_vector[0]->rxr_count
2191 && ec->tx_coalesce_usecs)
f7554a2b
NS		 2192 return -EINVAL;
2193
9a799d71 2194 if (ec->tx_max_coalesced_frames_irq)
4a0b9ca0 2195 adapter->tx_ring[0]->work_limit = ec->tx_max_coalesced_frames_irq;
30efa5a3
JB		 2196
2197 if (ec->rx_coalesce_usecs > 1) {
509ee935 2198 /* check the limits */
80fba3f4 2199 if ((1000000/ec->rx_coalesce_usecs > IXGBE_MAX_INT_RATE) ||
509ee935
JB		 2200 (1000000/ec->rx_coalesce_usecs < IXGBE_MIN_INT_RATE))
2201 return -EINVAL;
2202
80fba3f4
AD		 2203 /* check the old value and enable RSC if necessary */
2204 need_reset = ixgbe_update_rsc(adapter, ec);
2205
30efa5a3 2206 /* store the value in ints/second */
f7554a2b 2207 adapter->rx_eitr_param = 1000000/ec->rx_coalesce_usecs;
30efa5a3
JB		 2208
2209 /* static value of interrupt rate */
f7554a2b 2210 adapter->rx_itr_setting = adapter->rx_eitr_param;
509ee935 2211 /* clear the lower bit as its used for dynamic state */
f7554a2b 2212 adapter->rx_itr_setting &= ~1;
30efa5a3 2213 } else if (ec->rx_coalesce_usecs == 1) {
80fba3f4
AD		 2214 /* check the old value and enable RSC if necessary */
2215 need_reset = ixgbe_update_rsc(adapter, ec);
2216
30efa5a3 2217 /* 1 means dynamic mode */
f7554a2b
NS		 2218 adapter->rx_eitr_param = 20000;
2219 adapter->rx_itr_setting = 1;
30efa5a3 2220 } else {
80fba3f4
AD		 2221 /* check the old value and enable RSC if necessary */
2222 need_reset = ixgbe_update_rsc(adapter, ec);
509ee935
JB		 2223 /*
2224 * any other value means disable eitr, which is best
2225 * served by setting the interrupt rate very high
2226 */
f8d1dcaf 2227 adapter->rx_eitr_param = IXGBE_MAX_INT_RATE;
f7554a2b
NS		 2228 adapter->rx_itr_setting = 0;
2229 }
2230
2231 if (ec->tx_coalesce_usecs > 1) {
f8d1dcaf
JB		 2232 /*
2233 * don't have to worry about max_int as above because
2234 * tx vectors don't do hardware RSC (an rx function)
2235 */
f7554a2b
NS		 2236 /* check the limits */
2237 if ((1000000/ec->tx_coalesce_usecs > IXGBE_MAX_INT_RATE) ||
2238 (1000000/ec->tx_coalesce_usecs < IXGBE_MIN_INT_RATE))
2239 return -EINVAL;
2240
2241 /* store the value in ints/second */
2242 adapter->tx_eitr_param = 1000000/ec->tx_coalesce_usecs;
2243
2244 /* static value of interrupt rate */
2245 adapter->tx_itr_setting = adapter->tx_eitr_param;
2246
2247 /* clear the lower bit as its used for dynamic state */
2248 adapter->tx_itr_setting &= ~1;
2249 } else if (ec->tx_coalesce_usecs == 1) {
2250 /* 1 means dynamic mode */
2251 adapter->tx_eitr_param = 10000;
2252 adapter->tx_itr_setting = 1;
2253 } else {
2254 adapter->tx_eitr_param = IXGBE_MAX_INT_RATE;
2255 adapter->tx_itr_setting = 0;
30efa5a3 2256 }
9a799d71 2257
237057ad
DS		 2258 /* MSI/MSIx Interrupt Mode */
2259 if (adapter->flags &
2260 (IXGBE_FLAG_MSIX_ENABLED | IXGBE_FLAG_MSI_ENABLED)) {
2261 int num_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2262 for (i = 0; i < num_vectors; i++) {
2263 q_vector = adapter->q_vector[i];
2264 if (q_vector->txr_count && !q_vector->rxr_count)
f7554a2b
NS		 2265 /* tx only */
2266 q_vector->eitr = adapter->tx_eitr_param;
237057ad
DS		 2267 else
2268 /* rx only or mixed */
f7554a2b 2269 q_vector->eitr = adapter->rx_eitr_param;
237057ad
DS		 2270 ixgbe_write_eitr(q_vector);
2271 }
2272 /* Legacy Interrupt Mode */
2273 } else {
2274 q_vector = adapter->q_vector[0];
f7554a2b 2275 q_vector->eitr = adapter->rx_eitr_param;
fe49f04a 2276 ixgbe_write_eitr(q_vector);
9a799d71
AK		 2277 }
2278
ef021194
JB		 2279 /*
2280 * do reset here at the end to make sure EITR==0 case is handled
2281 * correctly w.r.t stopping tx, and changing TXDCTL.WTHRESH settings
2282 * also locks in RSC enable/disable which requires reset
2283 */
c988ee82
ET		 2284 if (need_reset)
2285 ixgbe_do_reset(netdev);
ef021194 2286
9a799d71
AK		 2287 return 0;
2288}
2289
f8212f97
AD		 2290static int ixgbe_set_flags(struct net_device *netdev, u32 data)
2291{
2292 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a713e7c 2293 bool need_reset = false;
1437ce39 2294 int rc;
f8212f97 2295
f62bbb5e
JG		 2296#ifdef CONFIG_IXGBE_DCB
2297 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
2298 !(data & ETH_FLAG_RXVLAN))
2299 return -EINVAL;
2300#endif
2301
2302 need_reset = (data & ETH_FLAG_RXVLAN) !=
2303 (netdev->features & NETIF_F_HW_VLAN_RX);
2304
67a74ee2
ET		 2305 if ((data & ETH_FLAG_RXHASH) &&
2306 !(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
2307 return -EOPNOTSUPP;
2308
5136cad3 2309 rc = ethtool_op_set_flags(netdev, data, ETH_FLAG_LRO | ETH_FLAG_NTUPLE |
67a74ee2
ET		 2310 ETH_FLAG_RXVLAN | ETH_FLAG_TXVLAN |
2311 ETH_FLAG_RXHASH);
1437ce39
BH		 2312 if (rc)
2313 return rc;
f8212f97 2314
f8212f97 2315 /* if state changes we need to update adapter->flags and reset */
80fba3f4
AD		 2316 if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
2317 (!!(data & ETH_FLAG_LRO) !=
2318 !!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))) {
2319 if ((data & ETH_FLAG_LRO) &&
2320 (!adapter->rx_itr_setting ||
2321 (adapter->rx_itr_setting > IXGBE_MAX_RSC_INT_RATE))) {
2322 e_info(probe, "rx-usecs set too low, "
2323 "not enabling RSC.\n");
2324 } else {
f8d1dcaf
JB		 2325 adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED;
2326 switch (adapter->hw.mac.type) {
3a289264
ET		 2327 case ixgbe_mac_X540:
2328 ixgbe_set_rsc(adapter);
2329 break;
f8d1dcaf
JB		 2330 case ixgbe_mac_82599EB:
2331 need_reset = true;
2332 break;
2333 default:
2334 break;
2335 }
f8d1dcaf 2336 }
9a713e7c
PW		 2337 }
2338
2339 /*
2340 * Check if Flow Director n-tuple support was enabled or disabled. If
2341 * the state changed, we need to reset.
2342 */
03ecf91a
AD		 2343 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
2344 /* turn off ATR, enable perfect filters and reset */
2345 if (data & ETH_FLAG_NTUPLE) {
2346 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
2347 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
2348 need_reset = true;
2349 }
2350 } else if (!(data & ETH_FLAG_NTUPLE)) {
2351 /* turn off Flow Director, set ATR and reset */
9a713e7c 2352 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
03ecf91a
AD		 2353 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
2354 !(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
2355 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
9a713e7c 2356 need_reset = true;
9a713e7c
PW		 2357 }
2358
c988ee82
ET		 2359 if (need_reset)
2360 ixgbe_do_reset(netdev);
9a713e7c 2361
f8212f97 2362 return 0;
9a713e7c
PW		 2363}
2364
3e05334f
AD		 2365static int ixgbe_get_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2366 struct ethtool_rxnfc *cmd)
2367{
2368 union ixgbe_atr_input *mask = &adapter->fdir_mask;
2369 struct ethtool_rx_flow_spec *fsp =
2370 (struct ethtool_rx_flow_spec *)&cmd->fs;
2371 struct hlist_node *node, *node2;
2372 struct ixgbe_fdir_filter *rule = NULL;
2373
2374 /* report total rule count */
2375 cmd->data = (1024 << adapter->fdir_pballoc) - 2;
2376
2377 hlist_for_each_entry_safe(rule, node, node2,
2378 &adapter->fdir_filter_list, fdir_node) {
2379 if (fsp->location <= rule->sw_idx)
2380 break;
2381 }
2382
2383 if (!rule || fsp->location != rule->sw_idx)
2384 return -EINVAL;
2385
2386 /* fill out the flow spec entry */
2387
2388 /* set flow type field */
2389 switch (rule->filter.formatted.flow_type) {
2390 case IXGBE_ATR_FLOW_TYPE_TCPV4:
2391 fsp->flow_type = TCP_V4_FLOW;
2392 break;
2393 case IXGBE_ATR_FLOW_TYPE_UDPV4:
2394 fsp->flow_type = UDP_V4_FLOW;
2395 break;
2396 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
2397 fsp->flow_type = SCTP_V4_FLOW;
2398 break;
2399 case IXGBE_ATR_FLOW_TYPE_IPV4:
2400 fsp->flow_type = IP_USER_FLOW;
2401 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
2402 fsp->h_u.usr_ip4_spec.proto = 0;
2403 fsp->m_u.usr_ip4_spec.proto = 0;
2404 break;
2405 default:
2406 return -EINVAL;
2407 }
2408
2409 fsp->h_u.tcp_ip4_spec.psrc = rule->filter.formatted.src_port;
2410 fsp->m_u.tcp_ip4_spec.psrc = mask->formatted.src_port;
2411 fsp->h_u.tcp_ip4_spec.pdst = rule->filter.formatted.dst_port;
2412 fsp->m_u.tcp_ip4_spec.pdst = mask->formatted.dst_port;
2413 fsp->h_u.tcp_ip4_spec.ip4src = rule->filter.formatted.src_ip[0];
2414 fsp->m_u.tcp_ip4_spec.ip4src = mask->formatted.src_ip[0];
2415 fsp->h_u.tcp_ip4_spec.ip4dst = rule->filter.formatted.dst_ip[0];
2416 fsp->m_u.tcp_ip4_spec.ip4dst = mask->formatted.dst_ip[0];
2417 fsp->h_ext.vlan_tci = rule->filter.formatted.vlan_id;
2418 fsp->m_ext.vlan_tci = mask->formatted.vlan_id;
2419 fsp->h_ext.vlan_etype = rule->filter.formatted.flex_bytes;
2420 fsp->m_ext.vlan_etype = mask->formatted.flex_bytes;
2421 fsp->h_ext.data[1] = htonl(rule->filter.formatted.vm_pool);
2422 fsp->m_ext.data[1] = htonl(mask->formatted.vm_pool);
2423 fsp->flow_type |= FLOW_EXT;
2424
2425 /* record action */
2426 if (rule->action == IXGBE_FDIR_DROP_QUEUE)
2427 fsp->ring_cookie = RX_CLS_FLOW_DISC;
2428 else
2429 fsp->ring_cookie = rule->action;
2430
2431 return 0;
2432}
2433
2434static int ixgbe_get_ethtool_fdir_all(struct ixgbe_adapter *adapter,
2435 struct ethtool_rxnfc *cmd,
2436 u32 *rule_locs)
2437{
2438 struct hlist_node *node, *node2;
2439 struct ixgbe_fdir_filter *rule;
2440 int cnt = 0;
2441
2442 /* report total rule count */
2443 cmd->data = (1024 << adapter->fdir_pballoc) - 2;
2444
2445 hlist_for_each_entry_safe(rule, node, node2,
2446 &adapter->fdir_filter_list, fdir_node) {
2447 if (cnt == cmd->rule_cnt)
2448 return -EMSGSIZE;
2449 rule_locs[cnt] = rule->sw_idx;
2450 cnt++;
2451 }
2452
2453 return 0;
2454}
2455
91cd94bf
AD		 2456static int ixgbe_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
2457 void *rule_locs)
2458{
2459 struct ixgbe_adapter *adapter = netdev_priv(dev);
2460 int ret = -EOPNOTSUPP;
2461
2462 switch (cmd->cmd) {
2463 case ETHTOOL_GRXRINGS:
2464 cmd->data = adapter->num_rx_queues;
2465 ret = 0;
2466 break;
3e05334f
AD		 2467 case ETHTOOL_GRXCLSRLCNT:
2468 cmd->rule_cnt = adapter->fdir_filter_count;
2469 ret = 0;
2470 break;
2471 case ETHTOOL_GRXCLSRULE:
2472 ret = ixgbe_get_ethtool_fdir_entry(adapter, cmd);
2473 break;
2474 case ETHTOOL_GRXCLSRLALL:
2475 ret = ixgbe_get_ethtool_fdir_all(adapter, cmd,
2476 (u32 *)rule_locs);
2477 break;
91cd94bf
AD		 2478 default:
2479 break;
2480 }
2481
2482 return ret;
2483}
2484
e4911d57
AD		 2485static int ixgbe_update_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2486 struct ixgbe_fdir_filter *input,
2487 u16 sw_idx)
2488{
2489 struct ixgbe_hw *hw = &adapter->hw;
2490 struct hlist_node *node, *node2, *parent;
2491 struct ixgbe_fdir_filter *rule;
2492 int err = -EINVAL;
2493
2494 parent = NULL;
2495 rule = NULL;
2496
2497 hlist_for_each_entry_safe(rule, node, node2,
2498 &adapter->fdir_filter_list, fdir_node) {
2499 /* hash found, or no matching entry */
2500 if (rule->sw_idx >= sw_idx)
2501 break;
2502 parent = node;
2503 }
2504
2505 /* if there is an old rule occupying our place remove it */
2506 if (rule && (rule->sw_idx == sw_idx)) {
2507 if (!input || (rule->filter.formatted.bkt_hash !=
2508 input->filter.formatted.bkt_hash)) {
2509 err = ixgbe_fdir_erase_perfect_filter_82599(hw,
2510 &rule->filter,
2511 sw_idx);
2512 }
2513
2514 hlist_del(&rule->fdir_node);
2515 kfree(rule);
2516 adapter->fdir_filter_count--;
2517 }
2518
2519 /*
2520 * If no input this was a delete, err should be 0 if a rule was
2521 * successfully found and removed from the list else -EINVAL
2522 */
2523 if (!input)
2524 return err;
2525
2526 /* initialize node and set software index */
2527 INIT_HLIST_NODE(&input->fdir_node);
2528
2529 /* add filter to the list */
2530 if (parent)
2531 hlist_add_after(parent, &input->fdir_node);
2532 else
2533 hlist_add_head(&input->fdir_node,
2534 &adapter->fdir_filter_list);
2535
2536 /* update counts */
2537 adapter->fdir_filter_count++;
2538
2539 return 0;
2540}
2541
2542static int ixgbe_flowspec_to_flow_type(struct ethtool_rx_flow_spec *fsp,
2543 u8 *flow_type)
2544{
2545 switch (fsp->flow_type & ~FLOW_EXT) {
2546 case TCP_V4_FLOW:
2547 *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
2548 break;
2549 case UDP_V4_FLOW:
2550 *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
2551 break;
2552 case SCTP_V4_FLOW:
2553 *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
2554 break;
2555 case IP_USER_FLOW:
2556 switch (fsp->h_u.usr_ip4_spec.proto) {
2557 case IPPROTO_TCP:
2558 *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
2559 break;
2560 case IPPROTO_UDP:
2561 *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
2562 break;
2563 case IPPROTO_SCTP:
2564 *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
2565 break;
2566 case 0:
2567 if (!fsp->m_u.usr_ip4_spec.proto) {
2568 *flow_type = IXGBE_ATR_FLOW_TYPE_IPV4;
2569 break;
2570 }
2571 default:
2572 return 0;
2573 }
2574 break;
2575 default:
2576 return 0;
2577 }
2578
2579 return 1;
2580}
2581
2582static int ixgbe_add_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2583 struct ethtool_rxnfc *cmd)
2584{
2585 struct ethtool_rx_flow_spec *fsp =
2586 (struct ethtool_rx_flow_spec *)&cmd->fs;
2587 struct ixgbe_hw *hw = &adapter->hw;
2588 struct ixgbe_fdir_filter *input;
2589 union ixgbe_atr_input mask;
2590 int err;
2591
2592 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
2593 return -EOPNOTSUPP;
2594
2595 /*
2596 * Don't allow programming if the action is a queue greater than
2597 * the number of online Rx queues.
2598 */
2599 if ((fsp->ring_cookie != RX_CLS_FLOW_DISC) &&
2600 (fsp->ring_cookie >= adapter->num_rx_queues))
2601 return -EINVAL;
2602
2603 /* Don't allow indexes to exist outside of available space */
2604 if (fsp->location >= ((1024 << adapter->fdir_pballoc) - 2)) {
2605 e_err(drv, "Location out of range\n");
2606 return -EINVAL;
2607 }
2608
2609 input = kzalloc(sizeof(*input), GFP_ATOMIC);
2610 if (!input)
2611 return -ENOMEM;
2612
2613 memset(&mask, 0, sizeof(union ixgbe_atr_input));
2614
2615 /* set SW index */
2616 input->sw_idx = fsp->location;
2617
2618 /* record flow type */
2619 if (!ixgbe_flowspec_to_flow_type(fsp,
2620 &input->filter.formatted.flow_type)) {
2621 e_err(drv, "Unrecognized flow type\n");
2622 goto err_out;
2623 }
2624
2625 mask.formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
2626 IXGBE_ATR_L4TYPE_MASK;
2627
2628 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4)
2629 mask.formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK;
2630
2631 /* Copy input into formatted structures */
2632 input->filter.formatted.src_ip[0] = fsp->h_u.tcp_ip4_spec.ip4src;
2633 mask.formatted.src_ip[0] = fsp->m_u.tcp_ip4_spec.ip4src;
2634 input->filter.formatted.dst_ip[0] = fsp->h_u.tcp_ip4_spec.ip4dst;
2635 mask.formatted.dst_ip[0] = fsp->m_u.tcp_ip4_spec.ip4dst;
2636 input->filter.formatted.src_port = fsp->h_u.tcp_ip4_spec.psrc;
2637 mask.formatted.src_port = fsp->m_u.tcp_ip4_spec.psrc;
2638 input->filter.formatted.dst_port = fsp->h_u.tcp_ip4_spec.pdst;
2639 mask.formatted.dst_port = fsp->m_u.tcp_ip4_spec.pdst;
2640
2641 if (fsp->flow_type & FLOW_EXT) {
2642 input->filter.formatted.vm_pool =
2643 (unsigned char)ntohl(fsp->h_ext.data[1]);
2644 mask.formatted.vm_pool =
2645 (unsigned char)ntohl(fsp->m_ext.data[1]);
2646 input->filter.formatted.vlan_id = fsp->h_ext.vlan_tci;
2647 mask.formatted.vlan_id = fsp->m_ext.vlan_tci;
2648 input->filter.formatted.flex_bytes =
2649 fsp->h_ext.vlan_etype;
2650 mask.formatted.flex_bytes = fsp->m_ext.vlan_etype;
2651 }
2652
2653 /* determine if we need to drop or route the packet */
2654 if (fsp->ring_cookie == RX_CLS_FLOW_DISC)
2655 input->action = IXGBE_FDIR_DROP_QUEUE;
2656 else
2657 input->action = fsp->ring_cookie;
2658
2659 spin_lock(&adapter->fdir_perfect_lock);
2660
2661 if (hlist_empty(&adapter->fdir_filter_list)) {
2662 /* save mask and program input mask into HW */
2663 memcpy(&adapter->fdir_mask, &mask, sizeof(mask));
2664 err = ixgbe_fdir_set_input_mask_82599(hw, &mask);
2665 if (err) {
2666 e_err(drv, "Error writing mask\n");
2667 goto err_out_w_lock;
2668 }
2669 } else if (memcmp(&adapter->fdir_mask, &mask, sizeof(mask))) {
2670 e_err(drv, "Only one mask supported per port\n");
2671 goto err_out_w_lock;
2672 }
2673
2674 /* apply mask and compute/store hash */
2675 ixgbe_atr_compute_perfect_hash_82599(&input->filter, &mask);
2676
2677 /* program filters to filter memory */
2678 err = ixgbe_fdir_write_perfect_filter_82599(hw,
2679 &input->filter, input->sw_idx,
2680 adapter->rx_ring[input->action]->reg_idx);
2681 if (err)
2682 goto err_out_w_lock;
2683
2684 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx);
2685
2686 spin_unlock(&adapter->fdir_perfect_lock);
2687
2688 return err;
2689err_out_w_lock:
2690 spin_unlock(&adapter->fdir_perfect_lock);
2691err_out:
2692 kfree(input);
2693 return -EINVAL;
2694}
2695
2696static int ixgbe_del_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2697 struct ethtool_rxnfc *cmd)
2698{
2699 struct ethtool_rx_flow_spec *fsp =
2700 (struct ethtool_rx_flow_spec *)&cmd->fs;
2701 int err;
2702
2703 spin_lock(&adapter->fdir_perfect_lock);
2704 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, fsp->location);
2705 spin_unlock(&adapter->fdir_perfect_lock);
2706
2707 return err;
2708}
2709
2710static int ixgbe_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
2711{
2712 struct ixgbe_adapter *adapter = netdev_priv(dev);
2713 int ret = -EOPNOTSUPP;
2714
2715 switch (cmd->cmd) {
2716 case ETHTOOL_SRXCLSRLINS:
2717 ret = ixgbe_add_ethtool_fdir_entry(adapter, cmd);
2718 break;
2719 case ETHTOOL_SRXCLSRLDEL:
2720 ret = ixgbe_del_ethtool_fdir_entry(adapter, cmd);
2721 break;
2722 default:
2723 break;
2724 }
2725
2726 return ret;
2727}
2728
b9804972 2729static const struct ethtool_ops ixgbe_ethtool_ops = {
9a799d71
AK		 2730 .get_settings = ixgbe_get_settings,
2731 .set_settings = ixgbe_set_settings,
2732 .get_drvinfo = ixgbe_get_drvinfo,
2733 .get_regs_len = ixgbe_get_regs_len,
2734 .get_regs = ixgbe_get_regs,
2735 .get_wol = ixgbe_get_wol,
e63d9762 2736 .set_wol = ixgbe_set_wol,
9a799d71
AK		 2737 .nway_reset = ixgbe_nway_reset,
2738 .get_link = ethtool_op_get_link,
2739 .get_eeprom_len = ixgbe_get_eeprom_len,
2740 .get_eeprom = ixgbe_get_eeprom,
2741 .get_ringparam = ixgbe_get_ringparam,
2742 .set_ringparam = ixgbe_set_ringparam,
2743 .get_pauseparam = ixgbe_get_pauseparam,
2744 .set_pauseparam = ixgbe_set_pauseparam,
2745 .get_rx_csum = ixgbe_get_rx_csum,
2746 .set_rx_csum = ixgbe_set_rx_csum,
2747 .get_tx_csum = ixgbe_get_tx_csum,
2748 .set_tx_csum = ixgbe_set_tx_csum,
2749 .get_sg = ethtool_op_get_sg,
2750 .set_sg = ethtool_op_set_sg,
2751 .get_msglevel = ixgbe_get_msglevel,
2752 .set_msglevel = ixgbe_set_msglevel,
2753 .get_tso = ethtool_op_get_tso,
2754 .set_tso = ixgbe_set_tso,
da4dd0f7 2755 .self_test = ixgbe_diag_test,
9a799d71 2756 .get_strings = ixgbe_get_strings,
66e6961c 2757 .set_phys_id = ixgbe_set_phys_id,
b4617240 2758 .get_sset_count = ixgbe_get_sset_count,
9a799d71
AK		 2759 .get_ethtool_stats = ixgbe_get_ethtool_stats,
2760 .get_coalesce = ixgbe_get_coalesce,
2761 .set_coalesce = ixgbe_set_coalesce,
177db6ff 2762 .get_flags = ethtool_op_get_flags,
f8212f97 2763 .set_flags = ixgbe_set_flags,
91cd94bf 2764 .get_rxnfc = ixgbe_get_rxnfc,
e4911d57 2765 .set_rxnfc = ixgbe_set_rxnfc,
9a799d71
AK		 2766};
2767
2768void ixgbe_set_ethtool_ops(struct net_device *netdev)
2769{
2770 SET_ETHTOOL_OPS(netdev, &ixgbe_ethtool_ops);
2771}
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