]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - drivers/net/ixgbe/ixgbe_main.c
projects / mirror_ubuntu-artful-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ixgbe: do not update stats twice each receive
[mirror_ubuntu-artful-kernel.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2007 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include <linux/types.h>
30#include <linux/module.h>
31#include <linux/pci.h>
32#include <linux/netdevice.h>
33#include <linux/vmalloc.h>
34#include <linux/string.h>
35#include <linux/in.h>
36#include <linux/ip.h>
37#include <linux/tcp.h>
38#include <linux/ipv6.h>
39#include <net/checksum.h>
40#include <net/ip6_checksum.h>
41#include <linux/ethtool.h>
42#include <linux/if_vlan.h>
43
44#include "ixgbe.h"
45#include "ixgbe_common.h"
46
47char ixgbe_driver_name[] = "ixgbe";
9c8eb720
SH		 48static const char ixgbe_driver_string[] =
49 "Intel(R) 10 Gigabit PCI Express Network Driver";
9a799d71 50
8d792cd9 51#define DRV_VERSION "1.3.18-k4"
9c8eb720
SH		 52const char ixgbe_driver_version[] = DRV_VERSION;
53static const char ixgbe_copyright[] =
54 "Copyright (c) 1999-2007 Intel Corporation.";
9a799d71
AK		 55
56static const struct ixgbe_info *ixgbe_info_tbl[] = {
3957d63d 57 [board_82598] = &ixgbe_82598_info,
9a799d71
AK		 58};
59
60/* ixgbe_pci_tbl - PCI Device ID Table
61 *
62 * Wildcard entries (PCI_ANY_ID) should come last
63 * Last entry must be all 0s
64 *
65 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
66 * Class, Class Mask, private data (not used) }
67 */
68static struct pci_device_id ixgbe_pci_tbl[] = {
69 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 70 board_82598 },
9a799d71 71 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 72 board_82598 },
9a799d71 73 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 74 board_82598 },
8d792cd9
JB		 75 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
76 board_82598 },
9a799d71
AK		 77
78 /* required last entry */
79 {0, }
80};
81MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
82
bd0362dd
JC		 83#ifdef CONFIG_DCA
84static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
85 void *p);
86static struct notifier_block dca_notifier = {
87 .notifier_call = ixgbe_notify_dca,
88 .next = NULL,
89 .priority = 0
90};
91#endif
92
9a799d71
AK		 93MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
94MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
95MODULE_LICENSE("GPL");
96MODULE_VERSION(DRV_VERSION);
97
98#define DEFAULT_DEBUG_LEVEL_SHIFT 3
99
5eba3699
AV		 100static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
101{
102 u32 ctrl_ext;
103
104 /* Let firmware take over control of h/w */
105 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
106 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
107 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
108}
109
110static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
111{
112 u32 ctrl_ext;
113
114 /* Let firmware know the driver has taken over */
115 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
116 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
117 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
118}
9a799d71
AK		 119
120#ifdef DEBUG
121/**
122 * ixgbe_get_hw_dev_name - return device name string
123 * used by hardware layer to print debugging information
124 **/
125char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
126{
127 struct ixgbe_adapter *adapter = hw->back;
128 struct net_device *netdev = adapter->netdev;
129 return netdev->name;
130}
131#endif
132
133static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, u16 int_alloc_entry,
134 u8 msix_vector)
135{
136 u32 ivar, index;
137
138 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
139 index = (int_alloc_entry >> 2) & 0x1F;
140 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR(index));
141 ivar &= ~(0xFF << (8 * (int_alloc_entry & 0x3)));
142 ivar |= (msix_vector << (8 * (int_alloc_entry & 0x3)));
143 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR(index), ivar);
144}
145
146static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
147 struct ixgbe_tx_buffer
148 *tx_buffer_info)
149{
150 if (tx_buffer_info->dma) {
151 pci_unmap_page(adapter->pdev,
152 tx_buffer_info->dma,
153 tx_buffer_info->length, PCI_DMA_TODEVICE);
154 tx_buffer_info->dma = 0;
155 }
156 if (tx_buffer_info->skb) {
157 dev_kfree_skb_any(tx_buffer_info->skb);
158 tx_buffer_info->skb = NULL;
159 }
160 /* tx_buffer_info must be completely set up in the transmit path */
161}
162
163static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
164 struct ixgbe_ring *tx_ring,
165 unsigned int eop,
166 union ixgbe_adv_tx_desc *eop_desc)
167{
168 /* Detect a transmit hang in hardware, this serializes the
169 * check with the clearing of time_stamp and movement of i */
170 adapter->detect_tx_hung = false;
171 if (tx_ring->tx_buffer_info[eop].dma &&
172 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
173 !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
174 /* detected Tx unit hang */
175 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
176 " TDH <%x>\n"
177 " TDT <%x>\n"
178 " next_to_use <%x>\n"
179 " next_to_clean <%x>\n"
180 "tx_buffer_info[next_to_clean]\n"
181 " time_stamp <%lx>\n"
182 " next_to_watch <%x>\n"
183 " jiffies <%lx>\n"
184 " next_to_watch.status <%x>\n",
185 readl(adapter->hw.hw_addr + tx_ring->head),
186 readl(adapter->hw.hw_addr + tx_ring->tail),
187 tx_ring->next_to_use,
188 tx_ring->next_to_clean,
189 tx_ring->tx_buffer_info[eop].time_stamp,
190 eop, jiffies, eop_desc->wb.status);
191 return true;
192 }
193
194 return false;
195}
196
e092be60
AV		 197#define IXGBE_MAX_TXD_PWR 14
198#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
199
200/* Tx Descriptors needed, worst case */
201#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
202 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
203#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
204 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
205
9a799d71
AK		 206/**
207 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
208 * @adapter: board private structure
209 **/
210static bool ixgbe_clean_tx_irq(struct ixgbe_adapter *adapter,
211 struct ixgbe_ring *tx_ring)
212{
213 struct net_device *netdev = adapter->netdev;
214 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
215 struct ixgbe_tx_buffer *tx_buffer_info;
216 unsigned int i, eop;
217 bool cleaned = false;
e092be60 218 unsigned int total_tx_bytes = 0, total_tx_packets = 0;
9a799d71
AK		 219
220 i = tx_ring->next_to_clean;
221 eop = tx_ring->tx_buffer_info[i].next_to_watch;
222 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
223 while (eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) {
e092be60
AV		 224 cleaned = false;
225 while (!cleaned) {
9a799d71
AK		 226 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
227 tx_buffer_info = &tx_ring->tx_buffer_info[i];
228 cleaned = (i == eop);
229
230 tx_ring->stats.bytes += tx_buffer_info->length;
e092be60
AV		 231 if (cleaned) {
232 struct sk_buff *skb = tx_buffer_info->skb;
e092be60
AV		 233 unsigned int segs, bytecount;
234 segs = skb_shinfo(skb)->gso_segs ?: 1;
235 /* multiply data chunks by size of headers */
236 bytecount = ((segs - 1) * skb_headlen(skb)) +
237 skb->len;
238 total_tx_packets += segs;
239 total_tx_bytes += bytecount;
e092be60 240 }
9a799d71
AK		 241 ixgbe_unmap_and_free_tx_resource(adapter,
242 tx_buffer_info);
243 tx_desc->wb.status = 0;
244
245 i++;
246 if (i == tx_ring->count)
247 i = 0;
248 }
249
250 tx_ring->stats.packets++;
251
252 eop = tx_ring->tx_buffer_info[i].next_to_watch;
253 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
254
255 /* weight of a sort for tx, avoid endless transmit cleanup */
e092be60 256 if (total_tx_packets >= tx_ring->work_limit)
9a799d71
AK		 257 break;
258 }
259
260 tx_ring->next_to_clean = i;
261
e092be60
AV		 262#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
263 if (total_tx_packets && netif_carrier_ok(netdev) &&
264 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD)) {
265 /* Make sure that anybody stopping the queue after this
266 * sees the new next_to_clean.
267 */
268 smp_mb();
30eba97a
AV		 269 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
270 !test_bit(__IXGBE_DOWN, &adapter->state)) {
271 netif_wake_subqueue(netdev, tx_ring->queue_index);
272 adapter->restart_queue++;
273 }
e092be60 274 }
9a799d71
AK		 275
276 if (adapter->detect_tx_hung)
277 if (ixgbe_check_tx_hang(adapter, tx_ring, eop, eop_desc))
30eba97a 278 netif_stop_subqueue(netdev, tx_ring->queue_index);
9a799d71 279
e092be60 280 if (total_tx_packets >= tx_ring->work_limit)
9a799d71
AK		 281 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, tx_ring->eims_value);
282
f494e8fa
AV		 283 tx_ring->total_bytes += total_tx_bytes;
284 tx_ring->total_packets += total_tx_packets;
d2f4fbe2
AV		 285 adapter->net_stats.tx_bytes += total_tx_bytes;
286 adapter->net_stats.tx_packets += total_tx_packets;
e092be60 287 cleaned = total_tx_packets ? true : false;
9a799d71
AK		 288 return cleaned;
289}
290
bd0362dd
JC		 291#ifdef CONFIG_DCA
292static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
293 struct ixgbe_ring *rxr)
294{
295 u32 rxctrl;
296 int cpu = get_cpu();
297 int q = rxr - adapter->rx_ring;
298
299 if (rxr->cpu != cpu) {
300 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
301 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
302 rxctrl |= dca_get_tag(cpu);
303 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
304 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
305 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
306 rxr->cpu = cpu;
307 }
308 put_cpu();
309}
310
311static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
312 struct ixgbe_ring *txr)
313{
314 u32 txctrl;
315 int cpu = get_cpu();
316 int q = txr - adapter->tx_ring;
317
318 if (txr->cpu != cpu) {
319 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
320 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
321 txctrl |= dca_get_tag(cpu);
322 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
323 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
324 txr->cpu = cpu;
325 }
326 put_cpu();
327}
328
329static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
330{
331 int i;
332
333 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
334 return;
335
336 for (i = 0; i < adapter->num_tx_queues; i++) {
337 adapter->tx_ring[i].cpu = -1;
338 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
339 }
340 for (i = 0; i < adapter->num_rx_queues; i++) {
341 adapter->rx_ring[i].cpu = -1;
342 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
343 }
344}
345
346static int __ixgbe_notify_dca(struct device *dev, void *data)
347{
348 struct net_device *netdev = dev_get_drvdata(dev);
349 struct ixgbe_adapter *adapter = netdev_priv(netdev);
350 unsigned long event = *(unsigned long *)data;
351
352 switch (event) {
353 case DCA_PROVIDER_ADD:
354 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
355 /* Always use CB2 mode, difference is masked
356 * in the CB driver. */
357 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
652f093f 358 if (dca_add_requester(dev) == 0) {
bd0362dd
JC		 359 ixgbe_setup_dca(adapter);
360 break;
361 }
362 /* Fall Through since DCA is disabled. */
363 case DCA_PROVIDER_REMOVE:
364 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
365 dca_remove_requester(dev);
366 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
367 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
368 }
369 break;
370 }
371
652f093f 372 return 0;
bd0362dd
JC		 373}
374
375#endif /* CONFIG_DCA */
9a799d71
AK		 376/**
377 * ixgbe_receive_skb - Send a completed packet up the stack
378 * @adapter: board private structure
379 * @skb: packet to send up
177db6ff
MC		 380 * @status: hardware indication of status of receive
381 * @rx_ring: rx descriptor ring (for a specific queue) to setup
382 * @rx_desc: rx descriptor
9a799d71
AK		 383 **/
384static void ixgbe_receive_skb(struct ixgbe_adapter *adapter,
177db6ff
MC		 385 struct sk_buff *skb, u8 status,
386 struct ixgbe_ring *ring,
387 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 388{
177db6ff
MC		 389 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
390 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 391
177db6ff
MC		 392 if (adapter->netdev->features & NETIF_F_LRO &&
393 skb->ip_summed == CHECKSUM_UNNECESSARY) {
9a799d71 394 if (adapter->vlgrp && is_vlan)
177db6ff
MC		 395 lro_vlan_hwaccel_receive_skb(&ring->lro_mgr, skb,
396 adapter->vlgrp, tag,
397 rx_desc);
9a799d71 398 else
177db6ff
MC		 399 lro_receive_skb(&ring->lro_mgr, skb, rx_desc);
400 ring->lro_used = true;
401 } else {
402 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
403 if (adapter->vlgrp && is_vlan)
404 vlan_hwaccel_receive_skb(skb, adapter->vlgrp, tag);
405 else
406 netif_receive_skb(skb);
407 } else {
408 if (adapter->vlgrp && is_vlan)
409 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
410 else
411 netif_rx(skb);
412 }
9a799d71
AK		 413 }
414}
415
e59bd25d
AV		 416/**
417 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
418 * @adapter: address of board private structure
419 * @status_err: hardware indication of status of receive
420 * @skb: skb currently being received and modified
421 **/
9a799d71 422static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
712744be 423 u32 status_err, struct sk_buff *skb)
9a799d71
AK		 424{
425 skb->ip_summed = CHECKSUM_NONE;
426
712744be
JB		 427 /* Rx csum disabled */
428 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 429 return;
e59bd25d
AV		 430
431 /* if IP and error */
432 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
433 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 434 adapter->hw_csum_rx_error++;
435 return;
436 }
e59bd25d
AV		 437
438 if (!(status_err & IXGBE_RXD_STAT_L4CS))
439 return;
440
441 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
442 adapter->hw_csum_rx_error++;
443 return;
444 }
445
9a799d71 446 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 447 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 448 adapter->hw_csum_rx_good++;
449}
450
451/**
452 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
453 * @adapter: address of board private structure
454 **/
455static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
456 struct ixgbe_ring *rx_ring,
457 int cleaned_count)
458{
459 struct net_device *netdev = adapter->netdev;
460 struct pci_dev *pdev = adapter->pdev;
461 union ixgbe_adv_rx_desc *rx_desc;
462 struct ixgbe_rx_buffer *rx_buffer_info;
463 struct sk_buff *skb;
464 unsigned int i;
465 unsigned int bufsz = adapter->rx_buf_len + NET_IP_ALIGN;
466
467 i = rx_ring->next_to_use;
468 rx_buffer_info = &rx_ring->rx_buffer_info[i];
469
470 while (cleaned_count--) {
471 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
472
473 if (!rx_buffer_info->page &&
474 (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) {
475 rx_buffer_info->page = alloc_page(GFP_ATOMIC);
476 if (!rx_buffer_info->page) {
477 adapter->alloc_rx_page_failed++;
478 goto no_buffers;
479 }
480 rx_buffer_info->page_dma =
481 pci_map_page(pdev, rx_buffer_info->page,
482 0, PAGE_SIZE, PCI_DMA_FROMDEVICE);
483 }
484
485 if (!rx_buffer_info->skb) {
486 skb = netdev_alloc_skb(netdev, bufsz);
487
488 if (!skb) {
489 adapter->alloc_rx_buff_failed++;
490 goto no_buffers;
491 }
492
493 /*
494 * Make buffer alignment 2 beyond a 16 byte boundary
495 * this will result in a 16 byte aligned IP header after
496 * the 14 byte MAC header is removed
497 */
498 skb_reserve(skb, NET_IP_ALIGN);
499
500 rx_buffer_info->skb = skb;
501 rx_buffer_info->dma = pci_map_single(pdev, skb->data,
502 bufsz,
503 PCI_DMA_FROMDEVICE);
504 }
505 /* Refresh the desc even if buffer_addrs didn't change because
506 * each write-back erases this info. */
507 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
508 rx_desc->read.pkt_addr =
509 cpu_to_le64(rx_buffer_info->page_dma);
510 rx_desc->read.hdr_addr =
511 cpu_to_le64(rx_buffer_info->dma);
512 } else {
513 rx_desc->read.pkt_addr =
514 cpu_to_le64(rx_buffer_info->dma);
515 }
516
517 i++;
518 if (i == rx_ring->count)
519 i = 0;
520 rx_buffer_info = &rx_ring->rx_buffer_info[i];
521 }
522no_buffers:
523 if (rx_ring->next_to_use != i) {
524 rx_ring->next_to_use = i;
525 if (i-- == 0)
526 i = (rx_ring->count - 1);
527
528 /*
529 * Force memory writes to complete before letting h/w
530 * know there are new descriptors to fetch. (Only
531 * applicable for weak-ordered memory model archs,
532 * such as IA-64).
533 */
534 wmb();
535 writel(i, adapter->hw.hw_addr + rx_ring->tail);
536 }
537}
538
539static bool ixgbe_clean_rx_irq(struct ixgbe_adapter *adapter,
540 struct ixgbe_ring *rx_ring,
541 int *work_done, int work_to_do)
542{
543 struct net_device *netdev = adapter->netdev;
544 struct pci_dev *pdev = adapter->pdev;
545 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
546 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
547 struct sk_buff *skb;
548 unsigned int i;
549 u32 upper_len, len, staterr;
177db6ff
MC		 550 u16 hdr_info;
551 bool cleaned = false;
9a799d71 552 int cleaned_count = 0;
d2f4fbe2 553 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
9a799d71
AK		 554
555 i = rx_ring->next_to_clean;
556 upper_len = 0;
557 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
558 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
559 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 560
561 while (staterr & IXGBE_RXD_STAT_DD) {
562 if (*work_done >= work_to_do)
563 break;
564 (*work_done)++;
565
566 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
567 hdr_info =
568 le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info);
569 len =
570 ((hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
571 IXGBE_RXDADV_HDRBUFLEN_SHIFT);
572 if (hdr_info & IXGBE_RXDADV_SPH)
573 adapter->rx_hdr_split++;
574 if (len > IXGBE_RX_HDR_SIZE)
575 len = IXGBE_RX_HDR_SIZE;
576 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
577 } else
578 len = le16_to_cpu(rx_desc->wb.upper.length);
579
580 cleaned = true;
581 skb = rx_buffer_info->skb;
582 prefetch(skb->data - NET_IP_ALIGN);
583 rx_buffer_info->skb = NULL;
584
585 if (len && !skb_shinfo(skb)->nr_frags) {
586 pci_unmap_single(pdev, rx_buffer_info->dma,
587 adapter->rx_buf_len + NET_IP_ALIGN,
588 PCI_DMA_FROMDEVICE);
589 skb_put(skb, len);
590 }
591
592 if (upper_len) {
593 pci_unmap_page(pdev, rx_buffer_info->page_dma,
594 PAGE_SIZE, PCI_DMA_FROMDEVICE);
595 rx_buffer_info->page_dma = 0;
596 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
597 rx_buffer_info->page, 0, upper_len);
598 rx_buffer_info->page = NULL;
599
600 skb->len += upper_len;
601 skb->data_len += upper_len;
602 skb->truesize += upper_len;
603 }
604
605 i++;
606 if (i == rx_ring->count)
607 i = 0;
608 next_buffer = &rx_ring->rx_buffer_info[i];
609
610 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
611 prefetch(next_rxd);
612
613 cleaned_count++;
614 if (staterr & IXGBE_RXD_STAT_EOP) {
615 rx_ring->stats.packets++;
616 rx_ring->stats.bytes += skb->len;
617 } else {
618 rx_buffer_info->skb = next_buffer->skb;
619 rx_buffer_info->dma = next_buffer->dma;
620 next_buffer->skb = skb;
621 adapter->non_eop_descs++;
622 goto next_desc;
623 }
624
625 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
626 dev_kfree_skb_irq(skb);
627 goto next_desc;
628 }
629
630 ixgbe_rx_checksum(adapter, staterr, skb);
d2f4fbe2
AV		 631
632 /* probably a little skewed due to removing CRC */
633 total_rx_bytes += skb->len;
634 total_rx_packets++;
635
9a799d71 636 skb->protocol = eth_type_trans(skb, netdev);
177db6ff 637 ixgbe_receive_skb(adapter, skb, staterr, rx_ring, rx_desc);
9a799d71
AK		 638 netdev->last_rx = jiffies;
639
640next_desc:
641 rx_desc->wb.upper.status_error = 0;
642
643 /* return some buffers to hardware, one at a time is too slow */
644 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
645 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
646 cleaned_count = 0;
647 }
648
649 /* use prefetched values */
650 rx_desc = next_rxd;
651 rx_buffer_info = next_buffer;
652
653 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 654 }
655
656 if (rx_ring->lro_used) {
657 lro_flush_all(&rx_ring->lro_mgr);
658 rx_ring->lro_used = false;
9a799d71
AK		 659 }
660
661 rx_ring->next_to_clean = i;
662 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
663
664 if (cleaned_count)
665 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
666
f494e8fa
AV		 667 rx_ring->total_packets += total_rx_packets;
668 rx_ring->total_bytes += total_rx_bytes;
669 adapter->net_stats.rx_bytes += total_rx_bytes;
670 adapter->net_stats.rx_packets += total_rx_packets;
671
9a799d71
AK		 672 return cleaned;
673}
674
021230d4 675static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 676/**
677 * ixgbe_configure_msix - Configure MSI-X hardware
678 * @adapter: board private structure
679 *
680 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
681 * interrupts.
682 **/
683static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
684{
021230d4
AV		 685 struct ixgbe_q_vector *q_vector;
686 int i, j, q_vectors, v_idx, r_idx;
687 u32 mask;
9a799d71 688
021230d4 689 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 690
021230d4
AV		 691 /* Populate the IVAR table and set the ITR values to the
692 * corresponding register.
693 */
694 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
695 q_vector = &adapter->q_vector[v_idx];
696 /* XXX for_each_bit(...) */
697 r_idx = find_first_bit(q_vector->rxr_idx,
698 adapter->num_rx_queues);
699
700 for (i = 0; i < q_vector->rxr_count; i++) {
701 j = adapter->rx_ring[r_idx].reg_idx;
702 ixgbe_set_ivar(adapter, IXGBE_IVAR_RX_QUEUE(j), v_idx);
703 r_idx = find_next_bit(q_vector->rxr_idx,
704 adapter->num_rx_queues,
705 r_idx + 1);
706 }
707 r_idx = find_first_bit(q_vector->txr_idx,
708 adapter->num_tx_queues);
709
710 for (i = 0; i < q_vector->txr_count; i++) {
711 j = adapter->tx_ring[r_idx].reg_idx;
712 ixgbe_set_ivar(adapter, IXGBE_IVAR_TX_QUEUE(j), v_idx);
713 r_idx = find_next_bit(q_vector->txr_idx,
714 adapter->num_tx_queues,
715 r_idx + 1);
716 }
717
718 /* if this is a tx only vector use half the irq (tx) rate */
719 if (q_vector->txr_count && !q_vector->rxr_count)
720 q_vector->eitr = adapter->tx_eitr;
721 else
722 /* rx only or mixed */
723 q_vector->eitr = adapter->rx_eitr;
724
725 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx),
726 EITR_INTS_PER_SEC_TO_REG(q_vector->eitr));
9a799d71
AK		 727 }
728
021230d4
AV		 729 ixgbe_set_ivar(adapter, IXGBE_IVAR_OTHER_CAUSES_INDEX, v_idx);
730 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
731
732 /* set up to autoclear timer, lsc, and the vectors */
733 mask = IXGBE_EIMS_ENABLE_MASK;
734 mask &= ~IXGBE_EIMS_OTHER;
735 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 736}
737
f494e8fa
AV		 738enum latency_range {
739 lowest_latency = 0,
740 low_latency = 1,
741 bulk_latency = 2,
742 latency_invalid = 255
743};
744
745/**
746 * ixgbe_update_itr - update the dynamic ITR value based on statistics
747 * @adapter: pointer to adapter
748 * @eitr: eitr setting (ints per sec) to give last timeslice
749 * @itr_setting: current throttle rate in ints/second
750 * @packets: the number of packets during this measurement interval
751 * @bytes: the number of bytes during this measurement interval
752 *
753 * Stores a new ITR value based on packets and byte
754 * counts during the last interrupt. The advantage of per interrupt
755 * computation is faster updates and more accurate ITR for the current
756 * traffic pattern. Constants in this function were computed
757 * based on theoretical maximum wire speed and thresholds were set based
758 * on testing data as well as attempting to minimize response time
759 * while increasing bulk throughput.
760 * this functionality is controlled by the InterruptThrottleRate module
761 * parameter (see ixgbe_param.c)
762 **/
763static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
764 u32 eitr, u8 itr_setting,
765 int packets, int bytes)
766{
767 unsigned int retval = itr_setting;
768 u32 timepassed_us;
769 u64 bytes_perint;
770
771 if (packets == 0)
772 goto update_itr_done;
773
774
775 /* simple throttlerate management
776 * 0-20MB/s lowest (100000 ints/s)
777 * 20-100MB/s low (20000 ints/s)
778 * 100-1249MB/s bulk (8000 ints/s)
779 */
780 /* what was last interrupt timeslice? */
781 timepassed_us = 1000000/eitr;
782 bytes_perint = bytes / timepassed_us; /* bytes/usec */
783
784 switch (itr_setting) {
785 case lowest_latency:
786 if (bytes_perint > adapter->eitr_low)
787 retval = low_latency;
788 break;
789 case low_latency:
790 if (bytes_perint > adapter->eitr_high)
791 retval = bulk_latency;
792 else if (bytes_perint <= adapter->eitr_low)
793 retval = lowest_latency;
794 break;
795 case bulk_latency:
796 if (bytes_perint <= adapter->eitr_high)
797 retval = low_latency;
798 break;
799 }
800
801update_itr_done:
802 return retval;
803}
804
805static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
806{
807 struct ixgbe_adapter *adapter = q_vector->adapter;
808 struct ixgbe_hw *hw = &adapter->hw;
809 u32 new_itr;
810 u8 current_itr, ret_itr;
811 int i, r_idx, v_idx = ((void *)q_vector - (void *)(adapter->q_vector)) /
812 sizeof(struct ixgbe_q_vector);
813 struct ixgbe_ring *rx_ring, *tx_ring;
814
815 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
816 for (i = 0; i < q_vector->txr_count; i++) {
817 tx_ring = &(adapter->tx_ring[r_idx]);
818 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
819 q_vector->tx_eitr,
820 tx_ring->total_packets,
821 tx_ring->total_bytes);
822 /* if the result for this queue would decrease interrupt
823 * rate for this vector then use that result */
824 q_vector->tx_eitr = ((q_vector->tx_eitr > ret_itr) ?
825 q_vector->tx_eitr - 1 : ret_itr);
826 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
827 r_idx + 1);
828 }
829
830 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
831 for (i = 0; i < q_vector->rxr_count; i++) {
832 rx_ring = &(adapter->rx_ring[r_idx]);
833 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
834 q_vector->rx_eitr,
835 rx_ring->total_packets,
836 rx_ring->total_bytes);
837 /* if the result for this queue would decrease interrupt
838 * rate for this vector then use that result */
839 q_vector->rx_eitr = ((q_vector->rx_eitr > ret_itr) ?
840 q_vector->rx_eitr - 1 : ret_itr);
841 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
842 r_idx + 1);
843 }
844
845 current_itr = max(q_vector->rx_eitr, q_vector->tx_eitr);
846
847 switch (current_itr) {
848 /* counts and packets in update_itr are dependent on these numbers */
849 case lowest_latency:
850 new_itr = 100000;
851 break;
852 case low_latency:
853 new_itr = 20000; /* aka hwitr = ~200 */
854 break;
855 case bulk_latency:
856 default:
857 new_itr = 8000;
858 break;
859 }
860
861 if (new_itr != q_vector->eitr) {
862 u32 itr_reg;
863 /* do an exponential smoothing */
864 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
865 q_vector->eitr = new_itr;
866 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
867 /* must write high and low 16 bits to reset counter */
868 DPRINTK(TX_ERR, DEBUG, "writing eitr(%d): %08X\n", v_idx,
869 itr_reg);
870 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg | (itr_reg)<<16);
871 }
872
873 return;
874}
875
9a799d71
AK		 876static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
877{
878 struct net_device *netdev = data;
879 struct ixgbe_adapter *adapter = netdev_priv(netdev);
880 struct ixgbe_hw *hw = &adapter->hw;
881 u32 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
882
883 if (eicr & IXGBE_EICR_LSC) {
884 adapter->lsc_int++;
885 if (!test_bit(__IXGBE_DOWN, &adapter->state))
886 mod_timer(&adapter->watchdog_timer, jiffies);
887 }
d4f80882
AV		 888
889 if (!test_bit(__IXGBE_DOWN, &adapter->state))
890 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 891
892 return IRQ_HANDLED;
893}
894
895static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
896{
021230d4
AV		 897 struct ixgbe_q_vector *q_vector = data;
898 struct ixgbe_adapter *adapter = q_vector->adapter;
899 struct ixgbe_ring *txr;
900 int i, r_idx;
901
902 if (!q_vector->txr_count)
903 return IRQ_HANDLED;
904
905 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
906 for (i = 0; i < q_vector->txr_count; i++) {
907 txr = &(adapter->tx_ring[r_idx]);
bd0362dd
JC		 908#ifdef CONFIG_DCA
909 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
910 ixgbe_update_tx_dca(adapter, txr);
911#endif
f494e8fa
AV		 912 txr->total_bytes = 0;
913 txr->total_packets = 0;
021230d4
AV		 914 ixgbe_clean_tx_irq(adapter, txr);
915 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
916 r_idx + 1);
917 }
9a799d71 918
9a799d71
AK		 919 return IRQ_HANDLED;
920}
921
021230d4
AV		 922/**
923 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
924 * @irq: unused
925 * @data: pointer to our q_vector struct for this interrupt vector
926 **/
9a799d71
AK		 927static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
928{
021230d4
AV		 929 struct ixgbe_q_vector *q_vector = data;
930 struct ixgbe_adapter *adapter = q_vector->adapter;
931 struct ixgbe_ring *rxr;
932 int r_idx;
933
934 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
935 if (!q_vector->rxr_count)
936 return IRQ_HANDLED;
937
938 rxr = &(adapter->rx_ring[r_idx]);
939 /* disable interrupts on this vector only */
940 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, rxr->v_idx);
f494e8fa
AV		 941 rxr->total_bytes = 0;
942 rxr->total_packets = 0;
021230d4
AV		 943 netif_rx_schedule(adapter->netdev, &q_vector->napi);
944
945 return IRQ_HANDLED;
946}
947
948static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
949{
950 ixgbe_msix_clean_rx(irq, data);
951 ixgbe_msix_clean_tx(irq, data);
9a799d71 952
9a799d71
AK		 953 return IRQ_HANDLED;
954}
955
021230d4
AV		 956/**
957 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
958 * @napi: napi struct with our devices info in it
959 * @budget: amount of work driver is allowed to do this pass, in packets
960 *
961 **/
9a799d71
AK		 962static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
963{
021230d4
AV		 964 struct ixgbe_q_vector *q_vector =
965 container_of(napi, struct ixgbe_q_vector, napi);
966 struct ixgbe_adapter *adapter = q_vector->adapter;
967 struct ixgbe_ring *rxr;
9a799d71 968 int work_done = 0;
021230d4 969 long r_idx;
9a799d71 970
021230d4
AV		 971 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
972 rxr = &(adapter->rx_ring[r_idx]);
bd0362dd
JC		 973#ifdef CONFIG_DCA
974 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
975 ixgbe_update_rx_dca(adapter, rxr);
976#endif
9a799d71
AK		 977
978 ixgbe_clean_rx_irq(adapter, rxr, &work_done, budget);
979
021230d4
AV		 980 /* If all Rx work done, exit the polling mode */
981 if (work_done < budget) {
982 netif_rx_complete(adapter->netdev, napi);
f494e8fa
AV		 983 if (adapter->rx_eitr < IXGBE_MIN_ITR_USECS)
984 ixgbe_set_itr_msix(q_vector);
9a799d71 985 if (!test_bit(__IXGBE_DOWN, &adapter->state))
021230d4 986 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, rxr->v_idx);
9a799d71
AK		 987 }
988
989 return work_done;
990}
991
021230d4
AV		 992static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
993 int r_idx)
994{
995 a->q_vector[v_idx].adapter = a;
996 set_bit(r_idx, a->q_vector[v_idx].rxr_idx);
997 a->q_vector[v_idx].rxr_count++;
998 a->rx_ring[r_idx].v_idx = 1 << v_idx;
999}
1000
1001static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
1002 int r_idx)
1003{
1004 a->q_vector[v_idx].adapter = a;
1005 set_bit(r_idx, a->q_vector[v_idx].txr_idx);
1006 a->q_vector[v_idx].txr_count++;
1007 a->tx_ring[r_idx].v_idx = 1 << v_idx;
1008}
1009
9a799d71 1010/**
021230d4
AV		 1011 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1012 * @adapter: board private structure to initialize
1013 * @vectors: allotted vector count for descriptor rings
9a799d71 1014 *
021230d4
AV		 1015 * This function maps descriptor rings to the queue-specific vectors
1016 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1017 * one vector per ring/queue, but on a constrained vector budget, we
1018 * group the rings as "efficiently" as possible. You would add new
1019 * mapping configurations in here.
9a799d71 1020 **/
021230d4
AV		 1021static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
1022 int vectors)
1023{
1024 int v_start = 0;
1025 int rxr_idx = 0, txr_idx = 0;
1026 int rxr_remaining = adapter->num_rx_queues;
1027 int txr_remaining = adapter->num_tx_queues;
1028 int i, j;
1029 int rqpv, tqpv;
1030 int err = 0;
1031
1032 /* No mapping required if MSI-X is disabled. */
1033 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1034 goto out;
9a799d71 1035
021230d4
AV		 1036 /*
1037 * The ideal configuration...
1038 * We have enough vectors to map one per queue.
1039 */
1040 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1041 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1042 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 1043
021230d4
AV		 1044 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1045 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 1046
9a799d71 1047 goto out;
021230d4 1048 }
9a799d71 1049
021230d4
AV		 1050 /*
1051 * If we don't have enough vectors for a 1-to-1
1052 * mapping, we'll have to group them so there are
1053 * multiple queues per vector.
1054 */
1055 /* Re-adjusting *qpv takes care of the remainder. */
1056 for (i = v_start; i < vectors; i++) {
1057 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1058 for (j = 0; j < rqpv; j++) {
1059 map_vector_to_rxq(adapter, i, rxr_idx);
1060 rxr_idx++;
1061 rxr_remaining--;
1062 }
1063 }
1064 for (i = v_start; i < vectors; i++) {
1065 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1066 for (j = 0; j < tqpv; j++) {
1067 map_vector_to_txq(adapter, i, txr_idx);
1068 txr_idx++;
1069 txr_remaining--;
9a799d71 1070 }
9a799d71
AK		 1071 }
1072
021230d4
AV		 1073out:
1074 return err;
1075}
1076
1077/**
1078 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1079 * @adapter: board private structure
1080 *
1081 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1082 * interrupts from the kernel.
1083 **/
1084static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1085{
1086 struct net_device *netdev = adapter->netdev;
1087 irqreturn_t (*handler)(int, void *);
1088 int i, vector, q_vectors, err;
1089
1090 /* Decrement for Other and TCP Timer vectors */
1091 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1092
1093 /* Map the Tx/Rx rings to the vectors we were allotted. */
1094 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1095 if (err)
1096 goto out;
1097
1098#define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
1099 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1100 &ixgbe_msix_clean_many)
1101 for (vector = 0; vector < q_vectors; vector++) {
1102 handler = SET_HANDLER(&adapter->q_vector[vector]);
1103 sprintf(adapter->name[vector], "%s:v%d-%s",
1104 netdev->name, vector,
1105 (handler == &ixgbe_msix_clean_rx) ? "Rx" :
1106 ((handler == &ixgbe_msix_clean_tx) ? "Tx" : "TxRx"));
1107 err = request_irq(adapter->msix_entries[vector].vector,
1108 handler, 0, adapter->name[vector],
1109 &(adapter->q_vector[vector]));
9a799d71
AK		 1110 if (err) {
1111 DPRINTK(PROBE, ERR,
1112 "request_irq failed for MSIX interrupt "
1113 "Error: %d\n", err);
021230d4 1114 goto free_queue_irqs;
9a799d71 1115 }
9a799d71
AK		 1116 }
1117
021230d4
AV		 1118 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1119 err = request_irq(adapter->msix_entries[vector].vector,
1120 &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
9a799d71
AK		 1121 if (err) {
1122 DPRINTK(PROBE, ERR,
1123 "request_irq for msix_lsc failed: %d\n", err);
021230d4 1124 goto free_queue_irqs;
9a799d71
AK		 1125 }
1126
9a799d71
AK		 1127 return 0;
1128
021230d4
AV		 1129free_queue_irqs:
1130 for (i = vector - 1; i >= 0; i--)
1131 free_irq(adapter->msix_entries[--vector].vector,
1132 &(adapter->q_vector[i]));
1133 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1134 pci_disable_msix(adapter->pdev);
9a799d71
AK		 1135 kfree(adapter->msix_entries);
1136 adapter->msix_entries = NULL;
021230d4 1137out:
9a799d71
AK		 1138 return err;
1139}
1140
f494e8fa
AV		 1141static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1142{
1143 struct ixgbe_hw *hw = &adapter->hw;
1144 struct ixgbe_q_vector *q_vector = adapter->q_vector;
1145 u8 current_itr;
1146 u32 new_itr = q_vector->eitr;
1147 struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1148 struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1149
1150 q_vector->tx_eitr = ixgbe_update_itr(adapter, new_itr,
1151 q_vector->tx_eitr,
1152 tx_ring->total_packets,
1153 tx_ring->total_bytes);
1154 q_vector->rx_eitr = ixgbe_update_itr(adapter, new_itr,
1155 q_vector->rx_eitr,
1156 rx_ring->total_packets,
1157 rx_ring->total_bytes);
1158
1159 current_itr = max(q_vector->rx_eitr, q_vector->tx_eitr);
1160
1161 switch (current_itr) {
1162 /* counts and packets in update_itr are dependent on these numbers */
1163 case lowest_latency:
1164 new_itr = 100000;
1165 break;
1166 case low_latency:
1167 new_itr = 20000; /* aka hwitr = ~200 */
1168 break;
1169 case bulk_latency:
1170 new_itr = 8000;
1171 break;
1172 default:
1173 break;
1174 }
1175
1176 if (new_itr != q_vector->eitr) {
1177 u32 itr_reg;
1178 /* do an exponential smoothing */
1179 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1180 q_vector->eitr = new_itr;
1181 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
1182 /* must write high and low 16 bits to reset counter */
1183 IXGBE_WRITE_REG(hw, IXGBE_EITR(0), itr_reg | (itr_reg)<<16);
1184 }
1185
1186 return;
1187}
1188
021230d4
AV		 1189static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter);
1190
9a799d71 1191/**
021230d4 1192 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 1193 * @irq: interrupt number
1194 * @data: pointer to a network interface device structure
1195 * @pt_regs: CPU registers structure
1196 **/
1197static irqreturn_t ixgbe_intr(int irq, void *data)
1198{
1199 struct net_device *netdev = data;
1200 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1201 struct ixgbe_hw *hw = &adapter->hw;
1202 u32 eicr;
1203
9a799d71 1204
021230d4
AV		 1205 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1206 * therefore no explict interrupt disable is necessary */
1207 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
9a799d71
AK		 1208 if (!eicr)
1209 return IRQ_NONE; /* Not our interrupt */
1210
1211 if (eicr & IXGBE_EICR_LSC) {
1212 adapter->lsc_int++;
1213 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1214 mod_timer(&adapter->watchdog_timer, jiffies);
1215 }
021230d4
AV		 1216
1217
1218 if (netif_rx_schedule_prep(netdev, &adapter->q_vector[0].napi)) {
f494e8fa
AV		 1219 adapter->tx_ring[0].total_packets = 0;
1220 adapter->tx_ring[0].total_bytes = 0;
1221 adapter->rx_ring[0].total_packets = 0;
1222 adapter->rx_ring[0].total_bytes = 0;
021230d4
AV		 1223 /* would disable interrupts here but EIAM disabled it */
1224 __netif_rx_schedule(netdev, &adapter->q_vector[0].napi);
9a799d71
AK		 1225 }
1226
1227 return IRQ_HANDLED;
1228}
1229
021230d4
AV		 1230static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1231{
1232 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1233
1234 for (i = 0; i < q_vectors; i++) {
1235 struct ixgbe_q_vector *q_vector = &adapter->q_vector[i];
1236 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1237 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1238 q_vector->rxr_count = 0;
1239 q_vector->txr_count = 0;
1240 }
1241}
1242
9a799d71
AK		 1243/**
1244 * ixgbe_request_irq - initialize interrupts
1245 * @adapter: board private structure
1246 *
1247 * Attempts to configure interrupts using the best available
1248 * capabilities of the hardware and kernel.
1249 **/
021230d4 1250static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 1251{
1252 struct net_device *netdev = adapter->netdev;
021230d4 1253 int err;
9a799d71 1254
021230d4
AV		 1255 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1256 err = ixgbe_request_msix_irqs(adapter);
1257 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1258 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
1259 netdev->name, netdev);
1260 } else {
1261 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
1262 netdev->name, netdev);
9a799d71
AK		 1263 }
1264
9a799d71
AK		 1265 if (err)
1266 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1267
9a799d71
AK		 1268 return err;
1269}
1270
1271static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1272{
1273 struct net_device *netdev = adapter->netdev;
1274
1275 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 1276 int i, q_vectors;
9a799d71 1277
021230d4
AV		 1278 q_vectors = adapter->num_msix_vectors;
1279
1280 i = q_vectors - 1;
9a799d71 1281 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 1282
021230d4
AV		 1283 i--;
1284 for (; i >= 0; i--) {
1285 free_irq(adapter->msix_entries[i].vector,
1286 &(adapter->q_vector[i]));
1287 }
1288
1289 ixgbe_reset_q_vectors(adapter);
1290 } else {
1291 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 1292 }
1293}
1294
1295/**
1296 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1297 * @adapter: board private structure
1298 **/
1299static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1300{
9a799d71
AK		 1301 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1302 IXGBE_WRITE_FLUSH(&adapter->hw);
021230d4
AV		 1303 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1304 int i;
1305 for (i = 0; i < adapter->num_msix_vectors; i++)
1306 synchronize_irq(adapter->msix_entries[i].vector);
1307 } else {
1308 synchronize_irq(adapter->pdev->irq);
1309 }
9a799d71
AK		 1310}
1311
1312/**
1313 * ixgbe_irq_enable - Enable default interrupt generation settings
1314 * @adapter: board private structure
1315 **/
1316static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1317{
021230d4
AV		 1318 u32 mask;
1319 mask = IXGBE_EIMS_ENABLE_MASK;
1320 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
d4f80882 1321 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 1322}
1323
1324/**
1325 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1326 *
1327 **/
1328static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1329{
9a799d71
AK		 1330 struct ixgbe_hw *hw = &adapter->hw;
1331
021230d4
AV		 1332 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
1333 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr));
9a799d71
AK		 1334
1335 ixgbe_set_ivar(adapter, IXGBE_IVAR_RX_QUEUE(0), 0);
021230d4
AV		 1336 ixgbe_set_ivar(adapter, IXGBE_IVAR_TX_QUEUE(0), 0);
1337
1338 map_vector_to_rxq(adapter, 0, 0);
1339 map_vector_to_txq(adapter, 0, 0);
1340
1341 DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 1342}
1343
1344/**
1345 * ixgbe_configure_tx - Configure 8254x Transmit Unit after Reset
1346 * @adapter: board private structure
1347 *
1348 * Configure the Tx unit of the MAC after a reset.
1349 **/
1350static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1351{
1352 u64 tdba;
1353 struct ixgbe_hw *hw = &adapter->hw;
021230d4 1354 u32 i, j, tdlen, txctrl;
9a799d71
AK		 1355
1356 /* Setup the HW Tx Head and Tail descriptor pointers */
1357 for (i = 0; i < adapter->num_tx_queues; i++) {
021230d4 1358 j = adapter->tx_ring[i].reg_idx;
9a799d71
AK		 1359 tdba = adapter->tx_ring[i].dma;
1360 tdlen = adapter->tx_ring[i].count *
021230d4
AV		 1361 sizeof(union ixgbe_adv_tx_desc);
1362 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
1363 (tdba & DMA_32BIT_MASK));
1364 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1365 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1366 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1367 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1368 adapter->tx_ring[i].head = IXGBE_TDH(j);
1369 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1370 /* Disable Tx Head Writeback RO bit, since this hoses
1371 * bookkeeping if things aren't delivered in order.
1372 */
1373 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
1374 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
1375 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), txctrl);
9a799d71 1376 }
9a799d71
AK		 1377}
1378
1379#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
1380 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
1381
1382#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
177db6ff
MC		 1383/**
1384 * ixgbe_get_skb_hdr - helper function for LRO header processing
1385 * @skb: pointer to sk_buff to be added to LRO packet
1386 * @iphdr: pointer to tcp header structure
1387 * @tcph: pointer to tcp header structure
1388 * @hdr_flags: pointer to header flags
1389 * @priv: private data
1390 **/
1391static int ixgbe_get_skb_hdr(struct sk_buff *skb, void **iphdr, void **tcph,
1392 u64 *hdr_flags, void *priv)
1393{
1394 union ixgbe_adv_rx_desc *rx_desc = priv;
1395
1396 /* Verify that this is a valid IPv4 TCP packet */
1397 if (!(rx_desc->wb.lower.lo_dword.pkt_info &
1398 (IXGBE_RXDADV_PKTTYPE_IPV4 | IXGBE_RXDADV_PKTTYPE_TCP)))
1399 return -1;
1400
1401 /* Set network headers */
1402 skb_reset_network_header(skb);
1403 skb_set_transport_header(skb, ip_hdrlen(skb));
1404 *iphdr = ip_hdr(skb);
1405 *tcph = tcp_hdr(skb);
1406 *hdr_flags = LRO_IPV4 | LRO_TCP;
1407 return 0;
1408}
1409
9a799d71
AK		 1410/**
1411 * ixgbe_configure_rx - Configure 8254x Receive Unit after Reset
1412 * @adapter: board private structure
1413 *
1414 * Configure the Rx unit of the MAC after a reset.
1415 **/
1416static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
1417{
1418 u64 rdba;
1419 struct ixgbe_hw *hw = &adapter->hw;
1420 struct net_device *netdev = adapter->netdev;
1421 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 1422 int i, j;
9a799d71
AK		 1423 u32 rdlen, rxctrl, rxcsum;
1424 u32 random[10];
9a799d71 1425 u32 fctrl, hlreg0;
9a799d71 1426 u32 pages;
021230d4 1427 u32 reta = 0, mrqc, srrctl;
9a799d71
AK		 1428
1429 /* Decide whether to use packet split mode or not */
1430 if (netdev->mtu > ETH_DATA_LEN)
1431 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
1432 else
1433 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
1434
1435 /* Set the RX buffer length according to the mode */
1436 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1437 adapter->rx_buf_len = IXGBE_RX_HDR_SIZE;
1438 } else {
1439 if (netdev->mtu <= ETH_DATA_LEN)
1440 adapter->rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1441 else
1442 adapter->rx_buf_len = ALIGN(max_frame, 1024);
1443 }
1444
1445 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1446 fctrl |= IXGBE_FCTRL_BAM;
021230d4 1447 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
9a799d71
AK		 1448 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
1449
1450 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1451 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1452 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
1453 else
1454 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
1455 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1456
1457 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
1458
1459 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(0));
1460 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1461 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1462
1463 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1464 srrctl |= PAGE_SIZE >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1465 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1466 srrctl |= ((IXGBE_RX_HDR_SIZE <<
1467 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1468 IXGBE_SRRCTL_BSIZEHDR_MASK);
1469 } else {
1470 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
1471
1472 if (adapter->rx_buf_len == MAXIMUM_ETHERNET_VLAN_SIZE)
1473 srrctl |=
1474 IXGBE_RXBUFFER_2048 >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1475 else
1476 srrctl |=
1477 adapter->rx_buf_len >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1478 }
1479 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(0), srrctl);
1480
1481 rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
1482 /* disable receives while setting up the descriptors */
1483 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1484 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
1485
1486 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1487 * the Base and Length of the Rx Descriptor Ring */
1488 for (i = 0; i < adapter->num_rx_queues; i++) {
1489 rdba = adapter->rx_ring[i].dma;
1490 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(i), (rdba & DMA_32BIT_MASK));
1491 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(i), (rdba >> 32));
1492 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(i), rdlen);
1493 IXGBE_WRITE_REG(hw, IXGBE_RDH(i), 0);
1494 IXGBE_WRITE_REG(hw, IXGBE_RDT(i), 0);
1495 adapter->rx_ring[i].head = IXGBE_RDH(i);
1496 adapter->rx_ring[i].tail = IXGBE_RDT(i);
1497 }
1498
177db6ff
MC		 1499 /* Intitial LRO Settings */
1500 adapter->rx_ring[i].lro_mgr.max_aggr = IXGBE_MAX_LRO_AGGREGATE;
1501 adapter->rx_ring[i].lro_mgr.max_desc = IXGBE_MAX_LRO_DESCRIPTORS;
1502 adapter->rx_ring[i].lro_mgr.get_skb_header = ixgbe_get_skb_hdr;
1503 adapter->rx_ring[i].lro_mgr.features = LRO_F_EXTRACT_VLAN_ID;
1504 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1505 adapter->rx_ring[i].lro_mgr.features |= LRO_F_NAPI;
1506 adapter->rx_ring[i].lro_mgr.dev = adapter->netdev;
1507 adapter->rx_ring[i].lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
1508 adapter->rx_ring[i].lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
1509
021230d4 1510 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
9a799d71 1511 /* Fill out redirection table */
021230d4
AV		 1512 for (i = 0, j = 0; i < 128; i++, j++) {
1513 if (j == adapter->ring_feature[RING_F_RSS].indices)
1514 j = 0;
1515 /* reta = 4-byte sliding window of
1516 * 0x00..(indices-1)(indices-1)00..etc. */
1517 reta = (reta << 8) | (j * 0x11);
1518 if ((i & 3) == 3)
1519 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
9a799d71
AK		 1520 }
1521
1522 /* Fill out hash function seeds */
021230d4
AV		 1523 /* XXX use a random constant here to glue certain flows */
1524 get_random_bytes(&random[0], 40);
9a799d71 1525 for (i = 0; i < 10; i++)
021230d4 1526 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), random[i]);
9a799d71
AK		 1527
1528 mrqc = IXGBE_MRQC_RSSEN
1529 /* Perform hash on these packet types */
1530 | IXGBE_MRQC_RSS_FIELD_IPV4
1531 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
1532 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
1533 | IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP
1534 | IXGBE_MRQC_RSS_FIELD_IPV6_EX
1535 | IXGBE_MRQC_RSS_FIELD_IPV6
1536 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
1537 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP
1538 | IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
1539 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
021230d4 1540 }
9a799d71 1541
021230d4
AV		 1542 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
1543
1544 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
1545 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
1546 /* Disable indicating checksum in descriptor, enables
1547 * RSS hash */
9a799d71 1548 rxcsum |= IXGBE_RXCSUM_PCSD;
9a799d71 1549 }
021230d4
AV		 1550 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
1551 /* Enable IPv4 payload checksum for UDP fragments
1552 * if PCSD is not set */
1553 rxcsum |= IXGBE_RXCSUM_IPPCSE;
1554 }
1555
1556 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
9a799d71
AK		 1557}
1558
1559static void ixgbe_vlan_rx_register(struct net_device *netdev,
1560 struct vlan_group *grp)
1561{
1562 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1563 u32 ctrl;
1564
d4f80882
AV		 1565 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1566 ixgbe_irq_disable(adapter);
9a799d71
AK		 1567 adapter->vlgrp = grp;
1568
1569 if (grp) {
1570 /* enable VLAN tag insert/strip */
1571 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
746b9f02 1572 ctrl |= IXGBE_VLNCTRL_VME;
9a799d71
AK		 1573 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
1574 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
1575 }
1576
d4f80882
AV		 1577 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1578 ixgbe_irq_enable(adapter);
9a799d71
AK		 1579}
1580
1581static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
1582{
1583 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1584
1585 /* add VID to filter table */
1586 ixgbe_set_vfta(&adapter->hw, vid, 0, true);
1587}
1588
1589static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
1590{
1591 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1592
d4f80882
AV		 1593 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1594 ixgbe_irq_disable(adapter);
1595
9a799d71 1596 vlan_group_set_device(adapter->vlgrp, vid, NULL);
d4f80882
AV		 1597
1598 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1599 ixgbe_irq_enable(adapter);
9a799d71
AK		 1600
1601 /* remove VID from filter table */
1602 ixgbe_set_vfta(&adapter->hw, vid, 0, false);
1603}
1604
1605static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
1606{
1607 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
1608
1609 if (adapter->vlgrp) {
1610 u16 vid;
1611 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
1612 if (!vlan_group_get_device(adapter->vlgrp, vid))
1613 continue;
1614 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
1615 }
1616 }
1617}
1618
2c5645cf
CL		 1619static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
1620{
1621 struct dev_mc_list *mc_ptr;
1622 u8 *addr = *mc_addr_ptr;
1623 *vmdq = 0;
1624
1625 mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
1626 if (mc_ptr->next)
1627 *mc_addr_ptr = mc_ptr->next->dmi_addr;
1628 else
1629 *mc_addr_ptr = NULL;
1630
1631 return addr;
1632}
1633
9a799d71 1634/**
2c5645cf 1635 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 1636 * @netdev: network interface device structure
1637 *
2c5645cf
CL		 1638 * The set_rx_method entry point is called whenever the unicast/multicast
1639 * address list or the network interface flags are updated. This routine is
1640 * responsible for configuring the hardware for proper unicast, multicast and
1641 * promiscuous mode.
9a799d71 1642 **/
2c5645cf 1643static void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 1644{
1645 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1646 struct ixgbe_hw *hw = &adapter->hw;
3d01625a 1647 u32 fctrl, vlnctrl;
2c5645cf
CL		 1648 u8 *addr_list = NULL;
1649 int addr_count = 0;
9a799d71
AK		 1650
1651 /* Check for Promiscuous and All Multicast modes */
1652
1653 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3d01625a 1654 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
9a799d71
AK		 1655
1656 if (netdev->flags & IFF_PROMISC) {
2c5645cf 1657 hw->addr_ctrl.user_set_promisc = 1;
9a799d71 1658 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3d01625a 1659 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
9a799d71 1660 } else {
746b9f02
PM		 1661 if (netdev->flags & IFF_ALLMULTI) {
1662 fctrl |= IXGBE_FCTRL_MPE;
1663 fctrl &= ~IXGBE_FCTRL_UPE;
1664 } else {
1665 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
1666 }
3d01625a 1667 vlnctrl |= IXGBE_VLNCTRL_VFE;
2c5645cf 1668 hw->addr_ctrl.user_set_promisc = 0;
9a799d71
AK		 1669 }
1670
1671 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3d01625a 1672 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
9a799d71 1673
2c5645cf
CL		 1674 /* reprogram secondary unicast list */
1675 addr_count = netdev->uc_count;
1676 if (addr_count)
1677 addr_list = netdev->uc_list->dmi_addr;
1678 ixgbe_update_uc_addr_list(hw, addr_list, addr_count,
1679 ixgbe_addr_list_itr);
9a799d71 1680
2c5645cf
CL		 1681 /* reprogram multicast list */
1682 addr_count = netdev->mc_count;
1683 if (addr_count)
1684 addr_list = netdev->mc_list->dmi_addr;
1685 ixgbe_update_mc_addr_list(hw, addr_list, addr_count,
1686 ixgbe_addr_list_itr);
9a799d71
AK		 1687}
1688
021230d4
AV		 1689static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
1690{
1691 int q_idx;
1692 struct ixgbe_q_vector *q_vector;
1693 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1694
1695 /* legacy and MSI only use one vector */
1696 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1697 q_vectors = 1;
1698
1699 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
1700 q_vector = &adapter->q_vector[q_idx];
1701 if (!q_vector->rxr_count)
1702 continue;
1703 napi_enable(&q_vector->napi);
1704 }
1705}
1706
1707static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
1708{
1709 int q_idx;
1710 struct ixgbe_q_vector *q_vector;
1711 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1712
1713 /* legacy and MSI only use one vector */
1714 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1715 q_vectors = 1;
1716
1717 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
1718 q_vector = &adapter->q_vector[q_idx];
1719 if (!q_vector->rxr_count)
1720 continue;
1721 napi_disable(&q_vector->napi);
1722 }
1723}
1724
9a799d71
AK		 1725static void ixgbe_configure(struct ixgbe_adapter *adapter)
1726{
1727 struct net_device *netdev = adapter->netdev;
1728 int i;
1729
2c5645cf 1730 ixgbe_set_rx_mode(netdev);
9a799d71
AK		 1731
1732 ixgbe_restore_vlan(adapter);
1733
1734 ixgbe_configure_tx(adapter);
1735 ixgbe_configure_rx(adapter);
1736 for (i = 0; i < adapter->num_rx_queues; i++)
1737 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
1738 (adapter->rx_ring[i].count - 1));
1739}
1740
1741static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
1742{
1743 struct net_device *netdev = adapter->netdev;
9a799d71 1744 struct ixgbe_hw *hw = &adapter->hw;
021230d4 1745 int i, j = 0;
9a799d71 1746 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4
AV		 1747 u32 txdctl, rxdctl, mhadd;
1748 u32 gpie;
9a799d71 1749
5eba3699
AV		 1750 ixgbe_get_hw_control(adapter);
1751
021230d4
AV		 1752 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
1753 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
9a799d71
AK		 1754 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1755 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
1756 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
1757 } else {
1758 /* MSI only */
021230d4 1759 gpie = 0;
9a799d71 1760 }
021230d4
AV		 1761 /* XXX: to interrupt immediately for EICS writes, enable this */
1762 /* gpie |= IXGBE_GPIE_EIMEN; */
1763 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
9a799d71
AK		 1764 }
1765
021230d4
AV		 1766 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
1767 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
1768 * specifically only auto mask tx and rx interrupts */
1769 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
1770 }
9a799d71 1771
021230d4 1772 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
9a799d71
AK		 1773 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
1774 mhadd &= ~IXGBE_MHADD_MFS_MASK;
1775 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
1776
1777 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
1778 }
1779
1780 for (i = 0; i < adapter->num_tx_queues; i++) {
021230d4
AV		 1781 j = adapter->tx_ring[i].reg_idx;
1782 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
9a799d71 1783 txdctl |= IXGBE_TXDCTL_ENABLE;
021230d4 1784 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
9a799d71
AK		 1785 }
1786
1787 for (i = 0; i < adapter->num_rx_queues; i++) {
021230d4
AV		 1788 j = adapter->rx_ring[i].reg_idx;
1789 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
1790 /* enable PTHRESH=32 descriptors (half the internal cache)
1791 * and HTHRESH=0 descriptors (to minimize latency on fetch),
1792 * this also removes a pesky rx_no_buffer_count increment */
1793 rxdctl |= 0x0020;
9a799d71 1794 rxdctl |= IXGBE_RXDCTL_ENABLE;
021230d4 1795 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
9a799d71
AK		 1796 }
1797 /* enable all receives */
1798 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1799 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
1800 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxdctl);
1801
1802 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
1803 ixgbe_configure_msix(adapter);
1804 else
1805 ixgbe_configure_msi_and_legacy(adapter);
1806
1807 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 1808 ixgbe_napi_enable_all(adapter);
1809
1810 /* clear any pending interrupts, may auto mask */
1811 IXGBE_READ_REG(hw, IXGBE_EICR);
1812
9a799d71
AK		 1813 ixgbe_irq_enable(adapter);
1814
1815 /* bring the link up in the watchdog, this could race with our first
1816 * link up interrupt but shouldn't be a problem */
1817 mod_timer(&adapter->watchdog_timer, jiffies);
1818 return 0;
1819}
1820
d4f80882
AV		 1821void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
1822{
1823 WARN_ON(in_interrupt());
1824 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
1825 msleep(1);
1826 ixgbe_down(adapter);
1827 ixgbe_up(adapter);
1828 clear_bit(__IXGBE_RESETTING, &adapter->state);
1829}
1830
9a799d71
AK		 1831int ixgbe_up(struct ixgbe_adapter *adapter)
1832{
1833 /* hardware has been reset, we need to reload some things */
1834 ixgbe_configure(adapter);
1835
1836 return ixgbe_up_complete(adapter);
1837}
1838
1839void ixgbe_reset(struct ixgbe_adapter *adapter)
1840{
1841 if (ixgbe_init_hw(&adapter->hw))
1842 DPRINTK(PROBE, ERR, "Hardware Error\n");
1843
1844 /* reprogram the RAR[0] in case user changed it. */
1845 ixgbe_set_rar(&adapter->hw, 0, adapter->hw.mac.addr, 0, IXGBE_RAH_AV);
1846
1847}
1848
1849#ifdef CONFIG_PM
1850static int ixgbe_resume(struct pci_dev *pdev)
1851{
1852 struct net_device *netdev = pci_get_drvdata(pdev);
1853 struct ixgbe_adapter *adapter = netdev_priv(netdev);
021230d4 1854 u32 err;
9a799d71
AK		 1855
1856 pci_set_power_state(pdev, PCI_D0);
1857 pci_restore_state(pdev);
1858 err = pci_enable_device(pdev);
1859 if (err) {
1860 printk(KERN_ERR "ixgbe: Cannot enable PCI device from " \
1861 "suspend\n");
1862 return err;
1863 }
1864 pci_set_master(pdev);
1865
1866 pci_enable_wake(pdev, PCI_D3hot, 0);
1867 pci_enable_wake(pdev, PCI_D3cold, 0);
1868
1869 if (netif_running(netdev)) {
021230d4 1870 err = ixgbe_request_irq(adapter);
9a799d71
AK		 1871 if (err)
1872 return err;
1873 }
1874
1875 ixgbe_reset(adapter);
1876
1877 if (netif_running(netdev))
1878 ixgbe_up(adapter);
1879
1880 netif_device_attach(netdev);
1881
1882 return 0;
1883}
1884#endif
1885
1886/**
1887 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
1888 * @adapter: board private structure
1889 * @rx_ring: ring to free buffers from
1890 **/
1891static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
1892 struct ixgbe_ring *rx_ring)
1893{
1894 struct pci_dev *pdev = adapter->pdev;
1895 unsigned long size;
1896 unsigned int i;
1897
1898 /* Free all the Rx ring sk_buffs */
1899
1900 for (i = 0; i < rx_ring->count; i++) {
1901 struct ixgbe_rx_buffer *rx_buffer_info;
1902
1903 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1904 if (rx_buffer_info->dma) {
1905 pci_unmap_single(pdev, rx_buffer_info->dma,
1906 adapter->rx_buf_len,
1907 PCI_DMA_FROMDEVICE);
1908 rx_buffer_info->dma = 0;
1909 }
1910 if (rx_buffer_info->skb) {
1911 dev_kfree_skb(rx_buffer_info->skb);
1912 rx_buffer_info->skb = NULL;
1913 }
1914 if (!rx_buffer_info->page)
1915 continue;
1916 pci_unmap_page(pdev, rx_buffer_info->page_dma, PAGE_SIZE,
1917 PCI_DMA_FROMDEVICE);
1918 rx_buffer_info->page_dma = 0;
1919
1920 put_page(rx_buffer_info->page);
1921 rx_buffer_info->page = NULL;
1922 }
1923
1924 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
1925 memset(rx_ring->rx_buffer_info, 0, size);
1926
1927 /* Zero out the descriptor ring */
1928 memset(rx_ring->desc, 0, rx_ring->size);
1929
1930 rx_ring->next_to_clean = 0;
1931 rx_ring->next_to_use = 0;
1932
1933 writel(0, adapter->hw.hw_addr + rx_ring->head);
1934 writel(0, adapter->hw.hw_addr + rx_ring->tail);
1935}
1936
1937/**
1938 * ixgbe_clean_tx_ring - Free Tx Buffers
1939 * @adapter: board private structure
1940 * @tx_ring: ring to be cleaned
1941 **/
1942static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
1943 struct ixgbe_ring *tx_ring)
1944{
1945 struct ixgbe_tx_buffer *tx_buffer_info;
1946 unsigned long size;
1947 unsigned int i;
1948
1949 /* Free all the Tx ring sk_buffs */
1950
1951 for (i = 0; i < tx_ring->count; i++) {
1952 tx_buffer_info = &tx_ring->tx_buffer_info[i];
1953 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
1954 }
1955
1956 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
1957 memset(tx_ring->tx_buffer_info, 0, size);
1958
1959 /* Zero out the descriptor ring */
1960 memset(tx_ring->desc, 0, tx_ring->size);
1961
1962 tx_ring->next_to_use = 0;
1963 tx_ring->next_to_clean = 0;
1964
1965 writel(0, adapter->hw.hw_addr + tx_ring->head);
1966 writel(0, adapter->hw.hw_addr + tx_ring->tail);
1967}
1968
1969/**
021230d4 1970 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 1971 * @adapter: board private structure
1972 **/
021230d4 1973static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 1974{
1975 int i;
1976
021230d4
AV		 1977 for (i = 0; i < adapter->num_rx_queues; i++)
1978 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
9a799d71
AK		 1979}
1980
1981/**
021230d4 1982 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 1983 * @adapter: board private structure
1984 **/
021230d4 1985static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 1986{
1987 int i;
1988
021230d4
AV		 1989 for (i = 0; i < adapter->num_tx_queues; i++)
1990 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
9a799d71
AK		 1991}
1992
1993void ixgbe_down(struct ixgbe_adapter *adapter)
1994{
1995 struct net_device *netdev = adapter->netdev;
1996 u32 rxctrl;
1997
1998 /* signal that we are down to the interrupt handler */
1999 set_bit(__IXGBE_DOWN, &adapter->state);
2000
2001 /* disable receives */
2002 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL);
2003 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL,
2004 rxctrl & ~IXGBE_RXCTRL_RXEN);
2005
2006 netif_tx_disable(netdev);
2007
2008 /* disable transmits in the hardware */
2009
2010 /* flush both disables */
2011 IXGBE_WRITE_FLUSH(&adapter->hw);
2012 msleep(10);
2013
2014 ixgbe_irq_disable(adapter);
2015
021230d4 2016 ixgbe_napi_disable_all(adapter);
9a799d71
AK		 2017 del_timer_sync(&adapter->watchdog_timer);
2018
2019 netif_carrier_off(netdev);
fd2ea0a7 2020 netif_tx_stop_all_queues(netdev);
9a799d71 2021
6f4a0e45
PL		 2022 if (!pci_channel_offline(adapter->pdev))
2023 ixgbe_reset(adapter);
9a799d71
AK		 2024 ixgbe_clean_all_tx_rings(adapter);
2025 ixgbe_clean_all_rx_rings(adapter);
2026
2027}
2028
2029static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
2030{
2031 struct net_device *netdev = pci_get_drvdata(pdev);
2032 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2033#ifdef CONFIG_PM
2034 int retval = 0;
2035#endif
2036
2037 netif_device_detach(netdev);
2038
2039 if (netif_running(netdev)) {
2040 ixgbe_down(adapter);
2041 ixgbe_free_irq(adapter);
2042 }
2043
2044#ifdef CONFIG_PM
2045 retval = pci_save_state(pdev);
2046 if (retval)
2047 return retval;
2048#endif
2049
2050 pci_enable_wake(pdev, PCI_D3hot, 0);
2051 pci_enable_wake(pdev, PCI_D3cold, 0);
2052
5eba3699
AV		 2053 ixgbe_release_hw_control(adapter);
2054
9a799d71
AK		 2055 pci_disable_device(pdev);
2056
2057 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2058
2059 return 0;
2060}
2061
2062static void ixgbe_shutdown(struct pci_dev *pdev)
2063{
2064 ixgbe_suspend(pdev, PMSG_SUSPEND);
2065}
2066
2067/**
021230d4
AV		 2068 * ixgbe_poll - NAPI Rx polling callback
2069 * @napi: structure for representing this polling device
2070 * @budget: how many packets driver is allowed to clean
2071 *
2072 * This function is used for legacy and MSI, NAPI mode
9a799d71 2073 **/
021230d4 2074static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 2075{
021230d4
AV		 2076 struct ixgbe_q_vector *q_vector = container_of(napi,
2077 struct ixgbe_q_vector, napi);
2078 struct ixgbe_adapter *adapter = q_vector->adapter;
d2c7ddd6 2079 int tx_cleaned = 0, work_done = 0;
9a799d71 2080
bd0362dd
JC		 2081#ifdef CONFIG_DCA
2082 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2083 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
2084 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
2085 }
2086#endif
2087
d2c7ddd6 2088 tx_cleaned = ixgbe_clean_tx_irq(adapter, adapter->tx_ring);
021230d4 2089 ixgbe_clean_rx_irq(adapter, adapter->rx_ring, &work_done, budget);
9a799d71 2090
d2c7ddd6
DM		 2091 if (tx_cleaned)
2092 work_done = budget;
2093
53e52c72
DM		 2094 /* If budget not fully consumed, exit the polling mode */
2095 if (work_done < budget) {
021230d4 2096 netif_rx_complete(adapter->netdev, napi);
f494e8fa
AV		 2097 if (adapter->rx_eitr < IXGBE_MIN_ITR_USECS)
2098 ixgbe_set_itr(adapter);
d4f80882
AV		 2099 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2100 ixgbe_irq_enable(adapter);
9a799d71
AK		 2101 }
2102
2103 return work_done;
2104}
2105
2106/**
2107 * ixgbe_tx_timeout - Respond to a Tx Hang
2108 * @netdev: network interface device structure
2109 **/
2110static void ixgbe_tx_timeout(struct net_device *netdev)
2111{
2112 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2113
2114 /* Do the reset outside of interrupt context */
2115 schedule_work(&adapter->reset_task);
2116}
2117
2118static void ixgbe_reset_task(struct work_struct *work)
2119{
2120 struct ixgbe_adapter *adapter;
2121 adapter = container_of(work, struct ixgbe_adapter, reset_task);
2122
2123 adapter->tx_timeout_count++;
2124
d4f80882 2125 ixgbe_reinit_locked(adapter);
9a799d71
AK		 2126}
2127
021230d4
AV		 2128static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
2129 int vectors)
2130{
2131 int err, vector_threshold;
2132
2133 /* We'll want at least 3 (vector_threshold):
2134 * 1) TxQ[0] Cleanup
2135 * 2) RxQ[0] Cleanup
2136 * 3) Other (Link Status Change, etc.)
2137 * 4) TCP Timer (optional)
2138 */
2139 vector_threshold = MIN_MSIX_COUNT;
2140
2141 /* The more we get, the more we will assign to Tx/Rx Cleanup
2142 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
2143 * Right now, we simply care about how many we'll get; we'll
2144 * set them up later while requesting irq's.
2145 */
2146 while (vectors >= vector_threshold) {
2147 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
2148 vectors);
2149 if (!err) /* Success in acquiring all requested vectors. */
2150 break;
2151 else if (err < 0)
2152 vectors = 0; /* Nasty failure, quit now */
2153 else /* err == number of vectors we should try again with */
2154 vectors = err;
2155 }
2156
2157 if (vectors < vector_threshold) {
2158 /* Can't allocate enough MSI-X interrupts? Oh well.
2159 * This just means we'll go with either a single MSI
2160 * vector or fall back to legacy interrupts.
2161 */
2162 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
2163 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2164 kfree(adapter->msix_entries);
2165 adapter->msix_entries = NULL;
2166 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
2167 adapter->num_tx_queues = 1;
2168 adapter->num_rx_queues = 1;
2169 } else {
2170 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
2171 adapter->num_msix_vectors = vectors;
2172 }
2173}
2174
2175static void __devinit ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
2176{
2177 int nrq, ntq;
2178 int feature_mask = 0, rss_i, rss_m;
2179
2180 /* Number of supported queues */
2181 switch (adapter->hw.mac.type) {
2182 case ixgbe_mac_82598EB:
2183 rss_i = adapter->ring_feature[RING_F_RSS].indices;
2184 rss_m = 0;
2185 feature_mask |= IXGBE_FLAG_RSS_ENABLED;
2186
2187 switch (adapter->flags & feature_mask) {
2188 case (IXGBE_FLAG_RSS_ENABLED):
2189 rss_m = 0xF;
2190 nrq = rss_i;
30eba97a 2191 ntq = rss_i;
021230d4
AV		 2192 break;
2193 case 0:
2194 default:
2195 rss_i = 0;
2196 rss_m = 0;
2197 nrq = 1;
2198 ntq = 1;
2199 break;
2200 }
2201
2202 adapter->ring_feature[RING_F_RSS].indices = rss_i;
2203 adapter->ring_feature[RING_F_RSS].mask = rss_m;
2204 break;
2205 default:
2206 nrq = 1;
2207 ntq = 1;
2208 break;
2209 }
2210
2211 adapter->num_rx_queues = nrq;
2212 adapter->num_tx_queues = ntq;
2213}
2214
2215/**
2216 * ixgbe_cache_ring_register - Descriptor ring to register mapping
2217 * @adapter: board private structure to initialize
2218 *
2219 * Once we know the feature-set enabled for the device, we'll cache
2220 * the register offset the descriptor ring is assigned to.
2221 **/
2222static void __devinit ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
2223{
2224 /* TODO: Remove all uses of the indices in the cases where multiple
2225 * features are OR'd together, if the feature set makes sense.
2226 */
2227 int feature_mask = 0, rss_i;
2228 int i, txr_idx, rxr_idx;
2229
2230 /* Number of supported queues */
2231 switch (adapter->hw.mac.type) {
2232 case ixgbe_mac_82598EB:
2233 rss_i = adapter->ring_feature[RING_F_RSS].indices;
2234 txr_idx = 0;
2235 rxr_idx = 0;
2236 feature_mask |= IXGBE_FLAG_RSS_ENABLED;
2237 switch (adapter->flags & feature_mask) {
2238 case (IXGBE_FLAG_RSS_ENABLED):
2239 for (i = 0; i < adapter->num_rx_queues; i++)
2240 adapter->rx_ring[i].reg_idx = i;
2241 for (i = 0; i < adapter->num_tx_queues; i++)
2242 adapter->tx_ring[i].reg_idx = i;
2243 break;
2244 case 0:
2245 default:
2246 break;
2247 }
2248 break;
2249 default:
2250 break;
2251 }
2252}
2253
9a799d71
AK		 2254/**
2255 * ixgbe_alloc_queues - Allocate memory for all rings
2256 * @adapter: board private structure to initialize
2257 *
2258 * We allocate one ring per queue at run-time since we don't know the
2259 * number of queues at compile-time. The polling_netdev array is
2260 * intended for Multiqueue, but should work fine with a single queue.
2261 **/
2262static int __devinit ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
2263{
2264 int i;
2265
2266 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
2267 sizeof(struct ixgbe_ring), GFP_KERNEL);
2268 if (!adapter->tx_ring)
021230d4 2269 goto err_tx_ring_allocation;
9a799d71
AK		 2270
2271 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
2272 sizeof(struct ixgbe_ring), GFP_KERNEL);
021230d4
AV		 2273 if (!adapter->rx_ring)
2274 goto err_rx_ring_allocation;
9a799d71 2275
021230d4
AV		 2276 for (i = 0; i < adapter->num_tx_queues; i++) {
2277 adapter->tx_ring[i].count = IXGBE_DEFAULT_TXD;
2278 adapter->tx_ring[i].queue_index = i;
2279 }
9a799d71 2280 for (i = 0; i < adapter->num_rx_queues; i++) {
9a799d71 2281 adapter->rx_ring[i].count = IXGBE_DEFAULT_RXD;
021230d4
AV		 2282 adapter->rx_ring[i].queue_index = i;
2283 }
2284
2285 ixgbe_cache_ring_register(adapter);
2286
2287 return 0;
2288
2289err_rx_ring_allocation:
2290 kfree(adapter->tx_ring);
2291err_tx_ring_allocation:
2292 return -ENOMEM;
2293}
2294
2295/**
2296 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
2297 * @adapter: board private structure to initialize
2298 *
2299 * Attempt to configure the interrupts using the best available
2300 * capabilities of the hardware and the kernel.
2301 **/
2302static int __devinit ixgbe_set_interrupt_capability(struct ixgbe_adapter
2303 *adapter)
2304{
2305 int err = 0;
2306 int vector, v_budget;
2307
2308 /*
2309 * It's easy to be greedy for MSI-X vectors, but it really
2310 * doesn't do us much good if we have a lot more vectors
2311 * than CPU's. So let's be conservative and only ask for
2312 * (roughly) twice the number of vectors as there are CPU's.
2313 */
2314 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
2315 (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
2316
2317 /*
2318 * At the same time, hardware can only support a maximum of
2319 * MAX_MSIX_COUNT vectors. With features such as RSS and VMDq,
2320 * we can easily reach upwards of 64 Rx descriptor queues and
2321 * 32 Tx queues. Thus, we cap it off in those rare cases where
2322 * the cpu count also exceeds our vector limit.
2323 */
2324 v_budget = min(v_budget, MAX_MSIX_COUNT);
2325
2326 /* A failure in MSI-X entry allocation isn't fatal, but it does
2327 * mean we disable MSI-X capabilities of the adapter. */
2328 adapter->msix_entries = kcalloc(v_budget,
2329 sizeof(struct msix_entry), GFP_KERNEL);
2330 if (!adapter->msix_entries) {
2331 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
2332 ixgbe_set_num_queues(adapter);
2333 kfree(adapter->tx_ring);
2334 kfree(adapter->rx_ring);
2335 err = ixgbe_alloc_queues(adapter);
2336 if (err) {
2337 DPRINTK(PROBE, ERR, "Unable to allocate memory "
2338 "for queues\n");
2339 goto out;
2340 }
2341
2342 goto try_msi;
2343 }
2344
2345 for (vector = 0; vector < v_budget; vector++)
2346 adapter->msix_entries[vector].entry = vector;
2347
2348 ixgbe_acquire_msix_vectors(adapter, v_budget);
2349
2350 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2351 goto out;
2352
2353try_msi:
2354 err = pci_enable_msi(adapter->pdev);
2355 if (!err) {
2356 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
2357 } else {
2358 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
2359 "falling back to legacy. Error: %d\n", err);
2360 /* reset err */
2361 err = 0;
2362 }
2363
2364out:
30eba97a 2365 /* Notify the stack of the (possibly) reduced Tx Queue count. */
fd2ea0a7 2366 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
021230d4
AV		 2367
2368 return err;
2369}
2370
2371static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
2372{
2373 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2374 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2375 pci_disable_msix(adapter->pdev);
2376 kfree(adapter->msix_entries);
2377 adapter->msix_entries = NULL;
2378 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2379 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
2380 pci_disable_msi(adapter->pdev);
2381 }
2382 return;
2383}
2384
2385/**
2386 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
2387 * @adapter: board private structure to initialize
2388 *
2389 * We determine which interrupt scheme to use based on...
2390 * - Kernel support (MSI, MSI-X)
2391 * - which can be user-defined (via MODULE_PARAM)
2392 * - Hardware queue count (num_*_queues)
2393 * - defined by miscellaneous hardware support/features (RSS, etc.)
2394 **/
2395static int __devinit ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
2396{
2397 int err;
2398
2399 /* Number of supported queues */
2400 ixgbe_set_num_queues(adapter);
2401
2402 err = ixgbe_alloc_queues(adapter);
2403 if (err) {
2404 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
2405 goto err_alloc_queues;
2406 }
2407
2408 err = ixgbe_set_interrupt_capability(adapter);
2409 if (err) {
2410 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
2411 goto err_set_interrupt;
9a799d71
AK		 2412 }
2413
021230d4
AV		 2414 DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
2415 "Tx Queue count = %u\n",
2416 (adapter->num_rx_queues > 1) ? "Enabled" :
2417 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
2418
2419 set_bit(__IXGBE_DOWN, &adapter->state);
2420
9a799d71 2421 return 0;
021230d4
AV		 2422
2423err_set_interrupt:
2424 kfree(adapter->tx_ring);
2425 kfree(adapter->rx_ring);
2426err_alloc_queues:
2427 return err;
9a799d71
AK		 2428}
2429
2430/**
2431 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
2432 * @adapter: board private structure to initialize
2433 *
2434 * ixgbe_sw_init initializes the Adapter private data structure.
2435 * Fields are initialized based on PCI device information and
2436 * OS network device settings (MTU size).
2437 **/
2438static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
2439{
2440 struct ixgbe_hw *hw = &adapter->hw;
2441 struct pci_dev *pdev = adapter->pdev;
021230d4
AV		 2442 unsigned int rss;
2443
2444 /* Set capability flags */
2445 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
2446 adapter->ring_feature[RING_F_RSS].indices = rss;
2447 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
9a799d71 2448
f494e8fa
AV		 2449 /* Enable Dynamic interrupt throttling by default */
2450 adapter->rx_eitr = 1;
2451 adapter->tx_eitr = 1;
2452
9a799d71
AK		 2453 /* default flow control settings */
2454 hw->fc.original_type = ixgbe_fc_full;
2455 hw->fc.type = ixgbe_fc_full;
2456
021230d4 2457 /* select 10G link by default */
9a799d71
AK		 2458 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_10G_LINK_NO_AN;
2459 if (hw->mac.ops.reset(hw)) {
2460 dev_err(&pdev->dev, "HW Init failed\n");
2461 return -EIO;
2462 }
3957d63d
AK		 2463 if (hw->mac.ops.setup_link_speed(hw, IXGBE_LINK_SPEED_10GB_FULL, true,
2464 false)) {
9a799d71
AK		 2465 dev_err(&pdev->dev, "Link Speed setup failed\n");
2466 return -EIO;
2467 }
2468
2469 /* initialize eeprom parameters */
2470 if (ixgbe_init_eeprom(hw)) {
2471 dev_err(&pdev->dev, "EEPROM initialization failed\n");
2472 return -EIO;
2473 }
2474
021230d4 2475 /* enable rx csum by default */
9a799d71
AK		 2476 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
2477
9a799d71
AK		 2478 set_bit(__IXGBE_DOWN, &adapter->state);
2479
2480 return 0;
2481}
2482
2483/**
2484 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
2485 * @adapter: board private structure
2486 * @txdr: tx descriptor ring (for a specific queue) to setup
2487 *
2488 * Return 0 on success, negative on failure
2489 **/
2490int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
2491 struct ixgbe_ring *txdr)
2492{
2493 struct pci_dev *pdev = adapter->pdev;
2494 int size;
2495
2496 size = sizeof(struct ixgbe_tx_buffer) * txdr->count;
2497 txdr->tx_buffer_info = vmalloc(size);
2498 if (!txdr->tx_buffer_info) {
2499 DPRINTK(PROBE, ERR,
2500 "Unable to allocate memory for the transmit descriptor ring\n");
2501 return -ENOMEM;
2502 }
2503 memset(txdr->tx_buffer_info, 0, size);
2504
2505 /* round up to nearest 4K */
2506 txdr->size = txdr->count * sizeof(union ixgbe_adv_tx_desc);
2507 txdr->size = ALIGN(txdr->size, 4096);
2508
2509 txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma);
2510 if (!txdr->desc) {
2511 vfree(txdr->tx_buffer_info);
2512 DPRINTK(PROBE, ERR,
2513 "Memory allocation failed for the tx desc ring\n");
2514 return -ENOMEM;
2515 }
2516
9a799d71
AK		 2517 txdr->next_to_use = 0;
2518 txdr->next_to_clean = 0;
2519 txdr->work_limit = txdr->count;
9a799d71
AK		 2520
2521 return 0;
2522}
2523
2524/**
2525 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
2526 * @adapter: board private structure
2527 * @rxdr: rx descriptor ring (for a specific queue) to setup
2528 *
2529 * Returns 0 on success, negative on failure
2530 **/
2531int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
2532 struct ixgbe_ring *rxdr)
2533{
2534 struct pci_dev *pdev = adapter->pdev;
021230d4 2535 int size;
9a799d71 2536
177db6ff
MC		 2537 size = sizeof(struct net_lro_desc) * IXGBE_MAX_LRO_DESCRIPTORS;
2538 rxdr->lro_mgr.lro_arr = vmalloc(size);
2539 if (!rxdr->lro_mgr.lro_arr)
2540 return -ENOMEM;
2541 memset(rxdr->lro_mgr.lro_arr, 0, size);
2542
9a799d71
AK		 2543 size = sizeof(struct ixgbe_rx_buffer) * rxdr->count;
2544 rxdr->rx_buffer_info = vmalloc(size);
2545 if (!rxdr->rx_buffer_info) {
2546 DPRINTK(PROBE, ERR,
2547 "vmalloc allocation failed for the rx desc ring\n");
177db6ff 2548 goto alloc_failed;
9a799d71
AK		 2549 }
2550 memset(rxdr->rx_buffer_info, 0, size);
2551
9a799d71 2552 /* Round up to nearest 4K */
021230d4 2553 rxdr->size = rxdr->count * sizeof(union ixgbe_adv_rx_desc);
9a799d71
AK		 2554 rxdr->size = ALIGN(rxdr->size, 4096);
2555
2556 rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma);
2557
2558 if (!rxdr->desc) {
2559 DPRINTK(PROBE, ERR,
2560 "Memory allocation failed for the rx desc ring\n");
2561 vfree(rxdr->rx_buffer_info);
177db6ff 2562 goto alloc_failed;
9a799d71
AK		 2563 }
2564
2565 rxdr->next_to_clean = 0;
2566 rxdr->next_to_use = 0;
9a799d71
AK		 2567
2568 return 0;
177db6ff
MC		 2569
2570alloc_failed:
2571 vfree(rxdr->lro_mgr.lro_arr);
2572 rxdr->lro_mgr.lro_arr = NULL;
2573 return -ENOMEM;
9a799d71
AK		 2574}
2575
2576/**
2577 * ixgbe_free_tx_resources - Free Tx Resources per Queue
2578 * @adapter: board private structure
2579 * @tx_ring: Tx descriptor ring for a specific queue
2580 *
2581 * Free all transmit software resources
2582 **/
2583static void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
2584 struct ixgbe_ring *tx_ring)
2585{
2586 struct pci_dev *pdev = adapter->pdev;
2587
2588 ixgbe_clean_tx_ring(adapter, tx_ring);
2589
2590 vfree(tx_ring->tx_buffer_info);
2591 tx_ring->tx_buffer_info = NULL;
2592
2593 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
2594
2595 tx_ring->desc = NULL;
2596}
2597
2598/**
2599 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
2600 * @adapter: board private structure
2601 *
2602 * Free all transmit software resources
2603 **/
2604static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
2605{
2606 int i;
2607
2608 for (i = 0; i < adapter->num_tx_queues; i++)
2609 ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
2610}
2611
2612/**
2613 * ixgbe_free_rx_resources - Free Rx Resources
2614 * @adapter: board private structure
2615 * @rx_ring: ring to clean the resources from
2616 *
2617 * Free all receive software resources
2618 **/
2619static void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
2620 struct ixgbe_ring *rx_ring)
2621{
2622 struct pci_dev *pdev = adapter->pdev;
2623
177db6ff
MC		 2624 vfree(rx_ring->lro_mgr.lro_arr);
2625 rx_ring->lro_mgr.lro_arr = NULL;
2626
9a799d71
AK		 2627 ixgbe_clean_rx_ring(adapter, rx_ring);
2628
2629 vfree(rx_ring->rx_buffer_info);
2630 rx_ring->rx_buffer_info = NULL;
2631
2632 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2633
2634 rx_ring->desc = NULL;
2635}
2636
2637/**
2638 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
2639 * @adapter: board private structure
2640 *
2641 * Free all receive software resources
2642 **/
2643static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
2644{
2645 int i;
2646
2647 for (i = 0; i < adapter->num_rx_queues; i++)
2648 ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
2649}
2650
2651/**
021230d4 2652 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
9a799d71
AK		 2653 * @adapter: board private structure
2654 *
2655 * If this function returns with an error, then it's possible one or
2656 * more of the rings is populated (while the rest are not). It is the
2657 * callers duty to clean those orphaned rings.
2658 *
2659 * Return 0 on success, negative on failure
2660 **/
2661static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
2662{
2663 int i, err = 0;
2664
2665 for (i = 0; i < adapter->num_tx_queues; i++) {
2666 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
2667 if (err) {
2668 DPRINTK(PROBE, ERR,
2669 "Allocation for Tx Queue %u failed\n", i);
2670 break;
2671 }
2672 }
2673
2674 return err;
2675}
2676
2677/**
021230d4 2678 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
9a799d71
AK		 2679 * @adapter: board private structure
2680 *
2681 * If this function returns with an error, then it's possible one or
2682 * more of the rings is populated (while the rest are not). It is the
2683 * callers duty to clean those orphaned rings.
2684 *
2685 * Return 0 on success, negative on failure
2686 **/
2687
2688static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
2689{
2690 int i, err = 0;
2691
2692 for (i = 0; i < adapter->num_rx_queues; i++) {
2693 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
2694 if (err) {
2695 DPRINTK(PROBE, ERR,
2696 "Allocation for Rx Queue %u failed\n", i);
2697 break;
2698 }
2699 }
2700
2701 return err;
2702}
2703
2704/**
2705 * ixgbe_change_mtu - Change the Maximum Transfer Unit
2706 * @netdev: network interface device structure
2707 * @new_mtu: new value for maximum frame size
2708 *
2709 * Returns 0 on success, negative on failure
2710 **/
2711static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
2712{
2713 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2714 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
2715
2716 if ((max_frame < (ETH_ZLEN + ETH_FCS_LEN)) ||
2717 (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
2718 return -EINVAL;
2719
021230d4
AV		 2720 DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
2721 netdev->mtu, new_mtu);
2722 /* must set new MTU before calling down or up */
9a799d71
AK		 2723 netdev->mtu = new_mtu;
2724
d4f80882
AV		 2725 if (netif_running(netdev))
2726 ixgbe_reinit_locked(adapter);
9a799d71
AK		 2727
2728 return 0;
2729}
2730
2731/**
2732 * ixgbe_open - Called when a network interface is made active
2733 * @netdev: network interface device structure
2734 *
2735 * Returns 0 on success, negative value on failure
2736 *
2737 * The open entry point is called when a network interface is made
2738 * active by the system (IFF_UP). At this point all resources needed
2739 * for transmit and receive operations are allocated, the interrupt
2740 * handler is registered with the OS, the watchdog timer is started,
2741 * and the stack is notified that the interface is ready.
2742 **/
2743static int ixgbe_open(struct net_device *netdev)
2744{
2745 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2746 int err;
4bebfaa5
AK		 2747
2748 /* disallow open during test */
2749 if (test_bit(__IXGBE_TESTING, &adapter->state))
2750 return -EBUSY;
9a799d71 2751
9a799d71
AK		 2752 /* allocate transmit descriptors */
2753 err = ixgbe_setup_all_tx_resources(adapter);
2754 if (err)
2755 goto err_setup_tx;
2756
9a799d71
AK		 2757 /* allocate receive descriptors */
2758 err = ixgbe_setup_all_rx_resources(adapter);
2759 if (err)
2760 goto err_setup_rx;
2761
2762 ixgbe_configure(adapter);
2763
021230d4 2764 err = ixgbe_request_irq(adapter);
9a799d71
AK		 2765 if (err)
2766 goto err_req_irq;
2767
9a799d71
AK		 2768 err = ixgbe_up_complete(adapter);
2769 if (err)
2770 goto err_up;
2771
d55b53ff
JK		 2772 netif_tx_start_all_queues(netdev);
2773
9a799d71
AK		 2774 return 0;
2775
2776err_up:
5eba3699 2777 ixgbe_release_hw_control(adapter);
9a799d71
AK		 2778 ixgbe_free_irq(adapter);
2779err_req_irq:
2780 ixgbe_free_all_rx_resources(adapter);
2781err_setup_rx:
2782 ixgbe_free_all_tx_resources(adapter);
2783err_setup_tx:
2784 ixgbe_reset(adapter);
2785
2786 return err;
2787}
2788
2789/**
2790 * ixgbe_close - Disables a network interface
2791 * @netdev: network interface device structure
2792 *
2793 * Returns 0, this is not allowed to fail
2794 *
2795 * The close entry point is called when an interface is de-activated
2796 * by the OS. The hardware is still under the drivers control, but
2797 * needs to be disabled. A global MAC reset is issued to stop the
2798 * hardware, and all transmit and receive resources are freed.
2799 **/
2800static int ixgbe_close(struct net_device *netdev)
2801{
2802 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 2803
2804 ixgbe_down(adapter);
2805 ixgbe_free_irq(adapter);
2806
2807 ixgbe_free_all_tx_resources(adapter);
2808 ixgbe_free_all_rx_resources(adapter);
2809
5eba3699 2810 ixgbe_release_hw_control(adapter);
9a799d71
AK		 2811
2812 return 0;
2813}
2814
2815/**
2816 * ixgbe_update_stats - Update the board statistics counters.
2817 * @adapter: board private structure
2818 **/
2819void ixgbe_update_stats(struct ixgbe_adapter *adapter)
2820{
2821 struct ixgbe_hw *hw = &adapter->hw;
6f11eef7
AV		 2822 u64 total_mpc = 0;
2823 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
9a799d71
AK		 2824
2825 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 2826 for (i = 0; i < 8; i++) {
2827 /* for packet buffers not used, the register should read 0 */
2828 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2829 missed_rx += mpc;
2830 adapter->stats.mpc[i] += mpc;
2831 total_mpc += adapter->stats.mpc[i];
2832 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2833 }
2834 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
2835 /* work around hardware counting issue */
2836 adapter->stats.gprc -= missed_rx;
2837
2838 /* 82598 hardware only has a 32 bit counter in the high register */
9a799d71 2839 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
6f11eef7
AV		 2840 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2841 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
9a799d71
AK		 2842 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2843 adapter->stats.bprc += bprc;
2844 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2845 adapter->stats.mprc -= bprc;
2846 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2847 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2848 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2849 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2850 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2851 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2852 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
9a799d71
AK		 2853 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2854 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
9a799d71 2855 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
6f11eef7
AV		 2856 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2857 adapter->stats.lxontxc += lxon;
2858 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2859 adapter->stats.lxofftxc += lxoff;
9a799d71
AK		 2860 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2861 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6f11eef7
AV		 2862 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2863 /*
2864 * 82598 errata - tx of flow control packets is included in tx counters
2865 */
2866 xon_off_tot = lxon + lxoff;
2867 adapter->stats.gptc -= xon_off_tot;
2868 adapter->stats.mptc -= xon_off_tot;
2869 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
9a799d71
AK		 2870 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2871 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2872 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
9a799d71
AK		 2873 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2874 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6f11eef7 2875 adapter->stats.ptc64 -= xon_off_tot;
9a799d71
AK		 2876 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2877 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2878 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2879 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2880 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
9a799d71
AK		 2881 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2882
2883 /* Fill out the OS statistics structure */
9a799d71
AK		 2884 adapter->net_stats.multicast = adapter->stats.mprc;
2885
2886 /* Rx Errors */
2887 adapter->net_stats.rx_errors = adapter->stats.crcerrs +
2888 adapter->stats.rlec;
2889 adapter->net_stats.rx_dropped = 0;
2890 adapter->net_stats.rx_length_errors = adapter->stats.rlec;
2891 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
6f11eef7 2892 adapter->net_stats.rx_missed_errors = total_mpc;
9a799d71
AK		 2893}
2894
2895/**
2896 * ixgbe_watchdog - Timer Call-back
2897 * @data: pointer to adapter cast into an unsigned long
2898 **/
2899static void ixgbe_watchdog(unsigned long data)
2900{
2901 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
2902 struct net_device *netdev = adapter->netdev;
2903 bool link_up;
2904 u32 link_speed = 0;
2905
3957d63d 2906 adapter->hw.mac.ops.check_link(&adapter->hw, &(link_speed), &link_up);
9a799d71
AK		 2907
2908 if (link_up) {
2909 if (!netif_carrier_ok(netdev)) {
2910 u32 frctl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2911 u32 rmcs = IXGBE_READ_REG(&adapter->hw, IXGBE_RMCS);
2912#define FLOW_RX (frctl & IXGBE_FCTRL_RFCE)
2913#define FLOW_TX (rmcs & IXGBE_RMCS_TFCE_802_3X)
2914 DPRINTK(LINK, INFO, "NIC Link is Up %s, "
2915 "Flow Control: %s\n",
2916 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
2917 "10 Gbps" :
2918 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5a059e9d 2919 "1 Gbps" : "unknown speed")),
9a799d71
AK		 2920 ((FLOW_RX && FLOW_TX) ? "RX/TX" :
2921 (FLOW_RX ? "RX" :
2922 (FLOW_TX ? "TX" : "None"))));
2923
2924 netif_carrier_on(netdev);
fd2ea0a7 2925 netif_tx_wake_all_queues(netdev);
9a799d71
AK		 2926 } else {
2927 /* Force detection of hung controller */
2928 adapter->detect_tx_hung = true;
2929 }
2930 } else {
2931 if (netif_carrier_ok(netdev)) {
2932 DPRINTK(LINK, INFO, "NIC Link is Down\n");
2933 netif_carrier_off(netdev);
fd2ea0a7 2934 netif_tx_stop_all_queues(netdev);
9a799d71
AK		 2935 }
2936 }
2937
2938 ixgbe_update_stats(adapter);
2939
021230d4
AV		 2940 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2941 /* Cause software interrupt to ensure rx rings are cleaned */
2942 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2943 u32 eics =
2944 (1 << (adapter->num_msix_vectors - NON_Q_VECTORS)) - 1;
2945 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, eics);
2946 } else {
2947 /* for legacy and MSI interrupts don't set any bits that
2948 * are enabled for EIAM, because this operation would
2949 * set *both* EIMS and EICS for any bit in EIAM */
2950 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
2951 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
2952 }
2953 /* Reset the timer */
9a799d71
AK		 2954 mod_timer(&adapter->watchdog_timer,
2955 round_jiffies(jiffies + 2 * HZ));
021230d4 2956 }
9a799d71
AK		 2957}
2958
9a799d71
AK		 2959static int ixgbe_tso(struct ixgbe_adapter *adapter,
2960 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
2961 u32 tx_flags, u8 *hdr_len)
2962{
2963 struct ixgbe_adv_tx_context_desc *context_desc;
2964 unsigned int i;
2965 int err;
2966 struct ixgbe_tx_buffer *tx_buffer_info;
2967 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
2968 u32 mss_l4len_idx = 0, l4len;
9a799d71
AK		 2969
2970 if (skb_is_gso(skb)) {
2971 if (skb_header_cloned(skb)) {
2972 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2973 if (err)
2974 return err;
2975 }
2976 l4len = tcp_hdrlen(skb);
2977 *hdr_len += l4len;
2978
8327d000 2979 if (skb->protocol == htons(ETH_P_IP)) {
9a799d71
AK		 2980 struct iphdr *iph = ip_hdr(skb);
2981 iph->tot_len = 0;
2982 iph->check = 0;
2983 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2984 iph->daddr, 0,
2985 IPPROTO_TCP,
2986 0);
2987 adapter->hw_tso_ctxt++;
2988 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
2989 ipv6_hdr(skb)->payload_len = 0;
2990 tcp_hdr(skb)->check =
2991 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2992 &ipv6_hdr(skb)->daddr,
2993 0, IPPROTO_TCP, 0);
2994 adapter->hw_tso6_ctxt++;
2995 }
2996
2997 i = tx_ring->next_to_use;
2998
2999 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3000 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
3001
3002 /* VLAN MACLEN IPLEN */
3003 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
3004 vlan_macip_lens |=
3005 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
3006 vlan_macip_lens |= ((skb_network_offset(skb)) <<
3007 IXGBE_ADVTXD_MACLEN_SHIFT);
3008 *hdr_len += skb_network_offset(skb);
3009 vlan_macip_lens |=
3010 (skb_transport_header(skb) - skb_network_header(skb));
3011 *hdr_len +=
3012 (skb_transport_header(skb) - skb_network_header(skb));
3013 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
3014 context_desc->seqnum_seed = 0;
3015
3016 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
3017 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
3018 IXGBE_ADVTXD_DTYP_CTXT);
3019
8327d000 3020 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 3021 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
3022 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
3023 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
3024
3025 /* MSS L4LEN IDX */
3026 mss_l4len_idx |=
3027 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
3028 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
3029 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
3030
3031 tx_buffer_info->time_stamp = jiffies;
3032 tx_buffer_info->next_to_watch = i;
3033
3034 i++;
3035 if (i == tx_ring->count)
3036 i = 0;
3037 tx_ring->next_to_use = i;
3038
3039 return true;
3040 }
3041 return false;
3042}
3043
3044static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
3045 struct ixgbe_ring *tx_ring,
3046 struct sk_buff *skb, u32 tx_flags)
3047{
3048 struct ixgbe_adv_tx_context_desc *context_desc;
3049 unsigned int i;
3050 struct ixgbe_tx_buffer *tx_buffer_info;
3051 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
3052
3053 if (skb->ip_summed == CHECKSUM_PARTIAL ||
3054 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
3055 i = tx_ring->next_to_use;
3056 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3057 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
3058
3059 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
3060 vlan_macip_lens |=
3061 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
3062 vlan_macip_lens |= (skb_network_offset(skb) <<
3063 IXGBE_ADVTXD_MACLEN_SHIFT);
3064 if (skb->ip_summed == CHECKSUM_PARTIAL)
3065 vlan_macip_lens |= (skb_transport_header(skb) -
3066 skb_network_header(skb));
3067
3068 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
3069 context_desc->seqnum_seed = 0;
3070
3071 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
3072 IXGBE_ADVTXD_DTYP_CTXT);
3073
3074 if (skb->ip_summed == CHECKSUM_PARTIAL) {
41825d71
AK		 3075 switch (skb->protocol) {
3076 case __constant_htons(ETH_P_IP):
9a799d71 3077 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
41825d71
AK		 3078 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
3079 type_tucmd_mlhl |=
3080 IXGBE_ADVTXD_TUCMD_L4T_TCP;
3081 break;
3082
3083 case __constant_htons(ETH_P_IPV6):
3084 /* XXX what about other V6 headers?? */
3085 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
3086 type_tucmd_mlhl |=
3087 IXGBE_ADVTXD_TUCMD_L4T_TCP;
3088 break;
9a799d71 3089
41825d71
AK		 3090 default:
3091 if (unlikely(net_ratelimit())) {
3092 DPRINTK(PROBE, WARNING,
3093 "partial checksum but proto=%x!\n",
3094 skb->protocol);
3095 }
3096 break;
3097 }
9a799d71
AK		 3098 }
3099
3100 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
3101 context_desc->mss_l4len_idx = 0;
3102
3103 tx_buffer_info->time_stamp = jiffies;
3104 tx_buffer_info->next_to_watch = i;
3105 adapter->hw_csum_tx_good++;
3106 i++;
3107 if (i == tx_ring->count)
3108 i = 0;
3109 tx_ring->next_to_use = i;
3110
3111 return true;
3112 }
3113 return false;
3114}
3115
3116static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
3117 struct ixgbe_ring *tx_ring,
3118 struct sk_buff *skb, unsigned int first)
3119{
3120 struct ixgbe_tx_buffer *tx_buffer_info;
3121 unsigned int len = skb->len;
3122 unsigned int offset = 0, size, count = 0, i;
3123 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
3124 unsigned int f;
3125
3126 len -= skb->data_len;
3127
3128 i = tx_ring->next_to_use;
3129
3130 while (len) {
3131 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3132 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
3133
3134 tx_buffer_info->length = size;
3135 tx_buffer_info->dma = pci_map_single(adapter->pdev,
3136 skb->data + offset,
3137 size, PCI_DMA_TODEVICE);
3138 tx_buffer_info->time_stamp = jiffies;
3139 tx_buffer_info->next_to_watch = i;
3140
3141 len -= size;
3142 offset += size;
3143 count++;
3144 i++;
3145 if (i == tx_ring->count)
3146 i = 0;
3147 }
3148
3149 for (f = 0; f < nr_frags; f++) {
3150 struct skb_frag_struct *frag;
3151
3152 frag = &skb_shinfo(skb)->frags[f];
3153 len = frag->size;
3154 offset = frag->page_offset;
3155
3156 while (len) {
3157 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3158 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
3159
3160 tx_buffer_info->length = size;
3161 tx_buffer_info->dma = pci_map_page(adapter->pdev,
3162 frag->page,
3163 offset,
3164 size, PCI_DMA_TODEVICE);
3165 tx_buffer_info->time_stamp = jiffies;
3166 tx_buffer_info->next_to_watch = i;
3167
3168 len -= size;
3169 offset += size;
3170 count++;
3171 i++;
3172 if (i == tx_ring->count)
3173 i = 0;
3174 }
3175 }
3176 if (i == 0)
3177 i = tx_ring->count - 1;
3178 else
3179 i = i - 1;
3180 tx_ring->tx_buffer_info[i].skb = skb;
3181 tx_ring->tx_buffer_info[first].next_to_watch = i;
3182
3183 return count;
3184}
3185
3186static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
3187 struct ixgbe_ring *tx_ring,
3188 int tx_flags, int count, u32 paylen, u8 hdr_len)
3189{
3190 union ixgbe_adv_tx_desc *tx_desc = NULL;
3191 struct ixgbe_tx_buffer *tx_buffer_info;
3192 u32 olinfo_status = 0, cmd_type_len = 0;
3193 unsigned int i;
3194 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
3195
3196 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
3197
3198 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
3199
3200 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
3201 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
3202
3203 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
3204 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
3205
3206 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
3207 IXGBE_ADVTXD_POPTS_SHIFT;
3208
3209 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
3210 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
3211 IXGBE_ADVTXD_POPTS_SHIFT;
3212
3213 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
3214 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
3215 IXGBE_ADVTXD_POPTS_SHIFT;
3216
3217 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
3218
3219 i = tx_ring->next_to_use;
3220 while (count--) {
3221 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3222 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
3223 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
3224 tx_desc->read.cmd_type_len =
3225 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
3226 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
3227
3228 i++;
3229 if (i == tx_ring->count)
3230 i = 0;
3231 }
3232
3233 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
3234
3235 /*
3236 * Force memory writes to complete before letting h/w
3237 * know there are new descriptors to fetch. (Only
3238 * applicable for weak-ordered memory model archs,
3239 * such as IA-64).
3240 */
3241 wmb();
3242
3243 tx_ring->next_to_use = i;
3244 writel(i, adapter->hw.hw_addr + tx_ring->tail);
3245}
3246
e092be60
AV		 3247static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
3248 struct ixgbe_ring *tx_ring, int size)
3249{
3250 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3251
30eba97a 3252 netif_stop_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 3253 /* Herbert's original patch had:
3254 * smp_mb__after_netif_stop_queue();
3255 * but since that doesn't exist yet, just open code it. */
3256 smp_mb();
3257
3258 /* We need to check again in a case another CPU has just
3259 * made room available. */
3260 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
3261 return -EBUSY;
3262
3263 /* A reprieve! - use start_queue because it doesn't call schedule */
30eba97a 3264 netif_wake_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 3265 ++adapter->restart_queue;
3266 return 0;
3267}
3268
3269static int ixgbe_maybe_stop_tx(struct net_device *netdev,
3270 struct ixgbe_ring *tx_ring, int size)
3271{
3272 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
3273 return 0;
3274 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
3275}
3276
3277
9a799d71
AK		 3278static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
3279{
3280 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3281 struct ixgbe_ring *tx_ring;
3282 unsigned int len = skb->len;
3283 unsigned int first;
3284 unsigned int tx_flags = 0;
30eba97a
AV		 3285 u8 hdr_len = 0;
3286 int r_idx = 0, tso;
9a799d71
AK		 3287 unsigned int mss = 0;
3288 int count = 0;
3289 unsigned int f;
3290 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
3291 len -= skb->data_len;
30eba97a 3292 r_idx = (adapter->num_tx_queues - 1) & skb->queue_mapping;
30eba97a 3293 tx_ring = &adapter->tx_ring[r_idx];
9a799d71 3294
9a799d71
AK		 3295
3296 if (skb->len <= 0) {
3297 dev_kfree_skb(skb);
3298 return NETDEV_TX_OK;
3299 }
3300 mss = skb_shinfo(skb)->gso_size;
3301
3302 if (mss)
3303 count++;
3304 else if (skb->ip_summed == CHECKSUM_PARTIAL)
3305 count++;
3306
3307 count += TXD_USE_COUNT(len);
3308 for (f = 0; f < nr_frags; f++)
3309 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
3310
e092be60 3311 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
9a799d71 3312 adapter->tx_busy++;
9a799d71
AK		 3313 return NETDEV_TX_BUSY;
3314 }
9a799d71
AK		 3315 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
3316 tx_flags |= IXGBE_TX_FLAGS_VLAN;
3317 tx_flags |= (vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT);
3318 }
3319
8327d000 3320 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 3321 tx_flags |= IXGBE_TX_FLAGS_IPV4;
3322 first = tx_ring->next_to_use;
3323 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
3324 if (tso < 0) {
3325 dev_kfree_skb_any(skb);
3326 return NETDEV_TX_OK;
3327 }
3328
3329 if (tso)
3330 tx_flags |= IXGBE_TX_FLAGS_TSO;
3331 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
3332 (skb->ip_summed == CHECKSUM_PARTIAL))
3333 tx_flags |= IXGBE_TX_FLAGS_CSUM;
3334
3335 ixgbe_tx_queue(adapter, tx_ring, tx_flags,
3336 ixgbe_tx_map(adapter, tx_ring, skb, first),
3337 skb->len, hdr_len);
3338
3339 netdev->trans_start = jiffies;
3340
e092be60 3341 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
9a799d71
AK		 3342
3343 return NETDEV_TX_OK;
3344}
3345
3346/**
3347 * ixgbe_get_stats - Get System Network Statistics
3348 * @netdev: network interface device structure
3349 *
3350 * Returns the address of the device statistics structure.
3351 * The statistics are actually updated from the timer callback.
3352 **/
3353static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
3354{
3355 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3356
3357 /* only return the current stats */
3358 return &adapter->net_stats;
3359}
3360
3361/**
3362 * ixgbe_set_mac - Change the Ethernet Address of the NIC
3363 * @netdev: network interface device structure
3364 * @p: pointer to an address structure
3365 *
3366 * Returns 0 on success, negative on failure
3367 **/
3368static int ixgbe_set_mac(struct net_device *netdev, void *p)
3369{
3370 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3371 struct sockaddr *addr = p;
3372
3373 if (!is_valid_ether_addr(addr->sa_data))
3374 return -EADDRNOTAVAIL;
3375
3376 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
3377 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
3378
3379 ixgbe_set_rar(&adapter->hw, 0, adapter->hw.mac.addr, 0, IXGBE_RAH_AV);
3380
3381 return 0;
3382}
3383
3384#ifdef CONFIG_NET_POLL_CONTROLLER
3385/*
3386 * Polling 'interrupt' - used by things like netconsole to send skbs
3387 * without having to re-enable interrupts. It's not called while
3388 * the interrupt routine is executing.
3389 */
3390static void ixgbe_netpoll(struct net_device *netdev)
3391{
3392 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3393
3394 disable_irq(adapter->pdev->irq);
3395 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
3396 ixgbe_intr(adapter->pdev->irq, netdev);
3397 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
3398 enable_irq(adapter->pdev->irq);
3399}
3400#endif
3401
021230d4
AV		 3402/**
3403 * ixgbe_napi_add_all - prep napi structs for use
3404 * @adapter: private struct
3405 * helper function to napi_add each possible q_vector->napi
3406 */
3407static void ixgbe_napi_add_all(struct ixgbe_adapter *adapter)
3408{
3409 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3410 int (*poll)(struct napi_struct *, int);
3411
3412 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3413 poll = &ixgbe_clean_rxonly;
3414 } else {
3415 poll = &ixgbe_poll;
3416 /* only one q_vector for legacy modes */
3417 q_vectors = 1;
3418 }
3419
3420 for (i = 0; i < q_vectors; i++) {
3421 struct ixgbe_q_vector *q_vector = &adapter->q_vector[i];
3422 netif_napi_add(adapter->netdev, &q_vector->napi,
3423 (*poll), 64);
3424 }
3425}
3426
9a799d71
AK		 3427/**
3428 * ixgbe_probe - Device Initialization Routine
3429 * @pdev: PCI device information struct
3430 * @ent: entry in ixgbe_pci_tbl
3431 *
3432 * Returns 0 on success, negative on failure
3433 *
3434 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
3435 * The OS initialization, configuring of the adapter private structure,
3436 * and a hardware reset occur.
3437 **/
3438static int __devinit ixgbe_probe(struct pci_dev *pdev,
3439 const struct pci_device_id *ent)
3440{
3441 struct net_device *netdev;
3442 struct ixgbe_adapter *adapter = NULL;
3443 struct ixgbe_hw *hw;
3444 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
3445 unsigned long mmio_start, mmio_len;
3446 static int cards_found;
3447 int i, err, pci_using_dac;
3448 u16 link_status, link_speed, link_width;
3449 u32 part_num;
3450
3451 err = pci_enable_device(pdev);
3452 if (err)
3453 return err;
3454
3455 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK) &&
3456 !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK)) {
3457 pci_using_dac = 1;
3458 } else {
3459 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3460 if (err) {
3461 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3462 if (err) {
3463 dev_err(&pdev->dev, "No usable DMA "
3464 "configuration, aborting\n");
3465 goto err_dma;
3466 }
3467 }
3468 pci_using_dac = 0;
3469 }
3470
3471 err = pci_request_regions(pdev, ixgbe_driver_name);
3472 if (err) {
3473 dev_err(&pdev->dev, "pci_request_regions failed 0x%x\n", err);
3474 goto err_pci_reg;
3475 }
3476
3477 pci_set_master(pdev);
fb3b27bc 3478 pci_save_state(pdev);
9a799d71 3479
30eba97a 3480 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
9a799d71
AK		 3481 if (!netdev) {
3482 err = -ENOMEM;
3483 goto err_alloc_etherdev;
3484 }
3485
9a799d71
AK		 3486 SET_NETDEV_DEV(netdev, &pdev->dev);
3487
3488 pci_set_drvdata(pdev, netdev);
3489 adapter = netdev_priv(netdev);
3490
3491 adapter->netdev = netdev;
3492 adapter->pdev = pdev;
3493 hw = &adapter->hw;
3494 hw->back = adapter;
3495 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
3496
3497 mmio_start = pci_resource_start(pdev, 0);
3498 mmio_len = pci_resource_len(pdev, 0);
3499
3500 hw->hw_addr = ioremap(mmio_start, mmio_len);
3501 if (!hw->hw_addr) {
3502 err = -EIO;
3503 goto err_ioremap;
3504 }
3505
3506 for (i = 1; i <= 5; i++) {
3507 if (pci_resource_len(pdev, i) == 0)
3508 continue;
3509 }
3510
3511 netdev->open = &ixgbe_open;
3512 netdev->stop = &ixgbe_close;
3513 netdev->hard_start_xmit = &ixgbe_xmit_frame;
3514 netdev->get_stats = &ixgbe_get_stats;
2c5645cf
CL		 3515 netdev->set_rx_mode = &ixgbe_set_rx_mode;
3516 netdev->set_multicast_list = &ixgbe_set_rx_mode;
9a799d71
AK		 3517 netdev->set_mac_address = &ixgbe_set_mac;
3518 netdev->change_mtu = &ixgbe_change_mtu;
3519 ixgbe_set_ethtool_ops(netdev);
3520 netdev->tx_timeout = &ixgbe_tx_timeout;
3521 netdev->watchdog_timeo = 5 * HZ;
9a799d71
AK		 3522 netdev->vlan_rx_register = ixgbe_vlan_rx_register;
3523 netdev->vlan_rx_add_vid = ixgbe_vlan_rx_add_vid;
3524 netdev->vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid;
3525#ifdef CONFIG_NET_POLL_CONTROLLER
3526 netdev->poll_controller = ixgbe_netpoll;
3527#endif
3528 strcpy(netdev->name, pci_name(pdev));
3529
3530 netdev->mem_start = mmio_start;
3531 netdev->mem_end = mmio_start + mmio_len;
3532
3533 adapter->bd_number = cards_found;
3534
3535 /* PCI config space info */
3536 hw->vendor_id = pdev->vendor;
3537 hw->device_id = pdev->device;
3538 hw->revision_id = pdev->revision;
3539 hw->subsystem_vendor_id = pdev->subsystem_vendor;
3540 hw->subsystem_device_id = pdev->subsystem_device;
3541
3542 /* Setup hw api */
3543 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 3544 hw->mac.type = ii->mac;
9a799d71
AK		 3545
3546 err = ii->get_invariants(hw);
3547 if (err)
3548 goto err_hw_init;
3549
3550 /* setup the private structure */
3551 err = ixgbe_sw_init(adapter);
3552 if (err)
3553 goto err_sw_init;
3554
3555 netdev->features = NETIF_F_SG |
3556 NETIF_F_HW_CSUM |
3557 NETIF_F_HW_VLAN_TX |
3558 NETIF_F_HW_VLAN_RX |
3559 NETIF_F_HW_VLAN_FILTER;
3560
177db6ff 3561 netdev->features |= NETIF_F_LRO;
9a799d71 3562 netdev->features |= NETIF_F_TSO;
9a799d71 3563 netdev->features |= NETIF_F_TSO6;
ad31c402
JK		 3564
3565 netdev->vlan_features |= NETIF_F_TSO;
3566 netdev->vlan_features |= NETIF_F_TSO6;
3567 netdev->vlan_features |= NETIF_F_HW_CSUM;
3568 netdev->vlan_features |= NETIF_F_SG;
3569
9a799d71
AK		 3570 if (pci_using_dac)
3571 netdev->features |= NETIF_F_HIGHDMA;
3572
9a799d71
AK		 3573 /* make sure the EEPROM is good */
3574 if (ixgbe_validate_eeprom_checksum(hw, NULL) < 0) {
3575 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
3576 err = -EIO;
3577 goto err_eeprom;
3578 }
3579
3580 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
3581 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
3582
3583 if (ixgbe_validate_mac_addr(netdev->dev_addr)) {
3584 err = -EIO;
3585 goto err_eeprom;
3586 }
3587
3588 init_timer(&adapter->watchdog_timer);
3589 adapter->watchdog_timer.function = &ixgbe_watchdog;
3590 adapter->watchdog_timer.data = (unsigned long)adapter;
3591
3592 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
3593
3594 /* initialize default flow control settings */
3595 hw->fc.original_type = ixgbe_fc_full;
3596 hw->fc.type = ixgbe_fc_full;
3597 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
3598 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
3599 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
3600
021230d4
AV		 3601 err = ixgbe_init_interrupt_scheme(adapter);
3602 if (err)
3603 goto err_sw_init;
9a799d71
AK		 3604
3605 /* print bus type/speed/width info */
3606 pci_read_config_word(pdev, IXGBE_PCI_LINK_STATUS, &link_status);
3607 link_speed = link_status & IXGBE_PCI_LINK_SPEED;
3608 link_width = link_status & IXGBE_PCI_LINK_WIDTH;
3609 dev_info(&pdev->dev, "(PCI Express:%s:%s) "
3610 "%02x:%02x:%02x:%02x:%02x:%02x\n",
3611 ((link_speed == IXGBE_PCI_LINK_SPEED_5000) ? "5.0Gb/s" :
3612 (link_speed == IXGBE_PCI_LINK_SPEED_2500) ? "2.5Gb/s" :
3613 "Unknown"),
3614 ((link_width == IXGBE_PCI_LINK_WIDTH_8) ? "Width x8" :
3615 (link_width == IXGBE_PCI_LINK_WIDTH_4) ? "Width x4" :
3616 (link_width == IXGBE_PCI_LINK_WIDTH_2) ? "Width x2" :
3617 (link_width == IXGBE_PCI_LINK_WIDTH_1) ? "Width x1" :
3618 "Unknown"),
3619 netdev->dev_addr[0], netdev->dev_addr[1], netdev->dev_addr[2],
3620 netdev->dev_addr[3], netdev->dev_addr[4], netdev->dev_addr[5]);
3621 ixgbe_read_part_num(hw, &part_num);
3622 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
3623 hw->mac.type, hw->phy.type,
3624 (part_num >> 8), (part_num & 0xff));
3625
0c254d86
AK		 3626 if (link_width <= IXGBE_PCI_LINK_WIDTH_4) {
3627 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
3628 "this card is not sufficient for optimal "
3629 "performance.\n");
3630 dev_warn(&pdev->dev, "For optimal performance a x8 "
3631 "PCI-Express slot is required.\n");
3632 }
3633
9a799d71
AK		 3634 /* reset the hardware with the new settings */
3635 ixgbe_start_hw(hw);
3636
3637 netif_carrier_off(netdev);
fd2ea0a7 3638 netif_tx_stop_all_queues(netdev);
9a799d71 3639
021230d4
AV		 3640 ixgbe_napi_add_all(adapter);
3641
9a799d71
AK		 3642 strcpy(netdev->name, "eth%d");
3643 err = register_netdev(netdev);
3644 if (err)
3645 goto err_register;
3646
bd0362dd 3647#ifdef CONFIG_DCA
652f093f 3648 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd
JC		 3649 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
3650 /* always use CB2 mode, difference is masked
3651 * in the CB driver */
3652 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
3653 ixgbe_setup_dca(adapter);
3654 }
3655#endif
9a799d71
AK		 3656
3657 dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
3658 cards_found++;
3659 return 0;
3660
3661err_register:
5eba3699 3662 ixgbe_release_hw_control(adapter);
9a799d71
AK		 3663err_hw_init:
3664err_sw_init:
021230d4 3665 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 3666err_eeprom:
3667 iounmap(hw->hw_addr);
3668err_ioremap:
3669 free_netdev(netdev);
3670err_alloc_etherdev:
3671 pci_release_regions(pdev);
3672err_pci_reg:
3673err_dma:
3674 pci_disable_device(pdev);
3675 return err;
3676}
3677
3678/**
3679 * ixgbe_remove - Device Removal Routine
3680 * @pdev: PCI device information struct
3681 *
3682 * ixgbe_remove is called by the PCI subsystem to alert the driver
3683 * that it should release a PCI device. The could be caused by a
3684 * Hot-Plug event, or because the driver is going to be removed from
3685 * memory.
3686 **/
3687static void __devexit ixgbe_remove(struct pci_dev *pdev)
3688{
3689 struct net_device *netdev = pci_get_drvdata(pdev);
3690 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3691
3692 set_bit(__IXGBE_DOWN, &adapter->state);
3693 del_timer_sync(&adapter->watchdog_timer);
3694
3695 flush_scheduled_work();
3696
bd0362dd
JC		 3697#ifdef CONFIG_DCA
3698 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
3699 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
3700 dca_remove_requester(&pdev->dev);
3701 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
3702 }
3703
3704#endif
9a799d71
AK		 3705 unregister_netdev(netdev);
3706
021230d4 3707 ixgbe_reset_interrupt_capability(adapter);
5eba3699 3708
021230d4 3709 ixgbe_release_hw_control(adapter);
9a799d71
AK		 3710
3711 iounmap(adapter->hw.hw_addr);
3712 pci_release_regions(pdev);
3713
021230d4
AV		 3714 DPRINTK(PROBE, INFO, "complete\n");
3715 kfree(adapter->tx_ring);
3716 kfree(adapter->rx_ring);
3717
9a799d71
AK		 3718 free_netdev(netdev);
3719
3720 pci_disable_device(pdev);
3721}
3722
3723/**
3724 * ixgbe_io_error_detected - called when PCI error is detected
3725 * @pdev: Pointer to PCI device
3726 * @state: The current pci connection state
3727 *
3728 * This function is called after a PCI bus error affecting
3729 * this device has been detected.
3730 */
3731static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
3732 pci_channel_state_t state)
3733{
3734 struct net_device *netdev = pci_get_drvdata(pdev);
3735 struct ixgbe_adapter *adapter = netdev->priv;
3736
3737 netif_device_detach(netdev);
3738
3739 if (netif_running(netdev))
3740 ixgbe_down(adapter);
3741 pci_disable_device(pdev);
3742
3743 /* Request a slot slot reset. */
3744 return PCI_ERS_RESULT_NEED_RESET;
3745}
3746
3747/**
3748 * ixgbe_io_slot_reset - called after the pci bus has been reset.
3749 * @pdev: Pointer to PCI device
3750 *
3751 * Restart the card from scratch, as if from a cold-boot.
3752 */
3753static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
3754{
3755 struct net_device *netdev = pci_get_drvdata(pdev);
3756 struct ixgbe_adapter *adapter = netdev->priv;
3757
3758 if (pci_enable_device(pdev)) {
3759 DPRINTK(PROBE, ERR,
3760 "Cannot re-enable PCI device after reset.\n");
3761 return PCI_ERS_RESULT_DISCONNECT;
3762 }
3763 pci_set_master(pdev);
fb3b27bc 3764 pci_restore_state(pdev);
9a799d71
AK		 3765
3766 pci_enable_wake(pdev, PCI_D3hot, 0);
3767 pci_enable_wake(pdev, PCI_D3cold, 0);
3768
3769 ixgbe_reset(adapter);
3770
3771 return PCI_ERS_RESULT_RECOVERED;
3772}
3773
3774/**
3775 * ixgbe_io_resume - called when traffic can start flowing again.
3776 * @pdev: Pointer to PCI device
3777 *
3778 * This callback is called when the error recovery driver tells us that
3779 * its OK to resume normal operation.
3780 */
3781static void ixgbe_io_resume(struct pci_dev *pdev)
3782{
3783 struct net_device *netdev = pci_get_drvdata(pdev);
3784 struct ixgbe_adapter *adapter = netdev->priv;
3785
3786 if (netif_running(netdev)) {
3787 if (ixgbe_up(adapter)) {
3788 DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
3789 return;
3790 }
3791 }
3792
3793 netif_device_attach(netdev);
3794
3795}
3796
3797static struct pci_error_handlers ixgbe_err_handler = {
3798 .error_detected = ixgbe_io_error_detected,
3799 .slot_reset = ixgbe_io_slot_reset,
3800 .resume = ixgbe_io_resume,
3801};
3802
3803static struct pci_driver ixgbe_driver = {
3804 .name = ixgbe_driver_name,
3805 .id_table = ixgbe_pci_tbl,
3806 .probe = ixgbe_probe,
3807 .remove = __devexit_p(ixgbe_remove),
3808#ifdef CONFIG_PM
3809 .suspend = ixgbe_suspend,
3810 .resume = ixgbe_resume,
3811#endif
3812 .shutdown = ixgbe_shutdown,
3813 .err_handler = &ixgbe_err_handler
3814};
3815
3816/**
3817 * ixgbe_init_module - Driver Registration Routine
3818 *
3819 * ixgbe_init_module is the first routine called when the driver is
3820 * loaded. All it does is register with the PCI subsystem.
3821 **/
3822static int __init ixgbe_init_module(void)
3823{
3824 int ret;
3825 printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
3826 ixgbe_driver_string, ixgbe_driver_version);
3827
3828 printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
3829
bd0362dd
JC		 3830#ifdef CONFIG_DCA
3831 dca_register_notify(&dca_notifier);
3832
3833#endif
9a799d71
AK		 3834 ret = pci_register_driver(&ixgbe_driver);
3835 return ret;
3836}
3837module_init(ixgbe_init_module);
3838
3839/**
3840 * ixgbe_exit_module - Driver Exit Cleanup Routine
3841 *
3842 * ixgbe_exit_module is called just before the driver is removed
3843 * from memory.
3844 **/
3845static void __exit ixgbe_exit_module(void)
3846{
bd0362dd
JC		 3847#ifdef CONFIG_DCA
3848 dca_unregister_notify(&dca_notifier);
3849#endif
9a799d71
AK		 3850 pci_unregister_driver(&ixgbe_driver);
3851}
bd0362dd
JC		 3852
3853#ifdef CONFIG_DCA
3854static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
3855 void *p)
3856{
3857 int ret_val;
3858
3859 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
3860 __ixgbe_notify_dca);
3861
3862 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
3863}
3864#endif /* CONFIG_DCA */
3865
9a799d71
AK		 3866module_exit(ixgbe_exit_module);
3867
3868/* ixgbe_main.c */
Ubuntu Artful kernel mirror