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ixgbe: set queue0 for srrctl configuration correctly for DCB
[mirror_ubuntu-zesty-kernel.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
3efac5a0 4 Copyright(c) 1999 - 2009 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
37#include <linux/ipv6.h>
38#include <net/checksum.h>
39#include <net/ip6_checksum.h>
40#include <linux/ethtool.h>
41#include <linux/if_vlan.h>
42
43#include "ixgbe.h"
44#include "ixgbe_common.h"
45
46char ixgbe_driver_name[] = "ixgbe";
9c8eb720 47static const char ixgbe_driver_string[] =
b4617240 48 "Intel(R) 10 Gigabit PCI Express Network Driver";
9a799d71 49
04193058 50#define DRV_VERSION "2.0.16-k2"
9c8eb720 51const char ixgbe_driver_version[] = DRV_VERSION;
3efac5a0 52static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
9a799d71
AK		 53
54static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 55 [board_82598] = &ixgbe_82598_info,
e8e26350 56 [board_82599] = &ixgbe_82599_info,
9a799d71
AK		 57};
58
59/* ixgbe_pci_tbl - PCI Device ID Table
60 *
61 * Wildcard entries (PCI_ANY_ID) should come last
62 * Last entry must be all 0s
63 *
64 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
65 * Class, Class Mask, private data (not used) }
66 */
67static struct pci_device_id ixgbe_pci_tbl[] = {
1e336d0f
DS		 68 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
69 board_82598 },
9a799d71 70 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 71 board_82598 },
9a799d71 72 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 73 board_82598 },
0befdb3e
JB		 74 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
75 board_82598 },
9a799d71 76 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 77 board_82598 },
8d792cd9
JB		 78 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
79 board_82598 },
c4900be0
DS		 80 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
81 board_82598 },
82 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
83 board_82598 },
b95f5fcb
JB		 84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
85 board_82598 },
c4900be0
DS		 86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
87 board_82598 },
2f21bdd3
DS		 88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
89 board_82598 },
e8e26350
PW		 90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
91 board_82599 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
93 board_82599 },
9a799d71
AK		 94
95 /* required last entry */
96 {0, }
97};
98MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
99
5dd2d332 100#ifdef CONFIG_IXGBE_DCA
bd0362dd 101static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
b4617240 102 void *p);
bd0362dd
JC		 103static struct notifier_block dca_notifier = {
104 .notifier_call = ixgbe_notify_dca,
105 .next = NULL,
106 .priority = 0
107};
108#endif
109
9a799d71
AK		 110MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
111MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
112MODULE_LICENSE("GPL");
113MODULE_VERSION(DRV_VERSION);
114
115#define DEFAULT_DEBUG_LEVEL_SHIFT 3
116
5eba3699
AV		 117static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
118{
119 u32 ctrl_ext;
120
121 /* Let firmware take over control of h/w */
122 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
123 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 124 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 125}
126
127static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
128{
129 u32 ctrl_ext;
130
131 /* Let firmware know the driver has taken over */
132 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
133 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 134 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 135}
9a799d71 136
e8e26350
PW		 137/*
138 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
139 * @adapter: pointer to adapter struct
140 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
141 * @queue: queue to map the corresponding interrupt to
142 * @msix_vector: the vector to map to the corresponding queue
143 *
144 */
145static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
146 u8 queue, u8 msix_vector)
9a799d71
AK		 147{
148 u32 ivar, index;
e8e26350
PW		 149 struct ixgbe_hw *hw = &adapter->hw;
150 switch (hw->mac.type) {
151 case ixgbe_mac_82598EB:
152 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
153 if (direction == -1)
154 direction = 0;
155 index = (((direction * 64) + queue) >> 2) & 0x1F;
156 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
157 ivar &= ~(0xFF << (8 * (queue & 0x3)));
158 ivar |= (msix_vector << (8 * (queue & 0x3)));
159 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
160 break;
161 case ixgbe_mac_82599EB:
162 if (direction == -1) {
163 /* other causes */
164 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
165 index = ((queue & 1) * 8);
166 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
167 ivar &= ~(0xFF << index);
168 ivar |= (msix_vector << index);
169 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
170 break;
171 } else {
172 /* tx or rx causes */
173 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
174 index = ((16 * (queue & 1)) + (8 * direction));
175 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
176 ivar &= ~(0xFF << index);
177 ivar |= (msix_vector << index);
178 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
179 break;
180 }
181 default:
182 break;
183 }
9a799d71
AK		 184}
185
186static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
b4617240
PW		 187 struct ixgbe_tx_buffer
188 *tx_buffer_info)
9a799d71 189{
44df32c5 190 tx_buffer_info->dma = 0;
9a799d71 191 if (tx_buffer_info->skb) {
44df32c5
AD		 192 skb_dma_unmap(&adapter->pdev->dev, tx_buffer_info->skb,
193 DMA_TO_DEVICE);
9a799d71
AK		 194 dev_kfree_skb_any(tx_buffer_info->skb);
195 tx_buffer_info->skb = NULL;
196 }
44df32c5 197 tx_buffer_info->time_stamp = 0;
9a799d71
AK		 198 /* tx_buffer_info must be completely set up in the transmit path */
199}
200
201static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
b4617240
PW		 202 struct ixgbe_ring *tx_ring,
203 unsigned int eop)
9a799d71 204{
e01c31a5 205 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 206
9a799d71 207 /* Detect a transmit hang in hardware, this serializes the
e01c31a5 208 * check with the clearing of time_stamp and movement of eop */
9a799d71 209 adapter->detect_tx_hung = false;
44df32c5 210 if (tx_ring->tx_buffer_info[eop].time_stamp &&
9a799d71
AK		 211 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
212 !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
213 /* detected Tx unit hang */
e01c31a5
JB		 214 union ixgbe_adv_tx_desc *tx_desc;
215 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
9a799d71 216 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
e01c31a5
JB		 217 " Tx Queue <%d>\n"
218 " TDH, TDT <%x>, <%x>\n"
9a799d71
AK		 219 " next_to_use <%x>\n"
220 " next_to_clean <%x>\n"
221 "tx_buffer_info[next_to_clean]\n"
222 " time_stamp <%lx>\n"
e01c31a5
JB		 223 " jiffies <%lx>\n",
224 tx_ring->queue_index,
44df32c5
AD		 225 IXGBE_READ_REG(hw, tx_ring->head),
226 IXGBE_READ_REG(hw, tx_ring->tail),
e01c31a5
JB		 227 tx_ring->next_to_use, eop,
228 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
9a799d71
AK		 229 return true;
230 }
231
232 return false;
233}
234
b4617240
PW		 235#define IXGBE_MAX_TXD_PWR 14
236#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
e092be60
AV		 237
238/* Tx Descriptors needed, worst case */
239#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
240 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
241#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
b4617240 242 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
e092be60 243
e01c31a5
JB		 244static void ixgbe_tx_timeout(struct net_device *netdev);
245
9a799d71
AK		 246/**
247 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
248 * @adapter: board private structure
e01c31a5 249 * @tx_ring: tx ring to clean
9a1a69ad
JB		 250 *
251 * returns true if transmit work is done
9a799d71
AK		 252 **/
253static bool ixgbe_clean_tx_irq(struct ixgbe_adapter *adapter,
e01c31a5 254 struct ixgbe_ring *tx_ring)
9a799d71 255{
e01c31a5 256 struct net_device *netdev = adapter->netdev;
12207e49
PWJ		 257 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
258 struct ixgbe_tx_buffer *tx_buffer_info;
259 unsigned int i, eop, count = 0;
e01c31a5 260 unsigned int total_bytes = 0, total_packets = 0;
9a799d71
AK		 261
262 i = tx_ring->next_to_clean;
12207e49
PWJ		 263 eop = tx_ring->tx_buffer_info[i].next_to_watch;
264 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
265
266 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
9a1a69ad 267 (count < tx_ring->work_limit)) {
12207e49
PWJ		 268 bool cleaned = false;
269 for ( ; !cleaned; count++) {
270 struct sk_buff *skb;
9a799d71
AK		 271 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
272 tx_buffer_info = &tx_ring->tx_buffer_info[i];
12207e49 273 cleaned = (i == eop);
e01c31a5 274 skb = tx_buffer_info->skb;
9a799d71 275
12207e49 276 if (cleaned && skb) {
e092be60 277 unsigned int segs, bytecount;
e01c31a5
JB		 278
279 /* gso_segs is currently only valid for tcp */
e092be60
AV		 280 segs = skb_shinfo(skb)->gso_segs ?: 1;
281 /* multiply data chunks by size of headers */
282 bytecount = ((segs - 1) * skb_headlen(skb)) +
e01c31a5
JB		 283 skb->len;
284 total_packets += segs;
285 total_bytes += bytecount;
e092be60 286 }
e01c31a5 287
9a799d71 288 ixgbe_unmap_and_free_tx_resource(adapter,
e01c31a5 289 tx_buffer_info);
9a799d71 290
12207e49
PWJ		 291 tx_desc->wb.status = 0;
292
9a799d71
AK		 293 i++;
294 if (i == tx_ring->count)
295 i = 0;
e01c31a5 296 }
12207e49
PWJ		 297
298 eop = tx_ring->tx_buffer_info[i].next_to_watch;
299 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
300 }
301
9a799d71
AK		 302 tx_ring->next_to_clean = i;
303
e092be60 304#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
e01c31a5
JB		 305 if (unlikely(count && netif_carrier_ok(netdev) &&
306 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 307 /* Make sure that anybody stopping the queue after this
308 * sees the new next_to_clean.
309 */
310 smp_mb();
30eba97a
AV		 311 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
312 !test_bit(__IXGBE_DOWN, &adapter->state)) {
313 netif_wake_subqueue(netdev, tx_ring->queue_index);
e01c31a5 314 ++adapter->restart_queue;
30eba97a 315 }
e092be60 316 }
9a799d71 317
e01c31a5
JB		 318 if (adapter->detect_tx_hung) {
319 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
320 /* schedule immediate reset if we believe we hung */
321 DPRINTK(PROBE, INFO,
322 "tx hang %d detected, resetting adapter\n",
323 adapter->tx_timeout_count + 1);
324 ixgbe_tx_timeout(adapter->netdev);
325 }
326 }
9a799d71 327
e01c31a5 328 /* re-arm the interrupt */
835462fc
NS		 329 if (count >= tx_ring->work_limit) {
330 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
331 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
332 tx_ring->v_idx);
333 else if (tx_ring->v_idx & 0xFFFFFFFF)
334 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0),
335 tx_ring->v_idx);
336 else
337 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1),
338 (tx_ring->v_idx >> 32));
339 }
340
9a799d71 341
e01c31a5
JB		 342 tx_ring->total_bytes += total_bytes;
343 tx_ring->total_packets += total_packets;
e01c31a5 344 tx_ring->stats.packets += total_packets;
12207e49 345 tx_ring->stats.bytes += total_bytes;
e01c31a5
JB		 346 adapter->net_stats.tx_bytes += total_bytes;
347 adapter->net_stats.tx_packets += total_packets;
9a1a69ad 348 return (count < tx_ring->work_limit);
9a799d71
AK		 349}
350
5dd2d332 351#ifdef CONFIG_IXGBE_DCA
bd0362dd 352static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
b4617240 353 struct ixgbe_ring *rx_ring)
bd0362dd
JC		 354{
355 u32 rxctrl;
356 int cpu = get_cpu();
3a581073 357 int q = rx_ring - adapter->rx_ring;
bd0362dd 358
3a581073 359 if (rx_ring->cpu != cpu) {
bd0362dd 360 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
e8e26350
PW		 361 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
362 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
363 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
364 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
365 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
366 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
367 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
368 }
bd0362dd
JC		 369 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
370 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
15005a32
DS		 371 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
372 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
e8e26350 373 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
bd0362dd 374 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
3a581073 375 rx_ring->cpu = cpu;
bd0362dd
JC		 376 }
377 put_cpu();
378}
379
380static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
b4617240 381 struct ixgbe_ring *tx_ring)
bd0362dd
JC		 382{
383 u32 txctrl;
384 int cpu = get_cpu();
3a581073 385 int q = tx_ring - adapter->tx_ring;
bd0362dd 386
3a581073 387 if (tx_ring->cpu != cpu) {
bd0362dd 388 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
e8e26350
PW		 389 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
390 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
391 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
392 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
393 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
394 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
395 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
396 }
bd0362dd
JC		 397 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
398 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
3a581073 399 tx_ring->cpu = cpu;
bd0362dd
JC		 400 }
401 put_cpu();
402}
403
404static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
405{
406 int i;
407
408 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
409 return;
410
411 for (i = 0; i < adapter->num_tx_queues; i++) {
412 adapter->tx_ring[i].cpu = -1;
413 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
414 }
415 for (i = 0; i < adapter->num_rx_queues; i++) {
416 adapter->rx_ring[i].cpu = -1;
417 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
418 }
419}
420
421static int __ixgbe_notify_dca(struct device *dev, void *data)
422{
423 struct net_device *netdev = dev_get_drvdata(dev);
424 struct ixgbe_adapter *adapter = netdev_priv(netdev);
425 unsigned long event = *(unsigned long *)data;
426
427 switch (event) {
428 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 429 /* if we're already enabled, don't do it again */
430 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
431 break;
bd0362dd
JC		 432 /* Always use CB2 mode, difference is masked
433 * in the CB driver. */
434 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
652f093f 435 if (dca_add_requester(dev) == 0) {
96b0e0f6 436 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 437 ixgbe_setup_dca(adapter);
438 break;
439 }
440 /* Fall Through since DCA is disabled. */
441 case DCA_PROVIDER_REMOVE:
442 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
443 dca_remove_requester(dev);
444 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
445 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
446 }
447 break;
448 }
449
652f093f 450 return 0;
bd0362dd
JC		 451}
452
5dd2d332 453#endif /* CONFIG_IXGBE_DCA */
9a799d71
AK		 454/**
455 * ixgbe_receive_skb - Send a completed packet up the stack
456 * @adapter: board private structure
457 * @skb: packet to send up
177db6ff
MC		 458 * @status: hardware indication of status of receive
459 * @rx_ring: rx descriptor ring (for a specific queue) to setup
460 * @rx_desc: rx descriptor
9a799d71 461 **/
78b6f4ce 462static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
b4617240 463 struct sk_buff *skb, u8 status,
fdaff1ce 464 struct ixgbe_ring *ring,
177db6ff 465 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 466{
78b6f4ce
HX		 467 struct ixgbe_adapter *adapter = q_vector->adapter;
468 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 469 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
470 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 471
fdaff1ce 472 skb_record_rx_queue(skb, ring->queue_index);
182ff8df 473 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
2f90b865 474 if (adapter->vlgrp && is_vlan && (tag != 0))
78b6f4ce 475 vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
9a799d71 476 else
78b6f4ce 477 napi_gro_receive(napi, skb);
177db6ff 478 } else {
182ff8df
AD		 479 if (adapter->vlgrp && is_vlan && (tag != 0))
480 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
481 else
482 netif_rx(skb);
9a799d71
AK		 483 }
484}
485
e59bd25d
AV		 486/**
487 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
488 * @adapter: address of board private structure
489 * @status_err: hardware indication of status of receive
490 * @skb: skb currently being received and modified
491 **/
9a799d71 492static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
712744be 493 u32 status_err, struct sk_buff *skb)
9a799d71
AK		 494{
495 skb->ip_summed = CHECKSUM_NONE;
496
712744be
JB		 497 /* Rx csum disabled */
498 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 499 return;
e59bd25d
AV		 500
501 /* if IP and error */
502 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
503 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 504 adapter->hw_csum_rx_error++;
505 return;
506 }
e59bd25d
AV		 507
508 if (!(status_err & IXGBE_RXD_STAT_L4CS))
509 return;
510
511 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
512 adapter->hw_csum_rx_error++;
513 return;
514 }
515
9a799d71 516 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 517 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 518 adapter->hw_csum_rx_good++;
519}
520
e8e26350
PW		 521static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
522 struct ixgbe_ring *rx_ring, u32 val)
523{
524 /*
525 * Force memory writes to complete before letting h/w
526 * know there are new descriptors to fetch. (Only
527 * applicable for weak-ordered memory model archs,
528 * such as IA-64).
529 */
530 wmb();
531 IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
532}
533
9a799d71
AK		 534/**
535 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
536 * @adapter: address of board private structure
537 **/
538static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
7c6e0a43
JB		 539 struct ixgbe_ring *rx_ring,
540 int cleaned_count)
9a799d71 541{
9a799d71
AK		 542 struct pci_dev *pdev = adapter->pdev;
543 union ixgbe_adv_rx_desc *rx_desc;
3a581073 544 struct ixgbe_rx_buffer *bi;
9a799d71 545 unsigned int i;
e8e26350 546 unsigned int bufsz = rx_ring->rx_buf_len + NET_IP_ALIGN;
9a799d71
AK		 547
548 i = rx_ring->next_to_use;
3a581073 549 bi = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 550
551 while (cleaned_count--) {
552 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
553
762f4c57 554 if (!bi->page_dma &&
3a581073 555 (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) {
3a581073 556 if (!bi->page) {
762f4c57
JB		 557 bi->page = alloc_page(GFP_ATOMIC);
558 if (!bi->page) {
559 adapter->alloc_rx_page_failed++;
560 goto no_buffers;
561 }
562 bi->page_offset = 0;
563 } else {
564 /* use a half page if we're re-using */
565 bi->page_offset ^= (PAGE_SIZE / 2);
9a799d71 566 }
762f4c57
JB		 567
568 bi->page_dma = pci_map_page(pdev, bi->page,
569 bi->page_offset,
570 (PAGE_SIZE / 2),
571 PCI_DMA_FROMDEVICE);
9a799d71
AK		 572 }
573
3a581073 574 if (!bi->skb) {
5ecc3614 575 struct sk_buff *skb;
e8e26350 576 skb = netdev_alloc_skb(adapter->netdev, bufsz);
9a799d71
AK		 577
578 if (!skb) {
579 adapter->alloc_rx_buff_failed++;
580 goto no_buffers;
581 }
582
583 /*
584 * Make buffer alignment 2 beyond a 16 byte boundary
585 * this will result in a 16 byte aligned IP header after
586 * the 14 byte MAC header is removed
587 */
588 skb_reserve(skb, NET_IP_ALIGN);
589
3a581073 590 bi->skb = skb;
e8e26350 591 bi->dma = pci_map_single(pdev, skb->data, bufsz,
3a581073 592 PCI_DMA_FROMDEVICE);
9a799d71
AK		 593 }
594 /* Refresh the desc even if buffer_addrs didn't change because
595 * each write-back erases this info. */
596 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
3a581073
JB		 597 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
598 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 599 } else {
3a581073 600 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
9a799d71
AK		 601 }
602
603 i++;
604 if (i == rx_ring->count)
605 i = 0;
3a581073 606 bi = &rx_ring->rx_buffer_info[i];
9a799d71 607 }
7c6e0a43 608
9a799d71
AK		 609no_buffers:
610 if (rx_ring->next_to_use != i) {
611 rx_ring->next_to_use = i;
612 if (i-- == 0)
613 i = (rx_ring->count - 1);
614
e8e26350 615 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
9a799d71
AK		 616 }
617}
618
7c6e0a43
JB		 619static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
620{
621 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
622}
623
624static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
625{
626 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
627}
628
f8212f97
AD		 629static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
630{
631 return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
632 IXGBE_RXDADV_RSCCNT_MASK) >>
633 IXGBE_RXDADV_RSCCNT_SHIFT;
634}
635
636/**
637 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
638 * @skb: pointer to the last skb in the rsc queue
639 *
640 * This function changes a queue full of hw rsc buffers into a completed
641 * packet. It uses the ->prev pointers to find the first packet and then
642 * turns it into the frag list owner.
643 **/
644static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
645{
646 unsigned int frag_list_size = 0;
647
648 while (skb->prev) {
649 struct sk_buff *prev = skb->prev;
650 frag_list_size += skb->len;
651 skb->prev = NULL;
652 skb = prev;
653 }
654
655 skb_shinfo(skb)->frag_list = skb->next;
656 skb->next = NULL;
657 skb->len += frag_list_size;
658 skb->data_len += frag_list_size;
659 skb->truesize += frag_list_size;
660 return skb;
661}
662
78b6f4ce 663static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
b4617240
PW		 664 struct ixgbe_ring *rx_ring,
665 int *work_done, int work_to_do)
9a799d71 666{
78b6f4ce 667 struct ixgbe_adapter *adapter = q_vector->adapter;
9a799d71
AK		 668 struct pci_dev *pdev = adapter->pdev;
669 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
670 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
671 struct sk_buff *skb;
f8212f97 672 unsigned int i, rsc_count = 0;
7c6e0a43 673 u32 len, staterr;
177db6ff
MC		 674 u16 hdr_info;
675 bool cleaned = false;
9a799d71 676 int cleaned_count = 0;
d2f4fbe2 677 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
9a799d71
AK		 678
679 i = rx_ring->next_to_clean;
9a799d71
AK		 680 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
681 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
682 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 683
684 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 685 u32 upper_len = 0;
9a799d71
AK		 686 if (*work_done >= work_to_do)
687 break;
688 (*work_done)++;
689
690 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43
JB		 691 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
692 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
762f4c57 693 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
9a799d71
AK		 694 if (hdr_info & IXGBE_RXDADV_SPH)
695 adapter->rx_hdr_split++;
696 if (len > IXGBE_RX_HDR_SIZE)
697 len = IXGBE_RX_HDR_SIZE;
698 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 699 } else {
9a799d71 700 len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 701 }
9a799d71
AK		 702
703 cleaned = true;
704 skb = rx_buffer_info->skb;
705 prefetch(skb->data - NET_IP_ALIGN);
706 rx_buffer_info->skb = NULL;
707
708 if (len && !skb_shinfo(skb)->nr_frags) {
709 pci_unmap_single(pdev, rx_buffer_info->dma,
5ecc3614 710 rx_ring->rx_buf_len,
b4617240 711 PCI_DMA_FROMDEVICE);
9a799d71
AK		 712 skb_put(skb, len);
713 }
714
715 if (upper_len) {
716 pci_unmap_page(pdev, rx_buffer_info->page_dma,
762f4c57 717 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9a799d71
AK		 718 rx_buffer_info->page_dma = 0;
719 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
762f4c57
JB		 720 rx_buffer_info->page,
721 rx_buffer_info->page_offset,
722 upper_len);
723
724 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
725 (page_count(rx_buffer_info->page) != 1))
726 rx_buffer_info->page = NULL;
727 else
728 get_page(rx_buffer_info->page);
9a799d71
AK		 729
730 skb->len += upper_len;
731 skb->data_len += upper_len;
732 skb->truesize += upper_len;
733 }
734
735 i++;
736 if (i == rx_ring->count)
737 i = 0;
9a799d71
AK		 738
739 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
740 prefetch(next_rxd);
9a799d71 741 cleaned_count++;
f8212f97
AD		 742
743 if (adapter->flags & IXGBE_FLAG_RSC_CAPABLE)
744 rsc_count = ixgbe_get_rsc_count(rx_desc);
745
746 if (rsc_count) {
747 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
748 IXGBE_RXDADV_NEXTP_SHIFT;
749 next_buffer = &rx_ring->rx_buffer_info[nextp];
750 rx_ring->rsc_count += (rsc_count - 1);
751 } else {
752 next_buffer = &rx_ring->rx_buffer_info[i];
753 }
754
9a799d71 755 if (staterr & IXGBE_RXD_STAT_EOP) {
f8212f97
AD		 756 if (skb->prev)
757 skb = ixgbe_transform_rsc_queue(skb);
9a799d71
AK		 758 rx_ring->stats.packets++;
759 rx_ring->stats.bytes += skb->len;
760 } else {
f8212f97
AD		 761 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
762 rx_buffer_info->skb = next_buffer->skb;
763 rx_buffer_info->dma = next_buffer->dma;
764 next_buffer->skb = skb;
765 next_buffer->dma = 0;
766 } else {
767 skb->next = next_buffer->skb;
768 skb->next->prev = skb;
769 }
9a799d71
AK		 770 adapter->non_eop_descs++;
771 goto next_desc;
772 }
773
774 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
775 dev_kfree_skb_irq(skb);
776 goto next_desc;
777 }
778
779 ixgbe_rx_checksum(adapter, staterr, skb);
d2f4fbe2
AV		 780
781 /* probably a little skewed due to removing CRC */
782 total_rx_bytes += skb->len;
783 total_rx_packets++;
784
74ce8dd2 785 skb->protocol = eth_type_trans(skb, adapter->netdev);
fdaff1ce 786 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
9a799d71
AK		 787
788next_desc:
789 rx_desc->wb.upper.status_error = 0;
790
791 /* return some buffers to hardware, one at a time is too slow */
792 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
793 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
794 cleaned_count = 0;
795 }
796
797 /* use prefetched values */
798 rx_desc = next_rxd;
f8212f97 799 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 800
801 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 802 }
803
9a799d71
AK		 804 rx_ring->next_to_clean = i;
805 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
806
807 if (cleaned_count)
808 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
809
f494e8fa
AV		 810 rx_ring->total_packets += total_rx_packets;
811 rx_ring->total_bytes += total_rx_bytes;
812 adapter->net_stats.rx_bytes += total_rx_bytes;
813 adapter->net_stats.rx_packets += total_rx_packets;
814
9a799d71
AK		 815 return cleaned;
816}
817
021230d4 818static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 819/**
820 * ixgbe_configure_msix - Configure MSI-X hardware
821 * @adapter: board private structure
822 *
823 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
824 * interrupts.
825 **/
826static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
827{
021230d4
AV		 828 struct ixgbe_q_vector *q_vector;
829 int i, j, q_vectors, v_idx, r_idx;
830 u32 mask;
9a799d71 831
021230d4 832 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 833
4df10466
JB		 834 /*
835 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 836 * corresponding register.
837 */
838 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
7a921c93 839 q_vector = adapter->q_vector[v_idx];
021230d4
AV		 840 /* XXX for_each_bit(...) */
841 r_idx = find_first_bit(q_vector->rxr_idx,
b4617240 842 adapter->num_rx_queues);
021230d4
AV		 843
844 for (i = 0; i < q_vector->rxr_count; i++) {
845 j = adapter->rx_ring[r_idx].reg_idx;
e8e26350 846 ixgbe_set_ivar(adapter, 0, j, v_idx);
021230d4 847 r_idx = find_next_bit(q_vector->rxr_idx,
b4617240
PW		 848 adapter->num_rx_queues,
849 r_idx + 1);
021230d4
AV		 850 }
851 r_idx = find_first_bit(q_vector->txr_idx,
b4617240 852 adapter->num_tx_queues);
021230d4
AV		 853
854 for (i = 0; i < q_vector->txr_count; i++) {
855 j = adapter->tx_ring[r_idx].reg_idx;
e8e26350 856 ixgbe_set_ivar(adapter, 1, j, v_idx);
021230d4 857 r_idx = find_next_bit(q_vector->txr_idx,
b4617240
PW		 858 adapter->num_tx_queues,
859 r_idx + 1);
021230d4
AV		 860 }
861
30efa5a3 862 /* if this is a tx only vector halve the interrupt rate */
021230d4 863 if (q_vector->txr_count && !q_vector->rxr_count)
30efa5a3 864 q_vector->eitr = (adapter->eitr_param >> 1);
509ee935 865 else if (q_vector->rxr_count)
30efa5a3
JB		 866 /* rx only */
867 q_vector->eitr = adapter->eitr_param;
021230d4 868
509ee935 869 /*
4df10466 870 * since this is initial set up don't need to call
509ee935
JB		 871 * ixgbe_write_eitr helper
872 */
021230d4 873 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx),
b4617240 874 EITR_INTS_PER_SEC_TO_REG(q_vector->eitr));
9a799d71
AK		 875 }
876
e8e26350
PW		 877 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
878 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
879 v_idx);
880 else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
881 ixgbe_set_ivar(adapter, -1, 1, v_idx);
021230d4
AV		 882 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
883
41fb9248 884 /* set up to autoclear timer, and the vectors */
021230d4 885 mask = IXGBE_EIMS_ENABLE_MASK;
41fb9248 886 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 887 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 888}
889
f494e8fa
AV		 890enum latency_range {
891 lowest_latency = 0,
892 low_latency = 1,
893 bulk_latency = 2,
894 latency_invalid = 255
895};
896
897/**
898 * ixgbe_update_itr - update the dynamic ITR value based on statistics
899 * @adapter: pointer to adapter
900 * @eitr: eitr setting (ints per sec) to give last timeslice
901 * @itr_setting: current throttle rate in ints/second
902 * @packets: the number of packets during this measurement interval
903 * @bytes: the number of bytes during this measurement interval
904 *
905 * Stores a new ITR value based on packets and byte
906 * counts during the last interrupt. The advantage of per interrupt
907 * computation is faster updates and more accurate ITR for the current
908 * traffic pattern. Constants in this function were computed
909 * based on theoretical maximum wire speed and thresholds were set based
910 * on testing data as well as attempting to minimize response time
911 * while increasing bulk throughput.
912 * this functionality is controlled by the InterruptThrottleRate module
913 * parameter (see ixgbe_param.c)
914 **/
915static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
b4617240
PW		 916 u32 eitr, u8 itr_setting,
917 int packets, int bytes)
f494e8fa
AV		 918{
919 unsigned int retval = itr_setting;
920 u32 timepassed_us;
921 u64 bytes_perint;
922
923 if (packets == 0)
924 goto update_itr_done;
925
926
927 /* simple throttlerate management
928 * 0-20MB/s lowest (100000 ints/s)
929 * 20-100MB/s low (20000 ints/s)
930 * 100-1249MB/s bulk (8000 ints/s)
931 */
932 /* what was last interrupt timeslice? */
933 timepassed_us = 1000000/eitr;
934 bytes_perint = bytes / timepassed_us; /* bytes/usec */
935
936 switch (itr_setting) {
937 case lowest_latency:
938 if (bytes_perint > adapter->eitr_low)
939 retval = low_latency;
940 break;
941 case low_latency:
942 if (bytes_perint > adapter->eitr_high)
943 retval = bulk_latency;
944 else if (bytes_perint <= adapter->eitr_low)
945 retval = lowest_latency;
946 break;
947 case bulk_latency:
948 if (bytes_perint <= adapter->eitr_high)
949 retval = low_latency;
950 break;
951 }
952
953update_itr_done:
954 return retval;
955}
956
509ee935
JB		 957/**
958 * ixgbe_write_eitr - write EITR register in hardware specific way
959 * @adapter: pointer to adapter struct
960 * @v_idx: vector index into q_vector array
961 * @itr_reg: new value to be written in *register* format, not ints/s
962 *
963 * This function is made to be called by ethtool and by the driver
964 * when it needs to update EITR registers at runtime. Hardware
965 * specific quirks/differences are taken care of here.
966 */
967void ixgbe_write_eitr(struct ixgbe_adapter *adapter, int v_idx, u32 itr_reg)
968{
969 struct ixgbe_hw *hw = &adapter->hw;
970 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
971 /* must write high and low 16 bits to reset counter */
972 itr_reg |= (itr_reg << 16);
973 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
974 /*
975 * set the WDIS bit to not clear the timer bits and cause an
976 * immediate assertion of the interrupt
977 */
978 itr_reg |= IXGBE_EITR_CNT_WDIS;
979 }
980 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
981}
982
f494e8fa
AV		 983static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
984{
985 struct ixgbe_adapter *adapter = q_vector->adapter;
f494e8fa
AV		 986 u32 new_itr;
987 u8 current_itr, ret_itr;
7a921c93 988 int i, r_idx, v_idx = q_vector->v_idx;
f494e8fa
AV		 989 struct ixgbe_ring *rx_ring, *tx_ring;
990
991 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
992 for (i = 0; i < q_vector->txr_count; i++) {
993 tx_ring = &(adapter->tx_ring[r_idx]);
994 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 995 q_vector->tx_itr,
996 tx_ring->total_packets,
997 tx_ring->total_bytes);
f494e8fa
AV		 998 /* if the result for this queue would decrease interrupt
999 * rate for this vector then use that result */
30efa5a3 1000 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
b4617240 1001 q_vector->tx_itr - 1 : ret_itr);
f494e8fa 1002 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1003 r_idx + 1);
f494e8fa
AV		 1004 }
1005
1006 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1007 for (i = 0; i < q_vector->rxr_count; i++) {
1008 rx_ring = &(adapter->rx_ring[r_idx]);
1009 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 1010 q_vector->rx_itr,
1011 rx_ring->total_packets,
1012 rx_ring->total_bytes);
f494e8fa
AV		 1013 /* if the result for this queue would decrease interrupt
1014 * rate for this vector then use that result */
30efa5a3 1015 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
b4617240 1016 q_vector->rx_itr - 1 : ret_itr);
f494e8fa 1017 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
b4617240 1018 r_idx + 1);
f494e8fa
AV		 1019 }
1020
30efa5a3 1021 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1022
1023 switch (current_itr) {
1024 /* counts and packets in update_itr are dependent on these numbers */
1025 case lowest_latency:
1026 new_itr = 100000;
1027 break;
1028 case low_latency:
1029 new_itr = 20000; /* aka hwitr = ~200 */
1030 break;
1031 case bulk_latency:
1032 default:
1033 new_itr = 8000;
1034 break;
1035 }
1036
1037 if (new_itr != q_vector->eitr) {
1038 u32 itr_reg;
509ee935
JB		 1039
1040 /* save the algorithm value here, not the smoothed one */
1041 q_vector->eitr = new_itr;
f494e8fa
AV		 1042 /* do an exponential smoothing */
1043 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
f494e8fa 1044 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
509ee935 1045 ixgbe_write_eitr(adapter, v_idx, itr_reg);
f494e8fa
AV		 1046 }
1047
1048 return;
1049}
1050
0befdb3e
JB		 1051static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1052{
1053 struct ixgbe_hw *hw = &adapter->hw;
1054
1055 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1056 (eicr & IXGBE_EICR_GPI_SDP1)) {
1057 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1058 /* write to clear the interrupt */
1059 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1060 }
1061}
cf8280ee 1062
e8e26350
PW		 1063static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1064{
1065 struct ixgbe_hw *hw = &adapter->hw;
1066
1067 if (eicr & IXGBE_EICR_GPI_SDP1) {
1068 /* Clear the interrupt */
1069 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1070 schedule_work(&adapter->multispeed_fiber_task);
1071 } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1072 /* Clear the interrupt */
1073 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1074 schedule_work(&adapter->sfp_config_module_task);
1075 } else {
1076 /* Interrupt isn't for us... */
1077 return;
1078 }
1079}
1080
cf8280ee
JB		 1081static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1082{
1083 struct ixgbe_hw *hw = &adapter->hw;
1084
1085 adapter->lsc_int++;
1086 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1087 adapter->link_check_timeout = jiffies;
1088 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1089 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1090 schedule_work(&adapter->watchdog_task);
1091 }
1092}
1093
9a799d71
AK		 1094static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1095{
1096 struct net_device *netdev = data;
1097 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1098 struct ixgbe_hw *hw = &adapter->hw;
54037505
DS		 1099 u32 eicr;
1100
1101 /*
1102 * Workaround for Silicon errata. Use clear-by-write instead
1103 * of clear-by-read. Reading with EICS will return the
1104 * interrupt causes without clearing, which later be done
1105 * with the write to EICR.
1106 */
1107 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1108 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
9a799d71 1109
cf8280ee
JB		 1110 if (eicr & IXGBE_EICR_LSC)
1111 ixgbe_check_lsc(adapter);
d4f80882 1112
e8e26350
PW		 1113 if (hw->mac.type == ixgbe_mac_82598EB)
1114 ixgbe_check_fan_failure(adapter, eicr);
0befdb3e 1115
e8e26350
PW		 1116 if (hw->mac.type == ixgbe_mac_82599EB)
1117 ixgbe_check_sfp_event(adapter, eicr);
d4f80882
AV		 1118 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1119 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 1120
1121 return IRQ_HANDLED;
1122}
1123
1124static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1125{
021230d4
AV		 1126 struct ixgbe_q_vector *q_vector = data;
1127 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1128 struct ixgbe_ring *tx_ring;
021230d4
AV		 1129 int i, r_idx;
1130
1131 if (!q_vector->txr_count)
1132 return IRQ_HANDLED;
1133
1134 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1135 for (i = 0; i < q_vector->txr_count; i++) {
3a581073 1136 tx_ring = &(adapter->tx_ring[r_idx]);
5dd2d332 1137#ifdef CONFIG_IXGBE_DCA
bd0362dd 1138 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1139 ixgbe_update_tx_dca(adapter, tx_ring);
bd0362dd 1140#endif
3a581073
JB		 1141 tx_ring->total_bytes = 0;
1142 tx_ring->total_packets = 0;
1143 ixgbe_clean_tx_irq(adapter, tx_ring);
021230d4 1144 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1145 r_idx + 1);
021230d4 1146 }
9a799d71 1147
9a799d71
AK		 1148 return IRQ_HANDLED;
1149}
1150
021230d4
AV		 1151/**
1152 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1153 * @irq: unused
1154 * @data: pointer to our q_vector struct for this interrupt vector
1155 **/
9a799d71
AK		 1156static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1157{
021230d4
AV		 1158 struct ixgbe_q_vector *q_vector = data;
1159 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1160 struct ixgbe_ring *rx_ring;
021230d4 1161 int r_idx;
30efa5a3 1162 int i;
021230d4
AV		 1163
1164 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
30efa5a3
JB		 1165 for (i = 0; i < q_vector->rxr_count; i++) {
1166 rx_ring = &(adapter->rx_ring[r_idx]);
1167 rx_ring->total_bytes = 0;
1168 rx_ring->total_packets = 0;
1169 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1170 r_idx + 1);
1171 }
1172
021230d4
AV		 1173 if (!q_vector->rxr_count)
1174 return IRQ_HANDLED;
1175
30efa5a3 1176 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
3a581073 1177 rx_ring = &(adapter->rx_ring[r_idx]);
021230d4 1178 /* disable interrupts on this vector only */
835462fc
NS		 1179 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1180 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, rx_ring->v_idx);
1181 else if (rx_ring->v_idx & 0xFFFFFFFF)
1182 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), rx_ring->v_idx);
1183 else
1184 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1),
1185 (rx_ring->v_idx >> 32));
288379f0 1186 napi_schedule(&q_vector->napi);
021230d4
AV		 1187
1188 return IRQ_HANDLED;
1189}
1190
1191static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1192{
1193 ixgbe_msix_clean_rx(irq, data);
1194 ixgbe_msix_clean_tx(irq, data);
9a799d71 1195
9a799d71
AK		 1196 return IRQ_HANDLED;
1197}
1198
835462fc
NS		 1199static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1200 u64 qmask)
1201{
1202 u32 mask;
1203
1204 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1205 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1206 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1207 } else {
1208 mask = (qmask & 0xFFFFFFFF);
1209 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1210 mask = (qmask >> 32);
1211 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1212 }
1213 /* skip the flush */
1214}
1215
021230d4
AV		 1216/**
1217 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1218 * @napi: napi struct with our devices info in it
1219 * @budget: amount of work driver is allowed to do this pass, in packets
1220 *
f0848276
JB		 1221 * This function is optimized for cleaning one queue only on a single
1222 * q_vector!!!
021230d4 1223 **/
9a799d71
AK		 1224static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1225{
021230d4 1226 struct ixgbe_q_vector *q_vector =
b4617240 1227 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 1228 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 1229 struct ixgbe_ring *rx_ring = NULL;
9a799d71 1230 int work_done = 0;
021230d4 1231 long r_idx;
9a799d71 1232
021230d4 1233 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
3a581073 1234 rx_ring = &(adapter->rx_ring[r_idx]);
5dd2d332 1235#ifdef CONFIG_IXGBE_DCA
bd0362dd 1236 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1237 ixgbe_update_rx_dca(adapter, rx_ring);
bd0362dd 1238#endif
9a799d71 1239
78b6f4ce 1240 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
9a799d71 1241
021230d4
AV		 1242 /* If all Rx work done, exit the polling mode */
1243 if (work_done < budget) {
288379f0 1244 napi_complete(napi);
509ee935 1245 if (adapter->itr_setting & 1)
f494e8fa 1246 ixgbe_set_itr_msix(q_vector);
9a799d71 1247 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 1248 ixgbe_irq_enable_queues(adapter, rx_ring->v_idx);
9a799d71
AK		 1249 }
1250
1251 return work_done;
1252}
1253
f0848276
JB		 1254/**
1255 * ixgbe_clean_rxonly_many - msix (aka one shot) rx clean routine
1256 * @napi: napi struct with our devices info in it
1257 * @budget: amount of work driver is allowed to do this pass, in packets
1258 *
1259 * This function will clean more than one rx queue associated with a
1260 * q_vector.
1261 **/
1262static int ixgbe_clean_rxonly_many(struct napi_struct *napi, int budget)
1263{
1264 struct ixgbe_q_vector *q_vector =
1265 container_of(napi, struct ixgbe_q_vector, napi);
1266 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276
JB		 1267 struct ixgbe_ring *rx_ring = NULL;
1268 int work_done = 0, i;
1269 long r_idx;
835462fc 1270 u64 enable_mask = 0;
f0848276
JB		 1271
1272 /* attempt to distribute budget to each queue fairly, but don't allow
1273 * the budget to go below 1 because we'll exit polling */
1274 budget /= (q_vector->rxr_count ?: 1);
1275 budget = max(budget, 1);
1276 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1277 for (i = 0; i < q_vector->rxr_count; i++) {
1278 rx_ring = &(adapter->rx_ring[r_idx]);
5dd2d332 1279#ifdef CONFIG_IXGBE_DCA
f0848276
JB		 1280 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1281 ixgbe_update_rx_dca(adapter, rx_ring);
1282#endif
78b6f4ce 1283 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
f0848276
JB		 1284 enable_mask |= rx_ring->v_idx;
1285 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1286 r_idx + 1);
1287 }
1288
1289 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1290 rx_ring = &(adapter->rx_ring[r_idx]);
1291 /* If all Rx work done, exit the polling mode */
7f821875 1292 if (work_done < budget) {
288379f0 1293 napi_complete(napi);
509ee935 1294 if (adapter->itr_setting & 1)
f0848276
JB		 1295 ixgbe_set_itr_msix(q_vector);
1296 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 1297 ixgbe_irq_enable_queues(adapter, enable_mask);
f0848276
JB		 1298 return 0;
1299 }
1300
1301 return work_done;
1302}
021230d4 1303static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
b4617240 1304 int r_idx)
021230d4 1305{
7a921c93
AD		 1306 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1307
1308 set_bit(r_idx, q_vector->rxr_idx);
1309 q_vector->rxr_count++;
021230d4
AV		 1310 a->rx_ring[r_idx].v_idx = 1 << v_idx;
1311}
1312
1313static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
7a921c93 1314 int t_idx)
021230d4 1315{
7a921c93
AD		 1316 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1317
1318 set_bit(t_idx, q_vector->txr_idx);
1319 q_vector->txr_count++;
1320 a->tx_ring[t_idx].v_idx = 1 << v_idx;
021230d4
AV		 1321}
1322
9a799d71 1323/**
021230d4
AV		 1324 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1325 * @adapter: board private structure to initialize
1326 * @vectors: allotted vector count for descriptor rings
9a799d71 1327 *
021230d4
AV		 1328 * This function maps descriptor rings to the queue-specific vectors
1329 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1330 * one vector per ring/queue, but on a constrained vector budget, we
1331 * group the rings as "efficiently" as possible. You would add new
1332 * mapping configurations in here.
9a799d71 1333 **/
021230d4 1334static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
b4617240 1335 int vectors)
021230d4
AV		 1336{
1337 int v_start = 0;
1338 int rxr_idx = 0, txr_idx = 0;
1339 int rxr_remaining = adapter->num_rx_queues;
1340 int txr_remaining = adapter->num_tx_queues;
1341 int i, j;
1342 int rqpv, tqpv;
1343 int err = 0;
1344
1345 /* No mapping required if MSI-X is disabled. */
1346 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1347 goto out;
9a799d71 1348
021230d4
AV		 1349 /*
1350 * The ideal configuration...
1351 * We have enough vectors to map one per queue.
1352 */
1353 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1354 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1355 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 1356
021230d4
AV		 1357 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1358 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 1359
9a799d71 1360 goto out;
021230d4 1361 }
9a799d71 1362
021230d4
AV		 1363 /*
1364 * If we don't have enough vectors for a 1-to-1
1365 * mapping, we'll have to group them so there are
1366 * multiple queues per vector.
1367 */
1368 /* Re-adjusting *qpv takes care of the remainder. */
1369 for (i = v_start; i < vectors; i++) {
1370 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1371 for (j = 0; j < rqpv; j++) {
1372 map_vector_to_rxq(adapter, i, rxr_idx);
1373 rxr_idx++;
1374 rxr_remaining--;
1375 }
1376 }
1377 for (i = v_start; i < vectors; i++) {
1378 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1379 for (j = 0; j < tqpv; j++) {
1380 map_vector_to_txq(adapter, i, txr_idx);
1381 txr_idx++;
1382 txr_remaining--;
9a799d71 1383 }
9a799d71
AK		 1384 }
1385
021230d4
AV		 1386out:
1387 return err;
1388}
1389
1390/**
1391 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1392 * @adapter: board private structure
1393 *
1394 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1395 * interrupts from the kernel.
1396 **/
1397static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1398{
1399 struct net_device *netdev = adapter->netdev;
1400 irqreturn_t (*handler)(int, void *);
1401 int i, vector, q_vectors, err;
cb13fc20 1402 int ri=0, ti=0;
021230d4
AV		 1403
1404 /* Decrement for Other and TCP Timer vectors */
1405 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1406
1407 /* Map the Tx/Rx rings to the vectors we were allotted. */
1408 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1409 if (err)
1410 goto out;
1411
1412#define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
b4617240
PW		 1413 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1414 &ixgbe_msix_clean_many)
021230d4 1415 for (vector = 0; vector < q_vectors; vector++) {
7a921c93 1416 handler = SET_HANDLER(adapter->q_vector[vector]);
cb13fc20
RO		 1417
1418 if(handler == &ixgbe_msix_clean_rx) {
1419 sprintf(adapter->name[vector], "%s-%s-%d",
1420 netdev->name, "rx", ri++);
1421 }
1422 else if(handler == &ixgbe_msix_clean_tx) {
1423 sprintf(adapter->name[vector], "%s-%s-%d",
1424 netdev->name, "tx", ti++);
1425 }
1426 else
1427 sprintf(adapter->name[vector], "%s-%s-%d",
1428 netdev->name, "TxRx", vector);
1429
021230d4 1430 err = request_irq(adapter->msix_entries[vector].vector,
b4617240 1431 handler, 0, adapter->name[vector],
7a921c93 1432 adapter->q_vector[vector]);
9a799d71
AK		 1433 if (err) {
1434 DPRINTK(PROBE, ERR,
b4617240
PW		 1435 "request_irq failed for MSIX interrupt "
1436 "Error: %d\n", err);
021230d4 1437 goto free_queue_irqs;
9a799d71 1438 }
9a799d71
AK		 1439 }
1440
021230d4
AV		 1441 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1442 err = request_irq(adapter->msix_entries[vector].vector,
b4617240 1443 &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
9a799d71
AK		 1444 if (err) {
1445 DPRINTK(PROBE, ERR,
1446 "request_irq for msix_lsc failed: %d\n", err);
021230d4 1447 goto free_queue_irqs;
9a799d71
AK		 1448 }
1449
9a799d71
AK		 1450 return 0;
1451
021230d4
AV		 1452free_queue_irqs:
1453 for (i = vector - 1; i >= 0; i--)
1454 free_irq(adapter->msix_entries[--vector].vector,
7a921c93 1455 adapter->q_vector[i]);
021230d4
AV		 1456 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1457 pci_disable_msix(adapter->pdev);
9a799d71
AK		 1458 kfree(adapter->msix_entries);
1459 adapter->msix_entries = NULL;
021230d4 1460out:
9a799d71
AK		 1461 return err;
1462}
1463
f494e8fa
AV		 1464static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1465{
7a921c93 1466 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
f494e8fa
AV		 1467 u8 current_itr;
1468 u32 new_itr = q_vector->eitr;
1469 struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1470 struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1471
30efa5a3 1472 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1473 q_vector->tx_itr,
1474 tx_ring->total_packets,
1475 tx_ring->total_bytes);
30efa5a3 1476 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1477 q_vector->rx_itr,
1478 rx_ring->total_packets,
1479 rx_ring->total_bytes);
f494e8fa 1480
30efa5a3 1481 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1482
1483 switch (current_itr) {
1484 /* counts and packets in update_itr are dependent on these numbers */
1485 case lowest_latency:
1486 new_itr = 100000;
1487 break;
1488 case low_latency:
1489 new_itr = 20000; /* aka hwitr = ~200 */
1490 break;
1491 case bulk_latency:
1492 new_itr = 8000;
1493 break;
1494 default:
1495 break;
1496 }
1497
1498 if (new_itr != q_vector->eitr) {
1499 u32 itr_reg;
509ee935
JB		 1500
1501 /* save the algorithm value here, not the smoothed one */
1502 q_vector->eitr = new_itr;
f494e8fa
AV		 1503 /* do an exponential smoothing */
1504 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
f494e8fa 1505 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
509ee935 1506 ixgbe_write_eitr(adapter, 0, itr_reg);
f494e8fa
AV		 1507 }
1508
1509 return;
1510}
1511
79aefa45
AD		 1512/**
1513 * ixgbe_irq_enable - Enable default interrupt generation settings
1514 * @adapter: board private structure
1515 **/
1516static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1517{
1518 u32 mask;
835462fc
NS		 1519
1520 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
6ab33d51
DM		 1521 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1522 mask |= IXGBE_EIMS_GPI_SDP1;
e8e26350 1523 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2a41ff81 1524 mask |= IXGBE_EIMS_ECC;
e8e26350
PW		 1525 mask |= IXGBE_EIMS_GPI_SDP1;
1526 mask |= IXGBE_EIMS_GPI_SDP2;
1527 }
1528
79aefa45 1529 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
835462fc 1530 ixgbe_irq_enable_queues(adapter, ~0);
79aefa45
AD		 1531 IXGBE_WRITE_FLUSH(&adapter->hw);
1532}
021230d4 1533
9a799d71 1534/**
021230d4 1535 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 1536 * @irq: interrupt number
1537 * @data: pointer to a network interface device structure
9a799d71
AK		 1538 **/
1539static irqreturn_t ixgbe_intr(int irq, void *data)
1540{
1541 struct net_device *netdev = data;
1542 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1543 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 1544 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 1545 u32 eicr;
1546
54037505
DS		 1547 /*
1548 * Workaround for silicon errata. Mask the interrupts
1549 * before the read of EICR.
1550 */
1551 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1552
021230d4
AV		 1553 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1554 * therefore no explict interrupt disable is necessary */
1555 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e
JB		 1556 if (!eicr) {
1557 /* shared interrupt alert!
1558 * make sure interrupts are enabled because the read will
1559 * have disabled interrupts due to EIAM */
1560 ixgbe_irq_enable(adapter);
9a799d71 1561 return IRQ_NONE; /* Not our interrupt */
f47cf66e 1562 }
9a799d71 1563
cf8280ee
JB		 1564 if (eicr & IXGBE_EICR_LSC)
1565 ixgbe_check_lsc(adapter);
021230d4 1566
e8e26350
PW		 1567 if (hw->mac.type == ixgbe_mac_82599EB)
1568 ixgbe_check_sfp_event(adapter, eicr);
1569
0befdb3e
JB		 1570 ixgbe_check_fan_failure(adapter, eicr);
1571
7a921c93 1572 if (napi_schedule_prep(&(q_vector->napi))) {
f494e8fa
AV		 1573 adapter->tx_ring[0].total_packets = 0;
1574 adapter->tx_ring[0].total_bytes = 0;
1575 adapter->rx_ring[0].total_packets = 0;
1576 adapter->rx_ring[0].total_bytes = 0;
021230d4 1577 /* would disable interrupts here but EIAM disabled it */
7a921c93 1578 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 1579 }
1580
1581 return IRQ_HANDLED;
1582}
1583
021230d4
AV		 1584static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1585{
1586 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1587
1588 for (i = 0; i < q_vectors; i++) {
7a921c93 1589 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
021230d4
AV		 1590 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1591 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1592 q_vector->rxr_count = 0;
1593 q_vector->txr_count = 0;
1594 }
1595}
1596
9a799d71
AK		 1597/**
1598 * ixgbe_request_irq - initialize interrupts
1599 * @adapter: board private structure
1600 *
1601 * Attempts to configure interrupts using the best available
1602 * capabilities of the hardware and kernel.
1603 **/
021230d4 1604static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 1605{
1606 struct net_device *netdev = adapter->netdev;
021230d4 1607 int err;
9a799d71 1608
021230d4
AV		 1609 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1610 err = ixgbe_request_msix_irqs(adapter);
1611 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1612 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
b4617240 1613 netdev->name, netdev);
021230d4
AV		 1614 } else {
1615 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
b4617240 1616 netdev->name, netdev);
9a799d71
AK		 1617 }
1618
9a799d71
AK		 1619 if (err)
1620 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1621
9a799d71
AK		 1622 return err;
1623}
1624
1625static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1626{
1627 struct net_device *netdev = adapter->netdev;
1628
1629 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 1630 int i, q_vectors;
9a799d71 1631
021230d4
AV		 1632 q_vectors = adapter->num_msix_vectors;
1633
1634 i = q_vectors - 1;
9a799d71 1635 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 1636
021230d4
AV		 1637 i--;
1638 for (; i >= 0; i--) {
1639 free_irq(adapter->msix_entries[i].vector,
7a921c93 1640 adapter->q_vector[i]);
021230d4
AV		 1641 }
1642
1643 ixgbe_reset_q_vectors(adapter);
1644 } else {
1645 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 1646 }
1647}
1648
22d5a71b
JB		 1649/**
1650 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1651 * @adapter: board private structure
1652 **/
1653static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1654{
835462fc
NS		 1655 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1656 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1657 } else {
1658 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
1659 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 1660 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
22d5a71b
JB		 1661 }
1662 IXGBE_WRITE_FLUSH(&adapter->hw);
1663 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1664 int i;
1665 for (i = 0; i < adapter->num_msix_vectors; i++)
1666 synchronize_irq(adapter->msix_entries[i].vector);
1667 } else {
1668 synchronize_irq(adapter->pdev->irq);
1669 }
1670}
1671
9a799d71
AK		 1672/**
1673 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1674 *
1675 **/
1676static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1677{
9a799d71
AK		 1678 struct ixgbe_hw *hw = &adapter->hw;
1679
021230d4 1680 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
30efa5a3 1681 EITR_INTS_PER_SEC_TO_REG(adapter->eitr_param));
9a799d71 1682
e8e26350
PW		 1683 ixgbe_set_ivar(adapter, 0, 0, 0);
1684 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4
AV		 1685
1686 map_vector_to_rxq(adapter, 0, 0);
1687 map_vector_to_txq(adapter, 0, 0);
1688
1689 DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 1690}
1691
1692/**
3a581073 1693 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 1694 * @adapter: board private structure
1695 *
1696 * Configure the Tx unit of the MAC after a reset.
1697 **/
1698static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1699{
12207e49 1700 u64 tdba;
9a799d71 1701 struct ixgbe_hw *hw = &adapter->hw;
021230d4 1702 u32 i, j, tdlen, txctrl;
9a799d71
AK		 1703
1704 /* Setup the HW Tx Head and Tail descriptor pointers */
1705 for (i = 0; i < adapter->num_tx_queues; i++) {
e01c31a5
JB		 1706 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1707 j = ring->reg_idx;
1708 tdba = ring->dma;
1709 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
021230d4 1710 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
284901a9 1711 (tdba & DMA_BIT_MASK(32)));
021230d4
AV		 1712 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1713 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1714 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1715 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1716 adapter->tx_ring[i].head = IXGBE_TDH(j);
1717 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1718 /* Disable Tx Head Writeback RO bit, since this hoses
1719 * bookkeeping if things aren't delivered in order.
1720 */
e01c31a5 1721 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
021230d4 1722 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
e01c31a5 1723 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
9a799d71 1724 }
e8e26350
PW		 1725 if (hw->mac.type == ixgbe_mac_82599EB) {
1726 /* We enable 8 traffic classes, DCB only */
1727 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
1728 IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA |
1729 IXGBE_MTQC_8TC_8TQ));
1730 }
9a799d71
AK		 1731}
1732
e8e26350 1733#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c
JB		 1734
1735static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, int index)
1736{
1737 struct ixgbe_ring *rx_ring;
1738 u32 srrctl;
e8e26350 1739 int queue0 = 0;
3be1adfb
AD		 1740 unsigned long mask;
1741
e8e26350 1742 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
163de42e
AD		 1743 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
1744 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
1745 if (dcb_i == 8)
1746 queue0 = index >> 4;
1747 else if (dcb_i == 4)
1748 queue0 = index >> 5;
1749 else
1750 dev_err(&adapter->pdev->dev, "Invalid DCB "
1751 "configuration\n");
1752 } else {
1753 queue0 = index;
1754 }
cc41ac7c 1755 } else {
3be1adfb
AD		 1756 mask = (unsigned long) adapter->ring_feature[RING_F_RSS].mask;
1757 queue0 = index & mask;
1758 index = index & mask;
cc41ac7c 1759 }
3be1adfb 1760
cc41ac7c
JB		 1761 rx_ring = &adapter->rx_ring[queue0];
1762
1763 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
1764
1765 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1766 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1767
afafd5b0
AD		 1768 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1769 IXGBE_SRRCTL_BSIZEHDR_MASK;
1770
cc41ac7c 1771 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
afafd5b0
AD		 1772#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
1773 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1774#else
1775 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1776#endif
cc41ac7c 1777 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 1778 } else {
afafd5b0
AD		 1779 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
1780 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 1781 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 1782 }
e8e26350 1783
cc41ac7c
JB		 1784 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
1785}
9a799d71 1786
9a799d71 1787/**
3a581073 1788 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
9a799d71
AK		 1789 * @adapter: board private structure
1790 *
1791 * Configure the Rx unit of the MAC after a reset.
1792 **/
1793static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
1794{
1795 u64 rdba;
1796 struct ixgbe_hw *hw = &adapter->hw;
1797 struct net_device *netdev = adapter->netdev;
1798 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 1799 int i, j;
9a799d71 1800 u32 rdlen, rxctrl, rxcsum;
7c6e0a43
JB		 1801 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
1802 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
1803 0x6A3E67EA, 0x14364D17, 0x3BED200D};
9a799d71 1804 u32 fctrl, hlreg0;
509ee935 1805 u32 reta = 0, mrqc = 0;
cc41ac7c 1806 u32 rdrxctl;
f8212f97 1807 u32 rscctrl;
7c6e0a43 1808 int rx_buf_len;
9a799d71
AK		 1809
1810 /* Decide whether to use packet split mode or not */
762f4c57 1811 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
9a799d71
AK		 1812
1813 /* Set the RX buffer length according to the mode */
1814 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 1815 rx_buf_len = IXGBE_RX_HDR_SIZE;
e8e26350
PW		 1816 if (hw->mac.type == ixgbe_mac_82599EB) {
1817 /* PSRTYPE must be initialized in 82599 */
1818 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
1819 IXGBE_PSRTYPE_UDPHDR |
1820 IXGBE_PSRTYPE_IPV4HDR |
1821 IXGBE_PSRTYPE_IPV6HDR;
1822 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype);
1823 }
9a799d71 1824 } else {
f8212f97
AD		 1825 if (!(adapter->flags & IXGBE_FLAG_RSC_ENABLED) &&
1826 (netdev->mtu <= ETH_DATA_LEN))
7c6e0a43 1827 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 1828 else
7c6e0a43 1829 rx_buf_len = ALIGN(max_frame, 1024);
9a799d71
AK		 1830 }
1831
1832 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1833 fctrl |= IXGBE_FCTRL_BAM;
021230d4 1834 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
e8e26350 1835 fctrl |= IXGBE_FCTRL_PMCF;
9a799d71
AK		 1836 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
1837
1838 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1839 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1840 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
1841 else
1842 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
1843 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1844
9a799d71
AK		 1845 rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
1846 /* disable receives while setting up the descriptors */
1847 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1848 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
1849
1850 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1851 * the Base and Length of the Rx Descriptor Ring */
1852 for (i = 0; i < adapter->num_rx_queues; i++) {
1853 rdba = adapter->rx_ring[i].dma;
7c6e0a43 1854 j = adapter->rx_ring[i].reg_idx;
284901a9 1855 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
7c6e0a43
JB		 1856 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
1857 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
1858 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
1859 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
1860 adapter->rx_ring[i].head = IXGBE_RDH(j);
1861 adapter->rx_ring[i].tail = IXGBE_RDT(j);
1862 adapter->rx_ring[i].rx_buf_len = rx_buf_len;
cc41ac7c
JB		 1863
1864 ixgbe_configure_srrctl(adapter, j);
9a799d71
AK		 1865 }
1866
e8e26350
PW		 1867 if (hw->mac.type == ixgbe_mac_82598EB) {
1868 /*
1869 * For VMDq support of different descriptor types or
1870 * buffer sizes through the use of multiple SRRCTL
1871 * registers, RDRXCTL.MVMEN must be set to 1
1872 *
1873 * also, the manual doesn't mention it clearly but DCA hints
1874 * will only use queue 0's tags unless this bit is set. Side
1875 * effects of setting this bit are only that SRRCTL must be
1876 * fully programmed [0..15]
1877 */
2a41ff81
JB		 1878 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1879 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
1880 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2f90b865 1881 }
177db6ff 1882
e8e26350
PW		 1883 /* Program MRQC for the distribution of queues */
1884 if (hw->mac.type == ixgbe_mac_82599EB) {
1885 int mask = adapter->flags & (
1886 IXGBE_FLAG_RSS_ENABLED
1887 | IXGBE_FLAG_DCB_ENABLED
1888 );
1889
1890 switch (mask) {
1891 case (IXGBE_FLAG_RSS_ENABLED):
1892 mrqc = IXGBE_MRQC_RSSEN;
1893 break;
1894 case (IXGBE_FLAG_DCB_ENABLED):
1895 mrqc = IXGBE_MRQC_RT8TCEN;
1896 break;
1897 default:
1898 break;
1899 }
1900 }
021230d4 1901 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
9a799d71 1902 /* Fill out redirection table */
021230d4
AV		 1903 for (i = 0, j = 0; i < 128; i++, j++) {
1904 if (j == adapter->ring_feature[RING_F_RSS].indices)
1905 j = 0;
1906 /* reta = 4-byte sliding window of
1907 * 0x00..(indices-1)(indices-1)00..etc. */
1908 reta = (reta << 8) | (j * 0x11);
1909 if ((i & 3) == 3)
1910 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
9a799d71
AK		 1911 }
1912
1913 /* Fill out hash function seeds */
1914 for (i = 0; i < 10; i++)
7c6e0a43 1915 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
9a799d71 1916
2a41ff81
JB		 1917 if (hw->mac.type == ixgbe_mac_82598EB)
1918 mrqc |= IXGBE_MRQC_RSSEN;
9a799d71 1919 /* Perform hash on these packet types */
2a41ff81
JB		 1920 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
1921 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
1922 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
1923 | IXGBE_MRQC_RSS_FIELD_IPV6
1924 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
1925 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
021230d4 1926 }
2a41ff81 1927 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
9a799d71 1928
021230d4
AV		 1929 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
1930
1931 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
1932 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
1933 /* Disable indicating checksum in descriptor, enables
1934 * RSS hash */
9a799d71 1935 rxcsum |= IXGBE_RXCSUM_PCSD;
9a799d71 1936 }
021230d4
AV		 1937 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
1938 /* Enable IPv4 payload checksum for UDP fragments
1939 * if PCSD is not set */
1940 rxcsum |= IXGBE_RXCSUM_IPPCSE;
1941 }
1942
1943 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
e8e26350
PW		 1944
1945 if (hw->mac.type == ixgbe_mac_82599EB) {
1946 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1947 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
f8212f97 1948 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
e8e26350
PW		 1949 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
1950 }
f8212f97
AD		 1951
1952 if (adapter->flags & IXGBE_FLAG_RSC_ENABLED) {
1953 /* Enable 82599 HW-RSC */
1954 for (i = 0; i < adapter->num_rx_queues; i++) {
1955 j = adapter->rx_ring[i].reg_idx;
1956 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
1957 rscctrl |= IXGBE_RSCCTL_RSCEN;
1958 /*
1959 * if packet split is enabled we can only support up
1960 * to max frags + 1 descriptors.
1961 */
1962 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
1963#if (MAX_SKB_FRAGS < 3)
1964 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
1965#elif (MAX_SKB_FRAGS < 7)
1966 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
1967#elif (MAX_SKB_FRAGS < 15)
1968 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
1969#else
1970 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
1971#endif
1972 else
1973 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
1974 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
1975 }
1976 /* Disable RSC for ACK packets */
1977 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
1978 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
1979 }
9a799d71
AK		 1980}
1981
068c89b0
DS		 1982static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
1983{
1984 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1985 struct ixgbe_hw *hw = &adapter->hw;
1986
1987 /* add VID to filter table */
1988 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
1989}
1990
1991static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
1992{
1993 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1994 struct ixgbe_hw *hw = &adapter->hw;
1995
1996 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1997 ixgbe_irq_disable(adapter);
1998
1999 vlan_group_set_device(adapter->vlgrp, vid, NULL);
2000
2001 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2002 ixgbe_irq_enable(adapter);
2003
2004 /* remove VID from filter table */
2005 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
2006}
2007
9a799d71 2008static void ixgbe_vlan_rx_register(struct net_device *netdev,
b4617240 2009 struct vlan_group *grp)
9a799d71
AK		 2010{
2011 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2012 u32 ctrl;
e8e26350 2013 int i, j;
9a799d71 2014
d4f80882
AV		 2015 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2016 ixgbe_irq_disable(adapter);
9a799d71
AK		 2017 adapter->vlgrp = grp;
2018
2f90b865
AD		 2019 /*
2020 * For a DCB driver, always enable VLAN tag stripping so we can
2021 * still receive traffic from a DCB-enabled host even if we're
2022 * not in DCB mode.
2023 */
2024 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
e8e26350
PW		 2025 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2026 ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2027 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2028 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2029 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2030 ctrl |= IXGBE_VLNCTRL_VFE;
9a799d71
AK		 2031 /* enable VLAN tag insert/strip */
2032 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
9a799d71
AK		 2033 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2034 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
e8e26350
PW		 2035 for (i = 0; i < adapter->num_rx_queues; i++) {
2036 j = adapter->rx_ring[i].reg_idx;
2037 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
2038 ctrl |= IXGBE_RXDCTL_VME;
2039 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
2040 }
9a799d71 2041 }
e8e26350 2042 ixgbe_vlan_rx_add_vid(netdev, 0);
9a799d71 2043
d4f80882
AV		 2044 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2045 ixgbe_irq_enable(adapter);
9a799d71
AK		 2046}
2047
9a799d71
AK		 2048static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2049{
2050 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2051
2052 if (adapter->vlgrp) {
2053 u16 vid;
2054 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2055 if (!vlan_group_get_device(adapter->vlgrp, vid))
2056 continue;
2057 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2058 }
2059 }
2060}
2061
2c5645cf
CL		 2062static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
2063{
2064 struct dev_mc_list *mc_ptr;
2065 u8 *addr = *mc_addr_ptr;
2066 *vmdq = 0;
2067
2068 mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
2069 if (mc_ptr->next)
2070 *mc_addr_ptr = mc_ptr->next->dmi_addr;
2071 else
2072 *mc_addr_ptr = NULL;
2073
2074 return addr;
2075}
2076
9a799d71 2077/**
2c5645cf 2078 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 2079 * @netdev: network interface device structure
2080 *
2c5645cf
CL		 2081 * The set_rx_method entry point is called whenever the unicast/multicast
2082 * address list or the network interface flags are updated. This routine is
2083 * responsible for configuring the hardware for proper unicast, multicast and
2084 * promiscuous mode.
9a799d71 2085 **/
2c5645cf 2086static void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 2087{
2088 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2089 struct ixgbe_hw *hw = &adapter->hw;
3d01625a 2090 u32 fctrl, vlnctrl;
2c5645cf
CL		 2091 u8 *addr_list = NULL;
2092 int addr_count = 0;
9a799d71
AK		 2093
2094 /* Check for Promiscuous and All Multicast modes */
2095
2096 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3d01625a 2097 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
9a799d71
AK		 2098
2099 if (netdev->flags & IFF_PROMISC) {
2c5645cf 2100 hw->addr_ctrl.user_set_promisc = 1;
9a799d71 2101 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3d01625a 2102 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
9a799d71 2103 } else {
746b9f02
PM		 2104 if (netdev->flags & IFF_ALLMULTI) {
2105 fctrl |= IXGBE_FCTRL_MPE;
2106 fctrl &= ~IXGBE_FCTRL_UPE;
2107 } else {
2108 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2109 }
3d01625a 2110 vlnctrl |= IXGBE_VLNCTRL_VFE;
2c5645cf 2111 hw->addr_ctrl.user_set_promisc = 0;
9a799d71
AK		 2112 }
2113
2114 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3d01625a 2115 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
9a799d71 2116
2c5645cf
CL		 2117 /* reprogram secondary unicast list */
2118 addr_count = netdev->uc_count;
2119 if (addr_count)
2120 addr_list = netdev->uc_list->dmi_addr;
c44ade9e
JB		 2121 hw->mac.ops.update_uc_addr_list(hw, addr_list, addr_count,
2122 ixgbe_addr_list_itr);
9a799d71 2123
2c5645cf
CL		 2124 /* reprogram multicast list */
2125 addr_count = netdev->mc_count;
2126 if (addr_count)
2127 addr_list = netdev->mc_list->dmi_addr;
c44ade9e
JB		 2128 hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2129 ixgbe_addr_list_itr);
9a799d71
AK		 2130}
2131
021230d4
AV		 2132static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2133{
2134 int q_idx;
2135 struct ixgbe_q_vector *q_vector;
2136 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2137
2138 /* legacy and MSI only use one vector */
2139 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2140 q_vectors = 1;
2141
2142 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 2143 struct napi_struct *napi;
7a921c93 2144 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 2145 if (!q_vector->rxr_count)
2146 continue;
f0848276
JB		 2147 napi = &q_vector->napi;
2148 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) &&
2149 (q_vector->rxr_count > 1))
2150 napi->poll = &ixgbe_clean_rxonly_many;
2151
2152 napi_enable(napi);
021230d4
AV		 2153 }
2154}
2155
2156static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2157{
2158 int q_idx;
2159 struct ixgbe_q_vector *q_vector;
2160 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2161
2162 /* legacy and MSI only use one vector */
2163 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2164 q_vectors = 1;
2165
2166 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 2167 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 2168 if (!q_vector->rxr_count)
2169 continue;
2170 napi_disable(&q_vector->napi);
2171 }
2172}
2173
7a6b6f51 2174#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 2175/*
2176 * ixgbe_configure_dcb - Configure DCB hardware
2177 * @adapter: ixgbe adapter struct
2178 *
2179 * This is called by the driver on open to configure the DCB hardware.
2180 * This is also called by the gennetlink interface when reconfiguring
2181 * the DCB state.
2182 */
2183static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2184{
2185 struct ixgbe_hw *hw = &adapter->hw;
2186 u32 txdctl, vlnctrl;
2187 int i, j;
2188
2189 ixgbe_dcb_check_config(&adapter->dcb_cfg);
2190 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2191 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2192
2193 /* reconfigure the hardware */
2194 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2195
2196 for (i = 0; i < adapter->num_tx_queues; i++) {
2197 j = adapter->tx_ring[i].reg_idx;
2198 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2199 /* PThresh workaround for Tx hang with DFP enabled. */
2200 txdctl |= 32;
2201 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2202 }
2203 /* Enable VLAN tag insert/strip */
2204 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
e8e26350
PW		 2205 if (hw->mac.type == ixgbe_mac_82598EB) {
2206 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2207 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2208 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2209 } else if (hw->mac.type == ixgbe_mac_82599EB) {
2210 vlnctrl |= IXGBE_VLNCTRL_VFE;
2211 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2212 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2213 for (i = 0; i < adapter->num_rx_queues; i++) {
2214 j = adapter->rx_ring[i].reg_idx;
2215 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2216 vlnctrl |= IXGBE_RXDCTL_VME;
2217 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2218 }
2219 }
2f90b865
AD		 2220 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2221}
2222
2223#endif
9a799d71
AK		 2224static void ixgbe_configure(struct ixgbe_adapter *adapter)
2225{
2226 struct net_device *netdev = adapter->netdev;
2227 int i;
2228
2c5645cf 2229 ixgbe_set_rx_mode(netdev);
9a799d71
AK		 2230
2231 ixgbe_restore_vlan(adapter);
7a6b6f51 2232#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 2233 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2234 netif_set_gso_max_size(netdev, 32768);
2235 ixgbe_configure_dcb(adapter);
2236 } else {
2237 netif_set_gso_max_size(netdev, 65536);
2238 }
2239#else
2240 netif_set_gso_max_size(netdev, 65536);
2241#endif
9a799d71
AK		 2242
2243 ixgbe_configure_tx(adapter);
2244 ixgbe_configure_rx(adapter);
2245 for (i = 0; i < adapter->num_rx_queues; i++)
2246 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
b4617240 2247 (adapter->rx_ring[i].count - 1));
9a799d71
AK		 2248}
2249
e8e26350
PW		 2250static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2251{
2252 switch (hw->phy.type) {
2253 case ixgbe_phy_sfp_avago:
2254 case ixgbe_phy_sfp_ftl:
2255 case ixgbe_phy_sfp_intel:
2256 case ixgbe_phy_sfp_unknown:
2257 case ixgbe_phy_tw_tyco:
2258 case ixgbe_phy_tw_unknown:
2259 return true;
2260 default:
2261 return false;
2262 }
2263}
2264
0ecc061d 2265/**
e8e26350
PW		 2266 * ixgbe_sfp_link_config - set up SFP+ link
2267 * @adapter: pointer to private adapter struct
2268 **/
2269static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2270{
2271 struct ixgbe_hw *hw = &adapter->hw;
2272
2273 if (hw->phy.multispeed_fiber) {
2274 /*
2275 * In multispeed fiber setups, the device may not have
2276 * had a physical connection when the driver loaded.
2277 * If that's the case, the initial link configuration
2278 * couldn't get the MAC into 10G or 1G mode, so we'll
2279 * never have a link status change interrupt fire.
2280 * We need to try and force an autonegotiation
2281 * session, then bring up link.
2282 */
2283 hw->mac.ops.setup_sfp(hw);
2284 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2285 schedule_work(&adapter->multispeed_fiber_task);
2286 } else {
2287 /*
2288 * Direct Attach Cu and non-multispeed fiber modules
2289 * still need to be configured properly prior to
2290 * attempting link.
2291 */
2292 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2293 schedule_work(&adapter->sfp_config_module_task);
2294 }
2295}
2296
2297/**
2298 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 2299 * @hw: pointer to private hardware struct
2300 *
2301 * Returns 0 on success, negative on failure
2302 **/
e8e26350 2303static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 2304{
2305 u32 autoneg;
2306 bool link_up = false;
2307 u32 ret = IXGBE_ERR_LINK_SETUP;
2308
2309 if (hw->mac.ops.check_link)
2310 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2311
2312 if (ret)
2313 goto link_cfg_out;
2314
2315 if (hw->mac.ops.get_link_capabilities)
2316 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
2317 &hw->mac.autoneg);
2318 if (ret)
2319 goto link_cfg_out;
2320
2321 if (hw->mac.ops.setup_link_speed)
2322 ret = hw->mac.ops.setup_link_speed(hw, autoneg, true, link_up);
0ecc061d
PWJ		 2323link_cfg_out:
2324 return ret;
2325}
2326
e8e26350
PW		 2327#define IXGBE_MAX_RX_DESC_POLL 10
2328static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2329 int rxr)
2330{
2331 int j = adapter->rx_ring[rxr].reg_idx;
2332 int k;
2333
2334 for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2335 if (IXGBE_READ_REG(&adapter->hw,
2336 IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2337 break;
2338 else
2339 msleep(1);
2340 }
2341 if (k >= IXGBE_MAX_RX_DESC_POLL) {
2342 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2343 "not set within the polling period\n", rxr);
2344 }
2345 ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
2346 (adapter->rx_ring[rxr].count - 1));
2347}
2348
9a799d71
AK		 2349static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2350{
2351 struct net_device *netdev = adapter->netdev;
9a799d71 2352 struct ixgbe_hw *hw = &adapter->hw;
021230d4 2353 int i, j = 0;
e8e26350 2354 int num_rx_rings = adapter->num_rx_queues;
0ecc061d 2355 int err;
9a799d71 2356 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 2357 u32 txdctl, rxdctl, mhadd;
e8e26350 2358 u32 dmatxctl;
021230d4 2359 u32 gpie;
9a799d71 2360
5eba3699
AV		 2361 ixgbe_get_hw_control(adapter);
2362
021230d4
AV		 2363 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2364 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
9a799d71
AK		 2365 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2366 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
b4617240 2367 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
9a799d71
AK		 2368 } else {
2369 /* MSI only */
021230d4 2370 gpie = 0;
9a799d71 2371 }
021230d4
AV		 2372 /* XXX: to interrupt immediately for EICS writes, enable this */
2373 /* gpie |= IXGBE_GPIE_EIMEN; */
2374 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
9a799d71
AK		 2375 }
2376
021230d4
AV		 2377 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2378 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2379 * specifically only auto mask tx and rx interrupts */
2380 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2381 }
9a799d71 2382
0befdb3e
JB		 2383 /* Enable fan failure interrupt if media type is copper */
2384 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2385 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2386 gpie |= IXGBE_SDP1_GPIEN;
2387 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2388 }
2389
e8e26350
PW		 2390 if (hw->mac.type == ixgbe_mac_82599EB) {
2391 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2392 gpie |= IXGBE_SDP1_GPIEN;
2393 gpie |= IXGBE_SDP2_GPIEN;
2394 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2395 }
2396
021230d4 2397 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
9a799d71
AK		 2398 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2399 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2400 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2401
2402 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2403 }
2404
2405 for (i = 0; i < adapter->num_tx_queues; i++) {
021230d4
AV		 2406 j = adapter->tx_ring[i].reg_idx;
2407 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
e01c31a5
JB		 2408 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2409 txdctl |= (8 << 16);
e8e26350
PW		 2410 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2411 }
2412
2413 if (hw->mac.type == ixgbe_mac_82599EB) {
2414 /* DMATXCTL.EN must be set after all Tx queue config is done */
2415 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2416 dmatxctl |= IXGBE_DMATXCTL_TE;
2417 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2418 }
2419 for (i = 0; i < adapter->num_tx_queues; i++) {
2420 j = adapter->tx_ring[i].reg_idx;
2421 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
9a799d71 2422 txdctl |= IXGBE_TXDCTL_ENABLE;
021230d4 2423 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
9a799d71
AK		 2424 }
2425
e8e26350 2426 for (i = 0; i < num_rx_rings; i++) {
021230d4
AV		 2427 j = adapter->rx_ring[i].reg_idx;
2428 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2429 /* enable PTHRESH=32 descriptors (half the internal cache)
2430 * and HTHRESH=0 descriptors (to minimize latency on fetch),
2431 * this also removes a pesky rx_no_buffer_count increment */
2432 rxdctl |= 0x0020;
9a799d71 2433 rxdctl |= IXGBE_RXDCTL_ENABLE;
021230d4 2434 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
e8e26350
PW		 2435 if (hw->mac.type == ixgbe_mac_82599EB)
2436 ixgbe_rx_desc_queue_enable(adapter, i);
9a799d71
AK		 2437 }
2438 /* enable all receives */
2439 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
e8e26350
PW		 2440 if (hw->mac.type == ixgbe_mac_82598EB)
2441 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2442 else
2443 rxdctl |= IXGBE_RXCTRL_RXEN;
2444 hw->mac.ops.enable_rx_dma(hw, rxdctl);
9a799d71
AK		 2445
2446 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2447 ixgbe_configure_msix(adapter);
2448 else
2449 ixgbe_configure_msi_and_legacy(adapter);
2450
2451 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 2452 ixgbe_napi_enable_all(adapter);
2453
2454 /* clear any pending interrupts, may auto mask */
2455 IXGBE_READ_REG(hw, IXGBE_EICR);
2456
9a799d71
AK		 2457 ixgbe_irq_enable(adapter);
2458
e8e26350
PW		 2459 /*
2460 * For hot-pluggable SFP+ devices, a new SFP+ module may have
2461 * arrived before interrupts were enabled. We need to kick off
2462 * the SFP+ module setup first, then try to bring up link.
2463 * If we're not hot-pluggable SFP+, we just need to configure link
2464 * and bring it up.
2465 */
2466 err = hw->phy.ops.identify(hw);
2467 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
2468 DPRINTK(PROBE, ERR, "PHY not supported on this NIC %d\n", err);
2469 ixgbe_down(adapter);
2470 return err;
2471 }
2472
2473 if (ixgbe_is_sfp(hw)) {
2474 ixgbe_sfp_link_config(adapter);
2475 } else {
2476 err = ixgbe_non_sfp_link_config(hw);
2477 if (err)
2478 DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
2479 }
0ecc061d 2480
1da100bb
PWJ		 2481 /* enable transmits */
2482 netif_tx_start_all_queues(netdev);
2483
9a799d71
AK		 2484 /* bring the link up in the watchdog, this could race with our first
2485 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 2486 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2487 adapter->link_check_timeout = jiffies;
9a799d71
AK		 2488 mod_timer(&adapter->watchdog_timer, jiffies);
2489 return 0;
2490}
2491
d4f80882
AV		 2492void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2493{
2494 WARN_ON(in_interrupt());
2495 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2496 msleep(1);
2497 ixgbe_down(adapter);
2498 ixgbe_up(adapter);
2499 clear_bit(__IXGBE_RESETTING, &adapter->state);
2500}
2501
9a799d71
AK		 2502int ixgbe_up(struct ixgbe_adapter *adapter)
2503{
2504 /* hardware has been reset, we need to reload some things */
2505 ixgbe_configure(adapter);
2506
2507 return ixgbe_up_complete(adapter);
2508}
2509
2510void ixgbe_reset(struct ixgbe_adapter *adapter)
2511{
c44ade9e
JB		 2512 struct ixgbe_hw *hw = &adapter->hw;
2513 if (hw->mac.ops.init_hw(hw))
2514 dev_err(&adapter->pdev->dev, "Hardware Error\n");
9a799d71
AK		 2515
2516 /* reprogram the RAR[0] in case user changed it. */
c44ade9e 2517 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71
AK		 2518
2519}
2520
9a799d71
AK		 2521/**
2522 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2523 * @adapter: board private structure
2524 * @rx_ring: ring to free buffers from
2525 **/
2526static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
b4617240 2527 struct ixgbe_ring *rx_ring)
9a799d71
AK		 2528{
2529 struct pci_dev *pdev = adapter->pdev;
2530 unsigned long size;
2531 unsigned int i;
2532
2533 /* Free all the Rx ring sk_buffs */
2534
2535 for (i = 0; i < rx_ring->count; i++) {
2536 struct ixgbe_rx_buffer *rx_buffer_info;
2537
2538 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2539 if (rx_buffer_info->dma) {
2540 pci_unmap_single(pdev, rx_buffer_info->dma,
b4617240
PW		 2541 rx_ring->rx_buf_len,
2542 PCI_DMA_FROMDEVICE);
9a799d71
AK		 2543 rx_buffer_info->dma = 0;
2544 }
2545 if (rx_buffer_info->skb) {
f8212f97 2546 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 2547 rx_buffer_info->skb = NULL;
f8212f97
AD		 2548 do {
2549 struct sk_buff *this = skb;
2550 skb = skb->prev;
2551 dev_kfree_skb(this);
2552 } while (skb);
9a799d71
AK		 2553 }
2554 if (!rx_buffer_info->page)
2555 continue;
762f4c57
JB		 2556 pci_unmap_page(pdev, rx_buffer_info->page_dma, PAGE_SIZE / 2,
2557 PCI_DMA_FROMDEVICE);
9a799d71 2558 rx_buffer_info->page_dma = 0;
9a799d71
AK		 2559 put_page(rx_buffer_info->page);
2560 rx_buffer_info->page = NULL;
762f4c57 2561 rx_buffer_info->page_offset = 0;
9a799d71
AK		 2562 }
2563
2564 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2565 memset(rx_ring->rx_buffer_info, 0, size);
2566
2567 /* Zero out the descriptor ring */
2568 memset(rx_ring->desc, 0, rx_ring->size);
2569
2570 rx_ring->next_to_clean = 0;
2571 rx_ring->next_to_use = 0;
2572
9891ca7c
JB		 2573 if (rx_ring->head)
2574 writel(0, adapter->hw.hw_addr + rx_ring->head);
2575 if (rx_ring->tail)
2576 writel(0, adapter->hw.hw_addr + rx_ring->tail);
9a799d71
AK		 2577}
2578
2579/**
2580 * ixgbe_clean_tx_ring - Free Tx Buffers
2581 * @adapter: board private structure
2582 * @tx_ring: ring to be cleaned
2583 **/
2584static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
b4617240 2585 struct ixgbe_ring *tx_ring)
9a799d71
AK		 2586{
2587 struct ixgbe_tx_buffer *tx_buffer_info;
2588 unsigned long size;
2589 unsigned int i;
2590
2591 /* Free all the Tx ring sk_buffs */
2592
2593 for (i = 0; i < tx_ring->count; i++) {
2594 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2595 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2596 }
2597
2598 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2599 memset(tx_ring->tx_buffer_info, 0, size);
2600
2601 /* Zero out the descriptor ring */
2602 memset(tx_ring->desc, 0, tx_ring->size);
2603
2604 tx_ring->next_to_use = 0;
2605 tx_ring->next_to_clean = 0;
2606
9891ca7c
JB		 2607 if (tx_ring->head)
2608 writel(0, adapter->hw.hw_addr + tx_ring->head);
2609 if (tx_ring->tail)
2610 writel(0, adapter->hw.hw_addr + tx_ring->tail);
9a799d71
AK		 2611}
2612
2613/**
021230d4 2614 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 2615 * @adapter: board private structure
2616 **/
021230d4 2617static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 2618{
2619 int i;
2620
021230d4
AV		 2621 for (i = 0; i < adapter->num_rx_queues; i++)
2622 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
9a799d71
AK		 2623}
2624
2625/**
021230d4 2626 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 2627 * @adapter: board private structure
2628 **/
021230d4 2629static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 2630{
2631 int i;
2632
021230d4
AV		 2633 for (i = 0; i < adapter->num_tx_queues; i++)
2634 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
9a799d71
AK		 2635}
2636
2637void ixgbe_down(struct ixgbe_adapter *adapter)
2638{
2639 struct net_device *netdev = adapter->netdev;
7f821875 2640 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 2641 u32 rxctrl;
7f821875
JB		 2642 u32 txdctl;
2643 int i, j;
9a799d71
AK		 2644
2645 /* signal that we are down to the interrupt handler */
2646 set_bit(__IXGBE_DOWN, &adapter->state);
2647
2648 /* disable receives */
7f821875
JB		 2649 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2650 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71
AK		 2651
2652 netif_tx_disable(netdev);
2653
7f821875 2654 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 2655 msleep(10);
2656
7f821875
JB		 2657 netif_tx_stop_all_queues(netdev);
2658
9a799d71
AK		 2659 ixgbe_irq_disable(adapter);
2660
021230d4 2661 ixgbe_napi_disable_all(adapter);
7f821875 2662
9a799d71 2663 del_timer_sync(&adapter->watchdog_timer);
cf8280ee 2664 cancel_work_sync(&adapter->watchdog_task);
9a799d71 2665
7f821875
JB		 2666 /* disable transmits in the hardware now that interrupts are off */
2667 for (i = 0; i < adapter->num_tx_queues; i++) {
2668 j = adapter->tx_ring[i].reg_idx;
2669 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2670 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
2671 (txdctl & ~IXGBE_TXDCTL_ENABLE));
2672 }
88512539
PW		 2673 /* Disable the Tx DMA engine on 82599 */
2674 if (hw->mac.type == ixgbe_mac_82599EB)
2675 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
2676 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
2677 ~IXGBE_DMATXCTL_TE));
7f821875 2678
9a799d71 2679 netif_carrier_off(netdev);
9a799d71 2680
5dd2d332 2681#ifdef CONFIG_IXGBE_DCA
96b0e0f6
JB		 2682 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2683 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
2684 dca_remove_requester(&adapter->pdev->dev);
2685 }
2686
2687#endif
6f4a0e45
PL		 2688 if (!pci_channel_offline(adapter->pdev))
2689 ixgbe_reset(adapter);
9a799d71
AK		 2690 ixgbe_clean_all_tx_rings(adapter);
2691 ixgbe_clean_all_rx_rings(adapter);
2692
5dd2d332 2693#ifdef CONFIG_IXGBE_DCA
96b0e0f6
JB		 2694 /* since we reset the hardware DCA settings were cleared */
2695 if (dca_add_requester(&adapter->pdev->dev) == 0) {
2696 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
2697 /* always use CB2 mode, difference is masked
2698 * in the CB driver */
b4617240 2699 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
96b0e0f6
JB		 2700 ixgbe_setup_dca(adapter);
2701 }
2702#endif
9a799d71
AK		 2703}
2704
9a799d71 2705/**
021230d4
AV		 2706 * ixgbe_poll - NAPI Rx polling callback
2707 * @napi: structure for representing this polling device
2708 * @budget: how many packets driver is allowed to clean
2709 *
2710 * This function is used for legacy and MSI, NAPI mode
9a799d71 2711 **/
021230d4 2712static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 2713{
9a1a69ad
JB		 2714 struct ixgbe_q_vector *q_vector =
2715 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 2716 struct ixgbe_adapter *adapter = q_vector->adapter;
9a1a69ad 2717 int tx_clean_complete, work_done = 0;
9a799d71 2718
5dd2d332 2719#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 2720 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2721 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
2722 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
2723 }
2724#endif
2725
9a1a69ad 2726 tx_clean_complete = ixgbe_clean_tx_irq(adapter, adapter->tx_ring);
78b6f4ce 2727 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
9a799d71 2728
9a1a69ad 2729 if (!tx_clean_complete)
d2c7ddd6
DM		 2730 work_done = budget;
2731
53e52c72
DM		 2732 /* If budget not fully consumed, exit the polling mode */
2733 if (work_done < budget) {
288379f0 2734 napi_complete(napi);
509ee935 2735 if (adapter->itr_setting & 1)
f494e8fa 2736 ixgbe_set_itr(adapter);
d4f80882 2737 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 2738 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
9a799d71 2739 }
9a799d71
AK		 2740 return work_done;
2741}
2742
2743/**
2744 * ixgbe_tx_timeout - Respond to a Tx Hang
2745 * @netdev: network interface device structure
2746 **/
2747static void ixgbe_tx_timeout(struct net_device *netdev)
2748{
2749 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2750
2751 /* Do the reset outside of interrupt context */
2752 schedule_work(&adapter->reset_task);
2753}
2754
2755static void ixgbe_reset_task(struct work_struct *work)
2756{
2757 struct ixgbe_adapter *adapter;
2758 adapter = container_of(work, struct ixgbe_adapter, reset_task);
2759
2f90b865
AD		 2760 /* If we're already down or resetting, just bail */
2761 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
2762 test_bit(__IXGBE_RESETTING, &adapter->state))
2763 return;
2764
9a799d71
AK		 2765 adapter->tx_timeout_count++;
2766
d4f80882 2767 ixgbe_reinit_locked(adapter);
9a799d71
AK		 2768}
2769
bc97114d
PWJ		 2770#ifdef CONFIG_IXGBE_DCB
2771static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
b9804972 2772{
bc97114d 2773 bool ret = false;
b9804972 2774
bc97114d
PWJ		 2775 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2776 adapter->ring_feature[RING_F_DCB].mask = 0x7 << 3;
2777 adapter->num_rx_queues =
2778 adapter->ring_feature[RING_F_DCB].indices;
2779 adapter->num_tx_queues =
2780 adapter->ring_feature[RING_F_DCB].indices;
2781 ret = true;
2782 } else {
bc97114d
PWJ		 2783 ret = false;
2784 }
2f90b865 2785
bc97114d
PWJ		 2786 return ret;
2787}
2788#endif
2789
4df10466
JB		 2790/**
2791 * ixgbe_set_rss_queues: Allocate queues for RSS
2792 * @adapter: board private structure to initialize
2793 *
2794 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
2795 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
2796 *
2797 **/
bc97114d
PWJ		 2798static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
2799{
2800 bool ret = false;
2801
2802 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2803 adapter->ring_feature[RING_F_RSS].mask = 0xF;
2804 adapter->num_rx_queues =
2805 adapter->ring_feature[RING_F_RSS].indices;
2806 adapter->num_tx_queues =
2807 adapter->ring_feature[RING_F_RSS].indices;
2808 ret = true;
2809 } else {
bc97114d 2810 ret = false;
b9804972
JB		 2811 }
2812
bc97114d
PWJ		 2813 return ret;
2814}
2815
4df10466
JB		 2816/*
2817 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
2818 * @adapter: board private structure to initialize
2819 *
2820 * This is the top level queue allocation routine. The order here is very
2821 * important, starting with the "most" number of features turned on at once,
2822 * and ending with the smallest set of features. This way large combinations
2823 * can be allocated if they're turned on, and smaller combinations are the
2824 * fallthrough conditions.
2825 *
2826 **/
bc97114d
PWJ		 2827static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
2828{
bc97114d
PWJ		 2829#ifdef CONFIG_IXGBE_DCB
2830 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 2831 goto done;
bc97114d
PWJ		 2832
2833#endif
2834 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 2835 goto done;
2836
2837 /* fallback to base case */
2838 adapter->num_rx_queues = 1;
2839 adapter->num_tx_queues = 1;
2840
2841done:
2842 /* Notify the stack of the (possibly) reduced Tx Queue count. */
2843 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
b9804972
JB		 2844}
2845
021230d4 2846static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
b4617240 2847 int vectors)
021230d4
AV		 2848{
2849 int err, vector_threshold;
2850
2851 /* We'll want at least 3 (vector_threshold):
2852 * 1) TxQ[0] Cleanup
2853 * 2) RxQ[0] Cleanup
2854 * 3) Other (Link Status Change, etc.)
2855 * 4) TCP Timer (optional)
2856 */
2857 vector_threshold = MIN_MSIX_COUNT;
2858
2859 /* The more we get, the more we will assign to Tx/Rx Cleanup
2860 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
2861 * Right now, we simply care about how many we'll get; we'll
2862 * set them up later while requesting irq's.
2863 */
2864 while (vectors >= vector_threshold) {
2865 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
b4617240 2866 vectors);
021230d4
AV		 2867 if (!err) /* Success in acquiring all requested vectors. */
2868 break;
2869 else if (err < 0)
2870 vectors = 0; /* Nasty failure, quit now */
2871 else /* err == number of vectors we should try again with */
2872 vectors = err;
2873 }
2874
2875 if (vectors < vector_threshold) {
2876 /* Can't allocate enough MSI-X interrupts? Oh well.
2877 * This just means we'll go with either a single MSI
2878 * vector or fall back to legacy interrupts.
2879 */
2880 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
2881 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2882 kfree(adapter->msix_entries);
2883 adapter->msix_entries = NULL;
021230d4
AV		 2884 } else {
2885 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 2886 /*
2887 * Adjust for only the vectors we'll use, which is minimum
2888 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
2889 * vectors we were allocated.
2890 */
2891 adapter->num_msix_vectors = min(vectors,
2892 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 2893 }
2894}
2895
021230d4 2896/**
bc97114d 2897 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 2898 * @adapter: board private structure to initialize
2899 *
bc97114d
PWJ		 2900 * Cache the descriptor ring offsets for RSS to the assigned rings.
2901 *
021230d4 2902 **/
bc97114d 2903static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 2904{
bc97114d
PWJ		 2905 int i;
2906 bool ret = false;
2907
2908 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2909 for (i = 0; i < adapter->num_rx_queues; i++)
2910 adapter->rx_ring[i].reg_idx = i;
2911 for (i = 0; i < adapter->num_tx_queues; i++)
2912 adapter->tx_ring[i].reg_idx = i;
2913 ret = true;
2914 } else {
2915 ret = false;
2916 }
2917
2918 return ret;
2919}
2920
2921#ifdef CONFIG_IXGBE_DCB
2922/**
2923 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
2924 * @adapter: board private structure to initialize
2925 *
2926 * Cache the descriptor ring offsets for DCB to the assigned rings.
2927 *
2928 **/
2929static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
2930{
2931 int i;
2932 bool ret = false;
2933 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
2934
2935 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2936 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2f90b865
AD		 2937 /* the number of queues is assumed to be symmetric */
2938 for (i = 0; i < dcb_i; i++) {
2939 adapter->rx_ring[i].reg_idx = i << 3;
2940 adapter->tx_ring[i].reg_idx = i << 2;
2941 }
bc97114d 2942 ret = true;
e8e26350 2943 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
f92ef202
PW		 2944 if (dcb_i == 8) {
2945 /*
2946 * Tx TC0 starts at: descriptor queue 0
2947 * Tx TC1 starts at: descriptor queue 32
2948 * Tx TC2 starts at: descriptor queue 64
2949 * Tx TC3 starts at: descriptor queue 80
2950 * Tx TC4 starts at: descriptor queue 96
2951 * Tx TC5 starts at: descriptor queue 104
2952 * Tx TC6 starts at: descriptor queue 112
2953 * Tx TC7 starts at: descriptor queue 120
2954 *
2955 * Rx TC0-TC7 are offset by 16 queues each
2956 */
2957 for (i = 0; i < 3; i++) {
2958 adapter->tx_ring[i].reg_idx = i << 5;
2959 adapter->rx_ring[i].reg_idx = i << 4;
2960 }
2961 for ( ; i < 5; i++) {
2962 adapter->tx_ring[i].reg_idx =
2963 ((i + 2) << 4);
2964 adapter->rx_ring[i].reg_idx = i << 4;
2965 }
2966 for ( ; i < dcb_i; i++) {
2967 adapter->tx_ring[i].reg_idx =
2968 ((i + 8) << 3);
2969 adapter->rx_ring[i].reg_idx = i << 4;
2970 }
2971
2972 ret = true;
2973 } else if (dcb_i == 4) {
2974 /*
2975 * Tx TC0 starts at: descriptor queue 0
2976 * Tx TC1 starts at: descriptor queue 64
2977 * Tx TC2 starts at: descriptor queue 96
2978 * Tx TC3 starts at: descriptor queue 112
2979 *
2980 * Rx TC0-TC3 are offset by 32 queues each
2981 */
2982 adapter->tx_ring[0].reg_idx = 0;
2983 adapter->tx_ring[1].reg_idx = 64;
2984 adapter->tx_ring[2].reg_idx = 96;
2985 adapter->tx_ring[3].reg_idx = 112;
2986 for (i = 0 ; i < dcb_i; i++)
2987 adapter->rx_ring[i].reg_idx = i << 5;
2988
2989 ret = true;
2990 } else {
2991 ret = false;
e8e26350 2992 }
bc97114d
PWJ		 2993 } else {
2994 ret = false;
021230d4 2995 }
bc97114d
PWJ		 2996 } else {
2997 ret = false;
021230d4 2998 }
bc97114d
PWJ		 2999
3000 return ret;
3001}
3002#endif
3003
3004/**
3005 * ixgbe_cache_ring_register - Descriptor ring to register mapping
3006 * @adapter: board private structure to initialize
3007 *
3008 * Once we know the feature-set enabled for the device, we'll cache
3009 * the register offset the descriptor ring is assigned to.
3010 *
3011 * Note, the order the various feature calls is important. It must start with
3012 * the "most" features enabled at the same time, then trickle down to the
3013 * least amount of features turned on at once.
3014 **/
3015static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
3016{
3017 /* start with default case */
3018 adapter->rx_ring[0].reg_idx = 0;
3019 adapter->tx_ring[0].reg_idx = 0;
3020
3021#ifdef CONFIG_IXGBE_DCB
3022 if (ixgbe_cache_ring_dcb(adapter))
3023 return;
3024
3025#endif
3026 if (ixgbe_cache_ring_rss(adapter))
3027 return;
021230d4
AV		 3028}
3029
9a799d71
AK		 3030/**
3031 * ixgbe_alloc_queues - Allocate memory for all rings
3032 * @adapter: board private structure to initialize
3033 *
3034 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 3035 * number of queues at compile-time. The polling_netdev array is
3036 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 3037 **/
2f90b865 3038static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71
AK		 3039{
3040 int i;
3041
3042 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
b4617240 3043 sizeof(struct ixgbe_ring), GFP_KERNEL);
9a799d71 3044 if (!adapter->tx_ring)
021230d4 3045 goto err_tx_ring_allocation;
9a799d71
AK		 3046
3047 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
b4617240 3048 sizeof(struct ixgbe_ring), GFP_KERNEL);
021230d4
AV		 3049 if (!adapter->rx_ring)
3050 goto err_rx_ring_allocation;
9a799d71 3051
021230d4 3052 for (i = 0; i < adapter->num_tx_queues; i++) {
b9804972 3053 adapter->tx_ring[i].count = adapter->tx_ring_count;
021230d4
AV		 3054 adapter->tx_ring[i].queue_index = i;
3055 }
b9804972 3056
9a799d71 3057 for (i = 0; i < adapter->num_rx_queues; i++) {
b9804972 3058 adapter->rx_ring[i].count = adapter->rx_ring_count;
021230d4
AV		 3059 adapter->rx_ring[i].queue_index = i;
3060 }
3061
3062 ixgbe_cache_ring_register(adapter);
3063
3064 return 0;
3065
3066err_rx_ring_allocation:
3067 kfree(adapter->tx_ring);
3068err_tx_ring_allocation:
3069 return -ENOMEM;
3070}
3071
3072/**
3073 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3074 * @adapter: board private structure to initialize
3075 *
3076 * Attempt to configure the interrupts using the best available
3077 * capabilities of the hardware and the kernel.
3078 **/
feea6a57 3079static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 3080{
8be0e467 3081 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 3082 int err = 0;
3083 int vector, v_budget;
3084
3085 /*
3086 * It's easy to be greedy for MSI-X vectors, but it really
3087 * doesn't do us much good if we have a lot more vectors
3088 * than CPU's. So let's be conservative and only ask for
3089 * (roughly) twice the number of vectors as there are CPU's.
3090 */
3091 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
b4617240 3092 (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
021230d4
AV		 3093
3094 /*
3095 * At the same time, hardware can only support a maximum of
8be0e467
PW		 3096 * hw.mac->max_msix_vectors vectors. With features
3097 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3098 * descriptor queues supported by our device. Thus, we cap it off in
3099 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 3100 */
8be0e467 3101 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 3102
3103 /* A failure in MSI-X entry allocation isn't fatal, but it does
3104 * mean we disable MSI-X capabilities of the adapter. */
3105 adapter->msix_entries = kcalloc(v_budget,
b4617240 3106 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 3107 if (adapter->msix_entries) {
3108 for (vector = 0; vector < v_budget; vector++)
3109 adapter->msix_entries[vector].entry = vector;
021230d4 3110
7a921c93 3111 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 3112
7a921c93
AD		 3113 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3114 goto out;
3115 }
021230d4 3116
7a921c93
AD		 3117 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
3118 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
3119 ixgbe_set_num_queues(adapter);
021230d4 3120
021230d4
AV		 3121 err = pci_enable_msi(adapter->pdev);
3122 if (!err) {
3123 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
3124 } else {
3125 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
b4617240 3126 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 3127 /* reset err */
3128 err = 0;
3129 }
3130
3131out:
021230d4
AV		 3132 return err;
3133}
3134
7a921c93
AD		 3135/**
3136 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
3137 * @adapter: board private structure to initialize
3138 *
3139 * We allocate one q_vector per queue interrupt. If allocation fails we
3140 * return -ENOMEM.
3141 **/
3142static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
3143{
3144 int q_idx, num_q_vectors;
3145 struct ixgbe_q_vector *q_vector;
3146 int napi_vectors;
3147 int (*poll)(struct napi_struct *, int);
3148
3149 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3150 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3151 napi_vectors = adapter->num_rx_queues;
3152 poll = &ixgbe_clean_rxonly;
3153 } else {
3154 num_q_vectors = 1;
3155 napi_vectors = 1;
3156 poll = &ixgbe_poll;
3157 }
3158
3159 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3160 q_vector = kzalloc(sizeof(struct ixgbe_q_vector), GFP_KERNEL);
3161 if (!q_vector)
3162 goto err_out;
3163 q_vector->adapter = adapter;
3164 q_vector->v_idx = q_idx;
3165 q_vector->eitr = adapter->eitr_param;
3166 if (q_idx < napi_vectors)
3167 netif_napi_add(adapter->netdev, &q_vector->napi,
3168 (*poll), 64);
3169 adapter->q_vector[q_idx] = q_vector;
3170 }
3171
3172 return 0;
3173
3174err_out:
3175 while (q_idx) {
3176 q_idx--;
3177 q_vector = adapter->q_vector[q_idx];
3178 netif_napi_del(&q_vector->napi);
3179 kfree(q_vector);
3180 adapter->q_vector[q_idx] = NULL;
3181 }
3182 return -ENOMEM;
3183}
3184
3185/**
3186 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
3187 * @adapter: board private structure to initialize
3188 *
3189 * This function frees the memory allocated to the q_vectors. In addition if
3190 * NAPI is enabled it will delete any references to the NAPI struct prior
3191 * to freeing the q_vector.
3192 **/
3193static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
3194{
3195 int q_idx, num_q_vectors;
3196 int napi_vectors;
3197
3198 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3199 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3200 napi_vectors = adapter->num_rx_queues;
3201 } else {
3202 num_q_vectors = 1;
3203 napi_vectors = 1;
3204 }
3205
3206 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3207 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
3208
3209 adapter->q_vector[q_idx] = NULL;
3210 if (q_idx < napi_vectors)
3211 netif_napi_del(&q_vector->napi);
3212 kfree(q_vector);
3213 }
3214}
3215
2f90b865 3216void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 3217{
3218 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3219 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3220 pci_disable_msix(adapter->pdev);
3221 kfree(adapter->msix_entries);
3222 adapter->msix_entries = NULL;
3223 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
3224 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
3225 pci_disable_msi(adapter->pdev);
3226 }
3227 return;
3228}
3229
3230/**
3231 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
3232 * @adapter: board private structure to initialize
3233 *
3234 * We determine which interrupt scheme to use based on...
3235 * - Kernel support (MSI, MSI-X)
3236 * - which can be user-defined (via MODULE_PARAM)
3237 * - Hardware queue count (num_*_queues)
3238 * - defined by miscellaneous hardware support/features (RSS, etc.)
3239 **/
2f90b865 3240int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 3241{
3242 int err;
3243
3244 /* Number of supported queues */
3245 ixgbe_set_num_queues(adapter);
3246
021230d4
AV		 3247 err = ixgbe_set_interrupt_capability(adapter);
3248 if (err) {
3249 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
3250 goto err_set_interrupt;
9a799d71
AK		 3251 }
3252
7a921c93
AD		 3253 err = ixgbe_alloc_q_vectors(adapter);
3254 if (err) {
3255 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
3256 "vectors\n");
3257 goto err_alloc_q_vectors;
3258 }
3259
3260 err = ixgbe_alloc_queues(adapter);
3261 if (err) {
3262 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
3263 goto err_alloc_queues;
3264 }
3265
021230d4 3266 DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
b4617240
PW		 3267 "Tx Queue count = %u\n",
3268 (adapter->num_rx_queues > 1) ? "Enabled" :
3269 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 3270
3271 set_bit(__IXGBE_DOWN, &adapter->state);
3272
9a799d71 3273 return 0;
021230d4 3274
7a921c93
AD		 3275err_alloc_queues:
3276 ixgbe_free_q_vectors(adapter);
3277err_alloc_q_vectors:
3278 ixgbe_reset_interrupt_capability(adapter);
021230d4 3279err_set_interrupt:
7a921c93
AD		 3280 return err;
3281}
3282
3283/**
3284 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
3285 * @adapter: board private structure to clear interrupt scheme on
3286 *
3287 * We go through and clear interrupt specific resources and reset the structure
3288 * to pre-load conditions
3289 **/
3290void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
3291{
021230d4
AV		 3292 kfree(adapter->tx_ring);
3293 kfree(adapter->rx_ring);
7a921c93
AD		 3294 adapter->tx_ring = NULL;
3295 adapter->rx_ring = NULL;
3296
3297 ixgbe_free_q_vectors(adapter);
3298 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 3299}
3300
c4900be0
DS		 3301/**
3302 * ixgbe_sfp_timer - worker thread to find a missing module
3303 * @data: pointer to our adapter struct
3304 **/
3305static void ixgbe_sfp_timer(unsigned long data)
3306{
3307 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3308
4df10466
JB		 3309 /*
3310 * Do the sfp_timer outside of interrupt context due to the
c4900be0
DS		 3311 * delays that sfp+ detection requires
3312 */
3313 schedule_work(&adapter->sfp_task);
3314}
3315
3316/**
3317 * ixgbe_sfp_task - worker thread to find a missing module
3318 * @work: pointer to work_struct containing our data
3319 **/
3320static void ixgbe_sfp_task(struct work_struct *work)
3321{
3322 struct ixgbe_adapter *adapter = container_of(work,
3323 struct ixgbe_adapter,
3324 sfp_task);
3325 struct ixgbe_hw *hw = &adapter->hw;
3326
3327 if ((hw->phy.type == ixgbe_phy_nl) &&
3328 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
3329 s32 ret = hw->phy.ops.identify_sfp(hw);
3330 if (ret)
3331 goto reschedule;
3332 ret = hw->phy.ops.reset(hw);
3333 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3334 DPRINTK(PROBE, ERR, "failed to initialize because an "
3335 "unsupported SFP+ module type was detected.\n"
3336 "Reload the driver after installing a "
3337 "supported module.\n");
3338 unregister_netdev(adapter->netdev);
3339 } else {
3340 DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
3341 hw->phy.sfp_type);
3342 }
3343 /* don't need this routine any more */
3344 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3345 }
3346 return;
3347reschedule:
3348 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
3349 mod_timer(&adapter->sfp_timer,
3350 round_jiffies(jiffies + (2 * HZ)));
3351}
3352
9a799d71
AK		 3353/**
3354 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
3355 * @adapter: board private structure to initialize
3356 *
3357 * ixgbe_sw_init initializes the Adapter private data structure.
3358 * Fields are initialized based on PCI device information and
3359 * OS network device settings (MTU size).
3360 **/
3361static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
3362{
3363 struct ixgbe_hw *hw = &adapter->hw;
3364 struct pci_dev *pdev = adapter->pdev;
021230d4 3365 unsigned int rss;
7a6b6f51 3366#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3367 int j;
3368 struct tc_configuration *tc;
3369#endif
021230d4 3370
c44ade9e
JB		 3371 /* PCI config space info */
3372
3373 hw->vendor_id = pdev->vendor;
3374 hw->device_id = pdev->device;
3375 hw->revision_id = pdev->revision;
3376 hw->subsystem_vendor_id = pdev->subsystem_vendor;
3377 hw->subsystem_device_id = pdev->subsystem_device;
3378
021230d4
AV		 3379 /* Set capability flags */
3380 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
3381 adapter->ring_feature[RING_F_RSS].indices = rss;
3382 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
2f90b865 3383 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
e8e26350
PW		 3384 if (hw->mac.type == ixgbe_mac_82598EB)
3385 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
f8212f97 3386 else if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 3387 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
f8212f97
AD		 3388 adapter->flags |= IXGBE_FLAG_RSC_CAPABLE;
3389 adapter->flags |= IXGBE_FLAG_RSC_ENABLED;
3390 }
2f90b865 3391
7a6b6f51 3392#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3393 /* Configure DCB traffic classes */
3394 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
3395 tc = &adapter->dcb_cfg.tc_config[j];
3396 tc->path[DCB_TX_CONFIG].bwg_id = 0;
3397 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
3398 tc->path[DCB_RX_CONFIG].bwg_id = 0;
3399 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
3400 tc->dcb_pfc = pfc_disabled;
3401 }
3402 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
3403 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
3404 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
3405 adapter->dcb_cfg.round_robin_enable = false;
3406 adapter->dcb_set_bitmap = 0x00;
3407 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
3408 adapter->ring_feature[RING_F_DCB].indices);
3409
3410#endif
9a799d71
AK		 3411
3412 /* default flow control settings */
cd7664f6 3413 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 3414 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
2b9ade93
JB		 3415 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
3416 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
3417 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
3418 hw->fc.send_xon = true;
71fd570b 3419 hw->fc.disable_fc_autoneg = false;
9a799d71 3420
30efa5a3
JB		 3421 /* enable itr by default in dynamic mode */
3422 adapter->itr_setting = 1;
3423 adapter->eitr_param = 20000;
3424
3425 /* set defaults for eitr in MegaBytes */
3426 adapter->eitr_low = 10;
3427 adapter->eitr_high = 20;
3428
3429 /* set default ring sizes */
3430 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
3431 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
3432
9a799d71 3433 /* initialize eeprom parameters */
c44ade9e 3434 if (ixgbe_init_eeprom_params_generic(hw)) {
9a799d71
AK		 3435 dev_err(&pdev->dev, "EEPROM initialization failed\n");
3436 return -EIO;
3437 }
3438
021230d4 3439 /* enable rx csum by default */
9a799d71
AK		 3440 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
3441
9a799d71
AK		 3442 set_bit(__IXGBE_DOWN, &adapter->state);
3443
3444 return 0;
3445}
3446
3447/**
3448 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3449 * @adapter: board private structure
3a581073 3450 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 3451 *
3452 * Return 0 on success, negative on failure
3453 **/
3454int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
e01c31a5 3455 struct ixgbe_ring *tx_ring)
9a799d71
AK		 3456{
3457 struct pci_dev *pdev = adapter->pdev;
3458 int size;
3459
3a581073
JB		 3460 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3461 tx_ring->tx_buffer_info = vmalloc(size);
e01c31a5
JB		 3462 if (!tx_ring->tx_buffer_info)
3463 goto err;
3a581073 3464 memset(tx_ring->tx_buffer_info, 0, size);
9a799d71
AK		 3465
3466 /* round up to nearest 4K */
12207e49 3467 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 3468 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 3469
3a581073
JB		 3470 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
3471 &tx_ring->dma);
e01c31a5
JB		 3472 if (!tx_ring->desc)
3473 goto err;
9a799d71 3474
3a581073
JB		 3475 tx_ring->next_to_use = 0;
3476 tx_ring->next_to_clean = 0;
3477 tx_ring->work_limit = tx_ring->count;
9a799d71 3478 return 0;
e01c31a5
JB		 3479
3480err:
3481 vfree(tx_ring->tx_buffer_info);
3482 tx_ring->tx_buffer_info = NULL;
3483 DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
3484 "descriptor ring\n");
3485 return -ENOMEM;
9a799d71
AK		 3486}
3487
69888674
AD		 3488/**
3489 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
3490 * @adapter: board private structure
3491 *
3492 * If this function returns with an error, then it's possible one or
3493 * more of the rings is populated (while the rest are not). It is the
3494 * callers duty to clean those orphaned rings.
3495 *
3496 * Return 0 on success, negative on failure
3497 **/
3498static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
3499{
3500 int i, err = 0;
3501
3502 for (i = 0; i < adapter->num_tx_queues; i++) {
3503 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
3504 if (!err)
3505 continue;
3506 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
3507 break;
3508 }
3509
3510 return err;
3511}
3512
9a799d71
AK		 3513/**
3514 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3515 * @adapter: board private structure
3a581073 3516 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 3517 *
3518 * Returns 0 on success, negative on failure
3519 **/
3520int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
b4617240 3521 struct ixgbe_ring *rx_ring)
9a799d71
AK		 3522{
3523 struct pci_dev *pdev = adapter->pdev;
021230d4 3524 int size;
9a799d71 3525
3a581073
JB		 3526 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3527 rx_ring->rx_buffer_info = vmalloc(size);
3528 if (!rx_ring->rx_buffer_info) {
9a799d71 3529 DPRINTK(PROBE, ERR,
b4617240 3530 "vmalloc allocation failed for the rx desc ring\n");
177db6ff 3531 goto alloc_failed;
9a799d71 3532 }
3a581073 3533 memset(rx_ring->rx_buffer_info, 0, size);
9a799d71 3534
9a799d71 3535 /* Round up to nearest 4K */
3a581073
JB		 3536 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
3537 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 3538
3a581073 3539 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
9a799d71 3540
3a581073 3541 if (!rx_ring->desc) {
9a799d71 3542 DPRINTK(PROBE, ERR,
b4617240 3543 "Memory allocation failed for the rx desc ring\n");
3a581073 3544 vfree(rx_ring->rx_buffer_info);
177db6ff 3545 goto alloc_failed;
9a799d71
AK		 3546 }
3547
3a581073
JB		 3548 rx_ring->next_to_clean = 0;
3549 rx_ring->next_to_use = 0;
9a799d71
AK		 3550
3551 return 0;
177db6ff
MC		 3552
3553alloc_failed:
177db6ff 3554 return -ENOMEM;
9a799d71
AK		 3555}
3556
69888674
AD		 3557/**
3558 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
3559 * @adapter: board private structure
3560 *
3561 * If this function returns with an error, then it's possible one or
3562 * more of the rings is populated (while the rest are not). It is the
3563 * callers duty to clean those orphaned rings.
3564 *
3565 * Return 0 on success, negative on failure
3566 **/
3567
3568static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
3569{
3570 int i, err = 0;
3571
3572 for (i = 0; i < adapter->num_rx_queues; i++) {
3573 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
3574 if (!err)
3575 continue;
3576 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
3577 break;
3578 }
3579
3580 return err;
3581}
3582
9a799d71
AK		 3583/**
3584 * ixgbe_free_tx_resources - Free Tx Resources per Queue
3585 * @adapter: board private structure
3586 * @tx_ring: Tx descriptor ring for a specific queue
3587 *
3588 * Free all transmit software resources
3589 **/
c431f97e
JB		 3590void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
3591 struct ixgbe_ring *tx_ring)
9a799d71
AK		 3592{
3593 struct pci_dev *pdev = adapter->pdev;
3594
3595 ixgbe_clean_tx_ring(adapter, tx_ring);
3596
3597 vfree(tx_ring->tx_buffer_info);
3598 tx_ring->tx_buffer_info = NULL;
3599
3600 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
3601
3602 tx_ring->desc = NULL;
3603}
3604
3605/**
3606 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
3607 * @adapter: board private structure
3608 *
3609 * Free all transmit software resources
3610 **/
3611static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
3612{
3613 int i;
3614
3615 for (i = 0; i < adapter->num_tx_queues; i++)
9891ca7c
JB		 3616 if (adapter->tx_ring[i].desc)
3617 ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
9a799d71
AK		 3618}
3619
3620/**
b4617240 3621 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 3622 * @adapter: board private structure
3623 * @rx_ring: ring to clean the resources from
3624 *
3625 * Free all receive software resources
3626 **/
c431f97e
JB		 3627void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
3628 struct ixgbe_ring *rx_ring)
9a799d71
AK		 3629{
3630 struct pci_dev *pdev = adapter->pdev;
3631
3632 ixgbe_clean_rx_ring(adapter, rx_ring);
3633
3634 vfree(rx_ring->rx_buffer_info);
3635 rx_ring->rx_buffer_info = NULL;
3636
3637 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
3638
3639 rx_ring->desc = NULL;
3640}
3641
3642/**
3643 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
3644 * @adapter: board private structure
3645 *
3646 * Free all receive software resources
3647 **/
3648static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
3649{
3650 int i;
3651
3652 for (i = 0; i < adapter->num_rx_queues; i++)
9891ca7c
JB		 3653 if (adapter->rx_ring[i].desc)
3654 ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
9a799d71
AK		 3655}
3656
9a799d71
AK		 3657/**
3658 * ixgbe_change_mtu - Change the Maximum Transfer Unit
3659 * @netdev: network interface device structure
3660 * @new_mtu: new value for maximum frame size
3661 *
3662 * Returns 0 on success, negative on failure
3663 **/
3664static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
3665{
3666 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3667 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3668
42c783c5
JB		 3669 /* MTU < 68 is an error and causes problems on some kernels */
3670 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
9a799d71
AK		 3671 return -EINVAL;
3672
021230d4 3673 DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
b4617240 3674 netdev->mtu, new_mtu);
021230d4 3675 /* must set new MTU before calling down or up */
9a799d71
AK		 3676 netdev->mtu = new_mtu;
3677
d4f80882
AV		 3678 if (netif_running(netdev))
3679 ixgbe_reinit_locked(adapter);
9a799d71
AK		 3680
3681 return 0;
3682}
3683
3684/**
3685 * ixgbe_open - Called when a network interface is made active
3686 * @netdev: network interface device structure
3687 *
3688 * Returns 0 on success, negative value on failure
3689 *
3690 * The open entry point is called when a network interface is made
3691 * active by the system (IFF_UP). At this point all resources needed
3692 * for transmit and receive operations are allocated, the interrupt
3693 * handler is registered with the OS, the watchdog timer is started,
3694 * and the stack is notified that the interface is ready.
3695 **/
3696static int ixgbe_open(struct net_device *netdev)
3697{
3698 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3699 int err;
4bebfaa5
AK		 3700
3701 /* disallow open during test */
3702 if (test_bit(__IXGBE_TESTING, &adapter->state))
3703 return -EBUSY;
9a799d71 3704
54386467
JB		 3705 netif_carrier_off(netdev);
3706
9a799d71
AK		 3707 /* allocate transmit descriptors */
3708 err = ixgbe_setup_all_tx_resources(adapter);
3709 if (err)
3710 goto err_setup_tx;
3711
9a799d71
AK		 3712 /* allocate receive descriptors */
3713 err = ixgbe_setup_all_rx_resources(adapter);
3714 if (err)
3715 goto err_setup_rx;
3716
3717 ixgbe_configure(adapter);
3718
021230d4 3719 err = ixgbe_request_irq(adapter);
9a799d71
AK		 3720 if (err)
3721 goto err_req_irq;
3722
9a799d71
AK		 3723 err = ixgbe_up_complete(adapter);
3724 if (err)
3725 goto err_up;
3726
d55b53ff
JK		 3727 netif_tx_start_all_queues(netdev);
3728
9a799d71
AK		 3729 return 0;
3730
3731err_up:
5eba3699 3732 ixgbe_release_hw_control(adapter);
9a799d71
AK		 3733 ixgbe_free_irq(adapter);
3734err_req_irq:
9a799d71 3735err_setup_rx:
a20a1199 3736 ixgbe_free_all_rx_resources(adapter);
9a799d71 3737err_setup_tx:
a20a1199 3738 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 3739 ixgbe_reset(adapter);
3740
3741 return err;
3742}
3743
3744/**
3745 * ixgbe_close - Disables a network interface
3746 * @netdev: network interface device structure
3747 *
3748 * Returns 0, this is not allowed to fail
3749 *
3750 * The close entry point is called when an interface is de-activated
3751 * by the OS. The hardware is still under the drivers control, but
3752 * needs to be disabled. A global MAC reset is issued to stop the
3753 * hardware, and all transmit and receive resources are freed.
3754 **/
3755static int ixgbe_close(struct net_device *netdev)
3756{
3757 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 3758
3759 ixgbe_down(adapter);
3760 ixgbe_free_irq(adapter);
3761
3762 ixgbe_free_all_tx_resources(adapter);
3763 ixgbe_free_all_rx_resources(adapter);
3764
5eba3699 3765 ixgbe_release_hw_control(adapter);
9a799d71
AK		 3766
3767 return 0;
3768}
3769
b3c8b4ba
AD		 3770#ifdef CONFIG_PM
3771static int ixgbe_resume(struct pci_dev *pdev)
3772{
3773 struct net_device *netdev = pci_get_drvdata(pdev);
3774 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3775 u32 err;
3776
3777 pci_set_power_state(pdev, PCI_D0);
3778 pci_restore_state(pdev);
9ce77666 3779
3780 err = pci_enable_device_mem(pdev);
b3c8b4ba 3781 if (err) {
69888674 3782 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
b3c8b4ba
AD		 3783 "suspend\n");
3784 return err;
3785 }
3786 pci_set_master(pdev);
3787
dd4d8ca6 3788 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 3789
3790 err = ixgbe_init_interrupt_scheme(adapter);
3791 if (err) {
3792 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
3793 "device\n");
3794 return err;
3795 }
3796
b3c8b4ba
AD		 3797 ixgbe_reset(adapter);
3798
495dce12
WJP		 3799 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
3800
b3c8b4ba
AD		 3801 if (netif_running(netdev)) {
3802 err = ixgbe_open(adapter->netdev);
3803 if (err)
3804 return err;
3805 }
3806
3807 netif_device_attach(netdev);
3808
3809 return 0;
3810}
b3c8b4ba 3811#endif /* CONFIG_PM */
9d8d05ae
RW		 3812
3813static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba
AD		 3814{
3815 struct net_device *netdev = pci_get_drvdata(pdev);
3816 struct ixgbe_adapter *adapter = netdev_priv(netdev);
e8e26350
PW		 3817 struct ixgbe_hw *hw = &adapter->hw;
3818 u32 ctrl, fctrl;
3819 u32 wufc = adapter->wol;
b3c8b4ba
AD		 3820#ifdef CONFIG_PM
3821 int retval = 0;
3822#endif
3823
3824 netif_device_detach(netdev);
3825
3826 if (netif_running(netdev)) {
3827 ixgbe_down(adapter);
3828 ixgbe_free_irq(adapter);
3829 ixgbe_free_all_tx_resources(adapter);
3830 ixgbe_free_all_rx_resources(adapter);
3831 }
7a921c93 3832 ixgbe_clear_interrupt_scheme(adapter);
b3c8b4ba
AD		 3833
3834#ifdef CONFIG_PM
3835 retval = pci_save_state(pdev);
3836 if (retval)
3837 return retval;
4df10466 3838
b3c8b4ba 3839#endif
e8e26350
PW		 3840 if (wufc) {
3841 ixgbe_set_rx_mode(netdev);
b3c8b4ba 3842
e8e26350
PW		 3843 /* turn on all-multi mode if wake on multicast is enabled */
3844 if (wufc & IXGBE_WUFC_MC) {
3845 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3846 fctrl |= IXGBE_FCTRL_MPE;
3847 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3848 }
3849
3850 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
3851 ctrl |= IXGBE_CTRL_GIO_DIS;
3852 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
3853
3854 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
3855 } else {
3856 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
3857 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
3858 }
3859
dd4d8ca6
DS		 3860 if (wufc && hw->mac.type == ixgbe_mac_82599EB)
3861 pci_wake_from_d3(pdev, true);
3862 else
3863 pci_wake_from_d3(pdev, false);
b3c8b4ba 3864
9d8d05ae
RW		 3865 *enable_wake = !!wufc;
3866
b3c8b4ba
AD		 3867 ixgbe_release_hw_control(adapter);
3868
3869 pci_disable_device(pdev);
3870
9d8d05ae
RW		 3871 return 0;
3872}
3873
3874#ifdef CONFIG_PM
3875static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
3876{
3877 int retval;
3878 bool wake;
3879
3880 retval = __ixgbe_shutdown(pdev, &wake);
3881 if (retval)
3882 return retval;
3883
3884 if (wake) {
3885 pci_prepare_to_sleep(pdev);
3886 } else {
3887 pci_wake_from_d3(pdev, false);
3888 pci_set_power_state(pdev, PCI_D3hot);
3889 }
b3c8b4ba
AD		 3890
3891 return 0;
3892}
9d8d05ae 3893#endif /* CONFIG_PM */
b3c8b4ba
AD		 3894
3895static void ixgbe_shutdown(struct pci_dev *pdev)
3896{
9d8d05ae
RW		 3897 bool wake;
3898
3899 __ixgbe_shutdown(pdev, &wake);
3900
3901 if (system_state == SYSTEM_POWER_OFF) {
3902 pci_wake_from_d3(pdev, wake);
3903 pci_set_power_state(pdev, PCI_D3hot);
3904 }
b3c8b4ba
AD		 3905}
3906
9a799d71
AK		 3907/**
3908 * ixgbe_update_stats - Update the board statistics counters.
3909 * @adapter: board private structure
3910 **/
3911void ixgbe_update_stats(struct ixgbe_adapter *adapter)
3912{
3913 struct ixgbe_hw *hw = &adapter->hw;
6f11eef7
AV		 3914 u64 total_mpc = 0;
3915 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
9a799d71 3916
d51019a4 3917 if (hw->mac.type == ixgbe_mac_82599EB) {
f8212f97 3918 u64 rsc_count = 0;
d51019a4
PW		 3919 for (i = 0; i < 16; i++)
3920 adapter->hw_rx_no_dma_resources +=
3921 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
f8212f97
AD		 3922 for (i = 0; i < adapter->num_rx_queues; i++)
3923 rsc_count += adapter->rx_ring[i].rsc_count;
3924 adapter->rsc_count = rsc_count;
d51019a4
PW		 3925 }
3926
9a799d71 3927 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 3928 for (i = 0; i < 8; i++) {
3929 /* for packet buffers not used, the register should read 0 */
3930 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3931 missed_rx += mpc;
3932 adapter->stats.mpc[i] += mpc;
3933 total_mpc += adapter->stats.mpc[i];
e8e26350
PW		 3934 if (hw->mac.type == ixgbe_mac_82598EB)
3935 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2f90b865
AD		 3936 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3937 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
3938 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3939 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
e8e26350
PW		 3940 if (hw->mac.type == ixgbe_mac_82599EB) {
3941 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
3942 IXGBE_PXONRXCNT(i));
3943 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
3944 IXGBE_PXOFFRXCNT(i));
3945 adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
e8e26350
PW		 3946 } else {
3947 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
3948 IXGBE_PXONRXC(i));
3949 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
3950 IXGBE_PXOFFRXC(i));
3951 }
2f90b865
AD		 3952 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
3953 IXGBE_PXONTXC(i));
2f90b865 3954 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
e8e26350 3955 IXGBE_PXOFFTXC(i));
6f11eef7
AV		 3956 }
3957 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
3958 /* work around hardware counting issue */
3959 adapter->stats.gprc -= missed_rx;
3960
3961 /* 82598 hardware only has a 32 bit counter in the high register */
e8e26350
PW		 3962 if (hw->mac.type == ixgbe_mac_82599EB) {
3963 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3964 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
3965 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3966 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
3967 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3968 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
3969 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3970 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3971 } else {
3972 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3973 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3974 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3975 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3976 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3977 }
9a799d71
AK		 3978 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3979 adapter->stats.bprc += bprc;
3980 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350
PW		 3981 if (hw->mac.type == ixgbe_mac_82598EB)
3982 adapter->stats.mprc -= bprc;
9a799d71
AK		 3983 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3984 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3985 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3986 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3987 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3988 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3989 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
9a799d71 3990 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7
AV		 3991 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3992 adapter->stats.lxontxc += lxon;
3993 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3994 adapter->stats.lxofftxc += lxoff;
9a799d71
AK		 3995 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3996 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6f11eef7
AV		 3997 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3998 /*
3999 * 82598 errata - tx of flow control packets is included in tx counters
4000 */
4001 xon_off_tot = lxon + lxoff;
4002 adapter->stats.gptc -= xon_off_tot;
4003 adapter->stats.mptc -= xon_off_tot;
4004 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
9a799d71
AK		 4005 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4006 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
4007 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
9a799d71
AK		 4008 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
4009 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6f11eef7 4010 adapter->stats.ptc64 -= xon_off_tot;
9a799d71
AK		 4011 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
4012 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
4013 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
4014 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
4015 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
9a799d71
AK		 4016 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
4017
4018 /* Fill out the OS statistics structure */
9a799d71
AK		 4019 adapter->net_stats.multicast = adapter->stats.mprc;
4020
4021 /* Rx Errors */
4022 adapter->net_stats.rx_errors = adapter->stats.crcerrs +
b4617240 4023 adapter->stats.rlec;
9a799d71
AK		 4024 adapter->net_stats.rx_dropped = 0;
4025 adapter->net_stats.rx_length_errors = adapter->stats.rlec;
4026 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
6f11eef7 4027 adapter->net_stats.rx_missed_errors = total_mpc;
9a799d71
AK		 4028}
4029
4030/**
4031 * ixgbe_watchdog - Timer Call-back
4032 * @data: pointer to adapter cast into an unsigned long
4033 **/
4034static void ixgbe_watchdog(unsigned long data)
4035{
4036 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
cf8280ee
JB		 4037 struct ixgbe_hw *hw = &adapter->hw;
4038
4039 /* Do the watchdog outside of interrupt context due to the lovely
4040 * delays that some of the newer hardware requires */
4041 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
22d5a71b
JB		 4042 u64 eics = 0;
4043 int i;
4044
4045 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++)
4046 eics |= (1 << i);
4047
cf8280ee 4048 /* Cause software interrupt to ensure rx rings are cleaned */
22d5a71b
JB		 4049 switch (hw->mac.type) {
4050 case ixgbe_mac_82598EB:
4051 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4052 IXGBE_WRITE_REG(hw, IXGBE_EICS, (u32)eics);
4053 } else {
4054 /*
4055 * for legacy and MSI interrupts don't set any
4056 * bits that are enabled for EIAM, because this
4057 * operation would set *both* EIMS and EICS for
4058 * any bit in EIAM
4059 */
4060 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4061 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4062 }
4063 break;
4064 case ixgbe_mac_82599EB:
4065 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
835462fc
NS		 4066 IXGBE_WRITE_REG(hw, IXGBE_EICS_EX(0),
4067 (u32)(eics & 0xFFFFFFFF));
22d5a71b 4068 IXGBE_WRITE_REG(hw, IXGBE_EICS_EX(1),
22d5a71b
JB		 4069 (u32)(eics >> 32));
4070 } else {
4071 /*
4072 * for legacy and MSI interrupts don't set any
4073 * bits that are enabled for EIAM, because this
4074 * operation would set *both* EIMS and EICS for
4075 * any bit in EIAM
4076 */
4077 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4078 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4079 }
4080 break;
4081 default:
4082 break;
cf8280ee
JB		 4083 }
4084 /* Reset the timer */
4085 mod_timer(&adapter->watchdog_timer,
4086 round_jiffies(jiffies + 2 * HZ));
4087 }
9a799d71 4088
cf8280ee
JB		 4089 schedule_work(&adapter->watchdog_task);
4090}
4091
e8e26350
PW		 4092/**
4093 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
4094 * @work: pointer to work_struct containing our data
4095 **/
4096static void ixgbe_multispeed_fiber_task(struct work_struct *work)
4097{
4098 struct ixgbe_adapter *adapter = container_of(work,
4099 struct ixgbe_adapter,
4100 multispeed_fiber_task);
4101 struct ixgbe_hw *hw = &adapter->hw;
4102 u32 autoneg;
4103
4104 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
4105 if (hw->mac.ops.get_link_capabilities)
4106 hw->mac.ops.get_link_capabilities(hw, &autoneg,
4107 &hw->mac.autoneg);
4108 if (hw->mac.ops.setup_link_speed)
4109 hw->mac.ops.setup_link_speed(hw, autoneg, true, true);
4110 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4111 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
4112}
4113
4114/**
4115 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
4116 * @work: pointer to work_struct containing our data
4117 **/
4118static void ixgbe_sfp_config_module_task(struct work_struct *work)
4119{
4120 struct ixgbe_adapter *adapter = container_of(work,
4121 struct ixgbe_adapter,
4122 sfp_config_module_task);
4123 struct ixgbe_hw *hw = &adapter->hw;
4124 u32 err;
4125
4126 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
4127 err = hw->phy.ops.identify_sfp(hw);
4128 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4129 DPRINTK(PROBE, ERR, "PHY not supported on this NIC %d\n", err);
4130 ixgbe_down(adapter);
4131 return;
4132 }
4133 hw->mac.ops.setup_sfp(hw);
4134
8d1c3c07 4135 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
e8e26350
PW		 4136 /* This will also work for DA Twinax connections */
4137 schedule_work(&adapter->multispeed_fiber_task);
4138 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
4139}
4140
cf8280ee 4141/**
69888674
AD		 4142 * ixgbe_watchdog_task - worker thread to bring link up
4143 * @work: pointer to work_struct containing our data
cf8280ee
JB		 4144 **/
4145static void ixgbe_watchdog_task(struct work_struct *work)
4146{
4147 struct ixgbe_adapter *adapter = container_of(work,
4148 struct ixgbe_adapter,
4149 watchdog_task);
4150 struct net_device *netdev = adapter->netdev;
4151 struct ixgbe_hw *hw = &adapter->hw;
4152 u32 link_speed = adapter->link_speed;
4153 bool link_up = adapter->link_up;
bc59fcda
NS		 4154 int i;
4155 struct ixgbe_ring *tx_ring;
4156 int some_tx_pending = 0;
cf8280ee
JB		 4157
4158 adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
4159
4160 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4161 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
4162 if (link_up ||
4163 time_after(jiffies, (adapter->link_check_timeout +
4164 IXGBE_TRY_LINK_TIMEOUT))) {
4165 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
4166 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4167 }
4168 adapter->link_up = link_up;
4169 adapter->link_speed = link_speed;
4170 }
9a799d71
AK		 4171
4172 if (link_up) {
4173 if (!netif_carrier_ok(netdev)) {
e8e26350
PW		 4174 bool flow_rx, flow_tx;
4175
4176 if (hw->mac.type == ixgbe_mac_82599EB) {
4177 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4178 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4179 flow_rx = (mflcn & IXGBE_MFLCN_RFCE);
4180 flow_tx = (fccfg & IXGBE_FCCFG_TFCE_802_3X);
4181 } else {
4182 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4183 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
4184 flow_rx = (frctl & IXGBE_FCTRL_RFCE);
4185 flow_tx = (rmcs & IXGBE_RMCS_TFCE_802_3X);
4186 }
4187
a46e534b
JK		 4188 printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
4189 "Flow Control: %s\n",
4190 netdev->name,
4191 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
4192 "10 Gbps" :
4193 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
4194 "1 Gbps" : "unknown speed")),
e8e26350
PW		 4195 ((flow_rx && flow_tx) ? "RX/TX" :
4196 (flow_rx ? "RX" :
4197 (flow_tx ? "TX" : "None"))));
9a799d71
AK		 4198
4199 netif_carrier_on(netdev);
9a799d71
AK		 4200 } else {
4201 /* Force detection of hung controller */
4202 adapter->detect_tx_hung = true;
4203 }
4204 } else {
cf8280ee
JB		 4205 adapter->link_up = false;
4206 adapter->link_speed = 0;
9a799d71 4207 if (netif_carrier_ok(netdev)) {
a46e534b
JK		 4208 printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
4209 netdev->name);
9a799d71 4210 netif_carrier_off(netdev);
9a799d71
AK		 4211 }
4212 }
4213
bc59fcda
NS		 4214 if (!netif_carrier_ok(netdev)) {
4215 for (i = 0; i < adapter->num_tx_queues; i++) {
4216 tx_ring = &adapter->tx_ring[i];
4217 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
4218 some_tx_pending = 1;
4219 break;
4220 }
4221 }
4222
4223 if (some_tx_pending) {
4224 /* We've lost link, so the controller stops DMA,
4225 * but we've got queued Tx work that's never going
4226 * to get done, so reset controller to flush Tx.
4227 * (Do the reset outside of interrupt context).
4228 */
4229 schedule_work(&adapter->reset_task);
4230 }
4231 }
4232
9a799d71 4233 ixgbe_update_stats(adapter);
cf8280ee 4234 adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
9a799d71
AK		 4235}
4236
9a799d71 4237static int ixgbe_tso(struct ixgbe_adapter *adapter,
b4617240
PW		 4238 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
4239 u32 tx_flags, u8 *hdr_len)
9a799d71
AK		 4240{
4241 struct ixgbe_adv_tx_context_desc *context_desc;
4242 unsigned int i;
4243 int err;
4244 struct ixgbe_tx_buffer *tx_buffer_info;
9f8cdf4f
JB		 4245 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
4246 u32 mss_l4len_idx, l4len;
9a799d71
AK		 4247
4248 if (skb_is_gso(skb)) {
4249 if (skb_header_cloned(skb)) {
4250 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4251 if (err)
4252 return err;
4253 }
4254 l4len = tcp_hdrlen(skb);
4255 *hdr_len += l4len;
4256
8327d000 4257 if (skb->protocol == htons(ETH_P_IP)) {
9a799d71
AK		 4258 struct iphdr *iph = ip_hdr(skb);
4259 iph->tot_len = 0;
4260 iph->check = 0;
4261 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b4617240
PW		 4262 iph->daddr, 0,
4263 IPPROTO_TCP,
4264 0);
9a799d71
AK		 4265 adapter->hw_tso_ctxt++;
4266 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
4267 ipv6_hdr(skb)->payload_len = 0;
4268 tcp_hdr(skb)->check =
4269 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
b4617240
PW		 4270 &ipv6_hdr(skb)->daddr,
4271 0, IPPROTO_TCP, 0);
9a799d71
AK		 4272 adapter->hw_tso6_ctxt++;
4273 }
4274
4275 i = tx_ring->next_to_use;
4276
4277 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4278 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4279
4280 /* VLAN MACLEN IPLEN */
4281 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4282 vlan_macip_lens |=
4283 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4284 vlan_macip_lens |= ((skb_network_offset(skb)) <<
b4617240 4285 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 4286 *hdr_len += skb_network_offset(skb);
4287 vlan_macip_lens |=
4288 (skb_transport_header(skb) - skb_network_header(skb));
4289 *hdr_len +=
4290 (skb_transport_header(skb) - skb_network_header(skb));
4291 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4292 context_desc->seqnum_seed = 0;
4293
4294 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
9f8cdf4f 4295 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
b4617240 4296 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 4297
8327d000 4298 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 4299 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4300 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
4301 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4302
4303 /* MSS L4LEN IDX */
9f8cdf4f 4304 mss_l4len_idx =
9a799d71
AK		 4305 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
4306 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4eeae6fd
PW		 4307 /* use index 1 for TSO */
4308 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 4309 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4310
4311 tx_buffer_info->time_stamp = jiffies;
4312 tx_buffer_info->next_to_watch = i;
4313
4314 i++;
4315 if (i == tx_ring->count)
4316 i = 0;
4317 tx_ring->next_to_use = i;
4318
4319 return true;
4320 }
4321 return false;
4322}
4323
4324static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
b4617240
PW		 4325 struct ixgbe_ring *tx_ring,
4326 struct sk_buff *skb, u32 tx_flags)
9a799d71
AK		 4327{
4328 struct ixgbe_adv_tx_context_desc *context_desc;
4329 unsigned int i;
4330 struct ixgbe_tx_buffer *tx_buffer_info;
4331 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
4332
4333 if (skb->ip_summed == CHECKSUM_PARTIAL ||
4334 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
4335 i = tx_ring->next_to_use;
4336 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4337 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4338
4339 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4340 vlan_macip_lens |=
4341 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4342 vlan_macip_lens |= (skb_network_offset(skb) <<
b4617240 4343 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 4344 if (skb->ip_summed == CHECKSUM_PARTIAL)
4345 vlan_macip_lens |= (skb_transport_header(skb) -
b4617240 4346 skb_network_header(skb));
9a799d71
AK		 4347
4348 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4349 context_desc->seqnum_seed = 0;
4350
4351 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
b4617240 4352 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71
AK		 4353
4354 if (skb->ip_summed == CHECKSUM_PARTIAL) {
41825d71 4355 switch (skb->protocol) {
09640e63 4356 case cpu_to_be16(ETH_P_IP):
9a799d71 4357 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
41825d71
AK		 4358 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4359 type_tucmd_mlhl |=
b4617240 4360 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 4361 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
4362 type_tucmd_mlhl |=
4363 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 4364 break;
09640e63 4365 case cpu_to_be16(ETH_P_IPV6):
41825d71
AK		 4366 /* XXX what about other V6 headers?? */
4367 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4368 type_tucmd_mlhl |=
b4617240 4369 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 4370 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
4371 type_tucmd_mlhl |=
4372 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 4373 break;
41825d71
AK		 4374 default:
4375 if (unlikely(net_ratelimit())) {
4376 DPRINTK(PROBE, WARNING,
4377 "partial checksum but proto=%x!\n",
4378 skb->protocol);
4379 }
4380 break;
4381 }
9a799d71
AK		 4382 }
4383
4384 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4eeae6fd 4385 /* use index zero for tx checksum offload */
9a799d71
AK		 4386 context_desc->mss_l4len_idx = 0;
4387
4388 tx_buffer_info->time_stamp = jiffies;
4389 tx_buffer_info->next_to_watch = i;
9f8cdf4f 4390
9a799d71
AK		 4391 adapter->hw_csum_tx_good++;
4392 i++;
4393 if (i == tx_ring->count)
4394 i = 0;
4395 tx_ring->next_to_use = i;
4396
4397 return true;
4398 }
9f8cdf4f 4399
9a799d71
AK		 4400 return false;
4401}
4402
4403static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
b4617240
PW		 4404 struct ixgbe_ring *tx_ring,
4405 struct sk_buff *skb, unsigned int first)
9a799d71
AK		 4406{
4407 struct ixgbe_tx_buffer *tx_buffer_info;
44df32c5 4408 unsigned int len = skb_headlen(skb);
9a799d71
AK		 4409 unsigned int offset = 0, size, count = 0, i;
4410 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
4411 unsigned int f;
44df32c5 4412 dma_addr_t *map;
9a799d71
AK		 4413
4414 i = tx_ring->next_to_use;
4415
44df32c5
AD		 4416 if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
4417 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
4418 return 0;
4419 }
4420
4421 map = skb_shinfo(skb)->dma_maps;
4422
9a799d71
AK		 4423 while (len) {
4424 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4425 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4426
4427 tx_buffer_info->length = size;
44df32c5 4428 tx_buffer_info->dma = map[0] + offset;
9a799d71
AK		 4429 tx_buffer_info->time_stamp = jiffies;
4430 tx_buffer_info->next_to_watch = i;
4431
4432 len -= size;
4433 offset += size;
4434 count++;
44df32c5
AD		 4435
4436 if (len) {
4437 i++;
4438 if (i == tx_ring->count)
4439 i = 0;
4440 }
9a799d71
AK		 4441 }
4442
4443 for (f = 0; f < nr_frags; f++) {
4444 struct skb_frag_struct *frag;
4445
4446 frag = &skb_shinfo(skb)->frags[f];
4447 len = frag->size;
44df32c5 4448 offset = 0;
9a799d71
AK		 4449
4450 while (len) {
44df32c5
AD		 4451 i++;
4452 if (i == tx_ring->count)
4453 i = 0;
4454
9a799d71
AK		 4455 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4456 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4457
4458 tx_buffer_info->length = size;
44df32c5 4459 tx_buffer_info->dma = map[f + 1] + offset;
9a799d71
AK		 4460 tx_buffer_info->time_stamp = jiffies;
4461 tx_buffer_info->next_to_watch = i;
4462
4463 len -= size;
4464 offset += size;
4465 count++;
9a799d71
AK		 4466 }
4467 }
44df32c5 4468
9a799d71
AK		 4469 tx_ring->tx_buffer_info[i].skb = skb;
4470 tx_ring->tx_buffer_info[first].next_to_watch = i;
4471
4472 return count;
4473}
4474
4475static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
b4617240
PW		 4476 struct ixgbe_ring *tx_ring,
4477 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 4478{
4479 union ixgbe_adv_tx_desc *tx_desc = NULL;
4480 struct ixgbe_tx_buffer *tx_buffer_info;
4481 u32 olinfo_status = 0, cmd_type_len = 0;
4482 unsigned int i;
4483 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
4484
4485 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
4486
4487 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
4488
4489 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4490 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
4491
4492 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
4493 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
4494
4495 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 4496 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 4497
4eeae6fd
PW		 4498 /* use index 1 context for tso */
4499 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 4500 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
4501 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
b4617240 4502 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 4503
4504 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
4505 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 4506 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 4507
4508 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
4509
4510 i = tx_ring->next_to_use;
4511 while (count--) {
4512 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4513 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
4514 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
4515 tx_desc->read.cmd_type_len =
b4617240 4516 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71 4517 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
9a799d71
AK		 4518 i++;
4519 if (i == tx_ring->count)
4520 i = 0;
4521 }
4522
4523 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
4524
4525 /*
4526 * Force memory writes to complete before letting h/w
4527 * know there are new descriptors to fetch. (Only
4528 * applicable for weak-ordered memory model archs,
4529 * such as IA-64).
4530 */
4531 wmb();
4532
4533 tx_ring->next_to_use = i;
4534 writel(i, adapter->hw.hw_addr + tx_ring->tail);
4535}
4536
e092be60 4537static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 4538 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 4539{
4540 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4541
30eba97a 4542 netif_stop_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 4543 /* Herbert's original patch had:
4544 * smp_mb__after_netif_stop_queue();
4545 * but since that doesn't exist yet, just open code it. */
4546 smp_mb();
4547
4548 /* We need to check again in a case another CPU has just
4549 * made room available. */
4550 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
4551 return -EBUSY;
4552
4553 /* A reprieve! - use start_queue because it doesn't call schedule */
af72166f 4554 netif_start_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 4555 ++adapter->restart_queue;
4556 return 0;
4557}
4558
4559static int ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 4560 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 4561{
4562 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
4563 return 0;
4564 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
4565}
4566
09a3b1f8
SH		 4567static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
4568{
4569 struct ixgbe_adapter *adapter = netdev_priv(dev);
4570
4571 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
4572 return 0; /* All traffic should default to class 0 */
4573
4574 return skb_tx_hash(dev, skb);
4575}
4576
9a799d71
AK		 4577static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
4578{
4579 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4580 struct ixgbe_ring *tx_ring;
9a799d71
AK		 4581 unsigned int first;
4582 unsigned int tx_flags = 0;
30eba97a
AV		 4583 u8 hdr_len = 0;
4584 int r_idx = 0, tso;
9a799d71
AK		 4585 int count = 0;
4586 unsigned int f;
9f8cdf4f 4587
95615d90 4588 r_idx = skb->queue_mapping;
30eba97a 4589 tx_ring = &adapter->tx_ring[r_idx];
9a799d71 4590
9f8cdf4f
JB		 4591 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
4592 tx_flags |= vlan_tx_tag_get(skb);
2f90b865
AD		 4593 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4594 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
4595 tx_flags |= (skb->queue_mapping << 13);
4596 }
4597 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
4598 tx_flags |= IXGBE_TX_FLAGS_VLAN;
4599 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4600 tx_flags |= (skb->queue_mapping << 13);
9f8cdf4f
JB		 4601 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
4602 tx_flags |= IXGBE_TX_FLAGS_VLAN;
9a799d71 4603 }
9f8cdf4f
JB		 4604 /* three things can cause us to need a context descriptor */
4605 if (skb_is_gso(skb) ||
4606 (skb->ip_summed == CHECKSUM_PARTIAL) ||
4607 (tx_flags & IXGBE_TX_FLAGS_VLAN))
9a799d71
AK		 4608 count++;
4609
9f8cdf4f
JB		 4610 count += TXD_USE_COUNT(skb_headlen(skb));
4611 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
9a799d71
AK		 4612 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
4613
e092be60 4614 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
9a799d71 4615 adapter->tx_busy++;
9a799d71
AK		 4616 return NETDEV_TX_BUSY;
4617 }
9a799d71 4618
8327d000 4619 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 4620 tx_flags |= IXGBE_TX_FLAGS_IPV4;
4621 first = tx_ring->next_to_use;
4622 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
4623 if (tso < 0) {
4624 dev_kfree_skb_any(skb);
4625 return NETDEV_TX_OK;
4626 }
4627
4628 if (tso)
4629 tx_flags |= IXGBE_TX_FLAGS_TSO;
4630 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
b4617240 4631 (skb->ip_summed == CHECKSUM_PARTIAL))
9a799d71
AK		 4632 tx_flags |= IXGBE_TX_FLAGS_CSUM;
4633
44df32c5 4634 count = ixgbe_tx_map(adapter, tx_ring, skb, first);
9a799d71 4635
44df32c5
AD		 4636 if (count) {
4637 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
4638 hdr_len);
4639 netdev->trans_start = jiffies;
4640 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
9a799d71 4641
44df32c5
AD		 4642 } else {
4643 dev_kfree_skb_any(skb);
4644 tx_ring->tx_buffer_info[first].time_stamp = 0;
4645 tx_ring->next_to_use = first;
4646 }
9a799d71
AK		 4647
4648 return NETDEV_TX_OK;
4649}
4650
4651/**
4652 * ixgbe_get_stats - Get System Network Statistics
4653 * @netdev: network interface device structure
4654 *
4655 * Returns the address of the device statistics structure.
4656 * The statistics are actually updated from the timer callback.
4657 **/
4658static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
4659{
4660 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4661
4662 /* only return the current stats */
4663 return &adapter->net_stats;
4664}
4665
4666/**
4667 * ixgbe_set_mac - Change the Ethernet Address of the NIC
4668 * @netdev: network interface device structure
4669 * @p: pointer to an address structure
4670 *
4671 * Returns 0 on success, negative on failure
4672 **/
4673static int ixgbe_set_mac(struct net_device *netdev, void *p)
4674{
4675 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 4676 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 4677 struct sockaddr *addr = p;
4678
4679 if (!is_valid_ether_addr(addr->sa_data))
4680 return -EADDRNOTAVAIL;
4681
4682 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 4683 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 4684
b4617240 4685 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71
AK		 4686
4687 return 0;
4688}
4689
6b73e10d
BH		 4690static int
4691ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
4692{
4693 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4694 struct ixgbe_hw *hw = &adapter->hw;
4695 u16 value;
4696 int rc;
4697
4698 if (prtad != hw->phy.mdio.prtad)
4699 return -EINVAL;
4700 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
4701 if (!rc)
4702 rc = value;
4703 return rc;
4704}
4705
4706static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
4707 u16 addr, u16 value)
4708{
4709 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4710 struct ixgbe_hw *hw = &adapter->hw;
4711
4712 if (prtad != hw->phy.mdio.prtad)
4713 return -EINVAL;
4714 return hw->phy.ops.write_reg(hw, addr, devad, value);
4715}
4716
4717static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
4718{
4719 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4720
4721 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
4722}
4723
9a799d71
AK		 4724#ifdef CONFIG_NET_POLL_CONTROLLER
4725/*
4726 * Polling 'interrupt' - used by things like netconsole to send skbs
4727 * without having to re-enable interrupts. It's not called while
4728 * the interrupt routine is executing.
4729 */
4730static void ixgbe_netpoll(struct net_device *netdev)
4731{
4732 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4733
4734 disable_irq(adapter->pdev->irq);
4735 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
4736 ixgbe_intr(adapter->pdev->irq, netdev);
4737 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
4738 enable_irq(adapter->pdev->irq);
4739}
4740#endif
4741
0edc3527
SH		 4742static const struct net_device_ops ixgbe_netdev_ops = {
4743 .ndo_open = ixgbe_open,
4744 .ndo_stop = ixgbe_close,
00829823 4745 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 4746 .ndo_select_queue = ixgbe_select_queue,
0edc3527 4747 .ndo_get_stats = ixgbe_get_stats,
e90d400c 4748 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 4749 .ndo_set_multicast_list = ixgbe_set_rx_mode,
4750 .ndo_validate_addr = eth_validate_addr,
4751 .ndo_set_mac_address = ixgbe_set_mac,
4752 .ndo_change_mtu = ixgbe_change_mtu,
4753 .ndo_tx_timeout = ixgbe_tx_timeout,
4754 .ndo_vlan_rx_register = ixgbe_vlan_rx_register,
4755 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
4756 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 4757 .ndo_do_ioctl = ixgbe_ioctl,
0edc3527
SH		 4758#ifdef CONFIG_NET_POLL_CONTROLLER
4759 .ndo_poll_controller = ixgbe_netpoll,
4760#endif
4761};
4762
9a799d71
AK		 4763/**
4764 * ixgbe_probe - Device Initialization Routine
4765 * @pdev: PCI device information struct
4766 * @ent: entry in ixgbe_pci_tbl
4767 *
4768 * Returns 0 on success, negative on failure
4769 *
4770 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
4771 * The OS initialization, configuring of the adapter private structure,
4772 * and a hardware reset occur.
4773 **/
4774static int __devinit ixgbe_probe(struct pci_dev *pdev,
b4617240 4775 const struct pci_device_id *ent)
9a799d71
AK		 4776{
4777 struct net_device *netdev;
4778 struct ixgbe_adapter *adapter = NULL;
4779 struct ixgbe_hw *hw;
4780 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 4781 static int cards_found;
4782 int i, err, pci_using_dac;
c44ade9e 4783 u32 part_num, eec;
9a799d71 4784
9ce77666 4785 err = pci_enable_device_mem(pdev);
9a799d71
AK		 4786 if (err)
4787 return err;
4788
6a35528a
YH		 4789 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
4790 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
9a799d71
AK		 4791 pci_using_dac = 1;
4792 } else {
284901a9 4793 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
9a799d71 4794 if (err) {
284901a9 4795 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
9a799d71 4796 if (err) {
b4617240
PW		 4797 dev_err(&pdev->dev, "No usable DMA "
4798 "configuration, aborting\n");
9a799d71
AK		 4799 goto err_dma;
4800 }
4801 }
4802 pci_using_dac = 0;
4803 }
4804
9ce77666 4805 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
4806 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 4807 if (err) {
9ce77666 4808 dev_err(&pdev->dev,
4809 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 4810 goto err_pci_reg;
4811 }
4812
6fabd715
PWJ		 4813 err = pci_enable_pcie_error_reporting(pdev);
4814 if (err) {
4815 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
4816 "0x%x\n", err);
4817 /* non-fatal, continue */
4818 }
4819
9a799d71 4820 pci_set_master(pdev);
fb3b27bc 4821 pci_save_state(pdev);
9a799d71 4822
30eba97a 4823 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
9a799d71
AK		 4824 if (!netdev) {
4825 err = -ENOMEM;
4826 goto err_alloc_etherdev;
4827 }
4828
9a799d71
AK		 4829 SET_NETDEV_DEV(netdev, &pdev->dev);
4830
4831 pci_set_drvdata(pdev, netdev);
4832 adapter = netdev_priv(netdev);
4833
4834 adapter->netdev = netdev;
4835 adapter->pdev = pdev;
4836 hw = &adapter->hw;
4837 hw->back = adapter;
4838 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
4839
05857980
JK		 4840 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
4841 pci_resource_len(pdev, 0));
9a799d71
AK		 4842 if (!hw->hw_addr) {
4843 err = -EIO;
4844 goto err_ioremap;
4845 }
4846
4847 for (i = 1; i <= 5; i++) {
4848 if (pci_resource_len(pdev, i) == 0)
4849 continue;
4850 }
4851
0edc3527 4852 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 4853 ixgbe_set_ethtool_ops(netdev);
9a799d71 4854 netdev->watchdog_timeo = 5 * HZ;
9a799d71
AK		 4855 strcpy(netdev->name, pci_name(pdev));
4856
9a799d71
AK		 4857 adapter->bd_number = cards_found;
4858
9a799d71
AK		 4859 /* Setup hw api */
4860 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 4861 hw->mac.type = ii->mac;
9a799d71 4862
c44ade9e
JB		 4863 /* EEPROM */
4864 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
4865 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
4866 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
4867 if (!(eec & (1 << 8)))
4868 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
4869
4870 /* PHY */
4871 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 4872 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 4873 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
4874 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
4875 hw->phy.mdio.mmds = 0;
4876 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
4877 hw->phy.mdio.dev = netdev;
4878 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
4879 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0
DS		 4880
4881 /* set up this timer and work struct before calling get_invariants
4882 * which might start the timer
4883 */
4884 init_timer(&adapter->sfp_timer);
4885 adapter->sfp_timer.function = &ixgbe_sfp_timer;
4886 adapter->sfp_timer.data = (unsigned long) adapter;
4887
4888 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
c44ade9e 4889
e8e26350
PW		 4890 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
4891 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
4892
4893 /* a new SFP+ module arrival, called from GPI SDP2 context */
4894 INIT_WORK(&adapter->sfp_config_module_task,
4895 ixgbe_sfp_config_module_task);
4896
9a799d71 4897 err = ii->get_invariants(hw);
c4900be0
DS		 4898 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
4899 /* start a kernel thread to watch for a module to arrive */
4900 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4901 mod_timer(&adapter->sfp_timer,
4902 round_jiffies(jiffies + (2 * HZ)));
4903 err = 0;
4904 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4905 DPRINTK(PROBE, ERR, "failed to load because an "
4906 "unsupported SFP+ module type was detected.\n");
9a799d71 4907 goto err_hw_init;
c4900be0
DS		 4908 } else if (err) {
4909 goto err_hw_init;
4910 }
9a799d71
AK		 4911
4912 /* setup the private structure */
4913 err = ixgbe_sw_init(adapter);
4914 if (err)
4915 goto err_sw_init;
4916
c44ade9e
JB		 4917 /* reset_hw fills in the perm_addr as well */
4918 err = hw->mac.ops.reset_hw(hw);
04f165ef
PW		 4919 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4920 dev_err(&adapter->pdev->dev, "failed to load because an "
4921 "unsupported SFP+ module type was detected.\n");
4922 goto err_sw_init;
4923 } else if (err) {
c44ade9e
JB		 4924 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
4925 goto err_sw_init;
4926 }
4927
9a799d71 4928 netdev->features = NETIF_F_SG |
b4617240
PW		 4929 NETIF_F_IP_CSUM |
4930 NETIF_F_HW_VLAN_TX |
4931 NETIF_F_HW_VLAN_RX |
4932 NETIF_F_HW_VLAN_FILTER;
9a799d71 4933
e9990a9c 4934 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 4935 netdev->features |= NETIF_F_TSO;
9a799d71 4936 netdev->features |= NETIF_F_TSO6;
78b6f4ce 4937 netdev->features |= NETIF_F_GRO;
ad31c402 4938
45a5ead0
JB		 4939 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
4940 netdev->features |= NETIF_F_SCTP_CSUM;
4941
ad31c402
JK		 4942 netdev->vlan_features |= NETIF_F_TSO;
4943 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 4944 netdev->vlan_features |= NETIF_F_IP_CSUM;
ad31c402
JK		 4945 netdev->vlan_features |= NETIF_F_SG;
4946
2f90b865
AD		 4947 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
4948 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4949
7a6b6f51 4950#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4951 netdev->dcbnl_ops = &dcbnl_ops;
4952#endif
4953
9a799d71
AK		 4954 if (pci_using_dac)
4955 netdev->features |= NETIF_F_HIGHDMA;
4956
f8212f97
AD		 4957 if (adapter->flags & IXGBE_FLAG_RSC_ENABLED)
4958 netdev->features |= NETIF_F_LRO;
4959
9a799d71 4960 /* make sure the EEPROM is good */
c44ade9e 4961 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
9a799d71
AK		 4962 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
4963 err = -EIO;
4964 goto err_eeprom;
4965 }
4966
4967 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
4968 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
4969
c44ade9e
JB		 4970 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
4971 dev_err(&pdev->dev, "invalid MAC address\n");
9a799d71
AK		 4972 err = -EIO;
4973 goto err_eeprom;
4974 }
4975
4976 init_timer(&adapter->watchdog_timer);
4977 adapter->watchdog_timer.function = &ixgbe_watchdog;
4978 adapter->watchdog_timer.data = (unsigned long)adapter;
4979
4980 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
cf8280ee 4981 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
9a799d71 4982
021230d4
AV		 4983 err = ixgbe_init_interrupt_scheme(adapter);
4984 if (err)
4985 goto err_sw_init;
9a799d71 4986
e8e26350
PW		 4987 switch (pdev->device) {
4988 case IXGBE_DEV_ID_82599_KX4:
495dce12
WJP		 4989 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
4990 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
e8e26350
PW		 4991 break;
4992 default:
4993 adapter->wol = 0;
4994 break;
4995 }
4996 device_init_wakeup(&adapter->pdev->dev, true);
4997 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
4998
04f165ef
PW		 4999 /* pick up the PCI bus settings for reporting later */
5000 hw->mac.ops.get_bus_info(hw);
5001
9a799d71 5002 /* print bus type/speed/width info */
7c510e4b 5003 dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
e8e26350
PW		 5004 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
5005 (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
5006 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
5007 (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
5008 (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
b4617240 5009 "Unknown"),
7c510e4b 5010 netdev->dev_addr);
c44ade9e 5011 ixgbe_read_pba_num_generic(hw, &part_num);
e8e26350
PW		 5012 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
5013 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
5014 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
5015 (part_num >> 8), (part_num & 0xff));
5016 else
5017 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
5018 hw->mac.type, hw->phy.type,
5019 (part_num >> 8), (part_num & 0xff));
9a799d71 5020
e8e26350 5021 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
0c254d86 5022 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
b4617240
PW		 5023 "this card is not sufficient for optimal "
5024 "performance.\n");
0c254d86 5025 dev_warn(&pdev->dev, "For optimal performance a x8 "
b4617240 5026 "PCI-Express slot is required.\n");
0c254d86
AK		 5027 }
5028
34b0368c
PWJ		 5029 /* save off EEPROM version number */
5030 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
5031
9a799d71 5032 /* reset the hardware with the new settings */
c44ade9e
JB		 5033 hw->mac.ops.start_hw(hw);
5034
9a799d71
AK		 5035 strcpy(netdev->name, "eth%d");
5036 err = register_netdev(netdev);
5037 if (err)
5038 goto err_register;
5039
54386467
JB		 5040 /* carrier off reporting is important to ethtool even BEFORE open */
5041 netif_carrier_off(netdev);
5042
5dd2d332 5043#ifdef CONFIG_IXGBE_DCA
652f093f 5044 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd
JC		 5045 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
5046 /* always use CB2 mode, difference is masked
5047 * in the CB driver */
5048 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
5049 ixgbe_setup_dca(adapter);
5050 }
5051#endif
9a799d71
AK		 5052
5053 dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
5054 cards_found++;
5055 return 0;
5056
5057err_register:
5eba3699 5058 ixgbe_release_hw_control(adapter);
9a799d71 5059err_hw_init:
7a921c93 5060 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 5061err_sw_init:
5062err_eeprom:
c4900be0
DS		 5063 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5064 del_timer_sync(&adapter->sfp_timer);
5065 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 5066 cancel_work_sync(&adapter->multispeed_fiber_task);
5067 cancel_work_sync(&adapter->sfp_config_module_task);
9a799d71
AK		 5068 iounmap(hw->hw_addr);
5069err_ioremap:
5070 free_netdev(netdev);
5071err_alloc_etherdev:
9ce77666 5072 pci_release_selected_regions(pdev, pci_select_bars(pdev,
5073 IORESOURCE_MEM));
9a799d71
AK		 5074err_pci_reg:
5075err_dma:
5076 pci_disable_device(pdev);
5077 return err;
5078}
5079
5080/**
5081 * ixgbe_remove - Device Removal Routine
5082 * @pdev: PCI device information struct
5083 *
5084 * ixgbe_remove is called by the PCI subsystem to alert the driver
5085 * that it should release a PCI device. The could be caused by a
5086 * Hot-Plug event, or because the driver is going to be removed from
5087 * memory.
5088 **/
5089static void __devexit ixgbe_remove(struct pci_dev *pdev)
5090{
5091 struct net_device *netdev = pci_get_drvdata(pdev);
5092 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715 5093 int err;
9a799d71
AK		 5094
5095 set_bit(__IXGBE_DOWN, &adapter->state);
c4900be0
DS		 5096 /* clear the module not found bit to make sure the worker won't
5097 * reschedule
5098 */
5099 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
9a799d71
AK		 5100 del_timer_sync(&adapter->watchdog_timer);
5101
c4900be0
DS		 5102 del_timer_sync(&adapter->sfp_timer);
5103 cancel_work_sync(&adapter->watchdog_task);
5104 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 5105 cancel_work_sync(&adapter->multispeed_fiber_task);
5106 cancel_work_sync(&adapter->sfp_config_module_task);
9a799d71
AK		 5107 flush_scheduled_work();
5108
5dd2d332 5109#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 5110 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
5111 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
5112 dca_remove_requester(&pdev->dev);
5113 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
5114 }
5115
5116#endif
c4900be0
DS		 5117 if (netdev->reg_state == NETREG_REGISTERED)
5118 unregister_netdev(netdev);
9a799d71 5119
7a921c93 5120 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 5121
021230d4 5122 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5123
5124 iounmap(adapter->hw.hw_addr);
9ce77666 5125 pci_release_selected_regions(pdev, pci_select_bars(pdev,
5126 IORESOURCE_MEM));
9a799d71 5127
021230d4 5128 DPRINTK(PROBE, INFO, "complete\n");
021230d4 5129
9a799d71
AK		 5130 free_netdev(netdev);
5131
6fabd715
PWJ		 5132 err = pci_disable_pcie_error_reporting(pdev);
5133 if (err)
5134 dev_err(&pdev->dev,
5135 "pci_disable_pcie_error_reporting failed 0x%x\n", err);
5136
9a799d71
AK		 5137 pci_disable_device(pdev);
5138}
5139
5140/**
5141 * ixgbe_io_error_detected - called when PCI error is detected
5142 * @pdev: Pointer to PCI device
5143 * @state: The current pci connection state
5144 *
5145 * This function is called after a PCI bus error affecting
5146 * this device has been detected.
5147 */
5148static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
b4617240 5149 pci_channel_state_t state)
9a799d71
AK		 5150{
5151 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 5152 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5153
5154 netif_device_detach(netdev);
5155
3044b8d1
BL		 5156 if (state == pci_channel_io_perm_failure)
5157 return PCI_ERS_RESULT_DISCONNECT;
5158
9a799d71
AK		 5159 if (netif_running(netdev))
5160 ixgbe_down(adapter);
5161 pci_disable_device(pdev);
5162
b4617240 5163 /* Request a slot reset. */
9a799d71
AK		 5164 return PCI_ERS_RESULT_NEED_RESET;
5165}
5166
5167/**
5168 * ixgbe_io_slot_reset - called after the pci bus has been reset.
5169 * @pdev: Pointer to PCI device
5170 *
5171 * Restart the card from scratch, as if from a cold-boot.
5172 */
5173static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
5174{
5175 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 5176 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715
PWJ		 5177 pci_ers_result_t result;
5178 int err;
9a799d71 5179
9ce77666 5180 if (pci_enable_device_mem(pdev)) {
9a799d71 5181 DPRINTK(PROBE, ERR,
b4617240 5182 "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 5183 result = PCI_ERS_RESULT_DISCONNECT;
5184 } else {
5185 pci_set_master(pdev);
5186 pci_restore_state(pdev);
9a799d71 5187
dd4d8ca6 5188 pci_wake_from_d3(pdev, false);
9a799d71 5189
6fabd715 5190 ixgbe_reset(adapter);
88512539 5191 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 5192 result = PCI_ERS_RESULT_RECOVERED;
5193 }
5194
5195 err = pci_cleanup_aer_uncorrect_error_status(pdev);
5196 if (err) {
5197 dev_err(&pdev->dev,
5198 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
5199 /* non-fatal, continue */
5200 }
9a799d71 5201
6fabd715 5202 return result;
9a799d71
AK		 5203}
5204
5205/**
5206 * ixgbe_io_resume - called when traffic can start flowing again.
5207 * @pdev: Pointer to PCI device
5208 *
5209 * This callback is called when the error recovery driver tells us that
5210 * its OK to resume normal operation.
5211 */
5212static void ixgbe_io_resume(struct pci_dev *pdev)
5213{
5214 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 5215 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5216
5217 if (netif_running(netdev)) {
5218 if (ixgbe_up(adapter)) {
5219 DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
5220 return;
5221 }
5222 }
5223
5224 netif_device_attach(netdev);
9a799d71
AK		 5225}
5226
5227static struct pci_error_handlers ixgbe_err_handler = {
5228 .error_detected = ixgbe_io_error_detected,
5229 .slot_reset = ixgbe_io_slot_reset,
5230 .resume = ixgbe_io_resume,
5231};
5232
5233static struct pci_driver ixgbe_driver = {
5234 .name = ixgbe_driver_name,
5235 .id_table = ixgbe_pci_tbl,
5236 .probe = ixgbe_probe,
5237 .remove = __devexit_p(ixgbe_remove),
5238#ifdef CONFIG_PM
5239 .suspend = ixgbe_suspend,
5240 .resume = ixgbe_resume,
5241#endif
5242 .shutdown = ixgbe_shutdown,
5243 .err_handler = &ixgbe_err_handler
5244};
5245
5246/**
5247 * ixgbe_init_module - Driver Registration Routine
5248 *
5249 * ixgbe_init_module is the first routine called when the driver is
5250 * loaded. All it does is register with the PCI subsystem.
5251 **/
5252static int __init ixgbe_init_module(void)
5253{
5254 int ret;
5255 printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
5256 ixgbe_driver_string, ixgbe_driver_version);
5257
5258 printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
5259
5dd2d332 5260#ifdef CONFIG_IXGBE_DCA
bd0362dd 5261 dca_register_notify(&dca_notifier);
bd0362dd 5262#endif
5dd2d332 5263
9a799d71
AK		 5264 ret = pci_register_driver(&ixgbe_driver);
5265 return ret;
5266}
b4617240 5267
9a799d71
AK		 5268module_init(ixgbe_init_module);
5269
5270/**
5271 * ixgbe_exit_module - Driver Exit Cleanup Routine
5272 *
5273 * ixgbe_exit_module is called just before the driver is removed
5274 * from memory.
5275 **/
5276static void __exit ixgbe_exit_module(void)
5277{
5dd2d332 5278#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 5279 dca_unregister_notify(&dca_notifier);
5280#endif
9a799d71
AK		 5281 pci_unregister_driver(&ixgbe_driver);
5282}
bd0362dd 5283
5dd2d332 5284#ifdef CONFIG_IXGBE_DCA
bd0362dd 5285static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
b4617240 5286 void *p)
bd0362dd
JC		 5287{
5288 int ret_val;
5289
5290 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
b4617240 5291 __ixgbe_notify_dca);
bd0362dd
JC		 5292
5293 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5294}
b453368d 5295
5dd2d332 5296#endif /* CONFIG_IXGBE_DCA */
b453368d
AD		 5297#ifdef DEBUG
5298/**
5299 * ixgbe_get_hw_dev_name - return device name string
5300 * used by hardware layer to print debugging information
5301 **/
5302char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
5303{
5304 struct ixgbe_adapter *adapter = hw->back;
5305 return adapter->netdev->name;
5306}
bd0362dd 5307
b453368d 5308#endif
9a799d71
AK		 5309module_exit(ixgbe_exit_module);
5310
5311/* ixgbe_main.c */
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