]>
Commit | Line | Data |
---|---|---|
9a799d71 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
3efac5a0 | 4 | Copyright(c) 1999 - 2009 Intel Corporation. |
9a799d71 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
9a799d71 AK |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #include <linux/types.h> | |
29 | #include <linux/module.h> | |
30 | #include <linux/pci.h> | |
31 | #include <linux/netdevice.h> | |
32 | #include <linux/vmalloc.h> | |
33 | #include <linux/string.h> | |
34 | #include <linux/in.h> | |
35 | #include <linux/ip.h> | |
36 | #include <linux/tcp.h> | |
37 | #include <linux/ipv6.h> | |
38 | #include <net/checksum.h> | |
39 | #include <net/ip6_checksum.h> | |
40 | #include <linux/ethtool.h> | |
41 | #include <linux/if_vlan.h> | |
42 | ||
43 | #include "ixgbe.h" | |
44 | #include "ixgbe_common.h" | |
45 | ||
46 | char ixgbe_driver_name[] = "ixgbe"; | |
9c8eb720 | 47 | static const char ixgbe_driver_string[] = |
b4617240 | 48 | "Intel(R) 10 Gigabit PCI Express Network Driver"; |
9a799d71 | 49 | |
04193058 | 50 | #define DRV_VERSION "2.0.16-k2" |
9c8eb720 | 51 | const char ixgbe_driver_version[] = DRV_VERSION; |
3efac5a0 | 52 | static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation."; |
9a799d71 AK |
53 | |
54 | static const struct ixgbe_info *ixgbe_info_tbl[] = { | |
b4617240 | 55 | [board_82598] = &ixgbe_82598_info, |
e8e26350 | 56 | [board_82599] = &ixgbe_82599_info, |
9a799d71 AK |
57 | }; |
58 | ||
59 | /* ixgbe_pci_tbl - PCI Device ID Table | |
60 | * | |
61 | * Wildcard entries (PCI_ANY_ID) should come last | |
62 | * Last entry must be all 0s | |
63 | * | |
64 | * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, | |
65 | * Class, Class Mask, private data (not used) } | |
66 | */ | |
67 | static struct pci_device_id ixgbe_pci_tbl[] = { | |
1e336d0f DS |
68 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), |
69 | board_82598 }, | |
9a799d71 | 70 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), |
3957d63d | 71 | board_82598 }, |
9a799d71 | 72 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), |
3957d63d | 73 | board_82598 }, |
0befdb3e JB |
74 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), |
75 | board_82598 }, | |
9a799d71 | 76 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), |
3957d63d | 77 | board_82598 }, |
8d792cd9 JB |
78 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), |
79 | board_82598 }, | |
c4900be0 DS |
80 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), |
81 | board_82598 }, | |
82 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), | |
83 | board_82598 }, | |
b95f5fcb JB |
84 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), |
85 | board_82598 }, | |
c4900be0 DS |
86 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), |
87 | board_82598 }, | |
2f21bdd3 DS |
88 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), |
89 | board_82598 }, | |
e8e26350 PW |
90 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), |
91 | board_82599 }, | |
92 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), | |
93 | board_82599 }, | |
9a799d71 AK |
94 | |
95 | /* required last entry */ | |
96 | {0, } | |
97 | }; | |
98 | MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl); | |
99 | ||
5dd2d332 | 100 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 101 | static int ixgbe_notify_dca(struct notifier_block *, unsigned long event, |
b4617240 | 102 | void *p); |
bd0362dd JC |
103 | static struct notifier_block dca_notifier = { |
104 | .notifier_call = ixgbe_notify_dca, | |
105 | .next = NULL, | |
106 | .priority = 0 | |
107 | }; | |
108 | #endif | |
109 | ||
9a799d71 AK |
110 | MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); |
111 | MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver"); | |
112 | MODULE_LICENSE("GPL"); | |
113 | MODULE_VERSION(DRV_VERSION); | |
114 | ||
115 | #define DEFAULT_DEBUG_LEVEL_SHIFT 3 | |
116 | ||
5eba3699 AV |
117 | static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter) |
118 | { | |
119 | u32 ctrl_ext; | |
120 | ||
121 | /* Let firmware take over control of h/w */ | |
122 | ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); | |
123 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, | |
b4617240 | 124 | ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD); |
5eba3699 AV |
125 | } |
126 | ||
127 | static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter) | |
128 | { | |
129 | u32 ctrl_ext; | |
130 | ||
131 | /* Let firmware know the driver has taken over */ | |
132 | ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); | |
133 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, | |
b4617240 | 134 | ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD); |
5eba3699 | 135 | } |
9a799d71 | 136 | |
e8e26350 PW |
137 | /* |
138 | * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors | |
139 | * @adapter: pointer to adapter struct | |
140 | * @direction: 0 for Rx, 1 for Tx, -1 for other causes | |
141 | * @queue: queue to map the corresponding interrupt to | |
142 | * @msix_vector: the vector to map to the corresponding queue | |
143 | * | |
144 | */ | |
145 | static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction, | |
146 | u8 queue, u8 msix_vector) | |
9a799d71 AK |
147 | { |
148 | u32 ivar, index; | |
e8e26350 PW |
149 | struct ixgbe_hw *hw = &adapter->hw; |
150 | switch (hw->mac.type) { | |
151 | case ixgbe_mac_82598EB: | |
152 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
153 | if (direction == -1) | |
154 | direction = 0; | |
155 | index = (((direction * 64) + queue) >> 2) & 0x1F; | |
156 | ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); | |
157 | ivar &= ~(0xFF << (8 * (queue & 0x3))); | |
158 | ivar |= (msix_vector << (8 * (queue & 0x3))); | |
159 | IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar); | |
160 | break; | |
161 | case ixgbe_mac_82599EB: | |
162 | if (direction == -1) { | |
163 | /* other causes */ | |
164 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
165 | index = ((queue & 1) * 8); | |
166 | ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC); | |
167 | ivar &= ~(0xFF << index); | |
168 | ivar |= (msix_vector << index); | |
169 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar); | |
170 | break; | |
171 | } else { | |
172 | /* tx or rx causes */ | |
173 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
174 | index = ((16 * (queue & 1)) + (8 * direction)); | |
175 | ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); | |
176 | ivar &= ~(0xFF << index); | |
177 | ivar |= (msix_vector << index); | |
178 | IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar); | |
179 | break; | |
180 | } | |
181 | default: | |
182 | break; | |
183 | } | |
9a799d71 AK |
184 | } |
185 | ||
186 | static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter, | |
b4617240 PW |
187 | struct ixgbe_tx_buffer |
188 | *tx_buffer_info) | |
9a799d71 | 189 | { |
44df32c5 | 190 | tx_buffer_info->dma = 0; |
9a799d71 | 191 | if (tx_buffer_info->skb) { |
44df32c5 AD |
192 | skb_dma_unmap(&adapter->pdev->dev, tx_buffer_info->skb, |
193 | DMA_TO_DEVICE); | |
9a799d71 AK |
194 | dev_kfree_skb_any(tx_buffer_info->skb); |
195 | tx_buffer_info->skb = NULL; | |
196 | } | |
44df32c5 | 197 | tx_buffer_info->time_stamp = 0; |
9a799d71 AK |
198 | /* tx_buffer_info must be completely set up in the transmit path */ |
199 | } | |
200 | ||
201 | static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter, | |
b4617240 PW |
202 | struct ixgbe_ring *tx_ring, |
203 | unsigned int eop) | |
9a799d71 | 204 | { |
e01c31a5 | 205 | struct ixgbe_hw *hw = &adapter->hw; |
e01c31a5 | 206 | |
9a799d71 | 207 | /* Detect a transmit hang in hardware, this serializes the |
e01c31a5 | 208 | * check with the clearing of time_stamp and movement of eop */ |
9a799d71 | 209 | adapter->detect_tx_hung = false; |
44df32c5 | 210 | if (tx_ring->tx_buffer_info[eop].time_stamp && |
9a799d71 AK |
211 | time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) && |
212 | !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) { | |
213 | /* detected Tx unit hang */ | |
e01c31a5 JB |
214 | union ixgbe_adv_tx_desc *tx_desc; |
215 | tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop); | |
9a799d71 | 216 | DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n" |
e01c31a5 JB |
217 | " Tx Queue <%d>\n" |
218 | " TDH, TDT <%x>, <%x>\n" | |
9a799d71 AK |
219 | " next_to_use <%x>\n" |
220 | " next_to_clean <%x>\n" | |
221 | "tx_buffer_info[next_to_clean]\n" | |
222 | " time_stamp <%lx>\n" | |
e01c31a5 JB |
223 | " jiffies <%lx>\n", |
224 | tx_ring->queue_index, | |
44df32c5 AD |
225 | IXGBE_READ_REG(hw, tx_ring->head), |
226 | IXGBE_READ_REG(hw, tx_ring->tail), | |
e01c31a5 JB |
227 | tx_ring->next_to_use, eop, |
228 | tx_ring->tx_buffer_info[eop].time_stamp, jiffies); | |
9a799d71 AK |
229 | return true; |
230 | } | |
231 | ||
232 | return false; | |
233 | } | |
234 | ||
b4617240 PW |
235 | #define IXGBE_MAX_TXD_PWR 14 |
236 | #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR) | |
e092be60 AV |
237 | |
238 | /* Tx Descriptors needed, worst case */ | |
239 | #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \ | |
240 | (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0)) | |
241 | #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \ | |
b4617240 | 242 | MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */ |
e092be60 | 243 | |
e01c31a5 JB |
244 | static void ixgbe_tx_timeout(struct net_device *netdev); |
245 | ||
9a799d71 AK |
246 | /** |
247 | * ixgbe_clean_tx_irq - Reclaim resources after transmit completes | |
248 | * @adapter: board private structure | |
e01c31a5 | 249 | * @tx_ring: tx ring to clean |
9a1a69ad JB |
250 | * |
251 | * returns true if transmit work is done | |
9a799d71 AK |
252 | **/ |
253 | static bool ixgbe_clean_tx_irq(struct ixgbe_adapter *adapter, | |
e01c31a5 | 254 | struct ixgbe_ring *tx_ring) |
9a799d71 | 255 | { |
e01c31a5 | 256 | struct net_device *netdev = adapter->netdev; |
12207e49 PWJ |
257 | union ixgbe_adv_tx_desc *tx_desc, *eop_desc; |
258 | struct ixgbe_tx_buffer *tx_buffer_info; | |
259 | unsigned int i, eop, count = 0; | |
e01c31a5 | 260 | unsigned int total_bytes = 0, total_packets = 0; |
9a799d71 AK |
261 | |
262 | i = tx_ring->next_to_clean; | |
12207e49 PWJ |
263 | eop = tx_ring->tx_buffer_info[i].next_to_watch; |
264 | eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop); | |
265 | ||
266 | while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) && | |
9a1a69ad | 267 | (count < tx_ring->work_limit)) { |
12207e49 PWJ |
268 | bool cleaned = false; |
269 | for ( ; !cleaned; count++) { | |
270 | struct sk_buff *skb; | |
9a799d71 AK |
271 | tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i); |
272 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
12207e49 | 273 | cleaned = (i == eop); |
e01c31a5 | 274 | skb = tx_buffer_info->skb; |
9a799d71 | 275 | |
12207e49 | 276 | if (cleaned && skb) { |
e092be60 | 277 | unsigned int segs, bytecount; |
e01c31a5 JB |
278 | |
279 | /* gso_segs is currently only valid for tcp */ | |
e092be60 AV |
280 | segs = skb_shinfo(skb)->gso_segs ?: 1; |
281 | /* multiply data chunks by size of headers */ | |
282 | bytecount = ((segs - 1) * skb_headlen(skb)) + | |
e01c31a5 JB |
283 | skb->len; |
284 | total_packets += segs; | |
285 | total_bytes += bytecount; | |
e092be60 | 286 | } |
e01c31a5 | 287 | |
9a799d71 | 288 | ixgbe_unmap_and_free_tx_resource(adapter, |
e01c31a5 | 289 | tx_buffer_info); |
9a799d71 | 290 | |
12207e49 PWJ |
291 | tx_desc->wb.status = 0; |
292 | ||
9a799d71 AK |
293 | i++; |
294 | if (i == tx_ring->count) | |
295 | i = 0; | |
e01c31a5 | 296 | } |
12207e49 PWJ |
297 | |
298 | eop = tx_ring->tx_buffer_info[i].next_to_watch; | |
299 | eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop); | |
300 | } | |
301 | ||
9a799d71 AK |
302 | tx_ring->next_to_clean = i; |
303 | ||
e092be60 | 304 | #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) |
e01c31a5 JB |
305 | if (unlikely(count && netif_carrier_ok(netdev) && |
306 | (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) { | |
e092be60 AV |
307 | /* Make sure that anybody stopping the queue after this |
308 | * sees the new next_to_clean. | |
309 | */ | |
310 | smp_mb(); | |
30eba97a AV |
311 | if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) && |
312 | !test_bit(__IXGBE_DOWN, &adapter->state)) { | |
313 | netif_wake_subqueue(netdev, tx_ring->queue_index); | |
e01c31a5 | 314 | ++adapter->restart_queue; |
30eba97a | 315 | } |
e092be60 | 316 | } |
9a799d71 | 317 | |
e01c31a5 JB |
318 | if (adapter->detect_tx_hung) { |
319 | if (ixgbe_check_tx_hang(adapter, tx_ring, i)) { | |
320 | /* schedule immediate reset if we believe we hung */ | |
321 | DPRINTK(PROBE, INFO, | |
322 | "tx hang %d detected, resetting adapter\n", | |
323 | adapter->tx_timeout_count + 1); | |
324 | ixgbe_tx_timeout(adapter->netdev); | |
325 | } | |
326 | } | |
9a799d71 | 327 | |
e01c31a5 | 328 | /* re-arm the interrupt */ |
835462fc NS |
329 | if (count >= tx_ring->work_limit) { |
330 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) | |
331 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, | |
332 | tx_ring->v_idx); | |
333 | else if (tx_ring->v_idx & 0xFFFFFFFF) | |
334 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), | |
335 | tx_ring->v_idx); | |
336 | else | |
337 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), | |
338 | (tx_ring->v_idx >> 32)); | |
339 | } | |
340 | ||
9a799d71 | 341 | |
e01c31a5 JB |
342 | tx_ring->total_bytes += total_bytes; |
343 | tx_ring->total_packets += total_packets; | |
e01c31a5 | 344 | tx_ring->stats.packets += total_packets; |
12207e49 | 345 | tx_ring->stats.bytes += total_bytes; |
e01c31a5 JB |
346 | adapter->net_stats.tx_bytes += total_bytes; |
347 | adapter->net_stats.tx_packets += total_packets; | |
9a1a69ad | 348 | return (count < tx_ring->work_limit); |
9a799d71 AK |
349 | } |
350 | ||
5dd2d332 | 351 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 352 | static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter, |
b4617240 | 353 | struct ixgbe_ring *rx_ring) |
bd0362dd JC |
354 | { |
355 | u32 rxctrl; | |
356 | int cpu = get_cpu(); | |
3a581073 | 357 | int q = rx_ring - adapter->rx_ring; |
bd0362dd | 358 | |
3a581073 | 359 | if (rx_ring->cpu != cpu) { |
bd0362dd | 360 | rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q)); |
e8e26350 PW |
361 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
362 | rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK; | |
363 | rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu); | |
364 | } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { | |
365 | rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599; | |
366 | rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) << | |
367 | IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599); | |
368 | } | |
bd0362dd JC |
369 | rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN; |
370 | rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN; | |
15005a32 DS |
371 | rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN); |
372 | rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN | | |
e8e26350 | 373 | IXGBE_DCA_RXCTRL_DESC_HSRO_EN); |
bd0362dd | 374 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl); |
3a581073 | 375 | rx_ring->cpu = cpu; |
bd0362dd JC |
376 | } |
377 | put_cpu(); | |
378 | } | |
379 | ||
380 | static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter, | |
b4617240 | 381 | struct ixgbe_ring *tx_ring) |
bd0362dd JC |
382 | { |
383 | u32 txctrl; | |
384 | int cpu = get_cpu(); | |
3a581073 | 385 | int q = tx_ring - adapter->tx_ring; |
bd0362dd | 386 | |
3a581073 | 387 | if (tx_ring->cpu != cpu) { |
bd0362dd | 388 | txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q)); |
e8e26350 PW |
389 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
390 | txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK; | |
391 | txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu); | |
392 | } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { | |
393 | txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599; | |
394 | txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) << | |
395 | IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599); | |
396 | } | |
bd0362dd JC |
397 | txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN; |
398 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl); | |
3a581073 | 399 | tx_ring->cpu = cpu; |
bd0362dd JC |
400 | } |
401 | put_cpu(); | |
402 | } | |
403 | ||
404 | static void ixgbe_setup_dca(struct ixgbe_adapter *adapter) | |
405 | { | |
406 | int i; | |
407 | ||
408 | if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED)) | |
409 | return; | |
410 | ||
411 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
412 | adapter->tx_ring[i].cpu = -1; | |
413 | ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]); | |
414 | } | |
415 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
416 | adapter->rx_ring[i].cpu = -1; | |
417 | ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]); | |
418 | } | |
419 | } | |
420 | ||
421 | static int __ixgbe_notify_dca(struct device *dev, void *data) | |
422 | { | |
423 | struct net_device *netdev = dev_get_drvdata(dev); | |
424 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
425 | unsigned long event = *(unsigned long *)data; | |
426 | ||
427 | switch (event) { | |
428 | case DCA_PROVIDER_ADD: | |
96b0e0f6 JB |
429 | /* if we're already enabled, don't do it again */ |
430 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
431 | break; | |
bd0362dd JC |
432 | /* Always use CB2 mode, difference is masked |
433 | * in the CB driver. */ | |
434 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2); | |
652f093f | 435 | if (dca_add_requester(dev) == 0) { |
96b0e0f6 | 436 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; |
bd0362dd JC |
437 | ixgbe_setup_dca(adapter); |
438 | break; | |
439 | } | |
440 | /* Fall Through since DCA is disabled. */ | |
441 | case DCA_PROVIDER_REMOVE: | |
442 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { | |
443 | dca_remove_requester(dev); | |
444 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
445 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); | |
446 | } | |
447 | break; | |
448 | } | |
449 | ||
652f093f | 450 | return 0; |
bd0362dd JC |
451 | } |
452 | ||
5dd2d332 | 453 | #endif /* CONFIG_IXGBE_DCA */ |
9a799d71 AK |
454 | /** |
455 | * ixgbe_receive_skb - Send a completed packet up the stack | |
456 | * @adapter: board private structure | |
457 | * @skb: packet to send up | |
177db6ff MC |
458 | * @status: hardware indication of status of receive |
459 | * @rx_ring: rx descriptor ring (for a specific queue) to setup | |
460 | * @rx_desc: rx descriptor | |
9a799d71 | 461 | **/ |
78b6f4ce | 462 | static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector, |
b4617240 | 463 | struct sk_buff *skb, u8 status, |
fdaff1ce | 464 | struct ixgbe_ring *ring, |
177db6ff | 465 | union ixgbe_adv_rx_desc *rx_desc) |
9a799d71 | 466 | { |
78b6f4ce HX |
467 | struct ixgbe_adapter *adapter = q_vector->adapter; |
468 | struct napi_struct *napi = &q_vector->napi; | |
177db6ff MC |
469 | bool is_vlan = (status & IXGBE_RXD_STAT_VP); |
470 | u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan); | |
9a799d71 | 471 | |
fdaff1ce | 472 | skb_record_rx_queue(skb, ring->queue_index); |
182ff8df | 473 | if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) { |
2f90b865 | 474 | if (adapter->vlgrp && is_vlan && (tag != 0)) |
78b6f4ce | 475 | vlan_gro_receive(napi, adapter->vlgrp, tag, skb); |
9a799d71 | 476 | else |
78b6f4ce | 477 | napi_gro_receive(napi, skb); |
177db6ff | 478 | } else { |
182ff8df AD |
479 | if (adapter->vlgrp && is_vlan && (tag != 0)) |
480 | vlan_hwaccel_rx(skb, adapter->vlgrp, tag); | |
481 | else | |
482 | netif_rx(skb); | |
9a799d71 AK |
483 | } |
484 | } | |
485 | ||
e59bd25d AV |
486 | /** |
487 | * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum | |
488 | * @adapter: address of board private structure | |
489 | * @status_err: hardware indication of status of receive | |
490 | * @skb: skb currently being received and modified | |
491 | **/ | |
9a799d71 | 492 | static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter, |
712744be | 493 | u32 status_err, struct sk_buff *skb) |
9a799d71 AK |
494 | { |
495 | skb->ip_summed = CHECKSUM_NONE; | |
496 | ||
712744be JB |
497 | /* Rx csum disabled */ |
498 | if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED)) | |
9a799d71 | 499 | return; |
e59bd25d AV |
500 | |
501 | /* if IP and error */ | |
502 | if ((status_err & IXGBE_RXD_STAT_IPCS) && | |
503 | (status_err & IXGBE_RXDADV_ERR_IPE)) { | |
9a799d71 AK |
504 | adapter->hw_csum_rx_error++; |
505 | return; | |
506 | } | |
e59bd25d AV |
507 | |
508 | if (!(status_err & IXGBE_RXD_STAT_L4CS)) | |
509 | return; | |
510 | ||
511 | if (status_err & IXGBE_RXDADV_ERR_TCPE) { | |
512 | adapter->hw_csum_rx_error++; | |
513 | return; | |
514 | } | |
515 | ||
9a799d71 | 516 | /* It must be a TCP or UDP packet with a valid checksum */ |
e59bd25d | 517 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
9a799d71 AK |
518 | adapter->hw_csum_rx_good++; |
519 | } | |
520 | ||
e8e26350 PW |
521 | static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw, |
522 | struct ixgbe_ring *rx_ring, u32 val) | |
523 | { | |
524 | /* | |
525 | * Force memory writes to complete before letting h/w | |
526 | * know there are new descriptors to fetch. (Only | |
527 | * applicable for weak-ordered memory model archs, | |
528 | * such as IA-64). | |
529 | */ | |
530 | wmb(); | |
531 | IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val); | |
532 | } | |
533 | ||
9a799d71 AK |
534 | /** |
535 | * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split | |
536 | * @adapter: address of board private structure | |
537 | **/ | |
538 | static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter, | |
7c6e0a43 JB |
539 | struct ixgbe_ring *rx_ring, |
540 | int cleaned_count) | |
9a799d71 | 541 | { |
9a799d71 AK |
542 | struct pci_dev *pdev = adapter->pdev; |
543 | union ixgbe_adv_rx_desc *rx_desc; | |
3a581073 | 544 | struct ixgbe_rx_buffer *bi; |
9a799d71 | 545 | unsigned int i; |
e8e26350 | 546 | unsigned int bufsz = rx_ring->rx_buf_len + NET_IP_ALIGN; |
9a799d71 AK |
547 | |
548 | i = rx_ring->next_to_use; | |
3a581073 | 549 | bi = &rx_ring->rx_buffer_info[i]; |
9a799d71 AK |
550 | |
551 | while (cleaned_count--) { | |
552 | rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i); | |
553 | ||
762f4c57 | 554 | if (!bi->page_dma && |
3a581073 | 555 | (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) { |
3a581073 | 556 | if (!bi->page) { |
762f4c57 JB |
557 | bi->page = alloc_page(GFP_ATOMIC); |
558 | if (!bi->page) { | |
559 | adapter->alloc_rx_page_failed++; | |
560 | goto no_buffers; | |
561 | } | |
562 | bi->page_offset = 0; | |
563 | } else { | |
564 | /* use a half page if we're re-using */ | |
565 | bi->page_offset ^= (PAGE_SIZE / 2); | |
9a799d71 | 566 | } |
762f4c57 JB |
567 | |
568 | bi->page_dma = pci_map_page(pdev, bi->page, | |
569 | bi->page_offset, | |
570 | (PAGE_SIZE / 2), | |
571 | PCI_DMA_FROMDEVICE); | |
9a799d71 AK |
572 | } |
573 | ||
3a581073 | 574 | if (!bi->skb) { |
5ecc3614 | 575 | struct sk_buff *skb; |
e8e26350 | 576 | skb = netdev_alloc_skb(adapter->netdev, bufsz); |
9a799d71 AK |
577 | |
578 | if (!skb) { | |
579 | adapter->alloc_rx_buff_failed++; | |
580 | goto no_buffers; | |
581 | } | |
582 | ||
583 | /* | |
584 | * Make buffer alignment 2 beyond a 16 byte boundary | |
585 | * this will result in a 16 byte aligned IP header after | |
586 | * the 14 byte MAC header is removed | |
587 | */ | |
588 | skb_reserve(skb, NET_IP_ALIGN); | |
589 | ||
3a581073 | 590 | bi->skb = skb; |
e8e26350 | 591 | bi->dma = pci_map_single(pdev, skb->data, bufsz, |
3a581073 | 592 | PCI_DMA_FROMDEVICE); |
9a799d71 AK |
593 | } |
594 | /* Refresh the desc even if buffer_addrs didn't change because | |
595 | * each write-back erases this info. */ | |
596 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { | |
3a581073 JB |
597 | rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma); |
598 | rx_desc->read.hdr_addr = cpu_to_le64(bi->dma); | |
9a799d71 | 599 | } else { |
3a581073 | 600 | rx_desc->read.pkt_addr = cpu_to_le64(bi->dma); |
9a799d71 AK |
601 | } |
602 | ||
603 | i++; | |
604 | if (i == rx_ring->count) | |
605 | i = 0; | |
3a581073 | 606 | bi = &rx_ring->rx_buffer_info[i]; |
9a799d71 | 607 | } |
7c6e0a43 | 608 | |
9a799d71 AK |
609 | no_buffers: |
610 | if (rx_ring->next_to_use != i) { | |
611 | rx_ring->next_to_use = i; | |
612 | if (i-- == 0) | |
613 | i = (rx_ring->count - 1); | |
614 | ||
e8e26350 | 615 | ixgbe_release_rx_desc(&adapter->hw, rx_ring, i); |
9a799d71 AK |
616 | } |
617 | } | |
618 | ||
7c6e0a43 JB |
619 | static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc) |
620 | { | |
621 | return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info; | |
622 | } | |
623 | ||
624 | static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc) | |
625 | { | |
626 | return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; | |
627 | } | |
628 | ||
f8212f97 AD |
629 | static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc) |
630 | { | |
631 | return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) & | |
632 | IXGBE_RXDADV_RSCCNT_MASK) >> | |
633 | IXGBE_RXDADV_RSCCNT_SHIFT; | |
634 | } | |
635 | ||
636 | /** | |
637 | * ixgbe_transform_rsc_queue - change rsc queue into a full packet | |
638 | * @skb: pointer to the last skb in the rsc queue | |
639 | * | |
640 | * This function changes a queue full of hw rsc buffers into a completed | |
641 | * packet. It uses the ->prev pointers to find the first packet and then | |
642 | * turns it into the frag list owner. | |
643 | **/ | |
644 | static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb) | |
645 | { | |
646 | unsigned int frag_list_size = 0; | |
647 | ||
648 | while (skb->prev) { | |
649 | struct sk_buff *prev = skb->prev; | |
650 | frag_list_size += skb->len; | |
651 | skb->prev = NULL; | |
652 | skb = prev; | |
653 | } | |
654 | ||
655 | skb_shinfo(skb)->frag_list = skb->next; | |
656 | skb->next = NULL; | |
657 | skb->len += frag_list_size; | |
658 | skb->data_len += frag_list_size; | |
659 | skb->truesize += frag_list_size; | |
660 | return skb; | |
661 | } | |
662 | ||
78b6f4ce | 663 | static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, |
b4617240 PW |
664 | struct ixgbe_ring *rx_ring, |
665 | int *work_done, int work_to_do) | |
9a799d71 | 666 | { |
78b6f4ce | 667 | struct ixgbe_adapter *adapter = q_vector->adapter; |
9a799d71 AK |
668 | struct pci_dev *pdev = adapter->pdev; |
669 | union ixgbe_adv_rx_desc *rx_desc, *next_rxd; | |
670 | struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer; | |
671 | struct sk_buff *skb; | |
f8212f97 | 672 | unsigned int i, rsc_count = 0; |
7c6e0a43 | 673 | u32 len, staterr; |
177db6ff MC |
674 | u16 hdr_info; |
675 | bool cleaned = false; | |
9a799d71 | 676 | int cleaned_count = 0; |
d2f4fbe2 | 677 | unsigned int total_rx_bytes = 0, total_rx_packets = 0; |
9a799d71 AK |
678 | |
679 | i = rx_ring->next_to_clean; | |
9a799d71 AK |
680 | rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i); |
681 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
682 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; | |
9a799d71 AK |
683 | |
684 | while (staterr & IXGBE_RXD_STAT_DD) { | |
7c6e0a43 | 685 | u32 upper_len = 0; |
9a799d71 AK |
686 | if (*work_done >= work_to_do) |
687 | break; | |
688 | (*work_done)++; | |
689 | ||
690 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { | |
7c6e0a43 JB |
691 | hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc)); |
692 | len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >> | |
762f4c57 | 693 | IXGBE_RXDADV_HDRBUFLEN_SHIFT; |
9a799d71 AK |
694 | if (hdr_info & IXGBE_RXDADV_SPH) |
695 | adapter->rx_hdr_split++; | |
696 | if (len > IXGBE_RX_HDR_SIZE) | |
697 | len = IXGBE_RX_HDR_SIZE; | |
698 | upper_len = le16_to_cpu(rx_desc->wb.upper.length); | |
7c6e0a43 | 699 | } else { |
9a799d71 | 700 | len = le16_to_cpu(rx_desc->wb.upper.length); |
7c6e0a43 | 701 | } |
9a799d71 AK |
702 | |
703 | cleaned = true; | |
704 | skb = rx_buffer_info->skb; | |
705 | prefetch(skb->data - NET_IP_ALIGN); | |
706 | rx_buffer_info->skb = NULL; | |
707 | ||
708 | if (len && !skb_shinfo(skb)->nr_frags) { | |
709 | pci_unmap_single(pdev, rx_buffer_info->dma, | |
5ecc3614 | 710 | rx_ring->rx_buf_len, |
b4617240 | 711 | PCI_DMA_FROMDEVICE); |
9a799d71 AK |
712 | skb_put(skb, len); |
713 | } | |
714 | ||
715 | if (upper_len) { | |
716 | pci_unmap_page(pdev, rx_buffer_info->page_dma, | |
762f4c57 | 717 | PAGE_SIZE / 2, PCI_DMA_FROMDEVICE); |
9a799d71 AK |
718 | rx_buffer_info->page_dma = 0; |
719 | skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, | |
762f4c57 JB |
720 | rx_buffer_info->page, |
721 | rx_buffer_info->page_offset, | |
722 | upper_len); | |
723 | ||
724 | if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) || | |
725 | (page_count(rx_buffer_info->page) != 1)) | |
726 | rx_buffer_info->page = NULL; | |
727 | else | |
728 | get_page(rx_buffer_info->page); | |
9a799d71 AK |
729 | |
730 | skb->len += upper_len; | |
731 | skb->data_len += upper_len; | |
732 | skb->truesize += upper_len; | |
733 | } | |
734 | ||
735 | i++; | |
736 | if (i == rx_ring->count) | |
737 | i = 0; | |
9a799d71 AK |
738 | |
739 | next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i); | |
740 | prefetch(next_rxd); | |
9a799d71 | 741 | cleaned_count++; |
f8212f97 AD |
742 | |
743 | if (adapter->flags & IXGBE_FLAG_RSC_CAPABLE) | |
744 | rsc_count = ixgbe_get_rsc_count(rx_desc); | |
745 | ||
746 | if (rsc_count) { | |
747 | u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >> | |
748 | IXGBE_RXDADV_NEXTP_SHIFT; | |
749 | next_buffer = &rx_ring->rx_buffer_info[nextp]; | |
750 | rx_ring->rsc_count += (rsc_count - 1); | |
751 | } else { | |
752 | next_buffer = &rx_ring->rx_buffer_info[i]; | |
753 | } | |
754 | ||
9a799d71 | 755 | if (staterr & IXGBE_RXD_STAT_EOP) { |
f8212f97 AD |
756 | if (skb->prev) |
757 | skb = ixgbe_transform_rsc_queue(skb); | |
9a799d71 AK |
758 | rx_ring->stats.packets++; |
759 | rx_ring->stats.bytes += skb->len; | |
760 | } else { | |
f8212f97 AD |
761 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { |
762 | rx_buffer_info->skb = next_buffer->skb; | |
763 | rx_buffer_info->dma = next_buffer->dma; | |
764 | next_buffer->skb = skb; | |
765 | next_buffer->dma = 0; | |
766 | } else { | |
767 | skb->next = next_buffer->skb; | |
768 | skb->next->prev = skb; | |
769 | } | |
9a799d71 AK |
770 | adapter->non_eop_descs++; |
771 | goto next_desc; | |
772 | } | |
773 | ||
774 | if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) { | |
775 | dev_kfree_skb_irq(skb); | |
776 | goto next_desc; | |
777 | } | |
778 | ||
779 | ixgbe_rx_checksum(adapter, staterr, skb); | |
d2f4fbe2 AV |
780 | |
781 | /* probably a little skewed due to removing CRC */ | |
782 | total_rx_bytes += skb->len; | |
783 | total_rx_packets++; | |
784 | ||
74ce8dd2 | 785 | skb->protocol = eth_type_trans(skb, adapter->netdev); |
fdaff1ce | 786 | ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc); |
9a799d71 AK |
787 | |
788 | next_desc: | |
789 | rx_desc->wb.upper.status_error = 0; | |
790 | ||
791 | /* return some buffers to hardware, one at a time is too slow */ | |
792 | if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) { | |
793 | ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count); | |
794 | cleaned_count = 0; | |
795 | } | |
796 | ||
797 | /* use prefetched values */ | |
798 | rx_desc = next_rxd; | |
f8212f97 | 799 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; |
9a799d71 AK |
800 | |
801 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
177db6ff MC |
802 | } |
803 | ||
9a799d71 AK |
804 | rx_ring->next_to_clean = i; |
805 | cleaned_count = IXGBE_DESC_UNUSED(rx_ring); | |
806 | ||
807 | if (cleaned_count) | |
808 | ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count); | |
809 | ||
f494e8fa AV |
810 | rx_ring->total_packets += total_rx_packets; |
811 | rx_ring->total_bytes += total_rx_bytes; | |
812 | adapter->net_stats.rx_bytes += total_rx_bytes; | |
813 | adapter->net_stats.rx_packets += total_rx_packets; | |
814 | ||
9a799d71 AK |
815 | return cleaned; |
816 | } | |
817 | ||
021230d4 | 818 | static int ixgbe_clean_rxonly(struct napi_struct *, int); |
9a799d71 AK |
819 | /** |
820 | * ixgbe_configure_msix - Configure MSI-X hardware | |
821 | * @adapter: board private structure | |
822 | * | |
823 | * ixgbe_configure_msix sets up the hardware to properly generate MSI-X | |
824 | * interrupts. | |
825 | **/ | |
826 | static void ixgbe_configure_msix(struct ixgbe_adapter *adapter) | |
827 | { | |
021230d4 AV |
828 | struct ixgbe_q_vector *q_vector; |
829 | int i, j, q_vectors, v_idx, r_idx; | |
830 | u32 mask; | |
9a799d71 | 831 | |
021230d4 | 832 | q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; |
9a799d71 | 833 | |
4df10466 JB |
834 | /* |
835 | * Populate the IVAR table and set the ITR values to the | |
021230d4 AV |
836 | * corresponding register. |
837 | */ | |
838 | for (v_idx = 0; v_idx < q_vectors; v_idx++) { | |
7a921c93 | 839 | q_vector = adapter->q_vector[v_idx]; |
021230d4 AV |
840 | /* XXX for_each_bit(...) */ |
841 | r_idx = find_first_bit(q_vector->rxr_idx, | |
b4617240 | 842 | adapter->num_rx_queues); |
021230d4 AV |
843 | |
844 | for (i = 0; i < q_vector->rxr_count; i++) { | |
845 | j = adapter->rx_ring[r_idx].reg_idx; | |
e8e26350 | 846 | ixgbe_set_ivar(adapter, 0, j, v_idx); |
021230d4 | 847 | r_idx = find_next_bit(q_vector->rxr_idx, |
b4617240 PW |
848 | adapter->num_rx_queues, |
849 | r_idx + 1); | |
021230d4 AV |
850 | } |
851 | r_idx = find_first_bit(q_vector->txr_idx, | |
b4617240 | 852 | adapter->num_tx_queues); |
021230d4 AV |
853 | |
854 | for (i = 0; i < q_vector->txr_count; i++) { | |
855 | j = adapter->tx_ring[r_idx].reg_idx; | |
e8e26350 | 856 | ixgbe_set_ivar(adapter, 1, j, v_idx); |
021230d4 | 857 | r_idx = find_next_bit(q_vector->txr_idx, |
b4617240 PW |
858 | adapter->num_tx_queues, |
859 | r_idx + 1); | |
021230d4 AV |
860 | } |
861 | ||
30efa5a3 | 862 | /* if this is a tx only vector halve the interrupt rate */ |
021230d4 | 863 | if (q_vector->txr_count && !q_vector->rxr_count) |
30efa5a3 | 864 | q_vector->eitr = (adapter->eitr_param >> 1); |
509ee935 | 865 | else if (q_vector->rxr_count) |
30efa5a3 JB |
866 | /* rx only */ |
867 | q_vector->eitr = adapter->eitr_param; | |
021230d4 | 868 | |
509ee935 | 869 | /* |
4df10466 | 870 | * since this is initial set up don't need to call |
509ee935 JB |
871 | * ixgbe_write_eitr helper |
872 | */ | |
021230d4 | 873 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), |
b4617240 | 874 | EITR_INTS_PER_SEC_TO_REG(q_vector->eitr)); |
9a799d71 AK |
875 | } |
876 | ||
e8e26350 PW |
877 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) |
878 | ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX, | |
879 | v_idx); | |
880 | else if (adapter->hw.mac.type == ixgbe_mac_82599EB) | |
881 | ixgbe_set_ivar(adapter, -1, 1, v_idx); | |
021230d4 AV |
882 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950); |
883 | ||
41fb9248 | 884 | /* set up to autoclear timer, and the vectors */ |
021230d4 | 885 | mask = IXGBE_EIMS_ENABLE_MASK; |
41fb9248 | 886 | mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC); |
021230d4 | 887 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask); |
9a799d71 AK |
888 | } |
889 | ||
f494e8fa AV |
890 | enum latency_range { |
891 | lowest_latency = 0, | |
892 | low_latency = 1, | |
893 | bulk_latency = 2, | |
894 | latency_invalid = 255 | |
895 | }; | |
896 | ||
897 | /** | |
898 | * ixgbe_update_itr - update the dynamic ITR value based on statistics | |
899 | * @adapter: pointer to adapter | |
900 | * @eitr: eitr setting (ints per sec) to give last timeslice | |
901 | * @itr_setting: current throttle rate in ints/second | |
902 | * @packets: the number of packets during this measurement interval | |
903 | * @bytes: the number of bytes during this measurement interval | |
904 | * | |
905 | * Stores a new ITR value based on packets and byte | |
906 | * counts during the last interrupt. The advantage of per interrupt | |
907 | * computation is faster updates and more accurate ITR for the current | |
908 | * traffic pattern. Constants in this function were computed | |
909 | * based on theoretical maximum wire speed and thresholds were set based | |
910 | * on testing data as well as attempting to minimize response time | |
911 | * while increasing bulk throughput. | |
912 | * this functionality is controlled by the InterruptThrottleRate module | |
913 | * parameter (see ixgbe_param.c) | |
914 | **/ | |
915 | static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter, | |
b4617240 PW |
916 | u32 eitr, u8 itr_setting, |
917 | int packets, int bytes) | |
f494e8fa AV |
918 | { |
919 | unsigned int retval = itr_setting; | |
920 | u32 timepassed_us; | |
921 | u64 bytes_perint; | |
922 | ||
923 | if (packets == 0) | |
924 | goto update_itr_done; | |
925 | ||
926 | ||
927 | /* simple throttlerate management | |
928 | * 0-20MB/s lowest (100000 ints/s) | |
929 | * 20-100MB/s low (20000 ints/s) | |
930 | * 100-1249MB/s bulk (8000 ints/s) | |
931 | */ | |
932 | /* what was last interrupt timeslice? */ | |
933 | timepassed_us = 1000000/eitr; | |
934 | bytes_perint = bytes / timepassed_us; /* bytes/usec */ | |
935 | ||
936 | switch (itr_setting) { | |
937 | case lowest_latency: | |
938 | if (bytes_perint > adapter->eitr_low) | |
939 | retval = low_latency; | |
940 | break; | |
941 | case low_latency: | |
942 | if (bytes_perint > adapter->eitr_high) | |
943 | retval = bulk_latency; | |
944 | else if (bytes_perint <= adapter->eitr_low) | |
945 | retval = lowest_latency; | |
946 | break; | |
947 | case bulk_latency: | |
948 | if (bytes_perint <= adapter->eitr_high) | |
949 | retval = low_latency; | |
950 | break; | |
951 | } | |
952 | ||
953 | update_itr_done: | |
954 | return retval; | |
955 | } | |
956 | ||
509ee935 JB |
957 | /** |
958 | * ixgbe_write_eitr - write EITR register in hardware specific way | |
959 | * @adapter: pointer to adapter struct | |
960 | * @v_idx: vector index into q_vector array | |
961 | * @itr_reg: new value to be written in *register* format, not ints/s | |
962 | * | |
963 | * This function is made to be called by ethtool and by the driver | |
964 | * when it needs to update EITR registers at runtime. Hardware | |
965 | * specific quirks/differences are taken care of here. | |
966 | */ | |
967 | void ixgbe_write_eitr(struct ixgbe_adapter *adapter, int v_idx, u32 itr_reg) | |
968 | { | |
969 | struct ixgbe_hw *hw = &adapter->hw; | |
970 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { | |
971 | /* must write high and low 16 bits to reset counter */ | |
972 | itr_reg |= (itr_reg << 16); | |
973 | } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { | |
974 | /* | |
975 | * set the WDIS bit to not clear the timer bits and cause an | |
976 | * immediate assertion of the interrupt | |
977 | */ | |
978 | itr_reg |= IXGBE_EITR_CNT_WDIS; | |
979 | } | |
980 | IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg); | |
981 | } | |
982 | ||
f494e8fa AV |
983 | static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector) |
984 | { | |
985 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
f494e8fa AV |
986 | u32 new_itr; |
987 | u8 current_itr, ret_itr; | |
7a921c93 | 988 | int i, r_idx, v_idx = q_vector->v_idx; |
f494e8fa AV |
989 | struct ixgbe_ring *rx_ring, *tx_ring; |
990 | ||
991 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
992 | for (i = 0; i < q_vector->txr_count; i++) { | |
993 | tx_ring = &(adapter->tx_ring[r_idx]); | |
994 | ret_itr = ixgbe_update_itr(adapter, q_vector->eitr, | |
b4617240 PW |
995 | q_vector->tx_itr, |
996 | tx_ring->total_packets, | |
997 | tx_ring->total_bytes); | |
f494e8fa AV |
998 | /* if the result for this queue would decrease interrupt |
999 | * rate for this vector then use that result */ | |
30efa5a3 | 1000 | q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ? |
b4617240 | 1001 | q_vector->tx_itr - 1 : ret_itr); |
f494e8fa | 1002 | r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, |
b4617240 | 1003 | r_idx + 1); |
f494e8fa AV |
1004 | } |
1005 | ||
1006 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
1007 | for (i = 0; i < q_vector->rxr_count; i++) { | |
1008 | rx_ring = &(adapter->rx_ring[r_idx]); | |
1009 | ret_itr = ixgbe_update_itr(adapter, q_vector->eitr, | |
b4617240 PW |
1010 | q_vector->rx_itr, |
1011 | rx_ring->total_packets, | |
1012 | rx_ring->total_bytes); | |
f494e8fa AV |
1013 | /* if the result for this queue would decrease interrupt |
1014 | * rate for this vector then use that result */ | |
30efa5a3 | 1015 | q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ? |
b4617240 | 1016 | q_vector->rx_itr - 1 : ret_itr); |
f494e8fa | 1017 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, |
b4617240 | 1018 | r_idx + 1); |
f494e8fa AV |
1019 | } |
1020 | ||
30efa5a3 | 1021 | current_itr = max(q_vector->rx_itr, q_vector->tx_itr); |
f494e8fa AV |
1022 | |
1023 | switch (current_itr) { | |
1024 | /* counts and packets in update_itr are dependent on these numbers */ | |
1025 | case lowest_latency: | |
1026 | new_itr = 100000; | |
1027 | break; | |
1028 | case low_latency: | |
1029 | new_itr = 20000; /* aka hwitr = ~200 */ | |
1030 | break; | |
1031 | case bulk_latency: | |
1032 | default: | |
1033 | new_itr = 8000; | |
1034 | break; | |
1035 | } | |
1036 | ||
1037 | if (new_itr != q_vector->eitr) { | |
1038 | u32 itr_reg; | |
509ee935 JB |
1039 | |
1040 | /* save the algorithm value here, not the smoothed one */ | |
1041 | q_vector->eitr = new_itr; | |
f494e8fa AV |
1042 | /* do an exponential smoothing */ |
1043 | new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100); | |
f494e8fa | 1044 | itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr); |
509ee935 | 1045 | ixgbe_write_eitr(adapter, v_idx, itr_reg); |
f494e8fa AV |
1046 | } |
1047 | ||
1048 | return; | |
1049 | } | |
1050 | ||
0befdb3e JB |
1051 | static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr) |
1052 | { | |
1053 | struct ixgbe_hw *hw = &adapter->hw; | |
1054 | ||
1055 | if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) && | |
1056 | (eicr & IXGBE_EICR_GPI_SDP1)) { | |
1057 | DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n"); | |
1058 | /* write to clear the interrupt */ | |
1059 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); | |
1060 | } | |
1061 | } | |
cf8280ee | 1062 | |
e8e26350 PW |
1063 | static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr) |
1064 | { | |
1065 | struct ixgbe_hw *hw = &adapter->hw; | |
1066 | ||
1067 | if (eicr & IXGBE_EICR_GPI_SDP1) { | |
1068 | /* Clear the interrupt */ | |
1069 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); | |
1070 | schedule_work(&adapter->multispeed_fiber_task); | |
1071 | } else if (eicr & IXGBE_EICR_GPI_SDP2) { | |
1072 | /* Clear the interrupt */ | |
1073 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2); | |
1074 | schedule_work(&adapter->sfp_config_module_task); | |
1075 | } else { | |
1076 | /* Interrupt isn't for us... */ | |
1077 | return; | |
1078 | } | |
1079 | } | |
1080 | ||
cf8280ee JB |
1081 | static void ixgbe_check_lsc(struct ixgbe_adapter *adapter) |
1082 | { | |
1083 | struct ixgbe_hw *hw = &adapter->hw; | |
1084 | ||
1085 | adapter->lsc_int++; | |
1086 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; | |
1087 | adapter->link_check_timeout = jiffies; | |
1088 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { | |
1089 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); | |
1090 | schedule_work(&adapter->watchdog_task); | |
1091 | } | |
1092 | } | |
1093 | ||
9a799d71 AK |
1094 | static irqreturn_t ixgbe_msix_lsc(int irq, void *data) |
1095 | { | |
1096 | struct net_device *netdev = data; | |
1097 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
1098 | struct ixgbe_hw *hw = &adapter->hw; | |
54037505 DS |
1099 | u32 eicr; |
1100 | ||
1101 | /* | |
1102 | * Workaround for Silicon errata. Use clear-by-write instead | |
1103 | * of clear-by-read. Reading with EICS will return the | |
1104 | * interrupt causes without clearing, which later be done | |
1105 | * with the write to EICR. | |
1106 | */ | |
1107 | eicr = IXGBE_READ_REG(hw, IXGBE_EICS); | |
1108 | IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); | |
9a799d71 | 1109 | |
cf8280ee JB |
1110 | if (eicr & IXGBE_EICR_LSC) |
1111 | ixgbe_check_lsc(adapter); | |
d4f80882 | 1112 | |
e8e26350 PW |
1113 | if (hw->mac.type == ixgbe_mac_82598EB) |
1114 | ixgbe_check_fan_failure(adapter, eicr); | |
0befdb3e | 1115 | |
e8e26350 PW |
1116 | if (hw->mac.type == ixgbe_mac_82599EB) |
1117 | ixgbe_check_sfp_event(adapter, eicr); | |
d4f80882 AV |
1118 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
1119 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER); | |
9a799d71 AK |
1120 | |
1121 | return IRQ_HANDLED; | |
1122 | } | |
1123 | ||
1124 | static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data) | |
1125 | { | |
021230d4 AV |
1126 | struct ixgbe_q_vector *q_vector = data; |
1127 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
3a581073 | 1128 | struct ixgbe_ring *tx_ring; |
021230d4 AV |
1129 | int i, r_idx; |
1130 | ||
1131 | if (!q_vector->txr_count) | |
1132 | return IRQ_HANDLED; | |
1133 | ||
1134 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
1135 | for (i = 0; i < q_vector->txr_count; i++) { | |
3a581073 | 1136 | tx_ring = &(adapter->tx_ring[r_idx]); |
5dd2d332 | 1137 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 1138 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) |
3a581073 | 1139 | ixgbe_update_tx_dca(adapter, tx_ring); |
bd0362dd | 1140 | #endif |
3a581073 JB |
1141 | tx_ring->total_bytes = 0; |
1142 | tx_ring->total_packets = 0; | |
1143 | ixgbe_clean_tx_irq(adapter, tx_ring); | |
021230d4 | 1144 | r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, |
b4617240 | 1145 | r_idx + 1); |
021230d4 | 1146 | } |
9a799d71 | 1147 | |
9a799d71 AK |
1148 | return IRQ_HANDLED; |
1149 | } | |
1150 | ||
021230d4 AV |
1151 | /** |
1152 | * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues) | |
1153 | * @irq: unused | |
1154 | * @data: pointer to our q_vector struct for this interrupt vector | |
1155 | **/ | |
9a799d71 AK |
1156 | static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data) |
1157 | { | |
021230d4 AV |
1158 | struct ixgbe_q_vector *q_vector = data; |
1159 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
3a581073 | 1160 | struct ixgbe_ring *rx_ring; |
021230d4 | 1161 | int r_idx; |
30efa5a3 | 1162 | int i; |
021230d4 AV |
1163 | |
1164 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
30efa5a3 JB |
1165 | for (i = 0; i < q_vector->rxr_count; i++) { |
1166 | rx_ring = &(adapter->rx_ring[r_idx]); | |
1167 | rx_ring->total_bytes = 0; | |
1168 | rx_ring->total_packets = 0; | |
1169 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, | |
1170 | r_idx + 1); | |
1171 | } | |
1172 | ||
021230d4 AV |
1173 | if (!q_vector->rxr_count) |
1174 | return IRQ_HANDLED; | |
1175 | ||
30efa5a3 | 1176 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); |
3a581073 | 1177 | rx_ring = &(adapter->rx_ring[r_idx]); |
021230d4 | 1178 | /* disable interrupts on this vector only */ |
835462fc NS |
1179 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) |
1180 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, rx_ring->v_idx); | |
1181 | else if (rx_ring->v_idx & 0xFFFFFFFF) | |
1182 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), rx_ring->v_idx); | |
1183 | else | |
1184 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), | |
1185 | (rx_ring->v_idx >> 32)); | |
288379f0 | 1186 | napi_schedule(&q_vector->napi); |
021230d4 AV |
1187 | |
1188 | return IRQ_HANDLED; | |
1189 | } | |
1190 | ||
1191 | static irqreturn_t ixgbe_msix_clean_many(int irq, void *data) | |
1192 | { | |
1193 | ixgbe_msix_clean_rx(irq, data); | |
1194 | ixgbe_msix_clean_tx(irq, data); | |
9a799d71 | 1195 | |
9a799d71 AK |
1196 | return IRQ_HANDLED; |
1197 | } | |
1198 | ||
835462fc NS |
1199 | static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter, |
1200 | u64 qmask) | |
1201 | { | |
1202 | u32 mask; | |
1203 | ||
1204 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { | |
1205 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); | |
1206 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); | |
1207 | } else { | |
1208 | mask = (qmask & 0xFFFFFFFF); | |
1209 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask); | |
1210 | mask = (qmask >> 32); | |
1211 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask); | |
1212 | } | |
1213 | /* skip the flush */ | |
1214 | } | |
1215 | ||
021230d4 AV |
1216 | /** |
1217 | * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine | |
1218 | * @napi: napi struct with our devices info in it | |
1219 | * @budget: amount of work driver is allowed to do this pass, in packets | |
1220 | * | |
f0848276 JB |
1221 | * This function is optimized for cleaning one queue only on a single |
1222 | * q_vector!!! | |
021230d4 | 1223 | **/ |
9a799d71 AK |
1224 | static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget) |
1225 | { | |
021230d4 | 1226 | struct ixgbe_q_vector *q_vector = |
b4617240 | 1227 | container_of(napi, struct ixgbe_q_vector, napi); |
021230d4 | 1228 | struct ixgbe_adapter *adapter = q_vector->adapter; |
f0848276 | 1229 | struct ixgbe_ring *rx_ring = NULL; |
9a799d71 | 1230 | int work_done = 0; |
021230d4 | 1231 | long r_idx; |
9a799d71 | 1232 | |
021230d4 | 1233 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); |
3a581073 | 1234 | rx_ring = &(adapter->rx_ring[r_idx]); |
5dd2d332 | 1235 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 1236 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) |
3a581073 | 1237 | ixgbe_update_rx_dca(adapter, rx_ring); |
bd0362dd | 1238 | #endif |
9a799d71 | 1239 | |
78b6f4ce | 1240 | ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget); |
9a799d71 | 1241 | |
021230d4 AV |
1242 | /* If all Rx work done, exit the polling mode */ |
1243 | if (work_done < budget) { | |
288379f0 | 1244 | napi_complete(napi); |
509ee935 | 1245 | if (adapter->itr_setting & 1) |
f494e8fa | 1246 | ixgbe_set_itr_msix(q_vector); |
9a799d71 | 1247 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
835462fc | 1248 | ixgbe_irq_enable_queues(adapter, rx_ring->v_idx); |
9a799d71 AK |
1249 | } |
1250 | ||
1251 | return work_done; | |
1252 | } | |
1253 | ||
f0848276 JB |
1254 | /** |
1255 | * ixgbe_clean_rxonly_many - msix (aka one shot) rx clean routine | |
1256 | * @napi: napi struct with our devices info in it | |
1257 | * @budget: amount of work driver is allowed to do this pass, in packets | |
1258 | * | |
1259 | * This function will clean more than one rx queue associated with a | |
1260 | * q_vector. | |
1261 | **/ | |
1262 | static int ixgbe_clean_rxonly_many(struct napi_struct *napi, int budget) | |
1263 | { | |
1264 | struct ixgbe_q_vector *q_vector = | |
1265 | container_of(napi, struct ixgbe_q_vector, napi); | |
1266 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
f0848276 JB |
1267 | struct ixgbe_ring *rx_ring = NULL; |
1268 | int work_done = 0, i; | |
1269 | long r_idx; | |
835462fc | 1270 | u64 enable_mask = 0; |
f0848276 JB |
1271 | |
1272 | /* attempt to distribute budget to each queue fairly, but don't allow | |
1273 | * the budget to go below 1 because we'll exit polling */ | |
1274 | budget /= (q_vector->rxr_count ?: 1); | |
1275 | budget = max(budget, 1); | |
1276 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
1277 | for (i = 0; i < q_vector->rxr_count; i++) { | |
1278 | rx_ring = &(adapter->rx_ring[r_idx]); | |
5dd2d332 | 1279 | #ifdef CONFIG_IXGBE_DCA |
f0848276 JB |
1280 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) |
1281 | ixgbe_update_rx_dca(adapter, rx_ring); | |
1282 | #endif | |
78b6f4ce | 1283 | ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget); |
f0848276 JB |
1284 | enable_mask |= rx_ring->v_idx; |
1285 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, | |
1286 | r_idx + 1); | |
1287 | } | |
1288 | ||
1289 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
1290 | rx_ring = &(adapter->rx_ring[r_idx]); | |
1291 | /* If all Rx work done, exit the polling mode */ | |
7f821875 | 1292 | if (work_done < budget) { |
288379f0 | 1293 | napi_complete(napi); |
509ee935 | 1294 | if (adapter->itr_setting & 1) |
f0848276 JB |
1295 | ixgbe_set_itr_msix(q_vector); |
1296 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
835462fc | 1297 | ixgbe_irq_enable_queues(adapter, enable_mask); |
f0848276 JB |
1298 | return 0; |
1299 | } | |
1300 | ||
1301 | return work_done; | |
1302 | } | |
021230d4 | 1303 | static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx, |
b4617240 | 1304 | int r_idx) |
021230d4 | 1305 | { |
7a921c93 AD |
1306 | struct ixgbe_q_vector *q_vector = a->q_vector[v_idx]; |
1307 | ||
1308 | set_bit(r_idx, q_vector->rxr_idx); | |
1309 | q_vector->rxr_count++; | |
021230d4 AV |
1310 | a->rx_ring[r_idx].v_idx = 1 << v_idx; |
1311 | } | |
1312 | ||
1313 | static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx, | |
7a921c93 | 1314 | int t_idx) |
021230d4 | 1315 | { |
7a921c93 AD |
1316 | struct ixgbe_q_vector *q_vector = a->q_vector[v_idx]; |
1317 | ||
1318 | set_bit(t_idx, q_vector->txr_idx); | |
1319 | q_vector->txr_count++; | |
1320 | a->tx_ring[t_idx].v_idx = 1 << v_idx; | |
021230d4 AV |
1321 | } |
1322 | ||
9a799d71 | 1323 | /** |
021230d4 AV |
1324 | * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors |
1325 | * @adapter: board private structure to initialize | |
1326 | * @vectors: allotted vector count for descriptor rings | |
9a799d71 | 1327 | * |
021230d4 AV |
1328 | * This function maps descriptor rings to the queue-specific vectors |
1329 | * we were allotted through the MSI-X enabling code. Ideally, we'd have | |
1330 | * one vector per ring/queue, but on a constrained vector budget, we | |
1331 | * group the rings as "efficiently" as possible. You would add new | |
1332 | * mapping configurations in here. | |
9a799d71 | 1333 | **/ |
021230d4 | 1334 | static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter, |
b4617240 | 1335 | int vectors) |
021230d4 AV |
1336 | { |
1337 | int v_start = 0; | |
1338 | int rxr_idx = 0, txr_idx = 0; | |
1339 | int rxr_remaining = adapter->num_rx_queues; | |
1340 | int txr_remaining = adapter->num_tx_queues; | |
1341 | int i, j; | |
1342 | int rqpv, tqpv; | |
1343 | int err = 0; | |
1344 | ||
1345 | /* No mapping required if MSI-X is disabled. */ | |
1346 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
1347 | goto out; | |
9a799d71 | 1348 | |
021230d4 AV |
1349 | /* |
1350 | * The ideal configuration... | |
1351 | * We have enough vectors to map one per queue. | |
1352 | */ | |
1353 | if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) { | |
1354 | for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++) | |
1355 | map_vector_to_rxq(adapter, v_start, rxr_idx); | |
9a799d71 | 1356 | |
021230d4 AV |
1357 | for (; txr_idx < txr_remaining; v_start++, txr_idx++) |
1358 | map_vector_to_txq(adapter, v_start, txr_idx); | |
9a799d71 | 1359 | |
9a799d71 | 1360 | goto out; |
021230d4 | 1361 | } |
9a799d71 | 1362 | |
021230d4 AV |
1363 | /* |
1364 | * If we don't have enough vectors for a 1-to-1 | |
1365 | * mapping, we'll have to group them so there are | |
1366 | * multiple queues per vector. | |
1367 | */ | |
1368 | /* Re-adjusting *qpv takes care of the remainder. */ | |
1369 | for (i = v_start; i < vectors; i++) { | |
1370 | rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i); | |
1371 | for (j = 0; j < rqpv; j++) { | |
1372 | map_vector_to_rxq(adapter, i, rxr_idx); | |
1373 | rxr_idx++; | |
1374 | rxr_remaining--; | |
1375 | } | |
1376 | } | |
1377 | for (i = v_start; i < vectors; i++) { | |
1378 | tqpv = DIV_ROUND_UP(txr_remaining, vectors - i); | |
1379 | for (j = 0; j < tqpv; j++) { | |
1380 | map_vector_to_txq(adapter, i, txr_idx); | |
1381 | txr_idx++; | |
1382 | txr_remaining--; | |
9a799d71 | 1383 | } |
9a799d71 AK |
1384 | } |
1385 | ||
021230d4 AV |
1386 | out: |
1387 | return err; | |
1388 | } | |
1389 | ||
1390 | /** | |
1391 | * ixgbe_request_msix_irqs - Initialize MSI-X interrupts | |
1392 | * @adapter: board private structure | |
1393 | * | |
1394 | * ixgbe_request_msix_irqs allocates MSI-X vectors and requests | |
1395 | * interrupts from the kernel. | |
1396 | **/ | |
1397 | static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter) | |
1398 | { | |
1399 | struct net_device *netdev = adapter->netdev; | |
1400 | irqreturn_t (*handler)(int, void *); | |
1401 | int i, vector, q_vectors, err; | |
cb13fc20 | 1402 | int ri=0, ti=0; |
021230d4 AV |
1403 | |
1404 | /* Decrement for Other and TCP Timer vectors */ | |
1405 | q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
1406 | ||
1407 | /* Map the Tx/Rx rings to the vectors we were allotted. */ | |
1408 | err = ixgbe_map_rings_to_vectors(adapter, q_vectors); | |
1409 | if (err) | |
1410 | goto out; | |
1411 | ||
1412 | #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \ | |
b4617240 PW |
1413 | (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \ |
1414 | &ixgbe_msix_clean_many) | |
021230d4 | 1415 | for (vector = 0; vector < q_vectors; vector++) { |
7a921c93 | 1416 | handler = SET_HANDLER(adapter->q_vector[vector]); |
cb13fc20 RO |
1417 | |
1418 | if(handler == &ixgbe_msix_clean_rx) { | |
1419 | sprintf(adapter->name[vector], "%s-%s-%d", | |
1420 | netdev->name, "rx", ri++); | |
1421 | } | |
1422 | else if(handler == &ixgbe_msix_clean_tx) { | |
1423 | sprintf(adapter->name[vector], "%s-%s-%d", | |
1424 | netdev->name, "tx", ti++); | |
1425 | } | |
1426 | else | |
1427 | sprintf(adapter->name[vector], "%s-%s-%d", | |
1428 | netdev->name, "TxRx", vector); | |
1429 | ||
021230d4 | 1430 | err = request_irq(adapter->msix_entries[vector].vector, |
b4617240 | 1431 | handler, 0, adapter->name[vector], |
7a921c93 | 1432 | adapter->q_vector[vector]); |
9a799d71 AK |
1433 | if (err) { |
1434 | DPRINTK(PROBE, ERR, | |
b4617240 PW |
1435 | "request_irq failed for MSIX interrupt " |
1436 | "Error: %d\n", err); | |
021230d4 | 1437 | goto free_queue_irqs; |
9a799d71 | 1438 | } |
9a799d71 AK |
1439 | } |
1440 | ||
021230d4 AV |
1441 | sprintf(adapter->name[vector], "%s:lsc", netdev->name); |
1442 | err = request_irq(adapter->msix_entries[vector].vector, | |
b4617240 | 1443 | &ixgbe_msix_lsc, 0, adapter->name[vector], netdev); |
9a799d71 AK |
1444 | if (err) { |
1445 | DPRINTK(PROBE, ERR, | |
1446 | "request_irq for msix_lsc failed: %d\n", err); | |
021230d4 | 1447 | goto free_queue_irqs; |
9a799d71 AK |
1448 | } |
1449 | ||
9a799d71 AK |
1450 | return 0; |
1451 | ||
021230d4 AV |
1452 | free_queue_irqs: |
1453 | for (i = vector - 1; i >= 0; i--) | |
1454 | free_irq(adapter->msix_entries[--vector].vector, | |
7a921c93 | 1455 | adapter->q_vector[i]); |
021230d4 AV |
1456 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; |
1457 | pci_disable_msix(adapter->pdev); | |
9a799d71 AK |
1458 | kfree(adapter->msix_entries); |
1459 | adapter->msix_entries = NULL; | |
021230d4 | 1460 | out: |
9a799d71 AK |
1461 | return err; |
1462 | } | |
1463 | ||
f494e8fa AV |
1464 | static void ixgbe_set_itr(struct ixgbe_adapter *adapter) |
1465 | { | |
7a921c93 | 1466 | struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; |
f494e8fa AV |
1467 | u8 current_itr; |
1468 | u32 new_itr = q_vector->eitr; | |
1469 | struct ixgbe_ring *rx_ring = &adapter->rx_ring[0]; | |
1470 | struct ixgbe_ring *tx_ring = &adapter->tx_ring[0]; | |
1471 | ||
30efa5a3 | 1472 | q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr, |
b4617240 PW |
1473 | q_vector->tx_itr, |
1474 | tx_ring->total_packets, | |
1475 | tx_ring->total_bytes); | |
30efa5a3 | 1476 | q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr, |
b4617240 PW |
1477 | q_vector->rx_itr, |
1478 | rx_ring->total_packets, | |
1479 | rx_ring->total_bytes); | |
f494e8fa | 1480 | |
30efa5a3 | 1481 | current_itr = max(q_vector->rx_itr, q_vector->tx_itr); |
f494e8fa AV |
1482 | |
1483 | switch (current_itr) { | |
1484 | /* counts and packets in update_itr are dependent on these numbers */ | |
1485 | case lowest_latency: | |
1486 | new_itr = 100000; | |
1487 | break; | |
1488 | case low_latency: | |
1489 | new_itr = 20000; /* aka hwitr = ~200 */ | |
1490 | break; | |
1491 | case bulk_latency: | |
1492 | new_itr = 8000; | |
1493 | break; | |
1494 | default: | |
1495 | break; | |
1496 | } | |
1497 | ||
1498 | if (new_itr != q_vector->eitr) { | |
1499 | u32 itr_reg; | |
509ee935 JB |
1500 | |
1501 | /* save the algorithm value here, not the smoothed one */ | |
1502 | q_vector->eitr = new_itr; | |
f494e8fa AV |
1503 | /* do an exponential smoothing */ |
1504 | new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100); | |
f494e8fa | 1505 | itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr); |
509ee935 | 1506 | ixgbe_write_eitr(adapter, 0, itr_reg); |
f494e8fa AV |
1507 | } |
1508 | ||
1509 | return; | |
1510 | } | |
1511 | ||
79aefa45 AD |
1512 | /** |
1513 | * ixgbe_irq_enable - Enable default interrupt generation settings | |
1514 | * @adapter: board private structure | |
1515 | **/ | |
1516 | static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter) | |
1517 | { | |
1518 | u32 mask; | |
835462fc NS |
1519 | |
1520 | mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE); | |
6ab33d51 DM |
1521 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) |
1522 | mask |= IXGBE_EIMS_GPI_SDP1; | |
e8e26350 | 1523 | if (adapter->hw.mac.type == ixgbe_mac_82599EB) { |
2a41ff81 | 1524 | mask |= IXGBE_EIMS_ECC; |
e8e26350 PW |
1525 | mask |= IXGBE_EIMS_GPI_SDP1; |
1526 | mask |= IXGBE_EIMS_GPI_SDP2; | |
1527 | } | |
1528 | ||
79aefa45 | 1529 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); |
835462fc | 1530 | ixgbe_irq_enable_queues(adapter, ~0); |
79aefa45 AD |
1531 | IXGBE_WRITE_FLUSH(&adapter->hw); |
1532 | } | |
021230d4 | 1533 | |
9a799d71 | 1534 | /** |
021230d4 | 1535 | * ixgbe_intr - legacy mode Interrupt Handler |
9a799d71 AK |
1536 | * @irq: interrupt number |
1537 | * @data: pointer to a network interface device structure | |
9a799d71 AK |
1538 | **/ |
1539 | static irqreturn_t ixgbe_intr(int irq, void *data) | |
1540 | { | |
1541 | struct net_device *netdev = data; | |
1542 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
1543 | struct ixgbe_hw *hw = &adapter->hw; | |
7a921c93 | 1544 | struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; |
9a799d71 AK |
1545 | u32 eicr; |
1546 | ||
54037505 DS |
1547 | /* |
1548 | * Workaround for silicon errata. Mask the interrupts | |
1549 | * before the read of EICR. | |
1550 | */ | |
1551 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); | |
1552 | ||
021230d4 AV |
1553 | /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read |
1554 | * therefore no explict interrupt disable is necessary */ | |
1555 | eicr = IXGBE_READ_REG(hw, IXGBE_EICR); | |
f47cf66e JB |
1556 | if (!eicr) { |
1557 | /* shared interrupt alert! | |
1558 | * make sure interrupts are enabled because the read will | |
1559 | * have disabled interrupts due to EIAM */ | |
1560 | ixgbe_irq_enable(adapter); | |
9a799d71 | 1561 | return IRQ_NONE; /* Not our interrupt */ |
f47cf66e | 1562 | } |
9a799d71 | 1563 | |
cf8280ee JB |
1564 | if (eicr & IXGBE_EICR_LSC) |
1565 | ixgbe_check_lsc(adapter); | |
021230d4 | 1566 | |
e8e26350 PW |
1567 | if (hw->mac.type == ixgbe_mac_82599EB) |
1568 | ixgbe_check_sfp_event(adapter, eicr); | |
1569 | ||
0befdb3e JB |
1570 | ixgbe_check_fan_failure(adapter, eicr); |
1571 | ||
7a921c93 | 1572 | if (napi_schedule_prep(&(q_vector->napi))) { |
f494e8fa AV |
1573 | adapter->tx_ring[0].total_packets = 0; |
1574 | adapter->tx_ring[0].total_bytes = 0; | |
1575 | adapter->rx_ring[0].total_packets = 0; | |
1576 | adapter->rx_ring[0].total_bytes = 0; | |
021230d4 | 1577 | /* would disable interrupts here but EIAM disabled it */ |
7a921c93 | 1578 | __napi_schedule(&(q_vector->napi)); |
9a799d71 AK |
1579 | } |
1580 | ||
1581 | return IRQ_HANDLED; | |
1582 | } | |
1583 | ||
021230d4 AV |
1584 | static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter) |
1585 | { | |
1586 | int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
1587 | ||
1588 | for (i = 0; i < q_vectors; i++) { | |
7a921c93 | 1589 | struct ixgbe_q_vector *q_vector = adapter->q_vector[i]; |
021230d4 AV |
1590 | bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES); |
1591 | bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES); | |
1592 | q_vector->rxr_count = 0; | |
1593 | q_vector->txr_count = 0; | |
1594 | } | |
1595 | } | |
1596 | ||
9a799d71 AK |
1597 | /** |
1598 | * ixgbe_request_irq - initialize interrupts | |
1599 | * @adapter: board private structure | |
1600 | * | |
1601 | * Attempts to configure interrupts using the best available | |
1602 | * capabilities of the hardware and kernel. | |
1603 | **/ | |
021230d4 | 1604 | static int ixgbe_request_irq(struct ixgbe_adapter *adapter) |
9a799d71 AK |
1605 | { |
1606 | struct net_device *netdev = adapter->netdev; | |
021230d4 | 1607 | int err; |
9a799d71 | 1608 | |
021230d4 AV |
1609 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
1610 | err = ixgbe_request_msix_irqs(adapter); | |
1611 | } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) { | |
1612 | err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0, | |
b4617240 | 1613 | netdev->name, netdev); |
021230d4 AV |
1614 | } else { |
1615 | err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED, | |
b4617240 | 1616 | netdev->name, netdev); |
9a799d71 AK |
1617 | } |
1618 | ||
9a799d71 AK |
1619 | if (err) |
1620 | DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err); | |
1621 | ||
9a799d71 AK |
1622 | return err; |
1623 | } | |
1624 | ||
1625 | static void ixgbe_free_irq(struct ixgbe_adapter *adapter) | |
1626 | { | |
1627 | struct net_device *netdev = adapter->netdev; | |
1628 | ||
1629 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
021230d4 | 1630 | int i, q_vectors; |
9a799d71 | 1631 | |
021230d4 AV |
1632 | q_vectors = adapter->num_msix_vectors; |
1633 | ||
1634 | i = q_vectors - 1; | |
9a799d71 | 1635 | free_irq(adapter->msix_entries[i].vector, netdev); |
9a799d71 | 1636 | |
021230d4 AV |
1637 | i--; |
1638 | for (; i >= 0; i--) { | |
1639 | free_irq(adapter->msix_entries[i].vector, | |
7a921c93 | 1640 | adapter->q_vector[i]); |
021230d4 AV |
1641 | } |
1642 | ||
1643 | ixgbe_reset_q_vectors(adapter); | |
1644 | } else { | |
1645 | free_irq(adapter->pdev->irq, netdev); | |
9a799d71 AK |
1646 | } |
1647 | } | |
1648 | ||
22d5a71b JB |
1649 | /** |
1650 | * ixgbe_irq_disable - Mask off interrupt generation on the NIC | |
1651 | * @adapter: board private structure | |
1652 | **/ | |
1653 | static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) | |
1654 | { | |
835462fc NS |
1655 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
1656 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); | |
1657 | } else { | |
1658 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000); | |
1659 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0); | |
22d5a71b | 1660 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0); |
22d5a71b JB |
1661 | } |
1662 | IXGBE_WRITE_FLUSH(&adapter->hw); | |
1663 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
1664 | int i; | |
1665 | for (i = 0; i < adapter->num_msix_vectors; i++) | |
1666 | synchronize_irq(adapter->msix_entries[i].vector); | |
1667 | } else { | |
1668 | synchronize_irq(adapter->pdev->irq); | |
1669 | } | |
1670 | } | |
1671 | ||
9a799d71 AK |
1672 | /** |
1673 | * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts | |
1674 | * | |
1675 | **/ | |
1676 | static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter) | |
1677 | { | |
9a799d71 AK |
1678 | struct ixgbe_hw *hw = &adapter->hw; |
1679 | ||
021230d4 | 1680 | IXGBE_WRITE_REG(hw, IXGBE_EITR(0), |
30efa5a3 | 1681 | EITR_INTS_PER_SEC_TO_REG(adapter->eitr_param)); |
9a799d71 | 1682 | |
e8e26350 PW |
1683 | ixgbe_set_ivar(adapter, 0, 0, 0); |
1684 | ixgbe_set_ivar(adapter, 1, 0, 0); | |
021230d4 AV |
1685 | |
1686 | map_vector_to_rxq(adapter, 0, 0); | |
1687 | map_vector_to_txq(adapter, 0, 0); | |
1688 | ||
1689 | DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n"); | |
9a799d71 AK |
1690 | } |
1691 | ||
1692 | /** | |
3a581073 | 1693 | * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset |
9a799d71 AK |
1694 | * @adapter: board private structure |
1695 | * | |
1696 | * Configure the Tx unit of the MAC after a reset. | |
1697 | **/ | |
1698 | static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) | |
1699 | { | |
12207e49 | 1700 | u64 tdba; |
9a799d71 | 1701 | struct ixgbe_hw *hw = &adapter->hw; |
021230d4 | 1702 | u32 i, j, tdlen, txctrl; |
9a799d71 AK |
1703 | |
1704 | /* Setup the HW Tx Head and Tail descriptor pointers */ | |
1705 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
e01c31a5 JB |
1706 | struct ixgbe_ring *ring = &adapter->tx_ring[i]; |
1707 | j = ring->reg_idx; | |
1708 | tdba = ring->dma; | |
1709 | tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc); | |
021230d4 | 1710 | IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j), |
284901a9 | 1711 | (tdba & DMA_BIT_MASK(32))); |
021230d4 AV |
1712 | IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32)); |
1713 | IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen); | |
1714 | IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0); | |
1715 | IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0); | |
1716 | adapter->tx_ring[i].head = IXGBE_TDH(j); | |
1717 | adapter->tx_ring[i].tail = IXGBE_TDT(j); | |
1718 | /* Disable Tx Head Writeback RO bit, since this hoses | |
1719 | * bookkeeping if things aren't delivered in order. | |
1720 | */ | |
e01c31a5 | 1721 | txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j)); |
021230d4 | 1722 | txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN; |
e01c31a5 | 1723 | IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl); |
9a799d71 | 1724 | } |
e8e26350 PW |
1725 | if (hw->mac.type == ixgbe_mac_82599EB) { |
1726 | /* We enable 8 traffic classes, DCB only */ | |
1727 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) | |
1728 | IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA | | |
1729 | IXGBE_MTQC_8TC_8TQ)); | |
1730 | } | |
9a799d71 AK |
1731 | } |
1732 | ||
e8e26350 | 1733 | #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 |
cc41ac7c JB |
1734 | |
1735 | static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, int index) | |
1736 | { | |
1737 | struct ixgbe_ring *rx_ring; | |
1738 | u32 srrctl; | |
e8e26350 | 1739 | int queue0 = 0; |
3be1adfb AD |
1740 | unsigned long mask; |
1741 | ||
e8e26350 PW |
1742 | if (adapter->hw.mac.type == ixgbe_mac_82599EB) { |
1743 | queue0 = index; | |
cc41ac7c | 1744 | } else { |
3be1adfb AD |
1745 | mask = (unsigned long) adapter->ring_feature[RING_F_RSS].mask; |
1746 | queue0 = index & mask; | |
1747 | index = index & mask; | |
cc41ac7c | 1748 | } |
3be1adfb | 1749 | |
cc41ac7c JB |
1750 | rx_ring = &adapter->rx_ring[queue0]; |
1751 | ||
1752 | srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index)); | |
1753 | ||
1754 | srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK; | |
1755 | srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK; | |
1756 | ||
1757 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { | |
32344a39 JB |
1758 | u16 bufsz = IXGBE_RXBUFFER_2048; |
1759 | /* grow the amount we can receive on large page machines */ | |
1760 | if (bufsz < (PAGE_SIZE / 2)) | |
1761 | bufsz = (PAGE_SIZE / 2); | |
1762 | /* cap the bufsz at our largest descriptor size */ | |
1763 | bufsz = min((u16)IXGBE_MAX_RXBUFFER, bufsz); | |
1764 | ||
1765 | srrctl |= bufsz >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
cc41ac7c JB |
1766 | srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS; |
1767 | srrctl |= ((IXGBE_RX_HDR_SIZE << | |
b4617240 PW |
1768 | IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) & |
1769 | IXGBE_SRRCTL_BSIZEHDR_MASK); | |
cc41ac7c JB |
1770 | } else { |
1771 | srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; | |
1772 | ||
1773 | if (rx_ring->rx_buf_len == MAXIMUM_ETHERNET_VLAN_SIZE) | |
1774 | srrctl |= IXGBE_RXBUFFER_2048 >> | |
1775 | IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
1776 | else | |
1777 | srrctl |= rx_ring->rx_buf_len >> | |
1778 | IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
1779 | } | |
e8e26350 | 1780 | |
cc41ac7c JB |
1781 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl); |
1782 | } | |
9a799d71 | 1783 | |
9a799d71 | 1784 | /** |
3a581073 | 1785 | * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset |
9a799d71 AK |
1786 | * @adapter: board private structure |
1787 | * | |
1788 | * Configure the Rx unit of the MAC after a reset. | |
1789 | **/ | |
1790 | static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) | |
1791 | { | |
1792 | u64 rdba; | |
1793 | struct ixgbe_hw *hw = &adapter->hw; | |
1794 | struct net_device *netdev = adapter->netdev; | |
1795 | int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; | |
021230d4 | 1796 | int i, j; |
9a799d71 | 1797 | u32 rdlen, rxctrl, rxcsum; |
7c6e0a43 JB |
1798 | static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D, |
1799 | 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE, | |
1800 | 0x6A3E67EA, 0x14364D17, 0x3BED200D}; | |
9a799d71 | 1801 | u32 fctrl, hlreg0; |
509ee935 | 1802 | u32 reta = 0, mrqc = 0; |
cc41ac7c | 1803 | u32 rdrxctl; |
f8212f97 | 1804 | u32 rscctrl; |
7c6e0a43 | 1805 | int rx_buf_len; |
9a799d71 AK |
1806 | |
1807 | /* Decide whether to use packet split mode or not */ | |
762f4c57 | 1808 | adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED; |
9a799d71 AK |
1809 | |
1810 | /* Set the RX buffer length according to the mode */ | |
1811 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { | |
7c6e0a43 | 1812 | rx_buf_len = IXGBE_RX_HDR_SIZE; |
e8e26350 PW |
1813 | if (hw->mac.type == ixgbe_mac_82599EB) { |
1814 | /* PSRTYPE must be initialized in 82599 */ | |
1815 | u32 psrtype = IXGBE_PSRTYPE_TCPHDR | | |
1816 | IXGBE_PSRTYPE_UDPHDR | | |
1817 | IXGBE_PSRTYPE_IPV4HDR | | |
1818 | IXGBE_PSRTYPE_IPV6HDR; | |
1819 | IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype); | |
1820 | } | |
9a799d71 | 1821 | } else { |
f8212f97 AD |
1822 | if (!(adapter->flags & IXGBE_FLAG_RSC_ENABLED) && |
1823 | (netdev->mtu <= ETH_DATA_LEN)) | |
7c6e0a43 | 1824 | rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE; |
9a799d71 | 1825 | else |
7c6e0a43 | 1826 | rx_buf_len = ALIGN(max_frame, 1024); |
9a799d71 AK |
1827 | } |
1828 | ||
1829 | fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL); | |
1830 | fctrl |= IXGBE_FCTRL_BAM; | |
021230d4 | 1831 | fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */ |
e8e26350 | 1832 | fctrl |= IXGBE_FCTRL_PMCF; |
9a799d71 AK |
1833 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl); |
1834 | ||
1835 | hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); | |
1836 | if (adapter->netdev->mtu <= ETH_DATA_LEN) | |
1837 | hlreg0 &= ~IXGBE_HLREG0_JUMBOEN; | |
1838 | else | |
1839 | hlreg0 |= IXGBE_HLREG0_JUMBOEN; | |
1840 | IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); | |
1841 | ||
9a799d71 AK |
1842 | rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc); |
1843 | /* disable receives while setting up the descriptors */ | |
1844 | rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); | |
1845 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); | |
1846 | ||
1847 | /* Setup the HW Rx Head and Tail Descriptor Pointers and | |
1848 | * the Base and Length of the Rx Descriptor Ring */ | |
1849 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
1850 | rdba = adapter->rx_ring[i].dma; | |
7c6e0a43 | 1851 | j = adapter->rx_ring[i].reg_idx; |
284901a9 | 1852 | IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32))); |
7c6e0a43 JB |
1853 | IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32)); |
1854 | IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen); | |
1855 | IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0); | |
1856 | IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0); | |
1857 | adapter->rx_ring[i].head = IXGBE_RDH(j); | |
1858 | adapter->rx_ring[i].tail = IXGBE_RDT(j); | |
1859 | adapter->rx_ring[i].rx_buf_len = rx_buf_len; | |
cc41ac7c JB |
1860 | |
1861 | ixgbe_configure_srrctl(adapter, j); | |
9a799d71 AK |
1862 | } |
1863 | ||
e8e26350 PW |
1864 | if (hw->mac.type == ixgbe_mac_82598EB) { |
1865 | /* | |
1866 | * For VMDq support of different descriptor types or | |
1867 | * buffer sizes through the use of multiple SRRCTL | |
1868 | * registers, RDRXCTL.MVMEN must be set to 1 | |
1869 | * | |
1870 | * also, the manual doesn't mention it clearly but DCA hints | |
1871 | * will only use queue 0's tags unless this bit is set. Side | |
1872 | * effects of setting this bit are only that SRRCTL must be | |
1873 | * fully programmed [0..15] | |
1874 | */ | |
2a41ff81 JB |
1875 | rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); |
1876 | rdrxctl |= IXGBE_RDRXCTL_MVMEN; | |
1877 | IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); | |
2f90b865 | 1878 | } |
177db6ff | 1879 | |
e8e26350 PW |
1880 | /* Program MRQC for the distribution of queues */ |
1881 | if (hw->mac.type == ixgbe_mac_82599EB) { | |
1882 | int mask = adapter->flags & ( | |
1883 | IXGBE_FLAG_RSS_ENABLED | |
1884 | | IXGBE_FLAG_DCB_ENABLED | |
1885 | ); | |
1886 | ||
1887 | switch (mask) { | |
1888 | case (IXGBE_FLAG_RSS_ENABLED): | |
1889 | mrqc = IXGBE_MRQC_RSSEN; | |
1890 | break; | |
1891 | case (IXGBE_FLAG_DCB_ENABLED): | |
1892 | mrqc = IXGBE_MRQC_RT8TCEN; | |
1893 | break; | |
1894 | default: | |
1895 | break; | |
1896 | } | |
1897 | } | |
021230d4 | 1898 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { |
9a799d71 | 1899 | /* Fill out redirection table */ |
021230d4 AV |
1900 | for (i = 0, j = 0; i < 128; i++, j++) { |
1901 | if (j == adapter->ring_feature[RING_F_RSS].indices) | |
1902 | j = 0; | |
1903 | /* reta = 4-byte sliding window of | |
1904 | * 0x00..(indices-1)(indices-1)00..etc. */ | |
1905 | reta = (reta << 8) | (j * 0x11); | |
1906 | if ((i & 3) == 3) | |
1907 | IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); | |
9a799d71 AK |
1908 | } |
1909 | ||
1910 | /* Fill out hash function seeds */ | |
1911 | for (i = 0; i < 10; i++) | |
7c6e0a43 | 1912 | IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]); |
9a799d71 | 1913 | |
2a41ff81 JB |
1914 | if (hw->mac.type == ixgbe_mac_82598EB) |
1915 | mrqc |= IXGBE_MRQC_RSSEN; | |
9a799d71 | 1916 | /* Perform hash on these packet types */ |
2a41ff81 JB |
1917 | mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 |
1918 | | IXGBE_MRQC_RSS_FIELD_IPV4_TCP | |
1919 | | IXGBE_MRQC_RSS_FIELD_IPV4_UDP | |
1920 | | IXGBE_MRQC_RSS_FIELD_IPV6 | |
1921 | | IXGBE_MRQC_RSS_FIELD_IPV6_TCP | |
1922 | | IXGBE_MRQC_RSS_FIELD_IPV6_UDP; | |
021230d4 | 1923 | } |
2a41ff81 | 1924 | IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); |
9a799d71 | 1925 | |
021230d4 AV |
1926 | rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); |
1927 | ||
1928 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED || | |
1929 | adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) { | |
1930 | /* Disable indicating checksum in descriptor, enables | |
1931 | * RSS hash */ | |
9a799d71 | 1932 | rxcsum |= IXGBE_RXCSUM_PCSD; |
9a799d71 | 1933 | } |
021230d4 AV |
1934 | if (!(rxcsum & IXGBE_RXCSUM_PCSD)) { |
1935 | /* Enable IPv4 payload checksum for UDP fragments | |
1936 | * if PCSD is not set */ | |
1937 | rxcsum |= IXGBE_RXCSUM_IPPCSE; | |
1938 | } | |
1939 | ||
1940 | IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); | |
e8e26350 PW |
1941 | |
1942 | if (hw->mac.type == ixgbe_mac_82599EB) { | |
1943 | rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); | |
1944 | rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP; | |
f8212f97 | 1945 | rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE; |
e8e26350 PW |
1946 | IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); |
1947 | } | |
f8212f97 AD |
1948 | |
1949 | if (adapter->flags & IXGBE_FLAG_RSC_ENABLED) { | |
1950 | /* Enable 82599 HW-RSC */ | |
1951 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
1952 | j = adapter->rx_ring[i].reg_idx; | |
1953 | rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j)); | |
1954 | rscctrl |= IXGBE_RSCCTL_RSCEN; | |
1955 | /* | |
1956 | * if packet split is enabled we can only support up | |
1957 | * to max frags + 1 descriptors. | |
1958 | */ | |
1959 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) | |
1960 | #if (MAX_SKB_FRAGS < 3) | |
1961 | rscctrl |= IXGBE_RSCCTL_MAXDESC_1; | |
1962 | #elif (MAX_SKB_FRAGS < 7) | |
1963 | rscctrl |= IXGBE_RSCCTL_MAXDESC_4; | |
1964 | #elif (MAX_SKB_FRAGS < 15) | |
1965 | rscctrl |= IXGBE_RSCCTL_MAXDESC_8; | |
1966 | #else | |
1967 | rscctrl |= IXGBE_RSCCTL_MAXDESC_16; | |
1968 | #endif | |
1969 | else | |
1970 | rscctrl |= IXGBE_RSCCTL_MAXDESC_16; | |
1971 | IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl); | |
1972 | } | |
1973 | /* Disable RSC for ACK packets */ | |
1974 | IXGBE_WRITE_REG(hw, IXGBE_RSCDBU, | |
1975 | (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU))); | |
1976 | } | |
9a799d71 AK |
1977 | } |
1978 | ||
068c89b0 DS |
1979 | static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid) |
1980 | { | |
1981 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
1982 | struct ixgbe_hw *hw = &adapter->hw; | |
1983 | ||
1984 | /* add VID to filter table */ | |
1985 | hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true); | |
1986 | } | |
1987 | ||
1988 | static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) | |
1989 | { | |
1990 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
1991 | struct ixgbe_hw *hw = &adapter->hw; | |
1992 | ||
1993 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
1994 | ixgbe_irq_disable(adapter); | |
1995 | ||
1996 | vlan_group_set_device(adapter->vlgrp, vid, NULL); | |
1997 | ||
1998 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
1999 | ixgbe_irq_enable(adapter); | |
2000 | ||
2001 | /* remove VID from filter table */ | |
2002 | hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false); | |
2003 | } | |
2004 | ||
9a799d71 | 2005 | static void ixgbe_vlan_rx_register(struct net_device *netdev, |
b4617240 | 2006 | struct vlan_group *grp) |
9a799d71 AK |
2007 | { |
2008 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
2009 | u32 ctrl; | |
e8e26350 | 2010 | int i, j; |
9a799d71 | 2011 | |
d4f80882 AV |
2012 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
2013 | ixgbe_irq_disable(adapter); | |
9a799d71 AK |
2014 | adapter->vlgrp = grp; |
2015 | ||
2f90b865 AD |
2016 | /* |
2017 | * For a DCB driver, always enable VLAN tag stripping so we can | |
2018 | * still receive traffic from a DCB-enabled host even if we're | |
2019 | * not in DCB mode. | |
2020 | */ | |
2021 | ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL); | |
e8e26350 PW |
2022 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
2023 | ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE; | |
2024 | ctrl &= ~IXGBE_VLNCTRL_CFIEN; | |
2025 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl); | |
2026 | } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { | |
2027 | ctrl |= IXGBE_VLNCTRL_VFE; | |
9a799d71 AK |
2028 | /* enable VLAN tag insert/strip */ |
2029 | ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL); | |
9a799d71 AK |
2030 | ctrl &= ~IXGBE_VLNCTRL_CFIEN; |
2031 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl); | |
e8e26350 PW |
2032 | for (i = 0; i < adapter->num_rx_queues; i++) { |
2033 | j = adapter->rx_ring[i].reg_idx; | |
2034 | ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j)); | |
2035 | ctrl |= IXGBE_RXDCTL_VME; | |
2036 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl); | |
2037 | } | |
9a799d71 | 2038 | } |
e8e26350 | 2039 | ixgbe_vlan_rx_add_vid(netdev, 0); |
9a799d71 | 2040 | |
d4f80882 AV |
2041 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
2042 | ixgbe_irq_enable(adapter); | |
9a799d71 AK |
2043 | } |
2044 | ||
9a799d71 AK |
2045 | static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter) |
2046 | { | |
2047 | ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp); | |
2048 | ||
2049 | if (adapter->vlgrp) { | |
2050 | u16 vid; | |
2051 | for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) { | |
2052 | if (!vlan_group_get_device(adapter->vlgrp, vid)) | |
2053 | continue; | |
2054 | ixgbe_vlan_rx_add_vid(adapter->netdev, vid); | |
2055 | } | |
2056 | } | |
2057 | } | |
2058 | ||
2c5645cf CL |
2059 | static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq) |
2060 | { | |
2061 | struct dev_mc_list *mc_ptr; | |
2062 | u8 *addr = *mc_addr_ptr; | |
2063 | *vmdq = 0; | |
2064 | ||
2065 | mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]); | |
2066 | if (mc_ptr->next) | |
2067 | *mc_addr_ptr = mc_ptr->next->dmi_addr; | |
2068 | else | |
2069 | *mc_addr_ptr = NULL; | |
2070 | ||
2071 | return addr; | |
2072 | } | |
2073 | ||
9a799d71 | 2074 | /** |
2c5645cf | 2075 | * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set |
9a799d71 AK |
2076 | * @netdev: network interface device structure |
2077 | * | |
2c5645cf CL |
2078 | * The set_rx_method entry point is called whenever the unicast/multicast |
2079 | * address list or the network interface flags are updated. This routine is | |
2080 | * responsible for configuring the hardware for proper unicast, multicast and | |
2081 | * promiscuous mode. | |
9a799d71 | 2082 | **/ |
2c5645cf | 2083 | static void ixgbe_set_rx_mode(struct net_device *netdev) |
9a799d71 AK |
2084 | { |
2085 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
2086 | struct ixgbe_hw *hw = &adapter->hw; | |
3d01625a | 2087 | u32 fctrl, vlnctrl; |
2c5645cf CL |
2088 | u8 *addr_list = NULL; |
2089 | int addr_count = 0; | |
9a799d71 AK |
2090 | |
2091 | /* Check for Promiscuous and All Multicast modes */ | |
2092 | ||
2093 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
3d01625a | 2094 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); |
9a799d71 AK |
2095 | |
2096 | if (netdev->flags & IFF_PROMISC) { | |
2c5645cf | 2097 | hw->addr_ctrl.user_set_promisc = 1; |
9a799d71 | 2098 | fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); |
3d01625a | 2099 | vlnctrl &= ~IXGBE_VLNCTRL_VFE; |
9a799d71 | 2100 | } else { |
746b9f02 PM |
2101 | if (netdev->flags & IFF_ALLMULTI) { |
2102 | fctrl |= IXGBE_FCTRL_MPE; | |
2103 | fctrl &= ~IXGBE_FCTRL_UPE; | |
2104 | } else { | |
2105 | fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); | |
2106 | } | |
3d01625a | 2107 | vlnctrl |= IXGBE_VLNCTRL_VFE; |
2c5645cf | 2108 | hw->addr_ctrl.user_set_promisc = 0; |
9a799d71 AK |
2109 | } |
2110 | ||
2111 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); | |
3d01625a | 2112 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); |
9a799d71 | 2113 | |
2c5645cf CL |
2114 | /* reprogram secondary unicast list */ |
2115 | addr_count = netdev->uc_count; | |
2116 | if (addr_count) | |
2117 | addr_list = netdev->uc_list->dmi_addr; | |
c44ade9e JB |
2118 | hw->mac.ops.update_uc_addr_list(hw, addr_list, addr_count, |
2119 | ixgbe_addr_list_itr); | |
9a799d71 | 2120 | |
2c5645cf CL |
2121 | /* reprogram multicast list */ |
2122 | addr_count = netdev->mc_count; | |
2123 | if (addr_count) | |
2124 | addr_list = netdev->mc_list->dmi_addr; | |
c44ade9e JB |
2125 | hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count, |
2126 | ixgbe_addr_list_itr); | |
9a799d71 AK |
2127 | } |
2128 | ||
021230d4 AV |
2129 | static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter) |
2130 | { | |
2131 | int q_idx; | |
2132 | struct ixgbe_q_vector *q_vector; | |
2133 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
2134 | ||
2135 | /* legacy and MSI only use one vector */ | |
2136 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
2137 | q_vectors = 1; | |
2138 | ||
2139 | for (q_idx = 0; q_idx < q_vectors; q_idx++) { | |
f0848276 | 2140 | struct napi_struct *napi; |
7a921c93 | 2141 | q_vector = adapter->q_vector[q_idx]; |
021230d4 AV |
2142 | if (!q_vector->rxr_count) |
2143 | continue; | |
f0848276 JB |
2144 | napi = &q_vector->napi; |
2145 | if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) && | |
2146 | (q_vector->rxr_count > 1)) | |
2147 | napi->poll = &ixgbe_clean_rxonly_many; | |
2148 | ||
2149 | napi_enable(napi); | |
021230d4 AV |
2150 | } |
2151 | } | |
2152 | ||
2153 | static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter) | |
2154 | { | |
2155 | int q_idx; | |
2156 | struct ixgbe_q_vector *q_vector; | |
2157 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
2158 | ||
2159 | /* legacy and MSI only use one vector */ | |
2160 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
2161 | q_vectors = 1; | |
2162 | ||
2163 | for (q_idx = 0; q_idx < q_vectors; q_idx++) { | |
7a921c93 | 2164 | q_vector = adapter->q_vector[q_idx]; |
021230d4 AV |
2165 | if (!q_vector->rxr_count) |
2166 | continue; | |
2167 | napi_disable(&q_vector->napi); | |
2168 | } | |
2169 | } | |
2170 | ||
7a6b6f51 | 2171 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
2172 | /* |
2173 | * ixgbe_configure_dcb - Configure DCB hardware | |
2174 | * @adapter: ixgbe adapter struct | |
2175 | * | |
2176 | * This is called by the driver on open to configure the DCB hardware. | |
2177 | * This is also called by the gennetlink interface when reconfiguring | |
2178 | * the DCB state. | |
2179 | */ | |
2180 | static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter) | |
2181 | { | |
2182 | struct ixgbe_hw *hw = &adapter->hw; | |
2183 | u32 txdctl, vlnctrl; | |
2184 | int i, j; | |
2185 | ||
2186 | ixgbe_dcb_check_config(&adapter->dcb_cfg); | |
2187 | ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG); | |
2188 | ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG); | |
2189 | ||
2190 | /* reconfigure the hardware */ | |
2191 | ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg); | |
2192 | ||
2193 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
2194 | j = adapter->tx_ring[i].reg_idx; | |
2195 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)); | |
2196 | /* PThresh workaround for Tx hang with DFP enabled. */ | |
2197 | txdctl |= 32; | |
2198 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl); | |
2199 | } | |
2200 | /* Enable VLAN tag insert/strip */ | |
2201 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); | |
e8e26350 PW |
2202 | if (hw->mac.type == ixgbe_mac_82598EB) { |
2203 | vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE; | |
2204 | vlnctrl &= ~IXGBE_VLNCTRL_CFIEN; | |
2205 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); | |
2206 | } else if (hw->mac.type == ixgbe_mac_82599EB) { | |
2207 | vlnctrl |= IXGBE_VLNCTRL_VFE; | |
2208 | vlnctrl &= ~IXGBE_VLNCTRL_CFIEN; | |
2209 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); | |
2210 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
2211 | j = adapter->rx_ring[i].reg_idx; | |
2212 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); | |
2213 | vlnctrl |= IXGBE_RXDCTL_VME; | |
2214 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); | |
2215 | } | |
2216 | } | |
2f90b865 AD |
2217 | hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true); |
2218 | } | |
2219 | ||
2220 | #endif | |
9a799d71 AK |
2221 | static void ixgbe_configure(struct ixgbe_adapter *adapter) |
2222 | { | |
2223 | struct net_device *netdev = adapter->netdev; | |
2224 | int i; | |
2225 | ||
2c5645cf | 2226 | ixgbe_set_rx_mode(netdev); |
9a799d71 AK |
2227 | |
2228 | ixgbe_restore_vlan(adapter); | |
7a6b6f51 | 2229 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
2230 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { |
2231 | netif_set_gso_max_size(netdev, 32768); | |
2232 | ixgbe_configure_dcb(adapter); | |
2233 | } else { | |
2234 | netif_set_gso_max_size(netdev, 65536); | |
2235 | } | |
2236 | #else | |
2237 | netif_set_gso_max_size(netdev, 65536); | |
2238 | #endif | |
9a799d71 AK |
2239 | |
2240 | ixgbe_configure_tx(adapter); | |
2241 | ixgbe_configure_rx(adapter); | |
2242 | for (i = 0; i < adapter->num_rx_queues; i++) | |
2243 | ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i], | |
b4617240 | 2244 | (adapter->rx_ring[i].count - 1)); |
9a799d71 AK |
2245 | } |
2246 | ||
e8e26350 PW |
2247 | static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw) |
2248 | { | |
2249 | switch (hw->phy.type) { | |
2250 | case ixgbe_phy_sfp_avago: | |
2251 | case ixgbe_phy_sfp_ftl: | |
2252 | case ixgbe_phy_sfp_intel: | |
2253 | case ixgbe_phy_sfp_unknown: | |
2254 | case ixgbe_phy_tw_tyco: | |
2255 | case ixgbe_phy_tw_unknown: | |
2256 | return true; | |
2257 | default: | |
2258 | return false; | |
2259 | } | |
2260 | } | |
2261 | ||
0ecc061d | 2262 | /** |
e8e26350 PW |
2263 | * ixgbe_sfp_link_config - set up SFP+ link |
2264 | * @adapter: pointer to private adapter struct | |
2265 | **/ | |
2266 | static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter) | |
2267 | { | |
2268 | struct ixgbe_hw *hw = &adapter->hw; | |
2269 | ||
2270 | if (hw->phy.multispeed_fiber) { | |
2271 | /* | |
2272 | * In multispeed fiber setups, the device may not have | |
2273 | * had a physical connection when the driver loaded. | |
2274 | * If that's the case, the initial link configuration | |
2275 | * couldn't get the MAC into 10G or 1G mode, so we'll | |
2276 | * never have a link status change interrupt fire. | |
2277 | * We need to try and force an autonegotiation | |
2278 | * session, then bring up link. | |
2279 | */ | |
2280 | hw->mac.ops.setup_sfp(hw); | |
2281 | if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK)) | |
2282 | schedule_work(&adapter->multispeed_fiber_task); | |
2283 | } else { | |
2284 | /* | |
2285 | * Direct Attach Cu and non-multispeed fiber modules | |
2286 | * still need to be configured properly prior to | |
2287 | * attempting link. | |
2288 | */ | |
2289 | if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK)) | |
2290 | schedule_work(&adapter->sfp_config_module_task); | |
2291 | } | |
2292 | } | |
2293 | ||
2294 | /** | |
2295 | * ixgbe_non_sfp_link_config - set up non-SFP+ link | |
0ecc061d PWJ |
2296 | * @hw: pointer to private hardware struct |
2297 | * | |
2298 | * Returns 0 on success, negative on failure | |
2299 | **/ | |
e8e26350 | 2300 | static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw) |
0ecc061d PWJ |
2301 | { |
2302 | u32 autoneg; | |
2303 | bool link_up = false; | |
2304 | u32 ret = IXGBE_ERR_LINK_SETUP; | |
2305 | ||
2306 | if (hw->mac.ops.check_link) | |
2307 | ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false); | |
2308 | ||
2309 | if (ret) | |
2310 | goto link_cfg_out; | |
2311 | ||
2312 | if (hw->mac.ops.get_link_capabilities) | |
2313 | ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, | |
2314 | &hw->mac.autoneg); | |
2315 | if (ret) | |
2316 | goto link_cfg_out; | |
2317 | ||
2318 | if (hw->mac.ops.setup_link_speed) | |
2319 | ret = hw->mac.ops.setup_link_speed(hw, autoneg, true, link_up); | |
0ecc061d PWJ |
2320 | link_cfg_out: |
2321 | return ret; | |
2322 | } | |
2323 | ||
e8e26350 PW |
2324 | #define IXGBE_MAX_RX_DESC_POLL 10 |
2325 | static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter, | |
2326 | int rxr) | |
2327 | { | |
2328 | int j = adapter->rx_ring[rxr].reg_idx; | |
2329 | int k; | |
2330 | ||
2331 | for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) { | |
2332 | if (IXGBE_READ_REG(&adapter->hw, | |
2333 | IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE) | |
2334 | break; | |
2335 | else | |
2336 | msleep(1); | |
2337 | } | |
2338 | if (k >= IXGBE_MAX_RX_DESC_POLL) { | |
2339 | DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d " | |
2340 | "not set within the polling period\n", rxr); | |
2341 | } | |
2342 | ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr], | |
2343 | (adapter->rx_ring[rxr].count - 1)); | |
2344 | } | |
2345 | ||
9a799d71 AK |
2346 | static int ixgbe_up_complete(struct ixgbe_adapter *adapter) |
2347 | { | |
2348 | struct net_device *netdev = adapter->netdev; | |
9a799d71 | 2349 | struct ixgbe_hw *hw = &adapter->hw; |
021230d4 | 2350 | int i, j = 0; |
e8e26350 | 2351 | int num_rx_rings = adapter->num_rx_queues; |
0ecc061d | 2352 | int err; |
9a799d71 | 2353 | int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; |
021230d4 | 2354 | u32 txdctl, rxdctl, mhadd; |
e8e26350 | 2355 | u32 dmatxctl; |
021230d4 | 2356 | u32 gpie; |
9a799d71 | 2357 | |
5eba3699 AV |
2358 | ixgbe_get_hw_control(adapter); |
2359 | ||
021230d4 AV |
2360 | if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) || |
2361 | (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) { | |
9a799d71 AK |
2362 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
2363 | gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME | | |
b4617240 | 2364 | IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD); |
9a799d71 AK |
2365 | } else { |
2366 | /* MSI only */ | |
021230d4 | 2367 | gpie = 0; |
9a799d71 | 2368 | } |
021230d4 AV |
2369 | /* XXX: to interrupt immediately for EICS writes, enable this */ |
2370 | /* gpie |= IXGBE_GPIE_EIMEN; */ | |
2371 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
9a799d71 AK |
2372 | } |
2373 | ||
021230d4 AV |
2374 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { |
2375 | /* legacy interrupts, use EIAM to auto-mask when reading EICR, | |
2376 | * specifically only auto mask tx and rx interrupts */ | |
2377 | IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); | |
2378 | } | |
9a799d71 | 2379 | |
0befdb3e JB |
2380 | /* Enable fan failure interrupt if media type is copper */ |
2381 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
2382 | gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); | |
2383 | gpie |= IXGBE_SDP1_GPIEN; | |
2384 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
2385 | } | |
2386 | ||
e8e26350 PW |
2387 | if (hw->mac.type == ixgbe_mac_82599EB) { |
2388 | gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); | |
2389 | gpie |= IXGBE_SDP1_GPIEN; | |
2390 | gpie |= IXGBE_SDP2_GPIEN; | |
2391 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
2392 | } | |
2393 | ||
021230d4 | 2394 | mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); |
9a799d71 AK |
2395 | if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) { |
2396 | mhadd &= ~IXGBE_MHADD_MFS_MASK; | |
2397 | mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT; | |
2398 | ||
2399 | IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); | |
2400 | } | |
2401 | ||
2402 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
021230d4 AV |
2403 | j = adapter->tx_ring[i].reg_idx; |
2404 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)); | |
e01c31a5 JB |
2405 | /* enable WTHRESH=8 descriptors, to encourage burst writeback */ |
2406 | txdctl |= (8 << 16); | |
e8e26350 PW |
2407 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl); |
2408 | } | |
2409 | ||
2410 | if (hw->mac.type == ixgbe_mac_82599EB) { | |
2411 | /* DMATXCTL.EN must be set after all Tx queue config is done */ | |
2412 | dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); | |
2413 | dmatxctl |= IXGBE_DMATXCTL_TE; | |
2414 | IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl); | |
2415 | } | |
2416 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
2417 | j = adapter->tx_ring[i].reg_idx; | |
2418 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)); | |
9a799d71 | 2419 | txdctl |= IXGBE_TXDCTL_ENABLE; |
021230d4 | 2420 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl); |
9a799d71 AK |
2421 | } |
2422 | ||
e8e26350 | 2423 | for (i = 0; i < num_rx_rings; i++) { |
021230d4 AV |
2424 | j = adapter->rx_ring[i].reg_idx; |
2425 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); | |
2426 | /* enable PTHRESH=32 descriptors (half the internal cache) | |
2427 | * and HTHRESH=0 descriptors (to minimize latency on fetch), | |
2428 | * this also removes a pesky rx_no_buffer_count increment */ | |
2429 | rxdctl |= 0x0020; | |
9a799d71 | 2430 | rxdctl |= IXGBE_RXDCTL_ENABLE; |
021230d4 | 2431 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl); |
e8e26350 PW |
2432 | if (hw->mac.type == ixgbe_mac_82599EB) |
2433 | ixgbe_rx_desc_queue_enable(adapter, i); | |
9a799d71 AK |
2434 | } |
2435 | /* enable all receives */ | |
2436 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); | |
e8e26350 PW |
2437 | if (hw->mac.type == ixgbe_mac_82598EB) |
2438 | rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN); | |
2439 | else | |
2440 | rxdctl |= IXGBE_RXCTRL_RXEN; | |
2441 | hw->mac.ops.enable_rx_dma(hw, rxdctl); | |
9a799d71 AK |
2442 | |
2443 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) | |
2444 | ixgbe_configure_msix(adapter); | |
2445 | else | |
2446 | ixgbe_configure_msi_and_legacy(adapter); | |
2447 | ||
2448 | clear_bit(__IXGBE_DOWN, &adapter->state); | |
021230d4 AV |
2449 | ixgbe_napi_enable_all(adapter); |
2450 | ||
2451 | /* clear any pending interrupts, may auto mask */ | |
2452 | IXGBE_READ_REG(hw, IXGBE_EICR); | |
2453 | ||
9a799d71 AK |
2454 | ixgbe_irq_enable(adapter); |
2455 | ||
e8e26350 PW |
2456 | /* |
2457 | * For hot-pluggable SFP+ devices, a new SFP+ module may have | |
2458 | * arrived before interrupts were enabled. We need to kick off | |
2459 | * the SFP+ module setup first, then try to bring up link. | |
2460 | * If we're not hot-pluggable SFP+, we just need to configure link | |
2461 | * and bring it up. | |
2462 | */ | |
2463 | err = hw->phy.ops.identify(hw); | |
2464 | if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
2465 | DPRINTK(PROBE, ERR, "PHY not supported on this NIC %d\n", err); | |
2466 | ixgbe_down(adapter); | |
2467 | return err; | |
2468 | } | |
2469 | ||
2470 | if (ixgbe_is_sfp(hw)) { | |
2471 | ixgbe_sfp_link_config(adapter); | |
2472 | } else { | |
2473 | err = ixgbe_non_sfp_link_config(hw); | |
2474 | if (err) | |
2475 | DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err); | |
2476 | } | |
0ecc061d | 2477 | |
1da100bb PWJ |
2478 | /* enable transmits */ |
2479 | netif_tx_start_all_queues(netdev); | |
2480 | ||
9a799d71 AK |
2481 | /* bring the link up in the watchdog, this could race with our first |
2482 | * link up interrupt but shouldn't be a problem */ | |
cf8280ee JB |
2483 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; |
2484 | adapter->link_check_timeout = jiffies; | |
9a799d71 AK |
2485 | mod_timer(&adapter->watchdog_timer, jiffies); |
2486 | return 0; | |
2487 | } | |
2488 | ||
d4f80882 AV |
2489 | void ixgbe_reinit_locked(struct ixgbe_adapter *adapter) |
2490 | { | |
2491 | WARN_ON(in_interrupt()); | |
2492 | while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) | |
2493 | msleep(1); | |
2494 | ixgbe_down(adapter); | |
2495 | ixgbe_up(adapter); | |
2496 | clear_bit(__IXGBE_RESETTING, &adapter->state); | |
2497 | } | |
2498 | ||
9a799d71 AK |
2499 | int ixgbe_up(struct ixgbe_adapter *adapter) |
2500 | { | |
2501 | /* hardware has been reset, we need to reload some things */ | |
2502 | ixgbe_configure(adapter); | |
2503 | ||
2504 | return ixgbe_up_complete(adapter); | |
2505 | } | |
2506 | ||
2507 | void ixgbe_reset(struct ixgbe_adapter *adapter) | |
2508 | { | |
c44ade9e JB |
2509 | struct ixgbe_hw *hw = &adapter->hw; |
2510 | if (hw->mac.ops.init_hw(hw)) | |
2511 | dev_err(&adapter->pdev->dev, "Hardware Error\n"); | |
9a799d71 AK |
2512 | |
2513 | /* reprogram the RAR[0] in case user changed it. */ | |
c44ade9e | 2514 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); |
9a799d71 AK |
2515 | |
2516 | } | |
2517 | ||
9a799d71 AK |
2518 | /** |
2519 | * ixgbe_clean_rx_ring - Free Rx Buffers per Queue | |
2520 | * @adapter: board private structure | |
2521 | * @rx_ring: ring to free buffers from | |
2522 | **/ | |
2523 | static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter, | |
b4617240 | 2524 | struct ixgbe_ring *rx_ring) |
9a799d71 AK |
2525 | { |
2526 | struct pci_dev *pdev = adapter->pdev; | |
2527 | unsigned long size; | |
2528 | unsigned int i; | |
2529 | ||
2530 | /* Free all the Rx ring sk_buffs */ | |
2531 | ||
2532 | for (i = 0; i < rx_ring->count; i++) { | |
2533 | struct ixgbe_rx_buffer *rx_buffer_info; | |
2534 | ||
2535 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; | |
2536 | if (rx_buffer_info->dma) { | |
2537 | pci_unmap_single(pdev, rx_buffer_info->dma, | |
b4617240 PW |
2538 | rx_ring->rx_buf_len, |
2539 | PCI_DMA_FROMDEVICE); | |
9a799d71 AK |
2540 | rx_buffer_info->dma = 0; |
2541 | } | |
2542 | if (rx_buffer_info->skb) { | |
f8212f97 | 2543 | struct sk_buff *skb = rx_buffer_info->skb; |
9a799d71 | 2544 | rx_buffer_info->skb = NULL; |
f8212f97 AD |
2545 | do { |
2546 | struct sk_buff *this = skb; | |
2547 | skb = skb->prev; | |
2548 | dev_kfree_skb(this); | |
2549 | } while (skb); | |
9a799d71 AK |
2550 | } |
2551 | if (!rx_buffer_info->page) | |
2552 | continue; | |
762f4c57 JB |
2553 | pci_unmap_page(pdev, rx_buffer_info->page_dma, PAGE_SIZE / 2, |
2554 | PCI_DMA_FROMDEVICE); | |
9a799d71 | 2555 | rx_buffer_info->page_dma = 0; |
9a799d71 AK |
2556 | put_page(rx_buffer_info->page); |
2557 | rx_buffer_info->page = NULL; | |
762f4c57 | 2558 | rx_buffer_info->page_offset = 0; |
9a799d71 AK |
2559 | } |
2560 | ||
2561 | size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; | |
2562 | memset(rx_ring->rx_buffer_info, 0, size); | |
2563 | ||
2564 | /* Zero out the descriptor ring */ | |
2565 | memset(rx_ring->desc, 0, rx_ring->size); | |
2566 | ||
2567 | rx_ring->next_to_clean = 0; | |
2568 | rx_ring->next_to_use = 0; | |
2569 | ||
9891ca7c JB |
2570 | if (rx_ring->head) |
2571 | writel(0, adapter->hw.hw_addr + rx_ring->head); | |
2572 | if (rx_ring->tail) | |
2573 | writel(0, adapter->hw.hw_addr + rx_ring->tail); | |
9a799d71 AK |
2574 | } |
2575 | ||
2576 | /** | |
2577 | * ixgbe_clean_tx_ring - Free Tx Buffers | |
2578 | * @adapter: board private structure | |
2579 | * @tx_ring: ring to be cleaned | |
2580 | **/ | |
2581 | static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter, | |
b4617240 | 2582 | struct ixgbe_ring *tx_ring) |
9a799d71 AK |
2583 | { |
2584 | struct ixgbe_tx_buffer *tx_buffer_info; | |
2585 | unsigned long size; | |
2586 | unsigned int i; | |
2587 | ||
2588 | /* Free all the Tx ring sk_buffs */ | |
2589 | ||
2590 | for (i = 0; i < tx_ring->count; i++) { | |
2591 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
2592 | ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info); | |
2593 | } | |
2594 | ||
2595 | size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; | |
2596 | memset(tx_ring->tx_buffer_info, 0, size); | |
2597 | ||
2598 | /* Zero out the descriptor ring */ | |
2599 | memset(tx_ring->desc, 0, tx_ring->size); | |
2600 | ||
2601 | tx_ring->next_to_use = 0; | |
2602 | tx_ring->next_to_clean = 0; | |
2603 | ||
9891ca7c JB |
2604 | if (tx_ring->head) |
2605 | writel(0, adapter->hw.hw_addr + tx_ring->head); | |
2606 | if (tx_ring->tail) | |
2607 | writel(0, adapter->hw.hw_addr + tx_ring->tail); | |
9a799d71 AK |
2608 | } |
2609 | ||
2610 | /** | |
021230d4 | 2611 | * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues |
9a799d71 AK |
2612 | * @adapter: board private structure |
2613 | **/ | |
021230d4 | 2614 | static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter) |
9a799d71 AK |
2615 | { |
2616 | int i; | |
2617 | ||
021230d4 AV |
2618 | for (i = 0; i < adapter->num_rx_queues; i++) |
2619 | ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]); | |
9a799d71 AK |
2620 | } |
2621 | ||
2622 | /** | |
021230d4 | 2623 | * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues |
9a799d71 AK |
2624 | * @adapter: board private structure |
2625 | **/ | |
021230d4 | 2626 | static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter) |
9a799d71 AK |
2627 | { |
2628 | int i; | |
2629 | ||
021230d4 AV |
2630 | for (i = 0; i < adapter->num_tx_queues; i++) |
2631 | ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]); | |
9a799d71 AK |
2632 | } |
2633 | ||
2634 | void ixgbe_down(struct ixgbe_adapter *adapter) | |
2635 | { | |
2636 | struct net_device *netdev = adapter->netdev; | |
7f821875 | 2637 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 | 2638 | u32 rxctrl; |
7f821875 JB |
2639 | u32 txdctl; |
2640 | int i, j; | |
9a799d71 AK |
2641 | |
2642 | /* signal that we are down to the interrupt handler */ | |
2643 | set_bit(__IXGBE_DOWN, &adapter->state); | |
2644 | ||
2645 | /* disable receives */ | |
7f821875 JB |
2646 | rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); |
2647 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); | |
9a799d71 AK |
2648 | |
2649 | netif_tx_disable(netdev); | |
2650 | ||
7f821875 | 2651 | IXGBE_WRITE_FLUSH(hw); |
9a799d71 AK |
2652 | msleep(10); |
2653 | ||
7f821875 JB |
2654 | netif_tx_stop_all_queues(netdev); |
2655 | ||
9a799d71 AK |
2656 | ixgbe_irq_disable(adapter); |
2657 | ||
021230d4 | 2658 | ixgbe_napi_disable_all(adapter); |
7f821875 | 2659 | |
9a799d71 | 2660 | del_timer_sync(&adapter->watchdog_timer); |
cf8280ee | 2661 | cancel_work_sync(&adapter->watchdog_task); |
9a799d71 | 2662 | |
7f821875 JB |
2663 | /* disable transmits in the hardware now that interrupts are off */ |
2664 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
2665 | j = adapter->tx_ring[i].reg_idx; | |
2666 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)); | |
2667 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), | |
2668 | (txdctl & ~IXGBE_TXDCTL_ENABLE)); | |
2669 | } | |
88512539 PW |
2670 | /* Disable the Tx DMA engine on 82599 */ |
2671 | if (hw->mac.type == ixgbe_mac_82599EB) | |
2672 | IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, | |
2673 | (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) & | |
2674 | ~IXGBE_DMATXCTL_TE)); | |
7f821875 | 2675 | |
9a799d71 | 2676 | netif_carrier_off(netdev); |
9a799d71 | 2677 | |
5dd2d332 | 2678 | #ifdef CONFIG_IXGBE_DCA |
96b0e0f6 JB |
2679 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { |
2680 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
2681 | dca_remove_requester(&adapter->pdev->dev); | |
2682 | } | |
2683 | ||
2684 | #endif | |
6f4a0e45 PL |
2685 | if (!pci_channel_offline(adapter->pdev)) |
2686 | ixgbe_reset(adapter); | |
9a799d71 AK |
2687 | ixgbe_clean_all_tx_rings(adapter); |
2688 | ixgbe_clean_all_rx_rings(adapter); | |
2689 | ||
5dd2d332 | 2690 | #ifdef CONFIG_IXGBE_DCA |
96b0e0f6 JB |
2691 | /* since we reset the hardware DCA settings were cleared */ |
2692 | if (dca_add_requester(&adapter->pdev->dev) == 0) { | |
2693 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; | |
2694 | /* always use CB2 mode, difference is masked | |
2695 | * in the CB driver */ | |
b4617240 | 2696 | IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2); |
96b0e0f6 JB |
2697 | ixgbe_setup_dca(adapter); |
2698 | } | |
2699 | #endif | |
9a799d71 AK |
2700 | } |
2701 | ||
9a799d71 | 2702 | /** |
021230d4 AV |
2703 | * ixgbe_poll - NAPI Rx polling callback |
2704 | * @napi: structure for representing this polling device | |
2705 | * @budget: how many packets driver is allowed to clean | |
2706 | * | |
2707 | * This function is used for legacy and MSI, NAPI mode | |
9a799d71 | 2708 | **/ |
021230d4 | 2709 | static int ixgbe_poll(struct napi_struct *napi, int budget) |
9a799d71 | 2710 | { |
9a1a69ad JB |
2711 | struct ixgbe_q_vector *q_vector = |
2712 | container_of(napi, struct ixgbe_q_vector, napi); | |
021230d4 | 2713 | struct ixgbe_adapter *adapter = q_vector->adapter; |
9a1a69ad | 2714 | int tx_clean_complete, work_done = 0; |
9a799d71 | 2715 | |
5dd2d332 | 2716 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
2717 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { |
2718 | ixgbe_update_tx_dca(adapter, adapter->tx_ring); | |
2719 | ixgbe_update_rx_dca(adapter, adapter->rx_ring); | |
2720 | } | |
2721 | #endif | |
2722 | ||
9a1a69ad | 2723 | tx_clean_complete = ixgbe_clean_tx_irq(adapter, adapter->tx_ring); |
78b6f4ce | 2724 | ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget); |
9a799d71 | 2725 | |
9a1a69ad | 2726 | if (!tx_clean_complete) |
d2c7ddd6 DM |
2727 | work_done = budget; |
2728 | ||
53e52c72 DM |
2729 | /* If budget not fully consumed, exit the polling mode */ |
2730 | if (work_done < budget) { | |
288379f0 | 2731 | napi_complete(napi); |
509ee935 | 2732 | if (adapter->itr_setting & 1) |
f494e8fa | 2733 | ixgbe_set_itr(adapter); |
d4f80882 | 2734 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
835462fc | 2735 | ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE); |
9a799d71 | 2736 | } |
9a799d71 AK |
2737 | return work_done; |
2738 | } | |
2739 | ||
2740 | /** | |
2741 | * ixgbe_tx_timeout - Respond to a Tx Hang | |
2742 | * @netdev: network interface device structure | |
2743 | **/ | |
2744 | static void ixgbe_tx_timeout(struct net_device *netdev) | |
2745 | { | |
2746 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
2747 | ||
2748 | /* Do the reset outside of interrupt context */ | |
2749 | schedule_work(&adapter->reset_task); | |
2750 | } | |
2751 | ||
2752 | static void ixgbe_reset_task(struct work_struct *work) | |
2753 | { | |
2754 | struct ixgbe_adapter *adapter; | |
2755 | adapter = container_of(work, struct ixgbe_adapter, reset_task); | |
2756 | ||
2f90b865 AD |
2757 | /* If we're already down or resetting, just bail */ |
2758 | if (test_bit(__IXGBE_DOWN, &adapter->state) || | |
2759 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
2760 | return; | |
2761 | ||
9a799d71 AK |
2762 | adapter->tx_timeout_count++; |
2763 | ||
d4f80882 | 2764 | ixgbe_reinit_locked(adapter); |
9a799d71 AK |
2765 | } |
2766 | ||
bc97114d PWJ |
2767 | #ifdef CONFIG_IXGBE_DCB |
2768 | static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter) | |
b9804972 | 2769 | { |
bc97114d | 2770 | bool ret = false; |
b9804972 | 2771 | |
bc97114d PWJ |
2772 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { |
2773 | adapter->ring_feature[RING_F_DCB].mask = 0x7 << 3; | |
2774 | adapter->num_rx_queues = | |
2775 | adapter->ring_feature[RING_F_DCB].indices; | |
2776 | adapter->num_tx_queues = | |
2777 | adapter->ring_feature[RING_F_DCB].indices; | |
2778 | ret = true; | |
2779 | } else { | |
bc97114d PWJ |
2780 | ret = false; |
2781 | } | |
2f90b865 | 2782 | |
bc97114d PWJ |
2783 | return ret; |
2784 | } | |
2785 | #endif | |
2786 | ||
4df10466 JB |
2787 | /** |
2788 | * ixgbe_set_rss_queues: Allocate queues for RSS | |
2789 | * @adapter: board private structure to initialize | |
2790 | * | |
2791 | * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try | |
2792 | * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU. | |
2793 | * | |
2794 | **/ | |
bc97114d PWJ |
2795 | static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter) |
2796 | { | |
2797 | bool ret = false; | |
2798 | ||
2799 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { | |
2800 | adapter->ring_feature[RING_F_RSS].mask = 0xF; | |
2801 | adapter->num_rx_queues = | |
2802 | adapter->ring_feature[RING_F_RSS].indices; | |
2803 | adapter->num_tx_queues = | |
2804 | adapter->ring_feature[RING_F_RSS].indices; | |
2805 | ret = true; | |
2806 | } else { | |
bc97114d | 2807 | ret = false; |
b9804972 JB |
2808 | } |
2809 | ||
bc97114d PWJ |
2810 | return ret; |
2811 | } | |
2812 | ||
4df10466 JB |
2813 | /* |
2814 | * ixgbe_set_num_queues: Allocate queues for device, feature dependant | |
2815 | * @adapter: board private structure to initialize | |
2816 | * | |
2817 | * This is the top level queue allocation routine. The order here is very | |
2818 | * important, starting with the "most" number of features turned on at once, | |
2819 | * and ending with the smallest set of features. This way large combinations | |
2820 | * can be allocated if they're turned on, and smaller combinations are the | |
2821 | * fallthrough conditions. | |
2822 | * | |
2823 | **/ | |
bc97114d PWJ |
2824 | static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter) |
2825 | { | |
bc97114d PWJ |
2826 | #ifdef CONFIG_IXGBE_DCB |
2827 | if (ixgbe_set_dcb_queues(adapter)) | |
af22ab1b | 2828 | goto done; |
bc97114d PWJ |
2829 | |
2830 | #endif | |
2831 | if (ixgbe_set_rss_queues(adapter)) | |
af22ab1b WF |
2832 | goto done; |
2833 | ||
2834 | /* fallback to base case */ | |
2835 | adapter->num_rx_queues = 1; | |
2836 | adapter->num_tx_queues = 1; | |
2837 | ||
2838 | done: | |
2839 | /* Notify the stack of the (possibly) reduced Tx Queue count. */ | |
2840 | adapter->netdev->real_num_tx_queues = adapter->num_tx_queues; | |
b9804972 JB |
2841 | } |
2842 | ||
021230d4 | 2843 | static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter, |
b4617240 | 2844 | int vectors) |
021230d4 AV |
2845 | { |
2846 | int err, vector_threshold; | |
2847 | ||
2848 | /* We'll want at least 3 (vector_threshold): | |
2849 | * 1) TxQ[0] Cleanup | |
2850 | * 2) RxQ[0] Cleanup | |
2851 | * 3) Other (Link Status Change, etc.) | |
2852 | * 4) TCP Timer (optional) | |
2853 | */ | |
2854 | vector_threshold = MIN_MSIX_COUNT; | |
2855 | ||
2856 | /* The more we get, the more we will assign to Tx/Rx Cleanup | |
2857 | * for the separate queues...where Rx Cleanup >= Tx Cleanup. | |
2858 | * Right now, we simply care about how many we'll get; we'll | |
2859 | * set them up later while requesting irq's. | |
2860 | */ | |
2861 | while (vectors >= vector_threshold) { | |
2862 | err = pci_enable_msix(adapter->pdev, adapter->msix_entries, | |
b4617240 | 2863 | vectors); |
021230d4 AV |
2864 | if (!err) /* Success in acquiring all requested vectors. */ |
2865 | break; | |
2866 | else if (err < 0) | |
2867 | vectors = 0; /* Nasty failure, quit now */ | |
2868 | else /* err == number of vectors we should try again with */ | |
2869 | vectors = err; | |
2870 | } | |
2871 | ||
2872 | if (vectors < vector_threshold) { | |
2873 | /* Can't allocate enough MSI-X interrupts? Oh well. | |
2874 | * This just means we'll go with either a single MSI | |
2875 | * vector or fall back to legacy interrupts. | |
2876 | */ | |
2877 | DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n"); | |
2878 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; | |
2879 | kfree(adapter->msix_entries); | |
2880 | adapter->msix_entries = NULL; | |
021230d4 AV |
2881 | } else { |
2882 | adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */ | |
eb7f139c PWJ |
2883 | /* |
2884 | * Adjust for only the vectors we'll use, which is minimum | |
2885 | * of max_msix_q_vectors + NON_Q_VECTORS, or the number of | |
2886 | * vectors we were allocated. | |
2887 | */ | |
2888 | adapter->num_msix_vectors = min(vectors, | |
2889 | adapter->max_msix_q_vectors + NON_Q_VECTORS); | |
021230d4 AV |
2890 | } |
2891 | } | |
2892 | ||
021230d4 | 2893 | /** |
bc97114d | 2894 | * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS |
021230d4 AV |
2895 | * @adapter: board private structure to initialize |
2896 | * | |
bc97114d PWJ |
2897 | * Cache the descriptor ring offsets for RSS to the assigned rings. |
2898 | * | |
021230d4 | 2899 | **/ |
bc97114d | 2900 | static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter) |
021230d4 | 2901 | { |
bc97114d PWJ |
2902 | int i; |
2903 | bool ret = false; | |
2904 | ||
2905 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { | |
2906 | for (i = 0; i < adapter->num_rx_queues; i++) | |
2907 | adapter->rx_ring[i].reg_idx = i; | |
2908 | for (i = 0; i < adapter->num_tx_queues; i++) | |
2909 | adapter->tx_ring[i].reg_idx = i; | |
2910 | ret = true; | |
2911 | } else { | |
2912 | ret = false; | |
2913 | } | |
2914 | ||
2915 | return ret; | |
2916 | } | |
2917 | ||
2918 | #ifdef CONFIG_IXGBE_DCB | |
2919 | /** | |
2920 | * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB | |
2921 | * @adapter: board private structure to initialize | |
2922 | * | |
2923 | * Cache the descriptor ring offsets for DCB to the assigned rings. | |
2924 | * | |
2925 | **/ | |
2926 | static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter) | |
2927 | { | |
2928 | int i; | |
2929 | bool ret = false; | |
2930 | int dcb_i = adapter->ring_feature[RING_F_DCB].indices; | |
2931 | ||
2932 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
2933 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { | |
2f90b865 AD |
2934 | /* the number of queues is assumed to be symmetric */ |
2935 | for (i = 0; i < dcb_i; i++) { | |
2936 | adapter->rx_ring[i].reg_idx = i << 3; | |
2937 | adapter->tx_ring[i].reg_idx = i << 2; | |
2938 | } | |
bc97114d | 2939 | ret = true; |
e8e26350 | 2940 | } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { |
f92ef202 PW |
2941 | if (dcb_i == 8) { |
2942 | /* | |
2943 | * Tx TC0 starts at: descriptor queue 0 | |
2944 | * Tx TC1 starts at: descriptor queue 32 | |
2945 | * Tx TC2 starts at: descriptor queue 64 | |
2946 | * Tx TC3 starts at: descriptor queue 80 | |
2947 | * Tx TC4 starts at: descriptor queue 96 | |
2948 | * Tx TC5 starts at: descriptor queue 104 | |
2949 | * Tx TC6 starts at: descriptor queue 112 | |
2950 | * Tx TC7 starts at: descriptor queue 120 | |
2951 | * | |
2952 | * Rx TC0-TC7 are offset by 16 queues each | |
2953 | */ | |
2954 | for (i = 0; i < 3; i++) { | |
2955 | adapter->tx_ring[i].reg_idx = i << 5; | |
2956 | adapter->rx_ring[i].reg_idx = i << 4; | |
2957 | } | |
2958 | for ( ; i < 5; i++) { | |
2959 | adapter->tx_ring[i].reg_idx = | |
2960 | ((i + 2) << 4); | |
2961 | adapter->rx_ring[i].reg_idx = i << 4; | |
2962 | } | |
2963 | for ( ; i < dcb_i; i++) { | |
2964 | adapter->tx_ring[i].reg_idx = | |
2965 | ((i + 8) << 3); | |
2966 | adapter->rx_ring[i].reg_idx = i << 4; | |
2967 | } | |
2968 | ||
2969 | ret = true; | |
2970 | } else if (dcb_i == 4) { | |
2971 | /* | |
2972 | * Tx TC0 starts at: descriptor queue 0 | |
2973 | * Tx TC1 starts at: descriptor queue 64 | |
2974 | * Tx TC2 starts at: descriptor queue 96 | |
2975 | * Tx TC3 starts at: descriptor queue 112 | |
2976 | * | |
2977 | * Rx TC0-TC3 are offset by 32 queues each | |
2978 | */ | |
2979 | adapter->tx_ring[0].reg_idx = 0; | |
2980 | adapter->tx_ring[1].reg_idx = 64; | |
2981 | adapter->tx_ring[2].reg_idx = 96; | |
2982 | adapter->tx_ring[3].reg_idx = 112; | |
2983 | for (i = 0 ; i < dcb_i; i++) | |
2984 | adapter->rx_ring[i].reg_idx = i << 5; | |
2985 | ||
2986 | ret = true; | |
2987 | } else { | |
2988 | ret = false; | |
e8e26350 | 2989 | } |
bc97114d PWJ |
2990 | } else { |
2991 | ret = false; | |
021230d4 | 2992 | } |
bc97114d PWJ |
2993 | } else { |
2994 | ret = false; | |
021230d4 | 2995 | } |
bc97114d PWJ |
2996 | |
2997 | return ret; | |
2998 | } | |
2999 | #endif | |
3000 | ||
3001 | /** | |
3002 | * ixgbe_cache_ring_register - Descriptor ring to register mapping | |
3003 | * @adapter: board private structure to initialize | |
3004 | * | |
3005 | * Once we know the feature-set enabled for the device, we'll cache | |
3006 | * the register offset the descriptor ring is assigned to. | |
3007 | * | |
3008 | * Note, the order the various feature calls is important. It must start with | |
3009 | * the "most" features enabled at the same time, then trickle down to the | |
3010 | * least amount of features turned on at once. | |
3011 | **/ | |
3012 | static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter) | |
3013 | { | |
3014 | /* start with default case */ | |
3015 | adapter->rx_ring[0].reg_idx = 0; | |
3016 | adapter->tx_ring[0].reg_idx = 0; | |
3017 | ||
3018 | #ifdef CONFIG_IXGBE_DCB | |
3019 | if (ixgbe_cache_ring_dcb(adapter)) | |
3020 | return; | |
3021 | ||
3022 | #endif | |
3023 | if (ixgbe_cache_ring_rss(adapter)) | |
3024 | return; | |
021230d4 AV |
3025 | } |
3026 | ||
9a799d71 AK |
3027 | /** |
3028 | * ixgbe_alloc_queues - Allocate memory for all rings | |
3029 | * @adapter: board private structure to initialize | |
3030 | * | |
3031 | * We allocate one ring per queue at run-time since we don't know the | |
4df10466 JB |
3032 | * number of queues at compile-time. The polling_netdev array is |
3033 | * intended for Multiqueue, but should work fine with a single queue. | |
9a799d71 | 3034 | **/ |
2f90b865 | 3035 | static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter) |
9a799d71 AK |
3036 | { |
3037 | int i; | |
3038 | ||
3039 | adapter->tx_ring = kcalloc(adapter->num_tx_queues, | |
b4617240 | 3040 | sizeof(struct ixgbe_ring), GFP_KERNEL); |
9a799d71 | 3041 | if (!adapter->tx_ring) |
021230d4 | 3042 | goto err_tx_ring_allocation; |
9a799d71 AK |
3043 | |
3044 | adapter->rx_ring = kcalloc(adapter->num_rx_queues, | |
b4617240 | 3045 | sizeof(struct ixgbe_ring), GFP_KERNEL); |
021230d4 AV |
3046 | if (!adapter->rx_ring) |
3047 | goto err_rx_ring_allocation; | |
9a799d71 | 3048 | |
021230d4 | 3049 | for (i = 0; i < adapter->num_tx_queues; i++) { |
b9804972 | 3050 | adapter->tx_ring[i].count = adapter->tx_ring_count; |
021230d4 AV |
3051 | adapter->tx_ring[i].queue_index = i; |
3052 | } | |
b9804972 | 3053 | |
9a799d71 | 3054 | for (i = 0; i < adapter->num_rx_queues; i++) { |
b9804972 | 3055 | adapter->rx_ring[i].count = adapter->rx_ring_count; |
021230d4 AV |
3056 | adapter->rx_ring[i].queue_index = i; |
3057 | } | |
3058 | ||
3059 | ixgbe_cache_ring_register(adapter); | |
3060 | ||
3061 | return 0; | |
3062 | ||
3063 | err_rx_ring_allocation: | |
3064 | kfree(adapter->tx_ring); | |
3065 | err_tx_ring_allocation: | |
3066 | return -ENOMEM; | |
3067 | } | |
3068 | ||
3069 | /** | |
3070 | * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported | |
3071 | * @adapter: board private structure to initialize | |
3072 | * | |
3073 | * Attempt to configure the interrupts using the best available | |
3074 | * capabilities of the hardware and the kernel. | |
3075 | **/ | |
feea6a57 | 3076 | static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter) |
021230d4 | 3077 | { |
8be0e467 | 3078 | struct ixgbe_hw *hw = &adapter->hw; |
021230d4 AV |
3079 | int err = 0; |
3080 | int vector, v_budget; | |
3081 | ||
3082 | /* | |
3083 | * It's easy to be greedy for MSI-X vectors, but it really | |
3084 | * doesn't do us much good if we have a lot more vectors | |
3085 | * than CPU's. So let's be conservative and only ask for | |
3086 | * (roughly) twice the number of vectors as there are CPU's. | |
3087 | */ | |
3088 | v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues, | |
b4617240 | 3089 | (int)(num_online_cpus() * 2)) + NON_Q_VECTORS; |
021230d4 AV |
3090 | |
3091 | /* | |
3092 | * At the same time, hardware can only support a maximum of | |
8be0e467 PW |
3093 | * hw.mac->max_msix_vectors vectors. With features |
3094 | * such as RSS and VMDq, we can easily surpass the number of Rx and Tx | |
3095 | * descriptor queues supported by our device. Thus, we cap it off in | |
3096 | * those rare cases where the cpu count also exceeds our vector limit. | |
021230d4 | 3097 | */ |
8be0e467 | 3098 | v_budget = min(v_budget, (int)hw->mac.max_msix_vectors); |
021230d4 AV |
3099 | |
3100 | /* A failure in MSI-X entry allocation isn't fatal, but it does | |
3101 | * mean we disable MSI-X capabilities of the adapter. */ | |
3102 | adapter->msix_entries = kcalloc(v_budget, | |
b4617240 | 3103 | sizeof(struct msix_entry), GFP_KERNEL); |
7a921c93 AD |
3104 | if (adapter->msix_entries) { |
3105 | for (vector = 0; vector < v_budget; vector++) | |
3106 | adapter->msix_entries[vector].entry = vector; | |
021230d4 | 3107 | |
7a921c93 | 3108 | ixgbe_acquire_msix_vectors(adapter, v_budget); |
021230d4 | 3109 | |
7a921c93 AD |
3110 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
3111 | goto out; | |
3112 | } | |
021230d4 | 3113 | |
7a921c93 AD |
3114 | adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; |
3115 | adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED; | |
3116 | ixgbe_set_num_queues(adapter); | |
021230d4 | 3117 | |
021230d4 AV |
3118 | err = pci_enable_msi(adapter->pdev); |
3119 | if (!err) { | |
3120 | adapter->flags |= IXGBE_FLAG_MSI_ENABLED; | |
3121 | } else { | |
3122 | DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, " | |
b4617240 | 3123 | "falling back to legacy. Error: %d\n", err); |
021230d4 AV |
3124 | /* reset err */ |
3125 | err = 0; | |
3126 | } | |
3127 | ||
3128 | out: | |
021230d4 AV |
3129 | return err; |
3130 | } | |
3131 | ||
7a921c93 AD |
3132 | /** |
3133 | * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors | |
3134 | * @adapter: board private structure to initialize | |
3135 | * | |
3136 | * We allocate one q_vector per queue interrupt. If allocation fails we | |
3137 | * return -ENOMEM. | |
3138 | **/ | |
3139 | static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter) | |
3140 | { | |
3141 | int q_idx, num_q_vectors; | |
3142 | struct ixgbe_q_vector *q_vector; | |
3143 | int napi_vectors; | |
3144 | int (*poll)(struct napi_struct *, int); | |
3145 | ||
3146 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
3147 | num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
3148 | napi_vectors = adapter->num_rx_queues; | |
3149 | poll = &ixgbe_clean_rxonly; | |
3150 | } else { | |
3151 | num_q_vectors = 1; | |
3152 | napi_vectors = 1; | |
3153 | poll = &ixgbe_poll; | |
3154 | } | |
3155 | ||
3156 | for (q_idx = 0; q_idx < num_q_vectors; q_idx++) { | |
3157 | q_vector = kzalloc(sizeof(struct ixgbe_q_vector), GFP_KERNEL); | |
3158 | if (!q_vector) | |
3159 | goto err_out; | |
3160 | q_vector->adapter = adapter; | |
3161 | q_vector->v_idx = q_idx; | |
3162 | q_vector->eitr = adapter->eitr_param; | |
3163 | if (q_idx < napi_vectors) | |
3164 | netif_napi_add(adapter->netdev, &q_vector->napi, | |
3165 | (*poll), 64); | |
3166 | adapter->q_vector[q_idx] = q_vector; | |
3167 | } | |
3168 | ||
3169 | return 0; | |
3170 | ||
3171 | err_out: | |
3172 | while (q_idx) { | |
3173 | q_idx--; | |
3174 | q_vector = adapter->q_vector[q_idx]; | |
3175 | netif_napi_del(&q_vector->napi); | |
3176 | kfree(q_vector); | |
3177 | adapter->q_vector[q_idx] = NULL; | |
3178 | } | |
3179 | return -ENOMEM; | |
3180 | } | |
3181 | ||
3182 | /** | |
3183 | * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors | |
3184 | * @adapter: board private structure to initialize | |
3185 | * | |
3186 | * This function frees the memory allocated to the q_vectors. In addition if | |
3187 | * NAPI is enabled it will delete any references to the NAPI struct prior | |
3188 | * to freeing the q_vector. | |
3189 | **/ | |
3190 | static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter) | |
3191 | { | |
3192 | int q_idx, num_q_vectors; | |
3193 | int napi_vectors; | |
3194 | ||
3195 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
3196 | num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
3197 | napi_vectors = adapter->num_rx_queues; | |
3198 | } else { | |
3199 | num_q_vectors = 1; | |
3200 | napi_vectors = 1; | |
3201 | } | |
3202 | ||
3203 | for (q_idx = 0; q_idx < num_q_vectors; q_idx++) { | |
3204 | struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx]; | |
3205 | ||
3206 | adapter->q_vector[q_idx] = NULL; | |
3207 | if (q_idx < napi_vectors) | |
3208 | netif_napi_del(&q_vector->napi); | |
3209 | kfree(q_vector); | |
3210 | } | |
3211 | } | |
3212 | ||
2f90b865 | 3213 | void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter) |
021230d4 AV |
3214 | { |
3215 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
3216 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; | |
3217 | pci_disable_msix(adapter->pdev); | |
3218 | kfree(adapter->msix_entries); | |
3219 | adapter->msix_entries = NULL; | |
3220 | } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) { | |
3221 | adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED; | |
3222 | pci_disable_msi(adapter->pdev); | |
3223 | } | |
3224 | return; | |
3225 | } | |
3226 | ||
3227 | /** | |
3228 | * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme | |
3229 | * @adapter: board private structure to initialize | |
3230 | * | |
3231 | * We determine which interrupt scheme to use based on... | |
3232 | * - Kernel support (MSI, MSI-X) | |
3233 | * - which can be user-defined (via MODULE_PARAM) | |
3234 | * - Hardware queue count (num_*_queues) | |
3235 | * - defined by miscellaneous hardware support/features (RSS, etc.) | |
3236 | **/ | |
2f90b865 | 3237 | int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter) |
021230d4 AV |
3238 | { |
3239 | int err; | |
3240 | ||
3241 | /* Number of supported queues */ | |
3242 | ixgbe_set_num_queues(adapter); | |
3243 | ||
021230d4 AV |
3244 | err = ixgbe_set_interrupt_capability(adapter); |
3245 | if (err) { | |
3246 | DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n"); | |
3247 | goto err_set_interrupt; | |
9a799d71 AK |
3248 | } |
3249 | ||
7a921c93 AD |
3250 | err = ixgbe_alloc_q_vectors(adapter); |
3251 | if (err) { | |
3252 | DPRINTK(PROBE, ERR, "Unable to allocate memory for queue " | |
3253 | "vectors\n"); | |
3254 | goto err_alloc_q_vectors; | |
3255 | } | |
3256 | ||
3257 | err = ixgbe_alloc_queues(adapter); | |
3258 | if (err) { | |
3259 | DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n"); | |
3260 | goto err_alloc_queues; | |
3261 | } | |
3262 | ||
021230d4 | 3263 | DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, " |
b4617240 PW |
3264 | "Tx Queue count = %u\n", |
3265 | (adapter->num_rx_queues > 1) ? "Enabled" : | |
3266 | "Disabled", adapter->num_rx_queues, adapter->num_tx_queues); | |
021230d4 AV |
3267 | |
3268 | set_bit(__IXGBE_DOWN, &adapter->state); | |
3269 | ||
9a799d71 | 3270 | return 0; |
021230d4 | 3271 | |
7a921c93 AD |
3272 | err_alloc_queues: |
3273 | ixgbe_free_q_vectors(adapter); | |
3274 | err_alloc_q_vectors: | |
3275 | ixgbe_reset_interrupt_capability(adapter); | |
021230d4 | 3276 | err_set_interrupt: |
7a921c93 AD |
3277 | return err; |
3278 | } | |
3279 | ||
3280 | /** | |
3281 | * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings | |
3282 | * @adapter: board private structure to clear interrupt scheme on | |
3283 | * | |
3284 | * We go through and clear interrupt specific resources and reset the structure | |
3285 | * to pre-load conditions | |
3286 | **/ | |
3287 | void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter) | |
3288 | { | |
021230d4 AV |
3289 | kfree(adapter->tx_ring); |
3290 | kfree(adapter->rx_ring); | |
7a921c93 AD |
3291 | adapter->tx_ring = NULL; |
3292 | adapter->rx_ring = NULL; | |
3293 | ||
3294 | ixgbe_free_q_vectors(adapter); | |
3295 | ixgbe_reset_interrupt_capability(adapter); | |
9a799d71 AK |
3296 | } |
3297 | ||
c4900be0 DS |
3298 | /** |
3299 | * ixgbe_sfp_timer - worker thread to find a missing module | |
3300 | * @data: pointer to our adapter struct | |
3301 | **/ | |
3302 | static void ixgbe_sfp_timer(unsigned long data) | |
3303 | { | |
3304 | struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data; | |
3305 | ||
4df10466 JB |
3306 | /* |
3307 | * Do the sfp_timer outside of interrupt context due to the | |
c4900be0 DS |
3308 | * delays that sfp+ detection requires |
3309 | */ | |
3310 | schedule_work(&adapter->sfp_task); | |
3311 | } | |
3312 | ||
3313 | /** | |
3314 | * ixgbe_sfp_task - worker thread to find a missing module | |
3315 | * @work: pointer to work_struct containing our data | |
3316 | **/ | |
3317 | static void ixgbe_sfp_task(struct work_struct *work) | |
3318 | { | |
3319 | struct ixgbe_adapter *adapter = container_of(work, | |
3320 | struct ixgbe_adapter, | |
3321 | sfp_task); | |
3322 | struct ixgbe_hw *hw = &adapter->hw; | |
3323 | ||
3324 | if ((hw->phy.type == ixgbe_phy_nl) && | |
3325 | (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) { | |
3326 | s32 ret = hw->phy.ops.identify_sfp(hw); | |
3327 | if (ret) | |
3328 | goto reschedule; | |
3329 | ret = hw->phy.ops.reset(hw); | |
3330 | if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
3331 | DPRINTK(PROBE, ERR, "failed to initialize because an " | |
3332 | "unsupported SFP+ module type was detected.\n" | |
3333 | "Reload the driver after installing a " | |
3334 | "supported module.\n"); | |
3335 | unregister_netdev(adapter->netdev); | |
3336 | } else { | |
3337 | DPRINTK(PROBE, INFO, "detected SFP+: %d\n", | |
3338 | hw->phy.sfp_type); | |
3339 | } | |
3340 | /* don't need this routine any more */ | |
3341 | clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); | |
3342 | } | |
3343 | return; | |
3344 | reschedule: | |
3345 | if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state)) | |
3346 | mod_timer(&adapter->sfp_timer, | |
3347 | round_jiffies(jiffies + (2 * HZ))); | |
3348 | } | |
3349 | ||
9a799d71 AK |
3350 | /** |
3351 | * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter) | |
3352 | * @adapter: board private structure to initialize | |
3353 | * | |
3354 | * ixgbe_sw_init initializes the Adapter private data structure. | |
3355 | * Fields are initialized based on PCI device information and | |
3356 | * OS network device settings (MTU size). | |
3357 | **/ | |
3358 | static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter) | |
3359 | { | |
3360 | struct ixgbe_hw *hw = &adapter->hw; | |
3361 | struct pci_dev *pdev = adapter->pdev; | |
021230d4 | 3362 | unsigned int rss; |
7a6b6f51 | 3363 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
3364 | int j; |
3365 | struct tc_configuration *tc; | |
3366 | #endif | |
021230d4 | 3367 | |
c44ade9e JB |
3368 | /* PCI config space info */ |
3369 | ||
3370 | hw->vendor_id = pdev->vendor; | |
3371 | hw->device_id = pdev->device; | |
3372 | hw->revision_id = pdev->revision; | |
3373 | hw->subsystem_vendor_id = pdev->subsystem_vendor; | |
3374 | hw->subsystem_device_id = pdev->subsystem_device; | |
3375 | ||
021230d4 AV |
3376 | /* Set capability flags */ |
3377 | rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus()); | |
3378 | adapter->ring_feature[RING_F_RSS].indices = rss; | |
3379 | adapter->flags |= IXGBE_FLAG_RSS_ENABLED; | |
2f90b865 | 3380 | adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES; |
e8e26350 PW |
3381 | if (hw->mac.type == ixgbe_mac_82598EB) |
3382 | adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598; | |
f8212f97 | 3383 | else if (hw->mac.type == ixgbe_mac_82599EB) { |
e8e26350 | 3384 | adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599; |
f8212f97 AD |
3385 | adapter->flags |= IXGBE_FLAG_RSC_CAPABLE; |
3386 | adapter->flags |= IXGBE_FLAG_RSC_ENABLED; | |
3387 | } | |
2f90b865 | 3388 | |
7a6b6f51 | 3389 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
3390 | /* Configure DCB traffic classes */ |
3391 | for (j = 0; j < MAX_TRAFFIC_CLASS; j++) { | |
3392 | tc = &adapter->dcb_cfg.tc_config[j]; | |
3393 | tc->path[DCB_TX_CONFIG].bwg_id = 0; | |
3394 | tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1); | |
3395 | tc->path[DCB_RX_CONFIG].bwg_id = 0; | |
3396 | tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1); | |
3397 | tc->dcb_pfc = pfc_disabled; | |
3398 | } | |
3399 | adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100; | |
3400 | adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100; | |
3401 | adapter->dcb_cfg.rx_pba_cfg = pba_equal; | |
3402 | adapter->dcb_cfg.round_robin_enable = false; | |
3403 | adapter->dcb_set_bitmap = 0x00; | |
3404 | ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg, | |
3405 | adapter->ring_feature[RING_F_DCB].indices); | |
3406 | ||
3407 | #endif | |
9a799d71 AK |
3408 | |
3409 | /* default flow control settings */ | |
cd7664f6 | 3410 | hw->fc.requested_mode = ixgbe_fc_full; |
71fd570b | 3411 | hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */ |
2b9ade93 JB |
3412 | hw->fc.high_water = IXGBE_DEFAULT_FCRTH; |
3413 | hw->fc.low_water = IXGBE_DEFAULT_FCRTL; | |
3414 | hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE; | |
3415 | hw->fc.send_xon = true; | |
71fd570b | 3416 | hw->fc.disable_fc_autoneg = false; |
9a799d71 | 3417 | |
30efa5a3 JB |
3418 | /* enable itr by default in dynamic mode */ |
3419 | adapter->itr_setting = 1; | |
3420 | adapter->eitr_param = 20000; | |
3421 | ||
3422 | /* set defaults for eitr in MegaBytes */ | |
3423 | adapter->eitr_low = 10; | |
3424 | adapter->eitr_high = 20; | |
3425 | ||
3426 | /* set default ring sizes */ | |
3427 | adapter->tx_ring_count = IXGBE_DEFAULT_TXD; | |
3428 | adapter->rx_ring_count = IXGBE_DEFAULT_RXD; | |
3429 | ||
9a799d71 | 3430 | /* initialize eeprom parameters */ |
c44ade9e | 3431 | if (ixgbe_init_eeprom_params_generic(hw)) { |
9a799d71 AK |
3432 | dev_err(&pdev->dev, "EEPROM initialization failed\n"); |
3433 | return -EIO; | |
3434 | } | |
3435 | ||
021230d4 | 3436 | /* enable rx csum by default */ |
9a799d71 AK |
3437 | adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED; |
3438 | ||
9a799d71 AK |
3439 | set_bit(__IXGBE_DOWN, &adapter->state); |
3440 | ||
3441 | return 0; | |
3442 | } | |
3443 | ||
3444 | /** | |
3445 | * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors) | |
3446 | * @adapter: board private structure | |
3a581073 | 3447 | * @tx_ring: tx descriptor ring (for a specific queue) to setup |
9a799d71 AK |
3448 | * |
3449 | * Return 0 on success, negative on failure | |
3450 | **/ | |
3451 | int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter, | |
e01c31a5 | 3452 | struct ixgbe_ring *tx_ring) |
9a799d71 AK |
3453 | { |
3454 | struct pci_dev *pdev = adapter->pdev; | |
3455 | int size; | |
3456 | ||
3a581073 JB |
3457 | size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; |
3458 | tx_ring->tx_buffer_info = vmalloc(size); | |
e01c31a5 JB |
3459 | if (!tx_ring->tx_buffer_info) |
3460 | goto err; | |
3a581073 | 3461 | memset(tx_ring->tx_buffer_info, 0, size); |
9a799d71 AK |
3462 | |
3463 | /* round up to nearest 4K */ | |
12207e49 | 3464 | tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc); |
3a581073 | 3465 | tx_ring->size = ALIGN(tx_ring->size, 4096); |
9a799d71 | 3466 | |
3a581073 JB |
3467 | tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size, |
3468 | &tx_ring->dma); | |
e01c31a5 JB |
3469 | if (!tx_ring->desc) |
3470 | goto err; | |
9a799d71 | 3471 | |
3a581073 JB |
3472 | tx_ring->next_to_use = 0; |
3473 | tx_ring->next_to_clean = 0; | |
3474 | tx_ring->work_limit = tx_ring->count; | |
9a799d71 | 3475 | return 0; |
e01c31a5 JB |
3476 | |
3477 | err: | |
3478 | vfree(tx_ring->tx_buffer_info); | |
3479 | tx_ring->tx_buffer_info = NULL; | |
3480 | DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit " | |
3481 | "descriptor ring\n"); | |
3482 | return -ENOMEM; | |
9a799d71 AK |
3483 | } |
3484 | ||
69888674 AD |
3485 | /** |
3486 | * ixgbe_setup_all_tx_resources - allocate all queues Tx resources | |
3487 | * @adapter: board private structure | |
3488 | * | |
3489 | * If this function returns with an error, then it's possible one or | |
3490 | * more of the rings is populated (while the rest are not). It is the | |
3491 | * callers duty to clean those orphaned rings. | |
3492 | * | |
3493 | * Return 0 on success, negative on failure | |
3494 | **/ | |
3495 | static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter) | |
3496 | { | |
3497 | int i, err = 0; | |
3498 | ||
3499 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
3500 | err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]); | |
3501 | if (!err) | |
3502 | continue; | |
3503 | DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i); | |
3504 | break; | |
3505 | } | |
3506 | ||
3507 | return err; | |
3508 | } | |
3509 | ||
9a799d71 AK |
3510 | /** |
3511 | * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors) | |
3512 | * @adapter: board private structure | |
3a581073 | 3513 | * @rx_ring: rx descriptor ring (for a specific queue) to setup |
9a799d71 AK |
3514 | * |
3515 | * Returns 0 on success, negative on failure | |
3516 | **/ | |
3517 | int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter, | |
b4617240 | 3518 | struct ixgbe_ring *rx_ring) |
9a799d71 AK |
3519 | { |
3520 | struct pci_dev *pdev = adapter->pdev; | |
021230d4 | 3521 | int size; |
9a799d71 | 3522 | |
3a581073 JB |
3523 | size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; |
3524 | rx_ring->rx_buffer_info = vmalloc(size); | |
3525 | if (!rx_ring->rx_buffer_info) { | |
9a799d71 | 3526 | DPRINTK(PROBE, ERR, |
b4617240 | 3527 | "vmalloc allocation failed for the rx desc ring\n"); |
177db6ff | 3528 | goto alloc_failed; |
9a799d71 | 3529 | } |
3a581073 | 3530 | memset(rx_ring->rx_buffer_info, 0, size); |
9a799d71 | 3531 | |
9a799d71 | 3532 | /* Round up to nearest 4K */ |
3a581073 JB |
3533 | rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); |
3534 | rx_ring->size = ALIGN(rx_ring->size, 4096); | |
9a799d71 | 3535 | |
3a581073 | 3536 | rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma); |
9a799d71 | 3537 | |
3a581073 | 3538 | if (!rx_ring->desc) { |
9a799d71 | 3539 | DPRINTK(PROBE, ERR, |
b4617240 | 3540 | "Memory allocation failed for the rx desc ring\n"); |
3a581073 | 3541 | vfree(rx_ring->rx_buffer_info); |
177db6ff | 3542 | goto alloc_failed; |
9a799d71 AK |
3543 | } |
3544 | ||
3a581073 JB |
3545 | rx_ring->next_to_clean = 0; |
3546 | rx_ring->next_to_use = 0; | |
9a799d71 AK |
3547 | |
3548 | return 0; | |
177db6ff MC |
3549 | |
3550 | alloc_failed: | |
177db6ff | 3551 | return -ENOMEM; |
9a799d71 AK |
3552 | } |
3553 | ||
69888674 AD |
3554 | /** |
3555 | * ixgbe_setup_all_rx_resources - allocate all queues Rx resources | |
3556 | * @adapter: board private structure | |
3557 | * | |
3558 | * If this function returns with an error, then it's possible one or | |
3559 | * more of the rings is populated (while the rest are not). It is the | |
3560 | * callers duty to clean those orphaned rings. | |
3561 | * | |
3562 | * Return 0 on success, negative on failure | |
3563 | **/ | |
3564 | ||
3565 | static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter) | |
3566 | { | |
3567 | int i, err = 0; | |
3568 | ||
3569 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
3570 | err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]); | |
3571 | if (!err) | |
3572 | continue; | |
3573 | DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i); | |
3574 | break; | |
3575 | } | |
3576 | ||
3577 | return err; | |
3578 | } | |
3579 | ||
9a799d71 AK |
3580 | /** |
3581 | * ixgbe_free_tx_resources - Free Tx Resources per Queue | |
3582 | * @adapter: board private structure | |
3583 | * @tx_ring: Tx descriptor ring for a specific queue | |
3584 | * | |
3585 | * Free all transmit software resources | |
3586 | **/ | |
c431f97e JB |
3587 | void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter, |
3588 | struct ixgbe_ring *tx_ring) | |
9a799d71 AK |
3589 | { |
3590 | struct pci_dev *pdev = adapter->pdev; | |
3591 | ||
3592 | ixgbe_clean_tx_ring(adapter, tx_ring); | |
3593 | ||
3594 | vfree(tx_ring->tx_buffer_info); | |
3595 | tx_ring->tx_buffer_info = NULL; | |
3596 | ||
3597 | pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma); | |
3598 | ||
3599 | tx_ring->desc = NULL; | |
3600 | } | |
3601 | ||
3602 | /** | |
3603 | * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues | |
3604 | * @adapter: board private structure | |
3605 | * | |
3606 | * Free all transmit software resources | |
3607 | **/ | |
3608 | static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter) | |
3609 | { | |
3610 | int i; | |
3611 | ||
3612 | for (i = 0; i < adapter->num_tx_queues; i++) | |
9891ca7c JB |
3613 | if (adapter->tx_ring[i].desc) |
3614 | ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]); | |
9a799d71 AK |
3615 | } |
3616 | ||
3617 | /** | |
b4617240 | 3618 | * ixgbe_free_rx_resources - Free Rx Resources |
9a799d71 AK |
3619 | * @adapter: board private structure |
3620 | * @rx_ring: ring to clean the resources from | |
3621 | * | |
3622 | * Free all receive software resources | |
3623 | **/ | |
c431f97e JB |
3624 | void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter, |
3625 | struct ixgbe_ring *rx_ring) | |
9a799d71 AK |
3626 | { |
3627 | struct pci_dev *pdev = adapter->pdev; | |
3628 | ||
3629 | ixgbe_clean_rx_ring(adapter, rx_ring); | |
3630 | ||
3631 | vfree(rx_ring->rx_buffer_info); | |
3632 | rx_ring->rx_buffer_info = NULL; | |
3633 | ||
3634 | pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma); | |
3635 | ||
3636 | rx_ring->desc = NULL; | |
3637 | } | |
3638 | ||
3639 | /** | |
3640 | * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues | |
3641 | * @adapter: board private structure | |
3642 | * | |
3643 | * Free all receive software resources | |
3644 | **/ | |
3645 | static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter) | |
3646 | { | |
3647 | int i; | |
3648 | ||
3649 | for (i = 0; i < adapter->num_rx_queues; i++) | |
9891ca7c JB |
3650 | if (adapter->rx_ring[i].desc) |
3651 | ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]); | |
9a799d71 AK |
3652 | } |
3653 | ||
9a799d71 AK |
3654 | /** |
3655 | * ixgbe_change_mtu - Change the Maximum Transfer Unit | |
3656 | * @netdev: network interface device structure | |
3657 | * @new_mtu: new value for maximum frame size | |
3658 | * | |
3659 | * Returns 0 on success, negative on failure | |
3660 | **/ | |
3661 | static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu) | |
3662 | { | |
3663 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3664 | int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; | |
3665 | ||
42c783c5 JB |
3666 | /* MTU < 68 is an error and causes problems on some kernels */ |
3667 | if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE)) | |
9a799d71 AK |
3668 | return -EINVAL; |
3669 | ||
021230d4 | 3670 | DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n", |
b4617240 | 3671 | netdev->mtu, new_mtu); |
021230d4 | 3672 | /* must set new MTU before calling down or up */ |
9a799d71 AK |
3673 | netdev->mtu = new_mtu; |
3674 | ||
d4f80882 AV |
3675 | if (netif_running(netdev)) |
3676 | ixgbe_reinit_locked(adapter); | |
9a799d71 AK |
3677 | |
3678 | return 0; | |
3679 | } | |
3680 | ||
3681 | /** | |
3682 | * ixgbe_open - Called when a network interface is made active | |
3683 | * @netdev: network interface device structure | |
3684 | * | |
3685 | * Returns 0 on success, negative value on failure | |
3686 | * | |
3687 | * The open entry point is called when a network interface is made | |
3688 | * active by the system (IFF_UP). At this point all resources needed | |
3689 | * for transmit and receive operations are allocated, the interrupt | |
3690 | * handler is registered with the OS, the watchdog timer is started, | |
3691 | * and the stack is notified that the interface is ready. | |
3692 | **/ | |
3693 | static int ixgbe_open(struct net_device *netdev) | |
3694 | { | |
3695 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3696 | int err; | |
4bebfaa5 AK |
3697 | |
3698 | /* disallow open during test */ | |
3699 | if (test_bit(__IXGBE_TESTING, &adapter->state)) | |
3700 | return -EBUSY; | |
9a799d71 | 3701 | |
54386467 JB |
3702 | netif_carrier_off(netdev); |
3703 | ||
9a799d71 AK |
3704 | /* allocate transmit descriptors */ |
3705 | err = ixgbe_setup_all_tx_resources(adapter); | |
3706 | if (err) | |
3707 | goto err_setup_tx; | |
3708 | ||
9a799d71 AK |
3709 | /* allocate receive descriptors */ |
3710 | err = ixgbe_setup_all_rx_resources(adapter); | |
3711 | if (err) | |
3712 | goto err_setup_rx; | |
3713 | ||
3714 | ixgbe_configure(adapter); | |
3715 | ||
021230d4 | 3716 | err = ixgbe_request_irq(adapter); |
9a799d71 AK |
3717 | if (err) |
3718 | goto err_req_irq; | |
3719 | ||
9a799d71 AK |
3720 | err = ixgbe_up_complete(adapter); |
3721 | if (err) | |
3722 | goto err_up; | |
3723 | ||
d55b53ff JK |
3724 | netif_tx_start_all_queues(netdev); |
3725 | ||
9a799d71 AK |
3726 | return 0; |
3727 | ||
3728 | err_up: | |
5eba3699 | 3729 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
3730 | ixgbe_free_irq(adapter); |
3731 | err_req_irq: | |
9a799d71 | 3732 | err_setup_rx: |
a20a1199 | 3733 | ixgbe_free_all_rx_resources(adapter); |
9a799d71 | 3734 | err_setup_tx: |
a20a1199 | 3735 | ixgbe_free_all_tx_resources(adapter); |
9a799d71 AK |
3736 | ixgbe_reset(adapter); |
3737 | ||
3738 | return err; | |
3739 | } | |
3740 | ||
3741 | /** | |
3742 | * ixgbe_close - Disables a network interface | |
3743 | * @netdev: network interface device structure | |
3744 | * | |
3745 | * Returns 0, this is not allowed to fail | |
3746 | * | |
3747 | * The close entry point is called when an interface is de-activated | |
3748 | * by the OS. The hardware is still under the drivers control, but | |
3749 | * needs to be disabled. A global MAC reset is issued to stop the | |
3750 | * hardware, and all transmit and receive resources are freed. | |
3751 | **/ | |
3752 | static int ixgbe_close(struct net_device *netdev) | |
3753 | { | |
3754 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
9a799d71 AK |
3755 | |
3756 | ixgbe_down(adapter); | |
3757 | ixgbe_free_irq(adapter); | |
3758 | ||
3759 | ixgbe_free_all_tx_resources(adapter); | |
3760 | ixgbe_free_all_rx_resources(adapter); | |
3761 | ||
5eba3699 | 3762 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
3763 | |
3764 | return 0; | |
3765 | } | |
3766 | ||
b3c8b4ba AD |
3767 | #ifdef CONFIG_PM |
3768 | static int ixgbe_resume(struct pci_dev *pdev) | |
3769 | { | |
3770 | struct net_device *netdev = pci_get_drvdata(pdev); | |
3771 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3772 | u32 err; | |
3773 | ||
3774 | pci_set_power_state(pdev, PCI_D0); | |
3775 | pci_restore_state(pdev); | |
3776 | err = pci_enable_device(pdev); | |
3777 | if (err) { | |
69888674 | 3778 | printk(KERN_ERR "ixgbe: Cannot enable PCI device from " |
b3c8b4ba AD |
3779 | "suspend\n"); |
3780 | return err; | |
3781 | } | |
3782 | pci_set_master(pdev); | |
3783 | ||
dd4d8ca6 | 3784 | pci_wake_from_d3(pdev, false); |
b3c8b4ba AD |
3785 | |
3786 | err = ixgbe_init_interrupt_scheme(adapter); | |
3787 | if (err) { | |
3788 | printk(KERN_ERR "ixgbe: Cannot initialize interrupts for " | |
3789 | "device\n"); | |
3790 | return err; | |
3791 | } | |
3792 | ||
b3c8b4ba AD |
3793 | ixgbe_reset(adapter); |
3794 | ||
495dce12 WJP |
3795 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
3796 | ||
b3c8b4ba AD |
3797 | if (netif_running(netdev)) { |
3798 | err = ixgbe_open(adapter->netdev); | |
3799 | if (err) | |
3800 | return err; | |
3801 | } | |
3802 | ||
3803 | netif_device_attach(netdev); | |
3804 | ||
3805 | return 0; | |
3806 | } | |
b3c8b4ba | 3807 | #endif /* CONFIG_PM */ |
9d8d05ae RW |
3808 | |
3809 | static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake) | |
b3c8b4ba AD |
3810 | { |
3811 | struct net_device *netdev = pci_get_drvdata(pdev); | |
3812 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
e8e26350 PW |
3813 | struct ixgbe_hw *hw = &adapter->hw; |
3814 | u32 ctrl, fctrl; | |
3815 | u32 wufc = adapter->wol; | |
b3c8b4ba AD |
3816 | #ifdef CONFIG_PM |
3817 | int retval = 0; | |
3818 | #endif | |
3819 | ||
3820 | netif_device_detach(netdev); | |
3821 | ||
3822 | if (netif_running(netdev)) { | |
3823 | ixgbe_down(adapter); | |
3824 | ixgbe_free_irq(adapter); | |
3825 | ixgbe_free_all_tx_resources(adapter); | |
3826 | ixgbe_free_all_rx_resources(adapter); | |
3827 | } | |
7a921c93 | 3828 | ixgbe_clear_interrupt_scheme(adapter); |
b3c8b4ba AD |
3829 | |
3830 | #ifdef CONFIG_PM | |
3831 | retval = pci_save_state(pdev); | |
3832 | if (retval) | |
3833 | return retval; | |
4df10466 | 3834 | |
b3c8b4ba | 3835 | #endif |
e8e26350 PW |
3836 | if (wufc) { |
3837 | ixgbe_set_rx_mode(netdev); | |
b3c8b4ba | 3838 | |
e8e26350 PW |
3839 | /* turn on all-multi mode if wake on multicast is enabled */ |
3840 | if (wufc & IXGBE_WUFC_MC) { | |
3841 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
3842 | fctrl |= IXGBE_FCTRL_MPE; | |
3843 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); | |
3844 | } | |
3845 | ||
3846 | ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); | |
3847 | ctrl |= IXGBE_CTRL_GIO_DIS; | |
3848 | IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); | |
3849 | ||
3850 | IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc); | |
3851 | } else { | |
3852 | IXGBE_WRITE_REG(hw, IXGBE_WUC, 0); | |
3853 | IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); | |
3854 | } | |
3855 | ||
dd4d8ca6 DS |
3856 | if (wufc && hw->mac.type == ixgbe_mac_82599EB) |
3857 | pci_wake_from_d3(pdev, true); | |
3858 | else | |
3859 | pci_wake_from_d3(pdev, false); | |
b3c8b4ba | 3860 | |
9d8d05ae RW |
3861 | *enable_wake = !!wufc; |
3862 | ||
b3c8b4ba AD |
3863 | ixgbe_release_hw_control(adapter); |
3864 | ||
3865 | pci_disable_device(pdev); | |
3866 | ||
9d8d05ae RW |
3867 | return 0; |
3868 | } | |
3869 | ||
3870 | #ifdef CONFIG_PM | |
3871 | static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state) | |
3872 | { | |
3873 | int retval; | |
3874 | bool wake; | |
3875 | ||
3876 | retval = __ixgbe_shutdown(pdev, &wake); | |
3877 | if (retval) | |
3878 | return retval; | |
3879 | ||
3880 | if (wake) { | |
3881 | pci_prepare_to_sleep(pdev); | |
3882 | } else { | |
3883 | pci_wake_from_d3(pdev, false); | |
3884 | pci_set_power_state(pdev, PCI_D3hot); | |
3885 | } | |
b3c8b4ba AD |
3886 | |
3887 | return 0; | |
3888 | } | |
9d8d05ae | 3889 | #endif /* CONFIG_PM */ |
b3c8b4ba AD |
3890 | |
3891 | static void ixgbe_shutdown(struct pci_dev *pdev) | |
3892 | { | |
9d8d05ae RW |
3893 | bool wake; |
3894 | ||
3895 | __ixgbe_shutdown(pdev, &wake); | |
3896 | ||
3897 | if (system_state == SYSTEM_POWER_OFF) { | |
3898 | pci_wake_from_d3(pdev, wake); | |
3899 | pci_set_power_state(pdev, PCI_D3hot); | |
3900 | } | |
b3c8b4ba AD |
3901 | } |
3902 | ||
9a799d71 AK |
3903 | /** |
3904 | * ixgbe_update_stats - Update the board statistics counters. | |
3905 | * @adapter: board private structure | |
3906 | **/ | |
3907 | void ixgbe_update_stats(struct ixgbe_adapter *adapter) | |
3908 | { | |
3909 | struct ixgbe_hw *hw = &adapter->hw; | |
6f11eef7 AV |
3910 | u64 total_mpc = 0; |
3911 | u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot; | |
9a799d71 | 3912 | |
d51019a4 | 3913 | if (hw->mac.type == ixgbe_mac_82599EB) { |
f8212f97 | 3914 | u64 rsc_count = 0; |
d51019a4 PW |
3915 | for (i = 0; i < 16; i++) |
3916 | adapter->hw_rx_no_dma_resources += | |
3917 | IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); | |
f8212f97 AD |
3918 | for (i = 0; i < adapter->num_rx_queues; i++) |
3919 | rsc_count += adapter->rx_ring[i].rsc_count; | |
3920 | adapter->rsc_count = rsc_count; | |
d51019a4 PW |
3921 | } |
3922 | ||
9a799d71 | 3923 | adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); |
6f11eef7 AV |
3924 | for (i = 0; i < 8; i++) { |
3925 | /* for packet buffers not used, the register should read 0 */ | |
3926 | mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i)); | |
3927 | missed_rx += mpc; | |
3928 | adapter->stats.mpc[i] += mpc; | |
3929 | total_mpc += adapter->stats.mpc[i]; | |
e8e26350 PW |
3930 | if (hw->mac.type == ixgbe_mac_82598EB) |
3931 | adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); | |
2f90b865 AD |
3932 | adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); |
3933 | adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i)); | |
3934 | adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); | |
3935 | adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i)); | |
e8e26350 PW |
3936 | if (hw->mac.type == ixgbe_mac_82599EB) { |
3937 | adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw, | |
3938 | IXGBE_PXONRXCNT(i)); | |
3939 | adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw, | |
3940 | IXGBE_PXOFFRXCNT(i)); | |
3941 | adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); | |
e8e26350 PW |
3942 | } else { |
3943 | adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw, | |
3944 | IXGBE_PXONRXC(i)); | |
3945 | adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw, | |
3946 | IXGBE_PXOFFRXC(i)); | |
3947 | } | |
2f90b865 AD |
3948 | adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw, |
3949 | IXGBE_PXONTXC(i)); | |
2f90b865 | 3950 | adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw, |
e8e26350 | 3951 | IXGBE_PXOFFTXC(i)); |
6f11eef7 AV |
3952 | } |
3953 | adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); | |
3954 | /* work around hardware counting issue */ | |
3955 | adapter->stats.gprc -= missed_rx; | |
3956 | ||
3957 | /* 82598 hardware only has a 32 bit counter in the high register */ | |
e8e26350 PW |
3958 | if (hw->mac.type == ixgbe_mac_82599EB) { |
3959 | adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); | |
3960 | IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */ | |
3961 | adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); | |
3962 | IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */ | |
3963 | adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL); | |
3964 | IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */ | |
3965 | adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); | |
3966 | adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); | |
3967 | } else { | |
3968 | adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); | |
3969 | adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); | |
3970 | adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); | |
3971 | adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); | |
3972 | adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH); | |
3973 | } | |
9a799d71 AK |
3974 | bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); |
3975 | adapter->stats.bprc += bprc; | |
3976 | adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); | |
e8e26350 PW |
3977 | if (hw->mac.type == ixgbe_mac_82598EB) |
3978 | adapter->stats.mprc -= bprc; | |
9a799d71 AK |
3979 | adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC); |
3980 | adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); | |
3981 | adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); | |
3982 | adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); | |
3983 | adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); | |
3984 | adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); | |
3985 | adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); | |
9a799d71 | 3986 | adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); |
6f11eef7 AV |
3987 | lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); |
3988 | adapter->stats.lxontxc += lxon; | |
3989 | lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); | |
3990 | adapter->stats.lxofftxc += lxoff; | |
9a799d71 AK |
3991 | adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC); |
3992 | adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); | |
6f11eef7 AV |
3993 | adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); |
3994 | /* | |
3995 | * 82598 errata - tx of flow control packets is included in tx counters | |
3996 | */ | |
3997 | xon_off_tot = lxon + lxoff; | |
3998 | adapter->stats.gptc -= xon_off_tot; | |
3999 | adapter->stats.mptc -= xon_off_tot; | |
4000 | adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN)); | |
9a799d71 AK |
4001 | adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC); |
4002 | adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC); | |
4003 | adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC); | |
9a799d71 AK |
4004 | adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR); |
4005 | adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); | |
6f11eef7 | 4006 | adapter->stats.ptc64 -= xon_off_tot; |
9a799d71 AK |
4007 | adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); |
4008 | adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); | |
4009 | adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); | |
4010 | adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); | |
4011 | adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); | |
9a799d71 AK |
4012 | adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); |
4013 | ||
4014 | /* Fill out the OS statistics structure */ | |
9a799d71 AK |
4015 | adapter->net_stats.multicast = adapter->stats.mprc; |
4016 | ||
4017 | /* Rx Errors */ | |
4018 | adapter->net_stats.rx_errors = adapter->stats.crcerrs + | |
b4617240 | 4019 | adapter->stats.rlec; |
9a799d71 AK |
4020 | adapter->net_stats.rx_dropped = 0; |
4021 | adapter->net_stats.rx_length_errors = adapter->stats.rlec; | |
4022 | adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs; | |
6f11eef7 | 4023 | adapter->net_stats.rx_missed_errors = total_mpc; |
9a799d71 AK |
4024 | } |
4025 | ||
4026 | /** | |
4027 | * ixgbe_watchdog - Timer Call-back | |
4028 | * @data: pointer to adapter cast into an unsigned long | |
4029 | **/ | |
4030 | static void ixgbe_watchdog(unsigned long data) | |
4031 | { | |
4032 | struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data; | |
cf8280ee JB |
4033 | struct ixgbe_hw *hw = &adapter->hw; |
4034 | ||
4035 | /* Do the watchdog outside of interrupt context due to the lovely | |
4036 | * delays that some of the newer hardware requires */ | |
4037 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { | |
22d5a71b JB |
4038 | u64 eics = 0; |
4039 | int i; | |
4040 | ||
4041 | for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) | |
4042 | eics |= (1 << i); | |
4043 | ||
cf8280ee | 4044 | /* Cause software interrupt to ensure rx rings are cleaned */ |
22d5a71b JB |
4045 | switch (hw->mac.type) { |
4046 | case ixgbe_mac_82598EB: | |
4047 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
4048 | IXGBE_WRITE_REG(hw, IXGBE_EICS, (u32)eics); | |
4049 | } else { | |
4050 | /* | |
4051 | * for legacy and MSI interrupts don't set any | |
4052 | * bits that are enabled for EIAM, because this | |
4053 | * operation would set *both* EIMS and EICS for | |
4054 | * any bit in EIAM | |
4055 | */ | |
4056 | IXGBE_WRITE_REG(hw, IXGBE_EICS, | |
4057 | (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); | |
4058 | } | |
4059 | break; | |
4060 | case ixgbe_mac_82599EB: | |
4061 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
835462fc NS |
4062 | IXGBE_WRITE_REG(hw, IXGBE_EICS_EX(0), |
4063 | (u32)(eics & 0xFFFFFFFF)); | |
22d5a71b | 4064 | IXGBE_WRITE_REG(hw, IXGBE_EICS_EX(1), |
22d5a71b JB |
4065 | (u32)(eics >> 32)); |
4066 | } else { | |
4067 | /* | |
4068 | * for legacy and MSI interrupts don't set any | |
4069 | * bits that are enabled for EIAM, because this | |
4070 | * operation would set *both* EIMS and EICS for | |
4071 | * any bit in EIAM | |
4072 | */ | |
4073 | IXGBE_WRITE_REG(hw, IXGBE_EICS, | |
4074 | (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); | |
4075 | } | |
4076 | break; | |
4077 | default: | |
4078 | break; | |
cf8280ee JB |
4079 | } |
4080 | /* Reset the timer */ | |
4081 | mod_timer(&adapter->watchdog_timer, | |
4082 | round_jiffies(jiffies + 2 * HZ)); | |
4083 | } | |
9a799d71 | 4084 | |
cf8280ee JB |
4085 | schedule_work(&adapter->watchdog_task); |
4086 | } | |
4087 | ||
e8e26350 PW |
4088 | /** |
4089 | * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber | |
4090 | * @work: pointer to work_struct containing our data | |
4091 | **/ | |
4092 | static void ixgbe_multispeed_fiber_task(struct work_struct *work) | |
4093 | { | |
4094 | struct ixgbe_adapter *adapter = container_of(work, | |
4095 | struct ixgbe_adapter, | |
4096 | multispeed_fiber_task); | |
4097 | struct ixgbe_hw *hw = &adapter->hw; | |
4098 | u32 autoneg; | |
4099 | ||
4100 | adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK; | |
4101 | if (hw->mac.ops.get_link_capabilities) | |
4102 | hw->mac.ops.get_link_capabilities(hw, &autoneg, | |
4103 | &hw->mac.autoneg); | |
4104 | if (hw->mac.ops.setup_link_speed) | |
4105 | hw->mac.ops.setup_link_speed(hw, autoneg, true, true); | |
4106 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; | |
4107 | adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK; | |
4108 | } | |
4109 | ||
4110 | /** | |
4111 | * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module | |
4112 | * @work: pointer to work_struct containing our data | |
4113 | **/ | |
4114 | static void ixgbe_sfp_config_module_task(struct work_struct *work) | |
4115 | { | |
4116 | struct ixgbe_adapter *adapter = container_of(work, | |
4117 | struct ixgbe_adapter, | |
4118 | sfp_config_module_task); | |
4119 | struct ixgbe_hw *hw = &adapter->hw; | |
4120 | u32 err; | |
4121 | ||
4122 | adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK; | |
4123 | err = hw->phy.ops.identify_sfp(hw); | |
4124 | if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
4125 | DPRINTK(PROBE, ERR, "PHY not supported on this NIC %d\n", err); | |
4126 | ixgbe_down(adapter); | |
4127 | return; | |
4128 | } | |
4129 | hw->mac.ops.setup_sfp(hw); | |
4130 | ||
8d1c3c07 | 4131 | if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK)) |
e8e26350 PW |
4132 | /* This will also work for DA Twinax connections */ |
4133 | schedule_work(&adapter->multispeed_fiber_task); | |
4134 | adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK; | |
4135 | } | |
4136 | ||
cf8280ee | 4137 | /** |
69888674 AD |
4138 | * ixgbe_watchdog_task - worker thread to bring link up |
4139 | * @work: pointer to work_struct containing our data | |
cf8280ee JB |
4140 | **/ |
4141 | static void ixgbe_watchdog_task(struct work_struct *work) | |
4142 | { | |
4143 | struct ixgbe_adapter *adapter = container_of(work, | |
4144 | struct ixgbe_adapter, | |
4145 | watchdog_task); | |
4146 | struct net_device *netdev = adapter->netdev; | |
4147 | struct ixgbe_hw *hw = &adapter->hw; | |
4148 | u32 link_speed = adapter->link_speed; | |
4149 | bool link_up = adapter->link_up; | |
bc59fcda NS |
4150 | int i; |
4151 | struct ixgbe_ring *tx_ring; | |
4152 | int some_tx_pending = 0; | |
cf8280ee JB |
4153 | |
4154 | adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK; | |
4155 | ||
4156 | if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) { | |
4157 | hw->mac.ops.check_link(hw, &link_speed, &link_up, false); | |
4158 | if (link_up || | |
4159 | time_after(jiffies, (adapter->link_check_timeout + | |
4160 | IXGBE_TRY_LINK_TIMEOUT))) { | |
4161 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC); | |
4162 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; | |
4163 | } | |
4164 | adapter->link_up = link_up; | |
4165 | adapter->link_speed = link_speed; | |
4166 | } | |
9a799d71 AK |
4167 | |
4168 | if (link_up) { | |
4169 | if (!netif_carrier_ok(netdev)) { | |
e8e26350 PW |
4170 | bool flow_rx, flow_tx; |
4171 | ||
4172 | if (hw->mac.type == ixgbe_mac_82599EB) { | |
4173 | u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); | |
4174 | u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG); | |
4175 | flow_rx = (mflcn & IXGBE_MFLCN_RFCE); | |
4176 | flow_tx = (fccfg & IXGBE_FCCFG_TFCE_802_3X); | |
4177 | } else { | |
4178 | u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
4179 | u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS); | |
4180 | flow_rx = (frctl & IXGBE_FCTRL_RFCE); | |
4181 | flow_tx = (rmcs & IXGBE_RMCS_TFCE_802_3X); | |
4182 | } | |
4183 | ||
a46e534b JK |
4184 | printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, " |
4185 | "Flow Control: %s\n", | |
4186 | netdev->name, | |
4187 | (link_speed == IXGBE_LINK_SPEED_10GB_FULL ? | |
4188 | "10 Gbps" : | |
4189 | (link_speed == IXGBE_LINK_SPEED_1GB_FULL ? | |
4190 | "1 Gbps" : "unknown speed")), | |
e8e26350 PW |
4191 | ((flow_rx && flow_tx) ? "RX/TX" : |
4192 | (flow_rx ? "RX" : | |
4193 | (flow_tx ? "TX" : "None")))); | |
9a799d71 AK |
4194 | |
4195 | netif_carrier_on(netdev); | |
9a799d71 AK |
4196 | } else { |
4197 | /* Force detection of hung controller */ | |
4198 | adapter->detect_tx_hung = true; | |
4199 | } | |
4200 | } else { | |
cf8280ee JB |
4201 | adapter->link_up = false; |
4202 | adapter->link_speed = 0; | |
9a799d71 | 4203 | if (netif_carrier_ok(netdev)) { |
a46e534b JK |
4204 | printk(KERN_INFO "ixgbe: %s NIC Link is Down\n", |
4205 | netdev->name); | |
9a799d71 | 4206 | netif_carrier_off(netdev); |
9a799d71 AK |
4207 | } |
4208 | } | |
4209 | ||
bc59fcda NS |
4210 | if (!netif_carrier_ok(netdev)) { |
4211 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
4212 | tx_ring = &adapter->tx_ring[i]; | |
4213 | if (tx_ring->next_to_use != tx_ring->next_to_clean) { | |
4214 | some_tx_pending = 1; | |
4215 | break; | |
4216 | } | |
4217 | } | |
4218 | ||
4219 | if (some_tx_pending) { | |
4220 | /* We've lost link, so the controller stops DMA, | |
4221 | * but we've got queued Tx work that's never going | |
4222 | * to get done, so reset controller to flush Tx. | |
4223 | * (Do the reset outside of interrupt context). | |
4224 | */ | |
4225 | schedule_work(&adapter->reset_task); | |
4226 | } | |
4227 | } | |
4228 | ||
9a799d71 | 4229 | ixgbe_update_stats(adapter); |
cf8280ee | 4230 | adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK; |
9a799d71 AK |
4231 | } |
4232 | ||
9a799d71 | 4233 | static int ixgbe_tso(struct ixgbe_adapter *adapter, |
b4617240 PW |
4234 | struct ixgbe_ring *tx_ring, struct sk_buff *skb, |
4235 | u32 tx_flags, u8 *hdr_len) | |
9a799d71 AK |
4236 | { |
4237 | struct ixgbe_adv_tx_context_desc *context_desc; | |
4238 | unsigned int i; | |
4239 | int err; | |
4240 | struct ixgbe_tx_buffer *tx_buffer_info; | |
9f8cdf4f JB |
4241 | u32 vlan_macip_lens = 0, type_tucmd_mlhl; |
4242 | u32 mss_l4len_idx, l4len; | |
9a799d71 AK |
4243 | |
4244 | if (skb_is_gso(skb)) { | |
4245 | if (skb_header_cloned(skb)) { | |
4246 | err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); | |
4247 | if (err) | |
4248 | return err; | |
4249 | } | |
4250 | l4len = tcp_hdrlen(skb); | |
4251 | *hdr_len += l4len; | |
4252 | ||
8327d000 | 4253 | if (skb->protocol == htons(ETH_P_IP)) { |
9a799d71 AK |
4254 | struct iphdr *iph = ip_hdr(skb); |
4255 | iph->tot_len = 0; | |
4256 | iph->check = 0; | |
4257 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, | |
b4617240 PW |
4258 | iph->daddr, 0, |
4259 | IPPROTO_TCP, | |
4260 | 0); | |
9a799d71 AK |
4261 | adapter->hw_tso_ctxt++; |
4262 | } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) { | |
4263 | ipv6_hdr(skb)->payload_len = 0; | |
4264 | tcp_hdr(skb)->check = | |
4265 | ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, | |
b4617240 PW |
4266 | &ipv6_hdr(skb)->daddr, |
4267 | 0, IPPROTO_TCP, 0); | |
9a799d71 AK |
4268 | adapter->hw_tso6_ctxt++; |
4269 | } | |
4270 | ||
4271 | i = tx_ring->next_to_use; | |
4272 | ||
4273 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
4274 | context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i); | |
4275 | ||
4276 | /* VLAN MACLEN IPLEN */ | |
4277 | if (tx_flags & IXGBE_TX_FLAGS_VLAN) | |
4278 | vlan_macip_lens |= | |
4279 | (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK); | |
4280 | vlan_macip_lens |= ((skb_network_offset(skb)) << | |
b4617240 | 4281 | IXGBE_ADVTXD_MACLEN_SHIFT); |
9a799d71 AK |
4282 | *hdr_len += skb_network_offset(skb); |
4283 | vlan_macip_lens |= | |
4284 | (skb_transport_header(skb) - skb_network_header(skb)); | |
4285 | *hdr_len += | |
4286 | (skb_transport_header(skb) - skb_network_header(skb)); | |
4287 | context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); | |
4288 | context_desc->seqnum_seed = 0; | |
4289 | ||
4290 | /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ | |
9f8cdf4f | 4291 | type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT | |
b4617240 | 4292 | IXGBE_ADVTXD_DTYP_CTXT); |
9a799d71 | 4293 | |
8327d000 | 4294 | if (skb->protocol == htons(ETH_P_IP)) |
9a799d71 AK |
4295 | type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4; |
4296 | type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP; | |
4297 | context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl); | |
4298 | ||
4299 | /* MSS L4LEN IDX */ | |
9f8cdf4f | 4300 | mss_l4len_idx = |
9a799d71 AK |
4301 | (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT); |
4302 | mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT); | |
4eeae6fd PW |
4303 | /* use index 1 for TSO */ |
4304 | mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT); | |
9a799d71 AK |
4305 | context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); |
4306 | ||
4307 | tx_buffer_info->time_stamp = jiffies; | |
4308 | tx_buffer_info->next_to_watch = i; | |
4309 | ||
4310 | i++; | |
4311 | if (i == tx_ring->count) | |
4312 | i = 0; | |
4313 | tx_ring->next_to_use = i; | |
4314 | ||
4315 | return true; | |
4316 | } | |
4317 | return false; | |
4318 | } | |
4319 | ||
4320 | static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter, | |
b4617240 PW |
4321 | struct ixgbe_ring *tx_ring, |
4322 | struct sk_buff *skb, u32 tx_flags) | |
9a799d71 AK |
4323 | { |
4324 | struct ixgbe_adv_tx_context_desc *context_desc; | |
4325 | unsigned int i; | |
4326 | struct ixgbe_tx_buffer *tx_buffer_info; | |
4327 | u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0; | |
4328 | ||
4329 | if (skb->ip_summed == CHECKSUM_PARTIAL || | |
4330 | (tx_flags & IXGBE_TX_FLAGS_VLAN)) { | |
4331 | i = tx_ring->next_to_use; | |
4332 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
4333 | context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i); | |
4334 | ||
4335 | if (tx_flags & IXGBE_TX_FLAGS_VLAN) | |
4336 | vlan_macip_lens |= | |
4337 | (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK); | |
4338 | vlan_macip_lens |= (skb_network_offset(skb) << | |
b4617240 | 4339 | IXGBE_ADVTXD_MACLEN_SHIFT); |
9a799d71 AK |
4340 | if (skb->ip_summed == CHECKSUM_PARTIAL) |
4341 | vlan_macip_lens |= (skb_transport_header(skb) - | |
b4617240 | 4342 | skb_network_header(skb)); |
9a799d71 AK |
4343 | |
4344 | context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); | |
4345 | context_desc->seqnum_seed = 0; | |
4346 | ||
4347 | type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT | | |
b4617240 | 4348 | IXGBE_ADVTXD_DTYP_CTXT); |
9a799d71 AK |
4349 | |
4350 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
41825d71 | 4351 | switch (skb->protocol) { |
09640e63 | 4352 | case cpu_to_be16(ETH_P_IP): |
9a799d71 | 4353 | type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4; |
41825d71 AK |
4354 | if (ip_hdr(skb)->protocol == IPPROTO_TCP) |
4355 | type_tucmd_mlhl |= | |
b4617240 | 4356 | IXGBE_ADVTXD_TUCMD_L4T_TCP; |
45a5ead0 JB |
4357 | else if (ip_hdr(skb)->protocol == IPPROTO_SCTP) |
4358 | type_tucmd_mlhl |= | |
4359 | IXGBE_ADVTXD_TUCMD_L4T_SCTP; | |
41825d71 | 4360 | break; |
09640e63 | 4361 | case cpu_to_be16(ETH_P_IPV6): |
41825d71 AK |
4362 | /* XXX what about other V6 headers?? */ |
4363 | if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP) | |
4364 | type_tucmd_mlhl |= | |
b4617240 | 4365 | IXGBE_ADVTXD_TUCMD_L4T_TCP; |
45a5ead0 JB |
4366 | else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP) |
4367 | type_tucmd_mlhl |= | |
4368 | IXGBE_ADVTXD_TUCMD_L4T_SCTP; | |
41825d71 | 4369 | break; |
41825d71 AK |
4370 | default: |
4371 | if (unlikely(net_ratelimit())) { | |
4372 | DPRINTK(PROBE, WARNING, | |
4373 | "partial checksum but proto=%x!\n", | |
4374 | skb->protocol); | |
4375 | } | |
4376 | break; | |
4377 | } | |
9a799d71 AK |
4378 | } |
4379 | ||
4380 | context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl); | |
4eeae6fd | 4381 | /* use index zero for tx checksum offload */ |
9a799d71 AK |
4382 | context_desc->mss_l4len_idx = 0; |
4383 | ||
4384 | tx_buffer_info->time_stamp = jiffies; | |
4385 | tx_buffer_info->next_to_watch = i; | |
9f8cdf4f | 4386 | |
9a799d71 AK |
4387 | adapter->hw_csum_tx_good++; |
4388 | i++; | |
4389 | if (i == tx_ring->count) | |
4390 | i = 0; | |
4391 | tx_ring->next_to_use = i; | |
4392 | ||
4393 | return true; | |
4394 | } | |
9f8cdf4f | 4395 | |
9a799d71 AK |
4396 | return false; |
4397 | } | |
4398 | ||
4399 | static int ixgbe_tx_map(struct ixgbe_adapter *adapter, | |
b4617240 PW |
4400 | struct ixgbe_ring *tx_ring, |
4401 | struct sk_buff *skb, unsigned int first) | |
9a799d71 AK |
4402 | { |
4403 | struct ixgbe_tx_buffer *tx_buffer_info; | |
44df32c5 | 4404 | unsigned int len = skb_headlen(skb); |
9a799d71 AK |
4405 | unsigned int offset = 0, size, count = 0, i; |
4406 | unsigned int nr_frags = skb_shinfo(skb)->nr_frags; | |
4407 | unsigned int f; | |
44df32c5 | 4408 | dma_addr_t *map; |
9a799d71 AK |
4409 | |
4410 | i = tx_ring->next_to_use; | |
4411 | ||
44df32c5 AD |
4412 | if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) { |
4413 | dev_err(&adapter->pdev->dev, "TX DMA map failed\n"); | |
4414 | return 0; | |
4415 | } | |
4416 | ||
4417 | map = skb_shinfo(skb)->dma_maps; | |
4418 | ||
9a799d71 AK |
4419 | while (len) { |
4420 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
4421 | size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD); | |
4422 | ||
4423 | tx_buffer_info->length = size; | |
44df32c5 | 4424 | tx_buffer_info->dma = map[0] + offset; |
9a799d71 AK |
4425 | tx_buffer_info->time_stamp = jiffies; |
4426 | tx_buffer_info->next_to_watch = i; | |
4427 | ||
4428 | len -= size; | |
4429 | offset += size; | |
4430 | count++; | |
44df32c5 AD |
4431 | |
4432 | if (len) { | |
4433 | i++; | |
4434 | if (i == tx_ring->count) | |
4435 | i = 0; | |
4436 | } | |
9a799d71 AK |
4437 | } |
4438 | ||
4439 | for (f = 0; f < nr_frags; f++) { | |
4440 | struct skb_frag_struct *frag; | |
4441 | ||
4442 | frag = &skb_shinfo(skb)->frags[f]; | |
4443 | len = frag->size; | |
44df32c5 | 4444 | offset = 0; |
9a799d71 AK |
4445 | |
4446 | while (len) { | |
44df32c5 AD |
4447 | i++; |
4448 | if (i == tx_ring->count) | |
4449 | i = 0; | |
4450 | ||
9a799d71 AK |
4451 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; |
4452 | size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD); | |
4453 | ||
4454 | tx_buffer_info->length = size; | |
44df32c5 | 4455 | tx_buffer_info->dma = map[f + 1] + offset; |
9a799d71 AK |
4456 | tx_buffer_info->time_stamp = jiffies; |
4457 | tx_buffer_info->next_to_watch = i; | |
4458 | ||
4459 | len -= size; | |
4460 | offset += size; | |
4461 | count++; | |
9a799d71 AK |
4462 | } |
4463 | } | |
44df32c5 | 4464 | |
9a799d71 AK |
4465 | tx_ring->tx_buffer_info[i].skb = skb; |
4466 | tx_ring->tx_buffer_info[first].next_to_watch = i; | |
4467 | ||
4468 | return count; | |
4469 | } | |
4470 | ||
4471 | static void ixgbe_tx_queue(struct ixgbe_adapter *adapter, | |
b4617240 PW |
4472 | struct ixgbe_ring *tx_ring, |
4473 | int tx_flags, int count, u32 paylen, u8 hdr_len) | |
9a799d71 AK |
4474 | { |
4475 | union ixgbe_adv_tx_desc *tx_desc = NULL; | |
4476 | struct ixgbe_tx_buffer *tx_buffer_info; | |
4477 | u32 olinfo_status = 0, cmd_type_len = 0; | |
4478 | unsigned int i; | |
4479 | u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS; | |
4480 | ||
4481 | cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA; | |
4482 | ||
4483 | cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT; | |
4484 | ||
4485 | if (tx_flags & IXGBE_TX_FLAGS_VLAN) | |
4486 | cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE; | |
4487 | ||
4488 | if (tx_flags & IXGBE_TX_FLAGS_TSO) { | |
4489 | cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE; | |
4490 | ||
4491 | olinfo_status |= IXGBE_TXD_POPTS_TXSM << | |
b4617240 | 4492 | IXGBE_ADVTXD_POPTS_SHIFT; |
9a799d71 | 4493 | |
4eeae6fd PW |
4494 | /* use index 1 context for tso */ |
4495 | olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT); | |
9a799d71 AK |
4496 | if (tx_flags & IXGBE_TX_FLAGS_IPV4) |
4497 | olinfo_status |= IXGBE_TXD_POPTS_IXSM << | |
b4617240 | 4498 | IXGBE_ADVTXD_POPTS_SHIFT; |
9a799d71 AK |
4499 | |
4500 | } else if (tx_flags & IXGBE_TX_FLAGS_CSUM) | |
4501 | olinfo_status |= IXGBE_TXD_POPTS_TXSM << | |
b4617240 | 4502 | IXGBE_ADVTXD_POPTS_SHIFT; |
9a799d71 AK |
4503 | |
4504 | olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT); | |
4505 | ||
4506 | i = tx_ring->next_to_use; | |
4507 | while (count--) { | |
4508 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
4509 | tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i); | |
4510 | tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma); | |
4511 | tx_desc->read.cmd_type_len = | |
b4617240 | 4512 | cpu_to_le32(cmd_type_len | tx_buffer_info->length); |
9a799d71 | 4513 | tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); |
9a799d71 AK |
4514 | i++; |
4515 | if (i == tx_ring->count) | |
4516 | i = 0; | |
4517 | } | |
4518 | ||
4519 | tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd); | |
4520 | ||
4521 | /* | |
4522 | * Force memory writes to complete before letting h/w | |
4523 | * know there are new descriptors to fetch. (Only | |
4524 | * applicable for weak-ordered memory model archs, | |
4525 | * such as IA-64). | |
4526 | */ | |
4527 | wmb(); | |
4528 | ||
4529 | tx_ring->next_to_use = i; | |
4530 | writel(i, adapter->hw.hw_addr + tx_ring->tail); | |
4531 | } | |
4532 | ||
e092be60 | 4533 | static int __ixgbe_maybe_stop_tx(struct net_device *netdev, |
b4617240 | 4534 | struct ixgbe_ring *tx_ring, int size) |
e092be60 AV |
4535 | { |
4536 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4537 | ||
30eba97a | 4538 | netif_stop_subqueue(netdev, tx_ring->queue_index); |
e092be60 AV |
4539 | /* Herbert's original patch had: |
4540 | * smp_mb__after_netif_stop_queue(); | |
4541 | * but since that doesn't exist yet, just open code it. */ | |
4542 | smp_mb(); | |
4543 | ||
4544 | /* We need to check again in a case another CPU has just | |
4545 | * made room available. */ | |
4546 | if (likely(IXGBE_DESC_UNUSED(tx_ring) < size)) | |
4547 | return -EBUSY; | |
4548 | ||
4549 | /* A reprieve! - use start_queue because it doesn't call schedule */ | |
af72166f | 4550 | netif_start_subqueue(netdev, tx_ring->queue_index); |
e092be60 AV |
4551 | ++adapter->restart_queue; |
4552 | return 0; | |
4553 | } | |
4554 | ||
4555 | static int ixgbe_maybe_stop_tx(struct net_device *netdev, | |
b4617240 | 4556 | struct ixgbe_ring *tx_ring, int size) |
e092be60 AV |
4557 | { |
4558 | if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size)) | |
4559 | return 0; | |
4560 | return __ixgbe_maybe_stop_tx(netdev, tx_ring, size); | |
4561 | } | |
4562 | ||
09a3b1f8 SH |
4563 | static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb) |
4564 | { | |
4565 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
4566 | ||
4567 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) | |
4568 | return 0; /* All traffic should default to class 0 */ | |
4569 | ||
4570 | return skb_tx_hash(dev, skb); | |
4571 | } | |
4572 | ||
9a799d71 AK |
4573 | static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev) |
4574 | { | |
4575 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4576 | struct ixgbe_ring *tx_ring; | |
9a799d71 AK |
4577 | unsigned int first; |
4578 | unsigned int tx_flags = 0; | |
30eba97a AV |
4579 | u8 hdr_len = 0; |
4580 | int r_idx = 0, tso; | |
9a799d71 AK |
4581 | int count = 0; |
4582 | unsigned int f; | |
9f8cdf4f | 4583 | |
95615d90 | 4584 | r_idx = skb->queue_mapping; |
30eba97a | 4585 | tx_ring = &adapter->tx_ring[r_idx]; |
9a799d71 | 4586 | |
9f8cdf4f JB |
4587 | if (adapter->vlgrp && vlan_tx_tag_present(skb)) { |
4588 | tx_flags |= vlan_tx_tag_get(skb); | |
2f90b865 AD |
4589 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { |
4590 | tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK; | |
4591 | tx_flags |= (skb->queue_mapping << 13); | |
4592 | } | |
4593 | tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT; | |
4594 | tx_flags |= IXGBE_TX_FLAGS_VLAN; | |
4595 | } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
4596 | tx_flags |= (skb->queue_mapping << 13); | |
9f8cdf4f JB |
4597 | tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT; |
4598 | tx_flags |= IXGBE_TX_FLAGS_VLAN; | |
9a799d71 | 4599 | } |
9f8cdf4f JB |
4600 | /* three things can cause us to need a context descriptor */ |
4601 | if (skb_is_gso(skb) || | |
4602 | (skb->ip_summed == CHECKSUM_PARTIAL) || | |
4603 | (tx_flags & IXGBE_TX_FLAGS_VLAN)) | |
9a799d71 AK |
4604 | count++; |
4605 | ||
9f8cdf4f JB |
4606 | count += TXD_USE_COUNT(skb_headlen(skb)); |
4607 | for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) | |
9a799d71 AK |
4608 | count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); |
4609 | ||
e092be60 | 4610 | if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) { |
9a799d71 | 4611 | adapter->tx_busy++; |
9a799d71 AK |
4612 | return NETDEV_TX_BUSY; |
4613 | } | |
9a799d71 | 4614 | |
8327d000 | 4615 | if (skb->protocol == htons(ETH_P_IP)) |
9a799d71 AK |
4616 | tx_flags |= IXGBE_TX_FLAGS_IPV4; |
4617 | first = tx_ring->next_to_use; | |
4618 | tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len); | |
4619 | if (tso < 0) { | |
4620 | dev_kfree_skb_any(skb); | |
4621 | return NETDEV_TX_OK; | |
4622 | } | |
4623 | ||
4624 | if (tso) | |
4625 | tx_flags |= IXGBE_TX_FLAGS_TSO; | |
4626 | else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) && | |
b4617240 | 4627 | (skb->ip_summed == CHECKSUM_PARTIAL)) |
9a799d71 AK |
4628 | tx_flags |= IXGBE_TX_FLAGS_CSUM; |
4629 | ||
44df32c5 | 4630 | count = ixgbe_tx_map(adapter, tx_ring, skb, first); |
9a799d71 | 4631 | |
44df32c5 AD |
4632 | if (count) { |
4633 | ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len, | |
4634 | hdr_len); | |
4635 | netdev->trans_start = jiffies; | |
4636 | ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED); | |
9a799d71 | 4637 | |
44df32c5 AD |
4638 | } else { |
4639 | dev_kfree_skb_any(skb); | |
4640 | tx_ring->tx_buffer_info[first].time_stamp = 0; | |
4641 | tx_ring->next_to_use = first; | |
4642 | } | |
9a799d71 AK |
4643 | |
4644 | return NETDEV_TX_OK; | |
4645 | } | |
4646 | ||
4647 | /** | |
4648 | * ixgbe_get_stats - Get System Network Statistics | |
4649 | * @netdev: network interface device structure | |
4650 | * | |
4651 | * Returns the address of the device statistics structure. | |
4652 | * The statistics are actually updated from the timer callback. | |
4653 | **/ | |
4654 | static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev) | |
4655 | { | |
4656 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4657 | ||
4658 | /* only return the current stats */ | |
4659 | return &adapter->net_stats; | |
4660 | } | |
4661 | ||
4662 | /** | |
4663 | * ixgbe_set_mac - Change the Ethernet Address of the NIC | |
4664 | * @netdev: network interface device structure | |
4665 | * @p: pointer to an address structure | |
4666 | * | |
4667 | * Returns 0 on success, negative on failure | |
4668 | **/ | |
4669 | static int ixgbe_set_mac(struct net_device *netdev, void *p) | |
4670 | { | |
4671 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
b4617240 | 4672 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 AK |
4673 | struct sockaddr *addr = p; |
4674 | ||
4675 | if (!is_valid_ether_addr(addr->sa_data)) | |
4676 | return -EADDRNOTAVAIL; | |
4677 | ||
4678 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | |
b4617240 | 4679 | memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); |
9a799d71 | 4680 | |
b4617240 | 4681 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); |
9a799d71 AK |
4682 | |
4683 | return 0; | |
4684 | } | |
4685 | ||
6b73e10d BH |
4686 | static int |
4687 | ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr) | |
4688 | { | |
4689 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4690 | struct ixgbe_hw *hw = &adapter->hw; | |
4691 | u16 value; | |
4692 | int rc; | |
4693 | ||
4694 | if (prtad != hw->phy.mdio.prtad) | |
4695 | return -EINVAL; | |
4696 | rc = hw->phy.ops.read_reg(hw, addr, devad, &value); | |
4697 | if (!rc) | |
4698 | rc = value; | |
4699 | return rc; | |
4700 | } | |
4701 | ||
4702 | static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad, | |
4703 | u16 addr, u16 value) | |
4704 | { | |
4705 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4706 | struct ixgbe_hw *hw = &adapter->hw; | |
4707 | ||
4708 | if (prtad != hw->phy.mdio.prtad) | |
4709 | return -EINVAL; | |
4710 | return hw->phy.ops.write_reg(hw, addr, devad, value); | |
4711 | } | |
4712 | ||
4713 | static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) | |
4714 | { | |
4715 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4716 | ||
4717 | return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd); | |
4718 | } | |
4719 | ||
9a799d71 AK |
4720 | #ifdef CONFIG_NET_POLL_CONTROLLER |
4721 | /* | |
4722 | * Polling 'interrupt' - used by things like netconsole to send skbs | |
4723 | * without having to re-enable interrupts. It's not called while | |
4724 | * the interrupt routine is executing. | |
4725 | */ | |
4726 | static void ixgbe_netpoll(struct net_device *netdev) | |
4727 | { | |
4728 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4729 | ||
4730 | disable_irq(adapter->pdev->irq); | |
4731 | adapter->flags |= IXGBE_FLAG_IN_NETPOLL; | |
4732 | ixgbe_intr(adapter->pdev->irq, netdev); | |
4733 | adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL; | |
4734 | enable_irq(adapter->pdev->irq); | |
4735 | } | |
4736 | #endif | |
4737 | ||
0edc3527 SH |
4738 | static const struct net_device_ops ixgbe_netdev_ops = { |
4739 | .ndo_open = ixgbe_open, | |
4740 | .ndo_stop = ixgbe_close, | |
00829823 | 4741 | .ndo_start_xmit = ixgbe_xmit_frame, |
09a3b1f8 | 4742 | .ndo_select_queue = ixgbe_select_queue, |
0edc3527 | 4743 | .ndo_get_stats = ixgbe_get_stats, |
e90d400c | 4744 | .ndo_set_rx_mode = ixgbe_set_rx_mode, |
0edc3527 SH |
4745 | .ndo_set_multicast_list = ixgbe_set_rx_mode, |
4746 | .ndo_validate_addr = eth_validate_addr, | |
4747 | .ndo_set_mac_address = ixgbe_set_mac, | |
4748 | .ndo_change_mtu = ixgbe_change_mtu, | |
4749 | .ndo_tx_timeout = ixgbe_tx_timeout, | |
4750 | .ndo_vlan_rx_register = ixgbe_vlan_rx_register, | |
4751 | .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid, | |
4752 | .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid, | |
6b73e10d | 4753 | .ndo_do_ioctl = ixgbe_ioctl, |
0edc3527 SH |
4754 | #ifdef CONFIG_NET_POLL_CONTROLLER |
4755 | .ndo_poll_controller = ixgbe_netpoll, | |
4756 | #endif | |
4757 | }; | |
4758 | ||
9a799d71 AK |
4759 | /** |
4760 | * ixgbe_probe - Device Initialization Routine | |
4761 | * @pdev: PCI device information struct | |
4762 | * @ent: entry in ixgbe_pci_tbl | |
4763 | * | |
4764 | * Returns 0 on success, negative on failure | |
4765 | * | |
4766 | * ixgbe_probe initializes an adapter identified by a pci_dev structure. | |
4767 | * The OS initialization, configuring of the adapter private structure, | |
4768 | * and a hardware reset occur. | |
4769 | **/ | |
4770 | static int __devinit ixgbe_probe(struct pci_dev *pdev, | |
b4617240 | 4771 | const struct pci_device_id *ent) |
9a799d71 AK |
4772 | { |
4773 | struct net_device *netdev; | |
4774 | struct ixgbe_adapter *adapter = NULL; | |
4775 | struct ixgbe_hw *hw; | |
4776 | const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data]; | |
9a799d71 AK |
4777 | static int cards_found; |
4778 | int i, err, pci_using_dac; | |
c44ade9e | 4779 | u32 part_num, eec; |
9a799d71 AK |
4780 | |
4781 | err = pci_enable_device(pdev); | |
4782 | if (err) | |
4783 | return err; | |
4784 | ||
6a35528a YH |
4785 | if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && |
4786 | !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) { | |
9a799d71 AK |
4787 | pci_using_dac = 1; |
4788 | } else { | |
284901a9 | 4789 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
9a799d71 | 4790 | if (err) { |
284901a9 | 4791 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
9a799d71 | 4792 | if (err) { |
b4617240 PW |
4793 | dev_err(&pdev->dev, "No usable DMA " |
4794 | "configuration, aborting\n"); | |
9a799d71 AK |
4795 | goto err_dma; |
4796 | } | |
4797 | } | |
4798 | pci_using_dac = 0; | |
4799 | } | |
4800 | ||
4801 | err = pci_request_regions(pdev, ixgbe_driver_name); | |
4802 | if (err) { | |
4803 | dev_err(&pdev->dev, "pci_request_regions failed 0x%x\n", err); | |
4804 | goto err_pci_reg; | |
4805 | } | |
4806 | ||
6fabd715 PWJ |
4807 | err = pci_enable_pcie_error_reporting(pdev); |
4808 | if (err) { | |
4809 | dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed " | |
4810 | "0x%x\n", err); | |
4811 | /* non-fatal, continue */ | |
4812 | } | |
4813 | ||
9a799d71 | 4814 | pci_set_master(pdev); |
fb3b27bc | 4815 | pci_save_state(pdev); |
9a799d71 | 4816 | |
30eba97a | 4817 | netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES); |
9a799d71 AK |
4818 | if (!netdev) { |
4819 | err = -ENOMEM; | |
4820 | goto err_alloc_etherdev; | |
4821 | } | |
4822 | ||
9a799d71 AK |
4823 | SET_NETDEV_DEV(netdev, &pdev->dev); |
4824 | ||
4825 | pci_set_drvdata(pdev, netdev); | |
4826 | adapter = netdev_priv(netdev); | |
4827 | ||
4828 | adapter->netdev = netdev; | |
4829 | adapter->pdev = pdev; | |
4830 | hw = &adapter->hw; | |
4831 | hw->back = adapter; | |
4832 | adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1; | |
4833 | ||
05857980 JK |
4834 | hw->hw_addr = ioremap(pci_resource_start(pdev, 0), |
4835 | pci_resource_len(pdev, 0)); | |
9a799d71 AK |
4836 | if (!hw->hw_addr) { |
4837 | err = -EIO; | |
4838 | goto err_ioremap; | |
4839 | } | |
4840 | ||
4841 | for (i = 1; i <= 5; i++) { | |
4842 | if (pci_resource_len(pdev, i) == 0) | |
4843 | continue; | |
4844 | } | |
4845 | ||
0edc3527 | 4846 | netdev->netdev_ops = &ixgbe_netdev_ops; |
9a799d71 | 4847 | ixgbe_set_ethtool_ops(netdev); |
9a799d71 | 4848 | netdev->watchdog_timeo = 5 * HZ; |
9a799d71 AK |
4849 | strcpy(netdev->name, pci_name(pdev)); |
4850 | ||
9a799d71 AK |
4851 | adapter->bd_number = cards_found; |
4852 | ||
9a799d71 AK |
4853 | /* Setup hw api */ |
4854 | memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops)); | |
021230d4 | 4855 | hw->mac.type = ii->mac; |
9a799d71 | 4856 | |
c44ade9e JB |
4857 | /* EEPROM */ |
4858 | memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops)); | |
4859 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); | |
4860 | /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */ | |
4861 | if (!(eec & (1 << 8))) | |
4862 | hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic; | |
4863 | ||
4864 | /* PHY */ | |
4865 | memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops)); | |
c4900be0 | 4866 | hw->phy.sfp_type = ixgbe_sfp_type_unknown; |
6b73e10d BH |
4867 | /* ixgbe_identify_phy_generic will set prtad and mmds properly */ |
4868 | hw->phy.mdio.prtad = MDIO_PRTAD_NONE; | |
4869 | hw->phy.mdio.mmds = 0; | |
4870 | hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; | |
4871 | hw->phy.mdio.dev = netdev; | |
4872 | hw->phy.mdio.mdio_read = ixgbe_mdio_read; | |
4873 | hw->phy.mdio.mdio_write = ixgbe_mdio_write; | |
c4900be0 DS |
4874 | |
4875 | /* set up this timer and work struct before calling get_invariants | |
4876 | * which might start the timer | |
4877 | */ | |
4878 | init_timer(&adapter->sfp_timer); | |
4879 | adapter->sfp_timer.function = &ixgbe_sfp_timer; | |
4880 | adapter->sfp_timer.data = (unsigned long) adapter; | |
4881 | ||
4882 | INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task); | |
c44ade9e | 4883 | |
e8e26350 PW |
4884 | /* multispeed fiber has its own tasklet, called from GPI SDP1 context */ |
4885 | INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task); | |
4886 | ||
4887 | /* a new SFP+ module arrival, called from GPI SDP2 context */ | |
4888 | INIT_WORK(&adapter->sfp_config_module_task, | |
4889 | ixgbe_sfp_config_module_task); | |
4890 | ||
9a799d71 | 4891 | err = ii->get_invariants(hw); |
c4900be0 DS |
4892 | if (err == IXGBE_ERR_SFP_NOT_PRESENT) { |
4893 | /* start a kernel thread to watch for a module to arrive */ | |
4894 | set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); | |
4895 | mod_timer(&adapter->sfp_timer, | |
4896 | round_jiffies(jiffies + (2 * HZ))); | |
4897 | err = 0; | |
4898 | } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
4899 | DPRINTK(PROBE, ERR, "failed to load because an " | |
4900 | "unsupported SFP+ module type was detected.\n"); | |
9a799d71 | 4901 | goto err_hw_init; |
c4900be0 DS |
4902 | } else if (err) { |
4903 | goto err_hw_init; | |
4904 | } | |
9a799d71 AK |
4905 | |
4906 | /* setup the private structure */ | |
4907 | err = ixgbe_sw_init(adapter); | |
4908 | if (err) | |
4909 | goto err_sw_init; | |
4910 | ||
c44ade9e JB |
4911 | /* reset_hw fills in the perm_addr as well */ |
4912 | err = hw->mac.ops.reset_hw(hw); | |
04f165ef PW |
4913 | if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { |
4914 | dev_err(&adapter->pdev->dev, "failed to load because an " | |
4915 | "unsupported SFP+ module type was detected.\n"); | |
4916 | goto err_sw_init; | |
4917 | } else if (err) { | |
c44ade9e JB |
4918 | dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err); |
4919 | goto err_sw_init; | |
4920 | } | |
4921 | ||
9a799d71 | 4922 | netdev->features = NETIF_F_SG | |
b4617240 PW |
4923 | NETIF_F_IP_CSUM | |
4924 | NETIF_F_HW_VLAN_TX | | |
4925 | NETIF_F_HW_VLAN_RX | | |
4926 | NETIF_F_HW_VLAN_FILTER; | |
9a799d71 | 4927 | |
e9990a9c | 4928 | netdev->features |= NETIF_F_IPV6_CSUM; |
9a799d71 | 4929 | netdev->features |= NETIF_F_TSO; |
9a799d71 | 4930 | netdev->features |= NETIF_F_TSO6; |
78b6f4ce | 4931 | netdev->features |= NETIF_F_GRO; |
ad31c402 | 4932 | |
45a5ead0 JB |
4933 | if (adapter->hw.mac.type == ixgbe_mac_82599EB) |
4934 | netdev->features |= NETIF_F_SCTP_CSUM; | |
4935 | ||
ad31c402 JK |
4936 | netdev->vlan_features |= NETIF_F_TSO; |
4937 | netdev->vlan_features |= NETIF_F_TSO6; | |
22f32b7a | 4938 | netdev->vlan_features |= NETIF_F_IP_CSUM; |
ad31c402 JK |
4939 | netdev->vlan_features |= NETIF_F_SG; |
4940 | ||
2f90b865 AD |
4941 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) |
4942 | adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED; | |
4943 | ||
7a6b6f51 | 4944 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
4945 | netdev->dcbnl_ops = &dcbnl_ops; |
4946 | #endif | |
4947 | ||
9a799d71 AK |
4948 | if (pci_using_dac) |
4949 | netdev->features |= NETIF_F_HIGHDMA; | |
4950 | ||
f8212f97 AD |
4951 | if (adapter->flags & IXGBE_FLAG_RSC_ENABLED) |
4952 | netdev->features |= NETIF_F_LRO; | |
4953 | ||
9a799d71 | 4954 | /* make sure the EEPROM is good */ |
c44ade9e | 4955 | if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) { |
9a799d71 AK |
4956 | dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n"); |
4957 | err = -EIO; | |
4958 | goto err_eeprom; | |
4959 | } | |
4960 | ||
4961 | memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len); | |
4962 | memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len); | |
4963 | ||
c44ade9e JB |
4964 | if (ixgbe_validate_mac_addr(netdev->perm_addr)) { |
4965 | dev_err(&pdev->dev, "invalid MAC address\n"); | |
9a799d71 AK |
4966 | err = -EIO; |
4967 | goto err_eeprom; | |
4968 | } | |
4969 | ||
4970 | init_timer(&adapter->watchdog_timer); | |
4971 | adapter->watchdog_timer.function = &ixgbe_watchdog; | |
4972 | adapter->watchdog_timer.data = (unsigned long)adapter; | |
4973 | ||
4974 | INIT_WORK(&adapter->reset_task, ixgbe_reset_task); | |
cf8280ee | 4975 | INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task); |
9a799d71 | 4976 | |
021230d4 AV |
4977 | err = ixgbe_init_interrupt_scheme(adapter); |
4978 | if (err) | |
4979 | goto err_sw_init; | |
9a799d71 | 4980 | |
e8e26350 PW |
4981 | switch (pdev->device) { |
4982 | case IXGBE_DEV_ID_82599_KX4: | |
495dce12 WJP |
4983 | adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX | |
4984 | IXGBE_WUFC_MC | IXGBE_WUFC_BC); | |
e8e26350 PW |
4985 | break; |
4986 | default: | |
4987 | adapter->wol = 0; | |
4988 | break; | |
4989 | } | |
4990 | device_init_wakeup(&adapter->pdev->dev, true); | |
4991 | device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); | |
4992 | ||
04f165ef PW |
4993 | /* pick up the PCI bus settings for reporting later */ |
4994 | hw->mac.ops.get_bus_info(hw); | |
4995 | ||
9a799d71 | 4996 | /* print bus type/speed/width info */ |
7c510e4b | 4997 | dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n", |
e8e26350 PW |
4998 | ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s": |
4999 | (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"), | |
5000 | ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" : | |
5001 | (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" : | |
5002 | (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" : | |
b4617240 | 5003 | "Unknown"), |
7c510e4b | 5004 | netdev->dev_addr); |
c44ade9e | 5005 | ixgbe_read_pba_num_generic(hw, &part_num); |
e8e26350 PW |
5006 | if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) |
5007 | dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n", | |
5008 | hw->mac.type, hw->phy.type, hw->phy.sfp_type, | |
5009 | (part_num >> 8), (part_num & 0xff)); | |
5010 | else | |
5011 | dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n", | |
5012 | hw->mac.type, hw->phy.type, | |
5013 | (part_num >> 8), (part_num & 0xff)); | |
9a799d71 | 5014 | |
e8e26350 | 5015 | if (hw->bus.width <= ixgbe_bus_width_pcie_x4) { |
0c254d86 | 5016 | dev_warn(&pdev->dev, "PCI-Express bandwidth available for " |
b4617240 PW |
5017 | "this card is not sufficient for optimal " |
5018 | "performance.\n"); | |
0c254d86 | 5019 | dev_warn(&pdev->dev, "For optimal performance a x8 " |
b4617240 | 5020 | "PCI-Express slot is required.\n"); |
0c254d86 AK |
5021 | } |
5022 | ||
34b0368c PWJ |
5023 | /* save off EEPROM version number */ |
5024 | hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version); | |
5025 | ||
9a799d71 | 5026 | /* reset the hardware with the new settings */ |
c44ade9e JB |
5027 | hw->mac.ops.start_hw(hw); |
5028 | ||
9a799d71 AK |
5029 | strcpy(netdev->name, "eth%d"); |
5030 | err = register_netdev(netdev); | |
5031 | if (err) | |
5032 | goto err_register; | |
5033 | ||
54386467 JB |
5034 | /* carrier off reporting is important to ethtool even BEFORE open */ |
5035 | netif_carrier_off(netdev); | |
5036 | ||
5dd2d332 | 5037 | #ifdef CONFIG_IXGBE_DCA |
652f093f | 5038 | if (dca_add_requester(&pdev->dev) == 0) { |
bd0362dd JC |
5039 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; |
5040 | /* always use CB2 mode, difference is masked | |
5041 | * in the CB driver */ | |
5042 | IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2); | |
5043 | ixgbe_setup_dca(adapter); | |
5044 | } | |
5045 | #endif | |
9a799d71 AK |
5046 | |
5047 | dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n"); | |
5048 | cards_found++; | |
5049 | return 0; | |
5050 | ||
5051 | err_register: | |
5eba3699 | 5052 | ixgbe_release_hw_control(adapter); |
9a799d71 | 5053 | err_hw_init: |
7a921c93 | 5054 | ixgbe_clear_interrupt_scheme(adapter); |
9a799d71 AK |
5055 | err_sw_init: |
5056 | err_eeprom: | |
c4900be0 DS |
5057 | clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); |
5058 | del_timer_sync(&adapter->sfp_timer); | |
5059 | cancel_work_sync(&adapter->sfp_task); | |
e8e26350 PW |
5060 | cancel_work_sync(&adapter->multispeed_fiber_task); |
5061 | cancel_work_sync(&adapter->sfp_config_module_task); | |
9a799d71 AK |
5062 | iounmap(hw->hw_addr); |
5063 | err_ioremap: | |
5064 | free_netdev(netdev); | |
5065 | err_alloc_etherdev: | |
5066 | pci_release_regions(pdev); | |
5067 | err_pci_reg: | |
5068 | err_dma: | |
5069 | pci_disable_device(pdev); | |
5070 | return err; | |
5071 | } | |
5072 | ||
5073 | /** | |
5074 | * ixgbe_remove - Device Removal Routine | |
5075 | * @pdev: PCI device information struct | |
5076 | * | |
5077 | * ixgbe_remove is called by the PCI subsystem to alert the driver | |
5078 | * that it should release a PCI device. The could be caused by a | |
5079 | * Hot-Plug event, or because the driver is going to be removed from | |
5080 | * memory. | |
5081 | **/ | |
5082 | static void __devexit ixgbe_remove(struct pci_dev *pdev) | |
5083 | { | |
5084 | struct net_device *netdev = pci_get_drvdata(pdev); | |
5085 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6fabd715 | 5086 | int err; |
9a799d71 AK |
5087 | |
5088 | set_bit(__IXGBE_DOWN, &adapter->state); | |
c4900be0 DS |
5089 | /* clear the module not found bit to make sure the worker won't |
5090 | * reschedule | |
5091 | */ | |
5092 | clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); | |
9a799d71 AK |
5093 | del_timer_sync(&adapter->watchdog_timer); |
5094 | ||
c4900be0 DS |
5095 | del_timer_sync(&adapter->sfp_timer); |
5096 | cancel_work_sync(&adapter->watchdog_task); | |
5097 | cancel_work_sync(&adapter->sfp_task); | |
e8e26350 PW |
5098 | cancel_work_sync(&adapter->multispeed_fiber_task); |
5099 | cancel_work_sync(&adapter->sfp_config_module_task); | |
9a799d71 AK |
5100 | flush_scheduled_work(); |
5101 | ||
5dd2d332 | 5102 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
5103 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { |
5104 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
5105 | dca_remove_requester(&pdev->dev); | |
5106 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); | |
5107 | } | |
5108 | ||
5109 | #endif | |
c4900be0 DS |
5110 | if (netdev->reg_state == NETREG_REGISTERED) |
5111 | unregister_netdev(netdev); | |
9a799d71 | 5112 | |
7a921c93 | 5113 | ixgbe_clear_interrupt_scheme(adapter); |
5eba3699 | 5114 | |
021230d4 | 5115 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
5116 | |
5117 | iounmap(adapter->hw.hw_addr); | |
5118 | pci_release_regions(pdev); | |
5119 | ||
021230d4 | 5120 | DPRINTK(PROBE, INFO, "complete\n"); |
021230d4 | 5121 | |
9a799d71 AK |
5122 | free_netdev(netdev); |
5123 | ||
6fabd715 PWJ |
5124 | err = pci_disable_pcie_error_reporting(pdev); |
5125 | if (err) | |
5126 | dev_err(&pdev->dev, | |
5127 | "pci_disable_pcie_error_reporting failed 0x%x\n", err); | |
5128 | ||
9a799d71 AK |
5129 | pci_disable_device(pdev); |
5130 | } | |
5131 | ||
5132 | /** | |
5133 | * ixgbe_io_error_detected - called when PCI error is detected | |
5134 | * @pdev: Pointer to PCI device | |
5135 | * @state: The current pci connection state | |
5136 | * | |
5137 | * This function is called after a PCI bus error affecting | |
5138 | * this device has been detected. | |
5139 | */ | |
5140 | static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev, | |
b4617240 | 5141 | pci_channel_state_t state) |
9a799d71 AK |
5142 | { |
5143 | struct net_device *netdev = pci_get_drvdata(pdev); | |
454d7c9b | 5144 | struct ixgbe_adapter *adapter = netdev_priv(netdev); |
9a799d71 AK |
5145 | |
5146 | netif_device_detach(netdev); | |
5147 | ||
5148 | if (netif_running(netdev)) | |
5149 | ixgbe_down(adapter); | |
5150 | pci_disable_device(pdev); | |
5151 | ||
b4617240 | 5152 | /* Request a slot reset. */ |
9a799d71 AK |
5153 | return PCI_ERS_RESULT_NEED_RESET; |
5154 | } | |
5155 | ||
5156 | /** | |
5157 | * ixgbe_io_slot_reset - called after the pci bus has been reset. | |
5158 | * @pdev: Pointer to PCI device | |
5159 | * | |
5160 | * Restart the card from scratch, as if from a cold-boot. | |
5161 | */ | |
5162 | static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev) | |
5163 | { | |
5164 | struct net_device *netdev = pci_get_drvdata(pdev); | |
454d7c9b | 5165 | struct ixgbe_adapter *adapter = netdev_priv(netdev); |
6fabd715 PWJ |
5166 | pci_ers_result_t result; |
5167 | int err; | |
9a799d71 AK |
5168 | |
5169 | if (pci_enable_device(pdev)) { | |
5170 | DPRINTK(PROBE, ERR, | |
b4617240 | 5171 | "Cannot re-enable PCI device after reset.\n"); |
6fabd715 PWJ |
5172 | result = PCI_ERS_RESULT_DISCONNECT; |
5173 | } else { | |
5174 | pci_set_master(pdev); | |
5175 | pci_restore_state(pdev); | |
9a799d71 | 5176 | |
dd4d8ca6 | 5177 | pci_wake_from_d3(pdev, false); |
9a799d71 | 5178 | |
6fabd715 | 5179 | ixgbe_reset(adapter); |
88512539 | 5180 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
6fabd715 PWJ |
5181 | result = PCI_ERS_RESULT_RECOVERED; |
5182 | } | |
5183 | ||
5184 | err = pci_cleanup_aer_uncorrect_error_status(pdev); | |
5185 | if (err) { | |
5186 | dev_err(&pdev->dev, | |
5187 | "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err); | |
5188 | /* non-fatal, continue */ | |
5189 | } | |
9a799d71 | 5190 | |
6fabd715 | 5191 | return result; |
9a799d71 AK |
5192 | } |
5193 | ||
5194 | /** | |
5195 | * ixgbe_io_resume - called when traffic can start flowing again. | |
5196 | * @pdev: Pointer to PCI device | |
5197 | * | |
5198 | * This callback is called when the error recovery driver tells us that | |
5199 | * its OK to resume normal operation. | |
5200 | */ | |
5201 | static void ixgbe_io_resume(struct pci_dev *pdev) | |
5202 | { | |
5203 | struct net_device *netdev = pci_get_drvdata(pdev); | |
454d7c9b | 5204 | struct ixgbe_adapter *adapter = netdev_priv(netdev); |
9a799d71 AK |
5205 | |
5206 | if (netif_running(netdev)) { | |
5207 | if (ixgbe_up(adapter)) { | |
5208 | DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n"); | |
5209 | return; | |
5210 | } | |
5211 | } | |
5212 | ||
5213 | netif_device_attach(netdev); | |
9a799d71 AK |
5214 | } |
5215 | ||
5216 | static struct pci_error_handlers ixgbe_err_handler = { | |
5217 | .error_detected = ixgbe_io_error_detected, | |
5218 | .slot_reset = ixgbe_io_slot_reset, | |
5219 | .resume = ixgbe_io_resume, | |
5220 | }; | |
5221 | ||
5222 | static struct pci_driver ixgbe_driver = { | |
5223 | .name = ixgbe_driver_name, | |
5224 | .id_table = ixgbe_pci_tbl, | |
5225 | .probe = ixgbe_probe, | |
5226 | .remove = __devexit_p(ixgbe_remove), | |
5227 | #ifdef CONFIG_PM | |
5228 | .suspend = ixgbe_suspend, | |
5229 | .resume = ixgbe_resume, | |
5230 | #endif | |
5231 | .shutdown = ixgbe_shutdown, | |
5232 | .err_handler = &ixgbe_err_handler | |
5233 | }; | |
5234 | ||
5235 | /** | |
5236 | * ixgbe_init_module - Driver Registration Routine | |
5237 | * | |
5238 | * ixgbe_init_module is the first routine called when the driver is | |
5239 | * loaded. All it does is register with the PCI subsystem. | |
5240 | **/ | |
5241 | static int __init ixgbe_init_module(void) | |
5242 | { | |
5243 | int ret; | |
5244 | printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name, | |
5245 | ixgbe_driver_string, ixgbe_driver_version); | |
5246 | ||
5247 | printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright); | |
5248 | ||
5dd2d332 | 5249 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 5250 | dca_register_notify(&dca_notifier); |
bd0362dd | 5251 | #endif |
5dd2d332 | 5252 | |
9a799d71 AK |
5253 | ret = pci_register_driver(&ixgbe_driver); |
5254 | return ret; | |
5255 | } | |
b4617240 | 5256 | |
9a799d71 AK |
5257 | module_init(ixgbe_init_module); |
5258 | ||
5259 | /** | |
5260 | * ixgbe_exit_module - Driver Exit Cleanup Routine | |
5261 | * | |
5262 | * ixgbe_exit_module is called just before the driver is removed | |
5263 | * from memory. | |
5264 | **/ | |
5265 | static void __exit ixgbe_exit_module(void) | |
5266 | { | |
5dd2d332 | 5267 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
5268 | dca_unregister_notify(&dca_notifier); |
5269 | #endif | |
9a799d71 AK |
5270 | pci_unregister_driver(&ixgbe_driver); |
5271 | } | |
bd0362dd | 5272 | |
5dd2d332 | 5273 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 5274 | static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event, |
b4617240 | 5275 | void *p) |
bd0362dd JC |
5276 | { |
5277 | int ret_val; | |
5278 | ||
5279 | ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event, | |
b4617240 | 5280 | __ixgbe_notify_dca); |
bd0362dd JC |
5281 | |
5282 | return ret_val ? NOTIFY_BAD : NOTIFY_DONE; | |
5283 | } | |
b453368d | 5284 | |
5dd2d332 | 5285 | #endif /* CONFIG_IXGBE_DCA */ |
b453368d AD |
5286 | #ifdef DEBUG |
5287 | /** | |
5288 | * ixgbe_get_hw_dev_name - return device name string | |
5289 | * used by hardware layer to print debugging information | |
5290 | **/ | |
5291 | char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw) | |
5292 | { | |
5293 | struct ixgbe_adapter *adapter = hw->back; | |
5294 | return adapter->netdev->name; | |
5295 | } | |
bd0362dd | 5296 | |
b453368d | 5297 | #endif |
9a799d71 AK |
5298 | module_exit(ixgbe_exit_module); |
5299 | ||
5300 | /* ixgbe_main.c */ |