]>
Commit | Line | Data |
---|---|---|
9a799d71 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
3efac5a0 | 4 | Copyright(c) 1999 - 2009 Intel Corporation. |
9a799d71 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
9a799d71 AK |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #include <linux/types.h> | |
29 | #include <linux/module.h> | |
30 | #include <linux/pci.h> | |
31 | #include <linux/netdevice.h> | |
32 | #include <linux/vmalloc.h> | |
33 | #include <linux/string.h> | |
34 | #include <linux/in.h> | |
35 | #include <linux/ip.h> | |
36 | #include <linux/tcp.h> | |
37 | #include <linux/ipv6.h> | |
38 | #include <net/checksum.h> | |
39 | #include <net/ip6_checksum.h> | |
40 | #include <linux/ethtool.h> | |
41 | #include <linux/if_vlan.h> | |
eacd73f7 | 42 | #include <scsi/fc/fc_fcoe.h> |
9a799d71 AK |
43 | |
44 | #include "ixgbe.h" | |
45 | #include "ixgbe_common.h" | |
46 | ||
47 | char ixgbe_driver_name[] = "ixgbe"; | |
9c8eb720 | 48 | static const char ixgbe_driver_string[] = |
b4617240 | 49 | "Intel(R) 10 Gigabit PCI Express Network Driver"; |
9a799d71 | 50 | |
ba98898e | 51 | #define DRV_VERSION "2.0.24-k2" |
9c8eb720 | 52 | const char ixgbe_driver_version[] = DRV_VERSION; |
3efac5a0 | 53 | static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation."; |
9a799d71 AK |
54 | |
55 | static const struct ixgbe_info *ixgbe_info_tbl[] = { | |
b4617240 | 56 | [board_82598] = &ixgbe_82598_info, |
e8e26350 | 57 | [board_82599] = &ixgbe_82599_info, |
9a799d71 AK |
58 | }; |
59 | ||
60 | /* ixgbe_pci_tbl - PCI Device ID Table | |
61 | * | |
62 | * Wildcard entries (PCI_ANY_ID) should come last | |
63 | * Last entry must be all 0s | |
64 | * | |
65 | * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, | |
66 | * Class, Class Mask, private data (not used) } | |
67 | */ | |
68 | static struct pci_device_id ixgbe_pci_tbl[] = { | |
1e336d0f DS |
69 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), |
70 | board_82598 }, | |
9a799d71 | 71 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), |
3957d63d | 72 | board_82598 }, |
9a799d71 | 73 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), |
3957d63d | 74 | board_82598 }, |
0befdb3e JB |
75 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), |
76 | board_82598 }, | |
9a799d71 | 77 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), |
3957d63d | 78 | board_82598 }, |
8d792cd9 JB |
79 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), |
80 | board_82598 }, | |
c4900be0 DS |
81 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), |
82 | board_82598 }, | |
83 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), | |
84 | board_82598 }, | |
b95f5fcb JB |
85 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), |
86 | board_82598 }, | |
c4900be0 DS |
87 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), |
88 | board_82598 }, | |
2f21bdd3 DS |
89 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), |
90 | board_82598 }, | |
e8e26350 PW |
91 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), |
92 | board_82599 }, | |
1fcf03e6 PWJ |
93 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), |
94 | board_82599 }, | |
e8e26350 PW |
95 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), |
96 | board_82599 }, | |
9a799d71 AK |
97 | |
98 | /* required last entry */ | |
99 | {0, } | |
100 | }; | |
101 | MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl); | |
102 | ||
5dd2d332 | 103 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 104 | static int ixgbe_notify_dca(struct notifier_block *, unsigned long event, |
b4617240 | 105 | void *p); |
bd0362dd JC |
106 | static struct notifier_block dca_notifier = { |
107 | .notifier_call = ixgbe_notify_dca, | |
108 | .next = NULL, | |
109 | .priority = 0 | |
110 | }; | |
111 | #endif | |
112 | ||
9a799d71 AK |
113 | MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); |
114 | MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver"); | |
115 | MODULE_LICENSE("GPL"); | |
116 | MODULE_VERSION(DRV_VERSION); | |
117 | ||
118 | #define DEFAULT_DEBUG_LEVEL_SHIFT 3 | |
119 | ||
5eba3699 AV |
120 | static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter) |
121 | { | |
122 | u32 ctrl_ext; | |
123 | ||
124 | /* Let firmware take over control of h/w */ | |
125 | ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); | |
126 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, | |
b4617240 | 127 | ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD); |
5eba3699 AV |
128 | } |
129 | ||
130 | static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter) | |
131 | { | |
132 | u32 ctrl_ext; | |
133 | ||
134 | /* Let firmware know the driver has taken over */ | |
135 | ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); | |
136 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, | |
b4617240 | 137 | ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD); |
5eba3699 | 138 | } |
9a799d71 | 139 | |
e8e26350 PW |
140 | /* |
141 | * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors | |
142 | * @adapter: pointer to adapter struct | |
143 | * @direction: 0 for Rx, 1 for Tx, -1 for other causes | |
144 | * @queue: queue to map the corresponding interrupt to | |
145 | * @msix_vector: the vector to map to the corresponding queue | |
146 | * | |
147 | */ | |
148 | static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction, | |
149 | u8 queue, u8 msix_vector) | |
9a799d71 AK |
150 | { |
151 | u32 ivar, index; | |
e8e26350 PW |
152 | struct ixgbe_hw *hw = &adapter->hw; |
153 | switch (hw->mac.type) { | |
154 | case ixgbe_mac_82598EB: | |
155 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
156 | if (direction == -1) | |
157 | direction = 0; | |
158 | index = (((direction * 64) + queue) >> 2) & 0x1F; | |
159 | ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); | |
160 | ivar &= ~(0xFF << (8 * (queue & 0x3))); | |
161 | ivar |= (msix_vector << (8 * (queue & 0x3))); | |
162 | IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar); | |
163 | break; | |
164 | case ixgbe_mac_82599EB: | |
165 | if (direction == -1) { | |
166 | /* other causes */ | |
167 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
168 | index = ((queue & 1) * 8); | |
169 | ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC); | |
170 | ivar &= ~(0xFF << index); | |
171 | ivar |= (msix_vector << index); | |
172 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar); | |
173 | break; | |
174 | } else { | |
175 | /* tx or rx causes */ | |
176 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
177 | index = ((16 * (queue & 1)) + (8 * direction)); | |
178 | ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); | |
179 | ivar &= ~(0xFF << index); | |
180 | ivar |= (msix_vector << index); | |
181 | IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar); | |
182 | break; | |
183 | } | |
184 | default: | |
185 | break; | |
186 | } | |
9a799d71 AK |
187 | } |
188 | ||
189 | static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter, | |
b4617240 PW |
190 | struct ixgbe_tx_buffer |
191 | *tx_buffer_info) | |
9a799d71 | 192 | { |
44df32c5 | 193 | tx_buffer_info->dma = 0; |
9a799d71 | 194 | if (tx_buffer_info->skb) { |
44df32c5 AD |
195 | skb_dma_unmap(&adapter->pdev->dev, tx_buffer_info->skb, |
196 | DMA_TO_DEVICE); | |
9a799d71 AK |
197 | dev_kfree_skb_any(tx_buffer_info->skb); |
198 | tx_buffer_info->skb = NULL; | |
199 | } | |
44df32c5 | 200 | tx_buffer_info->time_stamp = 0; |
9a799d71 AK |
201 | /* tx_buffer_info must be completely set up in the transmit path */ |
202 | } | |
203 | ||
204 | static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter, | |
b4617240 PW |
205 | struct ixgbe_ring *tx_ring, |
206 | unsigned int eop) | |
9a799d71 | 207 | { |
e01c31a5 | 208 | struct ixgbe_hw *hw = &adapter->hw; |
e01c31a5 | 209 | |
9a799d71 | 210 | /* Detect a transmit hang in hardware, this serializes the |
e01c31a5 | 211 | * check with the clearing of time_stamp and movement of eop */ |
9a799d71 | 212 | adapter->detect_tx_hung = false; |
44df32c5 | 213 | if (tx_ring->tx_buffer_info[eop].time_stamp && |
9a799d71 AK |
214 | time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) && |
215 | !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) { | |
216 | /* detected Tx unit hang */ | |
e01c31a5 JB |
217 | union ixgbe_adv_tx_desc *tx_desc; |
218 | tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop); | |
9a799d71 | 219 | DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n" |
e01c31a5 JB |
220 | " Tx Queue <%d>\n" |
221 | " TDH, TDT <%x>, <%x>\n" | |
9a799d71 AK |
222 | " next_to_use <%x>\n" |
223 | " next_to_clean <%x>\n" | |
224 | "tx_buffer_info[next_to_clean]\n" | |
225 | " time_stamp <%lx>\n" | |
e01c31a5 JB |
226 | " jiffies <%lx>\n", |
227 | tx_ring->queue_index, | |
44df32c5 AD |
228 | IXGBE_READ_REG(hw, tx_ring->head), |
229 | IXGBE_READ_REG(hw, tx_ring->tail), | |
e01c31a5 JB |
230 | tx_ring->next_to_use, eop, |
231 | tx_ring->tx_buffer_info[eop].time_stamp, jiffies); | |
9a799d71 AK |
232 | return true; |
233 | } | |
234 | ||
235 | return false; | |
236 | } | |
237 | ||
b4617240 PW |
238 | #define IXGBE_MAX_TXD_PWR 14 |
239 | #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR) | |
e092be60 AV |
240 | |
241 | /* Tx Descriptors needed, worst case */ | |
242 | #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \ | |
243 | (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0)) | |
244 | #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \ | |
b4617240 | 245 | MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */ |
e092be60 | 246 | |
e01c31a5 JB |
247 | static void ixgbe_tx_timeout(struct net_device *netdev); |
248 | ||
9a799d71 AK |
249 | /** |
250 | * ixgbe_clean_tx_irq - Reclaim resources after transmit completes | |
251 | * @adapter: board private structure | |
e01c31a5 | 252 | * @tx_ring: tx ring to clean |
9a1a69ad JB |
253 | * |
254 | * returns true if transmit work is done | |
9a799d71 AK |
255 | **/ |
256 | static bool ixgbe_clean_tx_irq(struct ixgbe_adapter *adapter, | |
e01c31a5 | 257 | struct ixgbe_ring *tx_ring) |
9a799d71 | 258 | { |
e01c31a5 | 259 | struct net_device *netdev = adapter->netdev; |
12207e49 PWJ |
260 | union ixgbe_adv_tx_desc *tx_desc, *eop_desc; |
261 | struct ixgbe_tx_buffer *tx_buffer_info; | |
262 | unsigned int i, eop, count = 0; | |
e01c31a5 | 263 | unsigned int total_bytes = 0, total_packets = 0; |
9a799d71 AK |
264 | |
265 | i = tx_ring->next_to_clean; | |
12207e49 PWJ |
266 | eop = tx_ring->tx_buffer_info[i].next_to_watch; |
267 | eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop); | |
268 | ||
269 | while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) && | |
9a1a69ad | 270 | (count < tx_ring->work_limit)) { |
12207e49 PWJ |
271 | bool cleaned = false; |
272 | for ( ; !cleaned; count++) { | |
273 | struct sk_buff *skb; | |
9a799d71 AK |
274 | tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i); |
275 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
12207e49 | 276 | cleaned = (i == eop); |
e01c31a5 | 277 | skb = tx_buffer_info->skb; |
9a799d71 | 278 | |
12207e49 | 279 | if (cleaned && skb) { |
e092be60 | 280 | unsigned int segs, bytecount; |
e01c31a5 JB |
281 | |
282 | /* gso_segs is currently only valid for tcp */ | |
e092be60 AV |
283 | segs = skb_shinfo(skb)->gso_segs ?: 1; |
284 | /* multiply data chunks by size of headers */ | |
285 | bytecount = ((segs - 1) * skb_headlen(skb)) + | |
e01c31a5 JB |
286 | skb->len; |
287 | total_packets += segs; | |
288 | total_bytes += bytecount; | |
e092be60 | 289 | } |
e01c31a5 | 290 | |
9a799d71 | 291 | ixgbe_unmap_and_free_tx_resource(adapter, |
e01c31a5 | 292 | tx_buffer_info); |
9a799d71 | 293 | |
12207e49 PWJ |
294 | tx_desc->wb.status = 0; |
295 | ||
9a799d71 AK |
296 | i++; |
297 | if (i == tx_ring->count) | |
298 | i = 0; | |
e01c31a5 | 299 | } |
12207e49 PWJ |
300 | |
301 | eop = tx_ring->tx_buffer_info[i].next_to_watch; | |
302 | eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop); | |
303 | } | |
304 | ||
9a799d71 AK |
305 | tx_ring->next_to_clean = i; |
306 | ||
e092be60 | 307 | #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) |
e01c31a5 JB |
308 | if (unlikely(count && netif_carrier_ok(netdev) && |
309 | (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) { | |
e092be60 AV |
310 | /* Make sure that anybody stopping the queue after this |
311 | * sees the new next_to_clean. | |
312 | */ | |
313 | smp_mb(); | |
30eba97a AV |
314 | if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) && |
315 | !test_bit(__IXGBE_DOWN, &adapter->state)) { | |
316 | netif_wake_subqueue(netdev, tx_ring->queue_index); | |
e01c31a5 | 317 | ++adapter->restart_queue; |
30eba97a | 318 | } |
e092be60 | 319 | } |
9a799d71 | 320 | |
e01c31a5 JB |
321 | if (adapter->detect_tx_hung) { |
322 | if (ixgbe_check_tx_hang(adapter, tx_ring, i)) { | |
323 | /* schedule immediate reset if we believe we hung */ | |
324 | DPRINTK(PROBE, INFO, | |
325 | "tx hang %d detected, resetting adapter\n", | |
326 | adapter->tx_timeout_count + 1); | |
327 | ixgbe_tx_timeout(adapter->netdev); | |
328 | } | |
329 | } | |
9a799d71 | 330 | |
e01c31a5 | 331 | /* re-arm the interrupt */ |
835462fc NS |
332 | if (count >= tx_ring->work_limit) { |
333 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) | |
334 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, | |
335 | tx_ring->v_idx); | |
336 | else if (tx_ring->v_idx & 0xFFFFFFFF) | |
337 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), | |
338 | tx_ring->v_idx); | |
339 | else | |
340 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), | |
341 | (tx_ring->v_idx >> 32)); | |
342 | } | |
343 | ||
9a799d71 | 344 | |
e01c31a5 JB |
345 | tx_ring->total_bytes += total_bytes; |
346 | tx_ring->total_packets += total_packets; | |
e01c31a5 | 347 | tx_ring->stats.packets += total_packets; |
12207e49 | 348 | tx_ring->stats.bytes += total_bytes; |
e01c31a5 JB |
349 | adapter->net_stats.tx_bytes += total_bytes; |
350 | adapter->net_stats.tx_packets += total_packets; | |
9a1a69ad | 351 | return (count < tx_ring->work_limit); |
9a799d71 AK |
352 | } |
353 | ||
5dd2d332 | 354 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 355 | static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter, |
b4617240 | 356 | struct ixgbe_ring *rx_ring) |
bd0362dd JC |
357 | { |
358 | u32 rxctrl; | |
359 | int cpu = get_cpu(); | |
3a581073 | 360 | int q = rx_ring - adapter->rx_ring; |
bd0362dd | 361 | |
3a581073 | 362 | if (rx_ring->cpu != cpu) { |
bd0362dd | 363 | rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q)); |
e8e26350 PW |
364 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
365 | rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK; | |
366 | rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu); | |
367 | } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { | |
368 | rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599; | |
369 | rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) << | |
370 | IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599); | |
371 | } | |
bd0362dd JC |
372 | rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN; |
373 | rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN; | |
15005a32 DS |
374 | rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN); |
375 | rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN | | |
e8e26350 | 376 | IXGBE_DCA_RXCTRL_DESC_HSRO_EN); |
bd0362dd | 377 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl); |
3a581073 | 378 | rx_ring->cpu = cpu; |
bd0362dd JC |
379 | } |
380 | put_cpu(); | |
381 | } | |
382 | ||
383 | static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter, | |
b4617240 | 384 | struct ixgbe_ring *tx_ring) |
bd0362dd JC |
385 | { |
386 | u32 txctrl; | |
387 | int cpu = get_cpu(); | |
3a581073 | 388 | int q = tx_ring - adapter->tx_ring; |
bd0362dd | 389 | |
3a581073 | 390 | if (tx_ring->cpu != cpu) { |
bd0362dd | 391 | txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q)); |
e8e26350 PW |
392 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
393 | txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK; | |
394 | txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu); | |
395 | } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { | |
396 | txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599; | |
397 | txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) << | |
398 | IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599); | |
399 | } | |
bd0362dd JC |
400 | txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN; |
401 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl); | |
3a581073 | 402 | tx_ring->cpu = cpu; |
bd0362dd JC |
403 | } |
404 | put_cpu(); | |
405 | } | |
406 | ||
407 | static void ixgbe_setup_dca(struct ixgbe_adapter *adapter) | |
408 | { | |
409 | int i; | |
410 | ||
411 | if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED)) | |
412 | return; | |
413 | ||
e35ec126 AD |
414 | /* always use CB2 mode, difference is masked in the CB driver */ |
415 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2); | |
416 | ||
bd0362dd JC |
417 | for (i = 0; i < adapter->num_tx_queues; i++) { |
418 | adapter->tx_ring[i].cpu = -1; | |
419 | ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]); | |
420 | } | |
421 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
422 | adapter->rx_ring[i].cpu = -1; | |
423 | ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]); | |
424 | } | |
425 | } | |
426 | ||
427 | static int __ixgbe_notify_dca(struct device *dev, void *data) | |
428 | { | |
429 | struct net_device *netdev = dev_get_drvdata(dev); | |
430 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
431 | unsigned long event = *(unsigned long *)data; | |
432 | ||
433 | switch (event) { | |
434 | case DCA_PROVIDER_ADD: | |
96b0e0f6 JB |
435 | /* if we're already enabled, don't do it again */ |
436 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
437 | break; | |
652f093f | 438 | if (dca_add_requester(dev) == 0) { |
96b0e0f6 | 439 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; |
bd0362dd JC |
440 | ixgbe_setup_dca(adapter); |
441 | break; | |
442 | } | |
443 | /* Fall Through since DCA is disabled. */ | |
444 | case DCA_PROVIDER_REMOVE: | |
445 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { | |
446 | dca_remove_requester(dev); | |
447 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
448 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); | |
449 | } | |
450 | break; | |
451 | } | |
452 | ||
652f093f | 453 | return 0; |
bd0362dd JC |
454 | } |
455 | ||
5dd2d332 | 456 | #endif /* CONFIG_IXGBE_DCA */ |
9a799d71 AK |
457 | /** |
458 | * ixgbe_receive_skb - Send a completed packet up the stack | |
459 | * @adapter: board private structure | |
460 | * @skb: packet to send up | |
177db6ff MC |
461 | * @status: hardware indication of status of receive |
462 | * @rx_ring: rx descriptor ring (for a specific queue) to setup | |
463 | * @rx_desc: rx descriptor | |
9a799d71 | 464 | **/ |
78b6f4ce | 465 | static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector, |
b4617240 | 466 | struct sk_buff *skb, u8 status, |
fdaff1ce | 467 | struct ixgbe_ring *ring, |
177db6ff | 468 | union ixgbe_adv_rx_desc *rx_desc) |
9a799d71 | 469 | { |
78b6f4ce HX |
470 | struct ixgbe_adapter *adapter = q_vector->adapter; |
471 | struct napi_struct *napi = &q_vector->napi; | |
177db6ff MC |
472 | bool is_vlan = (status & IXGBE_RXD_STAT_VP); |
473 | u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan); | |
9a799d71 | 474 | |
fdaff1ce | 475 | skb_record_rx_queue(skb, ring->queue_index); |
182ff8df | 476 | if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) { |
2f90b865 | 477 | if (adapter->vlgrp && is_vlan && (tag != 0)) |
78b6f4ce | 478 | vlan_gro_receive(napi, adapter->vlgrp, tag, skb); |
9a799d71 | 479 | else |
78b6f4ce | 480 | napi_gro_receive(napi, skb); |
177db6ff | 481 | } else { |
182ff8df AD |
482 | if (adapter->vlgrp && is_vlan && (tag != 0)) |
483 | vlan_hwaccel_rx(skb, adapter->vlgrp, tag); | |
484 | else | |
485 | netif_rx(skb); | |
9a799d71 AK |
486 | } |
487 | } | |
488 | ||
e59bd25d AV |
489 | /** |
490 | * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum | |
491 | * @adapter: address of board private structure | |
492 | * @status_err: hardware indication of status of receive | |
493 | * @skb: skb currently being received and modified | |
494 | **/ | |
9a799d71 | 495 | static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter, |
712744be | 496 | u32 status_err, struct sk_buff *skb) |
9a799d71 AK |
497 | { |
498 | skb->ip_summed = CHECKSUM_NONE; | |
499 | ||
712744be JB |
500 | /* Rx csum disabled */ |
501 | if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED)) | |
9a799d71 | 502 | return; |
e59bd25d AV |
503 | |
504 | /* if IP and error */ | |
505 | if ((status_err & IXGBE_RXD_STAT_IPCS) && | |
506 | (status_err & IXGBE_RXDADV_ERR_IPE)) { | |
9a799d71 AK |
507 | adapter->hw_csum_rx_error++; |
508 | return; | |
509 | } | |
e59bd25d AV |
510 | |
511 | if (!(status_err & IXGBE_RXD_STAT_L4CS)) | |
512 | return; | |
513 | ||
514 | if (status_err & IXGBE_RXDADV_ERR_TCPE) { | |
515 | adapter->hw_csum_rx_error++; | |
516 | return; | |
517 | } | |
518 | ||
9a799d71 | 519 | /* It must be a TCP or UDP packet with a valid checksum */ |
e59bd25d | 520 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
9a799d71 AK |
521 | adapter->hw_csum_rx_good++; |
522 | } | |
523 | ||
e8e26350 PW |
524 | static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw, |
525 | struct ixgbe_ring *rx_ring, u32 val) | |
526 | { | |
527 | /* | |
528 | * Force memory writes to complete before letting h/w | |
529 | * know there are new descriptors to fetch. (Only | |
530 | * applicable for weak-ordered memory model archs, | |
531 | * such as IA-64). | |
532 | */ | |
533 | wmb(); | |
534 | IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val); | |
535 | } | |
536 | ||
9a799d71 AK |
537 | /** |
538 | * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split | |
539 | * @adapter: address of board private structure | |
540 | **/ | |
541 | static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter, | |
7c6e0a43 JB |
542 | struct ixgbe_ring *rx_ring, |
543 | int cleaned_count) | |
9a799d71 | 544 | { |
9a799d71 AK |
545 | struct pci_dev *pdev = adapter->pdev; |
546 | union ixgbe_adv_rx_desc *rx_desc; | |
3a581073 | 547 | struct ixgbe_rx_buffer *bi; |
9a799d71 | 548 | unsigned int i; |
e8e26350 | 549 | unsigned int bufsz = rx_ring->rx_buf_len + NET_IP_ALIGN; |
9a799d71 AK |
550 | |
551 | i = rx_ring->next_to_use; | |
3a581073 | 552 | bi = &rx_ring->rx_buffer_info[i]; |
9a799d71 AK |
553 | |
554 | while (cleaned_count--) { | |
555 | rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i); | |
556 | ||
762f4c57 | 557 | if (!bi->page_dma && |
3a581073 | 558 | (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) { |
3a581073 | 559 | if (!bi->page) { |
762f4c57 JB |
560 | bi->page = alloc_page(GFP_ATOMIC); |
561 | if (!bi->page) { | |
562 | adapter->alloc_rx_page_failed++; | |
563 | goto no_buffers; | |
564 | } | |
565 | bi->page_offset = 0; | |
566 | } else { | |
567 | /* use a half page if we're re-using */ | |
568 | bi->page_offset ^= (PAGE_SIZE / 2); | |
9a799d71 | 569 | } |
762f4c57 JB |
570 | |
571 | bi->page_dma = pci_map_page(pdev, bi->page, | |
572 | bi->page_offset, | |
573 | (PAGE_SIZE / 2), | |
574 | PCI_DMA_FROMDEVICE); | |
9a799d71 AK |
575 | } |
576 | ||
3a581073 | 577 | if (!bi->skb) { |
5ecc3614 | 578 | struct sk_buff *skb; |
e8e26350 | 579 | skb = netdev_alloc_skb(adapter->netdev, bufsz); |
9a799d71 AK |
580 | |
581 | if (!skb) { | |
582 | adapter->alloc_rx_buff_failed++; | |
583 | goto no_buffers; | |
584 | } | |
585 | ||
586 | /* | |
587 | * Make buffer alignment 2 beyond a 16 byte boundary | |
588 | * this will result in a 16 byte aligned IP header after | |
589 | * the 14 byte MAC header is removed | |
590 | */ | |
591 | skb_reserve(skb, NET_IP_ALIGN); | |
592 | ||
3a581073 | 593 | bi->skb = skb; |
e8e26350 | 594 | bi->dma = pci_map_single(pdev, skb->data, bufsz, |
3a581073 | 595 | PCI_DMA_FROMDEVICE); |
9a799d71 AK |
596 | } |
597 | /* Refresh the desc even if buffer_addrs didn't change because | |
598 | * each write-back erases this info. */ | |
599 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { | |
3a581073 JB |
600 | rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma); |
601 | rx_desc->read.hdr_addr = cpu_to_le64(bi->dma); | |
9a799d71 | 602 | } else { |
3a581073 | 603 | rx_desc->read.pkt_addr = cpu_to_le64(bi->dma); |
9a799d71 AK |
604 | } |
605 | ||
606 | i++; | |
607 | if (i == rx_ring->count) | |
608 | i = 0; | |
3a581073 | 609 | bi = &rx_ring->rx_buffer_info[i]; |
9a799d71 | 610 | } |
7c6e0a43 | 611 | |
9a799d71 AK |
612 | no_buffers: |
613 | if (rx_ring->next_to_use != i) { | |
614 | rx_ring->next_to_use = i; | |
615 | if (i-- == 0) | |
616 | i = (rx_ring->count - 1); | |
617 | ||
e8e26350 | 618 | ixgbe_release_rx_desc(&adapter->hw, rx_ring, i); |
9a799d71 AK |
619 | } |
620 | } | |
621 | ||
7c6e0a43 JB |
622 | static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc) |
623 | { | |
624 | return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info; | |
625 | } | |
626 | ||
627 | static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc) | |
628 | { | |
629 | return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; | |
630 | } | |
631 | ||
f8212f97 AD |
632 | static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc) |
633 | { | |
634 | return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) & | |
635 | IXGBE_RXDADV_RSCCNT_MASK) >> | |
636 | IXGBE_RXDADV_RSCCNT_SHIFT; | |
637 | } | |
638 | ||
639 | /** | |
640 | * ixgbe_transform_rsc_queue - change rsc queue into a full packet | |
641 | * @skb: pointer to the last skb in the rsc queue | |
642 | * | |
643 | * This function changes a queue full of hw rsc buffers into a completed | |
644 | * packet. It uses the ->prev pointers to find the first packet and then | |
645 | * turns it into the frag list owner. | |
646 | **/ | |
647 | static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb) | |
648 | { | |
649 | unsigned int frag_list_size = 0; | |
650 | ||
651 | while (skb->prev) { | |
652 | struct sk_buff *prev = skb->prev; | |
653 | frag_list_size += skb->len; | |
654 | skb->prev = NULL; | |
655 | skb = prev; | |
656 | } | |
657 | ||
658 | skb_shinfo(skb)->frag_list = skb->next; | |
659 | skb->next = NULL; | |
660 | skb->len += frag_list_size; | |
661 | skb->data_len += frag_list_size; | |
662 | skb->truesize += frag_list_size; | |
663 | return skb; | |
664 | } | |
665 | ||
78b6f4ce | 666 | static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, |
b4617240 PW |
667 | struct ixgbe_ring *rx_ring, |
668 | int *work_done, int work_to_do) | |
9a799d71 | 669 | { |
78b6f4ce | 670 | struct ixgbe_adapter *adapter = q_vector->adapter; |
9a799d71 AK |
671 | struct pci_dev *pdev = adapter->pdev; |
672 | union ixgbe_adv_rx_desc *rx_desc, *next_rxd; | |
673 | struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer; | |
674 | struct sk_buff *skb; | |
f8212f97 | 675 | unsigned int i, rsc_count = 0; |
7c6e0a43 | 676 | u32 len, staterr; |
177db6ff MC |
677 | u16 hdr_info; |
678 | bool cleaned = false; | |
9a799d71 | 679 | int cleaned_count = 0; |
d2f4fbe2 | 680 | unsigned int total_rx_bytes = 0, total_rx_packets = 0; |
9a799d71 AK |
681 | |
682 | i = rx_ring->next_to_clean; | |
9a799d71 AK |
683 | rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i); |
684 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
685 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; | |
9a799d71 AK |
686 | |
687 | while (staterr & IXGBE_RXD_STAT_DD) { | |
7c6e0a43 | 688 | u32 upper_len = 0; |
9a799d71 AK |
689 | if (*work_done >= work_to_do) |
690 | break; | |
691 | (*work_done)++; | |
692 | ||
693 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { | |
7c6e0a43 JB |
694 | hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc)); |
695 | len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >> | |
762f4c57 | 696 | IXGBE_RXDADV_HDRBUFLEN_SHIFT; |
9a799d71 AK |
697 | if (hdr_info & IXGBE_RXDADV_SPH) |
698 | adapter->rx_hdr_split++; | |
699 | if (len > IXGBE_RX_HDR_SIZE) | |
700 | len = IXGBE_RX_HDR_SIZE; | |
701 | upper_len = le16_to_cpu(rx_desc->wb.upper.length); | |
7c6e0a43 | 702 | } else { |
9a799d71 | 703 | len = le16_to_cpu(rx_desc->wb.upper.length); |
7c6e0a43 | 704 | } |
9a799d71 AK |
705 | |
706 | cleaned = true; | |
707 | skb = rx_buffer_info->skb; | |
708 | prefetch(skb->data - NET_IP_ALIGN); | |
709 | rx_buffer_info->skb = NULL; | |
710 | ||
21fa4e66 | 711 | if (rx_buffer_info->dma) { |
9a799d71 | 712 | pci_unmap_single(pdev, rx_buffer_info->dma, |
5ecc3614 | 713 | rx_ring->rx_buf_len, |
b4617240 | 714 | PCI_DMA_FROMDEVICE); |
9a799d71 AK |
715 | skb_put(skb, len); |
716 | } | |
717 | ||
718 | if (upper_len) { | |
719 | pci_unmap_page(pdev, rx_buffer_info->page_dma, | |
762f4c57 | 720 | PAGE_SIZE / 2, PCI_DMA_FROMDEVICE); |
9a799d71 AK |
721 | rx_buffer_info->page_dma = 0; |
722 | skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, | |
762f4c57 JB |
723 | rx_buffer_info->page, |
724 | rx_buffer_info->page_offset, | |
725 | upper_len); | |
726 | ||
727 | if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) || | |
728 | (page_count(rx_buffer_info->page) != 1)) | |
729 | rx_buffer_info->page = NULL; | |
730 | else | |
731 | get_page(rx_buffer_info->page); | |
9a799d71 AK |
732 | |
733 | skb->len += upper_len; | |
734 | skb->data_len += upper_len; | |
735 | skb->truesize += upper_len; | |
736 | } | |
737 | ||
738 | i++; | |
739 | if (i == rx_ring->count) | |
740 | i = 0; | |
9a799d71 AK |
741 | |
742 | next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i); | |
743 | prefetch(next_rxd); | |
9a799d71 | 744 | cleaned_count++; |
f8212f97 AD |
745 | |
746 | if (adapter->flags & IXGBE_FLAG_RSC_CAPABLE) | |
747 | rsc_count = ixgbe_get_rsc_count(rx_desc); | |
748 | ||
749 | if (rsc_count) { | |
750 | u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >> | |
751 | IXGBE_RXDADV_NEXTP_SHIFT; | |
752 | next_buffer = &rx_ring->rx_buffer_info[nextp]; | |
753 | rx_ring->rsc_count += (rsc_count - 1); | |
754 | } else { | |
755 | next_buffer = &rx_ring->rx_buffer_info[i]; | |
756 | } | |
757 | ||
9a799d71 | 758 | if (staterr & IXGBE_RXD_STAT_EOP) { |
f8212f97 AD |
759 | if (skb->prev) |
760 | skb = ixgbe_transform_rsc_queue(skb); | |
9a799d71 AK |
761 | rx_ring->stats.packets++; |
762 | rx_ring->stats.bytes += skb->len; | |
763 | } else { | |
f8212f97 AD |
764 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { |
765 | rx_buffer_info->skb = next_buffer->skb; | |
766 | rx_buffer_info->dma = next_buffer->dma; | |
767 | next_buffer->skb = skb; | |
768 | next_buffer->dma = 0; | |
769 | } else { | |
770 | skb->next = next_buffer->skb; | |
771 | skb->next->prev = skb; | |
772 | } | |
9a799d71 AK |
773 | adapter->non_eop_descs++; |
774 | goto next_desc; | |
775 | } | |
776 | ||
777 | if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) { | |
778 | dev_kfree_skb_irq(skb); | |
779 | goto next_desc; | |
780 | } | |
781 | ||
782 | ixgbe_rx_checksum(adapter, staterr, skb); | |
d2f4fbe2 AV |
783 | |
784 | /* probably a little skewed due to removing CRC */ | |
785 | total_rx_bytes += skb->len; | |
786 | total_rx_packets++; | |
787 | ||
74ce8dd2 | 788 | skb->protocol = eth_type_trans(skb, adapter->netdev); |
332d4a7d YZ |
789 | #ifdef IXGBE_FCOE |
790 | /* if ddp, not passing to ULD unless for FCP_RSP or error */ | |
791 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) | |
792 | if (!ixgbe_fcoe_ddp(adapter, rx_desc, skb)) | |
793 | goto next_desc; | |
794 | #endif /* IXGBE_FCOE */ | |
fdaff1ce | 795 | ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc); |
9a799d71 AK |
796 | |
797 | next_desc: | |
798 | rx_desc->wb.upper.status_error = 0; | |
799 | ||
800 | /* return some buffers to hardware, one at a time is too slow */ | |
801 | if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) { | |
802 | ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count); | |
803 | cleaned_count = 0; | |
804 | } | |
805 | ||
806 | /* use prefetched values */ | |
807 | rx_desc = next_rxd; | |
f8212f97 | 808 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; |
9a799d71 AK |
809 | |
810 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
177db6ff MC |
811 | } |
812 | ||
9a799d71 AK |
813 | rx_ring->next_to_clean = i; |
814 | cleaned_count = IXGBE_DESC_UNUSED(rx_ring); | |
815 | ||
816 | if (cleaned_count) | |
817 | ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count); | |
818 | ||
f494e8fa AV |
819 | rx_ring->total_packets += total_rx_packets; |
820 | rx_ring->total_bytes += total_rx_bytes; | |
821 | adapter->net_stats.rx_bytes += total_rx_bytes; | |
822 | adapter->net_stats.rx_packets += total_rx_packets; | |
823 | ||
9a799d71 AK |
824 | return cleaned; |
825 | } | |
826 | ||
021230d4 | 827 | static int ixgbe_clean_rxonly(struct napi_struct *, int); |
9a799d71 AK |
828 | /** |
829 | * ixgbe_configure_msix - Configure MSI-X hardware | |
830 | * @adapter: board private structure | |
831 | * | |
832 | * ixgbe_configure_msix sets up the hardware to properly generate MSI-X | |
833 | * interrupts. | |
834 | **/ | |
835 | static void ixgbe_configure_msix(struct ixgbe_adapter *adapter) | |
836 | { | |
021230d4 AV |
837 | struct ixgbe_q_vector *q_vector; |
838 | int i, j, q_vectors, v_idx, r_idx; | |
839 | u32 mask; | |
9a799d71 | 840 | |
021230d4 | 841 | q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; |
9a799d71 | 842 | |
4df10466 JB |
843 | /* |
844 | * Populate the IVAR table and set the ITR values to the | |
021230d4 AV |
845 | * corresponding register. |
846 | */ | |
847 | for (v_idx = 0; v_idx < q_vectors; v_idx++) { | |
7a921c93 | 848 | q_vector = adapter->q_vector[v_idx]; |
021230d4 AV |
849 | /* XXX for_each_bit(...) */ |
850 | r_idx = find_first_bit(q_vector->rxr_idx, | |
b4617240 | 851 | adapter->num_rx_queues); |
021230d4 AV |
852 | |
853 | for (i = 0; i < q_vector->rxr_count; i++) { | |
854 | j = adapter->rx_ring[r_idx].reg_idx; | |
e8e26350 | 855 | ixgbe_set_ivar(adapter, 0, j, v_idx); |
021230d4 | 856 | r_idx = find_next_bit(q_vector->rxr_idx, |
b4617240 PW |
857 | adapter->num_rx_queues, |
858 | r_idx + 1); | |
021230d4 AV |
859 | } |
860 | r_idx = find_first_bit(q_vector->txr_idx, | |
b4617240 | 861 | adapter->num_tx_queues); |
021230d4 AV |
862 | |
863 | for (i = 0; i < q_vector->txr_count; i++) { | |
864 | j = adapter->tx_ring[r_idx].reg_idx; | |
e8e26350 | 865 | ixgbe_set_ivar(adapter, 1, j, v_idx); |
021230d4 | 866 | r_idx = find_next_bit(q_vector->txr_idx, |
b4617240 PW |
867 | adapter->num_tx_queues, |
868 | r_idx + 1); | |
021230d4 AV |
869 | } |
870 | ||
30efa5a3 | 871 | /* if this is a tx only vector halve the interrupt rate */ |
021230d4 | 872 | if (q_vector->txr_count && !q_vector->rxr_count) |
30efa5a3 | 873 | q_vector->eitr = (adapter->eitr_param >> 1); |
509ee935 | 874 | else if (q_vector->rxr_count) |
30efa5a3 JB |
875 | /* rx only */ |
876 | q_vector->eitr = adapter->eitr_param; | |
021230d4 | 877 | |
509ee935 | 878 | /* |
4df10466 | 879 | * since this is initial set up don't need to call |
509ee935 JB |
880 | * ixgbe_write_eitr helper |
881 | */ | |
021230d4 | 882 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), |
b4617240 | 883 | EITR_INTS_PER_SEC_TO_REG(q_vector->eitr)); |
9a799d71 AK |
884 | } |
885 | ||
e8e26350 PW |
886 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) |
887 | ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX, | |
888 | v_idx); | |
889 | else if (adapter->hw.mac.type == ixgbe_mac_82599EB) | |
890 | ixgbe_set_ivar(adapter, -1, 1, v_idx); | |
021230d4 AV |
891 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950); |
892 | ||
41fb9248 | 893 | /* set up to autoclear timer, and the vectors */ |
021230d4 | 894 | mask = IXGBE_EIMS_ENABLE_MASK; |
41fb9248 | 895 | mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC); |
021230d4 | 896 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask); |
9a799d71 AK |
897 | } |
898 | ||
f494e8fa AV |
899 | enum latency_range { |
900 | lowest_latency = 0, | |
901 | low_latency = 1, | |
902 | bulk_latency = 2, | |
903 | latency_invalid = 255 | |
904 | }; | |
905 | ||
906 | /** | |
907 | * ixgbe_update_itr - update the dynamic ITR value based on statistics | |
908 | * @adapter: pointer to adapter | |
909 | * @eitr: eitr setting (ints per sec) to give last timeslice | |
910 | * @itr_setting: current throttle rate in ints/second | |
911 | * @packets: the number of packets during this measurement interval | |
912 | * @bytes: the number of bytes during this measurement interval | |
913 | * | |
914 | * Stores a new ITR value based on packets and byte | |
915 | * counts during the last interrupt. The advantage of per interrupt | |
916 | * computation is faster updates and more accurate ITR for the current | |
917 | * traffic pattern. Constants in this function were computed | |
918 | * based on theoretical maximum wire speed and thresholds were set based | |
919 | * on testing data as well as attempting to minimize response time | |
920 | * while increasing bulk throughput. | |
921 | * this functionality is controlled by the InterruptThrottleRate module | |
922 | * parameter (see ixgbe_param.c) | |
923 | **/ | |
924 | static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter, | |
b4617240 PW |
925 | u32 eitr, u8 itr_setting, |
926 | int packets, int bytes) | |
f494e8fa AV |
927 | { |
928 | unsigned int retval = itr_setting; | |
929 | u32 timepassed_us; | |
930 | u64 bytes_perint; | |
931 | ||
932 | if (packets == 0) | |
933 | goto update_itr_done; | |
934 | ||
935 | ||
936 | /* simple throttlerate management | |
937 | * 0-20MB/s lowest (100000 ints/s) | |
938 | * 20-100MB/s low (20000 ints/s) | |
939 | * 100-1249MB/s bulk (8000 ints/s) | |
940 | */ | |
941 | /* what was last interrupt timeslice? */ | |
942 | timepassed_us = 1000000/eitr; | |
943 | bytes_perint = bytes / timepassed_us; /* bytes/usec */ | |
944 | ||
945 | switch (itr_setting) { | |
946 | case lowest_latency: | |
947 | if (bytes_perint > adapter->eitr_low) | |
948 | retval = low_latency; | |
949 | break; | |
950 | case low_latency: | |
951 | if (bytes_perint > adapter->eitr_high) | |
952 | retval = bulk_latency; | |
953 | else if (bytes_perint <= adapter->eitr_low) | |
954 | retval = lowest_latency; | |
955 | break; | |
956 | case bulk_latency: | |
957 | if (bytes_perint <= adapter->eitr_high) | |
958 | retval = low_latency; | |
959 | break; | |
960 | } | |
961 | ||
962 | update_itr_done: | |
963 | return retval; | |
964 | } | |
965 | ||
509ee935 JB |
966 | /** |
967 | * ixgbe_write_eitr - write EITR register in hardware specific way | |
968 | * @adapter: pointer to adapter struct | |
969 | * @v_idx: vector index into q_vector array | |
970 | * @itr_reg: new value to be written in *register* format, not ints/s | |
971 | * | |
972 | * This function is made to be called by ethtool and by the driver | |
973 | * when it needs to update EITR registers at runtime. Hardware | |
974 | * specific quirks/differences are taken care of here. | |
975 | */ | |
976 | void ixgbe_write_eitr(struct ixgbe_adapter *adapter, int v_idx, u32 itr_reg) | |
977 | { | |
978 | struct ixgbe_hw *hw = &adapter->hw; | |
979 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { | |
980 | /* must write high and low 16 bits to reset counter */ | |
981 | itr_reg |= (itr_reg << 16); | |
982 | } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { | |
983 | /* | |
984 | * set the WDIS bit to not clear the timer bits and cause an | |
985 | * immediate assertion of the interrupt | |
986 | */ | |
987 | itr_reg |= IXGBE_EITR_CNT_WDIS; | |
988 | } | |
989 | IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg); | |
990 | } | |
991 | ||
f494e8fa AV |
992 | static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector) |
993 | { | |
994 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
f494e8fa AV |
995 | u32 new_itr; |
996 | u8 current_itr, ret_itr; | |
7a921c93 | 997 | int i, r_idx, v_idx = q_vector->v_idx; |
f494e8fa AV |
998 | struct ixgbe_ring *rx_ring, *tx_ring; |
999 | ||
1000 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
1001 | for (i = 0; i < q_vector->txr_count; i++) { | |
1002 | tx_ring = &(adapter->tx_ring[r_idx]); | |
1003 | ret_itr = ixgbe_update_itr(adapter, q_vector->eitr, | |
b4617240 PW |
1004 | q_vector->tx_itr, |
1005 | tx_ring->total_packets, | |
1006 | tx_ring->total_bytes); | |
f494e8fa AV |
1007 | /* if the result for this queue would decrease interrupt |
1008 | * rate for this vector then use that result */ | |
30efa5a3 | 1009 | q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ? |
b4617240 | 1010 | q_vector->tx_itr - 1 : ret_itr); |
f494e8fa | 1011 | r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, |
b4617240 | 1012 | r_idx + 1); |
f494e8fa AV |
1013 | } |
1014 | ||
1015 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
1016 | for (i = 0; i < q_vector->rxr_count; i++) { | |
1017 | rx_ring = &(adapter->rx_ring[r_idx]); | |
1018 | ret_itr = ixgbe_update_itr(adapter, q_vector->eitr, | |
b4617240 PW |
1019 | q_vector->rx_itr, |
1020 | rx_ring->total_packets, | |
1021 | rx_ring->total_bytes); | |
f494e8fa AV |
1022 | /* if the result for this queue would decrease interrupt |
1023 | * rate for this vector then use that result */ | |
30efa5a3 | 1024 | q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ? |
b4617240 | 1025 | q_vector->rx_itr - 1 : ret_itr); |
f494e8fa | 1026 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, |
b4617240 | 1027 | r_idx + 1); |
f494e8fa AV |
1028 | } |
1029 | ||
30efa5a3 | 1030 | current_itr = max(q_vector->rx_itr, q_vector->tx_itr); |
f494e8fa AV |
1031 | |
1032 | switch (current_itr) { | |
1033 | /* counts and packets in update_itr are dependent on these numbers */ | |
1034 | case lowest_latency: | |
1035 | new_itr = 100000; | |
1036 | break; | |
1037 | case low_latency: | |
1038 | new_itr = 20000; /* aka hwitr = ~200 */ | |
1039 | break; | |
1040 | case bulk_latency: | |
1041 | default: | |
1042 | new_itr = 8000; | |
1043 | break; | |
1044 | } | |
1045 | ||
1046 | if (new_itr != q_vector->eitr) { | |
1047 | u32 itr_reg; | |
509ee935 JB |
1048 | |
1049 | /* save the algorithm value here, not the smoothed one */ | |
1050 | q_vector->eitr = new_itr; | |
f494e8fa AV |
1051 | /* do an exponential smoothing */ |
1052 | new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100); | |
f494e8fa | 1053 | itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr); |
509ee935 | 1054 | ixgbe_write_eitr(adapter, v_idx, itr_reg); |
f494e8fa AV |
1055 | } |
1056 | ||
1057 | return; | |
1058 | } | |
1059 | ||
0befdb3e JB |
1060 | static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr) |
1061 | { | |
1062 | struct ixgbe_hw *hw = &adapter->hw; | |
1063 | ||
1064 | if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) && | |
1065 | (eicr & IXGBE_EICR_GPI_SDP1)) { | |
1066 | DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n"); | |
1067 | /* write to clear the interrupt */ | |
1068 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); | |
1069 | } | |
1070 | } | |
cf8280ee | 1071 | |
e8e26350 PW |
1072 | static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr) |
1073 | { | |
1074 | struct ixgbe_hw *hw = &adapter->hw; | |
1075 | ||
1076 | if (eicr & IXGBE_EICR_GPI_SDP1) { | |
1077 | /* Clear the interrupt */ | |
1078 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); | |
1079 | schedule_work(&adapter->multispeed_fiber_task); | |
1080 | } else if (eicr & IXGBE_EICR_GPI_SDP2) { | |
1081 | /* Clear the interrupt */ | |
1082 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2); | |
1083 | schedule_work(&adapter->sfp_config_module_task); | |
1084 | } else { | |
1085 | /* Interrupt isn't for us... */ | |
1086 | return; | |
1087 | } | |
1088 | } | |
1089 | ||
cf8280ee JB |
1090 | static void ixgbe_check_lsc(struct ixgbe_adapter *adapter) |
1091 | { | |
1092 | struct ixgbe_hw *hw = &adapter->hw; | |
1093 | ||
1094 | adapter->lsc_int++; | |
1095 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; | |
1096 | adapter->link_check_timeout = jiffies; | |
1097 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { | |
1098 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); | |
1099 | schedule_work(&adapter->watchdog_task); | |
1100 | } | |
1101 | } | |
1102 | ||
9a799d71 AK |
1103 | static irqreturn_t ixgbe_msix_lsc(int irq, void *data) |
1104 | { | |
1105 | struct net_device *netdev = data; | |
1106 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
1107 | struct ixgbe_hw *hw = &adapter->hw; | |
54037505 DS |
1108 | u32 eicr; |
1109 | ||
1110 | /* | |
1111 | * Workaround for Silicon errata. Use clear-by-write instead | |
1112 | * of clear-by-read. Reading with EICS will return the | |
1113 | * interrupt causes without clearing, which later be done | |
1114 | * with the write to EICR. | |
1115 | */ | |
1116 | eicr = IXGBE_READ_REG(hw, IXGBE_EICS); | |
1117 | IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); | |
9a799d71 | 1118 | |
cf8280ee JB |
1119 | if (eicr & IXGBE_EICR_LSC) |
1120 | ixgbe_check_lsc(adapter); | |
d4f80882 | 1121 | |
e8e26350 PW |
1122 | if (hw->mac.type == ixgbe_mac_82598EB) |
1123 | ixgbe_check_fan_failure(adapter, eicr); | |
0befdb3e | 1124 | |
e8e26350 PW |
1125 | if (hw->mac.type == ixgbe_mac_82599EB) |
1126 | ixgbe_check_sfp_event(adapter, eicr); | |
d4f80882 AV |
1127 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
1128 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER); | |
9a799d71 AK |
1129 | |
1130 | return IRQ_HANDLED; | |
1131 | } | |
1132 | ||
1133 | static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data) | |
1134 | { | |
021230d4 AV |
1135 | struct ixgbe_q_vector *q_vector = data; |
1136 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
3a581073 | 1137 | struct ixgbe_ring *tx_ring; |
021230d4 AV |
1138 | int i, r_idx; |
1139 | ||
1140 | if (!q_vector->txr_count) | |
1141 | return IRQ_HANDLED; | |
1142 | ||
1143 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
1144 | for (i = 0; i < q_vector->txr_count; i++) { | |
3a581073 | 1145 | tx_ring = &(adapter->tx_ring[r_idx]); |
5dd2d332 | 1146 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 1147 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) |
3a581073 | 1148 | ixgbe_update_tx_dca(adapter, tx_ring); |
bd0362dd | 1149 | #endif |
3a581073 JB |
1150 | tx_ring->total_bytes = 0; |
1151 | tx_ring->total_packets = 0; | |
1152 | ixgbe_clean_tx_irq(adapter, tx_ring); | |
021230d4 | 1153 | r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, |
b4617240 | 1154 | r_idx + 1); |
021230d4 | 1155 | } |
9a799d71 | 1156 | |
9a799d71 AK |
1157 | return IRQ_HANDLED; |
1158 | } | |
1159 | ||
021230d4 AV |
1160 | /** |
1161 | * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues) | |
1162 | * @irq: unused | |
1163 | * @data: pointer to our q_vector struct for this interrupt vector | |
1164 | **/ | |
9a799d71 AK |
1165 | static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data) |
1166 | { | |
021230d4 AV |
1167 | struct ixgbe_q_vector *q_vector = data; |
1168 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
3a581073 | 1169 | struct ixgbe_ring *rx_ring; |
021230d4 | 1170 | int r_idx; |
30efa5a3 | 1171 | int i; |
021230d4 AV |
1172 | |
1173 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
30efa5a3 JB |
1174 | for (i = 0; i < q_vector->rxr_count; i++) { |
1175 | rx_ring = &(adapter->rx_ring[r_idx]); | |
1176 | rx_ring->total_bytes = 0; | |
1177 | rx_ring->total_packets = 0; | |
1178 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, | |
1179 | r_idx + 1); | |
1180 | } | |
1181 | ||
021230d4 AV |
1182 | if (!q_vector->rxr_count) |
1183 | return IRQ_HANDLED; | |
1184 | ||
30efa5a3 | 1185 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); |
3a581073 | 1186 | rx_ring = &(adapter->rx_ring[r_idx]); |
021230d4 | 1187 | /* disable interrupts on this vector only */ |
835462fc NS |
1188 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) |
1189 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, rx_ring->v_idx); | |
1190 | else if (rx_ring->v_idx & 0xFFFFFFFF) | |
1191 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), rx_ring->v_idx); | |
1192 | else | |
1193 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), | |
1194 | (rx_ring->v_idx >> 32)); | |
288379f0 | 1195 | napi_schedule(&q_vector->napi); |
021230d4 AV |
1196 | |
1197 | return IRQ_HANDLED; | |
1198 | } | |
1199 | ||
1200 | static irqreturn_t ixgbe_msix_clean_many(int irq, void *data) | |
1201 | { | |
1202 | ixgbe_msix_clean_rx(irq, data); | |
1203 | ixgbe_msix_clean_tx(irq, data); | |
9a799d71 | 1204 | |
9a799d71 AK |
1205 | return IRQ_HANDLED; |
1206 | } | |
1207 | ||
835462fc NS |
1208 | static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter, |
1209 | u64 qmask) | |
1210 | { | |
1211 | u32 mask; | |
1212 | ||
1213 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { | |
1214 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); | |
1215 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); | |
1216 | } else { | |
1217 | mask = (qmask & 0xFFFFFFFF); | |
1218 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask); | |
1219 | mask = (qmask >> 32); | |
1220 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask); | |
1221 | } | |
1222 | /* skip the flush */ | |
1223 | } | |
1224 | ||
021230d4 AV |
1225 | /** |
1226 | * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine | |
1227 | * @napi: napi struct with our devices info in it | |
1228 | * @budget: amount of work driver is allowed to do this pass, in packets | |
1229 | * | |
f0848276 JB |
1230 | * This function is optimized for cleaning one queue only on a single |
1231 | * q_vector!!! | |
021230d4 | 1232 | **/ |
9a799d71 AK |
1233 | static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget) |
1234 | { | |
021230d4 | 1235 | struct ixgbe_q_vector *q_vector = |
b4617240 | 1236 | container_of(napi, struct ixgbe_q_vector, napi); |
021230d4 | 1237 | struct ixgbe_adapter *adapter = q_vector->adapter; |
f0848276 | 1238 | struct ixgbe_ring *rx_ring = NULL; |
9a799d71 | 1239 | int work_done = 0; |
021230d4 | 1240 | long r_idx; |
9a799d71 | 1241 | |
021230d4 | 1242 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); |
3a581073 | 1243 | rx_ring = &(adapter->rx_ring[r_idx]); |
5dd2d332 | 1244 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 1245 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) |
3a581073 | 1246 | ixgbe_update_rx_dca(adapter, rx_ring); |
bd0362dd | 1247 | #endif |
9a799d71 | 1248 | |
78b6f4ce | 1249 | ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget); |
9a799d71 | 1250 | |
021230d4 AV |
1251 | /* If all Rx work done, exit the polling mode */ |
1252 | if (work_done < budget) { | |
288379f0 | 1253 | napi_complete(napi); |
509ee935 | 1254 | if (adapter->itr_setting & 1) |
f494e8fa | 1255 | ixgbe_set_itr_msix(q_vector); |
9a799d71 | 1256 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
835462fc | 1257 | ixgbe_irq_enable_queues(adapter, rx_ring->v_idx); |
9a799d71 AK |
1258 | } |
1259 | ||
1260 | return work_done; | |
1261 | } | |
1262 | ||
f0848276 JB |
1263 | /** |
1264 | * ixgbe_clean_rxonly_many - msix (aka one shot) rx clean routine | |
1265 | * @napi: napi struct with our devices info in it | |
1266 | * @budget: amount of work driver is allowed to do this pass, in packets | |
1267 | * | |
1268 | * This function will clean more than one rx queue associated with a | |
1269 | * q_vector. | |
1270 | **/ | |
1271 | static int ixgbe_clean_rxonly_many(struct napi_struct *napi, int budget) | |
1272 | { | |
1273 | struct ixgbe_q_vector *q_vector = | |
1274 | container_of(napi, struct ixgbe_q_vector, napi); | |
1275 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
f0848276 JB |
1276 | struct ixgbe_ring *rx_ring = NULL; |
1277 | int work_done = 0, i; | |
1278 | long r_idx; | |
835462fc | 1279 | u64 enable_mask = 0; |
f0848276 JB |
1280 | |
1281 | /* attempt to distribute budget to each queue fairly, but don't allow | |
1282 | * the budget to go below 1 because we'll exit polling */ | |
1283 | budget /= (q_vector->rxr_count ?: 1); | |
1284 | budget = max(budget, 1); | |
1285 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
1286 | for (i = 0; i < q_vector->rxr_count; i++) { | |
1287 | rx_ring = &(adapter->rx_ring[r_idx]); | |
5dd2d332 | 1288 | #ifdef CONFIG_IXGBE_DCA |
f0848276 JB |
1289 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) |
1290 | ixgbe_update_rx_dca(adapter, rx_ring); | |
1291 | #endif | |
78b6f4ce | 1292 | ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget); |
f0848276 JB |
1293 | enable_mask |= rx_ring->v_idx; |
1294 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, | |
1295 | r_idx + 1); | |
1296 | } | |
1297 | ||
1298 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
1299 | rx_ring = &(adapter->rx_ring[r_idx]); | |
1300 | /* If all Rx work done, exit the polling mode */ | |
7f821875 | 1301 | if (work_done < budget) { |
288379f0 | 1302 | napi_complete(napi); |
509ee935 | 1303 | if (adapter->itr_setting & 1) |
f0848276 JB |
1304 | ixgbe_set_itr_msix(q_vector); |
1305 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
835462fc | 1306 | ixgbe_irq_enable_queues(adapter, enable_mask); |
f0848276 JB |
1307 | return 0; |
1308 | } | |
1309 | ||
1310 | return work_done; | |
1311 | } | |
021230d4 | 1312 | static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx, |
b4617240 | 1313 | int r_idx) |
021230d4 | 1314 | { |
7a921c93 AD |
1315 | struct ixgbe_q_vector *q_vector = a->q_vector[v_idx]; |
1316 | ||
1317 | set_bit(r_idx, q_vector->rxr_idx); | |
1318 | q_vector->rxr_count++; | |
c9c7d2e5 | 1319 | a->rx_ring[r_idx].v_idx = (u64)1 << v_idx; |
021230d4 AV |
1320 | } |
1321 | ||
1322 | static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx, | |
7a921c93 | 1323 | int t_idx) |
021230d4 | 1324 | { |
7a921c93 AD |
1325 | struct ixgbe_q_vector *q_vector = a->q_vector[v_idx]; |
1326 | ||
1327 | set_bit(t_idx, q_vector->txr_idx); | |
1328 | q_vector->txr_count++; | |
c9c7d2e5 | 1329 | a->tx_ring[t_idx].v_idx = (u64)1 << v_idx; |
021230d4 AV |
1330 | } |
1331 | ||
9a799d71 | 1332 | /** |
021230d4 AV |
1333 | * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors |
1334 | * @adapter: board private structure to initialize | |
1335 | * @vectors: allotted vector count for descriptor rings | |
9a799d71 | 1336 | * |
021230d4 AV |
1337 | * This function maps descriptor rings to the queue-specific vectors |
1338 | * we were allotted through the MSI-X enabling code. Ideally, we'd have | |
1339 | * one vector per ring/queue, but on a constrained vector budget, we | |
1340 | * group the rings as "efficiently" as possible. You would add new | |
1341 | * mapping configurations in here. | |
9a799d71 | 1342 | **/ |
021230d4 | 1343 | static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter, |
b4617240 | 1344 | int vectors) |
021230d4 AV |
1345 | { |
1346 | int v_start = 0; | |
1347 | int rxr_idx = 0, txr_idx = 0; | |
1348 | int rxr_remaining = adapter->num_rx_queues; | |
1349 | int txr_remaining = adapter->num_tx_queues; | |
1350 | int i, j; | |
1351 | int rqpv, tqpv; | |
1352 | int err = 0; | |
1353 | ||
1354 | /* No mapping required if MSI-X is disabled. */ | |
1355 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
1356 | goto out; | |
9a799d71 | 1357 | |
021230d4 AV |
1358 | /* |
1359 | * The ideal configuration... | |
1360 | * We have enough vectors to map one per queue. | |
1361 | */ | |
1362 | if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) { | |
1363 | for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++) | |
1364 | map_vector_to_rxq(adapter, v_start, rxr_idx); | |
9a799d71 | 1365 | |
021230d4 AV |
1366 | for (; txr_idx < txr_remaining; v_start++, txr_idx++) |
1367 | map_vector_to_txq(adapter, v_start, txr_idx); | |
9a799d71 | 1368 | |
9a799d71 | 1369 | goto out; |
021230d4 | 1370 | } |
9a799d71 | 1371 | |
021230d4 AV |
1372 | /* |
1373 | * If we don't have enough vectors for a 1-to-1 | |
1374 | * mapping, we'll have to group them so there are | |
1375 | * multiple queues per vector. | |
1376 | */ | |
1377 | /* Re-adjusting *qpv takes care of the remainder. */ | |
1378 | for (i = v_start; i < vectors; i++) { | |
1379 | rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i); | |
1380 | for (j = 0; j < rqpv; j++) { | |
1381 | map_vector_to_rxq(adapter, i, rxr_idx); | |
1382 | rxr_idx++; | |
1383 | rxr_remaining--; | |
1384 | } | |
1385 | } | |
1386 | for (i = v_start; i < vectors; i++) { | |
1387 | tqpv = DIV_ROUND_UP(txr_remaining, vectors - i); | |
1388 | for (j = 0; j < tqpv; j++) { | |
1389 | map_vector_to_txq(adapter, i, txr_idx); | |
1390 | txr_idx++; | |
1391 | txr_remaining--; | |
9a799d71 | 1392 | } |
9a799d71 AK |
1393 | } |
1394 | ||
021230d4 AV |
1395 | out: |
1396 | return err; | |
1397 | } | |
1398 | ||
1399 | /** | |
1400 | * ixgbe_request_msix_irqs - Initialize MSI-X interrupts | |
1401 | * @adapter: board private structure | |
1402 | * | |
1403 | * ixgbe_request_msix_irqs allocates MSI-X vectors and requests | |
1404 | * interrupts from the kernel. | |
1405 | **/ | |
1406 | static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter) | |
1407 | { | |
1408 | struct net_device *netdev = adapter->netdev; | |
1409 | irqreturn_t (*handler)(int, void *); | |
1410 | int i, vector, q_vectors, err; | |
cb13fc20 | 1411 | int ri=0, ti=0; |
021230d4 AV |
1412 | |
1413 | /* Decrement for Other and TCP Timer vectors */ | |
1414 | q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
1415 | ||
1416 | /* Map the Tx/Rx rings to the vectors we were allotted. */ | |
1417 | err = ixgbe_map_rings_to_vectors(adapter, q_vectors); | |
1418 | if (err) | |
1419 | goto out; | |
1420 | ||
1421 | #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \ | |
b4617240 PW |
1422 | (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \ |
1423 | &ixgbe_msix_clean_many) | |
021230d4 | 1424 | for (vector = 0; vector < q_vectors; vector++) { |
7a921c93 | 1425 | handler = SET_HANDLER(adapter->q_vector[vector]); |
cb13fc20 RO |
1426 | |
1427 | if(handler == &ixgbe_msix_clean_rx) { | |
1428 | sprintf(adapter->name[vector], "%s-%s-%d", | |
1429 | netdev->name, "rx", ri++); | |
1430 | } | |
1431 | else if(handler == &ixgbe_msix_clean_tx) { | |
1432 | sprintf(adapter->name[vector], "%s-%s-%d", | |
1433 | netdev->name, "tx", ti++); | |
1434 | } | |
1435 | else | |
1436 | sprintf(adapter->name[vector], "%s-%s-%d", | |
1437 | netdev->name, "TxRx", vector); | |
1438 | ||
021230d4 | 1439 | err = request_irq(adapter->msix_entries[vector].vector, |
b4617240 | 1440 | handler, 0, adapter->name[vector], |
7a921c93 | 1441 | adapter->q_vector[vector]); |
9a799d71 AK |
1442 | if (err) { |
1443 | DPRINTK(PROBE, ERR, | |
b4617240 PW |
1444 | "request_irq failed for MSIX interrupt " |
1445 | "Error: %d\n", err); | |
021230d4 | 1446 | goto free_queue_irqs; |
9a799d71 | 1447 | } |
9a799d71 AK |
1448 | } |
1449 | ||
021230d4 AV |
1450 | sprintf(adapter->name[vector], "%s:lsc", netdev->name); |
1451 | err = request_irq(adapter->msix_entries[vector].vector, | |
b4617240 | 1452 | &ixgbe_msix_lsc, 0, adapter->name[vector], netdev); |
9a799d71 AK |
1453 | if (err) { |
1454 | DPRINTK(PROBE, ERR, | |
1455 | "request_irq for msix_lsc failed: %d\n", err); | |
021230d4 | 1456 | goto free_queue_irqs; |
9a799d71 AK |
1457 | } |
1458 | ||
9a799d71 AK |
1459 | return 0; |
1460 | ||
021230d4 AV |
1461 | free_queue_irqs: |
1462 | for (i = vector - 1; i >= 0; i--) | |
1463 | free_irq(adapter->msix_entries[--vector].vector, | |
7a921c93 | 1464 | adapter->q_vector[i]); |
021230d4 AV |
1465 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; |
1466 | pci_disable_msix(adapter->pdev); | |
9a799d71 AK |
1467 | kfree(adapter->msix_entries); |
1468 | adapter->msix_entries = NULL; | |
021230d4 | 1469 | out: |
9a799d71 AK |
1470 | return err; |
1471 | } | |
1472 | ||
f494e8fa AV |
1473 | static void ixgbe_set_itr(struct ixgbe_adapter *adapter) |
1474 | { | |
7a921c93 | 1475 | struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; |
f494e8fa AV |
1476 | u8 current_itr; |
1477 | u32 new_itr = q_vector->eitr; | |
1478 | struct ixgbe_ring *rx_ring = &adapter->rx_ring[0]; | |
1479 | struct ixgbe_ring *tx_ring = &adapter->tx_ring[0]; | |
1480 | ||
30efa5a3 | 1481 | q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr, |
b4617240 PW |
1482 | q_vector->tx_itr, |
1483 | tx_ring->total_packets, | |
1484 | tx_ring->total_bytes); | |
30efa5a3 | 1485 | q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr, |
b4617240 PW |
1486 | q_vector->rx_itr, |
1487 | rx_ring->total_packets, | |
1488 | rx_ring->total_bytes); | |
f494e8fa | 1489 | |
30efa5a3 | 1490 | current_itr = max(q_vector->rx_itr, q_vector->tx_itr); |
f494e8fa AV |
1491 | |
1492 | switch (current_itr) { | |
1493 | /* counts and packets in update_itr are dependent on these numbers */ | |
1494 | case lowest_latency: | |
1495 | new_itr = 100000; | |
1496 | break; | |
1497 | case low_latency: | |
1498 | new_itr = 20000; /* aka hwitr = ~200 */ | |
1499 | break; | |
1500 | case bulk_latency: | |
1501 | new_itr = 8000; | |
1502 | break; | |
1503 | default: | |
1504 | break; | |
1505 | } | |
1506 | ||
1507 | if (new_itr != q_vector->eitr) { | |
1508 | u32 itr_reg; | |
509ee935 JB |
1509 | |
1510 | /* save the algorithm value here, not the smoothed one */ | |
1511 | q_vector->eitr = new_itr; | |
f494e8fa AV |
1512 | /* do an exponential smoothing */ |
1513 | new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100); | |
f494e8fa | 1514 | itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr); |
509ee935 | 1515 | ixgbe_write_eitr(adapter, 0, itr_reg); |
f494e8fa AV |
1516 | } |
1517 | ||
1518 | return; | |
1519 | } | |
1520 | ||
79aefa45 AD |
1521 | /** |
1522 | * ixgbe_irq_enable - Enable default interrupt generation settings | |
1523 | * @adapter: board private structure | |
1524 | **/ | |
1525 | static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter) | |
1526 | { | |
1527 | u32 mask; | |
835462fc NS |
1528 | |
1529 | mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE); | |
6ab33d51 DM |
1530 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) |
1531 | mask |= IXGBE_EIMS_GPI_SDP1; | |
e8e26350 | 1532 | if (adapter->hw.mac.type == ixgbe_mac_82599EB) { |
2a41ff81 | 1533 | mask |= IXGBE_EIMS_ECC; |
e8e26350 PW |
1534 | mask |= IXGBE_EIMS_GPI_SDP1; |
1535 | mask |= IXGBE_EIMS_GPI_SDP2; | |
1536 | } | |
1537 | ||
79aefa45 | 1538 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); |
835462fc | 1539 | ixgbe_irq_enable_queues(adapter, ~0); |
79aefa45 AD |
1540 | IXGBE_WRITE_FLUSH(&adapter->hw); |
1541 | } | |
021230d4 | 1542 | |
9a799d71 | 1543 | /** |
021230d4 | 1544 | * ixgbe_intr - legacy mode Interrupt Handler |
9a799d71 AK |
1545 | * @irq: interrupt number |
1546 | * @data: pointer to a network interface device structure | |
9a799d71 AK |
1547 | **/ |
1548 | static irqreturn_t ixgbe_intr(int irq, void *data) | |
1549 | { | |
1550 | struct net_device *netdev = data; | |
1551 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
1552 | struct ixgbe_hw *hw = &adapter->hw; | |
7a921c93 | 1553 | struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; |
9a799d71 AK |
1554 | u32 eicr; |
1555 | ||
54037505 DS |
1556 | /* |
1557 | * Workaround for silicon errata. Mask the interrupts | |
1558 | * before the read of EICR. | |
1559 | */ | |
1560 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); | |
1561 | ||
021230d4 AV |
1562 | /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read |
1563 | * therefore no explict interrupt disable is necessary */ | |
1564 | eicr = IXGBE_READ_REG(hw, IXGBE_EICR); | |
f47cf66e JB |
1565 | if (!eicr) { |
1566 | /* shared interrupt alert! | |
1567 | * make sure interrupts are enabled because the read will | |
1568 | * have disabled interrupts due to EIAM */ | |
1569 | ixgbe_irq_enable(adapter); | |
9a799d71 | 1570 | return IRQ_NONE; /* Not our interrupt */ |
f47cf66e | 1571 | } |
9a799d71 | 1572 | |
cf8280ee JB |
1573 | if (eicr & IXGBE_EICR_LSC) |
1574 | ixgbe_check_lsc(adapter); | |
021230d4 | 1575 | |
e8e26350 PW |
1576 | if (hw->mac.type == ixgbe_mac_82599EB) |
1577 | ixgbe_check_sfp_event(adapter, eicr); | |
1578 | ||
0befdb3e JB |
1579 | ixgbe_check_fan_failure(adapter, eicr); |
1580 | ||
7a921c93 | 1581 | if (napi_schedule_prep(&(q_vector->napi))) { |
f494e8fa AV |
1582 | adapter->tx_ring[0].total_packets = 0; |
1583 | adapter->tx_ring[0].total_bytes = 0; | |
1584 | adapter->rx_ring[0].total_packets = 0; | |
1585 | adapter->rx_ring[0].total_bytes = 0; | |
021230d4 | 1586 | /* would disable interrupts here but EIAM disabled it */ |
7a921c93 | 1587 | __napi_schedule(&(q_vector->napi)); |
9a799d71 AK |
1588 | } |
1589 | ||
1590 | return IRQ_HANDLED; | |
1591 | } | |
1592 | ||
021230d4 AV |
1593 | static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter) |
1594 | { | |
1595 | int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
1596 | ||
1597 | for (i = 0; i < q_vectors; i++) { | |
7a921c93 | 1598 | struct ixgbe_q_vector *q_vector = adapter->q_vector[i]; |
021230d4 AV |
1599 | bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES); |
1600 | bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES); | |
1601 | q_vector->rxr_count = 0; | |
1602 | q_vector->txr_count = 0; | |
1603 | } | |
1604 | } | |
1605 | ||
9a799d71 AK |
1606 | /** |
1607 | * ixgbe_request_irq - initialize interrupts | |
1608 | * @adapter: board private structure | |
1609 | * | |
1610 | * Attempts to configure interrupts using the best available | |
1611 | * capabilities of the hardware and kernel. | |
1612 | **/ | |
021230d4 | 1613 | static int ixgbe_request_irq(struct ixgbe_adapter *adapter) |
9a799d71 AK |
1614 | { |
1615 | struct net_device *netdev = adapter->netdev; | |
021230d4 | 1616 | int err; |
9a799d71 | 1617 | |
021230d4 AV |
1618 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
1619 | err = ixgbe_request_msix_irqs(adapter); | |
1620 | } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) { | |
1621 | err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0, | |
b4617240 | 1622 | netdev->name, netdev); |
021230d4 AV |
1623 | } else { |
1624 | err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED, | |
b4617240 | 1625 | netdev->name, netdev); |
9a799d71 AK |
1626 | } |
1627 | ||
9a799d71 AK |
1628 | if (err) |
1629 | DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err); | |
1630 | ||
9a799d71 AK |
1631 | return err; |
1632 | } | |
1633 | ||
1634 | static void ixgbe_free_irq(struct ixgbe_adapter *adapter) | |
1635 | { | |
1636 | struct net_device *netdev = adapter->netdev; | |
1637 | ||
1638 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
021230d4 | 1639 | int i, q_vectors; |
9a799d71 | 1640 | |
021230d4 AV |
1641 | q_vectors = adapter->num_msix_vectors; |
1642 | ||
1643 | i = q_vectors - 1; | |
9a799d71 | 1644 | free_irq(adapter->msix_entries[i].vector, netdev); |
9a799d71 | 1645 | |
021230d4 AV |
1646 | i--; |
1647 | for (; i >= 0; i--) { | |
1648 | free_irq(adapter->msix_entries[i].vector, | |
7a921c93 | 1649 | adapter->q_vector[i]); |
021230d4 AV |
1650 | } |
1651 | ||
1652 | ixgbe_reset_q_vectors(adapter); | |
1653 | } else { | |
1654 | free_irq(adapter->pdev->irq, netdev); | |
9a799d71 AK |
1655 | } |
1656 | } | |
1657 | ||
22d5a71b JB |
1658 | /** |
1659 | * ixgbe_irq_disable - Mask off interrupt generation on the NIC | |
1660 | * @adapter: board private structure | |
1661 | **/ | |
1662 | static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) | |
1663 | { | |
835462fc NS |
1664 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
1665 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); | |
1666 | } else { | |
1667 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000); | |
1668 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0); | |
22d5a71b | 1669 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0); |
22d5a71b JB |
1670 | } |
1671 | IXGBE_WRITE_FLUSH(&adapter->hw); | |
1672 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
1673 | int i; | |
1674 | for (i = 0; i < adapter->num_msix_vectors; i++) | |
1675 | synchronize_irq(adapter->msix_entries[i].vector); | |
1676 | } else { | |
1677 | synchronize_irq(adapter->pdev->irq); | |
1678 | } | |
1679 | } | |
1680 | ||
9a799d71 AK |
1681 | /** |
1682 | * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts | |
1683 | * | |
1684 | **/ | |
1685 | static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter) | |
1686 | { | |
9a799d71 AK |
1687 | struct ixgbe_hw *hw = &adapter->hw; |
1688 | ||
021230d4 | 1689 | IXGBE_WRITE_REG(hw, IXGBE_EITR(0), |
30efa5a3 | 1690 | EITR_INTS_PER_SEC_TO_REG(adapter->eitr_param)); |
9a799d71 | 1691 | |
e8e26350 PW |
1692 | ixgbe_set_ivar(adapter, 0, 0, 0); |
1693 | ixgbe_set_ivar(adapter, 1, 0, 0); | |
021230d4 AV |
1694 | |
1695 | map_vector_to_rxq(adapter, 0, 0); | |
1696 | map_vector_to_txq(adapter, 0, 0); | |
1697 | ||
1698 | DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n"); | |
9a799d71 AK |
1699 | } |
1700 | ||
1701 | /** | |
3a581073 | 1702 | * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset |
9a799d71 AK |
1703 | * @adapter: board private structure |
1704 | * | |
1705 | * Configure the Tx unit of the MAC after a reset. | |
1706 | **/ | |
1707 | static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) | |
1708 | { | |
12207e49 | 1709 | u64 tdba; |
9a799d71 | 1710 | struct ixgbe_hw *hw = &adapter->hw; |
021230d4 | 1711 | u32 i, j, tdlen, txctrl; |
9a799d71 AK |
1712 | |
1713 | /* Setup the HW Tx Head and Tail descriptor pointers */ | |
1714 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
e01c31a5 JB |
1715 | struct ixgbe_ring *ring = &adapter->tx_ring[i]; |
1716 | j = ring->reg_idx; | |
1717 | tdba = ring->dma; | |
1718 | tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc); | |
021230d4 | 1719 | IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j), |
284901a9 | 1720 | (tdba & DMA_BIT_MASK(32))); |
021230d4 AV |
1721 | IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32)); |
1722 | IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen); | |
1723 | IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0); | |
1724 | IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0); | |
1725 | adapter->tx_ring[i].head = IXGBE_TDH(j); | |
1726 | adapter->tx_ring[i].tail = IXGBE_TDT(j); | |
1727 | /* Disable Tx Head Writeback RO bit, since this hoses | |
1728 | * bookkeeping if things aren't delivered in order. | |
1729 | */ | |
e01c31a5 | 1730 | txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j)); |
021230d4 | 1731 | txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN; |
e01c31a5 | 1732 | IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl); |
9a799d71 | 1733 | } |
e8e26350 PW |
1734 | if (hw->mac.type == ixgbe_mac_82599EB) { |
1735 | /* We enable 8 traffic classes, DCB only */ | |
1736 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) | |
1737 | IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA | | |
1738 | IXGBE_MTQC_8TC_8TQ)); | |
1739 | } | |
9a799d71 AK |
1740 | } |
1741 | ||
e8e26350 | 1742 | #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 |
cc41ac7c JB |
1743 | |
1744 | static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, int index) | |
1745 | { | |
1746 | struct ixgbe_ring *rx_ring; | |
1747 | u32 srrctl; | |
e8e26350 | 1748 | int queue0 = 0; |
3be1adfb | 1749 | unsigned long mask; |
0cefafad | 1750 | struct ixgbe_ring_feature *feature = adapter->ring_feature; |
3be1adfb | 1751 | |
e8e26350 | 1752 | if (adapter->hw.mac.type == ixgbe_mac_82599EB) { |
163de42e | 1753 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { |
0cefafad | 1754 | int dcb_i = feature[RING_F_DCB].indices; |
163de42e AD |
1755 | if (dcb_i == 8) |
1756 | queue0 = index >> 4; | |
1757 | else if (dcb_i == 4) | |
1758 | queue0 = index >> 5; | |
1759 | else | |
1760 | dev_err(&adapter->pdev->dev, "Invalid DCB " | |
1761 | "configuration\n"); | |
0331a832 YZ |
1762 | #ifdef IXGBE_FCOE |
1763 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { | |
1764 | struct ixgbe_ring_feature *f; | |
1765 | ||
1766 | rx_ring = &adapter->rx_ring[queue0]; | |
1767 | f = &adapter->ring_feature[RING_F_FCOE]; | |
1768 | if ((queue0 == 0) && (index > rx_ring->reg_idx)) | |
1769 | queue0 = f->mask + index - | |
1770 | rx_ring->reg_idx - 1; | |
1771 | } | |
1772 | #endif /* IXGBE_FCOE */ | |
163de42e AD |
1773 | } else { |
1774 | queue0 = index; | |
1775 | } | |
cc41ac7c | 1776 | } else { |
0cefafad | 1777 | mask = (unsigned long) feature[RING_F_RSS].mask; |
3be1adfb AD |
1778 | queue0 = index & mask; |
1779 | index = index & mask; | |
cc41ac7c | 1780 | } |
3be1adfb | 1781 | |
cc41ac7c JB |
1782 | rx_ring = &adapter->rx_ring[queue0]; |
1783 | ||
1784 | srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index)); | |
1785 | ||
1786 | srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK; | |
1787 | srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK; | |
1788 | ||
afafd5b0 AD |
1789 | srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) & |
1790 | IXGBE_SRRCTL_BSIZEHDR_MASK; | |
1791 | ||
cc41ac7c | 1792 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { |
afafd5b0 AD |
1793 | #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER |
1794 | srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
1795 | #else | |
1796 | srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
1797 | #endif | |
cc41ac7c | 1798 | srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS; |
cc41ac7c | 1799 | } else { |
afafd5b0 AD |
1800 | srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >> |
1801 | IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
cc41ac7c | 1802 | srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; |
cc41ac7c | 1803 | } |
e8e26350 | 1804 | |
cc41ac7c JB |
1805 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl); |
1806 | } | |
9a799d71 | 1807 | |
0cefafad JB |
1808 | static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter) |
1809 | { | |
1810 | u32 mrqc = 0; | |
1811 | int mask; | |
1812 | ||
1813 | if (!(adapter->hw.mac.type == ixgbe_mac_82599EB)) | |
1814 | return mrqc; | |
1815 | ||
1816 | mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED | |
1817 | #ifdef CONFIG_IXGBE_DCB | |
1818 | | IXGBE_FLAG_DCB_ENABLED | |
1819 | #endif | |
1820 | ); | |
1821 | ||
1822 | switch (mask) { | |
1823 | case (IXGBE_FLAG_RSS_ENABLED): | |
1824 | mrqc = IXGBE_MRQC_RSSEN; | |
1825 | break; | |
1826 | #ifdef CONFIG_IXGBE_DCB | |
1827 | case (IXGBE_FLAG_DCB_ENABLED): | |
1828 | mrqc = IXGBE_MRQC_RT8TCEN; | |
1829 | break; | |
1830 | #endif /* CONFIG_IXGBE_DCB */ | |
1831 | default: | |
1832 | break; | |
1833 | } | |
1834 | ||
1835 | return mrqc; | |
1836 | } | |
1837 | ||
9a799d71 | 1838 | /** |
3a581073 | 1839 | * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset |
9a799d71 AK |
1840 | * @adapter: board private structure |
1841 | * | |
1842 | * Configure the Rx unit of the MAC after a reset. | |
1843 | **/ | |
1844 | static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) | |
1845 | { | |
1846 | u64 rdba; | |
1847 | struct ixgbe_hw *hw = &adapter->hw; | |
1848 | struct net_device *netdev = adapter->netdev; | |
1849 | int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; | |
021230d4 | 1850 | int i, j; |
9a799d71 | 1851 | u32 rdlen, rxctrl, rxcsum; |
7c6e0a43 JB |
1852 | static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D, |
1853 | 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE, | |
1854 | 0x6A3E67EA, 0x14364D17, 0x3BED200D}; | |
9a799d71 | 1855 | u32 fctrl, hlreg0; |
509ee935 | 1856 | u32 reta = 0, mrqc = 0; |
cc41ac7c | 1857 | u32 rdrxctl; |
f8212f97 | 1858 | u32 rscctrl; |
7c6e0a43 | 1859 | int rx_buf_len; |
9a799d71 AK |
1860 | |
1861 | /* Decide whether to use packet split mode or not */ | |
762f4c57 | 1862 | adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED; |
9a799d71 | 1863 | |
eacd73f7 YZ |
1864 | #ifdef IXGBE_FCOE |
1865 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) | |
1866 | adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED; | |
1867 | #endif /* IXGBE_FCOE */ | |
1868 | ||
9a799d71 AK |
1869 | /* Set the RX buffer length according to the mode */ |
1870 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { | |
7c6e0a43 | 1871 | rx_buf_len = IXGBE_RX_HDR_SIZE; |
e8e26350 PW |
1872 | if (hw->mac.type == ixgbe_mac_82599EB) { |
1873 | /* PSRTYPE must be initialized in 82599 */ | |
1874 | u32 psrtype = IXGBE_PSRTYPE_TCPHDR | | |
1875 | IXGBE_PSRTYPE_UDPHDR | | |
1876 | IXGBE_PSRTYPE_IPV4HDR | | |
dfa12f05 YZ |
1877 | IXGBE_PSRTYPE_IPV6HDR | |
1878 | IXGBE_PSRTYPE_L2HDR; | |
e8e26350 PW |
1879 | IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype); |
1880 | } | |
9a799d71 | 1881 | } else { |
f8212f97 AD |
1882 | if (!(adapter->flags & IXGBE_FLAG_RSC_ENABLED) && |
1883 | (netdev->mtu <= ETH_DATA_LEN)) | |
7c6e0a43 | 1884 | rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE; |
9a799d71 | 1885 | else |
7c6e0a43 | 1886 | rx_buf_len = ALIGN(max_frame, 1024); |
9a799d71 AK |
1887 | } |
1888 | ||
1889 | fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL); | |
1890 | fctrl |= IXGBE_FCTRL_BAM; | |
021230d4 | 1891 | fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */ |
e8e26350 | 1892 | fctrl |= IXGBE_FCTRL_PMCF; |
9a799d71 AK |
1893 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl); |
1894 | ||
1895 | hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); | |
1896 | if (adapter->netdev->mtu <= ETH_DATA_LEN) | |
1897 | hlreg0 &= ~IXGBE_HLREG0_JUMBOEN; | |
1898 | else | |
1899 | hlreg0 |= IXGBE_HLREG0_JUMBOEN; | |
63f39bd1 YZ |
1900 | #ifdef IXGBE_FCOE |
1901 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) | |
1902 | hlreg0 |= IXGBE_HLREG0_JUMBOEN; | |
1903 | #endif | |
9a799d71 AK |
1904 | IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); |
1905 | ||
9a799d71 AK |
1906 | rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc); |
1907 | /* disable receives while setting up the descriptors */ | |
1908 | rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); | |
1909 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); | |
1910 | ||
0cefafad JB |
1911 | /* |
1912 | * Setup the HW Rx Head and Tail Descriptor Pointers and | |
1913 | * the Base and Length of the Rx Descriptor Ring | |
1914 | */ | |
9a799d71 AK |
1915 | for (i = 0; i < adapter->num_rx_queues; i++) { |
1916 | rdba = adapter->rx_ring[i].dma; | |
7c6e0a43 | 1917 | j = adapter->rx_ring[i].reg_idx; |
284901a9 | 1918 | IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32))); |
7c6e0a43 JB |
1919 | IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32)); |
1920 | IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen); | |
1921 | IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0); | |
1922 | IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0); | |
1923 | adapter->rx_ring[i].head = IXGBE_RDH(j); | |
1924 | adapter->rx_ring[i].tail = IXGBE_RDT(j); | |
1925 | adapter->rx_ring[i].rx_buf_len = rx_buf_len; | |
cc41ac7c | 1926 | |
63f39bd1 YZ |
1927 | #ifdef IXGBE_FCOE |
1928 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { | |
1929 | struct ixgbe_ring_feature *f; | |
1930 | f = &adapter->ring_feature[RING_F_FCOE]; | |
1931 | if ((rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE) && | |
1932 | (i >= f->mask) && (i < f->mask + f->indices)) | |
1933 | adapter->rx_ring[i].rx_buf_len = | |
1934 | IXGBE_FCOE_JUMBO_FRAME_SIZE; | |
1935 | } | |
1936 | ||
1937 | #endif /* IXGBE_FCOE */ | |
cc41ac7c | 1938 | ixgbe_configure_srrctl(adapter, j); |
9a799d71 AK |
1939 | } |
1940 | ||
e8e26350 PW |
1941 | if (hw->mac.type == ixgbe_mac_82598EB) { |
1942 | /* | |
1943 | * For VMDq support of different descriptor types or | |
1944 | * buffer sizes through the use of multiple SRRCTL | |
1945 | * registers, RDRXCTL.MVMEN must be set to 1 | |
1946 | * | |
1947 | * also, the manual doesn't mention it clearly but DCA hints | |
1948 | * will only use queue 0's tags unless this bit is set. Side | |
1949 | * effects of setting this bit are only that SRRCTL must be | |
1950 | * fully programmed [0..15] | |
1951 | */ | |
2a41ff81 JB |
1952 | rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); |
1953 | rdrxctl |= IXGBE_RDRXCTL_MVMEN; | |
1954 | IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); | |
2f90b865 | 1955 | } |
177db6ff | 1956 | |
e8e26350 | 1957 | /* Program MRQC for the distribution of queues */ |
0cefafad | 1958 | mrqc = ixgbe_setup_mrqc(adapter); |
e8e26350 | 1959 | |
021230d4 | 1960 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { |
9a799d71 | 1961 | /* Fill out redirection table */ |
021230d4 AV |
1962 | for (i = 0, j = 0; i < 128; i++, j++) { |
1963 | if (j == adapter->ring_feature[RING_F_RSS].indices) | |
1964 | j = 0; | |
1965 | /* reta = 4-byte sliding window of | |
1966 | * 0x00..(indices-1)(indices-1)00..etc. */ | |
1967 | reta = (reta << 8) | (j * 0x11); | |
1968 | if ((i & 3) == 3) | |
1969 | IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); | |
9a799d71 AK |
1970 | } |
1971 | ||
1972 | /* Fill out hash function seeds */ | |
1973 | for (i = 0; i < 10; i++) | |
7c6e0a43 | 1974 | IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]); |
9a799d71 | 1975 | |
2a41ff81 JB |
1976 | if (hw->mac.type == ixgbe_mac_82598EB) |
1977 | mrqc |= IXGBE_MRQC_RSSEN; | |
9a799d71 | 1978 | /* Perform hash on these packet types */ |
2a41ff81 JB |
1979 | mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 |
1980 | | IXGBE_MRQC_RSS_FIELD_IPV4_TCP | |
1981 | | IXGBE_MRQC_RSS_FIELD_IPV4_UDP | |
1982 | | IXGBE_MRQC_RSS_FIELD_IPV6 | |
1983 | | IXGBE_MRQC_RSS_FIELD_IPV6_TCP | |
1984 | | IXGBE_MRQC_RSS_FIELD_IPV6_UDP; | |
021230d4 | 1985 | } |
2a41ff81 | 1986 | IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); |
9a799d71 | 1987 | |
021230d4 AV |
1988 | rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); |
1989 | ||
1990 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED || | |
1991 | adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) { | |
1992 | /* Disable indicating checksum in descriptor, enables | |
1993 | * RSS hash */ | |
9a799d71 | 1994 | rxcsum |= IXGBE_RXCSUM_PCSD; |
9a799d71 | 1995 | } |
021230d4 AV |
1996 | if (!(rxcsum & IXGBE_RXCSUM_PCSD)) { |
1997 | /* Enable IPv4 payload checksum for UDP fragments | |
1998 | * if PCSD is not set */ | |
1999 | rxcsum |= IXGBE_RXCSUM_IPPCSE; | |
2000 | } | |
2001 | ||
2002 | IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); | |
e8e26350 PW |
2003 | |
2004 | if (hw->mac.type == ixgbe_mac_82599EB) { | |
2005 | rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); | |
2006 | rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP; | |
f8212f97 | 2007 | rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE; |
e8e26350 PW |
2008 | IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); |
2009 | } | |
f8212f97 AD |
2010 | |
2011 | if (adapter->flags & IXGBE_FLAG_RSC_ENABLED) { | |
2012 | /* Enable 82599 HW-RSC */ | |
2013 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
2014 | j = adapter->rx_ring[i].reg_idx; | |
2015 | rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j)); | |
2016 | rscctrl |= IXGBE_RSCCTL_RSCEN; | |
2017 | /* | |
e76678dd AD |
2018 | * we must limit the number of descriptors so that the |
2019 | * total size of max desc * buf_len is not greater | |
2020 | * than 65535 | |
f8212f97 | 2021 | */ |
e76678dd AD |
2022 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { |
2023 | #if (MAX_SKB_FRAGS > 16) | |
2024 | rscctrl |= IXGBE_RSCCTL_MAXDESC_16; | |
2025 | #elif (MAX_SKB_FRAGS > 8) | |
f8212f97 | 2026 | rscctrl |= IXGBE_RSCCTL_MAXDESC_8; |
e76678dd AD |
2027 | #elif (MAX_SKB_FRAGS > 4) |
2028 | rscctrl |= IXGBE_RSCCTL_MAXDESC_4; | |
f8212f97 | 2029 | #else |
e76678dd | 2030 | rscctrl |= IXGBE_RSCCTL_MAXDESC_1; |
f8212f97 | 2031 | #endif |
e76678dd AD |
2032 | } else { |
2033 | if (rx_buf_len < IXGBE_RXBUFFER_4096) | |
2034 | rscctrl |= IXGBE_RSCCTL_MAXDESC_16; | |
2035 | else if (rx_buf_len < IXGBE_RXBUFFER_8192) | |
2036 | rscctrl |= IXGBE_RSCCTL_MAXDESC_8; | |
2037 | else | |
2038 | rscctrl |= IXGBE_RSCCTL_MAXDESC_4; | |
2039 | } | |
f8212f97 AD |
2040 | IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl); |
2041 | } | |
2042 | /* Disable RSC for ACK packets */ | |
2043 | IXGBE_WRITE_REG(hw, IXGBE_RSCDBU, | |
2044 | (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU))); | |
2045 | } | |
9a799d71 AK |
2046 | } |
2047 | ||
068c89b0 DS |
2048 | static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid) |
2049 | { | |
2050 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
2051 | struct ixgbe_hw *hw = &adapter->hw; | |
2052 | ||
2053 | /* add VID to filter table */ | |
2054 | hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true); | |
2055 | } | |
2056 | ||
2057 | static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) | |
2058 | { | |
2059 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
2060 | struct ixgbe_hw *hw = &adapter->hw; | |
2061 | ||
2062 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
2063 | ixgbe_irq_disable(adapter); | |
2064 | ||
2065 | vlan_group_set_device(adapter->vlgrp, vid, NULL); | |
2066 | ||
2067 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
2068 | ixgbe_irq_enable(adapter); | |
2069 | ||
2070 | /* remove VID from filter table */ | |
2071 | hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false); | |
2072 | } | |
2073 | ||
9a799d71 | 2074 | static void ixgbe_vlan_rx_register(struct net_device *netdev, |
b4617240 | 2075 | struct vlan_group *grp) |
9a799d71 AK |
2076 | { |
2077 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
2078 | u32 ctrl; | |
e8e26350 | 2079 | int i, j; |
9a799d71 | 2080 | |
d4f80882 AV |
2081 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
2082 | ixgbe_irq_disable(adapter); | |
9a799d71 AK |
2083 | adapter->vlgrp = grp; |
2084 | ||
2f90b865 AD |
2085 | /* |
2086 | * For a DCB driver, always enable VLAN tag stripping so we can | |
2087 | * still receive traffic from a DCB-enabled host even if we're | |
2088 | * not in DCB mode. | |
2089 | */ | |
2090 | ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL); | |
e8e26350 PW |
2091 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
2092 | ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE; | |
2093 | ctrl &= ~IXGBE_VLNCTRL_CFIEN; | |
2094 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl); | |
2095 | } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { | |
2096 | ctrl |= IXGBE_VLNCTRL_VFE; | |
9a799d71 AK |
2097 | /* enable VLAN tag insert/strip */ |
2098 | ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL); | |
9a799d71 AK |
2099 | ctrl &= ~IXGBE_VLNCTRL_CFIEN; |
2100 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl); | |
e8e26350 PW |
2101 | for (i = 0; i < adapter->num_rx_queues; i++) { |
2102 | j = adapter->rx_ring[i].reg_idx; | |
2103 | ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j)); | |
2104 | ctrl |= IXGBE_RXDCTL_VME; | |
2105 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl); | |
2106 | } | |
9a799d71 | 2107 | } |
e8e26350 | 2108 | ixgbe_vlan_rx_add_vid(netdev, 0); |
9a799d71 | 2109 | |
d4f80882 AV |
2110 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
2111 | ixgbe_irq_enable(adapter); | |
9a799d71 AK |
2112 | } |
2113 | ||
9a799d71 AK |
2114 | static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter) |
2115 | { | |
2116 | ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp); | |
2117 | ||
2118 | if (adapter->vlgrp) { | |
2119 | u16 vid; | |
2120 | for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) { | |
2121 | if (!vlan_group_get_device(adapter->vlgrp, vid)) | |
2122 | continue; | |
2123 | ixgbe_vlan_rx_add_vid(adapter->netdev, vid); | |
2124 | } | |
2125 | } | |
2126 | } | |
2127 | ||
2c5645cf CL |
2128 | static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq) |
2129 | { | |
2130 | struct dev_mc_list *mc_ptr; | |
2131 | u8 *addr = *mc_addr_ptr; | |
2132 | *vmdq = 0; | |
2133 | ||
2134 | mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]); | |
2135 | if (mc_ptr->next) | |
2136 | *mc_addr_ptr = mc_ptr->next->dmi_addr; | |
2137 | else | |
2138 | *mc_addr_ptr = NULL; | |
2139 | ||
2140 | return addr; | |
2141 | } | |
2142 | ||
9a799d71 | 2143 | /** |
2c5645cf | 2144 | * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set |
9a799d71 AK |
2145 | * @netdev: network interface device structure |
2146 | * | |
2c5645cf CL |
2147 | * The set_rx_method entry point is called whenever the unicast/multicast |
2148 | * address list or the network interface flags are updated. This routine is | |
2149 | * responsible for configuring the hardware for proper unicast, multicast and | |
2150 | * promiscuous mode. | |
9a799d71 | 2151 | **/ |
2c5645cf | 2152 | static void ixgbe_set_rx_mode(struct net_device *netdev) |
9a799d71 AK |
2153 | { |
2154 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
2155 | struct ixgbe_hw *hw = &adapter->hw; | |
3d01625a | 2156 | u32 fctrl, vlnctrl; |
2c5645cf CL |
2157 | u8 *addr_list = NULL; |
2158 | int addr_count = 0; | |
9a799d71 AK |
2159 | |
2160 | /* Check for Promiscuous and All Multicast modes */ | |
2161 | ||
2162 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
3d01625a | 2163 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); |
9a799d71 AK |
2164 | |
2165 | if (netdev->flags & IFF_PROMISC) { | |
2c5645cf | 2166 | hw->addr_ctrl.user_set_promisc = 1; |
9a799d71 | 2167 | fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); |
3d01625a | 2168 | vlnctrl &= ~IXGBE_VLNCTRL_VFE; |
9a799d71 | 2169 | } else { |
746b9f02 PM |
2170 | if (netdev->flags & IFF_ALLMULTI) { |
2171 | fctrl |= IXGBE_FCTRL_MPE; | |
2172 | fctrl &= ~IXGBE_FCTRL_UPE; | |
2173 | } else { | |
2174 | fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); | |
2175 | } | |
3d01625a | 2176 | vlnctrl |= IXGBE_VLNCTRL_VFE; |
2c5645cf | 2177 | hw->addr_ctrl.user_set_promisc = 0; |
9a799d71 AK |
2178 | } |
2179 | ||
2180 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); | |
3d01625a | 2181 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); |
9a799d71 | 2182 | |
2c5645cf | 2183 | /* reprogram secondary unicast list */ |
ccffad25 | 2184 | hw->mac.ops.update_uc_addr_list(hw, &netdev->uc_list); |
9a799d71 | 2185 | |
2c5645cf CL |
2186 | /* reprogram multicast list */ |
2187 | addr_count = netdev->mc_count; | |
2188 | if (addr_count) | |
2189 | addr_list = netdev->mc_list->dmi_addr; | |
c44ade9e JB |
2190 | hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count, |
2191 | ixgbe_addr_list_itr); | |
9a799d71 AK |
2192 | } |
2193 | ||
021230d4 AV |
2194 | static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter) |
2195 | { | |
2196 | int q_idx; | |
2197 | struct ixgbe_q_vector *q_vector; | |
2198 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
2199 | ||
2200 | /* legacy and MSI only use one vector */ | |
2201 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
2202 | q_vectors = 1; | |
2203 | ||
2204 | for (q_idx = 0; q_idx < q_vectors; q_idx++) { | |
f0848276 | 2205 | struct napi_struct *napi; |
7a921c93 | 2206 | q_vector = adapter->q_vector[q_idx]; |
021230d4 AV |
2207 | if (!q_vector->rxr_count) |
2208 | continue; | |
f0848276 JB |
2209 | napi = &q_vector->napi; |
2210 | if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) && | |
2211 | (q_vector->rxr_count > 1)) | |
2212 | napi->poll = &ixgbe_clean_rxonly_many; | |
2213 | ||
2214 | napi_enable(napi); | |
021230d4 AV |
2215 | } |
2216 | } | |
2217 | ||
2218 | static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter) | |
2219 | { | |
2220 | int q_idx; | |
2221 | struct ixgbe_q_vector *q_vector; | |
2222 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
2223 | ||
2224 | /* legacy and MSI only use one vector */ | |
2225 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
2226 | q_vectors = 1; | |
2227 | ||
2228 | for (q_idx = 0; q_idx < q_vectors; q_idx++) { | |
7a921c93 | 2229 | q_vector = adapter->q_vector[q_idx]; |
021230d4 AV |
2230 | if (!q_vector->rxr_count) |
2231 | continue; | |
2232 | napi_disable(&q_vector->napi); | |
2233 | } | |
2234 | } | |
2235 | ||
7a6b6f51 | 2236 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
2237 | /* |
2238 | * ixgbe_configure_dcb - Configure DCB hardware | |
2239 | * @adapter: ixgbe adapter struct | |
2240 | * | |
2241 | * This is called by the driver on open to configure the DCB hardware. | |
2242 | * This is also called by the gennetlink interface when reconfiguring | |
2243 | * the DCB state. | |
2244 | */ | |
2245 | static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter) | |
2246 | { | |
2247 | struct ixgbe_hw *hw = &adapter->hw; | |
2248 | u32 txdctl, vlnctrl; | |
2249 | int i, j; | |
2250 | ||
2251 | ixgbe_dcb_check_config(&adapter->dcb_cfg); | |
2252 | ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG); | |
2253 | ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG); | |
2254 | ||
2255 | /* reconfigure the hardware */ | |
2256 | ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg); | |
2257 | ||
2258 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
2259 | j = adapter->tx_ring[i].reg_idx; | |
2260 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)); | |
2261 | /* PThresh workaround for Tx hang with DFP enabled. */ | |
2262 | txdctl |= 32; | |
2263 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl); | |
2264 | } | |
2265 | /* Enable VLAN tag insert/strip */ | |
2266 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); | |
e8e26350 PW |
2267 | if (hw->mac.type == ixgbe_mac_82598EB) { |
2268 | vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE; | |
2269 | vlnctrl &= ~IXGBE_VLNCTRL_CFIEN; | |
2270 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); | |
2271 | } else if (hw->mac.type == ixgbe_mac_82599EB) { | |
2272 | vlnctrl |= IXGBE_VLNCTRL_VFE; | |
2273 | vlnctrl &= ~IXGBE_VLNCTRL_CFIEN; | |
2274 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); | |
2275 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
2276 | j = adapter->rx_ring[i].reg_idx; | |
2277 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); | |
2278 | vlnctrl |= IXGBE_RXDCTL_VME; | |
2279 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); | |
2280 | } | |
2281 | } | |
2f90b865 AD |
2282 | hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true); |
2283 | } | |
2284 | ||
2285 | #endif | |
9a799d71 AK |
2286 | static void ixgbe_configure(struct ixgbe_adapter *adapter) |
2287 | { | |
2288 | struct net_device *netdev = adapter->netdev; | |
2289 | int i; | |
2290 | ||
2c5645cf | 2291 | ixgbe_set_rx_mode(netdev); |
9a799d71 AK |
2292 | |
2293 | ixgbe_restore_vlan(adapter); | |
7a6b6f51 | 2294 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
2295 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { |
2296 | netif_set_gso_max_size(netdev, 32768); | |
2297 | ixgbe_configure_dcb(adapter); | |
2298 | } else { | |
2299 | netif_set_gso_max_size(netdev, 65536); | |
2300 | } | |
2301 | #else | |
2302 | netif_set_gso_max_size(netdev, 65536); | |
2303 | #endif | |
9a799d71 | 2304 | |
eacd73f7 YZ |
2305 | #ifdef IXGBE_FCOE |
2306 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) | |
2307 | ixgbe_configure_fcoe(adapter); | |
2308 | ||
2309 | #endif /* IXGBE_FCOE */ | |
9a799d71 AK |
2310 | ixgbe_configure_tx(adapter); |
2311 | ixgbe_configure_rx(adapter); | |
2312 | for (i = 0; i < adapter->num_rx_queues; i++) | |
2313 | ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i], | |
b4617240 | 2314 | (adapter->rx_ring[i].count - 1)); |
9a799d71 AK |
2315 | } |
2316 | ||
e8e26350 PW |
2317 | static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw) |
2318 | { | |
2319 | switch (hw->phy.type) { | |
2320 | case ixgbe_phy_sfp_avago: | |
2321 | case ixgbe_phy_sfp_ftl: | |
2322 | case ixgbe_phy_sfp_intel: | |
2323 | case ixgbe_phy_sfp_unknown: | |
2324 | case ixgbe_phy_tw_tyco: | |
2325 | case ixgbe_phy_tw_unknown: | |
2326 | return true; | |
2327 | default: | |
2328 | return false; | |
2329 | } | |
2330 | } | |
2331 | ||
0ecc061d | 2332 | /** |
e8e26350 PW |
2333 | * ixgbe_sfp_link_config - set up SFP+ link |
2334 | * @adapter: pointer to private adapter struct | |
2335 | **/ | |
2336 | static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter) | |
2337 | { | |
2338 | struct ixgbe_hw *hw = &adapter->hw; | |
2339 | ||
2340 | if (hw->phy.multispeed_fiber) { | |
2341 | /* | |
2342 | * In multispeed fiber setups, the device may not have | |
2343 | * had a physical connection when the driver loaded. | |
2344 | * If that's the case, the initial link configuration | |
2345 | * couldn't get the MAC into 10G or 1G mode, so we'll | |
2346 | * never have a link status change interrupt fire. | |
2347 | * We need to try and force an autonegotiation | |
2348 | * session, then bring up link. | |
2349 | */ | |
2350 | hw->mac.ops.setup_sfp(hw); | |
2351 | if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK)) | |
2352 | schedule_work(&adapter->multispeed_fiber_task); | |
2353 | } else { | |
2354 | /* | |
2355 | * Direct Attach Cu and non-multispeed fiber modules | |
2356 | * still need to be configured properly prior to | |
2357 | * attempting link. | |
2358 | */ | |
2359 | if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK)) | |
2360 | schedule_work(&adapter->sfp_config_module_task); | |
2361 | } | |
2362 | } | |
2363 | ||
2364 | /** | |
2365 | * ixgbe_non_sfp_link_config - set up non-SFP+ link | |
0ecc061d PWJ |
2366 | * @hw: pointer to private hardware struct |
2367 | * | |
2368 | * Returns 0 on success, negative on failure | |
2369 | **/ | |
e8e26350 | 2370 | static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw) |
0ecc061d PWJ |
2371 | { |
2372 | u32 autoneg; | |
2373 | bool link_up = false; | |
2374 | u32 ret = IXGBE_ERR_LINK_SETUP; | |
2375 | ||
2376 | if (hw->mac.ops.check_link) | |
2377 | ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false); | |
2378 | ||
2379 | if (ret) | |
2380 | goto link_cfg_out; | |
2381 | ||
2382 | if (hw->mac.ops.get_link_capabilities) | |
2383 | ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, | |
2384 | &hw->mac.autoneg); | |
2385 | if (ret) | |
2386 | goto link_cfg_out; | |
2387 | ||
2388 | if (hw->mac.ops.setup_link_speed) | |
2389 | ret = hw->mac.ops.setup_link_speed(hw, autoneg, true, link_up); | |
0ecc061d PWJ |
2390 | link_cfg_out: |
2391 | return ret; | |
2392 | } | |
2393 | ||
e8e26350 PW |
2394 | #define IXGBE_MAX_RX_DESC_POLL 10 |
2395 | static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter, | |
2396 | int rxr) | |
2397 | { | |
2398 | int j = adapter->rx_ring[rxr].reg_idx; | |
2399 | int k; | |
2400 | ||
2401 | for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) { | |
2402 | if (IXGBE_READ_REG(&adapter->hw, | |
2403 | IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE) | |
2404 | break; | |
2405 | else | |
2406 | msleep(1); | |
2407 | } | |
2408 | if (k >= IXGBE_MAX_RX_DESC_POLL) { | |
2409 | DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d " | |
2410 | "not set within the polling period\n", rxr); | |
2411 | } | |
2412 | ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr], | |
2413 | (adapter->rx_ring[rxr].count - 1)); | |
2414 | } | |
2415 | ||
9a799d71 AK |
2416 | static int ixgbe_up_complete(struct ixgbe_adapter *adapter) |
2417 | { | |
2418 | struct net_device *netdev = adapter->netdev; | |
9a799d71 | 2419 | struct ixgbe_hw *hw = &adapter->hw; |
021230d4 | 2420 | int i, j = 0; |
e8e26350 | 2421 | int num_rx_rings = adapter->num_rx_queues; |
0ecc061d | 2422 | int err; |
9a799d71 | 2423 | int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; |
021230d4 | 2424 | u32 txdctl, rxdctl, mhadd; |
e8e26350 | 2425 | u32 dmatxctl; |
021230d4 | 2426 | u32 gpie; |
9a799d71 | 2427 | |
5eba3699 AV |
2428 | ixgbe_get_hw_control(adapter); |
2429 | ||
021230d4 AV |
2430 | if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) || |
2431 | (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) { | |
9a799d71 AK |
2432 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
2433 | gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME | | |
b4617240 | 2434 | IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD); |
9a799d71 AK |
2435 | } else { |
2436 | /* MSI only */ | |
021230d4 | 2437 | gpie = 0; |
9a799d71 | 2438 | } |
021230d4 AV |
2439 | /* XXX: to interrupt immediately for EICS writes, enable this */ |
2440 | /* gpie |= IXGBE_GPIE_EIMEN; */ | |
2441 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
9a799d71 AK |
2442 | } |
2443 | ||
021230d4 AV |
2444 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { |
2445 | /* legacy interrupts, use EIAM to auto-mask when reading EICR, | |
2446 | * specifically only auto mask tx and rx interrupts */ | |
2447 | IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); | |
2448 | } | |
9a799d71 | 2449 | |
0befdb3e JB |
2450 | /* Enable fan failure interrupt if media type is copper */ |
2451 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
2452 | gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); | |
2453 | gpie |= IXGBE_SDP1_GPIEN; | |
2454 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
2455 | } | |
2456 | ||
e8e26350 PW |
2457 | if (hw->mac.type == ixgbe_mac_82599EB) { |
2458 | gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); | |
2459 | gpie |= IXGBE_SDP1_GPIEN; | |
2460 | gpie |= IXGBE_SDP2_GPIEN; | |
2461 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
2462 | } | |
2463 | ||
63f39bd1 YZ |
2464 | #ifdef IXGBE_FCOE |
2465 | /* adjust max frame to be able to do baby jumbo for FCoE */ | |
2466 | if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && | |
2467 | (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE)) | |
2468 | max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE; | |
2469 | ||
2470 | #endif /* IXGBE_FCOE */ | |
021230d4 | 2471 | mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); |
9a799d71 AK |
2472 | if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) { |
2473 | mhadd &= ~IXGBE_MHADD_MFS_MASK; | |
2474 | mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT; | |
2475 | ||
2476 | IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); | |
2477 | } | |
2478 | ||
2479 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
021230d4 AV |
2480 | j = adapter->tx_ring[i].reg_idx; |
2481 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)); | |
e01c31a5 JB |
2482 | /* enable WTHRESH=8 descriptors, to encourage burst writeback */ |
2483 | txdctl |= (8 << 16); | |
e8e26350 PW |
2484 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl); |
2485 | } | |
2486 | ||
2487 | if (hw->mac.type == ixgbe_mac_82599EB) { | |
2488 | /* DMATXCTL.EN must be set after all Tx queue config is done */ | |
2489 | dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); | |
2490 | dmatxctl |= IXGBE_DMATXCTL_TE; | |
2491 | IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl); | |
2492 | } | |
2493 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
2494 | j = adapter->tx_ring[i].reg_idx; | |
2495 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)); | |
9a799d71 | 2496 | txdctl |= IXGBE_TXDCTL_ENABLE; |
021230d4 | 2497 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl); |
9a799d71 AK |
2498 | } |
2499 | ||
e8e26350 | 2500 | for (i = 0; i < num_rx_rings; i++) { |
021230d4 AV |
2501 | j = adapter->rx_ring[i].reg_idx; |
2502 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); | |
2503 | /* enable PTHRESH=32 descriptors (half the internal cache) | |
2504 | * and HTHRESH=0 descriptors (to minimize latency on fetch), | |
2505 | * this also removes a pesky rx_no_buffer_count increment */ | |
2506 | rxdctl |= 0x0020; | |
9a799d71 | 2507 | rxdctl |= IXGBE_RXDCTL_ENABLE; |
021230d4 | 2508 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl); |
e8e26350 PW |
2509 | if (hw->mac.type == ixgbe_mac_82599EB) |
2510 | ixgbe_rx_desc_queue_enable(adapter, i); | |
9a799d71 AK |
2511 | } |
2512 | /* enable all receives */ | |
2513 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); | |
e8e26350 PW |
2514 | if (hw->mac.type == ixgbe_mac_82598EB) |
2515 | rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN); | |
2516 | else | |
2517 | rxdctl |= IXGBE_RXCTRL_RXEN; | |
2518 | hw->mac.ops.enable_rx_dma(hw, rxdctl); | |
9a799d71 AK |
2519 | |
2520 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) | |
2521 | ixgbe_configure_msix(adapter); | |
2522 | else | |
2523 | ixgbe_configure_msi_and_legacy(adapter); | |
2524 | ||
2525 | clear_bit(__IXGBE_DOWN, &adapter->state); | |
021230d4 AV |
2526 | ixgbe_napi_enable_all(adapter); |
2527 | ||
2528 | /* clear any pending interrupts, may auto mask */ | |
2529 | IXGBE_READ_REG(hw, IXGBE_EICR); | |
2530 | ||
9a799d71 AK |
2531 | ixgbe_irq_enable(adapter); |
2532 | ||
bf069c97 DS |
2533 | /* |
2534 | * If this adapter has a fan, check to see if we had a failure | |
2535 | * before we enabled the interrupt. | |
2536 | */ | |
2537 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
2538 | u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); | |
2539 | if (esdp & IXGBE_ESDP_SDP1) | |
2540 | DPRINTK(DRV, CRIT, | |
2541 | "Fan has stopped, replace the adapter\n"); | |
2542 | } | |
2543 | ||
e8e26350 PW |
2544 | /* |
2545 | * For hot-pluggable SFP+ devices, a new SFP+ module may have | |
2546 | * arrived before interrupts were enabled. We need to kick off | |
2547 | * the SFP+ module setup first, then try to bring up link. | |
2548 | * If we're not hot-pluggable SFP+, we just need to configure link | |
2549 | * and bring it up. | |
2550 | */ | |
2551 | err = hw->phy.ops.identify(hw); | |
2552 | if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
2553 | DPRINTK(PROBE, ERR, "PHY not supported on this NIC %d\n", err); | |
2554 | ixgbe_down(adapter); | |
2555 | return err; | |
2556 | } | |
2557 | ||
2558 | if (ixgbe_is_sfp(hw)) { | |
2559 | ixgbe_sfp_link_config(adapter); | |
2560 | } else { | |
2561 | err = ixgbe_non_sfp_link_config(hw); | |
2562 | if (err) | |
2563 | DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err); | |
2564 | } | |
0ecc061d | 2565 | |
1da100bb PWJ |
2566 | /* enable transmits */ |
2567 | netif_tx_start_all_queues(netdev); | |
2568 | ||
9a799d71 AK |
2569 | /* bring the link up in the watchdog, this could race with our first |
2570 | * link up interrupt but shouldn't be a problem */ | |
cf8280ee JB |
2571 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; |
2572 | adapter->link_check_timeout = jiffies; | |
9a799d71 AK |
2573 | mod_timer(&adapter->watchdog_timer, jiffies); |
2574 | return 0; | |
2575 | } | |
2576 | ||
d4f80882 AV |
2577 | void ixgbe_reinit_locked(struct ixgbe_adapter *adapter) |
2578 | { | |
2579 | WARN_ON(in_interrupt()); | |
2580 | while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) | |
2581 | msleep(1); | |
2582 | ixgbe_down(adapter); | |
2583 | ixgbe_up(adapter); | |
2584 | clear_bit(__IXGBE_RESETTING, &adapter->state); | |
2585 | } | |
2586 | ||
9a799d71 AK |
2587 | int ixgbe_up(struct ixgbe_adapter *adapter) |
2588 | { | |
2589 | /* hardware has been reset, we need to reload some things */ | |
2590 | ixgbe_configure(adapter); | |
2591 | ||
2592 | return ixgbe_up_complete(adapter); | |
2593 | } | |
2594 | ||
2595 | void ixgbe_reset(struct ixgbe_adapter *adapter) | |
2596 | { | |
c44ade9e | 2597 | struct ixgbe_hw *hw = &adapter->hw; |
8ca783ab DS |
2598 | int err; |
2599 | ||
2600 | err = hw->mac.ops.init_hw(hw); | |
da4dd0f7 PWJ |
2601 | switch (err) { |
2602 | case 0: | |
2603 | case IXGBE_ERR_SFP_NOT_PRESENT: | |
2604 | break; | |
2605 | case IXGBE_ERR_MASTER_REQUESTS_PENDING: | |
2606 | dev_err(&adapter->pdev->dev, "master disable timed out\n"); | |
2607 | break; | |
2608 | default: | |
2609 | dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err); | |
2610 | } | |
9a799d71 AK |
2611 | |
2612 | /* reprogram the RAR[0] in case user changed it. */ | |
c44ade9e | 2613 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); |
9a799d71 AK |
2614 | } |
2615 | ||
9a799d71 AK |
2616 | /** |
2617 | * ixgbe_clean_rx_ring - Free Rx Buffers per Queue | |
2618 | * @adapter: board private structure | |
2619 | * @rx_ring: ring to free buffers from | |
2620 | **/ | |
2621 | static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter, | |
b4617240 | 2622 | struct ixgbe_ring *rx_ring) |
9a799d71 AK |
2623 | { |
2624 | struct pci_dev *pdev = adapter->pdev; | |
2625 | unsigned long size; | |
2626 | unsigned int i; | |
2627 | ||
2628 | /* Free all the Rx ring sk_buffs */ | |
2629 | ||
2630 | for (i = 0; i < rx_ring->count; i++) { | |
2631 | struct ixgbe_rx_buffer *rx_buffer_info; | |
2632 | ||
2633 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; | |
2634 | if (rx_buffer_info->dma) { | |
2635 | pci_unmap_single(pdev, rx_buffer_info->dma, | |
b4617240 PW |
2636 | rx_ring->rx_buf_len, |
2637 | PCI_DMA_FROMDEVICE); | |
9a799d71 AK |
2638 | rx_buffer_info->dma = 0; |
2639 | } | |
2640 | if (rx_buffer_info->skb) { | |
f8212f97 | 2641 | struct sk_buff *skb = rx_buffer_info->skb; |
9a799d71 | 2642 | rx_buffer_info->skb = NULL; |
f8212f97 AD |
2643 | do { |
2644 | struct sk_buff *this = skb; | |
2645 | skb = skb->prev; | |
2646 | dev_kfree_skb(this); | |
2647 | } while (skb); | |
9a799d71 AK |
2648 | } |
2649 | if (!rx_buffer_info->page) | |
2650 | continue; | |
762f4c57 JB |
2651 | pci_unmap_page(pdev, rx_buffer_info->page_dma, PAGE_SIZE / 2, |
2652 | PCI_DMA_FROMDEVICE); | |
9a799d71 | 2653 | rx_buffer_info->page_dma = 0; |
9a799d71 AK |
2654 | put_page(rx_buffer_info->page); |
2655 | rx_buffer_info->page = NULL; | |
762f4c57 | 2656 | rx_buffer_info->page_offset = 0; |
9a799d71 AK |
2657 | } |
2658 | ||
2659 | size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; | |
2660 | memset(rx_ring->rx_buffer_info, 0, size); | |
2661 | ||
2662 | /* Zero out the descriptor ring */ | |
2663 | memset(rx_ring->desc, 0, rx_ring->size); | |
2664 | ||
2665 | rx_ring->next_to_clean = 0; | |
2666 | rx_ring->next_to_use = 0; | |
2667 | ||
9891ca7c JB |
2668 | if (rx_ring->head) |
2669 | writel(0, adapter->hw.hw_addr + rx_ring->head); | |
2670 | if (rx_ring->tail) | |
2671 | writel(0, adapter->hw.hw_addr + rx_ring->tail); | |
9a799d71 AK |
2672 | } |
2673 | ||
2674 | /** | |
2675 | * ixgbe_clean_tx_ring - Free Tx Buffers | |
2676 | * @adapter: board private structure | |
2677 | * @tx_ring: ring to be cleaned | |
2678 | **/ | |
2679 | static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter, | |
b4617240 | 2680 | struct ixgbe_ring *tx_ring) |
9a799d71 AK |
2681 | { |
2682 | struct ixgbe_tx_buffer *tx_buffer_info; | |
2683 | unsigned long size; | |
2684 | unsigned int i; | |
2685 | ||
2686 | /* Free all the Tx ring sk_buffs */ | |
2687 | ||
2688 | for (i = 0; i < tx_ring->count; i++) { | |
2689 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
2690 | ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info); | |
2691 | } | |
2692 | ||
2693 | size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; | |
2694 | memset(tx_ring->tx_buffer_info, 0, size); | |
2695 | ||
2696 | /* Zero out the descriptor ring */ | |
2697 | memset(tx_ring->desc, 0, tx_ring->size); | |
2698 | ||
2699 | tx_ring->next_to_use = 0; | |
2700 | tx_ring->next_to_clean = 0; | |
2701 | ||
9891ca7c JB |
2702 | if (tx_ring->head) |
2703 | writel(0, adapter->hw.hw_addr + tx_ring->head); | |
2704 | if (tx_ring->tail) | |
2705 | writel(0, adapter->hw.hw_addr + tx_ring->tail); | |
9a799d71 AK |
2706 | } |
2707 | ||
2708 | /** | |
021230d4 | 2709 | * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues |
9a799d71 AK |
2710 | * @adapter: board private structure |
2711 | **/ | |
021230d4 | 2712 | static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter) |
9a799d71 AK |
2713 | { |
2714 | int i; | |
2715 | ||
021230d4 AV |
2716 | for (i = 0; i < adapter->num_rx_queues; i++) |
2717 | ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]); | |
9a799d71 AK |
2718 | } |
2719 | ||
2720 | /** | |
021230d4 | 2721 | * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues |
9a799d71 AK |
2722 | * @adapter: board private structure |
2723 | **/ | |
021230d4 | 2724 | static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter) |
9a799d71 AK |
2725 | { |
2726 | int i; | |
2727 | ||
021230d4 AV |
2728 | for (i = 0; i < adapter->num_tx_queues; i++) |
2729 | ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]); | |
9a799d71 AK |
2730 | } |
2731 | ||
2732 | void ixgbe_down(struct ixgbe_adapter *adapter) | |
2733 | { | |
2734 | struct net_device *netdev = adapter->netdev; | |
7f821875 | 2735 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 | 2736 | u32 rxctrl; |
7f821875 JB |
2737 | u32 txdctl; |
2738 | int i, j; | |
9a799d71 AK |
2739 | |
2740 | /* signal that we are down to the interrupt handler */ | |
2741 | set_bit(__IXGBE_DOWN, &adapter->state); | |
2742 | ||
2743 | /* disable receives */ | |
7f821875 JB |
2744 | rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); |
2745 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); | |
9a799d71 AK |
2746 | |
2747 | netif_tx_disable(netdev); | |
2748 | ||
7f821875 | 2749 | IXGBE_WRITE_FLUSH(hw); |
9a799d71 AK |
2750 | msleep(10); |
2751 | ||
7f821875 JB |
2752 | netif_tx_stop_all_queues(netdev); |
2753 | ||
9a799d71 AK |
2754 | ixgbe_irq_disable(adapter); |
2755 | ||
021230d4 | 2756 | ixgbe_napi_disable_all(adapter); |
7f821875 | 2757 | |
9a799d71 | 2758 | del_timer_sync(&adapter->watchdog_timer); |
cf8280ee | 2759 | cancel_work_sync(&adapter->watchdog_task); |
9a799d71 | 2760 | |
7f821875 JB |
2761 | /* disable transmits in the hardware now that interrupts are off */ |
2762 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
2763 | j = adapter->tx_ring[i].reg_idx; | |
2764 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)); | |
2765 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), | |
2766 | (txdctl & ~IXGBE_TXDCTL_ENABLE)); | |
2767 | } | |
88512539 PW |
2768 | /* Disable the Tx DMA engine on 82599 */ |
2769 | if (hw->mac.type == ixgbe_mac_82599EB) | |
2770 | IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, | |
2771 | (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) & | |
2772 | ~IXGBE_DMATXCTL_TE)); | |
7f821875 | 2773 | |
9a799d71 | 2774 | netif_carrier_off(netdev); |
9a799d71 | 2775 | |
6f4a0e45 PL |
2776 | if (!pci_channel_offline(adapter->pdev)) |
2777 | ixgbe_reset(adapter); | |
9a799d71 AK |
2778 | ixgbe_clean_all_tx_rings(adapter); |
2779 | ixgbe_clean_all_rx_rings(adapter); | |
2780 | ||
5dd2d332 | 2781 | #ifdef CONFIG_IXGBE_DCA |
96b0e0f6 | 2782 | /* since we reset the hardware DCA settings were cleared */ |
e35ec126 | 2783 | ixgbe_setup_dca(adapter); |
96b0e0f6 | 2784 | #endif |
9a799d71 AK |
2785 | } |
2786 | ||
9a799d71 | 2787 | /** |
021230d4 AV |
2788 | * ixgbe_poll - NAPI Rx polling callback |
2789 | * @napi: structure for representing this polling device | |
2790 | * @budget: how many packets driver is allowed to clean | |
2791 | * | |
2792 | * This function is used for legacy and MSI, NAPI mode | |
9a799d71 | 2793 | **/ |
021230d4 | 2794 | static int ixgbe_poll(struct napi_struct *napi, int budget) |
9a799d71 | 2795 | { |
9a1a69ad JB |
2796 | struct ixgbe_q_vector *q_vector = |
2797 | container_of(napi, struct ixgbe_q_vector, napi); | |
021230d4 | 2798 | struct ixgbe_adapter *adapter = q_vector->adapter; |
9a1a69ad | 2799 | int tx_clean_complete, work_done = 0; |
9a799d71 | 2800 | |
5dd2d332 | 2801 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
2802 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { |
2803 | ixgbe_update_tx_dca(adapter, adapter->tx_ring); | |
2804 | ixgbe_update_rx_dca(adapter, adapter->rx_ring); | |
2805 | } | |
2806 | #endif | |
2807 | ||
9a1a69ad | 2808 | tx_clean_complete = ixgbe_clean_tx_irq(adapter, adapter->tx_ring); |
78b6f4ce | 2809 | ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget); |
9a799d71 | 2810 | |
9a1a69ad | 2811 | if (!tx_clean_complete) |
d2c7ddd6 DM |
2812 | work_done = budget; |
2813 | ||
53e52c72 DM |
2814 | /* If budget not fully consumed, exit the polling mode */ |
2815 | if (work_done < budget) { | |
288379f0 | 2816 | napi_complete(napi); |
509ee935 | 2817 | if (adapter->itr_setting & 1) |
f494e8fa | 2818 | ixgbe_set_itr(adapter); |
d4f80882 | 2819 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
835462fc | 2820 | ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE); |
9a799d71 | 2821 | } |
9a799d71 AK |
2822 | return work_done; |
2823 | } | |
2824 | ||
2825 | /** | |
2826 | * ixgbe_tx_timeout - Respond to a Tx Hang | |
2827 | * @netdev: network interface device structure | |
2828 | **/ | |
2829 | static void ixgbe_tx_timeout(struct net_device *netdev) | |
2830 | { | |
2831 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
2832 | ||
2833 | /* Do the reset outside of interrupt context */ | |
2834 | schedule_work(&adapter->reset_task); | |
2835 | } | |
2836 | ||
2837 | static void ixgbe_reset_task(struct work_struct *work) | |
2838 | { | |
2839 | struct ixgbe_adapter *adapter; | |
2840 | adapter = container_of(work, struct ixgbe_adapter, reset_task); | |
2841 | ||
2f90b865 AD |
2842 | /* If we're already down or resetting, just bail */ |
2843 | if (test_bit(__IXGBE_DOWN, &adapter->state) || | |
2844 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
2845 | return; | |
2846 | ||
9a799d71 AK |
2847 | adapter->tx_timeout_count++; |
2848 | ||
d4f80882 | 2849 | ixgbe_reinit_locked(adapter); |
9a799d71 AK |
2850 | } |
2851 | ||
bc97114d PWJ |
2852 | #ifdef CONFIG_IXGBE_DCB |
2853 | static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter) | |
b9804972 | 2854 | { |
bc97114d | 2855 | bool ret = false; |
0cefafad | 2856 | struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB]; |
b9804972 | 2857 | |
0cefafad JB |
2858 | if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) |
2859 | return ret; | |
2860 | ||
2861 | f->mask = 0x7 << 3; | |
2862 | adapter->num_rx_queues = f->indices; | |
2863 | adapter->num_tx_queues = f->indices; | |
2864 | ret = true; | |
2f90b865 | 2865 | |
bc97114d PWJ |
2866 | return ret; |
2867 | } | |
2868 | #endif | |
2869 | ||
4df10466 JB |
2870 | /** |
2871 | * ixgbe_set_rss_queues: Allocate queues for RSS | |
2872 | * @adapter: board private structure to initialize | |
2873 | * | |
2874 | * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try | |
2875 | * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU. | |
2876 | * | |
2877 | **/ | |
bc97114d PWJ |
2878 | static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter) |
2879 | { | |
2880 | bool ret = false; | |
0cefafad | 2881 | struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS]; |
bc97114d PWJ |
2882 | |
2883 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { | |
0cefafad JB |
2884 | f->mask = 0xF; |
2885 | adapter->num_rx_queues = f->indices; | |
2886 | adapter->num_tx_queues = f->indices; | |
bc97114d PWJ |
2887 | ret = true; |
2888 | } else { | |
bc97114d | 2889 | ret = false; |
b9804972 JB |
2890 | } |
2891 | ||
bc97114d PWJ |
2892 | return ret; |
2893 | } | |
2894 | ||
0331a832 YZ |
2895 | #ifdef IXGBE_FCOE |
2896 | /** | |
2897 | * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE) | |
2898 | * @adapter: board private structure to initialize | |
2899 | * | |
2900 | * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges. | |
2901 | * The ring feature mask is not used as a mask for FCoE, as it can take any 8 | |
2902 | * rx queues out of the max number of rx queues, instead, it is used as the | |
2903 | * index of the first rx queue used by FCoE. | |
2904 | * | |
2905 | **/ | |
2906 | static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter) | |
2907 | { | |
2908 | bool ret = false; | |
2909 | struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE]; | |
2910 | ||
2911 | f->indices = min((int)num_online_cpus(), f->indices); | |
2912 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { | |
2913 | #ifdef CONFIG_IXGBE_DCB | |
2914 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
2915 | DPRINTK(PROBE, INFO, "FCOE enabled with DCB \n"); | |
2916 | ixgbe_set_dcb_queues(adapter); | |
2917 | } | |
2918 | #endif | |
2919 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { | |
2920 | DPRINTK(PROBE, INFO, "FCOE enabled with RSS \n"); | |
2921 | ixgbe_set_rss_queues(adapter); | |
2922 | } | |
2923 | /* adding FCoE rx rings to the end */ | |
2924 | f->mask = adapter->num_rx_queues; | |
2925 | adapter->num_rx_queues += f->indices; | |
2926 | if (adapter->num_tx_queues == 0) | |
2927 | adapter->num_tx_queues = f->indices; | |
2928 | ||
2929 | ret = true; | |
2930 | } | |
2931 | ||
2932 | return ret; | |
2933 | } | |
2934 | ||
2935 | #endif /* IXGBE_FCOE */ | |
4df10466 JB |
2936 | /* |
2937 | * ixgbe_set_num_queues: Allocate queues for device, feature dependant | |
2938 | * @adapter: board private structure to initialize | |
2939 | * | |
2940 | * This is the top level queue allocation routine. The order here is very | |
2941 | * important, starting with the "most" number of features turned on at once, | |
2942 | * and ending with the smallest set of features. This way large combinations | |
2943 | * can be allocated if they're turned on, and smaller combinations are the | |
2944 | * fallthrough conditions. | |
2945 | * | |
2946 | **/ | |
bc97114d PWJ |
2947 | static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter) |
2948 | { | |
0331a832 YZ |
2949 | #ifdef IXGBE_FCOE |
2950 | if (ixgbe_set_fcoe_queues(adapter)) | |
2951 | goto done; | |
2952 | ||
2953 | #endif /* IXGBE_FCOE */ | |
bc97114d PWJ |
2954 | #ifdef CONFIG_IXGBE_DCB |
2955 | if (ixgbe_set_dcb_queues(adapter)) | |
af22ab1b | 2956 | goto done; |
bc97114d PWJ |
2957 | |
2958 | #endif | |
2959 | if (ixgbe_set_rss_queues(adapter)) | |
af22ab1b WF |
2960 | goto done; |
2961 | ||
2962 | /* fallback to base case */ | |
2963 | adapter->num_rx_queues = 1; | |
2964 | adapter->num_tx_queues = 1; | |
2965 | ||
2966 | done: | |
2967 | /* Notify the stack of the (possibly) reduced Tx Queue count. */ | |
2968 | adapter->netdev->real_num_tx_queues = adapter->num_tx_queues; | |
b9804972 JB |
2969 | } |
2970 | ||
021230d4 | 2971 | static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter, |
b4617240 | 2972 | int vectors) |
021230d4 AV |
2973 | { |
2974 | int err, vector_threshold; | |
2975 | ||
2976 | /* We'll want at least 3 (vector_threshold): | |
2977 | * 1) TxQ[0] Cleanup | |
2978 | * 2) RxQ[0] Cleanup | |
2979 | * 3) Other (Link Status Change, etc.) | |
2980 | * 4) TCP Timer (optional) | |
2981 | */ | |
2982 | vector_threshold = MIN_MSIX_COUNT; | |
2983 | ||
2984 | /* The more we get, the more we will assign to Tx/Rx Cleanup | |
2985 | * for the separate queues...where Rx Cleanup >= Tx Cleanup. | |
2986 | * Right now, we simply care about how many we'll get; we'll | |
2987 | * set them up later while requesting irq's. | |
2988 | */ | |
2989 | while (vectors >= vector_threshold) { | |
2990 | err = pci_enable_msix(adapter->pdev, adapter->msix_entries, | |
b4617240 | 2991 | vectors); |
021230d4 AV |
2992 | if (!err) /* Success in acquiring all requested vectors. */ |
2993 | break; | |
2994 | else if (err < 0) | |
2995 | vectors = 0; /* Nasty failure, quit now */ | |
2996 | else /* err == number of vectors we should try again with */ | |
2997 | vectors = err; | |
2998 | } | |
2999 | ||
3000 | if (vectors < vector_threshold) { | |
3001 | /* Can't allocate enough MSI-X interrupts? Oh well. | |
3002 | * This just means we'll go with either a single MSI | |
3003 | * vector or fall back to legacy interrupts. | |
3004 | */ | |
3005 | DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n"); | |
3006 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; | |
3007 | kfree(adapter->msix_entries); | |
3008 | adapter->msix_entries = NULL; | |
021230d4 AV |
3009 | } else { |
3010 | adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */ | |
eb7f139c PWJ |
3011 | /* |
3012 | * Adjust for only the vectors we'll use, which is minimum | |
3013 | * of max_msix_q_vectors + NON_Q_VECTORS, or the number of | |
3014 | * vectors we were allocated. | |
3015 | */ | |
3016 | adapter->num_msix_vectors = min(vectors, | |
3017 | adapter->max_msix_q_vectors + NON_Q_VECTORS); | |
021230d4 AV |
3018 | } |
3019 | } | |
3020 | ||
021230d4 | 3021 | /** |
bc97114d | 3022 | * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS |
021230d4 AV |
3023 | * @adapter: board private structure to initialize |
3024 | * | |
bc97114d PWJ |
3025 | * Cache the descriptor ring offsets for RSS to the assigned rings. |
3026 | * | |
021230d4 | 3027 | **/ |
bc97114d | 3028 | static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter) |
021230d4 | 3029 | { |
bc97114d PWJ |
3030 | int i; |
3031 | bool ret = false; | |
3032 | ||
3033 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { | |
3034 | for (i = 0; i < adapter->num_rx_queues; i++) | |
3035 | adapter->rx_ring[i].reg_idx = i; | |
3036 | for (i = 0; i < adapter->num_tx_queues; i++) | |
3037 | adapter->tx_ring[i].reg_idx = i; | |
3038 | ret = true; | |
3039 | } else { | |
3040 | ret = false; | |
3041 | } | |
3042 | ||
3043 | return ret; | |
3044 | } | |
3045 | ||
3046 | #ifdef CONFIG_IXGBE_DCB | |
3047 | /** | |
3048 | * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB | |
3049 | * @adapter: board private structure to initialize | |
3050 | * | |
3051 | * Cache the descriptor ring offsets for DCB to the assigned rings. | |
3052 | * | |
3053 | **/ | |
3054 | static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter) | |
3055 | { | |
3056 | int i; | |
3057 | bool ret = false; | |
3058 | int dcb_i = adapter->ring_feature[RING_F_DCB].indices; | |
3059 | ||
3060 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
3061 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { | |
2f90b865 AD |
3062 | /* the number of queues is assumed to be symmetric */ |
3063 | for (i = 0; i < dcb_i; i++) { | |
3064 | adapter->rx_ring[i].reg_idx = i << 3; | |
3065 | adapter->tx_ring[i].reg_idx = i << 2; | |
3066 | } | |
bc97114d | 3067 | ret = true; |
e8e26350 | 3068 | } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { |
f92ef202 PW |
3069 | if (dcb_i == 8) { |
3070 | /* | |
3071 | * Tx TC0 starts at: descriptor queue 0 | |
3072 | * Tx TC1 starts at: descriptor queue 32 | |
3073 | * Tx TC2 starts at: descriptor queue 64 | |
3074 | * Tx TC3 starts at: descriptor queue 80 | |
3075 | * Tx TC4 starts at: descriptor queue 96 | |
3076 | * Tx TC5 starts at: descriptor queue 104 | |
3077 | * Tx TC6 starts at: descriptor queue 112 | |
3078 | * Tx TC7 starts at: descriptor queue 120 | |
3079 | * | |
3080 | * Rx TC0-TC7 are offset by 16 queues each | |
3081 | */ | |
3082 | for (i = 0; i < 3; i++) { | |
3083 | adapter->tx_ring[i].reg_idx = i << 5; | |
3084 | adapter->rx_ring[i].reg_idx = i << 4; | |
3085 | } | |
3086 | for ( ; i < 5; i++) { | |
3087 | adapter->tx_ring[i].reg_idx = | |
3088 | ((i + 2) << 4); | |
3089 | adapter->rx_ring[i].reg_idx = i << 4; | |
3090 | } | |
3091 | for ( ; i < dcb_i; i++) { | |
3092 | adapter->tx_ring[i].reg_idx = | |
3093 | ((i + 8) << 3); | |
3094 | adapter->rx_ring[i].reg_idx = i << 4; | |
3095 | } | |
3096 | ||
3097 | ret = true; | |
3098 | } else if (dcb_i == 4) { | |
3099 | /* | |
3100 | * Tx TC0 starts at: descriptor queue 0 | |
3101 | * Tx TC1 starts at: descriptor queue 64 | |
3102 | * Tx TC2 starts at: descriptor queue 96 | |
3103 | * Tx TC3 starts at: descriptor queue 112 | |
3104 | * | |
3105 | * Rx TC0-TC3 are offset by 32 queues each | |
3106 | */ | |
3107 | adapter->tx_ring[0].reg_idx = 0; | |
3108 | adapter->tx_ring[1].reg_idx = 64; | |
3109 | adapter->tx_ring[2].reg_idx = 96; | |
3110 | adapter->tx_ring[3].reg_idx = 112; | |
3111 | for (i = 0 ; i < dcb_i; i++) | |
3112 | adapter->rx_ring[i].reg_idx = i << 5; | |
3113 | ||
3114 | ret = true; | |
3115 | } else { | |
3116 | ret = false; | |
e8e26350 | 3117 | } |
bc97114d PWJ |
3118 | } else { |
3119 | ret = false; | |
021230d4 | 3120 | } |
bc97114d PWJ |
3121 | } else { |
3122 | ret = false; | |
021230d4 | 3123 | } |
bc97114d PWJ |
3124 | |
3125 | return ret; | |
3126 | } | |
3127 | #endif | |
3128 | ||
0331a832 YZ |
3129 | #ifdef IXGBE_FCOE |
3130 | /** | |
3131 | * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE | |
3132 | * @adapter: board private structure to initialize | |
3133 | * | |
3134 | * Cache the descriptor ring offsets for FCoE mode to the assigned rings. | |
3135 | * | |
3136 | */ | |
3137 | static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter) | |
3138 | { | |
3139 | int i, fcoe_i = 0; | |
3140 | bool ret = false; | |
3141 | struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE]; | |
3142 | ||
3143 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { | |
3144 | #ifdef CONFIG_IXGBE_DCB | |
3145 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
3146 | ixgbe_cache_ring_dcb(adapter); | |
3147 | fcoe_i = adapter->rx_ring[0].reg_idx + 1; | |
3148 | } | |
3149 | #endif /* CONFIG_IXGBE_DCB */ | |
3150 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { | |
3151 | ixgbe_cache_ring_rss(adapter); | |
3152 | fcoe_i = f->mask; | |
3153 | } | |
3154 | for (i = 0; i < f->indices; i++, fcoe_i++) | |
3155 | adapter->rx_ring[f->mask + i].reg_idx = fcoe_i; | |
3156 | ret = true; | |
3157 | } | |
3158 | return ret; | |
3159 | } | |
3160 | ||
3161 | #endif /* IXGBE_FCOE */ | |
bc97114d PWJ |
3162 | /** |
3163 | * ixgbe_cache_ring_register - Descriptor ring to register mapping | |
3164 | * @adapter: board private structure to initialize | |
3165 | * | |
3166 | * Once we know the feature-set enabled for the device, we'll cache | |
3167 | * the register offset the descriptor ring is assigned to. | |
3168 | * | |
3169 | * Note, the order the various feature calls is important. It must start with | |
3170 | * the "most" features enabled at the same time, then trickle down to the | |
3171 | * least amount of features turned on at once. | |
3172 | **/ | |
3173 | static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter) | |
3174 | { | |
3175 | /* start with default case */ | |
3176 | adapter->rx_ring[0].reg_idx = 0; | |
3177 | adapter->tx_ring[0].reg_idx = 0; | |
3178 | ||
0331a832 YZ |
3179 | #ifdef IXGBE_FCOE |
3180 | if (ixgbe_cache_ring_fcoe(adapter)) | |
3181 | return; | |
3182 | ||
3183 | #endif /* IXGBE_FCOE */ | |
bc97114d PWJ |
3184 | #ifdef CONFIG_IXGBE_DCB |
3185 | if (ixgbe_cache_ring_dcb(adapter)) | |
3186 | return; | |
3187 | ||
3188 | #endif | |
3189 | if (ixgbe_cache_ring_rss(adapter)) | |
3190 | return; | |
021230d4 AV |
3191 | } |
3192 | ||
9a799d71 AK |
3193 | /** |
3194 | * ixgbe_alloc_queues - Allocate memory for all rings | |
3195 | * @adapter: board private structure to initialize | |
3196 | * | |
3197 | * We allocate one ring per queue at run-time since we don't know the | |
4df10466 JB |
3198 | * number of queues at compile-time. The polling_netdev array is |
3199 | * intended for Multiqueue, but should work fine with a single queue. | |
9a799d71 | 3200 | **/ |
2f90b865 | 3201 | static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter) |
9a799d71 AK |
3202 | { |
3203 | int i; | |
3204 | ||
3205 | adapter->tx_ring = kcalloc(adapter->num_tx_queues, | |
b4617240 | 3206 | sizeof(struct ixgbe_ring), GFP_KERNEL); |
9a799d71 | 3207 | if (!adapter->tx_ring) |
021230d4 | 3208 | goto err_tx_ring_allocation; |
9a799d71 AK |
3209 | |
3210 | adapter->rx_ring = kcalloc(adapter->num_rx_queues, | |
b4617240 | 3211 | sizeof(struct ixgbe_ring), GFP_KERNEL); |
021230d4 AV |
3212 | if (!adapter->rx_ring) |
3213 | goto err_rx_ring_allocation; | |
9a799d71 | 3214 | |
021230d4 | 3215 | for (i = 0; i < adapter->num_tx_queues; i++) { |
b9804972 | 3216 | adapter->tx_ring[i].count = adapter->tx_ring_count; |
021230d4 AV |
3217 | adapter->tx_ring[i].queue_index = i; |
3218 | } | |
b9804972 | 3219 | |
9a799d71 | 3220 | for (i = 0; i < adapter->num_rx_queues; i++) { |
b9804972 | 3221 | adapter->rx_ring[i].count = adapter->rx_ring_count; |
021230d4 AV |
3222 | adapter->rx_ring[i].queue_index = i; |
3223 | } | |
3224 | ||
3225 | ixgbe_cache_ring_register(adapter); | |
3226 | ||
3227 | return 0; | |
3228 | ||
3229 | err_rx_ring_allocation: | |
3230 | kfree(adapter->tx_ring); | |
3231 | err_tx_ring_allocation: | |
3232 | return -ENOMEM; | |
3233 | } | |
3234 | ||
3235 | /** | |
3236 | * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported | |
3237 | * @adapter: board private structure to initialize | |
3238 | * | |
3239 | * Attempt to configure the interrupts using the best available | |
3240 | * capabilities of the hardware and the kernel. | |
3241 | **/ | |
feea6a57 | 3242 | static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter) |
021230d4 | 3243 | { |
8be0e467 | 3244 | struct ixgbe_hw *hw = &adapter->hw; |
021230d4 AV |
3245 | int err = 0; |
3246 | int vector, v_budget; | |
3247 | ||
3248 | /* | |
3249 | * It's easy to be greedy for MSI-X vectors, but it really | |
3250 | * doesn't do us much good if we have a lot more vectors | |
3251 | * than CPU's. So let's be conservative and only ask for | |
3252 | * (roughly) twice the number of vectors as there are CPU's. | |
3253 | */ | |
3254 | v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues, | |
b4617240 | 3255 | (int)(num_online_cpus() * 2)) + NON_Q_VECTORS; |
021230d4 AV |
3256 | |
3257 | /* | |
3258 | * At the same time, hardware can only support a maximum of | |
8be0e467 PW |
3259 | * hw.mac->max_msix_vectors vectors. With features |
3260 | * such as RSS and VMDq, we can easily surpass the number of Rx and Tx | |
3261 | * descriptor queues supported by our device. Thus, we cap it off in | |
3262 | * those rare cases where the cpu count also exceeds our vector limit. | |
021230d4 | 3263 | */ |
8be0e467 | 3264 | v_budget = min(v_budget, (int)hw->mac.max_msix_vectors); |
021230d4 AV |
3265 | |
3266 | /* A failure in MSI-X entry allocation isn't fatal, but it does | |
3267 | * mean we disable MSI-X capabilities of the adapter. */ | |
3268 | adapter->msix_entries = kcalloc(v_budget, | |
b4617240 | 3269 | sizeof(struct msix_entry), GFP_KERNEL); |
7a921c93 AD |
3270 | if (adapter->msix_entries) { |
3271 | for (vector = 0; vector < v_budget; vector++) | |
3272 | adapter->msix_entries[vector].entry = vector; | |
021230d4 | 3273 | |
7a921c93 | 3274 | ixgbe_acquire_msix_vectors(adapter, v_budget); |
021230d4 | 3275 | |
7a921c93 AD |
3276 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
3277 | goto out; | |
3278 | } | |
021230d4 | 3279 | |
7a921c93 AD |
3280 | adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; |
3281 | adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED; | |
3282 | ixgbe_set_num_queues(adapter); | |
021230d4 | 3283 | |
021230d4 AV |
3284 | err = pci_enable_msi(adapter->pdev); |
3285 | if (!err) { | |
3286 | adapter->flags |= IXGBE_FLAG_MSI_ENABLED; | |
3287 | } else { | |
3288 | DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, " | |
b4617240 | 3289 | "falling back to legacy. Error: %d\n", err); |
021230d4 AV |
3290 | /* reset err */ |
3291 | err = 0; | |
3292 | } | |
3293 | ||
3294 | out: | |
021230d4 AV |
3295 | return err; |
3296 | } | |
3297 | ||
7a921c93 AD |
3298 | /** |
3299 | * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors | |
3300 | * @adapter: board private structure to initialize | |
3301 | * | |
3302 | * We allocate one q_vector per queue interrupt. If allocation fails we | |
3303 | * return -ENOMEM. | |
3304 | **/ | |
3305 | static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter) | |
3306 | { | |
3307 | int q_idx, num_q_vectors; | |
3308 | struct ixgbe_q_vector *q_vector; | |
3309 | int napi_vectors; | |
3310 | int (*poll)(struct napi_struct *, int); | |
3311 | ||
3312 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
3313 | num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
3314 | napi_vectors = adapter->num_rx_queues; | |
3315 | poll = &ixgbe_clean_rxonly; | |
3316 | } else { | |
3317 | num_q_vectors = 1; | |
3318 | napi_vectors = 1; | |
3319 | poll = &ixgbe_poll; | |
3320 | } | |
3321 | ||
3322 | for (q_idx = 0; q_idx < num_q_vectors; q_idx++) { | |
3323 | q_vector = kzalloc(sizeof(struct ixgbe_q_vector), GFP_KERNEL); | |
3324 | if (!q_vector) | |
3325 | goto err_out; | |
3326 | q_vector->adapter = adapter; | |
3327 | q_vector->v_idx = q_idx; | |
3328 | q_vector->eitr = adapter->eitr_param; | |
3329 | if (q_idx < napi_vectors) | |
3330 | netif_napi_add(adapter->netdev, &q_vector->napi, | |
3331 | (*poll), 64); | |
3332 | adapter->q_vector[q_idx] = q_vector; | |
3333 | } | |
3334 | ||
3335 | return 0; | |
3336 | ||
3337 | err_out: | |
3338 | while (q_idx) { | |
3339 | q_idx--; | |
3340 | q_vector = adapter->q_vector[q_idx]; | |
3341 | netif_napi_del(&q_vector->napi); | |
3342 | kfree(q_vector); | |
3343 | adapter->q_vector[q_idx] = NULL; | |
3344 | } | |
3345 | return -ENOMEM; | |
3346 | } | |
3347 | ||
3348 | /** | |
3349 | * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors | |
3350 | * @adapter: board private structure to initialize | |
3351 | * | |
3352 | * This function frees the memory allocated to the q_vectors. In addition if | |
3353 | * NAPI is enabled it will delete any references to the NAPI struct prior | |
3354 | * to freeing the q_vector. | |
3355 | **/ | |
3356 | static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter) | |
3357 | { | |
3358 | int q_idx, num_q_vectors; | |
3359 | int napi_vectors; | |
3360 | ||
3361 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
3362 | num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
3363 | napi_vectors = adapter->num_rx_queues; | |
3364 | } else { | |
3365 | num_q_vectors = 1; | |
3366 | napi_vectors = 1; | |
3367 | } | |
3368 | ||
3369 | for (q_idx = 0; q_idx < num_q_vectors; q_idx++) { | |
3370 | struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx]; | |
3371 | ||
3372 | adapter->q_vector[q_idx] = NULL; | |
3373 | if (q_idx < napi_vectors) | |
3374 | netif_napi_del(&q_vector->napi); | |
3375 | kfree(q_vector); | |
3376 | } | |
3377 | } | |
3378 | ||
2f90b865 | 3379 | void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter) |
021230d4 AV |
3380 | { |
3381 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
3382 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; | |
3383 | pci_disable_msix(adapter->pdev); | |
3384 | kfree(adapter->msix_entries); | |
3385 | adapter->msix_entries = NULL; | |
3386 | } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) { | |
3387 | adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED; | |
3388 | pci_disable_msi(adapter->pdev); | |
3389 | } | |
3390 | return; | |
3391 | } | |
3392 | ||
3393 | /** | |
3394 | * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme | |
3395 | * @adapter: board private structure to initialize | |
3396 | * | |
3397 | * We determine which interrupt scheme to use based on... | |
3398 | * - Kernel support (MSI, MSI-X) | |
3399 | * - which can be user-defined (via MODULE_PARAM) | |
3400 | * - Hardware queue count (num_*_queues) | |
3401 | * - defined by miscellaneous hardware support/features (RSS, etc.) | |
3402 | **/ | |
2f90b865 | 3403 | int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter) |
021230d4 AV |
3404 | { |
3405 | int err; | |
3406 | ||
3407 | /* Number of supported queues */ | |
3408 | ixgbe_set_num_queues(adapter); | |
3409 | ||
021230d4 AV |
3410 | err = ixgbe_set_interrupt_capability(adapter); |
3411 | if (err) { | |
3412 | DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n"); | |
3413 | goto err_set_interrupt; | |
9a799d71 AK |
3414 | } |
3415 | ||
7a921c93 AD |
3416 | err = ixgbe_alloc_q_vectors(adapter); |
3417 | if (err) { | |
3418 | DPRINTK(PROBE, ERR, "Unable to allocate memory for queue " | |
3419 | "vectors\n"); | |
3420 | goto err_alloc_q_vectors; | |
3421 | } | |
3422 | ||
3423 | err = ixgbe_alloc_queues(adapter); | |
3424 | if (err) { | |
3425 | DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n"); | |
3426 | goto err_alloc_queues; | |
3427 | } | |
3428 | ||
021230d4 | 3429 | DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, " |
b4617240 PW |
3430 | "Tx Queue count = %u\n", |
3431 | (adapter->num_rx_queues > 1) ? "Enabled" : | |
3432 | "Disabled", adapter->num_rx_queues, adapter->num_tx_queues); | |
021230d4 AV |
3433 | |
3434 | set_bit(__IXGBE_DOWN, &adapter->state); | |
3435 | ||
9a799d71 | 3436 | return 0; |
021230d4 | 3437 | |
7a921c93 AD |
3438 | err_alloc_queues: |
3439 | ixgbe_free_q_vectors(adapter); | |
3440 | err_alloc_q_vectors: | |
3441 | ixgbe_reset_interrupt_capability(adapter); | |
021230d4 | 3442 | err_set_interrupt: |
7a921c93 AD |
3443 | return err; |
3444 | } | |
3445 | ||
3446 | /** | |
3447 | * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings | |
3448 | * @adapter: board private structure to clear interrupt scheme on | |
3449 | * | |
3450 | * We go through and clear interrupt specific resources and reset the structure | |
3451 | * to pre-load conditions | |
3452 | **/ | |
3453 | void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter) | |
3454 | { | |
021230d4 AV |
3455 | kfree(adapter->tx_ring); |
3456 | kfree(adapter->rx_ring); | |
7a921c93 AD |
3457 | adapter->tx_ring = NULL; |
3458 | adapter->rx_ring = NULL; | |
3459 | ||
3460 | ixgbe_free_q_vectors(adapter); | |
3461 | ixgbe_reset_interrupt_capability(adapter); | |
9a799d71 AK |
3462 | } |
3463 | ||
c4900be0 DS |
3464 | /** |
3465 | * ixgbe_sfp_timer - worker thread to find a missing module | |
3466 | * @data: pointer to our adapter struct | |
3467 | **/ | |
3468 | static void ixgbe_sfp_timer(unsigned long data) | |
3469 | { | |
3470 | struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data; | |
3471 | ||
4df10466 JB |
3472 | /* |
3473 | * Do the sfp_timer outside of interrupt context due to the | |
c4900be0 DS |
3474 | * delays that sfp+ detection requires |
3475 | */ | |
3476 | schedule_work(&adapter->sfp_task); | |
3477 | } | |
3478 | ||
3479 | /** | |
3480 | * ixgbe_sfp_task - worker thread to find a missing module | |
3481 | * @work: pointer to work_struct containing our data | |
3482 | **/ | |
3483 | static void ixgbe_sfp_task(struct work_struct *work) | |
3484 | { | |
3485 | struct ixgbe_adapter *adapter = container_of(work, | |
3486 | struct ixgbe_adapter, | |
3487 | sfp_task); | |
3488 | struct ixgbe_hw *hw = &adapter->hw; | |
3489 | ||
3490 | if ((hw->phy.type == ixgbe_phy_nl) && | |
3491 | (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) { | |
3492 | s32 ret = hw->phy.ops.identify_sfp(hw); | |
3493 | if (ret) | |
3494 | goto reschedule; | |
3495 | ret = hw->phy.ops.reset(hw); | |
3496 | if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
3497 | DPRINTK(PROBE, ERR, "failed to initialize because an " | |
3498 | "unsupported SFP+ module type was detected.\n" | |
3499 | "Reload the driver after installing a " | |
3500 | "supported module.\n"); | |
3501 | unregister_netdev(adapter->netdev); | |
3502 | } else { | |
3503 | DPRINTK(PROBE, INFO, "detected SFP+: %d\n", | |
3504 | hw->phy.sfp_type); | |
3505 | } | |
3506 | /* don't need this routine any more */ | |
3507 | clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); | |
3508 | } | |
3509 | return; | |
3510 | reschedule: | |
3511 | if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state)) | |
3512 | mod_timer(&adapter->sfp_timer, | |
3513 | round_jiffies(jiffies + (2 * HZ))); | |
3514 | } | |
3515 | ||
9a799d71 AK |
3516 | /** |
3517 | * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter) | |
3518 | * @adapter: board private structure to initialize | |
3519 | * | |
3520 | * ixgbe_sw_init initializes the Adapter private data structure. | |
3521 | * Fields are initialized based on PCI device information and | |
3522 | * OS network device settings (MTU size). | |
3523 | **/ | |
3524 | static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter) | |
3525 | { | |
3526 | struct ixgbe_hw *hw = &adapter->hw; | |
3527 | struct pci_dev *pdev = adapter->pdev; | |
021230d4 | 3528 | unsigned int rss; |
7a6b6f51 | 3529 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
3530 | int j; |
3531 | struct tc_configuration *tc; | |
3532 | #endif | |
021230d4 | 3533 | |
c44ade9e JB |
3534 | /* PCI config space info */ |
3535 | ||
3536 | hw->vendor_id = pdev->vendor; | |
3537 | hw->device_id = pdev->device; | |
3538 | hw->revision_id = pdev->revision; | |
3539 | hw->subsystem_vendor_id = pdev->subsystem_vendor; | |
3540 | hw->subsystem_device_id = pdev->subsystem_device; | |
3541 | ||
021230d4 AV |
3542 | /* Set capability flags */ |
3543 | rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus()); | |
3544 | adapter->ring_feature[RING_F_RSS].indices = rss; | |
3545 | adapter->flags |= IXGBE_FLAG_RSS_ENABLED; | |
2f90b865 | 3546 | adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES; |
bf069c97 DS |
3547 | if (hw->mac.type == ixgbe_mac_82598EB) { |
3548 | if (hw->device_id == IXGBE_DEV_ID_82598AT) | |
3549 | adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE; | |
e8e26350 | 3550 | adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598; |
bf069c97 | 3551 | } else if (hw->mac.type == ixgbe_mac_82599EB) { |
e8e26350 | 3552 | adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599; |
f8212f97 AD |
3553 | adapter->flags |= IXGBE_FLAG_RSC_CAPABLE; |
3554 | adapter->flags |= IXGBE_FLAG_RSC_ENABLED; | |
eacd73f7 YZ |
3555 | #ifdef IXGBE_FCOE |
3556 | adapter->flags |= IXGBE_FLAG_FCOE_ENABLED; | |
0331a832 | 3557 | adapter->ring_feature[RING_F_FCOE].indices = IXGBE_FCRETA_SIZE; |
eacd73f7 | 3558 | #endif /* IXGBE_FCOE */ |
f8212f97 | 3559 | } |
2f90b865 | 3560 | |
7a6b6f51 | 3561 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
3562 | /* Configure DCB traffic classes */ |
3563 | for (j = 0; j < MAX_TRAFFIC_CLASS; j++) { | |
3564 | tc = &adapter->dcb_cfg.tc_config[j]; | |
3565 | tc->path[DCB_TX_CONFIG].bwg_id = 0; | |
3566 | tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1); | |
3567 | tc->path[DCB_RX_CONFIG].bwg_id = 0; | |
3568 | tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1); | |
3569 | tc->dcb_pfc = pfc_disabled; | |
3570 | } | |
3571 | adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100; | |
3572 | adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100; | |
3573 | adapter->dcb_cfg.rx_pba_cfg = pba_equal; | |
264857b8 | 3574 | adapter->dcb_cfg.pfc_mode_enable = false; |
2f90b865 AD |
3575 | adapter->dcb_cfg.round_robin_enable = false; |
3576 | adapter->dcb_set_bitmap = 0x00; | |
3577 | ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg, | |
3578 | adapter->ring_feature[RING_F_DCB].indices); | |
3579 | ||
3580 | #endif | |
9a799d71 AK |
3581 | |
3582 | /* default flow control settings */ | |
cd7664f6 | 3583 | hw->fc.requested_mode = ixgbe_fc_full; |
71fd570b | 3584 | hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */ |
264857b8 PWJ |
3585 | #ifdef CONFIG_DCB |
3586 | adapter->last_lfc_mode = hw->fc.current_mode; | |
3587 | #endif | |
2b9ade93 JB |
3588 | hw->fc.high_water = IXGBE_DEFAULT_FCRTH; |
3589 | hw->fc.low_water = IXGBE_DEFAULT_FCRTL; | |
3590 | hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE; | |
3591 | hw->fc.send_xon = true; | |
71fd570b | 3592 | hw->fc.disable_fc_autoneg = false; |
9a799d71 | 3593 | |
30efa5a3 JB |
3594 | /* enable itr by default in dynamic mode */ |
3595 | adapter->itr_setting = 1; | |
3596 | adapter->eitr_param = 20000; | |
3597 | ||
3598 | /* set defaults for eitr in MegaBytes */ | |
3599 | adapter->eitr_low = 10; | |
3600 | adapter->eitr_high = 20; | |
3601 | ||
3602 | /* set default ring sizes */ | |
3603 | adapter->tx_ring_count = IXGBE_DEFAULT_TXD; | |
3604 | adapter->rx_ring_count = IXGBE_DEFAULT_RXD; | |
3605 | ||
9a799d71 | 3606 | /* initialize eeprom parameters */ |
c44ade9e | 3607 | if (ixgbe_init_eeprom_params_generic(hw)) { |
9a799d71 AK |
3608 | dev_err(&pdev->dev, "EEPROM initialization failed\n"); |
3609 | return -EIO; | |
3610 | } | |
3611 | ||
021230d4 | 3612 | /* enable rx csum by default */ |
9a799d71 AK |
3613 | adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED; |
3614 | ||
9a799d71 AK |
3615 | set_bit(__IXGBE_DOWN, &adapter->state); |
3616 | ||
3617 | return 0; | |
3618 | } | |
3619 | ||
3620 | /** | |
3621 | * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors) | |
3622 | * @adapter: board private structure | |
3a581073 | 3623 | * @tx_ring: tx descriptor ring (for a specific queue) to setup |
9a799d71 AK |
3624 | * |
3625 | * Return 0 on success, negative on failure | |
3626 | **/ | |
3627 | int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter, | |
e01c31a5 | 3628 | struct ixgbe_ring *tx_ring) |
9a799d71 AK |
3629 | { |
3630 | struct pci_dev *pdev = adapter->pdev; | |
3631 | int size; | |
3632 | ||
3a581073 JB |
3633 | size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; |
3634 | tx_ring->tx_buffer_info = vmalloc(size); | |
e01c31a5 JB |
3635 | if (!tx_ring->tx_buffer_info) |
3636 | goto err; | |
3a581073 | 3637 | memset(tx_ring->tx_buffer_info, 0, size); |
9a799d71 AK |
3638 | |
3639 | /* round up to nearest 4K */ | |
12207e49 | 3640 | tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc); |
3a581073 | 3641 | tx_ring->size = ALIGN(tx_ring->size, 4096); |
9a799d71 | 3642 | |
3a581073 JB |
3643 | tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size, |
3644 | &tx_ring->dma); | |
e01c31a5 JB |
3645 | if (!tx_ring->desc) |
3646 | goto err; | |
9a799d71 | 3647 | |
3a581073 JB |
3648 | tx_ring->next_to_use = 0; |
3649 | tx_ring->next_to_clean = 0; | |
3650 | tx_ring->work_limit = tx_ring->count; | |
9a799d71 | 3651 | return 0; |
e01c31a5 JB |
3652 | |
3653 | err: | |
3654 | vfree(tx_ring->tx_buffer_info); | |
3655 | tx_ring->tx_buffer_info = NULL; | |
3656 | DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit " | |
3657 | "descriptor ring\n"); | |
3658 | return -ENOMEM; | |
9a799d71 AK |
3659 | } |
3660 | ||
69888674 AD |
3661 | /** |
3662 | * ixgbe_setup_all_tx_resources - allocate all queues Tx resources | |
3663 | * @adapter: board private structure | |
3664 | * | |
3665 | * If this function returns with an error, then it's possible one or | |
3666 | * more of the rings is populated (while the rest are not). It is the | |
3667 | * callers duty to clean those orphaned rings. | |
3668 | * | |
3669 | * Return 0 on success, negative on failure | |
3670 | **/ | |
3671 | static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter) | |
3672 | { | |
3673 | int i, err = 0; | |
3674 | ||
3675 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
3676 | err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]); | |
3677 | if (!err) | |
3678 | continue; | |
3679 | DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i); | |
3680 | break; | |
3681 | } | |
3682 | ||
3683 | return err; | |
3684 | } | |
3685 | ||
9a799d71 AK |
3686 | /** |
3687 | * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors) | |
3688 | * @adapter: board private structure | |
3a581073 | 3689 | * @rx_ring: rx descriptor ring (for a specific queue) to setup |
9a799d71 AK |
3690 | * |
3691 | * Returns 0 on success, negative on failure | |
3692 | **/ | |
3693 | int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter, | |
b4617240 | 3694 | struct ixgbe_ring *rx_ring) |
9a799d71 AK |
3695 | { |
3696 | struct pci_dev *pdev = adapter->pdev; | |
021230d4 | 3697 | int size; |
9a799d71 | 3698 | |
3a581073 JB |
3699 | size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; |
3700 | rx_ring->rx_buffer_info = vmalloc(size); | |
3701 | if (!rx_ring->rx_buffer_info) { | |
9a799d71 | 3702 | DPRINTK(PROBE, ERR, |
b4617240 | 3703 | "vmalloc allocation failed for the rx desc ring\n"); |
177db6ff | 3704 | goto alloc_failed; |
9a799d71 | 3705 | } |
3a581073 | 3706 | memset(rx_ring->rx_buffer_info, 0, size); |
9a799d71 | 3707 | |
9a799d71 | 3708 | /* Round up to nearest 4K */ |
3a581073 JB |
3709 | rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); |
3710 | rx_ring->size = ALIGN(rx_ring->size, 4096); | |
9a799d71 | 3711 | |
3a581073 | 3712 | rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma); |
9a799d71 | 3713 | |
3a581073 | 3714 | if (!rx_ring->desc) { |
9a799d71 | 3715 | DPRINTK(PROBE, ERR, |
b4617240 | 3716 | "Memory allocation failed for the rx desc ring\n"); |
3a581073 | 3717 | vfree(rx_ring->rx_buffer_info); |
177db6ff | 3718 | goto alloc_failed; |
9a799d71 AK |
3719 | } |
3720 | ||
3a581073 JB |
3721 | rx_ring->next_to_clean = 0; |
3722 | rx_ring->next_to_use = 0; | |
9a799d71 AK |
3723 | |
3724 | return 0; | |
177db6ff MC |
3725 | |
3726 | alloc_failed: | |
177db6ff | 3727 | return -ENOMEM; |
9a799d71 AK |
3728 | } |
3729 | ||
69888674 AD |
3730 | /** |
3731 | * ixgbe_setup_all_rx_resources - allocate all queues Rx resources | |
3732 | * @adapter: board private structure | |
3733 | * | |
3734 | * If this function returns with an error, then it's possible one or | |
3735 | * more of the rings is populated (while the rest are not). It is the | |
3736 | * callers duty to clean those orphaned rings. | |
3737 | * | |
3738 | * Return 0 on success, negative on failure | |
3739 | **/ | |
3740 | ||
3741 | static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter) | |
3742 | { | |
3743 | int i, err = 0; | |
3744 | ||
3745 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
3746 | err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]); | |
3747 | if (!err) | |
3748 | continue; | |
3749 | DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i); | |
3750 | break; | |
3751 | } | |
3752 | ||
3753 | return err; | |
3754 | } | |
3755 | ||
9a799d71 AK |
3756 | /** |
3757 | * ixgbe_free_tx_resources - Free Tx Resources per Queue | |
3758 | * @adapter: board private structure | |
3759 | * @tx_ring: Tx descriptor ring for a specific queue | |
3760 | * | |
3761 | * Free all transmit software resources | |
3762 | **/ | |
c431f97e JB |
3763 | void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter, |
3764 | struct ixgbe_ring *tx_ring) | |
9a799d71 AK |
3765 | { |
3766 | struct pci_dev *pdev = adapter->pdev; | |
3767 | ||
3768 | ixgbe_clean_tx_ring(adapter, tx_ring); | |
3769 | ||
3770 | vfree(tx_ring->tx_buffer_info); | |
3771 | tx_ring->tx_buffer_info = NULL; | |
3772 | ||
3773 | pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma); | |
3774 | ||
3775 | tx_ring->desc = NULL; | |
3776 | } | |
3777 | ||
3778 | /** | |
3779 | * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues | |
3780 | * @adapter: board private structure | |
3781 | * | |
3782 | * Free all transmit software resources | |
3783 | **/ | |
3784 | static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter) | |
3785 | { | |
3786 | int i; | |
3787 | ||
3788 | for (i = 0; i < adapter->num_tx_queues; i++) | |
9891ca7c JB |
3789 | if (adapter->tx_ring[i].desc) |
3790 | ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]); | |
9a799d71 AK |
3791 | } |
3792 | ||
3793 | /** | |
b4617240 | 3794 | * ixgbe_free_rx_resources - Free Rx Resources |
9a799d71 AK |
3795 | * @adapter: board private structure |
3796 | * @rx_ring: ring to clean the resources from | |
3797 | * | |
3798 | * Free all receive software resources | |
3799 | **/ | |
c431f97e JB |
3800 | void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter, |
3801 | struct ixgbe_ring *rx_ring) | |
9a799d71 AK |
3802 | { |
3803 | struct pci_dev *pdev = adapter->pdev; | |
3804 | ||
3805 | ixgbe_clean_rx_ring(adapter, rx_ring); | |
3806 | ||
3807 | vfree(rx_ring->rx_buffer_info); | |
3808 | rx_ring->rx_buffer_info = NULL; | |
3809 | ||
3810 | pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma); | |
3811 | ||
3812 | rx_ring->desc = NULL; | |
3813 | } | |
3814 | ||
3815 | /** | |
3816 | * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues | |
3817 | * @adapter: board private structure | |
3818 | * | |
3819 | * Free all receive software resources | |
3820 | **/ | |
3821 | static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter) | |
3822 | { | |
3823 | int i; | |
3824 | ||
3825 | for (i = 0; i < adapter->num_rx_queues; i++) | |
9891ca7c JB |
3826 | if (adapter->rx_ring[i].desc) |
3827 | ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]); | |
9a799d71 AK |
3828 | } |
3829 | ||
9a799d71 AK |
3830 | /** |
3831 | * ixgbe_change_mtu - Change the Maximum Transfer Unit | |
3832 | * @netdev: network interface device structure | |
3833 | * @new_mtu: new value for maximum frame size | |
3834 | * | |
3835 | * Returns 0 on success, negative on failure | |
3836 | **/ | |
3837 | static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu) | |
3838 | { | |
3839 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3840 | int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; | |
3841 | ||
42c783c5 JB |
3842 | /* MTU < 68 is an error and causes problems on some kernels */ |
3843 | if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE)) | |
9a799d71 AK |
3844 | return -EINVAL; |
3845 | ||
021230d4 | 3846 | DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n", |
b4617240 | 3847 | netdev->mtu, new_mtu); |
021230d4 | 3848 | /* must set new MTU before calling down or up */ |
9a799d71 AK |
3849 | netdev->mtu = new_mtu; |
3850 | ||
d4f80882 AV |
3851 | if (netif_running(netdev)) |
3852 | ixgbe_reinit_locked(adapter); | |
9a799d71 AK |
3853 | |
3854 | return 0; | |
3855 | } | |
3856 | ||
3857 | /** | |
3858 | * ixgbe_open - Called when a network interface is made active | |
3859 | * @netdev: network interface device structure | |
3860 | * | |
3861 | * Returns 0 on success, negative value on failure | |
3862 | * | |
3863 | * The open entry point is called when a network interface is made | |
3864 | * active by the system (IFF_UP). At this point all resources needed | |
3865 | * for transmit and receive operations are allocated, the interrupt | |
3866 | * handler is registered with the OS, the watchdog timer is started, | |
3867 | * and the stack is notified that the interface is ready. | |
3868 | **/ | |
3869 | static int ixgbe_open(struct net_device *netdev) | |
3870 | { | |
3871 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3872 | int err; | |
4bebfaa5 AK |
3873 | |
3874 | /* disallow open during test */ | |
3875 | if (test_bit(__IXGBE_TESTING, &adapter->state)) | |
3876 | return -EBUSY; | |
9a799d71 | 3877 | |
54386467 JB |
3878 | netif_carrier_off(netdev); |
3879 | ||
9a799d71 AK |
3880 | /* allocate transmit descriptors */ |
3881 | err = ixgbe_setup_all_tx_resources(adapter); | |
3882 | if (err) | |
3883 | goto err_setup_tx; | |
3884 | ||
9a799d71 AK |
3885 | /* allocate receive descriptors */ |
3886 | err = ixgbe_setup_all_rx_resources(adapter); | |
3887 | if (err) | |
3888 | goto err_setup_rx; | |
3889 | ||
3890 | ixgbe_configure(adapter); | |
3891 | ||
021230d4 | 3892 | err = ixgbe_request_irq(adapter); |
9a799d71 AK |
3893 | if (err) |
3894 | goto err_req_irq; | |
3895 | ||
9a799d71 AK |
3896 | err = ixgbe_up_complete(adapter); |
3897 | if (err) | |
3898 | goto err_up; | |
3899 | ||
d55b53ff JK |
3900 | netif_tx_start_all_queues(netdev); |
3901 | ||
9a799d71 AK |
3902 | return 0; |
3903 | ||
3904 | err_up: | |
5eba3699 | 3905 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
3906 | ixgbe_free_irq(adapter); |
3907 | err_req_irq: | |
9a799d71 | 3908 | err_setup_rx: |
a20a1199 | 3909 | ixgbe_free_all_rx_resources(adapter); |
9a799d71 | 3910 | err_setup_tx: |
a20a1199 | 3911 | ixgbe_free_all_tx_resources(adapter); |
9a799d71 AK |
3912 | ixgbe_reset(adapter); |
3913 | ||
3914 | return err; | |
3915 | } | |
3916 | ||
3917 | /** | |
3918 | * ixgbe_close - Disables a network interface | |
3919 | * @netdev: network interface device structure | |
3920 | * | |
3921 | * Returns 0, this is not allowed to fail | |
3922 | * | |
3923 | * The close entry point is called when an interface is de-activated | |
3924 | * by the OS. The hardware is still under the drivers control, but | |
3925 | * needs to be disabled. A global MAC reset is issued to stop the | |
3926 | * hardware, and all transmit and receive resources are freed. | |
3927 | **/ | |
3928 | static int ixgbe_close(struct net_device *netdev) | |
3929 | { | |
3930 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
9a799d71 AK |
3931 | |
3932 | ixgbe_down(adapter); | |
3933 | ixgbe_free_irq(adapter); | |
3934 | ||
3935 | ixgbe_free_all_tx_resources(adapter); | |
3936 | ixgbe_free_all_rx_resources(adapter); | |
3937 | ||
5eba3699 | 3938 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
3939 | |
3940 | return 0; | |
3941 | } | |
3942 | ||
b3c8b4ba AD |
3943 | #ifdef CONFIG_PM |
3944 | static int ixgbe_resume(struct pci_dev *pdev) | |
3945 | { | |
3946 | struct net_device *netdev = pci_get_drvdata(pdev); | |
3947 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3948 | u32 err; | |
3949 | ||
3950 | pci_set_power_state(pdev, PCI_D0); | |
3951 | pci_restore_state(pdev); | |
9ce77666 | 3952 | |
3953 | err = pci_enable_device_mem(pdev); | |
b3c8b4ba | 3954 | if (err) { |
69888674 | 3955 | printk(KERN_ERR "ixgbe: Cannot enable PCI device from " |
b3c8b4ba AD |
3956 | "suspend\n"); |
3957 | return err; | |
3958 | } | |
3959 | pci_set_master(pdev); | |
3960 | ||
dd4d8ca6 | 3961 | pci_wake_from_d3(pdev, false); |
b3c8b4ba AD |
3962 | |
3963 | err = ixgbe_init_interrupt_scheme(adapter); | |
3964 | if (err) { | |
3965 | printk(KERN_ERR "ixgbe: Cannot initialize interrupts for " | |
3966 | "device\n"); | |
3967 | return err; | |
3968 | } | |
3969 | ||
b3c8b4ba AD |
3970 | ixgbe_reset(adapter); |
3971 | ||
495dce12 WJP |
3972 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
3973 | ||
b3c8b4ba AD |
3974 | if (netif_running(netdev)) { |
3975 | err = ixgbe_open(adapter->netdev); | |
3976 | if (err) | |
3977 | return err; | |
3978 | } | |
3979 | ||
3980 | netif_device_attach(netdev); | |
3981 | ||
3982 | return 0; | |
3983 | } | |
b3c8b4ba | 3984 | #endif /* CONFIG_PM */ |
9d8d05ae RW |
3985 | |
3986 | static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake) | |
b3c8b4ba AD |
3987 | { |
3988 | struct net_device *netdev = pci_get_drvdata(pdev); | |
3989 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
e8e26350 PW |
3990 | struct ixgbe_hw *hw = &adapter->hw; |
3991 | u32 ctrl, fctrl; | |
3992 | u32 wufc = adapter->wol; | |
b3c8b4ba AD |
3993 | #ifdef CONFIG_PM |
3994 | int retval = 0; | |
3995 | #endif | |
3996 | ||
3997 | netif_device_detach(netdev); | |
3998 | ||
3999 | if (netif_running(netdev)) { | |
4000 | ixgbe_down(adapter); | |
4001 | ixgbe_free_irq(adapter); | |
4002 | ixgbe_free_all_tx_resources(adapter); | |
4003 | ixgbe_free_all_rx_resources(adapter); | |
4004 | } | |
7a921c93 | 4005 | ixgbe_clear_interrupt_scheme(adapter); |
b3c8b4ba AD |
4006 | |
4007 | #ifdef CONFIG_PM | |
4008 | retval = pci_save_state(pdev); | |
4009 | if (retval) | |
4010 | return retval; | |
4df10466 | 4011 | |
b3c8b4ba | 4012 | #endif |
e8e26350 PW |
4013 | if (wufc) { |
4014 | ixgbe_set_rx_mode(netdev); | |
b3c8b4ba | 4015 | |
e8e26350 PW |
4016 | /* turn on all-multi mode if wake on multicast is enabled */ |
4017 | if (wufc & IXGBE_WUFC_MC) { | |
4018 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
4019 | fctrl |= IXGBE_FCTRL_MPE; | |
4020 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); | |
4021 | } | |
4022 | ||
4023 | ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); | |
4024 | ctrl |= IXGBE_CTRL_GIO_DIS; | |
4025 | IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); | |
4026 | ||
4027 | IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc); | |
4028 | } else { | |
4029 | IXGBE_WRITE_REG(hw, IXGBE_WUC, 0); | |
4030 | IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); | |
4031 | } | |
4032 | ||
dd4d8ca6 DS |
4033 | if (wufc && hw->mac.type == ixgbe_mac_82599EB) |
4034 | pci_wake_from_d3(pdev, true); | |
4035 | else | |
4036 | pci_wake_from_d3(pdev, false); | |
b3c8b4ba | 4037 | |
9d8d05ae RW |
4038 | *enable_wake = !!wufc; |
4039 | ||
b3c8b4ba AD |
4040 | ixgbe_release_hw_control(adapter); |
4041 | ||
4042 | pci_disable_device(pdev); | |
4043 | ||
9d8d05ae RW |
4044 | return 0; |
4045 | } | |
4046 | ||
4047 | #ifdef CONFIG_PM | |
4048 | static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state) | |
4049 | { | |
4050 | int retval; | |
4051 | bool wake; | |
4052 | ||
4053 | retval = __ixgbe_shutdown(pdev, &wake); | |
4054 | if (retval) | |
4055 | return retval; | |
4056 | ||
4057 | if (wake) { | |
4058 | pci_prepare_to_sleep(pdev); | |
4059 | } else { | |
4060 | pci_wake_from_d3(pdev, false); | |
4061 | pci_set_power_state(pdev, PCI_D3hot); | |
4062 | } | |
b3c8b4ba AD |
4063 | |
4064 | return 0; | |
4065 | } | |
9d8d05ae | 4066 | #endif /* CONFIG_PM */ |
b3c8b4ba AD |
4067 | |
4068 | static void ixgbe_shutdown(struct pci_dev *pdev) | |
4069 | { | |
9d8d05ae RW |
4070 | bool wake; |
4071 | ||
4072 | __ixgbe_shutdown(pdev, &wake); | |
4073 | ||
4074 | if (system_state == SYSTEM_POWER_OFF) { | |
4075 | pci_wake_from_d3(pdev, wake); | |
4076 | pci_set_power_state(pdev, PCI_D3hot); | |
4077 | } | |
b3c8b4ba AD |
4078 | } |
4079 | ||
9a799d71 AK |
4080 | /** |
4081 | * ixgbe_update_stats - Update the board statistics counters. | |
4082 | * @adapter: board private structure | |
4083 | **/ | |
4084 | void ixgbe_update_stats(struct ixgbe_adapter *adapter) | |
4085 | { | |
4086 | struct ixgbe_hw *hw = &adapter->hw; | |
6f11eef7 AV |
4087 | u64 total_mpc = 0; |
4088 | u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot; | |
9a799d71 | 4089 | |
d51019a4 | 4090 | if (hw->mac.type == ixgbe_mac_82599EB) { |
f8212f97 | 4091 | u64 rsc_count = 0; |
d51019a4 PW |
4092 | for (i = 0; i < 16; i++) |
4093 | adapter->hw_rx_no_dma_resources += | |
4094 | IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); | |
f8212f97 AD |
4095 | for (i = 0; i < adapter->num_rx_queues; i++) |
4096 | rsc_count += adapter->rx_ring[i].rsc_count; | |
4097 | adapter->rsc_count = rsc_count; | |
d51019a4 PW |
4098 | } |
4099 | ||
9a799d71 | 4100 | adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); |
6f11eef7 AV |
4101 | for (i = 0; i < 8; i++) { |
4102 | /* for packet buffers not used, the register should read 0 */ | |
4103 | mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i)); | |
4104 | missed_rx += mpc; | |
4105 | adapter->stats.mpc[i] += mpc; | |
4106 | total_mpc += adapter->stats.mpc[i]; | |
e8e26350 PW |
4107 | if (hw->mac.type == ixgbe_mac_82598EB) |
4108 | adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); | |
2f90b865 AD |
4109 | adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); |
4110 | adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i)); | |
4111 | adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); | |
4112 | adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i)); | |
e8e26350 PW |
4113 | if (hw->mac.type == ixgbe_mac_82599EB) { |
4114 | adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw, | |
4115 | IXGBE_PXONRXCNT(i)); | |
4116 | adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw, | |
4117 | IXGBE_PXOFFRXCNT(i)); | |
4118 | adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); | |
e8e26350 PW |
4119 | } else { |
4120 | adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw, | |
4121 | IXGBE_PXONRXC(i)); | |
4122 | adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw, | |
4123 | IXGBE_PXOFFRXC(i)); | |
4124 | } | |
2f90b865 AD |
4125 | adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw, |
4126 | IXGBE_PXONTXC(i)); | |
2f90b865 | 4127 | adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw, |
e8e26350 | 4128 | IXGBE_PXOFFTXC(i)); |
6f11eef7 AV |
4129 | } |
4130 | adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); | |
4131 | /* work around hardware counting issue */ | |
4132 | adapter->stats.gprc -= missed_rx; | |
4133 | ||
4134 | /* 82598 hardware only has a 32 bit counter in the high register */ | |
e8e26350 PW |
4135 | if (hw->mac.type == ixgbe_mac_82599EB) { |
4136 | adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); | |
4137 | IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */ | |
4138 | adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); | |
4139 | IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */ | |
4140 | adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL); | |
4141 | IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */ | |
4142 | adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); | |
4143 | adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); | |
6d45522c YZ |
4144 | #ifdef IXGBE_FCOE |
4145 | adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); | |
4146 | adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); | |
4147 | adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); | |
4148 | adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); | |
4149 | adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); | |
4150 | adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); | |
4151 | #endif /* IXGBE_FCOE */ | |
e8e26350 PW |
4152 | } else { |
4153 | adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); | |
4154 | adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); | |
4155 | adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); | |
4156 | adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); | |
4157 | adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH); | |
4158 | } | |
9a799d71 AK |
4159 | bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); |
4160 | adapter->stats.bprc += bprc; | |
4161 | adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); | |
e8e26350 PW |
4162 | if (hw->mac.type == ixgbe_mac_82598EB) |
4163 | adapter->stats.mprc -= bprc; | |
9a799d71 AK |
4164 | adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC); |
4165 | adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); | |
4166 | adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); | |
4167 | adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); | |
4168 | adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); | |
4169 | adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); | |
4170 | adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); | |
9a799d71 | 4171 | adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); |
6f11eef7 AV |
4172 | lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); |
4173 | adapter->stats.lxontxc += lxon; | |
4174 | lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); | |
4175 | adapter->stats.lxofftxc += lxoff; | |
9a799d71 AK |
4176 | adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC); |
4177 | adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); | |
6f11eef7 AV |
4178 | adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); |
4179 | /* | |
4180 | * 82598 errata - tx of flow control packets is included in tx counters | |
4181 | */ | |
4182 | xon_off_tot = lxon + lxoff; | |
4183 | adapter->stats.gptc -= xon_off_tot; | |
4184 | adapter->stats.mptc -= xon_off_tot; | |
4185 | adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN)); | |
9a799d71 AK |
4186 | adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC); |
4187 | adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC); | |
4188 | adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC); | |
9a799d71 AK |
4189 | adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR); |
4190 | adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); | |
6f11eef7 | 4191 | adapter->stats.ptc64 -= xon_off_tot; |
9a799d71 AK |
4192 | adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); |
4193 | adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); | |
4194 | adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); | |
4195 | adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); | |
4196 | adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); | |
9a799d71 AK |
4197 | adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); |
4198 | ||
4199 | /* Fill out the OS statistics structure */ | |
9a799d71 AK |
4200 | adapter->net_stats.multicast = adapter->stats.mprc; |
4201 | ||
4202 | /* Rx Errors */ | |
4203 | adapter->net_stats.rx_errors = adapter->stats.crcerrs + | |
b4617240 | 4204 | adapter->stats.rlec; |
9a799d71 AK |
4205 | adapter->net_stats.rx_dropped = 0; |
4206 | adapter->net_stats.rx_length_errors = adapter->stats.rlec; | |
4207 | adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs; | |
6f11eef7 | 4208 | adapter->net_stats.rx_missed_errors = total_mpc; |
9a799d71 AK |
4209 | } |
4210 | ||
4211 | /** | |
4212 | * ixgbe_watchdog - Timer Call-back | |
4213 | * @data: pointer to adapter cast into an unsigned long | |
4214 | **/ | |
4215 | static void ixgbe_watchdog(unsigned long data) | |
4216 | { | |
4217 | struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data; | |
cf8280ee JB |
4218 | struct ixgbe_hw *hw = &adapter->hw; |
4219 | ||
4220 | /* Do the watchdog outside of interrupt context due to the lovely | |
4221 | * delays that some of the newer hardware requires */ | |
4222 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { | |
22d5a71b JB |
4223 | u64 eics = 0; |
4224 | int i; | |
4225 | ||
4226 | for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) | |
c9c7d2e5 | 4227 | eics |= ((u64)1 << i); |
22d5a71b | 4228 | |
cf8280ee | 4229 | /* Cause software interrupt to ensure rx rings are cleaned */ |
22d5a71b JB |
4230 | switch (hw->mac.type) { |
4231 | case ixgbe_mac_82598EB: | |
4232 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
4233 | IXGBE_WRITE_REG(hw, IXGBE_EICS, (u32)eics); | |
4234 | } else { | |
4235 | /* | |
4236 | * for legacy and MSI interrupts don't set any | |
4237 | * bits that are enabled for EIAM, because this | |
4238 | * operation would set *both* EIMS and EICS for | |
4239 | * any bit in EIAM | |
4240 | */ | |
4241 | IXGBE_WRITE_REG(hw, IXGBE_EICS, | |
4242 | (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); | |
4243 | } | |
4244 | break; | |
4245 | case ixgbe_mac_82599EB: | |
4246 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
835462fc NS |
4247 | IXGBE_WRITE_REG(hw, IXGBE_EICS_EX(0), |
4248 | (u32)(eics & 0xFFFFFFFF)); | |
22d5a71b | 4249 | IXGBE_WRITE_REG(hw, IXGBE_EICS_EX(1), |
22d5a71b JB |
4250 | (u32)(eics >> 32)); |
4251 | } else { | |
4252 | /* | |
4253 | * for legacy and MSI interrupts don't set any | |
4254 | * bits that are enabled for EIAM, because this | |
4255 | * operation would set *both* EIMS and EICS for | |
4256 | * any bit in EIAM | |
4257 | */ | |
4258 | IXGBE_WRITE_REG(hw, IXGBE_EICS, | |
4259 | (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); | |
4260 | } | |
4261 | break; | |
4262 | default: | |
4263 | break; | |
cf8280ee JB |
4264 | } |
4265 | /* Reset the timer */ | |
4266 | mod_timer(&adapter->watchdog_timer, | |
4267 | round_jiffies(jiffies + 2 * HZ)); | |
4268 | } | |
9a799d71 | 4269 | |
cf8280ee JB |
4270 | schedule_work(&adapter->watchdog_task); |
4271 | } | |
4272 | ||
e8e26350 PW |
4273 | /** |
4274 | * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber | |
4275 | * @work: pointer to work_struct containing our data | |
4276 | **/ | |
4277 | static void ixgbe_multispeed_fiber_task(struct work_struct *work) | |
4278 | { | |
4279 | struct ixgbe_adapter *adapter = container_of(work, | |
4280 | struct ixgbe_adapter, | |
4281 | multispeed_fiber_task); | |
4282 | struct ixgbe_hw *hw = &adapter->hw; | |
4283 | u32 autoneg; | |
4284 | ||
4285 | adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK; | |
4286 | if (hw->mac.ops.get_link_capabilities) | |
4287 | hw->mac.ops.get_link_capabilities(hw, &autoneg, | |
4288 | &hw->mac.autoneg); | |
4289 | if (hw->mac.ops.setup_link_speed) | |
4290 | hw->mac.ops.setup_link_speed(hw, autoneg, true, true); | |
4291 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; | |
4292 | adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK; | |
4293 | } | |
4294 | ||
4295 | /** | |
4296 | * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module | |
4297 | * @work: pointer to work_struct containing our data | |
4298 | **/ | |
4299 | static void ixgbe_sfp_config_module_task(struct work_struct *work) | |
4300 | { | |
4301 | struct ixgbe_adapter *adapter = container_of(work, | |
4302 | struct ixgbe_adapter, | |
4303 | sfp_config_module_task); | |
4304 | struct ixgbe_hw *hw = &adapter->hw; | |
4305 | u32 err; | |
4306 | ||
4307 | adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK; | |
4308 | err = hw->phy.ops.identify_sfp(hw); | |
4309 | if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
4310 | DPRINTK(PROBE, ERR, "PHY not supported on this NIC %d\n", err); | |
4311 | ixgbe_down(adapter); | |
4312 | return; | |
4313 | } | |
4314 | hw->mac.ops.setup_sfp(hw); | |
4315 | ||
8d1c3c07 | 4316 | if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK)) |
e8e26350 PW |
4317 | /* This will also work for DA Twinax connections */ |
4318 | schedule_work(&adapter->multispeed_fiber_task); | |
4319 | adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK; | |
4320 | } | |
4321 | ||
cf8280ee | 4322 | /** |
69888674 AD |
4323 | * ixgbe_watchdog_task - worker thread to bring link up |
4324 | * @work: pointer to work_struct containing our data | |
cf8280ee JB |
4325 | **/ |
4326 | static void ixgbe_watchdog_task(struct work_struct *work) | |
4327 | { | |
4328 | struct ixgbe_adapter *adapter = container_of(work, | |
4329 | struct ixgbe_adapter, | |
4330 | watchdog_task); | |
4331 | struct net_device *netdev = adapter->netdev; | |
4332 | struct ixgbe_hw *hw = &adapter->hw; | |
4333 | u32 link_speed = adapter->link_speed; | |
4334 | bool link_up = adapter->link_up; | |
bc59fcda NS |
4335 | int i; |
4336 | struct ixgbe_ring *tx_ring; | |
4337 | int some_tx_pending = 0; | |
cf8280ee JB |
4338 | |
4339 | adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK; | |
4340 | ||
4341 | if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) { | |
4342 | hw->mac.ops.check_link(hw, &link_speed, &link_up, false); | |
264857b8 PWJ |
4343 | if (link_up) { |
4344 | #ifdef CONFIG_DCB | |
4345 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
4346 | for (i = 0; i < MAX_TRAFFIC_CLASS; i++) | |
620fa036 | 4347 | hw->mac.ops.fc_enable(hw, i); |
264857b8 | 4348 | } else { |
620fa036 | 4349 | hw->mac.ops.fc_enable(hw, 0); |
264857b8 PWJ |
4350 | } |
4351 | #else | |
620fa036 | 4352 | hw->mac.ops.fc_enable(hw, 0); |
264857b8 PWJ |
4353 | #endif |
4354 | } | |
4355 | ||
cf8280ee JB |
4356 | if (link_up || |
4357 | time_after(jiffies, (adapter->link_check_timeout + | |
4358 | IXGBE_TRY_LINK_TIMEOUT))) { | |
cf8280ee | 4359 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; |
264857b8 | 4360 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC); |
cf8280ee JB |
4361 | } |
4362 | adapter->link_up = link_up; | |
4363 | adapter->link_speed = link_speed; | |
4364 | } | |
9a799d71 AK |
4365 | |
4366 | if (link_up) { | |
4367 | if (!netif_carrier_ok(netdev)) { | |
e8e26350 PW |
4368 | bool flow_rx, flow_tx; |
4369 | ||
4370 | if (hw->mac.type == ixgbe_mac_82599EB) { | |
4371 | u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); | |
4372 | u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG); | |
4373 | flow_rx = (mflcn & IXGBE_MFLCN_RFCE); | |
4374 | flow_tx = (fccfg & IXGBE_FCCFG_TFCE_802_3X); | |
4375 | } else { | |
4376 | u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
4377 | u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS); | |
4378 | flow_rx = (frctl & IXGBE_FCTRL_RFCE); | |
4379 | flow_tx = (rmcs & IXGBE_RMCS_TFCE_802_3X); | |
4380 | } | |
4381 | ||
a46e534b JK |
4382 | printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, " |
4383 | "Flow Control: %s\n", | |
4384 | netdev->name, | |
4385 | (link_speed == IXGBE_LINK_SPEED_10GB_FULL ? | |
4386 | "10 Gbps" : | |
4387 | (link_speed == IXGBE_LINK_SPEED_1GB_FULL ? | |
4388 | "1 Gbps" : "unknown speed")), | |
e8e26350 PW |
4389 | ((flow_rx && flow_tx) ? "RX/TX" : |
4390 | (flow_rx ? "RX" : | |
4391 | (flow_tx ? "TX" : "None")))); | |
9a799d71 AK |
4392 | |
4393 | netif_carrier_on(netdev); | |
9a799d71 AK |
4394 | } else { |
4395 | /* Force detection of hung controller */ | |
4396 | adapter->detect_tx_hung = true; | |
4397 | } | |
4398 | } else { | |
cf8280ee JB |
4399 | adapter->link_up = false; |
4400 | adapter->link_speed = 0; | |
9a799d71 | 4401 | if (netif_carrier_ok(netdev)) { |
a46e534b JK |
4402 | printk(KERN_INFO "ixgbe: %s NIC Link is Down\n", |
4403 | netdev->name); | |
9a799d71 | 4404 | netif_carrier_off(netdev); |
9a799d71 AK |
4405 | } |
4406 | } | |
4407 | ||
bc59fcda NS |
4408 | if (!netif_carrier_ok(netdev)) { |
4409 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
4410 | tx_ring = &adapter->tx_ring[i]; | |
4411 | if (tx_ring->next_to_use != tx_ring->next_to_clean) { | |
4412 | some_tx_pending = 1; | |
4413 | break; | |
4414 | } | |
4415 | } | |
4416 | ||
4417 | if (some_tx_pending) { | |
4418 | /* We've lost link, so the controller stops DMA, | |
4419 | * but we've got queued Tx work that's never going | |
4420 | * to get done, so reset controller to flush Tx. | |
4421 | * (Do the reset outside of interrupt context). | |
4422 | */ | |
4423 | schedule_work(&adapter->reset_task); | |
4424 | } | |
4425 | } | |
4426 | ||
9a799d71 | 4427 | ixgbe_update_stats(adapter); |
cf8280ee | 4428 | adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK; |
9a799d71 AK |
4429 | } |
4430 | ||
9a799d71 | 4431 | static int ixgbe_tso(struct ixgbe_adapter *adapter, |
b4617240 PW |
4432 | struct ixgbe_ring *tx_ring, struct sk_buff *skb, |
4433 | u32 tx_flags, u8 *hdr_len) | |
9a799d71 AK |
4434 | { |
4435 | struct ixgbe_adv_tx_context_desc *context_desc; | |
4436 | unsigned int i; | |
4437 | int err; | |
4438 | struct ixgbe_tx_buffer *tx_buffer_info; | |
9f8cdf4f JB |
4439 | u32 vlan_macip_lens = 0, type_tucmd_mlhl; |
4440 | u32 mss_l4len_idx, l4len; | |
9a799d71 AK |
4441 | |
4442 | if (skb_is_gso(skb)) { | |
4443 | if (skb_header_cloned(skb)) { | |
4444 | err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); | |
4445 | if (err) | |
4446 | return err; | |
4447 | } | |
4448 | l4len = tcp_hdrlen(skb); | |
4449 | *hdr_len += l4len; | |
4450 | ||
8327d000 | 4451 | if (skb->protocol == htons(ETH_P_IP)) { |
9a799d71 AK |
4452 | struct iphdr *iph = ip_hdr(skb); |
4453 | iph->tot_len = 0; | |
4454 | iph->check = 0; | |
4455 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, | |
b4617240 PW |
4456 | iph->daddr, 0, |
4457 | IPPROTO_TCP, | |
4458 | 0); | |
9a799d71 AK |
4459 | adapter->hw_tso_ctxt++; |
4460 | } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) { | |
4461 | ipv6_hdr(skb)->payload_len = 0; | |
4462 | tcp_hdr(skb)->check = | |
4463 | ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, | |
b4617240 PW |
4464 | &ipv6_hdr(skb)->daddr, |
4465 | 0, IPPROTO_TCP, 0); | |
9a799d71 AK |
4466 | adapter->hw_tso6_ctxt++; |
4467 | } | |
4468 | ||
4469 | i = tx_ring->next_to_use; | |
4470 | ||
4471 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
4472 | context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i); | |
4473 | ||
4474 | /* VLAN MACLEN IPLEN */ | |
4475 | if (tx_flags & IXGBE_TX_FLAGS_VLAN) | |
4476 | vlan_macip_lens |= | |
4477 | (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK); | |
4478 | vlan_macip_lens |= ((skb_network_offset(skb)) << | |
b4617240 | 4479 | IXGBE_ADVTXD_MACLEN_SHIFT); |
9a799d71 AK |
4480 | *hdr_len += skb_network_offset(skb); |
4481 | vlan_macip_lens |= | |
4482 | (skb_transport_header(skb) - skb_network_header(skb)); | |
4483 | *hdr_len += | |
4484 | (skb_transport_header(skb) - skb_network_header(skb)); | |
4485 | context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); | |
4486 | context_desc->seqnum_seed = 0; | |
4487 | ||
4488 | /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ | |
9f8cdf4f | 4489 | type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT | |
b4617240 | 4490 | IXGBE_ADVTXD_DTYP_CTXT); |
9a799d71 | 4491 | |
8327d000 | 4492 | if (skb->protocol == htons(ETH_P_IP)) |
9a799d71 AK |
4493 | type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4; |
4494 | type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP; | |
4495 | context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl); | |
4496 | ||
4497 | /* MSS L4LEN IDX */ | |
9f8cdf4f | 4498 | mss_l4len_idx = |
9a799d71 AK |
4499 | (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT); |
4500 | mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT); | |
4eeae6fd PW |
4501 | /* use index 1 for TSO */ |
4502 | mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT); | |
9a799d71 AK |
4503 | context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); |
4504 | ||
4505 | tx_buffer_info->time_stamp = jiffies; | |
4506 | tx_buffer_info->next_to_watch = i; | |
4507 | ||
4508 | i++; | |
4509 | if (i == tx_ring->count) | |
4510 | i = 0; | |
4511 | tx_ring->next_to_use = i; | |
4512 | ||
4513 | return true; | |
4514 | } | |
4515 | return false; | |
4516 | } | |
4517 | ||
4518 | static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter, | |
b4617240 PW |
4519 | struct ixgbe_ring *tx_ring, |
4520 | struct sk_buff *skb, u32 tx_flags) | |
9a799d71 AK |
4521 | { |
4522 | struct ixgbe_adv_tx_context_desc *context_desc; | |
4523 | unsigned int i; | |
4524 | struct ixgbe_tx_buffer *tx_buffer_info; | |
4525 | u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0; | |
4526 | ||
4527 | if (skb->ip_summed == CHECKSUM_PARTIAL || | |
4528 | (tx_flags & IXGBE_TX_FLAGS_VLAN)) { | |
4529 | i = tx_ring->next_to_use; | |
4530 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
4531 | context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i); | |
4532 | ||
4533 | if (tx_flags & IXGBE_TX_FLAGS_VLAN) | |
4534 | vlan_macip_lens |= | |
4535 | (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK); | |
4536 | vlan_macip_lens |= (skb_network_offset(skb) << | |
b4617240 | 4537 | IXGBE_ADVTXD_MACLEN_SHIFT); |
9a799d71 AK |
4538 | if (skb->ip_summed == CHECKSUM_PARTIAL) |
4539 | vlan_macip_lens |= (skb_transport_header(skb) - | |
b4617240 | 4540 | skb_network_header(skb)); |
9a799d71 AK |
4541 | |
4542 | context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); | |
4543 | context_desc->seqnum_seed = 0; | |
4544 | ||
4545 | type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT | | |
b4617240 | 4546 | IXGBE_ADVTXD_DTYP_CTXT); |
9a799d71 AK |
4547 | |
4548 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
41825d71 | 4549 | switch (skb->protocol) { |
09640e63 | 4550 | case cpu_to_be16(ETH_P_IP): |
9a799d71 | 4551 | type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4; |
41825d71 AK |
4552 | if (ip_hdr(skb)->protocol == IPPROTO_TCP) |
4553 | type_tucmd_mlhl |= | |
b4617240 | 4554 | IXGBE_ADVTXD_TUCMD_L4T_TCP; |
45a5ead0 JB |
4555 | else if (ip_hdr(skb)->protocol == IPPROTO_SCTP) |
4556 | type_tucmd_mlhl |= | |
4557 | IXGBE_ADVTXD_TUCMD_L4T_SCTP; | |
41825d71 | 4558 | break; |
09640e63 | 4559 | case cpu_to_be16(ETH_P_IPV6): |
41825d71 AK |
4560 | /* XXX what about other V6 headers?? */ |
4561 | if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP) | |
4562 | type_tucmd_mlhl |= | |
b4617240 | 4563 | IXGBE_ADVTXD_TUCMD_L4T_TCP; |
45a5ead0 JB |
4564 | else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP) |
4565 | type_tucmd_mlhl |= | |
4566 | IXGBE_ADVTXD_TUCMD_L4T_SCTP; | |
41825d71 | 4567 | break; |
41825d71 AK |
4568 | default: |
4569 | if (unlikely(net_ratelimit())) { | |
4570 | DPRINTK(PROBE, WARNING, | |
4571 | "partial checksum but proto=%x!\n", | |
4572 | skb->protocol); | |
4573 | } | |
4574 | break; | |
4575 | } | |
9a799d71 AK |
4576 | } |
4577 | ||
4578 | context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl); | |
4eeae6fd | 4579 | /* use index zero for tx checksum offload */ |
9a799d71 AK |
4580 | context_desc->mss_l4len_idx = 0; |
4581 | ||
4582 | tx_buffer_info->time_stamp = jiffies; | |
4583 | tx_buffer_info->next_to_watch = i; | |
9f8cdf4f | 4584 | |
9a799d71 AK |
4585 | adapter->hw_csum_tx_good++; |
4586 | i++; | |
4587 | if (i == tx_ring->count) | |
4588 | i = 0; | |
4589 | tx_ring->next_to_use = i; | |
4590 | ||
4591 | return true; | |
4592 | } | |
9f8cdf4f | 4593 | |
9a799d71 AK |
4594 | return false; |
4595 | } | |
4596 | ||
4597 | static int ixgbe_tx_map(struct ixgbe_adapter *adapter, | |
b4617240 | 4598 | struct ixgbe_ring *tx_ring, |
eacd73f7 YZ |
4599 | struct sk_buff *skb, u32 tx_flags, |
4600 | unsigned int first) | |
9a799d71 AK |
4601 | { |
4602 | struct ixgbe_tx_buffer *tx_buffer_info; | |
eacd73f7 YZ |
4603 | unsigned int len; |
4604 | unsigned int total = skb->len; | |
9a799d71 AK |
4605 | unsigned int offset = 0, size, count = 0, i; |
4606 | unsigned int nr_frags = skb_shinfo(skb)->nr_frags; | |
4607 | unsigned int f; | |
44df32c5 | 4608 | dma_addr_t *map; |
9a799d71 AK |
4609 | |
4610 | i = tx_ring->next_to_use; | |
4611 | ||
44df32c5 AD |
4612 | if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) { |
4613 | dev_err(&adapter->pdev->dev, "TX DMA map failed\n"); | |
4614 | return 0; | |
4615 | } | |
4616 | ||
4617 | map = skb_shinfo(skb)->dma_maps; | |
4618 | ||
eacd73f7 YZ |
4619 | if (tx_flags & IXGBE_TX_FLAGS_FCOE) |
4620 | /* excluding fcoe_crc_eof for FCoE */ | |
4621 | total -= sizeof(struct fcoe_crc_eof); | |
4622 | ||
4623 | len = min(skb_headlen(skb), total); | |
9a799d71 AK |
4624 | while (len) { |
4625 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
4626 | size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD); | |
4627 | ||
4628 | tx_buffer_info->length = size; | |
44df32c5 | 4629 | tx_buffer_info->dma = map[0] + offset; |
9a799d71 AK |
4630 | tx_buffer_info->time_stamp = jiffies; |
4631 | tx_buffer_info->next_to_watch = i; | |
4632 | ||
4633 | len -= size; | |
eacd73f7 | 4634 | total -= size; |
9a799d71 AK |
4635 | offset += size; |
4636 | count++; | |
44df32c5 AD |
4637 | |
4638 | if (len) { | |
4639 | i++; | |
4640 | if (i == tx_ring->count) | |
4641 | i = 0; | |
4642 | } | |
9a799d71 AK |
4643 | } |
4644 | ||
4645 | for (f = 0; f < nr_frags; f++) { | |
4646 | struct skb_frag_struct *frag; | |
4647 | ||
4648 | frag = &skb_shinfo(skb)->frags[f]; | |
eacd73f7 | 4649 | len = min((unsigned int)frag->size, total); |
44df32c5 | 4650 | offset = 0; |
9a799d71 AK |
4651 | |
4652 | while (len) { | |
44df32c5 AD |
4653 | i++; |
4654 | if (i == tx_ring->count) | |
4655 | i = 0; | |
4656 | ||
9a799d71 AK |
4657 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; |
4658 | size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD); | |
4659 | ||
4660 | tx_buffer_info->length = size; | |
44df32c5 | 4661 | tx_buffer_info->dma = map[f + 1] + offset; |
9a799d71 AK |
4662 | tx_buffer_info->time_stamp = jiffies; |
4663 | tx_buffer_info->next_to_watch = i; | |
4664 | ||
4665 | len -= size; | |
eacd73f7 | 4666 | total -= size; |
9a799d71 AK |
4667 | offset += size; |
4668 | count++; | |
9a799d71 | 4669 | } |
eacd73f7 YZ |
4670 | if (total == 0) |
4671 | break; | |
9a799d71 | 4672 | } |
44df32c5 | 4673 | |
9a799d71 AK |
4674 | tx_ring->tx_buffer_info[i].skb = skb; |
4675 | tx_ring->tx_buffer_info[first].next_to_watch = i; | |
4676 | ||
4677 | return count; | |
4678 | } | |
4679 | ||
4680 | static void ixgbe_tx_queue(struct ixgbe_adapter *adapter, | |
b4617240 PW |
4681 | struct ixgbe_ring *tx_ring, |
4682 | int tx_flags, int count, u32 paylen, u8 hdr_len) | |
9a799d71 AK |
4683 | { |
4684 | union ixgbe_adv_tx_desc *tx_desc = NULL; | |
4685 | struct ixgbe_tx_buffer *tx_buffer_info; | |
4686 | u32 olinfo_status = 0, cmd_type_len = 0; | |
4687 | unsigned int i; | |
4688 | u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS; | |
4689 | ||
4690 | cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA; | |
4691 | ||
4692 | cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT; | |
4693 | ||
4694 | if (tx_flags & IXGBE_TX_FLAGS_VLAN) | |
4695 | cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE; | |
4696 | ||
4697 | if (tx_flags & IXGBE_TX_FLAGS_TSO) { | |
4698 | cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE; | |
4699 | ||
4700 | olinfo_status |= IXGBE_TXD_POPTS_TXSM << | |
b4617240 | 4701 | IXGBE_ADVTXD_POPTS_SHIFT; |
9a799d71 | 4702 | |
4eeae6fd PW |
4703 | /* use index 1 context for tso */ |
4704 | olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT); | |
9a799d71 AK |
4705 | if (tx_flags & IXGBE_TX_FLAGS_IPV4) |
4706 | olinfo_status |= IXGBE_TXD_POPTS_IXSM << | |
b4617240 | 4707 | IXGBE_ADVTXD_POPTS_SHIFT; |
9a799d71 AK |
4708 | |
4709 | } else if (tx_flags & IXGBE_TX_FLAGS_CSUM) | |
4710 | olinfo_status |= IXGBE_TXD_POPTS_TXSM << | |
b4617240 | 4711 | IXGBE_ADVTXD_POPTS_SHIFT; |
9a799d71 | 4712 | |
eacd73f7 YZ |
4713 | if (tx_flags & IXGBE_TX_FLAGS_FCOE) { |
4714 | olinfo_status |= IXGBE_ADVTXD_CC; | |
4715 | olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT); | |
4716 | if (tx_flags & IXGBE_TX_FLAGS_FSO) | |
4717 | cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE; | |
4718 | } | |
4719 | ||
9a799d71 AK |
4720 | olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT); |
4721 | ||
4722 | i = tx_ring->next_to_use; | |
4723 | while (count--) { | |
4724 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
4725 | tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i); | |
4726 | tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma); | |
4727 | tx_desc->read.cmd_type_len = | |
b4617240 | 4728 | cpu_to_le32(cmd_type_len | tx_buffer_info->length); |
9a799d71 | 4729 | tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); |
9a799d71 AK |
4730 | i++; |
4731 | if (i == tx_ring->count) | |
4732 | i = 0; | |
4733 | } | |
4734 | ||
4735 | tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd); | |
4736 | ||
4737 | /* | |
4738 | * Force memory writes to complete before letting h/w | |
4739 | * know there are new descriptors to fetch. (Only | |
4740 | * applicable for weak-ordered memory model archs, | |
4741 | * such as IA-64). | |
4742 | */ | |
4743 | wmb(); | |
4744 | ||
4745 | tx_ring->next_to_use = i; | |
4746 | writel(i, adapter->hw.hw_addr + tx_ring->tail); | |
4747 | } | |
4748 | ||
e092be60 | 4749 | static int __ixgbe_maybe_stop_tx(struct net_device *netdev, |
b4617240 | 4750 | struct ixgbe_ring *tx_ring, int size) |
e092be60 AV |
4751 | { |
4752 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4753 | ||
30eba97a | 4754 | netif_stop_subqueue(netdev, tx_ring->queue_index); |
e092be60 AV |
4755 | /* Herbert's original patch had: |
4756 | * smp_mb__after_netif_stop_queue(); | |
4757 | * but since that doesn't exist yet, just open code it. */ | |
4758 | smp_mb(); | |
4759 | ||
4760 | /* We need to check again in a case another CPU has just | |
4761 | * made room available. */ | |
4762 | if (likely(IXGBE_DESC_UNUSED(tx_ring) < size)) | |
4763 | return -EBUSY; | |
4764 | ||
4765 | /* A reprieve! - use start_queue because it doesn't call schedule */ | |
af72166f | 4766 | netif_start_subqueue(netdev, tx_ring->queue_index); |
e092be60 AV |
4767 | ++adapter->restart_queue; |
4768 | return 0; | |
4769 | } | |
4770 | ||
4771 | static int ixgbe_maybe_stop_tx(struct net_device *netdev, | |
b4617240 | 4772 | struct ixgbe_ring *tx_ring, int size) |
e092be60 AV |
4773 | { |
4774 | if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size)) | |
4775 | return 0; | |
4776 | return __ixgbe_maybe_stop_tx(netdev, tx_ring, size); | |
4777 | } | |
4778 | ||
09a3b1f8 SH |
4779 | static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb) |
4780 | { | |
4781 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
4782 | ||
4783 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) | |
4784 | return 0; /* All traffic should default to class 0 */ | |
4785 | ||
4786 | return skb_tx_hash(dev, skb); | |
4787 | } | |
4788 | ||
9a799d71 AK |
4789 | static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev) |
4790 | { | |
4791 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4792 | struct ixgbe_ring *tx_ring; | |
9a799d71 AK |
4793 | unsigned int first; |
4794 | unsigned int tx_flags = 0; | |
30eba97a AV |
4795 | u8 hdr_len = 0; |
4796 | int r_idx = 0, tso; | |
9a799d71 AK |
4797 | int count = 0; |
4798 | unsigned int f; | |
9f8cdf4f | 4799 | |
95615d90 | 4800 | r_idx = skb->queue_mapping; |
30eba97a | 4801 | tx_ring = &adapter->tx_ring[r_idx]; |
9a799d71 | 4802 | |
9f8cdf4f JB |
4803 | if (adapter->vlgrp && vlan_tx_tag_present(skb)) { |
4804 | tx_flags |= vlan_tx_tag_get(skb); | |
2f90b865 AD |
4805 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { |
4806 | tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK; | |
4807 | tx_flags |= (skb->queue_mapping << 13); | |
4808 | } | |
4809 | tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT; | |
4810 | tx_flags |= IXGBE_TX_FLAGS_VLAN; | |
4811 | } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
4812 | tx_flags |= (skb->queue_mapping << 13); | |
9f8cdf4f JB |
4813 | tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT; |
4814 | tx_flags |= IXGBE_TX_FLAGS_VLAN; | |
9a799d71 | 4815 | } |
eacd73f7 YZ |
4816 | |
4817 | if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && | |
4818 | (skb->protocol == htons(ETH_P_FCOE))) | |
4819 | tx_flags |= IXGBE_TX_FLAGS_FCOE; | |
4820 | ||
4821 | /* four things can cause us to need a context descriptor */ | |
9f8cdf4f JB |
4822 | if (skb_is_gso(skb) || |
4823 | (skb->ip_summed == CHECKSUM_PARTIAL) || | |
eacd73f7 YZ |
4824 | (tx_flags & IXGBE_TX_FLAGS_VLAN) || |
4825 | (tx_flags & IXGBE_TX_FLAGS_FCOE)) | |
9a799d71 AK |
4826 | count++; |
4827 | ||
9f8cdf4f JB |
4828 | count += TXD_USE_COUNT(skb_headlen(skb)); |
4829 | for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) | |
9a799d71 AK |
4830 | count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); |
4831 | ||
e092be60 | 4832 | if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) { |
9a799d71 | 4833 | adapter->tx_busy++; |
9a799d71 AK |
4834 | return NETDEV_TX_BUSY; |
4835 | } | |
9a799d71 | 4836 | |
9a799d71 | 4837 | first = tx_ring->next_to_use; |
eacd73f7 YZ |
4838 | if (tx_flags & IXGBE_TX_FLAGS_FCOE) { |
4839 | #ifdef IXGBE_FCOE | |
4840 | /* setup tx offload for FCoE */ | |
4841 | tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len); | |
4842 | if (tso < 0) { | |
4843 | dev_kfree_skb_any(skb); | |
4844 | return NETDEV_TX_OK; | |
4845 | } | |
4846 | if (tso) | |
4847 | tx_flags |= IXGBE_TX_FLAGS_FSO; | |
4848 | #endif /* IXGBE_FCOE */ | |
4849 | } else { | |
4850 | if (skb->protocol == htons(ETH_P_IP)) | |
4851 | tx_flags |= IXGBE_TX_FLAGS_IPV4; | |
4852 | tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len); | |
4853 | if (tso < 0) { | |
4854 | dev_kfree_skb_any(skb); | |
4855 | return NETDEV_TX_OK; | |
4856 | } | |
9a799d71 | 4857 | |
eacd73f7 YZ |
4858 | if (tso) |
4859 | tx_flags |= IXGBE_TX_FLAGS_TSO; | |
4860 | else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) && | |
4861 | (skb->ip_summed == CHECKSUM_PARTIAL)) | |
4862 | tx_flags |= IXGBE_TX_FLAGS_CSUM; | |
4863 | } | |
9a799d71 | 4864 | |
eacd73f7 | 4865 | count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first); |
44df32c5 AD |
4866 | if (count) { |
4867 | ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len, | |
4868 | hdr_len); | |
44df32c5 | 4869 | ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED); |
9a799d71 | 4870 | |
44df32c5 AD |
4871 | } else { |
4872 | dev_kfree_skb_any(skb); | |
4873 | tx_ring->tx_buffer_info[first].time_stamp = 0; | |
4874 | tx_ring->next_to_use = first; | |
4875 | } | |
9a799d71 AK |
4876 | |
4877 | return NETDEV_TX_OK; | |
4878 | } | |
4879 | ||
4880 | /** | |
4881 | * ixgbe_get_stats - Get System Network Statistics | |
4882 | * @netdev: network interface device structure | |
4883 | * | |
4884 | * Returns the address of the device statistics structure. | |
4885 | * The statistics are actually updated from the timer callback. | |
4886 | **/ | |
4887 | static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev) | |
4888 | { | |
4889 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4890 | ||
4891 | /* only return the current stats */ | |
4892 | return &adapter->net_stats; | |
4893 | } | |
4894 | ||
4895 | /** | |
4896 | * ixgbe_set_mac - Change the Ethernet Address of the NIC | |
4897 | * @netdev: network interface device structure | |
4898 | * @p: pointer to an address structure | |
4899 | * | |
4900 | * Returns 0 on success, negative on failure | |
4901 | **/ | |
4902 | static int ixgbe_set_mac(struct net_device *netdev, void *p) | |
4903 | { | |
4904 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
b4617240 | 4905 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 AK |
4906 | struct sockaddr *addr = p; |
4907 | ||
4908 | if (!is_valid_ether_addr(addr->sa_data)) | |
4909 | return -EADDRNOTAVAIL; | |
4910 | ||
4911 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | |
b4617240 | 4912 | memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); |
9a799d71 | 4913 | |
b4617240 | 4914 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); |
9a799d71 AK |
4915 | |
4916 | return 0; | |
4917 | } | |
4918 | ||
6b73e10d BH |
4919 | static int |
4920 | ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr) | |
4921 | { | |
4922 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4923 | struct ixgbe_hw *hw = &adapter->hw; | |
4924 | u16 value; | |
4925 | int rc; | |
4926 | ||
4927 | if (prtad != hw->phy.mdio.prtad) | |
4928 | return -EINVAL; | |
4929 | rc = hw->phy.ops.read_reg(hw, addr, devad, &value); | |
4930 | if (!rc) | |
4931 | rc = value; | |
4932 | return rc; | |
4933 | } | |
4934 | ||
4935 | static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad, | |
4936 | u16 addr, u16 value) | |
4937 | { | |
4938 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4939 | struct ixgbe_hw *hw = &adapter->hw; | |
4940 | ||
4941 | if (prtad != hw->phy.mdio.prtad) | |
4942 | return -EINVAL; | |
4943 | return hw->phy.ops.write_reg(hw, addr, devad, value); | |
4944 | } | |
4945 | ||
4946 | static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) | |
4947 | { | |
4948 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4949 | ||
4950 | return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd); | |
4951 | } | |
4952 | ||
0365e6e4 PW |
4953 | /** |
4954 | * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding | |
4955 | * netdev->dev_addr_list | |
4956 | * @netdev: network interface device structure | |
4957 | * | |
4958 | * Returns non-zero on failure | |
4959 | **/ | |
4960 | static int ixgbe_add_sanmac_netdev(struct net_device *dev) | |
4961 | { | |
4962 | int err = 0; | |
4963 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
4964 | struct ixgbe_mac_info *mac = &adapter->hw.mac; | |
4965 | ||
4966 | if (is_valid_ether_addr(mac->san_addr)) { | |
4967 | rtnl_lock(); | |
4968 | err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); | |
4969 | rtnl_unlock(); | |
4970 | } | |
4971 | return err; | |
4972 | } | |
4973 | ||
4974 | /** | |
4975 | * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding | |
4976 | * netdev->dev_addr_list | |
4977 | * @netdev: network interface device structure | |
4978 | * | |
4979 | * Returns non-zero on failure | |
4980 | **/ | |
4981 | static int ixgbe_del_sanmac_netdev(struct net_device *dev) | |
4982 | { | |
4983 | int err = 0; | |
4984 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
4985 | struct ixgbe_mac_info *mac = &adapter->hw.mac; | |
4986 | ||
4987 | if (is_valid_ether_addr(mac->san_addr)) { | |
4988 | rtnl_lock(); | |
4989 | err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); | |
4990 | rtnl_unlock(); | |
4991 | } | |
4992 | return err; | |
4993 | } | |
4994 | ||
9a799d71 AK |
4995 | #ifdef CONFIG_NET_POLL_CONTROLLER |
4996 | /* | |
4997 | * Polling 'interrupt' - used by things like netconsole to send skbs | |
4998 | * without having to re-enable interrupts. It's not called while | |
4999 | * the interrupt routine is executing. | |
5000 | */ | |
5001 | static void ixgbe_netpoll(struct net_device *netdev) | |
5002 | { | |
5003 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
5004 | ||
5005 | disable_irq(adapter->pdev->irq); | |
5006 | adapter->flags |= IXGBE_FLAG_IN_NETPOLL; | |
5007 | ixgbe_intr(adapter->pdev->irq, netdev); | |
5008 | adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL; | |
5009 | enable_irq(adapter->pdev->irq); | |
5010 | } | |
5011 | #endif | |
5012 | ||
0edc3527 SH |
5013 | static const struct net_device_ops ixgbe_netdev_ops = { |
5014 | .ndo_open = ixgbe_open, | |
5015 | .ndo_stop = ixgbe_close, | |
00829823 | 5016 | .ndo_start_xmit = ixgbe_xmit_frame, |
09a3b1f8 | 5017 | .ndo_select_queue = ixgbe_select_queue, |
0edc3527 | 5018 | .ndo_get_stats = ixgbe_get_stats, |
e90d400c | 5019 | .ndo_set_rx_mode = ixgbe_set_rx_mode, |
0edc3527 SH |
5020 | .ndo_set_multicast_list = ixgbe_set_rx_mode, |
5021 | .ndo_validate_addr = eth_validate_addr, | |
5022 | .ndo_set_mac_address = ixgbe_set_mac, | |
5023 | .ndo_change_mtu = ixgbe_change_mtu, | |
5024 | .ndo_tx_timeout = ixgbe_tx_timeout, | |
5025 | .ndo_vlan_rx_register = ixgbe_vlan_rx_register, | |
5026 | .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid, | |
5027 | .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid, | |
6b73e10d | 5028 | .ndo_do_ioctl = ixgbe_ioctl, |
0edc3527 SH |
5029 | #ifdef CONFIG_NET_POLL_CONTROLLER |
5030 | .ndo_poll_controller = ixgbe_netpoll, | |
5031 | #endif | |
332d4a7d YZ |
5032 | #ifdef IXGBE_FCOE |
5033 | .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get, | |
5034 | .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put, | |
5035 | #endif /* IXGBE_FCOE */ | |
0edc3527 SH |
5036 | }; |
5037 | ||
9a799d71 AK |
5038 | /** |
5039 | * ixgbe_probe - Device Initialization Routine | |
5040 | * @pdev: PCI device information struct | |
5041 | * @ent: entry in ixgbe_pci_tbl | |
5042 | * | |
5043 | * Returns 0 on success, negative on failure | |
5044 | * | |
5045 | * ixgbe_probe initializes an adapter identified by a pci_dev structure. | |
5046 | * The OS initialization, configuring of the adapter private structure, | |
5047 | * and a hardware reset occur. | |
5048 | **/ | |
5049 | static int __devinit ixgbe_probe(struct pci_dev *pdev, | |
b4617240 | 5050 | const struct pci_device_id *ent) |
9a799d71 AK |
5051 | { |
5052 | struct net_device *netdev; | |
5053 | struct ixgbe_adapter *adapter = NULL; | |
5054 | struct ixgbe_hw *hw; | |
5055 | const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data]; | |
9a799d71 AK |
5056 | static int cards_found; |
5057 | int i, err, pci_using_dac; | |
eacd73f7 YZ |
5058 | #ifdef IXGBE_FCOE |
5059 | u16 device_caps; | |
5060 | #endif | |
c44ade9e | 5061 | u32 part_num, eec; |
9a799d71 | 5062 | |
9ce77666 | 5063 | err = pci_enable_device_mem(pdev); |
9a799d71 AK |
5064 | if (err) |
5065 | return err; | |
5066 | ||
6a35528a YH |
5067 | if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && |
5068 | !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) { | |
9a799d71 AK |
5069 | pci_using_dac = 1; |
5070 | } else { | |
284901a9 | 5071 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
9a799d71 | 5072 | if (err) { |
284901a9 | 5073 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
9a799d71 | 5074 | if (err) { |
b4617240 PW |
5075 | dev_err(&pdev->dev, "No usable DMA " |
5076 | "configuration, aborting\n"); | |
9a799d71 AK |
5077 | goto err_dma; |
5078 | } | |
5079 | } | |
5080 | pci_using_dac = 0; | |
5081 | } | |
5082 | ||
9ce77666 | 5083 | err = pci_request_selected_regions(pdev, pci_select_bars(pdev, |
5084 | IORESOURCE_MEM), ixgbe_driver_name); | |
9a799d71 | 5085 | if (err) { |
9ce77666 | 5086 | dev_err(&pdev->dev, |
5087 | "pci_request_selected_regions failed 0x%x\n", err); | |
9a799d71 AK |
5088 | goto err_pci_reg; |
5089 | } | |
5090 | ||
6fabd715 PWJ |
5091 | err = pci_enable_pcie_error_reporting(pdev); |
5092 | if (err) { | |
5093 | dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed " | |
5094 | "0x%x\n", err); | |
5095 | /* non-fatal, continue */ | |
5096 | } | |
5097 | ||
9a799d71 | 5098 | pci_set_master(pdev); |
fb3b27bc | 5099 | pci_save_state(pdev); |
9a799d71 | 5100 | |
30eba97a | 5101 | netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES); |
9a799d71 AK |
5102 | if (!netdev) { |
5103 | err = -ENOMEM; | |
5104 | goto err_alloc_etherdev; | |
5105 | } | |
5106 | ||
9a799d71 AK |
5107 | SET_NETDEV_DEV(netdev, &pdev->dev); |
5108 | ||
5109 | pci_set_drvdata(pdev, netdev); | |
5110 | adapter = netdev_priv(netdev); | |
5111 | ||
5112 | adapter->netdev = netdev; | |
5113 | adapter->pdev = pdev; | |
5114 | hw = &adapter->hw; | |
5115 | hw->back = adapter; | |
5116 | adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1; | |
5117 | ||
05857980 JK |
5118 | hw->hw_addr = ioremap(pci_resource_start(pdev, 0), |
5119 | pci_resource_len(pdev, 0)); | |
9a799d71 AK |
5120 | if (!hw->hw_addr) { |
5121 | err = -EIO; | |
5122 | goto err_ioremap; | |
5123 | } | |
5124 | ||
5125 | for (i = 1; i <= 5; i++) { | |
5126 | if (pci_resource_len(pdev, i) == 0) | |
5127 | continue; | |
5128 | } | |
5129 | ||
0edc3527 | 5130 | netdev->netdev_ops = &ixgbe_netdev_ops; |
9a799d71 | 5131 | ixgbe_set_ethtool_ops(netdev); |
9a799d71 | 5132 | netdev->watchdog_timeo = 5 * HZ; |
9a799d71 AK |
5133 | strcpy(netdev->name, pci_name(pdev)); |
5134 | ||
9a799d71 AK |
5135 | adapter->bd_number = cards_found; |
5136 | ||
9a799d71 AK |
5137 | /* Setup hw api */ |
5138 | memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops)); | |
021230d4 | 5139 | hw->mac.type = ii->mac; |
9a799d71 | 5140 | |
c44ade9e JB |
5141 | /* EEPROM */ |
5142 | memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops)); | |
5143 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); | |
5144 | /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */ | |
5145 | if (!(eec & (1 << 8))) | |
5146 | hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic; | |
5147 | ||
5148 | /* PHY */ | |
5149 | memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops)); | |
c4900be0 | 5150 | hw->phy.sfp_type = ixgbe_sfp_type_unknown; |
6b73e10d BH |
5151 | /* ixgbe_identify_phy_generic will set prtad and mmds properly */ |
5152 | hw->phy.mdio.prtad = MDIO_PRTAD_NONE; | |
5153 | hw->phy.mdio.mmds = 0; | |
5154 | hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; | |
5155 | hw->phy.mdio.dev = netdev; | |
5156 | hw->phy.mdio.mdio_read = ixgbe_mdio_read; | |
5157 | hw->phy.mdio.mdio_write = ixgbe_mdio_write; | |
c4900be0 DS |
5158 | |
5159 | /* set up this timer and work struct before calling get_invariants | |
5160 | * which might start the timer | |
5161 | */ | |
5162 | init_timer(&adapter->sfp_timer); | |
5163 | adapter->sfp_timer.function = &ixgbe_sfp_timer; | |
5164 | adapter->sfp_timer.data = (unsigned long) adapter; | |
5165 | ||
5166 | INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task); | |
c44ade9e | 5167 | |
e8e26350 PW |
5168 | /* multispeed fiber has its own tasklet, called from GPI SDP1 context */ |
5169 | INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task); | |
5170 | ||
5171 | /* a new SFP+ module arrival, called from GPI SDP2 context */ | |
5172 | INIT_WORK(&adapter->sfp_config_module_task, | |
5173 | ixgbe_sfp_config_module_task); | |
5174 | ||
8ca783ab | 5175 | ii->get_invariants(hw); |
9a799d71 AK |
5176 | |
5177 | /* setup the private structure */ | |
5178 | err = ixgbe_sw_init(adapter); | |
5179 | if (err) | |
5180 | goto err_sw_init; | |
5181 | ||
bf069c97 DS |
5182 | /* |
5183 | * If there is a fan on this device and it has failed log the | |
5184 | * failure. | |
5185 | */ | |
5186 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
5187 | u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); | |
5188 | if (esdp & IXGBE_ESDP_SDP1) | |
5189 | DPRINTK(PROBE, CRIT, | |
5190 | "Fan has stopped, replace the adapter\n"); | |
5191 | } | |
5192 | ||
c44ade9e JB |
5193 | /* reset_hw fills in the perm_addr as well */ |
5194 | err = hw->mac.ops.reset_hw(hw); | |
8ca783ab DS |
5195 | if (err == IXGBE_ERR_SFP_NOT_PRESENT && |
5196 | hw->mac.type == ixgbe_mac_82598EB) { | |
5197 | /* | |
5198 | * Start a kernel thread to watch for a module to arrive. | |
5199 | * Only do this for 82598, since 82599 will generate | |
5200 | * interrupts on module arrival. | |
5201 | */ | |
5202 | set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); | |
5203 | mod_timer(&adapter->sfp_timer, | |
5204 | round_jiffies(jiffies + (2 * HZ))); | |
5205 | err = 0; | |
5206 | } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
04f165ef PW |
5207 | dev_err(&adapter->pdev->dev, "failed to load because an " |
5208 | "unsupported SFP+ module type was detected.\n"); | |
5209 | goto err_sw_init; | |
5210 | } else if (err) { | |
c44ade9e JB |
5211 | dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err); |
5212 | goto err_sw_init; | |
5213 | } | |
5214 | ||
9a799d71 | 5215 | netdev->features = NETIF_F_SG | |
b4617240 PW |
5216 | NETIF_F_IP_CSUM | |
5217 | NETIF_F_HW_VLAN_TX | | |
5218 | NETIF_F_HW_VLAN_RX | | |
5219 | NETIF_F_HW_VLAN_FILTER; | |
9a799d71 | 5220 | |
e9990a9c | 5221 | netdev->features |= NETIF_F_IPV6_CSUM; |
9a799d71 | 5222 | netdev->features |= NETIF_F_TSO; |
9a799d71 | 5223 | netdev->features |= NETIF_F_TSO6; |
78b6f4ce | 5224 | netdev->features |= NETIF_F_GRO; |
ad31c402 | 5225 | |
45a5ead0 JB |
5226 | if (adapter->hw.mac.type == ixgbe_mac_82599EB) |
5227 | netdev->features |= NETIF_F_SCTP_CSUM; | |
5228 | ||
ad31c402 JK |
5229 | netdev->vlan_features |= NETIF_F_TSO; |
5230 | netdev->vlan_features |= NETIF_F_TSO6; | |
22f32b7a | 5231 | netdev->vlan_features |= NETIF_F_IP_CSUM; |
ad31c402 JK |
5232 | netdev->vlan_features |= NETIF_F_SG; |
5233 | ||
2f90b865 AD |
5234 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) |
5235 | adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED; | |
5236 | ||
7a6b6f51 | 5237 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
5238 | netdev->dcbnl_ops = &dcbnl_ops; |
5239 | #endif | |
5240 | ||
eacd73f7 YZ |
5241 | #ifdef IXGBE_FCOE |
5242 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { | |
5243 | if (hw->mac.ops.get_device_caps) { | |
5244 | hw->mac.ops.get_device_caps(hw, &device_caps); | |
5245 | if (!(device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)) { | |
5246 | netdev->features |= NETIF_F_FCOE_CRC; | |
5247 | netdev->features |= NETIF_F_FSO; | |
332d4a7d | 5248 | netdev->fcoe_ddp_xid = IXGBE_FCOE_DDP_MAX - 1; |
eacd73f7 YZ |
5249 | } else { |
5250 | adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; | |
5251 | } | |
5252 | } | |
5253 | } | |
5254 | #endif /* IXGBE_FCOE */ | |
9a799d71 AK |
5255 | if (pci_using_dac) |
5256 | netdev->features |= NETIF_F_HIGHDMA; | |
5257 | ||
f8212f97 AD |
5258 | if (adapter->flags & IXGBE_FLAG_RSC_ENABLED) |
5259 | netdev->features |= NETIF_F_LRO; | |
5260 | ||
9a799d71 | 5261 | /* make sure the EEPROM is good */ |
c44ade9e | 5262 | if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) { |
9a799d71 AK |
5263 | dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n"); |
5264 | err = -EIO; | |
5265 | goto err_eeprom; | |
5266 | } | |
5267 | ||
5268 | memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len); | |
5269 | memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len); | |
5270 | ||
c44ade9e JB |
5271 | if (ixgbe_validate_mac_addr(netdev->perm_addr)) { |
5272 | dev_err(&pdev->dev, "invalid MAC address\n"); | |
9a799d71 AK |
5273 | err = -EIO; |
5274 | goto err_eeprom; | |
5275 | } | |
5276 | ||
5277 | init_timer(&adapter->watchdog_timer); | |
5278 | adapter->watchdog_timer.function = &ixgbe_watchdog; | |
5279 | adapter->watchdog_timer.data = (unsigned long)adapter; | |
5280 | ||
5281 | INIT_WORK(&adapter->reset_task, ixgbe_reset_task); | |
cf8280ee | 5282 | INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task); |
9a799d71 | 5283 | |
021230d4 AV |
5284 | err = ixgbe_init_interrupt_scheme(adapter); |
5285 | if (err) | |
5286 | goto err_sw_init; | |
9a799d71 | 5287 | |
e8e26350 PW |
5288 | switch (pdev->device) { |
5289 | case IXGBE_DEV_ID_82599_KX4: | |
495dce12 WJP |
5290 | adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX | |
5291 | IXGBE_WUFC_MC | IXGBE_WUFC_BC); | |
bdf0a550 PWJ |
5292 | /* Enable ACPI wakeup in GRC */ |
5293 | IXGBE_WRITE_REG(hw, IXGBE_GRC, | |
5294 | (IXGBE_READ_REG(hw, IXGBE_GRC) & ~IXGBE_GRC_APME)); | |
e8e26350 PW |
5295 | break; |
5296 | default: | |
5297 | adapter->wol = 0; | |
5298 | break; | |
5299 | } | |
5300 | device_init_wakeup(&adapter->pdev->dev, true); | |
5301 | device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); | |
5302 | ||
04f165ef PW |
5303 | /* pick up the PCI bus settings for reporting later */ |
5304 | hw->mac.ops.get_bus_info(hw); | |
5305 | ||
9a799d71 | 5306 | /* print bus type/speed/width info */ |
7c510e4b | 5307 | dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n", |
e8e26350 PW |
5308 | ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s": |
5309 | (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"), | |
5310 | ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" : | |
5311 | (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" : | |
5312 | (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" : | |
b4617240 | 5313 | "Unknown"), |
7c510e4b | 5314 | netdev->dev_addr); |
c44ade9e | 5315 | ixgbe_read_pba_num_generic(hw, &part_num); |
e8e26350 PW |
5316 | if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) |
5317 | dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n", | |
5318 | hw->mac.type, hw->phy.type, hw->phy.sfp_type, | |
5319 | (part_num >> 8), (part_num & 0xff)); | |
5320 | else | |
5321 | dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n", | |
5322 | hw->mac.type, hw->phy.type, | |
5323 | (part_num >> 8), (part_num & 0xff)); | |
9a799d71 | 5324 | |
e8e26350 | 5325 | if (hw->bus.width <= ixgbe_bus_width_pcie_x4) { |
0c254d86 | 5326 | dev_warn(&pdev->dev, "PCI-Express bandwidth available for " |
b4617240 PW |
5327 | "this card is not sufficient for optimal " |
5328 | "performance.\n"); | |
0c254d86 | 5329 | dev_warn(&pdev->dev, "For optimal performance a x8 " |
b4617240 | 5330 | "PCI-Express slot is required.\n"); |
0c254d86 AK |
5331 | } |
5332 | ||
34b0368c PWJ |
5333 | /* save off EEPROM version number */ |
5334 | hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version); | |
5335 | ||
9a799d71 | 5336 | /* reset the hardware with the new settings */ |
c44ade9e JB |
5337 | hw->mac.ops.start_hw(hw); |
5338 | ||
9a799d71 AK |
5339 | strcpy(netdev->name, "eth%d"); |
5340 | err = register_netdev(netdev); | |
5341 | if (err) | |
5342 | goto err_register; | |
5343 | ||
54386467 JB |
5344 | /* carrier off reporting is important to ethtool even BEFORE open */ |
5345 | netif_carrier_off(netdev); | |
5346 | ||
5dd2d332 | 5347 | #ifdef CONFIG_IXGBE_DCA |
652f093f | 5348 | if (dca_add_requester(&pdev->dev) == 0) { |
bd0362dd | 5349 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; |
bd0362dd JC |
5350 | ixgbe_setup_dca(adapter); |
5351 | } | |
5352 | #endif | |
0365e6e4 PW |
5353 | /* add san mac addr to netdev */ |
5354 | ixgbe_add_sanmac_netdev(netdev); | |
9a799d71 AK |
5355 | |
5356 | dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n"); | |
5357 | cards_found++; | |
5358 | return 0; | |
5359 | ||
5360 | err_register: | |
5eba3699 | 5361 | ixgbe_release_hw_control(adapter); |
7a921c93 | 5362 | ixgbe_clear_interrupt_scheme(adapter); |
9a799d71 AK |
5363 | err_sw_init: |
5364 | err_eeprom: | |
c4900be0 DS |
5365 | clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); |
5366 | del_timer_sync(&adapter->sfp_timer); | |
5367 | cancel_work_sync(&adapter->sfp_task); | |
e8e26350 PW |
5368 | cancel_work_sync(&adapter->multispeed_fiber_task); |
5369 | cancel_work_sync(&adapter->sfp_config_module_task); | |
9a799d71 AK |
5370 | iounmap(hw->hw_addr); |
5371 | err_ioremap: | |
5372 | free_netdev(netdev); | |
5373 | err_alloc_etherdev: | |
9ce77666 | 5374 | pci_release_selected_regions(pdev, pci_select_bars(pdev, |
5375 | IORESOURCE_MEM)); | |
9a799d71 AK |
5376 | err_pci_reg: |
5377 | err_dma: | |
5378 | pci_disable_device(pdev); | |
5379 | return err; | |
5380 | } | |
5381 | ||
5382 | /** | |
5383 | * ixgbe_remove - Device Removal Routine | |
5384 | * @pdev: PCI device information struct | |
5385 | * | |
5386 | * ixgbe_remove is called by the PCI subsystem to alert the driver | |
5387 | * that it should release a PCI device. The could be caused by a | |
5388 | * Hot-Plug event, or because the driver is going to be removed from | |
5389 | * memory. | |
5390 | **/ | |
5391 | static void __devexit ixgbe_remove(struct pci_dev *pdev) | |
5392 | { | |
5393 | struct net_device *netdev = pci_get_drvdata(pdev); | |
5394 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6fabd715 | 5395 | int err; |
9a799d71 AK |
5396 | |
5397 | set_bit(__IXGBE_DOWN, &adapter->state); | |
c4900be0 DS |
5398 | /* clear the module not found bit to make sure the worker won't |
5399 | * reschedule | |
5400 | */ | |
5401 | clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); | |
9a799d71 AK |
5402 | del_timer_sync(&adapter->watchdog_timer); |
5403 | ||
c4900be0 DS |
5404 | del_timer_sync(&adapter->sfp_timer); |
5405 | cancel_work_sync(&adapter->watchdog_task); | |
5406 | cancel_work_sync(&adapter->sfp_task); | |
e8e26350 PW |
5407 | cancel_work_sync(&adapter->multispeed_fiber_task); |
5408 | cancel_work_sync(&adapter->sfp_config_module_task); | |
9a799d71 AK |
5409 | flush_scheduled_work(); |
5410 | ||
5dd2d332 | 5411 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
5412 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { |
5413 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
5414 | dca_remove_requester(&pdev->dev); | |
5415 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); | |
5416 | } | |
5417 | ||
5418 | #endif | |
332d4a7d YZ |
5419 | #ifdef IXGBE_FCOE |
5420 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) | |
5421 | ixgbe_cleanup_fcoe(adapter); | |
5422 | ||
5423 | #endif /* IXGBE_FCOE */ | |
0365e6e4 PW |
5424 | |
5425 | /* remove the added san mac */ | |
5426 | ixgbe_del_sanmac_netdev(netdev); | |
5427 | ||
c4900be0 DS |
5428 | if (netdev->reg_state == NETREG_REGISTERED) |
5429 | unregister_netdev(netdev); | |
9a799d71 | 5430 | |
7a921c93 | 5431 | ixgbe_clear_interrupt_scheme(adapter); |
5eba3699 | 5432 | |
021230d4 | 5433 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
5434 | |
5435 | iounmap(adapter->hw.hw_addr); | |
9ce77666 | 5436 | pci_release_selected_regions(pdev, pci_select_bars(pdev, |
5437 | IORESOURCE_MEM)); | |
9a799d71 | 5438 | |
021230d4 | 5439 | DPRINTK(PROBE, INFO, "complete\n"); |
021230d4 | 5440 | |
9a799d71 AK |
5441 | free_netdev(netdev); |
5442 | ||
6fabd715 PWJ |
5443 | err = pci_disable_pcie_error_reporting(pdev); |
5444 | if (err) | |
5445 | dev_err(&pdev->dev, | |
5446 | "pci_disable_pcie_error_reporting failed 0x%x\n", err); | |
5447 | ||
9a799d71 AK |
5448 | pci_disable_device(pdev); |
5449 | } | |
5450 | ||
5451 | /** | |
5452 | * ixgbe_io_error_detected - called when PCI error is detected | |
5453 | * @pdev: Pointer to PCI device | |
5454 | * @state: The current pci connection state | |
5455 | * | |
5456 | * This function is called after a PCI bus error affecting | |
5457 | * this device has been detected. | |
5458 | */ | |
5459 | static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev, | |
b4617240 | 5460 | pci_channel_state_t state) |
9a799d71 AK |
5461 | { |
5462 | struct net_device *netdev = pci_get_drvdata(pdev); | |
454d7c9b | 5463 | struct ixgbe_adapter *adapter = netdev_priv(netdev); |
9a799d71 AK |
5464 | |
5465 | netif_device_detach(netdev); | |
5466 | ||
3044b8d1 BL |
5467 | if (state == pci_channel_io_perm_failure) |
5468 | return PCI_ERS_RESULT_DISCONNECT; | |
5469 | ||
9a799d71 AK |
5470 | if (netif_running(netdev)) |
5471 | ixgbe_down(adapter); | |
5472 | pci_disable_device(pdev); | |
5473 | ||
b4617240 | 5474 | /* Request a slot reset. */ |
9a799d71 AK |
5475 | return PCI_ERS_RESULT_NEED_RESET; |
5476 | } | |
5477 | ||
5478 | /** | |
5479 | * ixgbe_io_slot_reset - called after the pci bus has been reset. | |
5480 | * @pdev: Pointer to PCI device | |
5481 | * | |
5482 | * Restart the card from scratch, as if from a cold-boot. | |
5483 | */ | |
5484 | static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev) | |
5485 | { | |
5486 | struct net_device *netdev = pci_get_drvdata(pdev); | |
454d7c9b | 5487 | struct ixgbe_adapter *adapter = netdev_priv(netdev); |
6fabd715 PWJ |
5488 | pci_ers_result_t result; |
5489 | int err; | |
9a799d71 | 5490 | |
9ce77666 | 5491 | if (pci_enable_device_mem(pdev)) { |
9a799d71 | 5492 | DPRINTK(PROBE, ERR, |
b4617240 | 5493 | "Cannot re-enable PCI device after reset.\n"); |
6fabd715 PWJ |
5494 | result = PCI_ERS_RESULT_DISCONNECT; |
5495 | } else { | |
5496 | pci_set_master(pdev); | |
5497 | pci_restore_state(pdev); | |
9a799d71 | 5498 | |
dd4d8ca6 | 5499 | pci_wake_from_d3(pdev, false); |
9a799d71 | 5500 | |
6fabd715 | 5501 | ixgbe_reset(adapter); |
88512539 | 5502 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
6fabd715 PWJ |
5503 | result = PCI_ERS_RESULT_RECOVERED; |
5504 | } | |
5505 | ||
5506 | err = pci_cleanup_aer_uncorrect_error_status(pdev); | |
5507 | if (err) { | |
5508 | dev_err(&pdev->dev, | |
5509 | "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err); | |
5510 | /* non-fatal, continue */ | |
5511 | } | |
9a799d71 | 5512 | |
6fabd715 | 5513 | return result; |
9a799d71 AK |
5514 | } |
5515 | ||
5516 | /** | |
5517 | * ixgbe_io_resume - called when traffic can start flowing again. | |
5518 | * @pdev: Pointer to PCI device | |
5519 | * | |
5520 | * This callback is called when the error recovery driver tells us that | |
5521 | * its OK to resume normal operation. | |
5522 | */ | |
5523 | static void ixgbe_io_resume(struct pci_dev *pdev) | |
5524 | { | |
5525 | struct net_device *netdev = pci_get_drvdata(pdev); | |
454d7c9b | 5526 | struct ixgbe_adapter *adapter = netdev_priv(netdev); |
9a799d71 AK |
5527 | |
5528 | if (netif_running(netdev)) { | |
5529 | if (ixgbe_up(adapter)) { | |
5530 | DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n"); | |
5531 | return; | |
5532 | } | |
5533 | } | |
5534 | ||
5535 | netif_device_attach(netdev); | |
9a799d71 AK |
5536 | } |
5537 | ||
5538 | static struct pci_error_handlers ixgbe_err_handler = { | |
5539 | .error_detected = ixgbe_io_error_detected, | |
5540 | .slot_reset = ixgbe_io_slot_reset, | |
5541 | .resume = ixgbe_io_resume, | |
5542 | }; | |
5543 | ||
5544 | static struct pci_driver ixgbe_driver = { | |
5545 | .name = ixgbe_driver_name, | |
5546 | .id_table = ixgbe_pci_tbl, | |
5547 | .probe = ixgbe_probe, | |
5548 | .remove = __devexit_p(ixgbe_remove), | |
5549 | #ifdef CONFIG_PM | |
5550 | .suspend = ixgbe_suspend, | |
5551 | .resume = ixgbe_resume, | |
5552 | #endif | |
5553 | .shutdown = ixgbe_shutdown, | |
5554 | .err_handler = &ixgbe_err_handler | |
5555 | }; | |
5556 | ||
5557 | /** | |
5558 | * ixgbe_init_module - Driver Registration Routine | |
5559 | * | |
5560 | * ixgbe_init_module is the first routine called when the driver is | |
5561 | * loaded. All it does is register with the PCI subsystem. | |
5562 | **/ | |
5563 | static int __init ixgbe_init_module(void) | |
5564 | { | |
5565 | int ret; | |
5566 | printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name, | |
5567 | ixgbe_driver_string, ixgbe_driver_version); | |
5568 | ||
5569 | printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright); | |
5570 | ||
5dd2d332 | 5571 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 5572 | dca_register_notify(&dca_notifier); |
bd0362dd | 5573 | #endif |
5dd2d332 | 5574 | |
9a799d71 AK |
5575 | ret = pci_register_driver(&ixgbe_driver); |
5576 | return ret; | |
5577 | } | |
b4617240 | 5578 | |
9a799d71 AK |
5579 | module_init(ixgbe_init_module); |
5580 | ||
5581 | /** | |
5582 | * ixgbe_exit_module - Driver Exit Cleanup Routine | |
5583 | * | |
5584 | * ixgbe_exit_module is called just before the driver is removed | |
5585 | * from memory. | |
5586 | **/ | |
5587 | static void __exit ixgbe_exit_module(void) | |
5588 | { | |
5dd2d332 | 5589 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
5590 | dca_unregister_notify(&dca_notifier); |
5591 | #endif | |
9a799d71 AK |
5592 | pci_unregister_driver(&ixgbe_driver); |
5593 | } | |
bd0362dd | 5594 | |
5dd2d332 | 5595 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 5596 | static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event, |
b4617240 | 5597 | void *p) |
bd0362dd JC |
5598 | { |
5599 | int ret_val; | |
5600 | ||
5601 | ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event, | |
b4617240 | 5602 | __ixgbe_notify_dca); |
bd0362dd JC |
5603 | |
5604 | return ret_val ? NOTIFY_BAD : NOTIFY_DONE; | |
5605 | } | |
b453368d | 5606 | |
5dd2d332 | 5607 | #endif /* CONFIG_IXGBE_DCA */ |
b453368d AD |
5608 | #ifdef DEBUG |
5609 | /** | |
5610 | * ixgbe_get_hw_dev_name - return device name string | |
5611 | * used by hardware layer to print debugging information | |
5612 | **/ | |
5613 | char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw) | |
5614 | { | |
5615 | struct ixgbe_adapter *adapter = hw->back; | |
5616 | return adapter->netdev->name; | |
5617 | } | |
bd0362dd | 5618 | |
b453368d | 5619 | #endif |
9a799d71 AK |
5620 | module_exit(ixgbe_exit_module); |
5621 | ||
5622 | /* ixgbe_main.c */ |