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ixgbe: Add DCB for 82599, remove BCN support
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
3efac5a0 4 Copyright(c) 1999 - 2009 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
37#include <linux/ipv6.h>
38#include <net/checksum.h>
39#include <net/ip6_checksum.h>
40#include <linux/ethtool.h>
41#include <linux/if_vlan.h>
42
43#include "ixgbe.h"
44#include "ixgbe_common.h"
45
46char ixgbe_driver_name[] = "ixgbe";
9c8eb720 47static const char ixgbe_driver_string[] =
b4617240 48 "Intel(R) 10 Gigabit PCI Express Network Driver";
9a799d71 49
3efac5a0 50#define DRV_VERSION "1.3.56-k2"
9c8eb720 51const char ixgbe_driver_version[] = DRV_VERSION;
3efac5a0 52static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
9a799d71
AK		 53
54static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 55 [board_82598] = &ixgbe_82598_info,
9a799d71
AK		 56};
57
58/* ixgbe_pci_tbl - PCI Device ID Table
59 *
60 * Wildcard entries (PCI_ANY_ID) should come last
61 * Last entry must be all 0s
62 *
63 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
64 * Class, Class Mask, private data (not used) }
65 */
66static struct pci_device_id ixgbe_pci_tbl[] = {
1e336d0f
DS		 67 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
68 board_82598 },
9a799d71 69 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 70 board_82598 },
9a799d71 71 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 72 board_82598 },
0befdb3e
JB		 73 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
74 board_82598 },
9a799d71 75 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 76 board_82598 },
8d792cd9
JB		 77 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
78 board_82598 },
c4900be0
DS		 79 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
80 board_82598 },
81 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
82 board_82598 },
b95f5fcb
JB		 83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
84 board_82598 },
c4900be0
DS		 85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
86 board_82598 },
2f21bdd3
DS		 87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
88 board_82598 },
9a799d71
AK		 89
90 /* required last entry */
91 {0, }
92};
93MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
94
5dd2d332 95#ifdef CONFIG_IXGBE_DCA
bd0362dd 96static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
b4617240 97 void *p);
bd0362dd
JC		 98static struct notifier_block dca_notifier = {
99 .notifier_call = ixgbe_notify_dca,
100 .next = NULL,
101 .priority = 0
102};
103#endif
104
9a799d71
AK		 105MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
106MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
107MODULE_LICENSE("GPL");
108MODULE_VERSION(DRV_VERSION);
109
110#define DEFAULT_DEBUG_LEVEL_SHIFT 3
111
5eba3699
AV		 112static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
113{
114 u32 ctrl_ext;
115
116 /* Let firmware take over control of h/w */
117 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
118 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 119 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 120}
121
122static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
123{
124 u32 ctrl_ext;
125
126 /* Let firmware know the driver has taken over */
127 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
128 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 129 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 130}
9a799d71 131
9a799d71 132static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, u16 int_alloc_entry,
b4617240 133 u8 msix_vector)
9a799d71
AK		 134{
135 u32 ivar, index;
136
137 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
138 index = (int_alloc_entry >> 2) & 0x1F;
139 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR(index));
140 ivar &= ~(0xFF << (8 * (int_alloc_entry & 0x3)));
141 ivar |= (msix_vector << (8 * (int_alloc_entry & 0x3)));
142 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR(index), ivar);
143}
144
145static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
b4617240
PW		 146 struct ixgbe_tx_buffer
147 *tx_buffer_info)
9a799d71
AK		 148{
149 if (tx_buffer_info->dma) {
e01c31a5 150 pci_unmap_page(adapter->pdev, tx_buffer_info->dma,
b4617240 151 tx_buffer_info->length, PCI_DMA_TODEVICE);
9a799d71
AK		 152 tx_buffer_info->dma = 0;
153 }
154 if (tx_buffer_info->skb) {
155 dev_kfree_skb_any(tx_buffer_info->skb);
156 tx_buffer_info->skb = NULL;
157 }
158 /* tx_buffer_info must be completely set up in the transmit path */
159}
160
161static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
b4617240
PW		 162 struct ixgbe_ring *tx_ring,
163 unsigned int eop)
9a799d71 164{
e01c31a5
JB		 165 struct ixgbe_hw *hw = &adapter->hw;
166 u32 head, tail;
167
9a799d71 168 /* Detect a transmit hang in hardware, this serializes the
e01c31a5
JB		 169 * check with the clearing of time_stamp and movement of eop */
170 head = IXGBE_READ_REG(hw, tx_ring->head);
171 tail = IXGBE_READ_REG(hw, tx_ring->tail);
9a799d71 172 adapter->detect_tx_hung = false;
e01c31a5
JB		 173 if ((head != tail) &&
174 tx_ring->tx_buffer_info[eop].time_stamp &&
9a799d71
AK		 175 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
176 !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
177 /* detected Tx unit hang */
e01c31a5
JB		 178 union ixgbe_adv_tx_desc *tx_desc;
179 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
9a799d71 180 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
e01c31a5
JB		 181 " Tx Queue <%d>\n"
182 " TDH, TDT <%x>, <%x>\n"
9a799d71
AK		 183 " next_to_use <%x>\n"
184 " next_to_clean <%x>\n"
185 "tx_buffer_info[next_to_clean]\n"
186 " time_stamp <%lx>\n"
e01c31a5
JB		 187 " jiffies <%lx>\n",
188 tx_ring->queue_index,
189 head, tail,
190 tx_ring->next_to_use, eop,
191 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
9a799d71
AK		 192 return true;
193 }
194
195 return false;
196}
197
b4617240
PW		 198#define IXGBE_MAX_TXD_PWR 14
199#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
e092be60
AV		 200
201/* Tx Descriptors needed, worst case */
202#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
203 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
204#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
b4617240 205 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
e092be60 206
e01c31a5
JB		 207static void ixgbe_tx_timeout(struct net_device *netdev);
208
9a799d71
AK		 209/**
210 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
211 * @adapter: board private structure
e01c31a5 212 * @tx_ring: tx ring to clean
9a799d71
AK		 213 **/
214static bool ixgbe_clean_tx_irq(struct ixgbe_adapter *adapter,
e01c31a5 215 struct ixgbe_ring *tx_ring)
9a799d71 216{
e01c31a5 217 struct net_device *netdev = adapter->netdev;
12207e49
PWJ		 218 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
219 struct ixgbe_tx_buffer *tx_buffer_info;
220 unsigned int i, eop, count = 0;
e01c31a5 221 unsigned int total_bytes = 0, total_packets = 0;
9a799d71
AK		 222
223 i = tx_ring->next_to_clean;
12207e49
PWJ		 224 eop = tx_ring->tx_buffer_info[i].next_to_watch;
225 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
226
227 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
228 (count < tx_ring->count)) {
229 bool cleaned = false;
230 for ( ; !cleaned; count++) {
231 struct sk_buff *skb;
9a799d71
AK		 232 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
233 tx_buffer_info = &tx_ring->tx_buffer_info[i];
12207e49 234 cleaned = (i == eop);
e01c31a5 235 skb = tx_buffer_info->skb;
9a799d71 236
12207e49 237 if (cleaned && skb) {
e092be60 238 unsigned int segs, bytecount;
e01c31a5
JB		 239
240 /* gso_segs is currently only valid for tcp */
e092be60
AV		 241 segs = skb_shinfo(skb)->gso_segs ?: 1;
242 /* multiply data chunks by size of headers */
243 bytecount = ((segs - 1) * skb_headlen(skb)) +
e01c31a5
JB		 244 skb->len;
245 total_packets += segs;
246 total_bytes += bytecount;
e092be60 247 }
e01c31a5 248
9a799d71 249 ixgbe_unmap_and_free_tx_resource(adapter,
e01c31a5 250 tx_buffer_info);
9a799d71 251
12207e49
PWJ		 252 tx_desc->wb.status = 0;
253
9a799d71
AK		 254 i++;
255 if (i == tx_ring->count)
256 i = 0;
e01c31a5 257 }
12207e49
PWJ		 258
259 eop = tx_ring->tx_buffer_info[i].next_to_watch;
260 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
261 }
262
9a799d71
AK		 263 tx_ring->next_to_clean = i;
264
e092be60 265#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
e01c31a5
JB		 266 if (unlikely(count && netif_carrier_ok(netdev) &&
267 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 268 /* Make sure that anybody stopping the queue after this
269 * sees the new next_to_clean.
270 */
271 smp_mb();
30eba97a
AV		 272 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
273 !test_bit(__IXGBE_DOWN, &adapter->state)) {
274 netif_wake_subqueue(netdev, tx_ring->queue_index);
e01c31a5 275 ++adapter->restart_queue;
30eba97a 276 }
e092be60 277 }
9a799d71 278
e01c31a5
JB		 279 if (adapter->detect_tx_hung) {
280 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
281 /* schedule immediate reset if we believe we hung */
282 DPRINTK(PROBE, INFO,
283 "tx hang %d detected, resetting adapter\n",
284 adapter->tx_timeout_count + 1);
285 ixgbe_tx_timeout(adapter->netdev);
286 }
287 }
9a799d71 288
e01c31a5
JB		 289 /* re-arm the interrupt */
290 if ((total_packets >= tx_ring->work_limit) ||
291 (count == tx_ring->count))
292 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, tx_ring->v_idx);
9a799d71 293
e01c31a5
JB		 294 tx_ring->total_bytes += total_bytes;
295 tx_ring->total_packets += total_packets;
e01c31a5 296 tx_ring->stats.packets += total_packets;
12207e49 297 tx_ring->stats.bytes += total_bytes;
e01c31a5
JB		 298 adapter->net_stats.tx_bytes += total_bytes;
299 adapter->net_stats.tx_packets += total_packets;
300 return (total_packets ? true : false);
9a799d71
AK		 301}
302
5dd2d332 303#ifdef CONFIG_IXGBE_DCA
bd0362dd 304static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
b4617240 305 struct ixgbe_ring *rx_ring)
bd0362dd
JC		 306{
307 u32 rxctrl;
308 int cpu = get_cpu();
3a581073 309 int q = rx_ring - adapter->rx_ring;
bd0362dd 310
3a581073 311 if (rx_ring->cpu != cpu) {
bd0362dd
JC		 312 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
313 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
96b0e0f6 314 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
bd0362dd
JC		 315 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
316 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
15005a32
DS		 317 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
318 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
319 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
bd0362dd 320 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
3a581073 321 rx_ring->cpu = cpu;
bd0362dd
JC		 322 }
323 put_cpu();
324}
325
326static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
b4617240 327 struct ixgbe_ring *tx_ring)
bd0362dd
JC		 328{
329 u32 txctrl;
330 int cpu = get_cpu();
3a581073 331 int q = tx_ring - adapter->tx_ring;
bd0362dd 332
3a581073 333 if (tx_ring->cpu != cpu) {
bd0362dd
JC		 334 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
335 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
96b0e0f6 336 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
bd0362dd
JC		 337 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
338 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
3a581073 339 tx_ring->cpu = cpu;
bd0362dd
JC		 340 }
341 put_cpu();
342}
343
344static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
345{
346 int i;
347
348 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
349 return;
350
351 for (i = 0; i < adapter->num_tx_queues; i++) {
352 adapter->tx_ring[i].cpu = -1;
353 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
354 }
355 for (i = 0; i < adapter->num_rx_queues; i++) {
356 adapter->rx_ring[i].cpu = -1;
357 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
358 }
359}
360
361static int __ixgbe_notify_dca(struct device *dev, void *data)
362{
363 struct net_device *netdev = dev_get_drvdata(dev);
364 struct ixgbe_adapter *adapter = netdev_priv(netdev);
365 unsigned long event = *(unsigned long *)data;
366
367 switch (event) {
368 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 369 /* if we're already enabled, don't do it again */
370 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
371 break;
bd0362dd
JC		 372 /* Always use CB2 mode, difference is masked
373 * in the CB driver. */
374 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
652f093f 375 if (dca_add_requester(dev) == 0) {
96b0e0f6 376 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 377 ixgbe_setup_dca(adapter);
378 break;
379 }
380 /* Fall Through since DCA is disabled. */
381 case DCA_PROVIDER_REMOVE:
382 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
383 dca_remove_requester(dev);
384 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
385 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
386 }
387 break;
388 }
389
652f093f 390 return 0;
bd0362dd
JC		 391}
392
5dd2d332 393#endif /* CONFIG_IXGBE_DCA */
9a799d71
AK		 394/**
395 * ixgbe_receive_skb - Send a completed packet up the stack
396 * @adapter: board private structure
397 * @skb: packet to send up
177db6ff
MC		 398 * @status: hardware indication of status of receive
399 * @rx_ring: rx descriptor ring (for a specific queue) to setup
400 * @rx_desc: rx descriptor
9a799d71 401 **/
78b6f4ce 402static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
b4617240 403 struct sk_buff *skb, u8 status,
177db6ff 404 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 405{
78b6f4ce
HX		 406 struct ixgbe_adapter *adapter = q_vector->adapter;
407 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 408 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
409 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 410
0c8dfc83 411 skb_record_rx_queue(skb, q_vector - &adapter->q_vector[0]);
78b6f4ce 412 if (skb->ip_summed == CHECKSUM_UNNECESSARY) {
2f90b865 413 if (adapter->vlgrp && is_vlan && (tag != 0))
78b6f4ce 414 vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
9a799d71 415 else
78b6f4ce 416 napi_gro_receive(napi, skb);
177db6ff
MC		 417 } else {
418 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
2f90b865 419 if (adapter->vlgrp && is_vlan && (tag != 0))
177db6ff
MC		 420 vlan_hwaccel_receive_skb(skb, adapter->vlgrp, tag);
421 else
422 netif_receive_skb(skb);
423 } else {
2f90b865 424 if (adapter->vlgrp && is_vlan && (tag != 0))
177db6ff
MC		 425 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
426 else
427 netif_rx(skb);
428 }
9a799d71
AK		 429 }
430}
431
e59bd25d
AV		 432/**
433 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
434 * @adapter: address of board private structure
435 * @status_err: hardware indication of status of receive
436 * @skb: skb currently being received and modified
437 **/
9a799d71 438static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
712744be 439 u32 status_err, struct sk_buff *skb)
9a799d71
AK		 440{
441 skb->ip_summed = CHECKSUM_NONE;
442
712744be
JB		 443 /* Rx csum disabled */
444 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 445 return;
e59bd25d
AV		 446
447 /* if IP and error */
448 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
449 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 450 adapter->hw_csum_rx_error++;
451 return;
452 }
e59bd25d
AV		 453
454 if (!(status_err & IXGBE_RXD_STAT_L4CS))
455 return;
456
457 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
458 adapter->hw_csum_rx_error++;
459 return;
460 }
461
9a799d71 462 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 463 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 464 adapter->hw_csum_rx_good++;
465}
466
467/**
468 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
469 * @adapter: address of board private structure
470 **/
471static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
7c6e0a43
JB		 472 struct ixgbe_ring *rx_ring,
473 int cleaned_count)
9a799d71 474{
9a799d71
AK		 475 struct pci_dev *pdev = adapter->pdev;
476 union ixgbe_adv_rx_desc *rx_desc;
3a581073 477 struct ixgbe_rx_buffer *bi;
9a799d71 478 unsigned int i;
9a799d71
AK		 479
480 i = rx_ring->next_to_use;
3a581073 481 bi = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 482
483 while (cleaned_count--) {
484 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
485
762f4c57 486 if (!bi->page_dma &&
3a581073 487 (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) {
3a581073 488 if (!bi->page) {
762f4c57
JB		 489 bi->page = alloc_page(GFP_ATOMIC);
490 if (!bi->page) {
491 adapter->alloc_rx_page_failed++;
492 goto no_buffers;
493 }
494 bi->page_offset = 0;
495 } else {
496 /* use a half page if we're re-using */
497 bi->page_offset ^= (PAGE_SIZE / 2);
9a799d71 498 }
762f4c57
JB		 499
500 bi->page_dma = pci_map_page(pdev, bi->page,
501 bi->page_offset,
502 (PAGE_SIZE / 2),
503 PCI_DMA_FROMDEVICE);
9a799d71
AK		 504 }
505
3a581073 506 if (!bi->skb) {
5ecc3614
JB		 507 struct sk_buff *skb;
508 skb = netdev_alloc_skb(adapter->netdev,
509 (rx_ring->rx_buf_len +
510 NET_IP_ALIGN));
9a799d71
AK		 511
512 if (!skb) {
513 adapter->alloc_rx_buff_failed++;
514 goto no_buffers;
515 }
516
517 /*
518 * Make buffer alignment 2 beyond a 16 byte boundary
519 * this will result in a 16 byte aligned IP header after
520 * the 14 byte MAC header is removed
521 */
522 skb_reserve(skb, NET_IP_ALIGN);
523
3a581073 524 bi->skb = skb;
5ecc3614
JB		 525 bi->dma = pci_map_single(pdev, skb->data,
526 rx_ring->rx_buf_len,
3a581073 527 PCI_DMA_FROMDEVICE);
9a799d71
AK		 528 }
529 /* Refresh the desc even if buffer_addrs didn't change because
530 * each write-back erases this info. */
531 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
3a581073
JB		 532 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
533 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 534 } else {
3a581073 535 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
9a799d71
AK		 536 }
537
538 i++;
539 if (i == rx_ring->count)
540 i = 0;
3a581073 541 bi = &rx_ring->rx_buffer_info[i];
9a799d71 542 }
7c6e0a43 543
9a799d71
AK		 544no_buffers:
545 if (rx_ring->next_to_use != i) {
546 rx_ring->next_to_use = i;
547 if (i-- == 0)
548 i = (rx_ring->count - 1);
549
550 /*
551 * Force memory writes to complete before letting h/w
552 * know there are new descriptors to fetch. (Only
553 * applicable for weak-ordered memory model archs,
554 * such as IA-64).
555 */
556 wmb();
557 writel(i, adapter->hw.hw_addr + rx_ring->tail);
558 }
559}
560
7c6e0a43
JB		 561static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
562{
563 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
564}
565
566static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
567{
568 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
569}
570
78b6f4ce 571static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
b4617240
PW		 572 struct ixgbe_ring *rx_ring,
573 int *work_done, int work_to_do)
9a799d71 574{
78b6f4ce 575 struct ixgbe_adapter *adapter = q_vector->adapter;
9a799d71
AK		 576 struct pci_dev *pdev = adapter->pdev;
577 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
578 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
579 struct sk_buff *skb;
580 unsigned int i;
7c6e0a43 581 u32 len, staterr;
177db6ff
MC		 582 u16 hdr_info;
583 bool cleaned = false;
9a799d71 584 int cleaned_count = 0;
d2f4fbe2 585 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
9a799d71
AK		 586
587 i = rx_ring->next_to_clean;
9a799d71
AK		 588 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
589 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
590 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 591
592 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 593 u32 upper_len = 0;
9a799d71
AK		 594 if (*work_done >= work_to_do)
595 break;
596 (*work_done)++;
597
598 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43
JB		 599 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
600 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
762f4c57 601 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
9a799d71
AK		 602 if (hdr_info & IXGBE_RXDADV_SPH)
603 adapter->rx_hdr_split++;
604 if (len > IXGBE_RX_HDR_SIZE)
605 len = IXGBE_RX_HDR_SIZE;
606 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 607 } else {
9a799d71 608 len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 609 }
9a799d71
AK		 610
611 cleaned = true;
612 skb = rx_buffer_info->skb;
613 prefetch(skb->data - NET_IP_ALIGN);
614 rx_buffer_info->skb = NULL;
615
616 if (len && !skb_shinfo(skb)->nr_frags) {
617 pci_unmap_single(pdev, rx_buffer_info->dma,
5ecc3614 618 rx_ring->rx_buf_len,
b4617240 619 PCI_DMA_FROMDEVICE);
9a799d71
AK		 620 skb_put(skb, len);
621 }
622
623 if (upper_len) {
624 pci_unmap_page(pdev, rx_buffer_info->page_dma,
762f4c57 625 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9a799d71
AK		 626 rx_buffer_info->page_dma = 0;
627 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
762f4c57
JB		 628 rx_buffer_info->page,
629 rx_buffer_info->page_offset,
630 upper_len);
631
632 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
633 (page_count(rx_buffer_info->page) != 1))
634 rx_buffer_info->page = NULL;
635 else
636 get_page(rx_buffer_info->page);
9a799d71
AK		 637
638 skb->len += upper_len;
639 skb->data_len += upper_len;
640 skb->truesize += upper_len;
641 }
642
643 i++;
644 if (i == rx_ring->count)
645 i = 0;
646 next_buffer = &rx_ring->rx_buffer_info[i];
647
648 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
649 prefetch(next_rxd);
650
651 cleaned_count++;
652 if (staterr & IXGBE_RXD_STAT_EOP) {
653 rx_ring->stats.packets++;
654 rx_ring->stats.bytes += skb->len;
655 } else {
656 rx_buffer_info->skb = next_buffer->skb;
657 rx_buffer_info->dma = next_buffer->dma;
658 next_buffer->skb = skb;
762f4c57 659 next_buffer->dma = 0;
9a799d71
AK		 660 adapter->non_eop_descs++;
661 goto next_desc;
662 }
663
664 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
665 dev_kfree_skb_irq(skb);
666 goto next_desc;
667 }
668
669 ixgbe_rx_checksum(adapter, staterr, skb);
d2f4fbe2
AV		 670
671 /* probably a little skewed due to removing CRC */
672 total_rx_bytes += skb->len;
673 total_rx_packets++;
674
74ce8dd2 675 skb->protocol = eth_type_trans(skb, adapter->netdev);
78b6f4ce 676 ixgbe_receive_skb(q_vector, skb, staterr, rx_desc);
9a799d71
AK		 677
678next_desc:
679 rx_desc->wb.upper.status_error = 0;
680
681 /* return some buffers to hardware, one at a time is too slow */
682 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
683 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
684 cleaned_count = 0;
685 }
686
687 /* use prefetched values */
688 rx_desc = next_rxd;
689 rx_buffer_info = next_buffer;
690
691 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 692 }
693
9a799d71
AK		 694 rx_ring->next_to_clean = i;
695 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
696
697 if (cleaned_count)
698 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
699
f494e8fa
AV		 700 rx_ring->total_packets += total_rx_packets;
701 rx_ring->total_bytes += total_rx_bytes;
702 adapter->net_stats.rx_bytes += total_rx_bytes;
703 adapter->net_stats.rx_packets += total_rx_packets;
704
9a799d71
AK		 705 return cleaned;
706}
707
021230d4 708static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 709/**
710 * ixgbe_configure_msix - Configure MSI-X hardware
711 * @adapter: board private structure
712 *
713 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
714 * interrupts.
715 **/
716static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
717{
021230d4
AV		 718 struct ixgbe_q_vector *q_vector;
719 int i, j, q_vectors, v_idx, r_idx;
720 u32 mask;
9a799d71 721
021230d4 722 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 723
021230d4
AV		 724 /* Populate the IVAR table and set the ITR values to the
725 * corresponding register.
726 */
727 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
728 q_vector = &adapter->q_vector[v_idx];
729 /* XXX for_each_bit(...) */
730 r_idx = find_first_bit(q_vector->rxr_idx,
b4617240 731 adapter->num_rx_queues);
021230d4
AV		 732
733 for (i = 0; i < q_vector->rxr_count; i++) {
734 j = adapter->rx_ring[r_idx].reg_idx;
735 ixgbe_set_ivar(adapter, IXGBE_IVAR_RX_QUEUE(j), v_idx);
736 r_idx = find_next_bit(q_vector->rxr_idx,
b4617240
PW		 737 adapter->num_rx_queues,
738 r_idx + 1);
021230d4
AV		 739 }
740 r_idx = find_first_bit(q_vector->txr_idx,
b4617240 741 adapter->num_tx_queues);
021230d4
AV		 742
743 for (i = 0; i < q_vector->txr_count; i++) {
744 j = adapter->tx_ring[r_idx].reg_idx;
745 ixgbe_set_ivar(adapter, IXGBE_IVAR_TX_QUEUE(j), v_idx);
746 r_idx = find_next_bit(q_vector->txr_idx,
b4617240
PW		 747 adapter->num_tx_queues,
748 r_idx + 1);
021230d4
AV		 749 }
750
30efa5a3 751 /* if this is a tx only vector halve the interrupt rate */
021230d4 752 if (q_vector->txr_count && !q_vector->rxr_count)
30efa5a3 753 q_vector->eitr = (adapter->eitr_param >> 1);
021230d4 754 else
30efa5a3
JB		 755 /* rx only */
756 q_vector->eitr = adapter->eitr_param;
021230d4
AV		 757
758 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx),
b4617240 759 EITR_INTS_PER_SEC_TO_REG(q_vector->eitr));
9a799d71
AK		 760 }
761
021230d4
AV		 762 ixgbe_set_ivar(adapter, IXGBE_IVAR_OTHER_CAUSES_INDEX, v_idx);
763 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
764
41fb9248 765 /* set up to autoclear timer, and the vectors */
021230d4 766 mask = IXGBE_EIMS_ENABLE_MASK;
41fb9248 767 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 768 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 769}
770
f494e8fa
AV		 771enum latency_range {
772 lowest_latency = 0,
773 low_latency = 1,
774 bulk_latency = 2,
775 latency_invalid = 255
776};
777
778/**
779 * ixgbe_update_itr - update the dynamic ITR value based on statistics
780 * @adapter: pointer to adapter
781 * @eitr: eitr setting (ints per sec) to give last timeslice
782 * @itr_setting: current throttle rate in ints/second
783 * @packets: the number of packets during this measurement interval
784 * @bytes: the number of bytes during this measurement interval
785 *
786 * Stores a new ITR value based on packets and byte
787 * counts during the last interrupt. The advantage of per interrupt
788 * computation is faster updates and more accurate ITR for the current
789 * traffic pattern. Constants in this function were computed
790 * based on theoretical maximum wire speed and thresholds were set based
791 * on testing data as well as attempting to minimize response time
792 * while increasing bulk throughput.
793 * this functionality is controlled by the InterruptThrottleRate module
794 * parameter (see ixgbe_param.c)
795 **/
796static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
b4617240
PW		 797 u32 eitr, u8 itr_setting,
798 int packets, int bytes)
f494e8fa
AV		 799{
800 unsigned int retval = itr_setting;
801 u32 timepassed_us;
802 u64 bytes_perint;
803
804 if (packets == 0)
805 goto update_itr_done;
806
807
808 /* simple throttlerate management
809 * 0-20MB/s lowest (100000 ints/s)
810 * 20-100MB/s low (20000 ints/s)
811 * 100-1249MB/s bulk (8000 ints/s)
812 */
813 /* what was last interrupt timeslice? */
814 timepassed_us = 1000000/eitr;
815 bytes_perint = bytes / timepassed_us; /* bytes/usec */
816
817 switch (itr_setting) {
818 case lowest_latency:
819 if (bytes_perint > adapter->eitr_low)
820 retval = low_latency;
821 break;
822 case low_latency:
823 if (bytes_perint > adapter->eitr_high)
824 retval = bulk_latency;
825 else if (bytes_perint <= adapter->eitr_low)
826 retval = lowest_latency;
827 break;
828 case bulk_latency:
829 if (bytes_perint <= adapter->eitr_high)
830 retval = low_latency;
831 break;
832 }
833
834update_itr_done:
835 return retval;
836}
837
838static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
839{
840 struct ixgbe_adapter *adapter = q_vector->adapter;
841 struct ixgbe_hw *hw = &adapter->hw;
842 u32 new_itr;
843 u8 current_itr, ret_itr;
844 int i, r_idx, v_idx = ((void *)q_vector - (void *)(adapter->q_vector)) /
b4617240 845 sizeof(struct ixgbe_q_vector);
f494e8fa
AV		 846 struct ixgbe_ring *rx_ring, *tx_ring;
847
848 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
849 for (i = 0; i < q_vector->txr_count; i++) {
850 tx_ring = &(adapter->tx_ring[r_idx]);
851 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 852 q_vector->tx_itr,
853 tx_ring->total_packets,
854 tx_ring->total_bytes);
f494e8fa
AV		 855 /* if the result for this queue would decrease interrupt
856 * rate for this vector then use that result */
30efa5a3 857 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
b4617240 858 q_vector->tx_itr - 1 : ret_itr);
f494e8fa 859 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 860 r_idx + 1);
f494e8fa
AV		 861 }
862
863 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
864 for (i = 0; i < q_vector->rxr_count; i++) {
865 rx_ring = &(adapter->rx_ring[r_idx]);
866 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 867 q_vector->rx_itr,
868 rx_ring->total_packets,
869 rx_ring->total_bytes);
f494e8fa
AV		 870 /* if the result for this queue would decrease interrupt
871 * rate for this vector then use that result */
30efa5a3 872 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
b4617240 873 q_vector->rx_itr - 1 : ret_itr);
f494e8fa 874 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
b4617240 875 r_idx + 1);
f494e8fa
AV		 876 }
877
30efa5a3 878 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 879
880 switch (current_itr) {
881 /* counts and packets in update_itr are dependent on these numbers */
882 case lowest_latency:
883 new_itr = 100000;
884 break;
885 case low_latency:
886 new_itr = 20000; /* aka hwitr = ~200 */
887 break;
888 case bulk_latency:
889 default:
890 new_itr = 8000;
891 break;
892 }
893
894 if (new_itr != q_vector->eitr) {
895 u32 itr_reg;
896 /* do an exponential smoothing */
897 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
898 q_vector->eitr = new_itr;
899 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
900 /* must write high and low 16 bits to reset counter */
901 DPRINTK(TX_ERR, DEBUG, "writing eitr(%d): %08X\n", v_idx,
b4617240 902 itr_reg);
f494e8fa
AV		 903 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg | (itr_reg)<<16);
904 }
905
906 return;
907}
908
0befdb3e
JB		 909static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
910{
911 struct ixgbe_hw *hw = &adapter->hw;
912
913 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
914 (eicr & IXGBE_EICR_GPI_SDP1)) {
915 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
916 /* write to clear the interrupt */
917 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
918 }
919}
cf8280ee
JB		 920
921static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
922{
923 struct ixgbe_hw *hw = &adapter->hw;
924
925 adapter->lsc_int++;
926 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
927 adapter->link_check_timeout = jiffies;
928 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
929 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
930 schedule_work(&adapter->watchdog_task);
931 }
932}
933
9a799d71
AK		 934static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
935{
936 struct net_device *netdev = data;
937 struct ixgbe_adapter *adapter = netdev_priv(netdev);
938 struct ixgbe_hw *hw = &adapter->hw;
54037505
DS		 939 u32 eicr;
940
941 /*
942 * Workaround for Silicon errata. Use clear-by-write instead
943 * of clear-by-read. Reading with EICS will return the
944 * interrupt causes without clearing, which later be done
945 * with the write to EICR.
946 */
947 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
948 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
9a799d71 949
cf8280ee
JB		 950 if (eicr & IXGBE_EICR_LSC)
951 ixgbe_check_lsc(adapter);
d4f80882 952
0befdb3e
JB		 953 ixgbe_check_fan_failure(adapter, eicr);
954
d4f80882
AV		 955 if (!test_bit(__IXGBE_DOWN, &adapter->state))
956 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 957
958 return IRQ_HANDLED;
959}
960
961static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
962{
021230d4
AV		 963 struct ixgbe_q_vector *q_vector = data;
964 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 965 struct ixgbe_ring *tx_ring;
021230d4
AV		 966 int i, r_idx;
967
968 if (!q_vector->txr_count)
969 return IRQ_HANDLED;
970
971 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
972 for (i = 0; i < q_vector->txr_count; i++) {
3a581073 973 tx_ring = &(adapter->tx_ring[r_idx]);
5dd2d332 974#ifdef CONFIG_IXGBE_DCA
bd0362dd 975 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 976 ixgbe_update_tx_dca(adapter, tx_ring);
bd0362dd 977#endif
3a581073
JB		 978 tx_ring->total_bytes = 0;
979 tx_ring->total_packets = 0;
980 ixgbe_clean_tx_irq(adapter, tx_ring);
021230d4 981 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 982 r_idx + 1);
021230d4 983 }
9a799d71 984
9a799d71
AK		 985 return IRQ_HANDLED;
986}
987
021230d4
AV		 988/**
989 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
990 * @irq: unused
991 * @data: pointer to our q_vector struct for this interrupt vector
992 **/
9a799d71
AK		 993static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
994{
021230d4
AV		 995 struct ixgbe_q_vector *q_vector = data;
996 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 997 struct ixgbe_ring *rx_ring;
021230d4 998 int r_idx;
30efa5a3 999 int i;
021230d4
AV		 1000
1001 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
30efa5a3
JB		 1002 for (i = 0; i < q_vector->rxr_count; i++) {
1003 rx_ring = &(adapter->rx_ring[r_idx]);
1004 rx_ring->total_bytes = 0;
1005 rx_ring->total_packets = 0;
1006 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1007 r_idx + 1);
1008 }
1009
021230d4
AV		 1010 if (!q_vector->rxr_count)
1011 return IRQ_HANDLED;
1012
30efa5a3 1013 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
3a581073 1014 rx_ring = &(adapter->rx_ring[r_idx]);
021230d4 1015 /* disable interrupts on this vector only */
3a581073 1016 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, rx_ring->v_idx);
288379f0 1017 napi_schedule(&q_vector->napi);
021230d4
AV		 1018
1019 return IRQ_HANDLED;
1020}
1021
1022static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1023{
1024 ixgbe_msix_clean_rx(irq, data);
1025 ixgbe_msix_clean_tx(irq, data);
9a799d71 1026
9a799d71
AK		 1027 return IRQ_HANDLED;
1028}
1029
021230d4
AV		 1030/**
1031 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1032 * @napi: napi struct with our devices info in it
1033 * @budget: amount of work driver is allowed to do this pass, in packets
1034 *
f0848276
JB		 1035 * This function is optimized for cleaning one queue only on a single
1036 * q_vector!!!
021230d4 1037 **/
9a799d71
AK		 1038static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1039{
021230d4 1040 struct ixgbe_q_vector *q_vector =
b4617240 1041 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 1042 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 1043 struct ixgbe_ring *rx_ring = NULL;
9a799d71 1044 int work_done = 0;
021230d4 1045 long r_idx;
9a799d71 1046
021230d4 1047 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
3a581073 1048 rx_ring = &(adapter->rx_ring[r_idx]);
5dd2d332 1049#ifdef CONFIG_IXGBE_DCA
bd0362dd 1050 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1051 ixgbe_update_rx_dca(adapter, rx_ring);
bd0362dd 1052#endif
9a799d71 1053
78b6f4ce 1054 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
9a799d71 1055
021230d4
AV		 1056 /* If all Rx work done, exit the polling mode */
1057 if (work_done < budget) {
288379f0 1058 napi_complete(napi);
30efa5a3 1059 if (adapter->itr_setting & 3)
f494e8fa 1060 ixgbe_set_itr_msix(q_vector);
9a799d71 1061 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3a581073 1062 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, rx_ring->v_idx);
9a799d71
AK		 1063 }
1064
1065 return work_done;
1066}
1067
f0848276
JB		 1068/**
1069 * ixgbe_clean_rxonly_many - msix (aka one shot) rx clean routine
1070 * @napi: napi struct with our devices info in it
1071 * @budget: amount of work driver is allowed to do this pass, in packets
1072 *
1073 * This function will clean more than one rx queue associated with a
1074 * q_vector.
1075 **/
1076static int ixgbe_clean_rxonly_many(struct napi_struct *napi, int budget)
1077{
1078 struct ixgbe_q_vector *q_vector =
1079 container_of(napi, struct ixgbe_q_vector, napi);
1080 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276
JB		 1081 struct ixgbe_ring *rx_ring = NULL;
1082 int work_done = 0, i;
1083 long r_idx;
1084 u16 enable_mask = 0;
1085
1086 /* attempt to distribute budget to each queue fairly, but don't allow
1087 * the budget to go below 1 because we'll exit polling */
1088 budget /= (q_vector->rxr_count ?: 1);
1089 budget = max(budget, 1);
1090 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1091 for (i = 0; i < q_vector->rxr_count; i++) {
1092 rx_ring = &(adapter->rx_ring[r_idx]);
5dd2d332 1093#ifdef CONFIG_IXGBE_DCA
f0848276
JB		 1094 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1095 ixgbe_update_rx_dca(adapter, rx_ring);
1096#endif
78b6f4ce 1097 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
f0848276
JB		 1098 enable_mask |= rx_ring->v_idx;
1099 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1100 r_idx + 1);
1101 }
1102
1103 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1104 rx_ring = &(adapter->rx_ring[r_idx]);
1105 /* If all Rx work done, exit the polling mode */
7f821875 1106 if (work_done < budget) {
288379f0 1107 napi_complete(napi);
f0848276
JB		 1108 if (adapter->itr_setting & 3)
1109 ixgbe_set_itr_msix(q_vector);
1110 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1111 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, enable_mask);
1112 return 0;
1113 }
1114
1115 return work_done;
1116}
021230d4 1117static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
b4617240 1118 int r_idx)
021230d4
AV		 1119{
1120 a->q_vector[v_idx].adapter = a;
1121 set_bit(r_idx, a->q_vector[v_idx].rxr_idx);
1122 a->q_vector[v_idx].rxr_count++;
1123 a->rx_ring[r_idx].v_idx = 1 << v_idx;
1124}
1125
1126static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
b4617240 1127 int r_idx)
021230d4
AV		 1128{
1129 a->q_vector[v_idx].adapter = a;
1130 set_bit(r_idx, a->q_vector[v_idx].txr_idx);
1131 a->q_vector[v_idx].txr_count++;
1132 a->tx_ring[r_idx].v_idx = 1 << v_idx;
1133}
1134
9a799d71 1135/**
021230d4
AV		 1136 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1137 * @adapter: board private structure to initialize
1138 * @vectors: allotted vector count for descriptor rings
9a799d71 1139 *
021230d4
AV		 1140 * This function maps descriptor rings to the queue-specific vectors
1141 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1142 * one vector per ring/queue, but on a constrained vector budget, we
1143 * group the rings as "efficiently" as possible. You would add new
1144 * mapping configurations in here.
9a799d71 1145 **/
021230d4 1146static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
b4617240 1147 int vectors)
021230d4
AV		 1148{
1149 int v_start = 0;
1150 int rxr_idx = 0, txr_idx = 0;
1151 int rxr_remaining = adapter->num_rx_queues;
1152 int txr_remaining = adapter->num_tx_queues;
1153 int i, j;
1154 int rqpv, tqpv;
1155 int err = 0;
1156
1157 /* No mapping required if MSI-X is disabled. */
1158 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1159 goto out;
9a799d71 1160
021230d4
AV		 1161 /*
1162 * The ideal configuration...
1163 * We have enough vectors to map one per queue.
1164 */
1165 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1166 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1167 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 1168
021230d4
AV		 1169 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1170 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 1171
9a799d71 1172 goto out;
021230d4 1173 }
9a799d71 1174
021230d4
AV		 1175 /*
1176 * If we don't have enough vectors for a 1-to-1
1177 * mapping, we'll have to group them so there are
1178 * multiple queues per vector.
1179 */
1180 /* Re-adjusting *qpv takes care of the remainder. */
1181 for (i = v_start; i < vectors; i++) {
1182 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1183 for (j = 0; j < rqpv; j++) {
1184 map_vector_to_rxq(adapter, i, rxr_idx);
1185 rxr_idx++;
1186 rxr_remaining--;
1187 }
1188 }
1189 for (i = v_start; i < vectors; i++) {
1190 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1191 for (j = 0; j < tqpv; j++) {
1192 map_vector_to_txq(adapter, i, txr_idx);
1193 txr_idx++;
1194 txr_remaining--;
9a799d71 1195 }
9a799d71
AK		 1196 }
1197
021230d4
AV		 1198out:
1199 return err;
1200}
1201
1202/**
1203 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1204 * @adapter: board private structure
1205 *
1206 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1207 * interrupts from the kernel.
1208 **/
1209static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1210{
1211 struct net_device *netdev = adapter->netdev;
1212 irqreturn_t (*handler)(int, void *);
1213 int i, vector, q_vectors, err;
cb13fc20 1214 int ri=0, ti=0;
021230d4
AV		 1215
1216 /* Decrement for Other and TCP Timer vectors */
1217 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1218
1219 /* Map the Tx/Rx rings to the vectors we were allotted. */
1220 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1221 if (err)
1222 goto out;
1223
1224#define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
b4617240
PW		 1225 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1226 &ixgbe_msix_clean_many)
021230d4
AV		 1227 for (vector = 0; vector < q_vectors; vector++) {
1228 handler = SET_HANDLER(&adapter->q_vector[vector]);
cb13fc20
RO		 1229
1230 if(handler == &ixgbe_msix_clean_rx) {
1231 sprintf(adapter->name[vector], "%s-%s-%d",
1232 netdev->name, "rx", ri++);
1233 }
1234 else if(handler == &ixgbe_msix_clean_tx) {
1235 sprintf(adapter->name[vector], "%s-%s-%d",
1236 netdev->name, "tx", ti++);
1237 }
1238 else
1239 sprintf(adapter->name[vector], "%s-%s-%d",
1240 netdev->name, "TxRx", vector);
1241
021230d4 1242 err = request_irq(adapter->msix_entries[vector].vector,
b4617240
PW		 1243 handler, 0, adapter->name[vector],
1244 &(adapter->q_vector[vector]));
9a799d71
AK		 1245 if (err) {
1246 DPRINTK(PROBE, ERR,
b4617240
PW		 1247 "request_irq failed for MSIX interrupt "
1248 "Error: %d\n", err);
021230d4 1249 goto free_queue_irqs;
9a799d71 1250 }
9a799d71
AK		 1251 }
1252
021230d4
AV		 1253 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1254 err = request_irq(adapter->msix_entries[vector].vector,
b4617240 1255 &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
9a799d71
AK		 1256 if (err) {
1257 DPRINTK(PROBE, ERR,
1258 "request_irq for msix_lsc failed: %d\n", err);
021230d4 1259 goto free_queue_irqs;
9a799d71
AK		 1260 }
1261
9a799d71
AK		 1262 return 0;
1263
021230d4
AV		 1264free_queue_irqs:
1265 for (i = vector - 1; i >= 0; i--)
1266 free_irq(adapter->msix_entries[--vector].vector,
b4617240 1267 &(adapter->q_vector[i]));
021230d4
AV		 1268 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1269 pci_disable_msix(adapter->pdev);
9a799d71
AK		 1270 kfree(adapter->msix_entries);
1271 adapter->msix_entries = NULL;
021230d4 1272out:
9a799d71
AK		 1273 return err;
1274}
1275
f494e8fa
AV		 1276static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1277{
1278 struct ixgbe_hw *hw = &adapter->hw;
1279 struct ixgbe_q_vector *q_vector = adapter->q_vector;
1280 u8 current_itr;
1281 u32 new_itr = q_vector->eitr;
1282 struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1283 struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1284
30efa5a3 1285 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1286 q_vector->tx_itr,
1287 tx_ring->total_packets,
1288 tx_ring->total_bytes);
30efa5a3 1289 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1290 q_vector->rx_itr,
1291 rx_ring->total_packets,
1292 rx_ring->total_bytes);
f494e8fa 1293
30efa5a3 1294 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1295
1296 switch (current_itr) {
1297 /* counts and packets in update_itr are dependent on these numbers */
1298 case lowest_latency:
1299 new_itr = 100000;
1300 break;
1301 case low_latency:
1302 new_itr = 20000; /* aka hwitr = ~200 */
1303 break;
1304 case bulk_latency:
1305 new_itr = 8000;
1306 break;
1307 default:
1308 break;
1309 }
1310
1311 if (new_itr != q_vector->eitr) {
1312 u32 itr_reg;
1313 /* do an exponential smoothing */
1314 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1315 q_vector->eitr = new_itr;
1316 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
1317 /* must write high and low 16 bits to reset counter */
1318 IXGBE_WRITE_REG(hw, IXGBE_EITR(0), itr_reg | (itr_reg)<<16);
1319 }
1320
1321 return;
1322}
1323
79aefa45
AD		 1324/**
1325 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1326 * @adapter: board private structure
1327 **/
1328static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1329{
1330 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1331 IXGBE_WRITE_FLUSH(&adapter->hw);
1332 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1333 int i;
1334 for (i = 0; i < adapter->num_msix_vectors; i++)
1335 synchronize_irq(adapter->msix_entries[i].vector);
1336 } else {
1337 synchronize_irq(adapter->pdev->irq);
1338 }
1339}
1340
1341/**
1342 * ixgbe_irq_enable - Enable default interrupt generation settings
1343 * @adapter: board private structure
1344 **/
1345static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1346{
1347 u32 mask;
1348 mask = IXGBE_EIMS_ENABLE_MASK;
6ab33d51
DM		 1349 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1350 mask |= IXGBE_EIMS_GPI_SDP1;
79aefa45
AD		 1351 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1352 IXGBE_WRITE_FLUSH(&adapter->hw);
1353}
021230d4 1354
9a799d71 1355/**
021230d4 1356 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 1357 * @irq: interrupt number
1358 * @data: pointer to a network interface device structure
9a799d71
AK		 1359 **/
1360static irqreturn_t ixgbe_intr(int irq, void *data)
1361{
1362 struct net_device *netdev = data;
1363 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1364 struct ixgbe_hw *hw = &adapter->hw;
1365 u32 eicr;
1366
54037505
DS		 1367 /*
1368 * Workaround for silicon errata. Mask the interrupts
1369 * before the read of EICR.
1370 */
1371 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1372
021230d4
AV		 1373 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1374 * therefore no explict interrupt disable is necessary */
1375 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e
JB		 1376 if (!eicr) {
1377 /* shared interrupt alert!
1378 * make sure interrupts are enabled because the read will
1379 * have disabled interrupts due to EIAM */
1380 ixgbe_irq_enable(adapter);
9a799d71 1381 return IRQ_NONE; /* Not our interrupt */
f47cf66e 1382 }
9a799d71 1383
cf8280ee
JB		 1384 if (eicr & IXGBE_EICR_LSC)
1385 ixgbe_check_lsc(adapter);
021230d4 1386
0befdb3e
JB		 1387 ixgbe_check_fan_failure(adapter, eicr);
1388
288379f0 1389 if (napi_schedule_prep(&adapter->q_vector[0].napi)) {
f494e8fa
AV		 1390 adapter->tx_ring[0].total_packets = 0;
1391 adapter->tx_ring[0].total_bytes = 0;
1392 adapter->rx_ring[0].total_packets = 0;
1393 adapter->rx_ring[0].total_bytes = 0;
021230d4 1394 /* would disable interrupts here but EIAM disabled it */
288379f0 1395 __napi_schedule(&adapter->q_vector[0].napi);
9a799d71
AK		 1396 }
1397
1398 return IRQ_HANDLED;
1399}
1400
021230d4
AV		 1401static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1402{
1403 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1404
1405 for (i = 0; i < q_vectors; i++) {
1406 struct ixgbe_q_vector *q_vector = &adapter->q_vector[i];
1407 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1408 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1409 q_vector->rxr_count = 0;
1410 q_vector->txr_count = 0;
1411 }
1412}
1413
9a799d71
AK		 1414/**
1415 * ixgbe_request_irq - initialize interrupts
1416 * @adapter: board private structure
1417 *
1418 * Attempts to configure interrupts using the best available
1419 * capabilities of the hardware and kernel.
1420 **/
021230d4 1421static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 1422{
1423 struct net_device *netdev = adapter->netdev;
021230d4 1424 int err;
9a799d71 1425
021230d4
AV		 1426 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1427 err = ixgbe_request_msix_irqs(adapter);
1428 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1429 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
b4617240 1430 netdev->name, netdev);
021230d4
AV		 1431 } else {
1432 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
b4617240 1433 netdev->name, netdev);
9a799d71
AK		 1434 }
1435
9a799d71
AK		 1436 if (err)
1437 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1438
9a799d71
AK		 1439 return err;
1440}
1441
1442static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1443{
1444 struct net_device *netdev = adapter->netdev;
1445
1446 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 1447 int i, q_vectors;
9a799d71 1448
021230d4
AV		 1449 q_vectors = adapter->num_msix_vectors;
1450
1451 i = q_vectors - 1;
9a799d71 1452 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 1453
021230d4
AV		 1454 i--;
1455 for (; i >= 0; i--) {
1456 free_irq(adapter->msix_entries[i].vector,
b4617240 1457 &(adapter->q_vector[i]));
021230d4
AV		 1458 }
1459
1460 ixgbe_reset_q_vectors(adapter);
1461 } else {
1462 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 1463 }
1464}
1465
9a799d71
AK		 1466/**
1467 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1468 *
1469 **/
1470static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1471{
9a799d71
AK		 1472 struct ixgbe_hw *hw = &adapter->hw;
1473
021230d4 1474 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
30efa5a3 1475 EITR_INTS_PER_SEC_TO_REG(adapter->eitr_param));
9a799d71
AK		 1476
1477 ixgbe_set_ivar(adapter, IXGBE_IVAR_RX_QUEUE(0), 0);
021230d4
AV		 1478 ixgbe_set_ivar(adapter, IXGBE_IVAR_TX_QUEUE(0), 0);
1479
1480 map_vector_to_rxq(adapter, 0, 0);
1481 map_vector_to_txq(adapter, 0, 0);
1482
1483 DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 1484}
1485
1486/**
3a581073 1487 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 1488 * @adapter: board private structure
1489 *
1490 * Configure the Tx unit of the MAC after a reset.
1491 **/
1492static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1493{
12207e49 1494 u64 tdba;
9a799d71 1495 struct ixgbe_hw *hw = &adapter->hw;
021230d4 1496 u32 i, j, tdlen, txctrl;
9a799d71
AK		 1497
1498 /* Setup the HW Tx Head and Tail descriptor pointers */
1499 for (i = 0; i < adapter->num_tx_queues; i++) {
e01c31a5
JB		 1500 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1501 j = ring->reg_idx;
1502 tdba = ring->dma;
1503 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
021230d4 1504 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
e01c31a5 1505 (tdba & DMA_32BIT_MASK));
021230d4
AV		 1506 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1507 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1508 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1509 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1510 adapter->tx_ring[i].head = IXGBE_TDH(j);
1511 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1512 /* Disable Tx Head Writeback RO bit, since this hoses
1513 * bookkeeping if things aren't delivered in order.
1514 */
e01c31a5 1515 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
021230d4 1516 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
e01c31a5 1517 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
9a799d71 1518 }
9a799d71
AK		 1519}
1520
cc41ac7c
JB		 1521#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
1522
1523static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, int index)
1524{
1525 struct ixgbe_ring *rx_ring;
1526 u32 srrctl;
1527 int queue0;
3be1adfb
AD		 1528 unsigned long mask;
1529
1530 /* program one srrctl register per VMDq index */
1531 if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) {
1532 long shift, len;
1533 mask = (unsigned long) adapter->ring_feature[RING_F_RSS].mask;
1534 len = sizeof(adapter->ring_feature[RING_F_VMDQ].mask) * 8;
1535 shift = find_first_bit(&mask, len);
1536 queue0 = index & mask;
1537 index = (index & mask) >> shift;
1538 /* program one srrctl per RSS queue since RDRXCTL.MVMEN is enabled */
cc41ac7c 1539 } else {
3be1adfb
AD		 1540 mask = (unsigned long) adapter->ring_feature[RING_F_RSS].mask;
1541 queue0 = index & mask;
1542 index = index & mask;
cc41ac7c 1543 }
3be1adfb 1544
cc41ac7c
JB		 1545 rx_ring = &adapter->rx_ring[queue0];
1546
1547 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
1548
1549 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1550 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1551
1552 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
32344a39
JB		 1553 u16 bufsz = IXGBE_RXBUFFER_2048;
1554 /* grow the amount we can receive on large page machines */
1555 if (bufsz < (PAGE_SIZE / 2))
1556 bufsz = (PAGE_SIZE / 2);
1557 /* cap the bufsz at our largest descriptor size */
1558 bufsz = min((u16)IXGBE_MAX_RXBUFFER, bufsz);
1559
1560 srrctl |= bufsz >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c
JB		 1561 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1562 srrctl |= ((IXGBE_RX_HDR_SIZE <<
b4617240
PW		 1563 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1564 IXGBE_SRRCTL_BSIZEHDR_MASK);
cc41ac7c
JB		 1565 } else {
1566 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
1567
1568 if (rx_ring->rx_buf_len == MAXIMUM_ETHERNET_VLAN_SIZE)
1569 srrctl |= IXGBE_RXBUFFER_2048 >>
1570 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1571 else
1572 srrctl |= rx_ring->rx_buf_len >>
1573 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1574 }
1575 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
1576}
9a799d71 1577
9a799d71 1578/**
3a581073 1579 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
9a799d71
AK		 1580 * @adapter: board private structure
1581 *
1582 * Configure the Rx unit of the MAC after a reset.
1583 **/
1584static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
1585{
1586 u64 rdba;
1587 struct ixgbe_hw *hw = &adapter->hw;
1588 struct net_device *netdev = adapter->netdev;
1589 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 1590 int i, j;
9a799d71 1591 u32 rdlen, rxctrl, rxcsum;
7c6e0a43
JB		 1592 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
1593 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
1594 0x6A3E67EA, 0x14364D17, 0x3BED200D};
9a799d71 1595 u32 fctrl, hlreg0;
cc41ac7c
JB		 1596 u32 reta = 0, mrqc;
1597 u32 rdrxctl;
7c6e0a43 1598 int rx_buf_len;
9a799d71
AK		 1599
1600 /* Decide whether to use packet split mode or not */
762f4c57 1601 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
9a799d71
AK		 1602
1603 /* Set the RX buffer length according to the mode */
1604 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 1605 rx_buf_len = IXGBE_RX_HDR_SIZE;
9a799d71
AK		 1606 } else {
1607 if (netdev->mtu <= ETH_DATA_LEN)
7c6e0a43 1608 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 1609 else
7c6e0a43 1610 rx_buf_len = ALIGN(max_frame, 1024);
9a799d71
AK		 1611 }
1612
1613 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1614 fctrl |= IXGBE_FCTRL_BAM;
021230d4 1615 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
9a799d71
AK		 1616 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
1617
1618 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1619 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1620 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
1621 else
1622 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
1623 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1624
9a799d71
AK		 1625 rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
1626 /* disable receives while setting up the descriptors */
1627 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1628 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
1629
1630 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1631 * the Base and Length of the Rx Descriptor Ring */
1632 for (i = 0; i < adapter->num_rx_queues; i++) {
1633 rdba = adapter->rx_ring[i].dma;
7c6e0a43
JB		 1634 j = adapter->rx_ring[i].reg_idx;
1635 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_32BIT_MASK));
1636 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
1637 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
1638 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
1639 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
1640 adapter->rx_ring[i].head = IXGBE_RDH(j);
1641 adapter->rx_ring[i].tail = IXGBE_RDT(j);
1642 adapter->rx_ring[i].rx_buf_len = rx_buf_len;
cc41ac7c
JB		 1643
1644 ixgbe_configure_srrctl(adapter, j);
9a799d71
AK		 1645 }
1646
cc41ac7c
JB		 1647 /*
1648 * For VMDq support of different descriptor types or
1649 * buffer sizes through the use of multiple SRRCTL
1650 * registers, RDRXCTL.MVMEN must be set to 1
1651 *
1652 * also, the manual doesn't mention it clearly but DCA hints
1653 * will only use queue 0's tags unless this bit is set. Side
1654 * effects of setting this bit are only that SRRCTL must be
1655 * fully programmed [0..15]
1656 */
2f90b865
AD		 1657 if (adapter->flags &
1658 (IXGBE_FLAG_RSS_ENABLED | IXGBE_FLAG_VMDQ_ENABLED)) {
1659 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1660 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
1661 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
1662 }
177db6ff 1663
021230d4 1664 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
9a799d71 1665 /* Fill out redirection table */
021230d4
AV		 1666 for (i = 0, j = 0; i < 128; i++, j++) {
1667 if (j == adapter->ring_feature[RING_F_RSS].indices)
1668 j = 0;
1669 /* reta = 4-byte sliding window of
1670 * 0x00..(indices-1)(indices-1)00..etc. */
1671 reta = (reta << 8) | (j * 0x11);
1672 if ((i & 3) == 3)
1673 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
9a799d71
AK		 1674 }
1675
1676 /* Fill out hash function seeds */
1677 for (i = 0; i < 10; i++)
7c6e0a43 1678 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
9a799d71
AK		 1679
1680 mrqc = IXGBE_MRQC_RSSEN
1681 /* Perform hash on these packet types */
7c6e0a43
JB		 1682 | IXGBE_MRQC_RSS_FIELD_IPV4
1683 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
1684 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
1685 | IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP
1686 | IXGBE_MRQC_RSS_FIELD_IPV6_EX
1687 | IXGBE_MRQC_RSS_FIELD_IPV6
1688 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
1689 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP
1690 | IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
9a799d71 1691 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
021230d4 1692 }
9a799d71 1693
021230d4
AV		 1694 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
1695
1696 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
1697 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
1698 /* Disable indicating checksum in descriptor, enables
1699 * RSS hash */
9a799d71 1700 rxcsum |= IXGBE_RXCSUM_PCSD;
9a799d71 1701 }
021230d4
AV		 1702 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
1703 /* Enable IPv4 payload checksum for UDP fragments
1704 * if PCSD is not set */
1705 rxcsum |= IXGBE_RXCSUM_IPPCSE;
1706 }
1707
1708 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
9a799d71
AK		 1709}
1710
068c89b0
DS		 1711static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
1712{
1713 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1714 struct ixgbe_hw *hw = &adapter->hw;
1715
1716 /* add VID to filter table */
1717 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
1718}
1719
1720static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
1721{
1722 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1723 struct ixgbe_hw *hw = &adapter->hw;
1724
1725 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1726 ixgbe_irq_disable(adapter);
1727
1728 vlan_group_set_device(adapter->vlgrp, vid, NULL);
1729
1730 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1731 ixgbe_irq_enable(adapter);
1732
1733 /* remove VID from filter table */
1734 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
1735}
1736
9a799d71 1737static void ixgbe_vlan_rx_register(struct net_device *netdev,
b4617240 1738 struct vlan_group *grp)
9a799d71
AK		 1739{
1740 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1741 u32 ctrl;
1742
d4f80882
AV		 1743 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1744 ixgbe_irq_disable(adapter);
9a799d71
AK		 1745 adapter->vlgrp = grp;
1746
2f90b865
AD		 1747 /*
1748 * For a DCB driver, always enable VLAN tag stripping so we can
1749 * still receive traffic from a DCB-enabled host even if we're
1750 * not in DCB mode.
1751 */
1752 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
1753 ctrl |= IXGBE_VLNCTRL_VME;
1754 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
1755 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
068c89b0 1756 ixgbe_vlan_rx_add_vid(netdev, 0);
2f90b865 1757
9a799d71
AK		 1758 if (grp) {
1759 /* enable VLAN tag insert/strip */
1760 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
746b9f02 1761 ctrl |= IXGBE_VLNCTRL_VME;
9a799d71
AK		 1762 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
1763 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
1764 }
1765
d4f80882
AV		 1766 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1767 ixgbe_irq_enable(adapter);
9a799d71
AK		 1768}
1769
9a799d71
AK		 1770static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
1771{
1772 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
1773
1774 if (adapter->vlgrp) {
1775 u16 vid;
1776 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
1777 if (!vlan_group_get_device(adapter->vlgrp, vid))
1778 continue;
1779 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
1780 }
1781 }
1782}
1783
2c5645cf
CL		 1784static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
1785{
1786 struct dev_mc_list *mc_ptr;
1787 u8 *addr = *mc_addr_ptr;
1788 *vmdq = 0;
1789
1790 mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
1791 if (mc_ptr->next)
1792 *mc_addr_ptr = mc_ptr->next->dmi_addr;
1793 else
1794 *mc_addr_ptr = NULL;
1795
1796 return addr;
1797}
1798
9a799d71 1799/**
2c5645cf 1800 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 1801 * @netdev: network interface device structure
1802 *
2c5645cf
CL		 1803 * The set_rx_method entry point is called whenever the unicast/multicast
1804 * address list or the network interface flags are updated. This routine is
1805 * responsible for configuring the hardware for proper unicast, multicast and
1806 * promiscuous mode.
9a799d71 1807 **/
2c5645cf 1808static void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 1809{
1810 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1811 struct ixgbe_hw *hw = &adapter->hw;
3d01625a 1812 u32 fctrl, vlnctrl;
2c5645cf
CL		 1813 u8 *addr_list = NULL;
1814 int addr_count = 0;
9a799d71
AK		 1815
1816 /* Check for Promiscuous and All Multicast modes */
1817
1818 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3d01625a 1819 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
9a799d71
AK		 1820
1821 if (netdev->flags & IFF_PROMISC) {
2c5645cf 1822 hw->addr_ctrl.user_set_promisc = 1;
9a799d71 1823 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3d01625a 1824 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
9a799d71 1825 } else {
746b9f02
PM		 1826 if (netdev->flags & IFF_ALLMULTI) {
1827 fctrl |= IXGBE_FCTRL_MPE;
1828 fctrl &= ~IXGBE_FCTRL_UPE;
1829 } else {
1830 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
1831 }
3d01625a 1832 vlnctrl |= IXGBE_VLNCTRL_VFE;
2c5645cf 1833 hw->addr_ctrl.user_set_promisc = 0;
9a799d71
AK		 1834 }
1835
1836 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3d01625a 1837 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
9a799d71 1838
2c5645cf
CL		 1839 /* reprogram secondary unicast list */
1840 addr_count = netdev->uc_count;
1841 if (addr_count)
1842 addr_list = netdev->uc_list->dmi_addr;
c44ade9e
JB		 1843 hw->mac.ops.update_uc_addr_list(hw, addr_list, addr_count,
1844 ixgbe_addr_list_itr);
9a799d71 1845
2c5645cf
CL		 1846 /* reprogram multicast list */
1847 addr_count = netdev->mc_count;
1848 if (addr_count)
1849 addr_list = netdev->mc_list->dmi_addr;
c44ade9e
JB		 1850 hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
1851 ixgbe_addr_list_itr);
9a799d71
AK		 1852}
1853
021230d4
AV		 1854static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
1855{
1856 int q_idx;
1857 struct ixgbe_q_vector *q_vector;
1858 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1859
1860 /* legacy and MSI only use one vector */
1861 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1862 q_vectors = 1;
1863
1864 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 1865 struct napi_struct *napi;
021230d4
AV		 1866 q_vector = &adapter->q_vector[q_idx];
1867 if (!q_vector->rxr_count)
1868 continue;
f0848276
JB		 1869 napi = &q_vector->napi;
1870 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) &&
1871 (q_vector->rxr_count > 1))
1872 napi->poll = &ixgbe_clean_rxonly_many;
1873
1874 napi_enable(napi);
021230d4
AV		 1875 }
1876}
1877
1878static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
1879{
1880 int q_idx;
1881 struct ixgbe_q_vector *q_vector;
1882 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1883
1884 /* legacy and MSI only use one vector */
1885 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1886 q_vectors = 1;
1887
1888 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
1889 q_vector = &adapter->q_vector[q_idx];
1890 if (!q_vector->rxr_count)
1891 continue;
1892 napi_disable(&q_vector->napi);
1893 }
1894}
1895
7a6b6f51 1896#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 1897/*
1898 * ixgbe_configure_dcb - Configure DCB hardware
1899 * @adapter: ixgbe adapter struct
1900 *
1901 * This is called by the driver on open to configure the DCB hardware.
1902 * This is also called by the gennetlink interface when reconfiguring
1903 * the DCB state.
1904 */
1905static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
1906{
1907 struct ixgbe_hw *hw = &adapter->hw;
1908 u32 txdctl, vlnctrl;
1909 int i, j;
1910
1911 ixgbe_dcb_check_config(&adapter->dcb_cfg);
1912 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
1913 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
1914
1915 /* reconfigure the hardware */
1916 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
1917
1918 for (i = 0; i < adapter->num_tx_queues; i++) {
1919 j = adapter->tx_ring[i].reg_idx;
1920 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
1921 /* PThresh workaround for Tx hang with DFP enabled. */
1922 txdctl |= 32;
1923 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
1924 }
1925 /* Enable VLAN tag insert/strip */
1926 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1927 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
1928 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1929 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1930 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
1931}
1932
1933#endif
9a799d71
AK		 1934static void ixgbe_configure(struct ixgbe_adapter *adapter)
1935{
1936 struct net_device *netdev = adapter->netdev;
1937 int i;
1938
2c5645cf 1939 ixgbe_set_rx_mode(netdev);
9a799d71
AK		 1940
1941 ixgbe_restore_vlan(adapter);
7a6b6f51 1942#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 1943 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
1944 netif_set_gso_max_size(netdev, 32768);
1945 ixgbe_configure_dcb(adapter);
1946 } else {
1947 netif_set_gso_max_size(netdev, 65536);
1948 }
1949#else
1950 netif_set_gso_max_size(netdev, 65536);
1951#endif
9a799d71
AK		 1952
1953 ixgbe_configure_tx(adapter);
1954 ixgbe_configure_rx(adapter);
1955 for (i = 0; i < adapter->num_rx_queues; i++)
1956 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
b4617240 1957 (adapter->rx_ring[i].count - 1));
9a799d71
AK		 1958}
1959
0ecc061d
PWJ		 1960/**
1961 * ixgbe_link_config - set up initial link with default speed and duplex
1962 * @hw: pointer to private hardware struct
1963 *
1964 * Returns 0 on success, negative on failure
1965 **/
1966static int ixgbe_link_config(struct ixgbe_hw *hw)
1967{
1968 u32 autoneg;
1969 bool link_up = false;
1970 u32 ret = IXGBE_ERR_LINK_SETUP;
1971
1972 if (hw->mac.ops.check_link)
1973 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1974
1975 if (ret)
1976 goto link_cfg_out;
1977
1978 if (hw->mac.ops.get_link_capabilities)
1979 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
1980 &hw->mac.autoneg);
1981 if (ret)
1982 goto link_cfg_out;
1983
1984 if (hw->mac.ops.setup_link_speed)
1985 ret = hw->mac.ops.setup_link_speed(hw, autoneg, true, link_up);
1986
1987link_cfg_out:
1988 return ret;
1989}
1990
9a799d71
AK		 1991static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
1992{
1993 struct net_device *netdev = adapter->netdev;
9a799d71 1994 struct ixgbe_hw *hw = &adapter->hw;
021230d4 1995 int i, j = 0;
0ecc061d 1996 int err;
9a799d71 1997 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4
AV		 1998 u32 txdctl, rxdctl, mhadd;
1999 u32 gpie;
9a799d71 2000
5eba3699
AV		 2001 ixgbe_get_hw_control(adapter);
2002
021230d4
AV		 2003 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2004 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
9a799d71
AK		 2005 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2006 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
b4617240 2007 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
9a799d71
AK		 2008 } else {
2009 /* MSI only */
021230d4 2010 gpie = 0;
9a799d71 2011 }
021230d4
AV		 2012 /* XXX: to interrupt immediately for EICS writes, enable this */
2013 /* gpie |= IXGBE_GPIE_EIMEN; */
2014 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
9a799d71
AK		 2015 }
2016
021230d4
AV		 2017 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2018 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2019 * specifically only auto mask tx and rx interrupts */
2020 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2021 }
9a799d71 2022
0befdb3e
JB		 2023 /* Enable fan failure interrupt if media type is copper */
2024 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2025 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2026 gpie |= IXGBE_SDP1_GPIEN;
2027 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2028 }
2029
021230d4 2030 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
9a799d71
AK		 2031 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2032 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2033 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2034
2035 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2036 }
2037
2038 for (i = 0; i < adapter->num_tx_queues; i++) {
021230d4
AV		 2039 j = adapter->tx_ring[i].reg_idx;
2040 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
e01c31a5
JB		 2041 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2042 txdctl |= (8 << 16);
9a799d71 2043 txdctl |= IXGBE_TXDCTL_ENABLE;
021230d4 2044 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
9a799d71
AK		 2045 }
2046
2047 for (i = 0; i < adapter->num_rx_queues; i++) {
021230d4
AV		 2048 j = adapter->rx_ring[i].reg_idx;
2049 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2050 /* enable PTHRESH=32 descriptors (half the internal cache)
2051 * and HTHRESH=0 descriptors (to minimize latency on fetch),
2052 * this also removes a pesky rx_no_buffer_count increment */
2053 rxdctl |= 0x0020;
9a799d71 2054 rxdctl |= IXGBE_RXDCTL_ENABLE;
021230d4 2055 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
9a799d71
AK		 2056 }
2057 /* enable all receives */
2058 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2059 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2060 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxdctl);
2061
2062 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2063 ixgbe_configure_msix(adapter);
2064 else
2065 ixgbe_configure_msi_and_legacy(adapter);
2066
7adf1525
PWJ		 2067 ixgbe_napi_add_all(adapter);
2068
9a799d71 2069 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 2070 ixgbe_napi_enable_all(adapter);
2071
2072 /* clear any pending interrupts, may auto mask */
2073 IXGBE_READ_REG(hw, IXGBE_EICR);
2074
9a799d71
AK		 2075 ixgbe_irq_enable(adapter);
2076
0ecc061d
PWJ		 2077 err = ixgbe_link_config(hw);
2078 if (err)
2079 dev_err(&adapter->pdev->dev, "link_config FAILED %d\n", err);
2080
1da100bb
PWJ		 2081 /* enable transmits */
2082 netif_tx_start_all_queues(netdev);
2083
9a799d71
AK		 2084 /* bring the link up in the watchdog, this could race with our first
2085 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 2086 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2087 adapter->link_check_timeout = jiffies;
9a799d71
AK		 2088 mod_timer(&adapter->watchdog_timer, jiffies);
2089 return 0;
2090}
2091
d4f80882
AV		 2092void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2093{
2094 WARN_ON(in_interrupt());
2095 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2096 msleep(1);
2097 ixgbe_down(adapter);
2098 ixgbe_up(adapter);
2099 clear_bit(__IXGBE_RESETTING, &adapter->state);
2100}
2101
9a799d71
AK		 2102int ixgbe_up(struct ixgbe_adapter *adapter)
2103{
2104 /* hardware has been reset, we need to reload some things */
2105 ixgbe_configure(adapter);
2106
2107 return ixgbe_up_complete(adapter);
2108}
2109
2110void ixgbe_reset(struct ixgbe_adapter *adapter)
2111{
c44ade9e
JB		 2112 struct ixgbe_hw *hw = &adapter->hw;
2113 if (hw->mac.ops.init_hw(hw))
2114 dev_err(&adapter->pdev->dev, "Hardware Error\n");
9a799d71
AK		 2115
2116 /* reprogram the RAR[0] in case user changed it. */
c44ade9e 2117 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71
AK		 2118
2119}
2120
9a799d71
AK		 2121/**
2122 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2123 * @adapter: board private structure
2124 * @rx_ring: ring to free buffers from
2125 **/
2126static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
b4617240 2127 struct ixgbe_ring *rx_ring)
9a799d71
AK		 2128{
2129 struct pci_dev *pdev = adapter->pdev;
2130 unsigned long size;
2131 unsigned int i;
2132
2133 /* Free all the Rx ring sk_buffs */
2134
2135 for (i = 0; i < rx_ring->count; i++) {
2136 struct ixgbe_rx_buffer *rx_buffer_info;
2137
2138 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2139 if (rx_buffer_info->dma) {
2140 pci_unmap_single(pdev, rx_buffer_info->dma,
b4617240
PW		 2141 rx_ring->rx_buf_len,
2142 PCI_DMA_FROMDEVICE);
9a799d71
AK		 2143 rx_buffer_info->dma = 0;
2144 }
2145 if (rx_buffer_info->skb) {
2146 dev_kfree_skb(rx_buffer_info->skb);
2147 rx_buffer_info->skb = NULL;
2148 }
2149 if (!rx_buffer_info->page)
2150 continue;
762f4c57
JB		 2151 pci_unmap_page(pdev, rx_buffer_info->page_dma, PAGE_SIZE / 2,
2152 PCI_DMA_FROMDEVICE);
9a799d71 2153 rx_buffer_info->page_dma = 0;
9a799d71
AK		 2154 put_page(rx_buffer_info->page);
2155 rx_buffer_info->page = NULL;
762f4c57 2156 rx_buffer_info->page_offset = 0;
9a799d71
AK		 2157 }
2158
2159 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2160 memset(rx_ring->rx_buffer_info, 0, size);
2161
2162 /* Zero out the descriptor ring */
2163 memset(rx_ring->desc, 0, rx_ring->size);
2164
2165 rx_ring->next_to_clean = 0;
2166 rx_ring->next_to_use = 0;
2167
2168 writel(0, adapter->hw.hw_addr + rx_ring->head);
2169 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2170}
2171
2172/**
2173 * ixgbe_clean_tx_ring - Free Tx Buffers
2174 * @adapter: board private structure
2175 * @tx_ring: ring to be cleaned
2176 **/
2177static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
b4617240 2178 struct ixgbe_ring *tx_ring)
9a799d71
AK		 2179{
2180 struct ixgbe_tx_buffer *tx_buffer_info;
2181 unsigned long size;
2182 unsigned int i;
2183
2184 /* Free all the Tx ring sk_buffs */
2185
2186 for (i = 0; i < tx_ring->count; i++) {
2187 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2188 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2189 }
2190
2191 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2192 memset(tx_ring->tx_buffer_info, 0, size);
2193
2194 /* Zero out the descriptor ring */
2195 memset(tx_ring->desc, 0, tx_ring->size);
2196
2197 tx_ring->next_to_use = 0;
2198 tx_ring->next_to_clean = 0;
2199
2200 writel(0, adapter->hw.hw_addr + tx_ring->head);
2201 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2202}
2203
2204/**
021230d4 2205 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 2206 * @adapter: board private structure
2207 **/
021230d4 2208static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 2209{
2210 int i;
2211
021230d4
AV		 2212 for (i = 0; i < adapter->num_rx_queues; i++)
2213 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
9a799d71
AK		 2214}
2215
2216/**
021230d4 2217 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 2218 * @adapter: board private structure
2219 **/
021230d4 2220static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 2221{
2222 int i;
2223
021230d4
AV		 2224 for (i = 0; i < adapter->num_tx_queues; i++)
2225 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
9a799d71
AK		 2226}
2227
2228void ixgbe_down(struct ixgbe_adapter *adapter)
2229{
2230 struct net_device *netdev = adapter->netdev;
7f821875 2231 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 2232 u32 rxctrl;
7f821875
JB		 2233 u32 txdctl;
2234 int i, j;
9a799d71
AK		 2235
2236 /* signal that we are down to the interrupt handler */
2237 set_bit(__IXGBE_DOWN, &adapter->state);
2238
2239 /* disable receives */
7f821875
JB		 2240 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2241 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71
AK		 2242
2243 netif_tx_disable(netdev);
2244
7f821875 2245 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 2246 msleep(10);
2247
7f821875
JB		 2248 netif_tx_stop_all_queues(netdev);
2249
9a799d71
AK		 2250 ixgbe_irq_disable(adapter);
2251
021230d4 2252 ixgbe_napi_disable_all(adapter);
7f821875 2253
9a799d71 2254 del_timer_sync(&adapter->watchdog_timer);
cf8280ee 2255 cancel_work_sync(&adapter->watchdog_task);
9a799d71 2256
7f821875
JB		 2257 /* disable transmits in the hardware now that interrupts are off */
2258 for (i = 0; i < adapter->num_tx_queues; i++) {
2259 j = adapter->tx_ring[i].reg_idx;
2260 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2261 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
2262 (txdctl & ~IXGBE_TXDCTL_ENABLE));
2263 }
2264
9a799d71 2265 netif_carrier_off(netdev);
9a799d71 2266
5dd2d332 2267#ifdef CONFIG_IXGBE_DCA
96b0e0f6
JB		 2268 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2269 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
2270 dca_remove_requester(&adapter->pdev->dev);
2271 }
2272
2273#endif
6f4a0e45
PL		 2274 if (!pci_channel_offline(adapter->pdev))
2275 ixgbe_reset(adapter);
9a799d71
AK		 2276 ixgbe_clean_all_tx_rings(adapter);
2277 ixgbe_clean_all_rx_rings(adapter);
2278
5dd2d332 2279#ifdef CONFIG_IXGBE_DCA
96b0e0f6
JB		 2280 /* since we reset the hardware DCA settings were cleared */
2281 if (dca_add_requester(&adapter->pdev->dev) == 0) {
2282 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
2283 /* always use CB2 mode, difference is masked
2284 * in the CB driver */
b4617240 2285 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
96b0e0f6
JB		 2286 ixgbe_setup_dca(adapter);
2287 }
2288#endif
9a799d71
AK		 2289}
2290
9a799d71 2291/**
021230d4
AV		 2292 * ixgbe_poll - NAPI Rx polling callback
2293 * @napi: structure for representing this polling device
2294 * @budget: how many packets driver is allowed to clean
2295 *
2296 * This function is used for legacy and MSI, NAPI mode
9a799d71 2297 **/
021230d4 2298static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 2299{
021230d4 2300 struct ixgbe_q_vector *q_vector = container_of(napi,
b4617240 2301 struct ixgbe_q_vector, napi);
021230d4 2302 struct ixgbe_adapter *adapter = q_vector->adapter;
74ce8dd2 2303 int tx_cleaned, work_done = 0;
9a799d71 2304
5dd2d332 2305#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 2306 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2307 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
2308 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
2309 }
2310#endif
2311
d2c7ddd6 2312 tx_cleaned = ixgbe_clean_tx_irq(adapter, adapter->tx_ring);
78b6f4ce 2313 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
9a799d71 2314
d2c7ddd6
DM		 2315 if (tx_cleaned)
2316 work_done = budget;
2317
53e52c72
DM		 2318 /* If budget not fully consumed, exit the polling mode */
2319 if (work_done < budget) {
288379f0 2320 napi_complete(napi);
30efa5a3 2321 if (adapter->itr_setting & 3)
f494e8fa 2322 ixgbe_set_itr(adapter);
d4f80882
AV		 2323 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2324 ixgbe_irq_enable(adapter);
9a799d71 2325 }
9a799d71
AK		 2326 return work_done;
2327}
2328
2329/**
2330 * ixgbe_tx_timeout - Respond to a Tx Hang
2331 * @netdev: network interface device structure
2332 **/
2333static void ixgbe_tx_timeout(struct net_device *netdev)
2334{
2335 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2336
2337 /* Do the reset outside of interrupt context */
2338 schedule_work(&adapter->reset_task);
2339}
2340
2341static void ixgbe_reset_task(struct work_struct *work)
2342{
2343 struct ixgbe_adapter *adapter;
2344 adapter = container_of(work, struct ixgbe_adapter, reset_task);
2345
2f90b865
AD		 2346 /* If we're already down or resetting, just bail */
2347 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
2348 test_bit(__IXGBE_RESETTING, &adapter->state))
2349 return;
2350
9a799d71
AK		 2351 adapter->tx_timeout_count++;
2352
d4f80882 2353 ixgbe_reinit_locked(adapter);
9a799d71
AK		 2354}
2355
bc97114d
PWJ		 2356#ifdef CONFIG_IXGBE_DCB
2357static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
b9804972 2358{
bc97114d 2359 bool ret = false;
b9804972 2360
bc97114d
PWJ		 2361 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2362 adapter->ring_feature[RING_F_DCB].mask = 0x7 << 3;
2363 adapter->num_rx_queues =
2364 adapter->ring_feature[RING_F_DCB].indices;
2365 adapter->num_tx_queues =
2366 adapter->ring_feature[RING_F_DCB].indices;
2367 ret = true;
2368 } else {
bc97114d
PWJ		 2369 ret = false;
2370 }
2f90b865 2371
bc97114d
PWJ		 2372 return ret;
2373}
2374#endif
2375
2376static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
2377{
2378 bool ret = false;
2379
2380 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2381 adapter->ring_feature[RING_F_RSS].mask = 0xF;
2382 adapter->num_rx_queues =
2383 adapter->ring_feature[RING_F_RSS].indices;
2384 adapter->num_tx_queues =
2385 adapter->ring_feature[RING_F_RSS].indices;
2386 ret = true;
2387 } else {
bc97114d 2388 ret = false;
b9804972
JB		 2389 }
2390
bc97114d
PWJ		 2391 return ret;
2392}
2393
2394static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
2395{
2396 /* Start with base case */
2397 adapter->num_rx_queues = 1;
2398 adapter->num_tx_queues = 1;
2399
2400#ifdef CONFIG_IXGBE_DCB
2401 if (ixgbe_set_dcb_queues(adapter))
2402 return;
2403
2404#endif
2405 if (ixgbe_set_rss_queues(adapter))
2406 return;
b9804972
JB		 2407}
2408
021230d4 2409static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
b4617240 2410 int vectors)
021230d4
AV		 2411{
2412 int err, vector_threshold;
2413
2414 /* We'll want at least 3 (vector_threshold):
2415 * 1) TxQ[0] Cleanup
2416 * 2) RxQ[0] Cleanup
2417 * 3) Other (Link Status Change, etc.)
2418 * 4) TCP Timer (optional)
2419 */
2420 vector_threshold = MIN_MSIX_COUNT;
2421
2422 /* The more we get, the more we will assign to Tx/Rx Cleanup
2423 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
2424 * Right now, we simply care about how many we'll get; we'll
2425 * set them up later while requesting irq's.
2426 */
2427 while (vectors >= vector_threshold) {
2428 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
b4617240 2429 vectors);
021230d4
AV		 2430 if (!err) /* Success in acquiring all requested vectors. */
2431 break;
2432 else if (err < 0)
2433 vectors = 0; /* Nasty failure, quit now */
2434 else /* err == number of vectors we should try again with */
2435 vectors = err;
2436 }
2437
2438 if (vectors < vector_threshold) {
2439 /* Can't allocate enough MSI-X interrupts? Oh well.
2440 * This just means we'll go with either a single MSI
2441 * vector or fall back to legacy interrupts.
2442 */
2443 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
2444 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2445 kfree(adapter->msix_entries);
2446 adapter->msix_entries = NULL;
2f90b865 2447 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
021230d4 2448 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
b9804972 2449 ixgbe_set_num_queues(adapter);
021230d4
AV		 2450 } else {
2451 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 2452 /*
2453 * Adjust for only the vectors we'll use, which is minimum
2454 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
2455 * vectors we were allocated.
2456 */
2457 adapter->num_msix_vectors = min(vectors,
2458 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 2459 }
2460}
2461
021230d4 2462/**
bc97114d 2463 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 2464 * @adapter: board private structure to initialize
2465 *
bc97114d
PWJ		 2466 * Cache the descriptor ring offsets for RSS to the assigned rings.
2467 *
021230d4 2468 **/
bc97114d 2469static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 2470{
bc97114d
PWJ		 2471 int i;
2472 bool ret = false;
2473
2474 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2475 for (i = 0; i < adapter->num_rx_queues; i++)
2476 adapter->rx_ring[i].reg_idx = i;
2477 for (i = 0; i < adapter->num_tx_queues; i++)
2478 adapter->tx_ring[i].reg_idx = i;
2479 ret = true;
2480 } else {
2481 ret = false;
2482 }
2483
2484 return ret;
2485}
2486
2487#ifdef CONFIG_IXGBE_DCB
2488/**
2489 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
2490 * @adapter: board private structure to initialize
2491 *
2492 * Cache the descriptor ring offsets for DCB to the assigned rings.
2493 *
2494 **/
2495static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
2496{
2497 int i;
2498 bool ret = false;
2499 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
2500
2501 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2502 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2f90b865
AD		 2503 /* the number of queues is assumed to be symmetric */
2504 for (i = 0; i < dcb_i; i++) {
2505 adapter->rx_ring[i].reg_idx = i << 3;
2506 adapter->tx_ring[i].reg_idx = i << 2;
2507 }
bc97114d
PWJ		 2508 ret = true;
2509 } else {
2510 ret = false;
021230d4 2511 }
bc97114d
PWJ		 2512 } else {
2513 ret = false;
021230d4 2514 }
bc97114d
PWJ		 2515
2516 return ret;
2517}
2518#endif
2519
2520/**
2521 * ixgbe_cache_ring_register - Descriptor ring to register mapping
2522 * @adapter: board private structure to initialize
2523 *
2524 * Once we know the feature-set enabled for the device, we'll cache
2525 * the register offset the descriptor ring is assigned to.
2526 *
2527 * Note, the order the various feature calls is important. It must start with
2528 * the "most" features enabled at the same time, then trickle down to the
2529 * least amount of features turned on at once.
2530 **/
2531static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
2532{
2533 /* start with default case */
2534 adapter->rx_ring[0].reg_idx = 0;
2535 adapter->tx_ring[0].reg_idx = 0;
2536
2537#ifdef CONFIG_IXGBE_DCB
2538 if (ixgbe_cache_ring_dcb(adapter))
2539 return;
2540
2541#endif
2542 if (ixgbe_cache_ring_rss(adapter))
2543 return;
021230d4
AV		 2544}
2545
9a799d71
AK		 2546/**
2547 * ixgbe_alloc_queues - Allocate memory for all rings
2548 * @adapter: board private structure to initialize
2549 *
2550 * We allocate one ring per queue at run-time since we don't know the
a4d2f34b 2551 * number of queues at compile-time.
9a799d71 2552 **/
2f90b865 2553static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71
AK		 2554{
2555 int i;
2556
2557 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
b4617240 2558 sizeof(struct ixgbe_ring), GFP_KERNEL);
9a799d71 2559 if (!adapter->tx_ring)
021230d4 2560 goto err_tx_ring_allocation;
9a799d71
AK		 2561
2562 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
b4617240 2563 sizeof(struct ixgbe_ring), GFP_KERNEL);
021230d4
AV		 2564 if (!adapter->rx_ring)
2565 goto err_rx_ring_allocation;
9a799d71 2566
021230d4 2567 for (i = 0; i < adapter->num_tx_queues; i++) {
b9804972 2568 adapter->tx_ring[i].count = adapter->tx_ring_count;
021230d4
AV		 2569 adapter->tx_ring[i].queue_index = i;
2570 }
b9804972 2571
9a799d71 2572 for (i = 0; i < adapter->num_rx_queues; i++) {
b9804972 2573 adapter->rx_ring[i].count = adapter->rx_ring_count;
021230d4
AV		 2574 adapter->rx_ring[i].queue_index = i;
2575 }
2576
2577 ixgbe_cache_ring_register(adapter);
2578
2579 return 0;
2580
2581err_rx_ring_allocation:
2582 kfree(adapter->tx_ring);
2583err_tx_ring_allocation:
2584 return -ENOMEM;
2585}
2586
2587/**
2588 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
2589 * @adapter: board private structure to initialize
2590 *
2591 * Attempt to configure the interrupts using the best available
2592 * capabilities of the hardware and the kernel.
2593 **/
feea6a57 2594static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 2595{
2596 int err = 0;
2597 int vector, v_budget;
2598
2599 /*
2600 * It's easy to be greedy for MSI-X vectors, but it really
2601 * doesn't do us much good if we have a lot more vectors
2602 * than CPU's. So let's be conservative and only ask for
2603 * (roughly) twice the number of vectors as there are CPU's.
2604 */
2605 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
b4617240 2606 (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
021230d4
AV		 2607
2608 /*
2609 * At the same time, hardware can only support a maximum of
2610 * MAX_MSIX_COUNT vectors. With features such as RSS and VMDq,
2611 * we can easily reach upwards of 64 Rx descriptor queues and
2612 * 32 Tx queues. Thus, we cap it off in those rare cases where
2613 * the cpu count also exceeds our vector limit.
2614 */
2615 v_budget = min(v_budget, MAX_MSIX_COUNT);
2616
2617 /* A failure in MSI-X entry allocation isn't fatal, but it does
2618 * mean we disable MSI-X capabilities of the adapter. */
2619 adapter->msix_entries = kcalloc(v_budget,
b4617240 2620 sizeof(struct msix_entry), GFP_KERNEL);
021230d4 2621 if (!adapter->msix_entries) {
2f90b865 2622 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
021230d4
AV		 2623 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
2624 ixgbe_set_num_queues(adapter);
2625 kfree(adapter->tx_ring);
2626 kfree(adapter->rx_ring);
2627 err = ixgbe_alloc_queues(adapter);
2628 if (err) {
2629 DPRINTK(PROBE, ERR, "Unable to allocate memory "
b4617240 2630 "for queues\n");
021230d4
AV		 2631 goto out;
2632 }
2633
2634 goto try_msi;
2635 }
2636
2637 for (vector = 0; vector < v_budget; vector++)
2638 adapter->msix_entries[vector].entry = vector;
2639
2640 ixgbe_acquire_msix_vectors(adapter, v_budget);
2641
2642 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2643 goto out;
2644
2645try_msi:
2646 err = pci_enable_msi(adapter->pdev);
2647 if (!err) {
2648 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
2649 } else {
2650 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
b4617240 2651 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 2652 /* reset err */
2653 err = 0;
2654 }
2655
2656out:
30eba97a 2657 /* Notify the stack of the (possibly) reduced Tx Queue count. */
fd2ea0a7 2658 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
021230d4
AV		 2659
2660 return err;
2661}
2662
2f90b865 2663void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 2664{
2665 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2666 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2667 pci_disable_msix(adapter->pdev);
2668 kfree(adapter->msix_entries);
2669 adapter->msix_entries = NULL;
2670 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2671 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
2672 pci_disable_msi(adapter->pdev);
2673 }
2674 return;
2675}
2676
2677/**
2678 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
2679 * @adapter: board private structure to initialize
2680 *
2681 * We determine which interrupt scheme to use based on...
2682 * - Kernel support (MSI, MSI-X)
2683 * - which can be user-defined (via MODULE_PARAM)
2684 * - Hardware queue count (num_*_queues)
2685 * - defined by miscellaneous hardware support/features (RSS, etc.)
2686 **/
2f90b865 2687int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 2688{
2689 int err;
2690
2691 /* Number of supported queues */
2692 ixgbe_set_num_queues(adapter);
2693
2694 err = ixgbe_alloc_queues(adapter);
2695 if (err) {
2696 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
2697 goto err_alloc_queues;
2698 }
2699
2700 err = ixgbe_set_interrupt_capability(adapter);
2701 if (err) {
2702 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
2703 goto err_set_interrupt;
9a799d71
AK		 2704 }
2705
021230d4 2706 DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
b4617240
PW		 2707 "Tx Queue count = %u\n",
2708 (adapter->num_rx_queues > 1) ? "Enabled" :
2709 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 2710
2711 set_bit(__IXGBE_DOWN, &adapter->state);
2712
9a799d71 2713 return 0;
021230d4
AV		 2714
2715err_set_interrupt:
2716 kfree(adapter->tx_ring);
2717 kfree(adapter->rx_ring);
2718err_alloc_queues:
2719 return err;
9a799d71
AK		 2720}
2721
c4900be0
DS		 2722/**
2723 * ixgbe_sfp_timer - worker thread to find a missing module
2724 * @data: pointer to our adapter struct
2725 **/
2726static void ixgbe_sfp_timer(unsigned long data)
2727{
2728 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
2729
2730 /* Do the sfp_timer outside of interrupt context due to the
2731 * delays that sfp+ detection requires
2732 */
2733 schedule_work(&adapter->sfp_task);
2734}
2735
2736/**
2737 * ixgbe_sfp_task - worker thread to find a missing module
2738 * @work: pointer to work_struct containing our data
2739 **/
2740static void ixgbe_sfp_task(struct work_struct *work)
2741{
2742 struct ixgbe_adapter *adapter = container_of(work,
2743 struct ixgbe_adapter,
2744 sfp_task);
2745 struct ixgbe_hw *hw = &adapter->hw;
2746
2747 if ((hw->phy.type == ixgbe_phy_nl) &&
2748 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
2749 s32 ret = hw->phy.ops.identify_sfp(hw);
2750 if (ret)
2751 goto reschedule;
2752 ret = hw->phy.ops.reset(hw);
2753 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
2754 DPRINTK(PROBE, ERR, "failed to initialize because an "
2755 "unsupported SFP+ module type was detected.\n"
2756 "Reload the driver after installing a "
2757 "supported module.\n");
2758 unregister_netdev(adapter->netdev);
2759 } else {
2760 DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
2761 hw->phy.sfp_type);
2762 }
2763 /* don't need this routine any more */
2764 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
2765 }
2766 return;
2767reschedule:
2768 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
2769 mod_timer(&adapter->sfp_timer,
2770 round_jiffies(jiffies + (2 * HZ)));
2771}
2772
9a799d71
AK		 2773/**
2774 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
2775 * @adapter: board private structure to initialize
2776 *
2777 * ixgbe_sw_init initializes the Adapter private data structure.
2778 * Fields are initialized based on PCI device information and
2779 * OS network device settings (MTU size).
2780 **/
2781static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
2782{
2783 struct ixgbe_hw *hw = &adapter->hw;
2784 struct pci_dev *pdev = adapter->pdev;
021230d4 2785 unsigned int rss;
7a6b6f51 2786#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 2787 int j;
2788 struct tc_configuration *tc;
2789#endif
021230d4 2790
c44ade9e
JB		 2791 /* PCI config space info */
2792
2793 hw->vendor_id = pdev->vendor;
2794 hw->device_id = pdev->device;
2795 hw->revision_id = pdev->revision;
2796 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2797 hw->subsystem_device_id = pdev->subsystem_device;
2798
021230d4
AV		 2799 /* Set capability flags */
2800 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
2801 adapter->ring_feature[RING_F_RSS].indices = rss;
2802 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
2f90b865 2803 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
eb7f139c 2804 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
2f90b865 2805
7a6b6f51 2806#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 2807 /* Configure DCB traffic classes */
2808 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
2809 tc = &adapter->dcb_cfg.tc_config[j];
2810 tc->path[DCB_TX_CONFIG].bwg_id = 0;
2811 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
2812 tc->path[DCB_RX_CONFIG].bwg_id = 0;
2813 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
2814 tc->dcb_pfc = pfc_disabled;
2815 }
2816 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
2817 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
2818 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
2819 adapter->dcb_cfg.round_robin_enable = false;
2820 adapter->dcb_set_bitmap = 0x00;
2821 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
2822 adapter->ring_feature[RING_F_DCB].indices);
2823
2824#endif
0befdb3e
JB		 2825 if (hw->mac.ops.get_media_type &&
2826 (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper))
2827 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
9a799d71
AK		 2828
2829 /* default flow control settings */
0ecc061d 2830 hw->fc.requested_mode = ixgbe_fc_none;
2b9ade93
JB		 2831 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
2832 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
2833 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
2834 hw->fc.send_xon = true;
9a799d71 2835
30efa5a3
JB		 2836 /* enable itr by default in dynamic mode */
2837 adapter->itr_setting = 1;
2838 adapter->eitr_param = 20000;
2839
2840 /* set defaults for eitr in MegaBytes */
2841 adapter->eitr_low = 10;
2842 adapter->eitr_high = 20;
2843
2844 /* set default ring sizes */
2845 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
2846 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
2847
9a799d71 2848 /* initialize eeprom parameters */
c44ade9e 2849 if (ixgbe_init_eeprom_params_generic(hw)) {
9a799d71
AK		 2850 dev_err(&pdev->dev, "EEPROM initialization failed\n");
2851 return -EIO;
2852 }
2853
021230d4 2854 /* enable rx csum by default */
9a799d71
AK		 2855 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
2856
9a799d71
AK		 2857 set_bit(__IXGBE_DOWN, &adapter->state);
2858
2859 return 0;
2860}
2861
2862/**
2863 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
2864 * @adapter: board private structure
3a581073 2865 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 2866 *
2867 * Return 0 on success, negative on failure
2868 **/
2869int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
e01c31a5 2870 struct ixgbe_ring *tx_ring)
9a799d71
AK		 2871{
2872 struct pci_dev *pdev = adapter->pdev;
2873 int size;
2874
3a581073
JB		 2875 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2876 tx_ring->tx_buffer_info = vmalloc(size);
e01c31a5
JB		 2877 if (!tx_ring->tx_buffer_info)
2878 goto err;
3a581073 2879 memset(tx_ring->tx_buffer_info, 0, size);
9a799d71
AK		 2880
2881 /* round up to nearest 4K */
12207e49 2882 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 2883 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 2884
3a581073
JB		 2885 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
2886 &tx_ring->dma);
e01c31a5
JB		 2887 if (!tx_ring->desc)
2888 goto err;
9a799d71 2889
3a581073
JB		 2890 tx_ring->next_to_use = 0;
2891 tx_ring->next_to_clean = 0;
2892 tx_ring->work_limit = tx_ring->count;
9a799d71 2893 return 0;
e01c31a5
JB		 2894
2895err:
2896 vfree(tx_ring->tx_buffer_info);
2897 tx_ring->tx_buffer_info = NULL;
2898 DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
2899 "descriptor ring\n");
2900 return -ENOMEM;
9a799d71
AK		 2901}
2902
69888674
AD		 2903/**
2904 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
2905 * @adapter: board private structure
2906 *
2907 * If this function returns with an error, then it's possible one or
2908 * more of the rings is populated (while the rest are not). It is the
2909 * callers duty to clean those orphaned rings.
2910 *
2911 * Return 0 on success, negative on failure
2912 **/
2913static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
2914{
2915 int i, err = 0;
2916
2917 for (i = 0; i < adapter->num_tx_queues; i++) {
2918 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
2919 if (!err)
2920 continue;
2921 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
2922 break;
2923 }
2924
2925 return err;
2926}
2927
9a799d71
AK		 2928/**
2929 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
2930 * @adapter: board private structure
3a581073 2931 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 2932 *
2933 * Returns 0 on success, negative on failure
2934 **/
2935int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
b4617240 2936 struct ixgbe_ring *rx_ring)
9a799d71
AK		 2937{
2938 struct pci_dev *pdev = adapter->pdev;
021230d4 2939 int size;
9a799d71 2940
3a581073
JB		 2941 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2942 rx_ring->rx_buffer_info = vmalloc(size);
2943 if (!rx_ring->rx_buffer_info) {
9a799d71 2944 DPRINTK(PROBE, ERR,
b4617240 2945 "vmalloc allocation failed for the rx desc ring\n");
177db6ff 2946 goto alloc_failed;
9a799d71 2947 }
3a581073 2948 memset(rx_ring->rx_buffer_info, 0, size);
9a799d71 2949
9a799d71 2950 /* Round up to nearest 4K */
3a581073
JB		 2951 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
2952 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 2953
3a581073 2954 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
9a799d71 2955
3a581073 2956 if (!rx_ring->desc) {
9a799d71 2957 DPRINTK(PROBE, ERR,
b4617240 2958 "Memory allocation failed for the rx desc ring\n");
3a581073 2959 vfree(rx_ring->rx_buffer_info);
177db6ff 2960 goto alloc_failed;
9a799d71
AK		 2961 }
2962
3a581073
JB		 2963 rx_ring->next_to_clean = 0;
2964 rx_ring->next_to_use = 0;
9a799d71
AK		 2965
2966 return 0;
177db6ff
MC		 2967
2968alloc_failed:
177db6ff 2969 return -ENOMEM;
9a799d71
AK		 2970}
2971
69888674
AD		 2972/**
2973 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
2974 * @adapter: board private structure
2975 *
2976 * If this function returns with an error, then it's possible one or
2977 * more of the rings is populated (while the rest are not). It is the
2978 * callers duty to clean those orphaned rings.
2979 *
2980 * Return 0 on success, negative on failure
2981 **/
2982
2983static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
2984{
2985 int i, err = 0;
2986
2987 for (i = 0; i < adapter->num_rx_queues; i++) {
2988 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
2989 if (!err)
2990 continue;
2991 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
2992 break;
2993 }
2994
2995 return err;
2996}
2997
9a799d71
AK		 2998/**
2999 * ixgbe_free_tx_resources - Free Tx Resources per Queue
3000 * @adapter: board private structure
3001 * @tx_ring: Tx descriptor ring for a specific queue
3002 *
3003 * Free all transmit software resources
3004 **/
c431f97e
JB		 3005void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
3006 struct ixgbe_ring *tx_ring)
9a799d71
AK		 3007{
3008 struct pci_dev *pdev = adapter->pdev;
3009
3010 ixgbe_clean_tx_ring(adapter, tx_ring);
3011
3012 vfree(tx_ring->tx_buffer_info);
3013 tx_ring->tx_buffer_info = NULL;
3014
3015 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
3016
3017 tx_ring->desc = NULL;
3018}
3019
3020/**
3021 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
3022 * @adapter: board private structure
3023 *
3024 * Free all transmit software resources
3025 **/
3026static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
3027{
3028 int i;
3029
3030 for (i = 0; i < adapter->num_tx_queues; i++)
3031 ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
3032}
3033
3034/**
b4617240 3035 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 3036 * @adapter: board private structure
3037 * @rx_ring: ring to clean the resources from
3038 *
3039 * Free all receive software resources
3040 **/
c431f97e
JB		 3041void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
3042 struct ixgbe_ring *rx_ring)
9a799d71
AK		 3043{
3044 struct pci_dev *pdev = adapter->pdev;
3045
3046 ixgbe_clean_rx_ring(adapter, rx_ring);
3047
3048 vfree(rx_ring->rx_buffer_info);
3049 rx_ring->rx_buffer_info = NULL;
3050
3051 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
3052
3053 rx_ring->desc = NULL;
3054}
3055
3056/**
3057 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
3058 * @adapter: board private structure
3059 *
3060 * Free all receive software resources
3061 **/
3062static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
3063{
3064 int i;
3065
3066 for (i = 0; i < adapter->num_rx_queues; i++)
3067 ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
3068}
3069
9a799d71
AK		 3070/**
3071 * ixgbe_change_mtu - Change the Maximum Transfer Unit
3072 * @netdev: network interface device structure
3073 * @new_mtu: new value for maximum frame size
3074 *
3075 * Returns 0 on success, negative on failure
3076 **/
3077static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
3078{
3079 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3080 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3081
42c783c5
JB		 3082 /* MTU < 68 is an error and causes problems on some kernels */
3083 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
9a799d71
AK		 3084 return -EINVAL;
3085
021230d4 3086 DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
b4617240 3087 netdev->mtu, new_mtu);
021230d4 3088 /* must set new MTU before calling down or up */
9a799d71
AK		 3089 netdev->mtu = new_mtu;
3090
d4f80882
AV		 3091 if (netif_running(netdev))
3092 ixgbe_reinit_locked(adapter);
9a799d71
AK		 3093
3094 return 0;
3095}
3096
3097/**
3098 * ixgbe_open - Called when a network interface is made active
3099 * @netdev: network interface device structure
3100 *
3101 * Returns 0 on success, negative value on failure
3102 *
3103 * The open entry point is called when a network interface is made
3104 * active by the system (IFF_UP). At this point all resources needed
3105 * for transmit and receive operations are allocated, the interrupt
3106 * handler is registered with the OS, the watchdog timer is started,
3107 * and the stack is notified that the interface is ready.
3108 **/
3109static int ixgbe_open(struct net_device *netdev)
3110{
3111 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3112 int err;
4bebfaa5
AK		 3113
3114 /* disallow open during test */
3115 if (test_bit(__IXGBE_TESTING, &adapter->state))
3116 return -EBUSY;
9a799d71 3117
9a799d71
AK		 3118 /* allocate transmit descriptors */
3119 err = ixgbe_setup_all_tx_resources(adapter);
3120 if (err)
3121 goto err_setup_tx;
3122
9a799d71
AK		 3123 /* allocate receive descriptors */
3124 err = ixgbe_setup_all_rx_resources(adapter);
3125 if (err)
3126 goto err_setup_rx;
3127
3128 ixgbe_configure(adapter);
3129
021230d4 3130 err = ixgbe_request_irq(adapter);
9a799d71
AK		 3131 if (err)
3132 goto err_req_irq;
3133
9a799d71
AK		 3134 err = ixgbe_up_complete(adapter);
3135 if (err)
3136 goto err_up;
3137
d55b53ff
JK		 3138 netif_tx_start_all_queues(netdev);
3139
9a799d71
AK		 3140 return 0;
3141
3142err_up:
5eba3699 3143 ixgbe_release_hw_control(adapter);
9a799d71
AK		 3144 ixgbe_free_irq(adapter);
3145err_req_irq:
3146 ixgbe_free_all_rx_resources(adapter);
3147err_setup_rx:
3148 ixgbe_free_all_tx_resources(adapter);
3149err_setup_tx:
3150 ixgbe_reset(adapter);
3151
3152 return err;
3153}
3154
3155/**
3156 * ixgbe_close - Disables a network interface
3157 * @netdev: network interface device structure
3158 *
3159 * Returns 0, this is not allowed to fail
3160 *
3161 * The close entry point is called when an interface is de-activated
3162 * by the OS. The hardware is still under the drivers control, but
3163 * needs to be disabled. A global MAC reset is issued to stop the
3164 * hardware, and all transmit and receive resources are freed.
3165 **/
3166static int ixgbe_close(struct net_device *netdev)
3167{
3168 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 3169
3170 ixgbe_down(adapter);
3171 ixgbe_free_irq(adapter);
3172
3173 ixgbe_free_all_tx_resources(adapter);
3174 ixgbe_free_all_rx_resources(adapter);
3175
5eba3699 3176 ixgbe_release_hw_control(adapter);
9a799d71
AK		 3177
3178 return 0;
3179}
3180
b3c8b4ba
AD		 3181/**
3182 * ixgbe_napi_add_all - prep napi structs for use
3183 * @adapter: private struct
3184 * helper function to napi_add each possible q_vector->napi
3185 */
2f90b865 3186void ixgbe_napi_add_all(struct ixgbe_adapter *adapter)
b3c8b4ba
AD		 3187{
3188 int q_idx, q_vectors;
7adf1525 3189 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 3190 int (*poll)(struct napi_struct *, int);
3191
7adf1525
PWJ		 3192 /* check if we already have our netdev->napi_list populated */
3193 if (&netdev->napi_list != netdev->napi_list.next)
3194 return;
3195
b3c8b4ba
AD		 3196 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3197 poll = &ixgbe_clean_rxonly;
3198 /* Only enable as many vectors as we have rx queues. */
3199 q_vectors = adapter->num_rx_queues;
3200 } else {
3201 poll = &ixgbe_poll;
3202 /* only one q_vector for legacy modes */
3203 q_vectors = 1;
3204 }
3205
3206 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3207 struct ixgbe_q_vector *q_vector = &adapter->q_vector[q_idx];
3208 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
3209 }
3210}
3211
2f90b865 3212void ixgbe_napi_del_all(struct ixgbe_adapter *adapter)
b3c8b4ba
AD		 3213{
3214 int q_idx;
3215 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3216
3217 /* legacy and MSI only use one vector */
3218 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3219 q_vectors = 1;
3220
3221 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3222 struct ixgbe_q_vector *q_vector = &adapter->q_vector[q_idx];
3223 if (!q_vector->rxr_count)
3224 continue;
3225 netif_napi_del(&q_vector->napi);
3226 }
3227}
3228
3229#ifdef CONFIG_PM
3230static int ixgbe_resume(struct pci_dev *pdev)
3231{
3232 struct net_device *netdev = pci_get_drvdata(pdev);
3233 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3234 u32 err;
3235
3236 pci_set_power_state(pdev, PCI_D0);
3237 pci_restore_state(pdev);
3238 err = pci_enable_device(pdev);
3239 if (err) {
69888674 3240 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
b3c8b4ba
AD		 3241 "suspend\n");
3242 return err;
3243 }
3244 pci_set_master(pdev);
3245
3246 pci_enable_wake(pdev, PCI_D3hot, 0);
3247 pci_enable_wake(pdev, PCI_D3cold, 0);
3248
3249 err = ixgbe_init_interrupt_scheme(adapter);
3250 if (err) {
3251 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
3252 "device\n");
3253 return err;
3254 }
3255
3256 ixgbe_napi_add_all(adapter);
3257 ixgbe_reset(adapter);
3258
3259 if (netif_running(netdev)) {
3260 err = ixgbe_open(adapter->netdev);
3261 if (err)
3262 return err;
3263 }
3264
3265 netif_device_attach(netdev);
3266
3267 return 0;
3268}
3269
3270#endif /* CONFIG_PM */
3271static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
3272{
3273 struct net_device *netdev = pci_get_drvdata(pdev);
3274 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3275#ifdef CONFIG_PM
3276 int retval = 0;
3277#endif
3278
3279 netif_device_detach(netdev);
3280
3281 if (netif_running(netdev)) {
3282 ixgbe_down(adapter);
3283 ixgbe_free_irq(adapter);
3284 ixgbe_free_all_tx_resources(adapter);
3285 ixgbe_free_all_rx_resources(adapter);
3286 }
3287 ixgbe_reset_interrupt_capability(adapter);
3288 ixgbe_napi_del_all(adapter);
7adf1525 3289 INIT_LIST_HEAD(&netdev->napi_list);
b3c8b4ba
AD		 3290 kfree(adapter->tx_ring);
3291 kfree(adapter->rx_ring);
3292
3293#ifdef CONFIG_PM
3294 retval = pci_save_state(pdev);
3295 if (retval)
3296 return retval;
3297#endif
3298
3299 pci_enable_wake(pdev, PCI_D3hot, 0);
3300 pci_enable_wake(pdev, PCI_D3cold, 0);
3301
3302 ixgbe_release_hw_control(adapter);
3303
3304 pci_disable_device(pdev);
3305
3306 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3307
3308 return 0;
3309}
3310
3311static void ixgbe_shutdown(struct pci_dev *pdev)
3312{
3313 ixgbe_suspend(pdev, PMSG_SUSPEND);
3314}
3315
9a799d71
AK		 3316/**
3317 * ixgbe_update_stats - Update the board statistics counters.
3318 * @adapter: board private structure
3319 **/
3320void ixgbe_update_stats(struct ixgbe_adapter *adapter)
3321{
3322 struct ixgbe_hw *hw = &adapter->hw;
6f11eef7
AV		 3323 u64 total_mpc = 0;
3324 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
9a799d71
AK		 3325
3326 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 3327 for (i = 0; i < 8; i++) {
3328 /* for packet buffers not used, the register should read 0 */
3329 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3330 missed_rx += mpc;
3331 adapter->stats.mpc[i] += mpc;
3332 total_mpc += adapter->stats.mpc[i];
3333 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2f90b865
AD		 3334 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3335 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
3336 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3337 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
3338 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
3339 IXGBE_PXONRXC(i));
3340 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
3341 IXGBE_PXONTXC(i));
3342 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
3343 IXGBE_PXOFFRXC(i));
3344 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
3345 IXGBE_PXOFFTXC(i));
6f11eef7
AV		 3346 }
3347 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
3348 /* work around hardware counting issue */
3349 adapter->stats.gprc -= missed_rx;
3350
3351 /* 82598 hardware only has a 32 bit counter in the high register */
9a799d71 3352 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
6f11eef7
AV		 3353 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3354 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
9a799d71
AK		 3355 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3356 adapter->stats.bprc += bprc;
3357 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3358 adapter->stats.mprc -= bprc;
3359 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3360 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3361 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3362 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3363 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3364 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3365 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
9a799d71
AK		 3366 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3367 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
9a799d71 3368 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
6f11eef7
AV		 3369 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3370 adapter->stats.lxontxc += lxon;
3371 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3372 adapter->stats.lxofftxc += lxoff;
9a799d71
AK		 3373 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3374 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6f11eef7
AV		 3375 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3376 /*
3377 * 82598 errata - tx of flow control packets is included in tx counters
3378 */
3379 xon_off_tot = lxon + lxoff;
3380 adapter->stats.gptc -= xon_off_tot;
3381 adapter->stats.mptc -= xon_off_tot;
3382 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
9a799d71
AK		 3383 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3384 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3385 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
9a799d71
AK		 3386 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3387 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6f11eef7 3388 adapter->stats.ptc64 -= xon_off_tot;
9a799d71
AK		 3389 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3390 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3391 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3392 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3393 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
9a799d71
AK		 3394 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3395
3396 /* Fill out the OS statistics structure */
9a799d71
AK		 3397 adapter->net_stats.multicast = adapter->stats.mprc;
3398
3399 /* Rx Errors */
3400 adapter->net_stats.rx_errors = adapter->stats.crcerrs +
b4617240 3401 adapter->stats.rlec;
9a799d71
AK		 3402 adapter->net_stats.rx_dropped = 0;
3403 adapter->net_stats.rx_length_errors = adapter->stats.rlec;
3404 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
6f11eef7 3405 adapter->net_stats.rx_missed_errors = total_mpc;
9a799d71
AK		 3406}
3407
3408/**
3409 * ixgbe_watchdog - Timer Call-back
3410 * @data: pointer to adapter cast into an unsigned long
3411 **/
3412static void ixgbe_watchdog(unsigned long data)
3413{
3414 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
cf8280ee
JB		 3415 struct ixgbe_hw *hw = &adapter->hw;
3416
3417 /* Do the watchdog outside of interrupt context due to the lovely
3418 * delays that some of the newer hardware requires */
3419 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
3420 /* Cause software interrupt to ensure rx rings are cleaned */
3421 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3422 u32 eics =
3423 (1 << (adapter->num_msix_vectors - NON_Q_VECTORS)) - 1;
3424 IXGBE_WRITE_REG(hw, IXGBE_EICS, eics);
3425 } else {
3426 /* For legacy and MSI interrupts don't set any bits that
3427 * are enabled for EIAM, because this operation would
3428 * set *both* EIMS and EICS for any bit in EIAM */
3429 IXGBE_WRITE_REG(hw, IXGBE_EICS,
3430 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
3431 }
3432 /* Reset the timer */
3433 mod_timer(&adapter->watchdog_timer,
3434 round_jiffies(jiffies + 2 * HZ));
3435 }
9a799d71 3436
cf8280ee
JB		 3437 schedule_work(&adapter->watchdog_task);
3438}
3439
3440/**
69888674
AD		 3441 * ixgbe_watchdog_task - worker thread to bring link up
3442 * @work: pointer to work_struct containing our data
cf8280ee
JB		 3443 **/
3444static void ixgbe_watchdog_task(struct work_struct *work)
3445{
3446 struct ixgbe_adapter *adapter = container_of(work,
3447 struct ixgbe_adapter,
3448 watchdog_task);
3449 struct net_device *netdev = adapter->netdev;
3450 struct ixgbe_hw *hw = &adapter->hw;
3451 u32 link_speed = adapter->link_speed;
3452 bool link_up = adapter->link_up;
3453
3454 adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
3455
3456 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3457 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
3458 if (link_up ||
3459 time_after(jiffies, (adapter->link_check_timeout +
3460 IXGBE_TRY_LINK_TIMEOUT))) {
3461 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
3462 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3463 }
3464 adapter->link_up = link_up;
3465 adapter->link_speed = link_speed;
3466 }
9a799d71
AK		 3467
3468 if (link_up) {
3469 if (!netif_carrier_ok(netdev)) {
cf8280ee
JB		 3470 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3471 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
9a799d71
AK		 3472#define FLOW_RX (frctl & IXGBE_FCTRL_RFCE)
3473#define FLOW_TX (rmcs & IXGBE_RMCS_TFCE_802_3X)
a46e534b
JK		 3474 printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
3475 "Flow Control: %s\n",
3476 netdev->name,
3477 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
3478 "10 Gbps" :
3479 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
3480 "1 Gbps" : "unknown speed")),
3481 ((FLOW_RX && FLOW_TX) ? "RX/TX" :
3482 (FLOW_RX ? "RX" :
3483 (FLOW_TX ? "TX" : "None"))));
9a799d71
AK		 3484
3485 netif_carrier_on(netdev);
9a799d71
AK		 3486 } else {
3487 /* Force detection of hung controller */
3488 adapter->detect_tx_hung = true;
3489 }
3490 } else {
cf8280ee
JB		 3491 adapter->link_up = false;
3492 adapter->link_speed = 0;
9a799d71 3493 if (netif_carrier_ok(netdev)) {
a46e534b
JK		 3494 printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
3495 netdev->name);
9a799d71 3496 netif_carrier_off(netdev);
9a799d71
AK		 3497 }
3498 }
3499
3500 ixgbe_update_stats(adapter);
cf8280ee 3501 adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
9a799d71
AK		 3502}
3503
9a799d71 3504static int ixgbe_tso(struct ixgbe_adapter *adapter,
b4617240
PW		 3505 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
3506 u32 tx_flags, u8 *hdr_len)
9a799d71
AK		 3507{
3508 struct ixgbe_adv_tx_context_desc *context_desc;
3509 unsigned int i;
3510 int err;
3511 struct ixgbe_tx_buffer *tx_buffer_info;
9f8cdf4f
JB		 3512 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
3513 u32 mss_l4len_idx, l4len;
9a799d71
AK		 3514
3515 if (skb_is_gso(skb)) {
3516 if (skb_header_cloned(skb)) {
3517 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
3518 if (err)
3519 return err;
3520 }
3521 l4len = tcp_hdrlen(skb);
3522 *hdr_len += l4len;
3523
8327d000 3524 if (skb->protocol == htons(ETH_P_IP)) {
9a799d71
AK		 3525 struct iphdr *iph = ip_hdr(skb);
3526 iph->tot_len = 0;
3527 iph->check = 0;
3528 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b4617240
PW		 3529 iph->daddr, 0,
3530 IPPROTO_TCP,
3531 0);
9a799d71
AK		 3532 adapter->hw_tso_ctxt++;
3533 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
3534 ipv6_hdr(skb)->payload_len = 0;
3535 tcp_hdr(skb)->check =
3536 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
b4617240
PW		 3537 &ipv6_hdr(skb)->daddr,
3538 0, IPPROTO_TCP, 0);
9a799d71
AK		 3539 adapter->hw_tso6_ctxt++;
3540 }
3541
3542 i = tx_ring->next_to_use;
3543
3544 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3545 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
3546
3547 /* VLAN MACLEN IPLEN */
3548 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
3549 vlan_macip_lens |=
3550 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
3551 vlan_macip_lens |= ((skb_network_offset(skb)) <<
b4617240 3552 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 3553 *hdr_len += skb_network_offset(skb);
3554 vlan_macip_lens |=
3555 (skb_transport_header(skb) - skb_network_header(skb));
3556 *hdr_len +=
3557 (skb_transport_header(skb) - skb_network_header(skb));
3558 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
3559 context_desc->seqnum_seed = 0;
3560
3561 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
9f8cdf4f 3562 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
b4617240 3563 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 3564
8327d000 3565 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 3566 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
3567 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
3568 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
3569
3570 /* MSS L4LEN IDX */
9f8cdf4f 3571 mss_l4len_idx =
9a799d71
AK		 3572 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
3573 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4eeae6fd
PW		 3574 /* use index 1 for TSO */
3575 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 3576 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
3577
3578 tx_buffer_info->time_stamp = jiffies;
3579 tx_buffer_info->next_to_watch = i;
3580
3581 i++;
3582 if (i == tx_ring->count)
3583 i = 0;
3584 tx_ring->next_to_use = i;
3585
3586 return true;
3587 }
3588 return false;
3589}
3590
3591static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
b4617240
PW		 3592 struct ixgbe_ring *tx_ring,
3593 struct sk_buff *skb, u32 tx_flags)
9a799d71
AK		 3594{
3595 struct ixgbe_adv_tx_context_desc *context_desc;
3596 unsigned int i;
3597 struct ixgbe_tx_buffer *tx_buffer_info;
3598 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
3599
3600 if (skb->ip_summed == CHECKSUM_PARTIAL ||
3601 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
3602 i = tx_ring->next_to_use;
3603 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3604 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
3605
3606 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
3607 vlan_macip_lens |=
3608 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
3609 vlan_macip_lens |= (skb_network_offset(skb) <<
b4617240 3610 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 3611 if (skb->ip_summed == CHECKSUM_PARTIAL)
3612 vlan_macip_lens |= (skb_transport_header(skb) -
b4617240 3613 skb_network_header(skb));
9a799d71
AK		 3614
3615 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
3616 context_desc->seqnum_seed = 0;
3617
3618 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
b4617240 3619 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71
AK		 3620
3621 if (skb->ip_summed == CHECKSUM_PARTIAL) {
41825d71 3622 switch (skb->protocol) {
09640e63 3623 case cpu_to_be16(ETH_P_IP):
9a799d71 3624 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
41825d71
AK		 3625 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
3626 type_tucmd_mlhl |=
b4617240 3627 IXGBE_ADVTXD_TUCMD_L4T_TCP;
41825d71 3628 break;
09640e63 3629 case cpu_to_be16(ETH_P_IPV6):
41825d71
AK		 3630 /* XXX what about other V6 headers?? */
3631 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
3632 type_tucmd_mlhl |=
b4617240 3633 IXGBE_ADVTXD_TUCMD_L4T_TCP;
41825d71 3634 break;
41825d71
AK		 3635 default:
3636 if (unlikely(net_ratelimit())) {
3637 DPRINTK(PROBE, WARNING,
3638 "partial checksum but proto=%x!\n",
3639 skb->protocol);
3640 }
3641 break;
3642 }
9a799d71
AK		 3643 }
3644
3645 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4eeae6fd 3646 /* use index zero for tx checksum offload */
9a799d71
AK		 3647 context_desc->mss_l4len_idx = 0;
3648
3649 tx_buffer_info->time_stamp = jiffies;
3650 tx_buffer_info->next_to_watch = i;
9f8cdf4f 3651
9a799d71
AK		 3652 adapter->hw_csum_tx_good++;
3653 i++;
3654 if (i == tx_ring->count)
3655 i = 0;
3656 tx_ring->next_to_use = i;
3657
3658 return true;
3659 }
9f8cdf4f 3660
9a799d71
AK		 3661 return false;
3662}
3663
3664static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
b4617240
PW		 3665 struct ixgbe_ring *tx_ring,
3666 struct sk_buff *skb, unsigned int first)
9a799d71
AK		 3667{
3668 struct ixgbe_tx_buffer *tx_buffer_info;
3669 unsigned int len = skb->len;
3670 unsigned int offset = 0, size, count = 0, i;
3671 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
3672 unsigned int f;
3673
3674 len -= skb->data_len;
3675
3676 i = tx_ring->next_to_use;
3677
3678 while (len) {
3679 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3680 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
3681
3682 tx_buffer_info->length = size;
3683 tx_buffer_info->dma = pci_map_single(adapter->pdev,
b4617240
PW		 3684 skb->data + offset,
3685 size, PCI_DMA_TODEVICE);
9a799d71
AK		 3686 tx_buffer_info->time_stamp = jiffies;
3687 tx_buffer_info->next_to_watch = i;
3688
3689 len -= size;
3690 offset += size;
3691 count++;
3692 i++;
3693 if (i == tx_ring->count)
3694 i = 0;
3695 }
3696
3697 for (f = 0; f < nr_frags; f++) {
3698 struct skb_frag_struct *frag;
3699
3700 frag = &skb_shinfo(skb)->frags[f];
3701 len = frag->size;
3702 offset = frag->page_offset;
3703
3704 while (len) {
3705 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3706 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
3707
3708 tx_buffer_info->length = size;
3709 tx_buffer_info->dma = pci_map_page(adapter->pdev,
b4617240
PW		 3710 frag->page,
3711 offset,
3712 size,
3713 PCI_DMA_TODEVICE);
9a799d71
AK		 3714 tx_buffer_info->time_stamp = jiffies;
3715 tx_buffer_info->next_to_watch = i;
3716
3717 len -= size;
3718 offset += size;
3719 count++;
3720 i++;
3721 if (i == tx_ring->count)
3722 i = 0;
3723 }
3724 }
3725 if (i == 0)
3726 i = tx_ring->count - 1;
3727 else
3728 i = i - 1;
3729 tx_ring->tx_buffer_info[i].skb = skb;
3730 tx_ring->tx_buffer_info[first].next_to_watch = i;
3731
3732 return count;
3733}
3734
3735static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
b4617240
PW		 3736 struct ixgbe_ring *tx_ring,
3737 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 3738{
3739 union ixgbe_adv_tx_desc *tx_desc = NULL;
3740 struct ixgbe_tx_buffer *tx_buffer_info;
3741 u32 olinfo_status = 0, cmd_type_len = 0;
3742 unsigned int i;
3743 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
3744
3745 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
3746
3747 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
3748
3749 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
3750 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
3751
3752 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
3753 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
3754
3755 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 3756 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 3757
4eeae6fd
PW		 3758 /* use index 1 context for tso */
3759 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 3760 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
3761 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
b4617240 3762 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 3763
3764 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
3765 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 3766 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 3767
3768 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
3769
3770 i = tx_ring->next_to_use;
3771 while (count--) {
3772 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3773 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
3774 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
3775 tx_desc->read.cmd_type_len =
b4617240 3776 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71 3777 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
9a799d71
AK		 3778 i++;
3779 if (i == tx_ring->count)
3780 i = 0;
3781 }
3782
3783 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
3784
3785 /*
3786 * Force memory writes to complete before letting h/w
3787 * know there are new descriptors to fetch. (Only
3788 * applicable for weak-ordered memory model archs,
3789 * such as IA-64).
3790 */
3791 wmb();
3792
3793 tx_ring->next_to_use = i;
3794 writel(i, adapter->hw.hw_addr + tx_ring->tail);
3795}
3796
e092be60 3797static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 3798 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 3799{
3800 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3801
30eba97a 3802 netif_stop_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 3803 /* Herbert's original patch had:
3804 * smp_mb__after_netif_stop_queue();
3805 * but since that doesn't exist yet, just open code it. */
3806 smp_mb();
3807
3808 /* We need to check again in a case another CPU has just
3809 * made room available. */
3810 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
3811 return -EBUSY;
3812
3813 /* A reprieve! - use start_queue because it doesn't call schedule */
af72166f 3814 netif_start_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 3815 ++adapter->restart_queue;
3816 return 0;
3817}
3818
3819static int ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 3820 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 3821{
3822 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
3823 return 0;
3824 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
3825}
3826
9a799d71
AK		 3827static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
3828{
3829 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3830 struct ixgbe_ring *tx_ring;
9a799d71
AK		 3831 unsigned int first;
3832 unsigned int tx_flags = 0;
30eba97a
AV		 3833 u8 hdr_len = 0;
3834 int r_idx = 0, tso;
9a799d71
AK		 3835 int count = 0;
3836 unsigned int f;
9f8cdf4f 3837
30eba97a 3838 r_idx = (adapter->num_tx_queues - 1) & skb->queue_mapping;
30eba97a 3839 tx_ring = &adapter->tx_ring[r_idx];
9a799d71 3840
9f8cdf4f
JB		 3841 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
3842 tx_flags |= vlan_tx_tag_get(skb);
2f90b865
AD		 3843 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3844 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
3845 tx_flags |= (skb->queue_mapping << 13);
3846 }
3847 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
3848 tx_flags |= IXGBE_TX_FLAGS_VLAN;
3849 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3850 tx_flags |= (skb->queue_mapping << 13);
9f8cdf4f
JB		 3851 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
3852 tx_flags |= IXGBE_TX_FLAGS_VLAN;
9a799d71 3853 }
9f8cdf4f
JB		 3854 /* three things can cause us to need a context descriptor */
3855 if (skb_is_gso(skb) ||
3856 (skb->ip_summed == CHECKSUM_PARTIAL) ||
3857 (tx_flags & IXGBE_TX_FLAGS_VLAN))
9a799d71
AK		 3858 count++;
3859
9f8cdf4f
JB		 3860 count += TXD_USE_COUNT(skb_headlen(skb));
3861 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
9a799d71
AK		 3862 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
3863
e092be60 3864 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
9a799d71 3865 adapter->tx_busy++;
9a799d71
AK		 3866 return NETDEV_TX_BUSY;
3867 }
9a799d71 3868
8327d000 3869 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 3870 tx_flags |= IXGBE_TX_FLAGS_IPV4;
3871 first = tx_ring->next_to_use;
3872 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
3873 if (tso < 0) {
3874 dev_kfree_skb_any(skb);
3875 return NETDEV_TX_OK;
3876 }
3877
3878 if (tso)
3879 tx_flags |= IXGBE_TX_FLAGS_TSO;
3880 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
b4617240 3881 (skb->ip_summed == CHECKSUM_PARTIAL))
9a799d71
AK		 3882 tx_flags |= IXGBE_TX_FLAGS_CSUM;
3883
3884 ixgbe_tx_queue(adapter, tx_ring, tx_flags,
b4617240
PW		 3885 ixgbe_tx_map(adapter, tx_ring, skb, first),
3886 skb->len, hdr_len);
9a799d71
AK		 3887
3888 netdev->trans_start = jiffies;
3889
e092be60 3890 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
9a799d71
AK		 3891
3892 return NETDEV_TX_OK;
3893}
3894
3895/**
3896 * ixgbe_get_stats - Get System Network Statistics
3897 * @netdev: network interface device structure
3898 *
3899 * Returns the address of the device statistics structure.
3900 * The statistics are actually updated from the timer callback.
3901 **/
3902static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
3903{
3904 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3905
3906 /* only return the current stats */
3907 return &adapter->net_stats;
3908}
3909
3910/**
3911 * ixgbe_set_mac - Change the Ethernet Address of the NIC
3912 * @netdev: network interface device structure
3913 * @p: pointer to an address structure
3914 *
3915 * Returns 0 on success, negative on failure
3916 **/
3917static int ixgbe_set_mac(struct net_device *netdev, void *p)
3918{
3919 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 3920 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 3921 struct sockaddr *addr = p;
3922
3923 if (!is_valid_ether_addr(addr->sa_data))
3924 return -EADDRNOTAVAIL;
3925
3926 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 3927 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 3928
b4617240 3929 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71
AK		 3930
3931 return 0;
3932}
3933
3934#ifdef CONFIG_NET_POLL_CONTROLLER
3935/*
3936 * Polling 'interrupt' - used by things like netconsole to send skbs
3937 * without having to re-enable interrupts. It's not called while
3938 * the interrupt routine is executing.
3939 */
3940static void ixgbe_netpoll(struct net_device *netdev)
3941{
3942 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3943
3944 disable_irq(adapter->pdev->irq);
3945 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
3946 ixgbe_intr(adapter->pdev->irq, netdev);
3947 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
3948 enable_irq(adapter->pdev->irq);
3949}
3950#endif
3951
0edc3527
SH		 3952static const struct net_device_ops ixgbe_netdev_ops = {
3953 .ndo_open = ixgbe_open,
3954 .ndo_stop = ixgbe_close,
00829823 3955 .ndo_start_xmit = ixgbe_xmit_frame,
0edc3527
SH		 3956 .ndo_get_stats = ixgbe_get_stats,
3957 .ndo_set_multicast_list = ixgbe_set_rx_mode,
3958 .ndo_validate_addr = eth_validate_addr,
3959 .ndo_set_mac_address = ixgbe_set_mac,
3960 .ndo_change_mtu = ixgbe_change_mtu,
3961 .ndo_tx_timeout = ixgbe_tx_timeout,
3962 .ndo_vlan_rx_register = ixgbe_vlan_rx_register,
3963 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
3964 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
3965#ifdef CONFIG_NET_POLL_CONTROLLER
3966 .ndo_poll_controller = ixgbe_netpoll,
3967#endif
3968};
3969
9a799d71
AK		 3970/**
3971 * ixgbe_probe - Device Initialization Routine
3972 * @pdev: PCI device information struct
3973 * @ent: entry in ixgbe_pci_tbl
3974 *
3975 * Returns 0 on success, negative on failure
3976 *
3977 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
3978 * The OS initialization, configuring of the adapter private structure,
3979 * and a hardware reset occur.
3980 **/
3981static int __devinit ixgbe_probe(struct pci_dev *pdev,
b4617240 3982 const struct pci_device_id *ent)
9a799d71
AK		 3983{
3984 struct net_device *netdev;
3985 struct ixgbe_adapter *adapter = NULL;
3986 struct ixgbe_hw *hw;
3987 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 3988 static int cards_found;
3989 int i, err, pci_using_dac;
3990 u16 link_status, link_speed, link_width;
c44ade9e 3991 u32 part_num, eec;
9a799d71
AK		 3992
3993 err = pci_enable_device(pdev);
3994 if (err)
3995 return err;
3996
3997 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK) &&
3998 !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK)) {
3999 pci_using_dac = 1;
4000 } else {
4001 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
4002 if (err) {
4003 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
4004 if (err) {
b4617240
PW		 4005 dev_err(&pdev->dev, "No usable DMA "
4006 "configuration, aborting\n");
9a799d71
AK		 4007 goto err_dma;
4008 }
4009 }
4010 pci_using_dac = 0;
4011 }
4012
4013 err = pci_request_regions(pdev, ixgbe_driver_name);
4014 if (err) {
4015 dev_err(&pdev->dev, "pci_request_regions failed 0x%x\n", err);
4016 goto err_pci_reg;
4017 }
4018
6fabd715
PWJ		 4019 err = pci_enable_pcie_error_reporting(pdev);
4020 if (err) {
4021 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
4022 "0x%x\n", err);
4023 /* non-fatal, continue */
4024 }
4025
9a799d71 4026 pci_set_master(pdev);
fb3b27bc 4027 pci_save_state(pdev);
9a799d71 4028
30eba97a 4029 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
9a799d71
AK		 4030 if (!netdev) {
4031 err = -ENOMEM;
4032 goto err_alloc_etherdev;
4033 }
4034
9a799d71
AK		 4035 SET_NETDEV_DEV(netdev, &pdev->dev);
4036
4037 pci_set_drvdata(pdev, netdev);
4038 adapter = netdev_priv(netdev);
4039
4040 adapter->netdev = netdev;
4041 adapter->pdev = pdev;
4042 hw = &adapter->hw;
4043 hw->back = adapter;
4044 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
4045
05857980
JK		 4046 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
4047 pci_resource_len(pdev, 0));
9a799d71
AK		 4048 if (!hw->hw_addr) {
4049 err = -EIO;
4050 goto err_ioremap;
4051 }
4052
4053 for (i = 1; i <= 5; i++) {
4054 if (pci_resource_len(pdev, i) == 0)
4055 continue;
4056 }
4057
0edc3527 4058 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 4059 ixgbe_set_ethtool_ops(netdev);
9a799d71 4060 netdev->watchdog_timeo = 5 * HZ;
9a799d71
AK		 4061 strcpy(netdev->name, pci_name(pdev));
4062
9a799d71
AK		 4063 adapter->bd_number = cards_found;
4064
9a799d71
AK		 4065 /* Setup hw api */
4066 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 4067 hw->mac.type = ii->mac;
9a799d71 4068
c44ade9e
JB		 4069 /* EEPROM */
4070 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
4071 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
4072 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
4073 if (!(eec & (1 << 8)))
4074 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
4075
4076 /* PHY */
4077 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0
DS		 4078 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
4079
4080 /* set up this timer and work struct before calling get_invariants
4081 * which might start the timer
4082 */
4083 init_timer(&adapter->sfp_timer);
4084 adapter->sfp_timer.function = &ixgbe_sfp_timer;
4085 adapter->sfp_timer.data = (unsigned long) adapter;
4086
4087 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
c44ade9e 4088
9a799d71 4089 err = ii->get_invariants(hw);
c4900be0
DS		 4090 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
4091 /* start a kernel thread to watch for a module to arrive */
4092 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4093 mod_timer(&adapter->sfp_timer,
4094 round_jiffies(jiffies + (2 * HZ)));
4095 err = 0;
4096 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4097 DPRINTK(PROBE, ERR, "failed to load because an "
4098 "unsupported SFP+ module type was detected.\n");
9a799d71 4099 goto err_hw_init;
c4900be0
DS		 4100 } else if (err) {
4101 goto err_hw_init;
4102 }
9a799d71
AK		 4103
4104 /* setup the private structure */
4105 err = ixgbe_sw_init(adapter);
4106 if (err)
4107 goto err_sw_init;
4108
c44ade9e
JB		 4109 /* reset_hw fills in the perm_addr as well */
4110 err = hw->mac.ops.reset_hw(hw);
4111 if (err) {
4112 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
4113 goto err_sw_init;
4114 }
4115
9a799d71 4116 netdev->features = NETIF_F_SG |
b4617240
PW		 4117 NETIF_F_IP_CSUM |
4118 NETIF_F_HW_VLAN_TX |
4119 NETIF_F_HW_VLAN_RX |
4120 NETIF_F_HW_VLAN_FILTER;
9a799d71 4121
e9990a9c 4122 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 4123 netdev->features |= NETIF_F_TSO;
9a799d71 4124 netdev->features |= NETIF_F_TSO6;
78b6f4ce 4125 netdev->features |= NETIF_F_GRO;
ad31c402
JK		 4126
4127 netdev->vlan_features |= NETIF_F_TSO;
4128 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 4129 netdev->vlan_features |= NETIF_F_IP_CSUM;
ad31c402
JK		 4130 netdev->vlan_features |= NETIF_F_SG;
4131
2f90b865
AD		 4132 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
4133 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4134
7a6b6f51 4135#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4136 netdev->dcbnl_ops = &dcbnl_ops;
4137#endif
4138
9a799d71
AK		 4139 if (pci_using_dac)
4140 netdev->features |= NETIF_F_HIGHDMA;
4141
9a799d71 4142 /* make sure the EEPROM is good */
c44ade9e 4143 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
9a799d71
AK		 4144 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
4145 err = -EIO;
4146 goto err_eeprom;
4147 }
4148
4149 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
4150 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
4151
c44ade9e
JB		 4152 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
4153 dev_err(&pdev->dev, "invalid MAC address\n");
9a799d71
AK		 4154 err = -EIO;
4155 goto err_eeprom;
4156 }
4157
4158 init_timer(&adapter->watchdog_timer);
4159 adapter->watchdog_timer.function = &ixgbe_watchdog;
4160 adapter->watchdog_timer.data = (unsigned long)adapter;
4161
4162 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
cf8280ee 4163 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
9a799d71 4164
021230d4
AV		 4165 err = ixgbe_init_interrupt_scheme(adapter);
4166 if (err)
4167 goto err_sw_init;
9a799d71
AK		 4168
4169 /* print bus type/speed/width info */
4170 pci_read_config_word(pdev, IXGBE_PCI_LINK_STATUS, &link_status);
4171 link_speed = link_status & IXGBE_PCI_LINK_SPEED;
4172 link_width = link_status & IXGBE_PCI_LINK_WIDTH;
7c510e4b 4173 dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
b4617240
PW		 4174 ((link_speed == IXGBE_PCI_LINK_SPEED_5000) ? "5.0Gb/s" :
4175 (link_speed == IXGBE_PCI_LINK_SPEED_2500) ? "2.5Gb/s" :
4176 "Unknown"),
4177 ((link_width == IXGBE_PCI_LINK_WIDTH_8) ? "Width x8" :
4178 (link_width == IXGBE_PCI_LINK_WIDTH_4) ? "Width x4" :
4179 (link_width == IXGBE_PCI_LINK_WIDTH_2) ? "Width x2" :
4180 (link_width == IXGBE_PCI_LINK_WIDTH_1) ? "Width x1" :
4181 "Unknown"),
7c510e4b 4182 netdev->dev_addr);
c44ade9e 4183 ixgbe_read_pba_num_generic(hw, &part_num);
9a799d71 4184 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
b4617240
PW		 4185 hw->mac.type, hw->phy.type,
4186 (part_num >> 8), (part_num & 0xff));
9a799d71 4187
0c254d86
AK		 4188 if (link_width <= IXGBE_PCI_LINK_WIDTH_4) {
4189 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
b4617240
PW		 4190 "this card is not sufficient for optimal "
4191 "performance.\n");
0c254d86 4192 dev_warn(&pdev->dev, "For optimal performance a x8 "
b4617240 4193 "PCI-Express slot is required.\n");
0c254d86
AK		 4194 }
4195
34b0368c
PWJ		 4196 /* save off EEPROM version number */
4197 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
4198
9a799d71 4199 /* reset the hardware with the new settings */
c44ade9e
JB		 4200 hw->mac.ops.start_hw(hw);
4201
9a799d71 4202 netif_carrier_off(netdev);
9a799d71
AK		 4203
4204 strcpy(netdev->name, "eth%d");
4205 err = register_netdev(netdev);
4206 if (err)
4207 goto err_register;
4208
5dd2d332 4209#ifdef CONFIG_IXGBE_DCA
652f093f 4210 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd
JC		 4211 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
4212 /* always use CB2 mode, difference is masked
4213 * in the CB driver */
4214 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
4215 ixgbe_setup_dca(adapter);
4216 }
4217#endif
9a799d71
AK		 4218
4219 dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
4220 cards_found++;
4221 return 0;
4222
4223err_register:
5eba3699 4224 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4225err_hw_init:
4226err_sw_init:
021230d4 4227 ixgbe_reset_interrupt_capability(adapter);
9a799d71 4228err_eeprom:
c4900be0
DS		 4229 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4230 del_timer_sync(&adapter->sfp_timer);
4231 cancel_work_sync(&adapter->sfp_task);
9a799d71
AK		 4232 iounmap(hw->hw_addr);
4233err_ioremap:
4234 free_netdev(netdev);
4235err_alloc_etherdev:
4236 pci_release_regions(pdev);
4237err_pci_reg:
4238err_dma:
4239 pci_disable_device(pdev);
4240 return err;
4241}
4242
4243/**
4244 * ixgbe_remove - Device Removal Routine
4245 * @pdev: PCI device information struct
4246 *
4247 * ixgbe_remove is called by the PCI subsystem to alert the driver
4248 * that it should release a PCI device. The could be caused by a
4249 * Hot-Plug event, or because the driver is going to be removed from
4250 * memory.
4251 **/
4252static void __devexit ixgbe_remove(struct pci_dev *pdev)
4253{
4254 struct net_device *netdev = pci_get_drvdata(pdev);
4255 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715 4256 int err;
9a799d71
AK		 4257
4258 set_bit(__IXGBE_DOWN, &adapter->state);
c4900be0
DS		 4259 /* clear the module not found bit to make sure the worker won't
4260 * reschedule
4261 */
4262 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
9a799d71
AK		 4263 del_timer_sync(&adapter->watchdog_timer);
4264
c4900be0
DS		 4265 del_timer_sync(&adapter->sfp_timer);
4266 cancel_work_sync(&adapter->watchdog_task);
4267 cancel_work_sync(&adapter->sfp_task);
9a799d71
AK		 4268 flush_scheduled_work();
4269
5dd2d332 4270#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 4271 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
4272 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
4273 dca_remove_requester(&pdev->dev);
4274 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
4275 }
4276
4277#endif
c4900be0
DS		 4278 if (netdev->reg_state == NETREG_REGISTERED)
4279 unregister_netdev(netdev);
9a799d71 4280
021230d4 4281 ixgbe_reset_interrupt_capability(adapter);
5eba3699 4282
021230d4 4283 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4284
4285 iounmap(adapter->hw.hw_addr);
4286 pci_release_regions(pdev);
4287
021230d4
AV		 4288 DPRINTK(PROBE, INFO, "complete\n");
4289 kfree(adapter->tx_ring);
4290 kfree(adapter->rx_ring);
4291
9a799d71
AK		 4292 free_netdev(netdev);
4293
6fabd715
PWJ		 4294 err = pci_disable_pcie_error_reporting(pdev);
4295 if (err)
4296 dev_err(&pdev->dev,
4297 "pci_disable_pcie_error_reporting failed 0x%x\n", err);
4298
9a799d71
AK		 4299 pci_disable_device(pdev);
4300}
4301
4302/**
4303 * ixgbe_io_error_detected - called when PCI error is detected
4304 * @pdev: Pointer to PCI device
4305 * @state: The current pci connection state
4306 *
4307 * This function is called after a PCI bus error affecting
4308 * this device has been detected.
4309 */
4310static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
b4617240 4311 pci_channel_state_t state)
9a799d71
AK		 4312{
4313 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 4314 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 4315
4316 netif_device_detach(netdev);
4317
4318 if (netif_running(netdev))
4319 ixgbe_down(adapter);
4320 pci_disable_device(pdev);
4321
b4617240 4322 /* Request a slot reset. */
9a799d71
AK		 4323 return PCI_ERS_RESULT_NEED_RESET;
4324}
4325
4326/**
4327 * ixgbe_io_slot_reset - called after the pci bus has been reset.
4328 * @pdev: Pointer to PCI device
4329 *
4330 * Restart the card from scratch, as if from a cold-boot.
4331 */
4332static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
4333{
4334 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 4335 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715
PWJ		 4336 pci_ers_result_t result;
4337 int err;
9a799d71
AK		 4338
4339 if (pci_enable_device(pdev)) {
4340 DPRINTK(PROBE, ERR,
b4617240 4341 "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 4342 result = PCI_ERS_RESULT_DISCONNECT;
4343 } else {
4344 pci_set_master(pdev);
4345 pci_restore_state(pdev);
9a799d71 4346
6fabd715
PWJ		 4347 pci_enable_wake(pdev, PCI_D3hot, 0);
4348 pci_enable_wake(pdev, PCI_D3cold, 0);
9a799d71 4349
6fabd715
PWJ		 4350 ixgbe_reset(adapter);
4351
4352 result = PCI_ERS_RESULT_RECOVERED;
4353 }
4354
4355 err = pci_cleanup_aer_uncorrect_error_status(pdev);
4356 if (err) {
4357 dev_err(&pdev->dev,
4358 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
4359 /* non-fatal, continue */
4360 }
9a799d71 4361
6fabd715 4362 return result;
9a799d71
AK		 4363}
4364
4365/**
4366 * ixgbe_io_resume - called when traffic can start flowing again.
4367 * @pdev: Pointer to PCI device
4368 *
4369 * This callback is called when the error recovery driver tells us that
4370 * its OK to resume normal operation.
4371 */
4372static void ixgbe_io_resume(struct pci_dev *pdev)
4373{
4374 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 4375 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 4376
4377 if (netif_running(netdev)) {
4378 if (ixgbe_up(adapter)) {
4379 DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
4380 return;
4381 }
4382 }
4383
4384 netif_device_attach(netdev);
9a799d71
AK		 4385}
4386
4387static struct pci_error_handlers ixgbe_err_handler = {
4388 .error_detected = ixgbe_io_error_detected,
4389 .slot_reset = ixgbe_io_slot_reset,
4390 .resume = ixgbe_io_resume,
4391};
4392
4393static struct pci_driver ixgbe_driver = {
4394 .name = ixgbe_driver_name,
4395 .id_table = ixgbe_pci_tbl,
4396 .probe = ixgbe_probe,
4397 .remove = __devexit_p(ixgbe_remove),
4398#ifdef CONFIG_PM
4399 .suspend = ixgbe_suspend,
4400 .resume = ixgbe_resume,
4401#endif
4402 .shutdown = ixgbe_shutdown,
4403 .err_handler = &ixgbe_err_handler
4404};
4405
4406/**
4407 * ixgbe_init_module - Driver Registration Routine
4408 *
4409 * ixgbe_init_module is the first routine called when the driver is
4410 * loaded. All it does is register with the PCI subsystem.
4411 **/
4412static int __init ixgbe_init_module(void)
4413{
4414 int ret;
4415 printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
4416 ixgbe_driver_string, ixgbe_driver_version);
4417
4418 printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
4419
5dd2d332 4420#ifdef CONFIG_IXGBE_DCA
bd0362dd 4421 dca_register_notify(&dca_notifier);
bd0362dd 4422#endif
5dd2d332 4423
9a799d71
AK		 4424 ret = pci_register_driver(&ixgbe_driver);
4425 return ret;
4426}
b4617240 4427
9a799d71
AK		 4428module_init(ixgbe_init_module);
4429
4430/**
4431 * ixgbe_exit_module - Driver Exit Cleanup Routine
4432 *
4433 * ixgbe_exit_module is called just before the driver is removed
4434 * from memory.
4435 **/
4436static void __exit ixgbe_exit_module(void)
4437{
5dd2d332 4438#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 4439 dca_unregister_notify(&dca_notifier);
4440#endif
9a799d71
AK		 4441 pci_unregister_driver(&ixgbe_driver);
4442}
bd0362dd 4443
5dd2d332 4444#ifdef CONFIG_IXGBE_DCA
bd0362dd 4445static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
b4617240 4446 void *p)
bd0362dd
JC		 4447{
4448 int ret_val;
4449
4450 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
b4617240 4451 __ixgbe_notify_dca);
bd0362dd
JC		 4452
4453 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
4454}
5dd2d332 4455#endif /* CONFIG_IXGBE_DCA */
bd0362dd 4456
9a799d71
AK		 4457module_exit(ixgbe_exit_module);
4458
4459/* ixgbe_main.c */
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