]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - drivers/net/ixgbe/ixgbe_main.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ixgbe: pull all Tx init into ixgbe_configure_tx
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
8c47eaa7 4 Copyright(c) 1999 - 2010 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
60127865 37#include <linux/pkt_sched.h>
9a799d71 38#include <linux/ipv6.h>
5a0e3ad6 39#include <linux/slab.h>
9a799d71
AK		 40#include <net/checksum.h>
41#include <net/ip6_checksum.h>
42#include <linux/ethtool.h>
43#include <linux/if_vlan.h>
eacd73f7 44#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 45
46#include "ixgbe.h"
47#include "ixgbe_common.h"
ee5f784a 48#include "ixgbe_dcb_82599.h"
1cdd1ec8 49#include "ixgbe_sriov.h"
9a799d71
AK		 50
51char ixgbe_driver_name[] = "ixgbe";
9c8eb720 52static const char ixgbe_driver_string[] =
b4617240 53 "Intel(R) 10 Gigabit PCI Express Network Driver";
9a799d71 54
99faf68e 55#define DRV_VERSION "2.0.84-k2"
9c8eb720 56const char ixgbe_driver_version[] = DRV_VERSION;
8c47eaa7 57static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
9a799d71
AK		 58
59static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 60 [board_82598] = &ixgbe_82598_info,
e8e26350 61 [board_82599] = &ixgbe_82599_info,
9a799d71
AK		 62};
63
64/* ixgbe_pci_tbl - PCI Device ID Table
65 *
66 * Wildcard entries (PCI_ANY_ID) should come last
67 * Last entry must be all 0s
68 *
69 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
70 * Class, Class Mask, private data (not used) }
71 */
a3aa1884 72static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
1e336d0f
DS		 73 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
74 board_82598 },
9a799d71 75 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 76 board_82598 },
9a799d71 77 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 78 board_82598 },
0befdb3e
JB		 79 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
80 board_82598 },
3845bec0
PWJ		 81 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
82 board_82598 },
9a799d71 83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 84 board_82598 },
8d792cd9
JB		 85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
86 board_82598 },
c4900be0
DS		 87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
88 board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
90 board_82598 },
b95f5fcb
JB		 91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
92 board_82598 },
c4900be0
DS		 93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
94 board_82598 },
2f21bdd3
DS		 95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
96 board_82598 },
e8e26350
PW		 97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
98 board_82599 },
1fcf03e6
PWJ		 99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
100 board_82599 },
74757d49
DS		 101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
102 board_82599 },
e8e26350
PW		 103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
104 board_82599 },
38ad1c8e
DS		 105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
106 board_82599 },
dbfec662
DS		 107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
108 board_82599 },
8911184f
PWJ		 109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
110 board_82599 },
119fc60a
MC		 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
112 board_82599 },
312eb931
DS		 113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
114 board_82599 },
9a799d71
AK		 115
116 /* required last entry */
117 {0, }
118};
119MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
120
5dd2d332 121#ifdef CONFIG_IXGBE_DCA
bd0362dd 122static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
b4617240 123 void *p);
bd0362dd
JC		 124static struct notifier_block dca_notifier = {
125 .notifier_call = ixgbe_notify_dca,
126 .next = NULL,
127 .priority = 0
128};
129#endif
130
1cdd1ec8
GR		 131#ifdef CONFIG_PCI_IOV
132static unsigned int max_vfs;
133module_param(max_vfs, uint, 0);
134MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
135 "per physical function");
136#endif /* CONFIG_PCI_IOV */
137
9a799d71
AK		 138MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
139MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
140MODULE_LICENSE("GPL");
141MODULE_VERSION(DRV_VERSION);
142
143#define DEFAULT_DEBUG_LEVEL_SHIFT 3
144
1cdd1ec8
GR		 145static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
146{
147 struct ixgbe_hw *hw = &adapter->hw;
148 u32 gcr;
149 u32 gpie;
150 u32 vmdctl;
151
152#ifdef CONFIG_PCI_IOV
153 /* disable iov and allow time for transactions to clear */
154 pci_disable_sriov(adapter->pdev);
155#endif
156
157 /* turn off device IOV mode */
158 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
159 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
160 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
161 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
162 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
163 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
164
165 /* set default pool back to 0 */
166 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
167 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
168 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
169
170 /* take a breather then clean up driver data */
171 msleep(100);
172 if (adapter->vfinfo)
173 kfree(adapter->vfinfo);
174 adapter->vfinfo = NULL;
175
176 adapter->num_vfs = 0;
177 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
178}
179
dcd79aeb
TI		 180struct ixgbe_reg_info {
181 u32 ofs;
182 char *name;
183};
184
185static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
186
187 /* General Registers */
188 {IXGBE_CTRL, "CTRL"},
189 {IXGBE_STATUS, "STATUS"},
190 {IXGBE_CTRL_EXT, "CTRL_EXT"},
191
192 /* Interrupt Registers */
193 {IXGBE_EICR, "EICR"},
194
195 /* RX Registers */
196 {IXGBE_SRRCTL(0), "SRRCTL"},
197 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
198 {IXGBE_RDLEN(0), "RDLEN"},
199 {IXGBE_RDH(0), "RDH"},
200 {IXGBE_RDT(0), "RDT"},
201 {IXGBE_RXDCTL(0), "RXDCTL"},
202 {IXGBE_RDBAL(0), "RDBAL"},
203 {IXGBE_RDBAH(0), "RDBAH"},
204
205 /* TX Registers */
206 {IXGBE_TDBAL(0), "TDBAL"},
207 {IXGBE_TDBAH(0), "TDBAH"},
208 {IXGBE_TDLEN(0), "TDLEN"},
209 {IXGBE_TDH(0), "TDH"},
210 {IXGBE_TDT(0), "TDT"},
211 {IXGBE_TXDCTL(0), "TXDCTL"},
212
213 /* List Terminator */
214 {}
215};
216
217
218/*
219 * ixgbe_regdump - register printout routine
220 */
221static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
222{
223 int i = 0, j = 0;
224 char rname[16];
225 u32 regs[64];
226
227 switch (reginfo->ofs) {
228 case IXGBE_SRRCTL(0):
229 for (i = 0; i < 64; i++)
230 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
231 break;
232 case IXGBE_DCA_RXCTRL(0):
233 for (i = 0; i < 64; i++)
234 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
235 break;
236 case IXGBE_RDLEN(0):
237 for (i = 0; i < 64; i++)
238 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
239 break;
240 case IXGBE_RDH(0):
241 for (i = 0; i < 64; i++)
242 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
243 break;
244 case IXGBE_RDT(0):
245 for (i = 0; i < 64; i++)
246 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
247 break;
248 case IXGBE_RXDCTL(0):
249 for (i = 0; i < 64; i++)
250 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
251 break;
252 case IXGBE_RDBAL(0):
253 for (i = 0; i < 64; i++)
254 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
255 break;
256 case IXGBE_RDBAH(0):
257 for (i = 0; i < 64; i++)
258 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
259 break;
260 case IXGBE_TDBAL(0):
261 for (i = 0; i < 64; i++)
262 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
263 break;
264 case IXGBE_TDBAH(0):
265 for (i = 0; i < 64; i++)
266 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
267 break;
268 case IXGBE_TDLEN(0):
269 for (i = 0; i < 64; i++)
270 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
271 break;
272 case IXGBE_TDH(0):
273 for (i = 0; i < 64; i++)
274 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
275 break;
276 case IXGBE_TDT(0):
277 for (i = 0; i < 64; i++)
278 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
279 break;
280 case IXGBE_TXDCTL(0):
281 for (i = 0; i < 64; i++)
282 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
283 break;
284 default:
285 printk(KERN_INFO "%-15s %08x\n", reginfo->name,
286 IXGBE_READ_REG(hw, reginfo->ofs));
287 return;
288 }
289
290 for (i = 0; i < 8; i++) {
291 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
292 printk(KERN_ERR "%-15s ", rname);
293 for (j = 0; j < 8; j++)
294 printk(KERN_CONT "%08x ", regs[i*8+j]);
295 printk(KERN_CONT "\n");
296 }
297
298}
299
300/*
301 * ixgbe_dump - Print registers, tx-rings and rx-rings
302 */
303static void ixgbe_dump(struct ixgbe_adapter *adapter)
304{
305 struct net_device *netdev = adapter->netdev;
306 struct ixgbe_hw *hw = &adapter->hw;
307 struct ixgbe_reg_info *reginfo;
308 int n = 0;
309 struct ixgbe_ring *tx_ring;
310 struct ixgbe_tx_buffer *tx_buffer_info;
311 union ixgbe_adv_tx_desc *tx_desc;
312 struct my_u0 { u64 a; u64 b; } *u0;
313 struct ixgbe_ring *rx_ring;
314 union ixgbe_adv_rx_desc *rx_desc;
315 struct ixgbe_rx_buffer *rx_buffer_info;
316 u32 staterr;
317 int i = 0;
318
319 if (!netif_msg_hw(adapter))
320 return;
321
322 /* Print netdevice Info */
323 if (netdev) {
324 dev_info(&adapter->pdev->dev, "Net device Info\n");
325 printk(KERN_INFO "Device Name state "
326 "trans_start last_rx\n");
327 printk(KERN_INFO "%-15s %016lX %016lX %016lX\n",
328 netdev->name,
329 netdev->state,
330 netdev->trans_start,
331 netdev->last_rx);
332 }
333
334 /* Print Registers */
335 dev_info(&adapter->pdev->dev, "Register Dump\n");
336 printk(KERN_INFO " Register Name Value\n");
337 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
338 reginfo->name; reginfo++) {
339 ixgbe_regdump(hw, reginfo);
340 }
341
342 /* Print TX Ring Summary */
343 if (!netdev || !netif_running(netdev))
344 goto exit;
345
346 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
347 printk(KERN_INFO "Queue [NTU] [NTC] [bi(ntc)->dma ] "
348 "leng ntw timestamp\n");
349 for (n = 0; n < adapter->num_tx_queues; n++) {
350 tx_ring = adapter->tx_ring[n];
351 tx_buffer_info =
352 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
353 printk(KERN_INFO " %5d %5X %5X %016llX %04X %3X %016llX\n",
354 n, tx_ring->next_to_use, tx_ring->next_to_clean,
355 (u64)tx_buffer_info->dma,
356 tx_buffer_info->length,
357 tx_buffer_info->next_to_watch,
358 (u64)tx_buffer_info->time_stamp);
359 }
360
361 /* Print TX Rings */
362 if (!netif_msg_tx_done(adapter))
363 goto rx_ring_summary;
364
365 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
366
367 /* Transmit Descriptor Formats
368 *
369 * Advanced Transmit Descriptor
370 * +--------------------------------------------------------------+
371 * 0 | Buffer Address [63:0] |
372 * +--------------------------------------------------------------+
373 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
374 * +--------------------------------------------------------------+
375 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
376 */
377
378 for (n = 0; n < adapter->num_tx_queues; n++) {
379 tx_ring = adapter->tx_ring[n];
380 printk(KERN_INFO "------------------------------------\n");
381 printk(KERN_INFO "TX QUEUE INDEX = %d\n", tx_ring->queue_index);
382 printk(KERN_INFO "------------------------------------\n");
383 printk(KERN_INFO "T [desc] [address 63:0 ] "
384 "[PlPOIdStDDt Ln] [bi->dma ] "
385 "leng ntw timestamp bi->skb\n");
386
387 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
388 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
389 tx_buffer_info = &tx_ring->tx_buffer_info[i];
390 u0 = (struct my_u0 *)tx_desc;
391 printk(KERN_INFO "T [0x%03X] %016llX %016llX %016llX"
392 " %04X %3X %016llX %p", i,
393 le64_to_cpu(u0->a),
394 le64_to_cpu(u0->b),
395 (u64)tx_buffer_info->dma,
396 tx_buffer_info->length,
397 tx_buffer_info->next_to_watch,
398 (u64)tx_buffer_info->time_stamp,
399 tx_buffer_info->skb);
400 if (i == tx_ring->next_to_use &&
401 i == tx_ring->next_to_clean)
402 printk(KERN_CONT " NTC/U\n");
403 else if (i == tx_ring->next_to_use)
404 printk(KERN_CONT " NTU\n");
405 else if (i == tx_ring->next_to_clean)
406 printk(KERN_CONT " NTC\n");
407 else
408 printk(KERN_CONT "\n");
409
410 if (netif_msg_pktdata(adapter) &&
411 tx_buffer_info->dma != 0)
412 print_hex_dump(KERN_INFO, "",
413 DUMP_PREFIX_ADDRESS, 16, 1,
414 phys_to_virt(tx_buffer_info->dma),
415 tx_buffer_info->length, true);
416 }
417 }
418
419 /* Print RX Rings Summary */
420rx_ring_summary:
421 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
422 printk(KERN_INFO "Queue [NTU] [NTC]\n");
423 for (n = 0; n < adapter->num_rx_queues; n++) {
424 rx_ring = adapter->rx_ring[n];
425 printk(KERN_INFO "%5d %5X %5X\n", n,
426 rx_ring->next_to_use, rx_ring->next_to_clean);
427 }
428
429 /* Print RX Rings */
430 if (!netif_msg_rx_status(adapter))
431 goto exit;
432
433 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
434
435 /* Advanced Receive Descriptor (Read) Format
436 * 63 1 0
437 * +-----------------------------------------------------+
438 * 0 | Packet Buffer Address [63:1] |A0/NSE|
439 * +----------------------------------------------+------+
440 * 8 | Header Buffer Address [63:1] | DD |
441 * +-----------------------------------------------------+
442 *
443 *
444 * Advanced Receive Descriptor (Write-Back) Format
445 *
446 * 63 48 47 32 31 30 21 20 16 15 4 3 0
447 * +------------------------------------------------------+
448 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
449 * | Checksum Ident | | | | Type | Type |
450 * +------------------------------------------------------+
451 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
452 * +------------------------------------------------------+
453 * 63 48 47 32 31 20 19 0
454 */
455 for (n = 0; n < adapter->num_rx_queues; n++) {
456 rx_ring = adapter->rx_ring[n];
457 printk(KERN_INFO "------------------------------------\n");
458 printk(KERN_INFO "RX QUEUE INDEX = %d\n", rx_ring->queue_index);
459 printk(KERN_INFO "------------------------------------\n");
460 printk(KERN_INFO "R [desc] [ PktBuf A0] "
461 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
462 "<-- Adv Rx Read format\n");
463 printk(KERN_INFO "RWB[desc] [PcsmIpSHl PtRs] "
464 "[vl er S cks ln] ---------------- [bi->skb] "
465 "<-- Adv Rx Write-Back format\n");
466
467 for (i = 0; i < rx_ring->count; i++) {
468 rx_buffer_info = &rx_ring->rx_buffer_info[i];
469 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
470 u0 = (struct my_u0 *)rx_desc;
471 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
472 if (staterr & IXGBE_RXD_STAT_DD) {
473 /* Descriptor Done */
474 printk(KERN_INFO "RWB[0x%03X] %016llX "
475 "%016llX ---------------- %p", i,
476 le64_to_cpu(u0->a),
477 le64_to_cpu(u0->b),
478 rx_buffer_info->skb);
479 } else {
480 printk(KERN_INFO "R [0x%03X] %016llX "
481 "%016llX %016llX %p", i,
482 le64_to_cpu(u0->a),
483 le64_to_cpu(u0->b),
484 (u64)rx_buffer_info->dma,
485 rx_buffer_info->skb);
486
487 if (netif_msg_pktdata(adapter)) {
488 print_hex_dump(KERN_INFO, "",
489 DUMP_PREFIX_ADDRESS, 16, 1,
490 phys_to_virt(rx_buffer_info->dma),
491 rx_ring->rx_buf_len, true);
492
493 if (rx_ring->rx_buf_len
494 < IXGBE_RXBUFFER_2048)
495 print_hex_dump(KERN_INFO, "",
496 DUMP_PREFIX_ADDRESS, 16, 1,
497 phys_to_virt(
498 rx_buffer_info->page_dma +
499 rx_buffer_info->page_offset
500 ),
501 PAGE_SIZE/2, true);
502 }
503 }
504
505 if (i == rx_ring->next_to_use)
506 printk(KERN_CONT " NTU\n");
507 else if (i == rx_ring->next_to_clean)
508 printk(KERN_CONT " NTC\n");
509 else
510 printk(KERN_CONT "\n");
511
512 }
513 }
514
515exit:
516 return;
517}
518
5eba3699
AV		 519static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
520{
521 u32 ctrl_ext;
522
523 /* Let firmware take over control of h/w */
524 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
525 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 526 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 527}
528
529static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
530{
531 u32 ctrl_ext;
532
533 /* Let firmware know the driver has taken over */
534 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
535 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 536 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 537}
9a799d71 538
e8e26350
PW		 539/*
540 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
541 * @adapter: pointer to adapter struct
542 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
543 * @queue: queue to map the corresponding interrupt to
544 * @msix_vector: the vector to map to the corresponding queue
545 *
546 */
547static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
548 u8 queue, u8 msix_vector)
9a799d71
AK		 549{
550 u32 ivar, index;
e8e26350
PW		 551 struct ixgbe_hw *hw = &adapter->hw;
552 switch (hw->mac.type) {
553 case ixgbe_mac_82598EB:
554 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
555 if (direction == -1)
556 direction = 0;
557 index = (((direction * 64) + queue) >> 2) & 0x1F;
558 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
559 ivar &= ~(0xFF << (8 * (queue & 0x3)));
560 ivar |= (msix_vector << (8 * (queue & 0x3)));
561 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
562 break;
563 case ixgbe_mac_82599EB:
564 if (direction == -1) {
565 /* other causes */
566 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
567 index = ((queue & 1) * 8);
568 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
569 ivar &= ~(0xFF << index);
570 ivar |= (msix_vector << index);
571 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
572 break;
573 } else {
574 /* tx or rx causes */
575 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
576 index = ((16 * (queue & 1)) + (8 * direction));
577 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
578 ivar &= ~(0xFF << index);
579 ivar |= (msix_vector << index);
580 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
581 break;
582 }
583 default:
584 break;
585 }
9a799d71
AK		 586}
587
fe49f04a
AD		 588static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
589 u64 qmask)
590{
591 u32 mask;
592
593 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
594 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
595 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
596 } else {
597 mask = (qmask & 0xFFFFFFFF);
598 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
599 mask = (qmask >> 32);
600 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
601 }
602}
603
9a799d71 604static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
b4617240
PW		 605 struct ixgbe_tx_buffer
606 *tx_buffer_info)
9a799d71 607{
e5a43549
AD		 608 if (tx_buffer_info->dma) {
609 if (tx_buffer_info->mapped_as_page)
1b507730 610 dma_unmap_page(&adapter->pdev->dev,
e5a43549
AD		 611 tx_buffer_info->dma,
612 tx_buffer_info->length,
1b507730 613 DMA_TO_DEVICE);
e5a43549 614 else
1b507730 615 dma_unmap_single(&adapter->pdev->dev,
e5a43549
AD		 616 tx_buffer_info->dma,
617 tx_buffer_info->length,
1b507730 618 DMA_TO_DEVICE);
e5a43549
AD		 619 tx_buffer_info->dma = 0;
620 }
9a799d71
AK		 621 if (tx_buffer_info->skb) {
622 dev_kfree_skb_any(tx_buffer_info->skb);
623 tx_buffer_info->skb = NULL;
624 }
44df32c5 625 tx_buffer_info->time_stamp = 0;
9a799d71
AK		 626 /* tx_buffer_info must be completely set up in the transmit path */
627}
628
26f23d82 629/**
7483d9dd 630 * ixgbe_tx_xon_state - check the tx ring xon state
26f23d82
YZ		 631 * @adapter: the ixgbe adapter
632 * @tx_ring: the corresponding tx_ring
633 *
634 * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
635 * corresponding TC of this tx_ring when checking TFCS.
636 *
7483d9dd 637 * Returns : true if in xon state (currently not paused)
26f23d82 638 */
7483d9dd 639static inline bool ixgbe_tx_xon_state(struct ixgbe_adapter *adapter,
26f23d82
YZ		 640 struct ixgbe_ring *tx_ring)
641{
26f23d82
YZ		 642 u32 txoff = IXGBE_TFCS_TXOFF;
643
644#ifdef CONFIG_IXGBE_DCB
ca739481 645 if (adapter->dcb_cfg.pfc_mode_enable) {
30b76832 646 int tc;
26f23d82
YZ		 647 int reg_idx = tx_ring->reg_idx;
648 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
649
6837e895
PW		 650 switch (adapter->hw.mac.type) {
651 case ixgbe_mac_82598EB:
26f23d82
YZ		 652 tc = reg_idx >> 2;
653 txoff = IXGBE_TFCS_TXOFF0;
6837e895
PW		 654 break;
655 case ixgbe_mac_82599EB:
26f23d82
YZ		 656 tc = 0;
657 txoff = IXGBE_TFCS_TXOFF;
658 if (dcb_i == 8) {
659 /* TC0, TC1 */
660 tc = reg_idx >> 5;
661 if (tc == 2) /* TC2, TC3 */
662 tc += (reg_idx - 64) >> 4;
663 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
664 tc += 1 + ((reg_idx - 96) >> 3);
665 } else if (dcb_i == 4) {
666 /* TC0, TC1 */
667 tc = reg_idx >> 6;
668 if (tc == 1) {
669 tc += (reg_idx - 64) >> 5;
670 if (tc == 2) /* TC2, TC3 */
671 tc += (reg_idx - 96) >> 4;
672 }
673 }
6837e895
PW		 674 break;
675 default:
676 tc = 0;
26f23d82
YZ		 677 }
678 txoff <<= tc;
679 }
680#endif
681 return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
682}
683
9a799d71 684static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
b4617240
PW		 685 struct ixgbe_ring *tx_ring,
686 unsigned int eop)
9a799d71 687{
e01c31a5 688 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 689
9a799d71 690 /* Detect a transmit hang in hardware, this serializes the
e01c31a5 691 * check with the clearing of time_stamp and movement of eop */
9a799d71 692 adapter->detect_tx_hung = false;
44df32c5 693 if (tx_ring->tx_buffer_info[eop].time_stamp &&
9a799d71 694 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
7483d9dd 695 ixgbe_tx_xon_state(adapter, tx_ring)) {
9a799d71 696 /* detected Tx unit hang */
e01c31a5
JB		 697 union ixgbe_adv_tx_desc *tx_desc;
698 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
396e799c 699 e_err(drv, "Detected Tx Unit Hang\n"
849c4542
ET		 700 " Tx Queue <%d>\n"
701 " TDH, TDT <%x>, <%x>\n"
702 " next_to_use <%x>\n"
703 " next_to_clean <%x>\n"
704 "tx_buffer_info[next_to_clean]\n"
705 " time_stamp <%lx>\n"
706 " jiffies <%lx>\n",
707 tx_ring->queue_index,
708 IXGBE_READ_REG(hw, tx_ring->head),
709 IXGBE_READ_REG(hw, tx_ring->tail),
710 tx_ring->next_to_use, eop,
711 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
9a799d71
AK		 712 return true;
713 }
714
715 return false;
716}
717
b4617240
PW		 718#define IXGBE_MAX_TXD_PWR 14
719#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
e092be60
AV		 720
721/* Tx Descriptors needed, worst case */
722#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
723 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
724#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
b4617240 725 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
e092be60 726
e01c31a5
JB		 727static void ixgbe_tx_timeout(struct net_device *netdev);
728
9a799d71
AK		 729/**
730 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 731 * @q_vector: structure containing interrupt and ring information
e01c31a5 732 * @tx_ring: tx ring to clean
9a799d71 733 **/
fe49f04a 734static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e01c31a5 735 struct ixgbe_ring *tx_ring)
9a799d71 736{
fe49f04a 737 struct ixgbe_adapter *adapter = q_vector->adapter;
e01c31a5 738 struct net_device *netdev = adapter->netdev;
12207e49
PWJ		 739 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
740 struct ixgbe_tx_buffer *tx_buffer_info;
741 unsigned int i, eop, count = 0;
e01c31a5 742 unsigned int total_bytes = 0, total_packets = 0;
9a799d71
AK		 743
744 i = tx_ring->next_to_clean;
12207e49
PWJ		 745 eop = tx_ring->tx_buffer_info[i].next_to_watch;
746 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
747
748 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
9a1a69ad 749 (count < tx_ring->work_limit)) {
12207e49 750 bool cleaned = false;
2d0bb1c1 751 rmb(); /* read buffer_info after eop_desc */
12207e49
PWJ		 752 for ( ; !cleaned; count++) {
753 struct sk_buff *skb;
9a799d71
AK		 754 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
755 tx_buffer_info = &tx_ring->tx_buffer_info[i];
12207e49 756 cleaned = (i == eop);
e01c31a5 757 skb = tx_buffer_info->skb;
9a799d71 758
12207e49 759 if (cleaned && skb) {
e092be60 760 unsigned int segs, bytecount;
3d8fd385 761 unsigned int hlen = skb_headlen(skb);
e01c31a5
JB		 762
763 /* gso_segs is currently only valid for tcp */
e092be60 764 segs = skb_shinfo(skb)->gso_segs ?: 1;
3d8fd385
YZ		 765#ifdef IXGBE_FCOE
766 /* adjust for FCoE Sequence Offload */
767 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
768 && (skb->protocol == htons(ETH_P_FCOE)) &&
769 skb_is_gso(skb)) {
770 hlen = skb_transport_offset(skb) +
771 sizeof(struct fc_frame_header) +
772 sizeof(struct fcoe_crc_eof);
773 segs = DIV_ROUND_UP(skb->len - hlen,
774 skb_shinfo(skb)->gso_size);
775 }
776#endif /* IXGBE_FCOE */
e092be60 777 /* multiply data chunks by size of headers */
3d8fd385 778 bytecount = ((segs - 1) * hlen) + skb->len;
e01c31a5
JB		 779 total_packets += segs;
780 total_bytes += bytecount;
e092be60 781 }
e01c31a5 782
9a799d71 783 ixgbe_unmap_and_free_tx_resource(adapter,
e01c31a5 784 tx_buffer_info);
9a799d71 785
12207e49
PWJ		 786 tx_desc->wb.status = 0;
787
9a799d71
AK		 788 i++;
789 if (i == tx_ring->count)
790 i = 0;
e01c31a5 791 }
12207e49
PWJ		 792
793 eop = tx_ring->tx_buffer_info[i].next_to_watch;
794 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
795 }
796
9a799d71
AK		 797 tx_ring->next_to_clean = i;
798
e092be60 799#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
e01c31a5
JB		 800 if (unlikely(count && netif_carrier_ok(netdev) &&
801 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 802 /* Make sure that anybody stopping the queue after this
803 * sees the new next_to_clean.
804 */
805 smp_mb();
30eba97a
AV		 806 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
807 !test_bit(__IXGBE_DOWN, &adapter->state)) {
808 netif_wake_subqueue(netdev, tx_ring->queue_index);
7ca3bc58 809 ++tx_ring->restart_queue;
30eba97a 810 }
e092be60 811 }
9a799d71 812
e01c31a5
JB		 813 if (adapter->detect_tx_hung) {
814 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
815 /* schedule immediate reset if we believe we hung */
396e799c
ET		 816 e_info(probe, "tx hang %d detected, resetting "
817 "adapter\n", adapter->tx_timeout_count + 1);
e01c31a5
JB		 818 ixgbe_tx_timeout(adapter->netdev);
819 }
820 }
9a799d71 821
e01c31a5 822 /* re-arm the interrupt */
fe49f04a
AD		 823 if (count >= tx_ring->work_limit)
824 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
9a799d71 825
e01c31a5
JB		 826 tx_ring->total_bytes += total_bytes;
827 tx_ring->total_packets += total_packets;
e01c31a5 828 tx_ring->stats.packets += total_packets;
12207e49 829 tx_ring->stats.bytes += total_bytes;
9a1a69ad 830 return (count < tx_ring->work_limit);
9a799d71
AK		 831}
832
5dd2d332 833#ifdef CONFIG_IXGBE_DCA
bd0362dd 834static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
b4617240 835 struct ixgbe_ring *rx_ring)
bd0362dd
JC		 836{
837 u32 rxctrl;
838 int cpu = get_cpu();
4a0b9ca0 839 int q = rx_ring->reg_idx;
bd0362dd 840
3a581073 841 if (rx_ring->cpu != cpu) {
bd0362dd 842 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
e8e26350
PW		 843 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
844 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
845 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
846 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
847 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
848 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
849 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
850 }
bd0362dd
JC		 851 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
852 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
15005a32
DS		 853 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
854 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
e8e26350 855 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
bd0362dd 856 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
3a581073 857 rx_ring->cpu = cpu;
bd0362dd
JC		 858 }
859 put_cpu();
860}
861
862static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
b4617240 863 struct ixgbe_ring *tx_ring)
bd0362dd
JC		 864{
865 u32 txctrl;
866 int cpu = get_cpu();
4a0b9ca0 867 int q = tx_ring->reg_idx;
ee5f784a 868 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 869
3a581073 870 if (tx_ring->cpu != cpu) {
e8e26350 871 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
ee5f784a 872 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q));
e8e26350
PW		 873 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
874 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
ee5f784a
DS		 875 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
876 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl);
e8e26350 877 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
ee5f784a 878 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q));
e8e26350
PW		 879 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
880 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
ee5f784a
DS		 881 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
882 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
883 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl);
e8e26350 884 }
3a581073 885 tx_ring->cpu = cpu;
bd0362dd
JC		 886 }
887 put_cpu();
888}
889
890static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
891{
892 int i;
893
894 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
895 return;
896
e35ec126
AD		 897 /* always use CB2 mode, difference is masked in the CB driver */
898 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
899
bd0362dd 900 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0
PW		 901 adapter->tx_ring[i]->cpu = -1;
902 ixgbe_update_tx_dca(adapter, adapter->tx_ring[i]);
bd0362dd
JC		 903 }
904 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 905 adapter->rx_ring[i]->cpu = -1;
906 ixgbe_update_rx_dca(adapter, adapter->rx_ring[i]);
bd0362dd
JC		 907 }
908}
909
910static int __ixgbe_notify_dca(struct device *dev, void *data)
911{
912 struct net_device *netdev = dev_get_drvdata(dev);
913 struct ixgbe_adapter *adapter = netdev_priv(netdev);
914 unsigned long event = *(unsigned long *)data;
915
916 switch (event) {
917 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 918 /* if we're already enabled, don't do it again */
919 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
920 break;
652f093f 921 if (dca_add_requester(dev) == 0) {
96b0e0f6 922 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 923 ixgbe_setup_dca(adapter);
924 break;
925 }
926 /* Fall Through since DCA is disabled. */
927 case DCA_PROVIDER_REMOVE:
928 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
929 dca_remove_requester(dev);
930 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
931 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
932 }
933 break;
934 }
935
652f093f 936 return 0;
bd0362dd
JC		 937}
938
5dd2d332 939#endif /* CONFIG_IXGBE_DCA */
9a799d71
AK		 940/**
941 * ixgbe_receive_skb - Send a completed packet up the stack
942 * @adapter: board private structure
943 * @skb: packet to send up
177db6ff
MC		 944 * @status: hardware indication of status of receive
945 * @rx_ring: rx descriptor ring (for a specific queue) to setup
946 * @rx_desc: rx descriptor
9a799d71 947 **/
78b6f4ce 948static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
b4617240 949 struct sk_buff *skb, u8 status,
fdaff1ce 950 struct ixgbe_ring *ring,
177db6ff 951 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 952{
78b6f4ce
HX		 953 struct ixgbe_adapter *adapter = q_vector->adapter;
954 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 955 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
956 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 957
182ff8df 958 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
8a62babf 959 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
78b6f4ce 960 vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
9a799d71 961 else
78b6f4ce 962 napi_gro_receive(napi, skb);
177db6ff 963 } else {
8a62babf 964 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
182ff8df
AD		 965 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
966 else
967 netif_rx(skb);
9a799d71
AK		 968 }
969}
970
e59bd25d
AV		 971/**
972 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
973 * @adapter: address of board private structure
974 * @status_err: hardware indication of status of receive
975 * @skb: skb currently being received and modified
976 **/
9a799d71 977static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
8bae1b2b
DS		 978 union ixgbe_adv_rx_desc *rx_desc,
979 struct sk_buff *skb)
9a799d71 980{
8bae1b2b
DS		 981 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
982
9a799d71
AK		 983 skb->ip_summed = CHECKSUM_NONE;
984
712744be
JB		 985 /* Rx csum disabled */
986 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 987 return;
e59bd25d
AV		 988
989 /* if IP and error */
990 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
991 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 992 adapter->hw_csum_rx_error++;
993 return;
994 }
e59bd25d
AV		 995
996 if (!(status_err & IXGBE_RXD_STAT_L4CS))
997 return;
998
999 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
8bae1b2b
DS		 1000 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1001
1002 /*
1003 * 82599 errata, UDP frames with a 0 checksum can be marked as
1004 * checksum errors.
1005 */
1006 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1007 (adapter->hw.mac.type == ixgbe_mac_82599EB))
1008 return;
1009
e59bd25d
AV		 1010 adapter->hw_csum_rx_error++;
1011 return;
1012 }
1013
9a799d71 1014 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1015 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1016}
1017
e8e26350
PW		 1018static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
1019 struct ixgbe_ring *rx_ring, u32 val)
1020{
1021 /*
1022 * Force memory writes to complete before letting h/w
1023 * know there are new descriptors to fetch. (Only
1024 * applicable for weak-ordered memory model archs,
1025 * such as IA-64).
1026 */
1027 wmb();
1028 IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
1029}
1030
9a799d71
AK		 1031/**
1032 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1033 * @adapter: address of board private structure
1034 **/
1035static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
7c6e0a43
JB		 1036 struct ixgbe_ring *rx_ring,
1037 int cleaned_count)
9a799d71 1038{
d716a7d8 1039 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 1040 struct pci_dev *pdev = adapter->pdev;
1041 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1042 struct ixgbe_rx_buffer *bi;
9a799d71 1043 unsigned int i;
d716a7d8 1044 unsigned int bufsz = rx_ring->rx_buf_len;
9a799d71
AK		 1045
1046 i = rx_ring->next_to_use;
3a581073 1047 bi = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 1048
1049 while (cleaned_count--) {
1050 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
1051
762f4c57 1052 if (!bi->page_dma &&
6e455b89 1053 (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
3a581073 1054 if (!bi->page) {
d716a7d8 1055 bi->page = netdev_alloc_page(netdev);
762f4c57
JB		 1056 if (!bi->page) {
1057 adapter->alloc_rx_page_failed++;
1058 goto no_buffers;
1059 }
1060 bi->page_offset = 0;
1061 } else {
1062 /* use a half page if we're re-using */
1063 bi->page_offset ^= (PAGE_SIZE / 2);
9a799d71 1064 }
762f4c57 1065
1b507730 1066 bi->page_dma = dma_map_page(&pdev->dev, bi->page,
762f4c57
JB		 1067 bi->page_offset,
1068 (PAGE_SIZE / 2),
1b507730 1069 DMA_FROM_DEVICE);
9a799d71
AK		 1070 }
1071
3a581073 1072 if (!bi->skb) {
d716a7d8
AD		 1073 struct sk_buff *skb = netdev_alloc_skb_ip_align(netdev,
1074 bufsz);
1075 bi->skb = skb;
9a799d71
AK		 1076
1077 if (!skb) {
1078 adapter->alloc_rx_buff_failed++;
1079 goto no_buffers;
1080 }
d716a7d8
AD		 1081 /* initialize queue mapping */
1082 skb_record_rx_queue(skb, rx_ring->queue_index);
1083 }
9a799d71 1084
d716a7d8
AD		 1085 if (!bi->dma) {
1086 bi->dma = dma_map_single(&pdev->dev,
1087 bi->skb->data,
4f57ca6e 1088 rx_ring->rx_buf_len,
1b507730 1089 DMA_FROM_DEVICE);
9a799d71
AK		 1090 }
1091 /* Refresh the desc even if buffer_addrs didn't change because
1092 * each write-back erases this info. */
6e455b89 1093 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
3a581073
JB		 1094 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1095 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 1096 } else {
3a581073 1097 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
9a799d71
AK		 1098 }
1099
1100 i++;
1101 if (i == rx_ring->count)
1102 i = 0;
3a581073 1103 bi = &rx_ring->rx_buffer_info[i];
9a799d71 1104 }
7c6e0a43 1105
9a799d71
AK		 1106no_buffers:
1107 if (rx_ring->next_to_use != i) {
1108 rx_ring->next_to_use = i;
1109 if (i-- == 0)
1110 i = (rx_ring->count - 1);
1111
e8e26350 1112 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
9a799d71
AK		 1113 }
1114}
1115
7c6e0a43
JB		 1116static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
1117{
1118 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
1119}
1120
1121static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
1122{
1123 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1124}
1125
f8212f97
AD		 1126static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
1127{
1128 return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1129 IXGBE_RXDADV_RSCCNT_MASK) >>
1130 IXGBE_RXDADV_RSCCNT_SHIFT;
1131}
1132
1133/**
1134 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1135 * @skb: pointer to the last skb in the rsc queue
94b982b2 1136 * @count: pointer to number of packets coalesced in this context
f8212f97
AD		 1137 *
1138 * This function changes a queue full of hw rsc buffers into a completed
1139 * packet. It uses the ->prev pointers to find the first packet and then
1140 * turns it into the frag list owner.
1141 **/
94b982b2
MC		 1142static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb,
1143 u64 *count)
f8212f97
AD		 1144{
1145 unsigned int frag_list_size = 0;
1146
1147 while (skb->prev) {
1148 struct sk_buff *prev = skb->prev;
1149 frag_list_size += skb->len;
1150 skb->prev = NULL;
1151 skb = prev;
94b982b2 1152 *count += 1;
f8212f97
AD		 1153 }
1154
1155 skb_shinfo(skb)->frag_list = skb->next;
1156 skb->next = NULL;
1157 skb->len += frag_list_size;
1158 skb->data_len += frag_list_size;
1159 skb->truesize += frag_list_size;
1160 return skb;
1161}
1162
43634e82
MC		 1163struct ixgbe_rsc_cb {
1164 dma_addr_t dma;
e8171aaa 1165 bool delay_unmap;
43634e82
MC		 1166};
1167
1168#define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
1169
78b6f4ce 1170static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
b4617240
PW		 1171 struct ixgbe_ring *rx_ring,
1172 int *work_done, int work_to_do)
9a799d71 1173{
78b6f4ce 1174 struct ixgbe_adapter *adapter = q_vector->adapter;
2d86f139 1175 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 1176 struct pci_dev *pdev = adapter->pdev;
1177 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1178 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1179 struct sk_buff *skb;
f8212f97 1180 unsigned int i, rsc_count = 0;
7c6e0a43 1181 u32 len, staterr;
177db6ff
MC		 1182 u16 hdr_info;
1183 bool cleaned = false;
9a799d71 1184 int cleaned_count = 0;
d2f4fbe2 1185 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3d8fd385
YZ		 1186#ifdef IXGBE_FCOE
1187 int ddp_bytes = 0;
1188#endif /* IXGBE_FCOE */
9a799d71
AK		 1189
1190 i = rx_ring->next_to_clean;
9a799d71
AK		 1191 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
1192 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1193 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 1194
1195 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 1196 u32 upper_len = 0;
9a799d71
AK		 1197 if (*work_done >= work_to_do)
1198 break;
1199 (*work_done)++;
1200
3c945e5b 1201 rmb(); /* read descriptor and rx_buffer_info after status DD */
6e455b89 1202 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
7c6e0a43
JB		 1203 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
1204 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
762f4c57 1205 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
9a799d71 1206 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
0b746e08
SN		 1207 if ((len > IXGBE_RX_HDR_SIZE) ||
1208 (upper_len && !(hdr_info & IXGBE_RXDADV_SPH)))
1209 len = IXGBE_RX_HDR_SIZE;
7c6e0a43 1210 } else {
9a799d71 1211 len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 1212 }
9a799d71
AK		 1213
1214 cleaned = true;
1215 skb = rx_buffer_info->skb;
7ca3bc58 1216 prefetch(skb->data);
9a799d71
AK		 1217 rx_buffer_info->skb = NULL;
1218
21fa4e66 1219 if (rx_buffer_info->dma) {
43634e82
MC		 1220 if ((adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
1221 (!(staterr & IXGBE_RXD_STAT_EOP)) &&
e8171aaa 1222 (!(skb->prev))) {
43634e82
MC		 1223 /*
1224 * When HWRSC is enabled, delay unmapping
1225 * of the first packet. It carries the
1226 * header information, HW may still
1227 * access the header after the writeback.
1228 * Only unmap it when EOP is reached
1229 */
e8171aaa 1230 IXGBE_RSC_CB(skb)->delay_unmap = true;
43634e82 1231 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
e8171aaa 1232 } else {
1b507730 1233 dma_unmap_single(&pdev->dev,
e8171aaa 1234 rx_buffer_info->dma,
43634e82 1235 rx_ring->rx_buf_len,
e8171aaa
MC		 1236 DMA_FROM_DEVICE);
1237 }
4f57ca6e 1238 rx_buffer_info->dma = 0;
9a799d71
AK		 1239 skb_put(skb, len);
1240 }
1241
1242 if (upper_len) {
1b507730
NN		 1243 dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
1244 PAGE_SIZE / 2, DMA_FROM_DEVICE);
9a799d71
AK		 1245 rx_buffer_info->page_dma = 0;
1246 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
762f4c57
JB		 1247 rx_buffer_info->page,
1248 rx_buffer_info->page_offset,
1249 upper_len);
1250
1251 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
1252 (page_count(rx_buffer_info->page) != 1))
1253 rx_buffer_info->page = NULL;
1254 else
1255 get_page(rx_buffer_info->page);
9a799d71
AK		 1256
1257 skb->len += upper_len;
1258 skb->data_len += upper_len;
1259 skb->truesize += upper_len;
1260 }
1261
1262 i++;
1263 if (i == rx_ring->count)
1264 i = 0;
9a799d71
AK		 1265
1266 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
1267 prefetch(next_rxd);
9a799d71 1268 cleaned_count++;
f8212f97 1269
0c19d6af 1270 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
f8212f97
AD		 1271 rsc_count = ixgbe_get_rsc_count(rx_desc);
1272
1273 if (rsc_count) {
1274 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1275 IXGBE_RXDADV_NEXTP_SHIFT;
1276 next_buffer = &rx_ring->rx_buffer_info[nextp];
f8212f97
AD		 1277 } else {
1278 next_buffer = &rx_ring->rx_buffer_info[i];
1279 }
1280
9a799d71 1281 if (staterr & IXGBE_RXD_STAT_EOP) {
f8212f97 1282 if (skb->prev)
94b982b2
MC		 1283 skb = ixgbe_transform_rsc_queue(skb, &(rx_ring->rsc_count));
1284 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
e8171aaa 1285 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1b507730
NN		 1286 dma_unmap_single(&pdev->dev,
1287 IXGBE_RSC_CB(skb)->dma,
43634e82 1288 rx_ring->rx_buf_len,
1b507730 1289 DMA_FROM_DEVICE);
fd3686a8 1290 IXGBE_RSC_CB(skb)->dma = 0;
e8171aaa 1291 IXGBE_RSC_CB(skb)->delay_unmap = false;
fd3686a8 1292 }
94b982b2
MC		 1293 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)
1294 rx_ring->rsc_count += skb_shinfo(skb)->nr_frags;
1295 else
1296 rx_ring->rsc_count++;
1297 rx_ring->rsc_flush++;
1298 }
9a799d71
AK		 1299 rx_ring->stats.packets++;
1300 rx_ring->stats.bytes += skb->len;
1301 } else {
6e455b89 1302 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
f8212f97
AD		 1303 rx_buffer_info->skb = next_buffer->skb;
1304 rx_buffer_info->dma = next_buffer->dma;
1305 next_buffer->skb = skb;
1306 next_buffer->dma = 0;
1307 } else {
1308 skb->next = next_buffer->skb;
1309 skb->next->prev = skb;
1310 }
7ca3bc58 1311 rx_ring->non_eop_descs++;
9a799d71
AK		 1312 goto next_desc;
1313 }
1314
1315 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
1316 dev_kfree_skb_irq(skb);
1317 goto next_desc;
1318 }
1319
8bae1b2b 1320 ixgbe_rx_checksum(adapter, rx_desc, skb);
d2f4fbe2
AV		 1321
1322 /* probably a little skewed due to removing CRC */
1323 total_rx_bytes += skb->len;
1324 total_rx_packets++;
1325
74ce8dd2 1326 skb->protocol = eth_type_trans(skb, adapter->netdev);
332d4a7d
YZ		 1327#ifdef IXGBE_FCOE
1328 /* if ddp, not passing to ULD unless for FCP_RSP or error */
3d8fd385
YZ		 1329 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1330 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1331 if (!ddp_bytes)
332d4a7d 1332 goto next_desc;
3d8fd385 1333 }
332d4a7d 1334#endif /* IXGBE_FCOE */
fdaff1ce 1335 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
9a799d71
AK		 1336
1337next_desc:
1338 rx_desc->wb.upper.status_error = 0;
1339
1340 /* return some buffers to hardware, one at a time is too slow */
1341 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1342 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1343 cleaned_count = 0;
1344 }
1345
1346 /* use prefetched values */
1347 rx_desc = next_rxd;
f8212f97 1348 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 1349
1350 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 1351 }
1352
9a799d71
AK		 1353 rx_ring->next_to_clean = i;
1354 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1355
1356 if (cleaned_count)
1357 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1358
3d8fd385
YZ		 1359#ifdef IXGBE_FCOE
1360 /* include DDPed FCoE data */
1361 if (ddp_bytes > 0) {
1362 unsigned int mss;
1363
1364 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
1365 sizeof(struct fc_frame_header) -
1366 sizeof(struct fcoe_crc_eof);
1367 if (mss > 512)
1368 mss &= ~511;
1369 total_rx_bytes += ddp_bytes;
1370 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1371 }
1372#endif /* IXGBE_FCOE */
1373
f494e8fa
AV		 1374 rx_ring->total_packets += total_rx_packets;
1375 rx_ring->total_bytes += total_rx_bytes;
2d86f139
AK		 1376 netdev->stats.rx_bytes += total_rx_bytes;
1377 netdev->stats.rx_packets += total_rx_packets;
f494e8fa 1378
9a799d71
AK		 1379 return cleaned;
1380}
1381
021230d4 1382static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 1383/**
1384 * ixgbe_configure_msix - Configure MSI-X hardware
1385 * @adapter: board private structure
1386 *
1387 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1388 * interrupts.
1389 **/
1390static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1391{
021230d4
AV		 1392 struct ixgbe_q_vector *q_vector;
1393 int i, j, q_vectors, v_idx, r_idx;
1394 u32 mask;
9a799d71 1395
021230d4 1396 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 1397
4df10466
JB		 1398 /*
1399 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1400 * corresponding register.
1401 */
1402 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
7a921c93 1403 q_vector = adapter->q_vector[v_idx];
984b3f57 1404 /* XXX for_each_set_bit(...) */
021230d4 1405 r_idx = find_first_bit(q_vector->rxr_idx,
b4617240 1406 adapter->num_rx_queues);
021230d4
AV		 1407
1408 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1409 j = adapter->rx_ring[r_idx]->reg_idx;
e8e26350 1410 ixgbe_set_ivar(adapter, 0, j, v_idx);
021230d4 1411 r_idx = find_next_bit(q_vector->rxr_idx,
b4617240
PW		 1412 adapter->num_rx_queues,
1413 r_idx + 1);
021230d4
AV		 1414 }
1415 r_idx = find_first_bit(q_vector->txr_idx,
b4617240 1416 adapter->num_tx_queues);
021230d4
AV		 1417
1418 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1419 j = adapter->tx_ring[r_idx]->reg_idx;
e8e26350 1420 ixgbe_set_ivar(adapter, 1, j, v_idx);
021230d4 1421 r_idx = find_next_bit(q_vector->txr_idx,
b4617240
PW		 1422 adapter->num_tx_queues,
1423 r_idx + 1);
021230d4
AV		 1424 }
1425
021230d4 1426 if (q_vector->txr_count && !q_vector->rxr_count)
f7554a2b
NS		 1427 /* tx only */
1428 q_vector->eitr = adapter->tx_eitr_param;
509ee935 1429 else if (q_vector->rxr_count)
f7554a2b
NS		 1430 /* rx or mixed */
1431 q_vector->eitr = adapter->rx_eitr_param;
021230d4 1432
fe49f04a 1433 ixgbe_write_eitr(q_vector);
9a799d71
AK		 1434 }
1435
e8e26350
PW		 1436 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1437 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1438 v_idx);
1439 else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1440 ixgbe_set_ivar(adapter, -1, 1, v_idx);
021230d4
AV		 1441 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1442
41fb9248 1443 /* set up to autoclear timer, and the vectors */
021230d4 1444 mask = IXGBE_EIMS_ENABLE_MASK;
1cdd1ec8
GR		 1445 if (adapter->num_vfs)
1446 mask &= ~(IXGBE_EIMS_OTHER |
1447 IXGBE_EIMS_MAILBOX |
1448 IXGBE_EIMS_LSC);
1449 else
1450 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 1451 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1452}
1453
f494e8fa
AV		 1454enum latency_range {
1455 lowest_latency = 0,
1456 low_latency = 1,
1457 bulk_latency = 2,
1458 latency_invalid = 255
1459};
1460
1461/**
1462 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1463 * @adapter: pointer to adapter
1464 * @eitr: eitr setting (ints per sec) to give last timeslice
1465 * @itr_setting: current throttle rate in ints/second
1466 * @packets: the number of packets during this measurement interval
1467 * @bytes: the number of bytes during this measurement interval
1468 *
1469 * Stores a new ITR value based on packets and byte
1470 * counts during the last interrupt. The advantage of per interrupt
1471 * computation is faster updates and more accurate ITR for the current
1472 * traffic pattern. Constants in this function were computed
1473 * based on theoretical maximum wire speed and thresholds were set based
1474 * on testing data as well as attempting to minimize response time
1475 * while increasing bulk throughput.
1476 * this functionality is controlled by the InterruptThrottleRate module
1477 * parameter (see ixgbe_param.c)
1478 **/
1479static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
b4617240
PW		 1480 u32 eitr, u8 itr_setting,
1481 int packets, int bytes)
f494e8fa
AV		 1482{
1483 unsigned int retval = itr_setting;
1484 u32 timepassed_us;
1485 u64 bytes_perint;
1486
1487 if (packets == 0)
1488 goto update_itr_done;
1489
1490
1491 /* simple throttlerate management
1492 * 0-20MB/s lowest (100000 ints/s)
1493 * 20-100MB/s low (20000 ints/s)
1494 * 100-1249MB/s bulk (8000 ints/s)
1495 */
1496 /* what was last interrupt timeslice? */
1497 timepassed_us = 1000000/eitr;
1498 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1499
1500 switch (itr_setting) {
1501 case lowest_latency:
1502 if (bytes_perint > adapter->eitr_low)
1503 retval = low_latency;
1504 break;
1505 case low_latency:
1506 if (bytes_perint > adapter->eitr_high)
1507 retval = bulk_latency;
1508 else if (bytes_perint <= adapter->eitr_low)
1509 retval = lowest_latency;
1510 break;
1511 case bulk_latency:
1512 if (bytes_perint <= adapter->eitr_high)
1513 retval = low_latency;
1514 break;
1515 }
1516
1517update_itr_done:
1518 return retval;
1519}
1520
509ee935
JB		 1521/**
1522 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1523 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1524 *
1525 * This function is made to be called by ethtool and by the driver
1526 * when it needs to update EITR registers at runtime. Hardware
1527 * specific quirks/differences are taken care of here.
1528 */
fe49f04a 1529void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1530{
fe49f04a 1531 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1532 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 1533 int v_idx = q_vector->v_idx;
1534 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1535
509ee935
JB		 1536 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1537 /* must write high and low 16 bits to reset counter */
1538 itr_reg |= (itr_reg << 16);
1539 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
f8d1dcaf
JB		 1540 /*
1541 * 82599 can support a value of zero, so allow it for
1542 * max interrupt rate, but there is an errata where it can
1543 * not be zero with RSC
1544 */
1545 if (itr_reg == 8 &&
1546 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1547 itr_reg = 0;
1548
509ee935
JB		 1549 /*
1550 * set the WDIS bit to not clear the timer bits and cause an
1551 * immediate assertion of the interrupt
1552 */
1553 itr_reg |= IXGBE_EITR_CNT_WDIS;
1554 }
1555 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1556}
1557
f494e8fa
AV		 1558static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1559{
1560 struct ixgbe_adapter *adapter = q_vector->adapter;
f494e8fa
AV		 1561 u32 new_itr;
1562 u8 current_itr, ret_itr;
fe49f04a 1563 int i, r_idx;
f494e8fa
AV		 1564 struct ixgbe_ring *rx_ring, *tx_ring;
1565
1566 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1567 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1568 tx_ring = adapter->tx_ring[r_idx];
f494e8fa 1569 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 1570 q_vector->tx_itr,
1571 tx_ring->total_packets,
1572 tx_ring->total_bytes);
f494e8fa
AV		 1573 /* if the result for this queue would decrease interrupt
1574 * rate for this vector then use that result */
30efa5a3 1575 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
b4617240 1576 q_vector->tx_itr - 1 : ret_itr);
f494e8fa 1577 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1578 r_idx + 1);
f494e8fa
AV		 1579 }
1580
1581 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1582 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1583 rx_ring = adapter->rx_ring[r_idx];
f494e8fa 1584 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 1585 q_vector->rx_itr,
1586 rx_ring->total_packets,
1587 rx_ring->total_bytes);
f494e8fa
AV		 1588 /* if the result for this queue would decrease interrupt
1589 * rate for this vector then use that result */
30efa5a3 1590 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
b4617240 1591 q_vector->rx_itr - 1 : ret_itr);
f494e8fa 1592 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
b4617240 1593 r_idx + 1);
f494e8fa
AV		 1594 }
1595
30efa5a3 1596 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1597
1598 switch (current_itr) {
1599 /* counts and packets in update_itr are dependent on these numbers */
1600 case lowest_latency:
1601 new_itr = 100000;
1602 break;
1603 case low_latency:
1604 new_itr = 20000; /* aka hwitr = ~200 */
1605 break;
1606 case bulk_latency:
1607 default:
1608 new_itr = 8000;
1609 break;
1610 }
1611
1612 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 1613 /* do an exponential smoothing */
1614 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 1615
1616 /* save the algorithm value here, not the smoothed one */
1617 q_vector->eitr = new_itr;
fe49f04a
AD		 1618
1619 ixgbe_write_eitr(q_vector);
f494e8fa 1620 }
f494e8fa
AV		 1621}
1622
119fc60a
MC		 1623/**
1624 * ixgbe_check_overtemp_task - worker thread to check over tempurature
1625 * @work: pointer to work_struct containing our data
1626 **/
1627static void ixgbe_check_overtemp_task(struct work_struct *work)
1628{
1629 struct ixgbe_adapter *adapter = container_of(work,
1630 struct ixgbe_adapter,
1631 check_overtemp_task);
1632 struct ixgbe_hw *hw = &adapter->hw;
1633 u32 eicr = adapter->interrupt_event;
1634
1635 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
1636 switch (hw->device_id) {
1637 case IXGBE_DEV_ID_82599_T3_LOM: {
1638 u32 autoneg;
1639 bool link_up = false;
1640
1641 if (hw->mac.ops.check_link)
1642 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1643
1644 if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) ||
1645 (eicr & IXGBE_EICR_LSC))
1646 /* Check if this is due to overtemp */
1647 if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP)
1648 break;
1649 }
1650 return;
1651 default:
1652 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1653 return;
1654 break;
1655 }
396e799c
ET		 1656 e_crit(drv, "Network adapter has been stopped because it has "
1657 "over heated. Restart the computer. If the problem "
849c4542
ET		 1658 "persists, power off the system and replace the "
1659 "adapter\n");
119fc60a
MC		 1660 /* write to clear the interrupt */
1661 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0);
1662 }
1663}
1664
0befdb3e
JB		 1665static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1666{
1667 struct ixgbe_hw *hw = &adapter->hw;
1668
1669 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1670 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 1671 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 1672 /* write to clear the interrupt */
1673 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1674 }
1675}
cf8280ee 1676
e8e26350
PW		 1677static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1678{
1679 struct ixgbe_hw *hw = &adapter->hw;
1680
1681 if (eicr & IXGBE_EICR_GPI_SDP1) {
1682 /* Clear the interrupt */
1683 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1684 schedule_work(&adapter->multispeed_fiber_task);
1685 } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1686 /* Clear the interrupt */
1687 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1688 schedule_work(&adapter->sfp_config_module_task);
1689 } else {
1690 /* Interrupt isn't for us... */
1691 return;
1692 }
1693}
1694
cf8280ee
JB		 1695static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1696{
1697 struct ixgbe_hw *hw = &adapter->hw;
1698
1699 adapter->lsc_int++;
1700 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1701 adapter->link_check_timeout = jiffies;
1702 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1703 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 1704 IXGBE_WRITE_FLUSH(hw);
cf8280ee
JB		 1705 schedule_work(&adapter->watchdog_task);
1706 }
1707}
1708
9a799d71
AK		 1709static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1710{
1711 struct net_device *netdev = data;
1712 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1713 struct ixgbe_hw *hw = &adapter->hw;
54037505
DS		 1714 u32 eicr;
1715
1716 /*
1717 * Workaround for Silicon errata. Use clear-by-write instead
1718 * of clear-by-read. Reading with EICS will return the
1719 * interrupt causes without clearing, which later be done
1720 * with the write to EICR.
1721 */
1722 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1723 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
9a799d71 1724
cf8280ee
JB		 1725 if (eicr & IXGBE_EICR_LSC)
1726 ixgbe_check_lsc(adapter);
d4f80882 1727
1cdd1ec8
GR		 1728 if (eicr & IXGBE_EICR_MAILBOX)
1729 ixgbe_msg_task(adapter);
1730
e8e26350
PW		 1731 if (hw->mac.type == ixgbe_mac_82598EB)
1732 ixgbe_check_fan_failure(adapter, eicr);
0befdb3e 1733
c4cf55e5 1734 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 1735 ixgbe_check_sfp_event(adapter, eicr);
119fc60a
MC		 1736 adapter->interrupt_event = eicr;
1737 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1738 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
1739 schedule_work(&adapter->check_overtemp_task);
c4cf55e5
PWJ		 1740
1741 /* Handle Flow Director Full threshold interrupt */
1742 if (eicr & IXGBE_EICR_FLOW_DIR) {
1743 int i;
1744 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1745 /* Disable transmits before FDIR Re-initialization */
1746 netif_tx_stop_all_queues(netdev);
1747 for (i = 0; i < adapter->num_tx_queues; i++) {
1748 struct ixgbe_ring *tx_ring =
4a0b9ca0 1749 adapter->tx_ring[i];
c4cf55e5
PWJ		 1750 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1751 &tx_ring->reinit_state))
1752 schedule_work(&adapter->fdir_reinit_task);
1753 }
1754 }
1755 }
d4f80882
AV		 1756 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1757 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 1758
1759 return IRQ_HANDLED;
1760}
1761
fe49f04a
AD		 1762static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1763 u64 qmask)
1764{
1765 u32 mask;
1766
1767 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1768 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1769 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1770 } else {
1771 mask = (qmask & 0xFFFFFFFF);
1772 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1773 mask = (qmask >> 32);
1774 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1775 }
1776 /* skip the flush */
1777}
1778
1779static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1780 u64 qmask)
1781{
1782 u32 mask;
1783
1784 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1785 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1786 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1787 } else {
1788 mask = (qmask & 0xFFFFFFFF);
1789 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1790 mask = (qmask >> 32);
1791 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1792 }
1793 /* skip the flush */
1794}
1795
9a799d71
AK		 1796static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1797{
021230d4
AV		 1798 struct ixgbe_q_vector *q_vector = data;
1799 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1800 struct ixgbe_ring *tx_ring;
021230d4
AV		 1801 int i, r_idx;
1802
1803 if (!q_vector->txr_count)
1804 return IRQ_HANDLED;
1805
1806 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1807 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1808 tx_ring = adapter->tx_ring[r_idx];
3a581073
JB		 1809 tx_ring->total_bytes = 0;
1810 tx_ring->total_packets = 0;
021230d4 1811 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1812 r_idx + 1);
021230d4 1813 }
9a799d71 1814
9b471446 1815 /* EIAM disabled interrupts (on this vector) for us */
91281fd3
AD		 1816 napi_schedule(&q_vector->napi);
1817
9a799d71
AK		 1818 return IRQ_HANDLED;
1819}
1820
021230d4
AV		 1821/**
1822 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1823 * @irq: unused
1824 * @data: pointer to our q_vector struct for this interrupt vector
1825 **/
9a799d71
AK		 1826static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1827{
021230d4
AV		 1828 struct ixgbe_q_vector *q_vector = data;
1829 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1830 struct ixgbe_ring *rx_ring;
021230d4 1831 int r_idx;
30efa5a3 1832 int i;
021230d4
AV		 1833
1834 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
30efa5a3 1835 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1836 rx_ring = adapter->rx_ring[r_idx];
30efa5a3
JB		 1837 rx_ring->total_bytes = 0;
1838 rx_ring->total_packets = 0;
1839 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1840 r_idx + 1);
1841 }
1842
021230d4
AV		 1843 if (!q_vector->rxr_count)
1844 return IRQ_HANDLED;
1845
021230d4 1846 /* disable interrupts on this vector only */
9b471446 1847 /* EIAM disabled interrupts (on this vector) for us */
288379f0 1848 napi_schedule(&q_vector->napi);
021230d4
AV		 1849
1850 return IRQ_HANDLED;
1851}
1852
1853static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1854{
91281fd3
AD		 1855 struct ixgbe_q_vector *q_vector = data;
1856 struct ixgbe_adapter *adapter = q_vector->adapter;
1857 struct ixgbe_ring *ring;
1858 int r_idx;
1859 int i;
1860
1861 if (!q_vector->txr_count && !q_vector->rxr_count)
1862 return IRQ_HANDLED;
1863
1864 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1865 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1866 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 1867 ring->total_bytes = 0;
1868 ring->total_packets = 0;
1869 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1870 r_idx + 1);
1871 }
1872
1873 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1874 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1875 ring = adapter->rx_ring[r_idx];
91281fd3
AD		 1876 ring->total_bytes = 0;
1877 ring->total_packets = 0;
1878 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1879 r_idx + 1);
1880 }
1881
9b471446 1882 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 1883 napi_schedule(&q_vector->napi);
9a799d71 1884
9a799d71
AK		 1885 return IRQ_HANDLED;
1886}
1887
021230d4
AV		 1888/**
1889 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1890 * @napi: napi struct with our devices info in it
1891 * @budget: amount of work driver is allowed to do this pass, in packets
1892 *
f0848276
JB		 1893 * This function is optimized for cleaning one queue only on a single
1894 * q_vector!!!
021230d4 1895 **/
9a799d71
AK		 1896static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1897{
021230d4 1898 struct ixgbe_q_vector *q_vector =
b4617240 1899 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 1900 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 1901 struct ixgbe_ring *rx_ring = NULL;
9a799d71 1902 int work_done = 0;
021230d4 1903 long r_idx;
9a799d71 1904
021230d4 1905 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
4a0b9ca0 1906 rx_ring = adapter->rx_ring[r_idx];
5dd2d332 1907#ifdef CONFIG_IXGBE_DCA
bd0362dd 1908 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1909 ixgbe_update_rx_dca(adapter, rx_ring);
bd0362dd 1910#endif
9a799d71 1911
78b6f4ce 1912 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
9a799d71 1913
021230d4
AV		 1914 /* If all Rx work done, exit the polling mode */
1915 if (work_done < budget) {
288379f0 1916 napi_complete(napi);
f7554a2b 1917 if (adapter->rx_itr_setting & 1)
f494e8fa 1918 ixgbe_set_itr_msix(q_vector);
9a799d71 1919 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a
AD		 1920 ixgbe_irq_enable_queues(adapter,
1921 ((u64)1 << q_vector->v_idx));
9a799d71
AK		 1922 }
1923
1924 return work_done;
1925}
1926
f0848276 1927/**
91281fd3 1928 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
f0848276
JB		 1929 * @napi: napi struct with our devices info in it
1930 * @budget: amount of work driver is allowed to do this pass, in packets
1931 *
1932 * This function will clean more than one rx queue associated with a
1933 * q_vector.
1934 **/
91281fd3 1935static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
f0848276
JB		 1936{
1937 struct ixgbe_q_vector *q_vector =
1938 container_of(napi, struct ixgbe_q_vector, napi);
1939 struct ixgbe_adapter *adapter = q_vector->adapter;
91281fd3 1940 struct ixgbe_ring *ring = NULL;
f0848276
JB		 1941 int work_done = 0, i;
1942 long r_idx;
91281fd3
AD		 1943 bool tx_clean_complete = true;
1944
1945 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1946 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1947 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 1948#ifdef CONFIG_IXGBE_DCA
1949 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1950 ixgbe_update_tx_dca(adapter, ring);
1951#endif
1952 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1953 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1954 r_idx + 1);
1955 }
f0848276
JB		 1956
1957 /* attempt to distribute budget to each queue fairly, but don't allow
1958 * the budget to go below 1 because we'll exit polling */
1959 budget /= (q_vector->rxr_count ?: 1);
1960 budget = max(budget, 1);
1961 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1962 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1963 ring = adapter->rx_ring[r_idx];
5dd2d332 1964#ifdef CONFIG_IXGBE_DCA
f0848276 1965 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
91281fd3 1966 ixgbe_update_rx_dca(adapter, ring);
f0848276 1967#endif
91281fd3 1968 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
f0848276
JB		 1969 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1970 r_idx + 1);
1971 }
1972
1973 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
4a0b9ca0 1974 ring = adapter->rx_ring[r_idx];
f0848276 1975 /* If all Rx work done, exit the polling mode */
7f821875 1976 if (work_done < budget) {
288379f0 1977 napi_complete(napi);
f7554a2b 1978 if (adapter->rx_itr_setting & 1)
f0848276
JB		 1979 ixgbe_set_itr_msix(q_vector);
1980 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a
AD		 1981 ixgbe_irq_enable_queues(adapter,
1982 ((u64)1 << q_vector->v_idx));
f0848276
JB		 1983 return 0;
1984 }
1985
1986 return work_done;
1987}
91281fd3
AD		 1988
1989/**
1990 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1991 * @napi: napi struct with our devices info in it
1992 * @budget: amount of work driver is allowed to do this pass, in packets
1993 *
1994 * This function is optimized for cleaning one queue only on a single
1995 * q_vector!!!
1996 **/
1997static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1998{
1999 struct ixgbe_q_vector *q_vector =
2000 container_of(napi, struct ixgbe_q_vector, napi);
2001 struct ixgbe_adapter *adapter = q_vector->adapter;
2002 struct ixgbe_ring *tx_ring = NULL;
2003 int work_done = 0;
2004 long r_idx;
2005
2006 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
4a0b9ca0 2007 tx_ring = adapter->tx_ring[r_idx];
91281fd3
AD		 2008#ifdef CONFIG_IXGBE_DCA
2009 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2010 ixgbe_update_tx_dca(adapter, tx_ring);
2011#endif
2012
2013 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2014 work_done = budget;
2015
f7554a2b 2016 /* If all Tx work done, exit the polling mode */
91281fd3
AD		 2017 if (work_done < budget) {
2018 napi_complete(napi);
f7554a2b 2019 if (adapter->tx_itr_setting & 1)
91281fd3
AD		 2020 ixgbe_set_itr_msix(q_vector);
2021 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2022 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2023 }
2024
2025 return work_done;
2026}
2027
021230d4 2028static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
b4617240 2029 int r_idx)
021230d4 2030{
7a921c93
AD		 2031 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2032
2033 set_bit(r_idx, q_vector->rxr_idx);
2034 q_vector->rxr_count++;
021230d4
AV		 2035}
2036
2037static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
7a921c93 2038 int t_idx)
021230d4 2039{
7a921c93
AD		 2040 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2041
2042 set_bit(t_idx, q_vector->txr_idx);
2043 q_vector->txr_count++;
021230d4
AV		 2044}
2045
9a799d71 2046/**
021230d4
AV		 2047 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2048 * @adapter: board private structure to initialize
2049 * @vectors: allotted vector count for descriptor rings
9a799d71 2050 *
021230d4
AV		 2051 * This function maps descriptor rings to the queue-specific vectors
2052 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2053 * one vector per ring/queue, but on a constrained vector budget, we
2054 * group the rings as "efficiently" as possible. You would add new
2055 * mapping configurations in here.
9a799d71 2056 **/
021230d4 2057static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
b4617240 2058 int vectors)
021230d4
AV		 2059{
2060 int v_start = 0;
2061 int rxr_idx = 0, txr_idx = 0;
2062 int rxr_remaining = adapter->num_rx_queues;
2063 int txr_remaining = adapter->num_tx_queues;
2064 int i, j;
2065 int rqpv, tqpv;
2066 int err = 0;
2067
2068 /* No mapping required if MSI-X is disabled. */
2069 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2070 goto out;
9a799d71 2071
021230d4
AV		 2072 /*
2073 * The ideal configuration...
2074 * We have enough vectors to map one per queue.
2075 */
2076 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2077 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2078 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 2079
021230d4
AV		 2080 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2081 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 2082
9a799d71 2083 goto out;
021230d4 2084 }
9a799d71 2085
021230d4
AV		 2086 /*
2087 * If we don't have enough vectors for a 1-to-1
2088 * mapping, we'll have to group them so there are
2089 * multiple queues per vector.
2090 */
2091 /* Re-adjusting *qpv takes care of the remainder. */
2092 for (i = v_start; i < vectors; i++) {
2093 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
2094 for (j = 0; j < rqpv; j++) {
2095 map_vector_to_rxq(adapter, i, rxr_idx);
2096 rxr_idx++;
2097 rxr_remaining--;
2098 }
2099 }
2100 for (i = v_start; i < vectors; i++) {
2101 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
2102 for (j = 0; j < tqpv; j++) {
2103 map_vector_to_txq(adapter, i, txr_idx);
2104 txr_idx++;
2105 txr_remaining--;
9a799d71 2106 }
9a799d71
AK		 2107 }
2108
021230d4
AV		 2109out:
2110 return err;
2111}
2112
2113/**
2114 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2115 * @adapter: board private structure
2116 *
2117 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2118 * interrupts from the kernel.
2119 **/
2120static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2121{
2122 struct net_device *netdev = adapter->netdev;
2123 irqreturn_t (*handler)(int, void *);
2124 int i, vector, q_vectors, err;
cb13fc20 2125 int ri=0, ti=0;
021230d4
AV		 2126
2127 /* Decrement for Other and TCP Timer vectors */
2128 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2129
2130 /* Map the Tx/Rx rings to the vectors we were allotted. */
2131 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
2132 if (err)
2133 goto out;
2134
2135#define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
b4617240
PW		 2136 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
2137 &ixgbe_msix_clean_many)
021230d4 2138 for (vector = 0; vector < q_vectors; vector++) {
7a921c93 2139 handler = SET_HANDLER(adapter->q_vector[vector]);
cb13fc20
RO		 2140
2141 if(handler == &ixgbe_msix_clean_rx) {
2142 sprintf(adapter->name[vector], "%s-%s-%d",
2143 netdev->name, "rx", ri++);
2144 }
2145 else if(handler == &ixgbe_msix_clean_tx) {
2146 sprintf(adapter->name[vector], "%s-%s-%d",
2147 netdev->name, "tx", ti++);
2148 }
2149 else
2150 sprintf(adapter->name[vector], "%s-%s-%d",
2151 netdev->name, "TxRx", vector);
2152
021230d4 2153 err = request_irq(adapter->msix_entries[vector].vector,
b4617240 2154 handler, 0, adapter->name[vector],
7a921c93 2155 adapter->q_vector[vector]);
9a799d71 2156 if (err) {
396e799c 2157 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2158 "Error: %d\n", err);
021230d4 2159 goto free_queue_irqs;
9a799d71 2160 }
9a799d71
AK		 2161 }
2162
021230d4
AV		 2163 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
2164 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2165 ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
9a799d71 2166 if (err) {
396e799c 2167 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
021230d4 2168 goto free_queue_irqs;
9a799d71
AK		 2169 }
2170
9a799d71
AK		 2171 return 0;
2172
021230d4
AV		 2173free_queue_irqs:
2174 for (i = vector - 1; i >= 0; i--)
2175 free_irq(adapter->msix_entries[--vector].vector,
7a921c93 2176 adapter->q_vector[i]);
021230d4
AV		 2177 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2178 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2179 kfree(adapter->msix_entries);
2180 adapter->msix_entries = NULL;
021230d4 2181out:
9a799d71
AK		 2182 return err;
2183}
2184
f494e8fa
AV		 2185static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2186{
7a921c93 2187 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
f494e8fa
AV		 2188 u8 current_itr;
2189 u32 new_itr = q_vector->eitr;
4a0b9ca0
PW		 2190 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2191 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
f494e8fa 2192
30efa5a3 2193 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 2194 q_vector->tx_itr,
2195 tx_ring->total_packets,
2196 tx_ring->total_bytes);
30efa5a3 2197 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 2198 q_vector->rx_itr,
2199 rx_ring->total_packets,
2200 rx_ring->total_bytes);
f494e8fa 2201
30efa5a3 2202 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 2203
2204 switch (current_itr) {
2205 /* counts and packets in update_itr are dependent on these numbers */
2206 case lowest_latency:
2207 new_itr = 100000;
2208 break;
2209 case low_latency:
2210 new_itr = 20000; /* aka hwitr = ~200 */
2211 break;
2212 case bulk_latency:
2213 new_itr = 8000;
2214 break;
2215 default:
2216 break;
2217 }
2218
2219 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 2220 /* do an exponential smoothing */
2221 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 2222
2223 /* save the algorithm value here, not the smoothed one */
2224 q_vector->eitr = new_itr;
fe49f04a
AD		 2225
2226 ixgbe_write_eitr(q_vector);
f494e8fa 2227 }
f494e8fa
AV		 2228}
2229
79aefa45
AD		 2230/**
2231 * ixgbe_irq_enable - Enable default interrupt generation settings
2232 * @adapter: board private structure
2233 **/
2234static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
2235{
2236 u32 mask;
835462fc
NS		 2237
2238 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
119fc60a
MC		 2239 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2240 mask |= IXGBE_EIMS_GPI_SDP0;
6ab33d51
DM		 2241 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2242 mask |= IXGBE_EIMS_GPI_SDP1;
e8e26350 2243 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2a41ff81 2244 mask |= IXGBE_EIMS_ECC;
e8e26350
PW		 2245 mask |= IXGBE_EIMS_GPI_SDP1;
2246 mask |= IXGBE_EIMS_GPI_SDP2;
1cdd1ec8
GR		 2247 if (adapter->num_vfs)
2248 mask |= IXGBE_EIMS_MAILBOX;
e8e26350 2249 }
c4cf55e5
PWJ		 2250 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2251 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2252 mask |= IXGBE_EIMS_FLOW_DIR;
e8e26350 2253
79aefa45 2254 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
835462fc 2255 ixgbe_irq_enable_queues(adapter, ~0);
79aefa45 2256 IXGBE_WRITE_FLUSH(&adapter->hw);
1cdd1ec8
GR		 2257
2258 if (adapter->num_vfs > 32) {
2259 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2260 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2261 }
79aefa45 2262}
021230d4 2263
9a799d71 2264/**
021230d4 2265 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2266 * @irq: interrupt number
2267 * @data: pointer to a network interface device structure
9a799d71
AK		 2268 **/
2269static irqreturn_t ixgbe_intr(int irq, void *data)
2270{
2271 struct net_device *netdev = data;
2272 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2273 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2274 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2275 u32 eicr;
2276
54037505
DS		 2277 /*
2278 * Workaround for silicon errata. Mask the interrupts
2279 * before the read of EICR.
2280 */
2281 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2282
021230d4
AV		 2283 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2284 * therefore no explict interrupt disable is necessary */
2285 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e
JB		 2286 if (!eicr) {
2287 /* shared interrupt alert!
2288 * make sure interrupts are enabled because the read will
2289 * have disabled interrupts due to EIAM */
2290 ixgbe_irq_enable(adapter);
9a799d71 2291 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2292 }
9a799d71 2293
cf8280ee
JB		 2294 if (eicr & IXGBE_EICR_LSC)
2295 ixgbe_check_lsc(adapter);
021230d4 2296
e8e26350
PW		 2297 if (hw->mac.type == ixgbe_mac_82599EB)
2298 ixgbe_check_sfp_event(adapter, eicr);
2299
0befdb3e 2300 ixgbe_check_fan_failure(adapter, eicr);
119fc60a
MC		 2301 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2302 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
2303 schedule_work(&adapter->check_overtemp_task);
0befdb3e 2304
7a921c93 2305 if (napi_schedule_prep(&(q_vector->napi))) {
4a0b9ca0
PW		 2306 adapter->tx_ring[0]->total_packets = 0;
2307 adapter->tx_ring[0]->total_bytes = 0;
2308 adapter->rx_ring[0]->total_packets = 0;
2309 adapter->rx_ring[0]->total_bytes = 0;
021230d4 2310 /* would disable interrupts here but EIAM disabled it */
7a921c93 2311 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 2312 }
2313
2314 return IRQ_HANDLED;
2315}
2316
021230d4
AV		 2317static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2318{
2319 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2320
2321 for (i = 0; i < q_vectors; i++) {
7a921c93 2322 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
021230d4
AV		 2323 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2324 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2325 q_vector->rxr_count = 0;
2326 q_vector->txr_count = 0;
2327 }
2328}
2329
9a799d71
AK		 2330/**
2331 * ixgbe_request_irq - initialize interrupts
2332 * @adapter: board private structure
2333 *
2334 * Attempts to configure interrupts using the best available
2335 * capabilities of the hardware and kernel.
2336 **/
021230d4 2337static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2338{
2339 struct net_device *netdev = adapter->netdev;
021230d4 2340 int err;
9a799d71 2341
021230d4
AV		 2342 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2343 err = ixgbe_request_msix_irqs(adapter);
2344 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
a0607fd3 2345 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
b4617240 2346 netdev->name, netdev);
021230d4 2347 } else {
a0607fd3 2348 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
b4617240 2349 netdev->name, netdev);
9a799d71
AK		 2350 }
2351
9a799d71 2352 if (err)
396e799c 2353 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2354
9a799d71
AK		 2355 return err;
2356}
2357
2358static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2359{
2360 struct net_device *netdev = adapter->netdev;
2361
2362 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 2363 int i, q_vectors;
9a799d71 2364
021230d4
AV		 2365 q_vectors = adapter->num_msix_vectors;
2366
2367 i = q_vectors - 1;
9a799d71 2368 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 2369
021230d4
AV		 2370 i--;
2371 for (; i >= 0; i--) {
2372 free_irq(adapter->msix_entries[i].vector,
7a921c93 2373 adapter->q_vector[i]);
021230d4
AV		 2374 }
2375
2376 ixgbe_reset_q_vectors(adapter);
2377 } else {
2378 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 2379 }
2380}
2381
22d5a71b
JB		 2382/**
2383 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2384 * @adapter: board private structure
2385 **/
2386static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2387{
835462fc
NS		 2388 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2389 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2390 } else {
2391 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2392 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2393 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1cdd1ec8
GR		 2394 if (adapter->num_vfs > 32)
2395 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
22d5a71b
JB		 2396 }
2397 IXGBE_WRITE_FLUSH(&adapter->hw);
2398 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2399 int i;
2400 for (i = 0; i < adapter->num_msix_vectors; i++)
2401 synchronize_irq(adapter->msix_entries[i].vector);
2402 } else {
2403 synchronize_irq(adapter->pdev->irq);
2404 }
2405}
2406
9a799d71
AK		 2407/**
2408 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2409 *
2410 **/
2411static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2412{
9a799d71
AK		 2413 struct ixgbe_hw *hw = &adapter->hw;
2414
021230d4 2415 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
f7554a2b 2416 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
9a799d71 2417
e8e26350
PW		 2418 ixgbe_set_ivar(adapter, 0, 0, 0);
2419 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4
AV		 2420
2421 map_vector_to_rxq(adapter, 0, 0);
2422 map_vector_to_txq(adapter, 0, 0);
2423
396e799c 2424 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2425}
2426
43e69bf0
AD		 2427/**
2428 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2429 * @adapter: board private structure
2430 * @ring: structure containing ring specific data
2431 *
2432 * Configure the Tx descriptor ring after a reset.
2433 **/
2434 static void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2435 struct ixgbe_ring *ring)
2436{
2437 struct ixgbe_hw *hw = &adapter->hw;
2438 u64 tdba = ring->dma;
2f1860b8
AD		 2439 int wait_loop = 10;
2440 u32 txdctl;
43e69bf0
AD		 2441 u16 reg_idx = ring->reg_idx;
2442
2f1860b8
AD		 2443 /* disable queue to avoid issues while updating state */
2444 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2445 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2446 txdctl & ~IXGBE_TXDCTL_ENABLE);
2447 IXGBE_WRITE_FLUSH(hw);
2448
43e69bf0
AD		 2449 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2450 (tdba & DMA_BIT_MASK(32)));
2451 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2452 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2453 ring->count * sizeof(union ixgbe_adv_tx_desc));
2454 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2455 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2456 ring->head = IXGBE_TDH(reg_idx);
2457 ring->tail = IXGBE_TDT(reg_idx);
2458
2f1860b8
AD		 2459 /* configure fetching thresholds */
2460 if (adapter->rx_itr_setting == 0) {
2461 /* cannot set wthresh when itr==0 */
2462 txdctl &= ~0x007F0000;
2463 } else {
2464 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2465 txdctl |= (8 << 16);
2466 }
2467 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2468 /* PThresh workaround for Tx hang with DFP enabled. */
2469 txdctl |= 32;
2470 }
2471
2472 /* reinitialize flowdirector state */
2473 set_bit(__IXGBE_FDIR_INIT_DONE, &ring->reinit_state);
2474
2475 /* enable queue */
2476 txdctl |= IXGBE_TXDCTL_ENABLE;
2477 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2478
2479 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2480 if (hw->mac.type == ixgbe_mac_82598EB &&
2481 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2482 return;
2483
2484 /* poll to verify queue is enabled */
2485 do {
2486 msleep(1);
2487 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2488 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2489 if (!wait_loop)
2490 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 2491}
2492
120ff942
AD		 2493static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2494{
2495 struct ixgbe_hw *hw = &adapter->hw;
2496 u32 rttdcs;
2497 u32 mask;
2498
2499 if (hw->mac.type == ixgbe_mac_82598EB)
2500 return;
2501
2502 /* disable the arbiter while setting MTQC */
2503 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2504 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2505 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2506
2507 /* set transmit pool layout */
2508 mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2509 switch (adapter->flags & mask) {
2510
2511 case (IXGBE_FLAG_SRIOV_ENABLED):
2512 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2513 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2514 break;
2515
2516 case (IXGBE_FLAG_DCB_ENABLED):
2517 /* We enable 8 traffic classes, DCB only */
2518 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2519 (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2520 break;
2521
2522 default:
2523 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2524 break;
2525 }
2526
2527 /* re-enable the arbiter */
2528 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2529 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2530}
2531
9a799d71 2532/**
3a581073 2533 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2534 * @adapter: board private structure
2535 *
2536 * Configure the Tx unit of the MAC after a reset.
2537 **/
2538static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2539{
2f1860b8
AD		 2540 struct ixgbe_hw *hw = &adapter->hw;
2541 u32 dmatxctl;
43e69bf0 2542 u32 i;
9a799d71 2543
2f1860b8
AD		 2544 ixgbe_setup_mtqc(adapter);
2545
2546 if (hw->mac.type != ixgbe_mac_82598EB) {
2547 /* DMATXCTL.EN must be before Tx queues are enabled */
2548 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2549 dmatxctl |= IXGBE_DMATXCTL_TE;
2550 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2551 }
2552
9a799d71 2553 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 2554 for (i = 0; i < adapter->num_tx_queues; i++)
2555 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 2556}
2557
e8e26350 2558#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2559
a6616b42
YZ		 2560static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2561 struct ixgbe_ring *rx_ring)
cc41ac7c 2562{
cc41ac7c 2563 u32 srrctl;
a6616b42 2564 int index;
0cefafad 2565 struct ixgbe_ring_feature *feature = adapter->ring_feature;
3be1adfb 2566
a6616b42
YZ		 2567 index = rx_ring->reg_idx;
2568 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2569 unsigned long mask;
0cefafad 2570 mask = (unsigned long) feature[RING_F_RSS].mask;
3be1adfb 2571 index = index & mask;
cc41ac7c 2572 }
cc41ac7c
JB		 2573 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2574
2575 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2576 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2577
afafd5b0
AD		 2578 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2579 IXGBE_SRRCTL_BSIZEHDR_MASK;
2580
6e455b89 2581 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
afafd5b0
AD		 2582#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2583 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2584#else
2585 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2586#endif
cc41ac7c 2587 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 2588 } else {
afafd5b0
AD		 2589 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2590 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 2591 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 2592 }
e8e26350 2593
cc41ac7c
JB		 2594 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2595}
9a799d71 2596
05abb126 2597static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 2598{
05abb126
AD		 2599 struct ixgbe_hw *hw = &adapter->hw;
2600 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2601 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2602 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2603 u32 mrqc = 0, reta = 0;
2604 u32 rxcsum;
2605 int i, j;
0cefafad
JB		 2606 int mask;
2607
05abb126
AD		 2608 /* Fill out hash function seeds */
2609 for (i = 0; i < 10; i++)
2610 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2611
2612 /* Fill out redirection table */
2613 for (i = 0, j = 0; i < 128; i++, j++) {
2614 if (j == adapter->ring_feature[RING_F_RSS].indices)
2615 j = 0;
2616 /* reta = 4-byte sliding window of
2617 * 0x00..(indices-1)(indices-1)00..etc. */
2618 reta = (reta << 8) | (j * 0x11);
2619 if ((i & 3) == 3)
2620 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2621 }
0cefafad 2622
05abb126
AD		 2623 /* Disable indicating checksum in descriptor, enables RSS hash */
2624 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2625 rxcsum |= IXGBE_RXCSUM_PCSD;
2626 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2627
2628 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2629 mask = adapter->flags & IXGBE_FLAG_RSS_ENABLED;
2630 else
2631 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
0cefafad 2632#ifdef CONFIG_IXGBE_DCB
05abb126 2633 | IXGBE_FLAG_DCB_ENABLED
0cefafad 2634#endif
05abb126
AD		 2635 | IXGBE_FLAG_SRIOV_ENABLED
2636 );
0cefafad
JB		 2637
2638 switch (mask) {
2639 case (IXGBE_FLAG_RSS_ENABLED):
2640 mrqc = IXGBE_MRQC_RSSEN;
2641 break;
1cdd1ec8
GR		 2642 case (IXGBE_FLAG_SRIOV_ENABLED):
2643 mrqc = IXGBE_MRQC_VMDQEN;
2644 break;
0cefafad
JB		 2645#ifdef CONFIG_IXGBE_DCB
2646 case (IXGBE_FLAG_DCB_ENABLED):
2647 mrqc = IXGBE_MRQC_RT8TCEN;
2648 break;
2649#endif /* CONFIG_IXGBE_DCB */
2650 default:
2651 break;
2652 }
2653
05abb126
AD		 2654 /* Perform hash on these packet types */
2655 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2656 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2657 | IXGBE_MRQC_RSS_FIELD_IPV6
2658 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2659
2660 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 2661}
2662
bb5a9ad2
NS		 2663/**
2664 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2665 * @adapter: address of board private structure
2666 * @index: index of ring to set
bb5a9ad2 2667 **/
7367096a
AD		 2668static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2669 struct ixgbe_ring *ring)
bb5a9ad2 2670{
bb5a9ad2 2671 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 2672 u32 rscctrl;
edd2ea55 2673 int rx_buf_len;
7367096a
AD		 2674 u16 reg_idx = ring->reg_idx;
2675
2676 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
2677 return;
bb5a9ad2 2678
7367096a
AD		 2679 rx_buf_len = ring->rx_buf_len;
2680 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 2681 rscctrl |= IXGBE_RSCCTL_RSCEN;
2682 /*
2683 * we must limit the number of descriptors so that the
2684 * total size of max desc * buf_len is not greater
2685 * than 65535
2686 */
7367096a 2687 if (ring->flags & IXGBE_RING_RX_PS_ENABLED) {
bb5a9ad2
NS		 2688#if (MAX_SKB_FRAGS > 16)
2689 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2690#elif (MAX_SKB_FRAGS > 8)
2691 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2692#elif (MAX_SKB_FRAGS > 4)
2693 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2694#else
2695 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2696#endif
2697 } else {
2698 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2699 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2700 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2701 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2702 else
2703 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2704 }
7367096a 2705 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 2706}
2707
acd37177
AD		 2708static void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2709 struct ixgbe_ring *ring)
2710{
2711 struct ixgbe_hw *hw = &adapter->hw;
2712 u64 rdba = ring->dma;
2713 u16 reg_idx = ring->reg_idx;
2714
2715 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
2716 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
2717 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
2718 ring->count * sizeof(union ixgbe_adv_rx_desc));
2719 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
2720 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2721 ring->head = IXGBE_RDH(reg_idx);
2722 ring->tail = IXGBE_RDT(reg_idx);
2723}
2724
48654521
AD		 2725static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
2726{
2727 struct ixgbe_hw *hw = &adapter->hw;
2728 int p;
2729
2730 /* PSRTYPE must be initialized in non 82598 adapters */
2731 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2732 IXGBE_PSRTYPE_UDPHDR |
2733 IXGBE_PSRTYPE_IPV4HDR |
2734 IXGBE_PSRTYPE_L2HDR |
2735 IXGBE_PSRTYPE_IPV6HDR;
2736
2737 if (hw->mac.type == ixgbe_mac_82598EB)
2738 return;
2739
2740 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
2741 psrtype |= (adapter->num_rx_queues_per_pool << 29);
2742
2743 for (p = 0; p < adapter->num_rx_pools; p++)
2744 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
2745 psrtype);
2746}
2747
f5b4a52e
AD		 2748static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
2749{
2750 struct ixgbe_hw *hw = &adapter->hw;
2751 u32 gcr_ext;
2752 u32 vt_reg_bits;
2753 u32 reg_offset, vf_shift;
2754 u32 vmdctl;
2755
2756 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2757 return;
2758
2759 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2760 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
2761 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
2762 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2763
2764 vf_shift = adapter->num_vfs % 32;
2765 reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
2766
2767 /* Enable only the PF's pool for Tx/Rx */
2768 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2769 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
2770 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2771 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
2772 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2773
2774 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
2775 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2776
2777 /*
2778 * Set up VF register offsets for selected VT Mode,
2779 * i.e. 32 or 64 VFs for SR-IOV
2780 */
2781 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2782 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
2783 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
2784 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
2785
2786 /* enable Tx loopback for VF/PF communication */
2787 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2788}
2789
477de6ed 2790static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 2791{
9a799d71
AK		 2792 struct ixgbe_hw *hw = &adapter->hw;
2793 struct net_device *netdev = adapter->netdev;
2794 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
7c6e0a43 2795 int rx_buf_len;
477de6ed
AD		 2796 struct ixgbe_ring *rx_ring;
2797 int i;
2798 u32 mhadd, hlreg0;
48654521 2799
9a799d71 2800 /* Decide whether to use packet split mode or not */
1cdd1ec8
GR		 2801 /* Do not use packet split if we're in SR-IOV Mode */
2802 if (!adapter->num_vfs)
2803 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
9a799d71
AK		 2804
2805 /* Set the RX buffer length according to the mode */
2806 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 2807 rx_buf_len = IXGBE_RX_HDR_SIZE;
9a799d71 2808 } else {
0c19d6af 2809 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
f8212f97 2810 (netdev->mtu <= ETH_DATA_LEN))
7c6e0a43 2811 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 2812 else
477de6ed 2813 rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
9a799d71
AK		 2814 }
2815
63f39bd1 2816#ifdef IXGBE_FCOE
477de6ed
AD		 2817 /* adjust max frame to be able to do baby jumbo for FCoE */
2818 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
2819 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2820 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 2821
477de6ed
AD		 2822#endif /* IXGBE_FCOE */
2823 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2824 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2825 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2826 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2827
2828 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2829 }
2830
2831 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2832 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
2833 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2834 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 2835
0cefafad
JB		 2836 /*
2837 * Setup the HW Rx Head and Tail Descriptor Pointers and
2838 * the Base and Length of the Rx Descriptor Ring
2839 */
9a799d71 2840 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 2841 rx_ring = adapter->rx_ring[i];
a6616b42 2842 rx_ring->rx_buf_len = rx_buf_len;
cc41ac7c 2843
6e455b89
YZ		 2844 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2845 rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
1b3ff02e
PWJ		 2846 else
2847 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
cc41ac7c 2848
63f39bd1 2849#ifdef IXGBE_FCOE
477de6ed
AD		 2850 if (netdev->features & NETIF_F_FCOE_MTU)
2851 {
63f39bd1
YZ		 2852 struct ixgbe_ring_feature *f;
2853 f = &adapter->ring_feature[RING_F_FCOE];
6e455b89
YZ		 2854 if ((i >= f->mask) && (i < f->mask + f->indices)) {
2855 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2856 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2857 rx_ring->rx_buf_len =
2858 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2859 }
63f39bd1 2860 }
63f39bd1 2861#endif /* IXGBE_FCOE */
477de6ed
AD		 2862 }
2863
2864}
2865
7367096a
AD		 2866static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
2867{
2868 struct ixgbe_hw *hw = &adapter->hw;
2869 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2870
2871 switch (hw->mac.type) {
2872 case ixgbe_mac_82598EB:
2873 /*
2874 * For VMDq support of different descriptor types or
2875 * buffer sizes through the use of multiple SRRCTL
2876 * registers, RDRXCTL.MVMEN must be set to 1
2877 *
2878 * also, the manual doesn't mention it clearly but DCA hints
2879 * will only use queue 0's tags unless this bit is set. Side
2880 * effects of setting this bit are only that SRRCTL must be
2881 * fully programmed [0..15]
2882 */
2883 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2884 break;
2885 case ixgbe_mac_82599EB:
2886 /* Disable RSC for ACK packets */
2887 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2888 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2889 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2890 /* hardware requires some bits to be set by default */
2891 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
2892 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2893 break;
2894 default:
2895 /* We should do nothing since we don't know this hardware */
2896 return;
2897 }
2898
2899 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2900}
2901
477de6ed
AD		 2902/**
2903 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
2904 * @adapter: board private structure
2905 *
2906 * Configure the Rx unit of the MAC after a reset.
2907 **/
2908static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2909{
2910 struct ixgbe_hw *hw = &adapter->hw;
2911 struct ixgbe_ring *rx_ring;
2912 int i;
2913 u32 rxctrl;
477de6ed
AD		 2914
2915 /* disable receives while setting up the descriptors */
2916 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2917 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2918
2919 ixgbe_setup_psrtype(adapter);
7367096a 2920 ixgbe_setup_rdrxctl(adapter);
477de6ed 2921
f5b4a52e
AD		 2922 /* Program MRQC for the distribution of queues */
2923 ixgbe_setup_mrqc(adapter);
2924 ixgbe_configure_virtualization(adapter);
2925
477de6ed
AD		 2926 /* set_rx_buffer_len must be called before ring initialization */
2927 ixgbe_set_rx_buffer_len(adapter);
2928
2929 /*
2930 * Setup the HW Rx Head and Tail Descriptor Pointers and
2931 * the Base and Length of the Rx Descriptor Ring
2932 */
2933 for (i = 0; i < adapter->num_rx_queues; i++) {
2934 rx_ring = adapter->rx_ring[i];
acd37177 2935 ixgbe_configure_rx_ring(adapter, rx_ring);
a6616b42 2936 ixgbe_configure_srrctl(adapter, rx_ring);
7367096a 2937 ixgbe_configure_rscctl(adapter, rx_ring);
2f90b865 2938 }
177db6ff 2939
9a799d71
AK		 2940}
2941
068c89b0
DS		 2942static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2943{
2944 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2945 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 2946 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 2947
2948 /* add VID to filter table */
1ada1b1b 2949 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
068c89b0
DS		 2950}
2951
2952static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2953{
2954 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2955 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 2956 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 2957
2958 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2959 ixgbe_irq_disable(adapter);
2960
2961 vlan_group_set_device(adapter->vlgrp, vid, NULL);
2962
2963 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2964 ixgbe_irq_enable(adapter);
2965
2966 /* remove VID from filter table */
1ada1b1b 2967 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
068c89b0
DS		 2968}
2969
5f6c0181
JB		 2970/**
2971 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
2972 * @adapter: driver data
2973 */
2974static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
2975{
2976 struct ixgbe_hw *hw = &adapter->hw;
2977 u32 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2978 int i, j;
2979
2980 switch (hw->mac.type) {
2981 case ixgbe_mac_82598EB:
38e0bd98
YZ		 2982 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2983#ifdef CONFIG_IXGBE_DCB
2984 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
2985 vlnctrl &= ~IXGBE_VLNCTRL_VME;
2986#endif
5f6c0181
JB		 2987 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2988 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2989 break;
2990 case ixgbe_mac_82599EB:
2991 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2992 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2993 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
38e0bd98
YZ		 2994#ifdef CONFIG_IXGBE_DCB
2995 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
2996 break;
2997#endif
5f6c0181
JB		 2998 for (i = 0; i < adapter->num_rx_queues; i++) {
2999 j = adapter->rx_ring[i]->reg_idx;
3000 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3001 vlnctrl &= ~IXGBE_RXDCTL_VME;
3002 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3003 }
3004 break;
3005 default:
3006 break;
3007 }
3008}
3009
3010/**
3011 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3012 * @adapter: driver data
3013 */
3014static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3015{
3016 struct ixgbe_hw *hw = &adapter->hw;
3017 u32 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3018 int i, j;
3019
3020 switch (hw->mac.type) {
3021 case ixgbe_mac_82598EB:
3022 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
3023 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3024 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3025 break;
3026 case ixgbe_mac_82599EB:
3027 vlnctrl |= IXGBE_VLNCTRL_VFE;
3028 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3029 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3030 for (i = 0; i < adapter->num_rx_queues; i++) {
3031 j = adapter->rx_ring[i]->reg_idx;
3032 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3033 vlnctrl |= IXGBE_RXDCTL_VME;
3034 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3035 }
3036 break;
3037 default:
3038 break;
3039 }
3040}
3041
9a799d71 3042static void ixgbe_vlan_rx_register(struct net_device *netdev,
b4617240 3043 struct vlan_group *grp)
9a799d71
AK		 3044{
3045 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71 3046
d4f80882
AV		 3047 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3048 ixgbe_irq_disable(adapter);
9a799d71
AK		 3049 adapter->vlgrp = grp;
3050
2f90b865
AD		 3051 /*
3052 * For a DCB driver, always enable VLAN tag stripping so we can
3053 * still receive traffic from a DCB-enabled host even if we're
3054 * not in DCB mode.
3055 */
5f6c0181 3056 ixgbe_vlan_filter_enable(adapter);
dc63d377 3057
e8e26350 3058 ixgbe_vlan_rx_add_vid(netdev, 0);
9a799d71 3059
d4f80882
AV		 3060 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3061 ixgbe_irq_enable(adapter);
9a799d71
AK		 3062}
3063
9a799d71
AK		 3064static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3065{
3066 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
3067
3068 if (adapter->vlgrp) {
3069 u16 vid;
3070 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
3071 if (!vlan_group_get_device(adapter->vlgrp, vid))
3072 continue;
3073 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3074 }
3075 }
3076}
3077
2850062a
AD		 3078/**
3079 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3080 * @netdev: network interface device structure
3081 *
3082 * Writes unicast address list to the RAR table.
3083 * Returns: -ENOMEM on failure/insufficient address space
3084 * 0 on no addresses written
3085 * X on writing X addresses to the RAR table
3086 **/
3087static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3088{
3089 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3090 struct ixgbe_hw *hw = &adapter->hw;
3091 unsigned int vfn = adapter->num_vfs;
3092 unsigned int rar_entries = hw->mac.num_rar_entries - (vfn + 1);
3093 int count = 0;
3094
3095 /* return ENOMEM indicating insufficient memory for addresses */
3096 if (netdev_uc_count(netdev) > rar_entries)
3097 return -ENOMEM;
3098
3099 if (!netdev_uc_empty(netdev) && rar_entries) {
3100 struct netdev_hw_addr *ha;
3101 /* return error if we do not support writing to RAR table */
3102 if (!hw->mac.ops.set_rar)
3103 return -ENOMEM;
3104
3105 netdev_for_each_uc_addr(ha, netdev) {
3106 if (!rar_entries)
3107 break;
3108 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3109 vfn, IXGBE_RAH_AV);
3110 count++;
3111 }
3112 }
3113 /* write the addresses in reverse order to avoid write combining */
3114 for (; rar_entries > 0 ; rar_entries--)
3115 hw->mac.ops.clear_rar(hw, rar_entries);
3116
3117 return count;
3118}
3119
9a799d71 3120/**
2c5645cf 3121 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3122 * @netdev: network interface device structure
3123 *
2c5645cf
CL		 3124 * The set_rx_method entry point is called whenever the unicast/multicast
3125 * address list or the network interface flags are updated. This routine is
3126 * responsible for configuring the hardware for proper unicast, multicast and
3127 * promiscuous mode.
9a799d71 3128 **/
7f870475 3129void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3130{
3131 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3132 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3133 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3134 int count;
9a799d71
AK		 3135
3136 /* Check for Promiscuous and All Multicast modes */
3137
3138 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3139
f5dc442b
AD		 3140 /* set all bits that we expect to always be set */
3141 fctrl |= IXGBE_FCTRL_BAM;
3142 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3143 fctrl |= IXGBE_FCTRL_PMCF;
3144
2850062a
AD		 3145 /* clear the bits we are changing the status of */
3146 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3147
9a799d71 3148 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3149 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3150 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3151 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
5f6c0181
JB		 3152 /* don't hardware filter vlans in promisc mode */
3153 ixgbe_vlan_filter_disable(adapter);
9a799d71 3154 } else {
746b9f02
PM		 3155 if (netdev->flags & IFF_ALLMULTI) {
3156 fctrl |= IXGBE_FCTRL_MPE;
2850062a
AD		 3157 vmolr |= IXGBE_VMOLR_MPE;
3158 } else {
3159 /*
3160 * Write addresses to the MTA, if the attempt fails
3161 * then we should just turn on promiscous mode so
3162 * that we can at least receive multicast traffic
3163 */
3164 hw->mac.ops.update_mc_addr_list(hw, netdev);
3165 vmolr |= IXGBE_VMOLR_ROMPE;
746b9f02 3166 }
5f6c0181 3167 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3168 hw->addr_ctrl.user_set_promisc = false;
2850062a
AD		 3169 /*
3170 * Write addresses to available RAR registers, if there is not
3171 * sufficient space to store all the addresses then enable
3172 * unicast promiscous mode
3173 */
3174 count = ixgbe_write_uc_addr_list(netdev);
3175 if (count < 0) {
3176 fctrl |= IXGBE_FCTRL_UPE;
3177 vmolr |= IXGBE_VMOLR_ROPE;
3178 }
9a799d71
AK		 3179 }
3180
2850062a 3181 if (adapter->num_vfs) {
1cdd1ec8 3182 ixgbe_restore_vf_multicasts(adapter);
2850062a
AD		 3183 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3184 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3185 IXGBE_VMOLR_ROPE);
3186 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3187 }
3188
3189 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
9a799d71
AK		 3190}
3191
021230d4
AV		 3192static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3193{
3194 int q_idx;
3195 struct ixgbe_q_vector *q_vector;
3196 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3197
3198 /* legacy and MSI only use one vector */
3199 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3200 q_vectors = 1;
3201
3202 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 3203 struct napi_struct *napi;
7a921c93 3204 q_vector = adapter->q_vector[q_idx];
f0848276 3205 napi = &q_vector->napi;
91281fd3
AD		 3206 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3207 if (!q_vector->rxr_count || !q_vector->txr_count) {
3208 if (q_vector->txr_count == 1)
3209 napi->poll = &ixgbe_clean_txonly;
3210 else if (q_vector->rxr_count == 1)
3211 napi->poll = &ixgbe_clean_rxonly;
3212 }
3213 }
f0848276
JB		 3214
3215 napi_enable(napi);
021230d4
AV		 3216 }
3217}
3218
3219static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3220{
3221 int q_idx;
3222 struct ixgbe_q_vector *q_vector;
3223 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3224
3225 /* legacy and MSI only use one vector */
3226 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3227 q_vectors = 1;
3228
3229 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 3230 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 3231 napi_disable(&q_vector->napi);
3232 }
3233}
3234
7a6b6f51 3235#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3236/*
3237 * ixgbe_configure_dcb - Configure DCB hardware
3238 * @adapter: ixgbe adapter struct
3239 *
3240 * This is called by the driver on open to configure the DCB hardware.
3241 * This is also called by the gennetlink interface when reconfiguring
3242 * the DCB state.
3243 */
3244static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3245{
3246 struct ixgbe_hw *hw = &adapter->hw;
5f6c0181 3247 u32 txdctl;
2f90b865
AD		 3248 int i, j;
3249
67ebd791
AD		 3250 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3251 if (hw->mac.type == ixgbe_mac_82598EB)
3252 netif_set_gso_max_size(adapter->netdev, 65536);
3253 return;
3254 }
3255
3256 if (hw->mac.type == ixgbe_mac_82598EB)
3257 netif_set_gso_max_size(adapter->netdev, 32768);
3258
2f90b865
AD		 3259 ixgbe_dcb_check_config(&adapter->dcb_cfg);
3260 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
3261 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
3262
3263 /* reconfigure the hardware */
3264 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
3265
3266 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 3267 j = adapter->tx_ring[i]->reg_idx;
2f90b865
AD		 3268 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3269 /* PThresh workaround for Tx hang with DFP enabled. */
3270 txdctl |= 32;
3271 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
3272 }
3273 /* Enable VLAN tag insert/strip */
5f6c0181
JB		 3274 ixgbe_vlan_filter_enable(adapter);
3275
2f90b865
AD		 3276 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3277}
3278
3279#endif
9a799d71
AK		 3280static void ixgbe_configure(struct ixgbe_adapter *adapter)
3281{
3282 struct net_device *netdev = adapter->netdev;
c4cf55e5 3283 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 3284 int i;
3285
2c5645cf 3286 ixgbe_set_rx_mode(netdev);
9a799d71
AK		 3287
3288 ixgbe_restore_vlan(adapter);
7a6b6f51 3289#ifdef CONFIG_IXGBE_DCB
67ebd791 3290 ixgbe_configure_dcb(adapter);
2f90b865 3291#endif
9a799d71 3292
eacd73f7
YZ		 3293#ifdef IXGBE_FCOE
3294 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3295 ixgbe_configure_fcoe(adapter);
3296
3297#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 3298 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3299 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 3300 adapter->tx_ring[i]->atr_sample_rate =
c4cf55e5
PWJ		 3301 adapter->atr_sample_rate;
3302 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3303 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3304 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3305 }
3306
9a799d71
AK		 3307 ixgbe_configure_tx(adapter);
3308 ixgbe_configure_rx(adapter);
3309 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0
PW		 3310 ixgbe_alloc_rx_buffers(adapter, adapter->rx_ring[i],
3311 (adapter->rx_ring[i]->count - 1));
9a799d71
AK		 3312}
3313
e8e26350
PW		 3314static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3315{
3316 switch (hw->phy.type) {
3317 case ixgbe_phy_sfp_avago:
3318 case ixgbe_phy_sfp_ftl:
3319 case ixgbe_phy_sfp_intel:
3320 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 3321 case ixgbe_phy_sfp_passive_tyco:
3322 case ixgbe_phy_sfp_passive_unknown:
3323 case ixgbe_phy_sfp_active_unknown:
3324 case ixgbe_phy_sfp_ftl_active:
e8e26350
PW		 3325 return true;
3326 default:
3327 return false;
3328 }
3329}
3330
0ecc061d 3331/**
e8e26350
PW		 3332 * ixgbe_sfp_link_config - set up SFP+ link
3333 * @adapter: pointer to private adapter struct
3334 **/
3335static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3336{
3337 struct ixgbe_hw *hw = &adapter->hw;
3338
3339 if (hw->phy.multispeed_fiber) {
3340 /*
3341 * In multispeed fiber setups, the device may not have
3342 * had a physical connection when the driver loaded.
3343 * If that's the case, the initial link configuration
3344 * couldn't get the MAC into 10G or 1G mode, so we'll
3345 * never have a link status change interrupt fire.
3346 * We need to try and force an autonegotiation
3347 * session, then bring up link.
3348 */
3349 hw->mac.ops.setup_sfp(hw);
3350 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
3351 schedule_work(&adapter->multispeed_fiber_task);
3352 } else {
3353 /*
3354 * Direct Attach Cu and non-multispeed fiber modules
3355 * still need to be configured properly prior to
3356 * attempting link.
3357 */
3358 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
3359 schedule_work(&adapter->sfp_config_module_task);
3360 }
3361}
3362
3363/**
3364 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 3365 * @hw: pointer to private hardware struct
3366 *
3367 * Returns 0 on success, negative on failure
3368 **/
e8e26350 3369static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 3370{
3371 u32 autoneg;
8620a103 3372 bool negotiation, link_up = false;
0ecc061d
PWJ		 3373 u32 ret = IXGBE_ERR_LINK_SETUP;
3374
3375 if (hw->mac.ops.check_link)
3376 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3377
3378 if (ret)
3379 goto link_cfg_out;
3380
3381 if (hw->mac.ops.get_link_capabilities)
8620a103 3382 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
0ecc061d
PWJ		 3383 if (ret)
3384 goto link_cfg_out;
3385
8620a103
MC		 3386 if (hw->mac.ops.setup_link)
3387 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 3388link_cfg_out:
3389 return ret;
3390}
3391
e8e26350
PW		 3392#define IXGBE_MAX_RX_DESC_POLL 10
3393static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3394 int rxr)
3395{
4a0b9ca0 3396 int j = adapter->rx_ring[rxr]->reg_idx;
e8e26350
PW		 3397 int k;
3398
3399 for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
3400 if (IXGBE_READ_REG(&adapter->hw,
3401 IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
3402 break;
3403 else
3404 msleep(1);
3405 }
3406 if (k >= IXGBE_MAX_RX_DESC_POLL) {
396e799c 3407 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
849c4542 3408 "the polling period\n", rxr);
e8e26350 3409 }
4a0b9ca0
PW		 3410 ixgbe_release_rx_desc(&adapter->hw, adapter->rx_ring[rxr],
3411 (adapter->rx_ring[rxr]->count - 1));
e8e26350
PW		 3412}
3413
a34bcfff 3414static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 3415{
9a799d71 3416 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3417 u32 gpie = 0;
9a799d71 3418
9b471446 3419 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 3420 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3421 IXGBE_GPIE_OCD;
3422 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 3423 /*
3424 * use EIAM to auto-mask when MSI-X interrupt is asserted
3425 * this saves a register write for every interrupt
3426 */
3427 switch (hw->mac.type) {
3428 case ixgbe_mac_82598EB:
3429 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3430 break;
3431 default:
3432 case ixgbe_mac_82599EB:
3433 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3434 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3435 break;
3436 }
3437 } else {
021230d4
AV		 3438 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3439 * specifically only auto mask tx and rx interrupts */
3440 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3441 }
9a799d71 3442
a34bcfff
AD		 3443 /* XXX: to interrupt immediately for EICS writes, enable this */
3444 /* gpie |= IXGBE_GPIE_EIMEN; */
3445
3446 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3447 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3448 gpie |= IXGBE_GPIE_VTMODE_64;
119fc60a
MC		 3449 }
3450
a34bcfff
AD		 3451 /* Enable fan failure interrupt */
3452 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 3453 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 3454
a34bcfff 3455 if (hw->mac.type == ixgbe_mac_82599EB)
e8e26350
PW		 3456 gpie |= IXGBE_SDP1_GPIEN;
3457 gpie |= IXGBE_SDP2_GPIEN;
a34bcfff
AD		 3458
3459 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3460}
3461
3462static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3463{
3464 struct ixgbe_hw *hw = &adapter->hw;
3465 int i, j = 0;
3466 int num_rx_rings = adapter->num_rx_queues;
3467 int err;
2f1860b8 3468 u32 rxdctl;
a34bcfff
AD		 3469 u32 ctrl_ext;
3470
3471 ixgbe_get_hw_control(adapter);
3472 ixgbe_setup_gpie(adapter);
e8e26350 3473
e8e26350 3474 for (i = 0; i < num_rx_rings; i++) {
4a0b9ca0 3475 j = adapter->rx_ring[i]->reg_idx;
021230d4
AV		 3476 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3477 /* enable PTHRESH=32 descriptors (half the internal cache)
3478 * and HTHRESH=0 descriptors (to minimize latency on fetch),
3479 * this also removes a pesky rx_no_buffer_count increment */
3480 rxdctl |= 0x0020;
9a799d71 3481 rxdctl |= IXGBE_RXDCTL_ENABLE;
021230d4 3482 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
e8e26350
PW		 3483 if (hw->mac.type == ixgbe_mac_82599EB)
3484 ixgbe_rx_desc_queue_enable(adapter, i);
9a799d71
AK		 3485 }
3486 /* enable all receives */
3487 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
e8e26350
PW		 3488 if (hw->mac.type == ixgbe_mac_82598EB)
3489 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
3490 else
3491 rxdctl |= IXGBE_RXCTRL_RXEN;
3492 hw->mac.ops.enable_rx_dma(hw, rxdctl);
9a799d71
AK		 3493
3494 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3495 ixgbe_configure_msix(adapter);
3496 else
3497 ixgbe_configure_msi_and_legacy(adapter);
3498
61fac744
PW		 3499 /* enable the optics */
3500 if (hw->phy.multispeed_fiber)
3501 hw->mac.ops.enable_tx_laser(hw);
3502
9a799d71 3503 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 3504 ixgbe_napi_enable_all(adapter);
3505
3506 /* clear any pending interrupts, may auto mask */
3507 IXGBE_READ_REG(hw, IXGBE_EICR);
3508
9a799d71
AK		 3509 ixgbe_irq_enable(adapter);
3510
bf069c97
DS		 3511 /*
3512 * If this adapter has a fan, check to see if we had a failure
3513 * before we enabled the interrupt.
3514 */
3515 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3516 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3517 if (esdp & IXGBE_ESDP_SDP1)
396e799c 3518 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 3519 }
3520
e8e26350
PW		 3521 /*
3522 * For hot-pluggable SFP+ devices, a new SFP+ module may have
19343de2
DS		 3523 * arrived before interrupts were enabled but after probe. Such
3524 * devices wouldn't have their type identified yet. We need to
3525 * kick off the SFP+ module setup first, then try to bring up link.
e8e26350
PW		 3526 * If we're not hot-pluggable SFP+, we just need to configure link
3527 * and bring it up.
3528 */
19343de2
DS		 3529 if (hw->phy.type == ixgbe_phy_unknown) {
3530 err = hw->phy.ops.identify(hw);
3531 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5da43c1a
DS		 3532 /*
3533 * Take the device down and schedule the sfp tasklet
3534 * which will unregister_netdev and log it.
3535 */
19343de2 3536 ixgbe_down(adapter);
5da43c1a 3537 schedule_work(&adapter->sfp_config_module_task);
19343de2
DS		 3538 return err;
3539 }
e8e26350
PW		 3540 }
3541
3542 if (ixgbe_is_sfp(hw)) {
3543 ixgbe_sfp_link_config(adapter);
3544 } else {
3545 err = ixgbe_non_sfp_link_config(hw);
3546 if (err)
396e799c 3547 e_err(probe, "link_config FAILED %d\n", err);
e8e26350 3548 }
0ecc061d 3549
1da100bb 3550 /* enable transmits */
477de6ed 3551 netif_tx_start_all_queues(adapter->netdev);
1da100bb 3552
9a799d71
AK		 3553 /* bring the link up in the watchdog, this could race with our first
3554 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 3555 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3556 adapter->link_check_timeout = jiffies;
9a799d71 3557 mod_timer(&adapter->watchdog_timer, jiffies);
c9205697
GR		 3558
3559 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3560 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3561 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3562 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3563
9a799d71
AK		 3564 return 0;
3565}
3566
d4f80882
AV		 3567void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3568{
3569 WARN_ON(in_interrupt());
3570 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3571 msleep(1);
3572 ixgbe_down(adapter);
5809a1ae
GR		 3573 /*
3574 * If SR-IOV enabled then wait a bit before bringing the adapter
3575 * back up to give the VFs time to respond to the reset. The
3576 * two second wait is based upon the watchdog timer cycle in
3577 * the VF driver.
3578 */
3579 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3580 msleep(2000);
d4f80882
AV		 3581 ixgbe_up(adapter);
3582 clear_bit(__IXGBE_RESETTING, &adapter->state);
3583}
3584
9a799d71
AK		 3585int ixgbe_up(struct ixgbe_adapter *adapter)
3586{
3587 /* hardware has been reset, we need to reload some things */
3588 ixgbe_configure(adapter);
3589
3590 return ixgbe_up_complete(adapter);
3591}
3592
3593void ixgbe_reset(struct ixgbe_adapter *adapter)
3594{
c44ade9e 3595 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 3596 int err;
3597
3598 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 3599 switch (err) {
3600 case 0:
3601 case IXGBE_ERR_SFP_NOT_PRESENT:
3602 break;
3603 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 3604 e_dev_err("master disable timed out\n");
da4dd0f7 3605 break;
794caeb2
PWJ		 3606 case IXGBE_ERR_EEPROM_VERSION:
3607 /* We are running on a pre-production device, log a warning */
849c4542
ET		 3608 e_dev_warn("This device is a pre-production adapter/LOM. "
3609 "Please be aware there may be issuesassociated with "
3610 "your hardware. If you are experiencing problems "
3611 "please contact your Intel or hardware "
3612 "representative who provided you with this "
3613 "hardware.\n");
794caeb2 3614 break;
da4dd0f7 3615 default:
849c4542 3616 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 3617 }
9a799d71
AK		 3618
3619 /* reprogram the RAR[0] in case user changed it. */
1cdd1ec8
GR		 3620 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3621 IXGBE_RAH_AV);
9a799d71
AK		 3622}
3623
9a799d71
AK		 3624/**
3625 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3626 * @adapter: board private structure
3627 * @rx_ring: ring to free buffers from
3628 **/
3629static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
b4617240 3630 struct ixgbe_ring *rx_ring)
9a799d71
AK		 3631{
3632 struct pci_dev *pdev = adapter->pdev;
3633 unsigned long size;
3634 unsigned int i;
3635
3636 /* Free all the Rx ring sk_buffs */
3637
3638 for (i = 0; i < rx_ring->count; i++) {
3639 struct ixgbe_rx_buffer *rx_buffer_info;
3640
3641 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3642 if (rx_buffer_info->dma) {
1b507730 3643 dma_unmap_single(&pdev->dev, rx_buffer_info->dma,
b4617240 3644 rx_ring->rx_buf_len,
1b507730 3645 DMA_FROM_DEVICE);
9a799d71
AK		 3646 rx_buffer_info->dma = 0;
3647 }
3648 if (rx_buffer_info->skb) {
f8212f97 3649 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 3650 rx_buffer_info->skb = NULL;
f8212f97
AD		 3651 do {
3652 struct sk_buff *this = skb;
e8171aaa 3653 if (IXGBE_RSC_CB(this)->delay_unmap) {
1b507730
NN		 3654 dma_unmap_single(&pdev->dev,
3655 IXGBE_RSC_CB(this)->dma,
43634e82 3656 rx_ring->rx_buf_len,
1b507730 3657 DMA_FROM_DEVICE);
fd3686a8 3658 IXGBE_RSC_CB(this)->dma = 0;
e8171aaa 3659 IXGBE_RSC_CB(skb)->delay_unmap = false;
fd3686a8 3660 }
f8212f97
AD		 3661 skb = skb->prev;
3662 dev_kfree_skb(this);
3663 } while (skb);
9a799d71
AK		 3664 }
3665 if (!rx_buffer_info->page)
3666 continue;
4f57ca6e 3667 if (rx_buffer_info->page_dma) {
1b507730
NN		 3668 dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
3669 PAGE_SIZE / 2, DMA_FROM_DEVICE);
4f57ca6e
JB		 3670 rx_buffer_info->page_dma = 0;
3671 }
9a799d71
AK		 3672 put_page(rx_buffer_info->page);
3673 rx_buffer_info->page = NULL;
762f4c57 3674 rx_buffer_info->page_offset = 0;
9a799d71
AK		 3675 }
3676
3677 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3678 memset(rx_ring->rx_buffer_info, 0, size);
3679
3680 /* Zero out the descriptor ring */
3681 memset(rx_ring->desc, 0, rx_ring->size);
3682
3683 rx_ring->next_to_clean = 0;
3684 rx_ring->next_to_use = 0;
3685
9891ca7c
JB		 3686 if (rx_ring->head)
3687 writel(0, adapter->hw.hw_addr + rx_ring->head);
3688 if (rx_ring->tail)
3689 writel(0, adapter->hw.hw_addr + rx_ring->tail);
9a799d71
AK		 3690}
3691
3692/**
3693 * ixgbe_clean_tx_ring - Free Tx Buffers
3694 * @adapter: board private structure
3695 * @tx_ring: ring to be cleaned
3696 **/
3697static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
b4617240 3698 struct ixgbe_ring *tx_ring)
9a799d71
AK		 3699{
3700 struct ixgbe_tx_buffer *tx_buffer_info;
3701 unsigned long size;
3702 unsigned int i;
3703
3704 /* Free all the Tx ring sk_buffs */
3705
3706 for (i = 0; i < tx_ring->count; i++) {
3707 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3708 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
3709 }
3710
3711 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3712 memset(tx_ring->tx_buffer_info, 0, size);
3713
3714 /* Zero out the descriptor ring */
3715 memset(tx_ring->desc, 0, tx_ring->size);
3716
3717 tx_ring->next_to_use = 0;
3718 tx_ring->next_to_clean = 0;
3719
9891ca7c
JB		 3720 if (tx_ring->head)
3721 writel(0, adapter->hw.hw_addr + tx_ring->head);
3722 if (tx_ring->tail)
3723 writel(0, adapter->hw.hw_addr + tx_ring->tail);
9a799d71
AK		 3724}
3725
3726/**
021230d4 3727 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 3728 * @adapter: board private structure
3729 **/
021230d4 3730static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3731{
3732 int i;
3733
021230d4 3734 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 3735 ixgbe_clean_rx_ring(adapter, adapter->rx_ring[i]);
9a799d71
AK		 3736}
3737
3738/**
021230d4 3739 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 3740 * @adapter: board private structure
3741 **/
021230d4 3742static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3743{
3744 int i;
3745
021230d4 3746 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 3747 ixgbe_clean_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 3748}
3749
3750void ixgbe_down(struct ixgbe_adapter *adapter)
3751{
3752 struct net_device *netdev = adapter->netdev;
7f821875 3753 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 3754 u32 rxctrl;
7f821875
JB		 3755 u32 txdctl;
3756 int i, j;
9a799d71
AK		 3757
3758 /* signal that we are down to the interrupt handler */
3759 set_bit(__IXGBE_DOWN, &adapter->state);
3760
767081ad
GR		 3761 /* disable receive for all VFs and wait one second */
3762 if (adapter->num_vfs) {
767081ad
GR		 3763 /* ping all the active vfs to let them know we are going down */
3764 ixgbe_ping_all_vfs(adapter);
581d1aa7 3765
767081ad
GR		 3766 /* Disable all VFTE/VFRE TX/RX */
3767 ixgbe_disable_tx_rx(adapter);
581d1aa7
GR		 3768
3769 /* Mark all the VFs as inactive */
3770 for (i = 0 ; i < adapter->num_vfs; i++)
3771 adapter->vfinfo[i].clear_to_send = 0;
767081ad
GR		 3772 }
3773
9a799d71 3774 /* disable receives */
7f821875
JB		 3775 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3776 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 3777
7f821875 3778 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 3779 msleep(10);
3780
7f821875
JB		 3781 netif_tx_stop_all_queues(netdev);
3782
0a1f87cb
DS		 3783 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3784 del_timer_sync(&adapter->sfp_timer);
9a799d71 3785 del_timer_sync(&adapter->watchdog_timer);
cf8280ee 3786 cancel_work_sync(&adapter->watchdog_task);
9a799d71 3787
c0dfb90e
JF		 3788 netif_carrier_off(netdev);
3789 netif_tx_disable(netdev);
3790
3791 ixgbe_irq_disable(adapter);
3792
3793 ixgbe_napi_disable_all(adapter);
3794
c4cf55e5
PWJ		 3795 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3796 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3797 cancel_work_sync(&adapter->fdir_reinit_task);
3798
119fc60a
MC		 3799 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
3800 cancel_work_sync(&adapter->check_overtemp_task);
3801
7f821875
JB		 3802 /* disable transmits in the hardware now that interrupts are off */
3803 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 3804 j = adapter->tx_ring[i]->reg_idx;
7f821875
JB		 3805 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3806 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
3807 (txdctl & ~IXGBE_TXDCTL_ENABLE));
3808 }
88512539
PW		 3809 /* Disable the Tx DMA engine on 82599 */
3810 if (hw->mac.type == ixgbe_mac_82599EB)
3811 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3812 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3813 ~IXGBE_DMATXCTL_TE));
7f821875 3814
9f756f01
JF		 3815 /* power down the optics */
3816 if (hw->phy.multispeed_fiber)
3817 hw->mac.ops.disable_tx_laser(hw);
3818
9a713e7c
PW		 3819 /* clear n-tuple filters that are cached */
3820 ethtool_ntuple_flush(netdev);
3821
6f4a0e45
PL		 3822 if (!pci_channel_offline(adapter->pdev))
3823 ixgbe_reset(adapter);
9a799d71
AK		 3824 ixgbe_clean_all_tx_rings(adapter);
3825 ixgbe_clean_all_rx_rings(adapter);
3826
5dd2d332 3827#ifdef CONFIG_IXGBE_DCA
96b0e0f6 3828 /* since we reset the hardware DCA settings were cleared */
e35ec126 3829 ixgbe_setup_dca(adapter);
96b0e0f6 3830#endif
9a799d71
AK		 3831}
3832
9a799d71 3833/**
021230d4
AV		 3834 * ixgbe_poll - NAPI Rx polling callback
3835 * @napi: structure for representing this polling device
3836 * @budget: how many packets driver is allowed to clean
3837 *
3838 * This function is used for legacy and MSI, NAPI mode
9a799d71 3839 **/
021230d4 3840static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 3841{
9a1a69ad
JB		 3842 struct ixgbe_q_vector *q_vector =
3843 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 3844 struct ixgbe_adapter *adapter = q_vector->adapter;
9a1a69ad 3845 int tx_clean_complete, work_done = 0;
9a799d71 3846
5dd2d332 3847#ifdef CONFIG_IXGBE_DCA
bd0362dd 3848 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
4a0b9ca0
PW		 3849 ixgbe_update_tx_dca(adapter, adapter->tx_ring[0]);
3850 ixgbe_update_rx_dca(adapter, adapter->rx_ring[0]);
bd0362dd
JC		 3851 }
3852#endif
3853
4a0b9ca0
PW		 3854 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
3855 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
9a799d71 3856
9a1a69ad 3857 if (!tx_clean_complete)
d2c7ddd6
DM		 3858 work_done = budget;
3859
53e52c72
DM		 3860 /* If budget not fully consumed, exit the polling mode */
3861 if (work_done < budget) {
288379f0 3862 napi_complete(napi);
f7554a2b 3863 if (adapter->rx_itr_setting & 1)
f494e8fa 3864 ixgbe_set_itr(adapter);
d4f80882 3865 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 3866 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
9a799d71 3867 }
9a799d71
AK		 3868 return work_done;
3869}
3870
3871/**
3872 * ixgbe_tx_timeout - Respond to a Tx Hang
3873 * @netdev: network interface device structure
3874 **/
3875static void ixgbe_tx_timeout(struct net_device *netdev)
3876{
3877 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3878
3879 /* Do the reset outside of interrupt context */
3880 schedule_work(&adapter->reset_task);
3881}
3882
3883static void ixgbe_reset_task(struct work_struct *work)
3884{
3885 struct ixgbe_adapter *adapter;
3886 adapter = container_of(work, struct ixgbe_adapter, reset_task);
3887
2f90b865
AD		 3888 /* If we're already down or resetting, just bail */
3889 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3890 test_bit(__IXGBE_RESETTING, &adapter->state))
3891 return;
3892
9a799d71
AK		 3893 adapter->tx_timeout_count++;
3894
dcd79aeb
TI		 3895 ixgbe_dump(adapter);
3896 netdev_err(adapter->netdev, "Reset adapter\n");
d4f80882 3897 ixgbe_reinit_locked(adapter);
9a799d71
AK		 3898}
3899
bc97114d
PWJ		 3900#ifdef CONFIG_IXGBE_DCB
3901static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
b9804972 3902{
bc97114d 3903 bool ret = false;
0cefafad 3904 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
b9804972 3905
0cefafad
JB		 3906 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3907 return ret;
3908
3909 f->mask = 0x7 << 3;
3910 adapter->num_rx_queues = f->indices;
3911 adapter->num_tx_queues = f->indices;
3912 ret = true;
2f90b865 3913
bc97114d
PWJ		 3914 return ret;
3915}
3916#endif
3917
4df10466
JB		 3918/**
3919 * ixgbe_set_rss_queues: Allocate queues for RSS
3920 * @adapter: board private structure to initialize
3921 *
3922 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
3923 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3924 *
3925 **/
bc97114d
PWJ		 3926static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3927{
3928 bool ret = false;
0cefafad 3929 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
bc97114d
PWJ		 3930
3931 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
0cefafad
JB		 3932 f->mask = 0xF;
3933 adapter->num_rx_queues = f->indices;
3934 adapter->num_tx_queues = f->indices;
bc97114d
PWJ		 3935 ret = true;
3936 } else {
bc97114d 3937 ret = false;
b9804972
JB		 3938 }
3939
bc97114d
PWJ		 3940 return ret;
3941}
3942
c4cf55e5
PWJ		 3943/**
3944 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3945 * @adapter: board private structure to initialize
3946 *
3947 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3948 * to the original CPU that initiated the Tx session. This runs in addition
3949 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3950 * Rx load across CPUs using RSS.
3951 *
3952 **/
3953static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3954{
3955 bool ret = false;
3956 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3957
3958 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3959 f_fdir->mask = 0;
3960
3961 /* Flow Director must have RSS enabled */
3962 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3963 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3964 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3965 adapter->num_tx_queues = f_fdir->indices;
3966 adapter->num_rx_queues = f_fdir->indices;
3967 ret = true;
3968 } else {
3969 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3970 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3971 }
3972 return ret;
3973}
3974
0331a832
YZ		 3975#ifdef IXGBE_FCOE
3976/**
3977 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3978 * @adapter: board private structure to initialize
3979 *
3980 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3981 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3982 * rx queues out of the max number of rx queues, instead, it is used as the
3983 * index of the first rx queue used by FCoE.
3984 *
3985 **/
3986static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3987{
3988 bool ret = false;
3989 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3990
3991 f->indices = min((int)num_online_cpus(), f->indices);
3992 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
8de8b2e6
YZ		 3993 adapter->num_rx_queues = 1;
3994 adapter->num_tx_queues = 1;
0331a832
YZ		 3995#ifdef CONFIG_IXGBE_DCB
3996 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
396e799c 3997 e_info(probe, "FCoE enabled with DCB\n");
0331a832
YZ		 3998 ixgbe_set_dcb_queues(adapter);
3999 }
4000#endif
4001 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
396e799c 4002 e_info(probe, "FCoE enabled with RSS\n");
8faa2a78
YZ		 4003 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4004 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4005 ixgbe_set_fdir_queues(adapter);
4006 else
4007 ixgbe_set_rss_queues(adapter);
0331a832
YZ		 4008 }
4009 /* adding FCoE rx rings to the end */
4010 f->mask = adapter->num_rx_queues;
4011 adapter->num_rx_queues += f->indices;
8de8b2e6 4012 adapter->num_tx_queues += f->indices;
0331a832
YZ		 4013
4014 ret = true;
4015 }
4016
4017 return ret;
4018}
4019
4020#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 4021/**
4022 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4023 * @adapter: board private structure to initialize
4024 *
4025 * IOV doesn't actually use anything, so just NAK the
4026 * request for now and let the other queue routines
4027 * figure out what to do.
4028 */
4029static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4030{
4031 return false;
4032}
4033
4df10466
JB		 4034/*
4035 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
4036 * @adapter: board private structure to initialize
4037 *
4038 * This is the top level queue allocation routine. The order here is very
4039 * important, starting with the "most" number of features turned on at once,
4040 * and ending with the smallest set of features. This way large combinations
4041 * can be allocated if they're turned on, and smaller combinations are the
4042 * fallthrough conditions.
4043 *
4044 **/
bc97114d
PWJ		 4045static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4046{
1cdd1ec8
GR		 4047 /* Start with base case */
4048 adapter->num_rx_queues = 1;
4049 adapter->num_tx_queues = 1;
4050 adapter->num_rx_pools = adapter->num_rx_queues;
4051 adapter->num_rx_queues_per_pool = 1;
4052
4053 if (ixgbe_set_sriov_queues(adapter))
4054 return;
4055
0331a832
YZ		 4056#ifdef IXGBE_FCOE
4057 if (ixgbe_set_fcoe_queues(adapter))
4058 goto done;
4059
4060#endif /* IXGBE_FCOE */
bc97114d
PWJ		 4061#ifdef CONFIG_IXGBE_DCB
4062 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 4063 goto done;
bc97114d
PWJ		 4064
4065#endif
c4cf55e5
PWJ		 4066 if (ixgbe_set_fdir_queues(adapter))
4067 goto done;
4068
bc97114d 4069 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 4070 goto done;
4071
4072 /* fallback to base case */
4073 adapter->num_rx_queues = 1;
4074 adapter->num_tx_queues = 1;
4075
4076done:
4077 /* Notify the stack of the (possibly) reduced Tx Queue count. */
f0796d5c 4078 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
b9804972
JB		 4079}
4080
021230d4 4081static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
b4617240 4082 int vectors)
021230d4
AV		 4083{
4084 int err, vector_threshold;
4085
4086 /* We'll want at least 3 (vector_threshold):
4087 * 1) TxQ[0] Cleanup
4088 * 2) RxQ[0] Cleanup
4089 * 3) Other (Link Status Change, etc.)
4090 * 4) TCP Timer (optional)
4091 */
4092 vector_threshold = MIN_MSIX_COUNT;
4093
4094 /* The more we get, the more we will assign to Tx/Rx Cleanup
4095 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4096 * Right now, we simply care about how many we'll get; we'll
4097 * set them up later while requesting irq's.
4098 */
4099 while (vectors >= vector_threshold) {
4100 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
b4617240 4101 vectors);
021230d4
AV		 4102 if (!err) /* Success in acquiring all requested vectors. */
4103 break;
4104 else if (err < 0)
4105 vectors = 0; /* Nasty failure, quit now */
4106 else /* err == number of vectors we should try again with */
4107 vectors = err;
4108 }
4109
4110 if (vectors < vector_threshold) {
4111 /* Can't allocate enough MSI-X interrupts? Oh well.
4112 * This just means we'll go with either a single MSI
4113 * vector or fall back to legacy interrupts.
4114 */
849c4542
ET		 4115 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4116 "Unable to allocate MSI-X interrupts\n");
021230d4
AV		 4117 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4118 kfree(adapter->msix_entries);
4119 adapter->msix_entries = NULL;
021230d4
AV		 4120 } else {
4121 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 4122 /*
4123 * Adjust for only the vectors we'll use, which is minimum
4124 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4125 * vectors we were allocated.
4126 */
4127 adapter->num_msix_vectors = min(vectors,
4128 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 4129 }
4130}
4131
021230d4 4132/**
bc97114d 4133 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 4134 * @adapter: board private structure to initialize
4135 *
bc97114d
PWJ		 4136 * Cache the descriptor ring offsets for RSS to the assigned rings.
4137 *
021230d4 4138 **/
bc97114d 4139static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 4140{
bc97114d
PWJ		 4141 int i;
4142 bool ret = false;
4143
4144 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4145 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4146 adapter->rx_ring[i]->reg_idx = i;
bc97114d 4147 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4148 adapter->tx_ring[i]->reg_idx = i;
bc97114d
PWJ		 4149 ret = true;
4150 } else {
4151 ret = false;
4152 }
4153
4154 return ret;
4155}
4156
4157#ifdef CONFIG_IXGBE_DCB
4158/**
4159 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4160 * @adapter: board private structure to initialize
4161 *
4162 * Cache the descriptor ring offsets for DCB to the assigned rings.
4163 *
4164 **/
4165static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4166{
4167 int i;
4168 bool ret = false;
4169 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
4170
4171 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4172 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2f90b865
AD		 4173 /* the number of queues is assumed to be symmetric */
4174 for (i = 0; i < dcb_i; i++) {
4a0b9ca0
PW		 4175 adapter->rx_ring[i]->reg_idx = i << 3;
4176 adapter->tx_ring[i]->reg_idx = i << 2;
2f90b865 4177 }
bc97114d 4178 ret = true;
e8e26350 4179 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
f92ef202
PW		 4180 if (dcb_i == 8) {
4181 /*
4182 * Tx TC0 starts at: descriptor queue 0
4183 * Tx TC1 starts at: descriptor queue 32
4184 * Tx TC2 starts at: descriptor queue 64
4185 * Tx TC3 starts at: descriptor queue 80
4186 * Tx TC4 starts at: descriptor queue 96
4187 * Tx TC5 starts at: descriptor queue 104
4188 * Tx TC6 starts at: descriptor queue 112
4189 * Tx TC7 starts at: descriptor queue 120
4190 *
4191 * Rx TC0-TC7 are offset by 16 queues each
4192 */
4193 for (i = 0; i < 3; i++) {
4a0b9ca0
PW		 4194 adapter->tx_ring[i]->reg_idx = i << 5;
4195 adapter->rx_ring[i]->reg_idx = i << 4;
f92ef202
PW		 4196 }
4197 for ( ; i < 5; i++) {
4a0b9ca0 4198 adapter->tx_ring[i]->reg_idx =
f92ef202 4199 ((i + 2) << 4);
4a0b9ca0 4200 adapter->rx_ring[i]->reg_idx = i << 4;
f92ef202
PW		 4201 }
4202 for ( ; i < dcb_i; i++) {
4a0b9ca0 4203 adapter->tx_ring[i]->reg_idx =
f92ef202 4204 ((i + 8) << 3);
4a0b9ca0 4205 adapter->rx_ring[i]->reg_idx = i << 4;
f92ef202
PW		 4206 }
4207
4208 ret = true;
4209 } else if (dcb_i == 4) {
4210 /*
4211 * Tx TC0 starts at: descriptor queue 0
4212 * Tx TC1 starts at: descriptor queue 64
4213 * Tx TC2 starts at: descriptor queue 96
4214 * Tx TC3 starts at: descriptor queue 112
4215 *
4216 * Rx TC0-TC3 are offset by 32 queues each
4217 */
4a0b9ca0
PW		 4218 adapter->tx_ring[0]->reg_idx = 0;
4219 adapter->tx_ring[1]->reg_idx = 64;
4220 adapter->tx_ring[2]->reg_idx = 96;
4221 adapter->tx_ring[3]->reg_idx = 112;
f92ef202 4222 for (i = 0 ; i < dcb_i; i++)
4a0b9ca0 4223 adapter->rx_ring[i]->reg_idx = i << 5;
f92ef202
PW		 4224
4225 ret = true;
4226 } else {
4227 ret = false;
e8e26350 4228 }
bc97114d
PWJ		 4229 } else {
4230 ret = false;
021230d4 4231 }
bc97114d
PWJ		 4232 } else {
4233 ret = false;
021230d4 4234 }
bc97114d
PWJ		 4235
4236 return ret;
4237}
4238#endif
4239
c4cf55e5
PWJ		 4240/**
4241 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4242 * @adapter: board private structure to initialize
4243 *
4244 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4245 *
4246 **/
4247static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4248{
4249 int i;
4250 bool ret = false;
4251
4252 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4253 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4254 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4255 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4256 adapter->rx_ring[i]->reg_idx = i;
c4cf55e5 4257 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4258 adapter->tx_ring[i]->reg_idx = i;
c4cf55e5
PWJ		 4259 ret = true;
4260 }
4261
4262 return ret;
4263}
4264
0331a832
YZ		 4265#ifdef IXGBE_FCOE
4266/**
4267 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4268 * @adapter: board private structure to initialize
4269 *
4270 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4271 *
4272 */
4273static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4274{
8de8b2e6 4275 int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
0331a832
YZ		 4276 bool ret = false;
4277 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4278
4279 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4280#ifdef CONFIG_IXGBE_DCB
4281 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
8de8b2e6
YZ		 4282 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
4283
0331a832 4284 ixgbe_cache_ring_dcb(adapter);
8de8b2e6 4285 /* find out queues in TC for FCoE */
4a0b9ca0
PW		 4286 fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
4287 fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
8de8b2e6
YZ		 4288 /*
4289 * In 82599, the number of Tx queues for each traffic
4290 * class for both 8-TC and 4-TC modes are:
4291 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4292 * 8 TCs: 32 32 16 16 8 8 8 8
4293 * 4 TCs: 64 64 32 32
4294 * We have max 8 queues for FCoE, where 8 the is
4295 * FCoE redirection table size. If TC for FCoE is
4296 * less than or equal to TC3, we have enough queues
4297 * to add max of 8 queues for FCoE, so we start FCoE
4298 * tx descriptor from the next one, i.e., reg_idx + 1.
4299 * If TC for FCoE is above TC3, implying 8 TC mode,
4300 * and we need 8 for FCoE, we have to take all queues
4301 * in that traffic class for FCoE.
4302 */
4303 if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
4304 fcoe_tx_i--;
0331a832
YZ		 4305 }
4306#endif /* CONFIG_IXGBE_DCB */
4307 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
8faa2a78
YZ		 4308 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4309 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4310 ixgbe_cache_ring_fdir(adapter);
4311 else
4312 ixgbe_cache_ring_rss(adapter);
4313
8de8b2e6
YZ		 4314 fcoe_rx_i = f->mask;
4315 fcoe_tx_i = f->mask;
4316 }
4317 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4a0b9ca0
PW		 4318 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4319 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
0331a832 4320 }
0331a832
YZ		 4321 ret = true;
4322 }
4323 return ret;
4324}
4325
4326#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 4327/**
4328 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4329 * @adapter: board private structure to initialize
4330 *
4331 * SR-IOV doesn't use any descriptor rings but changes the default if
4332 * no other mapping is used.
4333 *
4334 */
4335static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4336{
4a0b9ca0
PW		 4337 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4338 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
1cdd1ec8
GR		 4339 if (adapter->num_vfs)
4340 return true;
4341 else
4342 return false;
4343}
4344
bc97114d
PWJ		 4345/**
4346 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4347 * @adapter: board private structure to initialize
4348 *
4349 * Once we know the feature-set enabled for the device, we'll cache
4350 * the register offset the descriptor ring is assigned to.
4351 *
4352 * Note, the order the various feature calls is important. It must start with
4353 * the "most" features enabled at the same time, then trickle down to the
4354 * least amount of features turned on at once.
4355 **/
4356static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4357{
4358 /* start with default case */
4a0b9ca0
PW		 4359 adapter->rx_ring[0]->reg_idx = 0;
4360 adapter->tx_ring[0]->reg_idx = 0;
bc97114d 4361
1cdd1ec8
GR		 4362 if (ixgbe_cache_ring_sriov(adapter))
4363 return;
4364
0331a832
YZ		 4365#ifdef IXGBE_FCOE
4366 if (ixgbe_cache_ring_fcoe(adapter))
4367 return;
4368
4369#endif /* IXGBE_FCOE */
bc97114d
PWJ		 4370#ifdef CONFIG_IXGBE_DCB
4371 if (ixgbe_cache_ring_dcb(adapter))
4372 return;
4373
4374#endif
c4cf55e5
PWJ		 4375 if (ixgbe_cache_ring_fdir(adapter))
4376 return;
4377
bc97114d
PWJ		 4378 if (ixgbe_cache_ring_rss(adapter))
4379 return;
021230d4
AV		 4380}
4381
9a799d71
AK		 4382/**
4383 * ixgbe_alloc_queues - Allocate memory for all rings
4384 * @adapter: board private structure to initialize
4385 *
4386 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 4387 * number of queues at compile-time. The polling_netdev array is
4388 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 4389 **/
2f90b865 4390static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71
AK		 4391{
4392 int i;
4a0b9ca0 4393 int orig_node = adapter->node;
9a799d71 4394
021230d4 4395 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0
PW		 4396 struct ixgbe_ring *ring = adapter->tx_ring[i];
4397 if (orig_node == -1) {
4398 int cur_node = next_online_node(adapter->node);
4399 if (cur_node == MAX_NUMNODES)
4400 cur_node = first_online_node;
4401 adapter->node = cur_node;
4402 }
4403 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4404 adapter->node);
4405 if (!ring)
4406 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4407 if (!ring)
4408 goto err_tx_ring_allocation;
4409 ring->count = adapter->tx_ring_count;
4410 ring->queue_index = i;
4411 ring->numa_node = adapter->node;
4412
4413 adapter->tx_ring[i] = ring;
021230d4 4414 }
b9804972 4415
4a0b9ca0
PW		 4416 /* Restore the adapter's original node */
4417 adapter->node = orig_node;
4418
9a799d71 4419 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 4420 struct ixgbe_ring *ring = adapter->rx_ring[i];
4421 if (orig_node == -1) {
4422 int cur_node = next_online_node(adapter->node);
4423 if (cur_node == MAX_NUMNODES)
4424 cur_node = first_online_node;
4425 adapter->node = cur_node;
4426 }
4427 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4428 adapter->node);
4429 if (!ring)
4430 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4431 if (!ring)
4432 goto err_rx_ring_allocation;
4433 ring->count = adapter->rx_ring_count;
4434 ring->queue_index = i;
4435 ring->numa_node = adapter->node;
4436
4437 adapter->rx_ring[i] = ring;
021230d4
AV		 4438 }
4439
4a0b9ca0
PW		 4440 /* Restore the adapter's original node */
4441 adapter->node = orig_node;
4442
021230d4
AV		 4443 ixgbe_cache_ring_register(adapter);
4444
4445 return 0;
4446
4447err_rx_ring_allocation:
4a0b9ca0
PW		 4448 for (i = 0; i < adapter->num_tx_queues; i++)
4449 kfree(adapter->tx_ring[i]);
021230d4
AV		 4450err_tx_ring_allocation:
4451 return -ENOMEM;
4452}
4453
4454/**
4455 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4456 * @adapter: board private structure to initialize
4457 *
4458 * Attempt to configure the interrupts using the best available
4459 * capabilities of the hardware and the kernel.
4460 **/
feea6a57 4461static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 4462{
8be0e467 4463 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 4464 int err = 0;
4465 int vector, v_budget;
4466
4467 /*
4468 * It's easy to be greedy for MSI-X vectors, but it really
4469 * doesn't do us much good if we have a lot more vectors
4470 * than CPU's. So let's be conservative and only ask for
342bde1b 4471 * (roughly) the same number of vectors as there are CPU's.
021230d4
AV		 4472 */
4473 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
342bde1b 4474 (int)num_online_cpus()) + NON_Q_VECTORS;
021230d4
AV		 4475
4476 /*
4477 * At the same time, hardware can only support a maximum of
8be0e467
PW		 4478 * hw.mac->max_msix_vectors vectors. With features
4479 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4480 * descriptor queues supported by our device. Thus, we cap it off in
4481 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 4482 */
8be0e467 4483 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 4484
4485 /* A failure in MSI-X entry allocation isn't fatal, but it does
4486 * mean we disable MSI-X capabilities of the adapter. */
4487 adapter->msix_entries = kcalloc(v_budget,
b4617240 4488 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 4489 if (adapter->msix_entries) {
4490 for (vector = 0; vector < v_budget; vector++)
4491 adapter->msix_entries[vector].entry = vector;
021230d4 4492
7a921c93 4493 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 4494
7a921c93
AD		 4495 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4496 goto out;
4497 }
26d27844 4498
7a921c93
AD		 4499 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4500 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
c4cf55e5
PWJ		 4501 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4502 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4503 adapter->atr_sample_rate = 0;
1cdd1ec8
GR		 4504 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4505 ixgbe_disable_sriov(adapter);
4506
7a921c93 4507 ixgbe_set_num_queues(adapter);
021230d4 4508
021230d4
AV		 4509 err = pci_enable_msi(adapter->pdev);
4510 if (!err) {
4511 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4512 } else {
849c4542
ET		 4513 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4514 "Unable to allocate MSI interrupt, "
4515 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 4516 /* reset err */
4517 err = 0;
4518 }
4519
4520out:
021230d4
AV		 4521 return err;
4522}
4523
7a921c93
AD		 4524/**
4525 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4526 * @adapter: board private structure to initialize
4527 *
4528 * We allocate one q_vector per queue interrupt. If allocation fails we
4529 * return -ENOMEM.
4530 **/
4531static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4532{
4533 int q_idx, num_q_vectors;
4534 struct ixgbe_q_vector *q_vector;
4535 int napi_vectors;
4536 int (*poll)(struct napi_struct *, int);
4537
4538 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4539 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4540 napi_vectors = adapter->num_rx_queues;
91281fd3 4541 poll = &ixgbe_clean_rxtx_many;
7a921c93
AD		 4542 } else {
4543 num_q_vectors = 1;
4544 napi_vectors = 1;
4545 poll = &ixgbe_poll;
4546 }
4547
4548 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
1a6c14a2
JB		 4549 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4550 GFP_KERNEL, adapter->node);
4551 if (!q_vector)
4552 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4553 GFP_KERNEL);
7a921c93
AD		 4554 if (!q_vector)
4555 goto err_out;
4556 q_vector->adapter = adapter;
f7554a2b
NS		 4557 if (q_vector->txr_count && !q_vector->rxr_count)
4558 q_vector->eitr = adapter->tx_eitr_param;
4559 else
4560 q_vector->eitr = adapter->rx_eitr_param;
fe49f04a 4561 q_vector->v_idx = q_idx;
91281fd3 4562 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
7a921c93
AD		 4563 adapter->q_vector[q_idx] = q_vector;
4564 }
4565
4566 return 0;
4567
4568err_out:
4569 while (q_idx) {
4570 q_idx--;
4571 q_vector = adapter->q_vector[q_idx];
4572 netif_napi_del(&q_vector->napi);
4573 kfree(q_vector);
4574 adapter->q_vector[q_idx] = NULL;
4575 }
4576 return -ENOMEM;
4577}
4578
4579/**
4580 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4581 * @adapter: board private structure to initialize
4582 *
4583 * This function frees the memory allocated to the q_vectors. In addition if
4584 * NAPI is enabled it will delete any references to the NAPI struct prior
4585 * to freeing the q_vector.
4586 **/
4587static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4588{
4589 int q_idx, num_q_vectors;
7a921c93 4590
91281fd3 4591 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 4592 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 4593 else
7a921c93 4594 num_q_vectors = 1;
7a921c93
AD		 4595
4596 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4597 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
7a921c93 4598 adapter->q_vector[q_idx] = NULL;
91281fd3 4599 netif_napi_del(&q_vector->napi);
7a921c93
AD		 4600 kfree(q_vector);
4601 }
4602}
4603
7b25cdba 4604static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 4605{
4606 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4607 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4608 pci_disable_msix(adapter->pdev);
4609 kfree(adapter->msix_entries);
4610 adapter->msix_entries = NULL;
4611 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4612 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4613 pci_disable_msi(adapter->pdev);
4614 }
021230d4
AV		 4615}
4616
4617/**
4618 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4619 * @adapter: board private structure to initialize
4620 *
4621 * We determine which interrupt scheme to use based on...
4622 * - Kernel support (MSI, MSI-X)
4623 * - which can be user-defined (via MODULE_PARAM)
4624 * - Hardware queue count (num_*_queues)
4625 * - defined by miscellaneous hardware support/features (RSS, etc.)
4626 **/
2f90b865 4627int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 4628{
4629 int err;
4630
4631 /* Number of supported queues */
4632 ixgbe_set_num_queues(adapter);
4633
021230d4
AV		 4634 err = ixgbe_set_interrupt_capability(adapter);
4635 if (err) {
849c4542 4636 e_dev_err("Unable to setup interrupt capabilities\n");
021230d4 4637 goto err_set_interrupt;
9a799d71
AK		 4638 }
4639
7a921c93
AD		 4640 err = ixgbe_alloc_q_vectors(adapter);
4641 if (err) {
849c4542 4642 e_dev_err("Unable to allocate memory for queue vectors\n");
7a921c93
AD		 4643 goto err_alloc_q_vectors;
4644 }
4645
4646 err = ixgbe_alloc_queues(adapter);
4647 if (err) {
849c4542 4648 e_dev_err("Unable to allocate memory for queues\n");
7a921c93
AD		 4649 goto err_alloc_queues;
4650 }
4651
849c4542 4652 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
396e799c
ET		 4653 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4654 adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 4655
4656 set_bit(__IXGBE_DOWN, &adapter->state);
4657
9a799d71 4658 return 0;
021230d4 4659
7a921c93
AD		 4660err_alloc_queues:
4661 ixgbe_free_q_vectors(adapter);
4662err_alloc_q_vectors:
4663 ixgbe_reset_interrupt_capability(adapter);
021230d4 4664err_set_interrupt:
7a921c93
AD		 4665 return err;
4666}
4667
4668/**
4669 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4670 * @adapter: board private structure to clear interrupt scheme on
4671 *
4672 * We go through and clear interrupt specific resources and reset the structure
4673 * to pre-load conditions
4674 **/
4675void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4676{
4a0b9ca0
PW		 4677 int i;
4678
4679 for (i = 0; i < adapter->num_tx_queues; i++) {
4680 kfree(adapter->tx_ring[i]);
4681 adapter->tx_ring[i] = NULL;
4682 }
4683 for (i = 0; i < adapter->num_rx_queues; i++) {
4684 kfree(adapter->rx_ring[i]);
4685 adapter->rx_ring[i] = NULL;
4686 }
7a921c93
AD		 4687
4688 ixgbe_free_q_vectors(adapter);
4689 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 4690}
4691
c4900be0
DS		 4692/**
4693 * ixgbe_sfp_timer - worker thread to find a missing module
4694 * @data: pointer to our adapter struct
4695 **/
4696static void ixgbe_sfp_timer(unsigned long data)
4697{
4698 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4699
4df10466
JB		 4700 /*
4701 * Do the sfp_timer outside of interrupt context due to the
c4900be0
DS		 4702 * delays that sfp+ detection requires
4703 */
4704 schedule_work(&adapter->sfp_task);
4705}
4706
4707/**
4708 * ixgbe_sfp_task - worker thread to find a missing module
4709 * @work: pointer to work_struct containing our data
4710 **/
4711static void ixgbe_sfp_task(struct work_struct *work)
4712{
4713 struct ixgbe_adapter *adapter = container_of(work,
4714 struct ixgbe_adapter,
4715 sfp_task);
4716 struct ixgbe_hw *hw = &adapter->hw;
4717
4718 if ((hw->phy.type == ixgbe_phy_nl) &&
4719 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
4720 s32 ret = hw->phy.ops.identify_sfp(hw);
63d6e1d8 4721 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
c4900be0
DS		 4722 goto reschedule;
4723 ret = hw->phy.ops.reset(hw);
4724 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
849c4542
ET		 4725 e_dev_err("failed to initialize because an unsupported "
4726 "SFP+ module type was detected.\n");
4727 e_dev_err("Reload the driver after installing a "
4728 "supported module.\n");
c4900be0
DS		 4729 unregister_netdev(adapter->netdev);
4730 } else {
396e799c 4731 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
c4900be0
DS		 4732 }
4733 /* don't need this routine any more */
4734 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4735 }
4736 return;
4737reschedule:
4738 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
4739 mod_timer(&adapter->sfp_timer,
4740 round_jiffies(jiffies + (2 * HZ)));
4741}
4742
9a799d71
AK		 4743/**
4744 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4745 * @adapter: board private structure to initialize
4746 *
4747 * ixgbe_sw_init initializes the Adapter private data structure.
4748 * Fields are initialized based on PCI device information and
4749 * OS network device settings (MTU size).
4750 **/
4751static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4752{
4753 struct ixgbe_hw *hw = &adapter->hw;
4754 struct pci_dev *pdev = adapter->pdev;
9a713e7c 4755 struct net_device *dev = adapter->netdev;
021230d4 4756 unsigned int rss;
7a6b6f51 4757#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4758 int j;
4759 struct tc_configuration *tc;
4760#endif
021230d4 4761
c44ade9e
JB		 4762 /* PCI config space info */
4763
4764 hw->vendor_id = pdev->vendor;
4765 hw->device_id = pdev->device;
4766 hw->revision_id = pdev->revision;
4767 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4768 hw->subsystem_device_id = pdev->subsystem_device;
4769
021230d4
AV		 4770 /* Set capability flags */
4771 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4772 adapter->ring_feature[RING_F_RSS].indices = rss;
4773 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
2f90b865 4774 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
bf069c97
DS		 4775 if (hw->mac.type == ixgbe_mac_82598EB) {
4776 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4777 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 4778 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bf069c97 4779 } else if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 4780 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
0c19d6af
PWJ		 4781 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4782 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
119fc60a
MC		 4783 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4784 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
9a713e7c
PW		 4785 if (dev->features & NETIF_F_NTUPLE) {
4786 /* Flow Director perfect filter enabled */
4787 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4788 adapter->atr_sample_rate = 0;
4789 spin_lock_init(&adapter->fdir_perfect_lock);
4790 } else {
4791 /* Flow Director hash filters enabled */
4792 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4793 adapter->atr_sample_rate = 20;
4794 }
c4cf55e5
PWJ		 4795 adapter->ring_feature[RING_F_FDIR].indices =
4796 IXGBE_MAX_FDIR_INDICES;
c4cf55e5 4797 adapter->fdir_pballoc = 0;
eacd73f7 4798#ifdef IXGBE_FCOE
0d551589
YZ		 4799 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4800 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4801 adapter->ring_feature[RING_F_FCOE].indices = 0;
61a0f421 4802#ifdef CONFIG_IXGBE_DCB
6ee16520
YZ		 4803 /* Default traffic class to use for FCoE */
4804 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
56075a98 4805 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
61a0f421 4806#endif
eacd73f7 4807#endif /* IXGBE_FCOE */
f8212f97 4808 }
2f90b865 4809
7a6b6f51 4810#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4811 /* Configure DCB traffic classes */
4812 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4813 tc = &adapter->dcb_cfg.tc_config[j];
4814 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4815 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4816 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4817 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4818 tc->dcb_pfc = pfc_disabled;
4819 }
4820 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4821 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4822 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
264857b8 4823 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865
AD		 4824 adapter->dcb_cfg.round_robin_enable = false;
4825 adapter->dcb_set_bitmap = 0x00;
4826 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
4827 adapter->ring_feature[RING_F_DCB].indices);
4828
4829#endif
9a799d71
AK		 4830
4831 /* default flow control settings */
cd7664f6 4832 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 4833 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 4834#ifdef CONFIG_DCB
4835 adapter->last_lfc_mode = hw->fc.current_mode;
4836#endif
2b9ade93
JB		 4837 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
4838 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
4839 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4840 hw->fc.send_xon = true;
71fd570b 4841 hw->fc.disable_fc_autoneg = false;
9a799d71 4842
30efa5a3 4843 /* enable itr by default in dynamic mode */
f7554a2b
NS		 4844 adapter->rx_itr_setting = 1;
4845 adapter->rx_eitr_param = 20000;
4846 adapter->tx_itr_setting = 1;
4847 adapter->tx_eitr_param = 10000;
30efa5a3
JB		 4848
4849 /* set defaults for eitr in MegaBytes */
4850 adapter->eitr_low = 10;
4851 adapter->eitr_high = 20;
4852
4853 /* set default ring sizes */
4854 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4855 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4856
9a799d71 4857 /* initialize eeprom parameters */
c44ade9e 4858 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 4859 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 4860 return -EIO;
4861 }
4862
021230d4 4863 /* enable rx csum by default */
9a799d71
AK		 4864 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4865
1a6c14a2
JB		 4866 /* get assigned NUMA node */
4867 adapter->node = dev_to_node(&pdev->dev);
4868
9a799d71
AK		 4869 set_bit(__IXGBE_DOWN, &adapter->state);
4870
4871 return 0;
4872}
4873
4874/**
4875 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4876 * @adapter: board private structure
3a581073 4877 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4878 *
4879 * Return 0 on success, negative on failure
4880 **/
4881int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
e01c31a5 4882 struct ixgbe_ring *tx_ring)
9a799d71
AK		 4883{
4884 struct pci_dev *pdev = adapter->pdev;
4885 int size;
4886
3a581073 4887 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4a0b9ca0 4888 tx_ring->tx_buffer_info = vmalloc_node(size, tx_ring->numa_node);
1a6c14a2
JB		 4889 if (!tx_ring->tx_buffer_info)
4890 tx_ring->tx_buffer_info = vmalloc(size);
e01c31a5
JB		 4891 if (!tx_ring->tx_buffer_info)
4892 goto err;
3a581073 4893 memset(tx_ring->tx_buffer_info, 0, size);
9a799d71
AK		 4894
4895 /* round up to nearest 4K */
12207e49 4896 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 4897 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 4898
1b507730
NN		 4899 tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size,
4900 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 4901 if (!tx_ring->desc)
4902 goto err;
9a799d71 4903
3a581073
JB		 4904 tx_ring->next_to_use = 0;
4905 tx_ring->next_to_clean = 0;
4906 tx_ring->work_limit = tx_ring->count;
9a799d71 4907 return 0;
e01c31a5
JB		 4908
4909err:
4910 vfree(tx_ring->tx_buffer_info);
4911 tx_ring->tx_buffer_info = NULL;
396e799c 4912 e_err(probe, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 4913 return -ENOMEM;
9a799d71
AK		 4914}
4915
69888674
AD		 4916/**
4917 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4918 * @adapter: board private structure
4919 *
4920 * If this function returns with an error, then it's possible one or
4921 * more of the rings is populated (while the rest are not). It is the
4922 * callers duty to clean those orphaned rings.
4923 *
4924 * Return 0 on success, negative on failure
4925 **/
4926static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4927{
4928 int i, err = 0;
4929
4930 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 4931 err = ixgbe_setup_tx_resources(adapter, adapter->tx_ring[i]);
69888674
AD		 4932 if (!err)
4933 continue;
396e799c 4934 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
69888674
AD		 4935 break;
4936 }
4937
4938 return err;
4939}
4940
9a799d71
AK		 4941/**
4942 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4943 * @adapter: board private structure
3a581073 4944 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4945 *
4946 * Returns 0 on success, negative on failure
4947 **/
4948int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
b4617240 4949 struct ixgbe_ring *rx_ring)
9a799d71
AK		 4950{
4951 struct pci_dev *pdev = adapter->pdev;
021230d4 4952 int size;
9a799d71 4953
3a581073 4954 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
1a6c14a2
JB		 4955 rx_ring->rx_buffer_info = vmalloc_node(size, adapter->node);
4956 if (!rx_ring->rx_buffer_info)
4957 rx_ring->rx_buffer_info = vmalloc(size);
3a581073 4958 if (!rx_ring->rx_buffer_info) {
396e799c
ET		 4959 e_err(probe, "vmalloc allocation failed for the Rx "
4960 "descriptor ring\n");
177db6ff 4961 goto alloc_failed;
9a799d71 4962 }
3a581073 4963 memset(rx_ring->rx_buffer_info, 0, size);
9a799d71 4964
9a799d71 4965 /* Round up to nearest 4K */
3a581073
JB		 4966 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4967 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 4968
1b507730
NN		 4969 rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size,
4970 &rx_ring->dma, GFP_KERNEL);
9a799d71 4971
3a581073 4972 if (!rx_ring->desc) {
396e799c
ET		 4973 e_err(probe, "Memory allocation failed for the Rx "
4974 "descriptor ring\n");
3a581073 4975 vfree(rx_ring->rx_buffer_info);
177db6ff 4976 goto alloc_failed;
9a799d71
AK		 4977 }
4978
3a581073
JB		 4979 rx_ring->next_to_clean = 0;
4980 rx_ring->next_to_use = 0;
9a799d71
AK		 4981
4982 return 0;
177db6ff
MC		 4983
4984alloc_failed:
177db6ff 4985 return -ENOMEM;
9a799d71
AK		 4986}
4987
69888674
AD		 4988/**
4989 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4990 * @adapter: board private structure
4991 *
4992 * If this function returns with an error, then it's possible one or
4993 * more of the rings is populated (while the rest are not). It is the
4994 * callers duty to clean those orphaned rings.
4995 *
4996 * Return 0 on success, negative on failure
4997 **/
4998
4999static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5000{
5001 int i, err = 0;
5002
5003 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 5004 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]);
69888674
AD		 5005 if (!err)
5006 continue;
396e799c 5007 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
69888674
AD		 5008 break;
5009 }
5010
5011 return err;
5012}
5013
9a799d71
AK		 5014/**
5015 * ixgbe_free_tx_resources - Free Tx Resources per Queue
5016 * @adapter: board private structure
5017 * @tx_ring: Tx descriptor ring for a specific queue
5018 *
5019 * Free all transmit software resources
5020 **/
c431f97e
JB		 5021void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
5022 struct ixgbe_ring *tx_ring)
9a799d71
AK		 5023{
5024 struct pci_dev *pdev = adapter->pdev;
5025
5026 ixgbe_clean_tx_ring(adapter, tx_ring);
5027
5028 vfree(tx_ring->tx_buffer_info);
5029 tx_ring->tx_buffer_info = NULL;
5030
1b507730
NN		 5031 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
5032 tx_ring->dma);
9a799d71
AK		 5033
5034 tx_ring->desc = NULL;
5035}
5036
5037/**
5038 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5039 * @adapter: board private structure
5040 *
5041 * Free all transmit software resources
5042 **/
5043static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5044{
5045 int i;
5046
5047 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0
PW		 5048 if (adapter->tx_ring[i]->desc)
5049 ixgbe_free_tx_resources(adapter, adapter->tx_ring[i]);
9a799d71
AK		 5050}
5051
5052/**
b4617240 5053 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5054 * @adapter: board private structure
5055 * @rx_ring: ring to clean the resources from
5056 *
5057 * Free all receive software resources
5058 **/
c431f97e
JB		 5059void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
5060 struct ixgbe_ring *rx_ring)
9a799d71
AK		 5061{
5062 struct pci_dev *pdev = adapter->pdev;
5063
5064 ixgbe_clean_rx_ring(adapter, rx_ring);
5065
5066 vfree(rx_ring->rx_buffer_info);
5067 rx_ring->rx_buffer_info = NULL;
5068
1b507730
NN		 5069 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
5070 rx_ring->dma);
9a799d71
AK		 5071
5072 rx_ring->desc = NULL;
5073}
5074
5075/**
5076 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5077 * @adapter: board private structure
5078 *
5079 * Free all receive software resources
5080 **/
5081static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5082{
5083 int i;
5084
5085 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0
PW		 5086 if (adapter->rx_ring[i]->desc)
5087 ixgbe_free_rx_resources(adapter, adapter->rx_ring[i]);
9a799d71
AK		 5088}
5089
9a799d71
AK		 5090/**
5091 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5092 * @netdev: network interface device structure
5093 * @new_mtu: new value for maximum frame size
5094 *
5095 * Returns 0 on success, negative on failure
5096 **/
5097static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5098{
5099 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5100 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5101
42c783c5
JB		 5102 /* MTU < 68 is an error and causes problems on some kernels */
5103 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
9a799d71
AK		 5104 return -EINVAL;
5105
396e799c 5106 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
021230d4 5107 /* must set new MTU before calling down or up */
9a799d71
AK		 5108 netdev->mtu = new_mtu;
5109
d4f80882
AV		 5110 if (netif_running(netdev))
5111 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5112
5113 return 0;
5114}
5115
5116/**
5117 * ixgbe_open - Called when a network interface is made active
5118 * @netdev: network interface device structure
5119 *
5120 * Returns 0 on success, negative value on failure
5121 *
5122 * The open entry point is called when a network interface is made
5123 * active by the system (IFF_UP). At this point all resources needed
5124 * for transmit and receive operations are allocated, the interrupt
5125 * handler is registered with the OS, the watchdog timer is started,
5126 * and the stack is notified that the interface is ready.
5127 **/
5128static int ixgbe_open(struct net_device *netdev)
5129{
5130 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5131 int err;
4bebfaa5
AK		 5132
5133 /* disallow open during test */
5134 if (test_bit(__IXGBE_TESTING, &adapter->state))
5135 return -EBUSY;
9a799d71 5136
54386467
JB		 5137 netif_carrier_off(netdev);
5138
9a799d71
AK		 5139 /* allocate transmit descriptors */
5140 err = ixgbe_setup_all_tx_resources(adapter);
5141 if (err)
5142 goto err_setup_tx;
5143
9a799d71
AK		 5144 /* allocate receive descriptors */
5145 err = ixgbe_setup_all_rx_resources(adapter);
5146 if (err)
5147 goto err_setup_rx;
5148
5149 ixgbe_configure(adapter);
5150
021230d4 5151 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5152 if (err)
5153 goto err_req_irq;
5154
9a799d71
AK		 5155 err = ixgbe_up_complete(adapter);
5156 if (err)
5157 goto err_up;
5158
d55b53ff
JK		 5159 netif_tx_start_all_queues(netdev);
5160
9a799d71
AK		 5161 return 0;
5162
5163err_up:
5eba3699 5164 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5165 ixgbe_free_irq(adapter);
5166err_req_irq:
9a799d71 5167err_setup_rx:
a20a1199 5168 ixgbe_free_all_rx_resources(adapter);
9a799d71 5169err_setup_tx:
a20a1199 5170 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 5171 ixgbe_reset(adapter);
5172
5173 return err;
5174}
5175
5176/**
5177 * ixgbe_close - Disables a network interface
5178 * @netdev: network interface device structure
5179 *
5180 * Returns 0, this is not allowed to fail
5181 *
5182 * The close entry point is called when an interface is de-activated
5183 * by the OS. The hardware is still under the drivers control, but
5184 * needs to be disabled. A global MAC reset is issued to stop the
5185 * hardware, and all transmit and receive resources are freed.
5186 **/
5187static int ixgbe_close(struct net_device *netdev)
5188{
5189 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5190
5191 ixgbe_down(adapter);
5192 ixgbe_free_irq(adapter);
5193
5194 ixgbe_free_all_tx_resources(adapter);
5195 ixgbe_free_all_rx_resources(adapter);
5196
5eba3699 5197 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5198
5199 return 0;
5200}
5201
b3c8b4ba
AD		 5202#ifdef CONFIG_PM
5203static int ixgbe_resume(struct pci_dev *pdev)
5204{
5205 struct net_device *netdev = pci_get_drvdata(pdev);
5206 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5207 u32 err;
5208
5209 pci_set_power_state(pdev, PCI_D0);
5210 pci_restore_state(pdev);
656ab817
DS		 5211 /*
5212 * pci_restore_state clears dev->state_saved so call
5213 * pci_save_state to restore it.
5214 */
5215 pci_save_state(pdev);
9ce77666 5216
5217 err = pci_enable_device_mem(pdev);
b3c8b4ba 5218 if (err) {
849c4542 5219 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5220 return err;
5221 }
5222 pci_set_master(pdev);
5223
dd4d8ca6 5224 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 5225
5226 err = ixgbe_init_interrupt_scheme(adapter);
5227 if (err) {
849c4542 5228 e_dev_err("Cannot initialize interrupts for device\n");
b3c8b4ba
AD		 5229 return err;
5230 }
5231
b3c8b4ba
AD		 5232 ixgbe_reset(adapter);
5233
495dce12
WJP		 5234 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5235
b3c8b4ba
AD		 5236 if (netif_running(netdev)) {
5237 err = ixgbe_open(adapter->netdev);
5238 if (err)
5239 return err;
5240 }
5241
5242 netif_device_attach(netdev);
5243
5244 return 0;
5245}
b3c8b4ba 5246#endif /* CONFIG_PM */
9d8d05ae
RW		 5247
5248static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba
AD		 5249{
5250 struct net_device *netdev = pci_get_drvdata(pdev);
5251 struct ixgbe_adapter *adapter = netdev_priv(netdev);
e8e26350
PW		 5252 struct ixgbe_hw *hw = &adapter->hw;
5253 u32 ctrl, fctrl;
5254 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5255#ifdef CONFIG_PM
5256 int retval = 0;
5257#endif
5258
5259 netif_device_detach(netdev);
5260
5261 if (netif_running(netdev)) {
5262 ixgbe_down(adapter);
5263 ixgbe_free_irq(adapter);
5264 ixgbe_free_all_tx_resources(adapter);
5265 ixgbe_free_all_rx_resources(adapter);
5266 }
b3c8b4ba
AD		 5267
5268#ifdef CONFIG_PM
5269 retval = pci_save_state(pdev);
5270 if (retval)
5271 return retval;
4df10466 5272
b3c8b4ba 5273#endif
e8e26350
PW		 5274 if (wufc) {
5275 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5276
e8e26350
PW		 5277 /* turn on all-multi mode if wake on multicast is enabled */
5278 if (wufc & IXGBE_WUFC_MC) {
5279 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5280 fctrl |= IXGBE_FCTRL_MPE;
5281 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5282 }
5283
5284 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5285 ctrl |= IXGBE_CTRL_GIO_DIS;
5286 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5287
5288 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5289 } else {
5290 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5291 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5292 }
5293
dd4d8ca6
DS		 5294 if (wufc && hw->mac.type == ixgbe_mac_82599EB)
5295 pci_wake_from_d3(pdev, true);
5296 else
5297 pci_wake_from_d3(pdev, false);
b3c8b4ba 5298
9d8d05ae
RW		 5299 *enable_wake = !!wufc;
5300
fa378134
AG		 5301 ixgbe_clear_interrupt_scheme(adapter);
5302
b3c8b4ba
AD		 5303 ixgbe_release_hw_control(adapter);
5304
5305 pci_disable_device(pdev);
5306
9d8d05ae
RW		 5307 return 0;
5308}
5309
5310#ifdef CONFIG_PM
5311static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5312{
5313 int retval;
5314 bool wake;
5315
5316 retval = __ixgbe_shutdown(pdev, &wake);
5317 if (retval)
5318 return retval;
5319
5320 if (wake) {
5321 pci_prepare_to_sleep(pdev);
5322 } else {
5323 pci_wake_from_d3(pdev, false);
5324 pci_set_power_state(pdev, PCI_D3hot);
5325 }
b3c8b4ba
AD		 5326
5327 return 0;
5328}
9d8d05ae 5329#endif /* CONFIG_PM */
b3c8b4ba
AD		 5330
5331static void ixgbe_shutdown(struct pci_dev *pdev)
5332{
9d8d05ae
RW		 5333 bool wake;
5334
5335 __ixgbe_shutdown(pdev, &wake);
5336
5337 if (system_state == SYSTEM_POWER_OFF) {
5338 pci_wake_from_d3(pdev, wake);
5339 pci_set_power_state(pdev, PCI_D3hot);
5340 }
b3c8b4ba
AD		 5341}
5342
9a799d71
AK		 5343/**
5344 * ixgbe_update_stats - Update the board statistics counters.
5345 * @adapter: board private structure
5346 **/
5347void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5348{
2d86f139 5349 struct net_device *netdev = adapter->netdev;
9a799d71 5350 struct ixgbe_hw *hw = &adapter->hw;
6f11eef7
AV		 5351 u64 total_mpc = 0;
5352 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
eb985f09 5353 u64 non_eop_descs = 0, restart_queue = 0;
9a799d71 5354
d08935c2
DS		 5355 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5356 test_bit(__IXGBE_RESETTING, &adapter->state))
5357 return;
5358
94b982b2 5359 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5360 u64 rsc_count = 0;
94b982b2 5361 u64 rsc_flush = 0;
d51019a4
PW		 5362 for (i = 0; i < 16; i++)
5363 adapter->hw_rx_no_dma_resources +=
5364 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
94b982b2 5365 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 5366 rsc_count += adapter->rx_ring[i]->rsc_count;
5367 rsc_flush += adapter->rx_ring[i]->rsc_flush;
94b982b2
MC		 5368 }
5369 adapter->rsc_total_count = rsc_count;
5370 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5371 }
5372
7ca3bc58
JB		 5373 /* gather some stats to the adapter struct that are per queue */
5374 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5375 restart_queue += adapter->tx_ring[i]->restart_queue;
eb985f09 5376 adapter->restart_queue = restart_queue;
7ca3bc58
JB		 5377
5378 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5379 non_eop_descs += adapter->rx_ring[i]->non_eop_descs;
eb985f09 5380 adapter->non_eop_descs = non_eop_descs;
7ca3bc58 5381
9a799d71 5382 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 5383 for (i = 0; i < 8; i++) {
5384 /* for packet buffers not used, the register should read 0 */
5385 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5386 missed_rx += mpc;
5387 adapter->stats.mpc[i] += mpc;
5388 total_mpc += adapter->stats.mpc[i];
e8e26350
PW		 5389 if (hw->mac.type == ixgbe_mac_82598EB)
5390 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2f90b865
AD		 5391 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5392 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5393 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5394 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
e8e26350
PW		 5395 if (hw->mac.type == ixgbe_mac_82599EB) {
5396 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
5397 IXGBE_PXONRXCNT(i));
5398 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
5399 IXGBE_PXOFFRXCNT(i));
5400 adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
e8e26350
PW		 5401 } else {
5402 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
5403 IXGBE_PXONRXC(i));
5404 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
5405 IXGBE_PXOFFRXC(i));
5406 }
2f90b865
AD		 5407 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
5408 IXGBE_PXONTXC(i));
2f90b865 5409 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
e8e26350 5410 IXGBE_PXOFFTXC(i));
6f11eef7
AV		 5411 }
5412 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5413 /* work around hardware counting issue */
5414 adapter->stats.gprc -= missed_rx;
5415
5416 /* 82598 hardware only has a 32 bit counter in the high register */
e8e26350 5417 if (hw->mac.type == ixgbe_mac_82599EB) {
aad71918 5418 u64 tmp;
e8e26350 5419 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
aad71918
BG		 5420 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF; /* 4 high bits of GORC */
5421 adapter->stats.gorc += (tmp << 32);
e8e26350 5422 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
aad71918
BG		 5423 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF; /* 4 high bits of GOTC */
5424 adapter->stats.gotc += (tmp << 32);
e8e26350
PW		 5425 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5426 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5427 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5428 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
c4cf55e5
PWJ		 5429 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5430 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c
YZ		 5431#ifdef IXGBE_FCOE
5432 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5433 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5434 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5435 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5436 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5437 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5438#endif /* IXGBE_FCOE */
e8e26350
PW		 5439 } else {
5440 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5441 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
5442 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5443 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5444 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5445 }
9a799d71
AK		 5446 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5447 adapter->stats.bprc += bprc;
5448 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350
PW		 5449 if (hw->mac.type == ixgbe_mac_82598EB)
5450 adapter->stats.mprc -= bprc;
9a799d71
AK		 5451 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5452 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5453 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5454 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5455 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5456 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5457 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
9a799d71 5458 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7
AV		 5459 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5460 adapter->stats.lxontxc += lxon;
5461 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5462 adapter->stats.lxofftxc += lxoff;
9a799d71
AK		 5463 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5464 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6f11eef7
AV		 5465 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5466 /*
5467 * 82598 errata - tx of flow control packets is included in tx counters
5468 */
5469 xon_off_tot = lxon + lxoff;
5470 adapter->stats.gptc -= xon_off_tot;
5471 adapter->stats.mptc -= xon_off_tot;
5472 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
9a799d71
AK		 5473 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5474 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5475 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
9a799d71
AK		 5476 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5477 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6f11eef7 5478 adapter->stats.ptc64 -= xon_off_tot;
9a799d71
AK		 5479 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5480 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5481 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5482 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5483 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
9a799d71
AK		 5484 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5485
5486 /* Fill out the OS statistics structure */
2d86f139 5487 netdev->stats.multicast = adapter->stats.mprc;
9a799d71
AK		 5488
5489 /* Rx Errors */
2d86f139 5490 netdev->stats.rx_errors = adapter->stats.crcerrs +
b4617240 5491 adapter->stats.rlec;
2d86f139
AK		 5492 netdev->stats.rx_dropped = 0;
5493 netdev->stats.rx_length_errors = adapter->stats.rlec;
5494 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
5495 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5496}
5497
5498/**
5499 * ixgbe_watchdog - Timer Call-back
5500 * @data: pointer to adapter cast into an unsigned long
5501 **/
5502static void ixgbe_watchdog(unsigned long data)
5503{
5504 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
cf8280ee 5505 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 5506 u64 eics = 0;
5507 int i;
cf8280ee 5508
fe49f04a
AD		 5509 /*
5510 * Do the watchdog outside of interrupt context due to the lovely
5511 * delays that some of the newer hardware requires
5512 */
22d5a71b 5513
fe49f04a
AD		 5514 if (test_bit(__IXGBE_DOWN, &adapter->state))
5515 goto watchdog_short_circuit;
22d5a71b 5516
fe49f04a
AD		 5517 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5518 /*
5519 * for legacy and MSI interrupts don't set any bits
5520 * that are enabled for EIAM, because this operation
5521 * would set *both* EIMS and EICS for any bit in EIAM
5522 */
5523 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5524 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5525 goto watchdog_reschedule;
5526 }
5527
5528 /* get one bit for every active tx/rx interrupt vector */
5529 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5530 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5531 if (qv->rxr_count || qv->txr_count)
5532 eics |= ((u64)1 << i);
cf8280ee 5533 }
9a799d71 5534
fe49f04a
AD		 5535 /* Cause software interrupt to ensure rx rings are cleaned */
5536 ixgbe_irq_rearm_queues(adapter, eics);
5537
5538watchdog_reschedule:
5539 /* Reset the timer */
5540 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
5541
5542watchdog_short_circuit:
cf8280ee
JB		 5543 schedule_work(&adapter->watchdog_task);
5544}
5545
e8e26350
PW		 5546/**
5547 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5548 * @work: pointer to work_struct containing our data
5549 **/
5550static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5551{
5552 struct ixgbe_adapter *adapter = container_of(work,
5553 struct ixgbe_adapter,
5554 multispeed_fiber_task);
5555 struct ixgbe_hw *hw = &adapter->hw;
5556 u32 autoneg;
8620a103 5557 bool negotiation;
e8e26350
PW		 5558
5559 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
a1f25324
MC		 5560 autoneg = hw->phy.autoneg_advertised;
5561 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
8620a103 5562 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
1097cd17 5563 hw->mac.autotry_restart = false;
8620a103
MC		 5564 if (hw->mac.ops.setup_link)
5565 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
e8e26350
PW		 5566 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5567 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5568}
5569
5570/**
5571 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5572 * @work: pointer to work_struct containing our data
5573 **/
5574static void ixgbe_sfp_config_module_task(struct work_struct *work)
5575{
5576 struct ixgbe_adapter *adapter = container_of(work,
5577 struct ixgbe_adapter,
5578 sfp_config_module_task);
5579 struct ixgbe_hw *hw = &adapter->hw;
5580 u32 err;
5581
5582 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
63d6e1d8
DS		 5583
5584 /* Time for electrical oscillations to settle down */
5585 msleep(100);
e8e26350 5586 err = hw->phy.ops.identify_sfp(hw);
63d6e1d8 5587
e8e26350 5588 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
849c4542
ET		 5589 e_dev_err("failed to initialize because an unsupported SFP+ "
5590 "module type was detected.\n");
5591 e_dev_err("Reload the driver after installing a supported "
5592 "module.\n");
63d6e1d8 5593 unregister_netdev(adapter->netdev);
e8e26350
PW		 5594 return;
5595 }
5596 hw->mac.ops.setup_sfp(hw);
5597
8d1c3c07 5598 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
e8e26350
PW		 5599 /* This will also work for DA Twinax connections */
5600 schedule_work(&adapter->multispeed_fiber_task);
5601 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
5602}
5603
c4cf55e5
PWJ		 5604/**
5605 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5606 * @work: pointer to work_struct containing our data
5607 **/
5608static void ixgbe_fdir_reinit_task(struct work_struct *work)
5609{
5610 struct ixgbe_adapter *adapter = container_of(work,
5611 struct ixgbe_adapter,
5612 fdir_reinit_task);
5613 struct ixgbe_hw *hw = &adapter->hw;
5614 int i;
5615
5616 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5617 for (i = 0; i < adapter->num_tx_queues; i++)
5618 set_bit(__IXGBE_FDIR_INIT_DONE,
4a0b9ca0 5619 &(adapter->tx_ring[i]->reinit_state));
c4cf55e5 5620 } else {
396e799c 5621 e_err(probe, "failed to finish FDIR re-initialization, "
849c4542 5622 "ignored adding FDIR ATR filters\n");
c4cf55e5
PWJ		 5623 }
5624 /* Done FDIR Re-initialization, enable transmits */
5625 netif_tx_start_all_queues(adapter->netdev);
5626}
5627
10eec955
JF		 5628static DEFINE_MUTEX(ixgbe_watchdog_lock);
5629
cf8280ee 5630/**
69888674
AD		 5631 * ixgbe_watchdog_task - worker thread to bring link up
5632 * @work: pointer to work_struct containing our data
cf8280ee
JB		 5633 **/
5634static void ixgbe_watchdog_task(struct work_struct *work)
5635{
5636 struct ixgbe_adapter *adapter = container_of(work,
5637 struct ixgbe_adapter,
5638 watchdog_task);
5639 struct net_device *netdev = adapter->netdev;
5640 struct ixgbe_hw *hw = &adapter->hw;
10eec955
JF		 5641 u32 link_speed;
5642 bool link_up;
bc59fcda
NS		 5643 int i;
5644 struct ixgbe_ring *tx_ring;
5645 int some_tx_pending = 0;
cf8280ee 5646
10eec955
JF		 5647 mutex_lock(&ixgbe_watchdog_lock);
5648
5649 link_up = adapter->link_up;
5650 link_speed = adapter->link_speed;
cf8280ee
JB		 5651
5652 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
5653 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
264857b8
PWJ		 5654 if (link_up) {
5655#ifdef CONFIG_DCB
5656 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5657 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
620fa036 5658 hw->mac.ops.fc_enable(hw, i);
264857b8 5659 } else {
620fa036 5660 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 5661 }
5662#else
620fa036 5663 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 5664#endif
5665 }
5666
cf8280ee
JB		 5667 if (link_up ||
5668 time_after(jiffies, (adapter->link_check_timeout +
5669 IXGBE_TRY_LINK_TIMEOUT))) {
cf8280ee 5670 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
264857b8 5671 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
cf8280ee
JB		 5672 }
5673 adapter->link_up = link_up;
5674 adapter->link_speed = link_speed;
5675 }
9a799d71
AK		 5676
5677 if (link_up) {
5678 if (!netif_carrier_ok(netdev)) {
e8e26350
PW		 5679 bool flow_rx, flow_tx;
5680
5681 if (hw->mac.type == ixgbe_mac_82599EB) {
5682 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5683 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
078788b6
PWJ		 5684 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5685 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
e8e26350
PW		 5686 } else {
5687 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5688 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
078788b6
PWJ		 5689 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5690 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
e8e26350
PW		 5691 }
5692
396e799c 5693 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
a46e534b 5694 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
849c4542
ET		 5695 "10 Gbps" :
5696 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5697 "1 Gbps" : "unknown speed")),
e8e26350 5698 ((flow_rx && flow_tx) ? "RX/TX" :
849c4542
ET		 5699 (flow_rx ? "RX" :
5700 (flow_tx ? "TX" : "None"))));
9a799d71
AK		 5701
5702 netif_carrier_on(netdev);
9a799d71
AK		 5703 } else {
5704 /* Force detection of hung controller */
5705 adapter->detect_tx_hung = true;
5706 }
5707 } else {
cf8280ee
JB		 5708 adapter->link_up = false;
5709 adapter->link_speed = 0;
9a799d71 5710 if (netif_carrier_ok(netdev)) {
396e799c 5711 e_info(drv, "NIC Link is Down\n");
9a799d71 5712 netif_carrier_off(netdev);
9a799d71
AK		 5713 }
5714 }
5715
bc59fcda
NS		 5716 if (!netif_carrier_ok(netdev)) {
5717 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 5718 tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 5719 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5720 some_tx_pending = 1;
5721 break;
5722 }
5723 }
5724
5725 if (some_tx_pending) {
5726 /* We've lost link, so the controller stops DMA,
5727 * but we've got queued Tx work that's never going
5728 * to get done, so reset controller to flush Tx.
5729 * (Do the reset outside of interrupt context).
5730 */
5731 schedule_work(&adapter->reset_task);
5732 }
5733 }
5734
9a799d71 5735 ixgbe_update_stats(adapter);
10eec955 5736 mutex_unlock(&ixgbe_watchdog_lock);
9a799d71
AK		 5737}
5738
9a799d71 5739static int ixgbe_tso(struct ixgbe_adapter *adapter,
b4617240
PW		 5740 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5741 u32 tx_flags, u8 *hdr_len)
9a799d71
AK		 5742{
5743 struct ixgbe_adv_tx_context_desc *context_desc;
5744 unsigned int i;
5745 int err;
5746 struct ixgbe_tx_buffer *tx_buffer_info;
9f8cdf4f
JB		 5747 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
5748 u32 mss_l4len_idx, l4len;
9a799d71
AK		 5749
5750 if (skb_is_gso(skb)) {
5751 if (skb_header_cloned(skb)) {
5752 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5753 if (err)
5754 return err;
5755 }
5756 l4len = tcp_hdrlen(skb);
5757 *hdr_len += l4len;
5758
8327d000 5759 if (skb->protocol == htons(ETH_P_IP)) {
9a799d71
AK		 5760 struct iphdr *iph = ip_hdr(skb);
5761 iph->tot_len = 0;
5762 iph->check = 0;
5763 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b4617240
PW		 5764 iph->daddr, 0,
5765 IPPROTO_TCP,
5766 0);
8e1e8a47 5767 } else if (skb_is_gso_v6(skb)) {
9a799d71
AK		 5768 ipv6_hdr(skb)->payload_len = 0;
5769 tcp_hdr(skb)->check =
5770 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
b4617240
PW		 5771 &ipv6_hdr(skb)->daddr,
5772 0, IPPROTO_TCP, 0);
9a799d71
AK		 5773 }
5774
5775 i = tx_ring->next_to_use;
5776
5777 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5778 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5779
5780 /* VLAN MACLEN IPLEN */
5781 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5782 vlan_macip_lens |=
5783 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5784 vlan_macip_lens |= ((skb_network_offset(skb)) <<
b4617240 5785 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 5786 *hdr_len += skb_network_offset(skb);
5787 vlan_macip_lens |=
5788 (skb_transport_header(skb) - skb_network_header(skb));
5789 *hdr_len +=
5790 (skb_transport_header(skb) - skb_network_header(skb));
5791 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5792 context_desc->seqnum_seed = 0;
5793
5794 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
9f8cdf4f 5795 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
b4617240 5796 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 5797
8327d000 5798 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 5799 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5800 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5801 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5802
5803 /* MSS L4LEN IDX */
9f8cdf4f 5804 mss_l4len_idx =
9a799d71
AK		 5805 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
5806 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4eeae6fd
PW		 5807 /* use index 1 for TSO */
5808 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 5809 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
5810
5811 tx_buffer_info->time_stamp = jiffies;
5812 tx_buffer_info->next_to_watch = i;
5813
5814 i++;
5815 if (i == tx_ring->count)
5816 i = 0;
5817 tx_ring->next_to_use = i;
5818
5819 return true;
5820 }
5821 return false;
5822}
5823
5824static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
b4617240
PW		 5825 struct ixgbe_ring *tx_ring,
5826 struct sk_buff *skb, u32 tx_flags)
9a799d71
AK		 5827{
5828 struct ixgbe_adv_tx_context_desc *context_desc;
5829 unsigned int i;
5830 struct ixgbe_tx_buffer *tx_buffer_info;
5831 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
5832
5833 if (skb->ip_summed == CHECKSUM_PARTIAL ||
5834 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
5835 i = tx_ring->next_to_use;
5836 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5837 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5838
5839 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5840 vlan_macip_lens |=
5841 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5842 vlan_macip_lens |= (skb_network_offset(skb) <<
b4617240 5843 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 5844 if (skb->ip_summed == CHECKSUM_PARTIAL)
5845 vlan_macip_lens |= (skb_transport_header(skb) -
b4617240 5846 skb_network_header(skb));
9a799d71
AK		 5847
5848 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5849 context_desc->seqnum_seed = 0;
5850
5851 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
b4617240 5852 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71
AK		 5853
5854 if (skb->ip_summed == CHECKSUM_PARTIAL) {
ca553980
GS		 5855 __be16 protocol;
5856
5857 if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
5858 const struct vlan_ethhdr *vhdr =
5859 (const struct vlan_ethhdr *)skb->data;
5860
5861 protocol = vhdr->h_vlan_encapsulated_proto;
5862 } else {
5863 protocol = skb->protocol;
5864 }
5865
5866 switch (protocol) {
09640e63 5867 case cpu_to_be16(ETH_P_IP):
9a799d71 5868 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
41825d71
AK		 5869 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5870 type_tucmd_mlhl |=
b4617240 5871 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 5872 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
5873 type_tucmd_mlhl |=
5874 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 5875 break;
09640e63 5876 case cpu_to_be16(ETH_P_IPV6):
41825d71
AK		 5877 /* XXX what about other V6 headers?? */
5878 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5879 type_tucmd_mlhl |=
b4617240 5880 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 5881 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
5882 type_tucmd_mlhl |=
5883 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 5884 break;
41825d71
AK		 5885 default:
5886 if (unlikely(net_ratelimit())) {
396e799c
ET		 5887 e_warn(probe, "partial checksum "
5888 "but proto=%x!\n",
5889 skb->protocol);
41825d71
AK		 5890 }
5891 break;
5892 }
9a799d71
AK		 5893 }
5894
5895 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4eeae6fd 5896 /* use index zero for tx checksum offload */
9a799d71
AK		 5897 context_desc->mss_l4len_idx = 0;
5898
5899 tx_buffer_info->time_stamp = jiffies;
5900 tx_buffer_info->next_to_watch = i;
9f8cdf4f 5901
9a799d71
AK		 5902 i++;
5903 if (i == tx_ring->count)
5904 i = 0;
5905 tx_ring->next_to_use = i;
5906
5907 return true;
5908 }
9f8cdf4f 5909
9a799d71
AK		 5910 return false;
5911}
5912
5913static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
b4617240 5914 struct ixgbe_ring *tx_ring,
eacd73f7
YZ		 5915 struct sk_buff *skb, u32 tx_flags,
5916 unsigned int first)
9a799d71 5917{
e5a43549 5918 struct pci_dev *pdev = adapter->pdev;
9a799d71 5919 struct ixgbe_tx_buffer *tx_buffer_info;
eacd73f7
YZ		 5920 unsigned int len;
5921 unsigned int total = skb->len;
9a799d71
AK		 5922 unsigned int offset = 0, size, count = 0, i;
5923 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
5924 unsigned int f;
9a799d71
AK		 5925
5926 i = tx_ring->next_to_use;
5927
eacd73f7
YZ		 5928 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
5929 /* excluding fcoe_crc_eof for FCoE */
5930 total -= sizeof(struct fcoe_crc_eof);
5931
5932 len = min(skb_headlen(skb), total);
9a799d71
AK		 5933 while (len) {
5934 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5935 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5936
5937 tx_buffer_info->length = size;
e5a43549 5938 tx_buffer_info->mapped_as_page = false;
1b507730 5939 tx_buffer_info->dma = dma_map_single(&pdev->dev,
e5a43549 5940 skb->data + offset,
1b507730
NN		 5941 size, DMA_TO_DEVICE);
5942 if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
e5a43549 5943 goto dma_error;
9a799d71
AK		 5944 tx_buffer_info->time_stamp = jiffies;
5945 tx_buffer_info->next_to_watch = i;
5946
5947 len -= size;
eacd73f7 5948 total -= size;
9a799d71
AK		 5949 offset += size;
5950 count++;
44df32c5
AD		 5951
5952 if (len) {
5953 i++;
5954 if (i == tx_ring->count)
5955 i = 0;
5956 }
9a799d71
AK		 5957 }
5958
5959 for (f = 0; f < nr_frags; f++) {
5960 struct skb_frag_struct *frag;
5961
5962 frag = &skb_shinfo(skb)->frags[f];
eacd73f7 5963 len = min((unsigned int)frag->size, total);
e5a43549 5964 offset = frag->page_offset;
9a799d71
AK		 5965
5966 while (len) {
44df32c5
AD		 5967 i++;
5968 if (i == tx_ring->count)
5969 i = 0;
5970
9a799d71
AK		 5971 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5972 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5973
5974 tx_buffer_info->length = size;
1b507730 5975 tx_buffer_info->dma = dma_map_page(&adapter->pdev->dev,
e5a43549
AD		 5976 frag->page,
5977 offset, size,
1b507730 5978 DMA_TO_DEVICE);
e5a43549 5979 tx_buffer_info->mapped_as_page = true;
1b507730 5980 if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
e5a43549 5981 goto dma_error;
9a799d71
AK		 5982 tx_buffer_info->time_stamp = jiffies;
5983 tx_buffer_info->next_to_watch = i;
5984
5985 len -= size;
eacd73f7 5986 total -= size;
9a799d71
AK		 5987 offset += size;
5988 count++;
9a799d71 5989 }
eacd73f7
YZ		 5990 if (total == 0)
5991 break;
9a799d71 5992 }
44df32c5 5993
9a799d71
AK		 5994 tx_ring->tx_buffer_info[i].skb = skb;
5995 tx_ring->tx_buffer_info[first].next_to_watch = i;
5996
e5a43549
AD		 5997 return count;
5998
5999dma_error:
849c4542 6000 e_dev_err("TX DMA map failed\n");
e5a43549
AD		 6001
6002 /* clear timestamp and dma mappings for failed tx_buffer_info map */
6003 tx_buffer_info->dma = 0;
6004 tx_buffer_info->time_stamp = 0;
6005 tx_buffer_info->next_to_watch = 0;
c1fa347f
RK		 6006 if (count)
6007 count--;
e5a43549
AD		 6008
6009 /* clear timestamp and dma mappings for remaining portion of packet */
c1fa347f
RK		 6010 while (count--) {
6011 if (i==0)
e5a43549 6012 i += tx_ring->count;
c1fa347f 6013 i--;
e5a43549
AD		 6014 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6015 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
6016 }
6017
e44d38e1 6018 return 0;
9a799d71
AK		 6019}
6020
6021static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
b4617240
PW		 6022 struct ixgbe_ring *tx_ring,
6023 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 6024{
6025 union ixgbe_adv_tx_desc *tx_desc = NULL;
6026 struct ixgbe_tx_buffer *tx_buffer_info;
6027 u32 olinfo_status = 0, cmd_type_len = 0;
6028 unsigned int i;
6029 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6030
6031 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6032
6033 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6034
6035 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6036 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6037
6038 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6039 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6040
6041 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 6042 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 6043
4eeae6fd
PW		 6044 /* use index 1 context for tso */
6045 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 6046 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6047 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
b4617240 6048 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 6049
6050 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6051 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 6052 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 6053
eacd73f7
YZ		 6054 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6055 olinfo_status |= IXGBE_ADVTXD_CC;
6056 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6057 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6058 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6059 }
6060
9a799d71
AK		 6061 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6062
6063 i = tx_ring->next_to_use;
6064 while (count--) {
6065 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6066 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
6067 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6068 tx_desc->read.cmd_type_len =
b4617240 6069 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71 6070 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
9a799d71
AK		 6071 i++;
6072 if (i == tx_ring->count)
6073 i = 0;
6074 }
6075
6076 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6077
6078 /*
6079 * Force memory writes to complete before letting h/w
6080 * know there are new descriptors to fetch. (Only
6081 * applicable for weak-ordered memory model archs,
6082 * such as IA-64).
6083 */
6084 wmb();
6085
6086 tx_ring->next_to_use = i;
6087 writel(i, adapter->hw.hw_addr + tx_ring->tail);
6088}
6089
c4cf55e5
PWJ		 6090static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6091 int queue, u32 tx_flags)
6092{
c4cf55e5
PWJ		 6093 struct ixgbe_atr_input atr_input;
6094 struct tcphdr *th;
c4cf55e5
PWJ		 6095 struct iphdr *iph = ip_hdr(skb);
6096 struct ethhdr *eth = (struct ethhdr *)skb->data;
6097 u16 vlan_id, src_port, dst_port, flex_bytes;
6098 u32 src_ipv4_addr, dst_ipv4_addr;
6099 u8 l4type = 0;
6100
d3ead241
GG		 6101 /* Right now, we support IPv4 only */
6102 if (skb->protocol != htons(ETH_P_IP))
6103 return;
c4cf55e5
PWJ		 6104 /* check if we're UDP or TCP */
6105 if (iph->protocol == IPPROTO_TCP) {
6106 th = tcp_hdr(skb);
6107 src_port = th->source;
6108 dst_port = th->dest;
6109 l4type |= IXGBE_ATR_L4TYPE_TCP;
6110 /* l4type IPv4 type is 0, no need to assign */
c4cf55e5
PWJ		 6111 } else {
6112 /* Unsupported L4 header, just bail here */
6113 return;
6114 }
6115
6116 memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
6117
6118 vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
6119 IXGBE_TX_FLAGS_VLAN_SHIFT;
6120 src_ipv4_addr = iph->saddr;
6121 dst_ipv4_addr = iph->daddr;
6122 flex_bytes = eth->h_proto;
6123
6124 ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
6125 ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
6126 ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
6127 ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
6128 ixgbe_atr_set_l4type_82599(&atr_input, l4type);
6129 /* src and dst are inverted, think how the receiver sees them */
6130 ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
6131 ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
6132
6133 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6134 ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
6135}
6136
e092be60 6137static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 6138 struct ixgbe_ring *tx_ring, int size)
e092be60 6139{
30eba97a 6140 netif_stop_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 6141 /* Herbert's original patch had:
6142 * smp_mb__after_netif_stop_queue();
6143 * but since that doesn't exist yet, just open code it. */
6144 smp_mb();
6145
6146 /* We need to check again in a case another CPU has just
6147 * made room available. */
6148 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6149 return -EBUSY;
6150
6151 /* A reprieve! - use start_queue because it doesn't call schedule */
af72166f 6152 netif_start_subqueue(netdev, tx_ring->queue_index);
7ca3bc58 6153 ++tx_ring->restart_queue;
e092be60
AV		 6154 return 0;
6155}
6156
6157static int ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 6158 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 6159{
6160 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6161 return 0;
6162 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
6163}
6164
09a3b1f8
SH		 6165static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6166{
6167 struct ixgbe_adapter *adapter = netdev_priv(dev);
5f715823 6168 int txq = smp_processor_id();
09a3b1f8 6169
56075a98
JF		 6170#ifdef IXGBE_FCOE
6171 if ((skb->protocol == htons(ETH_P_FCOE)) ||
6172 (skb->protocol == htons(ETH_P_FIP))) {
6173 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
6174 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6175 txq += adapter->ring_feature[RING_F_FCOE].mask;
6176 return txq;
4bc091d8 6177#ifdef CONFIG_IXGBE_DCB
56075a98
JF		 6178 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6179 txq = adapter->fcoe.up;
6180 return txq;
4bc091d8 6181#endif
56075a98
JF		 6182 }
6183 }
6184#endif
6185
fdd3d631
KK		 6186 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6187 while (unlikely(txq >= dev->real_num_tx_queues))
6188 txq -= dev->real_num_tx_queues;
5f715823 6189 return txq;
fdd3d631 6190 }
c4cf55e5 6191
2ea186ae
JF		 6192 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6193 if (skb->priority == TC_PRIO_CONTROL)
6194 txq = adapter->ring_feature[RING_F_DCB].indices-1;
6195 else
6196 txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
6197 >> 13;
6198 return txq;
6199 }
09a3b1f8
SH		 6200
6201 return skb_tx_hash(dev, skb);
6202}
6203
3b29a56d
SH		 6204static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
6205 struct net_device *netdev)
9a799d71
AK		 6206{
6207 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6208 struct ixgbe_ring *tx_ring;
60d51134 6209 struct netdev_queue *txq;
9a799d71
AK		 6210 unsigned int first;
6211 unsigned int tx_flags = 0;
30eba97a 6212 u8 hdr_len = 0;
5f715823 6213 int tso;
9a799d71
AK		 6214 int count = 0;
6215 unsigned int f;
9f8cdf4f 6216
9f8cdf4f
JB		 6217 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
6218 tx_flags |= vlan_tx_tag_get(skb);
2f90b865
AD		 6219 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6220 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5f715823 6221 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
2f90b865
AD		 6222 }
6223 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6224 tx_flags |= IXGBE_TX_FLAGS_VLAN;
33c66bd1
JF		 6225 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6226 skb->priority != TC_PRIO_CONTROL) {
2ea186ae
JF		 6227 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6228 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6229 tx_flags |= IXGBE_TX_FLAGS_VLAN;
9a799d71 6230 }
eacd73f7 6231
4a0b9ca0 6232 tx_ring = adapter->tx_ring[skb->queue_mapping];
60127865 6233
09ad1cc0 6234#ifdef IXGBE_FCOE
56075a98
JF		 6235 /* for FCoE with DCB, we force the priority to what
6236 * was specified by the switch */
6237 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
6238 (skb->protocol == htons(ETH_P_FCOE) ||
6239 skb->protocol == htons(ETH_P_FIP))) {
4bc091d8
JF		 6240#ifdef CONFIG_IXGBE_DCB
6241 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6242 tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6243 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6244 tx_flags |= ((adapter->fcoe.up << 13)
6245 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6246 }
6247#endif
ca77cd59
RL		 6248 /* flag for FCoE offloads */
6249 if (skb->protocol == htons(ETH_P_FCOE))
6250 tx_flags |= IXGBE_TX_FLAGS_FCOE;
09ad1cc0 6251 }
ca77cd59
RL		 6252#endif
6253
eacd73f7 6254 /* four things can cause us to need a context descriptor */
9f8cdf4f
JB		 6255 if (skb_is_gso(skb) ||
6256 (skb->ip_summed == CHECKSUM_PARTIAL) ||
eacd73f7
YZ		 6257 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6258 (tx_flags & IXGBE_TX_FLAGS_FCOE))
9a799d71
AK		 6259 count++;
6260
9f8cdf4f
JB		 6261 count += TXD_USE_COUNT(skb_headlen(skb));
6262 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
9a799d71
AK		 6263 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6264
e092be60 6265 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
9a799d71 6266 adapter->tx_busy++;
9a799d71
AK		 6267 return NETDEV_TX_BUSY;
6268 }
9a799d71 6269
9a799d71 6270 first = tx_ring->next_to_use;
eacd73f7
YZ		 6271 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6272#ifdef IXGBE_FCOE
6273 /* setup tx offload for FCoE */
6274 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6275 if (tso < 0) {
6276 dev_kfree_skb_any(skb);
6277 return NETDEV_TX_OK;
6278 }
6279 if (tso)
6280 tx_flags |= IXGBE_TX_FLAGS_FSO;
6281#endif /* IXGBE_FCOE */
6282 } else {
6283 if (skb->protocol == htons(ETH_P_IP))
6284 tx_flags |= IXGBE_TX_FLAGS_IPV4;
6285 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6286 if (tso < 0) {
6287 dev_kfree_skb_any(skb);
6288 return NETDEV_TX_OK;
6289 }
9a799d71 6290
eacd73f7
YZ		 6291 if (tso)
6292 tx_flags |= IXGBE_TX_FLAGS_TSO;
6293 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
6294 (skb->ip_summed == CHECKSUM_PARTIAL))
6295 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6296 }
9a799d71 6297
eacd73f7 6298 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
44df32c5 6299 if (count) {
c4cf55e5
PWJ		 6300 /* add the ATR filter if ATR is on */
6301 if (tx_ring->atr_sample_rate) {
6302 ++tx_ring->atr_count;
6303 if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
6304 test_bit(__IXGBE_FDIR_INIT_DONE,
6305 &tx_ring->reinit_state)) {
6306 ixgbe_atr(adapter, skb, tx_ring->queue_index,
6307 tx_flags);
6308 tx_ring->atr_count = 0;
6309 }
6310 }
60d51134
ED		 6311 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
6312 txq->tx_bytes += skb->len;
6313 txq->tx_packets++;
44df32c5
AD		 6314 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
6315 hdr_len);
44df32c5 6316 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
9a799d71 6317
44df32c5
AD		 6318 } else {
6319 dev_kfree_skb_any(skb);
6320 tx_ring->tx_buffer_info[first].time_stamp = 0;
6321 tx_ring->next_to_use = first;
6322 }
9a799d71
AK		 6323
6324 return NETDEV_TX_OK;
6325}
6326
9a799d71
AK		 6327/**
6328 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6329 * @netdev: network interface device structure
6330 * @p: pointer to an address structure
6331 *
6332 * Returns 0 on success, negative on failure
6333 **/
6334static int ixgbe_set_mac(struct net_device *netdev, void *p)
6335{
6336 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 6337 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 6338 struct sockaddr *addr = p;
6339
6340 if (!is_valid_ether_addr(addr->sa_data))
6341 return -EADDRNOTAVAIL;
6342
6343 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 6344 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 6345
1cdd1ec8
GR		 6346 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6347 IXGBE_RAH_AV);
9a799d71
AK		 6348
6349 return 0;
6350}
6351
6b73e10d
BH		 6352static int
6353ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6354{
6355 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6356 struct ixgbe_hw *hw = &adapter->hw;
6357 u16 value;
6358 int rc;
6359
6360 if (prtad != hw->phy.mdio.prtad)
6361 return -EINVAL;
6362 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6363 if (!rc)
6364 rc = value;
6365 return rc;
6366}
6367
6368static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6369 u16 addr, u16 value)
6370{
6371 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6372 struct ixgbe_hw *hw = &adapter->hw;
6373
6374 if (prtad != hw->phy.mdio.prtad)
6375 return -EINVAL;
6376 return hw->phy.ops.write_reg(hw, addr, devad, value);
6377}
6378
6379static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6380{
6381 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6382
6383 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6384}
6385
0365e6e4
PW		 6386/**
6387 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 6388 * netdev->dev_addrs
0365e6e4
PW		 6389 * @netdev: network interface device structure
6390 *
6391 * Returns non-zero on failure
6392 **/
6393static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6394{
6395 int err = 0;
6396 struct ixgbe_adapter *adapter = netdev_priv(dev);
6397 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6398
6399 if (is_valid_ether_addr(mac->san_addr)) {
6400 rtnl_lock();
6401 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6402 rtnl_unlock();
6403 }
6404 return err;
6405}
6406
6407/**
6408 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 6409 * netdev->dev_addrs
0365e6e4
PW		 6410 * @netdev: network interface device structure
6411 *
6412 * Returns non-zero on failure
6413 **/
6414static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6415{
6416 int err = 0;
6417 struct ixgbe_adapter *adapter = netdev_priv(dev);
6418 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6419
6420 if (is_valid_ether_addr(mac->san_addr)) {
6421 rtnl_lock();
6422 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6423 rtnl_unlock();
6424 }
6425 return err;
6426}
6427
9a799d71
AK		 6428#ifdef CONFIG_NET_POLL_CONTROLLER
6429/*
6430 * Polling 'interrupt' - used by things like netconsole to send skbs
6431 * without having to re-enable interrupts. It's not called while
6432 * the interrupt routine is executing.
6433 */
6434static void ixgbe_netpoll(struct net_device *netdev)
6435{
6436 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 6437 int i;
9a799d71 6438
1a647bd2
AD		 6439 /* if interface is down do nothing */
6440 if (test_bit(__IXGBE_DOWN, &adapter->state))
6441 return;
6442
9a799d71 6443 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167
PWJ		 6444 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6445 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6446 for (i = 0; i < num_q_vectors; i++) {
6447 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6448 ixgbe_msix_clean_many(0, q_vector);
6449 }
6450 } else {
6451 ixgbe_intr(adapter->pdev->irq, netdev);
6452 }
9a799d71 6453 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71
AK		 6454}
6455#endif
6456
0edc3527
SH		 6457static const struct net_device_ops ixgbe_netdev_ops = {
6458 .ndo_open = ixgbe_open,
6459 .ndo_stop = ixgbe_close,
00829823 6460 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 6461 .ndo_select_queue = ixgbe_select_queue,
e90d400c 6462 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 6463 .ndo_set_multicast_list = ixgbe_set_rx_mode,
6464 .ndo_validate_addr = eth_validate_addr,
6465 .ndo_set_mac_address = ixgbe_set_mac,
6466 .ndo_change_mtu = ixgbe_change_mtu,
6467 .ndo_tx_timeout = ixgbe_tx_timeout,
6468 .ndo_vlan_rx_register = ixgbe_vlan_rx_register,
6469 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
6470 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 6471 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 6472 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
6473 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
6474 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
6475 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
0edc3527
SH		 6476#ifdef CONFIG_NET_POLL_CONTROLLER
6477 .ndo_poll_controller = ixgbe_netpoll,
6478#endif
332d4a7d
YZ		 6479#ifdef IXGBE_FCOE
6480 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
6481 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 6482 .ndo_fcoe_enable = ixgbe_fcoe_enable,
6483 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 6484 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
332d4a7d 6485#endif /* IXGBE_FCOE */
0edc3527
SH		 6486};
6487
1cdd1ec8
GR		 6488static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
6489 const struct ixgbe_info *ii)
6490{
6491#ifdef CONFIG_PCI_IOV
6492 struct ixgbe_hw *hw = &adapter->hw;
6493 int err;
6494
6495 if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs)
6496 return;
6497
6498 /* The 82599 supports up to 64 VFs per physical function
6499 * but this implementation limits allocation to 63 so that
6500 * basic networking resources are still available to the
6501 * physical function
6502 */
6503 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
6504 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
6505 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
6506 if (err) {
396e799c 6507 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
1cdd1ec8
GR		 6508 goto err_novfs;
6509 }
6510 /* If call to enable VFs succeeded then allocate memory
6511 * for per VF control structures.
6512 */
6513 adapter->vfinfo =
6514 kcalloc(adapter->num_vfs,
6515 sizeof(struct vf_data_storage), GFP_KERNEL);
6516 if (adapter->vfinfo) {
6517 /* Now that we're sure SR-IOV is enabled
6518 * and memory allocated set up the mailbox parameters
6519 */
6520 ixgbe_init_mbx_params_pf(hw);
6521 memcpy(&hw->mbx.ops, ii->mbx_ops,
6522 sizeof(hw->mbx.ops));
6523
6524 /* Disable RSC when in SR-IOV mode */
6525 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
6526 IXGBE_FLAG2_RSC_ENABLED);
6527 return;
6528 }
6529
6530 /* Oh oh */
396e799c
ET		 6531 e_err(probe, "Unable to allocate memory for VF Data Storage - "
6532 "SRIOV disabled\n");
1cdd1ec8
GR		 6533 pci_disable_sriov(adapter->pdev);
6534
6535err_novfs:
6536 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
6537 adapter->num_vfs = 0;
6538#endif /* CONFIG_PCI_IOV */
6539}
6540
9a799d71
AK		 6541/**
6542 * ixgbe_probe - Device Initialization Routine
6543 * @pdev: PCI device information struct
6544 * @ent: entry in ixgbe_pci_tbl
6545 *
6546 * Returns 0 on success, negative on failure
6547 *
6548 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6549 * The OS initialization, configuring of the adapter private structure,
6550 * and a hardware reset occur.
6551 **/
6552static int __devinit ixgbe_probe(struct pci_dev *pdev,
b4617240 6553 const struct pci_device_id *ent)
9a799d71
AK		 6554{
6555 struct net_device *netdev;
6556 struct ixgbe_adapter *adapter = NULL;
6557 struct ixgbe_hw *hw;
6558 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 6559 static int cards_found;
6560 int i, err, pci_using_dac;
c85a2618 6561 unsigned int indices = num_possible_cpus();
eacd73f7
YZ		 6562#ifdef IXGBE_FCOE
6563 u16 device_caps;
6564#endif
c44ade9e 6565 u32 part_num, eec;
9a799d71 6566
bded64a7
AG		 6567 /* Catch broken hardware that put the wrong VF device ID in
6568 * the PCIe SR-IOV capability.
6569 */
6570 if (pdev->is_virtfn) {
6571 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
6572 pci_name(pdev), pdev->vendor, pdev->device);
6573 return -EINVAL;
6574 }
6575
9ce77666 6576 err = pci_enable_device_mem(pdev);
9a799d71
AK		 6577 if (err)
6578 return err;
6579
1b507730
NN		 6580 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
6581 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 6582 pci_using_dac = 1;
6583 } else {
1b507730 6584 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 6585 if (err) {
1b507730
NN		 6586 err = dma_set_coherent_mask(&pdev->dev,
6587 DMA_BIT_MASK(32));
9a799d71 6588 if (err) {
b8bc0421
DC		 6589 dev_err(&pdev->dev,
6590 "No usable DMA configuration, aborting\n");
9a799d71
AK		 6591 goto err_dma;
6592 }
6593 }
6594 pci_using_dac = 0;
6595 }
6596
9ce77666 6597 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
6598 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 6599 if (err) {
b8bc0421
DC		 6600 dev_err(&pdev->dev,
6601 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 6602 goto err_pci_reg;
6603 }
6604
19d5afd4 6605 pci_enable_pcie_error_reporting(pdev);
6fabd715 6606
9a799d71 6607 pci_set_master(pdev);
fb3b27bc 6608 pci_save_state(pdev);
9a799d71 6609
c85a2618
JF		 6610 if (ii->mac == ixgbe_mac_82598EB)
6611 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
6612 else
6613 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
6614
6615 indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
6616#ifdef IXGBE_FCOE
6617 indices += min_t(unsigned int, num_possible_cpus(),
6618 IXGBE_MAX_FCOE_INDICES);
6619#endif
c85a2618 6620 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 6621 if (!netdev) {
6622 err = -ENOMEM;
6623 goto err_alloc_etherdev;
6624 }
6625
9a799d71
AK		 6626 SET_NETDEV_DEV(netdev, &pdev->dev);
6627
6628 pci_set_drvdata(pdev, netdev);
6629 adapter = netdev_priv(netdev);
6630
6631 adapter->netdev = netdev;
6632 adapter->pdev = pdev;
6633 hw = &adapter->hw;
6634 hw->back = adapter;
6635 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
6636
05857980
JK		 6637 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
6638 pci_resource_len(pdev, 0));
9a799d71
AK		 6639 if (!hw->hw_addr) {
6640 err = -EIO;
6641 goto err_ioremap;
6642 }
6643
6644 for (i = 1; i <= 5; i++) {
6645 if (pci_resource_len(pdev, i) == 0)
6646 continue;
6647 }
6648
0edc3527 6649 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 6650 ixgbe_set_ethtool_ops(netdev);
9a799d71 6651 netdev->watchdog_timeo = 5 * HZ;
9a799d71
AK		 6652 strcpy(netdev->name, pci_name(pdev));
6653
9a799d71
AK		 6654 adapter->bd_number = cards_found;
6655
9a799d71
AK		 6656 /* Setup hw api */
6657 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 6658 hw->mac.type = ii->mac;
9a799d71 6659
c44ade9e
JB		 6660 /* EEPROM */
6661 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
6662 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
6663 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6664 if (!(eec & (1 << 8)))
6665 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
6666
6667 /* PHY */
6668 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 6669 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 6670 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6671 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
6672 hw->phy.mdio.mmds = 0;
6673 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
6674 hw->phy.mdio.dev = netdev;
6675 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
6676 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0
DS		 6677
6678 /* set up this timer and work struct before calling get_invariants
6679 * which might start the timer
6680 */
6681 init_timer(&adapter->sfp_timer);
6682 adapter->sfp_timer.function = &ixgbe_sfp_timer;
6683 adapter->sfp_timer.data = (unsigned long) adapter;
6684
6685 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
c44ade9e 6686
e8e26350
PW		 6687 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
6688 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
6689
6690 /* a new SFP+ module arrival, called from GPI SDP2 context */
6691 INIT_WORK(&adapter->sfp_config_module_task,
6692 ixgbe_sfp_config_module_task);
6693
8ca783ab 6694 ii->get_invariants(hw);
9a799d71
AK		 6695
6696 /* setup the private structure */
6697 err = ixgbe_sw_init(adapter);
6698 if (err)
6699 goto err_sw_init;
6700
e86bff0e
DS		 6701 /* Make it possible the adapter to be woken up via WOL */
6702 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6703 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6704
bf069c97
DS		 6705 /*
6706 * If there is a fan on this device and it has failed log the
6707 * failure.
6708 */
6709 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
6710 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
6711 if (esdp & IXGBE_ESDP_SDP1)
396e799c 6712 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 6713 }
6714
c44ade9e 6715 /* reset_hw fills in the perm_addr as well */
119fc60a 6716 hw->phy.reset_if_overtemp = true;
c44ade9e 6717 err = hw->mac.ops.reset_hw(hw);
119fc60a 6718 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 6719 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
6720 hw->mac.type == ixgbe_mac_82598EB) {
6721 /*
6722 * Start a kernel thread to watch for a module to arrive.
6723 * Only do this for 82598, since 82599 will generate
6724 * interrupts on module arrival.
6725 */
6726 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6727 mod_timer(&adapter->sfp_timer,
6728 round_jiffies(jiffies + (2 * HZ)));
6729 err = 0;
6730 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
849c4542
ET		 6731 e_dev_err("failed to initialize because an unsupported SFP+ "
6732 "module type was detected.\n");
6733 e_dev_err("Reload the driver after installing a supported "
6734 "module.\n");
04f165ef
PW		 6735 goto err_sw_init;
6736 } else if (err) {
849c4542 6737 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 6738 goto err_sw_init;
6739 }
6740
1cdd1ec8
GR		 6741 ixgbe_probe_vf(adapter, ii);
6742
396e799c 6743 netdev->features = NETIF_F_SG |
b4617240
PW		 6744 NETIF_F_IP_CSUM |
6745 NETIF_F_HW_VLAN_TX |
6746 NETIF_F_HW_VLAN_RX |
6747 NETIF_F_HW_VLAN_FILTER;
9a799d71 6748
e9990a9c 6749 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 6750 netdev->features |= NETIF_F_TSO;
9a799d71 6751 netdev->features |= NETIF_F_TSO6;
78b6f4ce 6752 netdev->features |= NETIF_F_GRO;
ad31c402 6753
45a5ead0
JB		 6754 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6755 netdev->features |= NETIF_F_SCTP_CSUM;
6756
ad31c402
JK		 6757 netdev->vlan_features |= NETIF_F_TSO;
6758 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 6759 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 6760 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 6761 netdev->vlan_features |= NETIF_F_SG;
6762
1cdd1ec8
GR		 6763 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6764 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
6765 IXGBE_FLAG_DCB_ENABLED);
2f90b865
AD		 6766 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
6767 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
6768
7a6b6f51 6769#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 6770 netdev->dcbnl_ops = &dcbnl_ops;
6771#endif
6772
eacd73f7 6773#ifdef IXGBE_FCOE
0d551589 6774 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 6775 if (hw->mac.ops.get_device_caps) {
6776 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 6777 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
6778 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7
YZ		 6779 }
6780 }
5e09d7f6
YZ		 6781 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6782 netdev->vlan_features |= NETIF_F_FCOE_CRC;
6783 netdev->vlan_features |= NETIF_F_FSO;
6784 netdev->vlan_features |= NETIF_F_FCOE_MTU;
6785 }
eacd73f7 6786#endif /* IXGBE_FCOE */
9a799d71
AK		 6787 if (pci_using_dac)
6788 netdev->features |= NETIF_F_HIGHDMA;
6789
0c19d6af 6790 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 6791 netdev->features |= NETIF_F_LRO;
6792
9a799d71 6793 /* make sure the EEPROM is good */
c44ade9e 6794 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 6795 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71
AK		 6796 err = -EIO;
6797 goto err_eeprom;
6798 }
6799
6800 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
6801 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
6802
c44ade9e 6803 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
849c4542 6804 e_dev_err("invalid MAC address\n");
9a799d71
AK		 6805 err = -EIO;
6806 goto err_eeprom;
6807 }
6808
61fac744
PW		 6809 /* power down the optics */
6810 if (hw->phy.multispeed_fiber)
6811 hw->mac.ops.disable_tx_laser(hw);
6812
9a799d71
AK		 6813 init_timer(&adapter->watchdog_timer);
6814 adapter->watchdog_timer.function = &ixgbe_watchdog;
6815 adapter->watchdog_timer.data = (unsigned long)adapter;
6816
6817 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
cf8280ee 6818 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
9a799d71 6819
021230d4
AV		 6820 err = ixgbe_init_interrupt_scheme(adapter);
6821 if (err)
6822 goto err_sw_init;
9a799d71 6823
e8e26350
PW		 6824 switch (pdev->device) {
6825 case IXGBE_DEV_ID_82599_KX4:
495dce12
WJP		 6826 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
6827 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
e8e26350
PW		 6828 break;
6829 default:
6830 adapter->wol = 0;
6831 break;
6832 }
e8e26350
PW		 6833 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
6834
04f165ef
PW		 6835 /* pick up the PCI bus settings for reporting later */
6836 hw->mac.ops.get_bus_info(hw);
6837
9a799d71 6838 /* print bus type/speed/width info */
849c4542 6839 e_dev_info("(PCI Express:%s:%s) %pM\n",
e8e26350
PW		 6840 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
6841 (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
6842 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
6843 (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
6844 (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
b4617240 6845 "Unknown"),
7c510e4b 6846 netdev->dev_addr);
c44ade9e 6847 ixgbe_read_pba_num_generic(hw, &part_num);
e8e26350 6848 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
849c4542
ET		 6849 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, "
6850 "PBA No: %06x-%03x\n",
6851 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
6852 (part_num >> 8), (part_num & 0xff));
e8e26350 6853 else
849c4542
ET		 6854 e_dev_info("MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
6855 hw->mac.type, hw->phy.type,
6856 (part_num >> 8), (part_num & 0xff));
9a799d71 6857
e8e26350 6858 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
849c4542
ET		 6859 e_dev_warn("PCI-Express bandwidth available for this card is "
6860 "not sufficient for optimal performance.\n");
6861 e_dev_warn("For optimal performance a x8 PCI-Express slot "
6862 "is required.\n");
0c254d86
AK		 6863 }
6864
34b0368c
PWJ		 6865 /* save off EEPROM version number */
6866 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
6867
9a799d71 6868 /* reset the hardware with the new settings */
794caeb2 6869 err = hw->mac.ops.start_hw(hw);
c44ade9e 6870
794caeb2
PWJ		 6871 if (err == IXGBE_ERR_EEPROM_VERSION) {
6872 /* We are running on a pre-production device, log a warning */
849c4542
ET		 6873 e_dev_warn("This device is a pre-production adapter/LOM. "
6874 "Please be aware there may be issues associated "
6875 "with your hardware. If you are experiencing "
6876 "problems please contact your Intel or hardware "
6877 "representative who provided you with this "
6878 "hardware.\n");
794caeb2 6879 }
9a799d71
AK		 6880 strcpy(netdev->name, "eth%d");
6881 err = register_netdev(netdev);
6882 if (err)
6883 goto err_register;
6884
54386467
JB		 6885 /* carrier off reporting is important to ethtool even BEFORE open */
6886 netif_carrier_off(netdev);
6887
c4cf55e5
PWJ		 6888 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6889 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6890 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
6891
119fc60a
MC		 6892 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
6893 INIT_WORK(&adapter->check_overtemp_task, ixgbe_check_overtemp_task);
5dd2d332 6894#ifdef CONFIG_IXGBE_DCA
652f093f 6895 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 6896 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 6897 ixgbe_setup_dca(adapter);
6898 }
6899#endif
1cdd1ec8 6900 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 6901 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 6902 for (i = 0; i < adapter->num_vfs; i++)
6903 ixgbe_vf_configuration(pdev, (i | 0x10000000));
6904 }
6905
0365e6e4
PW		 6906 /* add san mac addr to netdev */
6907 ixgbe_add_sanmac_netdev(netdev);
9a799d71 6908
849c4542 6909 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
9a799d71
AK		 6910 cards_found++;
6911 return 0;
6912
6913err_register:
5eba3699 6914 ixgbe_release_hw_control(adapter);
7a921c93 6915 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 6916err_sw_init:
6917err_eeprom:
1cdd1ec8
GR		 6918 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6919 ixgbe_disable_sriov(adapter);
c4900be0
DS		 6920 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6921 del_timer_sync(&adapter->sfp_timer);
6922 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 6923 cancel_work_sync(&adapter->multispeed_fiber_task);
6924 cancel_work_sync(&adapter->sfp_config_module_task);
9a799d71
AK		 6925 iounmap(hw->hw_addr);
6926err_ioremap:
6927 free_netdev(netdev);
6928err_alloc_etherdev:
9ce77666 6929 pci_release_selected_regions(pdev, pci_select_bars(pdev,
6930 IORESOURCE_MEM));
9a799d71
AK		 6931err_pci_reg:
6932err_dma:
6933 pci_disable_device(pdev);
6934 return err;
6935}
6936
6937/**
6938 * ixgbe_remove - Device Removal Routine
6939 * @pdev: PCI device information struct
6940 *
6941 * ixgbe_remove is called by the PCI subsystem to alert the driver
6942 * that it should release a PCI device. The could be caused by a
6943 * Hot-Plug event, or because the driver is going to be removed from
6944 * memory.
6945 **/
6946static void __devexit ixgbe_remove(struct pci_dev *pdev)
6947{
6948 struct net_device *netdev = pci_get_drvdata(pdev);
6949 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6950
6951 set_bit(__IXGBE_DOWN, &adapter->state);
c4900be0
DS		 6952 /* clear the module not found bit to make sure the worker won't
6953 * reschedule
6954 */
6955 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
9a799d71
AK		 6956 del_timer_sync(&adapter->watchdog_timer);
6957
c4900be0
DS		 6958 del_timer_sync(&adapter->sfp_timer);
6959 cancel_work_sync(&adapter->watchdog_task);
6960 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 6961 cancel_work_sync(&adapter->multispeed_fiber_task);
6962 cancel_work_sync(&adapter->sfp_config_module_task);
c4cf55e5
PWJ		 6963 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6964 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6965 cancel_work_sync(&adapter->fdir_reinit_task);
9a799d71
AK		 6966 flush_scheduled_work();
6967
5dd2d332 6968#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 6969 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
6970 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
6971 dca_remove_requester(&pdev->dev);
6972 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
6973 }
6974
6975#endif
332d4a7d
YZ		 6976#ifdef IXGBE_FCOE
6977 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
6978 ixgbe_cleanup_fcoe(adapter);
6979
6980#endif /* IXGBE_FCOE */
0365e6e4
PW		 6981
6982 /* remove the added san mac */
6983 ixgbe_del_sanmac_netdev(netdev);
6984
c4900be0
DS		 6985 if (netdev->reg_state == NETREG_REGISTERED)
6986 unregister_netdev(netdev);
9a799d71 6987
1cdd1ec8
GR		 6988 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6989 ixgbe_disable_sriov(adapter);
6990
7a921c93 6991 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 6992
021230d4 6993 ixgbe_release_hw_control(adapter);
9a799d71
AK		 6994
6995 iounmap(adapter->hw.hw_addr);
9ce77666 6996 pci_release_selected_regions(pdev, pci_select_bars(pdev,
6997 IORESOURCE_MEM));
9a799d71 6998
849c4542 6999 e_dev_info("complete\n");
021230d4 7000
9a799d71
AK		 7001 free_netdev(netdev);
7002
19d5afd4 7003 pci_disable_pcie_error_reporting(pdev);
6fabd715 7004
9a799d71
AK		 7005 pci_disable_device(pdev);
7006}
7007
7008/**
7009 * ixgbe_io_error_detected - called when PCI error is detected
7010 * @pdev: Pointer to PCI device
7011 * @state: The current pci connection state
7012 *
7013 * This function is called after a PCI bus error affecting
7014 * this device has been detected.
7015 */
7016static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
b4617240 7017 pci_channel_state_t state)
9a799d71
AK		 7018{
7019 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 7020 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 7021
7022 netif_device_detach(netdev);
7023
3044b8d1
BL		 7024 if (state == pci_channel_io_perm_failure)
7025 return PCI_ERS_RESULT_DISCONNECT;
7026
9a799d71
AK		 7027 if (netif_running(netdev))
7028 ixgbe_down(adapter);
7029 pci_disable_device(pdev);
7030
b4617240 7031 /* Request a slot reset. */
9a799d71
AK		 7032 return PCI_ERS_RESULT_NEED_RESET;
7033}
7034
7035/**
7036 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7037 * @pdev: Pointer to PCI device
7038 *
7039 * Restart the card from scratch, as if from a cold-boot.
7040 */
7041static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7042{
7043 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 7044 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715
PWJ		 7045 pci_ers_result_t result;
7046 int err;
9a799d71 7047
9ce77666 7048 if (pci_enable_device_mem(pdev)) {
396e799c 7049 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 7050 result = PCI_ERS_RESULT_DISCONNECT;
7051 } else {
7052 pci_set_master(pdev);
7053 pci_restore_state(pdev);
c0e1f68b 7054 pci_save_state(pdev);
9a799d71 7055
dd4d8ca6 7056 pci_wake_from_d3(pdev, false);
9a799d71 7057
6fabd715 7058 ixgbe_reset(adapter);
88512539 7059 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 7060 result = PCI_ERS_RESULT_RECOVERED;
7061 }
7062
7063 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7064 if (err) {
849c4542
ET		 7065 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7066 "failed 0x%0x\n", err);
6fabd715
PWJ		 7067 /* non-fatal, continue */
7068 }
9a799d71 7069
6fabd715 7070 return result;
9a799d71
AK		 7071}
7072
7073/**
7074 * ixgbe_io_resume - called when traffic can start flowing again.
7075 * @pdev: Pointer to PCI device
7076 *
7077 * This callback is called when the error recovery driver tells us that
7078 * its OK to resume normal operation.
7079 */
7080static void ixgbe_io_resume(struct pci_dev *pdev)
7081{
7082 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 7083 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 7084
7085 if (netif_running(netdev)) {
7086 if (ixgbe_up(adapter)) {
396e799c 7087 e_info(probe, "ixgbe_up failed after reset\n");
9a799d71
AK		 7088 return;
7089 }
7090 }
7091
7092 netif_device_attach(netdev);
9a799d71
AK		 7093}
7094
7095static struct pci_error_handlers ixgbe_err_handler = {
7096 .error_detected = ixgbe_io_error_detected,
7097 .slot_reset = ixgbe_io_slot_reset,
7098 .resume = ixgbe_io_resume,
7099};
7100
7101static struct pci_driver ixgbe_driver = {
7102 .name = ixgbe_driver_name,
7103 .id_table = ixgbe_pci_tbl,
7104 .probe = ixgbe_probe,
7105 .remove = __devexit_p(ixgbe_remove),
7106#ifdef CONFIG_PM
7107 .suspend = ixgbe_suspend,
7108 .resume = ixgbe_resume,
7109#endif
7110 .shutdown = ixgbe_shutdown,
7111 .err_handler = &ixgbe_err_handler
7112};
7113
7114/**
7115 * ixgbe_init_module - Driver Registration Routine
7116 *
7117 * ixgbe_init_module is the first routine called when the driver is
7118 * loaded. All it does is register with the PCI subsystem.
7119 **/
7120static int __init ixgbe_init_module(void)
7121{
7122 int ret;
849c4542
ET		 7123 pr_info("%s - version %s\n", ixgbe_driver_string,
7124 ixgbe_driver_version);
7125 pr_info("%s\n", ixgbe_copyright);
9a799d71 7126
5dd2d332 7127#ifdef CONFIG_IXGBE_DCA
bd0362dd 7128 dca_register_notify(&dca_notifier);
bd0362dd 7129#endif
5dd2d332 7130
9a799d71
AK		 7131 ret = pci_register_driver(&ixgbe_driver);
7132 return ret;
7133}
b4617240 7134
9a799d71
AK		 7135module_init(ixgbe_init_module);
7136
7137/**
7138 * ixgbe_exit_module - Driver Exit Cleanup Routine
7139 *
7140 * ixgbe_exit_module is called just before the driver is removed
7141 * from memory.
7142 **/
7143static void __exit ixgbe_exit_module(void)
7144{
5dd2d332 7145#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7146 dca_unregister_notify(&dca_notifier);
7147#endif
9a799d71
AK		 7148 pci_unregister_driver(&ixgbe_driver);
7149}
bd0362dd 7150
5dd2d332 7151#ifdef CONFIG_IXGBE_DCA
bd0362dd 7152static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
b4617240 7153 void *p)
bd0362dd
JC		 7154{
7155 int ret_val;
7156
7157 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
b4617240 7158 __ixgbe_notify_dca);
bd0362dd
JC		 7159
7160 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7161}
b453368d 7162
5dd2d332 7163#endif /* CONFIG_IXGBE_DCA */
849c4542 7164
b453368d 7165/**
849c4542 7166 * ixgbe_get_hw_dev return device
b453368d
AD		 7167 * used by hardware layer to print debugging information
7168 **/
849c4542 7169struct net_device *ixgbe_get_hw_dev(struct ixgbe_hw *hw)
b453368d
AD		 7170{
7171 struct ixgbe_adapter *adapter = hw->back;
849c4542 7172 return adapter->netdev;
b453368d 7173}
bd0362dd 7174
9a799d71
AK		 7175module_exit(ixgbe_exit_module);
7176
7177/* ixgbe_main.c */
ubuntu-bionic-kernel mirror