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9a799d71 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
3efac5a0 | 4 | Copyright(c) 1999 - 2009 Intel Corporation. |
9a799d71 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
9a799d71 AK |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #include <linux/types.h> | |
29 | #include <linux/module.h> | |
30 | #include <linux/pci.h> | |
31 | #include <linux/netdevice.h> | |
32 | #include <linux/vmalloc.h> | |
33 | #include <linux/string.h> | |
34 | #include <linux/in.h> | |
35 | #include <linux/ip.h> | |
36 | #include <linux/tcp.h> | |
37 | #include <linux/ipv6.h> | |
38 | #include <net/checksum.h> | |
39 | #include <net/ip6_checksum.h> | |
40 | #include <linux/ethtool.h> | |
41 | #include <linux/if_vlan.h> | |
42 | ||
43 | #include "ixgbe.h" | |
44 | #include "ixgbe_common.h" | |
45 | ||
46 | char ixgbe_driver_name[] = "ixgbe"; | |
9c8eb720 | 47 | static const char ixgbe_driver_string[] = |
b4617240 | 48 | "Intel(R) 10 Gigabit PCI Express Network Driver"; |
9a799d71 | 49 | |
3efac5a0 | 50 | #define DRV_VERSION "1.3.56-k2" |
9c8eb720 | 51 | const char ixgbe_driver_version[] = DRV_VERSION; |
3efac5a0 | 52 | static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation."; |
9a799d71 AK |
53 | |
54 | static const struct ixgbe_info *ixgbe_info_tbl[] = { | |
b4617240 | 55 | [board_82598] = &ixgbe_82598_info, |
9a799d71 AK |
56 | }; |
57 | ||
58 | /* ixgbe_pci_tbl - PCI Device ID Table | |
59 | * | |
60 | * Wildcard entries (PCI_ANY_ID) should come last | |
61 | * Last entry must be all 0s | |
62 | * | |
63 | * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, | |
64 | * Class, Class Mask, private data (not used) } | |
65 | */ | |
66 | static struct pci_device_id ixgbe_pci_tbl[] = { | |
1e336d0f DS |
67 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), |
68 | board_82598 }, | |
9a799d71 | 69 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), |
3957d63d | 70 | board_82598 }, |
9a799d71 | 71 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), |
3957d63d | 72 | board_82598 }, |
0befdb3e JB |
73 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), |
74 | board_82598 }, | |
9a799d71 | 75 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), |
3957d63d | 76 | board_82598 }, |
8d792cd9 JB |
77 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), |
78 | board_82598 }, | |
c4900be0 DS |
79 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), |
80 | board_82598 }, | |
81 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), | |
82 | board_82598 }, | |
b95f5fcb JB |
83 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), |
84 | board_82598 }, | |
c4900be0 DS |
85 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), |
86 | board_82598 }, | |
2f21bdd3 DS |
87 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), |
88 | board_82598 }, | |
9a799d71 AK |
89 | |
90 | /* required last entry */ | |
91 | {0, } | |
92 | }; | |
93 | MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl); | |
94 | ||
5dd2d332 | 95 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 96 | static int ixgbe_notify_dca(struct notifier_block *, unsigned long event, |
b4617240 | 97 | void *p); |
bd0362dd JC |
98 | static struct notifier_block dca_notifier = { |
99 | .notifier_call = ixgbe_notify_dca, | |
100 | .next = NULL, | |
101 | .priority = 0 | |
102 | }; | |
103 | #endif | |
104 | ||
9a799d71 AK |
105 | MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); |
106 | MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver"); | |
107 | MODULE_LICENSE("GPL"); | |
108 | MODULE_VERSION(DRV_VERSION); | |
109 | ||
110 | #define DEFAULT_DEBUG_LEVEL_SHIFT 3 | |
111 | ||
5eba3699 AV |
112 | static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter) |
113 | { | |
114 | u32 ctrl_ext; | |
115 | ||
116 | /* Let firmware take over control of h/w */ | |
117 | ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); | |
118 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, | |
b4617240 | 119 | ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD); |
5eba3699 AV |
120 | } |
121 | ||
122 | static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter) | |
123 | { | |
124 | u32 ctrl_ext; | |
125 | ||
126 | /* Let firmware know the driver has taken over */ | |
127 | ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); | |
128 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, | |
b4617240 | 129 | ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD); |
5eba3699 | 130 | } |
9a799d71 | 131 | |
9a799d71 | 132 | static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, u16 int_alloc_entry, |
b4617240 | 133 | u8 msix_vector) |
9a799d71 AK |
134 | { |
135 | u32 ivar, index; | |
136 | ||
137 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
138 | index = (int_alloc_entry >> 2) & 0x1F; | |
139 | ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR(index)); | |
140 | ivar &= ~(0xFF << (8 * (int_alloc_entry & 0x3))); | |
141 | ivar |= (msix_vector << (8 * (int_alloc_entry & 0x3))); | |
142 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR(index), ivar); | |
143 | } | |
144 | ||
145 | static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter, | |
b4617240 PW |
146 | struct ixgbe_tx_buffer |
147 | *tx_buffer_info) | |
9a799d71 AK |
148 | { |
149 | if (tx_buffer_info->dma) { | |
e01c31a5 | 150 | pci_unmap_page(adapter->pdev, tx_buffer_info->dma, |
b4617240 | 151 | tx_buffer_info->length, PCI_DMA_TODEVICE); |
9a799d71 AK |
152 | tx_buffer_info->dma = 0; |
153 | } | |
154 | if (tx_buffer_info->skb) { | |
155 | dev_kfree_skb_any(tx_buffer_info->skb); | |
156 | tx_buffer_info->skb = NULL; | |
157 | } | |
158 | /* tx_buffer_info must be completely set up in the transmit path */ | |
159 | } | |
160 | ||
161 | static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter, | |
b4617240 PW |
162 | struct ixgbe_ring *tx_ring, |
163 | unsigned int eop) | |
9a799d71 | 164 | { |
e01c31a5 JB |
165 | struct ixgbe_hw *hw = &adapter->hw; |
166 | u32 head, tail; | |
167 | ||
9a799d71 | 168 | /* Detect a transmit hang in hardware, this serializes the |
e01c31a5 JB |
169 | * check with the clearing of time_stamp and movement of eop */ |
170 | head = IXGBE_READ_REG(hw, tx_ring->head); | |
171 | tail = IXGBE_READ_REG(hw, tx_ring->tail); | |
9a799d71 | 172 | adapter->detect_tx_hung = false; |
e01c31a5 JB |
173 | if ((head != tail) && |
174 | tx_ring->tx_buffer_info[eop].time_stamp && | |
9a799d71 AK |
175 | time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) && |
176 | !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) { | |
177 | /* detected Tx unit hang */ | |
e01c31a5 JB |
178 | union ixgbe_adv_tx_desc *tx_desc; |
179 | tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop); | |
9a799d71 | 180 | DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n" |
e01c31a5 JB |
181 | " Tx Queue <%d>\n" |
182 | " TDH, TDT <%x>, <%x>\n" | |
9a799d71 AK |
183 | " next_to_use <%x>\n" |
184 | " next_to_clean <%x>\n" | |
185 | "tx_buffer_info[next_to_clean]\n" | |
186 | " time_stamp <%lx>\n" | |
e01c31a5 JB |
187 | " jiffies <%lx>\n", |
188 | tx_ring->queue_index, | |
189 | head, tail, | |
190 | tx_ring->next_to_use, eop, | |
191 | tx_ring->tx_buffer_info[eop].time_stamp, jiffies); | |
9a799d71 AK |
192 | return true; |
193 | } | |
194 | ||
195 | return false; | |
196 | } | |
197 | ||
b4617240 PW |
198 | #define IXGBE_MAX_TXD_PWR 14 |
199 | #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR) | |
e092be60 AV |
200 | |
201 | /* Tx Descriptors needed, worst case */ | |
202 | #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \ | |
203 | (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0)) | |
204 | #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \ | |
b4617240 | 205 | MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */ |
e092be60 | 206 | |
e01c31a5 JB |
207 | #define GET_TX_HEAD_FROM_RING(ring) (\ |
208 | *(volatile u32 *) \ | |
209 | ((union ixgbe_adv_tx_desc *)(ring)->desc + (ring)->count)) | |
210 | static void ixgbe_tx_timeout(struct net_device *netdev); | |
211 | ||
9a799d71 AK |
212 | /** |
213 | * ixgbe_clean_tx_irq - Reclaim resources after transmit completes | |
214 | * @adapter: board private structure | |
e01c31a5 | 215 | * @tx_ring: tx ring to clean |
9a799d71 AK |
216 | **/ |
217 | static bool ixgbe_clean_tx_irq(struct ixgbe_adapter *adapter, | |
e01c31a5 | 218 | struct ixgbe_ring *tx_ring) |
9a799d71 | 219 | { |
e01c31a5 | 220 | union ixgbe_adv_tx_desc *tx_desc; |
9a799d71 | 221 | struct ixgbe_tx_buffer *tx_buffer_info; |
e01c31a5 JB |
222 | struct net_device *netdev = adapter->netdev; |
223 | struct sk_buff *skb; | |
224 | unsigned int i; | |
225 | u32 head, oldhead; | |
226 | unsigned int count = 0; | |
227 | unsigned int total_bytes = 0, total_packets = 0; | |
9a799d71 | 228 | |
e01c31a5 JB |
229 | rmb(); |
230 | head = GET_TX_HEAD_FROM_RING(tx_ring); | |
231 | head = le32_to_cpu(head); | |
9a799d71 | 232 | i = tx_ring->next_to_clean; |
e01c31a5 JB |
233 | while (1) { |
234 | while (i != head) { | |
9a799d71 AK |
235 | tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i); |
236 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
e01c31a5 | 237 | skb = tx_buffer_info->skb; |
9a799d71 | 238 | |
e01c31a5 | 239 | if (skb) { |
e092be60 | 240 | unsigned int segs, bytecount; |
e01c31a5 JB |
241 | |
242 | /* gso_segs is currently only valid for tcp */ | |
e092be60 AV |
243 | segs = skb_shinfo(skb)->gso_segs ?: 1; |
244 | /* multiply data chunks by size of headers */ | |
245 | bytecount = ((segs - 1) * skb_headlen(skb)) + | |
e01c31a5 JB |
246 | skb->len; |
247 | total_packets += segs; | |
248 | total_bytes += bytecount; | |
e092be60 | 249 | } |
e01c31a5 | 250 | |
9a799d71 | 251 | ixgbe_unmap_and_free_tx_resource(adapter, |
e01c31a5 | 252 | tx_buffer_info); |
9a799d71 AK |
253 | |
254 | i++; | |
255 | if (i == tx_ring->count) | |
256 | i = 0; | |
9a799d71 | 257 | |
e01c31a5 JB |
258 | count++; |
259 | if (count == tx_ring->count) | |
260 | goto done_cleaning; | |
261 | } | |
262 | oldhead = head; | |
263 | rmb(); | |
264 | head = GET_TX_HEAD_FROM_RING(tx_ring); | |
265 | head = le32_to_cpu(head); | |
266 | if (head == oldhead) | |
267 | goto done_cleaning; | |
268 | } /* while (1) */ | |
269 | ||
270 | done_cleaning: | |
9a799d71 AK |
271 | tx_ring->next_to_clean = i; |
272 | ||
e092be60 | 273 | #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) |
e01c31a5 JB |
274 | if (unlikely(count && netif_carrier_ok(netdev) && |
275 | (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) { | |
e092be60 AV |
276 | /* Make sure that anybody stopping the queue after this |
277 | * sees the new next_to_clean. | |
278 | */ | |
279 | smp_mb(); | |
30eba97a AV |
280 | if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) && |
281 | !test_bit(__IXGBE_DOWN, &adapter->state)) { | |
282 | netif_wake_subqueue(netdev, tx_ring->queue_index); | |
e01c31a5 | 283 | ++adapter->restart_queue; |
30eba97a | 284 | } |
e092be60 | 285 | } |
9a799d71 | 286 | |
e01c31a5 JB |
287 | if (adapter->detect_tx_hung) { |
288 | if (ixgbe_check_tx_hang(adapter, tx_ring, i)) { | |
289 | /* schedule immediate reset if we believe we hung */ | |
290 | DPRINTK(PROBE, INFO, | |
291 | "tx hang %d detected, resetting adapter\n", | |
292 | adapter->tx_timeout_count + 1); | |
293 | ixgbe_tx_timeout(adapter->netdev); | |
294 | } | |
295 | } | |
9a799d71 | 296 | |
e01c31a5 JB |
297 | /* re-arm the interrupt */ |
298 | if ((total_packets >= tx_ring->work_limit) || | |
299 | (count == tx_ring->count)) | |
300 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, tx_ring->v_idx); | |
9a799d71 | 301 | |
e01c31a5 JB |
302 | tx_ring->total_bytes += total_bytes; |
303 | tx_ring->total_packets += total_packets; | |
304 | tx_ring->stats.bytes += total_bytes; | |
305 | tx_ring->stats.packets += total_packets; | |
306 | adapter->net_stats.tx_bytes += total_bytes; | |
307 | adapter->net_stats.tx_packets += total_packets; | |
308 | return (total_packets ? true : false); | |
9a799d71 AK |
309 | } |
310 | ||
5dd2d332 | 311 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 312 | static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter, |
b4617240 | 313 | struct ixgbe_ring *rx_ring) |
bd0362dd JC |
314 | { |
315 | u32 rxctrl; | |
316 | int cpu = get_cpu(); | |
3a581073 | 317 | int q = rx_ring - adapter->rx_ring; |
bd0362dd | 318 | |
3a581073 | 319 | if (rx_ring->cpu != cpu) { |
bd0362dd JC |
320 | rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q)); |
321 | rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK; | |
96b0e0f6 | 322 | rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu); |
bd0362dd JC |
323 | rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN; |
324 | rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN; | |
15005a32 DS |
325 | rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN); |
326 | rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN | | |
327 | IXGBE_DCA_RXCTRL_DESC_HSRO_EN); | |
bd0362dd | 328 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl); |
3a581073 | 329 | rx_ring->cpu = cpu; |
bd0362dd JC |
330 | } |
331 | put_cpu(); | |
332 | } | |
333 | ||
334 | static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter, | |
b4617240 | 335 | struct ixgbe_ring *tx_ring) |
bd0362dd JC |
336 | { |
337 | u32 txctrl; | |
338 | int cpu = get_cpu(); | |
3a581073 | 339 | int q = tx_ring - adapter->tx_ring; |
bd0362dd | 340 | |
3a581073 | 341 | if (tx_ring->cpu != cpu) { |
bd0362dd JC |
342 | txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q)); |
343 | txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK; | |
96b0e0f6 | 344 | txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu); |
bd0362dd JC |
345 | txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN; |
346 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl); | |
3a581073 | 347 | tx_ring->cpu = cpu; |
bd0362dd JC |
348 | } |
349 | put_cpu(); | |
350 | } | |
351 | ||
352 | static void ixgbe_setup_dca(struct ixgbe_adapter *adapter) | |
353 | { | |
354 | int i; | |
355 | ||
356 | if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED)) | |
357 | return; | |
358 | ||
359 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
360 | adapter->tx_ring[i].cpu = -1; | |
361 | ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]); | |
362 | } | |
363 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
364 | adapter->rx_ring[i].cpu = -1; | |
365 | ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]); | |
366 | } | |
367 | } | |
368 | ||
369 | static int __ixgbe_notify_dca(struct device *dev, void *data) | |
370 | { | |
371 | struct net_device *netdev = dev_get_drvdata(dev); | |
372 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
373 | unsigned long event = *(unsigned long *)data; | |
374 | ||
375 | switch (event) { | |
376 | case DCA_PROVIDER_ADD: | |
96b0e0f6 JB |
377 | /* if we're already enabled, don't do it again */ |
378 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
379 | break; | |
bd0362dd JC |
380 | /* Always use CB2 mode, difference is masked |
381 | * in the CB driver. */ | |
382 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2); | |
652f093f | 383 | if (dca_add_requester(dev) == 0) { |
96b0e0f6 | 384 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; |
bd0362dd JC |
385 | ixgbe_setup_dca(adapter); |
386 | break; | |
387 | } | |
388 | /* Fall Through since DCA is disabled. */ | |
389 | case DCA_PROVIDER_REMOVE: | |
390 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { | |
391 | dca_remove_requester(dev); | |
392 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
393 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); | |
394 | } | |
395 | break; | |
396 | } | |
397 | ||
652f093f | 398 | return 0; |
bd0362dd JC |
399 | } |
400 | ||
5dd2d332 | 401 | #endif /* CONFIG_IXGBE_DCA */ |
9a799d71 AK |
402 | /** |
403 | * ixgbe_receive_skb - Send a completed packet up the stack | |
404 | * @adapter: board private structure | |
405 | * @skb: packet to send up | |
177db6ff MC |
406 | * @status: hardware indication of status of receive |
407 | * @rx_ring: rx descriptor ring (for a specific queue) to setup | |
408 | * @rx_desc: rx descriptor | |
9a799d71 | 409 | **/ |
78b6f4ce | 410 | static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector, |
b4617240 | 411 | struct sk_buff *skb, u8 status, |
177db6ff | 412 | union ixgbe_adv_rx_desc *rx_desc) |
9a799d71 | 413 | { |
78b6f4ce HX |
414 | struct ixgbe_adapter *adapter = q_vector->adapter; |
415 | struct napi_struct *napi = &q_vector->napi; | |
177db6ff MC |
416 | bool is_vlan = (status & IXGBE_RXD_STAT_VP); |
417 | u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan); | |
9a799d71 | 418 | |
0c8dfc83 | 419 | skb_record_rx_queue(skb, q_vector - &adapter->q_vector[0]); |
78b6f4ce | 420 | if (skb->ip_summed == CHECKSUM_UNNECESSARY) { |
2f90b865 | 421 | if (adapter->vlgrp && is_vlan && (tag != 0)) |
78b6f4ce | 422 | vlan_gro_receive(napi, adapter->vlgrp, tag, skb); |
9a799d71 | 423 | else |
78b6f4ce | 424 | napi_gro_receive(napi, skb); |
177db6ff MC |
425 | } else { |
426 | if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) { | |
2f90b865 | 427 | if (adapter->vlgrp && is_vlan && (tag != 0)) |
177db6ff MC |
428 | vlan_hwaccel_receive_skb(skb, adapter->vlgrp, tag); |
429 | else | |
430 | netif_receive_skb(skb); | |
431 | } else { | |
2f90b865 | 432 | if (adapter->vlgrp && is_vlan && (tag != 0)) |
177db6ff MC |
433 | vlan_hwaccel_rx(skb, adapter->vlgrp, tag); |
434 | else | |
435 | netif_rx(skb); | |
436 | } | |
9a799d71 AK |
437 | } |
438 | } | |
439 | ||
e59bd25d AV |
440 | /** |
441 | * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum | |
442 | * @adapter: address of board private structure | |
443 | * @status_err: hardware indication of status of receive | |
444 | * @skb: skb currently being received and modified | |
445 | **/ | |
9a799d71 | 446 | static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter, |
712744be | 447 | u32 status_err, struct sk_buff *skb) |
9a799d71 AK |
448 | { |
449 | skb->ip_summed = CHECKSUM_NONE; | |
450 | ||
712744be JB |
451 | /* Rx csum disabled */ |
452 | if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED)) | |
9a799d71 | 453 | return; |
e59bd25d AV |
454 | |
455 | /* if IP and error */ | |
456 | if ((status_err & IXGBE_RXD_STAT_IPCS) && | |
457 | (status_err & IXGBE_RXDADV_ERR_IPE)) { | |
9a799d71 AK |
458 | adapter->hw_csum_rx_error++; |
459 | return; | |
460 | } | |
e59bd25d AV |
461 | |
462 | if (!(status_err & IXGBE_RXD_STAT_L4CS)) | |
463 | return; | |
464 | ||
465 | if (status_err & IXGBE_RXDADV_ERR_TCPE) { | |
466 | adapter->hw_csum_rx_error++; | |
467 | return; | |
468 | } | |
469 | ||
9a799d71 | 470 | /* It must be a TCP or UDP packet with a valid checksum */ |
e59bd25d | 471 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
9a799d71 AK |
472 | adapter->hw_csum_rx_good++; |
473 | } | |
474 | ||
475 | /** | |
476 | * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split | |
477 | * @adapter: address of board private structure | |
478 | **/ | |
479 | static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter, | |
7c6e0a43 JB |
480 | struct ixgbe_ring *rx_ring, |
481 | int cleaned_count) | |
9a799d71 | 482 | { |
9a799d71 AK |
483 | struct pci_dev *pdev = adapter->pdev; |
484 | union ixgbe_adv_rx_desc *rx_desc; | |
3a581073 | 485 | struct ixgbe_rx_buffer *bi; |
9a799d71 | 486 | unsigned int i; |
9a799d71 AK |
487 | |
488 | i = rx_ring->next_to_use; | |
3a581073 | 489 | bi = &rx_ring->rx_buffer_info[i]; |
9a799d71 AK |
490 | |
491 | while (cleaned_count--) { | |
492 | rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i); | |
493 | ||
762f4c57 | 494 | if (!bi->page_dma && |
3a581073 | 495 | (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) { |
3a581073 | 496 | if (!bi->page) { |
762f4c57 JB |
497 | bi->page = alloc_page(GFP_ATOMIC); |
498 | if (!bi->page) { | |
499 | adapter->alloc_rx_page_failed++; | |
500 | goto no_buffers; | |
501 | } | |
502 | bi->page_offset = 0; | |
503 | } else { | |
504 | /* use a half page if we're re-using */ | |
505 | bi->page_offset ^= (PAGE_SIZE / 2); | |
9a799d71 | 506 | } |
762f4c57 JB |
507 | |
508 | bi->page_dma = pci_map_page(pdev, bi->page, | |
509 | bi->page_offset, | |
510 | (PAGE_SIZE / 2), | |
511 | PCI_DMA_FROMDEVICE); | |
9a799d71 AK |
512 | } |
513 | ||
3a581073 | 514 | if (!bi->skb) { |
5ecc3614 JB |
515 | struct sk_buff *skb; |
516 | skb = netdev_alloc_skb(adapter->netdev, | |
517 | (rx_ring->rx_buf_len + | |
518 | NET_IP_ALIGN)); | |
9a799d71 AK |
519 | |
520 | if (!skb) { | |
521 | adapter->alloc_rx_buff_failed++; | |
522 | goto no_buffers; | |
523 | } | |
524 | ||
525 | /* | |
526 | * Make buffer alignment 2 beyond a 16 byte boundary | |
527 | * this will result in a 16 byte aligned IP header after | |
528 | * the 14 byte MAC header is removed | |
529 | */ | |
530 | skb_reserve(skb, NET_IP_ALIGN); | |
531 | ||
3a581073 | 532 | bi->skb = skb; |
5ecc3614 JB |
533 | bi->dma = pci_map_single(pdev, skb->data, |
534 | rx_ring->rx_buf_len, | |
3a581073 | 535 | PCI_DMA_FROMDEVICE); |
9a799d71 AK |
536 | } |
537 | /* Refresh the desc even if buffer_addrs didn't change because | |
538 | * each write-back erases this info. */ | |
539 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { | |
3a581073 JB |
540 | rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma); |
541 | rx_desc->read.hdr_addr = cpu_to_le64(bi->dma); | |
9a799d71 | 542 | } else { |
3a581073 | 543 | rx_desc->read.pkt_addr = cpu_to_le64(bi->dma); |
9a799d71 AK |
544 | } |
545 | ||
546 | i++; | |
547 | if (i == rx_ring->count) | |
548 | i = 0; | |
3a581073 | 549 | bi = &rx_ring->rx_buffer_info[i]; |
9a799d71 | 550 | } |
7c6e0a43 | 551 | |
9a799d71 AK |
552 | no_buffers: |
553 | if (rx_ring->next_to_use != i) { | |
554 | rx_ring->next_to_use = i; | |
555 | if (i-- == 0) | |
556 | i = (rx_ring->count - 1); | |
557 | ||
558 | /* | |
559 | * Force memory writes to complete before letting h/w | |
560 | * know there are new descriptors to fetch. (Only | |
561 | * applicable for weak-ordered memory model archs, | |
562 | * such as IA-64). | |
563 | */ | |
564 | wmb(); | |
565 | writel(i, adapter->hw.hw_addr + rx_ring->tail); | |
566 | } | |
567 | } | |
568 | ||
7c6e0a43 JB |
569 | static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc) |
570 | { | |
571 | return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info; | |
572 | } | |
573 | ||
574 | static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc) | |
575 | { | |
576 | return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; | |
577 | } | |
578 | ||
78b6f4ce | 579 | static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, |
b4617240 PW |
580 | struct ixgbe_ring *rx_ring, |
581 | int *work_done, int work_to_do) | |
9a799d71 | 582 | { |
78b6f4ce | 583 | struct ixgbe_adapter *adapter = q_vector->adapter; |
9a799d71 AK |
584 | struct pci_dev *pdev = adapter->pdev; |
585 | union ixgbe_adv_rx_desc *rx_desc, *next_rxd; | |
586 | struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer; | |
587 | struct sk_buff *skb; | |
588 | unsigned int i; | |
7c6e0a43 | 589 | u32 len, staterr; |
177db6ff MC |
590 | u16 hdr_info; |
591 | bool cleaned = false; | |
9a799d71 | 592 | int cleaned_count = 0; |
d2f4fbe2 | 593 | unsigned int total_rx_bytes = 0, total_rx_packets = 0; |
9a799d71 AK |
594 | |
595 | i = rx_ring->next_to_clean; | |
9a799d71 AK |
596 | rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i); |
597 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
598 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; | |
9a799d71 AK |
599 | |
600 | while (staterr & IXGBE_RXD_STAT_DD) { | |
7c6e0a43 | 601 | u32 upper_len = 0; |
9a799d71 AK |
602 | if (*work_done >= work_to_do) |
603 | break; | |
604 | (*work_done)++; | |
605 | ||
606 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { | |
7c6e0a43 JB |
607 | hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc)); |
608 | len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >> | |
762f4c57 | 609 | IXGBE_RXDADV_HDRBUFLEN_SHIFT; |
9a799d71 AK |
610 | if (hdr_info & IXGBE_RXDADV_SPH) |
611 | adapter->rx_hdr_split++; | |
612 | if (len > IXGBE_RX_HDR_SIZE) | |
613 | len = IXGBE_RX_HDR_SIZE; | |
614 | upper_len = le16_to_cpu(rx_desc->wb.upper.length); | |
7c6e0a43 | 615 | } else { |
9a799d71 | 616 | len = le16_to_cpu(rx_desc->wb.upper.length); |
7c6e0a43 | 617 | } |
9a799d71 AK |
618 | |
619 | cleaned = true; | |
620 | skb = rx_buffer_info->skb; | |
621 | prefetch(skb->data - NET_IP_ALIGN); | |
622 | rx_buffer_info->skb = NULL; | |
623 | ||
624 | if (len && !skb_shinfo(skb)->nr_frags) { | |
625 | pci_unmap_single(pdev, rx_buffer_info->dma, | |
5ecc3614 | 626 | rx_ring->rx_buf_len, |
b4617240 | 627 | PCI_DMA_FROMDEVICE); |
9a799d71 AK |
628 | skb_put(skb, len); |
629 | } | |
630 | ||
631 | if (upper_len) { | |
632 | pci_unmap_page(pdev, rx_buffer_info->page_dma, | |
762f4c57 | 633 | PAGE_SIZE / 2, PCI_DMA_FROMDEVICE); |
9a799d71 AK |
634 | rx_buffer_info->page_dma = 0; |
635 | skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, | |
762f4c57 JB |
636 | rx_buffer_info->page, |
637 | rx_buffer_info->page_offset, | |
638 | upper_len); | |
639 | ||
640 | if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) || | |
641 | (page_count(rx_buffer_info->page) != 1)) | |
642 | rx_buffer_info->page = NULL; | |
643 | else | |
644 | get_page(rx_buffer_info->page); | |
9a799d71 AK |
645 | |
646 | skb->len += upper_len; | |
647 | skb->data_len += upper_len; | |
648 | skb->truesize += upper_len; | |
649 | } | |
650 | ||
651 | i++; | |
652 | if (i == rx_ring->count) | |
653 | i = 0; | |
654 | next_buffer = &rx_ring->rx_buffer_info[i]; | |
655 | ||
656 | next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i); | |
657 | prefetch(next_rxd); | |
658 | ||
659 | cleaned_count++; | |
660 | if (staterr & IXGBE_RXD_STAT_EOP) { | |
661 | rx_ring->stats.packets++; | |
662 | rx_ring->stats.bytes += skb->len; | |
663 | } else { | |
664 | rx_buffer_info->skb = next_buffer->skb; | |
665 | rx_buffer_info->dma = next_buffer->dma; | |
666 | next_buffer->skb = skb; | |
762f4c57 | 667 | next_buffer->dma = 0; |
9a799d71 AK |
668 | adapter->non_eop_descs++; |
669 | goto next_desc; | |
670 | } | |
671 | ||
672 | if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) { | |
673 | dev_kfree_skb_irq(skb); | |
674 | goto next_desc; | |
675 | } | |
676 | ||
677 | ixgbe_rx_checksum(adapter, staterr, skb); | |
d2f4fbe2 AV |
678 | |
679 | /* probably a little skewed due to removing CRC */ | |
680 | total_rx_bytes += skb->len; | |
681 | total_rx_packets++; | |
682 | ||
74ce8dd2 | 683 | skb->protocol = eth_type_trans(skb, adapter->netdev); |
78b6f4ce | 684 | ixgbe_receive_skb(q_vector, skb, staterr, rx_desc); |
9a799d71 AK |
685 | |
686 | next_desc: | |
687 | rx_desc->wb.upper.status_error = 0; | |
688 | ||
689 | /* return some buffers to hardware, one at a time is too slow */ | |
690 | if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) { | |
691 | ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count); | |
692 | cleaned_count = 0; | |
693 | } | |
694 | ||
695 | /* use prefetched values */ | |
696 | rx_desc = next_rxd; | |
697 | rx_buffer_info = next_buffer; | |
698 | ||
699 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
177db6ff MC |
700 | } |
701 | ||
9a799d71 AK |
702 | rx_ring->next_to_clean = i; |
703 | cleaned_count = IXGBE_DESC_UNUSED(rx_ring); | |
704 | ||
705 | if (cleaned_count) | |
706 | ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count); | |
707 | ||
f494e8fa AV |
708 | rx_ring->total_packets += total_rx_packets; |
709 | rx_ring->total_bytes += total_rx_bytes; | |
710 | adapter->net_stats.rx_bytes += total_rx_bytes; | |
711 | adapter->net_stats.rx_packets += total_rx_packets; | |
712 | ||
9a799d71 AK |
713 | return cleaned; |
714 | } | |
715 | ||
021230d4 | 716 | static int ixgbe_clean_rxonly(struct napi_struct *, int); |
9a799d71 AK |
717 | /** |
718 | * ixgbe_configure_msix - Configure MSI-X hardware | |
719 | * @adapter: board private structure | |
720 | * | |
721 | * ixgbe_configure_msix sets up the hardware to properly generate MSI-X | |
722 | * interrupts. | |
723 | **/ | |
724 | static void ixgbe_configure_msix(struct ixgbe_adapter *adapter) | |
725 | { | |
021230d4 AV |
726 | struct ixgbe_q_vector *q_vector; |
727 | int i, j, q_vectors, v_idx, r_idx; | |
728 | u32 mask; | |
9a799d71 | 729 | |
021230d4 | 730 | q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; |
9a799d71 | 731 | |
021230d4 AV |
732 | /* Populate the IVAR table and set the ITR values to the |
733 | * corresponding register. | |
734 | */ | |
735 | for (v_idx = 0; v_idx < q_vectors; v_idx++) { | |
736 | q_vector = &adapter->q_vector[v_idx]; | |
737 | /* XXX for_each_bit(...) */ | |
738 | r_idx = find_first_bit(q_vector->rxr_idx, | |
b4617240 | 739 | adapter->num_rx_queues); |
021230d4 AV |
740 | |
741 | for (i = 0; i < q_vector->rxr_count; i++) { | |
742 | j = adapter->rx_ring[r_idx].reg_idx; | |
743 | ixgbe_set_ivar(adapter, IXGBE_IVAR_RX_QUEUE(j), v_idx); | |
744 | r_idx = find_next_bit(q_vector->rxr_idx, | |
b4617240 PW |
745 | adapter->num_rx_queues, |
746 | r_idx + 1); | |
021230d4 AV |
747 | } |
748 | r_idx = find_first_bit(q_vector->txr_idx, | |
b4617240 | 749 | adapter->num_tx_queues); |
021230d4 AV |
750 | |
751 | for (i = 0; i < q_vector->txr_count; i++) { | |
752 | j = adapter->tx_ring[r_idx].reg_idx; | |
753 | ixgbe_set_ivar(adapter, IXGBE_IVAR_TX_QUEUE(j), v_idx); | |
754 | r_idx = find_next_bit(q_vector->txr_idx, | |
b4617240 PW |
755 | adapter->num_tx_queues, |
756 | r_idx + 1); | |
021230d4 AV |
757 | } |
758 | ||
30efa5a3 | 759 | /* if this is a tx only vector halve the interrupt rate */ |
021230d4 | 760 | if (q_vector->txr_count && !q_vector->rxr_count) |
30efa5a3 | 761 | q_vector->eitr = (adapter->eitr_param >> 1); |
021230d4 | 762 | else |
30efa5a3 JB |
763 | /* rx only */ |
764 | q_vector->eitr = adapter->eitr_param; | |
021230d4 AV |
765 | |
766 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), | |
b4617240 | 767 | EITR_INTS_PER_SEC_TO_REG(q_vector->eitr)); |
9a799d71 AK |
768 | } |
769 | ||
021230d4 AV |
770 | ixgbe_set_ivar(adapter, IXGBE_IVAR_OTHER_CAUSES_INDEX, v_idx); |
771 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950); | |
772 | ||
41fb9248 | 773 | /* set up to autoclear timer, and the vectors */ |
021230d4 | 774 | mask = IXGBE_EIMS_ENABLE_MASK; |
41fb9248 | 775 | mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC); |
021230d4 | 776 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask); |
9a799d71 AK |
777 | } |
778 | ||
f494e8fa AV |
779 | enum latency_range { |
780 | lowest_latency = 0, | |
781 | low_latency = 1, | |
782 | bulk_latency = 2, | |
783 | latency_invalid = 255 | |
784 | }; | |
785 | ||
786 | /** | |
787 | * ixgbe_update_itr - update the dynamic ITR value based on statistics | |
788 | * @adapter: pointer to adapter | |
789 | * @eitr: eitr setting (ints per sec) to give last timeslice | |
790 | * @itr_setting: current throttle rate in ints/second | |
791 | * @packets: the number of packets during this measurement interval | |
792 | * @bytes: the number of bytes during this measurement interval | |
793 | * | |
794 | * Stores a new ITR value based on packets and byte | |
795 | * counts during the last interrupt. The advantage of per interrupt | |
796 | * computation is faster updates and more accurate ITR for the current | |
797 | * traffic pattern. Constants in this function were computed | |
798 | * based on theoretical maximum wire speed and thresholds were set based | |
799 | * on testing data as well as attempting to minimize response time | |
800 | * while increasing bulk throughput. | |
801 | * this functionality is controlled by the InterruptThrottleRate module | |
802 | * parameter (see ixgbe_param.c) | |
803 | **/ | |
804 | static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter, | |
b4617240 PW |
805 | u32 eitr, u8 itr_setting, |
806 | int packets, int bytes) | |
f494e8fa AV |
807 | { |
808 | unsigned int retval = itr_setting; | |
809 | u32 timepassed_us; | |
810 | u64 bytes_perint; | |
811 | ||
812 | if (packets == 0) | |
813 | goto update_itr_done; | |
814 | ||
815 | ||
816 | /* simple throttlerate management | |
817 | * 0-20MB/s lowest (100000 ints/s) | |
818 | * 20-100MB/s low (20000 ints/s) | |
819 | * 100-1249MB/s bulk (8000 ints/s) | |
820 | */ | |
821 | /* what was last interrupt timeslice? */ | |
822 | timepassed_us = 1000000/eitr; | |
823 | bytes_perint = bytes / timepassed_us; /* bytes/usec */ | |
824 | ||
825 | switch (itr_setting) { | |
826 | case lowest_latency: | |
827 | if (bytes_perint > adapter->eitr_low) | |
828 | retval = low_latency; | |
829 | break; | |
830 | case low_latency: | |
831 | if (bytes_perint > adapter->eitr_high) | |
832 | retval = bulk_latency; | |
833 | else if (bytes_perint <= adapter->eitr_low) | |
834 | retval = lowest_latency; | |
835 | break; | |
836 | case bulk_latency: | |
837 | if (bytes_perint <= adapter->eitr_high) | |
838 | retval = low_latency; | |
839 | break; | |
840 | } | |
841 | ||
842 | update_itr_done: | |
843 | return retval; | |
844 | } | |
845 | ||
846 | static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector) | |
847 | { | |
848 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
849 | struct ixgbe_hw *hw = &adapter->hw; | |
850 | u32 new_itr; | |
851 | u8 current_itr, ret_itr; | |
852 | int i, r_idx, v_idx = ((void *)q_vector - (void *)(adapter->q_vector)) / | |
b4617240 | 853 | sizeof(struct ixgbe_q_vector); |
f494e8fa AV |
854 | struct ixgbe_ring *rx_ring, *tx_ring; |
855 | ||
856 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
857 | for (i = 0; i < q_vector->txr_count; i++) { | |
858 | tx_ring = &(adapter->tx_ring[r_idx]); | |
859 | ret_itr = ixgbe_update_itr(adapter, q_vector->eitr, | |
b4617240 PW |
860 | q_vector->tx_itr, |
861 | tx_ring->total_packets, | |
862 | tx_ring->total_bytes); | |
f494e8fa AV |
863 | /* if the result for this queue would decrease interrupt |
864 | * rate for this vector then use that result */ | |
30efa5a3 | 865 | q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ? |
b4617240 | 866 | q_vector->tx_itr - 1 : ret_itr); |
f494e8fa | 867 | r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, |
b4617240 | 868 | r_idx + 1); |
f494e8fa AV |
869 | } |
870 | ||
871 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
872 | for (i = 0; i < q_vector->rxr_count; i++) { | |
873 | rx_ring = &(adapter->rx_ring[r_idx]); | |
874 | ret_itr = ixgbe_update_itr(adapter, q_vector->eitr, | |
b4617240 PW |
875 | q_vector->rx_itr, |
876 | rx_ring->total_packets, | |
877 | rx_ring->total_bytes); | |
f494e8fa AV |
878 | /* if the result for this queue would decrease interrupt |
879 | * rate for this vector then use that result */ | |
30efa5a3 | 880 | q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ? |
b4617240 | 881 | q_vector->rx_itr - 1 : ret_itr); |
f494e8fa | 882 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, |
b4617240 | 883 | r_idx + 1); |
f494e8fa AV |
884 | } |
885 | ||
30efa5a3 | 886 | current_itr = max(q_vector->rx_itr, q_vector->tx_itr); |
f494e8fa AV |
887 | |
888 | switch (current_itr) { | |
889 | /* counts and packets in update_itr are dependent on these numbers */ | |
890 | case lowest_latency: | |
891 | new_itr = 100000; | |
892 | break; | |
893 | case low_latency: | |
894 | new_itr = 20000; /* aka hwitr = ~200 */ | |
895 | break; | |
896 | case bulk_latency: | |
897 | default: | |
898 | new_itr = 8000; | |
899 | break; | |
900 | } | |
901 | ||
902 | if (new_itr != q_vector->eitr) { | |
903 | u32 itr_reg; | |
904 | /* do an exponential smoothing */ | |
905 | new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100); | |
906 | q_vector->eitr = new_itr; | |
907 | itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr); | |
908 | /* must write high and low 16 bits to reset counter */ | |
909 | DPRINTK(TX_ERR, DEBUG, "writing eitr(%d): %08X\n", v_idx, | |
b4617240 | 910 | itr_reg); |
f494e8fa AV |
911 | IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg | (itr_reg)<<16); |
912 | } | |
913 | ||
914 | return; | |
915 | } | |
916 | ||
0befdb3e JB |
917 | static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr) |
918 | { | |
919 | struct ixgbe_hw *hw = &adapter->hw; | |
920 | ||
921 | if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) && | |
922 | (eicr & IXGBE_EICR_GPI_SDP1)) { | |
923 | DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n"); | |
924 | /* write to clear the interrupt */ | |
925 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); | |
926 | } | |
927 | } | |
cf8280ee JB |
928 | |
929 | static void ixgbe_check_lsc(struct ixgbe_adapter *adapter) | |
930 | { | |
931 | struct ixgbe_hw *hw = &adapter->hw; | |
932 | ||
933 | adapter->lsc_int++; | |
934 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; | |
935 | adapter->link_check_timeout = jiffies; | |
936 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { | |
937 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); | |
938 | schedule_work(&adapter->watchdog_task); | |
939 | } | |
940 | } | |
941 | ||
9a799d71 AK |
942 | static irqreturn_t ixgbe_msix_lsc(int irq, void *data) |
943 | { | |
944 | struct net_device *netdev = data; | |
945 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
946 | struct ixgbe_hw *hw = &adapter->hw; | |
947 | u32 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); | |
948 | ||
cf8280ee JB |
949 | if (eicr & IXGBE_EICR_LSC) |
950 | ixgbe_check_lsc(adapter); | |
d4f80882 | 951 | |
0befdb3e JB |
952 | ixgbe_check_fan_failure(adapter, eicr); |
953 | ||
d4f80882 AV |
954 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
955 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER); | |
9a799d71 AK |
956 | |
957 | return IRQ_HANDLED; | |
958 | } | |
959 | ||
960 | static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data) | |
961 | { | |
021230d4 AV |
962 | struct ixgbe_q_vector *q_vector = data; |
963 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
3a581073 | 964 | struct ixgbe_ring *tx_ring; |
021230d4 AV |
965 | int i, r_idx; |
966 | ||
967 | if (!q_vector->txr_count) | |
968 | return IRQ_HANDLED; | |
969 | ||
970 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
971 | for (i = 0; i < q_vector->txr_count; i++) { | |
3a581073 | 972 | tx_ring = &(adapter->tx_ring[r_idx]); |
5dd2d332 | 973 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 974 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) |
3a581073 | 975 | ixgbe_update_tx_dca(adapter, tx_ring); |
bd0362dd | 976 | #endif |
3a581073 JB |
977 | tx_ring->total_bytes = 0; |
978 | tx_ring->total_packets = 0; | |
979 | ixgbe_clean_tx_irq(adapter, tx_ring); | |
021230d4 | 980 | r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, |
b4617240 | 981 | r_idx + 1); |
021230d4 | 982 | } |
9a799d71 | 983 | |
9a799d71 AK |
984 | return IRQ_HANDLED; |
985 | } | |
986 | ||
021230d4 AV |
987 | /** |
988 | * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues) | |
989 | * @irq: unused | |
990 | * @data: pointer to our q_vector struct for this interrupt vector | |
991 | **/ | |
9a799d71 AK |
992 | static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data) |
993 | { | |
021230d4 AV |
994 | struct ixgbe_q_vector *q_vector = data; |
995 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
3a581073 | 996 | struct ixgbe_ring *rx_ring; |
021230d4 | 997 | int r_idx; |
30efa5a3 | 998 | int i; |
021230d4 AV |
999 | |
1000 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
30efa5a3 JB |
1001 | for (i = 0; i < q_vector->rxr_count; i++) { |
1002 | rx_ring = &(adapter->rx_ring[r_idx]); | |
1003 | rx_ring->total_bytes = 0; | |
1004 | rx_ring->total_packets = 0; | |
1005 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, | |
1006 | r_idx + 1); | |
1007 | } | |
1008 | ||
021230d4 AV |
1009 | if (!q_vector->rxr_count) |
1010 | return IRQ_HANDLED; | |
1011 | ||
30efa5a3 | 1012 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); |
3a581073 | 1013 | rx_ring = &(adapter->rx_ring[r_idx]); |
021230d4 | 1014 | /* disable interrupts on this vector only */ |
3a581073 | 1015 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, rx_ring->v_idx); |
288379f0 | 1016 | napi_schedule(&q_vector->napi); |
021230d4 AV |
1017 | |
1018 | return IRQ_HANDLED; | |
1019 | } | |
1020 | ||
1021 | static irqreturn_t ixgbe_msix_clean_many(int irq, void *data) | |
1022 | { | |
1023 | ixgbe_msix_clean_rx(irq, data); | |
1024 | ixgbe_msix_clean_tx(irq, data); | |
9a799d71 | 1025 | |
9a799d71 AK |
1026 | return IRQ_HANDLED; |
1027 | } | |
1028 | ||
021230d4 AV |
1029 | /** |
1030 | * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine | |
1031 | * @napi: napi struct with our devices info in it | |
1032 | * @budget: amount of work driver is allowed to do this pass, in packets | |
1033 | * | |
f0848276 JB |
1034 | * This function is optimized for cleaning one queue only on a single |
1035 | * q_vector!!! | |
021230d4 | 1036 | **/ |
9a799d71 AK |
1037 | static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget) |
1038 | { | |
021230d4 | 1039 | struct ixgbe_q_vector *q_vector = |
b4617240 | 1040 | container_of(napi, struct ixgbe_q_vector, napi); |
021230d4 | 1041 | struct ixgbe_adapter *adapter = q_vector->adapter; |
f0848276 | 1042 | struct ixgbe_ring *rx_ring = NULL; |
9a799d71 | 1043 | int work_done = 0; |
021230d4 | 1044 | long r_idx; |
9a799d71 | 1045 | |
021230d4 | 1046 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); |
3a581073 | 1047 | rx_ring = &(adapter->rx_ring[r_idx]); |
5dd2d332 | 1048 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 1049 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) |
3a581073 | 1050 | ixgbe_update_rx_dca(adapter, rx_ring); |
bd0362dd | 1051 | #endif |
9a799d71 | 1052 | |
78b6f4ce | 1053 | ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget); |
9a799d71 | 1054 | |
021230d4 AV |
1055 | /* If all Rx work done, exit the polling mode */ |
1056 | if (work_done < budget) { | |
288379f0 | 1057 | napi_complete(napi); |
30efa5a3 | 1058 | if (adapter->itr_setting & 3) |
f494e8fa | 1059 | ixgbe_set_itr_msix(q_vector); |
9a799d71 | 1060 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
3a581073 | 1061 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, rx_ring->v_idx); |
9a799d71 AK |
1062 | } |
1063 | ||
1064 | return work_done; | |
1065 | } | |
1066 | ||
f0848276 JB |
1067 | /** |
1068 | * ixgbe_clean_rxonly_many - msix (aka one shot) rx clean routine | |
1069 | * @napi: napi struct with our devices info in it | |
1070 | * @budget: amount of work driver is allowed to do this pass, in packets | |
1071 | * | |
1072 | * This function will clean more than one rx queue associated with a | |
1073 | * q_vector. | |
1074 | **/ | |
1075 | static int ixgbe_clean_rxonly_many(struct napi_struct *napi, int budget) | |
1076 | { | |
1077 | struct ixgbe_q_vector *q_vector = | |
1078 | container_of(napi, struct ixgbe_q_vector, napi); | |
1079 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
f0848276 JB |
1080 | struct ixgbe_ring *rx_ring = NULL; |
1081 | int work_done = 0, i; | |
1082 | long r_idx; | |
1083 | u16 enable_mask = 0; | |
1084 | ||
1085 | /* attempt to distribute budget to each queue fairly, but don't allow | |
1086 | * the budget to go below 1 because we'll exit polling */ | |
1087 | budget /= (q_vector->rxr_count ?: 1); | |
1088 | budget = max(budget, 1); | |
1089 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
1090 | for (i = 0; i < q_vector->rxr_count; i++) { | |
1091 | rx_ring = &(adapter->rx_ring[r_idx]); | |
5dd2d332 | 1092 | #ifdef CONFIG_IXGBE_DCA |
f0848276 JB |
1093 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) |
1094 | ixgbe_update_rx_dca(adapter, rx_ring); | |
1095 | #endif | |
78b6f4ce | 1096 | ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget); |
f0848276 JB |
1097 | enable_mask |= rx_ring->v_idx; |
1098 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, | |
1099 | r_idx + 1); | |
1100 | } | |
1101 | ||
1102 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
1103 | rx_ring = &(adapter->rx_ring[r_idx]); | |
1104 | /* If all Rx work done, exit the polling mode */ | |
7f821875 | 1105 | if (work_done < budget) { |
288379f0 | 1106 | napi_complete(napi); |
f0848276 JB |
1107 | if (adapter->itr_setting & 3) |
1108 | ixgbe_set_itr_msix(q_vector); | |
1109 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
1110 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, enable_mask); | |
1111 | return 0; | |
1112 | } | |
1113 | ||
1114 | return work_done; | |
1115 | } | |
021230d4 | 1116 | static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx, |
b4617240 | 1117 | int r_idx) |
021230d4 AV |
1118 | { |
1119 | a->q_vector[v_idx].adapter = a; | |
1120 | set_bit(r_idx, a->q_vector[v_idx].rxr_idx); | |
1121 | a->q_vector[v_idx].rxr_count++; | |
1122 | a->rx_ring[r_idx].v_idx = 1 << v_idx; | |
1123 | } | |
1124 | ||
1125 | static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx, | |
b4617240 | 1126 | int r_idx) |
021230d4 AV |
1127 | { |
1128 | a->q_vector[v_idx].adapter = a; | |
1129 | set_bit(r_idx, a->q_vector[v_idx].txr_idx); | |
1130 | a->q_vector[v_idx].txr_count++; | |
1131 | a->tx_ring[r_idx].v_idx = 1 << v_idx; | |
1132 | } | |
1133 | ||
9a799d71 | 1134 | /** |
021230d4 AV |
1135 | * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors |
1136 | * @adapter: board private structure to initialize | |
1137 | * @vectors: allotted vector count for descriptor rings | |
9a799d71 | 1138 | * |
021230d4 AV |
1139 | * This function maps descriptor rings to the queue-specific vectors |
1140 | * we were allotted through the MSI-X enabling code. Ideally, we'd have | |
1141 | * one vector per ring/queue, but on a constrained vector budget, we | |
1142 | * group the rings as "efficiently" as possible. You would add new | |
1143 | * mapping configurations in here. | |
9a799d71 | 1144 | **/ |
021230d4 | 1145 | static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter, |
b4617240 | 1146 | int vectors) |
021230d4 AV |
1147 | { |
1148 | int v_start = 0; | |
1149 | int rxr_idx = 0, txr_idx = 0; | |
1150 | int rxr_remaining = adapter->num_rx_queues; | |
1151 | int txr_remaining = adapter->num_tx_queues; | |
1152 | int i, j; | |
1153 | int rqpv, tqpv; | |
1154 | int err = 0; | |
1155 | ||
1156 | /* No mapping required if MSI-X is disabled. */ | |
1157 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
1158 | goto out; | |
9a799d71 | 1159 | |
021230d4 AV |
1160 | /* |
1161 | * The ideal configuration... | |
1162 | * We have enough vectors to map one per queue. | |
1163 | */ | |
1164 | if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) { | |
1165 | for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++) | |
1166 | map_vector_to_rxq(adapter, v_start, rxr_idx); | |
9a799d71 | 1167 | |
021230d4 AV |
1168 | for (; txr_idx < txr_remaining; v_start++, txr_idx++) |
1169 | map_vector_to_txq(adapter, v_start, txr_idx); | |
9a799d71 | 1170 | |
9a799d71 | 1171 | goto out; |
021230d4 | 1172 | } |
9a799d71 | 1173 | |
021230d4 AV |
1174 | /* |
1175 | * If we don't have enough vectors for a 1-to-1 | |
1176 | * mapping, we'll have to group them so there are | |
1177 | * multiple queues per vector. | |
1178 | */ | |
1179 | /* Re-adjusting *qpv takes care of the remainder. */ | |
1180 | for (i = v_start; i < vectors; i++) { | |
1181 | rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i); | |
1182 | for (j = 0; j < rqpv; j++) { | |
1183 | map_vector_to_rxq(adapter, i, rxr_idx); | |
1184 | rxr_idx++; | |
1185 | rxr_remaining--; | |
1186 | } | |
1187 | } | |
1188 | for (i = v_start; i < vectors; i++) { | |
1189 | tqpv = DIV_ROUND_UP(txr_remaining, vectors - i); | |
1190 | for (j = 0; j < tqpv; j++) { | |
1191 | map_vector_to_txq(adapter, i, txr_idx); | |
1192 | txr_idx++; | |
1193 | txr_remaining--; | |
9a799d71 | 1194 | } |
9a799d71 AK |
1195 | } |
1196 | ||
021230d4 AV |
1197 | out: |
1198 | return err; | |
1199 | } | |
1200 | ||
1201 | /** | |
1202 | * ixgbe_request_msix_irqs - Initialize MSI-X interrupts | |
1203 | * @adapter: board private structure | |
1204 | * | |
1205 | * ixgbe_request_msix_irqs allocates MSI-X vectors and requests | |
1206 | * interrupts from the kernel. | |
1207 | **/ | |
1208 | static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter) | |
1209 | { | |
1210 | struct net_device *netdev = adapter->netdev; | |
1211 | irqreturn_t (*handler)(int, void *); | |
1212 | int i, vector, q_vectors, err; | |
cb13fc20 | 1213 | int ri=0, ti=0; |
021230d4 AV |
1214 | |
1215 | /* Decrement for Other and TCP Timer vectors */ | |
1216 | q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
1217 | ||
1218 | /* Map the Tx/Rx rings to the vectors we were allotted. */ | |
1219 | err = ixgbe_map_rings_to_vectors(adapter, q_vectors); | |
1220 | if (err) | |
1221 | goto out; | |
1222 | ||
1223 | #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \ | |
b4617240 PW |
1224 | (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \ |
1225 | &ixgbe_msix_clean_many) | |
021230d4 AV |
1226 | for (vector = 0; vector < q_vectors; vector++) { |
1227 | handler = SET_HANDLER(&adapter->q_vector[vector]); | |
cb13fc20 RO |
1228 | |
1229 | if(handler == &ixgbe_msix_clean_rx) { | |
1230 | sprintf(adapter->name[vector], "%s-%s-%d", | |
1231 | netdev->name, "rx", ri++); | |
1232 | } | |
1233 | else if(handler == &ixgbe_msix_clean_tx) { | |
1234 | sprintf(adapter->name[vector], "%s-%s-%d", | |
1235 | netdev->name, "tx", ti++); | |
1236 | } | |
1237 | else | |
1238 | sprintf(adapter->name[vector], "%s-%s-%d", | |
1239 | netdev->name, "TxRx", vector); | |
1240 | ||
021230d4 | 1241 | err = request_irq(adapter->msix_entries[vector].vector, |
b4617240 PW |
1242 | handler, 0, adapter->name[vector], |
1243 | &(adapter->q_vector[vector])); | |
9a799d71 AK |
1244 | if (err) { |
1245 | DPRINTK(PROBE, ERR, | |
b4617240 PW |
1246 | "request_irq failed for MSIX interrupt " |
1247 | "Error: %d\n", err); | |
021230d4 | 1248 | goto free_queue_irqs; |
9a799d71 | 1249 | } |
9a799d71 AK |
1250 | } |
1251 | ||
021230d4 AV |
1252 | sprintf(adapter->name[vector], "%s:lsc", netdev->name); |
1253 | err = request_irq(adapter->msix_entries[vector].vector, | |
b4617240 | 1254 | &ixgbe_msix_lsc, 0, adapter->name[vector], netdev); |
9a799d71 AK |
1255 | if (err) { |
1256 | DPRINTK(PROBE, ERR, | |
1257 | "request_irq for msix_lsc failed: %d\n", err); | |
021230d4 | 1258 | goto free_queue_irqs; |
9a799d71 AK |
1259 | } |
1260 | ||
9a799d71 AK |
1261 | return 0; |
1262 | ||
021230d4 AV |
1263 | free_queue_irqs: |
1264 | for (i = vector - 1; i >= 0; i--) | |
1265 | free_irq(adapter->msix_entries[--vector].vector, | |
b4617240 | 1266 | &(adapter->q_vector[i])); |
021230d4 AV |
1267 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; |
1268 | pci_disable_msix(adapter->pdev); | |
9a799d71 AK |
1269 | kfree(adapter->msix_entries); |
1270 | adapter->msix_entries = NULL; | |
021230d4 | 1271 | out: |
9a799d71 AK |
1272 | return err; |
1273 | } | |
1274 | ||
f494e8fa AV |
1275 | static void ixgbe_set_itr(struct ixgbe_adapter *adapter) |
1276 | { | |
1277 | struct ixgbe_hw *hw = &adapter->hw; | |
1278 | struct ixgbe_q_vector *q_vector = adapter->q_vector; | |
1279 | u8 current_itr; | |
1280 | u32 new_itr = q_vector->eitr; | |
1281 | struct ixgbe_ring *rx_ring = &adapter->rx_ring[0]; | |
1282 | struct ixgbe_ring *tx_ring = &adapter->tx_ring[0]; | |
1283 | ||
30efa5a3 | 1284 | q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr, |
b4617240 PW |
1285 | q_vector->tx_itr, |
1286 | tx_ring->total_packets, | |
1287 | tx_ring->total_bytes); | |
30efa5a3 | 1288 | q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr, |
b4617240 PW |
1289 | q_vector->rx_itr, |
1290 | rx_ring->total_packets, | |
1291 | rx_ring->total_bytes); | |
f494e8fa | 1292 | |
30efa5a3 | 1293 | current_itr = max(q_vector->rx_itr, q_vector->tx_itr); |
f494e8fa AV |
1294 | |
1295 | switch (current_itr) { | |
1296 | /* counts and packets in update_itr are dependent on these numbers */ | |
1297 | case lowest_latency: | |
1298 | new_itr = 100000; | |
1299 | break; | |
1300 | case low_latency: | |
1301 | new_itr = 20000; /* aka hwitr = ~200 */ | |
1302 | break; | |
1303 | case bulk_latency: | |
1304 | new_itr = 8000; | |
1305 | break; | |
1306 | default: | |
1307 | break; | |
1308 | } | |
1309 | ||
1310 | if (new_itr != q_vector->eitr) { | |
1311 | u32 itr_reg; | |
1312 | /* do an exponential smoothing */ | |
1313 | new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100); | |
1314 | q_vector->eitr = new_itr; | |
1315 | itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr); | |
1316 | /* must write high and low 16 bits to reset counter */ | |
1317 | IXGBE_WRITE_REG(hw, IXGBE_EITR(0), itr_reg | (itr_reg)<<16); | |
1318 | } | |
1319 | ||
1320 | return; | |
1321 | } | |
1322 | ||
79aefa45 AD |
1323 | /** |
1324 | * ixgbe_irq_disable - Mask off interrupt generation on the NIC | |
1325 | * @adapter: board private structure | |
1326 | **/ | |
1327 | static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) | |
1328 | { | |
1329 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); | |
1330 | IXGBE_WRITE_FLUSH(&adapter->hw); | |
1331 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
1332 | int i; | |
1333 | for (i = 0; i < adapter->num_msix_vectors; i++) | |
1334 | synchronize_irq(adapter->msix_entries[i].vector); | |
1335 | } else { | |
1336 | synchronize_irq(adapter->pdev->irq); | |
1337 | } | |
1338 | } | |
1339 | ||
1340 | /** | |
1341 | * ixgbe_irq_enable - Enable default interrupt generation settings | |
1342 | * @adapter: board private structure | |
1343 | **/ | |
1344 | static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter) | |
1345 | { | |
1346 | u32 mask; | |
1347 | mask = IXGBE_EIMS_ENABLE_MASK; | |
6ab33d51 DM |
1348 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) |
1349 | mask |= IXGBE_EIMS_GPI_SDP1; | |
79aefa45 AD |
1350 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); |
1351 | IXGBE_WRITE_FLUSH(&adapter->hw); | |
1352 | } | |
021230d4 | 1353 | |
9a799d71 | 1354 | /** |
021230d4 | 1355 | * ixgbe_intr - legacy mode Interrupt Handler |
9a799d71 AK |
1356 | * @irq: interrupt number |
1357 | * @data: pointer to a network interface device structure | |
9a799d71 AK |
1358 | **/ |
1359 | static irqreturn_t ixgbe_intr(int irq, void *data) | |
1360 | { | |
1361 | struct net_device *netdev = data; | |
1362 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
1363 | struct ixgbe_hw *hw = &adapter->hw; | |
1364 | u32 eicr; | |
1365 | ||
021230d4 AV |
1366 | /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read |
1367 | * therefore no explict interrupt disable is necessary */ | |
1368 | eicr = IXGBE_READ_REG(hw, IXGBE_EICR); | |
f47cf66e JB |
1369 | if (!eicr) { |
1370 | /* shared interrupt alert! | |
1371 | * make sure interrupts are enabled because the read will | |
1372 | * have disabled interrupts due to EIAM */ | |
1373 | ixgbe_irq_enable(adapter); | |
9a799d71 | 1374 | return IRQ_NONE; /* Not our interrupt */ |
f47cf66e | 1375 | } |
9a799d71 | 1376 | |
cf8280ee JB |
1377 | if (eicr & IXGBE_EICR_LSC) |
1378 | ixgbe_check_lsc(adapter); | |
021230d4 | 1379 | |
0befdb3e JB |
1380 | ixgbe_check_fan_failure(adapter, eicr); |
1381 | ||
288379f0 | 1382 | if (napi_schedule_prep(&adapter->q_vector[0].napi)) { |
f494e8fa AV |
1383 | adapter->tx_ring[0].total_packets = 0; |
1384 | adapter->tx_ring[0].total_bytes = 0; | |
1385 | adapter->rx_ring[0].total_packets = 0; | |
1386 | adapter->rx_ring[0].total_bytes = 0; | |
021230d4 | 1387 | /* would disable interrupts here but EIAM disabled it */ |
288379f0 | 1388 | __napi_schedule(&adapter->q_vector[0].napi); |
9a799d71 AK |
1389 | } |
1390 | ||
1391 | return IRQ_HANDLED; | |
1392 | } | |
1393 | ||
021230d4 AV |
1394 | static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter) |
1395 | { | |
1396 | int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
1397 | ||
1398 | for (i = 0; i < q_vectors; i++) { | |
1399 | struct ixgbe_q_vector *q_vector = &adapter->q_vector[i]; | |
1400 | bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES); | |
1401 | bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES); | |
1402 | q_vector->rxr_count = 0; | |
1403 | q_vector->txr_count = 0; | |
1404 | } | |
1405 | } | |
1406 | ||
9a799d71 AK |
1407 | /** |
1408 | * ixgbe_request_irq - initialize interrupts | |
1409 | * @adapter: board private structure | |
1410 | * | |
1411 | * Attempts to configure interrupts using the best available | |
1412 | * capabilities of the hardware and kernel. | |
1413 | **/ | |
021230d4 | 1414 | static int ixgbe_request_irq(struct ixgbe_adapter *adapter) |
9a799d71 AK |
1415 | { |
1416 | struct net_device *netdev = adapter->netdev; | |
021230d4 | 1417 | int err; |
9a799d71 | 1418 | |
021230d4 AV |
1419 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
1420 | err = ixgbe_request_msix_irqs(adapter); | |
1421 | } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) { | |
1422 | err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0, | |
b4617240 | 1423 | netdev->name, netdev); |
021230d4 AV |
1424 | } else { |
1425 | err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED, | |
b4617240 | 1426 | netdev->name, netdev); |
9a799d71 AK |
1427 | } |
1428 | ||
9a799d71 AK |
1429 | if (err) |
1430 | DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err); | |
1431 | ||
9a799d71 AK |
1432 | return err; |
1433 | } | |
1434 | ||
1435 | static void ixgbe_free_irq(struct ixgbe_adapter *adapter) | |
1436 | { | |
1437 | struct net_device *netdev = adapter->netdev; | |
1438 | ||
1439 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
021230d4 | 1440 | int i, q_vectors; |
9a799d71 | 1441 | |
021230d4 AV |
1442 | q_vectors = adapter->num_msix_vectors; |
1443 | ||
1444 | i = q_vectors - 1; | |
9a799d71 | 1445 | free_irq(adapter->msix_entries[i].vector, netdev); |
9a799d71 | 1446 | |
021230d4 AV |
1447 | i--; |
1448 | for (; i >= 0; i--) { | |
1449 | free_irq(adapter->msix_entries[i].vector, | |
b4617240 | 1450 | &(adapter->q_vector[i])); |
021230d4 AV |
1451 | } |
1452 | ||
1453 | ixgbe_reset_q_vectors(adapter); | |
1454 | } else { | |
1455 | free_irq(adapter->pdev->irq, netdev); | |
9a799d71 AK |
1456 | } |
1457 | } | |
1458 | ||
9a799d71 AK |
1459 | /** |
1460 | * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts | |
1461 | * | |
1462 | **/ | |
1463 | static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter) | |
1464 | { | |
9a799d71 AK |
1465 | struct ixgbe_hw *hw = &adapter->hw; |
1466 | ||
021230d4 | 1467 | IXGBE_WRITE_REG(hw, IXGBE_EITR(0), |
30efa5a3 | 1468 | EITR_INTS_PER_SEC_TO_REG(adapter->eitr_param)); |
9a799d71 AK |
1469 | |
1470 | ixgbe_set_ivar(adapter, IXGBE_IVAR_RX_QUEUE(0), 0); | |
021230d4 AV |
1471 | ixgbe_set_ivar(adapter, IXGBE_IVAR_TX_QUEUE(0), 0); |
1472 | ||
1473 | map_vector_to_rxq(adapter, 0, 0); | |
1474 | map_vector_to_txq(adapter, 0, 0); | |
1475 | ||
1476 | DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n"); | |
9a799d71 AK |
1477 | } |
1478 | ||
1479 | /** | |
3a581073 | 1480 | * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset |
9a799d71 AK |
1481 | * @adapter: board private structure |
1482 | * | |
1483 | * Configure the Tx unit of the MAC after a reset. | |
1484 | **/ | |
1485 | static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) | |
1486 | { | |
e01c31a5 | 1487 | u64 tdba, tdwba; |
9a799d71 | 1488 | struct ixgbe_hw *hw = &adapter->hw; |
021230d4 | 1489 | u32 i, j, tdlen, txctrl; |
9a799d71 AK |
1490 | |
1491 | /* Setup the HW Tx Head and Tail descriptor pointers */ | |
1492 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
e01c31a5 JB |
1493 | struct ixgbe_ring *ring = &adapter->tx_ring[i]; |
1494 | j = ring->reg_idx; | |
1495 | tdba = ring->dma; | |
1496 | tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc); | |
021230d4 | 1497 | IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j), |
e01c31a5 | 1498 | (tdba & DMA_32BIT_MASK)); |
021230d4 | 1499 | IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32)); |
e01c31a5 JB |
1500 | tdwba = ring->dma + |
1501 | (ring->count * sizeof(union ixgbe_adv_tx_desc)); | |
1502 | tdwba |= IXGBE_TDWBAL_HEAD_WB_ENABLE; | |
1503 | IXGBE_WRITE_REG(hw, IXGBE_TDWBAL(j), tdwba & DMA_32BIT_MASK); | |
1504 | IXGBE_WRITE_REG(hw, IXGBE_TDWBAH(j), (tdwba >> 32)); | |
021230d4 AV |
1505 | IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen); |
1506 | IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0); | |
1507 | IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0); | |
1508 | adapter->tx_ring[i].head = IXGBE_TDH(j); | |
1509 | adapter->tx_ring[i].tail = IXGBE_TDT(j); | |
1510 | /* Disable Tx Head Writeback RO bit, since this hoses | |
1511 | * bookkeeping if things aren't delivered in order. | |
1512 | */ | |
e01c31a5 | 1513 | txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j)); |
021230d4 | 1514 | txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN; |
e01c31a5 | 1515 | IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl); |
9a799d71 | 1516 | } |
9a799d71 AK |
1517 | } |
1518 | ||
cc41ac7c JB |
1519 | #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 |
1520 | ||
1521 | static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, int index) | |
1522 | { | |
1523 | struct ixgbe_ring *rx_ring; | |
1524 | u32 srrctl; | |
1525 | int queue0; | |
3be1adfb AD |
1526 | unsigned long mask; |
1527 | ||
1528 | /* program one srrctl register per VMDq index */ | |
1529 | if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) { | |
1530 | long shift, len; | |
1531 | mask = (unsigned long) adapter->ring_feature[RING_F_RSS].mask; | |
1532 | len = sizeof(adapter->ring_feature[RING_F_VMDQ].mask) * 8; | |
1533 | shift = find_first_bit(&mask, len); | |
1534 | queue0 = index & mask; | |
1535 | index = (index & mask) >> shift; | |
1536 | /* program one srrctl per RSS queue since RDRXCTL.MVMEN is enabled */ | |
cc41ac7c | 1537 | } else { |
3be1adfb AD |
1538 | mask = (unsigned long) adapter->ring_feature[RING_F_RSS].mask; |
1539 | queue0 = index & mask; | |
1540 | index = index & mask; | |
cc41ac7c | 1541 | } |
3be1adfb | 1542 | |
cc41ac7c JB |
1543 | rx_ring = &adapter->rx_ring[queue0]; |
1544 | ||
1545 | srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index)); | |
1546 | ||
1547 | srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK; | |
1548 | srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK; | |
1549 | ||
1550 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { | |
1551 | srrctl |= IXGBE_RXBUFFER_2048 >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
1552 | srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS; | |
1553 | srrctl |= ((IXGBE_RX_HDR_SIZE << | |
b4617240 PW |
1554 | IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) & |
1555 | IXGBE_SRRCTL_BSIZEHDR_MASK); | |
cc41ac7c JB |
1556 | } else { |
1557 | srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; | |
1558 | ||
1559 | if (rx_ring->rx_buf_len == MAXIMUM_ETHERNET_VLAN_SIZE) | |
1560 | srrctl |= IXGBE_RXBUFFER_2048 >> | |
1561 | IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
1562 | else | |
1563 | srrctl |= rx_ring->rx_buf_len >> | |
1564 | IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
1565 | } | |
1566 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl); | |
1567 | } | |
9a799d71 | 1568 | |
cc41ac7c | 1569 | #define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \ |
b4617240 | 1570 | (((S) & (PAGE_SIZE - 1)) ? 1 : 0)) |
cc41ac7c | 1571 | |
9a799d71 | 1572 | /** |
3a581073 | 1573 | * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset |
9a799d71 AK |
1574 | * @adapter: board private structure |
1575 | * | |
1576 | * Configure the Rx unit of the MAC after a reset. | |
1577 | **/ | |
1578 | static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) | |
1579 | { | |
1580 | u64 rdba; | |
1581 | struct ixgbe_hw *hw = &adapter->hw; | |
1582 | struct net_device *netdev = adapter->netdev; | |
1583 | int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; | |
021230d4 | 1584 | int i, j; |
9a799d71 | 1585 | u32 rdlen, rxctrl, rxcsum; |
7c6e0a43 JB |
1586 | static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D, |
1587 | 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE, | |
1588 | 0x6A3E67EA, 0x14364D17, 0x3BED200D}; | |
9a799d71 | 1589 | u32 fctrl, hlreg0; |
9a799d71 | 1590 | u32 pages; |
cc41ac7c JB |
1591 | u32 reta = 0, mrqc; |
1592 | u32 rdrxctl; | |
7c6e0a43 | 1593 | int rx_buf_len; |
9a799d71 AK |
1594 | |
1595 | /* Decide whether to use packet split mode or not */ | |
762f4c57 | 1596 | adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED; |
9a799d71 AK |
1597 | |
1598 | /* Set the RX buffer length according to the mode */ | |
1599 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { | |
7c6e0a43 | 1600 | rx_buf_len = IXGBE_RX_HDR_SIZE; |
9a799d71 AK |
1601 | } else { |
1602 | if (netdev->mtu <= ETH_DATA_LEN) | |
7c6e0a43 | 1603 | rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE; |
9a799d71 | 1604 | else |
7c6e0a43 | 1605 | rx_buf_len = ALIGN(max_frame, 1024); |
9a799d71 AK |
1606 | } |
1607 | ||
1608 | fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL); | |
1609 | fctrl |= IXGBE_FCTRL_BAM; | |
021230d4 | 1610 | fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */ |
9a799d71 AK |
1611 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl); |
1612 | ||
1613 | hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); | |
1614 | if (adapter->netdev->mtu <= ETH_DATA_LEN) | |
1615 | hlreg0 &= ~IXGBE_HLREG0_JUMBOEN; | |
1616 | else | |
1617 | hlreg0 |= IXGBE_HLREG0_JUMBOEN; | |
1618 | IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); | |
1619 | ||
1620 | pages = PAGE_USE_COUNT(adapter->netdev->mtu); | |
1621 | ||
9a799d71 AK |
1622 | rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc); |
1623 | /* disable receives while setting up the descriptors */ | |
1624 | rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); | |
1625 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); | |
1626 | ||
1627 | /* Setup the HW Rx Head and Tail Descriptor Pointers and | |
1628 | * the Base and Length of the Rx Descriptor Ring */ | |
1629 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
1630 | rdba = adapter->rx_ring[i].dma; | |
7c6e0a43 JB |
1631 | j = adapter->rx_ring[i].reg_idx; |
1632 | IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_32BIT_MASK)); | |
1633 | IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32)); | |
1634 | IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen); | |
1635 | IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0); | |
1636 | IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0); | |
1637 | adapter->rx_ring[i].head = IXGBE_RDH(j); | |
1638 | adapter->rx_ring[i].tail = IXGBE_RDT(j); | |
1639 | adapter->rx_ring[i].rx_buf_len = rx_buf_len; | |
cc41ac7c JB |
1640 | |
1641 | ixgbe_configure_srrctl(adapter, j); | |
9a799d71 AK |
1642 | } |
1643 | ||
cc41ac7c JB |
1644 | /* |
1645 | * For VMDq support of different descriptor types or | |
1646 | * buffer sizes through the use of multiple SRRCTL | |
1647 | * registers, RDRXCTL.MVMEN must be set to 1 | |
1648 | * | |
1649 | * also, the manual doesn't mention it clearly but DCA hints | |
1650 | * will only use queue 0's tags unless this bit is set. Side | |
1651 | * effects of setting this bit are only that SRRCTL must be | |
1652 | * fully programmed [0..15] | |
1653 | */ | |
2f90b865 AD |
1654 | if (adapter->flags & |
1655 | (IXGBE_FLAG_RSS_ENABLED | IXGBE_FLAG_VMDQ_ENABLED)) { | |
1656 | rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); | |
1657 | rdrxctl |= IXGBE_RDRXCTL_MVMEN; | |
1658 | IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); | |
1659 | } | |
177db6ff | 1660 | |
021230d4 | 1661 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { |
9a799d71 | 1662 | /* Fill out redirection table */ |
021230d4 AV |
1663 | for (i = 0, j = 0; i < 128; i++, j++) { |
1664 | if (j == adapter->ring_feature[RING_F_RSS].indices) | |
1665 | j = 0; | |
1666 | /* reta = 4-byte sliding window of | |
1667 | * 0x00..(indices-1)(indices-1)00..etc. */ | |
1668 | reta = (reta << 8) | (j * 0x11); | |
1669 | if ((i & 3) == 3) | |
1670 | IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); | |
9a799d71 AK |
1671 | } |
1672 | ||
1673 | /* Fill out hash function seeds */ | |
1674 | for (i = 0; i < 10; i++) | |
7c6e0a43 | 1675 | IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]); |
9a799d71 AK |
1676 | |
1677 | mrqc = IXGBE_MRQC_RSSEN | |
1678 | /* Perform hash on these packet types */ | |
7c6e0a43 JB |
1679 | | IXGBE_MRQC_RSS_FIELD_IPV4 |
1680 | | IXGBE_MRQC_RSS_FIELD_IPV4_TCP | |
1681 | | IXGBE_MRQC_RSS_FIELD_IPV4_UDP | |
1682 | | IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP | |
1683 | | IXGBE_MRQC_RSS_FIELD_IPV6_EX | |
1684 | | IXGBE_MRQC_RSS_FIELD_IPV6 | |
1685 | | IXGBE_MRQC_RSS_FIELD_IPV6_TCP | |
1686 | | IXGBE_MRQC_RSS_FIELD_IPV6_UDP | |
1687 | | IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP; | |
9a799d71 | 1688 | IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); |
021230d4 | 1689 | } |
9a799d71 | 1690 | |
021230d4 AV |
1691 | rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); |
1692 | ||
1693 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED || | |
1694 | adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) { | |
1695 | /* Disable indicating checksum in descriptor, enables | |
1696 | * RSS hash */ | |
9a799d71 | 1697 | rxcsum |= IXGBE_RXCSUM_PCSD; |
9a799d71 | 1698 | } |
021230d4 AV |
1699 | if (!(rxcsum & IXGBE_RXCSUM_PCSD)) { |
1700 | /* Enable IPv4 payload checksum for UDP fragments | |
1701 | * if PCSD is not set */ | |
1702 | rxcsum |= IXGBE_RXCSUM_IPPCSE; | |
1703 | } | |
1704 | ||
1705 | IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); | |
9a799d71 AK |
1706 | } |
1707 | ||
068c89b0 DS |
1708 | static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid) |
1709 | { | |
1710 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
1711 | struct ixgbe_hw *hw = &adapter->hw; | |
1712 | ||
1713 | /* add VID to filter table */ | |
1714 | hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true); | |
1715 | } | |
1716 | ||
1717 | static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) | |
1718 | { | |
1719 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
1720 | struct ixgbe_hw *hw = &adapter->hw; | |
1721 | ||
1722 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
1723 | ixgbe_irq_disable(adapter); | |
1724 | ||
1725 | vlan_group_set_device(adapter->vlgrp, vid, NULL); | |
1726 | ||
1727 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
1728 | ixgbe_irq_enable(adapter); | |
1729 | ||
1730 | /* remove VID from filter table */ | |
1731 | hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false); | |
1732 | } | |
1733 | ||
9a799d71 | 1734 | static void ixgbe_vlan_rx_register(struct net_device *netdev, |
b4617240 | 1735 | struct vlan_group *grp) |
9a799d71 AK |
1736 | { |
1737 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
1738 | u32 ctrl; | |
1739 | ||
d4f80882 AV |
1740 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
1741 | ixgbe_irq_disable(adapter); | |
9a799d71 AK |
1742 | adapter->vlgrp = grp; |
1743 | ||
2f90b865 AD |
1744 | /* |
1745 | * For a DCB driver, always enable VLAN tag stripping so we can | |
1746 | * still receive traffic from a DCB-enabled host even if we're | |
1747 | * not in DCB mode. | |
1748 | */ | |
1749 | ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL); | |
1750 | ctrl |= IXGBE_VLNCTRL_VME; | |
1751 | ctrl &= ~IXGBE_VLNCTRL_CFIEN; | |
1752 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl); | |
068c89b0 | 1753 | ixgbe_vlan_rx_add_vid(netdev, 0); |
2f90b865 | 1754 | |
9a799d71 AK |
1755 | if (grp) { |
1756 | /* enable VLAN tag insert/strip */ | |
1757 | ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL); | |
746b9f02 | 1758 | ctrl |= IXGBE_VLNCTRL_VME; |
9a799d71 AK |
1759 | ctrl &= ~IXGBE_VLNCTRL_CFIEN; |
1760 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl); | |
1761 | } | |
1762 | ||
d4f80882 AV |
1763 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
1764 | ixgbe_irq_enable(adapter); | |
9a799d71 AK |
1765 | } |
1766 | ||
9a799d71 AK |
1767 | static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter) |
1768 | { | |
1769 | ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp); | |
1770 | ||
1771 | if (adapter->vlgrp) { | |
1772 | u16 vid; | |
1773 | for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) { | |
1774 | if (!vlan_group_get_device(adapter->vlgrp, vid)) | |
1775 | continue; | |
1776 | ixgbe_vlan_rx_add_vid(adapter->netdev, vid); | |
1777 | } | |
1778 | } | |
1779 | } | |
1780 | ||
2c5645cf CL |
1781 | static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq) |
1782 | { | |
1783 | struct dev_mc_list *mc_ptr; | |
1784 | u8 *addr = *mc_addr_ptr; | |
1785 | *vmdq = 0; | |
1786 | ||
1787 | mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]); | |
1788 | if (mc_ptr->next) | |
1789 | *mc_addr_ptr = mc_ptr->next->dmi_addr; | |
1790 | else | |
1791 | *mc_addr_ptr = NULL; | |
1792 | ||
1793 | return addr; | |
1794 | } | |
1795 | ||
9a799d71 | 1796 | /** |
2c5645cf | 1797 | * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set |
9a799d71 AK |
1798 | * @netdev: network interface device structure |
1799 | * | |
2c5645cf CL |
1800 | * The set_rx_method entry point is called whenever the unicast/multicast |
1801 | * address list or the network interface flags are updated. This routine is | |
1802 | * responsible for configuring the hardware for proper unicast, multicast and | |
1803 | * promiscuous mode. | |
9a799d71 | 1804 | **/ |
2c5645cf | 1805 | static void ixgbe_set_rx_mode(struct net_device *netdev) |
9a799d71 AK |
1806 | { |
1807 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
1808 | struct ixgbe_hw *hw = &adapter->hw; | |
3d01625a | 1809 | u32 fctrl, vlnctrl; |
2c5645cf CL |
1810 | u8 *addr_list = NULL; |
1811 | int addr_count = 0; | |
9a799d71 AK |
1812 | |
1813 | /* Check for Promiscuous and All Multicast modes */ | |
1814 | ||
1815 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
3d01625a | 1816 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); |
9a799d71 AK |
1817 | |
1818 | if (netdev->flags & IFF_PROMISC) { | |
2c5645cf | 1819 | hw->addr_ctrl.user_set_promisc = 1; |
9a799d71 | 1820 | fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); |
3d01625a | 1821 | vlnctrl &= ~IXGBE_VLNCTRL_VFE; |
9a799d71 | 1822 | } else { |
746b9f02 PM |
1823 | if (netdev->flags & IFF_ALLMULTI) { |
1824 | fctrl |= IXGBE_FCTRL_MPE; | |
1825 | fctrl &= ~IXGBE_FCTRL_UPE; | |
1826 | } else { | |
1827 | fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); | |
1828 | } | |
3d01625a | 1829 | vlnctrl |= IXGBE_VLNCTRL_VFE; |
2c5645cf | 1830 | hw->addr_ctrl.user_set_promisc = 0; |
9a799d71 AK |
1831 | } |
1832 | ||
1833 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); | |
3d01625a | 1834 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); |
9a799d71 | 1835 | |
2c5645cf CL |
1836 | /* reprogram secondary unicast list */ |
1837 | addr_count = netdev->uc_count; | |
1838 | if (addr_count) | |
1839 | addr_list = netdev->uc_list->dmi_addr; | |
c44ade9e JB |
1840 | hw->mac.ops.update_uc_addr_list(hw, addr_list, addr_count, |
1841 | ixgbe_addr_list_itr); | |
9a799d71 | 1842 | |
2c5645cf CL |
1843 | /* reprogram multicast list */ |
1844 | addr_count = netdev->mc_count; | |
1845 | if (addr_count) | |
1846 | addr_list = netdev->mc_list->dmi_addr; | |
c44ade9e JB |
1847 | hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count, |
1848 | ixgbe_addr_list_itr); | |
9a799d71 AK |
1849 | } |
1850 | ||
021230d4 AV |
1851 | static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter) |
1852 | { | |
1853 | int q_idx; | |
1854 | struct ixgbe_q_vector *q_vector; | |
1855 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
1856 | ||
1857 | /* legacy and MSI only use one vector */ | |
1858 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
1859 | q_vectors = 1; | |
1860 | ||
1861 | for (q_idx = 0; q_idx < q_vectors; q_idx++) { | |
f0848276 | 1862 | struct napi_struct *napi; |
021230d4 AV |
1863 | q_vector = &adapter->q_vector[q_idx]; |
1864 | if (!q_vector->rxr_count) | |
1865 | continue; | |
f0848276 JB |
1866 | napi = &q_vector->napi; |
1867 | if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) && | |
1868 | (q_vector->rxr_count > 1)) | |
1869 | napi->poll = &ixgbe_clean_rxonly_many; | |
1870 | ||
1871 | napi_enable(napi); | |
021230d4 AV |
1872 | } |
1873 | } | |
1874 | ||
1875 | static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter) | |
1876 | { | |
1877 | int q_idx; | |
1878 | struct ixgbe_q_vector *q_vector; | |
1879 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
1880 | ||
1881 | /* legacy and MSI only use one vector */ | |
1882 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
1883 | q_vectors = 1; | |
1884 | ||
1885 | for (q_idx = 0; q_idx < q_vectors; q_idx++) { | |
1886 | q_vector = &adapter->q_vector[q_idx]; | |
1887 | if (!q_vector->rxr_count) | |
1888 | continue; | |
1889 | napi_disable(&q_vector->napi); | |
1890 | } | |
1891 | } | |
1892 | ||
7a6b6f51 | 1893 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
1894 | /* |
1895 | * ixgbe_configure_dcb - Configure DCB hardware | |
1896 | * @adapter: ixgbe adapter struct | |
1897 | * | |
1898 | * This is called by the driver on open to configure the DCB hardware. | |
1899 | * This is also called by the gennetlink interface when reconfiguring | |
1900 | * the DCB state. | |
1901 | */ | |
1902 | static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter) | |
1903 | { | |
1904 | struct ixgbe_hw *hw = &adapter->hw; | |
1905 | u32 txdctl, vlnctrl; | |
1906 | int i, j; | |
1907 | ||
1908 | ixgbe_dcb_check_config(&adapter->dcb_cfg); | |
1909 | ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG); | |
1910 | ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG); | |
1911 | ||
1912 | /* reconfigure the hardware */ | |
1913 | ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg); | |
1914 | ||
1915 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
1916 | j = adapter->tx_ring[i].reg_idx; | |
1917 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)); | |
1918 | /* PThresh workaround for Tx hang with DFP enabled. */ | |
1919 | txdctl |= 32; | |
1920 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl); | |
1921 | } | |
1922 | /* Enable VLAN tag insert/strip */ | |
1923 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); | |
1924 | vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE; | |
1925 | vlnctrl &= ~IXGBE_VLNCTRL_CFIEN; | |
1926 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); | |
1927 | hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true); | |
1928 | } | |
1929 | ||
1930 | #endif | |
9a799d71 AK |
1931 | static void ixgbe_configure(struct ixgbe_adapter *adapter) |
1932 | { | |
1933 | struct net_device *netdev = adapter->netdev; | |
1934 | int i; | |
1935 | ||
2c5645cf | 1936 | ixgbe_set_rx_mode(netdev); |
9a799d71 AK |
1937 | |
1938 | ixgbe_restore_vlan(adapter); | |
7a6b6f51 | 1939 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
1940 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { |
1941 | netif_set_gso_max_size(netdev, 32768); | |
1942 | ixgbe_configure_dcb(adapter); | |
1943 | } else { | |
1944 | netif_set_gso_max_size(netdev, 65536); | |
1945 | } | |
1946 | #else | |
1947 | netif_set_gso_max_size(netdev, 65536); | |
1948 | #endif | |
9a799d71 AK |
1949 | |
1950 | ixgbe_configure_tx(adapter); | |
1951 | ixgbe_configure_rx(adapter); | |
1952 | for (i = 0; i < adapter->num_rx_queues; i++) | |
1953 | ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i], | |
b4617240 | 1954 | (adapter->rx_ring[i].count - 1)); |
9a799d71 AK |
1955 | } |
1956 | ||
1957 | static int ixgbe_up_complete(struct ixgbe_adapter *adapter) | |
1958 | { | |
1959 | struct net_device *netdev = adapter->netdev; | |
9a799d71 | 1960 | struct ixgbe_hw *hw = &adapter->hw; |
021230d4 | 1961 | int i, j = 0; |
9a799d71 | 1962 | int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; |
021230d4 AV |
1963 | u32 txdctl, rxdctl, mhadd; |
1964 | u32 gpie; | |
9a799d71 | 1965 | |
5eba3699 AV |
1966 | ixgbe_get_hw_control(adapter); |
1967 | ||
021230d4 AV |
1968 | if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) || |
1969 | (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) { | |
9a799d71 AK |
1970 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
1971 | gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME | | |
b4617240 | 1972 | IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD); |
9a799d71 AK |
1973 | } else { |
1974 | /* MSI only */ | |
021230d4 | 1975 | gpie = 0; |
9a799d71 | 1976 | } |
021230d4 AV |
1977 | /* XXX: to interrupt immediately for EICS writes, enable this */ |
1978 | /* gpie |= IXGBE_GPIE_EIMEN; */ | |
1979 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
9a799d71 AK |
1980 | } |
1981 | ||
021230d4 AV |
1982 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { |
1983 | /* legacy interrupts, use EIAM to auto-mask when reading EICR, | |
1984 | * specifically only auto mask tx and rx interrupts */ | |
1985 | IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); | |
1986 | } | |
9a799d71 | 1987 | |
0befdb3e JB |
1988 | /* Enable fan failure interrupt if media type is copper */ |
1989 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
1990 | gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); | |
1991 | gpie |= IXGBE_SDP1_GPIEN; | |
1992 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
1993 | } | |
1994 | ||
021230d4 | 1995 | mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); |
9a799d71 AK |
1996 | if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) { |
1997 | mhadd &= ~IXGBE_MHADD_MFS_MASK; | |
1998 | mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT; | |
1999 | ||
2000 | IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); | |
2001 | } | |
2002 | ||
2003 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
021230d4 AV |
2004 | j = adapter->tx_ring[i].reg_idx; |
2005 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)); | |
e01c31a5 JB |
2006 | /* enable WTHRESH=8 descriptors, to encourage burst writeback */ |
2007 | txdctl |= (8 << 16); | |
9a799d71 | 2008 | txdctl |= IXGBE_TXDCTL_ENABLE; |
021230d4 | 2009 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl); |
9a799d71 AK |
2010 | } |
2011 | ||
2012 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
021230d4 AV |
2013 | j = adapter->rx_ring[i].reg_idx; |
2014 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); | |
2015 | /* enable PTHRESH=32 descriptors (half the internal cache) | |
2016 | * and HTHRESH=0 descriptors (to minimize latency on fetch), | |
2017 | * this also removes a pesky rx_no_buffer_count increment */ | |
2018 | rxdctl |= 0x0020; | |
9a799d71 | 2019 | rxdctl |= IXGBE_RXDCTL_ENABLE; |
021230d4 | 2020 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl); |
9a799d71 AK |
2021 | } |
2022 | /* enable all receives */ | |
2023 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); | |
2024 | rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN); | |
2025 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxdctl); | |
2026 | ||
2027 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) | |
2028 | ixgbe_configure_msix(adapter); | |
2029 | else | |
2030 | ixgbe_configure_msi_and_legacy(adapter); | |
2031 | ||
7adf1525 PWJ |
2032 | ixgbe_napi_add_all(adapter); |
2033 | ||
9a799d71 | 2034 | clear_bit(__IXGBE_DOWN, &adapter->state); |
021230d4 AV |
2035 | ixgbe_napi_enable_all(adapter); |
2036 | ||
2037 | /* clear any pending interrupts, may auto mask */ | |
2038 | IXGBE_READ_REG(hw, IXGBE_EICR); | |
2039 | ||
9a799d71 AK |
2040 | ixgbe_irq_enable(adapter); |
2041 | ||
1da100bb PWJ |
2042 | /* enable transmits */ |
2043 | netif_tx_start_all_queues(netdev); | |
2044 | ||
9a799d71 AK |
2045 | /* bring the link up in the watchdog, this could race with our first |
2046 | * link up interrupt but shouldn't be a problem */ | |
cf8280ee JB |
2047 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; |
2048 | adapter->link_check_timeout = jiffies; | |
9a799d71 AK |
2049 | mod_timer(&adapter->watchdog_timer, jiffies); |
2050 | return 0; | |
2051 | } | |
2052 | ||
d4f80882 AV |
2053 | void ixgbe_reinit_locked(struct ixgbe_adapter *adapter) |
2054 | { | |
2055 | WARN_ON(in_interrupt()); | |
2056 | while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) | |
2057 | msleep(1); | |
2058 | ixgbe_down(adapter); | |
2059 | ixgbe_up(adapter); | |
2060 | clear_bit(__IXGBE_RESETTING, &adapter->state); | |
2061 | } | |
2062 | ||
9a799d71 AK |
2063 | int ixgbe_up(struct ixgbe_adapter *adapter) |
2064 | { | |
2065 | /* hardware has been reset, we need to reload some things */ | |
2066 | ixgbe_configure(adapter); | |
2067 | ||
2068 | return ixgbe_up_complete(adapter); | |
2069 | } | |
2070 | ||
2071 | void ixgbe_reset(struct ixgbe_adapter *adapter) | |
2072 | { | |
c44ade9e JB |
2073 | struct ixgbe_hw *hw = &adapter->hw; |
2074 | if (hw->mac.ops.init_hw(hw)) | |
2075 | dev_err(&adapter->pdev->dev, "Hardware Error\n"); | |
9a799d71 AK |
2076 | |
2077 | /* reprogram the RAR[0] in case user changed it. */ | |
c44ade9e | 2078 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); |
9a799d71 AK |
2079 | |
2080 | } | |
2081 | ||
9a799d71 AK |
2082 | /** |
2083 | * ixgbe_clean_rx_ring - Free Rx Buffers per Queue | |
2084 | * @adapter: board private structure | |
2085 | * @rx_ring: ring to free buffers from | |
2086 | **/ | |
2087 | static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter, | |
b4617240 | 2088 | struct ixgbe_ring *rx_ring) |
9a799d71 AK |
2089 | { |
2090 | struct pci_dev *pdev = adapter->pdev; | |
2091 | unsigned long size; | |
2092 | unsigned int i; | |
2093 | ||
2094 | /* Free all the Rx ring sk_buffs */ | |
2095 | ||
2096 | for (i = 0; i < rx_ring->count; i++) { | |
2097 | struct ixgbe_rx_buffer *rx_buffer_info; | |
2098 | ||
2099 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; | |
2100 | if (rx_buffer_info->dma) { | |
2101 | pci_unmap_single(pdev, rx_buffer_info->dma, | |
b4617240 PW |
2102 | rx_ring->rx_buf_len, |
2103 | PCI_DMA_FROMDEVICE); | |
9a799d71 AK |
2104 | rx_buffer_info->dma = 0; |
2105 | } | |
2106 | if (rx_buffer_info->skb) { | |
2107 | dev_kfree_skb(rx_buffer_info->skb); | |
2108 | rx_buffer_info->skb = NULL; | |
2109 | } | |
2110 | if (!rx_buffer_info->page) | |
2111 | continue; | |
762f4c57 JB |
2112 | pci_unmap_page(pdev, rx_buffer_info->page_dma, PAGE_SIZE / 2, |
2113 | PCI_DMA_FROMDEVICE); | |
9a799d71 | 2114 | rx_buffer_info->page_dma = 0; |
9a799d71 AK |
2115 | put_page(rx_buffer_info->page); |
2116 | rx_buffer_info->page = NULL; | |
762f4c57 | 2117 | rx_buffer_info->page_offset = 0; |
9a799d71 AK |
2118 | } |
2119 | ||
2120 | size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; | |
2121 | memset(rx_ring->rx_buffer_info, 0, size); | |
2122 | ||
2123 | /* Zero out the descriptor ring */ | |
2124 | memset(rx_ring->desc, 0, rx_ring->size); | |
2125 | ||
2126 | rx_ring->next_to_clean = 0; | |
2127 | rx_ring->next_to_use = 0; | |
2128 | ||
2129 | writel(0, adapter->hw.hw_addr + rx_ring->head); | |
2130 | writel(0, adapter->hw.hw_addr + rx_ring->tail); | |
2131 | } | |
2132 | ||
2133 | /** | |
2134 | * ixgbe_clean_tx_ring - Free Tx Buffers | |
2135 | * @adapter: board private structure | |
2136 | * @tx_ring: ring to be cleaned | |
2137 | **/ | |
2138 | static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter, | |
b4617240 | 2139 | struct ixgbe_ring *tx_ring) |
9a799d71 AK |
2140 | { |
2141 | struct ixgbe_tx_buffer *tx_buffer_info; | |
2142 | unsigned long size; | |
2143 | unsigned int i; | |
2144 | ||
2145 | /* Free all the Tx ring sk_buffs */ | |
2146 | ||
2147 | for (i = 0; i < tx_ring->count; i++) { | |
2148 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
2149 | ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info); | |
2150 | } | |
2151 | ||
2152 | size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; | |
2153 | memset(tx_ring->tx_buffer_info, 0, size); | |
2154 | ||
2155 | /* Zero out the descriptor ring */ | |
2156 | memset(tx_ring->desc, 0, tx_ring->size); | |
2157 | ||
2158 | tx_ring->next_to_use = 0; | |
2159 | tx_ring->next_to_clean = 0; | |
2160 | ||
2161 | writel(0, adapter->hw.hw_addr + tx_ring->head); | |
2162 | writel(0, adapter->hw.hw_addr + tx_ring->tail); | |
2163 | } | |
2164 | ||
2165 | /** | |
021230d4 | 2166 | * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues |
9a799d71 AK |
2167 | * @adapter: board private structure |
2168 | **/ | |
021230d4 | 2169 | static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter) |
9a799d71 AK |
2170 | { |
2171 | int i; | |
2172 | ||
021230d4 AV |
2173 | for (i = 0; i < adapter->num_rx_queues; i++) |
2174 | ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]); | |
9a799d71 AK |
2175 | } |
2176 | ||
2177 | /** | |
021230d4 | 2178 | * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues |
9a799d71 AK |
2179 | * @adapter: board private structure |
2180 | **/ | |
021230d4 | 2181 | static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter) |
9a799d71 AK |
2182 | { |
2183 | int i; | |
2184 | ||
021230d4 AV |
2185 | for (i = 0; i < adapter->num_tx_queues; i++) |
2186 | ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]); | |
9a799d71 AK |
2187 | } |
2188 | ||
2189 | void ixgbe_down(struct ixgbe_adapter *adapter) | |
2190 | { | |
2191 | struct net_device *netdev = adapter->netdev; | |
7f821875 | 2192 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 | 2193 | u32 rxctrl; |
7f821875 JB |
2194 | u32 txdctl; |
2195 | int i, j; | |
9a799d71 AK |
2196 | |
2197 | /* signal that we are down to the interrupt handler */ | |
2198 | set_bit(__IXGBE_DOWN, &adapter->state); | |
2199 | ||
2200 | /* disable receives */ | |
7f821875 JB |
2201 | rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); |
2202 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); | |
9a799d71 AK |
2203 | |
2204 | netif_tx_disable(netdev); | |
2205 | ||
7f821875 | 2206 | IXGBE_WRITE_FLUSH(hw); |
9a799d71 AK |
2207 | msleep(10); |
2208 | ||
7f821875 JB |
2209 | netif_tx_stop_all_queues(netdev); |
2210 | ||
9a799d71 AK |
2211 | ixgbe_irq_disable(adapter); |
2212 | ||
021230d4 | 2213 | ixgbe_napi_disable_all(adapter); |
7f821875 | 2214 | |
9a799d71 | 2215 | del_timer_sync(&adapter->watchdog_timer); |
cf8280ee | 2216 | cancel_work_sync(&adapter->watchdog_task); |
9a799d71 | 2217 | |
7f821875 JB |
2218 | /* disable transmits in the hardware now that interrupts are off */ |
2219 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
2220 | j = adapter->tx_ring[i].reg_idx; | |
2221 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)); | |
2222 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), | |
2223 | (txdctl & ~IXGBE_TXDCTL_ENABLE)); | |
2224 | } | |
2225 | ||
9a799d71 | 2226 | netif_carrier_off(netdev); |
9a799d71 | 2227 | |
5dd2d332 | 2228 | #ifdef CONFIG_IXGBE_DCA |
96b0e0f6 JB |
2229 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { |
2230 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
2231 | dca_remove_requester(&adapter->pdev->dev); | |
2232 | } | |
2233 | ||
2234 | #endif | |
6f4a0e45 PL |
2235 | if (!pci_channel_offline(adapter->pdev)) |
2236 | ixgbe_reset(adapter); | |
9a799d71 AK |
2237 | ixgbe_clean_all_tx_rings(adapter); |
2238 | ixgbe_clean_all_rx_rings(adapter); | |
2239 | ||
5dd2d332 | 2240 | #ifdef CONFIG_IXGBE_DCA |
96b0e0f6 JB |
2241 | /* since we reset the hardware DCA settings were cleared */ |
2242 | if (dca_add_requester(&adapter->pdev->dev) == 0) { | |
2243 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; | |
2244 | /* always use CB2 mode, difference is masked | |
2245 | * in the CB driver */ | |
b4617240 | 2246 | IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2); |
96b0e0f6 JB |
2247 | ixgbe_setup_dca(adapter); |
2248 | } | |
2249 | #endif | |
9a799d71 AK |
2250 | } |
2251 | ||
9a799d71 | 2252 | /** |
021230d4 AV |
2253 | * ixgbe_poll - NAPI Rx polling callback |
2254 | * @napi: structure for representing this polling device | |
2255 | * @budget: how many packets driver is allowed to clean | |
2256 | * | |
2257 | * This function is used for legacy and MSI, NAPI mode | |
9a799d71 | 2258 | **/ |
021230d4 | 2259 | static int ixgbe_poll(struct napi_struct *napi, int budget) |
9a799d71 | 2260 | { |
021230d4 | 2261 | struct ixgbe_q_vector *q_vector = container_of(napi, |
b4617240 | 2262 | struct ixgbe_q_vector, napi); |
021230d4 | 2263 | struct ixgbe_adapter *adapter = q_vector->adapter; |
74ce8dd2 | 2264 | int tx_cleaned, work_done = 0; |
9a799d71 | 2265 | |
5dd2d332 | 2266 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
2267 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { |
2268 | ixgbe_update_tx_dca(adapter, adapter->tx_ring); | |
2269 | ixgbe_update_rx_dca(adapter, adapter->rx_ring); | |
2270 | } | |
2271 | #endif | |
2272 | ||
d2c7ddd6 | 2273 | tx_cleaned = ixgbe_clean_tx_irq(adapter, adapter->tx_ring); |
78b6f4ce | 2274 | ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget); |
9a799d71 | 2275 | |
d2c7ddd6 DM |
2276 | if (tx_cleaned) |
2277 | work_done = budget; | |
2278 | ||
53e52c72 DM |
2279 | /* If budget not fully consumed, exit the polling mode */ |
2280 | if (work_done < budget) { | |
288379f0 | 2281 | napi_complete(napi); |
30efa5a3 | 2282 | if (adapter->itr_setting & 3) |
f494e8fa | 2283 | ixgbe_set_itr(adapter); |
d4f80882 AV |
2284 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
2285 | ixgbe_irq_enable(adapter); | |
9a799d71 | 2286 | } |
9a799d71 AK |
2287 | return work_done; |
2288 | } | |
2289 | ||
2290 | /** | |
2291 | * ixgbe_tx_timeout - Respond to a Tx Hang | |
2292 | * @netdev: network interface device structure | |
2293 | **/ | |
2294 | static void ixgbe_tx_timeout(struct net_device *netdev) | |
2295 | { | |
2296 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
2297 | ||
2298 | /* Do the reset outside of interrupt context */ | |
2299 | schedule_work(&adapter->reset_task); | |
2300 | } | |
2301 | ||
2302 | static void ixgbe_reset_task(struct work_struct *work) | |
2303 | { | |
2304 | struct ixgbe_adapter *adapter; | |
2305 | adapter = container_of(work, struct ixgbe_adapter, reset_task); | |
2306 | ||
2f90b865 AD |
2307 | /* If we're already down or resetting, just bail */ |
2308 | if (test_bit(__IXGBE_DOWN, &adapter->state) || | |
2309 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
2310 | return; | |
2311 | ||
9a799d71 AK |
2312 | adapter->tx_timeout_count++; |
2313 | ||
d4f80882 | 2314 | ixgbe_reinit_locked(adapter); |
9a799d71 AK |
2315 | } |
2316 | ||
bc97114d PWJ |
2317 | #ifdef CONFIG_IXGBE_DCB |
2318 | static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter) | |
b9804972 | 2319 | { |
bc97114d | 2320 | bool ret = false; |
b9804972 | 2321 | |
bc97114d PWJ |
2322 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { |
2323 | adapter->ring_feature[RING_F_DCB].mask = 0x7 << 3; | |
2324 | adapter->num_rx_queues = | |
2325 | adapter->ring_feature[RING_F_DCB].indices; | |
2326 | adapter->num_tx_queues = | |
2327 | adapter->ring_feature[RING_F_DCB].indices; | |
2328 | ret = true; | |
2329 | } else { | |
2330 | adapter->ring_feature[RING_F_DCB].mask = 0; | |
2331 | adapter->ring_feature[RING_F_DCB].indices = 0; | |
2332 | ret = false; | |
2333 | } | |
2f90b865 | 2334 | |
bc97114d PWJ |
2335 | return ret; |
2336 | } | |
2337 | #endif | |
2338 | ||
2339 | static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter) | |
2340 | { | |
2341 | bool ret = false; | |
2342 | ||
2343 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { | |
2344 | adapter->ring_feature[RING_F_RSS].mask = 0xF; | |
2345 | adapter->num_rx_queues = | |
2346 | adapter->ring_feature[RING_F_RSS].indices; | |
2347 | adapter->num_tx_queues = | |
2348 | adapter->ring_feature[RING_F_RSS].indices; | |
2349 | ret = true; | |
2350 | } else { | |
2351 | adapter->ring_feature[RING_F_RSS].mask = 0; | |
2352 | adapter->ring_feature[RING_F_RSS].indices = 0; | |
2353 | ret = false; | |
b9804972 JB |
2354 | } |
2355 | ||
bc97114d PWJ |
2356 | return ret; |
2357 | } | |
2358 | ||
2359 | static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter) | |
2360 | { | |
2361 | /* Start with base case */ | |
2362 | adapter->num_rx_queues = 1; | |
2363 | adapter->num_tx_queues = 1; | |
2364 | ||
2365 | #ifdef CONFIG_IXGBE_DCB | |
2366 | if (ixgbe_set_dcb_queues(adapter)) | |
2367 | return; | |
2368 | ||
2369 | #endif | |
2370 | if (ixgbe_set_rss_queues(adapter)) | |
2371 | return; | |
b9804972 JB |
2372 | } |
2373 | ||
021230d4 | 2374 | static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter, |
b4617240 | 2375 | int vectors) |
021230d4 AV |
2376 | { |
2377 | int err, vector_threshold; | |
2378 | ||
2379 | /* We'll want at least 3 (vector_threshold): | |
2380 | * 1) TxQ[0] Cleanup | |
2381 | * 2) RxQ[0] Cleanup | |
2382 | * 3) Other (Link Status Change, etc.) | |
2383 | * 4) TCP Timer (optional) | |
2384 | */ | |
2385 | vector_threshold = MIN_MSIX_COUNT; | |
2386 | ||
2387 | /* The more we get, the more we will assign to Tx/Rx Cleanup | |
2388 | * for the separate queues...where Rx Cleanup >= Tx Cleanup. | |
2389 | * Right now, we simply care about how many we'll get; we'll | |
2390 | * set them up later while requesting irq's. | |
2391 | */ | |
2392 | while (vectors >= vector_threshold) { | |
2393 | err = pci_enable_msix(adapter->pdev, adapter->msix_entries, | |
b4617240 | 2394 | vectors); |
021230d4 AV |
2395 | if (!err) /* Success in acquiring all requested vectors. */ |
2396 | break; | |
2397 | else if (err < 0) | |
2398 | vectors = 0; /* Nasty failure, quit now */ | |
2399 | else /* err == number of vectors we should try again with */ | |
2400 | vectors = err; | |
2401 | } | |
2402 | ||
2403 | if (vectors < vector_threshold) { | |
2404 | /* Can't allocate enough MSI-X interrupts? Oh well. | |
2405 | * This just means we'll go with either a single MSI | |
2406 | * vector or fall back to legacy interrupts. | |
2407 | */ | |
2408 | DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n"); | |
2409 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; | |
2410 | kfree(adapter->msix_entries); | |
2411 | adapter->msix_entries = NULL; | |
2f90b865 | 2412 | adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; |
021230d4 | 2413 | adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED; |
b9804972 | 2414 | ixgbe_set_num_queues(adapter); |
021230d4 AV |
2415 | } else { |
2416 | adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */ | |
eb7f139c PWJ |
2417 | /* |
2418 | * Adjust for only the vectors we'll use, which is minimum | |
2419 | * of max_msix_q_vectors + NON_Q_VECTORS, or the number of | |
2420 | * vectors we were allocated. | |
2421 | */ | |
2422 | adapter->num_msix_vectors = min(vectors, | |
2423 | adapter->max_msix_q_vectors + NON_Q_VECTORS); | |
021230d4 AV |
2424 | } |
2425 | } | |
2426 | ||
021230d4 | 2427 | /** |
bc97114d | 2428 | * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS |
021230d4 AV |
2429 | * @adapter: board private structure to initialize |
2430 | * | |
bc97114d PWJ |
2431 | * Cache the descriptor ring offsets for RSS to the assigned rings. |
2432 | * | |
021230d4 | 2433 | **/ |
bc97114d | 2434 | static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter) |
021230d4 | 2435 | { |
bc97114d PWJ |
2436 | int i; |
2437 | bool ret = false; | |
2438 | ||
2439 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { | |
2440 | for (i = 0; i < adapter->num_rx_queues; i++) | |
2441 | adapter->rx_ring[i].reg_idx = i; | |
2442 | for (i = 0; i < adapter->num_tx_queues; i++) | |
2443 | adapter->tx_ring[i].reg_idx = i; | |
2444 | ret = true; | |
2445 | } else { | |
2446 | ret = false; | |
2447 | } | |
2448 | ||
2449 | return ret; | |
2450 | } | |
2451 | ||
2452 | #ifdef CONFIG_IXGBE_DCB | |
2453 | /** | |
2454 | * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB | |
2455 | * @adapter: board private structure to initialize | |
2456 | * | |
2457 | * Cache the descriptor ring offsets for DCB to the assigned rings. | |
2458 | * | |
2459 | **/ | |
2460 | static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter) | |
2461 | { | |
2462 | int i; | |
2463 | bool ret = false; | |
2464 | int dcb_i = adapter->ring_feature[RING_F_DCB].indices; | |
2465 | ||
2466 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
2467 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { | |
2f90b865 AD |
2468 | /* the number of queues is assumed to be symmetric */ |
2469 | for (i = 0; i < dcb_i; i++) { | |
2470 | adapter->rx_ring[i].reg_idx = i << 3; | |
2471 | adapter->tx_ring[i].reg_idx = i << 2; | |
2472 | } | |
bc97114d PWJ |
2473 | ret = true; |
2474 | } else { | |
2475 | ret = false; | |
021230d4 | 2476 | } |
bc97114d PWJ |
2477 | } else { |
2478 | ret = false; | |
021230d4 | 2479 | } |
bc97114d PWJ |
2480 | |
2481 | return ret; | |
2482 | } | |
2483 | #endif | |
2484 | ||
2485 | /** | |
2486 | * ixgbe_cache_ring_register - Descriptor ring to register mapping | |
2487 | * @adapter: board private structure to initialize | |
2488 | * | |
2489 | * Once we know the feature-set enabled for the device, we'll cache | |
2490 | * the register offset the descriptor ring is assigned to. | |
2491 | * | |
2492 | * Note, the order the various feature calls is important. It must start with | |
2493 | * the "most" features enabled at the same time, then trickle down to the | |
2494 | * least amount of features turned on at once. | |
2495 | **/ | |
2496 | static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter) | |
2497 | { | |
2498 | /* start with default case */ | |
2499 | adapter->rx_ring[0].reg_idx = 0; | |
2500 | adapter->tx_ring[0].reg_idx = 0; | |
2501 | ||
2502 | #ifdef CONFIG_IXGBE_DCB | |
2503 | if (ixgbe_cache_ring_dcb(adapter)) | |
2504 | return; | |
2505 | ||
2506 | #endif | |
2507 | if (ixgbe_cache_ring_rss(adapter)) | |
2508 | return; | |
021230d4 AV |
2509 | } |
2510 | ||
9a799d71 AK |
2511 | /** |
2512 | * ixgbe_alloc_queues - Allocate memory for all rings | |
2513 | * @adapter: board private structure to initialize | |
2514 | * | |
2515 | * We allocate one ring per queue at run-time since we don't know the | |
a4d2f34b | 2516 | * number of queues at compile-time. |
9a799d71 | 2517 | **/ |
2f90b865 | 2518 | static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter) |
9a799d71 AK |
2519 | { |
2520 | int i; | |
2521 | ||
2522 | adapter->tx_ring = kcalloc(adapter->num_tx_queues, | |
b4617240 | 2523 | sizeof(struct ixgbe_ring), GFP_KERNEL); |
9a799d71 | 2524 | if (!adapter->tx_ring) |
021230d4 | 2525 | goto err_tx_ring_allocation; |
9a799d71 AK |
2526 | |
2527 | adapter->rx_ring = kcalloc(adapter->num_rx_queues, | |
b4617240 | 2528 | sizeof(struct ixgbe_ring), GFP_KERNEL); |
021230d4 AV |
2529 | if (!adapter->rx_ring) |
2530 | goto err_rx_ring_allocation; | |
9a799d71 | 2531 | |
021230d4 | 2532 | for (i = 0; i < adapter->num_tx_queues; i++) { |
b9804972 | 2533 | adapter->tx_ring[i].count = adapter->tx_ring_count; |
021230d4 AV |
2534 | adapter->tx_ring[i].queue_index = i; |
2535 | } | |
b9804972 | 2536 | |
9a799d71 | 2537 | for (i = 0; i < adapter->num_rx_queues; i++) { |
b9804972 | 2538 | adapter->rx_ring[i].count = adapter->rx_ring_count; |
021230d4 AV |
2539 | adapter->rx_ring[i].queue_index = i; |
2540 | } | |
2541 | ||
2542 | ixgbe_cache_ring_register(adapter); | |
2543 | ||
2544 | return 0; | |
2545 | ||
2546 | err_rx_ring_allocation: | |
2547 | kfree(adapter->tx_ring); | |
2548 | err_tx_ring_allocation: | |
2549 | return -ENOMEM; | |
2550 | } | |
2551 | ||
2552 | /** | |
2553 | * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported | |
2554 | * @adapter: board private structure to initialize | |
2555 | * | |
2556 | * Attempt to configure the interrupts using the best available | |
2557 | * capabilities of the hardware and the kernel. | |
2558 | **/ | |
feea6a57 | 2559 | static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter) |
021230d4 AV |
2560 | { |
2561 | int err = 0; | |
2562 | int vector, v_budget; | |
2563 | ||
2564 | /* | |
2565 | * It's easy to be greedy for MSI-X vectors, but it really | |
2566 | * doesn't do us much good if we have a lot more vectors | |
2567 | * than CPU's. So let's be conservative and only ask for | |
2568 | * (roughly) twice the number of vectors as there are CPU's. | |
2569 | */ | |
2570 | v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues, | |
b4617240 | 2571 | (int)(num_online_cpus() * 2)) + NON_Q_VECTORS; |
021230d4 AV |
2572 | |
2573 | /* | |
2574 | * At the same time, hardware can only support a maximum of | |
2575 | * MAX_MSIX_COUNT vectors. With features such as RSS and VMDq, | |
2576 | * we can easily reach upwards of 64 Rx descriptor queues and | |
2577 | * 32 Tx queues. Thus, we cap it off in those rare cases where | |
2578 | * the cpu count also exceeds our vector limit. | |
2579 | */ | |
2580 | v_budget = min(v_budget, MAX_MSIX_COUNT); | |
2581 | ||
2582 | /* A failure in MSI-X entry allocation isn't fatal, but it does | |
2583 | * mean we disable MSI-X capabilities of the adapter. */ | |
2584 | adapter->msix_entries = kcalloc(v_budget, | |
b4617240 | 2585 | sizeof(struct msix_entry), GFP_KERNEL); |
021230d4 | 2586 | if (!adapter->msix_entries) { |
2f90b865 | 2587 | adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; |
021230d4 AV |
2588 | adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED; |
2589 | ixgbe_set_num_queues(adapter); | |
2590 | kfree(adapter->tx_ring); | |
2591 | kfree(adapter->rx_ring); | |
2592 | err = ixgbe_alloc_queues(adapter); | |
2593 | if (err) { | |
2594 | DPRINTK(PROBE, ERR, "Unable to allocate memory " | |
b4617240 | 2595 | "for queues\n"); |
021230d4 AV |
2596 | goto out; |
2597 | } | |
2598 | ||
2599 | goto try_msi; | |
2600 | } | |
2601 | ||
2602 | for (vector = 0; vector < v_budget; vector++) | |
2603 | adapter->msix_entries[vector].entry = vector; | |
2604 | ||
2605 | ixgbe_acquire_msix_vectors(adapter, v_budget); | |
2606 | ||
2607 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) | |
2608 | goto out; | |
2609 | ||
2610 | try_msi: | |
2611 | err = pci_enable_msi(adapter->pdev); | |
2612 | if (!err) { | |
2613 | adapter->flags |= IXGBE_FLAG_MSI_ENABLED; | |
2614 | } else { | |
2615 | DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, " | |
b4617240 | 2616 | "falling back to legacy. Error: %d\n", err); |
021230d4 AV |
2617 | /* reset err */ |
2618 | err = 0; | |
2619 | } | |
2620 | ||
2621 | out: | |
30eba97a | 2622 | /* Notify the stack of the (possibly) reduced Tx Queue count. */ |
fd2ea0a7 | 2623 | adapter->netdev->real_num_tx_queues = adapter->num_tx_queues; |
021230d4 AV |
2624 | |
2625 | return err; | |
2626 | } | |
2627 | ||
2f90b865 | 2628 | void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter) |
021230d4 AV |
2629 | { |
2630 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
2631 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; | |
2632 | pci_disable_msix(adapter->pdev); | |
2633 | kfree(adapter->msix_entries); | |
2634 | adapter->msix_entries = NULL; | |
2635 | } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) { | |
2636 | adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED; | |
2637 | pci_disable_msi(adapter->pdev); | |
2638 | } | |
2639 | return; | |
2640 | } | |
2641 | ||
2642 | /** | |
2643 | * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme | |
2644 | * @adapter: board private structure to initialize | |
2645 | * | |
2646 | * We determine which interrupt scheme to use based on... | |
2647 | * - Kernel support (MSI, MSI-X) | |
2648 | * - which can be user-defined (via MODULE_PARAM) | |
2649 | * - Hardware queue count (num_*_queues) | |
2650 | * - defined by miscellaneous hardware support/features (RSS, etc.) | |
2651 | **/ | |
2f90b865 | 2652 | int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter) |
021230d4 AV |
2653 | { |
2654 | int err; | |
2655 | ||
2656 | /* Number of supported queues */ | |
2657 | ixgbe_set_num_queues(adapter); | |
2658 | ||
2659 | err = ixgbe_alloc_queues(adapter); | |
2660 | if (err) { | |
2661 | DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n"); | |
2662 | goto err_alloc_queues; | |
2663 | } | |
2664 | ||
2665 | err = ixgbe_set_interrupt_capability(adapter); | |
2666 | if (err) { | |
2667 | DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n"); | |
2668 | goto err_set_interrupt; | |
9a799d71 AK |
2669 | } |
2670 | ||
021230d4 | 2671 | DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, " |
b4617240 PW |
2672 | "Tx Queue count = %u\n", |
2673 | (adapter->num_rx_queues > 1) ? "Enabled" : | |
2674 | "Disabled", adapter->num_rx_queues, adapter->num_tx_queues); | |
021230d4 AV |
2675 | |
2676 | set_bit(__IXGBE_DOWN, &adapter->state); | |
2677 | ||
9a799d71 | 2678 | return 0; |
021230d4 AV |
2679 | |
2680 | err_set_interrupt: | |
2681 | kfree(adapter->tx_ring); | |
2682 | kfree(adapter->rx_ring); | |
2683 | err_alloc_queues: | |
2684 | return err; | |
9a799d71 AK |
2685 | } |
2686 | ||
c4900be0 DS |
2687 | /** |
2688 | * ixgbe_sfp_timer - worker thread to find a missing module | |
2689 | * @data: pointer to our adapter struct | |
2690 | **/ | |
2691 | static void ixgbe_sfp_timer(unsigned long data) | |
2692 | { | |
2693 | struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data; | |
2694 | ||
2695 | /* Do the sfp_timer outside of interrupt context due to the | |
2696 | * delays that sfp+ detection requires | |
2697 | */ | |
2698 | schedule_work(&adapter->sfp_task); | |
2699 | } | |
2700 | ||
2701 | /** | |
2702 | * ixgbe_sfp_task - worker thread to find a missing module | |
2703 | * @work: pointer to work_struct containing our data | |
2704 | **/ | |
2705 | static void ixgbe_sfp_task(struct work_struct *work) | |
2706 | { | |
2707 | struct ixgbe_adapter *adapter = container_of(work, | |
2708 | struct ixgbe_adapter, | |
2709 | sfp_task); | |
2710 | struct ixgbe_hw *hw = &adapter->hw; | |
2711 | ||
2712 | if ((hw->phy.type == ixgbe_phy_nl) && | |
2713 | (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) { | |
2714 | s32 ret = hw->phy.ops.identify_sfp(hw); | |
2715 | if (ret) | |
2716 | goto reschedule; | |
2717 | ret = hw->phy.ops.reset(hw); | |
2718 | if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
2719 | DPRINTK(PROBE, ERR, "failed to initialize because an " | |
2720 | "unsupported SFP+ module type was detected.\n" | |
2721 | "Reload the driver after installing a " | |
2722 | "supported module.\n"); | |
2723 | unregister_netdev(adapter->netdev); | |
2724 | } else { | |
2725 | DPRINTK(PROBE, INFO, "detected SFP+: %d\n", | |
2726 | hw->phy.sfp_type); | |
2727 | } | |
2728 | /* don't need this routine any more */ | |
2729 | clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); | |
2730 | } | |
2731 | return; | |
2732 | reschedule: | |
2733 | if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state)) | |
2734 | mod_timer(&adapter->sfp_timer, | |
2735 | round_jiffies(jiffies + (2 * HZ))); | |
2736 | } | |
2737 | ||
9a799d71 AK |
2738 | /** |
2739 | * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter) | |
2740 | * @adapter: board private structure to initialize | |
2741 | * | |
2742 | * ixgbe_sw_init initializes the Adapter private data structure. | |
2743 | * Fields are initialized based on PCI device information and | |
2744 | * OS network device settings (MTU size). | |
2745 | **/ | |
2746 | static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter) | |
2747 | { | |
2748 | struct ixgbe_hw *hw = &adapter->hw; | |
2749 | struct pci_dev *pdev = adapter->pdev; | |
021230d4 | 2750 | unsigned int rss; |
7a6b6f51 | 2751 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
2752 | int j; |
2753 | struct tc_configuration *tc; | |
2754 | #endif | |
021230d4 | 2755 | |
c44ade9e JB |
2756 | /* PCI config space info */ |
2757 | ||
2758 | hw->vendor_id = pdev->vendor; | |
2759 | hw->device_id = pdev->device; | |
2760 | hw->revision_id = pdev->revision; | |
2761 | hw->subsystem_vendor_id = pdev->subsystem_vendor; | |
2762 | hw->subsystem_device_id = pdev->subsystem_device; | |
2763 | ||
021230d4 AV |
2764 | /* Set capability flags */ |
2765 | rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus()); | |
2766 | adapter->ring_feature[RING_F_RSS].indices = rss; | |
2767 | adapter->flags |= IXGBE_FLAG_RSS_ENABLED; | |
2f90b865 | 2768 | adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES; |
eb7f139c | 2769 | adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598; |
2f90b865 | 2770 | |
7a6b6f51 | 2771 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
2772 | /* Configure DCB traffic classes */ |
2773 | for (j = 0; j < MAX_TRAFFIC_CLASS; j++) { | |
2774 | tc = &adapter->dcb_cfg.tc_config[j]; | |
2775 | tc->path[DCB_TX_CONFIG].bwg_id = 0; | |
2776 | tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1); | |
2777 | tc->path[DCB_RX_CONFIG].bwg_id = 0; | |
2778 | tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1); | |
2779 | tc->dcb_pfc = pfc_disabled; | |
2780 | } | |
2781 | adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100; | |
2782 | adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100; | |
2783 | adapter->dcb_cfg.rx_pba_cfg = pba_equal; | |
2784 | adapter->dcb_cfg.round_robin_enable = false; | |
2785 | adapter->dcb_set_bitmap = 0x00; | |
2786 | ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg, | |
2787 | adapter->ring_feature[RING_F_DCB].indices); | |
2788 | ||
2789 | #endif | |
0befdb3e JB |
2790 | if (hw->mac.ops.get_media_type && |
2791 | (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) | |
2792 | adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE; | |
9a799d71 AK |
2793 | |
2794 | /* default flow control settings */ | |
2b9ade93 JB |
2795 | hw->fc.original_type = ixgbe_fc_none; |
2796 | hw->fc.type = ixgbe_fc_none; | |
2797 | hw->fc.high_water = IXGBE_DEFAULT_FCRTH; | |
2798 | hw->fc.low_water = IXGBE_DEFAULT_FCRTL; | |
2799 | hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE; | |
2800 | hw->fc.send_xon = true; | |
9a799d71 | 2801 | |
30efa5a3 JB |
2802 | /* enable itr by default in dynamic mode */ |
2803 | adapter->itr_setting = 1; | |
2804 | adapter->eitr_param = 20000; | |
2805 | ||
2806 | /* set defaults for eitr in MegaBytes */ | |
2807 | adapter->eitr_low = 10; | |
2808 | adapter->eitr_high = 20; | |
2809 | ||
2810 | /* set default ring sizes */ | |
2811 | adapter->tx_ring_count = IXGBE_DEFAULT_TXD; | |
2812 | adapter->rx_ring_count = IXGBE_DEFAULT_RXD; | |
2813 | ||
9a799d71 | 2814 | /* initialize eeprom parameters */ |
c44ade9e | 2815 | if (ixgbe_init_eeprom_params_generic(hw)) { |
9a799d71 AK |
2816 | dev_err(&pdev->dev, "EEPROM initialization failed\n"); |
2817 | return -EIO; | |
2818 | } | |
2819 | ||
021230d4 | 2820 | /* enable rx csum by default */ |
9a799d71 AK |
2821 | adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED; |
2822 | ||
9a799d71 AK |
2823 | set_bit(__IXGBE_DOWN, &adapter->state); |
2824 | ||
2825 | return 0; | |
2826 | } | |
2827 | ||
2828 | /** | |
2829 | * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors) | |
2830 | * @adapter: board private structure | |
3a581073 | 2831 | * @tx_ring: tx descriptor ring (for a specific queue) to setup |
9a799d71 AK |
2832 | * |
2833 | * Return 0 on success, negative on failure | |
2834 | **/ | |
2835 | int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter, | |
e01c31a5 | 2836 | struct ixgbe_ring *tx_ring) |
9a799d71 AK |
2837 | { |
2838 | struct pci_dev *pdev = adapter->pdev; | |
2839 | int size; | |
2840 | ||
3a581073 JB |
2841 | size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; |
2842 | tx_ring->tx_buffer_info = vmalloc(size); | |
e01c31a5 JB |
2843 | if (!tx_ring->tx_buffer_info) |
2844 | goto err; | |
3a581073 | 2845 | memset(tx_ring->tx_buffer_info, 0, size); |
9a799d71 AK |
2846 | |
2847 | /* round up to nearest 4K */ | |
e01c31a5 JB |
2848 | tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc) + |
2849 | sizeof(u32); | |
3a581073 | 2850 | tx_ring->size = ALIGN(tx_ring->size, 4096); |
9a799d71 | 2851 | |
3a581073 JB |
2852 | tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size, |
2853 | &tx_ring->dma); | |
e01c31a5 JB |
2854 | if (!tx_ring->desc) |
2855 | goto err; | |
9a799d71 | 2856 | |
3a581073 JB |
2857 | tx_ring->next_to_use = 0; |
2858 | tx_ring->next_to_clean = 0; | |
2859 | tx_ring->work_limit = tx_ring->count; | |
9a799d71 | 2860 | return 0; |
e01c31a5 JB |
2861 | |
2862 | err: | |
2863 | vfree(tx_ring->tx_buffer_info); | |
2864 | tx_ring->tx_buffer_info = NULL; | |
2865 | DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit " | |
2866 | "descriptor ring\n"); | |
2867 | return -ENOMEM; | |
9a799d71 AK |
2868 | } |
2869 | ||
69888674 AD |
2870 | /** |
2871 | * ixgbe_setup_all_tx_resources - allocate all queues Tx resources | |
2872 | * @adapter: board private structure | |
2873 | * | |
2874 | * If this function returns with an error, then it's possible one or | |
2875 | * more of the rings is populated (while the rest are not). It is the | |
2876 | * callers duty to clean those orphaned rings. | |
2877 | * | |
2878 | * Return 0 on success, negative on failure | |
2879 | **/ | |
2880 | static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter) | |
2881 | { | |
2882 | int i, err = 0; | |
2883 | ||
2884 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
2885 | err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]); | |
2886 | if (!err) | |
2887 | continue; | |
2888 | DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i); | |
2889 | break; | |
2890 | } | |
2891 | ||
2892 | return err; | |
2893 | } | |
2894 | ||
9a799d71 AK |
2895 | /** |
2896 | * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors) | |
2897 | * @adapter: board private structure | |
3a581073 | 2898 | * @rx_ring: rx descriptor ring (for a specific queue) to setup |
9a799d71 AK |
2899 | * |
2900 | * Returns 0 on success, negative on failure | |
2901 | **/ | |
2902 | int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter, | |
b4617240 | 2903 | struct ixgbe_ring *rx_ring) |
9a799d71 AK |
2904 | { |
2905 | struct pci_dev *pdev = adapter->pdev; | |
021230d4 | 2906 | int size; |
9a799d71 | 2907 | |
3a581073 JB |
2908 | size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; |
2909 | rx_ring->rx_buffer_info = vmalloc(size); | |
2910 | if (!rx_ring->rx_buffer_info) { | |
9a799d71 | 2911 | DPRINTK(PROBE, ERR, |
b4617240 | 2912 | "vmalloc allocation failed for the rx desc ring\n"); |
177db6ff | 2913 | goto alloc_failed; |
9a799d71 | 2914 | } |
3a581073 | 2915 | memset(rx_ring->rx_buffer_info, 0, size); |
9a799d71 | 2916 | |
9a799d71 | 2917 | /* Round up to nearest 4K */ |
3a581073 JB |
2918 | rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); |
2919 | rx_ring->size = ALIGN(rx_ring->size, 4096); | |
9a799d71 | 2920 | |
3a581073 | 2921 | rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma); |
9a799d71 | 2922 | |
3a581073 | 2923 | if (!rx_ring->desc) { |
9a799d71 | 2924 | DPRINTK(PROBE, ERR, |
b4617240 | 2925 | "Memory allocation failed for the rx desc ring\n"); |
3a581073 | 2926 | vfree(rx_ring->rx_buffer_info); |
177db6ff | 2927 | goto alloc_failed; |
9a799d71 AK |
2928 | } |
2929 | ||
3a581073 JB |
2930 | rx_ring->next_to_clean = 0; |
2931 | rx_ring->next_to_use = 0; | |
9a799d71 AK |
2932 | |
2933 | return 0; | |
177db6ff MC |
2934 | |
2935 | alloc_failed: | |
177db6ff | 2936 | return -ENOMEM; |
9a799d71 AK |
2937 | } |
2938 | ||
69888674 AD |
2939 | /** |
2940 | * ixgbe_setup_all_rx_resources - allocate all queues Rx resources | |
2941 | * @adapter: board private structure | |
2942 | * | |
2943 | * If this function returns with an error, then it's possible one or | |
2944 | * more of the rings is populated (while the rest are not). It is the | |
2945 | * callers duty to clean those orphaned rings. | |
2946 | * | |
2947 | * Return 0 on success, negative on failure | |
2948 | **/ | |
2949 | ||
2950 | static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter) | |
2951 | { | |
2952 | int i, err = 0; | |
2953 | ||
2954 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
2955 | err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]); | |
2956 | if (!err) | |
2957 | continue; | |
2958 | DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i); | |
2959 | break; | |
2960 | } | |
2961 | ||
2962 | return err; | |
2963 | } | |
2964 | ||
9a799d71 AK |
2965 | /** |
2966 | * ixgbe_free_tx_resources - Free Tx Resources per Queue | |
2967 | * @adapter: board private structure | |
2968 | * @tx_ring: Tx descriptor ring for a specific queue | |
2969 | * | |
2970 | * Free all transmit software resources | |
2971 | **/ | |
c431f97e JB |
2972 | void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter, |
2973 | struct ixgbe_ring *tx_ring) | |
9a799d71 AK |
2974 | { |
2975 | struct pci_dev *pdev = adapter->pdev; | |
2976 | ||
2977 | ixgbe_clean_tx_ring(adapter, tx_ring); | |
2978 | ||
2979 | vfree(tx_ring->tx_buffer_info); | |
2980 | tx_ring->tx_buffer_info = NULL; | |
2981 | ||
2982 | pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma); | |
2983 | ||
2984 | tx_ring->desc = NULL; | |
2985 | } | |
2986 | ||
2987 | /** | |
2988 | * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues | |
2989 | * @adapter: board private structure | |
2990 | * | |
2991 | * Free all transmit software resources | |
2992 | **/ | |
2993 | static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter) | |
2994 | { | |
2995 | int i; | |
2996 | ||
2997 | for (i = 0; i < adapter->num_tx_queues; i++) | |
2998 | ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]); | |
2999 | } | |
3000 | ||
3001 | /** | |
b4617240 | 3002 | * ixgbe_free_rx_resources - Free Rx Resources |
9a799d71 AK |
3003 | * @adapter: board private structure |
3004 | * @rx_ring: ring to clean the resources from | |
3005 | * | |
3006 | * Free all receive software resources | |
3007 | **/ | |
c431f97e JB |
3008 | void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter, |
3009 | struct ixgbe_ring *rx_ring) | |
9a799d71 AK |
3010 | { |
3011 | struct pci_dev *pdev = adapter->pdev; | |
3012 | ||
3013 | ixgbe_clean_rx_ring(adapter, rx_ring); | |
3014 | ||
3015 | vfree(rx_ring->rx_buffer_info); | |
3016 | rx_ring->rx_buffer_info = NULL; | |
3017 | ||
3018 | pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma); | |
3019 | ||
3020 | rx_ring->desc = NULL; | |
3021 | } | |
3022 | ||
3023 | /** | |
3024 | * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues | |
3025 | * @adapter: board private structure | |
3026 | * | |
3027 | * Free all receive software resources | |
3028 | **/ | |
3029 | static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter) | |
3030 | { | |
3031 | int i; | |
3032 | ||
3033 | for (i = 0; i < adapter->num_rx_queues; i++) | |
3034 | ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]); | |
3035 | } | |
3036 | ||
9a799d71 AK |
3037 | /** |
3038 | * ixgbe_change_mtu - Change the Maximum Transfer Unit | |
3039 | * @netdev: network interface device structure | |
3040 | * @new_mtu: new value for maximum frame size | |
3041 | * | |
3042 | * Returns 0 on success, negative on failure | |
3043 | **/ | |
3044 | static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu) | |
3045 | { | |
3046 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3047 | int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; | |
3048 | ||
42c783c5 JB |
3049 | /* MTU < 68 is an error and causes problems on some kernels */ |
3050 | if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE)) | |
9a799d71 AK |
3051 | return -EINVAL; |
3052 | ||
021230d4 | 3053 | DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n", |
b4617240 | 3054 | netdev->mtu, new_mtu); |
021230d4 | 3055 | /* must set new MTU before calling down or up */ |
9a799d71 AK |
3056 | netdev->mtu = new_mtu; |
3057 | ||
d4f80882 AV |
3058 | if (netif_running(netdev)) |
3059 | ixgbe_reinit_locked(adapter); | |
9a799d71 AK |
3060 | |
3061 | return 0; | |
3062 | } | |
3063 | ||
3064 | /** | |
3065 | * ixgbe_open - Called when a network interface is made active | |
3066 | * @netdev: network interface device structure | |
3067 | * | |
3068 | * Returns 0 on success, negative value on failure | |
3069 | * | |
3070 | * The open entry point is called when a network interface is made | |
3071 | * active by the system (IFF_UP). At this point all resources needed | |
3072 | * for transmit and receive operations are allocated, the interrupt | |
3073 | * handler is registered with the OS, the watchdog timer is started, | |
3074 | * and the stack is notified that the interface is ready. | |
3075 | **/ | |
3076 | static int ixgbe_open(struct net_device *netdev) | |
3077 | { | |
3078 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3079 | int err; | |
4bebfaa5 AK |
3080 | |
3081 | /* disallow open during test */ | |
3082 | if (test_bit(__IXGBE_TESTING, &adapter->state)) | |
3083 | return -EBUSY; | |
9a799d71 | 3084 | |
9a799d71 AK |
3085 | /* allocate transmit descriptors */ |
3086 | err = ixgbe_setup_all_tx_resources(adapter); | |
3087 | if (err) | |
3088 | goto err_setup_tx; | |
3089 | ||
9a799d71 AK |
3090 | /* allocate receive descriptors */ |
3091 | err = ixgbe_setup_all_rx_resources(adapter); | |
3092 | if (err) | |
3093 | goto err_setup_rx; | |
3094 | ||
3095 | ixgbe_configure(adapter); | |
3096 | ||
021230d4 | 3097 | err = ixgbe_request_irq(adapter); |
9a799d71 AK |
3098 | if (err) |
3099 | goto err_req_irq; | |
3100 | ||
9a799d71 AK |
3101 | err = ixgbe_up_complete(adapter); |
3102 | if (err) | |
3103 | goto err_up; | |
3104 | ||
d55b53ff JK |
3105 | netif_tx_start_all_queues(netdev); |
3106 | ||
9a799d71 AK |
3107 | return 0; |
3108 | ||
3109 | err_up: | |
5eba3699 | 3110 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
3111 | ixgbe_free_irq(adapter); |
3112 | err_req_irq: | |
3113 | ixgbe_free_all_rx_resources(adapter); | |
3114 | err_setup_rx: | |
3115 | ixgbe_free_all_tx_resources(adapter); | |
3116 | err_setup_tx: | |
3117 | ixgbe_reset(adapter); | |
3118 | ||
3119 | return err; | |
3120 | } | |
3121 | ||
3122 | /** | |
3123 | * ixgbe_close - Disables a network interface | |
3124 | * @netdev: network interface device structure | |
3125 | * | |
3126 | * Returns 0, this is not allowed to fail | |
3127 | * | |
3128 | * The close entry point is called when an interface is de-activated | |
3129 | * by the OS. The hardware is still under the drivers control, but | |
3130 | * needs to be disabled. A global MAC reset is issued to stop the | |
3131 | * hardware, and all transmit and receive resources are freed. | |
3132 | **/ | |
3133 | static int ixgbe_close(struct net_device *netdev) | |
3134 | { | |
3135 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
9a799d71 AK |
3136 | |
3137 | ixgbe_down(adapter); | |
3138 | ixgbe_free_irq(adapter); | |
3139 | ||
3140 | ixgbe_free_all_tx_resources(adapter); | |
3141 | ixgbe_free_all_rx_resources(adapter); | |
3142 | ||
5eba3699 | 3143 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
3144 | |
3145 | return 0; | |
3146 | } | |
3147 | ||
b3c8b4ba AD |
3148 | /** |
3149 | * ixgbe_napi_add_all - prep napi structs for use | |
3150 | * @adapter: private struct | |
3151 | * helper function to napi_add each possible q_vector->napi | |
3152 | */ | |
2f90b865 | 3153 | void ixgbe_napi_add_all(struct ixgbe_adapter *adapter) |
b3c8b4ba AD |
3154 | { |
3155 | int q_idx, q_vectors; | |
7adf1525 | 3156 | struct net_device *netdev = adapter->netdev; |
b3c8b4ba AD |
3157 | int (*poll)(struct napi_struct *, int); |
3158 | ||
7adf1525 PWJ |
3159 | /* check if we already have our netdev->napi_list populated */ |
3160 | if (&netdev->napi_list != netdev->napi_list.next) | |
3161 | return; | |
3162 | ||
b3c8b4ba AD |
3163 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
3164 | poll = &ixgbe_clean_rxonly; | |
3165 | /* Only enable as many vectors as we have rx queues. */ | |
3166 | q_vectors = adapter->num_rx_queues; | |
3167 | } else { | |
3168 | poll = &ixgbe_poll; | |
3169 | /* only one q_vector for legacy modes */ | |
3170 | q_vectors = 1; | |
3171 | } | |
3172 | ||
3173 | for (q_idx = 0; q_idx < q_vectors; q_idx++) { | |
3174 | struct ixgbe_q_vector *q_vector = &adapter->q_vector[q_idx]; | |
3175 | netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64); | |
3176 | } | |
3177 | } | |
3178 | ||
2f90b865 | 3179 | void ixgbe_napi_del_all(struct ixgbe_adapter *adapter) |
b3c8b4ba AD |
3180 | { |
3181 | int q_idx; | |
3182 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
3183 | ||
3184 | /* legacy and MSI only use one vector */ | |
3185 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
3186 | q_vectors = 1; | |
3187 | ||
3188 | for (q_idx = 0; q_idx < q_vectors; q_idx++) { | |
3189 | struct ixgbe_q_vector *q_vector = &adapter->q_vector[q_idx]; | |
3190 | if (!q_vector->rxr_count) | |
3191 | continue; | |
3192 | netif_napi_del(&q_vector->napi); | |
3193 | } | |
3194 | } | |
3195 | ||
3196 | #ifdef CONFIG_PM | |
3197 | static int ixgbe_resume(struct pci_dev *pdev) | |
3198 | { | |
3199 | struct net_device *netdev = pci_get_drvdata(pdev); | |
3200 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3201 | u32 err; | |
3202 | ||
3203 | pci_set_power_state(pdev, PCI_D0); | |
3204 | pci_restore_state(pdev); | |
3205 | err = pci_enable_device(pdev); | |
3206 | if (err) { | |
69888674 | 3207 | printk(KERN_ERR "ixgbe: Cannot enable PCI device from " |
b3c8b4ba AD |
3208 | "suspend\n"); |
3209 | return err; | |
3210 | } | |
3211 | pci_set_master(pdev); | |
3212 | ||
3213 | pci_enable_wake(pdev, PCI_D3hot, 0); | |
3214 | pci_enable_wake(pdev, PCI_D3cold, 0); | |
3215 | ||
3216 | err = ixgbe_init_interrupt_scheme(adapter); | |
3217 | if (err) { | |
3218 | printk(KERN_ERR "ixgbe: Cannot initialize interrupts for " | |
3219 | "device\n"); | |
3220 | return err; | |
3221 | } | |
3222 | ||
3223 | ixgbe_napi_add_all(adapter); | |
3224 | ixgbe_reset(adapter); | |
3225 | ||
3226 | if (netif_running(netdev)) { | |
3227 | err = ixgbe_open(adapter->netdev); | |
3228 | if (err) | |
3229 | return err; | |
3230 | } | |
3231 | ||
3232 | netif_device_attach(netdev); | |
3233 | ||
3234 | return 0; | |
3235 | } | |
3236 | ||
3237 | #endif /* CONFIG_PM */ | |
3238 | static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state) | |
3239 | { | |
3240 | struct net_device *netdev = pci_get_drvdata(pdev); | |
3241 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3242 | #ifdef CONFIG_PM | |
3243 | int retval = 0; | |
3244 | #endif | |
3245 | ||
3246 | netif_device_detach(netdev); | |
3247 | ||
3248 | if (netif_running(netdev)) { | |
3249 | ixgbe_down(adapter); | |
3250 | ixgbe_free_irq(adapter); | |
3251 | ixgbe_free_all_tx_resources(adapter); | |
3252 | ixgbe_free_all_rx_resources(adapter); | |
3253 | } | |
3254 | ixgbe_reset_interrupt_capability(adapter); | |
3255 | ixgbe_napi_del_all(adapter); | |
7adf1525 | 3256 | INIT_LIST_HEAD(&netdev->napi_list); |
b3c8b4ba AD |
3257 | kfree(adapter->tx_ring); |
3258 | kfree(adapter->rx_ring); | |
3259 | ||
3260 | #ifdef CONFIG_PM | |
3261 | retval = pci_save_state(pdev); | |
3262 | if (retval) | |
3263 | return retval; | |
3264 | #endif | |
3265 | ||
3266 | pci_enable_wake(pdev, PCI_D3hot, 0); | |
3267 | pci_enable_wake(pdev, PCI_D3cold, 0); | |
3268 | ||
3269 | ixgbe_release_hw_control(adapter); | |
3270 | ||
3271 | pci_disable_device(pdev); | |
3272 | ||
3273 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); | |
3274 | ||
3275 | return 0; | |
3276 | } | |
3277 | ||
3278 | static void ixgbe_shutdown(struct pci_dev *pdev) | |
3279 | { | |
3280 | ixgbe_suspend(pdev, PMSG_SUSPEND); | |
3281 | } | |
3282 | ||
9a799d71 AK |
3283 | /** |
3284 | * ixgbe_update_stats - Update the board statistics counters. | |
3285 | * @adapter: board private structure | |
3286 | **/ | |
3287 | void ixgbe_update_stats(struct ixgbe_adapter *adapter) | |
3288 | { | |
3289 | struct ixgbe_hw *hw = &adapter->hw; | |
6f11eef7 AV |
3290 | u64 total_mpc = 0; |
3291 | u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot; | |
9a799d71 AK |
3292 | |
3293 | adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); | |
6f11eef7 AV |
3294 | for (i = 0; i < 8; i++) { |
3295 | /* for packet buffers not used, the register should read 0 */ | |
3296 | mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i)); | |
3297 | missed_rx += mpc; | |
3298 | adapter->stats.mpc[i] += mpc; | |
3299 | total_mpc += adapter->stats.mpc[i]; | |
3300 | adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); | |
2f90b865 AD |
3301 | adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); |
3302 | adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i)); | |
3303 | adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); | |
3304 | adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i)); | |
3305 | adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw, | |
3306 | IXGBE_PXONRXC(i)); | |
3307 | adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw, | |
3308 | IXGBE_PXONTXC(i)); | |
3309 | adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw, | |
3310 | IXGBE_PXOFFRXC(i)); | |
3311 | adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw, | |
3312 | IXGBE_PXOFFTXC(i)); | |
6f11eef7 AV |
3313 | } |
3314 | adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); | |
3315 | /* work around hardware counting issue */ | |
3316 | adapter->stats.gprc -= missed_rx; | |
3317 | ||
3318 | /* 82598 hardware only has a 32 bit counter in the high register */ | |
9a799d71 | 3319 | adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); |
6f11eef7 AV |
3320 | adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); |
3321 | adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH); | |
9a799d71 AK |
3322 | bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); |
3323 | adapter->stats.bprc += bprc; | |
3324 | adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); | |
3325 | adapter->stats.mprc -= bprc; | |
3326 | adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC); | |
3327 | adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); | |
3328 | adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); | |
3329 | adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); | |
3330 | adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); | |
3331 | adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); | |
3332 | adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); | |
9a799d71 AK |
3333 | adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); |
3334 | adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); | |
9a799d71 | 3335 | adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); |
6f11eef7 AV |
3336 | lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); |
3337 | adapter->stats.lxontxc += lxon; | |
3338 | lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); | |
3339 | adapter->stats.lxofftxc += lxoff; | |
9a799d71 AK |
3340 | adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC); |
3341 | adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); | |
6f11eef7 AV |
3342 | adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); |
3343 | /* | |
3344 | * 82598 errata - tx of flow control packets is included in tx counters | |
3345 | */ | |
3346 | xon_off_tot = lxon + lxoff; | |
3347 | adapter->stats.gptc -= xon_off_tot; | |
3348 | adapter->stats.mptc -= xon_off_tot; | |
3349 | adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN)); | |
9a799d71 AK |
3350 | adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC); |
3351 | adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC); | |
3352 | adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC); | |
9a799d71 AK |
3353 | adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR); |
3354 | adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); | |
6f11eef7 | 3355 | adapter->stats.ptc64 -= xon_off_tot; |
9a799d71 AK |
3356 | adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); |
3357 | adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); | |
3358 | adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); | |
3359 | adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); | |
3360 | adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); | |
9a799d71 AK |
3361 | adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); |
3362 | ||
3363 | /* Fill out the OS statistics structure */ | |
9a799d71 AK |
3364 | adapter->net_stats.multicast = adapter->stats.mprc; |
3365 | ||
3366 | /* Rx Errors */ | |
3367 | adapter->net_stats.rx_errors = adapter->stats.crcerrs + | |
b4617240 | 3368 | adapter->stats.rlec; |
9a799d71 AK |
3369 | adapter->net_stats.rx_dropped = 0; |
3370 | adapter->net_stats.rx_length_errors = adapter->stats.rlec; | |
3371 | adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs; | |
6f11eef7 | 3372 | adapter->net_stats.rx_missed_errors = total_mpc; |
9a799d71 AK |
3373 | } |
3374 | ||
3375 | /** | |
3376 | * ixgbe_watchdog - Timer Call-back | |
3377 | * @data: pointer to adapter cast into an unsigned long | |
3378 | **/ | |
3379 | static void ixgbe_watchdog(unsigned long data) | |
3380 | { | |
3381 | struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data; | |
cf8280ee JB |
3382 | struct ixgbe_hw *hw = &adapter->hw; |
3383 | ||
3384 | /* Do the watchdog outside of interrupt context due to the lovely | |
3385 | * delays that some of the newer hardware requires */ | |
3386 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { | |
3387 | /* Cause software interrupt to ensure rx rings are cleaned */ | |
3388 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
3389 | u32 eics = | |
3390 | (1 << (adapter->num_msix_vectors - NON_Q_VECTORS)) - 1; | |
3391 | IXGBE_WRITE_REG(hw, IXGBE_EICS, eics); | |
3392 | } else { | |
3393 | /* For legacy and MSI interrupts don't set any bits that | |
3394 | * are enabled for EIAM, because this operation would | |
3395 | * set *both* EIMS and EICS for any bit in EIAM */ | |
3396 | IXGBE_WRITE_REG(hw, IXGBE_EICS, | |
3397 | (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); | |
3398 | } | |
3399 | /* Reset the timer */ | |
3400 | mod_timer(&adapter->watchdog_timer, | |
3401 | round_jiffies(jiffies + 2 * HZ)); | |
3402 | } | |
9a799d71 | 3403 | |
cf8280ee JB |
3404 | schedule_work(&adapter->watchdog_task); |
3405 | } | |
3406 | ||
3407 | /** | |
69888674 AD |
3408 | * ixgbe_watchdog_task - worker thread to bring link up |
3409 | * @work: pointer to work_struct containing our data | |
cf8280ee JB |
3410 | **/ |
3411 | static void ixgbe_watchdog_task(struct work_struct *work) | |
3412 | { | |
3413 | struct ixgbe_adapter *adapter = container_of(work, | |
3414 | struct ixgbe_adapter, | |
3415 | watchdog_task); | |
3416 | struct net_device *netdev = adapter->netdev; | |
3417 | struct ixgbe_hw *hw = &adapter->hw; | |
3418 | u32 link_speed = adapter->link_speed; | |
3419 | bool link_up = adapter->link_up; | |
3420 | ||
3421 | adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK; | |
3422 | ||
3423 | if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) { | |
3424 | hw->mac.ops.check_link(hw, &link_speed, &link_up, false); | |
3425 | if (link_up || | |
3426 | time_after(jiffies, (adapter->link_check_timeout + | |
3427 | IXGBE_TRY_LINK_TIMEOUT))) { | |
3428 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC); | |
3429 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; | |
3430 | } | |
3431 | adapter->link_up = link_up; | |
3432 | adapter->link_speed = link_speed; | |
3433 | } | |
9a799d71 AK |
3434 | |
3435 | if (link_up) { | |
3436 | if (!netif_carrier_ok(netdev)) { | |
cf8280ee JB |
3437 | u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL); |
3438 | u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS); | |
9a799d71 AK |
3439 | #define FLOW_RX (frctl & IXGBE_FCTRL_RFCE) |
3440 | #define FLOW_TX (rmcs & IXGBE_RMCS_TFCE_802_3X) | |
a46e534b JK |
3441 | printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, " |
3442 | "Flow Control: %s\n", | |
3443 | netdev->name, | |
3444 | (link_speed == IXGBE_LINK_SPEED_10GB_FULL ? | |
3445 | "10 Gbps" : | |
3446 | (link_speed == IXGBE_LINK_SPEED_1GB_FULL ? | |
3447 | "1 Gbps" : "unknown speed")), | |
3448 | ((FLOW_RX && FLOW_TX) ? "RX/TX" : | |
3449 | (FLOW_RX ? "RX" : | |
3450 | (FLOW_TX ? "TX" : "None")))); | |
9a799d71 AK |
3451 | |
3452 | netif_carrier_on(netdev); | |
9a799d71 AK |
3453 | } else { |
3454 | /* Force detection of hung controller */ | |
3455 | adapter->detect_tx_hung = true; | |
3456 | } | |
3457 | } else { | |
cf8280ee JB |
3458 | adapter->link_up = false; |
3459 | adapter->link_speed = 0; | |
9a799d71 | 3460 | if (netif_carrier_ok(netdev)) { |
a46e534b JK |
3461 | printk(KERN_INFO "ixgbe: %s NIC Link is Down\n", |
3462 | netdev->name); | |
9a799d71 | 3463 | netif_carrier_off(netdev); |
9a799d71 AK |
3464 | } |
3465 | } | |
3466 | ||
3467 | ixgbe_update_stats(adapter); | |
cf8280ee | 3468 | adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK; |
9a799d71 AK |
3469 | } |
3470 | ||
9a799d71 | 3471 | static int ixgbe_tso(struct ixgbe_adapter *adapter, |
b4617240 PW |
3472 | struct ixgbe_ring *tx_ring, struct sk_buff *skb, |
3473 | u32 tx_flags, u8 *hdr_len) | |
9a799d71 AK |
3474 | { |
3475 | struct ixgbe_adv_tx_context_desc *context_desc; | |
3476 | unsigned int i; | |
3477 | int err; | |
3478 | struct ixgbe_tx_buffer *tx_buffer_info; | |
9f8cdf4f JB |
3479 | u32 vlan_macip_lens = 0, type_tucmd_mlhl; |
3480 | u32 mss_l4len_idx, l4len; | |
9a799d71 AK |
3481 | |
3482 | if (skb_is_gso(skb)) { | |
3483 | if (skb_header_cloned(skb)) { | |
3484 | err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); | |
3485 | if (err) | |
3486 | return err; | |
3487 | } | |
3488 | l4len = tcp_hdrlen(skb); | |
3489 | *hdr_len += l4len; | |
3490 | ||
8327d000 | 3491 | if (skb->protocol == htons(ETH_P_IP)) { |
9a799d71 AK |
3492 | struct iphdr *iph = ip_hdr(skb); |
3493 | iph->tot_len = 0; | |
3494 | iph->check = 0; | |
3495 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, | |
b4617240 PW |
3496 | iph->daddr, 0, |
3497 | IPPROTO_TCP, | |
3498 | 0); | |
9a799d71 AK |
3499 | adapter->hw_tso_ctxt++; |
3500 | } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) { | |
3501 | ipv6_hdr(skb)->payload_len = 0; | |
3502 | tcp_hdr(skb)->check = | |
3503 | ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, | |
b4617240 PW |
3504 | &ipv6_hdr(skb)->daddr, |
3505 | 0, IPPROTO_TCP, 0); | |
9a799d71 AK |
3506 | adapter->hw_tso6_ctxt++; |
3507 | } | |
3508 | ||
3509 | i = tx_ring->next_to_use; | |
3510 | ||
3511 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
3512 | context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i); | |
3513 | ||
3514 | /* VLAN MACLEN IPLEN */ | |
3515 | if (tx_flags & IXGBE_TX_FLAGS_VLAN) | |
3516 | vlan_macip_lens |= | |
3517 | (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK); | |
3518 | vlan_macip_lens |= ((skb_network_offset(skb)) << | |
b4617240 | 3519 | IXGBE_ADVTXD_MACLEN_SHIFT); |
9a799d71 AK |
3520 | *hdr_len += skb_network_offset(skb); |
3521 | vlan_macip_lens |= | |
3522 | (skb_transport_header(skb) - skb_network_header(skb)); | |
3523 | *hdr_len += | |
3524 | (skb_transport_header(skb) - skb_network_header(skb)); | |
3525 | context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); | |
3526 | context_desc->seqnum_seed = 0; | |
3527 | ||
3528 | /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ | |
9f8cdf4f | 3529 | type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT | |
b4617240 | 3530 | IXGBE_ADVTXD_DTYP_CTXT); |
9a799d71 | 3531 | |
8327d000 | 3532 | if (skb->protocol == htons(ETH_P_IP)) |
9a799d71 AK |
3533 | type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4; |
3534 | type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP; | |
3535 | context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl); | |
3536 | ||
3537 | /* MSS L4LEN IDX */ | |
9f8cdf4f | 3538 | mss_l4len_idx = |
9a799d71 AK |
3539 | (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT); |
3540 | mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT); | |
4eeae6fd PW |
3541 | /* use index 1 for TSO */ |
3542 | mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT); | |
9a799d71 AK |
3543 | context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); |
3544 | ||
3545 | tx_buffer_info->time_stamp = jiffies; | |
3546 | tx_buffer_info->next_to_watch = i; | |
3547 | ||
3548 | i++; | |
3549 | if (i == tx_ring->count) | |
3550 | i = 0; | |
3551 | tx_ring->next_to_use = i; | |
3552 | ||
3553 | return true; | |
3554 | } | |
3555 | return false; | |
3556 | } | |
3557 | ||
3558 | static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter, | |
b4617240 PW |
3559 | struct ixgbe_ring *tx_ring, |
3560 | struct sk_buff *skb, u32 tx_flags) | |
9a799d71 AK |
3561 | { |
3562 | struct ixgbe_adv_tx_context_desc *context_desc; | |
3563 | unsigned int i; | |
3564 | struct ixgbe_tx_buffer *tx_buffer_info; | |
3565 | u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0; | |
3566 | ||
3567 | if (skb->ip_summed == CHECKSUM_PARTIAL || | |
3568 | (tx_flags & IXGBE_TX_FLAGS_VLAN)) { | |
3569 | i = tx_ring->next_to_use; | |
3570 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
3571 | context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i); | |
3572 | ||
3573 | if (tx_flags & IXGBE_TX_FLAGS_VLAN) | |
3574 | vlan_macip_lens |= | |
3575 | (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK); | |
3576 | vlan_macip_lens |= (skb_network_offset(skb) << | |
b4617240 | 3577 | IXGBE_ADVTXD_MACLEN_SHIFT); |
9a799d71 AK |
3578 | if (skb->ip_summed == CHECKSUM_PARTIAL) |
3579 | vlan_macip_lens |= (skb_transport_header(skb) - | |
b4617240 | 3580 | skb_network_header(skb)); |
9a799d71 AK |
3581 | |
3582 | context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); | |
3583 | context_desc->seqnum_seed = 0; | |
3584 | ||
3585 | type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT | | |
b4617240 | 3586 | IXGBE_ADVTXD_DTYP_CTXT); |
9a799d71 AK |
3587 | |
3588 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
41825d71 | 3589 | switch (skb->protocol) { |
09640e63 | 3590 | case cpu_to_be16(ETH_P_IP): |
9a799d71 | 3591 | type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4; |
41825d71 AK |
3592 | if (ip_hdr(skb)->protocol == IPPROTO_TCP) |
3593 | type_tucmd_mlhl |= | |
b4617240 | 3594 | IXGBE_ADVTXD_TUCMD_L4T_TCP; |
41825d71 | 3595 | break; |
09640e63 | 3596 | case cpu_to_be16(ETH_P_IPV6): |
41825d71 AK |
3597 | /* XXX what about other V6 headers?? */ |
3598 | if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP) | |
3599 | type_tucmd_mlhl |= | |
b4617240 | 3600 | IXGBE_ADVTXD_TUCMD_L4T_TCP; |
41825d71 | 3601 | break; |
41825d71 AK |
3602 | default: |
3603 | if (unlikely(net_ratelimit())) { | |
3604 | DPRINTK(PROBE, WARNING, | |
3605 | "partial checksum but proto=%x!\n", | |
3606 | skb->protocol); | |
3607 | } | |
3608 | break; | |
3609 | } | |
9a799d71 AK |
3610 | } |
3611 | ||
3612 | context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl); | |
4eeae6fd | 3613 | /* use index zero for tx checksum offload */ |
9a799d71 AK |
3614 | context_desc->mss_l4len_idx = 0; |
3615 | ||
3616 | tx_buffer_info->time_stamp = jiffies; | |
3617 | tx_buffer_info->next_to_watch = i; | |
9f8cdf4f | 3618 | |
9a799d71 AK |
3619 | adapter->hw_csum_tx_good++; |
3620 | i++; | |
3621 | if (i == tx_ring->count) | |
3622 | i = 0; | |
3623 | tx_ring->next_to_use = i; | |
3624 | ||
3625 | return true; | |
3626 | } | |
9f8cdf4f | 3627 | |
9a799d71 AK |
3628 | return false; |
3629 | } | |
3630 | ||
3631 | static int ixgbe_tx_map(struct ixgbe_adapter *adapter, | |
b4617240 PW |
3632 | struct ixgbe_ring *tx_ring, |
3633 | struct sk_buff *skb, unsigned int first) | |
9a799d71 AK |
3634 | { |
3635 | struct ixgbe_tx_buffer *tx_buffer_info; | |
3636 | unsigned int len = skb->len; | |
3637 | unsigned int offset = 0, size, count = 0, i; | |
3638 | unsigned int nr_frags = skb_shinfo(skb)->nr_frags; | |
3639 | unsigned int f; | |
3640 | ||
3641 | len -= skb->data_len; | |
3642 | ||
3643 | i = tx_ring->next_to_use; | |
3644 | ||
3645 | while (len) { | |
3646 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
3647 | size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD); | |
3648 | ||
3649 | tx_buffer_info->length = size; | |
3650 | tx_buffer_info->dma = pci_map_single(adapter->pdev, | |
b4617240 PW |
3651 | skb->data + offset, |
3652 | size, PCI_DMA_TODEVICE); | |
9a799d71 AK |
3653 | tx_buffer_info->time_stamp = jiffies; |
3654 | tx_buffer_info->next_to_watch = i; | |
3655 | ||
3656 | len -= size; | |
3657 | offset += size; | |
3658 | count++; | |
3659 | i++; | |
3660 | if (i == tx_ring->count) | |
3661 | i = 0; | |
3662 | } | |
3663 | ||
3664 | for (f = 0; f < nr_frags; f++) { | |
3665 | struct skb_frag_struct *frag; | |
3666 | ||
3667 | frag = &skb_shinfo(skb)->frags[f]; | |
3668 | len = frag->size; | |
3669 | offset = frag->page_offset; | |
3670 | ||
3671 | while (len) { | |
3672 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
3673 | size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD); | |
3674 | ||
3675 | tx_buffer_info->length = size; | |
3676 | tx_buffer_info->dma = pci_map_page(adapter->pdev, | |
b4617240 PW |
3677 | frag->page, |
3678 | offset, | |
3679 | size, | |
3680 | PCI_DMA_TODEVICE); | |
9a799d71 AK |
3681 | tx_buffer_info->time_stamp = jiffies; |
3682 | tx_buffer_info->next_to_watch = i; | |
3683 | ||
3684 | len -= size; | |
3685 | offset += size; | |
3686 | count++; | |
3687 | i++; | |
3688 | if (i == tx_ring->count) | |
3689 | i = 0; | |
3690 | } | |
3691 | } | |
3692 | if (i == 0) | |
3693 | i = tx_ring->count - 1; | |
3694 | else | |
3695 | i = i - 1; | |
3696 | tx_ring->tx_buffer_info[i].skb = skb; | |
3697 | tx_ring->tx_buffer_info[first].next_to_watch = i; | |
3698 | ||
3699 | return count; | |
3700 | } | |
3701 | ||
3702 | static void ixgbe_tx_queue(struct ixgbe_adapter *adapter, | |
b4617240 PW |
3703 | struct ixgbe_ring *tx_ring, |
3704 | int tx_flags, int count, u32 paylen, u8 hdr_len) | |
9a799d71 AK |
3705 | { |
3706 | union ixgbe_adv_tx_desc *tx_desc = NULL; | |
3707 | struct ixgbe_tx_buffer *tx_buffer_info; | |
3708 | u32 olinfo_status = 0, cmd_type_len = 0; | |
3709 | unsigned int i; | |
3710 | u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS; | |
3711 | ||
3712 | cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA; | |
3713 | ||
3714 | cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT; | |
3715 | ||
3716 | if (tx_flags & IXGBE_TX_FLAGS_VLAN) | |
3717 | cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE; | |
3718 | ||
3719 | if (tx_flags & IXGBE_TX_FLAGS_TSO) { | |
3720 | cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE; | |
3721 | ||
3722 | olinfo_status |= IXGBE_TXD_POPTS_TXSM << | |
b4617240 | 3723 | IXGBE_ADVTXD_POPTS_SHIFT; |
9a799d71 | 3724 | |
4eeae6fd PW |
3725 | /* use index 1 context for tso */ |
3726 | olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT); | |
9a799d71 AK |
3727 | if (tx_flags & IXGBE_TX_FLAGS_IPV4) |
3728 | olinfo_status |= IXGBE_TXD_POPTS_IXSM << | |
b4617240 | 3729 | IXGBE_ADVTXD_POPTS_SHIFT; |
9a799d71 AK |
3730 | |
3731 | } else if (tx_flags & IXGBE_TX_FLAGS_CSUM) | |
3732 | olinfo_status |= IXGBE_TXD_POPTS_TXSM << | |
b4617240 | 3733 | IXGBE_ADVTXD_POPTS_SHIFT; |
9a799d71 AK |
3734 | |
3735 | olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT); | |
3736 | ||
3737 | i = tx_ring->next_to_use; | |
3738 | while (count--) { | |
3739 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
3740 | tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i); | |
3741 | tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma); | |
3742 | tx_desc->read.cmd_type_len = | |
b4617240 | 3743 | cpu_to_le32(cmd_type_len | tx_buffer_info->length); |
9a799d71 | 3744 | tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); |
9a799d71 AK |
3745 | i++; |
3746 | if (i == tx_ring->count) | |
3747 | i = 0; | |
3748 | } | |
3749 | ||
3750 | tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd); | |
3751 | ||
3752 | /* | |
3753 | * Force memory writes to complete before letting h/w | |
3754 | * know there are new descriptors to fetch. (Only | |
3755 | * applicable for weak-ordered memory model archs, | |
3756 | * such as IA-64). | |
3757 | */ | |
3758 | wmb(); | |
3759 | ||
3760 | tx_ring->next_to_use = i; | |
3761 | writel(i, adapter->hw.hw_addr + tx_ring->tail); | |
3762 | } | |
3763 | ||
e092be60 | 3764 | static int __ixgbe_maybe_stop_tx(struct net_device *netdev, |
b4617240 | 3765 | struct ixgbe_ring *tx_ring, int size) |
e092be60 AV |
3766 | { |
3767 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3768 | ||
30eba97a | 3769 | netif_stop_subqueue(netdev, tx_ring->queue_index); |
e092be60 AV |
3770 | /* Herbert's original patch had: |
3771 | * smp_mb__after_netif_stop_queue(); | |
3772 | * but since that doesn't exist yet, just open code it. */ | |
3773 | smp_mb(); | |
3774 | ||
3775 | /* We need to check again in a case another CPU has just | |
3776 | * made room available. */ | |
3777 | if (likely(IXGBE_DESC_UNUSED(tx_ring) < size)) | |
3778 | return -EBUSY; | |
3779 | ||
3780 | /* A reprieve! - use start_queue because it doesn't call schedule */ | |
af72166f | 3781 | netif_start_subqueue(netdev, tx_ring->queue_index); |
e092be60 AV |
3782 | ++adapter->restart_queue; |
3783 | return 0; | |
3784 | } | |
3785 | ||
3786 | static int ixgbe_maybe_stop_tx(struct net_device *netdev, | |
b4617240 | 3787 | struct ixgbe_ring *tx_ring, int size) |
e092be60 AV |
3788 | { |
3789 | if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size)) | |
3790 | return 0; | |
3791 | return __ixgbe_maybe_stop_tx(netdev, tx_ring, size); | |
3792 | } | |
3793 | ||
9a799d71 AK |
3794 | static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev) |
3795 | { | |
3796 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3797 | struct ixgbe_ring *tx_ring; | |
9a799d71 AK |
3798 | unsigned int first; |
3799 | unsigned int tx_flags = 0; | |
30eba97a AV |
3800 | u8 hdr_len = 0; |
3801 | int r_idx = 0, tso; | |
9a799d71 AK |
3802 | int count = 0; |
3803 | unsigned int f; | |
9f8cdf4f | 3804 | |
30eba97a | 3805 | r_idx = (adapter->num_tx_queues - 1) & skb->queue_mapping; |
30eba97a | 3806 | tx_ring = &adapter->tx_ring[r_idx]; |
9a799d71 | 3807 | |
9f8cdf4f JB |
3808 | if (adapter->vlgrp && vlan_tx_tag_present(skb)) { |
3809 | tx_flags |= vlan_tx_tag_get(skb); | |
2f90b865 AD |
3810 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { |
3811 | tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK; | |
3812 | tx_flags |= (skb->queue_mapping << 13); | |
3813 | } | |
3814 | tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT; | |
3815 | tx_flags |= IXGBE_TX_FLAGS_VLAN; | |
3816 | } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
3817 | tx_flags |= (skb->queue_mapping << 13); | |
9f8cdf4f JB |
3818 | tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT; |
3819 | tx_flags |= IXGBE_TX_FLAGS_VLAN; | |
9a799d71 | 3820 | } |
9f8cdf4f JB |
3821 | /* three things can cause us to need a context descriptor */ |
3822 | if (skb_is_gso(skb) || | |
3823 | (skb->ip_summed == CHECKSUM_PARTIAL) || | |
3824 | (tx_flags & IXGBE_TX_FLAGS_VLAN)) | |
9a799d71 AK |
3825 | count++; |
3826 | ||
9f8cdf4f JB |
3827 | count += TXD_USE_COUNT(skb_headlen(skb)); |
3828 | for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) | |
9a799d71 AK |
3829 | count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); |
3830 | ||
e092be60 | 3831 | if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) { |
9a799d71 | 3832 | adapter->tx_busy++; |
9a799d71 AK |
3833 | return NETDEV_TX_BUSY; |
3834 | } | |
9a799d71 | 3835 | |
8327d000 | 3836 | if (skb->protocol == htons(ETH_P_IP)) |
9a799d71 AK |
3837 | tx_flags |= IXGBE_TX_FLAGS_IPV4; |
3838 | first = tx_ring->next_to_use; | |
3839 | tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len); | |
3840 | if (tso < 0) { | |
3841 | dev_kfree_skb_any(skb); | |
3842 | return NETDEV_TX_OK; | |
3843 | } | |
3844 | ||
3845 | if (tso) | |
3846 | tx_flags |= IXGBE_TX_FLAGS_TSO; | |
3847 | else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) && | |
b4617240 | 3848 | (skb->ip_summed == CHECKSUM_PARTIAL)) |
9a799d71 AK |
3849 | tx_flags |= IXGBE_TX_FLAGS_CSUM; |
3850 | ||
3851 | ixgbe_tx_queue(adapter, tx_ring, tx_flags, | |
b4617240 PW |
3852 | ixgbe_tx_map(adapter, tx_ring, skb, first), |
3853 | skb->len, hdr_len); | |
9a799d71 AK |
3854 | |
3855 | netdev->trans_start = jiffies; | |
3856 | ||
e092be60 | 3857 | ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED); |
9a799d71 AK |
3858 | |
3859 | return NETDEV_TX_OK; | |
3860 | } | |
3861 | ||
3862 | /** | |
3863 | * ixgbe_get_stats - Get System Network Statistics | |
3864 | * @netdev: network interface device structure | |
3865 | * | |
3866 | * Returns the address of the device statistics structure. | |
3867 | * The statistics are actually updated from the timer callback. | |
3868 | **/ | |
3869 | static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev) | |
3870 | { | |
3871 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3872 | ||
3873 | /* only return the current stats */ | |
3874 | return &adapter->net_stats; | |
3875 | } | |
3876 | ||
3877 | /** | |
3878 | * ixgbe_set_mac - Change the Ethernet Address of the NIC | |
3879 | * @netdev: network interface device structure | |
3880 | * @p: pointer to an address structure | |
3881 | * | |
3882 | * Returns 0 on success, negative on failure | |
3883 | **/ | |
3884 | static int ixgbe_set_mac(struct net_device *netdev, void *p) | |
3885 | { | |
3886 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
b4617240 | 3887 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 AK |
3888 | struct sockaddr *addr = p; |
3889 | ||
3890 | if (!is_valid_ether_addr(addr->sa_data)) | |
3891 | return -EADDRNOTAVAIL; | |
3892 | ||
3893 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | |
b4617240 | 3894 | memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); |
9a799d71 | 3895 | |
b4617240 | 3896 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); |
9a799d71 AK |
3897 | |
3898 | return 0; | |
3899 | } | |
3900 | ||
3901 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
3902 | /* | |
3903 | * Polling 'interrupt' - used by things like netconsole to send skbs | |
3904 | * without having to re-enable interrupts. It's not called while | |
3905 | * the interrupt routine is executing. | |
3906 | */ | |
3907 | static void ixgbe_netpoll(struct net_device *netdev) | |
3908 | { | |
3909 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3910 | ||
3911 | disable_irq(adapter->pdev->irq); | |
3912 | adapter->flags |= IXGBE_FLAG_IN_NETPOLL; | |
3913 | ixgbe_intr(adapter->pdev->irq, netdev); | |
3914 | adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL; | |
3915 | enable_irq(adapter->pdev->irq); | |
3916 | } | |
3917 | #endif | |
3918 | ||
c44ade9e JB |
3919 | /** |
3920 | * ixgbe_link_config - set up initial link with default speed and duplex | |
3921 | * @hw: pointer to private hardware struct | |
3922 | * | |
3923 | * Returns 0 on success, negative on failure | |
3924 | **/ | |
3925 | static int ixgbe_link_config(struct ixgbe_hw *hw) | |
3926 | { | |
5b9c3cdd DS |
3927 | u32 autoneg; |
3928 | bool link_up = false; | |
3929 | u32 ret = IXGBE_ERR_LINK_SETUP; | |
c44ade9e | 3930 | |
5b9c3cdd DS |
3931 | if (hw->mac.ops.check_link) |
3932 | ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false); | |
c44ade9e | 3933 | |
5b9c3cdd DS |
3934 | if (ret || !link_up) |
3935 | goto link_cfg_out; | |
0befdb3e | 3936 | |
5b9c3cdd DS |
3937 | if (hw->mac.ops.get_link_capabilities) |
3938 | ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, | |
3939 | &hw->mac.autoneg); | |
3940 | if (ret) | |
3941 | goto link_cfg_out; | |
3942 | ||
3943 | if (hw->mac.ops.setup_link_speed) | |
3944 | ret = hw->mac.ops.setup_link_speed(hw, autoneg, true, true); | |
3945 | ||
3946 | link_cfg_out: | |
3947 | return ret; | |
c44ade9e JB |
3948 | } |
3949 | ||
0edc3527 SH |
3950 | static const struct net_device_ops ixgbe_netdev_ops = { |
3951 | .ndo_open = ixgbe_open, | |
3952 | .ndo_stop = ixgbe_close, | |
00829823 | 3953 | .ndo_start_xmit = ixgbe_xmit_frame, |
0edc3527 SH |
3954 | .ndo_get_stats = ixgbe_get_stats, |
3955 | .ndo_set_multicast_list = ixgbe_set_rx_mode, | |
3956 | .ndo_validate_addr = eth_validate_addr, | |
3957 | .ndo_set_mac_address = ixgbe_set_mac, | |
3958 | .ndo_change_mtu = ixgbe_change_mtu, | |
3959 | .ndo_tx_timeout = ixgbe_tx_timeout, | |
3960 | .ndo_vlan_rx_register = ixgbe_vlan_rx_register, | |
3961 | .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid, | |
3962 | .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid, | |
3963 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
3964 | .ndo_poll_controller = ixgbe_netpoll, | |
3965 | #endif | |
3966 | }; | |
3967 | ||
9a799d71 AK |
3968 | /** |
3969 | * ixgbe_probe - Device Initialization Routine | |
3970 | * @pdev: PCI device information struct | |
3971 | * @ent: entry in ixgbe_pci_tbl | |
3972 | * | |
3973 | * Returns 0 on success, negative on failure | |
3974 | * | |
3975 | * ixgbe_probe initializes an adapter identified by a pci_dev structure. | |
3976 | * The OS initialization, configuring of the adapter private structure, | |
3977 | * and a hardware reset occur. | |
3978 | **/ | |
3979 | static int __devinit ixgbe_probe(struct pci_dev *pdev, | |
b4617240 | 3980 | const struct pci_device_id *ent) |
9a799d71 AK |
3981 | { |
3982 | struct net_device *netdev; | |
3983 | struct ixgbe_adapter *adapter = NULL; | |
3984 | struct ixgbe_hw *hw; | |
3985 | const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data]; | |
9a799d71 AK |
3986 | static int cards_found; |
3987 | int i, err, pci_using_dac; | |
3988 | u16 link_status, link_speed, link_width; | |
c44ade9e | 3989 | u32 part_num, eec; |
9a799d71 AK |
3990 | |
3991 | err = pci_enable_device(pdev); | |
3992 | if (err) | |
3993 | return err; | |
3994 | ||
3995 | if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK) && | |
3996 | !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK)) { | |
3997 | pci_using_dac = 1; | |
3998 | } else { | |
3999 | err = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
4000 | if (err) { | |
4001 | err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
4002 | if (err) { | |
b4617240 PW |
4003 | dev_err(&pdev->dev, "No usable DMA " |
4004 | "configuration, aborting\n"); | |
9a799d71 AK |
4005 | goto err_dma; |
4006 | } | |
4007 | } | |
4008 | pci_using_dac = 0; | |
4009 | } | |
4010 | ||
4011 | err = pci_request_regions(pdev, ixgbe_driver_name); | |
4012 | if (err) { | |
4013 | dev_err(&pdev->dev, "pci_request_regions failed 0x%x\n", err); | |
4014 | goto err_pci_reg; | |
4015 | } | |
4016 | ||
6fabd715 PWJ |
4017 | err = pci_enable_pcie_error_reporting(pdev); |
4018 | if (err) { | |
4019 | dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed " | |
4020 | "0x%x\n", err); | |
4021 | /* non-fatal, continue */ | |
4022 | } | |
4023 | ||
9a799d71 | 4024 | pci_set_master(pdev); |
fb3b27bc | 4025 | pci_save_state(pdev); |
9a799d71 | 4026 | |
30eba97a | 4027 | netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES); |
9a799d71 AK |
4028 | if (!netdev) { |
4029 | err = -ENOMEM; | |
4030 | goto err_alloc_etherdev; | |
4031 | } | |
4032 | ||
9a799d71 AK |
4033 | SET_NETDEV_DEV(netdev, &pdev->dev); |
4034 | ||
4035 | pci_set_drvdata(pdev, netdev); | |
4036 | adapter = netdev_priv(netdev); | |
4037 | ||
4038 | adapter->netdev = netdev; | |
4039 | adapter->pdev = pdev; | |
4040 | hw = &adapter->hw; | |
4041 | hw->back = adapter; | |
4042 | adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1; | |
4043 | ||
05857980 JK |
4044 | hw->hw_addr = ioremap(pci_resource_start(pdev, 0), |
4045 | pci_resource_len(pdev, 0)); | |
9a799d71 AK |
4046 | if (!hw->hw_addr) { |
4047 | err = -EIO; | |
4048 | goto err_ioremap; | |
4049 | } | |
4050 | ||
4051 | for (i = 1; i <= 5; i++) { | |
4052 | if (pci_resource_len(pdev, i) == 0) | |
4053 | continue; | |
4054 | } | |
4055 | ||
0edc3527 | 4056 | netdev->netdev_ops = &ixgbe_netdev_ops; |
9a799d71 | 4057 | ixgbe_set_ethtool_ops(netdev); |
9a799d71 | 4058 | netdev->watchdog_timeo = 5 * HZ; |
9a799d71 AK |
4059 | strcpy(netdev->name, pci_name(pdev)); |
4060 | ||
9a799d71 AK |
4061 | adapter->bd_number = cards_found; |
4062 | ||
9a799d71 AK |
4063 | /* Setup hw api */ |
4064 | memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops)); | |
021230d4 | 4065 | hw->mac.type = ii->mac; |
9a799d71 | 4066 | |
c44ade9e JB |
4067 | /* EEPROM */ |
4068 | memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops)); | |
4069 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); | |
4070 | /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */ | |
4071 | if (!(eec & (1 << 8))) | |
4072 | hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic; | |
4073 | ||
4074 | /* PHY */ | |
4075 | memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops)); | |
c4900be0 DS |
4076 | hw->phy.sfp_type = ixgbe_sfp_type_unknown; |
4077 | ||
4078 | /* set up this timer and work struct before calling get_invariants | |
4079 | * which might start the timer | |
4080 | */ | |
4081 | init_timer(&adapter->sfp_timer); | |
4082 | adapter->sfp_timer.function = &ixgbe_sfp_timer; | |
4083 | adapter->sfp_timer.data = (unsigned long) adapter; | |
4084 | ||
4085 | INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task); | |
c44ade9e | 4086 | |
9a799d71 | 4087 | err = ii->get_invariants(hw); |
c4900be0 DS |
4088 | if (err == IXGBE_ERR_SFP_NOT_PRESENT) { |
4089 | /* start a kernel thread to watch for a module to arrive */ | |
4090 | set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); | |
4091 | mod_timer(&adapter->sfp_timer, | |
4092 | round_jiffies(jiffies + (2 * HZ))); | |
4093 | err = 0; | |
4094 | } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
4095 | DPRINTK(PROBE, ERR, "failed to load because an " | |
4096 | "unsupported SFP+ module type was detected.\n"); | |
9a799d71 | 4097 | goto err_hw_init; |
c4900be0 DS |
4098 | } else if (err) { |
4099 | goto err_hw_init; | |
4100 | } | |
9a799d71 AK |
4101 | |
4102 | /* setup the private structure */ | |
4103 | err = ixgbe_sw_init(adapter); | |
4104 | if (err) | |
4105 | goto err_sw_init; | |
4106 | ||
c44ade9e JB |
4107 | /* reset_hw fills in the perm_addr as well */ |
4108 | err = hw->mac.ops.reset_hw(hw); | |
4109 | if (err) { | |
4110 | dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err); | |
4111 | goto err_sw_init; | |
4112 | } | |
4113 | ||
9a799d71 | 4114 | netdev->features = NETIF_F_SG | |
b4617240 PW |
4115 | NETIF_F_IP_CSUM | |
4116 | NETIF_F_HW_VLAN_TX | | |
4117 | NETIF_F_HW_VLAN_RX | | |
4118 | NETIF_F_HW_VLAN_FILTER; | |
9a799d71 | 4119 | |
e9990a9c | 4120 | netdev->features |= NETIF_F_IPV6_CSUM; |
9a799d71 | 4121 | netdev->features |= NETIF_F_TSO; |
9a799d71 | 4122 | netdev->features |= NETIF_F_TSO6; |
78b6f4ce | 4123 | netdev->features |= NETIF_F_GRO; |
ad31c402 JK |
4124 | |
4125 | netdev->vlan_features |= NETIF_F_TSO; | |
4126 | netdev->vlan_features |= NETIF_F_TSO6; | |
22f32b7a | 4127 | netdev->vlan_features |= NETIF_F_IP_CSUM; |
ad31c402 JK |
4128 | netdev->vlan_features |= NETIF_F_SG; |
4129 | ||
2f90b865 AD |
4130 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) |
4131 | adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED; | |
4132 | ||
7a6b6f51 | 4133 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
4134 | netdev->dcbnl_ops = &dcbnl_ops; |
4135 | #endif | |
4136 | ||
9a799d71 AK |
4137 | if (pci_using_dac) |
4138 | netdev->features |= NETIF_F_HIGHDMA; | |
4139 | ||
9a799d71 | 4140 | /* make sure the EEPROM is good */ |
c44ade9e | 4141 | if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) { |
9a799d71 AK |
4142 | dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n"); |
4143 | err = -EIO; | |
4144 | goto err_eeprom; | |
4145 | } | |
4146 | ||
4147 | memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len); | |
4148 | memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len); | |
4149 | ||
c44ade9e JB |
4150 | if (ixgbe_validate_mac_addr(netdev->perm_addr)) { |
4151 | dev_err(&pdev->dev, "invalid MAC address\n"); | |
9a799d71 AK |
4152 | err = -EIO; |
4153 | goto err_eeprom; | |
4154 | } | |
4155 | ||
4156 | init_timer(&adapter->watchdog_timer); | |
4157 | adapter->watchdog_timer.function = &ixgbe_watchdog; | |
4158 | adapter->watchdog_timer.data = (unsigned long)adapter; | |
4159 | ||
4160 | INIT_WORK(&adapter->reset_task, ixgbe_reset_task); | |
cf8280ee | 4161 | INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task); |
9a799d71 | 4162 | |
021230d4 AV |
4163 | err = ixgbe_init_interrupt_scheme(adapter); |
4164 | if (err) | |
4165 | goto err_sw_init; | |
9a799d71 AK |
4166 | |
4167 | /* print bus type/speed/width info */ | |
4168 | pci_read_config_word(pdev, IXGBE_PCI_LINK_STATUS, &link_status); | |
4169 | link_speed = link_status & IXGBE_PCI_LINK_SPEED; | |
4170 | link_width = link_status & IXGBE_PCI_LINK_WIDTH; | |
7c510e4b | 4171 | dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n", |
b4617240 PW |
4172 | ((link_speed == IXGBE_PCI_LINK_SPEED_5000) ? "5.0Gb/s" : |
4173 | (link_speed == IXGBE_PCI_LINK_SPEED_2500) ? "2.5Gb/s" : | |
4174 | "Unknown"), | |
4175 | ((link_width == IXGBE_PCI_LINK_WIDTH_8) ? "Width x8" : | |
4176 | (link_width == IXGBE_PCI_LINK_WIDTH_4) ? "Width x4" : | |
4177 | (link_width == IXGBE_PCI_LINK_WIDTH_2) ? "Width x2" : | |
4178 | (link_width == IXGBE_PCI_LINK_WIDTH_1) ? "Width x1" : | |
4179 | "Unknown"), | |
7c510e4b | 4180 | netdev->dev_addr); |
c44ade9e | 4181 | ixgbe_read_pba_num_generic(hw, &part_num); |
9a799d71 | 4182 | dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n", |
b4617240 PW |
4183 | hw->mac.type, hw->phy.type, |
4184 | (part_num >> 8), (part_num & 0xff)); | |
9a799d71 | 4185 | |
0c254d86 AK |
4186 | if (link_width <= IXGBE_PCI_LINK_WIDTH_4) { |
4187 | dev_warn(&pdev->dev, "PCI-Express bandwidth available for " | |
b4617240 PW |
4188 | "this card is not sufficient for optimal " |
4189 | "performance.\n"); | |
0c254d86 | 4190 | dev_warn(&pdev->dev, "For optimal performance a x8 " |
b4617240 | 4191 | "PCI-Express slot is required.\n"); |
0c254d86 AK |
4192 | } |
4193 | ||
9a799d71 | 4194 | /* reset the hardware with the new settings */ |
c44ade9e JB |
4195 | hw->mac.ops.start_hw(hw); |
4196 | ||
4197 | /* link_config depends on start_hw being called at least once */ | |
4198 | err = ixgbe_link_config(hw); | |
4199 | if (err) { | |
4200 | dev_err(&pdev->dev, "setup_link_speed FAILED %d\n", err); | |
4201 | goto err_register; | |
4202 | } | |
9a799d71 AK |
4203 | |
4204 | netif_carrier_off(netdev); | |
9a799d71 AK |
4205 | |
4206 | strcpy(netdev->name, "eth%d"); | |
4207 | err = register_netdev(netdev); | |
4208 | if (err) | |
4209 | goto err_register; | |
4210 | ||
5dd2d332 | 4211 | #ifdef CONFIG_IXGBE_DCA |
652f093f | 4212 | if (dca_add_requester(&pdev->dev) == 0) { |
bd0362dd JC |
4213 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; |
4214 | /* always use CB2 mode, difference is masked | |
4215 | * in the CB driver */ | |
4216 | IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2); | |
4217 | ixgbe_setup_dca(adapter); | |
4218 | } | |
4219 | #endif | |
9a799d71 AK |
4220 | |
4221 | dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n"); | |
4222 | cards_found++; | |
4223 | return 0; | |
4224 | ||
4225 | err_register: | |
5eba3699 | 4226 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
4227 | err_hw_init: |
4228 | err_sw_init: | |
021230d4 | 4229 | ixgbe_reset_interrupt_capability(adapter); |
9a799d71 | 4230 | err_eeprom: |
c4900be0 DS |
4231 | clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); |
4232 | del_timer_sync(&adapter->sfp_timer); | |
4233 | cancel_work_sync(&adapter->sfp_task); | |
9a799d71 AK |
4234 | iounmap(hw->hw_addr); |
4235 | err_ioremap: | |
4236 | free_netdev(netdev); | |
4237 | err_alloc_etherdev: | |
4238 | pci_release_regions(pdev); | |
4239 | err_pci_reg: | |
4240 | err_dma: | |
4241 | pci_disable_device(pdev); | |
4242 | return err; | |
4243 | } | |
4244 | ||
4245 | /** | |
4246 | * ixgbe_remove - Device Removal Routine | |
4247 | * @pdev: PCI device information struct | |
4248 | * | |
4249 | * ixgbe_remove is called by the PCI subsystem to alert the driver | |
4250 | * that it should release a PCI device. The could be caused by a | |
4251 | * Hot-Plug event, or because the driver is going to be removed from | |
4252 | * memory. | |
4253 | **/ | |
4254 | static void __devexit ixgbe_remove(struct pci_dev *pdev) | |
4255 | { | |
4256 | struct net_device *netdev = pci_get_drvdata(pdev); | |
4257 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6fabd715 | 4258 | int err; |
9a799d71 AK |
4259 | |
4260 | set_bit(__IXGBE_DOWN, &adapter->state); | |
c4900be0 DS |
4261 | /* clear the module not found bit to make sure the worker won't |
4262 | * reschedule | |
4263 | */ | |
4264 | clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); | |
9a799d71 AK |
4265 | del_timer_sync(&adapter->watchdog_timer); |
4266 | ||
c4900be0 DS |
4267 | del_timer_sync(&adapter->sfp_timer); |
4268 | cancel_work_sync(&adapter->watchdog_task); | |
4269 | cancel_work_sync(&adapter->sfp_task); | |
9a799d71 AK |
4270 | flush_scheduled_work(); |
4271 | ||
5dd2d332 | 4272 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
4273 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { |
4274 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
4275 | dca_remove_requester(&pdev->dev); | |
4276 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); | |
4277 | } | |
4278 | ||
4279 | #endif | |
c4900be0 DS |
4280 | if (netdev->reg_state == NETREG_REGISTERED) |
4281 | unregister_netdev(netdev); | |
9a799d71 | 4282 | |
021230d4 | 4283 | ixgbe_reset_interrupt_capability(adapter); |
5eba3699 | 4284 | |
021230d4 | 4285 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
4286 | |
4287 | iounmap(adapter->hw.hw_addr); | |
4288 | pci_release_regions(pdev); | |
4289 | ||
021230d4 AV |
4290 | DPRINTK(PROBE, INFO, "complete\n"); |
4291 | kfree(adapter->tx_ring); | |
4292 | kfree(adapter->rx_ring); | |
4293 | ||
9a799d71 AK |
4294 | free_netdev(netdev); |
4295 | ||
6fabd715 PWJ |
4296 | err = pci_disable_pcie_error_reporting(pdev); |
4297 | if (err) | |
4298 | dev_err(&pdev->dev, | |
4299 | "pci_disable_pcie_error_reporting failed 0x%x\n", err); | |
4300 | ||
9a799d71 AK |
4301 | pci_disable_device(pdev); |
4302 | } | |
4303 | ||
4304 | /** | |
4305 | * ixgbe_io_error_detected - called when PCI error is detected | |
4306 | * @pdev: Pointer to PCI device | |
4307 | * @state: The current pci connection state | |
4308 | * | |
4309 | * This function is called after a PCI bus error affecting | |
4310 | * this device has been detected. | |
4311 | */ | |
4312 | static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev, | |
b4617240 | 4313 | pci_channel_state_t state) |
9a799d71 AK |
4314 | { |
4315 | struct net_device *netdev = pci_get_drvdata(pdev); | |
454d7c9b | 4316 | struct ixgbe_adapter *adapter = netdev_priv(netdev); |
9a799d71 AK |
4317 | |
4318 | netif_device_detach(netdev); | |
4319 | ||
4320 | if (netif_running(netdev)) | |
4321 | ixgbe_down(adapter); | |
4322 | pci_disable_device(pdev); | |
4323 | ||
b4617240 | 4324 | /* Request a slot reset. */ |
9a799d71 AK |
4325 | return PCI_ERS_RESULT_NEED_RESET; |
4326 | } | |
4327 | ||
4328 | /** | |
4329 | * ixgbe_io_slot_reset - called after the pci bus has been reset. | |
4330 | * @pdev: Pointer to PCI device | |
4331 | * | |
4332 | * Restart the card from scratch, as if from a cold-boot. | |
4333 | */ | |
4334 | static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev) | |
4335 | { | |
4336 | struct net_device *netdev = pci_get_drvdata(pdev); | |
454d7c9b | 4337 | struct ixgbe_adapter *adapter = netdev_priv(netdev); |
6fabd715 PWJ |
4338 | pci_ers_result_t result; |
4339 | int err; | |
9a799d71 AK |
4340 | |
4341 | if (pci_enable_device(pdev)) { | |
4342 | DPRINTK(PROBE, ERR, | |
b4617240 | 4343 | "Cannot re-enable PCI device after reset.\n"); |
6fabd715 PWJ |
4344 | result = PCI_ERS_RESULT_DISCONNECT; |
4345 | } else { | |
4346 | pci_set_master(pdev); | |
4347 | pci_restore_state(pdev); | |
9a799d71 | 4348 | |
6fabd715 PWJ |
4349 | pci_enable_wake(pdev, PCI_D3hot, 0); |
4350 | pci_enable_wake(pdev, PCI_D3cold, 0); | |
9a799d71 | 4351 | |
6fabd715 PWJ |
4352 | ixgbe_reset(adapter); |
4353 | ||
4354 | result = PCI_ERS_RESULT_RECOVERED; | |
4355 | } | |
4356 | ||
4357 | err = pci_cleanup_aer_uncorrect_error_status(pdev); | |
4358 | if (err) { | |
4359 | dev_err(&pdev->dev, | |
4360 | "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err); | |
4361 | /* non-fatal, continue */ | |
4362 | } | |
9a799d71 | 4363 | |
6fabd715 | 4364 | return result; |
9a799d71 AK |
4365 | } |
4366 | ||
4367 | /** | |
4368 | * ixgbe_io_resume - called when traffic can start flowing again. | |
4369 | * @pdev: Pointer to PCI device | |
4370 | * | |
4371 | * This callback is called when the error recovery driver tells us that | |
4372 | * its OK to resume normal operation. | |
4373 | */ | |
4374 | static void ixgbe_io_resume(struct pci_dev *pdev) | |
4375 | { | |
4376 | struct net_device *netdev = pci_get_drvdata(pdev); | |
454d7c9b | 4377 | struct ixgbe_adapter *adapter = netdev_priv(netdev); |
9a799d71 AK |
4378 | |
4379 | if (netif_running(netdev)) { | |
4380 | if (ixgbe_up(adapter)) { | |
4381 | DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n"); | |
4382 | return; | |
4383 | } | |
4384 | } | |
4385 | ||
4386 | netif_device_attach(netdev); | |
9a799d71 AK |
4387 | } |
4388 | ||
4389 | static struct pci_error_handlers ixgbe_err_handler = { | |
4390 | .error_detected = ixgbe_io_error_detected, | |
4391 | .slot_reset = ixgbe_io_slot_reset, | |
4392 | .resume = ixgbe_io_resume, | |
4393 | }; | |
4394 | ||
4395 | static struct pci_driver ixgbe_driver = { | |
4396 | .name = ixgbe_driver_name, | |
4397 | .id_table = ixgbe_pci_tbl, | |
4398 | .probe = ixgbe_probe, | |
4399 | .remove = __devexit_p(ixgbe_remove), | |
4400 | #ifdef CONFIG_PM | |
4401 | .suspend = ixgbe_suspend, | |
4402 | .resume = ixgbe_resume, | |
4403 | #endif | |
4404 | .shutdown = ixgbe_shutdown, | |
4405 | .err_handler = &ixgbe_err_handler | |
4406 | }; | |
4407 | ||
4408 | /** | |
4409 | * ixgbe_init_module - Driver Registration Routine | |
4410 | * | |
4411 | * ixgbe_init_module is the first routine called when the driver is | |
4412 | * loaded. All it does is register with the PCI subsystem. | |
4413 | **/ | |
4414 | static int __init ixgbe_init_module(void) | |
4415 | { | |
4416 | int ret; | |
4417 | printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name, | |
4418 | ixgbe_driver_string, ixgbe_driver_version); | |
4419 | ||
4420 | printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright); | |
4421 | ||
5dd2d332 | 4422 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 4423 | dca_register_notify(&dca_notifier); |
bd0362dd | 4424 | #endif |
5dd2d332 | 4425 | |
9a799d71 AK |
4426 | ret = pci_register_driver(&ixgbe_driver); |
4427 | return ret; | |
4428 | } | |
b4617240 | 4429 | |
9a799d71 AK |
4430 | module_init(ixgbe_init_module); |
4431 | ||
4432 | /** | |
4433 | * ixgbe_exit_module - Driver Exit Cleanup Routine | |
4434 | * | |
4435 | * ixgbe_exit_module is called just before the driver is removed | |
4436 | * from memory. | |
4437 | **/ | |
4438 | static void __exit ixgbe_exit_module(void) | |
4439 | { | |
5dd2d332 | 4440 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
4441 | dca_unregister_notify(&dca_notifier); |
4442 | #endif | |
9a799d71 AK |
4443 | pci_unregister_driver(&ixgbe_driver); |
4444 | } | |
bd0362dd | 4445 | |
5dd2d332 | 4446 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 4447 | static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event, |
b4617240 | 4448 | void *p) |
bd0362dd JC |
4449 | { |
4450 | int ret_val; | |
4451 | ||
4452 | ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event, | |
b4617240 | 4453 | __ixgbe_notify_dca); |
bd0362dd JC |
4454 | |
4455 | return ret_val ? NOTIFY_BAD : NOTIFY_DONE; | |
4456 | } | |
5dd2d332 | 4457 | #endif /* CONFIG_IXGBE_DCA */ |
bd0362dd | 4458 | |
9a799d71 AK |
4459 | module_exit(ixgbe_exit_module); |
4460 | ||
4461 | /* ixgbe_main.c */ |