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9a799d71 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
3efac5a0 | 4 | Copyright(c) 1999 - 2009 Intel Corporation. |
9a799d71 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
9a799d71 AK |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #include <linux/types.h> | |
29 | #include <linux/module.h> | |
30 | #include <linux/pci.h> | |
31 | #include <linux/netdevice.h> | |
32 | #include <linux/vmalloc.h> | |
33 | #include <linux/string.h> | |
34 | #include <linux/in.h> | |
35 | #include <linux/ip.h> | |
36 | #include <linux/tcp.h> | |
60127865 | 37 | #include <linux/pkt_sched.h> |
9a799d71 AK |
38 | #include <linux/ipv6.h> |
39 | #include <net/checksum.h> | |
40 | #include <net/ip6_checksum.h> | |
41 | #include <linux/ethtool.h> | |
42 | #include <linux/if_vlan.h> | |
eacd73f7 | 43 | #include <scsi/fc/fc_fcoe.h> |
9a799d71 AK |
44 | |
45 | #include "ixgbe.h" | |
46 | #include "ixgbe_common.h" | |
ee5f784a | 47 | #include "ixgbe_dcb_82599.h" |
9a799d71 AK |
48 | |
49 | char ixgbe_driver_name[] = "ixgbe"; | |
9c8eb720 | 50 | static const char ixgbe_driver_string[] = |
b4617240 | 51 | "Intel(R) 10 Gigabit PCI Express Network Driver"; |
9a799d71 | 52 | |
e0f4daff | 53 | #define DRV_VERSION "2.0.44-k2" |
9c8eb720 | 54 | const char ixgbe_driver_version[] = DRV_VERSION; |
3efac5a0 | 55 | static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation."; |
9a799d71 AK |
56 | |
57 | static const struct ixgbe_info *ixgbe_info_tbl[] = { | |
b4617240 | 58 | [board_82598] = &ixgbe_82598_info, |
e8e26350 | 59 | [board_82599] = &ixgbe_82599_info, |
9a799d71 AK |
60 | }; |
61 | ||
62 | /* ixgbe_pci_tbl - PCI Device ID Table | |
63 | * | |
64 | * Wildcard entries (PCI_ANY_ID) should come last | |
65 | * Last entry must be all 0s | |
66 | * | |
67 | * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, | |
68 | * Class, Class Mask, private data (not used) } | |
69 | */ | |
70 | static struct pci_device_id ixgbe_pci_tbl[] = { | |
1e336d0f DS |
71 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), |
72 | board_82598 }, | |
9a799d71 | 73 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), |
3957d63d | 74 | board_82598 }, |
9a799d71 | 75 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), |
3957d63d | 76 | board_82598 }, |
0befdb3e JB |
77 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), |
78 | board_82598 }, | |
3845bec0 PWJ |
79 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), |
80 | board_82598 }, | |
9a799d71 | 81 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), |
3957d63d | 82 | board_82598 }, |
8d792cd9 JB |
83 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), |
84 | board_82598 }, | |
c4900be0 DS |
85 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), |
86 | board_82598 }, | |
87 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), | |
88 | board_82598 }, | |
b95f5fcb JB |
89 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), |
90 | board_82598 }, | |
c4900be0 DS |
91 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), |
92 | board_82598 }, | |
2f21bdd3 DS |
93 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), |
94 | board_82598 }, | |
e8e26350 PW |
95 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), |
96 | board_82599 }, | |
1fcf03e6 PWJ |
97 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), |
98 | board_82599 }, | |
e8e26350 PW |
99 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), |
100 | board_82599 }, | |
38ad1c8e DS |
101 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), |
102 | board_82599 }, | |
dbfec662 DS |
103 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), |
104 | board_82599 }, | |
8911184f PWJ |
105 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), |
106 | board_82599 }, | |
312eb931 DS |
107 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), |
108 | board_82599 }, | |
9a799d71 AK |
109 | |
110 | /* required last entry */ | |
111 | {0, } | |
112 | }; | |
113 | MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl); | |
114 | ||
5dd2d332 | 115 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 116 | static int ixgbe_notify_dca(struct notifier_block *, unsigned long event, |
b4617240 | 117 | void *p); |
bd0362dd JC |
118 | static struct notifier_block dca_notifier = { |
119 | .notifier_call = ixgbe_notify_dca, | |
120 | .next = NULL, | |
121 | .priority = 0 | |
122 | }; | |
123 | #endif | |
124 | ||
9a799d71 AK |
125 | MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); |
126 | MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver"); | |
127 | MODULE_LICENSE("GPL"); | |
128 | MODULE_VERSION(DRV_VERSION); | |
129 | ||
130 | #define DEFAULT_DEBUG_LEVEL_SHIFT 3 | |
131 | ||
5eba3699 AV |
132 | static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter) |
133 | { | |
134 | u32 ctrl_ext; | |
135 | ||
136 | /* Let firmware take over control of h/w */ | |
137 | ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); | |
138 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, | |
b4617240 | 139 | ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD); |
5eba3699 AV |
140 | } |
141 | ||
142 | static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter) | |
143 | { | |
144 | u32 ctrl_ext; | |
145 | ||
146 | /* Let firmware know the driver has taken over */ | |
147 | ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); | |
148 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, | |
b4617240 | 149 | ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD); |
5eba3699 | 150 | } |
9a799d71 | 151 | |
e8e26350 PW |
152 | /* |
153 | * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors | |
154 | * @adapter: pointer to adapter struct | |
155 | * @direction: 0 for Rx, 1 for Tx, -1 for other causes | |
156 | * @queue: queue to map the corresponding interrupt to | |
157 | * @msix_vector: the vector to map to the corresponding queue | |
158 | * | |
159 | */ | |
160 | static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction, | |
161 | u8 queue, u8 msix_vector) | |
9a799d71 AK |
162 | { |
163 | u32 ivar, index; | |
e8e26350 PW |
164 | struct ixgbe_hw *hw = &adapter->hw; |
165 | switch (hw->mac.type) { | |
166 | case ixgbe_mac_82598EB: | |
167 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
168 | if (direction == -1) | |
169 | direction = 0; | |
170 | index = (((direction * 64) + queue) >> 2) & 0x1F; | |
171 | ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); | |
172 | ivar &= ~(0xFF << (8 * (queue & 0x3))); | |
173 | ivar |= (msix_vector << (8 * (queue & 0x3))); | |
174 | IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar); | |
175 | break; | |
176 | case ixgbe_mac_82599EB: | |
177 | if (direction == -1) { | |
178 | /* other causes */ | |
179 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
180 | index = ((queue & 1) * 8); | |
181 | ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC); | |
182 | ivar &= ~(0xFF << index); | |
183 | ivar |= (msix_vector << index); | |
184 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar); | |
185 | break; | |
186 | } else { | |
187 | /* tx or rx causes */ | |
188 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
189 | index = ((16 * (queue & 1)) + (8 * direction)); | |
190 | ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); | |
191 | ivar &= ~(0xFF << index); | |
192 | ivar |= (msix_vector << index); | |
193 | IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar); | |
194 | break; | |
195 | } | |
196 | default: | |
197 | break; | |
198 | } | |
9a799d71 AK |
199 | } |
200 | ||
fe49f04a AD |
201 | static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter, |
202 | u64 qmask) | |
203 | { | |
204 | u32 mask; | |
205 | ||
206 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { | |
207 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); | |
208 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); | |
209 | } else { | |
210 | mask = (qmask & 0xFFFFFFFF); | |
211 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask); | |
212 | mask = (qmask >> 32); | |
213 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask); | |
214 | } | |
215 | } | |
216 | ||
9a799d71 | 217 | static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter, |
b4617240 PW |
218 | struct ixgbe_tx_buffer |
219 | *tx_buffer_info) | |
9a799d71 | 220 | { |
e5a43549 AD |
221 | if (tx_buffer_info->dma) { |
222 | if (tx_buffer_info->mapped_as_page) | |
223 | pci_unmap_page(adapter->pdev, | |
224 | tx_buffer_info->dma, | |
225 | tx_buffer_info->length, | |
226 | PCI_DMA_TODEVICE); | |
227 | else | |
228 | pci_unmap_single(adapter->pdev, | |
229 | tx_buffer_info->dma, | |
230 | tx_buffer_info->length, | |
231 | PCI_DMA_TODEVICE); | |
232 | tx_buffer_info->dma = 0; | |
233 | } | |
9a799d71 AK |
234 | if (tx_buffer_info->skb) { |
235 | dev_kfree_skb_any(tx_buffer_info->skb); | |
236 | tx_buffer_info->skb = NULL; | |
237 | } | |
44df32c5 | 238 | tx_buffer_info->time_stamp = 0; |
9a799d71 AK |
239 | /* tx_buffer_info must be completely set up in the transmit path */ |
240 | } | |
241 | ||
26f23d82 YZ |
242 | /** |
243 | * ixgbe_tx_is_paused - check if the tx ring is paused | |
244 | * @adapter: the ixgbe adapter | |
245 | * @tx_ring: the corresponding tx_ring | |
246 | * | |
247 | * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the | |
248 | * corresponding TC of this tx_ring when checking TFCS. | |
249 | * | |
250 | * Returns : true if paused | |
251 | */ | |
252 | static inline bool ixgbe_tx_is_paused(struct ixgbe_adapter *adapter, | |
253 | struct ixgbe_ring *tx_ring) | |
254 | { | |
26f23d82 YZ |
255 | u32 txoff = IXGBE_TFCS_TXOFF; |
256 | ||
257 | #ifdef CONFIG_IXGBE_DCB | |
258 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
30b76832 | 259 | int tc; |
26f23d82 YZ |
260 | int reg_idx = tx_ring->reg_idx; |
261 | int dcb_i = adapter->ring_feature[RING_F_DCB].indices; | |
262 | ||
263 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { | |
264 | tc = reg_idx >> 2; | |
265 | txoff = IXGBE_TFCS_TXOFF0; | |
266 | } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { | |
267 | tc = 0; | |
268 | txoff = IXGBE_TFCS_TXOFF; | |
269 | if (dcb_i == 8) { | |
270 | /* TC0, TC1 */ | |
271 | tc = reg_idx >> 5; | |
272 | if (tc == 2) /* TC2, TC3 */ | |
273 | tc += (reg_idx - 64) >> 4; | |
274 | else if (tc == 3) /* TC4, TC5, TC6, TC7 */ | |
275 | tc += 1 + ((reg_idx - 96) >> 3); | |
276 | } else if (dcb_i == 4) { | |
277 | /* TC0, TC1 */ | |
278 | tc = reg_idx >> 6; | |
279 | if (tc == 1) { | |
280 | tc += (reg_idx - 64) >> 5; | |
281 | if (tc == 2) /* TC2, TC3 */ | |
282 | tc += (reg_idx - 96) >> 4; | |
283 | } | |
284 | } | |
285 | } | |
286 | txoff <<= tc; | |
287 | } | |
288 | #endif | |
289 | return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff; | |
290 | } | |
291 | ||
9a799d71 | 292 | static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter, |
b4617240 PW |
293 | struct ixgbe_ring *tx_ring, |
294 | unsigned int eop) | |
9a799d71 | 295 | { |
e01c31a5 | 296 | struct ixgbe_hw *hw = &adapter->hw; |
e01c31a5 | 297 | |
9a799d71 | 298 | /* Detect a transmit hang in hardware, this serializes the |
e01c31a5 | 299 | * check with the clearing of time_stamp and movement of eop */ |
9a799d71 | 300 | adapter->detect_tx_hung = false; |
44df32c5 | 301 | if (tx_ring->tx_buffer_info[eop].time_stamp && |
9a799d71 | 302 | time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) && |
26f23d82 | 303 | !ixgbe_tx_is_paused(adapter, tx_ring)) { |
9a799d71 | 304 | /* detected Tx unit hang */ |
e01c31a5 JB |
305 | union ixgbe_adv_tx_desc *tx_desc; |
306 | tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop); | |
9a799d71 | 307 | DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n" |
e01c31a5 JB |
308 | " Tx Queue <%d>\n" |
309 | " TDH, TDT <%x>, <%x>\n" | |
9a799d71 AK |
310 | " next_to_use <%x>\n" |
311 | " next_to_clean <%x>\n" | |
312 | "tx_buffer_info[next_to_clean]\n" | |
313 | " time_stamp <%lx>\n" | |
e01c31a5 JB |
314 | " jiffies <%lx>\n", |
315 | tx_ring->queue_index, | |
44df32c5 AD |
316 | IXGBE_READ_REG(hw, tx_ring->head), |
317 | IXGBE_READ_REG(hw, tx_ring->tail), | |
e01c31a5 JB |
318 | tx_ring->next_to_use, eop, |
319 | tx_ring->tx_buffer_info[eop].time_stamp, jiffies); | |
9a799d71 AK |
320 | return true; |
321 | } | |
322 | ||
323 | return false; | |
324 | } | |
325 | ||
b4617240 PW |
326 | #define IXGBE_MAX_TXD_PWR 14 |
327 | #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR) | |
e092be60 AV |
328 | |
329 | /* Tx Descriptors needed, worst case */ | |
330 | #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \ | |
331 | (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0)) | |
332 | #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \ | |
b4617240 | 333 | MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */ |
e092be60 | 334 | |
e01c31a5 JB |
335 | static void ixgbe_tx_timeout(struct net_device *netdev); |
336 | ||
9a799d71 AK |
337 | /** |
338 | * ixgbe_clean_tx_irq - Reclaim resources after transmit completes | |
fe49f04a | 339 | * @q_vector: structure containing interrupt and ring information |
e01c31a5 | 340 | * @tx_ring: tx ring to clean |
9a799d71 | 341 | **/ |
fe49f04a | 342 | static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector, |
e01c31a5 | 343 | struct ixgbe_ring *tx_ring) |
9a799d71 | 344 | { |
fe49f04a | 345 | struct ixgbe_adapter *adapter = q_vector->adapter; |
e01c31a5 | 346 | struct net_device *netdev = adapter->netdev; |
12207e49 PWJ |
347 | union ixgbe_adv_tx_desc *tx_desc, *eop_desc; |
348 | struct ixgbe_tx_buffer *tx_buffer_info; | |
349 | unsigned int i, eop, count = 0; | |
e01c31a5 | 350 | unsigned int total_bytes = 0, total_packets = 0; |
9a799d71 AK |
351 | |
352 | i = tx_ring->next_to_clean; | |
12207e49 PWJ |
353 | eop = tx_ring->tx_buffer_info[i].next_to_watch; |
354 | eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop); | |
355 | ||
356 | while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) && | |
9a1a69ad | 357 | (count < tx_ring->work_limit)) { |
12207e49 PWJ |
358 | bool cleaned = false; |
359 | for ( ; !cleaned; count++) { | |
360 | struct sk_buff *skb; | |
9a799d71 AK |
361 | tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i); |
362 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
12207e49 | 363 | cleaned = (i == eop); |
e01c31a5 | 364 | skb = tx_buffer_info->skb; |
9a799d71 | 365 | |
12207e49 | 366 | if (cleaned && skb) { |
e092be60 | 367 | unsigned int segs, bytecount; |
3d8fd385 | 368 | unsigned int hlen = skb_headlen(skb); |
e01c31a5 JB |
369 | |
370 | /* gso_segs is currently only valid for tcp */ | |
e092be60 | 371 | segs = skb_shinfo(skb)->gso_segs ?: 1; |
3d8fd385 YZ |
372 | #ifdef IXGBE_FCOE |
373 | /* adjust for FCoE Sequence Offload */ | |
374 | if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) | |
375 | && (skb->protocol == htons(ETH_P_FCOE)) && | |
376 | skb_is_gso(skb)) { | |
377 | hlen = skb_transport_offset(skb) + | |
378 | sizeof(struct fc_frame_header) + | |
379 | sizeof(struct fcoe_crc_eof); | |
380 | segs = DIV_ROUND_UP(skb->len - hlen, | |
381 | skb_shinfo(skb)->gso_size); | |
382 | } | |
383 | #endif /* IXGBE_FCOE */ | |
e092be60 | 384 | /* multiply data chunks by size of headers */ |
3d8fd385 | 385 | bytecount = ((segs - 1) * hlen) + skb->len; |
e01c31a5 JB |
386 | total_packets += segs; |
387 | total_bytes += bytecount; | |
e092be60 | 388 | } |
e01c31a5 | 389 | |
9a799d71 | 390 | ixgbe_unmap_and_free_tx_resource(adapter, |
e01c31a5 | 391 | tx_buffer_info); |
9a799d71 | 392 | |
12207e49 PWJ |
393 | tx_desc->wb.status = 0; |
394 | ||
9a799d71 AK |
395 | i++; |
396 | if (i == tx_ring->count) | |
397 | i = 0; | |
e01c31a5 | 398 | } |
12207e49 PWJ |
399 | |
400 | eop = tx_ring->tx_buffer_info[i].next_to_watch; | |
401 | eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop); | |
402 | } | |
403 | ||
9a799d71 AK |
404 | tx_ring->next_to_clean = i; |
405 | ||
e092be60 | 406 | #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) |
e01c31a5 JB |
407 | if (unlikely(count && netif_carrier_ok(netdev) && |
408 | (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) { | |
e092be60 AV |
409 | /* Make sure that anybody stopping the queue after this |
410 | * sees the new next_to_clean. | |
411 | */ | |
412 | smp_mb(); | |
30eba97a AV |
413 | if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) && |
414 | !test_bit(__IXGBE_DOWN, &adapter->state)) { | |
415 | netif_wake_subqueue(netdev, tx_ring->queue_index); | |
7ca3bc58 | 416 | ++tx_ring->restart_queue; |
30eba97a | 417 | } |
e092be60 | 418 | } |
9a799d71 | 419 | |
e01c31a5 JB |
420 | if (adapter->detect_tx_hung) { |
421 | if (ixgbe_check_tx_hang(adapter, tx_ring, i)) { | |
422 | /* schedule immediate reset if we believe we hung */ | |
423 | DPRINTK(PROBE, INFO, | |
424 | "tx hang %d detected, resetting adapter\n", | |
425 | adapter->tx_timeout_count + 1); | |
426 | ixgbe_tx_timeout(adapter->netdev); | |
427 | } | |
428 | } | |
9a799d71 | 429 | |
e01c31a5 | 430 | /* re-arm the interrupt */ |
fe49f04a AD |
431 | if (count >= tx_ring->work_limit) |
432 | ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx)); | |
9a799d71 | 433 | |
e01c31a5 JB |
434 | tx_ring->total_bytes += total_bytes; |
435 | tx_ring->total_packets += total_packets; | |
e01c31a5 | 436 | tx_ring->stats.packets += total_packets; |
12207e49 | 437 | tx_ring->stats.bytes += total_bytes; |
9a1a69ad | 438 | return (count < tx_ring->work_limit); |
9a799d71 AK |
439 | } |
440 | ||
5dd2d332 | 441 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 442 | static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter, |
b4617240 | 443 | struct ixgbe_ring *rx_ring) |
bd0362dd JC |
444 | { |
445 | u32 rxctrl; | |
446 | int cpu = get_cpu(); | |
3a581073 | 447 | int q = rx_ring - adapter->rx_ring; |
bd0362dd | 448 | |
3a581073 | 449 | if (rx_ring->cpu != cpu) { |
bd0362dd | 450 | rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q)); |
e8e26350 PW |
451 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
452 | rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK; | |
453 | rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu); | |
454 | } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { | |
455 | rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599; | |
456 | rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) << | |
457 | IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599); | |
458 | } | |
bd0362dd JC |
459 | rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN; |
460 | rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN; | |
15005a32 DS |
461 | rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN); |
462 | rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN | | |
e8e26350 | 463 | IXGBE_DCA_RXCTRL_DESC_HSRO_EN); |
bd0362dd | 464 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl); |
3a581073 | 465 | rx_ring->cpu = cpu; |
bd0362dd JC |
466 | } |
467 | put_cpu(); | |
468 | } | |
469 | ||
470 | static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter, | |
b4617240 | 471 | struct ixgbe_ring *tx_ring) |
bd0362dd JC |
472 | { |
473 | u32 txctrl; | |
474 | int cpu = get_cpu(); | |
3a581073 | 475 | int q = tx_ring - adapter->tx_ring; |
ee5f784a | 476 | struct ixgbe_hw *hw = &adapter->hw; |
bd0362dd | 477 | |
3a581073 | 478 | if (tx_ring->cpu != cpu) { |
e8e26350 | 479 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
ee5f784a | 480 | txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q)); |
e8e26350 PW |
481 | txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK; |
482 | txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu); | |
ee5f784a DS |
483 | txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN; |
484 | IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl); | |
e8e26350 | 485 | } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { |
ee5f784a | 486 | txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q)); |
e8e26350 PW |
487 | txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599; |
488 | txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) << | |
ee5f784a DS |
489 | IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599); |
490 | txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN; | |
491 | IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl); | |
e8e26350 | 492 | } |
3a581073 | 493 | tx_ring->cpu = cpu; |
bd0362dd JC |
494 | } |
495 | put_cpu(); | |
496 | } | |
497 | ||
498 | static void ixgbe_setup_dca(struct ixgbe_adapter *adapter) | |
499 | { | |
500 | int i; | |
501 | ||
502 | if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED)) | |
503 | return; | |
504 | ||
e35ec126 AD |
505 | /* always use CB2 mode, difference is masked in the CB driver */ |
506 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2); | |
507 | ||
bd0362dd JC |
508 | for (i = 0; i < adapter->num_tx_queues; i++) { |
509 | adapter->tx_ring[i].cpu = -1; | |
510 | ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]); | |
511 | } | |
512 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
513 | adapter->rx_ring[i].cpu = -1; | |
514 | ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]); | |
515 | } | |
516 | } | |
517 | ||
518 | static int __ixgbe_notify_dca(struct device *dev, void *data) | |
519 | { | |
520 | struct net_device *netdev = dev_get_drvdata(dev); | |
521 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
522 | unsigned long event = *(unsigned long *)data; | |
523 | ||
524 | switch (event) { | |
525 | case DCA_PROVIDER_ADD: | |
96b0e0f6 JB |
526 | /* if we're already enabled, don't do it again */ |
527 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
528 | break; | |
652f093f | 529 | if (dca_add_requester(dev) == 0) { |
96b0e0f6 | 530 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; |
bd0362dd JC |
531 | ixgbe_setup_dca(adapter); |
532 | break; | |
533 | } | |
534 | /* Fall Through since DCA is disabled. */ | |
535 | case DCA_PROVIDER_REMOVE: | |
536 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { | |
537 | dca_remove_requester(dev); | |
538 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
539 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); | |
540 | } | |
541 | break; | |
542 | } | |
543 | ||
652f093f | 544 | return 0; |
bd0362dd JC |
545 | } |
546 | ||
5dd2d332 | 547 | #endif /* CONFIG_IXGBE_DCA */ |
9a799d71 AK |
548 | /** |
549 | * ixgbe_receive_skb - Send a completed packet up the stack | |
550 | * @adapter: board private structure | |
551 | * @skb: packet to send up | |
177db6ff MC |
552 | * @status: hardware indication of status of receive |
553 | * @rx_ring: rx descriptor ring (for a specific queue) to setup | |
554 | * @rx_desc: rx descriptor | |
9a799d71 | 555 | **/ |
78b6f4ce | 556 | static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector, |
b4617240 | 557 | struct sk_buff *skb, u8 status, |
fdaff1ce | 558 | struct ixgbe_ring *ring, |
177db6ff | 559 | union ixgbe_adv_rx_desc *rx_desc) |
9a799d71 | 560 | { |
78b6f4ce HX |
561 | struct ixgbe_adapter *adapter = q_vector->adapter; |
562 | struct napi_struct *napi = &q_vector->napi; | |
177db6ff MC |
563 | bool is_vlan = (status & IXGBE_RXD_STAT_VP); |
564 | u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan); | |
9a799d71 | 565 | |
fdaff1ce | 566 | skb_record_rx_queue(skb, ring->queue_index); |
182ff8df | 567 | if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) { |
8a62babf | 568 | if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK)) |
78b6f4ce | 569 | vlan_gro_receive(napi, adapter->vlgrp, tag, skb); |
9a799d71 | 570 | else |
78b6f4ce | 571 | napi_gro_receive(napi, skb); |
177db6ff | 572 | } else { |
8a62babf | 573 | if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK)) |
182ff8df AD |
574 | vlan_hwaccel_rx(skb, adapter->vlgrp, tag); |
575 | else | |
576 | netif_rx(skb); | |
9a799d71 AK |
577 | } |
578 | } | |
579 | ||
e59bd25d AV |
580 | /** |
581 | * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum | |
582 | * @adapter: address of board private structure | |
583 | * @status_err: hardware indication of status of receive | |
584 | * @skb: skb currently being received and modified | |
585 | **/ | |
9a799d71 | 586 | static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter, |
8bae1b2b DS |
587 | union ixgbe_adv_rx_desc *rx_desc, |
588 | struct sk_buff *skb) | |
9a799d71 | 589 | { |
8bae1b2b DS |
590 | u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error); |
591 | ||
9a799d71 AK |
592 | skb->ip_summed = CHECKSUM_NONE; |
593 | ||
712744be JB |
594 | /* Rx csum disabled */ |
595 | if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED)) | |
9a799d71 | 596 | return; |
e59bd25d AV |
597 | |
598 | /* if IP and error */ | |
599 | if ((status_err & IXGBE_RXD_STAT_IPCS) && | |
600 | (status_err & IXGBE_RXDADV_ERR_IPE)) { | |
9a799d71 AK |
601 | adapter->hw_csum_rx_error++; |
602 | return; | |
603 | } | |
e59bd25d AV |
604 | |
605 | if (!(status_err & IXGBE_RXD_STAT_L4CS)) | |
606 | return; | |
607 | ||
608 | if (status_err & IXGBE_RXDADV_ERR_TCPE) { | |
8bae1b2b DS |
609 | u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; |
610 | ||
611 | /* | |
612 | * 82599 errata, UDP frames with a 0 checksum can be marked as | |
613 | * checksum errors. | |
614 | */ | |
615 | if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) && | |
616 | (adapter->hw.mac.type == ixgbe_mac_82599EB)) | |
617 | return; | |
618 | ||
e59bd25d AV |
619 | adapter->hw_csum_rx_error++; |
620 | return; | |
621 | } | |
622 | ||
9a799d71 | 623 | /* It must be a TCP or UDP packet with a valid checksum */ |
e59bd25d | 624 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
9a799d71 AK |
625 | } |
626 | ||
e8e26350 PW |
627 | static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw, |
628 | struct ixgbe_ring *rx_ring, u32 val) | |
629 | { | |
630 | /* | |
631 | * Force memory writes to complete before letting h/w | |
632 | * know there are new descriptors to fetch. (Only | |
633 | * applicable for weak-ordered memory model archs, | |
634 | * such as IA-64). | |
635 | */ | |
636 | wmb(); | |
637 | IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val); | |
638 | } | |
639 | ||
9a799d71 AK |
640 | /** |
641 | * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split | |
642 | * @adapter: address of board private structure | |
643 | **/ | |
644 | static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter, | |
7c6e0a43 JB |
645 | struct ixgbe_ring *rx_ring, |
646 | int cleaned_count) | |
9a799d71 | 647 | { |
9a799d71 AK |
648 | struct pci_dev *pdev = adapter->pdev; |
649 | union ixgbe_adv_rx_desc *rx_desc; | |
3a581073 | 650 | struct ixgbe_rx_buffer *bi; |
9a799d71 | 651 | unsigned int i; |
9a799d71 AK |
652 | |
653 | i = rx_ring->next_to_use; | |
3a581073 | 654 | bi = &rx_ring->rx_buffer_info[i]; |
9a799d71 AK |
655 | |
656 | while (cleaned_count--) { | |
657 | rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i); | |
658 | ||
762f4c57 | 659 | if (!bi->page_dma && |
6e455b89 | 660 | (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) { |
3a581073 | 661 | if (!bi->page) { |
762f4c57 JB |
662 | bi->page = alloc_page(GFP_ATOMIC); |
663 | if (!bi->page) { | |
664 | adapter->alloc_rx_page_failed++; | |
665 | goto no_buffers; | |
666 | } | |
667 | bi->page_offset = 0; | |
668 | } else { | |
669 | /* use a half page if we're re-using */ | |
670 | bi->page_offset ^= (PAGE_SIZE / 2); | |
9a799d71 | 671 | } |
762f4c57 JB |
672 | |
673 | bi->page_dma = pci_map_page(pdev, bi->page, | |
674 | bi->page_offset, | |
675 | (PAGE_SIZE / 2), | |
676 | PCI_DMA_FROMDEVICE); | |
9a799d71 AK |
677 | } |
678 | ||
3a581073 | 679 | if (!bi->skb) { |
5ecc3614 | 680 | struct sk_buff *skb; |
7ca3bc58 JB |
681 | /* netdev_alloc_skb reserves 32 bytes up front!! */ |
682 | uint bufsz = rx_ring->rx_buf_len + SMP_CACHE_BYTES; | |
683 | skb = netdev_alloc_skb(adapter->netdev, bufsz); | |
9a799d71 AK |
684 | |
685 | if (!skb) { | |
686 | adapter->alloc_rx_buff_failed++; | |
687 | goto no_buffers; | |
688 | } | |
689 | ||
7ca3bc58 JB |
690 | /* advance the data pointer to the next cache line */ |
691 | skb_reserve(skb, (PTR_ALIGN(skb->data, SMP_CACHE_BYTES) | |
692 | - skb->data)); | |
693 | ||
3a581073 | 694 | bi->skb = skb; |
4f57ca6e JB |
695 | bi->dma = pci_map_single(pdev, skb->data, |
696 | rx_ring->rx_buf_len, | |
3a581073 | 697 | PCI_DMA_FROMDEVICE); |
9a799d71 AK |
698 | } |
699 | /* Refresh the desc even if buffer_addrs didn't change because | |
700 | * each write-back erases this info. */ | |
6e455b89 | 701 | if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) { |
3a581073 JB |
702 | rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma); |
703 | rx_desc->read.hdr_addr = cpu_to_le64(bi->dma); | |
9a799d71 | 704 | } else { |
3a581073 | 705 | rx_desc->read.pkt_addr = cpu_to_le64(bi->dma); |
9a799d71 AK |
706 | } |
707 | ||
708 | i++; | |
709 | if (i == rx_ring->count) | |
710 | i = 0; | |
3a581073 | 711 | bi = &rx_ring->rx_buffer_info[i]; |
9a799d71 | 712 | } |
7c6e0a43 | 713 | |
9a799d71 AK |
714 | no_buffers: |
715 | if (rx_ring->next_to_use != i) { | |
716 | rx_ring->next_to_use = i; | |
717 | if (i-- == 0) | |
718 | i = (rx_ring->count - 1); | |
719 | ||
e8e26350 | 720 | ixgbe_release_rx_desc(&adapter->hw, rx_ring, i); |
9a799d71 AK |
721 | } |
722 | } | |
723 | ||
7c6e0a43 JB |
724 | static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc) |
725 | { | |
726 | return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info; | |
727 | } | |
728 | ||
729 | static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc) | |
730 | { | |
731 | return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; | |
732 | } | |
733 | ||
f8212f97 AD |
734 | static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc) |
735 | { | |
736 | return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) & | |
737 | IXGBE_RXDADV_RSCCNT_MASK) >> | |
738 | IXGBE_RXDADV_RSCCNT_SHIFT; | |
739 | } | |
740 | ||
741 | /** | |
742 | * ixgbe_transform_rsc_queue - change rsc queue into a full packet | |
743 | * @skb: pointer to the last skb in the rsc queue | |
94b982b2 | 744 | * @count: pointer to number of packets coalesced in this context |
f8212f97 AD |
745 | * |
746 | * This function changes a queue full of hw rsc buffers into a completed | |
747 | * packet. It uses the ->prev pointers to find the first packet and then | |
748 | * turns it into the frag list owner. | |
749 | **/ | |
94b982b2 MC |
750 | static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb, |
751 | u64 *count) | |
f8212f97 AD |
752 | { |
753 | unsigned int frag_list_size = 0; | |
754 | ||
755 | while (skb->prev) { | |
756 | struct sk_buff *prev = skb->prev; | |
757 | frag_list_size += skb->len; | |
758 | skb->prev = NULL; | |
759 | skb = prev; | |
94b982b2 | 760 | *count += 1; |
f8212f97 AD |
761 | } |
762 | ||
763 | skb_shinfo(skb)->frag_list = skb->next; | |
764 | skb->next = NULL; | |
765 | skb->len += frag_list_size; | |
766 | skb->data_len += frag_list_size; | |
767 | skb->truesize += frag_list_size; | |
768 | return skb; | |
769 | } | |
770 | ||
78b6f4ce | 771 | static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, |
b4617240 PW |
772 | struct ixgbe_ring *rx_ring, |
773 | int *work_done, int work_to_do) | |
9a799d71 | 774 | { |
78b6f4ce | 775 | struct ixgbe_adapter *adapter = q_vector->adapter; |
2d86f139 | 776 | struct net_device *netdev = adapter->netdev; |
9a799d71 AK |
777 | struct pci_dev *pdev = adapter->pdev; |
778 | union ixgbe_adv_rx_desc *rx_desc, *next_rxd; | |
779 | struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer; | |
780 | struct sk_buff *skb; | |
f8212f97 | 781 | unsigned int i, rsc_count = 0; |
7c6e0a43 | 782 | u32 len, staterr; |
177db6ff MC |
783 | u16 hdr_info; |
784 | bool cleaned = false; | |
9a799d71 | 785 | int cleaned_count = 0; |
d2f4fbe2 | 786 | unsigned int total_rx_bytes = 0, total_rx_packets = 0; |
3d8fd385 YZ |
787 | #ifdef IXGBE_FCOE |
788 | int ddp_bytes = 0; | |
789 | #endif /* IXGBE_FCOE */ | |
9a799d71 AK |
790 | |
791 | i = rx_ring->next_to_clean; | |
9a799d71 AK |
792 | rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i); |
793 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
794 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; | |
9a799d71 AK |
795 | |
796 | while (staterr & IXGBE_RXD_STAT_DD) { | |
7c6e0a43 | 797 | u32 upper_len = 0; |
9a799d71 AK |
798 | if (*work_done >= work_to_do) |
799 | break; | |
800 | (*work_done)++; | |
801 | ||
6e455b89 | 802 | if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) { |
7c6e0a43 JB |
803 | hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc)); |
804 | len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >> | |
762f4c57 | 805 | IXGBE_RXDADV_HDRBUFLEN_SHIFT; |
9a799d71 AK |
806 | if (len > IXGBE_RX_HDR_SIZE) |
807 | len = IXGBE_RX_HDR_SIZE; | |
808 | upper_len = le16_to_cpu(rx_desc->wb.upper.length); | |
7c6e0a43 | 809 | } else { |
9a799d71 | 810 | len = le16_to_cpu(rx_desc->wb.upper.length); |
7c6e0a43 | 811 | } |
9a799d71 AK |
812 | |
813 | cleaned = true; | |
814 | skb = rx_buffer_info->skb; | |
7ca3bc58 | 815 | prefetch(skb->data); |
9a799d71 AK |
816 | rx_buffer_info->skb = NULL; |
817 | ||
21fa4e66 | 818 | if (rx_buffer_info->dma) { |
9a799d71 | 819 | pci_unmap_single(pdev, rx_buffer_info->dma, |
5ecc3614 | 820 | rx_ring->rx_buf_len, |
b4617240 | 821 | PCI_DMA_FROMDEVICE); |
4f57ca6e | 822 | rx_buffer_info->dma = 0; |
9a799d71 AK |
823 | skb_put(skb, len); |
824 | } | |
825 | ||
826 | if (upper_len) { | |
827 | pci_unmap_page(pdev, rx_buffer_info->page_dma, | |
762f4c57 | 828 | PAGE_SIZE / 2, PCI_DMA_FROMDEVICE); |
9a799d71 AK |
829 | rx_buffer_info->page_dma = 0; |
830 | skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, | |
762f4c57 JB |
831 | rx_buffer_info->page, |
832 | rx_buffer_info->page_offset, | |
833 | upper_len); | |
834 | ||
835 | if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) || | |
836 | (page_count(rx_buffer_info->page) != 1)) | |
837 | rx_buffer_info->page = NULL; | |
838 | else | |
839 | get_page(rx_buffer_info->page); | |
9a799d71 AK |
840 | |
841 | skb->len += upper_len; | |
842 | skb->data_len += upper_len; | |
843 | skb->truesize += upper_len; | |
844 | } | |
845 | ||
846 | i++; | |
847 | if (i == rx_ring->count) | |
848 | i = 0; | |
9a799d71 AK |
849 | |
850 | next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i); | |
851 | prefetch(next_rxd); | |
9a799d71 | 852 | cleaned_count++; |
f8212f97 | 853 | |
0c19d6af | 854 | if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) |
f8212f97 AD |
855 | rsc_count = ixgbe_get_rsc_count(rx_desc); |
856 | ||
857 | if (rsc_count) { | |
858 | u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >> | |
859 | IXGBE_RXDADV_NEXTP_SHIFT; | |
860 | next_buffer = &rx_ring->rx_buffer_info[nextp]; | |
f8212f97 AD |
861 | } else { |
862 | next_buffer = &rx_ring->rx_buffer_info[i]; | |
863 | } | |
864 | ||
9a799d71 | 865 | if (staterr & IXGBE_RXD_STAT_EOP) { |
f8212f97 | 866 | if (skb->prev) |
94b982b2 MC |
867 | skb = ixgbe_transform_rsc_queue(skb, &(rx_ring->rsc_count)); |
868 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { | |
869 | if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) | |
870 | rx_ring->rsc_count += skb_shinfo(skb)->nr_frags; | |
871 | else | |
872 | rx_ring->rsc_count++; | |
873 | rx_ring->rsc_flush++; | |
874 | } | |
9a799d71 AK |
875 | rx_ring->stats.packets++; |
876 | rx_ring->stats.bytes += skb->len; | |
877 | } else { | |
6e455b89 | 878 | if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) { |
f8212f97 AD |
879 | rx_buffer_info->skb = next_buffer->skb; |
880 | rx_buffer_info->dma = next_buffer->dma; | |
881 | next_buffer->skb = skb; | |
882 | next_buffer->dma = 0; | |
883 | } else { | |
884 | skb->next = next_buffer->skb; | |
885 | skb->next->prev = skb; | |
886 | } | |
7ca3bc58 | 887 | rx_ring->non_eop_descs++; |
9a799d71 AK |
888 | goto next_desc; |
889 | } | |
890 | ||
891 | if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) { | |
892 | dev_kfree_skb_irq(skb); | |
893 | goto next_desc; | |
894 | } | |
895 | ||
8bae1b2b | 896 | ixgbe_rx_checksum(adapter, rx_desc, skb); |
d2f4fbe2 AV |
897 | |
898 | /* probably a little skewed due to removing CRC */ | |
899 | total_rx_bytes += skb->len; | |
900 | total_rx_packets++; | |
901 | ||
74ce8dd2 | 902 | skb->protocol = eth_type_trans(skb, adapter->netdev); |
332d4a7d YZ |
903 | #ifdef IXGBE_FCOE |
904 | /* if ddp, not passing to ULD unless for FCP_RSP or error */ | |
3d8fd385 YZ |
905 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { |
906 | ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb); | |
907 | if (!ddp_bytes) | |
332d4a7d | 908 | goto next_desc; |
3d8fd385 | 909 | } |
332d4a7d | 910 | #endif /* IXGBE_FCOE */ |
fdaff1ce | 911 | ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc); |
9a799d71 AK |
912 | |
913 | next_desc: | |
914 | rx_desc->wb.upper.status_error = 0; | |
915 | ||
916 | /* return some buffers to hardware, one at a time is too slow */ | |
917 | if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) { | |
918 | ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count); | |
919 | cleaned_count = 0; | |
920 | } | |
921 | ||
922 | /* use prefetched values */ | |
923 | rx_desc = next_rxd; | |
f8212f97 | 924 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; |
9a799d71 AK |
925 | |
926 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
177db6ff MC |
927 | } |
928 | ||
9a799d71 AK |
929 | rx_ring->next_to_clean = i; |
930 | cleaned_count = IXGBE_DESC_UNUSED(rx_ring); | |
931 | ||
932 | if (cleaned_count) | |
933 | ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count); | |
934 | ||
3d8fd385 YZ |
935 | #ifdef IXGBE_FCOE |
936 | /* include DDPed FCoE data */ | |
937 | if (ddp_bytes > 0) { | |
938 | unsigned int mss; | |
939 | ||
940 | mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) - | |
941 | sizeof(struct fc_frame_header) - | |
942 | sizeof(struct fcoe_crc_eof); | |
943 | if (mss > 512) | |
944 | mss &= ~511; | |
945 | total_rx_bytes += ddp_bytes; | |
946 | total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss); | |
947 | } | |
948 | #endif /* IXGBE_FCOE */ | |
949 | ||
f494e8fa AV |
950 | rx_ring->total_packets += total_rx_packets; |
951 | rx_ring->total_bytes += total_rx_bytes; | |
2d86f139 AK |
952 | netdev->stats.rx_bytes += total_rx_bytes; |
953 | netdev->stats.rx_packets += total_rx_packets; | |
f494e8fa | 954 | |
9a799d71 AK |
955 | return cleaned; |
956 | } | |
957 | ||
021230d4 | 958 | static int ixgbe_clean_rxonly(struct napi_struct *, int); |
9a799d71 AK |
959 | /** |
960 | * ixgbe_configure_msix - Configure MSI-X hardware | |
961 | * @adapter: board private structure | |
962 | * | |
963 | * ixgbe_configure_msix sets up the hardware to properly generate MSI-X | |
964 | * interrupts. | |
965 | **/ | |
966 | static void ixgbe_configure_msix(struct ixgbe_adapter *adapter) | |
967 | { | |
021230d4 AV |
968 | struct ixgbe_q_vector *q_vector; |
969 | int i, j, q_vectors, v_idx, r_idx; | |
970 | u32 mask; | |
9a799d71 | 971 | |
021230d4 | 972 | q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; |
9a799d71 | 973 | |
4df10466 JB |
974 | /* |
975 | * Populate the IVAR table and set the ITR values to the | |
021230d4 AV |
976 | * corresponding register. |
977 | */ | |
978 | for (v_idx = 0; v_idx < q_vectors; v_idx++) { | |
7a921c93 | 979 | q_vector = adapter->q_vector[v_idx]; |
021230d4 AV |
980 | /* XXX for_each_bit(...) */ |
981 | r_idx = find_first_bit(q_vector->rxr_idx, | |
b4617240 | 982 | adapter->num_rx_queues); |
021230d4 AV |
983 | |
984 | for (i = 0; i < q_vector->rxr_count; i++) { | |
985 | j = adapter->rx_ring[r_idx].reg_idx; | |
e8e26350 | 986 | ixgbe_set_ivar(adapter, 0, j, v_idx); |
021230d4 | 987 | r_idx = find_next_bit(q_vector->rxr_idx, |
b4617240 PW |
988 | adapter->num_rx_queues, |
989 | r_idx + 1); | |
021230d4 AV |
990 | } |
991 | r_idx = find_first_bit(q_vector->txr_idx, | |
b4617240 | 992 | adapter->num_tx_queues); |
021230d4 AV |
993 | |
994 | for (i = 0; i < q_vector->txr_count; i++) { | |
995 | j = adapter->tx_ring[r_idx].reg_idx; | |
e8e26350 | 996 | ixgbe_set_ivar(adapter, 1, j, v_idx); |
021230d4 | 997 | r_idx = find_next_bit(q_vector->txr_idx, |
b4617240 PW |
998 | adapter->num_tx_queues, |
999 | r_idx + 1); | |
021230d4 AV |
1000 | } |
1001 | ||
021230d4 | 1002 | if (q_vector->txr_count && !q_vector->rxr_count) |
f7554a2b NS |
1003 | /* tx only */ |
1004 | q_vector->eitr = adapter->tx_eitr_param; | |
509ee935 | 1005 | else if (q_vector->rxr_count) |
f7554a2b NS |
1006 | /* rx or mixed */ |
1007 | q_vector->eitr = adapter->rx_eitr_param; | |
021230d4 | 1008 | |
fe49f04a | 1009 | ixgbe_write_eitr(q_vector); |
9a799d71 AK |
1010 | } |
1011 | ||
e8e26350 PW |
1012 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) |
1013 | ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX, | |
1014 | v_idx); | |
1015 | else if (adapter->hw.mac.type == ixgbe_mac_82599EB) | |
1016 | ixgbe_set_ivar(adapter, -1, 1, v_idx); | |
021230d4 AV |
1017 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950); |
1018 | ||
41fb9248 | 1019 | /* set up to autoclear timer, and the vectors */ |
021230d4 | 1020 | mask = IXGBE_EIMS_ENABLE_MASK; |
41fb9248 | 1021 | mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC); |
021230d4 | 1022 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask); |
9a799d71 AK |
1023 | } |
1024 | ||
f494e8fa AV |
1025 | enum latency_range { |
1026 | lowest_latency = 0, | |
1027 | low_latency = 1, | |
1028 | bulk_latency = 2, | |
1029 | latency_invalid = 255 | |
1030 | }; | |
1031 | ||
1032 | /** | |
1033 | * ixgbe_update_itr - update the dynamic ITR value based on statistics | |
1034 | * @adapter: pointer to adapter | |
1035 | * @eitr: eitr setting (ints per sec) to give last timeslice | |
1036 | * @itr_setting: current throttle rate in ints/second | |
1037 | * @packets: the number of packets during this measurement interval | |
1038 | * @bytes: the number of bytes during this measurement interval | |
1039 | * | |
1040 | * Stores a new ITR value based on packets and byte | |
1041 | * counts during the last interrupt. The advantage of per interrupt | |
1042 | * computation is faster updates and more accurate ITR for the current | |
1043 | * traffic pattern. Constants in this function were computed | |
1044 | * based on theoretical maximum wire speed and thresholds were set based | |
1045 | * on testing data as well as attempting to minimize response time | |
1046 | * while increasing bulk throughput. | |
1047 | * this functionality is controlled by the InterruptThrottleRate module | |
1048 | * parameter (see ixgbe_param.c) | |
1049 | **/ | |
1050 | static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter, | |
b4617240 PW |
1051 | u32 eitr, u8 itr_setting, |
1052 | int packets, int bytes) | |
f494e8fa AV |
1053 | { |
1054 | unsigned int retval = itr_setting; | |
1055 | u32 timepassed_us; | |
1056 | u64 bytes_perint; | |
1057 | ||
1058 | if (packets == 0) | |
1059 | goto update_itr_done; | |
1060 | ||
1061 | ||
1062 | /* simple throttlerate management | |
1063 | * 0-20MB/s lowest (100000 ints/s) | |
1064 | * 20-100MB/s low (20000 ints/s) | |
1065 | * 100-1249MB/s bulk (8000 ints/s) | |
1066 | */ | |
1067 | /* what was last interrupt timeslice? */ | |
1068 | timepassed_us = 1000000/eitr; | |
1069 | bytes_perint = bytes / timepassed_us; /* bytes/usec */ | |
1070 | ||
1071 | switch (itr_setting) { | |
1072 | case lowest_latency: | |
1073 | if (bytes_perint > adapter->eitr_low) | |
1074 | retval = low_latency; | |
1075 | break; | |
1076 | case low_latency: | |
1077 | if (bytes_perint > adapter->eitr_high) | |
1078 | retval = bulk_latency; | |
1079 | else if (bytes_perint <= adapter->eitr_low) | |
1080 | retval = lowest_latency; | |
1081 | break; | |
1082 | case bulk_latency: | |
1083 | if (bytes_perint <= adapter->eitr_high) | |
1084 | retval = low_latency; | |
1085 | break; | |
1086 | } | |
1087 | ||
1088 | update_itr_done: | |
1089 | return retval; | |
1090 | } | |
1091 | ||
509ee935 JB |
1092 | /** |
1093 | * ixgbe_write_eitr - write EITR register in hardware specific way | |
fe49f04a | 1094 | * @q_vector: structure containing interrupt and ring information |
509ee935 JB |
1095 | * |
1096 | * This function is made to be called by ethtool and by the driver | |
1097 | * when it needs to update EITR registers at runtime. Hardware | |
1098 | * specific quirks/differences are taken care of here. | |
1099 | */ | |
fe49f04a | 1100 | void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector) |
509ee935 | 1101 | { |
fe49f04a | 1102 | struct ixgbe_adapter *adapter = q_vector->adapter; |
509ee935 | 1103 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a AD |
1104 | int v_idx = q_vector->v_idx; |
1105 | u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr); | |
1106 | ||
509ee935 JB |
1107 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
1108 | /* must write high and low 16 bits to reset counter */ | |
1109 | itr_reg |= (itr_reg << 16); | |
1110 | } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { | |
1111 | /* | |
1112 | * set the WDIS bit to not clear the timer bits and cause an | |
1113 | * immediate assertion of the interrupt | |
1114 | */ | |
1115 | itr_reg |= IXGBE_EITR_CNT_WDIS; | |
1116 | } | |
1117 | IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg); | |
1118 | } | |
1119 | ||
f494e8fa AV |
1120 | static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector) |
1121 | { | |
1122 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
f494e8fa AV |
1123 | u32 new_itr; |
1124 | u8 current_itr, ret_itr; | |
fe49f04a | 1125 | int i, r_idx; |
f494e8fa AV |
1126 | struct ixgbe_ring *rx_ring, *tx_ring; |
1127 | ||
1128 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
1129 | for (i = 0; i < q_vector->txr_count; i++) { | |
1130 | tx_ring = &(adapter->tx_ring[r_idx]); | |
1131 | ret_itr = ixgbe_update_itr(adapter, q_vector->eitr, | |
b4617240 PW |
1132 | q_vector->tx_itr, |
1133 | tx_ring->total_packets, | |
1134 | tx_ring->total_bytes); | |
f494e8fa AV |
1135 | /* if the result for this queue would decrease interrupt |
1136 | * rate for this vector then use that result */ | |
30efa5a3 | 1137 | q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ? |
b4617240 | 1138 | q_vector->tx_itr - 1 : ret_itr); |
f494e8fa | 1139 | r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, |
b4617240 | 1140 | r_idx + 1); |
f494e8fa AV |
1141 | } |
1142 | ||
1143 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
1144 | for (i = 0; i < q_vector->rxr_count; i++) { | |
1145 | rx_ring = &(adapter->rx_ring[r_idx]); | |
1146 | ret_itr = ixgbe_update_itr(adapter, q_vector->eitr, | |
b4617240 PW |
1147 | q_vector->rx_itr, |
1148 | rx_ring->total_packets, | |
1149 | rx_ring->total_bytes); | |
f494e8fa AV |
1150 | /* if the result for this queue would decrease interrupt |
1151 | * rate for this vector then use that result */ | |
30efa5a3 | 1152 | q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ? |
b4617240 | 1153 | q_vector->rx_itr - 1 : ret_itr); |
f494e8fa | 1154 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, |
b4617240 | 1155 | r_idx + 1); |
f494e8fa AV |
1156 | } |
1157 | ||
30efa5a3 | 1158 | current_itr = max(q_vector->rx_itr, q_vector->tx_itr); |
f494e8fa AV |
1159 | |
1160 | switch (current_itr) { | |
1161 | /* counts and packets in update_itr are dependent on these numbers */ | |
1162 | case lowest_latency: | |
1163 | new_itr = 100000; | |
1164 | break; | |
1165 | case low_latency: | |
1166 | new_itr = 20000; /* aka hwitr = ~200 */ | |
1167 | break; | |
1168 | case bulk_latency: | |
1169 | default: | |
1170 | new_itr = 8000; | |
1171 | break; | |
1172 | } | |
1173 | ||
1174 | if (new_itr != q_vector->eitr) { | |
fe49f04a AD |
1175 | /* do an exponential smoothing */ |
1176 | new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100); | |
509ee935 JB |
1177 | |
1178 | /* save the algorithm value here, not the smoothed one */ | |
1179 | q_vector->eitr = new_itr; | |
fe49f04a AD |
1180 | |
1181 | ixgbe_write_eitr(q_vector); | |
f494e8fa AV |
1182 | } |
1183 | ||
1184 | return; | |
1185 | } | |
1186 | ||
0befdb3e JB |
1187 | static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr) |
1188 | { | |
1189 | struct ixgbe_hw *hw = &adapter->hw; | |
1190 | ||
1191 | if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) && | |
1192 | (eicr & IXGBE_EICR_GPI_SDP1)) { | |
1193 | DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n"); | |
1194 | /* write to clear the interrupt */ | |
1195 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); | |
1196 | } | |
1197 | } | |
cf8280ee | 1198 | |
e8e26350 PW |
1199 | static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr) |
1200 | { | |
1201 | struct ixgbe_hw *hw = &adapter->hw; | |
1202 | ||
1203 | if (eicr & IXGBE_EICR_GPI_SDP1) { | |
1204 | /* Clear the interrupt */ | |
1205 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); | |
1206 | schedule_work(&adapter->multispeed_fiber_task); | |
1207 | } else if (eicr & IXGBE_EICR_GPI_SDP2) { | |
1208 | /* Clear the interrupt */ | |
1209 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2); | |
1210 | schedule_work(&adapter->sfp_config_module_task); | |
1211 | } else { | |
1212 | /* Interrupt isn't for us... */ | |
1213 | return; | |
1214 | } | |
1215 | } | |
1216 | ||
cf8280ee JB |
1217 | static void ixgbe_check_lsc(struct ixgbe_adapter *adapter) |
1218 | { | |
1219 | struct ixgbe_hw *hw = &adapter->hw; | |
1220 | ||
1221 | adapter->lsc_int++; | |
1222 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; | |
1223 | adapter->link_check_timeout = jiffies; | |
1224 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { | |
1225 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); | |
8a0717f3 | 1226 | IXGBE_WRITE_FLUSH(hw); |
cf8280ee JB |
1227 | schedule_work(&adapter->watchdog_task); |
1228 | } | |
1229 | } | |
1230 | ||
9a799d71 AK |
1231 | static irqreturn_t ixgbe_msix_lsc(int irq, void *data) |
1232 | { | |
1233 | struct net_device *netdev = data; | |
1234 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
1235 | struct ixgbe_hw *hw = &adapter->hw; | |
54037505 DS |
1236 | u32 eicr; |
1237 | ||
1238 | /* | |
1239 | * Workaround for Silicon errata. Use clear-by-write instead | |
1240 | * of clear-by-read. Reading with EICS will return the | |
1241 | * interrupt causes without clearing, which later be done | |
1242 | * with the write to EICR. | |
1243 | */ | |
1244 | eicr = IXGBE_READ_REG(hw, IXGBE_EICS); | |
1245 | IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); | |
9a799d71 | 1246 | |
cf8280ee JB |
1247 | if (eicr & IXGBE_EICR_LSC) |
1248 | ixgbe_check_lsc(adapter); | |
d4f80882 | 1249 | |
e8e26350 PW |
1250 | if (hw->mac.type == ixgbe_mac_82598EB) |
1251 | ixgbe_check_fan_failure(adapter, eicr); | |
0befdb3e | 1252 | |
c4cf55e5 | 1253 | if (hw->mac.type == ixgbe_mac_82599EB) { |
e8e26350 | 1254 | ixgbe_check_sfp_event(adapter, eicr); |
c4cf55e5 PWJ |
1255 | |
1256 | /* Handle Flow Director Full threshold interrupt */ | |
1257 | if (eicr & IXGBE_EICR_FLOW_DIR) { | |
1258 | int i; | |
1259 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR); | |
1260 | /* Disable transmits before FDIR Re-initialization */ | |
1261 | netif_tx_stop_all_queues(netdev); | |
1262 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
1263 | struct ixgbe_ring *tx_ring = | |
1264 | &adapter->tx_ring[i]; | |
1265 | if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE, | |
1266 | &tx_ring->reinit_state)) | |
1267 | schedule_work(&adapter->fdir_reinit_task); | |
1268 | } | |
1269 | } | |
1270 | } | |
d4f80882 AV |
1271 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
1272 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER); | |
9a799d71 AK |
1273 | |
1274 | return IRQ_HANDLED; | |
1275 | } | |
1276 | ||
fe49f04a AD |
1277 | static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter, |
1278 | u64 qmask) | |
1279 | { | |
1280 | u32 mask; | |
1281 | ||
1282 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { | |
1283 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); | |
1284 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); | |
1285 | } else { | |
1286 | mask = (qmask & 0xFFFFFFFF); | |
1287 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask); | |
1288 | mask = (qmask >> 32); | |
1289 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask); | |
1290 | } | |
1291 | /* skip the flush */ | |
1292 | } | |
1293 | ||
1294 | static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter, | |
1295 | u64 qmask) | |
1296 | { | |
1297 | u32 mask; | |
1298 | ||
1299 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { | |
1300 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); | |
1301 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask); | |
1302 | } else { | |
1303 | mask = (qmask & 0xFFFFFFFF); | |
1304 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask); | |
1305 | mask = (qmask >> 32); | |
1306 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask); | |
1307 | } | |
1308 | /* skip the flush */ | |
1309 | } | |
1310 | ||
9a799d71 AK |
1311 | static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data) |
1312 | { | |
021230d4 AV |
1313 | struct ixgbe_q_vector *q_vector = data; |
1314 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
3a581073 | 1315 | struct ixgbe_ring *tx_ring; |
021230d4 AV |
1316 | int i, r_idx; |
1317 | ||
1318 | if (!q_vector->txr_count) | |
1319 | return IRQ_HANDLED; | |
1320 | ||
1321 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
1322 | for (i = 0; i < q_vector->txr_count; i++) { | |
3a581073 | 1323 | tx_ring = &(adapter->tx_ring[r_idx]); |
3a581073 JB |
1324 | tx_ring->total_bytes = 0; |
1325 | tx_ring->total_packets = 0; | |
021230d4 | 1326 | r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, |
b4617240 | 1327 | r_idx + 1); |
021230d4 | 1328 | } |
9a799d71 | 1329 | |
9b471446 | 1330 | /* EIAM disabled interrupts (on this vector) for us */ |
91281fd3 AD |
1331 | napi_schedule(&q_vector->napi); |
1332 | ||
9a799d71 AK |
1333 | return IRQ_HANDLED; |
1334 | } | |
1335 | ||
021230d4 AV |
1336 | /** |
1337 | * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues) | |
1338 | * @irq: unused | |
1339 | * @data: pointer to our q_vector struct for this interrupt vector | |
1340 | **/ | |
9a799d71 AK |
1341 | static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data) |
1342 | { | |
021230d4 AV |
1343 | struct ixgbe_q_vector *q_vector = data; |
1344 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
3a581073 | 1345 | struct ixgbe_ring *rx_ring; |
021230d4 | 1346 | int r_idx; |
30efa5a3 | 1347 | int i; |
021230d4 AV |
1348 | |
1349 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
30efa5a3 JB |
1350 | for (i = 0; i < q_vector->rxr_count; i++) { |
1351 | rx_ring = &(adapter->rx_ring[r_idx]); | |
1352 | rx_ring->total_bytes = 0; | |
1353 | rx_ring->total_packets = 0; | |
1354 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, | |
1355 | r_idx + 1); | |
1356 | } | |
1357 | ||
021230d4 AV |
1358 | if (!q_vector->rxr_count) |
1359 | return IRQ_HANDLED; | |
1360 | ||
021230d4 | 1361 | /* disable interrupts on this vector only */ |
9b471446 | 1362 | /* EIAM disabled interrupts (on this vector) for us */ |
288379f0 | 1363 | napi_schedule(&q_vector->napi); |
021230d4 AV |
1364 | |
1365 | return IRQ_HANDLED; | |
1366 | } | |
1367 | ||
1368 | static irqreturn_t ixgbe_msix_clean_many(int irq, void *data) | |
1369 | { | |
91281fd3 AD |
1370 | struct ixgbe_q_vector *q_vector = data; |
1371 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
1372 | struct ixgbe_ring *ring; | |
1373 | int r_idx; | |
1374 | int i; | |
1375 | ||
1376 | if (!q_vector->txr_count && !q_vector->rxr_count) | |
1377 | return IRQ_HANDLED; | |
1378 | ||
1379 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
1380 | for (i = 0; i < q_vector->txr_count; i++) { | |
1381 | ring = &(adapter->tx_ring[r_idx]); | |
1382 | ring->total_bytes = 0; | |
1383 | ring->total_packets = 0; | |
1384 | r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, | |
1385 | r_idx + 1); | |
1386 | } | |
1387 | ||
1388 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
1389 | for (i = 0; i < q_vector->rxr_count; i++) { | |
1390 | ring = &(adapter->rx_ring[r_idx]); | |
1391 | ring->total_bytes = 0; | |
1392 | ring->total_packets = 0; | |
1393 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, | |
1394 | r_idx + 1); | |
1395 | } | |
1396 | ||
9b471446 | 1397 | /* EIAM disabled interrupts (on this vector) for us */ |
91281fd3 | 1398 | napi_schedule(&q_vector->napi); |
9a799d71 | 1399 | |
9a799d71 AK |
1400 | return IRQ_HANDLED; |
1401 | } | |
1402 | ||
021230d4 AV |
1403 | /** |
1404 | * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine | |
1405 | * @napi: napi struct with our devices info in it | |
1406 | * @budget: amount of work driver is allowed to do this pass, in packets | |
1407 | * | |
f0848276 JB |
1408 | * This function is optimized for cleaning one queue only on a single |
1409 | * q_vector!!! | |
021230d4 | 1410 | **/ |
9a799d71 AK |
1411 | static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget) |
1412 | { | |
021230d4 | 1413 | struct ixgbe_q_vector *q_vector = |
b4617240 | 1414 | container_of(napi, struct ixgbe_q_vector, napi); |
021230d4 | 1415 | struct ixgbe_adapter *adapter = q_vector->adapter; |
f0848276 | 1416 | struct ixgbe_ring *rx_ring = NULL; |
9a799d71 | 1417 | int work_done = 0; |
021230d4 | 1418 | long r_idx; |
9a799d71 | 1419 | |
021230d4 | 1420 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); |
3a581073 | 1421 | rx_ring = &(adapter->rx_ring[r_idx]); |
5dd2d332 | 1422 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 1423 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) |
3a581073 | 1424 | ixgbe_update_rx_dca(adapter, rx_ring); |
bd0362dd | 1425 | #endif |
9a799d71 | 1426 | |
78b6f4ce | 1427 | ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget); |
9a799d71 | 1428 | |
021230d4 AV |
1429 | /* If all Rx work done, exit the polling mode */ |
1430 | if (work_done < budget) { | |
288379f0 | 1431 | napi_complete(napi); |
f7554a2b | 1432 | if (adapter->rx_itr_setting & 1) |
f494e8fa | 1433 | ixgbe_set_itr_msix(q_vector); |
9a799d71 | 1434 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
fe49f04a AD |
1435 | ixgbe_irq_enable_queues(adapter, |
1436 | ((u64)1 << q_vector->v_idx)); | |
9a799d71 AK |
1437 | } |
1438 | ||
1439 | return work_done; | |
1440 | } | |
1441 | ||
f0848276 | 1442 | /** |
91281fd3 | 1443 | * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine |
f0848276 JB |
1444 | * @napi: napi struct with our devices info in it |
1445 | * @budget: amount of work driver is allowed to do this pass, in packets | |
1446 | * | |
1447 | * This function will clean more than one rx queue associated with a | |
1448 | * q_vector. | |
1449 | **/ | |
91281fd3 | 1450 | static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget) |
f0848276 JB |
1451 | { |
1452 | struct ixgbe_q_vector *q_vector = | |
1453 | container_of(napi, struct ixgbe_q_vector, napi); | |
1454 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
91281fd3 | 1455 | struct ixgbe_ring *ring = NULL; |
f0848276 JB |
1456 | int work_done = 0, i; |
1457 | long r_idx; | |
91281fd3 AD |
1458 | bool tx_clean_complete = true; |
1459 | ||
1460 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
1461 | for (i = 0; i < q_vector->txr_count; i++) { | |
1462 | ring = &(adapter->tx_ring[r_idx]); | |
1463 | #ifdef CONFIG_IXGBE_DCA | |
1464 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
1465 | ixgbe_update_tx_dca(adapter, ring); | |
1466 | #endif | |
1467 | tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring); | |
1468 | r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, | |
1469 | r_idx + 1); | |
1470 | } | |
f0848276 JB |
1471 | |
1472 | /* attempt to distribute budget to each queue fairly, but don't allow | |
1473 | * the budget to go below 1 because we'll exit polling */ | |
1474 | budget /= (q_vector->rxr_count ?: 1); | |
1475 | budget = max(budget, 1); | |
1476 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
1477 | for (i = 0; i < q_vector->rxr_count; i++) { | |
91281fd3 | 1478 | ring = &(adapter->rx_ring[r_idx]); |
5dd2d332 | 1479 | #ifdef CONFIG_IXGBE_DCA |
f0848276 | 1480 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) |
91281fd3 | 1481 | ixgbe_update_rx_dca(adapter, ring); |
f0848276 | 1482 | #endif |
91281fd3 | 1483 | ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget); |
f0848276 JB |
1484 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, |
1485 | r_idx + 1); | |
1486 | } | |
1487 | ||
1488 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
91281fd3 | 1489 | ring = &(adapter->rx_ring[r_idx]); |
f0848276 | 1490 | /* If all Rx work done, exit the polling mode */ |
7f821875 | 1491 | if (work_done < budget) { |
288379f0 | 1492 | napi_complete(napi); |
f7554a2b | 1493 | if (adapter->rx_itr_setting & 1) |
f0848276 JB |
1494 | ixgbe_set_itr_msix(q_vector); |
1495 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
fe49f04a AD |
1496 | ixgbe_irq_enable_queues(adapter, |
1497 | ((u64)1 << q_vector->v_idx)); | |
f0848276 JB |
1498 | return 0; |
1499 | } | |
1500 | ||
1501 | return work_done; | |
1502 | } | |
91281fd3 AD |
1503 | |
1504 | /** | |
1505 | * ixgbe_clean_txonly - msix (aka one shot) tx clean routine | |
1506 | * @napi: napi struct with our devices info in it | |
1507 | * @budget: amount of work driver is allowed to do this pass, in packets | |
1508 | * | |
1509 | * This function is optimized for cleaning one queue only on a single | |
1510 | * q_vector!!! | |
1511 | **/ | |
1512 | static int ixgbe_clean_txonly(struct napi_struct *napi, int budget) | |
1513 | { | |
1514 | struct ixgbe_q_vector *q_vector = | |
1515 | container_of(napi, struct ixgbe_q_vector, napi); | |
1516 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
1517 | struct ixgbe_ring *tx_ring = NULL; | |
1518 | int work_done = 0; | |
1519 | long r_idx; | |
1520 | ||
1521 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
1522 | tx_ring = &(adapter->tx_ring[r_idx]); | |
1523 | #ifdef CONFIG_IXGBE_DCA | |
1524 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
1525 | ixgbe_update_tx_dca(adapter, tx_ring); | |
1526 | #endif | |
1527 | ||
1528 | if (!ixgbe_clean_tx_irq(q_vector, tx_ring)) | |
1529 | work_done = budget; | |
1530 | ||
f7554a2b | 1531 | /* If all Tx work done, exit the polling mode */ |
91281fd3 AD |
1532 | if (work_done < budget) { |
1533 | napi_complete(napi); | |
f7554a2b | 1534 | if (adapter->tx_itr_setting & 1) |
91281fd3 AD |
1535 | ixgbe_set_itr_msix(q_vector); |
1536 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
1537 | ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx)); | |
1538 | } | |
1539 | ||
1540 | return work_done; | |
1541 | } | |
1542 | ||
021230d4 | 1543 | static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx, |
b4617240 | 1544 | int r_idx) |
021230d4 | 1545 | { |
7a921c93 AD |
1546 | struct ixgbe_q_vector *q_vector = a->q_vector[v_idx]; |
1547 | ||
1548 | set_bit(r_idx, q_vector->rxr_idx); | |
1549 | q_vector->rxr_count++; | |
021230d4 AV |
1550 | } |
1551 | ||
1552 | static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx, | |
7a921c93 | 1553 | int t_idx) |
021230d4 | 1554 | { |
7a921c93 AD |
1555 | struct ixgbe_q_vector *q_vector = a->q_vector[v_idx]; |
1556 | ||
1557 | set_bit(t_idx, q_vector->txr_idx); | |
1558 | q_vector->txr_count++; | |
021230d4 AV |
1559 | } |
1560 | ||
9a799d71 | 1561 | /** |
021230d4 AV |
1562 | * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors |
1563 | * @adapter: board private structure to initialize | |
1564 | * @vectors: allotted vector count for descriptor rings | |
9a799d71 | 1565 | * |
021230d4 AV |
1566 | * This function maps descriptor rings to the queue-specific vectors |
1567 | * we were allotted through the MSI-X enabling code. Ideally, we'd have | |
1568 | * one vector per ring/queue, but on a constrained vector budget, we | |
1569 | * group the rings as "efficiently" as possible. You would add new | |
1570 | * mapping configurations in here. | |
9a799d71 | 1571 | **/ |
021230d4 | 1572 | static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter, |
b4617240 | 1573 | int vectors) |
021230d4 AV |
1574 | { |
1575 | int v_start = 0; | |
1576 | int rxr_idx = 0, txr_idx = 0; | |
1577 | int rxr_remaining = adapter->num_rx_queues; | |
1578 | int txr_remaining = adapter->num_tx_queues; | |
1579 | int i, j; | |
1580 | int rqpv, tqpv; | |
1581 | int err = 0; | |
1582 | ||
1583 | /* No mapping required if MSI-X is disabled. */ | |
1584 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
1585 | goto out; | |
9a799d71 | 1586 | |
021230d4 AV |
1587 | /* |
1588 | * The ideal configuration... | |
1589 | * We have enough vectors to map one per queue. | |
1590 | */ | |
1591 | if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) { | |
1592 | for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++) | |
1593 | map_vector_to_rxq(adapter, v_start, rxr_idx); | |
9a799d71 | 1594 | |
021230d4 AV |
1595 | for (; txr_idx < txr_remaining; v_start++, txr_idx++) |
1596 | map_vector_to_txq(adapter, v_start, txr_idx); | |
9a799d71 | 1597 | |
9a799d71 | 1598 | goto out; |
021230d4 | 1599 | } |
9a799d71 | 1600 | |
021230d4 AV |
1601 | /* |
1602 | * If we don't have enough vectors for a 1-to-1 | |
1603 | * mapping, we'll have to group them so there are | |
1604 | * multiple queues per vector. | |
1605 | */ | |
1606 | /* Re-adjusting *qpv takes care of the remainder. */ | |
1607 | for (i = v_start; i < vectors; i++) { | |
1608 | rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i); | |
1609 | for (j = 0; j < rqpv; j++) { | |
1610 | map_vector_to_rxq(adapter, i, rxr_idx); | |
1611 | rxr_idx++; | |
1612 | rxr_remaining--; | |
1613 | } | |
1614 | } | |
1615 | for (i = v_start; i < vectors; i++) { | |
1616 | tqpv = DIV_ROUND_UP(txr_remaining, vectors - i); | |
1617 | for (j = 0; j < tqpv; j++) { | |
1618 | map_vector_to_txq(adapter, i, txr_idx); | |
1619 | txr_idx++; | |
1620 | txr_remaining--; | |
9a799d71 | 1621 | } |
9a799d71 AK |
1622 | } |
1623 | ||
021230d4 AV |
1624 | out: |
1625 | return err; | |
1626 | } | |
1627 | ||
1628 | /** | |
1629 | * ixgbe_request_msix_irqs - Initialize MSI-X interrupts | |
1630 | * @adapter: board private structure | |
1631 | * | |
1632 | * ixgbe_request_msix_irqs allocates MSI-X vectors and requests | |
1633 | * interrupts from the kernel. | |
1634 | **/ | |
1635 | static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter) | |
1636 | { | |
1637 | struct net_device *netdev = adapter->netdev; | |
1638 | irqreturn_t (*handler)(int, void *); | |
1639 | int i, vector, q_vectors, err; | |
cb13fc20 | 1640 | int ri=0, ti=0; |
021230d4 AV |
1641 | |
1642 | /* Decrement for Other and TCP Timer vectors */ | |
1643 | q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
1644 | ||
1645 | /* Map the Tx/Rx rings to the vectors we were allotted. */ | |
1646 | err = ixgbe_map_rings_to_vectors(adapter, q_vectors); | |
1647 | if (err) | |
1648 | goto out; | |
1649 | ||
1650 | #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \ | |
b4617240 PW |
1651 | (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \ |
1652 | &ixgbe_msix_clean_many) | |
021230d4 | 1653 | for (vector = 0; vector < q_vectors; vector++) { |
7a921c93 | 1654 | handler = SET_HANDLER(adapter->q_vector[vector]); |
cb13fc20 RO |
1655 | |
1656 | if(handler == &ixgbe_msix_clean_rx) { | |
1657 | sprintf(adapter->name[vector], "%s-%s-%d", | |
1658 | netdev->name, "rx", ri++); | |
1659 | } | |
1660 | else if(handler == &ixgbe_msix_clean_tx) { | |
1661 | sprintf(adapter->name[vector], "%s-%s-%d", | |
1662 | netdev->name, "tx", ti++); | |
1663 | } | |
1664 | else | |
1665 | sprintf(adapter->name[vector], "%s-%s-%d", | |
1666 | netdev->name, "TxRx", vector); | |
1667 | ||
021230d4 | 1668 | err = request_irq(adapter->msix_entries[vector].vector, |
b4617240 | 1669 | handler, 0, adapter->name[vector], |
7a921c93 | 1670 | adapter->q_vector[vector]); |
9a799d71 AK |
1671 | if (err) { |
1672 | DPRINTK(PROBE, ERR, | |
b4617240 PW |
1673 | "request_irq failed for MSIX interrupt " |
1674 | "Error: %d\n", err); | |
021230d4 | 1675 | goto free_queue_irqs; |
9a799d71 | 1676 | } |
9a799d71 AK |
1677 | } |
1678 | ||
021230d4 AV |
1679 | sprintf(adapter->name[vector], "%s:lsc", netdev->name); |
1680 | err = request_irq(adapter->msix_entries[vector].vector, | |
a0607fd3 | 1681 | ixgbe_msix_lsc, 0, adapter->name[vector], netdev); |
9a799d71 AK |
1682 | if (err) { |
1683 | DPRINTK(PROBE, ERR, | |
1684 | "request_irq for msix_lsc failed: %d\n", err); | |
021230d4 | 1685 | goto free_queue_irqs; |
9a799d71 AK |
1686 | } |
1687 | ||
9a799d71 AK |
1688 | return 0; |
1689 | ||
021230d4 AV |
1690 | free_queue_irqs: |
1691 | for (i = vector - 1; i >= 0; i--) | |
1692 | free_irq(adapter->msix_entries[--vector].vector, | |
7a921c93 | 1693 | adapter->q_vector[i]); |
021230d4 AV |
1694 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; |
1695 | pci_disable_msix(adapter->pdev); | |
9a799d71 AK |
1696 | kfree(adapter->msix_entries); |
1697 | adapter->msix_entries = NULL; | |
021230d4 | 1698 | out: |
9a799d71 AK |
1699 | return err; |
1700 | } | |
1701 | ||
f494e8fa AV |
1702 | static void ixgbe_set_itr(struct ixgbe_adapter *adapter) |
1703 | { | |
7a921c93 | 1704 | struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; |
f494e8fa AV |
1705 | u8 current_itr; |
1706 | u32 new_itr = q_vector->eitr; | |
1707 | struct ixgbe_ring *rx_ring = &adapter->rx_ring[0]; | |
1708 | struct ixgbe_ring *tx_ring = &adapter->tx_ring[0]; | |
1709 | ||
30efa5a3 | 1710 | q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr, |
b4617240 PW |
1711 | q_vector->tx_itr, |
1712 | tx_ring->total_packets, | |
1713 | tx_ring->total_bytes); | |
30efa5a3 | 1714 | q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr, |
b4617240 PW |
1715 | q_vector->rx_itr, |
1716 | rx_ring->total_packets, | |
1717 | rx_ring->total_bytes); | |
f494e8fa | 1718 | |
30efa5a3 | 1719 | current_itr = max(q_vector->rx_itr, q_vector->tx_itr); |
f494e8fa AV |
1720 | |
1721 | switch (current_itr) { | |
1722 | /* counts and packets in update_itr are dependent on these numbers */ | |
1723 | case lowest_latency: | |
1724 | new_itr = 100000; | |
1725 | break; | |
1726 | case low_latency: | |
1727 | new_itr = 20000; /* aka hwitr = ~200 */ | |
1728 | break; | |
1729 | case bulk_latency: | |
1730 | new_itr = 8000; | |
1731 | break; | |
1732 | default: | |
1733 | break; | |
1734 | } | |
1735 | ||
1736 | if (new_itr != q_vector->eitr) { | |
fe49f04a AD |
1737 | /* do an exponential smoothing */ |
1738 | new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100); | |
509ee935 JB |
1739 | |
1740 | /* save the algorithm value here, not the smoothed one */ | |
1741 | q_vector->eitr = new_itr; | |
fe49f04a AD |
1742 | |
1743 | ixgbe_write_eitr(q_vector); | |
f494e8fa AV |
1744 | } |
1745 | ||
1746 | return; | |
1747 | } | |
1748 | ||
79aefa45 AD |
1749 | /** |
1750 | * ixgbe_irq_enable - Enable default interrupt generation settings | |
1751 | * @adapter: board private structure | |
1752 | **/ | |
1753 | static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter) | |
1754 | { | |
1755 | u32 mask; | |
835462fc NS |
1756 | |
1757 | mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE); | |
6ab33d51 DM |
1758 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) |
1759 | mask |= IXGBE_EIMS_GPI_SDP1; | |
e8e26350 | 1760 | if (adapter->hw.mac.type == ixgbe_mac_82599EB) { |
2a41ff81 | 1761 | mask |= IXGBE_EIMS_ECC; |
e8e26350 PW |
1762 | mask |= IXGBE_EIMS_GPI_SDP1; |
1763 | mask |= IXGBE_EIMS_GPI_SDP2; | |
1764 | } | |
c4cf55e5 PWJ |
1765 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || |
1766 | adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) | |
1767 | mask |= IXGBE_EIMS_FLOW_DIR; | |
e8e26350 | 1768 | |
79aefa45 | 1769 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); |
835462fc | 1770 | ixgbe_irq_enable_queues(adapter, ~0); |
79aefa45 AD |
1771 | IXGBE_WRITE_FLUSH(&adapter->hw); |
1772 | } | |
021230d4 | 1773 | |
9a799d71 | 1774 | /** |
021230d4 | 1775 | * ixgbe_intr - legacy mode Interrupt Handler |
9a799d71 AK |
1776 | * @irq: interrupt number |
1777 | * @data: pointer to a network interface device structure | |
9a799d71 AK |
1778 | **/ |
1779 | static irqreturn_t ixgbe_intr(int irq, void *data) | |
1780 | { | |
1781 | struct net_device *netdev = data; | |
1782 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
1783 | struct ixgbe_hw *hw = &adapter->hw; | |
7a921c93 | 1784 | struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; |
9a799d71 AK |
1785 | u32 eicr; |
1786 | ||
54037505 DS |
1787 | /* |
1788 | * Workaround for silicon errata. Mask the interrupts | |
1789 | * before the read of EICR. | |
1790 | */ | |
1791 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); | |
1792 | ||
021230d4 AV |
1793 | /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read |
1794 | * therefore no explict interrupt disable is necessary */ | |
1795 | eicr = IXGBE_READ_REG(hw, IXGBE_EICR); | |
f47cf66e JB |
1796 | if (!eicr) { |
1797 | /* shared interrupt alert! | |
1798 | * make sure interrupts are enabled because the read will | |
1799 | * have disabled interrupts due to EIAM */ | |
1800 | ixgbe_irq_enable(adapter); | |
9a799d71 | 1801 | return IRQ_NONE; /* Not our interrupt */ |
f47cf66e | 1802 | } |
9a799d71 | 1803 | |
cf8280ee JB |
1804 | if (eicr & IXGBE_EICR_LSC) |
1805 | ixgbe_check_lsc(adapter); | |
021230d4 | 1806 | |
e8e26350 PW |
1807 | if (hw->mac.type == ixgbe_mac_82599EB) |
1808 | ixgbe_check_sfp_event(adapter, eicr); | |
1809 | ||
0befdb3e JB |
1810 | ixgbe_check_fan_failure(adapter, eicr); |
1811 | ||
7a921c93 | 1812 | if (napi_schedule_prep(&(q_vector->napi))) { |
f494e8fa AV |
1813 | adapter->tx_ring[0].total_packets = 0; |
1814 | adapter->tx_ring[0].total_bytes = 0; | |
1815 | adapter->rx_ring[0].total_packets = 0; | |
1816 | adapter->rx_ring[0].total_bytes = 0; | |
021230d4 | 1817 | /* would disable interrupts here but EIAM disabled it */ |
7a921c93 | 1818 | __napi_schedule(&(q_vector->napi)); |
9a799d71 AK |
1819 | } |
1820 | ||
1821 | return IRQ_HANDLED; | |
1822 | } | |
1823 | ||
021230d4 AV |
1824 | static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter) |
1825 | { | |
1826 | int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
1827 | ||
1828 | for (i = 0; i < q_vectors; i++) { | |
7a921c93 | 1829 | struct ixgbe_q_vector *q_vector = adapter->q_vector[i]; |
021230d4 AV |
1830 | bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES); |
1831 | bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES); | |
1832 | q_vector->rxr_count = 0; | |
1833 | q_vector->txr_count = 0; | |
1834 | } | |
1835 | } | |
1836 | ||
9a799d71 AK |
1837 | /** |
1838 | * ixgbe_request_irq - initialize interrupts | |
1839 | * @adapter: board private structure | |
1840 | * | |
1841 | * Attempts to configure interrupts using the best available | |
1842 | * capabilities of the hardware and kernel. | |
1843 | **/ | |
021230d4 | 1844 | static int ixgbe_request_irq(struct ixgbe_adapter *adapter) |
9a799d71 AK |
1845 | { |
1846 | struct net_device *netdev = adapter->netdev; | |
021230d4 | 1847 | int err; |
9a799d71 | 1848 | |
021230d4 AV |
1849 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
1850 | err = ixgbe_request_msix_irqs(adapter); | |
1851 | } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) { | |
a0607fd3 | 1852 | err = request_irq(adapter->pdev->irq, ixgbe_intr, 0, |
b4617240 | 1853 | netdev->name, netdev); |
021230d4 | 1854 | } else { |
a0607fd3 | 1855 | err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED, |
b4617240 | 1856 | netdev->name, netdev); |
9a799d71 AK |
1857 | } |
1858 | ||
9a799d71 AK |
1859 | if (err) |
1860 | DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err); | |
1861 | ||
9a799d71 AK |
1862 | return err; |
1863 | } | |
1864 | ||
1865 | static void ixgbe_free_irq(struct ixgbe_adapter *adapter) | |
1866 | { | |
1867 | struct net_device *netdev = adapter->netdev; | |
1868 | ||
1869 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
021230d4 | 1870 | int i, q_vectors; |
9a799d71 | 1871 | |
021230d4 AV |
1872 | q_vectors = adapter->num_msix_vectors; |
1873 | ||
1874 | i = q_vectors - 1; | |
9a799d71 | 1875 | free_irq(adapter->msix_entries[i].vector, netdev); |
9a799d71 | 1876 | |
021230d4 AV |
1877 | i--; |
1878 | for (; i >= 0; i--) { | |
1879 | free_irq(adapter->msix_entries[i].vector, | |
7a921c93 | 1880 | adapter->q_vector[i]); |
021230d4 AV |
1881 | } |
1882 | ||
1883 | ixgbe_reset_q_vectors(adapter); | |
1884 | } else { | |
1885 | free_irq(adapter->pdev->irq, netdev); | |
9a799d71 AK |
1886 | } |
1887 | } | |
1888 | ||
22d5a71b JB |
1889 | /** |
1890 | * ixgbe_irq_disable - Mask off interrupt generation on the NIC | |
1891 | * @adapter: board private structure | |
1892 | **/ | |
1893 | static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) | |
1894 | { | |
835462fc NS |
1895 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
1896 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); | |
1897 | } else { | |
1898 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000); | |
1899 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0); | |
22d5a71b | 1900 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0); |
22d5a71b JB |
1901 | } |
1902 | IXGBE_WRITE_FLUSH(&adapter->hw); | |
1903 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
1904 | int i; | |
1905 | for (i = 0; i < adapter->num_msix_vectors; i++) | |
1906 | synchronize_irq(adapter->msix_entries[i].vector); | |
1907 | } else { | |
1908 | synchronize_irq(adapter->pdev->irq); | |
1909 | } | |
1910 | } | |
1911 | ||
9a799d71 AK |
1912 | /** |
1913 | * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts | |
1914 | * | |
1915 | **/ | |
1916 | static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter) | |
1917 | { | |
9a799d71 AK |
1918 | struct ixgbe_hw *hw = &adapter->hw; |
1919 | ||
021230d4 | 1920 | IXGBE_WRITE_REG(hw, IXGBE_EITR(0), |
f7554a2b | 1921 | EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param)); |
9a799d71 | 1922 | |
e8e26350 PW |
1923 | ixgbe_set_ivar(adapter, 0, 0, 0); |
1924 | ixgbe_set_ivar(adapter, 1, 0, 0); | |
021230d4 AV |
1925 | |
1926 | map_vector_to_rxq(adapter, 0, 0); | |
1927 | map_vector_to_txq(adapter, 0, 0); | |
1928 | ||
1929 | DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n"); | |
9a799d71 AK |
1930 | } |
1931 | ||
1932 | /** | |
3a581073 | 1933 | * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset |
9a799d71 AK |
1934 | * @adapter: board private structure |
1935 | * | |
1936 | * Configure the Tx unit of the MAC after a reset. | |
1937 | **/ | |
1938 | static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) | |
1939 | { | |
12207e49 | 1940 | u64 tdba; |
9a799d71 | 1941 | struct ixgbe_hw *hw = &adapter->hw; |
021230d4 | 1942 | u32 i, j, tdlen, txctrl; |
9a799d71 AK |
1943 | |
1944 | /* Setup the HW Tx Head and Tail descriptor pointers */ | |
1945 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
e01c31a5 JB |
1946 | struct ixgbe_ring *ring = &adapter->tx_ring[i]; |
1947 | j = ring->reg_idx; | |
1948 | tdba = ring->dma; | |
1949 | tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc); | |
021230d4 | 1950 | IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j), |
284901a9 | 1951 | (tdba & DMA_BIT_MASK(32))); |
021230d4 AV |
1952 | IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32)); |
1953 | IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen); | |
1954 | IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0); | |
1955 | IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0); | |
1956 | adapter->tx_ring[i].head = IXGBE_TDH(j); | |
1957 | adapter->tx_ring[i].tail = IXGBE_TDT(j); | |
84f62d4b PWJ |
1958 | /* |
1959 | * Disable Tx Head Writeback RO bit, since this hoses | |
021230d4 AV |
1960 | * bookkeeping if things aren't delivered in order. |
1961 | */ | |
84f62d4b PWJ |
1962 | switch (hw->mac.type) { |
1963 | case ixgbe_mac_82598EB: | |
1964 | txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j)); | |
1965 | break; | |
1966 | case ixgbe_mac_82599EB: | |
1967 | default: | |
1968 | txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(j)); | |
1969 | break; | |
1970 | } | |
021230d4 | 1971 | txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN; |
84f62d4b PWJ |
1972 | switch (hw->mac.type) { |
1973 | case ixgbe_mac_82598EB: | |
1974 | IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl); | |
1975 | break; | |
1976 | case ixgbe_mac_82599EB: | |
1977 | default: | |
1978 | IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(j), txctrl); | |
1979 | break; | |
1980 | } | |
9a799d71 | 1981 | } |
ee5f784a | 1982 | |
e8e26350 | 1983 | if (hw->mac.type == ixgbe_mac_82599EB) { |
ee5f784a DS |
1984 | u32 rttdcs; |
1985 | ||
1986 | /* disable the arbiter while setting MTQC */ | |
1987 | rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS); | |
1988 | rttdcs |= IXGBE_RTTDCS_ARBDIS; | |
1989 | IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); | |
1990 | ||
e8e26350 PW |
1991 | /* We enable 8 traffic classes, DCB only */ |
1992 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) | |
1993 | IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA | | |
1994 | IXGBE_MTQC_8TC_8TQ)); | |
ee5f784a DS |
1995 | else |
1996 | IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB); | |
1997 | ||
1998 | /* re-eable the arbiter */ | |
1999 | rttdcs &= ~IXGBE_RTTDCS_ARBDIS; | |
2000 | IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); | |
e8e26350 | 2001 | } |
9a799d71 AK |
2002 | } |
2003 | ||
e8e26350 | 2004 | #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 |
cc41ac7c | 2005 | |
a6616b42 YZ |
2006 | static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, |
2007 | struct ixgbe_ring *rx_ring) | |
cc41ac7c | 2008 | { |
cc41ac7c | 2009 | u32 srrctl; |
a6616b42 | 2010 | int index; |
0cefafad | 2011 | struct ixgbe_ring_feature *feature = adapter->ring_feature; |
3be1adfb | 2012 | |
a6616b42 YZ |
2013 | index = rx_ring->reg_idx; |
2014 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { | |
2015 | unsigned long mask; | |
0cefafad | 2016 | mask = (unsigned long) feature[RING_F_RSS].mask; |
3be1adfb | 2017 | index = index & mask; |
cc41ac7c | 2018 | } |
cc41ac7c JB |
2019 | srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index)); |
2020 | ||
2021 | srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK; | |
2022 | srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK; | |
2023 | ||
afafd5b0 AD |
2024 | srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) & |
2025 | IXGBE_SRRCTL_BSIZEHDR_MASK; | |
2026 | ||
6e455b89 | 2027 | if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) { |
afafd5b0 AD |
2028 | #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER |
2029 | srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
2030 | #else | |
2031 | srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
2032 | #endif | |
cc41ac7c | 2033 | srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS; |
cc41ac7c | 2034 | } else { |
afafd5b0 AD |
2035 | srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >> |
2036 | IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
cc41ac7c | 2037 | srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; |
cc41ac7c | 2038 | } |
e8e26350 | 2039 | |
cc41ac7c JB |
2040 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl); |
2041 | } | |
9a799d71 | 2042 | |
0cefafad JB |
2043 | static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter) |
2044 | { | |
2045 | u32 mrqc = 0; | |
2046 | int mask; | |
2047 | ||
2048 | if (!(adapter->hw.mac.type == ixgbe_mac_82599EB)) | |
2049 | return mrqc; | |
2050 | ||
2051 | mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED | |
2052 | #ifdef CONFIG_IXGBE_DCB | |
2053 | | IXGBE_FLAG_DCB_ENABLED | |
2054 | #endif | |
2055 | ); | |
2056 | ||
2057 | switch (mask) { | |
2058 | case (IXGBE_FLAG_RSS_ENABLED): | |
2059 | mrqc = IXGBE_MRQC_RSSEN; | |
2060 | break; | |
2061 | #ifdef CONFIG_IXGBE_DCB | |
2062 | case (IXGBE_FLAG_DCB_ENABLED): | |
2063 | mrqc = IXGBE_MRQC_RT8TCEN; | |
2064 | break; | |
2065 | #endif /* CONFIG_IXGBE_DCB */ | |
2066 | default: | |
2067 | break; | |
2068 | } | |
2069 | ||
2070 | return mrqc; | |
2071 | } | |
2072 | ||
bb5a9ad2 NS |
2073 | /** |
2074 | * ixgbe_configure_rscctl - enable RSC for the indicated ring | |
2075 | * @adapter: address of board private structure | |
2076 | * @index: index of ring to set | |
bb5a9ad2 | 2077 | **/ |
edd2ea55 | 2078 | static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, int index) |
bb5a9ad2 NS |
2079 | { |
2080 | struct ixgbe_ring *rx_ring; | |
2081 | struct ixgbe_hw *hw = &adapter->hw; | |
2082 | int j; | |
2083 | u32 rscctrl; | |
edd2ea55 | 2084 | int rx_buf_len; |
bb5a9ad2 NS |
2085 | |
2086 | rx_ring = &adapter->rx_ring[index]; | |
2087 | j = rx_ring->reg_idx; | |
edd2ea55 | 2088 | rx_buf_len = rx_ring->rx_buf_len; |
bb5a9ad2 NS |
2089 | rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j)); |
2090 | rscctrl |= IXGBE_RSCCTL_RSCEN; | |
2091 | /* | |
2092 | * we must limit the number of descriptors so that the | |
2093 | * total size of max desc * buf_len is not greater | |
2094 | * than 65535 | |
2095 | */ | |
2096 | if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) { | |
2097 | #if (MAX_SKB_FRAGS > 16) | |
2098 | rscctrl |= IXGBE_RSCCTL_MAXDESC_16; | |
2099 | #elif (MAX_SKB_FRAGS > 8) | |
2100 | rscctrl |= IXGBE_RSCCTL_MAXDESC_8; | |
2101 | #elif (MAX_SKB_FRAGS > 4) | |
2102 | rscctrl |= IXGBE_RSCCTL_MAXDESC_4; | |
2103 | #else | |
2104 | rscctrl |= IXGBE_RSCCTL_MAXDESC_1; | |
2105 | #endif | |
2106 | } else { | |
2107 | if (rx_buf_len < IXGBE_RXBUFFER_4096) | |
2108 | rscctrl |= IXGBE_RSCCTL_MAXDESC_16; | |
2109 | else if (rx_buf_len < IXGBE_RXBUFFER_8192) | |
2110 | rscctrl |= IXGBE_RSCCTL_MAXDESC_8; | |
2111 | else | |
2112 | rscctrl |= IXGBE_RSCCTL_MAXDESC_4; | |
2113 | } | |
2114 | IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl); | |
2115 | } | |
2116 | ||
9a799d71 | 2117 | /** |
3a581073 | 2118 | * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset |
9a799d71 AK |
2119 | * @adapter: board private structure |
2120 | * | |
2121 | * Configure the Rx unit of the MAC after a reset. | |
2122 | **/ | |
2123 | static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) | |
2124 | { | |
2125 | u64 rdba; | |
2126 | struct ixgbe_hw *hw = &adapter->hw; | |
a6616b42 | 2127 | struct ixgbe_ring *rx_ring; |
9a799d71 AK |
2128 | struct net_device *netdev = adapter->netdev; |
2129 | int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; | |
021230d4 | 2130 | int i, j; |
9a799d71 | 2131 | u32 rdlen, rxctrl, rxcsum; |
7c6e0a43 JB |
2132 | static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D, |
2133 | 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE, | |
2134 | 0x6A3E67EA, 0x14364D17, 0x3BED200D}; | |
9a799d71 | 2135 | u32 fctrl, hlreg0; |
509ee935 | 2136 | u32 reta = 0, mrqc = 0; |
cc41ac7c | 2137 | u32 rdrxctl; |
7c6e0a43 | 2138 | int rx_buf_len; |
9a799d71 AK |
2139 | |
2140 | /* Decide whether to use packet split mode or not */ | |
762f4c57 | 2141 | adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED; |
9a799d71 AK |
2142 | |
2143 | /* Set the RX buffer length according to the mode */ | |
2144 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { | |
7c6e0a43 | 2145 | rx_buf_len = IXGBE_RX_HDR_SIZE; |
e8e26350 PW |
2146 | if (hw->mac.type == ixgbe_mac_82599EB) { |
2147 | /* PSRTYPE must be initialized in 82599 */ | |
2148 | u32 psrtype = IXGBE_PSRTYPE_TCPHDR | | |
2149 | IXGBE_PSRTYPE_UDPHDR | | |
2150 | IXGBE_PSRTYPE_IPV4HDR | | |
dfa12f05 YZ |
2151 | IXGBE_PSRTYPE_IPV6HDR | |
2152 | IXGBE_PSRTYPE_L2HDR; | |
e8e26350 PW |
2153 | IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype); |
2154 | } | |
9a799d71 | 2155 | } else { |
0c19d6af | 2156 | if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) && |
f8212f97 | 2157 | (netdev->mtu <= ETH_DATA_LEN)) |
7c6e0a43 | 2158 | rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE; |
9a799d71 | 2159 | else |
7c6e0a43 | 2160 | rx_buf_len = ALIGN(max_frame, 1024); |
9a799d71 AK |
2161 | } |
2162 | ||
2163 | fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL); | |
2164 | fctrl |= IXGBE_FCTRL_BAM; | |
021230d4 | 2165 | fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */ |
e8e26350 | 2166 | fctrl |= IXGBE_FCTRL_PMCF; |
9a799d71 AK |
2167 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl); |
2168 | ||
2169 | hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); | |
2170 | if (adapter->netdev->mtu <= ETH_DATA_LEN) | |
2171 | hlreg0 &= ~IXGBE_HLREG0_JUMBOEN; | |
2172 | else | |
2173 | hlreg0 |= IXGBE_HLREG0_JUMBOEN; | |
63f39bd1 | 2174 | #ifdef IXGBE_FCOE |
f34c5c82 | 2175 | if (netdev->features & NETIF_F_FCOE_MTU) |
63f39bd1 YZ |
2176 | hlreg0 |= IXGBE_HLREG0_JUMBOEN; |
2177 | #endif | |
9a799d71 AK |
2178 | IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); |
2179 | ||
9a799d71 AK |
2180 | rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc); |
2181 | /* disable receives while setting up the descriptors */ | |
2182 | rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); | |
2183 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); | |
2184 | ||
0cefafad JB |
2185 | /* |
2186 | * Setup the HW Rx Head and Tail Descriptor Pointers and | |
2187 | * the Base and Length of the Rx Descriptor Ring | |
2188 | */ | |
9a799d71 | 2189 | for (i = 0; i < adapter->num_rx_queues; i++) { |
a6616b42 YZ |
2190 | rx_ring = &adapter->rx_ring[i]; |
2191 | rdba = rx_ring->dma; | |
2192 | j = rx_ring->reg_idx; | |
284901a9 | 2193 | IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32))); |
7c6e0a43 JB |
2194 | IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32)); |
2195 | IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen); | |
2196 | IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0); | |
2197 | IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0); | |
a6616b42 YZ |
2198 | rx_ring->head = IXGBE_RDH(j); |
2199 | rx_ring->tail = IXGBE_RDT(j); | |
2200 | rx_ring->rx_buf_len = rx_buf_len; | |
cc41ac7c | 2201 | |
6e455b89 YZ |
2202 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) |
2203 | rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED; | |
1b3ff02e PWJ |
2204 | else |
2205 | rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED; | |
cc41ac7c | 2206 | |
63f39bd1 | 2207 | #ifdef IXGBE_FCOE |
f34c5c82 | 2208 | if (netdev->features & NETIF_F_FCOE_MTU) { |
63f39bd1 YZ |
2209 | struct ixgbe_ring_feature *f; |
2210 | f = &adapter->ring_feature[RING_F_FCOE]; | |
6e455b89 YZ |
2211 | if ((i >= f->mask) && (i < f->mask + f->indices)) { |
2212 | rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED; | |
2213 | if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE) | |
2214 | rx_ring->rx_buf_len = | |
2215 | IXGBE_FCOE_JUMBO_FRAME_SIZE; | |
2216 | } | |
63f39bd1 YZ |
2217 | } |
2218 | ||
2219 | #endif /* IXGBE_FCOE */ | |
a6616b42 | 2220 | ixgbe_configure_srrctl(adapter, rx_ring); |
9a799d71 AK |
2221 | } |
2222 | ||
e8e26350 PW |
2223 | if (hw->mac.type == ixgbe_mac_82598EB) { |
2224 | /* | |
2225 | * For VMDq support of different descriptor types or | |
2226 | * buffer sizes through the use of multiple SRRCTL | |
2227 | * registers, RDRXCTL.MVMEN must be set to 1 | |
2228 | * | |
2229 | * also, the manual doesn't mention it clearly but DCA hints | |
2230 | * will only use queue 0's tags unless this bit is set. Side | |
2231 | * effects of setting this bit are only that SRRCTL must be | |
2232 | * fully programmed [0..15] | |
2233 | */ | |
2a41ff81 JB |
2234 | rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); |
2235 | rdrxctl |= IXGBE_RDRXCTL_MVMEN; | |
2236 | IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); | |
2f90b865 | 2237 | } |
177db6ff | 2238 | |
e8e26350 | 2239 | /* Program MRQC for the distribution of queues */ |
0cefafad | 2240 | mrqc = ixgbe_setup_mrqc(adapter); |
e8e26350 | 2241 | |
021230d4 | 2242 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { |
9a799d71 | 2243 | /* Fill out redirection table */ |
021230d4 AV |
2244 | for (i = 0, j = 0; i < 128; i++, j++) { |
2245 | if (j == adapter->ring_feature[RING_F_RSS].indices) | |
2246 | j = 0; | |
2247 | /* reta = 4-byte sliding window of | |
2248 | * 0x00..(indices-1)(indices-1)00..etc. */ | |
2249 | reta = (reta << 8) | (j * 0x11); | |
2250 | if ((i & 3) == 3) | |
2251 | IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); | |
9a799d71 AK |
2252 | } |
2253 | ||
2254 | /* Fill out hash function seeds */ | |
2255 | for (i = 0; i < 10; i++) | |
7c6e0a43 | 2256 | IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]); |
9a799d71 | 2257 | |
2a41ff81 JB |
2258 | if (hw->mac.type == ixgbe_mac_82598EB) |
2259 | mrqc |= IXGBE_MRQC_RSSEN; | |
9a799d71 | 2260 | /* Perform hash on these packet types */ |
2a41ff81 JB |
2261 | mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 |
2262 | | IXGBE_MRQC_RSS_FIELD_IPV4_TCP | |
2263 | | IXGBE_MRQC_RSS_FIELD_IPV4_UDP | |
2264 | | IXGBE_MRQC_RSS_FIELD_IPV6 | |
2265 | | IXGBE_MRQC_RSS_FIELD_IPV6_TCP | |
2266 | | IXGBE_MRQC_RSS_FIELD_IPV6_UDP; | |
021230d4 | 2267 | } |
2a41ff81 | 2268 | IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); |
9a799d71 | 2269 | |
021230d4 AV |
2270 | rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); |
2271 | ||
2272 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED || | |
2273 | adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) { | |
2274 | /* Disable indicating checksum in descriptor, enables | |
2275 | * RSS hash */ | |
9a799d71 | 2276 | rxcsum |= IXGBE_RXCSUM_PCSD; |
9a799d71 | 2277 | } |
021230d4 AV |
2278 | if (!(rxcsum & IXGBE_RXCSUM_PCSD)) { |
2279 | /* Enable IPv4 payload checksum for UDP fragments | |
2280 | * if PCSD is not set */ | |
2281 | rxcsum |= IXGBE_RXCSUM_IPPCSE; | |
2282 | } | |
2283 | ||
2284 | IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); | |
e8e26350 PW |
2285 | |
2286 | if (hw->mac.type == ixgbe_mac_82599EB) { | |
2287 | rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); | |
2288 | rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP; | |
f8212f97 | 2289 | rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE; |
e8e26350 PW |
2290 | IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); |
2291 | } | |
f8212f97 | 2292 | |
0c19d6af | 2293 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { |
f8212f97 | 2294 | /* Enable 82599 HW-RSC */ |
bb5a9ad2 | 2295 | for (i = 0; i < adapter->num_rx_queues; i++) |
edd2ea55 | 2296 | ixgbe_configure_rscctl(adapter, i); |
bb5a9ad2 | 2297 | |
f8212f97 AD |
2298 | /* Disable RSC for ACK packets */ |
2299 | IXGBE_WRITE_REG(hw, IXGBE_RSCDBU, | |
2300 | (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU))); | |
2301 | } | |
9a799d71 AK |
2302 | } |
2303 | ||
068c89b0 DS |
2304 | static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid) |
2305 | { | |
2306 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
2307 | struct ixgbe_hw *hw = &adapter->hw; | |
2308 | ||
2309 | /* add VID to filter table */ | |
2310 | hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true); | |
2311 | } | |
2312 | ||
2313 | static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) | |
2314 | { | |
2315 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
2316 | struct ixgbe_hw *hw = &adapter->hw; | |
2317 | ||
2318 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
2319 | ixgbe_irq_disable(adapter); | |
2320 | ||
2321 | vlan_group_set_device(adapter->vlgrp, vid, NULL); | |
2322 | ||
2323 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
2324 | ixgbe_irq_enable(adapter); | |
2325 | ||
2326 | /* remove VID from filter table */ | |
2327 | hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false); | |
2328 | } | |
2329 | ||
9a799d71 | 2330 | static void ixgbe_vlan_rx_register(struct net_device *netdev, |
b4617240 | 2331 | struct vlan_group *grp) |
9a799d71 AK |
2332 | { |
2333 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
2334 | u32 ctrl; | |
e8e26350 | 2335 | int i, j; |
9a799d71 | 2336 | |
d4f80882 AV |
2337 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
2338 | ixgbe_irq_disable(adapter); | |
9a799d71 AK |
2339 | adapter->vlgrp = grp; |
2340 | ||
2f90b865 AD |
2341 | /* |
2342 | * For a DCB driver, always enable VLAN tag stripping so we can | |
2343 | * still receive traffic from a DCB-enabled host even if we're | |
2344 | * not in DCB mode. | |
2345 | */ | |
2346 | ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL); | |
dc63d377 AD |
2347 | |
2348 | /* Disable CFI check */ | |
2349 | ctrl &= ~IXGBE_VLNCTRL_CFIEN; | |
2350 | ||
2351 | /* enable VLAN tag stripping */ | |
e8e26350 | 2352 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
dc63d377 | 2353 | ctrl |= IXGBE_VLNCTRL_VME; |
e8e26350 | 2354 | } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { |
e8e26350 | 2355 | for (i = 0; i < adapter->num_rx_queues; i++) { |
dc63d377 | 2356 | u32 ctrl; |
e8e26350 PW |
2357 | j = adapter->rx_ring[i].reg_idx; |
2358 | ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j)); | |
2359 | ctrl |= IXGBE_RXDCTL_VME; | |
2360 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl); | |
2361 | } | |
9a799d71 | 2362 | } |
dc63d377 AD |
2363 | |
2364 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl); | |
2365 | ||
e8e26350 | 2366 | ixgbe_vlan_rx_add_vid(netdev, 0); |
9a799d71 | 2367 | |
d4f80882 AV |
2368 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
2369 | ixgbe_irq_enable(adapter); | |
9a799d71 AK |
2370 | } |
2371 | ||
9a799d71 AK |
2372 | static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter) |
2373 | { | |
2374 | ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp); | |
2375 | ||
2376 | if (adapter->vlgrp) { | |
2377 | u16 vid; | |
2378 | for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) { | |
2379 | if (!vlan_group_get_device(adapter->vlgrp, vid)) | |
2380 | continue; | |
2381 | ixgbe_vlan_rx_add_vid(adapter->netdev, vid); | |
2382 | } | |
2383 | } | |
2384 | } | |
2385 | ||
2c5645cf CL |
2386 | static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq) |
2387 | { | |
2388 | struct dev_mc_list *mc_ptr; | |
2389 | u8 *addr = *mc_addr_ptr; | |
2390 | *vmdq = 0; | |
2391 | ||
2392 | mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]); | |
2393 | if (mc_ptr->next) | |
2394 | *mc_addr_ptr = mc_ptr->next->dmi_addr; | |
2395 | else | |
2396 | *mc_addr_ptr = NULL; | |
2397 | ||
2398 | return addr; | |
2399 | } | |
2400 | ||
9a799d71 | 2401 | /** |
2c5645cf | 2402 | * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set |
9a799d71 AK |
2403 | * @netdev: network interface device structure |
2404 | * | |
2c5645cf CL |
2405 | * The set_rx_method entry point is called whenever the unicast/multicast |
2406 | * address list or the network interface flags are updated. This routine is | |
2407 | * responsible for configuring the hardware for proper unicast, multicast and | |
2408 | * promiscuous mode. | |
9a799d71 | 2409 | **/ |
2c5645cf | 2410 | static void ixgbe_set_rx_mode(struct net_device *netdev) |
9a799d71 AK |
2411 | { |
2412 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
2413 | struct ixgbe_hw *hw = &adapter->hw; | |
3d01625a | 2414 | u32 fctrl, vlnctrl; |
2c5645cf CL |
2415 | u8 *addr_list = NULL; |
2416 | int addr_count = 0; | |
9a799d71 AK |
2417 | |
2418 | /* Check for Promiscuous and All Multicast modes */ | |
2419 | ||
2420 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
3d01625a | 2421 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); |
9a799d71 AK |
2422 | |
2423 | if (netdev->flags & IFF_PROMISC) { | |
2c5645cf | 2424 | hw->addr_ctrl.user_set_promisc = 1; |
9a799d71 | 2425 | fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); |
3d01625a | 2426 | vlnctrl &= ~IXGBE_VLNCTRL_VFE; |
9a799d71 | 2427 | } else { |
746b9f02 PM |
2428 | if (netdev->flags & IFF_ALLMULTI) { |
2429 | fctrl |= IXGBE_FCTRL_MPE; | |
2430 | fctrl &= ~IXGBE_FCTRL_UPE; | |
2431 | } else { | |
2432 | fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); | |
2433 | } | |
3d01625a | 2434 | vlnctrl |= IXGBE_VLNCTRL_VFE; |
2c5645cf | 2435 | hw->addr_ctrl.user_set_promisc = 0; |
9a799d71 AK |
2436 | } |
2437 | ||
2438 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); | |
3d01625a | 2439 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); |
9a799d71 | 2440 | |
2c5645cf | 2441 | /* reprogram secondary unicast list */ |
31278e71 | 2442 | hw->mac.ops.update_uc_addr_list(hw, &netdev->uc.list); |
9a799d71 | 2443 | |
2c5645cf CL |
2444 | /* reprogram multicast list */ |
2445 | addr_count = netdev->mc_count; | |
2446 | if (addr_count) | |
2447 | addr_list = netdev->mc_list->dmi_addr; | |
c44ade9e JB |
2448 | hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count, |
2449 | ixgbe_addr_list_itr); | |
9a799d71 AK |
2450 | } |
2451 | ||
021230d4 AV |
2452 | static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter) |
2453 | { | |
2454 | int q_idx; | |
2455 | struct ixgbe_q_vector *q_vector; | |
2456 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
2457 | ||
2458 | /* legacy and MSI only use one vector */ | |
2459 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
2460 | q_vectors = 1; | |
2461 | ||
2462 | for (q_idx = 0; q_idx < q_vectors; q_idx++) { | |
f0848276 | 2463 | struct napi_struct *napi; |
7a921c93 | 2464 | q_vector = adapter->q_vector[q_idx]; |
f0848276 | 2465 | napi = &q_vector->napi; |
91281fd3 AD |
2466 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
2467 | if (!q_vector->rxr_count || !q_vector->txr_count) { | |
2468 | if (q_vector->txr_count == 1) | |
2469 | napi->poll = &ixgbe_clean_txonly; | |
2470 | else if (q_vector->rxr_count == 1) | |
2471 | napi->poll = &ixgbe_clean_rxonly; | |
2472 | } | |
2473 | } | |
f0848276 JB |
2474 | |
2475 | napi_enable(napi); | |
021230d4 AV |
2476 | } |
2477 | } | |
2478 | ||
2479 | static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter) | |
2480 | { | |
2481 | int q_idx; | |
2482 | struct ixgbe_q_vector *q_vector; | |
2483 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
2484 | ||
2485 | /* legacy and MSI only use one vector */ | |
2486 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
2487 | q_vectors = 1; | |
2488 | ||
2489 | for (q_idx = 0; q_idx < q_vectors; q_idx++) { | |
7a921c93 | 2490 | q_vector = adapter->q_vector[q_idx]; |
021230d4 AV |
2491 | napi_disable(&q_vector->napi); |
2492 | } | |
2493 | } | |
2494 | ||
7a6b6f51 | 2495 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
2496 | /* |
2497 | * ixgbe_configure_dcb - Configure DCB hardware | |
2498 | * @adapter: ixgbe adapter struct | |
2499 | * | |
2500 | * This is called by the driver on open to configure the DCB hardware. | |
2501 | * This is also called by the gennetlink interface when reconfiguring | |
2502 | * the DCB state. | |
2503 | */ | |
2504 | static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter) | |
2505 | { | |
2506 | struct ixgbe_hw *hw = &adapter->hw; | |
2507 | u32 txdctl, vlnctrl; | |
2508 | int i, j; | |
2509 | ||
2510 | ixgbe_dcb_check_config(&adapter->dcb_cfg); | |
2511 | ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG); | |
2512 | ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG); | |
2513 | ||
2514 | /* reconfigure the hardware */ | |
2515 | ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg); | |
2516 | ||
2517 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
2518 | j = adapter->tx_ring[i].reg_idx; | |
2519 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)); | |
2520 | /* PThresh workaround for Tx hang with DFP enabled. */ | |
2521 | txdctl |= 32; | |
2522 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl); | |
2523 | } | |
2524 | /* Enable VLAN tag insert/strip */ | |
2525 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); | |
e8e26350 PW |
2526 | if (hw->mac.type == ixgbe_mac_82598EB) { |
2527 | vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE; | |
2528 | vlnctrl &= ~IXGBE_VLNCTRL_CFIEN; | |
2529 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); | |
2530 | } else if (hw->mac.type == ixgbe_mac_82599EB) { | |
2531 | vlnctrl |= IXGBE_VLNCTRL_VFE; | |
2532 | vlnctrl &= ~IXGBE_VLNCTRL_CFIEN; | |
2533 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); | |
2534 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
2535 | j = adapter->rx_ring[i].reg_idx; | |
2536 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); | |
2537 | vlnctrl |= IXGBE_RXDCTL_VME; | |
2538 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); | |
2539 | } | |
2540 | } | |
2f90b865 AD |
2541 | hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true); |
2542 | } | |
2543 | ||
2544 | #endif | |
9a799d71 AK |
2545 | static void ixgbe_configure(struct ixgbe_adapter *adapter) |
2546 | { | |
2547 | struct net_device *netdev = adapter->netdev; | |
c4cf55e5 | 2548 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 AK |
2549 | int i; |
2550 | ||
2c5645cf | 2551 | ixgbe_set_rx_mode(netdev); |
9a799d71 AK |
2552 | |
2553 | ixgbe_restore_vlan(adapter); | |
7a6b6f51 | 2554 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 | 2555 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { |
b352e40d YZ |
2556 | if (hw->mac.type == ixgbe_mac_82598EB) |
2557 | netif_set_gso_max_size(netdev, 32768); | |
2558 | else | |
2559 | netif_set_gso_max_size(netdev, 65536); | |
2f90b865 AD |
2560 | ixgbe_configure_dcb(adapter); |
2561 | } else { | |
2562 | netif_set_gso_max_size(netdev, 65536); | |
2563 | } | |
2564 | #else | |
2565 | netif_set_gso_max_size(netdev, 65536); | |
2566 | #endif | |
9a799d71 | 2567 | |
eacd73f7 YZ |
2568 | #ifdef IXGBE_FCOE |
2569 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) | |
2570 | ixgbe_configure_fcoe(adapter); | |
2571 | ||
2572 | #endif /* IXGBE_FCOE */ | |
c4cf55e5 PWJ |
2573 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { |
2574 | for (i = 0; i < adapter->num_tx_queues; i++) | |
2575 | adapter->tx_ring[i].atr_sample_rate = | |
2576 | adapter->atr_sample_rate; | |
2577 | ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc); | |
2578 | } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) { | |
2579 | ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc); | |
2580 | } | |
2581 | ||
9a799d71 AK |
2582 | ixgbe_configure_tx(adapter); |
2583 | ixgbe_configure_rx(adapter); | |
2584 | for (i = 0; i < adapter->num_rx_queues; i++) | |
2585 | ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i], | |
b4617240 | 2586 | (adapter->rx_ring[i].count - 1)); |
9a799d71 AK |
2587 | } |
2588 | ||
e8e26350 PW |
2589 | static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw) |
2590 | { | |
2591 | switch (hw->phy.type) { | |
2592 | case ixgbe_phy_sfp_avago: | |
2593 | case ixgbe_phy_sfp_ftl: | |
2594 | case ixgbe_phy_sfp_intel: | |
2595 | case ixgbe_phy_sfp_unknown: | |
2596 | case ixgbe_phy_tw_tyco: | |
2597 | case ixgbe_phy_tw_unknown: | |
2598 | return true; | |
2599 | default: | |
2600 | return false; | |
2601 | } | |
2602 | } | |
2603 | ||
0ecc061d | 2604 | /** |
e8e26350 PW |
2605 | * ixgbe_sfp_link_config - set up SFP+ link |
2606 | * @adapter: pointer to private adapter struct | |
2607 | **/ | |
2608 | static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter) | |
2609 | { | |
2610 | struct ixgbe_hw *hw = &adapter->hw; | |
2611 | ||
2612 | if (hw->phy.multispeed_fiber) { | |
2613 | /* | |
2614 | * In multispeed fiber setups, the device may not have | |
2615 | * had a physical connection when the driver loaded. | |
2616 | * If that's the case, the initial link configuration | |
2617 | * couldn't get the MAC into 10G or 1G mode, so we'll | |
2618 | * never have a link status change interrupt fire. | |
2619 | * We need to try and force an autonegotiation | |
2620 | * session, then bring up link. | |
2621 | */ | |
2622 | hw->mac.ops.setup_sfp(hw); | |
2623 | if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK)) | |
2624 | schedule_work(&adapter->multispeed_fiber_task); | |
2625 | } else { | |
2626 | /* | |
2627 | * Direct Attach Cu and non-multispeed fiber modules | |
2628 | * still need to be configured properly prior to | |
2629 | * attempting link. | |
2630 | */ | |
2631 | if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK)) | |
2632 | schedule_work(&adapter->sfp_config_module_task); | |
2633 | } | |
2634 | } | |
2635 | ||
2636 | /** | |
2637 | * ixgbe_non_sfp_link_config - set up non-SFP+ link | |
0ecc061d PWJ |
2638 | * @hw: pointer to private hardware struct |
2639 | * | |
2640 | * Returns 0 on success, negative on failure | |
2641 | **/ | |
e8e26350 | 2642 | static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw) |
0ecc061d PWJ |
2643 | { |
2644 | u32 autoneg; | |
8620a103 | 2645 | bool negotiation, link_up = false; |
0ecc061d PWJ |
2646 | u32 ret = IXGBE_ERR_LINK_SETUP; |
2647 | ||
2648 | if (hw->mac.ops.check_link) | |
2649 | ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false); | |
2650 | ||
2651 | if (ret) | |
2652 | goto link_cfg_out; | |
2653 | ||
2654 | if (hw->mac.ops.get_link_capabilities) | |
8620a103 | 2655 | ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation); |
0ecc061d PWJ |
2656 | if (ret) |
2657 | goto link_cfg_out; | |
2658 | ||
8620a103 MC |
2659 | if (hw->mac.ops.setup_link) |
2660 | ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up); | |
0ecc061d PWJ |
2661 | link_cfg_out: |
2662 | return ret; | |
2663 | } | |
2664 | ||
e8e26350 PW |
2665 | #define IXGBE_MAX_RX_DESC_POLL 10 |
2666 | static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter, | |
2667 | int rxr) | |
2668 | { | |
2669 | int j = adapter->rx_ring[rxr].reg_idx; | |
2670 | int k; | |
2671 | ||
2672 | for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) { | |
2673 | if (IXGBE_READ_REG(&adapter->hw, | |
2674 | IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE) | |
2675 | break; | |
2676 | else | |
2677 | msleep(1); | |
2678 | } | |
2679 | if (k >= IXGBE_MAX_RX_DESC_POLL) { | |
2680 | DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d " | |
2681 | "not set within the polling period\n", rxr); | |
2682 | } | |
2683 | ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr], | |
2684 | (adapter->rx_ring[rxr].count - 1)); | |
2685 | } | |
2686 | ||
9a799d71 AK |
2687 | static int ixgbe_up_complete(struct ixgbe_adapter *adapter) |
2688 | { | |
2689 | struct net_device *netdev = adapter->netdev; | |
9a799d71 | 2690 | struct ixgbe_hw *hw = &adapter->hw; |
021230d4 | 2691 | int i, j = 0; |
e8e26350 | 2692 | int num_rx_rings = adapter->num_rx_queues; |
0ecc061d | 2693 | int err; |
9a799d71 | 2694 | int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; |
021230d4 | 2695 | u32 txdctl, rxdctl, mhadd; |
e8e26350 | 2696 | u32 dmatxctl; |
021230d4 | 2697 | u32 gpie; |
9a799d71 | 2698 | |
5eba3699 AV |
2699 | ixgbe_get_hw_control(adapter); |
2700 | ||
021230d4 AV |
2701 | if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) || |
2702 | (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) { | |
9a799d71 AK |
2703 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
2704 | gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME | | |
b4617240 | 2705 | IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD); |
9a799d71 AK |
2706 | } else { |
2707 | /* MSI only */ | |
021230d4 | 2708 | gpie = 0; |
9a799d71 | 2709 | } |
021230d4 AV |
2710 | /* XXX: to interrupt immediately for EICS writes, enable this */ |
2711 | /* gpie |= IXGBE_GPIE_EIMEN; */ | |
2712 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
9a799d71 AK |
2713 | } |
2714 | ||
9b471446 JB |
2715 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
2716 | /* | |
2717 | * use EIAM to auto-mask when MSI-X interrupt is asserted | |
2718 | * this saves a register write for every interrupt | |
2719 | */ | |
2720 | switch (hw->mac.type) { | |
2721 | case ixgbe_mac_82598EB: | |
2722 | IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); | |
2723 | break; | |
2724 | default: | |
2725 | case ixgbe_mac_82599EB: | |
2726 | IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); | |
2727 | IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); | |
2728 | break; | |
2729 | } | |
2730 | } else { | |
021230d4 AV |
2731 | /* legacy interrupts, use EIAM to auto-mask when reading EICR, |
2732 | * specifically only auto mask tx and rx interrupts */ | |
2733 | IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); | |
2734 | } | |
9a799d71 | 2735 | |
0befdb3e JB |
2736 | /* Enable fan failure interrupt if media type is copper */ |
2737 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
2738 | gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); | |
2739 | gpie |= IXGBE_SDP1_GPIEN; | |
2740 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
2741 | } | |
2742 | ||
e8e26350 PW |
2743 | if (hw->mac.type == ixgbe_mac_82599EB) { |
2744 | gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); | |
2745 | gpie |= IXGBE_SDP1_GPIEN; | |
2746 | gpie |= IXGBE_SDP2_GPIEN; | |
2747 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
2748 | } | |
2749 | ||
63f39bd1 YZ |
2750 | #ifdef IXGBE_FCOE |
2751 | /* adjust max frame to be able to do baby jumbo for FCoE */ | |
f34c5c82 | 2752 | if ((netdev->features & NETIF_F_FCOE_MTU) && |
63f39bd1 YZ |
2753 | (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE)) |
2754 | max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE; | |
2755 | ||
2756 | #endif /* IXGBE_FCOE */ | |
021230d4 | 2757 | mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); |
9a799d71 AK |
2758 | if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) { |
2759 | mhadd &= ~IXGBE_MHADD_MFS_MASK; | |
2760 | mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT; | |
2761 | ||
2762 | IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); | |
2763 | } | |
2764 | ||
2765 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
021230d4 AV |
2766 | j = adapter->tx_ring[i].reg_idx; |
2767 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)); | |
e01c31a5 JB |
2768 | /* enable WTHRESH=8 descriptors, to encourage burst writeback */ |
2769 | txdctl |= (8 << 16); | |
e8e26350 PW |
2770 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl); |
2771 | } | |
2772 | ||
2773 | if (hw->mac.type == ixgbe_mac_82599EB) { | |
2774 | /* DMATXCTL.EN must be set after all Tx queue config is done */ | |
2775 | dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); | |
2776 | dmatxctl |= IXGBE_DMATXCTL_TE; | |
2777 | IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl); | |
2778 | } | |
2779 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
2780 | j = adapter->tx_ring[i].reg_idx; | |
2781 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)); | |
9a799d71 | 2782 | txdctl |= IXGBE_TXDCTL_ENABLE; |
021230d4 | 2783 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl); |
9a799d71 AK |
2784 | } |
2785 | ||
e8e26350 | 2786 | for (i = 0; i < num_rx_rings; i++) { |
021230d4 AV |
2787 | j = adapter->rx_ring[i].reg_idx; |
2788 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); | |
2789 | /* enable PTHRESH=32 descriptors (half the internal cache) | |
2790 | * and HTHRESH=0 descriptors (to minimize latency on fetch), | |
2791 | * this also removes a pesky rx_no_buffer_count increment */ | |
2792 | rxdctl |= 0x0020; | |
9a799d71 | 2793 | rxdctl |= IXGBE_RXDCTL_ENABLE; |
021230d4 | 2794 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl); |
e8e26350 PW |
2795 | if (hw->mac.type == ixgbe_mac_82599EB) |
2796 | ixgbe_rx_desc_queue_enable(adapter, i); | |
9a799d71 AK |
2797 | } |
2798 | /* enable all receives */ | |
2799 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); | |
e8e26350 PW |
2800 | if (hw->mac.type == ixgbe_mac_82598EB) |
2801 | rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN); | |
2802 | else | |
2803 | rxdctl |= IXGBE_RXCTRL_RXEN; | |
2804 | hw->mac.ops.enable_rx_dma(hw, rxdctl); | |
9a799d71 AK |
2805 | |
2806 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) | |
2807 | ixgbe_configure_msix(adapter); | |
2808 | else | |
2809 | ixgbe_configure_msi_and_legacy(adapter); | |
2810 | ||
2811 | clear_bit(__IXGBE_DOWN, &adapter->state); | |
021230d4 AV |
2812 | ixgbe_napi_enable_all(adapter); |
2813 | ||
2814 | /* clear any pending interrupts, may auto mask */ | |
2815 | IXGBE_READ_REG(hw, IXGBE_EICR); | |
2816 | ||
9a799d71 AK |
2817 | ixgbe_irq_enable(adapter); |
2818 | ||
bf069c97 DS |
2819 | /* |
2820 | * If this adapter has a fan, check to see if we had a failure | |
2821 | * before we enabled the interrupt. | |
2822 | */ | |
2823 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
2824 | u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); | |
2825 | if (esdp & IXGBE_ESDP_SDP1) | |
2826 | DPRINTK(DRV, CRIT, | |
2827 | "Fan has stopped, replace the adapter\n"); | |
2828 | } | |
2829 | ||
e8e26350 PW |
2830 | /* |
2831 | * For hot-pluggable SFP+ devices, a new SFP+ module may have | |
19343de2 DS |
2832 | * arrived before interrupts were enabled but after probe. Such |
2833 | * devices wouldn't have their type identified yet. We need to | |
2834 | * kick off the SFP+ module setup first, then try to bring up link. | |
e8e26350 PW |
2835 | * If we're not hot-pluggable SFP+, we just need to configure link |
2836 | * and bring it up. | |
2837 | */ | |
19343de2 DS |
2838 | if (hw->phy.type == ixgbe_phy_unknown) { |
2839 | err = hw->phy.ops.identify(hw); | |
2840 | if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
5da43c1a DS |
2841 | /* |
2842 | * Take the device down and schedule the sfp tasklet | |
2843 | * which will unregister_netdev and log it. | |
2844 | */ | |
19343de2 | 2845 | ixgbe_down(adapter); |
5da43c1a | 2846 | schedule_work(&adapter->sfp_config_module_task); |
19343de2 DS |
2847 | return err; |
2848 | } | |
e8e26350 PW |
2849 | } |
2850 | ||
2851 | if (ixgbe_is_sfp(hw)) { | |
2852 | ixgbe_sfp_link_config(adapter); | |
2853 | } else { | |
2854 | err = ixgbe_non_sfp_link_config(hw); | |
2855 | if (err) | |
2856 | DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err); | |
2857 | } | |
0ecc061d | 2858 | |
c4cf55e5 PWJ |
2859 | for (i = 0; i < adapter->num_tx_queues; i++) |
2860 | set_bit(__IXGBE_FDIR_INIT_DONE, | |
2861 | &(adapter->tx_ring[i].reinit_state)); | |
2862 | ||
1da100bb PWJ |
2863 | /* enable transmits */ |
2864 | netif_tx_start_all_queues(netdev); | |
2865 | ||
9a799d71 AK |
2866 | /* bring the link up in the watchdog, this could race with our first |
2867 | * link up interrupt but shouldn't be a problem */ | |
cf8280ee JB |
2868 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; |
2869 | adapter->link_check_timeout = jiffies; | |
9a799d71 AK |
2870 | mod_timer(&adapter->watchdog_timer, jiffies); |
2871 | return 0; | |
2872 | } | |
2873 | ||
d4f80882 AV |
2874 | void ixgbe_reinit_locked(struct ixgbe_adapter *adapter) |
2875 | { | |
2876 | WARN_ON(in_interrupt()); | |
2877 | while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) | |
2878 | msleep(1); | |
2879 | ixgbe_down(adapter); | |
2880 | ixgbe_up(adapter); | |
2881 | clear_bit(__IXGBE_RESETTING, &adapter->state); | |
2882 | } | |
2883 | ||
9a799d71 AK |
2884 | int ixgbe_up(struct ixgbe_adapter *adapter) |
2885 | { | |
2886 | /* hardware has been reset, we need to reload some things */ | |
2887 | ixgbe_configure(adapter); | |
2888 | ||
2889 | return ixgbe_up_complete(adapter); | |
2890 | } | |
2891 | ||
2892 | void ixgbe_reset(struct ixgbe_adapter *adapter) | |
2893 | { | |
c44ade9e | 2894 | struct ixgbe_hw *hw = &adapter->hw; |
8ca783ab DS |
2895 | int err; |
2896 | ||
2897 | err = hw->mac.ops.init_hw(hw); | |
da4dd0f7 PWJ |
2898 | switch (err) { |
2899 | case 0: | |
2900 | case IXGBE_ERR_SFP_NOT_PRESENT: | |
2901 | break; | |
2902 | case IXGBE_ERR_MASTER_REQUESTS_PENDING: | |
2903 | dev_err(&adapter->pdev->dev, "master disable timed out\n"); | |
2904 | break; | |
794caeb2 PWJ |
2905 | case IXGBE_ERR_EEPROM_VERSION: |
2906 | /* We are running on a pre-production device, log a warning */ | |
2907 | dev_warn(&adapter->pdev->dev, "This device is a pre-production " | |
2908 | "adapter/LOM. Please be aware there may be issues " | |
2909 | "associated with your hardware. If you are " | |
2910 | "experiencing problems please contact your Intel or " | |
2911 | "hardware representative who provided you with this " | |
2912 | "hardware.\n"); | |
2913 | break; | |
da4dd0f7 PWJ |
2914 | default: |
2915 | dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err); | |
2916 | } | |
9a799d71 AK |
2917 | |
2918 | /* reprogram the RAR[0] in case user changed it. */ | |
c44ade9e | 2919 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); |
9a799d71 AK |
2920 | } |
2921 | ||
9a799d71 AK |
2922 | /** |
2923 | * ixgbe_clean_rx_ring - Free Rx Buffers per Queue | |
2924 | * @adapter: board private structure | |
2925 | * @rx_ring: ring to free buffers from | |
2926 | **/ | |
2927 | static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter, | |
b4617240 | 2928 | struct ixgbe_ring *rx_ring) |
9a799d71 AK |
2929 | { |
2930 | struct pci_dev *pdev = adapter->pdev; | |
2931 | unsigned long size; | |
2932 | unsigned int i; | |
2933 | ||
2934 | /* Free all the Rx ring sk_buffs */ | |
2935 | ||
2936 | for (i = 0; i < rx_ring->count; i++) { | |
2937 | struct ixgbe_rx_buffer *rx_buffer_info; | |
2938 | ||
2939 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; | |
2940 | if (rx_buffer_info->dma) { | |
2941 | pci_unmap_single(pdev, rx_buffer_info->dma, | |
b4617240 PW |
2942 | rx_ring->rx_buf_len, |
2943 | PCI_DMA_FROMDEVICE); | |
9a799d71 AK |
2944 | rx_buffer_info->dma = 0; |
2945 | } | |
2946 | if (rx_buffer_info->skb) { | |
f8212f97 | 2947 | struct sk_buff *skb = rx_buffer_info->skb; |
9a799d71 | 2948 | rx_buffer_info->skb = NULL; |
f8212f97 AD |
2949 | do { |
2950 | struct sk_buff *this = skb; | |
2951 | skb = skb->prev; | |
2952 | dev_kfree_skb(this); | |
2953 | } while (skb); | |
9a799d71 AK |
2954 | } |
2955 | if (!rx_buffer_info->page) | |
2956 | continue; | |
4f57ca6e JB |
2957 | if (rx_buffer_info->page_dma) { |
2958 | pci_unmap_page(pdev, rx_buffer_info->page_dma, | |
2959 | PAGE_SIZE / 2, PCI_DMA_FROMDEVICE); | |
2960 | rx_buffer_info->page_dma = 0; | |
2961 | } | |
9a799d71 AK |
2962 | put_page(rx_buffer_info->page); |
2963 | rx_buffer_info->page = NULL; | |
762f4c57 | 2964 | rx_buffer_info->page_offset = 0; |
9a799d71 AK |
2965 | } |
2966 | ||
2967 | size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; | |
2968 | memset(rx_ring->rx_buffer_info, 0, size); | |
2969 | ||
2970 | /* Zero out the descriptor ring */ | |
2971 | memset(rx_ring->desc, 0, rx_ring->size); | |
2972 | ||
2973 | rx_ring->next_to_clean = 0; | |
2974 | rx_ring->next_to_use = 0; | |
2975 | ||
9891ca7c JB |
2976 | if (rx_ring->head) |
2977 | writel(0, adapter->hw.hw_addr + rx_ring->head); | |
2978 | if (rx_ring->tail) | |
2979 | writel(0, adapter->hw.hw_addr + rx_ring->tail); | |
9a799d71 AK |
2980 | } |
2981 | ||
2982 | /** | |
2983 | * ixgbe_clean_tx_ring - Free Tx Buffers | |
2984 | * @adapter: board private structure | |
2985 | * @tx_ring: ring to be cleaned | |
2986 | **/ | |
2987 | static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter, | |
b4617240 | 2988 | struct ixgbe_ring *tx_ring) |
9a799d71 AK |
2989 | { |
2990 | struct ixgbe_tx_buffer *tx_buffer_info; | |
2991 | unsigned long size; | |
2992 | unsigned int i; | |
2993 | ||
2994 | /* Free all the Tx ring sk_buffs */ | |
2995 | ||
2996 | for (i = 0; i < tx_ring->count; i++) { | |
2997 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
2998 | ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info); | |
2999 | } | |
3000 | ||
3001 | size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; | |
3002 | memset(tx_ring->tx_buffer_info, 0, size); | |
3003 | ||
3004 | /* Zero out the descriptor ring */ | |
3005 | memset(tx_ring->desc, 0, tx_ring->size); | |
3006 | ||
3007 | tx_ring->next_to_use = 0; | |
3008 | tx_ring->next_to_clean = 0; | |
3009 | ||
9891ca7c JB |
3010 | if (tx_ring->head) |
3011 | writel(0, adapter->hw.hw_addr + tx_ring->head); | |
3012 | if (tx_ring->tail) | |
3013 | writel(0, adapter->hw.hw_addr + tx_ring->tail); | |
9a799d71 AK |
3014 | } |
3015 | ||
3016 | /** | |
021230d4 | 3017 | * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues |
9a799d71 AK |
3018 | * @adapter: board private structure |
3019 | **/ | |
021230d4 | 3020 | static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter) |
9a799d71 AK |
3021 | { |
3022 | int i; | |
3023 | ||
021230d4 AV |
3024 | for (i = 0; i < adapter->num_rx_queues; i++) |
3025 | ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]); | |
9a799d71 AK |
3026 | } |
3027 | ||
3028 | /** | |
021230d4 | 3029 | * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues |
9a799d71 AK |
3030 | * @adapter: board private structure |
3031 | **/ | |
021230d4 | 3032 | static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter) |
9a799d71 AK |
3033 | { |
3034 | int i; | |
3035 | ||
021230d4 AV |
3036 | for (i = 0; i < adapter->num_tx_queues; i++) |
3037 | ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]); | |
9a799d71 AK |
3038 | } |
3039 | ||
3040 | void ixgbe_down(struct ixgbe_adapter *adapter) | |
3041 | { | |
3042 | struct net_device *netdev = adapter->netdev; | |
7f821875 | 3043 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 | 3044 | u32 rxctrl; |
7f821875 JB |
3045 | u32 txdctl; |
3046 | int i, j; | |
9a799d71 AK |
3047 | |
3048 | /* signal that we are down to the interrupt handler */ | |
3049 | set_bit(__IXGBE_DOWN, &adapter->state); | |
3050 | ||
3051 | /* disable receives */ | |
7f821875 JB |
3052 | rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); |
3053 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); | |
9a799d71 AK |
3054 | |
3055 | netif_tx_disable(netdev); | |
3056 | ||
7f821875 | 3057 | IXGBE_WRITE_FLUSH(hw); |
9a799d71 AK |
3058 | msleep(10); |
3059 | ||
7f821875 JB |
3060 | netif_tx_stop_all_queues(netdev); |
3061 | ||
9a799d71 AK |
3062 | ixgbe_irq_disable(adapter); |
3063 | ||
021230d4 | 3064 | ixgbe_napi_disable_all(adapter); |
7f821875 | 3065 | |
0a1f87cb DS |
3066 | clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); |
3067 | del_timer_sync(&adapter->sfp_timer); | |
9a799d71 | 3068 | del_timer_sync(&adapter->watchdog_timer); |
cf8280ee | 3069 | cancel_work_sync(&adapter->watchdog_task); |
9a799d71 | 3070 | |
c4cf55e5 PWJ |
3071 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || |
3072 | adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) | |
3073 | cancel_work_sync(&adapter->fdir_reinit_task); | |
3074 | ||
7f821875 JB |
3075 | /* disable transmits in the hardware now that interrupts are off */ |
3076 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
3077 | j = adapter->tx_ring[i].reg_idx; | |
3078 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)); | |
3079 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), | |
3080 | (txdctl & ~IXGBE_TXDCTL_ENABLE)); | |
3081 | } | |
88512539 PW |
3082 | /* Disable the Tx DMA engine on 82599 */ |
3083 | if (hw->mac.type == ixgbe_mac_82599EB) | |
3084 | IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, | |
3085 | (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) & | |
3086 | ~IXGBE_DMATXCTL_TE)); | |
7f821875 | 3087 | |
9a799d71 | 3088 | netif_carrier_off(netdev); |
9a799d71 | 3089 | |
6f4a0e45 PL |
3090 | if (!pci_channel_offline(adapter->pdev)) |
3091 | ixgbe_reset(adapter); | |
9a799d71 AK |
3092 | ixgbe_clean_all_tx_rings(adapter); |
3093 | ixgbe_clean_all_rx_rings(adapter); | |
3094 | ||
5dd2d332 | 3095 | #ifdef CONFIG_IXGBE_DCA |
96b0e0f6 | 3096 | /* since we reset the hardware DCA settings were cleared */ |
e35ec126 | 3097 | ixgbe_setup_dca(adapter); |
96b0e0f6 | 3098 | #endif |
9a799d71 AK |
3099 | } |
3100 | ||
9a799d71 | 3101 | /** |
021230d4 AV |
3102 | * ixgbe_poll - NAPI Rx polling callback |
3103 | * @napi: structure for representing this polling device | |
3104 | * @budget: how many packets driver is allowed to clean | |
3105 | * | |
3106 | * This function is used for legacy and MSI, NAPI mode | |
9a799d71 | 3107 | **/ |
021230d4 | 3108 | static int ixgbe_poll(struct napi_struct *napi, int budget) |
9a799d71 | 3109 | { |
9a1a69ad JB |
3110 | struct ixgbe_q_vector *q_vector = |
3111 | container_of(napi, struct ixgbe_q_vector, napi); | |
021230d4 | 3112 | struct ixgbe_adapter *adapter = q_vector->adapter; |
9a1a69ad | 3113 | int tx_clean_complete, work_done = 0; |
9a799d71 | 3114 | |
5dd2d332 | 3115 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
3116 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { |
3117 | ixgbe_update_tx_dca(adapter, adapter->tx_ring); | |
3118 | ixgbe_update_rx_dca(adapter, adapter->rx_ring); | |
3119 | } | |
3120 | #endif | |
3121 | ||
fe49f04a | 3122 | tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring); |
78b6f4ce | 3123 | ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget); |
9a799d71 | 3124 | |
9a1a69ad | 3125 | if (!tx_clean_complete) |
d2c7ddd6 DM |
3126 | work_done = budget; |
3127 | ||
53e52c72 DM |
3128 | /* If budget not fully consumed, exit the polling mode */ |
3129 | if (work_done < budget) { | |
288379f0 | 3130 | napi_complete(napi); |
f7554a2b | 3131 | if (adapter->rx_itr_setting & 1) |
f494e8fa | 3132 | ixgbe_set_itr(adapter); |
d4f80882 | 3133 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
835462fc | 3134 | ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE); |
9a799d71 | 3135 | } |
9a799d71 AK |
3136 | return work_done; |
3137 | } | |
3138 | ||
3139 | /** | |
3140 | * ixgbe_tx_timeout - Respond to a Tx Hang | |
3141 | * @netdev: network interface device structure | |
3142 | **/ | |
3143 | static void ixgbe_tx_timeout(struct net_device *netdev) | |
3144 | { | |
3145 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3146 | ||
3147 | /* Do the reset outside of interrupt context */ | |
3148 | schedule_work(&adapter->reset_task); | |
3149 | } | |
3150 | ||
3151 | static void ixgbe_reset_task(struct work_struct *work) | |
3152 | { | |
3153 | struct ixgbe_adapter *adapter; | |
3154 | adapter = container_of(work, struct ixgbe_adapter, reset_task); | |
3155 | ||
2f90b865 AD |
3156 | /* If we're already down or resetting, just bail */ |
3157 | if (test_bit(__IXGBE_DOWN, &adapter->state) || | |
3158 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
3159 | return; | |
3160 | ||
9a799d71 AK |
3161 | adapter->tx_timeout_count++; |
3162 | ||
d4f80882 | 3163 | ixgbe_reinit_locked(adapter); |
9a799d71 AK |
3164 | } |
3165 | ||
bc97114d PWJ |
3166 | #ifdef CONFIG_IXGBE_DCB |
3167 | static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter) | |
b9804972 | 3168 | { |
bc97114d | 3169 | bool ret = false; |
0cefafad | 3170 | struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB]; |
b9804972 | 3171 | |
0cefafad JB |
3172 | if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) |
3173 | return ret; | |
3174 | ||
3175 | f->mask = 0x7 << 3; | |
3176 | adapter->num_rx_queues = f->indices; | |
3177 | adapter->num_tx_queues = f->indices; | |
3178 | ret = true; | |
2f90b865 | 3179 | |
bc97114d PWJ |
3180 | return ret; |
3181 | } | |
3182 | #endif | |
3183 | ||
4df10466 JB |
3184 | /** |
3185 | * ixgbe_set_rss_queues: Allocate queues for RSS | |
3186 | * @adapter: board private structure to initialize | |
3187 | * | |
3188 | * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try | |
3189 | * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU. | |
3190 | * | |
3191 | **/ | |
bc97114d PWJ |
3192 | static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter) |
3193 | { | |
3194 | bool ret = false; | |
0cefafad | 3195 | struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS]; |
bc97114d PWJ |
3196 | |
3197 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { | |
0cefafad JB |
3198 | f->mask = 0xF; |
3199 | adapter->num_rx_queues = f->indices; | |
3200 | adapter->num_tx_queues = f->indices; | |
bc97114d PWJ |
3201 | ret = true; |
3202 | } else { | |
bc97114d | 3203 | ret = false; |
b9804972 JB |
3204 | } |
3205 | ||
bc97114d PWJ |
3206 | return ret; |
3207 | } | |
3208 | ||
c4cf55e5 PWJ |
3209 | /** |
3210 | * ixgbe_set_fdir_queues: Allocate queues for Flow Director | |
3211 | * @adapter: board private structure to initialize | |
3212 | * | |
3213 | * Flow Director is an advanced Rx filter, attempting to get Rx flows back | |
3214 | * to the original CPU that initiated the Tx session. This runs in addition | |
3215 | * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the | |
3216 | * Rx load across CPUs using RSS. | |
3217 | * | |
3218 | **/ | |
3219 | static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter) | |
3220 | { | |
3221 | bool ret = false; | |
3222 | struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR]; | |
3223 | ||
3224 | f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices); | |
3225 | f_fdir->mask = 0; | |
3226 | ||
3227 | /* Flow Director must have RSS enabled */ | |
3228 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED && | |
3229 | ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || | |
3230 | (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) { | |
3231 | adapter->num_tx_queues = f_fdir->indices; | |
3232 | adapter->num_rx_queues = f_fdir->indices; | |
3233 | ret = true; | |
3234 | } else { | |
3235 | adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
3236 | adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; | |
3237 | } | |
3238 | return ret; | |
3239 | } | |
3240 | ||
0331a832 YZ |
3241 | #ifdef IXGBE_FCOE |
3242 | /** | |
3243 | * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE) | |
3244 | * @adapter: board private structure to initialize | |
3245 | * | |
3246 | * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges. | |
3247 | * The ring feature mask is not used as a mask for FCoE, as it can take any 8 | |
3248 | * rx queues out of the max number of rx queues, instead, it is used as the | |
3249 | * index of the first rx queue used by FCoE. | |
3250 | * | |
3251 | **/ | |
3252 | static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter) | |
3253 | { | |
3254 | bool ret = false; | |
3255 | struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE]; | |
3256 | ||
3257 | f->indices = min((int)num_online_cpus(), f->indices); | |
3258 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { | |
8de8b2e6 YZ |
3259 | adapter->num_rx_queues = 1; |
3260 | adapter->num_tx_queues = 1; | |
0331a832 YZ |
3261 | #ifdef CONFIG_IXGBE_DCB |
3262 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
8de8b2e6 | 3263 | DPRINTK(PROBE, INFO, "FCoE enabled with DCB \n"); |
0331a832 YZ |
3264 | ixgbe_set_dcb_queues(adapter); |
3265 | } | |
3266 | #endif | |
3267 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { | |
8de8b2e6 | 3268 | DPRINTK(PROBE, INFO, "FCoE enabled with RSS \n"); |
8faa2a78 YZ |
3269 | if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) || |
3270 | (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) | |
3271 | ixgbe_set_fdir_queues(adapter); | |
3272 | else | |
3273 | ixgbe_set_rss_queues(adapter); | |
0331a832 YZ |
3274 | } |
3275 | /* adding FCoE rx rings to the end */ | |
3276 | f->mask = adapter->num_rx_queues; | |
3277 | adapter->num_rx_queues += f->indices; | |
8de8b2e6 | 3278 | adapter->num_tx_queues += f->indices; |
0331a832 YZ |
3279 | |
3280 | ret = true; | |
3281 | } | |
3282 | ||
3283 | return ret; | |
3284 | } | |
3285 | ||
3286 | #endif /* IXGBE_FCOE */ | |
4df10466 JB |
3287 | /* |
3288 | * ixgbe_set_num_queues: Allocate queues for device, feature dependant | |
3289 | * @adapter: board private structure to initialize | |
3290 | * | |
3291 | * This is the top level queue allocation routine. The order here is very | |
3292 | * important, starting with the "most" number of features turned on at once, | |
3293 | * and ending with the smallest set of features. This way large combinations | |
3294 | * can be allocated if they're turned on, and smaller combinations are the | |
3295 | * fallthrough conditions. | |
3296 | * | |
3297 | **/ | |
bc97114d PWJ |
3298 | static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter) |
3299 | { | |
0331a832 YZ |
3300 | #ifdef IXGBE_FCOE |
3301 | if (ixgbe_set_fcoe_queues(adapter)) | |
3302 | goto done; | |
3303 | ||
3304 | #endif /* IXGBE_FCOE */ | |
bc97114d PWJ |
3305 | #ifdef CONFIG_IXGBE_DCB |
3306 | if (ixgbe_set_dcb_queues(adapter)) | |
af22ab1b | 3307 | goto done; |
bc97114d PWJ |
3308 | |
3309 | #endif | |
c4cf55e5 PWJ |
3310 | if (ixgbe_set_fdir_queues(adapter)) |
3311 | goto done; | |
3312 | ||
bc97114d | 3313 | if (ixgbe_set_rss_queues(adapter)) |
af22ab1b WF |
3314 | goto done; |
3315 | ||
3316 | /* fallback to base case */ | |
3317 | adapter->num_rx_queues = 1; | |
3318 | adapter->num_tx_queues = 1; | |
3319 | ||
3320 | done: | |
3321 | /* Notify the stack of the (possibly) reduced Tx Queue count. */ | |
3322 | adapter->netdev->real_num_tx_queues = adapter->num_tx_queues; | |
b9804972 JB |
3323 | } |
3324 | ||
021230d4 | 3325 | static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter, |
b4617240 | 3326 | int vectors) |
021230d4 AV |
3327 | { |
3328 | int err, vector_threshold; | |
3329 | ||
3330 | /* We'll want at least 3 (vector_threshold): | |
3331 | * 1) TxQ[0] Cleanup | |
3332 | * 2) RxQ[0] Cleanup | |
3333 | * 3) Other (Link Status Change, etc.) | |
3334 | * 4) TCP Timer (optional) | |
3335 | */ | |
3336 | vector_threshold = MIN_MSIX_COUNT; | |
3337 | ||
3338 | /* The more we get, the more we will assign to Tx/Rx Cleanup | |
3339 | * for the separate queues...where Rx Cleanup >= Tx Cleanup. | |
3340 | * Right now, we simply care about how many we'll get; we'll | |
3341 | * set them up later while requesting irq's. | |
3342 | */ | |
3343 | while (vectors >= vector_threshold) { | |
3344 | err = pci_enable_msix(adapter->pdev, adapter->msix_entries, | |
b4617240 | 3345 | vectors); |
021230d4 AV |
3346 | if (!err) /* Success in acquiring all requested vectors. */ |
3347 | break; | |
3348 | else if (err < 0) | |
3349 | vectors = 0; /* Nasty failure, quit now */ | |
3350 | else /* err == number of vectors we should try again with */ | |
3351 | vectors = err; | |
3352 | } | |
3353 | ||
3354 | if (vectors < vector_threshold) { | |
3355 | /* Can't allocate enough MSI-X interrupts? Oh well. | |
3356 | * This just means we'll go with either a single MSI | |
3357 | * vector or fall back to legacy interrupts. | |
3358 | */ | |
3359 | DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n"); | |
3360 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; | |
3361 | kfree(adapter->msix_entries); | |
3362 | adapter->msix_entries = NULL; | |
021230d4 AV |
3363 | } else { |
3364 | adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */ | |
eb7f139c PWJ |
3365 | /* |
3366 | * Adjust for only the vectors we'll use, which is minimum | |
3367 | * of max_msix_q_vectors + NON_Q_VECTORS, or the number of | |
3368 | * vectors we were allocated. | |
3369 | */ | |
3370 | adapter->num_msix_vectors = min(vectors, | |
3371 | adapter->max_msix_q_vectors + NON_Q_VECTORS); | |
021230d4 AV |
3372 | } |
3373 | } | |
3374 | ||
021230d4 | 3375 | /** |
bc97114d | 3376 | * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS |
021230d4 AV |
3377 | * @adapter: board private structure to initialize |
3378 | * | |
bc97114d PWJ |
3379 | * Cache the descriptor ring offsets for RSS to the assigned rings. |
3380 | * | |
021230d4 | 3381 | **/ |
bc97114d | 3382 | static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter) |
021230d4 | 3383 | { |
bc97114d PWJ |
3384 | int i; |
3385 | bool ret = false; | |
3386 | ||
3387 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { | |
3388 | for (i = 0; i < adapter->num_rx_queues; i++) | |
3389 | adapter->rx_ring[i].reg_idx = i; | |
3390 | for (i = 0; i < adapter->num_tx_queues; i++) | |
3391 | adapter->tx_ring[i].reg_idx = i; | |
3392 | ret = true; | |
3393 | } else { | |
3394 | ret = false; | |
3395 | } | |
3396 | ||
3397 | return ret; | |
3398 | } | |
3399 | ||
3400 | #ifdef CONFIG_IXGBE_DCB | |
3401 | /** | |
3402 | * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB | |
3403 | * @adapter: board private structure to initialize | |
3404 | * | |
3405 | * Cache the descriptor ring offsets for DCB to the assigned rings. | |
3406 | * | |
3407 | **/ | |
3408 | static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter) | |
3409 | { | |
3410 | int i; | |
3411 | bool ret = false; | |
3412 | int dcb_i = adapter->ring_feature[RING_F_DCB].indices; | |
3413 | ||
3414 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
3415 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { | |
2f90b865 AD |
3416 | /* the number of queues is assumed to be symmetric */ |
3417 | for (i = 0; i < dcb_i; i++) { | |
3418 | adapter->rx_ring[i].reg_idx = i << 3; | |
3419 | adapter->tx_ring[i].reg_idx = i << 2; | |
3420 | } | |
bc97114d | 3421 | ret = true; |
e8e26350 | 3422 | } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { |
f92ef202 PW |
3423 | if (dcb_i == 8) { |
3424 | /* | |
3425 | * Tx TC0 starts at: descriptor queue 0 | |
3426 | * Tx TC1 starts at: descriptor queue 32 | |
3427 | * Tx TC2 starts at: descriptor queue 64 | |
3428 | * Tx TC3 starts at: descriptor queue 80 | |
3429 | * Tx TC4 starts at: descriptor queue 96 | |
3430 | * Tx TC5 starts at: descriptor queue 104 | |
3431 | * Tx TC6 starts at: descriptor queue 112 | |
3432 | * Tx TC7 starts at: descriptor queue 120 | |
3433 | * | |
3434 | * Rx TC0-TC7 are offset by 16 queues each | |
3435 | */ | |
3436 | for (i = 0; i < 3; i++) { | |
3437 | adapter->tx_ring[i].reg_idx = i << 5; | |
3438 | adapter->rx_ring[i].reg_idx = i << 4; | |
3439 | } | |
3440 | for ( ; i < 5; i++) { | |
3441 | adapter->tx_ring[i].reg_idx = | |
3442 | ((i + 2) << 4); | |
3443 | adapter->rx_ring[i].reg_idx = i << 4; | |
3444 | } | |
3445 | for ( ; i < dcb_i; i++) { | |
3446 | adapter->tx_ring[i].reg_idx = | |
3447 | ((i + 8) << 3); | |
3448 | adapter->rx_ring[i].reg_idx = i << 4; | |
3449 | } | |
3450 | ||
3451 | ret = true; | |
3452 | } else if (dcb_i == 4) { | |
3453 | /* | |
3454 | * Tx TC0 starts at: descriptor queue 0 | |
3455 | * Tx TC1 starts at: descriptor queue 64 | |
3456 | * Tx TC2 starts at: descriptor queue 96 | |
3457 | * Tx TC3 starts at: descriptor queue 112 | |
3458 | * | |
3459 | * Rx TC0-TC3 are offset by 32 queues each | |
3460 | */ | |
3461 | adapter->tx_ring[0].reg_idx = 0; | |
3462 | adapter->tx_ring[1].reg_idx = 64; | |
3463 | adapter->tx_ring[2].reg_idx = 96; | |
3464 | adapter->tx_ring[3].reg_idx = 112; | |
3465 | for (i = 0 ; i < dcb_i; i++) | |
3466 | adapter->rx_ring[i].reg_idx = i << 5; | |
3467 | ||
3468 | ret = true; | |
3469 | } else { | |
3470 | ret = false; | |
e8e26350 | 3471 | } |
bc97114d PWJ |
3472 | } else { |
3473 | ret = false; | |
021230d4 | 3474 | } |
bc97114d PWJ |
3475 | } else { |
3476 | ret = false; | |
021230d4 | 3477 | } |
bc97114d PWJ |
3478 | |
3479 | return ret; | |
3480 | } | |
3481 | #endif | |
3482 | ||
c4cf55e5 PWJ |
3483 | /** |
3484 | * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director | |
3485 | * @adapter: board private structure to initialize | |
3486 | * | |
3487 | * Cache the descriptor ring offsets for Flow Director to the assigned rings. | |
3488 | * | |
3489 | **/ | |
3490 | static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter) | |
3491 | { | |
3492 | int i; | |
3493 | bool ret = false; | |
3494 | ||
3495 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED && | |
3496 | ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) || | |
3497 | (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) { | |
3498 | for (i = 0; i < adapter->num_rx_queues; i++) | |
3499 | adapter->rx_ring[i].reg_idx = i; | |
3500 | for (i = 0; i < adapter->num_tx_queues; i++) | |
3501 | adapter->tx_ring[i].reg_idx = i; | |
3502 | ret = true; | |
3503 | } | |
3504 | ||
3505 | return ret; | |
3506 | } | |
3507 | ||
0331a832 YZ |
3508 | #ifdef IXGBE_FCOE |
3509 | /** | |
3510 | * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE | |
3511 | * @adapter: board private structure to initialize | |
3512 | * | |
3513 | * Cache the descriptor ring offsets for FCoE mode to the assigned rings. | |
3514 | * | |
3515 | */ | |
3516 | static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter) | |
3517 | { | |
8de8b2e6 | 3518 | int i, fcoe_rx_i = 0, fcoe_tx_i = 0; |
0331a832 YZ |
3519 | bool ret = false; |
3520 | struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE]; | |
3521 | ||
3522 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { | |
3523 | #ifdef CONFIG_IXGBE_DCB | |
3524 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
8de8b2e6 YZ |
3525 | struct ixgbe_fcoe *fcoe = &adapter->fcoe; |
3526 | ||
0331a832 | 3527 | ixgbe_cache_ring_dcb(adapter); |
8de8b2e6 YZ |
3528 | /* find out queues in TC for FCoE */ |
3529 | fcoe_rx_i = adapter->rx_ring[fcoe->tc].reg_idx + 1; | |
3530 | fcoe_tx_i = adapter->tx_ring[fcoe->tc].reg_idx + 1; | |
3531 | /* | |
3532 | * In 82599, the number of Tx queues for each traffic | |
3533 | * class for both 8-TC and 4-TC modes are: | |
3534 | * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7 | |
3535 | * 8 TCs: 32 32 16 16 8 8 8 8 | |
3536 | * 4 TCs: 64 64 32 32 | |
3537 | * We have max 8 queues for FCoE, where 8 the is | |
3538 | * FCoE redirection table size. If TC for FCoE is | |
3539 | * less than or equal to TC3, we have enough queues | |
3540 | * to add max of 8 queues for FCoE, so we start FCoE | |
3541 | * tx descriptor from the next one, i.e., reg_idx + 1. | |
3542 | * If TC for FCoE is above TC3, implying 8 TC mode, | |
3543 | * and we need 8 for FCoE, we have to take all queues | |
3544 | * in that traffic class for FCoE. | |
3545 | */ | |
3546 | if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3)) | |
3547 | fcoe_tx_i--; | |
0331a832 YZ |
3548 | } |
3549 | #endif /* CONFIG_IXGBE_DCB */ | |
3550 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { | |
8faa2a78 YZ |
3551 | if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) || |
3552 | (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) | |
3553 | ixgbe_cache_ring_fdir(adapter); | |
3554 | else | |
3555 | ixgbe_cache_ring_rss(adapter); | |
3556 | ||
8de8b2e6 YZ |
3557 | fcoe_rx_i = f->mask; |
3558 | fcoe_tx_i = f->mask; | |
3559 | } | |
3560 | for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) { | |
3561 | adapter->rx_ring[f->mask + i].reg_idx = fcoe_rx_i; | |
3562 | adapter->tx_ring[f->mask + i].reg_idx = fcoe_tx_i; | |
0331a832 | 3563 | } |
0331a832 YZ |
3564 | ret = true; |
3565 | } | |
3566 | return ret; | |
3567 | } | |
3568 | ||
3569 | #endif /* IXGBE_FCOE */ | |
bc97114d PWJ |
3570 | /** |
3571 | * ixgbe_cache_ring_register - Descriptor ring to register mapping | |
3572 | * @adapter: board private structure to initialize | |
3573 | * | |
3574 | * Once we know the feature-set enabled for the device, we'll cache | |
3575 | * the register offset the descriptor ring is assigned to. | |
3576 | * | |
3577 | * Note, the order the various feature calls is important. It must start with | |
3578 | * the "most" features enabled at the same time, then trickle down to the | |
3579 | * least amount of features turned on at once. | |
3580 | **/ | |
3581 | static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter) | |
3582 | { | |
3583 | /* start with default case */ | |
3584 | adapter->rx_ring[0].reg_idx = 0; | |
3585 | adapter->tx_ring[0].reg_idx = 0; | |
3586 | ||
0331a832 YZ |
3587 | #ifdef IXGBE_FCOE |
3588 | if (ixgbe_cache_ring_fcoe(adapter)) | |
3589 | return; | |
3590 | ||
3591 | #endif /* IXGBE_FCOE */ | |
bc97114d PWJ |
3592 | #ifdef CONFIG_IXGBE_DCB |
3593 | if (ixgbe_cache_ring_dcb(adapter)) | |
3594 | return; | |
3595 | ||
3596 | #endif | |
c4cf55e5 PWJ |
3597 | if (ixgbe_cache_ring_fdir(adapter)) |
3598 | return; | |
3599 | ||
bc97114d PWJ |
3600 | if (ixgbe_cache_ring_rss(adapter)) |
3601 | return; | |
021230d4 AV |
3602 | } |
3603 | ||
9a799d71 AK |
3604 | /** |
3605 | * ixgbe_alloc_queues - Allocate memory for all rings | |
3606 | * @adapter: board private structure to initialize | |
3607 | * | |
3608 | * We allocate one ring per queue at run-time since we don't know the | |
4df10466 JB |
3609 | * number of queues at compile-time. The polling_netdev array is |
3610 | * intended for Multiqueue, but should work fine with a single queue. | |
9a799d71 | 3611 | **/ |
2f90b865 | 3612 | static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter) |
9a799d71 AK |
3613 | { |
3614 | int i; | |
3615 | ||
3616 | adapter->tx_ring = kcalloc(adapter->num_tx_queues, | |
b4617240 | 3617 | sizeof(struct ixgbe_ring), GFP_KERNEL); |
9a799d71 | 3618 | if (!adapter->tx_ring) |
021230d4 | 3619 | goto err_tx_ring_allocation; |
9a799d71 AK |
3620 | |
3621 | adapter->rx_ring = kcalloc(adapter->num_rx_queues, | |
b4617240 | 3622 | sizeof(struct ixgbe_ring), GFP_KERNEL); |
021230d4 AV |
3623 | if (!adapter->rx_ring) |
3624 | goto err_rx_ring_allocation; | |
9a799d71 | 3625 | |
021230d4 | 3626 | for (i = 0; i < adapter->num_tx_queues; i++) { |
b9804972 | 3627 | adapter->tx_ring[i].count = adapter->tx_ring_count; |
021230d4 AV |
3628 | adapter->tx_ring[i].queue_index = i; |
3629 | } | |
b9804972 | 3630 | |
9a799d71 | 3631 | for (i = 0; i < adapter->num_rx_queues; i++) { |
b9804972 | 3632 | adapter->rx_ring[i].count = adapter->rx_ring_count; |
021230d4 AV |
3633 | adapter->rx_ring[i].queue_index = i; |
3634 | } | |
3635 | ||
3636 | ixgbe_cache_ring_register(adapter); | |
3637 | ||
3638 | return 0; | |
3639 | ||
3640 | err_rx_ring_allocation: | |
3641 | kfree(adapter->tx_ring); | |
3642 | err_tx_ring_allocation: | |
3643 | return -ENOMEM; | |
3644 | } | |
3645 | ||
3646 | /** | |
3647 | * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported | |
3648 | * @adapter: board private structure to initialize | |
3649 | * | |
3650 | * Attempt to configure the interrupts using the best available | |
3651 | * capabilities of the hardware and the kernel. | |
3652 | **/ | |
feea6a57 | 3653 | static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter) |
021230d4 | 3654 | { |
8be0e467 | 3655 | struct ixgbe_hw *hw = &adapter->hw; |
021230d4 AV |
3656 | int err = 0; |
3657 | int vector, v_budget; | |
3658 | ||
3659 | /* | |
3660 | * It's easy to be greedy for MSI-X vectors, but it really | |
3661 | * doesn't do us much good if we have a lot more vectors | |
3662 | * than CPU's. So let's be conservative and only ask for | |
342bde1b | 3663 | * (roughly) the same number of vectors as there are CPU's. |
021230d4 AV |
3664 | */ |
3665 | v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues, | |
342bde1b | 3666 | (int)num_online_cpus()) + NON_Q_VECTORS; |
021230d4 AV |
3667 | |
3668 | /* | |
3669 | * At the same time, hardware can only support a maximum of | |
8be0e467 PW |
3670 | * hw.mac->max_msix_vectors vectors. With features |
3671 | * such as RSS and VMDq, we can easily surpass the number of Rx and Tx | |
3672 | * descriptor queues supported by our device. Thus, we cap it off in | |
3673 | * those rare cases where the cpu count also exceeds our vector limit. | |
021230d4 | 3674 | */ |
8be0e467 | 3675 | v_budget = min(v_budget, (int)hw->mac.max_msix_vectors); |
021230d4 AV |
3676 | |
3677 | /* A failure in MSI-X entry allocation isn't fatal, but it does | |
3678 | * mean we disable MSI-X capabilities of the adapter. */ | |
3679 | adapter->msix_entries = kcalloc(v_budget, | |
b4617240 | 3680 | sizeof(struct msix_entry), GFP_KERNEL); |
7a921c93 AD |
3681 | if (adapter->msix_entries) { |
3682 | for (vector = 0; vector < v_budget; vector++) | |
3683 | adapter->msix_entries[vector].entry = vector; | |
021230d4 | 3684 | |
7a921c93 | 3685 | ixgbe_acquire_msix_vectors(adapter, v_budget); |
021230d4 | 3686 | |
7a921c93 AD |
3687 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
3688 | goto out; | |
3689 | } | |
021230d4 | 3690 | |
7a921c93 AD |
3691 | adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; |
3692 | adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED; | |
c4cf55e5 PWJ |
3693 | adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; |
3694 | adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; | |
3695 | adapter->atr_sample_rate = 0; | |
7a921c93 | 3696 | ixgbe_set_num_queues(adapter); |
021230d4 | 3697 | |
021230d4 AV |
3698 | err = pci_enable_msi(adapter->pdev); |
3699 | if (!err) { | |
3700 | adapter->flags |= IXGBE_FLAG_MSI_ENABLED; | |
3701 | } else { | |
3702 | DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, " | |
b4617240 | 3703 | "falling back to legacy. Error: %d\n", err); |
021230d4 AV |
3704 | /* reset err */ |
3705 | err = 0; | |
3706 | } | |
3707 | ||
3708 | out: | |
021230d4 AV |
3709 | return err; |
3710 | } | |
3711 | ||
7a921c93 AD |
3712 | /** |
3713 | * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors | |
3714 | * @adapter: board private structure to initialize | |
3715 | * | |
3716 | * We allocate one q_vector per queue interrupt. If allocation fails we | |
3717 | * return -ENOMEM. | |
3718 | **/ | |
3719 | static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter) | |
3720 | { | |
3721 | int q_idx, num_q_vectors; | |
3722 | struct ixgbe_q_vector *q_vector; | |
3723 | int napi_vectors; | |
3724 | int (*poll)(struct napi_struct *, int); | |
3725 | ||
3726 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
3727 | num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
3728 | napi_vectors = adapter->num_rx_queues; | |
91281fd3 | 3729 | poll = &ixgbe_clean_rxtx_many; |
7a921c93 AD |
3730 | } else { |
3731 | num_q_vectors = 1; | |
3732 | napi_vectors = 1; | |
3733 | poll = &ixgbe_poll; | |
3734 | } | |
3735 | ||
3736 | for (q_idx = 0; q_idx < num_q_vectors; q_idx++) { | |
3737 | q_vector = kzalloc(sizeof(struct ixgbe_q_vector), GFP_KERNEL); | |
3738 | if (!q_vector) | |
3739 | goto err_out; | |
3740 | q_vector->adapter = adapter; | |
f7554a2b NS |
3741 | if (q_vector->txr_count && !q_vector->rxr_count) |
3742 | q_vector->eitr = adapter->tx_eitr_param; | |
3743 | else | |
3744 | q_vector->eitr = adapter->rx_eitr_param; | |
fe49f04a | 3745 | q_vector->v_idx = q_idx; |
91281fd3 | 3746 | netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64); |
7a921c93 AD |
3747 | adapter->q_vector[q_idx] = q_vector; |
3748 | } | |
3749 | ||
3750 | return 0; | |
3751 | ||
3752 | err_out: | |
3753 | while (q_idx) { | |
3754 | q_idx--; | |
3755 | q_vector = adapter->q_vector[q_idx]; | |
3756 | netif_napi_del(&q_vector->napi); | |
3757 | kfree(q_vector); | |
3758 | adapter->q_vector[q_idx] = NULL; | |
3759 | } | |
3760 | return -ENOMEM; | |
3761 | } | |
3762 | ||
3763 | /** | |
3764 | * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors | |
3765 | * @adapter: board private structure to initialize | |
3766 | * | |
3767 | * This function frees the memory allocated to the q_vectors. In addition if | |
3768 | * NAPI is enabled it will delete any references to the NAPI struct prior | |
3769 | * to freeing the q_vector. | |
3770 | **/ | |
3771 | static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter) | |
3772 | { | |
3773 | int q_idx, num_q_vectors; | |
7a921c93 | 3774 | |
91281fd3 | 3775 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
7a921c93 | 3776 | num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; |
91281fd3 | 3777 | else |
7a921c93 | 3778 | num_q_vectors = 1; |
7a921c93 AD |
3779 | |
3780 | for (q_idx = 0; q_idx < num_q_vectors; q_idx++) { | |
3781 | struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx]; | |
7a921c93 | 3782 | adapter->q_vector[q_idx] = NULL; |
91281fd3 | 3783 | netif_napi_del(&q_vector->napi); |
7a921c93 AD |
3784 | kfree(q_vector); |
3785 | } | |
3786 | } | |
3787 | ||
7b25cdba | 3788 | static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter) |
021230d4 AV |
3789 | { |
3790 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
3791 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; | |
3792 | pci_disable_msix(adapter->pdev); | |
3793 | kfree(adapter->msix_entries); | |
3794 | adapter->msix_entries = NULL; | |
3795 | } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) { | |
3796 | adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED; | |
3797 | pci_disable_msi(adapter->pdev); | |
3798 | } | |
3799 | return; | |
3800 | } | |
3801 | ||
3802 | /** | |
3803 | * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme | |
3804 | * @adapter: board private structure to initialize | |
3805 | * | |
3806 | * We determine which interrupt scheme to use based on... | |
3807 | * - Kernel support (MSI, MSI-X) | |
3808 | * - which can be user-defined (via MODULE_PARAM) | |
3809 | * - Hardware queue count (num_*_queues) | |
3810 | * - defined by miscellaneous hardware support/features (RSS, etc.) | |
3811 | **/ | |
2f90b865 | 3812 | int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter) |
021230d4 AV |
3813 | { |
3814 | int err; | |
3815 | ||
3816 | /* Number of supported queues */ | |
3817 | ixgbe_set_num_queues(adapter); | |
3818 | ||
021230d4 AV |
3819 | err = ixgbe_set_interrupt_capability(adapter); |
3820 | if (err) { | |
3821 | DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n"); | |
3822 | goto err_set_interrupt; | |
9a799d71 AK |
3823 | } |
3824 | ||
7a921c93 AD |
3825 | err = ixgbe_alloc_q_vectors(adapter); |
3826 | if (err) { | |
3827 | DPRINTK(PROBE, ERR, "Unable to allocate memory for queue " | |
3828 | "vectors\n"); | |
3829 | goto err_alloc_q_vectors; | |
3830 | } | |
3831 | ||
3832 | err = ixgbe_alloc_queues(adapter); | |
3833 | if (err) { | |
3834 | DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n"); | |
3835 | goto err_alloc_queues; | |
3836 | } | |
3837 | ||
021230d4 | 3838 | DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, " |
b4617240 PW |
3839 | "Tx Queue count = %u\n", |
3840 | (adapter->num_rx_queues > 1) ? "Enabled" : | |
3841 | "Disabled", adapter->num_rx_queues, adapter->num_tx_queues); | |
021230d4 AV |
3842 | |
3843 | set_bit(__IXGBE_DOWN, &adapter->state); | |
3844 | ||
9a799d71 | 3845 | return 0; |
021230d4 | 3846 | |
7a921c93 AD |
3847 | err_alloc_queues: |
3848 | ixgbe_free_q_vectors(adapter); | |
3849 | err_alloc_q_vectors: | |
3850 | ixgbe_reset_interrupt_capability(adapter); | |
021230d4 | 3851 | err_set_interrupt: |
7a921c93 AD |
3852 | return err; |
3853 | } | |
3854 | ||
3855 | /** | |
3856 | * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings | |
3857 | * @adapter: board private structure to clear interrupt scheme on | |
3858 | * | |
3859 | * We go through and clear interrupt specific resources and reset the structure | |
3860 | * to pre-load conditions | |
3861 | **/ | |
3862 | void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter) | |
3863 | { | |
021230d4 AV |
3864 | kfree(adapter->tx_ring); |
3865 | kfree(adapter->rx_ring); | |
7a921c93 AD |
3866 | adapter->tx_ring = NULL; |
3867 | adapter->rx_ring = NULL; | |
3868 | ||
3869 | ixgbe_free_q_vectors(adapter); | |
3870 | ixgbe_reset_interrupt_capability(adapter); | |
9a799d71 AK |
3871 | } |
3872 | ||
c4900be0 DS |
3873 | /** |
3874 | * ixgbe_sfp_timer - worker thread to find a missing module | |
3875 | * @data: pointer to our adapter struct | |
3876 | **/ | |
3877 | static void ixgbe_sfp_timer(unsigned long data) | |
3878 | { | |
3879 | struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data; | |
3880 | ||
4df10466 JB |
3881 | /* |
3882 | * Do the sfp_timer outside of interrupt context due to the | |
c4900be0 DS |
3883 | * delays that sfp+ detection requires |
3884 | */ | |
3885 | schedule_work(&adapter->sfp_task); | |
3886 | } | |
3887 | ||
3888 | /** | |
3889 | * ixgbe_sfp_task - worker thread to find a missing module | |
3890 | * @work: pointer to work_struct containing our data | |
3891 | **/ | |
3892 | static void ixgbe_sfp_task(struct work_struct *work) | |
3893 | { | |
3894 | struct ixgbe_adapter *adapter = container_of(work, | |
3895 | struct ixgbe_adapter, | |
3896 | sfp_task); | |
3897 | struct ixgbe_hw *hw = &adapter->hw; | |
3898 | ||
3899 | if ((hw->phy.type == ixgbe_phy_nl) && | |
3900 | (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) { | |
3901 | s32 ret = hw->phy.ops.identify_sfp(hw); | |
63d6e1d8 | 3902 | if (ret == IXGBE_ERR_SFP_NOT_PRESENT) |
c4900be0 DS |
3903 | goto reschedule; |
3904 | ret = hw->phy.ops.reset(hw); | |
3905 | if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
88d2b81f DS |
3906 | dev_err(&adapter->pdev->dev, "failed to initialize " |
3907 | "because an unsupported SFP+ module type " | |
3908 | "was detected.\n" | |
3909 | "Reload the driver after installing a " | |
3910 | "supported module.\n"); | |
c4900be0 DS |
3911 | unregister_netdev(adapter->netdev); |
3912 | } else { | |
3913 | DPRINTK(PROBE, INFO, "detected SFP+: %d\n", | |
3914 | hw->phy.sfp_type); | |
3915 | } | |
3916 | /* don't need this routine any more */ | |
3917 | clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); | |
3918 | } | |
3919 | return; | |
3920 | reschedule: | |
3921 | if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state)) | |
3922 | mod_timer(&adapter->sfp_timer, | |
3923 | round_jiffies(jiffies + (2 * HZ))); | |
3924 | } | |
3925 | ||
9a799d71 AK |
3926 | /** |
3927 | * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter) | |
3928 | * @adapter: board private structure to initialize | |
3929 | * | |
3930 | * ixgbe_sw_init initializes the Adapter private data structure. | |
3931 | * Fields are initialized based on PCI device information and | |
3932 | * OS network device settings (MTU size). | |
3933 | **/ | |
3934 | static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter) | |
3935 | { | |
3936 | struct ixgbe_hw *hw = &adapter->hw; | |
3937 | struct pci_dev *pdev = adapter->pdev; | |
021230d4 | 3938 | unsigned int rss; |
7a6b6f51 | 3939 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
3940 | int j; |
3941 | struct tc_configuration *tc; | |
3942 | #endif | |
021230d4 | 3943 | |
c44ade9e JB |
3944 | /* PCI config space info */ |
3945 | ||
3946 | hw->vendor_id = pdev->vendor; | |
3947 | hw->device_id = pdev->device; | |
3948 | hw->revision_id = pdev->revision; | |
3949 | hw->subsystem_vendor_id = pdev->subsystem_vendor; | |
3950 | hw->subsystem_device_id = pdev->subsystem_device; | |
3951 | ||
021230d4 AV |
3952 | /* Set capability flags */ |
3953 | rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus()); | |
3954 | adapter->ring_feature[RING_F_RSS].indices = rss; | |
3955 | adapter->flags |= IXGBE_FLAG_RSS_ENABLED; | |
2f90b865 | 3956 | adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES; |
bf069c97 DS |
3957 | if (hw->mac.type == ixgbe_mac_82598EB) { |
3958 | if (hw->device_id == IXGBE_DEV_ID_82598AT) | |
3959 | adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE; | |
e8e26350 | 3960 | adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598; |
bf069c97 | 3961 | } else if (hw->mac.type == ixgbe_mac_82599EB) { |
e8e26350 | 3962 | adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599; |
0c19d6af PWJ |
3963 | adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE; |
3964 | adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; | |
c4cf55e5 PWJ |
3965 | adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; |
3966 | adapter->ring_feature[RING_F_FDIR].indices = | |
3967 | IXGBE_MAX_FDIR_INDICES; | |
3968 | adapter->atr_sample_rate = 20; | |
3969 | adapter->fdir_pballoc = 0; | |
eacd73f7 | 3970 | #ifdef IXGBE_FCOE |
0d551589 YZ |
3971 | adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE; |
3972 | adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; | |
3973 | adapter->ring_feature[RING_F_FCOE].indices = 0; | |
61a0f421 | 3974 | #ifdef CONFIG_IXGBE_DCB |
6ee16520 YZ |
3975 | /* Default traffic class to use for FCoE */ |
3976 | adapter->fcoe.tc = IXGBE_FCOE_DEFTC; | |
61a0f421 | 3977 | #endif |
eacd73f7 | 3978 | #endif /* IXGBE_FCOE */ |
f8212f97 | 3979 | } |
2f90b865 | 3980 | |
7a6b6f51 | 3981 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
3982 | /* Configure DCB traffic classes */ |
3983 | for (j = 0; j < MAX_TRAFFIC_CLASS; j++) { | |
3984 | tc = &adapter->dcb_cfg.tc_config[j]; | |
3985 | tc->path[DCB_TX_CONFIG].bwg_id = 0; | |
3986 | tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1); | |
3987 | tc->path[DCB_RX_CONFIG].bwg_id = 0; | |
3988 | tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1); | |
3989 | tc->dcb_pfc = pfc_disabled; | |
3990 | } | |
3991 | adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100; | |
3992 | adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100; | |
3993 | adapter->dcb_cfg.rx_pba_cfg = pba_equal; | |
264857b8 | 3994 | adapter->dcb_cfg.pfc_mode_enable = false; |
2f90b865 AD |
3995 | adapter->dcb_cfg.round_robin_enable = false; |
3996 | adapter->dcb_set_bitmap = 0x00; | |
3997 | ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg, | |
3998 | adapter->ring_feature[RING_F_DCB].indices); | |
3999 | ||
4000 | #endif | |
9a799d71 AK |
4001 | |
4002 | /* default flow control settings */ | |
cd7664f6 | 4003 | hw->fc.requested_mode = ixgbe_fc_full; |
71fd570b | 4004 | hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */ |
264857b8 PWJ |
4005 | #ifdef CONFIG_DCB |
4006 | adapter->last_lfc_mode = hw->fc.current_mode; | |
4007 | #endif | |
2b9ade93 JB |
4008 | hw->fc.high_water = IXGBE_DEFAULT_FCRTH; |
4009 | hw->fc.low_water = IXGBE_DEFAULT_FCRTL; | |
4010 | hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE; | |
4011 | hw->fc.send_xon = true; | |
71fd570b | 4012 | hw->fc.disable_fc_autoneg = false; |
9a799d71 | 4013 | |
30efa5a3 | 4014 | /* enable itr by default in dynamic mode */ |
f7554a2b NS |
4015 | adapter->rx_itr_setting = 1; |
4016 | adapter->rx_eitr_param = 20000; | |
4017 | adapter->tx_itr_setting = 1; | |
4018 | adapter->tx_eitr_param = 10000; | |
30efa5a3 JB |
4019 | |
4020 | /* set defaults for eitr in MegaBytes */ | |
4021 | adapter->eitr_low = 10; | |
4022 | adapter->eitr_high = 20; | |
4023 | ||
4024 | /* set default ring sizes */ | |
4025 | adapter->tx_ring_count = IXGBE_DEFAULT_TXD; | |
4026 | adapter->rx_ring_count = IXGBE_DEFAULT_RXD; | |
4027 | ||
9a799d71 | 4028 | /* initialize eeprom parameters */ |
c44ade9e | 4029 | if (ixgbe_init_eeprom_params_generic(hw)) { |
9a799d71 AK |
4030 | dev_err(&pdev->dev, "EEPROM initialization failed\n"); |
4031 | return -EIO; | |
4032 | } | |
4033 | ||
021230d4 | 4034 | /* enable rx csum by default */ |
9a799d71 AK |
4035 | adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED; |
4036 | ||
9a799d71 AK |
4037 | set_bit(__IXGBE_DOWN, &adapter->state); |
4038 | ||
4039 | return 0; | |
4040 | } | |
4041 | ||
4042 | /** | |
4043 | * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors) | |
4044 | * @adapter: board private structure | |
3a581073 | 4045 | * @tx_ring: tx descriptor ring (for a specific queue) to setup |
9a799d71 AK |
4046 | * |
4047 | * Return 0 on success, negative on failure | |
4048 | **/ | |
4049 | int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter, | |
e01c31a5 | 4050 | struct ixgbe_ring *tx_ring) |
9a799d71 AK |
4051 | { |
4052 | struct pci_dev *pdev = adapter->pdev; | |
4053 | int size; | |
4054 | ||
3a581073 JB |
4055 | size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; |
4056 | tx_ring->tx_buffer_info = vmalloc(size); | |
e01c31a5 JB |
4057 | if (!tx_ring->tx_buffer_info) |
4058 | goto err; | |
3a581073 | 4059 | memset(tx_ring->tx_buffer_info, 0, size); |
9a799d71 AK |
4060 | |
4061 | /* round up to nearest 4K */ | |
12207e49 | 4062 | tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc); |
3a581073 | 4063 | tx_ring->size = ALIGN(tx_ring->size, 4096); |
9a799d71 | 4064 | |
3a581073 JB |
4065 | tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size, |
4066 | &tx_ring->dma); | |
e01c31a5 JB |
4067 | if (!tx_ring->desc) |
4068 | goto err; | |
9a799d71 | 4069 | |
3a581073 JB |
4070 | tx_ring->next_to_use = 0; |
4071 | tx_ring->next_to_clean = 0; | |
4072 | tx_ring->work_limit = tx_ring->count; | |
9a799d71 | 4073 | return 0; |
e01c31a5 JB |
4074 | |
4075 | err: | |
4076 | vfree(tx_ring->tx_buffer_info); | |
4077 | tx_ring->tx_buffer_info = NULL; | |
4078 | DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit " | |
4079 | "descriptor ring\n"); | |
4080 | return -ENOMEM; | |
9a799d71 AK |
4081 | } |
4082 | ||
69888674 AD |
4083 | /** |
4084 | * ixgbe_setup_all_tx_resources - allocate all queues Tx resources | |
4085 | * @adapter: board private structure | |
4086 | * | |
4087 | * If this function returns with an error, then it's possible one or | |
4088 | * more of the rings is populated (while the rest are not). It is the | |
4089 | * callers duty to clean those orphaned rings. | |
4090 | * | |
4091 | * Return 0 on success, negative on failure | |
4092 | **/ | |
4093 | static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter) | |
4094 | { | |
4095 | int i, err = 0; | |
4096 | ||
4097 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
4098 | err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]); | |
4099 | if (!err) | |
4100 | continue; | |
4101 | DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i); | |
4102 | break; | |
4103 | } | |
4104 | ||
4105 | return err; | |
4106 | } | |
4107 | ||
9a799d71 AK |
4108 | /** |
4109 | * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors) | |
4110 | * @adapter: board private structure | |
3a581073 | 4111 | * @rx_ring: rx descriptor ring (for a specific queue) to setup |
9a799d71 AK |
4112 | * |
4113 | * Returns 0 on success, negative on failure | |
4114 | **/ | |
4115 | int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter, | |
b4617240 | 4116 | struct ixgbe_ring *rx_ring) |
9a799d71 AK |
4117 | { |
4118 | struct pci_dev *pdev = adapter->pdev; | |
021230d4 | 4119 | int size; |
9a799d71 | 4120 | |
3a581073 JB |
4121 | size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; |
4122 | rx_ring->rx_buffer_info = vmalloc(size); | |
4123 | if (!rx_ring->rx_buffer_info) { | |
9a799d71 | 4124 | DPRINTK(PROBE, ERR, |
b4617240 | 4125 | "vmalloc allocation failed for the rx desc ring\n"); |
177db6ff | 4126 | goto alloc_failed; |
9a799d71 | 4127 | } |
3a581073 | 4128 | memset(rx_ring->rx_buffer_info, 0, size); |
9a799d71 | 4129 | |
9a799d71 | 4130 | /* Round up to nearest 4K */ |
3a581073 JB |
4131 | rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); |
4132 | rx_ring->size = ALIGN(rx_ring->size, 4096); | |
9a799d71 | 4133 | |
3a581073 | 4134 | rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma); |
9a799d71 | 4135 | |
3a581073 | 4136 | if (!rx_ring->desc) { |
9a799d71 | 4137 | DPRINTK(PROBE, ERR, |
b4617240 | 4138 | "Memory allocation failed for the rx desc ring\n"); |
3a581073 | 4139 | vfree(rx_ring->rx_buffer_info); |
177db6ff | 4140 | goto alloc_failed; |
9a799d71 AK |
4141 | } |
4142 | ||
3a581073 JB |
4143 | rx_ring->next_to_clean = 0; |
4144 | rx_ring->next_to_use = 0; | |
9a799d71 AK |
4145 | |
4146 | return 0; | |
177db6ff MC |
4147 | |
4148 | alloc_failed: | |
177db6ff | 4149 | return -ENOMEM; |
9a799d71 AK |
4150 | } |
4151 | ||
69888674 AD |
4152 | /** |
4153 | * ixgbe_setup_all_rx_resources - allocate all queues Rx resources | |
4154 | * @adapter: board private structure | |
4155 | * | |
4156 | * If this function returns with an error, then it's possible one or | |
4157 | * more of the rings is populated (while the rest are not). It is the | |
4158 | * callers duty to clean those orphaned rings. | |
4159 | * | |
4160 | * Return 0 on success, negative on failure | |
4161 | **/ | |
4162 | ||
4163 | static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter) | |
4164 | { | |
4165 | int i, err = 0; | |
4166 | ||
4167 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
4168 | err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]); | |
4169 | if (!err) | |
4170 | continue; | |
4171 | DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i); | |
4172 | break; | |
4173 | } | |
4174 | ||
4175 | return err; | |
4176 | } | |
4177 | ||
9a799d71 AK |
4178 | /** |
4179 | * ixgbe_free_tx_resources - Free Tx Resources per Queue | |
4180 | * @adapter: board private structure | |
4181 | * @tx_ring: Tx descriptor ring for a specific queue | |
4182 | * | |
4183 | * Free all transmit software resources | |
4184 | **/ | |
c431f97e JB |
4185 | void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter, |
4186 | struct ixgbe_ring *tx_ring) | |
9a799d71 AK |
4187 | { |
4188 | struct pci_dev *pdev = adapter->pdev; | |
4189 | ||
4190 | ixgbe_clean_tx_ring(adapter, tx_ring); | |
4191 | ||
4192 | vfree(tx_ring->tx_buffer_info); | |
4193 | tx_ring->tx_buffer_info = NULL; | |
4194 | ||
4195 | pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma); | |
4196 | ||
4197 | tx_ring->desc = NULL; | |
4198 | } | |
4199 | ||
4200 | /** | |
4201 | * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues | |
4202 | * @adapter: board private structure | |
4203 | * | |
4204 | * Free all transmit software resources | |
4205 | **/ | |
4206 | static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter) | |
4207 | { | |
4208 | int i; | |
4209 | ||
4210 | for (i = 0; i < adapter->num_tx_queues; i++) | |
9891ca7c JB |
4211 | if (adapter->tx_ring[i].desc) |
4212 | ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]); | |
9a799d71 AK |
4213 | } |
4214 | ||
4215 | /** | |
b4617240 | 4216 | * ixgbe_free_rx_resources - Free Rx Resources |
9a799d71 AK |
4217 | * @adapter: board private structure |
4218 | * @rx_ring: ring to clean the resources from | |
4219 | * | |
4220 | * Free all receive software resources | |
4221 | **/ | |
c431f97e JB |
4222 | void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter, |
4223 | struct ixgbe_ring *rx_ring) | |
9a799d71 AK |
4224 | { |
4225 | struct pci_dev *pdev = adapter->pdev; | |
4226 | ||
4227 | ixgbe_clean_rx_ring(adapter, rx_ring); | |
4228 | ||
4229 | vfree(rx_ring->rx_buffer_info); | |
4230 | rx_ring->rx_buffer_info = NULL; | |
4231 | ||
4232 | pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma); | |
4233 | ||
4234 | rx_ring->desc = NULL; | |
4235 | } | |
4236 | ||
4237 | /** | |
4238 | * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues | |
4239 | * @adapter: board private structure | |
4240 | * | |
4241 | * Free all receive software resources | |
4242 | **/ | |
4243 | static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter) | |
4244 | { | |
4245 | int i; | |
4246 | ||
4247 | for (i = 0; i < adapter->num_rx_queues; i++) | |
9891ca7c JB |
4248 | if (adapter->rx_ring[i].desc) |
4249 | ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]); | |
9a799d71 AK |
4250 | } |
4251 | ||
9a799d71 AK |
4252 | /** |
4253 | * ixgbe_change_mtu - Change the Maximum Transfer Unit | |
4254 | * @netdev: network interface device structure | |
4255 | * @new_mtu: new value for maximum frame size | |
4256 | * | |
4257 | * Returns 0 on success, negative on failure | |
4258 | **/ | |
4259 | static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu) | |
4260 | { | |
4261 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4262 | int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; | |
4263 | ||
42c783c5 JB |
4264 | /* MTU < 68 is an error and causes problems on some kernels */ |
4265 | if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE)) | |
9a799d71 AK |
4266 | return -EINVAL; |
4267 | ||
021230d4 | 4268 | DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n", |
b4617240 | 4269 | netdev->mtu, new_mtu); |
021230d4 | 4270 | /* must set new MTU before calling down or up */ |
9a799d71 AK |
4271 | netdev->mtu = new_mtu; |
4272 | ||
d4f80882 AV |
4273 | if (netif_running(netdev)) |
4274 | ixgbe_reinit_locked(adapter); | |
9a799d71 AK |
4275 | |
4276 | return 0; | |
4277 | } | |
4278 | ||
4279 | /** | |
4280 | * ixgbe_open - Called when a network interface is made active | |
4281 | * @netdev: network interface device structure | |
4282 | * | |
4283 | * Returns 0 on success, negative value on failure | |
4284 | * | |
4285 | * The open entry point is called when a network interface is made | |
4286 | * active by the system (IFF_UP). At this point all resources needed | |
4287 | * for transmit and receive operations are allocated, the interrupt | |
4288 | * handler is registered with the OS, the watchdog timer is started, | |
4289 | * and the stack is notified that the interface is ready. | |
4290 | **/ | |
4291 | static int ixgbe_open(struct net_device *netdev) | |
4292 | { | |
4293 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4294 | int err; | |
4bebfaa5 AK |
4295 | |
4296 | /* disallow open during test */ | |
4297 | if (test_bit(__IXGBE_TESTING, &adapter->state)) | |
4298 | return -EBUSY; | |
9a799d71 | 4299 | |
54386467 JB |
4300 | netif_carrier_off(netdev); |
4301 | ||
9a799d71 AK |
4302 | /* allocate transmit descriptors */ |
4303 | err = ixgbe_setup_all_tx_resources(adapter); | |
4304 | if (err) | |
4305 | goto err_setup_tx; | |
4306 | ||
9a799d71 AK |
4307 | /* allocate receive descriptors */ |
4308 | err = ixgbe_setup_all_rx_resources(adapter); | |
4309 | if (err) | |
4310 | goto err_setup_rx; | |
4311 | ||
4312 | ixgbe_configure(adapter); | |
4313 | ||
021230d4 | 4314 | err = ixgbe_request_irq(adapter); |
9a799d71 AK |
4315 | if (err) |
4316 | goto err_req_irq; | |
4317 | ||
9a799d71 AK |
4318 | err = ixgbe_up_complete(adapter); |
4319 | if (err) | |
4320 | goto err_up; | |
4321 | ||
d55b53ff JK |
4322 | netif_tx_start_all_queues(netdev); |
4323 | ||
9a799d71 AK |
4324 | return 0; |
4325 | ||
4326 | err_up: | |
5eba3699 | 4327 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
4328 | ixgbe_free_irq(adapter); |
4329 | err_req_irq: | |
9a799d71 | 4330 | err_setup_rx: |
a20a1199 | 4331 | ixgbe_free_all_rx_resources(adapter); |
9a799d71 | 4332 | err_setup_tx: |
a20a1199 | 4333 | ixgbe_free_all_tx_resources(adapter); |
9a799d71 AK |
4334 | ixgbe_reset(adapter); |
4335 | ||
4336 | return err; | |
4337 | } | |
4338 | ||
4339 | /** | |
4340 | * ixgbe_close - Disables a network interface | |
4341 | * @netdev: network interface device structure | |
4342 | * | |
4343 | * Returns 0, this is not allowed to fail | |
4344 | * | |
4345 | * The close entry point is called when an interface is de-activated | |
4346 | * by the OS. The hardware is still under the drivers control, but | |
4347 | * needs to be disabled. A global MAC reset is issued to stop the | |
4348 | * hardware, and all transmit and receive resources are freed. | |
4349 | **/ | |
4350 | static int ixgbe_close(struct net_device *netdev) | |
4351 | { | |
4352 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
9a799d71 AK |
4353 | |
4354 | ixgbe_down(adapter); | |
4355 | ixgbe_free_irq(adapter); | |
4356 | ||
4357 | ixgbe_free_all_tx_resources(adapter); | |
4358 | ixgbe_free_all_rx_resources(adapter); | |
4359 | ||
5eba3699 | 4360 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
4361 | |
4362 | return 0; | |
4363 | } | |
4364 | ||
b3c8b4ba AD |
4365 | #ifdef CONFIG_PM |
4366 | static int ixgbe_resume(struct pci_dev *pdev) | |
4367 | { | |
4368 | struct net_device *netdev = pci_get_drvdata(pdev); | |
4369 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4370 | u32 err; | |
4371 | ||
4372 | pci_set_power_state(pdev, PCI_D0); | |
4373 | pci_restore_state(pdev); | |
9ce77666 | 4374 | |
4375 | err = pci_enable_device_mem(pdev); | |
b3c8b4ba | 4376 | if (err) { |
69888674 | 4377 | printk(KERN_ERR "ixgbe: Cannot enable PCI device from " |
b3c8b4ba AD |
4378 | "suspend\n"); |
4379 | return err; | |
4380 | } | |
4381 | pci_set_master(pdev); | |
4382 | ||
dd4d8ca6 | 4383 | pci_wake_from_d3(pdev, false); |
b3c8b4ba AD |
4384 | |
4385 | err = ixgbe_init_interrupt_scheme(adapter); | |
4386 | if (err) { | |
4387 | printk(KERN_ERR "ixgbe: Cannot initialize interrupts for " | |
4388 | "device\n"); | |
4389 | return err; | |
4390 | } | |
4391 | ||
b3c8b4ba AD |
4392 | ixgbe_reset(adapter); |
4393 | ||
495dce12 WJP |
4394 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
4395 | ||
b3c8b4ba AD |
4396 | if (netif_running(netdev)) { |
4397 | err = ixgbe_open(adapter->netdev); | |
4398 | if (err) | |
4399 | return err; | |
4400 | } | |
4401 | ||
4402 | netif_device_attach(netdev); | |
4403 | ||
4404 | return 0; | |
4405 | } | |
b3c8b4ba | 4406 | #endif /* CONFIG_PM */ |
9d8d05ae RW |
4407 | |
4408 | static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake) | |
b3c8b4ba AD |
4409 | { |
4410 | struct net_device *netdev = pci_get_drvdata(pdev); | |
4411 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
e8e26350 PW |
4412 | struct ixgbe_hw *hw = &adapter->hw; |
4413 | u32 ctrl, fctrl; | |
4414 | u32 wufc = adapter->wol; | |
b3c8b4ba AD |
4415 | #ifdef CONFIG_PM |
4416 | int retval = 0; | |
4417 | #endif | |
4418 | ||
4419 | netif_device_detach(netdev); | |
4420 | ||
4421 | if (netif_running(netdev)) { | |
4422 | ixgbe_down(adapter); | |
4423 | ixgbe_free_irq(adapter); | |
4424 | ixgbe_free_all_tx_resources(adapter); | |
4425 | ixgbe_free_all_rx_resources(adapter); | |
4426 | } | |
7a921c93 | 4427 | ixgbe_clear_interrupt_scheme(adapter); |
b3c8b4ba AD |
4428 | |
4429 | #ifdef CONFIG_PM | |
4430 | retval = pci_save_state(pdev); | |
4431 | if (retval) | |
4432 | return retval; | |
4df10466 | 4433 | |
b3c8b4ba | 4434 | #endif |
e8e26350 PW |
4435 | if (wufc) { |
4436 | ixgbe_set_rx_mode(netdev); | |
b3c8b4ba | 4437 | |
e8e26350 PW |
4438 | /* turn on all-multi mode if wake on multicast is enabled */ |
4439 | if (wufc & IXGBE_WUFC_MC) { | |
4440 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
4441 | fctrl |= IXGBE_FCTRL_MPE; | |
4442 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); | |
4443 | } | |
4444 | ||
4445 | ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); | |
4446 | ctrl |= IXGBE_CTRL_GIO_DIS; | |
4447 | IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); | |
4448 | ||
4449 | IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc); | |
4450 | } else { | |
4451 | IXGBE_WRITE_REG(hw, IXGBE_WUC, 0); | |
4452 | IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); | |
4453 | } | |
4454 | ||
dd4d8ca6 DS |
4455 | if (wufc && hw->mac.type == ixgbe_mac_82599EB) |
4456 | pci_wake_from_d3(pdev, true); | |
4457 | else | |
4458 | pci_wake_from_d3(pdev, false); | |
b3c8b4ba | 4459 | |
9d8d05ae RW |
4460 | *enable_wake = !!wufc; |
4461 | ||
b3c8b4ba AD |
4462 | ixgbe_release_hw_control(adapter); |
4463 | ||
4464 | pci_disable_device(pdev); | |
4465 | ||
9d8d05ae RW |
4466 | return 0; |
4467 | } | |
4468 | ||
4469 | #ifdef CONFIG_PM | |
4470 | static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state) | |
4471 | { | |
4472 | int retval; | |
4473 | bool wake; | |
4474 | ||
4475 | retval = __ixgbe_shutdown(pdev, &wake); | |
4476 | if (retval) | |
4477 | return retval; | |
4478 | ||
4479 | if (wake) { | |
4480 | pci_prepare_to_sleep(pdev); | |
4481 | } else { | |
4482 | pci_wake_from_d3(pdev, false); | |
4483 | pci_set_power_state(pdev, PCI_D3hot); | |
4484 | } | |
b3c8b4ba AD |
4485 | |
4486 | return 0; | |
4487 | } | |
9d8d05ae | 4488 | #endif /* CONFIG_PM */ |
b3c8b4ba AD |
4489 | |
4490 | static void ixgbe_shutdown(struct pci_dev *pdev) | |
4491 | { | |
9d8d05ae RW |
4492 | bool wake; |
4493 | ||
4494 | __ixgbe_shutdown(pdev, &wake); | |
4495 | ||
4496 | if (system_state == SYSTEM_POWER_OFF) { | |
4497 | pci_wake_from_d3(pdev, wake); | |
4498 | pci_set_power_state(pdev, PCI_D3hot); | |
4499 | } | |
b3c8b4ba AD |
4500 | } |
4501 | ||
9a799d71 AK |
4502 | /** |
4503 | * ixgbe_update_stats - Update the board statistics counters. | |
4504 | * @adapter: board private structure | |
4505 | **/ | |
4506 | void ixgbe_update_stats(struct ixgbe_adapter *adapter) | |
4507 | { | |
2d86f139 | 4508 | struct net_device *netdev = adapter->netdev; |
9a799d71 | 4509 | struct ixgbe_hw *hw = &adapter->hw; |
6f11eef7 AV |
4510 | u64 total_mpc = 0; |
4511 | u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot; | |
9a799d71 | 4512 | |
94b982b2 | 4513 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { |
f8212f97 | 4514 | u64 rsc_count = 0; |
94b982b2 | 4515 | u64 rsc_flush = 0; |
d51019a4 PW |
4516 | for (i = 0; i < 16; i++) |
4517 | adapter->hw_rx_no_dma_resources += | |
4518 | IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); | |
94b982b2 | 4519 | for (i = 0; i < adapter->num_rx_queues; i++) { |
f8212f97 | 4520 | rsc_count += adapter->rx_ring[i].rsc_count; |
94b982b2 MC |
4521 | rsc_flush += adapter->rx_ring[i].rsc_flush; |
4522 | } | |
4523 | adapter->rsc_total_count = rsc_count; | |
4524 | adapter->rsc_total_flush = rsc_flush; | |
d51019a4 PW |
4525 | } |
4526 | ||
7ca3bc58 JB |
4527 | /* gather some stats to the adapter struct that are per queue */ |
4528 | for (i = 0; i < adapter->num_tx_queues; i++) | |
4529 | adapter->restart_queue += adapter->tx_ring[i].restart_queue; | |
4530 | ||
4531 | for (i = 0; i < adapter->num_rx_queues; i++) | |
4532 | adapter->non_eop_descs += adapter->tx_ring[i].non_eop_descs; | |
4533 | ||
9a799d71 | 4534 | adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); |
6f11eef7 AV |
4535 | for (i = 0; i < 8; i++) { |
4536 | /* for packet buffers not used, the register should read 0 */ | |
4537 | mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i)); | |
4538 | missed_rx += mpc; | |
4539 | adapter->stats.mpc[i] += mpc; | |
4540 | total_mpc += adapter->stats.mpc[i]; | |
e8e26350 PW |
4541 | if (hw->mac.type == ixgbe_mac_82598EB) |
4542 | adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); | |
2f90b865 AD |
4543 | adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); |
4544 | adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i)); | |
4545 | adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); | |
4546 | adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i)); | |
e8e26350 PW |
4547 | if (hw->mac.type == ixgbe_mac_82599EB) { |
4548 | adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw, | |
4549 | IXGBE_PXONRXCNT(i)); | |
4550 | adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw, | |
4551 | IXGBE_PXOFFRXCNT(i)); | |
4552 | adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); | |
e8e26350 PW |
4553 | } else { |
4554 | adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw, | |
4555 | IXGBE_PXONRXC(i)); | |
4556 | adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw, | |
4557 | IXGBE_PXOFFRXC(i)); | |
4558 | } | |
2f90b865 AD |
4559 | adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw, |
4560 | IXGBE_PXONTXC(i)); | |
2f90b865 | 4561 | adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw, |
e8e26350 | 4562 | IXGBE_PXOFFTXC(i)); |
6f11eef7 AV |
4563 | } |
4564 | adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); | |
4565 | /* work around hardware counting issue */ | |
4566 | adapter->stats.gprc -= missed_rx; | |
4567 | ||
4568 | /* 82598 hardware only has a 32 bit counter in the high register */ | |
e8e26350 | 4569 | if (hw->mac.type == ixgbe_mac_82599EB) { |
aad71918 | 4570 | u64 tmp; |
e8e26350 | 4571 | adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); |
aad71918 BG |
4572 | tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF; /* 4 high bits of GORC */ |
4573 | adapter->stats.gorc += (tmp << 32); | |
e8e26350 | 4574 | adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); |
aad71918 BG |
4575 | tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF; /* 4 high bits of GOTC */ |
4576 | adapter->stats.gotc += (tmp << 32); | |
e8e26350 PW |
4577 | adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL); |
4578 | IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */ | |
4579 | adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); | |
4580 | adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); | |
c4cf55e5 PWJ |
4581 | adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); |
4582 | adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); | |
6d45522c YZ |
4583 | #ifdef IXGBE_FCOE |
4584 | adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); | |
4585 | adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); | |
4586 | adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); | |
4587 | adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); | |
4588 | adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); | |
4589 | adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); | |
4590 | #endif /* IXGBE_FCOE */ | |
e8e26350 PW |
4591 | } else { |
4592 | adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); | |
4593 | adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); | |
4594 | adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); | |
4595 | adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); | |
4596 | adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH); | |
4597 | } | |
9a799d71 AK |
4598 | bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); |
4599 | adapter->stats.bprc += bprc; | |
4600 | adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); | |
e8e26350 PW |
4601 | if (hw->mac.type == ixgbe_mac_82598EB) |
4602 | adapter->stats.mprc -= bprc; | |
9a799d71 AK |
4603 | adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC); |
4604 | adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); | |
4605 | adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); | |
4606 | adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); | |
4607 | adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); | |
4608 | adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); | |
4609 | adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); | |
9a799d71 | 4610 | adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); |
6f11eef7 AV |
4611 | lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); |
4612 | adapter->stats.lxontxc += lxon; | |
4613 | lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); | |
4614 | adapter->stats.lxofftxc += lxoff; | |
9a799d71 AK |
4615 | adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC); |
4616 | adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); | |
6f11eef7 AV |
4617 | adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); |
4618 | /* | |
4619 | * 82598 errata - tx of flow control packets is included in tx counters | |
4620 | */ | |
4621 | xon_off_tot = lxon + lxoff; | |
4622 | adapter->stats.gptc -= xon_off_tot; | |
4623 | adapter->stats.mptc -= xon_off_tot; | |
4624 | adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN)); | |
9a799d71 AK |
4625 | adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC); |
4626 | adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC); | |
4627 | adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC); | |
9a799d71 AK |
4628 | adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR); |
4629 | adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); | |
6f11eef7 | 4630 | adapter->stats.ptc64 -= xon_off_tot; |
9a799d71 AK |
4631 | adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); |
4632 | adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); | |
4633 | adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); | |
4634 | adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); | |
4635 | adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); | |
9a799d71 AK |
4636 | adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); |
4637 | ||
4638 | /* Fill out the OS statistics structure */ | |
2d86f139 | 4639 | netdev->stats.multicast = adapter->stats.mprc; |
9a799d71 AK |
4640 | |
4641 | /* Rx Errors */ | |
2d86f139 | 4642 | netdev->stats.rx_errors = adapter->stats.crcerrs + |
b4617240 | 4643 | adapter->stats.rlec; |
2d86f139 AK |
4644 | netdev->stats.rx_dropped = 0; |
4645 | netdev->stats.rx_length_errors = adapter->stats.rlec; | |
4646 | netdev->stats.rx_crc_errors = adapter->stats.crcerrs; | |
4647 | netdev->stats.rx_missed_errors = total_mpc; | |
9a799d71 AK |
4648 | } |
4649 | ||
4650 | /** | |
4651 | * ixgbe_watchdog - Timer Call-back | |
4652 | * @data: pointer to adapter cast into an unsigned long | |
4653 | **/ | |
4654 | static void ixgbe_watchdog(unsigned long data) | |
4655 | { | |
4656 | struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data; | |
cf8280ee | 4657 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a AD |
4658 | u64 eics = 0; |
4659 | int i; | |
cf8280ee | 4660 | |
fe49f04a AD |
4661 | /* |
4662 | * Do the watchdog outside of interrupt context due to the lovely | |
4663 | * delays that some of the newer hardware requires | |
4664 | */ | |
22d5a71b | 4665 | |
fe49f04a AD |
4666 | if (test_bit(__IXGBE_DOWN, &adapter->state)) |
4667 | goto watchdog_short_circuit; | |
22d5a71b | 4668 | |
fe49f04a AD |
4669 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { |
4670 | /* | |
4671 | * for legacy and MSI interrupts don't set any bits | |
4672 | * that are enabled for EIAM, because this operation | |
4673 | * would set *both* EIMS and EICS for any bit in EIAM | |
4674 | */ | |
4675 | IXGBE_WRITE_REG(hw, IXGBE_EICS, | |
4676 | (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); | |
4677 | goto watchdog_reschedule; | |
4678 | } | |
4679 | ||
4680 | /* get one bit for every active tx/rx interrupt vector */ | |
4681 | for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) { | |
4682 | struct ixgbe_q_vector *qv = adapter->q_vector[i]; | |
4683 | if (qv->rxr_count || qv->txr_count) | |
4684 | eics |= ((u64)1 << i); | |
cf8280ee | 4685 | } |
9a799d71 | 4686 | |
fe49f04a AD |
4687 | /* Cause software interrupt to ensure rx rings are cleaned */ |
4688 | ixgbe_irq_rearm_queues(adapter, eics); | |
4689 | ||
4690 | watchdog_reschedule: | |
4691 | /* Reset the timer */ | |
4692 | mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ)); | |
4693 | ||
4694 | watchdog_short_circuit: | |
cf8280ee JB |
4695 | schedule_work(&adapter->watchdog_task); |
4696 | } | |
4697 | ||
e8e26350 PW |
4698 | /** |
4699 | * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber | |
4700 | * @work: pointer to work_struct containing our data | |
4701 | **/ | |
4702 | static void ixgbe_multispeed_fiber_task(struct work_struct *work) | |
4703 | { | |
4704 | struct ixgbe_adapter *adapter = container_of(work, | |
4705 | struct ixgbe_adapter, | |
4706 | multispeed_fiber_task); | |
4707 | struct ixgbe_hw *hw = &adapter->hw; | |
4708 | u32 autoneg; | |
8620a103 | 4709 | bool negotiation; |
e8e26350 PW |
4710 | |
4711 | adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK; | |
a1f25324 MC |
4712 | autoneg = hw->phy.autoneg_advertised; |
4713 | if ((!autoneg) && (hw->mac.ops.get_link_capabilities)) | |
8620a103 MC |
4714 | hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation); |
4715 | if (hw->mac.ops.setup_link) | |
4716 | hw->mac.ops.setup_link(hw, autoneg, negotiation, true); | |
e8e26350 PW |
4717 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; |
4718 | adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK; | |
4719 | } | |
4720 | ||
4721 | /** | |
4722 | * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module | |
4723 | * @work: pointer to work_struct containing our data | |
4724 | **/ | |
4725 | static void ixgbe_sfp_config_module_task(struct work_struct *work) | |
4726 | { | |
4727 | struct ixgbe_adapter *adapter = container_of(work, | |
4728 | struct ixgbe_adapter, | |
4729 | sfp_config_module_task); | |
4730 | struct ixgbe_hw *hw = &adapter->hw; | |
4731 | u32 err; | |
4732 | ||
4733 | adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK; | |
63d6e1d8 DS |
4734 | |
4735 | /* Time for electrical oscillations to settle down */ | |
4736 | msleep(100); | |
e8e26350 | 4737 | err = hw->phy.ops.identify_sfp(hw); |
63d6e1d8 | 4738 | |
e8e26350 | 4739 | if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { |
88d2b81f DS |
4740 | dev_err(&adapter->pdev->dev, "failed to initialize because " |
4741 | "an unsupported SFP+ module type was detected.\n" | |
4742 | "Reload the driver after installing a supported " | |
4743 | "module.\n"); | |
63d6e1d8 | 4744 | unregister_netdev(adapter->netdev); |
e8e26350 PW |
4745 | return; |
4746 | } | |
4747 | hw->mac.ops.setup_sfp(hw); | |
4748 | ||
8d1c3c07 | 4749 | if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK)) |
e8e26350 PW |
4750 | /* This will also work for DA Twinax connections */ |
4751 | schedule_work(&adapter->multispeed_fiber_task); | |
4752 | adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK; | |
4753 | } | |
4754 | ||
c4cf55e5 PWJ |
4755 | /** |
4756 | * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table | |
4757 | * @work: pointer to work_struct containing our data | |
4758 | **/ | |
4759 | static void ixgbe_fdir_reinit_task(struct work_struct *work) | |
4760 | { | |
4761 | struct ixgbe_adapter *adapter = container_of(work, | |
4762 | struct ixgbe_adapter, | |
4763 | fdir_reinit_task); | |
4764 | struct ixgbe_hw *hw = &adapter->hw; | |
4765 | int i; | |
4766 | ||
4767 | if (ixgbe_reinit_fdir_tables_82599(hw) == 0) { | |
4768 | for (i = 0; i < adapter->num_tx_queues; i++) | |
4769 | set_bit(__IXGBE_FDIR_INIT_DONE, | |
4770 | &(adapter->tx_ring[i].reinit_state)); | |
4771 | } else { | |
4772 | DPRINTK(PROBE, ERR, "failed to finish FDIR re-initialization, " | |
4773 | "ignored adding FDIR ATR filters \n"); | |
4774 | } | |
4775 | /* Done FDIR Re-initialization, enable transmits */ | |
4776 | netif_tx_start_all_queues(adapter->netdev); | |
4777 | } | |
4778 | ||
cf8280ee | 4779 | /** |
69888674 AD |
4780 | * ixgbe_watchdog_task - worker thread to bring link up |
4781 | * @work: pointer to work_struct containing our data | |
cf8280ee JB |
4782 | **/ |
4783 | static void ixgbe_watchdog_task(struct work_struct *work) | |
4784 | { | |
4785 | struct ixgbe_adapter *adapter = container_of(work, | |
4786 | struct ixgbe_adapter, | |
4787 | watchdog_task); | |
4788 | struct net_device *netdev = adapter->netdev; | |
4789 | struct ixgbe_hw *hw = &adapter->hw; | |
4790 | u32 link_speed = adapter->link_speed; | |
4791 | bool link_up = adapter->link_up; | |
bc59fcda NS |
4792 | int i; |
4793 | struct ixgbe_ring *tx_ring; | |
4794 | int some_tx_pending = 0; | |
cf8280ee JB |
4795 | |
4796 | adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK; | |
4797 | ||
4798 | if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) { | |
4799 | hw->mac.ops.check_link(hw, &link_speed, &link_up, false); | |
264857b8 PWJ |
4800 | if (link_up) { |
4801 | #ifdef CONFIG_DCB | |
4802 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
4803 | for (i = 0; i < MAX_TRAFFIC_CLASS; i++) | |
620fa036 | 4804 | hw->mac.ops.fc_enable(hw, i); |
264857b8 | 4805 | } else { |
620fa036 | 4806 | hw->mac.ops.fc_enable(hw, 0); |
264857b8 PWJ |
4807 | } |
4808 | #else | |
620fa036 | 4809 | hw->mac.ops.fc_enable(hw, 0); |
264857b8 PWJ |
4810 | #endif |
4811 | } | |
4812 | ||
cf8280ee JB |
4813 | if (link_up || |
4814 | time_after(jiffies, (adapter->link_check_timeout + | |
4815 | IXGBE_TRY_LINK_TIMEOUT))) { | |
cf8280ee | 4816 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; |
264857b8 | 4817 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC); |
cf8280ee JB |
4818 | } |
4819 | adapter->link_up = link_up; | |
4820 | adapter->link_speed = link_speed; | |
4821 | } | |
9a799d71 AK |
4822 | |
4823 | if (link_up) { | |
4824 | if (!netif_carrier_ok(netdev)) { | |
e8e26350 PW |
4825 | bool flow_rx, flow_tx; |
4826 | ||
4827 | if (hw->mac.type == ixgbe_mac_82599EB) { | |
4828 | u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); | |
4829 | u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG); | |
078788b6 PWJ |
4830 | flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE); |
4831 | flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X); | |
e8e26350 PW |
4832 | } else { |
4833 | u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
4834 | u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS); | |
078788b6 PWJ |
4835 | flow_rx = !!(frctl & IXGBE_FCTRL_RFCE); |
4836 | flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X); | |
e8e26350 PW |
4837 | } |
4838 | ||
a46e534b JK |
4839 | printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, " |
4840 | "Flow Control: %s\n", | |
4841 | netdev->name, | |
4842 | (link_speed == IXGBE_LINK_SPEED_10GB_FULL ? | |
4843 | "10 Gbps" : | |
4844 | (link_speed == IXGBE_LINK_SPEED_1GB_FULL ? | |
4845 | "1 Gbps" : "unknown speed")), | |
e8e26350 PW |
4846 | ((flow_rx && flow_tx) ? "RX/TX" : |
4847 | (flow_rx ? "RX" : | |
4848 | (flow_tx ? "TX" : "None")))); | |
9a799d71 AK |
4849 | |
4850 | netif_carrier_on(netdev); | |
9a799d71 AK |
4851 | } else { |
4852 | /* Force detection of hung controller */ | |
4853 | adapter->detect_tx_hung = true; | |
4854 | } | |
4855 | } else { | |
cf8280ee JB |
4856 | adapter->link_up = false; |
4857 | adapter->link_speed = 0; | |
9a799d71 | 4858 | if (netif_carrier_ok(netdev)) { |
a46e534b JK |
4859 | printk(KERN_INFO "ixgbe: %s NIC Link is Down\n", |
4860 | netdev->name); | |
9a799d71 | 4861 | netif_carrier_off(netdev); |
9a799d71 AK |
4862 | } |
4863 | } | |
4864 | ||
bc59fcda NS |
4865 | if (!netif_carrier_ok(netdev)) { |
4866 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
4867 | tx_ring = &adapter->tx_ring[i]; | |
4868 | if (tx_ring->next_to_use != tx_ring->next_to_clean) { | |
4869 | some_tx_pending = 1; | |
4870 | break; | |
4871 | } | |
4872 | } | |
4873 | ||
4874 | if (some_tx_pending) { | |
4875 | /* We've lost link, so the controller stops DMA, | |
4876 | * but we've got queued Tx work that's never going | |
4877 | * to get done, so reset controller to flush Tx. | |
4878 | * (Do the reset outside of interrupt context). | |
4879 | */ | |
4880 | schedule_work(&adapter->reset_task); | |
4881 | } | |
4882 | } | |
4883 | ||
9a799d71 | 4884 | ixgbe_update_stats(adapter); |
cf8280ee | 4885 | adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK; |
9a799d71 AK |
4886 | } |
4887 | ||
9a799d71 | 4888 | static int ixgbe_tso(struct ixgbe_adapter *adapter, |
b4617240 PW |
4889 | struct ixgbe_ring *tx_ring, struct sk_buff *skb, |
4890 | u32 tx_flags, u8 *hdr_len) | |
9a799d71 AK |
4891 | { |
4892 | struct ixgbe_adv_tx_context_desc *context_desc; | |
4893 | unsigned int i; | |
4894 | int err; | |
4895 | struct ixgbe_tx_buffer *tx_buffer_info; | |
9f8cdf4f JB |
4896 | u32 vlan_macip_lens = 0, type_tucmd_mlhl; |
4897 | u32 mss_l4len_idx, l4len; | |
9a799d71 AK |
4898 | |
4899 | if (skb_is_gso(skb)) { | |
4900 | if (skb_header_cloned(skb)) { | |
4901 | err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); | |
4902 | if (err) | |
4903 | return err; | |
4904 | } | |
4905 | l4len = tcp_hdrlen(skb); | |
4906 | *hdr_len += l4len; | |
4907 | ||
8327d000 | 4908 | if (skb->protocol == htons(ETH_P_IP)) { |
9a799d71 AK |
4909 | struct iphdr *iph = ip_hdr(skb); |
4910 | iph->tot_len = 0; | |
4911 | iph->check = 0; | |
4912 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, | |
b4617240 PW |
4913 | iph->daddr, 0, |
4914 | IPPROTO_TCP, | |
4915 | 0); | |
9a799d71 AK |
4916 | } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) { |
4917 | ipv6_hdr(skb)->payload_len = 0; | |
4918 | tcp_hdr(skb)->check = | |
4919 | ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, | |
b4617240 PW |
4920 | &ipv6_hdr(skb)->daddr, |
4921 | 0, IPPROTO_TCP, 0); | |
9a799d71 AK |
4922 | } |
4923 | ||
4924 | i = tx_ring->next_to_use; | |
4925 | ||
4926 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
4927 | context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i); | |
4928 | ||
4929 | /* VLAN MACLEN IPLEN */ | |
4930 | if (tx_flags & IXGBE_TX_FLAGS_VLAN) | |
4931 | vlan_macip_lens |= | |
4932 | (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK); | |
4933 | vlan_macip_lens |= ((skb_network_offset(skb)) << | |
b4617240 | 4934 | IXGBE_ADVTXD_MACLEN_SHIFT); |
9a799d71 AK |
4935 | *hdr_len += skb_network_offset(skb); |
4936 | vlan_macip_lens |= | |
4937 | (skb_transport_header(skb) - skb_network_header(skb)); | |
4938 | *hdr_len += | |
4939 | (skb_transport_header(skb) - skb_network_header(skb)); | |
4940 | context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); | |
4941 | context_desc->seqnum_seed = 0; | |
4942 | ||
4943 | /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ | |
9f8cdf4f | 4944 | type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT | |
b4617240 | 4945 | IXGBE_ADVTXD_DTYP_CTXT); |
9a799d71 | 4946 | |
8327d000 | 4947 | if (skb->protocol == htons(ETH_P_IP)) |
9a799d71 AK |
4948 | type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4; |
4949 | type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP; | |
4950 | context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl); | |
4951 | ||
4952 | /* MSS L4LEN IDX */ | |
9f8cdf4f | 4953 | mss_l4len_idx = |
9a799d71 AK |
4954 | (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT); |
4955 | mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT); | |
4eeae6fd PW |
4956 | /* use index 1 for TSO */ |
4957 | mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT); | |
9a799d71 AK |
4958 | context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); |
4959 | ||
4960 | tx_buffer_info->time_stamp = jiffies; | |
4961 | tx_buffer_info->next_to_watch = i; | |
4962 | ||
4963 | i++; | |
4964 | if (i == tx_ring->count) | |
4965 | i = 0; | |
4966 | tx_ring->next_to_use = i; | |
4967 | ||
4968 | return true; | |
4969 | } | |
4970 | return false; | |
4971 | } | |
4972 | ||
4973 | static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter, | |
b4617240 PW |
4974 | struct ixgbe_ring *tx_ring, |
4975 | struct sk_buff *skb, u32 tx_flags) | |
9a799d71 AK |
4976 | { |
4977 | struct ixgbe_adv_tx_context_desc *context_desc; | |
4978 | unsigned int i; | |
4979 | struct ixgbe_tx_buffer *tx_buffer_info; | |
4980 | u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0; | |
4981 | ||
4982 | if (skb->ip_summed == CHECKSUM_PARTIAL || | |
4983 | (tx_flags & IXGBE_TX_FLAGS_VLAN)) { | |
4984 | i = tx_ring->next_to_use; | |
4985 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
4986 | context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i); | |
4987 | ||
4988 | if (tx_flags & IXGBE_TX_FLAGS_VLAN) | |
4989 | vlan_macip_lens |= | |
4990 | (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK); | |
4991 | vlan_macip_lens |= (skb_network_offset(skb) << | |
b4617240 | 4992 | IXGBE_ADVTXD_MACLEN_SHIFT); |
9a799d71 AK |
4993 | if (skb->ip_summed == CHECKSUM_PARTIAL) |
4994 | vlan_macip_lens |= (skb_transport_header(skb) - | |
b4617240 | 4995 | skb_network_header(skb)); |
9a799d71 AK |
4996 | |
4997 | context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); | |
4998 | context_desc->seqnum_seed = 0; | |
4999 | ||
5000 | type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT | | |
b4617240 | 5001 | IXGBE_ADVTXD_DTYP_CTXT); |
9a799d71 AK |
5002 | |
5003 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
41825d71 | 5004 | switch (skb->protocol) { |
09640e63 | 5005 | case cpu_to_be16(ETH_P_IP): |
9a799d71 | 5006 | type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4; |
41825d71 AK |
5007 | if (ip_hdr(skb)->protocol == IPPROTO_TCP) |
5008 | type_tucmd_mlhl |= | |
b4617240 | 5009 | IXGBE_ADVTXD_TUCMD_L4T_TCP; |
45a5ead0 JB |
5010 | else if (ip_hdr(skb)->protocol == IPPROTO_SCTP) |
5011 | type_tucmd_mlhl |= | |
5012 | IXGBE_ADVTXD_TUCMD_L4T_SCTP; | |
41825d71 | 5013 | break; |
09640e63 | 5014 | case cpu_to_be16(ETH_P_IPV6): |
41825d71 AK |
5015 | /* XXX what about other V6 headers?? */ |
5016 | if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP) | |
5017 | type_tucmd_mlhl |= | |
b4617240 | 5018 | IXGBE_ADVTXD_TUCMD_L4T_TCP; |
45a5ead0 JB |
5019 | else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP) |
5020 | type_tucmd_mlhl |= | |
5021 | IXGBE_ADVTXD_TUCMD_L4T_SCTP; | |
41825d71 | 5022 | break; |
41825d71 AK |
5023 | default: |
5024 | if (unlikely(net_ratelimit())) { | |
5025 | DPRINTK(PROBE, WARNING, | |
5026 | "partial checksum but proto=%x!\n", | |
5027 | skb->protocol); | |
5028 | } | |
5029 | break; | |
5030 | } | |
9a799d71 AK |
5031 | } |
5032 | ||
5033 | context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl); | |
4eeae6fd | 5034 | /* use index zero for tx checksum offload */ |
9a799d71 AK |
5035 | context_desc->mss_l4len_idx = 0; |
5036 | ||
5037 | tx_buffer_info->time_stamp = jiffies; | |
5038 | tx_buffer_info->next_to_watch = i; | |
9f8cdf4f | 5039 | |
9a799d71 AK |
5040 | i++; |
5041 | if (i == tx_ring->count) | |
5042 | i = 0; | |
5043 | tx_ring->next_to_use = i; | |
5044 | ||
5045 | return true; | |
5046 | } | |
9f8cdf4f | 5047 | |
9a799d71 AK |
5048 | return false; |
5049 | } | |
5050 | ||
5051 | static int ixgbe_tx_map(struct ixgbe_adapter *adapter, | |
b4617240 | 5052 | struct ixgbe_ring *tx_ring, |
eacd73f7 YZ |
5053 | struct sk_buff *skb, u32 tx_flags, |
5054 | unsigned int first) | |
9a799d71 | 5055 | { |
e5a43549 | 5056 | struct pci_dev *pdev = adapter->pdev; |
9a799d71 | 5057 | struct ixgbe_tx_buffer *tx_buffer_info; |
eacd73f7 YZ |
5058 | unsigned int len; |
5059 | unsigned int total = skb->len; | |
9a799d71 AK |
5060 | unsigned int offset = 0, size, count = 0, i; |
5061 | unsigned int nr_frags = skb_shinfo(skb)->nr_frags; | |
5062 | unsigned int f; | |
9a799d71 AK |
5063 | |
5064 | i = tx_ring->next_to_use; | |
5065 | ||
eacd73f7 YZ |
5066 | if (tx_flags & IXGBE_TX_FLAGS_FCOE) |
5067 | /* excluding fcoe_crc_eof for FCoE */ | |
5068 | total -= sizeof(struct fcoe_crc_eof); | |
5069 | ||
5070 | len = min(skb_headlen(skb), total); | |
9a799d71 AK |
5071 | while (len) { |
5072 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
5073 | size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD); | |
5074 | ||
5075 | tx_buffer_info->length = size; | |
e5a43549 AD |
5076 | tx_buffer_info->mapped_as_page = false; |
5077 | tx_buffer_info->dma = pci_map_single(pdev, | |
5078 | skb->data + offset, | |
5079 | size, PCI_DMA_TODEVICE); | |
5080 | if (pci_dma_mapping_error(pdev, tx_buffer_info->dma)) | |
5081 | goto dma_error; | |
9a799d71 AK |
5082 | tx_buffer_info->time_stamp = jiffies; |
5083 | tx_buffer_info->next_to_watch = i; | |
5084 | ||
5085 | len -= size; | |
eacd73f7 | 5086 | total -= size; |
9a799d71 AK |
5087 | offset += size; |
5088 | count++; | |
44df32c5 AD |
5089 | |
5090 | if (len) { | |
5091 | i++; | |
5092 | if (i == tx_ring->count) | |
5093 | i = 0; | |
5094 | } | |
9a799d71 AK |
5095 | } |
5096 | ||
5097 | for (f = 0; f < nr_frags; f++) { | |
5098 | struct skb_frag_struct *frag; | |
5099 | ||
5100 | frag = &skb_shinfo(skb)->frags[f]; | |
eacd73f7 | 5101 | len = min((unsigned int)frag->size, total); |
e5a43549 | 5102 | offset = frag->page_offset; |
9a799d71 AK |
5103 | |
5104 | while (len) { | |
44df32c5 AD |
5105 | i++; |
5106 | if (i == tx_ring->count) | |
5107 | i = 0; | |
5108 | ||
9a799d71 AK |
5109 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; |
5110 | size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD); | |
5111 | ||
5112 | tx_buffer_info->length = size; | |
e5a43549 AD |
5113 | tx_buffer_info->dma = pci_map_page(adapter->pdev, |
5114 | frag->page, | |
5115 | offset, size, | |
5116 | PCI_DMA_TODEVICE); | |
5117 | tx_buffer_info->mapped_as_page = true; | |
5118 | if (pci_dma_mapping_error(pdev, tx_buffer_info->dma)) | |
5119 | goto dma_error; | |
9a799d71 AK |
5120 | tx_buffer_info->time_stamp = jiffies; |
5121 | tx_buffer_info->next_to_watch = i; | |
5122 | ||
5123 | len -= size; | |
eacd73f7 | 5124 | total -= size; |
9a799d71 AK |
5125 | offset += size; |
5126 | count++; | |
9a799d71 | 5127 | } |
eacd73f7 YZ |
5128 | if (total == 0) |
5129 | break; | |
9a799d71 | 5130 | } |
44df32c5 | 5131 | |
9a799d71 AK |
5132 | tx_ring->tx_buffer_info[i].skb = skb; |
5133 | tx_ring->tx_buffer_info[first].next_to_watch = i; | |
5134 | ||
e5a43549 AD |
5135 | return count; |
5136 | ||
5137 | dma_error: | |
5138 | dev_err(&pdev->dev, "TX DMA map failed\n"); | |
5139 | ||
5140 | /* clear timestamp and dma mappings for failed tx_buffer_info map */ | |
5141 | tx_buffer_info->dma = 0; | |
5142 | tx_buffer_info->time_stamp = 0; | |
5143 | tx_buffer_info->next_to_watch = 0; | |
5144 | count--; | |
5145 | ||
5146 | /* clear timestamp and dma mappings for remaining portion of packet */ | |
5147 | while (count >= 0) { | |
5148 | count--; | |
5149 | i--; | |
5150 | if (i < 0) | |
5151 | i += tx_ring->count; | |
5152 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
5153 | ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info); | |
5154 | } | |
5155 | ||
9a799d71 AK |
5156 | return count; |
5157 | } | |
5158 | ||
5159 | static void ixgbe_tx_queue(struct ixgbe_adapter *adapter, | |
b4617240 PW |
5160 | struct ixgbe_ring *tx_ring, |
5161 | int tx_flags, int count, u32 paylen, u8 hdr_len) | |
9a799d71 AK |
5162 | { |
5163 | union ixgbe_adv_tx_desc *tx_desc = NULL; | |
5164 | struct ixgbe_tx_buffer *tx_buffer_info; | |
5165 | u32 olinfo_status = 0, cmd_type_len = 0; | |
5166 | unsigned int i; | |
5167 | u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS; | |
5168 | ||
5169 | cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA; | |
5170 | ||
5171 | cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT; | |
5172 | ||
5173 | if (tx_flags & IXGBE_TX_FLAGS_VLAN) | |
5174 | cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE; | |
5175 | ||
5176 | if (tx_flags & IXGBE_TX_FLAGS_TSO) { | |
5177 | cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE; | |
5178 | ||
5179 | olinfo_status |= IXGBE_TXD_POPTS_TXSM << | |
b4617240 | 5180 | IXGBE_ADVTXD_POPTS_SHIFT; |
9a799d71 | 5181 | |
4eeae6fd PW |
5182 | /* use index 1 context for tso */ |
5183 | olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT); | |
9a799d71 AK |
5184 | if (tx_flags & IXGBE_TX_FLAGS_IPV4) |
5185 | olinfo_status |= IXGBE_TXD_POPTS_IXSM << | |
b4617240 | 5186 | IXGBE_ADVTXD_POPTS_SHIFT; |
9a799d71 AK |
5187 | |
5188 | } else if (tx_flags & IXGBE_TX_FLAGS_CSUM) | |
5189 | olinfo_status |= IXGBE_TXD_POPTS_TXSM << | |
b4617240 | 5190 | IXGBE_ADVTXD_POPTS_SHIFT; |
9a799d71 | 5191 | |
eacd73f7 YZ |
5192 | if (tx_flags & IXGBE_TX_FLAGS_FCOE) { |
5193 | olinfo_status |= IXGBE_ADVTXD_CC; | |
5194 | olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT); | |
5195 | if (tx_flags & IXGBE_TX_FLAGS_FSO) | |
5196 | cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE; | |
5197 | } | |
5198 | ||
9a799d71 AK |
5199 | olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT); |
5200 | ||
5201 | i = tx_ring->next_to_use; | |
5202 | while (count--) { | |
5203 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
5204 | tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i); | |
5205 | tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma); | |
5206 | tx_desc->read.cmd_type_len = | |
b4617240 | 5207 | cpu_to_le32(cmd_type_len | tx_buffer_info->length); |
9a799d71 | 5208 | tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); |
9a799d71 AK |
5209 | i++; |
5210 | if (i == tx_ring->count) | |
5211 | i = 0; | |
5212 | } | |
5213 | ||
5214 | tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd); | |
5215 | ||
5216 | /* | |
5217 | * Force memory writes to complete before letting h/w | |
5218 | * know there are new descriptors to fetch. (Only | |
5219 | * applicable for weak-ordered memory model archs, | |
5220 | * such as IA-64). | |
5221 | */ | |
5222 | wmb(); | |
5223 | ||
5224 | tx_ring->next_to_use = i; | |
5225 | writel(i, adapter->hw.hw_addr + tx_ring->tail); | |
5226 | } | |
5227 | ||
c4cf55e5 PWJ |
5228 | static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb, |
5229 | int queue, u32 tx_flags) | |
5230 | { | |
5231 | /* Right now, we support IPv4 only */ | |
5232 | struct ixgbe_atr_input atr_input; | |
5233 | struct tcphdr *th; | |
c4cf55e5 PWJ |
5234 | struct iphdr *iph = ip_hdr(skb); |
5235 | struct ethhdr *eth = (struct ethhdr *)skb->data; | |
5236 | u16 vlan_id, src_port, dst_port, flex_bytes; | |
5237 | u32 src_ipv4_addr, dst_ipv4_addr; | |
5238 | u8 l4type = 0; | |
5239 | ||
5240 | /* check if we're UDP or TCP */ | |
5241 | if (iph->protocol == IPPROTO_TCP) { | |
5242 | th = tcp_hdr(skb); | |
5243 | src_port = th->source; | |
5244 | dst_port = th->dest; | |
5245 | l4type |= IXGBE_ATR_L4TYPE_TCP; | |
5246 | /* l4type IPv4 type is 0, no need to assign */ | |
c4cf55e5 PWJ |
5247 | } else { |
5248 | /* Unsupported L4 header, just bail here */ | |
5249 | return; | |
5250 | } | |
5251 | ||
5252 | memset(&atr_input, 0, sizeof(struct ixgbe_atr_input)); | |
5253 | ||
5254 | vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >> | |
5255 | IXGBE_TX_FLAGS_VLAN_SHIFT; | |
5256 | src_ipv4_addr = iph->saddr; | |
5257 | dst_ipv4_addr = iph->daddr; | |
5258 | flex_bytes = eth->h_proto; | |
5259 | ||
5260 | ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id); | |
5261 | ixgbe_atr_set_src_port_82599(&atr_input, dst_port); | |
5262 | ixgbe_atr_set_dst_port_82599(&atr_input, src_port); | |
5263 | ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes); | |
5264 | ixgbe_atr_set_l4type_82599(&atr_input, l4type); | |
5265 | /* src and dst are inverted, think how the receiver sees them */ | |
5266 | ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr); | |
5267 | ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr); | |
5268 | ||
5269 | /* This assumes the Rx queue and Tx queue are bound to the same CPU */ | |
5270 | ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue); | |
5271 | } | |
5272 | ||
e092be60 | 5273 | static int __ixgbe_maybe_stop_tx(struct net_device *netdev, |
b4617240 | 5274 | struct ixgbe_ring *tx_ring, int size) |
e092be60 | 5275 | { |
30eba97a | 5276 | netif_stop_subqueue(netdev, tx_ring->queue_index); |
e092be60 AV |
5277 | /* Herbert's original patch had: |
5278 | * smp_mb__after_netif_stop_queue(); | |
5279 | * but since that doesn't exist yet, just open code it. */ | |
5280 | smp_mb(); | |
5281 | ||
5282 | /* We need to check again in a case another CPU has just | |
5283 | * made room available. */ | |
5284 | if (likely(IXGBE_DESC_UNUSED(tx_ring) < size)) | |
5285 | return -EBUSY; | |
5286 | ||
5287 | /* A reprieve! - use start_queue because it doesn't call schedule */ | |
af72166f | 5288 | netif_start_subqueue(netdev, tx_ring->queue_index); |
7ca3bc58 | 5289 | ++tx_ring->restart_queue; |
e092be60 AV |
5290 | return 0; |
5291 | } | |
5292 | ||
5293 | static int ixgbe_maybe_stop_tx(struct net_device *netdev, | |
b4617240 | 5294 | struct ixgbe_ring *tx_ring, int size) |
e092be60 AV |
5295 | { |
5296 | if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size)) | |
5297 | return 0; | |
5298 | return __ixgbe_maybe_stop_tx(netdev, tx_ring, size); | |
5299 | } | |
5300 | ||
09a3b1f8 SH |
5301 | static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb) |
5302 | { | |
5303 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
5f715823 | 5304 | int txq = smp_processor_id(); |
09a3b1f8 | 5305 | |
c4cf55e5 | 5306 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) |
5f715823 | 5307 | return txq; |
c4cf55e5 | 5308 | |
5f715823 YZ |
5309 | #ifdef IXGBE_FCOE |
5310 | if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && | |
5311 | (skb->protocol == htons(ETH_P_FCOE))) { | |
5312 | txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1); | |
5313 | txq += adapter->ring_feature[RING_F_FCOE].mask; | |
5314 | return txq; | |
5315 | } | |
5316 | #endif | |
09a3b1f8 | 5317 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) |
36e89d73 | 5318 | return (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK) >> 13; |
09a3b1f8 SH |
5319 | |
5320 | return skb_tx_hash(dev, skb); | |
5321 | } | |
5322 | ||
3b29a56d SH |
5323 | static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, |
5324 | struct net_device *netdev) | |
9a799d71 AK |
5325 | { |
5326 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
5327 | struct ixgbe_ring *tx_ring; | |
60d51134 | 5328 | struct netdev_queue *txq; |
9a799d71 AK |
5329 | unsigned int first; |
5330 | unsigned int tx_flags = 0; | |
30eba97a | 5331 | u8 hdr_len = 0; |
5f715823 | 5332 | int tso; |
9a799d71 AK |
5333 | int count = 0; |
5334 | unsigned int f; | |
9f8cdf4f | 5335 | |
9f8cdf4f JB |
5336 | if (adapter->vlgrp && vlan_tx_tag_present(skb)) { |
5337 | tx_flags |= vlan_tx_tag_get(skb); | |
2f90b865 AD |
5338 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { |
5339 | tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK; | |
5f715823 | 5340 | tx_flags |= ((skb->queue_mapping & 0x7) << 13); |
2f90b865 AD |
5341 | } |
5342 | tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT; | |
5343 | tx_flags |= IXGBE_TX_FLAGS_VLAN; | |
5344 | } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
60127865 | 5345 | if (skb->priority != TC_PRIO_CONTROL) { |
5f715823 | 5346 | tx_flags |= ((skb->queue_mapping & 0x7) << 13); |
60127865 LL |
5347 | tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT; |
5348 | tx_flags |= IXGBE_TX_FLAGS_VLAN; | |
5349 | } else { | |
5350 | skb->queue_mapping = | |
5351 | adapter->ring_feature[RING_F_DCB].indices-1; | |
5352 | } | |
9a799d71 | 5353 | } |
eacd73f7 | 5354 | |
5f715823 | 5355 | tx_ring = &adapter->tx_ring[skb->queue_mapping]; |
60127865 | 5356 | |
eacd73f7 | 5357 | if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && |
09ad1cc0 | 5358 | (skb->protocol == htons(ETH_P_FCOE))) { |
eacd73f7 | 5359 | tx_flags |= IXGBE_TX_FLAGS_FCOE; |
09ad1cc0 | 5360 | #ifdef IXGBE_FCOE |
61a0f421 YZ |
5361 | #ifdef CONFIG_IXGBE_DCB |
5362 | tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK | |
5363 | << IXGBE_TX_FLAGS_VLAN_SHIFT); | |
5364 | tx_flags |= ((adapter->fcoe.up << 13) | |
5365 | << IXGBE_TX_FLAGS_VLAN_SHIFT); | |
5366 | #endif | |
09ad1cc0 YZ |
5367 | #endif |
5368 | } | |
eacd73f7 | 5369 | /* four things can cause us to need a context descriptor */ |
9f8cdf4f JB |
5370 | if (skb_is_gso(skb) || |
5371 | (skb->ip_summed == CHECKSUM_PARTIAL) || | |
eacd73f7 YZ |
5372 | (tx_flags & IXGBE_TX_FLAGS_VLAN) || |
5373 | (tx_flags & IXGBE_TX_FLAGS_FCOE)) | |
9a799d71 AK |
5374 | count++; |
5375 | ||
9f8cdf4f JB |
5376 | count += TXD_USE_COUNT(skb_headlen(skb)); |
5377 | for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) | |
9a799d71 AK |
5378 | count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); |
5379 | ||
e092be60 | 5380 | if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) { |
9a799d71 | 5381 | adapter->tx_busy++; |
9a799d71 AK |
5382 | return NETDEV_TX_BUSY; |
5383 | } | |
9a799d71 | 5384 | |
9a799d71 | 5385 | first = tx_ring->next_to_use; |
eacd73f7 YZ |
5386 | if (tx_flags & IXGBE_TX_FLAGS_FCOE) { |
5387 | #ifdef IXGBE_FCOE | |
5388 | /* setup tx offload for FCoE */ | |
5389 | tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len); | |
5390 | if (tso < 0) { | |
5391 | dev_kfree_skb_any(skb); | |
5392 | return NETDEV_TX_OK; | |
5393 | } | |
5394 | if (tso) | |
5395 | tx_flags |= IXGBE_TX_FLAGS_FSO; | |
5396 | #endif /* IXGBE_FCOE */ | |
5397 | } else { | |
5398 | if (skb->protocol == htons(ETH_P_IP)) | |
5399 | tx_flags |= IXGBE_TX_FLAGS_IPV4; | |
5400 | tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len); | |
5401 | if (tso < 0) { | |
5402 | dev_kfree_skb_any(skb); | |
5403 | return NETDEV_TX_OK; | |
5404 | } | |
9a799d71 | 5405 | |
eacd73f7 YZ |
5406 | if (tso) |
5407 | tx_flags |= IXGBE_TX_FLAGS_TSO; | |
5408 | else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) && | |
5409 | (skb->ip_summed == CHECKSUM_PARTIAL)) | |
5410 | tx_flags |= IXGBE_TX_FLAGS_CSUM; | |
5411 | } | |
9a799d71 | 5412 | |
eacd73f7 | 5413 | count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first); |
44df32c5 | 5414 | if (count) { |
c4cf55e5 PWJ |
5415 | /* add the ATR filter if ATR is on */ |
5416 | if (tx_ring->atr_sample_rate) { | |
5417 | ++tx_ring->atr_count; | |
5418 | if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) && | |
5419 | test_bit(__IXGBE_FDIR_INIT_DONE, | |
5420 | &tx_ring->reinit_state)) { | |
5421 | ixgbe_atr(adapter, skb, tx_ring->queue_index, | |
5422 | tx_flags); | |
5423 | tx_ring->atr_count = 0; | |
5424 | } | |
5425 | } | |
60d51134 ED |
5426 | txq = netdev_get_tx_queue(netdev, tx_ring->queue_index); |
5427 | txq->tx_bytes += skb->len; | |
5428 | txq->tx_packets++; | |
44df32c5 AD |
5429 | ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len, |
5430 | hdr_len); | |
44df32c5 | 5431 | ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED); |
9a799d71 | 5432 | |
44df32c5 AD |
5433 | } else { |
5434 | dev_kfree_skb_any(skb); | |
5435 | tx_ring->tx_buffer_info[first].time_stamp = 0; | |
5436 | tx_ring->next_to_use = first; | |
5437 | } | |
9a799d71 AK |
5438 | |
5439 | return NETDEV_TX_OK; | |
5440 | } | |
5441 | ||
9a799d71 AK |
5442 | /** |
5443 | * ixgbe_set_mac - Change the Ethernet Address of the NIC | |
5444 | * @netdev: network interface device structure | |
5445 | * @p: pointer to an address structure | |
5446 | * | |
5447 | * Returns 0 on success, negative on failure | |
5448 | **/ | |
5449 | static int ixgbe_set_mac(struct net_device *netdev, void *p) | |
5450 | { | |
5451 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
b4617240 | 5452 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 AK |
5453 | struct sockaddr *addr = p; |
5454 | ||
5455 | if (!is_valid_ether_addr(addr->sa_data)) | |
5456 | return -EADDRNOTAVAIL; | |
5457 | ||
5458 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | |
b4617240 | 5459 | memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); |
9a799d71 | 5460 | |
b4617240 | 5461 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); |
9a799d71 AK |
5462 | |
5463 | return 0; | |
5464 | } | |
5465 | ||
6b73e10d BH |
5466 | static int |
5467 | ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr) | |
5468 | { | |
5469 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
5470 | struct ixgbe_hw *hw = &adapter->hw; | |
5471 | u16 value; | |
5472 | int rc; | |
5473 | ||
5474 | if (prtad != hw->phy.mdio.prtad) | |
5475 | return -EINVAL; | |
5476 | rc = hw->phy.ops.read_reg(hw, addr, devad, &value); | |
5477 | if (!rc) | |
5478 | rc = value; | |
5479 | return rc; | |
5480 | } | |
5481 | ||
5482 | static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad, | |
5483 | u16 addr, u16 value) | |
5484 | { | |
5485 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
5486 | struct ixgbe_hw *hw = &adapter->hw; | |
5487 | ||
5488 | if (prtad != hw->phy.mdio.prtad) | |
5489 | return -EINVAL; | |
5490 | return hw->phy.ops.write_reg(hw, addr, devad, value); | |
5491 | } | |
5492 | ||
5493 | static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) | |
5494 | { | |
5495 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
5496 | ||
5497 | return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd); | |
5498 | } | |
5499 | ||
0365e6e4 PW |
5500 | /** |
5501 | * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding | |
31278e71 | 5502 | * netdev->dev_addrs |
0365e6e4 PW |
5503 | * @netdev: network interface device structure |
5504 | * | |
5505 | * Returns non-zero on failure | |
5506 | **/ | |
5507 | static int ixgbe_add_sanmac_netdev(struct net_device *dev) | |
5508 | { | |
5509 | int err = 0; | |
5510 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
5511 | struct ixgbe_mac_info *mac = &adapter->hw.mac; | |
5512 | ||
5513 | if (is_valid_ether_addr(mac->san_addr)) { | |
5514 | rtnl_lock(); | |
5515 | err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); | |
5516 | rtnl_unlock(); | |
5517 | } | |
5518 | return err; | |
5519 | } | |
5520 | ||
5521 | /** | |
5522 | * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding | |
31278e71 | 5523 | * netdev->dev_addrs |
0365e6e4 PW |
5524 | * @netdev: network interface device structure |
5525 | * | |
5526 | * Returns non-zero on failure | |
5527 | **/ | |
5528 | static int ixgbe_del_sanmac_netdev(struct net_device *dev) | |
5529 | { | |
5530 | int err = 0; | |
5531 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
5532 | struct ixgbe_mac_info *mac = &adapter->hw.mac; | |
5533 | ||
5534 | if (is_valid_ether_addr(mac->san_addr)) { | |
5535 | rtnl_lock(); | |
5536 | err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); | |
5537 | rtnl_unlock(); | |
5538 | } | |
5539 | return err; | |
5540 | } | |
5541 | ||
9a799d71 AK |
5542 | #ifdef CONFIG_NET_POLL_CONTROLLER |
5543 | /* | |
5544 | * Polling 'interrupt' - used by things like netconsole to send skbs | |
5545 | * without having to re-enable interrupts. It's not called while | |
5546 | * the interrupt routine is executing. | |
5547 | */ | |
5548 | static void ixgbe_netpoll(struct net_device *netdev) | |
5549 | { | |
5550 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
8f9a7167 | 5551 | int i; |
9a799d71 | 5552 | |
9a799d71 | 5553 | adapter->flags |= IXGBE_FLAG_IN_NETPOLL; |
8f9a7167 PWJ |
5554 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
5555 | int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
5556 | for (i = 0; i < num_q_vectors; i++) { | |
5557 | struct ixgbe_q_vector *q_vector = adapter->q_vector[i]; | |
5558 | ixgbe_msix_clean_many(0, q_vector); | |
5559 | } | |
5560 | } else { | |
5561 | ixgbe_intr(adapter->pdev->irq, netdev); | |
5562 | } | |
9a799d71 | 5563 | adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL; |
9a799d71 AK |
5564 | } |
5565 | #endif | |
5566 | ||
0edc3527 SH |
5567 | static const struct net_device_ops ixgbe_netdev_ops = { |
5568 | .ndo_open = ixgbe_open, | |
5569 | .ndo_stop = ixgbe_close, | |
00829823 | 5570 | .ndo_start_xmit = ixgbe_xmit_frame, |
09a3b1f8 | 5571 | .ndo_select_queue = ixgbe_select_queue, |
e90d400c | 5572 | .ndo_set_rx_mode = ixgbe_set_rx_mode, |
0edc3527 SH |
5573 | .ndo_set_multicast_list = ixgbe_set_rx_mode, |
5574 | .ndo_validate_addr = eth_validate_addr, | |
5575 | .ndo_set_mac_address = ixgbe_set_mac, | |
5576 | .ndo_change_mtu = ixgbe_change_mtu, | |
5577 | .ndo_tx_timeout = ixgbe_tx_timeout, | |
5578 | .ndo_vlan_rx_register = ixgbe_vlan_rx_register, | |
5579 | .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid, | |
5580 | .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid, | |
6b73e10d | 5581 | .ndo_do_ioctl = ixgbe_ioctl, |
0edc3527 SH |
5582 | #ifdef CONFIG_NET_POLL_CONTROLLER |
5583 | .ndo_poll_controller = ixgbe_netpoll, | |
5584 | #endif | |
332d4a7d YZ |
5585 | #ifdef IXGBE_FCOE |
5586 | .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get, | |
5587 | .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put, | |
8450ff8c YZ |
5588 | .ndo_fcoe_enable = ixgbe_fcoe_enable, |
5589 | .ndo_fcoe_disable = ixgbe_fcoe_disable, | |
61a1fa10 | 5590 | .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn, |
332d4a7d | 5591 | #endif /* IXGBE_FCOE */ |
0edc3527 SH |
5592 | }; |
5593 | ||
9a799d71 AK |
5594 | /** |
5595 | * ixgbe_probe - Device Initialization Routine | |
5596 | * @pdev: PCI device information struct | |
5597 | * @ent: entry in ixgbe_pci_tbl | |
5598 | * | |
5599 | * Returns 0 on success, negative on failure | |
5600 | * | |
5601 | * ixgbe_probe initializes an adapter identified by a pci_dev structure. | |
5602 | * The OS initialization, configuring of the adapter private structure, | |
5603 | * and a hardware reset occur. | |
5604 | **/ | |
5605 | static int __devinit ixgbe_probe(struct pci_dev *pdev, | |
b4617240 | 5606 | const struct pci_device_id *ent) |
9a799d71 AK |
5607 | { |
5608 | struct net_device *netdev; | |
5609 | struct ixgbe_adapter *adapter = NULL; | |
5610 | struct ixgbe_hw *hw; | |
5611 | const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data]; | |
9a799d71 AK |
5612 | static int cards_found; |
5613 | int i, err, pci_using_dac; | |
eacd73f7 YZ |
5614 | #ifdef IXGBE_FCOE |
5615 | u16 device_caps; | |
5616 | #endif | |
c44ade9e | 5617 | u32 part_num, eec; |
9a799d71 | 5618 | |
9ce77666 | 5619 | err = pci_enable_device_mem(pdev); |
9a799d71 AK |
5620 | if (err) |
5621 | return err; | |
5622 | ||
6a35528a YH |
5623 | if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && |
5624 | !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) { | |
9a799d71 AK |
5625 | pci_using_dac = 1; |
5626 | } else { | |
284901a9 | 5627 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
9a799d71 | 5628 | if (err) { |
284901a9 | 5629 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
9a799d71 | 5630 | if (err) { |
b4617240 PW |
5631 | dev_err(&pdev->dev, "No usable DMA " |
5632 | "configuration, aborting\n"); | |
9a799d71 AK |
5633 | goto err_dma; |
5634 | } | |
5635 | } | |
5636 | pci_using_dac = 0; | |
5637 | } | |
5638 | ||
9ce77666 | 5639 | err = pci_request_selected_regions(pdev, pci_select_bars(pdev, |
5640 | IORESOURCE_MEM), ixgbe_driver_name); | |
9a799d71 | 5641 | if (err) { |
9ce77666 | 5642 | dev_err(&pdev->dev, |
5643 | "pci_request_selected_regions failed 0x%x\n", err); | |
9a799d71 AK |
5644 | goto err_pci_reg; |
5645 | } | |
5646 | ||
19d5afd4 | 5647 | pci_enable_pcie_error_reporting(pdev); |
6fabd715 | 5648 | |
9a799d71 | 5649 | pci_set_master(pdev); |
fb3b27bc | 5650 | pci_save_state(pdev); |
9a799d71 | 5651 | |
30eba97a | 5652 | netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES); |
9a799d71 AK |
5653 | if (!netdev) { |
5654 | err = -ENOMEM; | |
5655 | goto err_alloc_etherdev; | |
5656 | } | |
5657 | ||
9a799d71 AK |
5658 | SET_NETDEV_DEV(netdev, &pdev->dev); |
5659 | ||
5660 | pci_set_drvdata(pdev, netdev); | |
5661 | adapter = netdev_priv(netdev); | |
5662 | ||
5663 | adapter->netdev = netdev; | |
5664 | adapter->pdev = pdev; | |
5665 | hw = &adapter->hw; | |
5666 | hw->back = adapter; | |
5667 | adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1; | |
5668 | ||
05857980 JK |
5669 | hw->hw_addr = ioremap(pci_resource_start(pdev, 0), |
5670 | pci_resource_len(pdev, 0)); | |
9a799d71 AK |
5671 | if (!hw->hw_addr) { |
5672 | err = -EIO; | |
5673 | goto err_ioremap; | |
5674 | } | |
5675 | ||
5676 | for (i = 1; i <= 5; i++) { | |
5677 | if (pci_resource_len(pdev, i) == 0) | |
5678 | continue; | |
5679 | } | |
5680 | ||
0edc3527 | 5681 | netdev->netdev_ops = &ixgbe_netdev_ops; |
9a799d71 | 5682 | ixgbe_set_ethtool_ops(netdev); |
9a799d71 | 5683 | netdev->watchdog_timeo = 5 * HZ; |
9a799d71 AK |
5684 | strcpy(netdev->name, pci_name(pdev)); |
5685 | ||
9a799d71 AK |
5686 | adapter->bd_number = cards_found; |
5687 | ||
9a799d71 AK |
5688 | /* Setup hw api */ |
5689 | memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops)); | |
021230d4 | 5690 | hw->mac.type = ii->mac; |
9a799d71 | 5691 | |
c44ade9e JB |
5692 | /* EEPROM */ |
5693 | memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops)); | |
5694 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); | |
5695 | /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */ | |
5696 | if (!(eec & (1 << 8))) | |
5697 | hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic; | |
5698 | ||
5699 | /* PHY */ | |
5700 | memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops)); | |
c4900be0 | 5701 | hw->phy.sfp_type = ixgbe_sfp_type_unknown; |
6b73e10d BH |
5702 | /* ixgbe_identify_phy_generic will set prtad and mmds properly */ |
5703 | hw->phy.mdio.prtad = MDIO_PRTAD_NONE; | |
5704 | hw->phy.mdio.mmds = 0; | |
5705 | hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; | |
5706 | hw->phy.mdio.dev = netdev; | |
5707 | hw->phy.mdio.mdio_read = ixgbe_mdio_read; | |
5708 | hw->phy.mdio.mdio_write = ixgbe_mdio_write; | |
c4900be0 DS |
5709 | |
5710 | /* set up this timer and work struct before calling get_invariants | |
5711 | * which might start the timer | |
5712 | */ | |
5713 | init_timer(&adapter->sfp_timer); | |
5714 | adapter->sfp_timer.function = &ixgbe_sfp_timer; | |
5715 | adapter->sfp_timer.data = (unsigned long) adapter; | |
5716 | ||
5717 | INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task); | |
c44ade9e | 5718 | |
e8e26350 PW |
5719 | /* multispeed fiber has its own tasklet, called from GPI SDP1 context */ |
5720 | INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task); | |
5721 | ||
5722 | /* a new SFP+ module arrival, called from GPI SDP2 context */ | |
5723 | INIT_WORK(&adapter->sfp_config_module_task, | |
5724 | ixgbe_sfp_config_module_task); | |
5725 | ||
8ca783ab | 5726 | ii->get_invariants(hw); |
9a799d71 AK |
5727 | |
5728 | /* setup the private structure */ | |
5729 | err = ixgbe_sw_init(adapter); | |
5730 | if (err) | |
5731 | goto err_sw_init; | |
5732 | ||
bf069c97 DS |
5733 | /* |
5734 | * If there is a fan on this device and it has failed log the | |
5735 | * failure. | |
5736 | */ | |
5737 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
5738 | u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); | |
5739 | if (esdp & IXGBE_ESDP_SDP1) | |
5740 | DPRINTK(PROBE, CRIT, | |
5741 | "Fan has stopped, replace the adapter\n"); | |
5742 | } | |
5743 | ||
c44ade9e JB |
5744 | /* reset_hw fills in the perm_addr as well */ |
5745 | err = hw->mac.ops.reset_hw(hw); | |
8ca783ab DS |
5746 | if (err == IXGBE_ERR_SFP_NOT_PRESENT && |
5747 | hw->mac.type == ixgbe_mac_82598EB) { | |
5748 | /* | |
5749 | * Start a kernel thread to watch for a module to arrive. | |
5750 | * Only do this for 82598, since 82599 will generate | |
5751 | * interrupts on module arrival. | |
5752 | */ | |
5753 | set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); | |
5754 | mod_timer(&adapter->sfp_timer, | |
5755 | round_jiffies(jiffies + (2 * HZ))); | |
5756 | err = 0; | |
5757 | } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
88d2b81f DS |
5758 | dev_err(&adapter->pdev->dev, "failed to initialize because " |
5759 | "an unsupported SFP+ module type was detected.\n" | |
5760 | "Reload the driver after installing a supported " | |
5761 | "module.\n"); | |
04f165ef PW |
5762 | goto err_sw_init; |
5763 | } else if (err) { | |
c44ade9e JB |
5764 | dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err); |
5765 | goto err_sw_init; | |
5766 | } | |
5767 | ||
9a799d71 | 5768 | netdev->features = NETIF_F_SG | |
b4617240 PW |
5769 | NETIF_F_IP_CSUM | |
5770 | NETIF_F_HW_VLAN_TX | | |
5771 | NETIF_F_HW_VLAN_RX | | |
5772 | NETIF_F_HW_VLAN_FILTER; | |
9a799d71 | 5773 | |
e9990a9c | 5774 | netdev->features |= NETIF_F_IPV6_CSUM; |
9a799d71 | 5775 | netdev->features |= NETIF_F_TSO; |
9a799d71 | 5776 | netdev->features |= NETIF_F_TSO6; |
78b6f4ce | 5777 | netdev->features |= NETIF_F_GRO; |
ad31c402 | 5778 | |
45a5ead0 JB |
5779 | if (adapter->hw.mac.type == ixgbe_mac_82599EB) |
5780 | netdev->features |= NETIF_F_SCTP_CSUM; | |
5781 | ||
ad31c402 JK |
5782 | netdev->vlan_features |= NETIF_F_TSO; |
5783 | netdev->vlan_features |= NETIF_F_TSO6; | |
22f32b7a | 5784 | netdev->vlan_features |= NETIF_F_IP_CSUM; |
cd1da503 | 5785 | netdev->vlan_features |= NETIF_F_IPV6_CSUM; |
ad31c402 JK |
5786 | netdev->vlan_features |= NETIF_F_SG; |
5787 | ||
2f90b865 AD |
5788 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) |
5789 | adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED; | |
5790 | ||
7a6b6f51 | 5791 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
5792 | netdev->dcbnl_ops = &dcbnl_ops; |
5793 | #endif | |
5794 | ||
eacd73f7 | 5795 | #ifdef IXGBE_FCOE |
0d551589 | 5796 | if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) { |
eacd73f7 YZ |
5797 | if (hw->mac.ops.get_device_caps) { |
5798 | hw->mac.ops.get_device_caps(hw, &device_caps); | |
0d551589 YZ |
5799 | if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS) |
5800 | adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; | |
eacd73f7 YZ |
5801 | } |
5802 | } | |
5803 | #endif /* IXGBE_FCOE */ | |
9a799d71 AK |
5804 | if (pci_using_dac) |
5805 | netdev->features |= NETIF_F_HIGHDMA; | |
5806 | ||
0c19d6af | 5807 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) |
f8212f97 AD |
5808 | netdev->features |= NETIF_F_LRO; |
5809 | ||
9a799d71 | 5810 | /* make sure the EEPROM is good */ |
c44ade9e | 5811 | if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) { |
9a799d71 AK |
5812 | dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n"); |
5813 | err = -EIO; | |
5814 | goto err_eeprom; | |
5815 | } | |
5816 | ||
5817 | memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len); | |
5818 | memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len); | |
5819 | ||
c44ade9e JB |
5820 | if (ixgbe_validate_mac_addr(netdev->perm_addr)) { |
5821 | dev_err(&pdev->dev, "invalid MAC address\n"); | |
9a799d71 AK |
5822 | err = -EIO; |
5823 | goto err_eeprom; | |
5824 | } | |
5825 | ||
5826 | init_timer(&adapter->watchdog_timer); | |
5827 | adapter->watchdog_timer.function = &ixgbe_watchdog; | |
5828 | adapter->watchdog_timer.data = (unsigned long)adapter; | |
5829 | ||
5830 | INIT_WORK(&adapter->reset_task, ixgbe_reset_task); | |
cf8280ee | 5831 | INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task); |
9a799d71 | 5832 | |
021230d4 AV |
5833 | err = ixgbe_init_interrupt_scheme(adapter); |
5834 | if (err) | |
5835 | goto err_sw_init; | |
9a799d71 | 5836 | |
e8e26350 PW |
5837 | switch (pdev->device) { |
5838 | case IXGBE_DEV_ID_82599_KX4: | |
495dce12 WJP |
5839 | adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX | |
5840 | IXGBE_WUFC_MC | IXGBE_WUFC_BC); | |
bdf0a550 PWJ |
5841 | /* Enable ACPI wakeup in GRC */ |
5842 | IXGBE_WRITE_REG(hw, IXGBE_GRC, | |
5843 | (IXGBE_READ_REG(hw, IXGBE_GRC) & ~IXGBE_GRC_APME)); | |
e8e26350 PW |
5844 | break; |
5845 | default: | |
5846 | adapter->wol = 0; | |
5847 | break; | |
5848 | } | |
e8e26350 PW |
5849 | device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); |
5850 | ||
04f165ef PW |
5851 | /* pick up the PCI bus settings for reporting later */ |
5852 | hw->mac.ops.get_bus_info(hw); | |
5853 | ||
9a799d71 | 5854 | /* print bus type/speed/width info */ |
7c510e4b | 5855 | dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n", |
e8e26350 PW |
5856 | ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s": |
5857 | (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"), | |
5858 | ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" : | |
5859 | (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" : | |
5860 | (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" : | |
b4617240 | 5861 | "Unknown"), |
7c510e4b | 5862 | netdev->dev_addr); |
c44ade9e | 5863 | ixgbe_read_pba_num_generic(hw, &part_num); |
e8e26350 PW |
5864 | if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) |
5865 | dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n", | |
5866 | hw->mac.type, hw->phy.type, hw->phy.sfp_type, | |
5867 | (part_num >> 8), (part_num & 0xff)); | |
5868 | else | |
5869 | dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n", | |
5870 | hw->mac.type, hw->phy.type, | |
5871 | (part_num >> 8), (part_num & 0xff)); | |
9a799d71 | 5872 | |
e8e26350 | 5873 | if (hw->bus.width <= ixgbe_bus_width_pcie_x4) { |
0c254d86 | 5874 | dev_warn(&pdev->dev, "PCI-Express bandwidth available for " |
b4617240 PW |
5875 | "this card is not sufficient for optimal " |
5876 | "performance.\n"); | |
0c254d86 | 5877 | dev_warn(&pdev->dev, "For optimal performance a x8 " |
b4617240 | 5878 | "PCI-Express slot is required.\n"); |
0c254d86 AK |
5879 | } |
5880 | ||
34b0368c PWJ |
5881 | /* save off EEPROM version number */ |
5882 | hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version); | |
5883 | ||
9a799d71 | 5884 | /* reset the hardware with the new settings */ |
794caeb2 | 5885 | err = hw->mac.ops.start_hw(hw); |
c44ade9e | 5886 | |
794caeb2 PWJ |
5887 | if (err == IXGBE_ERR_EEPROM_VERSION) { |
5888 | /* We are running on a pre-production device, log a warning */ | |
5889 | dev_warn(&pdev->dev, "This device is a pre-production " | |
5890 | "adapter/LOM. Please be aware there may be issues " | |
5891 | "associated with your hardware. If you are " | |
5892 | "experiencing problems please contact your Intel or " | |
5893 | "hardware representative who provided you with this " | |
5894 | "hardware.\n"); | |
5895 | } | |
9a799d71 AK |
5896 | strcpy(netdev->name, "eth%d"); |
5897 | err = register_netdev(netdev); | |
5898 | if (err) | |
5899 | goto err_register; | |
5900 | ||
54386467 JB |
5901 | /* carrier off reporting is important to ethtool even BEFORE open */ |
5902 | netif_carrier_off(netdev); | |
5903 | ||
c4cf55e5 PWJ |
5904 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || |
5905 | adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) | |
5906 | INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task); | |
5907 | ||
5dd2d332 | 5908 | #ifdef CONFIG_IXGBE_DCA |
652f093f | 5909 | if (dca_add_requester(&pdev->dev) == 0) { |
bd0362dd | 5910 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; |
bd0362dd JC |
5911 | ixgbe_setup_dca(adapter); |
5912 | } | |
5913 | #endif | |
0365e6e4 PW |
5914 | /* add san mac addr to netdev */ |
5915 | ixgbe_add_sanmac_netdev(netdev); | |
9a799d71 AK |
5916 | |
5917 | dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n"); | |
5918 | cards_found++; | |
5919 | return 0; | |
5920 | ||
5921 | err_register: | |
5eba3699 | 5922 | ixgbe_release_hw_control(adapter); |
7a921c93 | 5923 | ixgbe_clear_interrupt_scheme(adapter); |
9a799d71 AK |
5924 | err_sw_init: |
5925 | err_eeprom: | |
c4900be0 DS |
5926 | clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); |
5927 | del_timer_sync(&adapter->sfp_timer); | |
5928 | cancel_work_sync(&adapter->sfp_task); | |
e8e26350 PW |
5929 | cancel_work_sync(&adapter->multispeed_fiber_task); |
5930 | cancel_work_sync(&adapter->sfp_config_module_task); | |
9a799d71 AK |
5931 | iounmap(hw->hw_addr); |
5932 | err_ioremap: | |
5933 | free_netdev(netdev); | |
5934 | err_alloc_etherdev: | |
9ce77666 | 5935 | pci_release_selected_regions(pdev, pci_select_bars(pdev, |
5936 | IORESOURCE_MEM)); | |
9a799d71 AK |
5937 | err_pci_reg: |
5938 | err_dma: | |
5939 | pci_disable_device(pdev); | |
5940 | return err; | |
5941 | } | |
5942 | ||
5943 | /** | |
5944 | * ixgbe_remove - Device Removal Routine | |
5945 | * @pdev: PCI device information struct | |
5946 | * | |
5947 | * ixgbe_remove is called by the PCI subsystem to alert the driver | |
5948 | * that it should release a PCI device. The could be caused by a | |
5949 | * Hot-Plug event, or because the driver is going to be removed from | |
5950 | * memory. | |
5951 | **/ | |
5952 | static void __devexit ixgbe_remove(struct pci_dev *pdev) | |
5953 | { | |
5954 | struct net_device *netdev = pci_get_drvdata(pdev); | |
5955 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
5956 | ||
5957 | set_bit(__IXGBE_DOWN, &adapter->state); | |
c4900be0 DS |
5958 | /* clear the module not found bit to make sure the worker won't |
5959 | * reschedule | |
5960 | */ | |
5961 | clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); | |
9a799d71 AK |
5962 | del_timer_sync(&adapter->watchdog_timer); |
5963 | ||
c4900be0 DS |
5964 | del_timer_sync(&adapter->sfp_timer); |
5965 | cancel_work_sync(&adapter->watchdog_task); | |
5966 | cancel_work_sync(&adapter->sfp_task); | |
e8e26350 PW |
5967 | cancel_work_sync(&adapter->multispeed_fiber_task); |
5968 | cancel_work_sync(&adapter->sfp_config_module_task); | |
c4cf55e5 PWJ |
5969 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || |
5970 | adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) | |
5971 | cancel_work_sync(&adapter->fdir_reinit_task); | |
9a799d71 AK |
5972 | flush_scheduled_work(); |
5973 | ||
5dd2d332 | 5974 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
5975 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { |
5976 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
5977 | dca_remove_requester(&pdev->dev); | |
5978 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); | |
5979 | } | |
5980 | ||
5981 | #endif | |
332d4a7d YZ |
5982 | #ifdef IXGBE_FCOE |
5983 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) | |
5984 | ixgbe_cleanup_fcoe(adapter); | |
5985 | ||
5986 | #endif /* IXGBE_FCOE */ | |
0365e6e4 PW |
5987 | |
5988 | /* remove the added san mac */ | |
5989 | ixgbe_del_sanmac_netdev(netdev); | |
5990 | ||
c4900be0 DS |
5991 | if (netdev->reg_state == NETREG_REGISTERED) |
5992 | unregister_netdev(netdev); | |
9a799d71 | 5993 | |
7a921c93 | 5994 | ixgbe_clear_interrupt_scheme(adapter); |
5eba3699 | 5995 | |
021230d4 | 5996 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
5997 | |
5998 | iounmap(adapter->hw.hw_addr); | |
9ce77666 | 5999 | pci_release_selected_regions(pdev, pci_select_bars(pdev, |
6000 | IORESOURCE_MEM)); | |
9a799d71 | 6001 | |
021230d4 | 6002 | DPRINTK(PROBE, INFO, "complete\n"); |
021230d4 | 6003 | |
9a799d71 AK |
6004 | free_netdev(netdev); |
6005 | ||
19d5afd4 | 6006 | pci_disable_pcie_error_reporting(pdev); |
6fabd715 | 6007 | |
9a799d71 AK |
6008 | pci_disable_device(pdev); |
6009 | } | |
6010 | ||
6011 | /** | |
6012 | * ixgbe_io_error_detected - called when PCI error is detected | |
6013 | * @pdev: Pointer to PCI device | |
6014 | * @state: The current pci connection state | |
6015 | * | |
6016 | * This function is called after a PCI bus error affecting | |
6017 | * this device has been detected. | |
6018 | */ | |
6019 | static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev, | |
b4617240 | 6020 | pci_channel_state_t state) |
9a799d71 AK |
6021 | { |
6022 | struct net_device *netdev = pci_get_drvdata(pdev); | |
454d7c9b | 6023 | struct ixgbe_adapter *adapter = netdev_priv(netdev); |
9a799d71 AK |
6024 | |
6025 | netif_device_detach(netdev); | |
6026 | ||
3044b8d1 BL |
6027 | if (state == pci_channel_io_perm_failure) |
6028 | return PCI_ERS_RESULT_DISCONNECT; | |
6029 | ||
9a799d71 AK |
6030 | if (netif_running(netdev)) |
6031 | ixgbe_down(adapter); | |
6032 | pci_disable_device(pdev); | |
6033 | ||
b4617240 | 6034 | /* Request a slot reset. */ |
9a799d71 AK |
6035 | return PCI_ERS_RESULT_NEED_RESET; |
6036 | } | |
6037 | ||
6038 | /** | |
6039 | * ixgbe_io_slot_reset - called after the pci bus has been reset. | |
6040 | * @pdev: Pointer to PCI device | |
6041 | * | |
6042 | * Restart the card from scratch, as if from a cold-boot. | |
6043 | */ | |
6044 | static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev) | |
6045 | { | |
6046 | struct net_device *netdev = pci_get_drvdata(pdev); | |
454d7c9b | 6047 | struct ixgbe_adapter *adapter = netdev_priv(netdev); |
6fabd715 PWJ |
6048 | pci_ers_result_t result; |
6049 | int err; | |
9a799d71 | 6050 | |
9ce77666 | 6051 | if (pci_enable_device_mem(pdev)) { |
9a799d71 | 6052 | DPRINTK(PROBE, ERR, |
b4617240 | 6053 | "Cannot re-enable PCI device after reset.\n"); |
6fabd715 PWJ |
6054 | result = PCI_ERS_RESULT_DISCONNECT; |
6055 | } else { | |
6056 | pci_set_master(pdev); | |
6057 | pci_restore_state(pdev); | |
c0e1f68b | 6058 | pci_save_state(pdev); |
9a799d71 | 6059 | |
dd4d8ca6 | 6060 | pci_wake_from_d3(pdev, false); |
9a799d71 | 6061 | |
6fabd715 | 6062 | ixgbe_reset(adapter); |
88512539 | 6063 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
6fabd715 PWJ |
6064 | result = PCI_ERS_RESULT_RECOVERED; |
6065 | } | |
6066 | ||
6067 | err = pci_cleanup_aer_uncorrect_error_status(pdev); | |
6068 | if (err) { | |
6069 | dev_err(&pdev->dev, | |
6070 | "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err); | |
6071 | /* non-fatal, continue */ | |
6072 | } | |
9a799d71 | 6073 | |
6fabd715 | 6074 | return result; |
9a799d71 AK |
6075 | } |
6076 | ||
6077 | /** | |
6078 | * ixgbe_io_resume - called when traffic can start flowing again. | |
6079 | * @pdev: Pointer to PCI device | |
6080 | * | |
6081 | * This callback is called when the error recovery driver tells us that | |
6082 | * its OK to resume normal operation. | |
6083 | */ | |
6084 | static void ixgbe_io_resume(struct pci_dev *pdev) | |
6085 | { | |
6086 | struct net_device *netdev = pci_get_drvdata(pdev); | |
454d7c9b | 6087 | struct ixgbe_adapter *adapter = netdev_priv(netdev); |
9a799d71 AK |
6088 | |
6089 | if (netif_running(netdev)) { | |
6090 | if (ixgbe_up(adapter)) { | |
6091 | DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n"); | |
6092 | return; | |
6093 | } | |
6094 | } | |
6095 | ||
6096 | netif_device_attach(netdev); | |
9a799d71 AK |
6097 | } |
6098 | ||
6099 | static struct pci_error_handlers ixgbe_err_handler = { | |
6100 | .error_detected = ixgbe_io_error_detected, | |
6101 | .slot_reset = ixgbe_io_slot_reset, | |
6102 | .resume = ixgbe_io_resume, | |
6103 | }; | |
6104 | ||
6105 | static struct pci_driver ixgbe_driver = { | |
6106 | .name = ixgbe_driver_name, | |
6107 | .id_table = ixgbe_pci_tbl, | |
6108 | .probe = ixgbe_probe, | |
6109 | .remove = __devexit_p(ixgbe_remove), | |
6110 | #ifdef CONFIG_PM | |
6111 | .suspend = ixgbe_suspend, | |
6112 | .resume = ixgbe_resume, | |
6113 | #endif | |
6114 | .shutdown = ixgbe_shutdown, | |
6115 | .err_handler = &ixgbe_err_handler | |
6116 | }; | |
6117 | ||
6118 | /** | |
6119 | * ixgbe_init_module - Driver Registration Routine | |
6120 | * | |
6121 | * ixgbe_init_module is the first routine called when the driver is | |
6122 | * loaded. All it does is register with the PCI subsystem. | |
6123 | **/ | |
6124 | static int __init ixgbe_init_module(void) | |
6125 | { | |
6126 | int ret; | |
6127 | printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name, | |
6128 | ixgbe_driver_string, ixgbe_driver_version); | |
6129 | ||
6130 | printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright); | |
6131 | ||
5dd2d332 | 6132 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 6133 | dca_register_notify(&dca_notifier); |
bd0362dd | 6134 | #endif |
5dd2d332 | 6135 | |
9a799d71 AK |
6136 | ret = pci_register_driver(&ixgbe_driver); |
6137 | return ret; | |
6138 | } | |
b4617240 | 6139 | |
9a799d71 AK |
6140 | module_init(ixgbe_init_module); |
6141 | ||
6142 | /** | |
6143 | * ixgbe_exit_module - Driver Exit Cleanup Routine | |
6144 | * | |
6145 | * ixgbe_exit_module is called just before the driver is removed | |
6146 | * from memory. | |
6147 | **/ | |
6148 | static void __exit ixgbe_exit_module(void) | |
6149 | { | |
5dd2d332 | 6150 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
6151 | dca_unregister_notify(&dca_notifier); |
6152 | #endif | |
9a799d71 AK |
6153 | pci_unregister_driver(&ixgbe_driver); |
6154 | } | |
bd0362dd | 6155 | |
5dd2d332 | 6156 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 6157 | static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event, |
b4617240 | 6158 | void *p) |
bd0362dd JC |
6159 | { |
6160 | int ret_val; | |
6161 | ||
6162 | ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event, | |
b4617240 | 6163 | __ixgbe_notify_dca); |
bd0362dd JC |
6164 | |
6165 | return ret_val ? NOTIFY_BAD : NOTIFY_DONE; | |
6166 | } | |
b453368d | 6167 | |
5dd2d332 | 6168 | #endif /* CONFIG_IXGBE_DCA */ |
b453368d AD |
6169 | #ifdef DEBUG |
6170 | /** | |
6171 | * ixgbe_get_hw_dev_name - return device name string | |
6172 | * used by hardware layer to print debugging information | |
6173 | **/ | |
6174 | char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw) | |
6175 | { | |
6176 | struct ixgbe_adapter *adapter = hw->back; | |
6177 | return adapter->netdev->name; | |
6178 | } | |
bd0362dd | 6179 | |
b453368d | 6180 | #endif |
9a799d71 AK |
6181 | module_exit(ixgbe_exit_module); |
6182 | ||
6183 | /* ixgbe_main.c */ |