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9a799d71 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
a52055e0 | 4 | Copyright(c) 1999 - 2011 Intel Corporation. |
9a799d71 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
9a799d71 AK |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #include <linux/types.h> | |
29 | #include <linux/module.h> | |
30 | #include <linux/pci.h> | |
31 | #include <linux/netdevice.h> | |
32 | #include <linux/vmalloc.h> | |
33 | #include <linux/string.h> | |
34 | #include <linux/in.h> | |
a6b7a407 | 35 | #include <linux/interrupt.h> |
9a799d71 AK |
36 | #include <linux/ip.h> |
37 | #include <linux/tcp.h> | |
60127865 | 38 | #include <linux/pkt_sched.h> |
9a799d71 | 39 | #include <linux/ipv6.h> |
5a0e3ad6 | 40 | #include <linux/slab.h> |
9a799d71 AK |
41 | #include <net/checksum.h> |
42 | #include <net/ip6_checksum.h> | |
43 | #include <linux/ethtool.h> | |
44 | #include <linux/if_vlan.h> | |
70c71606 | 45 | #include <linux/prefetch.h> |
eacd73f7 | 46 | #include <scsi/fc/fc_fcoe.h> |
9a799d71 AK |
47 | |
48 | #include "ixgbe.h" | |
49 | #include "ixgbe_common.h" | |
ee5f784a | 50 | #include "ixgbe_dcb_82599.h" |
1cdd1ec8 | 51 | #include "ixgbe_sriov.h" |
9a799d71 AK |
52 | |
53 | char ixgbe_driver_name[] = "ixgbe"; | |
9c8eb720 | 54 | static const char ixgbe_driver_string[] = |
e8e9f696 | 55 | "Intel(R) 10 Gigabit PCI Express Network Driver"; |
75e3d3c6 | 56 | #define MAJ 3 |
c89c7112 DS |
57 | #define MIN 3 |
58 | #define BUILD 8 | |
75e3d3c6 JK |
59 | #define KFIX 2 |
60 | #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \ | |
61 | __stringify(BUILD) "-k" __stringify(KFIX) | |
9c8eb720 | 62 | const char ixgbe_driver_version[] = DRV_VERSION; |
a52055e0 DS |
63 | static const char ixgbe_copyright[] = |
64 | "Copyright (c) 1999-2011 Intel Corporation."; | |
9a799d71 AK |
65 | |
66 | static const struct ixgbe_info *ixgbe_info_tbl[] = { | |
b4617240 | 67 | [board_82598] = &ixgbe_82598_info, |
e8e26350 | 68 | [board_82599] = &ixgbe_82599_info, |
fe15e8e1 | 69 | [board_X540] = &ixgbe_X540_info, |
9a799d71 AK |
70 | }; |
71 | ||
72 | /* ixgbe_pci_tbl - PCI Device ID Table | |
73 | * | |
74 | * Wildcard entries (PCI_ANY_ID) should come last | |
75 | * Last entry must be all 0s | |
76 | * | |
77 | * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, | |
78 | * Class, Class Mask, private data (not used) } | |
79 | */ | |
a3aa1884 | 80 | static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = { |
1e336d0f DS |
81 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), |
82 | board_82598 }, | |
9a799d71 | 83 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), |
3957d63d | 84 | board_82598 }, |
9a799d71 | 85 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), |
3957d63d | 86 | board_82598 }, |
0befdb3e JB |
87 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), |
88 | board_82598 }, | |
3845bec0 PWJ |
89 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), |
90 | board_82598 }, | |
9a799d71 | 91 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), |
3957d63d | 92 | board_82598 }, |
8d792cd9 JB |
93 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), |
94 | board_82598 }, | |
c4900be0 DS |
95 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), |
96 | board_82598 }, | |
97 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), | |
98 | board_82598 }, | |
b95f5fcb JB |
99 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), |
100 | board_82598 }, | |
c4900be0 DS |
101 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), |
102 | board_82598 }, | |
2f21bdd3 DS |
103 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), |
104 | board_82598 }, | |
e8e26350 PW |
105 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), |
106 | board_82599 }, | |
1fcf03e6 PWJ |
107 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), |
108 | board_82599 }, | |
74757d49 DS |
109 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), |
110 | board_82599 }, | |
e8e26350 PW |
111 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), |
112 | board_82599 }, | |
38ad1c8e DS |
113 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), |
114 | board_82599 }, | |
dbfec662 DS |
115 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), |
116 | board_82599 }, | |
8911184f PWJ |
117 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), |
118 | board_82599 }, | |
dbffcb21 DS |
119 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), |
120 | board_82599 }, | |
121 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), | |
122 | board_82599 }, | |
119fc60a MC |
123 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), |
124 | board_82599 }, | |
312eb931 DS |
125 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), |
126 | board_82599 }, | |
b93a2226 | 127 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), |
d994653d | 128 | board_X540 }, |
4c40ef02 ET |
129 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), |
130 | board_82599 }, | |
4f6290cf DS |
131 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), |
132 | board_82599 }, | |
9a799d71 AK |
133 | |
134 | /* required last entry */ | |
135 | {0, } | |
136 | }; | |
137 | MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl); | |
138 | ||
5dd2d332 | 139 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 140 | static int ixgbe_notify_dca(struct notifier_block *, unsigned long event, |
e8e9f696 | 141 | void *p); |
bd0362dd JC |
142 | static struct notifier_block dca_notifier = { |
143 | .notifier_call = ixgbe_notify_dca, | |
144 | .next = NULL, | |
145 | .priority = 0 | |
146 | }; | |
147 | #endif | |
148 | ||
1cdd1ec8 GR |
149 | #ifdef CONFIG_PCI_IOV |
150 | static unsigned int max_vfs; | |
151 | module_param(max_vfs, uint, 0); | |
e8e9f696 JP |
152 | MODULE_PARM_DESC(max_vfs, |
153 | "Maximum number of virtual functions to allocate per physical function"); | |
1cdd1ec8 GR |
154 | #endif /* CONFIG_PCI_IOV */ |
155 | ||
9a799d71 AK |
156 | MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); |
157 | MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver"); | |
158 | MODULE_LICENSE("GPL"); | |
159 | MODULE_VERSION(DRV_VERSION); | |
160 | ||
161 | #define DEFAULT_DEBUG_LEVEL_SHIFT 3 | |
162 | ||
1cdd1ec8 GR |
163 | static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter) |
164 | { | |
165 | struct ixgbe_hw *hw = &adapter->hw; | |
166 | u32 gcr; | |
167 | u32 gpie; | |
168 | u32 vmdctl; | |
169 | ||
170 | #ifdef CONFIG_PCI_IOV | |
171 | /* disable iov and allow time for transactions to clear */ | |
172 | pci_disable_sriov(adapter->pdev); | |
173 | #endif | |
174 | ||
175 | /* turn off device IOV mode */ | |
176 | gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); | |
177 | gcr &= ~(IXGBE_GCR_EXT_SRIOV); | |
178 | IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr); | |
179 | gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); | |
180 | gpie &= ~IXGBE_GPIE_VTMODE_MASK; | |
181 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
182 | ||
183 | /* set default pool back to 0 */ | |
184 | vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); | |
185 | vmdctl &= ~IXGBE_VT_CTL_POOL_MASK; | |
186 | IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl); | |
187 | ||
188 | /* take a breather then clean up driver data */ | |
189 | msleep(100); | |
e8e9f696 JP |
190 | |
191 | kfree(adapter->vfinfo); | |
1cdd1ec8 GR |
192 | adapter->vfinfo = NULL; |
193 | ||
194 | adapter->num_vfs = 0; | |
195 | adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED; | |
196 | } | |
197 | ||
7086400d AD |
198 | static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter) |
199 | { | |
200 | if (!test_bit(__IXGBE_DOWN, &adapter->state) && | |
201 | !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state)) | |
202 | schedule_work(&adapter->service_task); | |
203 | } | |
204 | ||
205 | static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter) | |
206 | { | |
207 | BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state)); | |
208 | ||
209 | /* flush memory to make sure state is correct before next watchog */ | |
210 | smp_mb__before_clear_bit(); | |
211 | clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); | |
212 | } | |
213 | ||
dcd79aeb TI |
214 | struct ixgbe_reg_info { |
215 | u32 ofs; | |
216 | char *name; | |
217 | }; | |
218 | ||
219 | static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = { | |
220 | ||
221 | /* General Registers */ | |
222 | {IXGBE_CTRL, "CTRL"}, | |
223 | {IXGBE_STATUS, "STATUS"}, | |
224 | {IXGBE_CTRL_EXT, "CTRL_EXT"}, | |
225 | ||
226 | /* Interrupt Registers */ | |
227 | {IXGBE_EICR, "EICR"}, | |
228 | ||
229 | /* RX Registers */ | |
230 | {IXGBE_SRRCTL(0), "SRRCTL"}, | |
231 | {IXGBE_DCA_RXCTRL(0), "DRXCTL"}, | |
232 | {IXGBE_RDLEN(0), "RDLEN"}, | |
233 | {IXGBE_RDH(0), "RDH"}, | |
234 | {IXGBE_RDT(0), "RDT"}, | |
235 | {IXGBE_RXDCTL(0), "RXDCTL"}, | |
236 | {IXGBE_RDBAL(0), "RDBAL"}, | |
237 | {IXGBE_RDBAH(0), "RDBAH"}, | |
238 | ||
239 | /* TX Registers */ | |
240 | {IXGBE_TDBAL(0), "TDBAL"}, | |
241 | {IXGBE_TDBAH(0), "TDBAH"}, | |
242 | {IXGBE_TDLEN(0), "TDLEN"}, | |
243 | {IXGBE_TDH(0), "TDH"}, | |
244 | {IXGBE_TDT(0), "TDT"}, | |
245 | {IXGBE_TXDCTL(0), "TXDCTL"}, | |
246 | ||
247 | /* List Terminator */ | |
248 | {} | |
249 | }; | |
250 | ||
251 | ||
252 | /* | |
253 | * ixgbe_regdump - register printout routine | |
254 | */ | |
255 | static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo) | |
256 | { | |
257 | int i = 0, j = 0; | |
258 | char rname[16]; | |
259 | u32 regs[64]; | |
260 | ||
261 | switch (reginfo->ofs) { | |
262 | case IXGBE_SRRCTL(0): | |
263 | for (i = 0; i < 64; i++) | |
264 | regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); | |
265 | break; | |
266 | case IXGBE_DCA_RXCTRL(0): | |
267 | for (i = 0; i < 64; i++) | |
268 | regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); | |
269 | break; | |
270 | case IXGBE_RDLEN(0): | |
271 | for (i = 0; i < 64; i++) | |
272 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i)); | |
273 | break; | |
274 | case IXGBE_RDH(0): | |
275 | for (i = 0; i < 64; i++) | |
276 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i)); | |
277 | break; | |
278 | case IXGBE_RDT(0): | |
279 | for (i = 0; i < 64; i++) | |
280 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i)); | |
281 | break; | |
282 | case IXGBE_RXDCTL(0): | |
283 | for (i = 0; i < 64; i++) | |
284 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); | |
285 | break; | |
286 | case IXGBE_RDBAL(0): | |
287 | for (i = 0; i < 64; i++) | |
288 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i)); | |
289 | break; | |
290 | case IXGBE_RDBAH(0): | |
291 | for (i = 0; i < 64; i++) | |
292 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i)); | |
293 | break; | |
294 | case IXGBE_TDBAL(0): | |
295 | for (i = 0; i < 64; i++) | |
296 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i)); | |
297 | break; | |
298 | case IXGBE_TDBAH(0): | |
299 | for (i = 0; i < 64; i++) | |
300 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i)); | |
301 | break; | |
302 | case IXGBE_TDLEN(0): | |
303 | for (i = 0; i < 64; i++) | |
304 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i)); | |
305 | break; | |
306 | case IXGBE_TDH(0): | |
307 | for (i = 0; i < 64; i++) | |
308 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i)); | |
309 | break; | |
310 | case IXGBE_TDT(0): | |
311 | for (i = 0; i < 64; i++) | |
312 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i)); | |
313 | break; | |
314 | case IXGBE_TXDCTL(0): | |
315 | for (i = 0; i < 64; i++) | |
316 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); | |
317 | break; | |
318 | default: | |
c7689578 | 319 | pr_info("%-15s %08x\n", reginfo->name, |
dcd79aeb TI |
320 | IXGBE_READ_REG(hw, reginfo->ofs)); |
321 | return; | |
322 | } | |
323 | ||
324 | for (i = 0; i < 8; i++) { | |
325 | snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7); | |
c7689578 | 326 | pr_err("%-15s", rname); |
dcd79aeb | 327 | for (j = 0; j < 8; j++) |
c7689578 JP |
328 | pr_cont(" %08x", regs[i*8+j]); |
329 | pr_cont("\n"); | |
dcd79aeb TI |
330 | } |
331 | ||
332 | } | |
333 | ||
334 | /* | |
335 | * ixgbe_dump - Print registers, tx-rings and rx-rings | |
336 | */ | |
337 | static void ixgbe_dump(struct ixgbe_adapter *adapter) | |
338 | { | |
339 | struct net_device *netdev = adapter->netdev; | |
340 | struct ixgbe_hw *hw = &adapter->hw; | |
341 | struct ixgbe_reg_info *reginfo; | |
342 | int n = 0; | |
343 | struct ixgbe_ring *tx_ring; | |
344 | struct ixgbe_tx_buffer *tx_buffer_info; | |
345 | union ixgbe_adv_tx_desc *tx_desc; | |
346 | struct my_u0 { u64 a; u64 b; } *u0; | |
347 | struct ixgbe_ring *rx_ring; | |
348 | union ixgbe_adv_rx_desc *rx_desc; | |
349 | struct ixgbe_rx_buffer *rx_buffer_info; | |
350 | u32 staterr; | |
351 | int i = 0; | |
352 | ||
353 | if (!netif_msg_hw(adapter)) | |
354 | return; | |
355 | ||
356 | /* Print netdevice Info */ | |
357 | if (netdev) { | |
358 | dev_info(&adapter->pdev->dev, "Net device Info\n"); | |
c7689578 | 359 | pr_info("Device Name state " |
dcd79aeb | 360 | "trans_start last_rx\n"); |
c7689578 JP |
361 | pr_info("%-15s %016lX %016lX %016lX\n", |
362 | netdev->name, | |
363 | netdev->state, | |
364 | netdev->trans_start, | |
365 | netdev->last_rx); | |
dcd79aeb TI |
366 | } |
367 | ||
368 | /* Print Registers */ | |
369 | dev_info(&adapter->pdev->dev, "Register Dump\n"); | |
c7689578 | 370 | pr_info(" Register Name Value\n"); |
dcd79aeb TI |
371 | for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl; |
372 | reginfo->name; reginfo++) { | |
373 | ixgbe_regdump(hw, reginfo); | |
374 | } | |
375 | ||
376 | /* Print TX Ring Summary */ | |
377 | if (!netdev || !netif_running(netdev)) | |
378 | goto exit; | |
379 | ||
380 | dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); | |
c7689578 | 381 | pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); |
dcd79aeb TI |
382 | for (n = 0; n < adapter->num_tx_queues; n++) { |
383 | tx_ring = adapter->tx_ring[n]; | |
384 | tx_buffer_info = | |
385 | &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; | |
c7689578 | 386 | pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n", |
dcd79aeb TI |
387 | n, tx_ring->next_to_use, tx_ring->next_to_clean, |
388 | (u64)tx_buffer_info->dma, | |
389 | tx_buffer_info->length, | |
390 | tx_buffer_info->next_to_watch, | |
391 | (u64)tx_buffer_info->time_stamp); | |
392 | } | |
393 | ||
394 | /* Print TX Rings */ | |
395 | if (!netif_msg_tx_done(adapter)) | |
396 | goto rx_ring_summary; | |
397 | ||
398 | dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); | |
399 | ||
400 | /* Transmit Descriptor Formats | |
401 | * | |
402 | * Advanced Transmit Descriptor | |
403 | * +--------------------------------------------------------------+ | |
404 | * 0 | Buffer Address [63:0] | | |
405 | * +--------------------------------------------------------------+ | |
406 | * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN | | |
407 | * +--------------------------------------------------------------+ | |
408 | * 63 46 45 40 39 36 35 32 31 24 23 20 19 0 | |
409 | */ | |
410 | ||
411 | for (n = 0; n < adapter->num_tx_queues; n++) { | |
412 | tx_ring = adapter->tx_ring[n]; | |
c7689578 JP |
413 | pr_info("------------------------------------\n"); |
414 | pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); | |
415 | pr_info("------------------------------------\n"); | |
416 | pr_info("T [desc] [address 63:0 ] " | |
dcd79aeb TI |
417 | "[PlPOIdStDDt Ln] [bi->dma ] " |
418 | "leng ntw timestamp bi->skb\n"); | |
419 | ||
420 | for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { | |
31f05a2d | 421 | tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i); |
dcd79aeb TI |
422 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; |
423 | u0 = (struct my_u0 *)tx_desc; | |
c7689578 | 424 | pr_info("T [0x%03X] %016llX %016llX %016llX" |
dcd79aeb TI |
425 | " %04X %3X %016llX %p", i, |
426 | le64_to_cpu(u0->a), | |
427 | le64_to_cpu(u0->b), | |
428 | (u64)tx_buffer_info->dma, | |
429 | tx_buffer_info->length, | |
430 | tx_buffer_info->next_to_watch, | |
431 | (u64)tx_buffer_info->time_stamp, | |
432 | tx_buffer_info->skb); | |
433 | if (i == tx_ring->next_to_use && | |
434 | i == tx_ring->next_to_clean) | |
c7689578 | 435 | pr_cont(" NTC/U\n"); |
dcd79aeb | 436 | else if (i == tx_ring->next_to_use) |
c7689578 | 437 | pr_cont(" NTU\n"); |
dcd79aeb | 438 | else if (i == tx_ring->next_to_clean) |
c7689578 | 439 | pr_cont(" NTC\n"); |
dcd79aeb | 440 | else |
c7689578 | 441 | pr_cont("\n"); |
dcd79aeb TI |
442 | |
443 | if (netif_msg_pktdata(adapter) && | |
444 | tx_buffer_info->dma != 0) | |
445 | print_hex_dump(KERN_INFO, "", | |
446 | DUMP_PREFIX_ADDRESS, 16, 1, | |
447 | phys_to_virt(tx_buffer_info->dma), | |
448 | tx_buffer_info->length, true); | |
449 | } | |
450 | } | |
451 | ||
452 | /* Print RX Rings Summary */ | |
453 | rx_ring_summary: | |
454 | dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); | |
c7689578 | 455 | pr_info("Queue [NTU] [NTC]\n"); |
dcd79aeb TI |
456 | for (n = 0; n < adapter->num_rx_queues; n++) { |
457 | rx_ring = adapter->rx_ring[n]; | |
c7689578 JP |
458 | pr_info("%5d %5X %5X\n", |
459 | n, rx_ring->next_to_use, rx_ring->next_to_clean); | |
dcd79aeb TI |
460 | } |
461 | ||
462 | /* Print RX Rings */ | |
463 | if (!netif_msg_rx_status(adapter)) | |
464 | goto exit; | |
465 | ||
466 | dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); | |
467 | ||
468 | /* Advanced Receive Descriptor (Read) Format | |
469 | * 63 1 0 | |
470 | * +-----------------------------------------------------+ | |
471 | * 0 | Packet Buffer Address [63:1] |A0/NSE| | |
472 | * +----------------------------------------------+------+ | |
473 | * 8 | Header Buffer Address [63:1] | DD | | |
474 | * +-----------------------------------------------------+ | |
475 | * | |
476 | * | |
477 | * Advanced Receive Descriptor (Write-Back) Format | |
478 | * | |
479 | * 63 48 47 32 31 30 21 20 16 15 4 3 0 | |
480 | * +------------------------------------------------------+ | |
481 | * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | | |
482 | * | Checksum Ident | | | | Type | Type | | |
483 | * +------------------------------------------------------+ | |
484 | * 8 | VLAN Tag | Length | Extended Error | Extended Status | | |
485 | * +------------------------------------------------------+ | |
486 | * 63 48 47 32 31 20 19 0 | |
487 | */ | |
488 | for (n = 0; n < adapter->num_rx_queues; n++) { | |
489 | rx_ring = adapter->rx_ring[n]; | |
c7689578 JP |
490 | pr_info("------------------------------------\n"); |
491 | pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); | |
492 | pr_info("------------------------------------\n"); | |
493 | pr_info("R [desc] [ PktBuf A0] " | |
dcd79aeb TI |
494 | "[ HeadBuf DD] [bi->dma ] [bi->skb] " |
495 | "<-- Adv Rx Read format\n"); | |
c7689578 | 496 | pr_info("RWB[desc] [PcsmIpSHl PtRs] " |
dcd79aeb TI |
497 | "[vl er S cks ln] ---------------- [bi->skb] " |
498 | "<-- Adv Rx Write-Back format\n"); | |
499 | ||
500 | for (i = 0; i < rx_ring->count; i++) { | |
501 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; | |
31f05a2d | 502 | rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i); |
dcd79aeb TI |
503 | u0 = (struct my_u0 *)rx_desc; |
504 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
505 | if (staterr & IXGBE_RXD_STAT_DD) { | |
506 | /* Descriptor Done */ | |
c7689578 | 507 | pr_info("RWB[0x%03X] %016llX " |
dcd79aeb TI |
508 | "%016llX ---------------- %p", i, |
509 | le64_to_cpu(u0->a), | |
510 | le64_to_cpu(u0->b), | |
511 | rx_buffer_info->skb); | |
512 | } else { | |
c7689578 | 513 | pr_info("R [0x%03X] %016llX " |
dcd79aeb TI |
514 | "%016llX %016llX %p", i, |
515 | le64_to_cpu(u0->a), | |
516 | le64_to_cpu(u0->b), | |
517 | (u64)rx_buffer_info->dma, | |
518 | rx_buffer_info->skb); | |
519 | ||
520 | if (netif_msg_pktdata(adapter)) { | |
521 | print_hex_dump(KERN_INFO, "", | |
522 | DUMP_PREFIX_ADDRESS, 16, 1, | |
523 | phys_to_virt(rx_buffer_info->dma), | |
524 | rx_ring->rx_buf_len, true); | |
525 | ||
526 | if (rx_ring->rx_buf_len | |
527 | < IXGBE_RXBUFFER_2048) | |
528 | print_hex_dump(KERN_INFO, "", | |
529 | DUMP_PREFIX_ADDRESS, 16, 1, | |
530 | phys_to_virt( | |
531 | rx_buffer_info->page_dma + | |
532 | rx_buffer_info->page_offset | |
533 | ), | |
534 | PAGE_SIZE/2, true); | |
535 | } | |
536 | } | |
537 | ||
538 | if (i == rx_ring->next_to_use) | |
c7689578 | 539 | pr_cont(" NTU\n"); |
dcd79aeb | 540 | else if (i == rx_ring->next_to_clean) |
c7689578 | 541 | pr_cont(" NTC\n"); |
dcd79aeb | 542 | else |
c7689578 | 543 | pr_cont("\n"); |
dcd79aeb TI |
544 | |
545 | } | |
546 | } | |
547 | ||
548 | exit: | |
549 | return; | |
550 | } | |
551 | ||
5eba3699 AV |
552 | static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter) |
553 | { | |
554 | u32 ctrl_ext; | |
555 | ||
556 | /* Let firmware take over control of h/w */ | |
557 | ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); | |
558 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, | |
e8e9f696 | 559 | ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD); |
5eba3699 AV |
560 | } |
561 | ||
562 | static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter) | |
563 | { | |
564 | u32 ctrl_ext; | |
565 | ||
566 | /* Let firmware know the driver has taken over */ | |
567 | ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); | |
568 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, | |
e8e9f696 | 569 | ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD); |
5eba3699 | 570 | } |
9a799d71 | 571 | |
e8e26350 PW |
572 | /* |
573 | * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors | |
574 | * @adapter: pointer to adapter struct | |
575 | * @direction: 0 for Rx, 1 for Tx, -1 for other causes | |
576 | * @queue: queue to map the corresponding interrupt to | |
577 | * @msix_vector: the vector to map to the corresponding queue | |
578 | * | |
579 | */ | |
580 | static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction, | |
e8e9f696 | 581 | u8 queue, u8 msix_vector) |
9a799d71 AK |
582 | { |
583 | u32 ivar, index; | |
e8e26350 PW |
584 | struct ixgbe_hw *hw = &adapter->hw; |
585 | switch (hw->mac.type) { | |
586 | case ixgbe_mac_82598EB: | |
587 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
588 | if (direction == -1) | |
589 | direction = 0; | |
590 | index = (((direction * 64) + queue) >> 2) & 0x1F; | |
591 | ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); | |
592 | ivar &= ~(0xFF << (8 * (queue & 0x3))); | |
593 | ivar |= (msix_vector << (8 * (queue & 0x3))); | |
594 | IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar); | |
595 | break; | |
596 | case ixgbe_mac_82599EB: | |
b93a2226 | 597 | case ixgbe_mac_X540: |
e8e26350 PW |
598 | if (direction == -1) { |
599 | /* other causes */ | |
600 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
601 | index = ((queue & 1) * 8); | |
602 | ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC); | |
603 | ivar &= ~(0xFF << index); | |
604 | ivar |= (msix_vector << index); | |
605 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar); | |
606 | break; | |
607 | } else { | |
608 | /* tx or rx causes */ | |
609 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
610 | index = ((16 * (queue & 1)) + (8 * direction)); | |
611 | ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); | |
612 | ivar &= ~(0xFF << index); | |
613 | ivar |= (msix_vector << index); | |
614 | IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar); | |
615 | break; | |
616 | } | |
617 | default: | |
618 | break; | |
619 | } | |
9a799d71 AK |
620 | } |
621 | ||
fe49f04a | 622 | static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter, |
e8e9f696 | 623 | u64 qmask) |
fe49f04a AD |
624 | { |
625 | u32 mask; | |
626 | ||
bd508178 AD |
627 | switch (adapter->hw.mac.type) { |
628 | case ixgbe_mac_82598EB: | |
fe49f04a AD |
629 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); |
630 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); | |
bd508178 AD |
631 | break; |
632 | case ixgbe_mac_82599EB: | |
b93a2226 | 633 | case ixgbe_mac_X540: |
fe49f04a AD |
634 | mask = (qmask & 0xFFFFFFFF); |
635 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask); | |
636 | mask = (qmask >> 32); | |
637 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask); | |
bd508178 AD |
638 | break; |
639 | default: | |
640 | break; | |
fe49f04a AD |
641 | } |
642 | } | |
643 | ||
b6ec895e AD |
644 | void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring, |
645 | struct ixgbe_tx_buffer *tx_buffer_info) | |
9a799d71 | 646 | { |
e5a43549 AD |
647 | if (tx_buffer_info->dma) { |
648 | if (tx_buffer_info->mapped_as_page) | |
b6ec895e | 649 | dma_unmap_page(tx_ring->dev, |
e5a43549 AD |
650 | tx_buffer_info->dma, |
651 | tx_buffer_info->length, | |
1b507730 | 652 | DMA_TO_DEVICE); |
e5a43549 | 653 | else |
b6ec895e | 654 | dma_unmap_single(tx_ring->dev, |
e5a43549 AD |
655 | tx_buffer_info->dma, |
656 | tx_buffer_info->length, | |
1b507730 | 657 | DMA_TO_DEVICE); |
e5a43549 AD |
658 | tx_buffer_info->dma = 0; |
659 | } | |
9a799d71 AK |
660 | if (tx_buffer_info->skb) { |
661 | dev_kfree_skb_any(tx_buffer_info->skb); | |
662 | tx_buffer_info->skb = NULL; | |
663 | } | |
44df32c5 | 664 | tx_buffer_info->time_stamp = 0; |
9a799d71 AK |
665 | /* tx_buffer_info must be completely set up in the transmit path */ |
666 | } | |
667 | ||
26f23d82 | 668 | /** |
c84d324c JF |
669 | * ixgbe_dcb_txq_to_tc - convert a reg index to a traffic class |
670 | * @adapter: driver private struct | |
671 | * @index: reg idx of queue to query (0-127) | |
26f23d82 | 672 | * |
25985edc | 673 | * Helper function to determine the traffic index for a particular |
c84d324c | 674 | * register index. |
26f23d82 | 675 | * |
c84d324c | 676 | * Returns : a tc index for use in range 0-7, or 0-3 |
26f23d82 | 677 | */ |
3b2ee943 | 678 | static u8 ixgbe_dcb_txq_to_tc(struct ixgbe_adapter *adapter, u8 reg_idx) |
26f23d82 | 679 | { |
c84d324c | 680 | int tc = -1; |
e5b64635 | 681 | int dcb_i = netdev_get_num_tc(adapter->netdev); |
26f23d82 | 682 | |
c84d324c JF |
683 | /* if DCB is not enabled the queues have no TC */ |
684 | if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) | |
685 | return tc; | |
26f23d82 | 686 | |
c84d324c JF |
687 | /* check valid range */ |
688 | if (reg_idx >= adapter->hw.mac.max_tx_queues) | |
689 | return tc; | |
690 | ||
691 | switch (adapter->hw.mac.type) { | |
692 | case ixgbe_mac_82598EB: | |
693 | tc = reg_idx >> 2; | |
694 | break; | |
695 | default: | |
696 | if (dcb_i != 4 && dcb_i != 8) | |
6837e895 | 697 | break; |
c84d324c JF |
698 | |
699 | /* if VMDq is enabled the lowest order bits determine TC */ | |
700 | if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED | | |
701 | IXGBE_FLAG_VMDQ_ENABLED)) { | |
702 | tc = reg_idx & (dcb_i - 1); | |
703 | break; | |
704 | } | |
705 | ||
706 | /* | |
707 | * Convert the reg_idx into the correct TC. This bitmask | |
708 | * targets the last full 32 ring traffic class and assigns | |
709 | * it a value of 1. From there the rest of the rings are | |
710 | * based on shifting the mask further up to include the | |
711 | * reg_idx / 16 and then reg_idx / 8. It assumes dcB_i | |
712 | * will only ever be 8 or 4 and that reg_idx will never | |
713 | * be greater then 128. The code without the power of 2 | |
714 | * optimizations would be: | |
715 | * (((reg_idx % 32) + 32) * dcb_i) >> (9 - reg_idx / 32) | |
716 | */ | |
717 | tc = ((reg_idx & 0X1F) + 0x20) * dcb_i; | |
718 | tc >>= 9 - (reg_idx >> 5); | |
719 | } | |
720 | ||
721 | return tc; | |
722 | } | |
723 | ||
724 | static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter) | |
725 | { | |
726 | struct ixgbe_hw *hw = &adapter->hw; | |
727 | struct ixgbe_hw_stats *hwstats = &adapter->stats; | |
728 | u32 data = 0; | |
729 | u32 xoff[8] = {0}; | |
730 | int i; | |
731 | ||
732 | if ((hw->fc.current_mode == ixgbe_fc_full) || | |
733 | (hw->fc.current_mode == ixgbe_fc_rx_pause)) { | |
734 | switch (hw->mac.type) { | |
735 | case ixgbe_mac_82598EB: | |
736 | data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); | |
6837e895 PW |
737 | break; |
738 | default: | |
c84d324c JF |
739 | data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); |
740 | } | |
741 | hwstats->lxoffrxc += data; | |
742 | ||
743 | /* refill credits (no tx hang) if we received xoff */ | |
744 | if (!data) | |
745 | return; | |
746 | ||
747 | for (i = 0; i < adapter->num_tx_queues; i++) | |
748 | clear_bit(__IXGBE_HANG_CHECK_ARMED, | |
749 | &adapter->tx_ring[i]->state); | |
750 | return; | |
751 | } else if (!(adapter->dcb_cfg.pfc_mode_enable)) | |
752 | return; | |
753 | ||
754 | /* update stats for each tc, only valid with PFC enabled */ | |
755 | for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) { | |
756 | switch (hw->mac.type) { | |
757 | case ixgbe_mac_82598EB: | |
758 | xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); | |
bd508178 | 759 | break; |
c84d324c JF |
760 | default: |
761 | xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); | |
26f23d82 | 762 | } |
c84d324c JF |
763 | hwstats->pxoffrxc[i] += xoff[i]; |
764 | } | |
765 | ||
766 | /* disarm tx queues that have received xoff frames */ | |
767 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
768 | struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; | |
769 | u32 tc = ixgbe_dcb_txq_to_tc(adapter, tx_ring->reg_idx); | |
770 | ||
771 | if (xoff[tc]) | |
772 | clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); | |
26f23d82 | 773 | } |
26f23d82 YZ |
774 | } |
775 | ||
c84d324c | 776 | static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring) |
9a799d71 | 777 | { |
c84d324c JF |
778 | return ring->tx_stats.completed; |
779 | } | |
780 | ||
781 | static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring) | |
782 | { | |
783 | struct ixgbe_adapter *adapter = netdev_priv(ring->netdev); | |
e01c31a5 | 784 | struct ixgbe_hw *hw = &adapter->hw; |
e01c31a5 | 785 | |
c84d324c JF |
786 | u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx)); |
787 | u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx)); | |
788 | ||
789 | if (head != tail) | |
790 | return (head < tail) ? | |
791 | tail - head : (tail + ring->count - head); | |
792 | ||
793 | return 0; | |
794 | } | |
795 | ||
796 | static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring) | |
797 | { | |
798 | u32 tx_done = ixgbe_get_tx_completed(tx_ring); | |
799 | u32 tx_done_old = tx_ring->tx_stats.tx_done_old; | |
800 | u32 tx_pending = ixgbe_get_tx_pending(tx_ring); | |
801 | bool ret = false; | |
802 | ||
7d637bcc | 803 | clear_check_for_tx_hang(tx_ring); |
c84d324c JF |
804 | |
805 | /* | |
806 | * Check for a hung queue, but be thorough. This verifies | |
807 | * that a transmit has been completed since the previous | |
808 | * check AND there is at least one packet pending. The | |
809 | * ARMED bit is set to indicate a potential hang. The | |
810 | * bit is cleared if a pause frame is received to remove | |
811 | * false hang detection due to PFC or 802.3x frames. By | |
812 | * requiring this to fail twice we avoid races with | |
813 | * pfc clearing the ARMED bit and conditions where we | |
814 | * run the check_tx_hang logic with a transmit completion | |
815 | * pending but without time to complete it yet. | |
816 | */ | |
817 | if ((tx_done_old == tx_done) && tx_pending) { | |
818 | /* make sure it is true for two checks in a row */ | |
819 | ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED, | |
820 | &tx_ring->state); | |
821 | } else { | |
822 | /* update completed stats and continue */ | |
823 | tx_ring->tx_stats.tx_done_old = tx_done; | |
824 | /* reset the countdown */ | |
825 | clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); | |
9a799d71 AK |
826 | } |
827 | ||
c84d324c | 828 | return ret; |
9a799d71 AK |
829 | } |
830 | ||
b4617240 PW |
831 | #define IXGBE_MAX_TXD_PWR 14 |
832 | #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR) | |
e092be60 AV |
833 | |
834 | /* Tx Descriptors needed, worst case */ | |
835 | #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \ | |
836 | (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0)) | |
837 | #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \ | |
b4617240 | 838 | MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */ |
e092be60 | 839 | |
c83c6cbd AD |
840 | /** |
841 | * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout | |
842 | * @adapter: driver private struct | |
843 | **/ | |
844 | static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter) | |
845 | { | |
846 | ||
847 | /* Do the reset outside of interrupt context */ | |
848 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { | |
849 | adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED; | |
850 | ixgbe_service_event_schedule(adapter); | |
851 | } | |
852 | } | |
e01c31a5 | 853 | |
9a799d71 AK |
854 | /** |
855 | * ixgbe_clean_tx_irq - Reclaim resources after transmit completes | |
fe49f04a | 856 | * @q_vector: structure containing interrupt and ring information |
e01c31a5 | 857 | * @tx_ring: tx ring to clean |
9a799d71 | 858 | **/ |
fe49f04a | 859 | static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector, |
e8e9f696 | 860 | struct ixgbe_ring *tx_ring) |
9a799d71 | 861 | { |
fe49f04a | 862 | struct ixgbe_adapter *adapter = q_vector->adapter; |
12207e49 PWJ |
863 | union ixgbe_adv_tx_desc *tx_desc, *eop_desc; |
864 | struct ixgbe_tx_buffer *tx_buffer_info; | |
e01c31a5 | 865 | unsigned int total_bytes = 0, total_packets = 0; |
b953799e | 866 | u16 i, eop, count = 0; |
9a799d71 AK |
867 | |
868 | i = tx_ring->next_to_clean; | |
12207e49 | 869 | eop = tx_ring->tx_buffer_info[i].next_to_watch; |
31f05a2d | 870 | eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop); |
12207e49 PWJ |
871 | |
872 | while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) && | |
9a1a69ad | 873 | (count < tx_ring->work_limit)) { |
12207e49 | 874 | bool cleaned = false; |
2d0bb1c1 | 875 | rmb(); /* read buffer_info after eop_desc */ |
12207e49 | 876 | for ( ; !cleaned; count++) { |
31f05a2d | 877 | tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i); |
9a799d71 | 878 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; |
8ad494b0 AD |
879 | |
880 | tx_desc->wb.status = 0; | |
12207e49 | 881 | cleaned = (i == eop); |
9a799d71 | 882 | |
8ad494b0 AD |
883 | i++; |
884 | if (i == tx_ring->count) | |
885 | i = 0; | |
e01c31a5 | 886 | |
8ad494b0 AD |
887 | if (cleaned && tx_buffer_info->skb) { |
888 | total_bytes += tx_buffer_info->bytecount; | |
889 | total_packets += tx_buffer_info->gso_segs; | |
e092be60 | 890 | } |
e01c31a5 | 891 | |
b6ec895e | 892 | ixgbe_unmap_and_free_tx_resource(tx_ring, |
e8e9f696 | 893 | tx_buffer_info); |
e01c31a5 | 894 | } |
12207e49 | 895 | |
c84d324c | 896 | tx_ring->tx_stats.completed++; |
12207e49 | 897 | eop = tx_ring->tx_buffer_info[i].next_to_watch; |
31f05a2d | 898 | eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop); |
12207e49 PWJ |
899 | } |
900 | ||
9a799d71 | 901 | tx_ring->next_to_clean = i; |
b953799e AD |
902 | tx_ring->total_bytes += total_bytes; |
903 | tx_ring->total_packets += total_packets; | |
904 | u64_stats_update_begin(&tx_ring->syncp); | |
905 | tx_ring->stats.packets += total_packets; | |
906 | tx_ring->stats.bytes += total_bytes; | |
907 | u64_stats_update_end(&tx_ring->syncp); | |
908 | ||
c84d324c JF |
909 | if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) { |
910 | /* schedule immediate reset if we believe we hung */ | |
911 | struct ixgbe_hw *hw = &adapter->hw; | |
912 | tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop); | |
913 | e_err(drv, "Detected Tx Unit Hang\n" | |
914 | " Tx Queue <%d>\n" | |
915 | " TDH, TDT <%x>, <%x>\n" | |
916 | " next_to_use <%x>\n" | |
917 | " next_to_clean <%x>\n" | |
918 | "tx_buffer_info[next_to_clean]\n" | |
919 | " time_stamp <%lx>\n" | |
920 | " jiffies <%lx>\n", | |
921 | tx_ring->queue_index, | |
922 | IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)), | |
923 | IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)), | |
924 | tx_ring->next_to_use, eop, | |
925 | tx_ring->tx_buffer_info[eop].time_stamp, jiffies); | |
926 | ||
927 | netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); | |
928 | ||
929 | e_info(probe, | |
930 | "tx hang %d detected on queue %d, resetting adapter\n", | |
931 | adapter->tx_timeout_count + 1, tx_ring->queue_index); | |
932 | ||
b953799e | 933 | /* schedule immediate reset if we believe we hung */ |
c83c6cbd | 934 | ixgbe_tx_timeout_reset(adapter); |
b953799e AD |
935 | |
936 | /* the adapter is about to reset, no point in enabling stuff */ | |
937 | return true; | |
938 | } | |
9a799d71 | 939 | |
e092be60 | 940 | #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) |
fc77dc3c | 941 | if (unlikely(count && netif_carrier_ok(tx_ring->netdev) && |
e8e9f696 | 942 | (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) { |
e092be60 AV |
943 | /* Make sure that anybody stopping the queue after this |
944 | * sees the new next_to_clean. | |
945 | */ | |
946 | smp_mb(); | |
fc77dc3c | 947 | if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) && |
30eba97a | 948 | !test_bit(__IXGBE_DOWN, &adapter->state)) { |
fc77dc3c | 949 | netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index); |
5b7da515 | 950 | ++tx_ring->tx_stats.restart_queue; |
30eba97a | 951 | } |
e092be60 | 952 | } |
9a799d71 | 953 | |
807540ba | 954 | return count < tx_ring->work_limit; |
9a799d71 AK |
955 | } |
956 | ||
5dd2d332 | 957 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 958 | static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter, |
33cf09c9 AD |
959 | struct ixgbe_ring *rx_ring, |
960 | int cpu) | |
bd0362dd | 961 | { |
33cf09c9 | 962 | struct ixgbe_hw *hw = &adapter->hw; |
bd0362dd | 963 | u32 rxctrl; |
33cf09c9 AD |
964 | u8 reg_idx = rx_ring->reg_idx; |
965 | ||
966 | rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx)); | |
967 | switch (hw->mac.type) { | |
968 | case ixgbe_mac_82598EB: | |
969 | rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK; | |
970 | rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu); | |
971 | break; | |
972 | case ixgbe_mac_82599EB: | |
b93a2226 | 973 | case ixgbe_mac_X540: |
33cf09c9 AD |
974 | rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599; |
975 | rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) << | |
976 | IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599); | |
977 | break; | |
978 | default: | |
979 | break; | |
bd0362dd | 980 | } |
33cf09c9 AD |
981 | rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN; |
982 | rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN; | |
983 | rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN); | |
33cf09c9 | 984 | IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl); |
bd0362dd JC |
985 | } |
986 | ||
987 | static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter, | |
33cf09c9 AD |
988 | struct ixgbe_ring *tx_ring, |
989 | int cpu) | |
bd0362dd | 990 | { |
33cf09c9 | 991 | struct ixgbe_hw *hw = &adapter->hw; |
bd0362dd | 992 | u32 txctrl; |
33cf09c9 AD |
993 | u8 reg_idx = tx_ring->reg_idx; |
994 | ||
995 | switch (hw->mac.type) { | |
996 | case ixgbe_mac_82598EB: | |
997 | txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx)); | |
998 | txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK; | |
999 | txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu); | |
1000 | txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN; | |
33cf09c9 AD |
1001 | IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl); |
1002 | break; | |
1003 | case ixgbe_mac_82599EB: | |
b93a2226 | 1004 | case ixgbe_mac_X540: |
33cf09c9 AD |
1005 | txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx)); |
1006 | txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599; | |
1007 | txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) << | |
1008 | IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599); | |
1009 | txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN; | |
33cf09c9 AD |
1010 | IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl); |
1011 | break; | |
1012 | default: | |
1013 | break; | |
1014 | } | |
1015 | } | |
1016 | ||
1017 | static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector) | |
1018 | { | |
1019 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
bd0362dd | 1020 | int cpu = get_cpu(); |
33cf09c9 AD |
1021 | long r_idx; |
1022 | int i; | |
bd0362dd | 1023 | |
33cf09c9 AD |
1024 | if (q_vector->cpu == cpu) |
1025 | goto out_no_update; | |
1026 | ||
1027 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
1028 | for (i = 0; i < q_vector->txr_count; i++) { | |
1029 | ixgbe_update_tx_dca(adapter, adapter->tx_ring[r_idx], cpu); | |
1030 | r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, | |
1031 | r_idx + 1); | |
bd0362dd | 1032 | } |
33cf09c9 AD |
1033 | |
1034 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
1035 | for (i = 0; i < q_vector->rxr_count; i++) { | |
1036 | ixgbe_update_rx_dca(adapter, adapter->rx_ring[r_idx], cpu); | |
1037 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, | |
1038 | r_idx + 1); | |
1039 | } | |
1040 | ||
1041 | q_vector->cpu = cpu; | |
1042 | out_no_update: | |
bd0362dd JC |
1043 | put_cpu(); |
1044 | } | |
1045 | ||
1046 | static void ixgbe_setup_dca(struct ixgbe_adapter *adapter) | |
1047 | { | |
33cf09c9 | 1048 | int num_q_vectors; |
bd0362dd JC |
1049 | int i; |
1050 | ||
1051 | if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED)) | |
1052 | return; | |
1053 | ||
e35ec126 AD |
1054 | /* always use CB2 mode, difference is masked in the CB driver */ |
1055 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2); | |
1056 | ||
33cf09c9 AD |
1057 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
1058 | num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
1059 | else | |
1060 | num_q_vectors = 1; | |
1061 | ||
1062 | for (i = 0; i < num_q_vectors; i++) { | |
1063 | adapter->q_vector[i]->cpu = -1; | |
1064 | ixgbe_update_dca(adapter->q_vector[i]); | |
bd0362dd JC |
1065 | } |
1066 | } | |
1067 | ||
1068 | static int __ixgbe_notify_dca(struct device *dev, void *data) | |
1069 | { | |
c60fbb00 | 1070 | struct ixgbe_adapter *adapter = dev_get_drvdata(dev); |
bd0362dd JC |
1071 | unsigned long event = *(unsigned long *)data; |
1072 | ||
33cf09c9 AD |
1073 | if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED)) |
1074 | return 0; | |
1075 | ||
bd0362dd JC |
1076 | switch (event) { |
1077 | case DCA_PROVIDER_ADD: | |
96b0e0f6 JB |
1078 | /* if we're already enabled, don't do it again */ |
1079 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
1080 | break; | |
652f093f | 1081 | if (dca_add_requester(dev) == 0) { |
96b0e0f6 | 1082 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; |
bd0362dd JC |
1083 | ixgbe_setup_dca(adapter); |
1084 | break; | |
1085 | } | |
1086 | /* Fall Through since DCA is disabled. */ | |
1087 | case DCA_PROVIDER_REMOVE: | |
1088 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { | |
1089 | dca_remove_requester(dev); | |
1090 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
1091 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); | |
1092 | } | |
1093 | break; | |
1094 | } | |
1095 | ||
652f093f | 1096 | return 0; |
bd0362dd | 1097 | } |
5dd2d332 | 1098 | #endif /* CONFIG_IXGBE_DCA */ |
67a74ee2 ET |
1099 | |
1100 | static inline void ixgbe_rx_hash(union ixgbe_adv_rx_desc *rx_desc, | |
1101 | struct sk_buff *skb) | |
1102 | { | |
1103 | skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss); | |
1104 | } | |
1105 | ||
9a799d71 AK |
1106 | /** |
1107 | * ixgbe_receive_skb - Send a completed packet up the stack | |
1108 | * @adapter: board private structure | |
1109 | * @skb: packet to send up | |
177db6ff MC |
1110 | * @status: hardware indication of status of receive |
1111 | * @rx_ring: rx descriptor ring (for a specific queue) to setup | |
1112 | * @rx_desc: rx descriptor | |
9a799d71 | 1113 | **/ |
78b6f4ce | 1114 | static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector, |
e8e9f696 JP |
1115 | struct sk_buff *skb, u8 status, |
1116 | struct ixgbe_ring *ring, | |
1117 | union ixgbe_adv_rx_desc *rx_desc) | |
9a799d71 | 1118 | { |
78b6f4ce HX |
1119 | struct ixgbe_adapter *adapter = q_vector->adapter; |
1120 | struct napi_struct *napi = &q_vector->napi; | |
177db6ff MC |
1121 | bool is_vlan = (status & IXGBE_RXD_STAT_VP); |
1122 | u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan); | |
9a799d71 | 1123 | |
f62bbb5e JG |
1124 | if (is_vlan && (tag & VLAN_VID_MASK)) |
1125 | __vlan_hwaccel_put_tag(skb, tag); | |
1126 | ||
1127 | if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) | |
1128 | napi_gro_receive(napi, skb); | |
1129 | else | |
1130 | netif_rx(skb); | |
9a799d71 AK |
1131 | } |
1132 | ||
e59bd25d AV |
1133 | /** |
1134 | * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum | |
1135 | * @adapter: address of board private structure | |
1136 | * @status_err: hardware indication of status of receive | |
1137 | * @skb: skb currently being received and modified | |
1138 | **/ | |
9a799d71 | 1139 | static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter, |
8bae1b2b DS |
1140 | union ixgbe_adv_rx_desc *rx_desc, |
1141 | struct sk_buff *skb) | |
9a799d71 | 1142 | { |
8bae1b2b DS |
1143 | u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error); |
1144 | ||
bc8acf2c | 1145 | skb_checksum_none_assert(skb); |
9a799d71 | 1146 | |
712744be JB |
1147 | /* Rx csum disabled */ |
1148 | if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED)) | |
9a799d71 | 1149 | return; |
e59bd25d AV |
1150 | |
1151 | /* if IP and error */ | |
1152 | if ((status_err & IXGBE_RXD_STAT_IPCS) && | |
1153 | (status_err & IXGBE_RXDADV_ERR_IPE)) { | |
9a799d71 AK |
1154 | adapter->hw_csum_rx_error++; |
1155 | return; | |
1156 | } | |
e59bd25d AV |
1157 | |
1158 | if (!(status_err & IXGBE_RXD_STAT_L4CS)) | |
1159 | return; | |
1160 | ||
1161 | if (status_err & IXGBE_RXDADV_ERR_TCPE) { | |
8bae1b2b DS |
1162 | u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; |
1163 | ||
1164 | /* | |
1165 | * 82599 errata, UDP frames with a 0 checksum can be marked as | |
1166 | * checksum errors. | |
1167 | */ | |
1168 | if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) && | |
1169 | (adapter->hw.mac.type == ixgbe_mac_82599EB)) | |
1170 | return; | |
1171 | ||
e59bd25d AV |
1172 | adapter->hw_csum_rx_error++; |
1173 | return; | |
1174 | } | |
1175 | ||
9a799d71 | 1176 | /* It must be a TCP or UDP packet with a valid checksum */ |
e59bd25d | 1177 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
9a799d71 AK |
1178 | } |
1179 | ||
84ea2591 | 1180 | static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val) |
e8e26350 PW |
1181 | { |
1182 | /* | |
1183 | * Force memory writes to complete before letting h/w | |
1184 | * know there are new descriptors to fetch. (Only | |
1185 | * applicable for weak-ordered memory model archs, | |
1186 | * such as IA-64). | |
1187 | */ | |
1188 | wmb(); | |
84ea2591 | 1189 | writel(val, rx_ring->tail); |
e8e26350 PW |
1190 | } |
1191 | ||
9a799d71 AK |
1192 | /** |
1193 | * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split | |
fc77dc3c AD |
1194 | * @rx_ring: ring to place buffers on |
1195 | * @cleaned_count: number of buffers to replace | |
9a799d71 | 1196 | **/ |
fc77dc3c | 1197 | void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count) |
9a799d71 | 1198 | { |
9a799d71 | 1199 | union ixgbe_adv_rx_desc *rx_desc; |
3a581073 | 1200 | struct ixgbe_rx_buffer *bi; |
d5f398ed AD |
1201 | struct sk_buff *skb; |
1202 | u16 i = rx_ring->next_to_use; | |
9a799d71 | 1203 | |
fc77dc3c AD |
1204 | /* do nothing if no valid netdev defined */ |
1205 | if (!rx_ring->netdev) | |
1206 | return; | |
1207 | ||
9a799d71 | 1208 | while (cleaned_count--) { |
31f05a2d | 1209 | rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i); |
d5f398ed AD |
1210 | bi = &rx_ring->rx_buffer_info[i]; |
1211 | skb = bi->skb; | |
9a799d71 | 1212 | |
d5f398ed | 1213 | if (!skb) { |
fc77dc3c | 1214 | skb = netdev_alloc_skb_ip_align(rx_ring->netdev, |
d5f398ed | 1215 | rx_ring->rx_buf_len); |
9a799d71 | 1216 | if (!skb) { |
5b7da515 | 1217 | rx_ring->rx_stats.alloc_rx_buff_failed++; |
9a799d71 AK |
1218 | goto no_buffers; |
1219 | } | |
d716a7d8 AD |
1220 | /* initialize queue mapping */ |
1221 | skb_record_rx_queue(skb, rx_ring->queue_index); | |
d5f398ed | 1222 | bi->skb = skb; |
d716a7d8 | 1223 | } |
9a799d71 | 1224 | |
d716a7d8 | 1225 | if (!bi->dma) { |
b6ec895e | 1226 | bi->dma = dma_map_single(rx_ring->dev, |
d5f398ed | 1227 | skb->data, |
e8e9f696 | 1228 | rx_ring->rx_buf_len, |
1b507730 | 1229 | DMA_FROM_DEVICE); |
b6ec895e | 1230 | if (dma_mapping_error(rx_ring->dev, bi->dma)) { |
5b7da515 | 1231 | rx_ring->rx_stats.alloc_rx_buff_failed++; |
d5f398ed AD |
1232 | bi->dma = 0; |
1233 | goto no_buffers; | |
1234 | } | |
9a799d71 | 1235 | } |
d5f398ed | 1236 | |
7d637bcc | 1237 | if (ring_is_ps_enabled(rx_ring)) { |
d5f398ed | 1238 | if (!bi->page) { |
fc77dc3c | 1239 | bi->page = netdev_alloc_page(rx_ring->netdev); |
d5f398ed | 1240 | if (!bi->page) { |
5b7da515 | 1241 | rx_ring->rx_stats.alloc_rx_page_failed++; |
d5f398ed AD |
1242 | goto no_buffers; |
1243 | } | |
1244 | } | |
1245 | ||
1246 | if (!bi->page_dma) { | |
1247 | /* use a half page if we're re-using */ | |
1248 | bi->page_offset ^= PAGE_SIZE / 2; | |
b6ec895e | 1249 | bi->page_dma = dma_map_page(rx_ring->dev, |
d5f398ed AD |
1250 | bi->page, |
1251 | bi->page_offset, | |
1252 | PAGE_SIZE / 2, | |
1253 | DMA_FROM_DEVICE); | |
b6ec895e | 1254 | if (dma_mapping_error(rx_ring->dev, |
d5f398ed | 1255 | bi->page_dma)) { |
5b7da515 | 1256 | rx_ring->rx_stats.alloc_rx_page_failed++; |
d5f398ed AD |
1257 | bi->page_dma = 0; |
1258 | goto no_buffers; | |
1259 | } | |
1260 | } | |
1261 | ||
1262 | /* Refresh the desc even if buffer_addrs didn't change | |
1263 | * because each write-back erases this info. */ | |
3a581073 JB |
1264 | rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma); |
1265 | rx_desc->read.hdr_addr = cpu_to_le64(bi->dma); | |
9a799d71 | 1266 | } else { |
3a581073 | 1267 | rx_desc->read.pkt_addr = cpu_to_le64(bi->dma); |
84418e3b | 1268 | rx_desc->read.hdr_addr = 0; |
9a799d71 AK |
1269 | } |
1270 | ||
1271 | i++; | |
1272 | if (i == rx_ring->count) | |
1273 | i = 0; | |
9a799d71 | 1274 | } |
7c6e0a43 | 1275 | |
9a799d71 AK |
1276 | no_buffers: |
1277 | if (rx_ring->next_to_use != i) { | |
1278 | rx_ring->next_to_use = i; | |
84ea2591 | 1279 | ixgbe_release_rx_desc(rx_ring, i); |
9a799d71 AK |
1280 | } |
1281 | } | |
1282 | ||
c267fc16 | 1283 | static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc) |
7c6e0a43 | 1284 | { |
c267fc16 AD |
1285 | /* HW will not DMA in data larger than the given buffer, even if it |
1286 | * parses the (NFS, of course) header to be larger. In that case, it | |
1287 | * fills the header buffer and spills the rest into the page. | |
1288 | */ | |
1289 | u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info); | |
1290 | u16 hlen = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >> | |
1291 | IXGBE_RXDADV_HDRBUFLEN_SHIFT; | |
1292 | if (hlen > IXGBE_RX_HDR_SIZE) | |
1293 | hlen = IXGBE_RX_HDR_SIZE; | |
1294 | return hlen; | |
7c6e0a43 JB |
1295 | } |
1296 | ||
f8212f97 AD |
1297 | /** |
1298 | * ixgbe_transform_rsc_queue - change rsc queue into a full packet | |
1299 | * @skb: pointer to the last skb in the rsc queue | |
1300 | * | |
1301 | * This function changes a queue full of hw rsc buffers into a completed | |
1302 | * packet. It uses the ->prev pointers to find the first packet and then | |
1303 | * turns it into the frag list owner. | |
1304 | **/ | |
aa80175a | 1305 | static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb) |
f8212f97 AD |
1306 | { |
1307 | unsigned int frag_list_size = 0; | |
aa80175a | 1308 | unsigned int skb_cnt = 1; |
f8212f97 AD |
1309 | |
1310 | while (skb->prev) { | |
1311 | struct sk_buff *prev = skb->prev; | |
1312 | frag_list_size += skb->len; | |
1313 | skb->prev = NULL; | |
1314 | skb = prev; | |
aa80175a | 1315 | skb_cnt++; |
f8212f97 AD |
1316 | } |
1317 | ||
1318 | skb_shinfo(skb)->frag_list = skb->next; | |
1319 | skb->next = NULL; | |
1320 | skb->len += frag_list_size; | |
1321 | skb->data_len += frag_list_size; | |
1322 | skb->truesize += frag_list_size; | |
aa80175a AD |
1323 | IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt; |
1324 | ||
f8212f97 AD |
1325 | return skb; |
1326 | } | |
1327 | ||
aa80175a AD |
1328 | static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc) |
1329 | { | |
1330 | return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) & | |
1331 | IXGBE_RXDADV_RSCCNT_MASK); | |
1332 | } | |
43634e82 | 1333 | |
c267fc16 | 1334 | static void ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, |
e8e9f696 JP |
1335 | struct ixgbe_ring *rx_ring, |
1336 | int *work_done, int work_to_do) | |
9a799d71 | 1337 | { |
78b6f4ce | 1338 | struct ixgbe_adapter *adapter = q_vector->adapter; |
9a799d71 AK |
1339 | union ixgbe_adv_rx_desc *rx_desc, *next_rxd; |
1340 | struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer; | |
1341 | struct sk_buff *skb; | |
d2f4fbe2 | 1342 | unsigned int total_rx_bytes = 0, total_rx_packets = 0; |
c267fc16 | 1343 | const int current_node = numa_node_id(); |
3d8fd385 YZ |
1344 | #ifdef IXGBE_FCOE |
1345 | int ddp_bytes = 0; | |
1346 | #endif /* IXGBE_FCOE */ | |
c267fc16 AD |
1347 | u32 staterr; |
1348 | u16 i; | |
1349 | u16 cleaned_count = 0; | |
aa80175a | 1350 | bool pkt_is_rsc = false; |
9a799d71 AK |
1351 | |
1352 | i = rx_ring->next_to_clean; | |
31f05a2d | 1353 | rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i); |
9a799d71 | 1354 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); |
9a799d71 AK |
1355 | |
1356 | while (staterr & IXGBE_RXD_STAT_DD) { | |
7c6e0a43 | 1357 | u32 upper_len = 0; |
9a799d71 | 1358 | |
3c945e5b | 1359 | rmb(); /* read descriptor and rx_buffer_info after status DD */ |
9a799d71 | 1360 | |
c267fc16 AD |
1361 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; |
1362 | ||
9a799d71 | 1363 | skb = rx_buffer_info->skb; |
9a799d71 | 1364 | rx_buffer_info->skb = NULL; |
c267fc16 | 1365 | prefetch(skb->data); |
9a799d71 | 1366 | |
c267fc16 | 1367 | if (ring_is_rsc_enabled(rx_ring)) |
aa80175a | 1368 | pkt_is_rsc = ixgbe_get_rsc_state(rx_desc); |
c267fc16 AD |
1369 | |
1370 | /* if this is a skb from previous receive DMA will be 0 */ | |
21fa4e66 | 1371 | if (rx_buffer_info->dma) { |
c267fc16 | 1372 | u16 hlen; |
aa80175a | 1373 | if (pkt_is_rsc && |
c267fc16 AD |
1374 | !(staterr & IXGBE_RXD_STAT_EOP) && |
1375 | !skb->prev) { | |
43634e82 MC |
1376 | /* |
1377 | * When HWRSC is enabled, delay unmapping | |
1378 | * of the first packet. It carries the | |
1379 | * header information, HW may still | |
1380 | * access the header after the writeback. | |
1381 | * Only unmap it when EOP is reached | |
1382 | */ | |
e8171aaa | 1383 | IXGBE_RSC_CB(skb)->delay_unmap = true; |
43634e82 | 1384 | IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma; |
e8171aaa | 1385 | } else { |
b6ec895e | 1386 | dma_unmap_single(rx_ring->dev, |
e8e9f696 JP |
1387 | rx_buffer_info->dma, |
1388 | rx_ring->rx_buf_len, | |
1389 | DMA_FROM_DEVICE); | |
e8171aaa | 1390 | } |
4f57ca6e | 1391 | rx_buffer_info->dma = 0; |
c267fc16 AD |
1392 | |
1393 | if (ring_is_ps_enabled(rx_ring)) { | |
1394 | hlen = ixgbe_get_hlen(rx_desc); | |
1395 | upper_len = le16_to_cpu(rx_desc->wb.upper.length); | |
1396 | } else { | |
1397 | hlen = le16_to_cpu(rx_desc->wb.upper.length); | |
1398 | } | |
1399 | ||
1400 | skb_put(skb, hlen); | |
1401 | } else { | |
1402 | /* assume packet split since header is unmapped */ | |
1403 | upper_len = le16_to_cpu(rx_desc->wb.upper.length); | |
9a799d71 AK |
1404 | } |
1405 | ||
1406 | if (upper_len) { | |
b6ec895e AD |
1407 | dma_unmap_page(rx_ring->dev, |
1408 | rx_buffer_info->page_dma, | |
1409 | PAGE_SIZE / 2, | |
1410 | DMA_FROM_DEVICE); | |
9a799d71 AK |
1411 | rx_buffer_info->page_dma = 0; |
1412 | skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, | |
e8e9f696 JP |
1413 | rx_buffer_info->page, |
1414 | rx_buffer_info->page_offset, | |
1415 | upper_len); | |
762f4c57 | 1416 | |
c267fc16 AD |
1417 | if ((page_count(rx_buffer_info->page) == 1) && |
1418 | (page_to_nid(rx_buffer_info->page) == current_node)) | |
762f4c57 | 1419 | get_page(rx_buffer_info->page); |
c267fc16 AD |
1420 | else |
1421 | rx_buffer_info->page = NULL; | |
9a799d71 AK |
1422 | |
1423 | skb->len += upper_len; | |
1424 | skb->data_len += upper_len; | |
1425 | skb->truesize += upper_len; | |
1426 | } | |
1427 | ||
1428 | i++; | |
1429 | if (i == rx_ring->count) | |
1430 | i = 0; | |
9a799d71 | 1431 | |
31f05a2d | 1432 | next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i); |
9a799d71 | 1433 | prefetch(next_rxd); |
9a799d71 | 1434 | cleaned_count++; |
f8212f97 | 1435 | |
aa80175a | 1436 | if (pkt_is_rsc) { |
f8212f97 AD |
1437 | u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >> |
1438 | IXGBE_RXDADV_NEXTP_SHIFT; | |
1439 | next_buffer = &rx_ring->rx_buffer_info[nextp]; | |
f8212f97 AD |
1440 | } else { |
1441 | next_buffer = &rx_ring->rx_buffer_info[i]; | |
1442 | } | |
1443 | ||
c267fc16 | 1444 | if (!(staterr & IXGBE_RXD_STAT_EOP)) { |
7d637bcc | 1445 | if (ring_is_ps_enabled(rx_ring)) { |
f8212f97 AD |
1446 | rx_buffer_info->skb = next_buffer->skb; |
1447 | rx_buffer_info->dma = next_buffer->dma; | |
1448 | next_buffer->skb = skb; | |
1449 | next_buffer->dma = 0; | |
1450 | } else { | |
1451 | skb->next = next_buffer->skb; | |
1452 | skb->next->prev = skb; | |
1453 | } | |
5b7da515 | 1454 | rx_ring->rx_stats.non_eop_descs++; |
9a799d71 AK |
1455 | goto next_desc; |
1456 | } | |
1457 | ||
aa80175a AD |
1458 | if (skb->prev) { |
1459 | skb = ixgbe_transform_rsc_queue(skb); | |
1460 | /* if we got here without RSC the packet is invalid */ | |
1461 | if (!pkt_is_rsc) { | |
1462 | __pskb_trim(skb, 0); | |
1463 | rx_buffer_info->skb = skb; | |
1464 | goto next_desc; | |
1465 | } | |
1466 | } | |
c267fc16 AD |
1467 | |
1468 | if (ring_is_rsc_enabled(rx_ring)) { | |
1469 | if (IXGBE_RSC_CB(skb)->delay_unmap) { | |
1470 | dma_unmap_single(rx_ring->dev, | |
1471 | IXGBE_RSC_CB(skb)->dma, | |
1472 | rx_ring->rx_buf_len, | |
1473 | DMA_FROM_DEVICE); | |
1474 | IXGBE_RSC_CB(skb)->dma = 0; | |
1475 | IXGBE_RSC_CB(skb)->delay_unmap = false; | |
1476 | } | |
aa80175a AD |
1477 | } |
1478 | if (pkt_is_rsc) { | |
c267fc16 AD |
1479 | if (ring_is_ps_enabled(rx_ring)) |
1480 | rx_ring->rx_stats.rsc_count += | |
aa80175a | 1481 | skb_shinfo(skb)->nr_frags; |
c267fc16 | 1482 | else |
aa80175a AD |
1483 | rx_ring->rx_stats.rsc_count += |
1484 | IXGBE_RSC_CB(skb)->skb_cnt; | |
c267fc16 AD |
1485 | rx_ring->rx_stats.rsc_flush++; |
1486 | } | |
1487 | ||
1488 | /* ERR_MASK will only have valid bits if EOP set */ | |
9a799d71 | 1489 | if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) { |
c267fc16 AD |
1490 | /* trim packet back to size 0 and recycle it */ |
1491 | __pskb_trim(skb, 0); | |
1492 | rx_buffer_info->skb = skb; | |
9a799d71 AK |
1493 | goto next_desc; |
1494 | } | |
1495 | ||
8bae1b2b | 1496 | ixgbe_rx_checksum(adapter, rx_desc, skb); |
67a74ee2 ET |
1497 | if (adapter->netdev->features & NETIF_F_RXHASH) |
1498 | ixgbe_rx_hash(rx_desc, skb); | |
d2f4fbe2 AV |
1499 | |
1500 | /* probably a little skewed due to removing CRC */ | |
1501 | total_rx_bytes += skb->len; | |
1502 | total_rx_packets++; | |
1503 | ||
fc77dc3c | 1504 | skb->protocol = eth_type_trans(skb, rx_ring->netdev); |
332d4a7d YZ |
1505 | #ifdef IXGBE_FCOE |
1506 | /* if ddp, not passing to ULD unless for FCP_RSP or error */ | |
3d8fd385 YZ |
1507 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { |
1508 | ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb); | |
1509 | if (!ddp_bytes) | |
332d4a7d | 1510 | goto next_desc; |
3d8fd385 | 1511 | } |
332d4a7d | 1512 | #endif /* IXGBE_FCOE */ |
fdaff1ce | 1513 | ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc); |
9a799d71 AK |
1514 | |
1515 | next_desc: | |
1516 | rx_desc->wb.upper.status_error = 0; | |
1517 | ||
c267fc16 AD |
1518 | (*work_done)++; |
1519 | if (*work_done >= work_to_do) | |
1520 | break; | |
1521 | ||
9a799d71 AK |
1522 | /* return some buffers to hardware, one at a time is too slow */ |
1523 | if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) { | |
fc77dc3c | 1524 | ixgbe_alloc_rx_buffers(rx_ring, cleaned_count); |
9a799d71 AK |
1525 | cleaned_count = 0; |
1526 | } | |
1527 | ||
1528 | /* use prefetched values */ | |
1529 | rx_desc = next_rxd; | |
9a799d71 | 1530 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); |
177db6ff MC |
1531 | } |
1532 | ||
9a799d71 AK |
1533 | rx_ring->next_to_clean = i; |
1534 | cleaned_count = IXGBE_DESC_UNUSED(rx_ring); | |
1535 | ||
1536 | if (cleaned_count) | |
fc77dc3c | 1537 | ixgbe_alloc_rx_buffers(rx_ring, cleaned_count); |
9a799d71 | 1538 | |
3d8fd385 YZ |
1539 | #ifdef IXGBE_FCOE |
1540 | /* include DDPed FCoE data */ | |
1541 | if (ddp_bytes > 0) { | |
1542 | unsigned int mss; | |
1543 | ||
fc77dc3c | 1544 | mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) - |
3d8fd385 YZ |
1545 | sizeof(struct fc_frame_header) - |
1546 | sizeof(struct fcoe_crc_eof); | |
1547 | if (mss > 512) | |
1548 | mss &= ~511; | |
1549 | total_rx_bytes += ddp_bytes; | |
1550 | total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss); | |
1551 | } | |
1552 | #endif /* IXGBE_FCOE */ | |
1553 | ||
f494e8fa AV |
1554 | rx_ring->total_packets += total_rx_packets; |
1555 | rx_ring->total_bytes += total_rx_bytes; | |
c267fc16 AD |
1556 | u64_stats_update_begin(&rx_ring->syncp); |
1557 | rx_ring->stats.packets += total_rx_packets; | |
1558 | rx_ring->stats.bytes += total_rx_bytes; | |
1559 | u64_stats_update_end(&rx_ring->syncp); | |
9a799d71 AK |
1560 | } |
1561 | ||
021230d4 | 1562 | static int ixgbe_clean_rxonly(struct napi_struct *, int); |
9a799d71 AK |
1563 | /** |
1564 | * ixgbe_configure_msix - Configure MSI-X hardware | |
1565 | * @adapter: board private structure | |
1566 | * | |
1567 | * ixgbe_configure_msix sets up the hardware to properly generate MSI-X | |
1568 | * interrupts. | |
1569 | **/ | |
1570 | static void ixgbe_configure_msix(struct ixgbe_adapter *adapter) | |
1571 | { | |
021230d4 | 1572 | struct ixgbe_q_vector *q_vector; |
bf29ee6c | 1573 | int i, q_vectors, v_idx, r_idx; |
021230d4 | 1574 | u32 mask; |
9a799d71 | 1575 | |
021230d4 | 1576 | q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; |
9a799d71 | 1577 | |
4df10466 JB |
1578 | /* |
1579 | * Populate the IVAR table and set the ITR values to the | |
021230d4 AV |
1580 | * corresponding register. |
1581 | */ | |
1582 | for (v_idx = 0; v_idx < q_vectors; v_idx++) { | |
7a921c93 | 1583 | q_vector = adapter->q_vector[v_idx]; |
984b3f57 | 1584 | /* XXX for_each_set_bit(...) */ |
021230d4 | 1585 | r_idx = find_first_bit(q_vector->rxr_idx, |
e8e9f696 | 1586 | adapter->num_rx_queues); |
021230d4 AV |
1587 | |
1588 | for (i = 0; i < q_vector->rxr_count; i++) { | |
bf29ee6c AD |
1589 | u8 reg_idx = adapter->rx_ring[r_idx]->reg_idx; |
1590 | ixgbe_set_ivar(adapter, 0, reg_idx, v_idx); | |
021230d4 | 1591 | r_idx = find_next_bit(q_vector->rxr_idx, |
e8e9f696 JP |
1592 | adapter->num_rx_queues, |
1593 | r_idx + 1); | |
021230d4 AV |
1594 | } |
1595 | r_idx = find_first_bit(q_vector->txr_idx, | |
e8e9f696 | 1596 | adapter->num_tx_queues); |
021230d4 AV |
1597 | |
1598 | for (i = 0; i < q_vector->txr_count; i++) { | |
bf29ee6c AD |
1599 | u8 reg_idx = adapter->tx_ring[r_idx]->reg_idx; |
1600 | ixgbe_set_ivar(adapter, 1, reg_idx, v_idx); | |
021230d4 | 1601 | r_idx = find_next_bit(q_vector->txr_idx, |
e8e9f696 JP |
1602 | adapter->num_tx_queues, |
1603 | r_idx + 1); | |
021230d4 AV |
1604 | } |
1605 | ||
021230d4 | 1606 | if (q_vector->txr_count && !q_vector->rxr_count) |
f7554a2b NS |
1607 | /* tx only */ |
1608 | q_vector->eitr = adapter->tx_eitr_param; | |
509ee935 | 1609 | else if (q_vector->rxr_count) |
f7554a2b NS |
1610 | /* rx or mixed */ |
1611 | q_vector->eitr = adapter->rx_eitr_param; | |
021230d4 | 1612 | |
fe49f04a | 1613 | ixgbe_write_eitr(q_vector); |
b25ebfd2 PW |
1614 | /* If Flow Director is enabled, set interrupt affinity */ |
1615 | if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) || | |
1616 | (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) { | |
1617 | /* | |
1618 | * Allocate the affinity_hint cpumask, assign the mask | |
1619 | * for this vector, and set our affinity_hint for | |
1620 | * this irq. | |
1621 | */ | |
1622 | if (!alloc_cpumask_var(&q_vector->affinity_mask, | |
1623 | GFP_KERNEL)) | |
1624 | return; | |
1625 | cpumask_set_cpu(v_idx, q_vector->affinity_mask); | |
1626 | irq_set_affinity_hint(adapter->msix_entries[v_idx].vector, | |
1627 | q_vector->affinity_mask); | |
1628 | } | |
9a799d71 AK |
1629 | } |
1630 | ||
bd508178 AD |
1631 | switch (adapter->hw.mac.type) { |
1632 | case ixgbe_mac_82598EB: | |
e8e26350 | 1633 | ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX, |
e8e9f696 | 1634 | v_idx); |
bd508178 AD |
1635 | break; |
1636 | case ixgbe_mac_82599EB: | |
b93a2226 | 1637 | case ixgbe_mac_X540: |
e8e26350 | 1638 | ixgbe_set_ivar(adapter, -1, 1, v_idx); |
bd508178 AD |
1639 | break; |
1640 | ||
1641 | default: | |
1642 | break; | |
1643 | } | |
021230d4 AV |
1644 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950); |
1645 | ||
41fb9248 | 1646 | /* set up to autoclear timer, and the vectors */ |
021230d4 | 1647 | mask = IXGBE_EIMS_ENABLE_MASK; |
1cdd1ec8 GR |
1648 | if (adapter->num_vfs) |
1649 | mask &= ~(IXGBE_EIMS_OTHER | | |
1650 | IXGBE_EIMS_MAILBOX | | |
1651 | IXGBE_EIMS_LSC); | |
1652 | else | |
1653 | mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC); | |
021230d4 | 1654 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask); |
9a799d71 AK |
1655 | } |
1656 | ||
f494e8fa AV |
1657 | enum latency_range { |
1658 | lowest_latency = 0, | |
1659 | low_latency = 1, | |
1660 | bulk_latency = 2, | |
1661 | latency_invalid = 255 | |
1662 | }; | |
1663 | ||
1664 | /** | |
1665 | * ixgbe_update_itr - update the dynamic ITR value based on statistics | |
1666 | * @adapter: pointer to adapter | |
1667 | * @eitr: eitr setting (ints per sec) to give last timeslice | |
1668 | * @itr_setting: current throttle rate in ints/second | |
1669 | * @packets: the number of packets during this measurement interval | |
1670 | * @bytes: the number of bytes during this measurement interval | |
1671 | * | |
1672 | * Stores a new ITR value based on packets and byte | |
1673 | * counts during the last interrupt. The advantage of per interrupt | |
1674 | * computation is faster updates and more accurate ITR for the current | |
1675 | * traffic pattern. Constants in this function were computed | |
1676 | * based on theoretical maximum wire speed and thresholds were set based | |
1677 | * on testing data as well as attempting to minimize response time | |
1678 | * while increasing bulk throughput. | |
1679 | * this functionality is controlled by the InterruptThrottleRate module | |
1680 | * parameter (see ixgbe_param.c) | |
1681 | **/ | |
1682 | static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter, | |
e8e9f696 JP |
1683 | u32 eitr, u8 itr_setting, |
1684 | int packets, int bytes) | |
f494e8fa AV |
1685 | { |
1686 | unsigned int retval = itr_setting; | |
1687 | u32 timepassed_us; | |
1688 | u64 bytes_perint; | |
1689 | ||
1690 | if (packets == 0) | |
1691 | goto update_itr_done; | |
1692 | ||
1693 | ||
1694 | /* simple throttlerate management | |
1695 | * 0-20MB/s lowest (100000 ints/s) | |
1696 | * 20-100MB/s low (20000 ints/s) | |
1697 | * 100-1249MB/s bulk (8000 ints/s) | |
1698 | */ | |
1699 | /* what was last interrupt timeslice? */ | |
1700 | timepassed_us = 1000000/eitr; | |
1701 | bytes_perint = bytes / timepassed_us; /* bytes/usec */ | |
1702 | ||
1703 | switch (itr_setting) { | |
1704 | case lowest_latency: | |
1705 | if (bytes_perint > adapter->eitr_low) | |
1706 | retval = low_latency; | |
1707 | break; | |
1708 | case low_latency: | |
1709 | if (bytes_perint > adapter->eitr_high) | |
1710 | retval = bulk_latency; | |
1711 | else if (bytes_perint <= adapter->eitr_low) | |
1712 | retval = lowest_latency; | |
1713 | break; | |
1714 | case bulk_latency: | |
1715 | if (bytes_perint <= adapter->eitr_high) | |
1716 | retval = low_latency; | |
1717 | break; | |
1718 | } | |
1719 | ||
1720 | update_itr_done: | |
1721 | return retval; | |
1722 | } | |
1723 | ||
509ee935 JB |
1724 | /** |
1725 | * ixgbe_write_eitr - write EITR register in hardware specific way | |
fe49f04a | 1726 | * @q_vector: structure containing interrupt and ring information |
509ee935 JB |
1727 | * |
1728 | * This function is made to be called by ethtool and by the driver | |
1729 | * when it needs to update EITR registers at runtime. Hardware | |
1730 | * specific quirks/differences are taken care of here. | |
1731 | */ | |
fe49f04a | 1732 | void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector) |
509ee935 | 1733 | { |
fe49f04a | 1734 | struct ixgbe_adapter *adapter = q_vector->adapter; |
509ee935 | 1735 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a AD |
1736 | int v_idx = q_vector->v_idx; |
1737 | u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr); | |
1738 | ||
bd508178 AD |
1739 | switch (adapter->hw.mac.type) { |
1740 | case ixgbe_mac_82598EB: | |
509ee935 JB |
1741 | /* must write high and low 16 bits to reset counter */ |
1742 | itr_reg |= (itr_reg << 16); | |
bd508178 AD |
1743 | break; |
1744 | case ixgbe_mac_82599EB: | |
b93a2226 | 1745 | case ixgbe_mac_X540: |
f8d1dcaf | 1746 | /* |
b93a2226 | 1747 | * 82599 and X540 can support a value of zero, so allow it for |
f8d1dcaf JB |
1748 | * max interrupt rate, but there is an errata where it can |
1749 | * not be zero with RSC | |
1750 | */ | |
1751 | if (itr_reg == 8 && | |
1752 | !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) | |
1753 | itr_reg = 0; | |
1754 | ||
509ee935 JB |
1755 | /* |
1756 | * set the WDIS bit to not clear the timer bits and cause an | |
1757 | * immediate assertion of the interrupt | |
1758 | */ | |
1759 | itr_reg |= IXGBE_EITR_CNT_WDIS; | |
bd508178 AD |
1760 | break; |
1761 | default: | |
1762 | break; | |
509ee935 JB |
1763 | } |
1764 | IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg); | |
1765 | } | |
1766 | ||
f494e8fa AV |
1767 | static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector) |
1768 | { | |
1769 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
125601bf | 1770 | int i, r_idx; |
f494e8fa AV |
1771 | u32 new_itr; |
1772 | u8 current_itr, ret_itr; | |
f494e8fa AV |
1773 | |
1774 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
1775 | for (i = 0; i < q_vector->txr_count; i++) { | |
125601bf | 1776 | struct ixgbe_ring *tx_ring = adapter->tx_ring[r_idx]; |
f494e8fa | 1777 | ret_itr = ixgbe_update_itr(adapter, q_vector->eitr, |
e8e9f696 JP |
1778 | q_vector->tx_itr, |
1779 | tx_ring->total_packets, | |
1780 | tx_ring->total_bytes); | |
f494e8fa AV |
1781 | /* if the result for this queue would decrease interrupt |
1782 | * rate for this vector then use that result */ | |
30efa5a3 | 1783 | q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ? |
e8e9f696 | 1784 | q_vector->tx_itr - 1 : ret_itr); |
f494e8fa | 1785 | r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, |
e8e9f696 | 1786 | r_idx + 1); |
f494e8fa AV |
1787 | } |
1788 | ||
1789 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
1790 | for (i = 0; i < q_vector->rxr_count; i++) { | |
125601bf | 1791 | struct ixgbe_ring *rx_ring = adapter->rx_ring[r_idx]; |
f494e8fa | 1792 | ret_itr = ixgbe_update_itr(adapter, q_vector->eitr, |
e8e9f696 JP |
1793 | q_vector->rx_itr, |
1794 | rx_ring->total_packets, | |
1795 | rx_ring->total_bytes); | |
f494e8fa AV |
1796 | /* if the result for this queue would decrease interrupt |
1797 | * rate for this vector then use that result */ | |
30efa5a3 | 1798 | q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ? |
e8e9f696 | 1799 | q_vector->rx_itr - 1 : ret_itr); |
f494e8fa | 1800 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, |
e8e9f696 | 1801 | r_idx + 1); |
f494e8fa AV |
1802 | } |
1803 | ||
30efa5a3 | 1804 | current_itr = max(q_vector->rx_itr, q_vector->tx_itr); |
f494e8fa AV |
1805 | |
1806 | switch (current_itr) { | |
1807 | /* counts and packets in update_itr are dependent on these numbers */ | |
1808 | case lowest_latency: | |
1809 | new_itr = 100000; | |
1810 | break; | |
1811 | case low_latency: | |
1812 | new_itr = 20000; /* aka hwitr = ~200 */ | |
1813 | break; | |
1814 | case bulk_latency: | |
1815 | default: | |
1816 | new_itr = 8000; | |
1817 | break; | |
1818 | } | |
1819 | ||
1820 | if (new_itr != q_vector->eitr) { | |
fe49f04a | 1821 | /* do an exponential smoothing */ |
125601bf | 1822 | new_itr = ((q_vector->eitr * 9) + new_itr)/10; |
509ee935 JB |
1823 | |
1824 | /* save the algorithm value here, not the smoothed one */ | |
1825 | q_vector->eitr = new_itr; | |
fe49f04a AD |
1826 | |
1827 | ixgbe_write_eitr(q_vector); | |
f494e8fa | 1828 | } |
f494e8fa AV |
1829 | } |
1830 | ||
119fc60a | 1831 | /** |
f0f9778d AD |
1832 | * ixgbe_check_overtemp_subtask - check for over tempurature |
1833 | * @adapter: pointer to adapter | |
119fc60a | 1834 | **/ |
f0f9778d | 1835 | static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter) |
119fc60a | 1836 | { |
119fc60a MC |
1837 | struct ixgbe_hw *hw = &adapter->hw; |
1838 | u32 eicr = adapter->interrupt_event; | |
1839 | ||
f0f9778d | 1840 | if (test_bit(__IXGBE_DOWN, &adapter->state)) |
7ca647bd JP |
1841 | return; |
1842 | ||
f0f9778d AD |
1843 | if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) && |
1844 | !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT)) | |
1845 | return; | |
1846 | ||
1847 | adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT; | |
1848 | ||
7ca647bd | 1849 | switch (hw->device_id) { |
f0f9778d AD |
1850 | case IXGBE_DEV_ID_82599_T3_LOM: |
1851 | /* | |
1852 | * Since the warning interrupt is for both ports | |
1853 | * we don't have to check if: | |
1854 | * - This interrupt wasn't for our port. | |
1855 | * - We may have missed the interrupt so always have to | |
1856 | * check if we got a LSC | |
1857 | */ | |
1858 | if (!(eicr & IXGBE_EICR_GPI_SDP0) && | |
1859 | !(eicr & IXGBE_EICR_LSC)) | |
1860 | return; | |
1861 | ||
1862 | if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) { | |
1863 | u32 autoneg; | |
1864 | bool link_up = false; | |
7ca647bd | 1865 | |
7ca647bd JP |
1866 | hw->mac.ops.check_link(hw, &autoneg, &link_up, false); |
1867 | ||
f0f9778d AD |
1868 | if (link_up) |
1869 | return; | |
1870 | } | |
1871 | ||
1872 | /* Check if this is not due to overtemp */ | |
1873 | if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP) | |
1874 | return; | |
1875 | ||
1876 | break; | |
7ca647bd JP |
1877 | default: |
1878 | if (!(eicr & IXGBE_EICR_GPI_SDP0)) | |
119fc60a | 1879 | return; |
7ca647bd | 1880 | break; |
119fc60a | 1881 | } |
7ca647bd JP |
1882 | e_crit(drv, |
1883 | "Network adapter has been stopped because it has over heated. " | |
1884 | "Restart the computer. If the problem persists, " | |
1885 | "power off the system and replace the adapter\n"); | |
f0f9778d AD |
1886 | |
1887 | adapter->interrupt_event = 0; | |
119fc60a MC |
1888 | } |
1889 | ||
0befdb3e JB |
1890 | static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr) |
1891 | { | |
1892 | struct ixgbe_hw *hw = &adapter->hw; | |
1893 | ||
1894 | if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) && | |
1895 | (eicr & IXGBE_EICR_GPI_SDP1)) { | |
396e799c | 1896 | e_crit(probe, "Fan has stopped, replace the adapter\n"); |
0befdb3e JB |
1897 | /* write to clear the interrupt */ |
1898 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); | |
1899 | } | |
1900 | } | |
cf8280ee | 1901 | |
e8e26350 PW |
1902 | static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr) |
1903 | { | |
1904 | struct ixgbe_hw *hw = &adapter->hw; | |
1905 | ||
73c4b7cd AD |
1906 | if (eicr & IXGBE_EICR_GPI_SDP2) { |
1907 | /* Clear the interrupt */ | |
1908 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2); | |
7086400d AD |
1909 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { |
1910 | adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; | |
1911 | ixgbe_service_event_schedule(adapter); | |
1912 | } | |
73c4b7cd AD |
1913 | } |
1914 | ||
e8e26350 PW |
1915 | if (eicr & IXGBE_EICR_GPI_SDP1) { |
1916 | /* Clear the interrupt */ | |
1917 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); | |
7086400d AD |
1918 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { |
1919 | adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; | |
1920 | ixgbe_service_event_schedule(adapter); | |
1921 | } | |
e8e26350 PW |
1922 | } |
1923 | } | |
1924 | ||
cf8280ee JB |
1925 | static void ixgbe_check_lsc(struct ixgbe_adapter *adapter) |
1926 | { | |
1927 | struct ixgbe_hw *hw = &adapter->hw; | |
1928 | ||
1929 | adapter->lsc_int++; | |
1930 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; | |
1931 | adapter->link_check_timeout = jiffies; | |
1932 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { | |
1933 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); | |
8a0717f3 | 1934 | IXGBE_WRITE_FLUSH(hw); |
93c52dd0 | 1935 | ixgbe_service_event_schedule(adapter); |
cf8280ee JB |
1936 | } |
1937 | } | |
1938 | ||
9a799d71 AK |
1939 | static irqreturn_t ixgbe_msix_lsc(int irq, void *data) |
1940 | { | |
1941 | struct net_device *netdev = data; | |
1942 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
1943 | struct ixgbe_hw *hw = &adapter->hw; | |
54037505 DS |
1944 | u32 eicr; |
1945 | ||
1946 | /* | |
1947 | * Workaround for Silicon errata. Use clear-by-write instead | |
1948 | * of clear-by-read. Reading with EICS will return the | |
1949 | * interrupt causes without clearing, which later be done | |
1950 | * with the write to EICR. | |
1951 | */ | |
1952 | eicr = IXGBE_READ_REG(hw, IXGBE_EICS); | |
1953 | IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); | |
9a799d71 | 1954 | |
cf8280ee JB |
1955 | if (eicr & IXGBE_EICR_LSC) |
1956 | ixgbe_check_lsc(adapter); | |
d4f80882 | 1957 | |
1cdd1ec8 GR |
1958 | if (eicr & IXGBE_EICR_MAILBOX) |
1959 | ixgbe_msg_task(adapter); | |
1960 | ||
bd508178 AD |
1961 | switch (hw->mac.type) { |
1962 | case ixgbe_mac_82599EB: | |
b93a2226 | 1963 | case ixgbe_mac_X540: |
c4cf55e5 PWJ |
1964 | /* Handle Flow Director Full threshold interrupt */ |
1965 | if (eicr & IXGBE_EICR_FLOW_DIR) { | |
d034acf1 | 1966 | int reinit_count = 0; |
c4cf55e5 | 1967 | int i; |
c4cf55e5 | 1968 | for (i = 0; i < adapter->num_tx_queues; i++) { |
d034acf1 | 1969 | struct ixgbe_ring *ring = adapter->tx_ring[i]; |
7d637bcc | 1970 | if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE, |
d034acf1 AD |
1971 | &ring->state)) |
1972 | reinit_count++; | |
1973 | } | |
1974 | if (reinit_count) { | |
1975 | /* no more flow director interrupts until after init */ | |
1976 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR); | |
1977 | eicr &= ~IXGBE_EICR_FLOW_DIR; | |
1978 | adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT; | |
1979 | ixgbe_service_event_schedule(adapter); | |
c4cf55e5 PWJ |
1980 | } |
1981 | } | |
f0f9778d AD |
1982 | ixgbe_check_sfp_event(adapter, eicr); |
1983 | if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) && | |
1984 | ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) { | |
1985 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { | |
1986 | adapter->interrupt_event = eicr; | |
1987 | adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; | |
1988 | ixgbe_service_event_schedule(adapter); | |
c4cf55e5 PWJ |
1989 | } |
1990 | } | |
bd508178 AD |
1991 | break; |
1992 | default: | |
1993 | break; | |
c4cf55e5 | 1994 | } |
bd508178 AD |
1995 | |
1996 | ixgbe_check_fan_failure(adapter, eicr); | |
1997 | ||
7086400d | 1998 | /* re-enable the original interrupt state, no lsc, no queues */ |
d4f80882 | 1999 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
7086400d AD |
2000 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, eicr & |
2001 | ~(IXGBE_EIMS_LSC | IXGBE_EIMS_RTX_QUEUE)); | |
9a799d71 AK |
2002 | |
2003 | return IRQ_HANDLED; | |
2004 | } | |
2005 | ||
fe49f04a AD |
2006 | static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter, |
2007 | u64 qmask) | |
2008 | { | |
2009 | u32 mask; | |
bd508178 | 2010 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a | 2011 | |
bd508178 AD |
2012 | switch (hw->mac.type) { |
2013 | case ixgbe_mac_82598EB: | |
fe49f04a | 2014 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); |
bd508178 AD |
2015 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask); |
2016 | break; | |
2017 | case ixgbe_mac_82599EB: | |
b93a2226 | 2018 | case ixgbe_mac_X540: |
fe49f04a | 2019 | mask = (qmask & 0xFFFFFFFF); |
bd508178 AD |
2020 | if (mask) |
2021 | IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); | |
fe49f04a | 2022 | mask = (qmask >> 32); |
bd508178 AD |
2023 | if (mask) |
2024 | IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); | |
2025 | break; | |
2026 | default: | |
2027 | break; | |
fe49f04a AD |
2028 | } |
2029 | /* skip the flush */ | |
2030 | } | |
2031 | ||
2032 | static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter, | |
e8e9f696 | 2033 | u64 qmask) |
fe49f04a AD |
2034 | { |
2035 | u32 mask; | |
bd508178 | 2036 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a | 2037 | |
bd508178 AD |
2038 | switch (hw->mac.type) { |
2039 | case ixgbe_mac_82598EB: | |
fe49f04a | 2040 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); |
bd508178 AD |
2041 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask); |
2042 | break; | |
2043 | case ixgbe_mac_82599EB: | |
b93a2226 | 2044 | case ixgbe_mac_X540: |
fe49f04a | 2045 | mask = (qmask & 0xFFFFFFFF); |
bd508178 AD |
2046 | if (mask) |
2047 | IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask); | |
fe49f04a | 2048 | mask = (qmask >> 32); |
bd508178 AD |
2049 | if (mask) |
2050 | IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask); | |
2051 | break; | |
2052 | default: | |
2053 | break; | |
fe49f04a AD |
2054 | } |
2055 | /* skip the flush */ | |
2056 | } | |
2057 | ||
9a799d71 AK |
2058 | static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data) |
2059 | { | |
021230d4 AV |
2060 | struct ixgbe_q_vector *q_vector = data; |
2061 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
3a581073 | 2062 | struct ixgbe_ring *tx_ring; |
021230d4 AV |
2063 | int i, r_idx; |
2064 | ||
2065 | if (!q_vector->txr_count) | |
2066 | return IRQ_HANDLED; | |
2067 | ||
2068 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
2069 | for (i = 0; i < q_vector->txr_count; i++) { | |
4a0b9ca0 | 2070 | tx_ring = adapter->tx_ring[r_idx]; |
3a581073 JB |
2071 | tx_ring->total_bytes = 0; |
2072 | tx_ring->total_packets = 0; | |
021230d4 | 2073 | r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, |
e8e9f696 | 2074 | r_idx + 1); |
021230d4 | 2075 | } |
9a799d71 | 2076 | |
9b471446 | 2077 | /* EIAM disabled interrupts (on this vector) for us */ |
91281fd3 AD |
2078 | napi_schedule(&q_vector->napi); |
2079 | ||
9a799d71 AK |
2080 | return IRQ_HANDLED; |
2081 | } | |
2082 | ||
021230d4 AV |
2083 | /** |
2084 | * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues) | |
2085 | * @irq: unused | |
2086 | * @data: pointer to our q_vector struct for this interrupt vector | |
2087 | **/ | |
9a799d71 AK |
2088 | static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data) |
2089 | { | |
021230d4 AV |
2090 | struct ixgbe_q_vector *q_vector = data; |
2091 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
3a581073 | 2092 | struct ixgbe_ring *rx_ring; |
021230d4 | 2093 | int r_idx; |
30efa5a3 | 2094 | int i; |
021230d4 | 2095 | |
33cf09c9 AD |
2096 | #ifdef CONFIG_IXGBE_DCA |
2097 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
2098 | ixgbe_update_dca(q_vector); | |
2099 | #endif | |
2100 | ||
021230d4 | 2101 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); |
33cf09c9 | 2102 | for (i = 0; i < q_vector->rxr_count; i++) { |
4a0b9ca0 | 2103 | rx_ring = adapter->rx_ring[r_idx]; |
30efa5a3 JB |
2104 | rx_ring->total_bytes = 0; |
2105 | rx_ring->total_packets = 0; | |
2106 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, | |
e8e9f696 | 2107 | r_idx + 1); |
30efa5a3 JB |
2108 | } |
2109 | ||
021230d4 AV |
2110 | if (!q_vector->rxr_count) |
2111 | return IRQ_HANDLED; | |
2112 | ||
9b471446 | 2113 | /* EIAM disabled interrupts (on this vector) for us */ |
288379f0 | 2114 | napi_schedule(&q_vector->napi); |
021230d4 AV |
2115 | |
2116 | return IRQ_HANDLED; | |
2117 | } | |
2118 | ||
2119 | static irqreturn_t ixgbe_msix_clean_many(int irq, void *data) | |
2120 | { | |
91281fd3 AD |
2121 | struct ixgbe_q_vector *q_vector = data; |
2122 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
2123 | struct ixgbe_ring *ring; | |
2124 | int r_idx; | |
2125 | int i; | |
2126 | ||
2127 | if (!q_vector->txr_count && !q_vector->rxr_count) | |
2128 | return IRQ_HANDLED; | |
2129 | ||
2130 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
2131 | for (i = 0; i < q_vector->txr_count; i++) { | |
4a0b9ca0 | 2132 | ring = adapter->tx_ring[r_idx]; |
91281fd3 AD |
2133 | ring->total_bytes = 0; |
2134 | ring->total_packets = 0; | |
2135 | r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, | |
e8e9f696 | 2136 | r_idx + 1); |
91281fd3 AD |
2137 | } |
2138 | ||
2139 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
2140 | for (i = 0; i < q_vector->rxr_count; i++) { | |
4a0b9ca0 | 2141 | ring = adapter->rx_ring[r_idx]; |
91281fd3 AD |
2142 | ring->total_bytes = 0; |
2143 | ring->total_packets = 0; | |
2144 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, | |
e8e9f696 | 2145 | r_idx + 1); |
91281fd3 AD |
2146 | } |
2147 | ||
9b471446 | 2148 | /* EIAM disabled interrupts (on this vector) for us */ |
91281fd3 | 2149 | napi_schedule(&q_vector->napi); |
9a799d71 | 2150 | |
9a799d71 AK |
2151 | return IRQ_HANDLED; |
2152 | } | |
2153 | ||
021230d4 AV |
2154 | /** |
2155 | * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine | |
2156 | * @napi: napi struct with our devices info in it | |
2157 | * @budget: amount of work driver is allowed to do this pass, in packets | |
2158 | * | |
f0848276 JB |
2159 | * This function is optimized for cleaning one queue only on a single |
2160 | * q_vector!!! | |
021230d4 | 2161 | **/ |
9a799d71 AK |
2162 | static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget) |
2163 | { | |
021230d4 | 2164 | struct ixgbe_q_vector *q_vector = |
e8e9f696 | 2165 | container_of(napi, struct ixgbe_q_vector, napi); |
021230d4 | 2166 | struct ixgbe_adapter *adapter = q_vector->adapter; |
f0848276 | 2167 | struct ixgbe_ring *rx_ring = NULL; |
9a799d71 | 2168 | int work_done = 0; |
021230d4 | 2169 | long r_idx; |
9a799d71 | 2170 | |
5dd2d332 | 2171 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 2172 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) |
33cf09c9 | 2173 | ixgbe_update_dca(q_vector); |
bd0362dd | 2174 | #endif |
9a799d71 | 2175 | |
33cf09c9 AD |
2176 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); |
2177 | rx_ring = adapter->rx_ring[r_idx]; | |
2178 | ||
78b6f4ce | 2179 | ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget); |
9a799d71 | 2180 | |
021230d4 AV |
2181 | /* If all Rx work done, exit the polling mode */ |
2182 | if (work_done < budget) { | |
288379f0 | 2183 | napi_complete(napi); |
f7554a2b | 2184 | if (adapter->rx_itr_setting & 1) |
f494e8fa | 2185 | ixgbe_set_itr_msix(q_vector); |
9a799d71 | 2186 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
fe49f04a | 2187 | ixgbe_irq_enable_queues(adapter, |
e8e9f696 | 2188 | ((u64)1 << q_vector->v_idx)); |
9a799d71 AK |
2189 | } |
2190 | ||
2191 | return work_done; | |
2192 | } | |
2193 | ||
f0848276 | 2194 | /** |
91281fd3 | 2195 | * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine |
f0848276 JB |
2196 | * @napi: napi struct with our devices info in it |
2197 | * @budget: amount of work driver is allowed to do this pass, in packets | |
2198 | * | |
2199 | * This function will clean more than one rx queue associated with a | |
2200 | * q_vector. | |
2201 | **/ | |
91281fd3 | 2202 | static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget) |
f0848276 JB |
2203 | { |
2204 | struct ixgbe_q_vector *q_vector = | |
e8e9f696 | 2205 | container_of(napi, struct ixgbe_q_vector, napi); |
f0848276 | 2206 | struct ixgbe_adapter *adapter = q_vector->adapter; |
91281fd3 | 2207 | struct ixgbe_ring *ring = NULL; |
f0848276 JB |
2208 | int work_done = 0, i; |
2209 | long r_idx; | |
91281fd3 AD |
2210 | bool tx_clean_complete = true; |
2211 | ||
33cf09c9 AD |
2212 | #ifdef CONFIG_IXGBE_DCA |
2213 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
2214 | ixgbe_update_dca(q_vector); | |
2215 | #endif | |
2216 | ||
91281fd3 AD |
2217 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); |
2218 | for (i = 0; i < q_vector->txr_count; i++) { | |
4a0b9ca0 | 2219 | ring = adapter->tx_ring[r_idx]; |
91281fd3 AD |
2220 | tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring); |
2221 | r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, | |
e8e9f696 | 2222 | r_idx + 1); |
91281fd3 | 2223 | } |
f0848276 JB |
2224 | |
2225 | /* attempt to distribute budget to each queue fairly, but don't allow | |
2226 | * the budget to go below 1 because we'll exit polling */ | |
2227 | budget /= (q_vector->rxr_count ?: 1); | |
2228 | budget = max(budget, 1); | |
2229 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
2230 | for (i = 0; i < q_vector->rxr_count; i++) { | |
4a0b9ca0 | 2231 | ring = adapter->rx_ring[r_idx]; |
91281fd3 | 2232 | ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget); |
f0848276 | 2233 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, |
e8e9f696 | 2234 | r_idx + 1); |
f0848276 JB |
2235 | } |
2236 | ||
2237 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
4a0b9ca0 | 2238 | ring = adapter->rx_ring[r_idx]; |
f0848276 | 2239 | /* If all Rx work done, exit the polling mode */ |
7f821875 | 2240 | if (work_done < budget) { |
288379f0 | 2241 | napi_complete(napi); |
f7554a2b | 2242 | if (adapter->rx_itr_setting & 1) |
f0848276 JB |
2243 | ixgbe_set_itr_msix(q_vector); |
2244 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
fe49f04a | 2245 | ixgbe_irq_enable_queues(adapter, |
e8e9f696 | 2246 | ((u64)1 << q_vector->v_idx)); |
f0848276 JB |
2247 | return 0; |
2248 | } | |
2249 | ||
2250 | return work_done; | |
2251 | } | |
91281fd3 AD |
2252 | |
2253 | /** | |
2254 | * ixgbe_clean_txonly - msix (aka one shot) tx clean routine | |
2255 | * @napi: napi struct with our devices info in it | |
2256 | * @budget: amount of work driver is allowed to do this pass, in packets | |
2257 | * | |
2258 | * This function is optimized for cleaning one queue only on a single | |
2259 | * q_vector!!! | |
2260 | **/ | |
2261 | static int ixgbe_clean_txonly(struct napi_struct *napi, int budget) | |
2262 | { | |
2263 | struct ixgbe_q_vector *q_vector = | |
e8e9f696 | 2264 | container_of(napi, struct ixgbe_q_vector, napi); |
91281fd3 AD |
2265 | struct ixgbe_adapter *adapter = q_vector->adapter; |
2266 | struct ixgbe_ring *tx_ring = NULL; | |
2267 | int work_done = 0; | |
2268 | long r_idx; | |
2269 | ||
91281fd3 AD |
2270 | #ifdef CONFIG_IXGBE_DCA |
2271 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
33cf09c9 | 2272 | ixgbe_update_dca(q_vector); |
91281fd3 AD |
2273 | #endif |
2274 | ||
33cf09c9 AD |
2275 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); |
2276 | tx_ring = adapter->tx_ring[r_idx]; | |
2277 | ||
91281fd3 AD |
2278 | if (!ixgbe_clean_tx_irq(q_vector, tx_ring)) |
2279 | work_done = budget; | |
2280 | ||
f7554a2b | 2281 | /* If all Tx work done, exit the polling mode */ |
91281fd3 AD |
2282 | if (work_done < budget) { |
2283 | napi_complete(napi); | |
f7554a2b | 2284 | if (adapter->tx_itr_setting & 1) |
91281fd3 AD |
2285 | ixgbe_set_itr_msix(q_vector); |
2286 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
e8e9f696 JP |
2287 | ixgbe_irq_enable_queues(adapter, |
2288 | ((u64)1 << q_vector->v_idx)); | |
91281fd3 AD |
2289 | } |
2290 | ||
2291 | return work_done; | |
2292 | } | |
2293 | ||
021230d4 | 2294 | static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx, |
e8e9f696 | 2295 | int r_idx) |
021230d4 | 2296 | { |
7a921c93 | 2297 | struct ixgbe_q_vector *q_vector = a->q_vector[v_idx]; |
2274543f | 2298 | struct ixgbe_ring *rx_ring = a->rx_ring[r_idx]; |
7a921c93 AD |
2299 | |
2300 | set_bit(r_idx, q_vector->rxr_idx); | |
2301 | q_vector->rxr_count++; | |
2274543f | 2302 | rx_ring->q_vector = q_vector; |
021230d4 AV |
2303 | } |
2304 | ||
2305 | static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx, | |
e8e9f696 | 2306 | int t_idx) |
021230d4 | 2307 | { |
7a921c93 | 2308 | struct ixgbe_q_vector *q_vector = a->q_vector[v_idx]; |
2274543f | 2309 | struct ixgbe_ring *tx_ring = a->tx_ring[t_idx]; |
7a921c93 AD |
2310 | |
2311 | set_bit(t_idx, q_vector->txr_idx); | |
2312 | q_vector->txr_count++; | |
2274543f | 2313 | tx_ring->q_vector = q_vector; |
021230d4 AV |
2314 | } |
2315 | ||
9a799d71 | 2316 | /** |
021230d4 AV |
2317 | * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors |
2318 | * @adapter: board private structure to initialize | |
9a799d71 | 2319 | * |
021230d4 AV |
2320 | * This function maps descriptor rings to the queue-specific vectors |
2321 | * we were allotted through the MSI-X enabling code. Ideally, we'd have | |
2322 | * one vector per ring/queue, but on a constrained vector budget, we | |
2323 | * group the rings as "efficiently" as possible. You would add new | |
2324 | * mapping configurations in here. | |
9a799d71 | 2325 | **/ |
d0759ebb | 2326 | static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter) |
021230d4 | 2327 | { |
d0759ebb | 2328 | int q_vectors; |
021230d4 AV |
2329 | int v_start = 0; |
2330 | int rxr_idx = 0, txr_idx = 0; | |
2331 | int rxr_remaining = adapter->num_rx_queues; | |
2332 | int txr_remaining = adapter->num_tx_queues; | |
2333 | int i, j; | |
2334 | int rqpv, tqpv; | |
2335 | int err = 0; | |
2336 | ||
2337 | /* No mapping required if MSI-X is disabled. */ | |
2338 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
2339 | goto out; | |
9a799d71 | 2340 | |
d0759ebb AD |
2341 | q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; |
2342 | ||
021230d4 AV |
2343 | /* |
2344 | * The ideal configuration... | |
2345 | * We have enough vectors to map one per queue. | |
2346 | */ | |
d0759ebb | 2347 | if (q_vectors == adapter->num_rx_queues + adapter->num_tx_queues) { |
021230d4 AV |
2348 | for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++) |
2349 | map_vector_to_rxq(adapter, v_start, rxr_idx); | |
9a799d71 | 2350 | |
021230d4 AV |
2351 | for (; txr_idx < txr_remaining; v_start++, txr_idx++) |
2352 | map_vector_to_txq(adapter, v_start, txr_idx); | |
9a799d71 | 2353 | |
9a799d71 | 2354 | goto out; |
021230d4 | 2355 | } |
9a799d71 | 2356 | |
021230d4 AV |
2357 | /* |
2358 | * If we don't have enough vectors for a 1-to-1 | |
2359 | * mapping, we'll have to group them so there are | |
2360 | * multiple queues per vector. | |
2361 | */ | |
2362 | /* Re-adjusting *qpv takes care of the remainder. */ | |
d0759ebb AD |
2363 | for (i = v_start; i < q_vectors; i++) { |
2364 | rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - i); | |
021230d4 AV |
2365 | for (j = 0; j < rqpv; j++) { |
2366 | map_vector_to_rxq(adapter, i, rxr_idx); | |
2367 | rxr_idx++; | |
2368 | rxr_remaining--; | |
2369 | } | |
d0759ebb | 2370 | tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - i); |
021230d4 AV |
2371 | for (j = 0; j < tqpv; j++) { |
2372 | map_vector_to_txq(adapter, i, txr_idx); | |
2373 | txr_idx++; | |
2374 | txr_remaining--; | |
9a799d71 | 2375 | } |
9a799d71 | 2376 | } |
021230d4 AV |
2377 | out: |
2378 | return err; | |
2379 | } | |
2380 | ||
2381 | /** | |
2382 | * ixgbe_request_msix_irqs - Initialize MSI-X interrupts | |
2383 | * @adapter: board private structure | |
2384 | * | |
2385 | * ixgbe_request_msix_irqs allocates MSI-X vectors and requests | |
2386 | * interrupts from the kernel. | |
2387 | **/ | |
2388 | static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter) | |
2389 | { | |
2390 | struct net_device *netdev = adapter->netdev; | |
2391 | irqreturn_t (*handler)(int, void *); | |
2392 | int i, vector, q_vectors, err; | |
e8e9f696 | 2393 | int ri = 0, ti = 0; |
021230d4 AV |
2394 | |
2395 | /* Decrement for Other and TCP Timer vectors */ | |
2396 | q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
2397 | ||
d0759ebb | 2398 | err = ixgbe_map_rings_to_vectors(adapter); |
021230d4 | 2399 | if (err) |
d0759ebb | 2400 | return err; |
021230d4 | 2401 | |
d0759ebb AD |
2402 | #define SET_HANDLER(_v) (((_v)->rxr_count && (_v)->txr_count) \ |
2403 | ? &ixgbe_msix_clean_many : \ | |
2404 | (_v)->rxr_count ? &ixgbe_msix_clean_rx : \ | |
2405 | (_v)->txr_count ? &ixgbe_msix_clean_tx : \ | |
2406 | NULL) | |
021230d4 | 2407 | for (vector = 0; vector < q_vectors; vector++) { |
d0759ebb AD |
2408 | struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; |
2409 | handler = SET_HANDLER(q_vector); | |
cb13fc20 | 2410 | |
e8e9f696 | 2411 | if (handler == &ixgbe_msix_clean_rx) { |
9fe93afd DS |
2412 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, |
2413 | "%s-%s-%d", netdev->name, "rx", ri++); | |
e8e9f696 | 2414 | } else if (handler == &ixgbe_msix_clean_tx) { |
9fe93afd DS |
2415 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, |
2416 | "%s-%s-%d", netdev->name, "tx", ti++); | |
d0759ebb | 2417 | } else if (handler == &ixgbe_msix_clean_many) { |
9fe93afd DS |
2418 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, |
2419 | "%s-%s-%d", netdev->name, "TxRx", ri++); | |
32aa77a4 | 2420 | ti++; |
d0759ebb AD |
2421 | } else { |
2422 | /* skip this unused q_vector */ | |
2423 | continue; | |
32aa77a4 | 2424 | } |
021230d4 | 2425 | err = request_irq(adapter->msix_entries[vector].vector, |
d0759ebb AD |
2426 | handler, 0, q_vector->name, |
2427 | q_vector); | |
9a799d71 | 2428 | if (err) { |
396e799c | 2429 | e_err(probe, "request_irq failed for MSIX interrupt " |
849c4542 | 2430 | "Error: %d\n", err); |
021230d4 | 2431 | goto free_queue_irqs; |
9a799d71 | 2432 | } |
9a799d71 AK |
2433 | } |
2434 | ||
d0759ebb | 2435 | sprintf(adapter->lsc_int_name, "%s:lsc", netdev->name); |
021230d4 | 2436 | err = request_irq(adapter->msix_entries[vector].vector, |
d0759ebb | 2437 | ixgbe_msix_lsc, 0, adapter->lsc_int_name, netdev); |
9a799d71 | 2438 | if (err) { |
396e799c | 2439 | e_err(probe, "request_irq for msix_lsc failed: %d\n", err); |
021230d4 | 2440 | goto free_queue_irqs; |
9a799d71 AK |
2441 | } |
2442 | ||
9a799d71 AK |
2443 | return 0; |
2444 | ||
021230d4 AV |
2445 | free_queue_irqs: |
2446 | for (i = vector - 1; i >= 0; i--) | |
2447 | free_irq(adapter->msix_entries[--vector].vector, | |
e8e9f696 | 2448 | adapter->q_vector[i]); |
021230d4 AV |
2449 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; |
2450 | pci_disable_msix(adapter->pdev); | |
9a799d71 AK |
2451 | kfree(adapter->msix_entries); |
2452 | adapter->msix_entries = NULL; | |
9a799d71 AK |
2453 | return err; |
2454 | } | |
2455 | ||
f494e8fa AV |
2456 | static void ixgbe_set_itr(struct ixgbe_adapter *adapter) |
2457 | { | |
7a921c93 | 2458 | struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; |
4a0b9ca0 PW |
2459 | struct ixgbe_ring *rx_ring = adapter->rx_ring[0]; |
2460 | struct ixgbe_ring *tx_ring = adapter->tx_ring[0]; | |
125601bf AD |
2461 | u32 new_itr = q_vector->eitr; |
2462 | u8 current_itr; | |
f494e8fa | 2463 | |
30efa5a3 | 2464 | q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr, |
e8e9f696 JP |
2465 | q_vector->tx_itr, |
2466 | tx_ring->total_packets, | |
2467 | tx_ring->total_bytes); | |
30efa5a3 | 2468 | q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr, |
e8e9f696 JP |
2469 | q_vector->rx_itr, |
2470 | rx_ring->total_packets, | |
2471 | rx_ring->total_bytes); | |
f494e8fa | 2472 | |
30efa5a3 | 2473 | current_itr = max(q_vector->rx_itr, q_vector->tx_itr); |
f494e8fa AV |
2474 | |
2475 | switch (current_itr) { | |
2476 | /* counts and packets in update_itr are dependent on these numbers */ | |
2477 | case lowest_latency: | |
2478 | new_itr = 100000; | |
2479 | break; | |
2480 | case low_latency: | |
2481 | new_itr = 20000; /* aka hwitr = ~200 */ | |
2482 | break; | |
2483 | case bulk_latency: | |
2484 | new_itr = 8000; | |
2485 | break; | |
2486 | default: | |
2487 | break; | |
2488 | } | |
2489 | ||
2490 | if (new_itr != q_vector->eitr) { | |
fe49f04a | 2491 | /* do an exponential smoothing */ |
125601bf | 2492 | new_itr = ((q_vector->eitr * 9) + new_itr)/10; |
509ee935 | 2493 | |
125601bf | 2494 | /* save the algorithm value here */ |
509ee935 | 2495 | q_vector->eitr = new_itr; |
fe49f04a AD |
2496 | |
2497 | ixgbe_write_eitr(q_vector); | |
f494e8fa | 2498 | } |
f494e8fa AV |
2499 | } |
2500 | ||
79aefa45 AD |
2501 | /** |
2502 | * ixgbe_irq_enable - Enable default interrupt generation settings | |
2503 | * @adapter: board private structure | |
2504 | **/ | |
6af3b9eb ET |
2505 | static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues, |
2506 | bool flush) | |
79aefa45 AD |
2507 | { |
2508 | u32 mask; | |
835462fc NS |
2509 | |
2510 | mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE); | |
119fc60a MC |
2511 | if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) |
2512 | mask |= IXGBE_EIMS_GPI_SDP0; | |
6ab33d51 DM |
2513 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) |
2514 | mask |= IXGBE_EIMS_GPI_SDP1; | |
bd508178 AD |
2515 | switch (adapter->hw.mac.type) { |
2516 | case ixgbe_mac_82599EB: | |
b93a2226 | 2517 | case ixgbe_mac_X540: |
2a41ff81 | 2518 | mask |= IXGBE_EIMS_ECC; |
e8e26350 PW |
2519 | mask |= IXGBE_EIMS_GPI_SDP1; |
2520 | mask |= IXGBE_EIMS_GPI_SDP2; | |
1cdd1ec8 GR |
2521 | if (adapter->num_vfs) |
2522 | mask |= IXGBE_EIMS_MAILBOX; | |
bd508178 AD |
2523 | break; |
2524 | default: | |
2525 | break; | |
e8e26350 | 2526 | } |
c4cf55e5 PWJ |
2527 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || |
2528 | adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) | |
2529 | mask |= IXGBE_EIMS_FLOW_DIR; | |
e8e26350 | 2530 | |
79aefa45 | 2531 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); |
6af3b9eb ET |
2532 | if (queues) |
2533 | ixgbe_irq_enable_queues(adapter, ~0); | |
2534 | if (flush) | |
2535 | IXGBE_WRITE_FLUSH(&adapter->hw); | |
1cdd1ec8 GR |
2536 | |
2537 | if (adapter->num_vfs > 32) { | |
2538 | u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1; | |
2539 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel); | |
2540 | } | |
79aefa45 | 2541 | } |
021230d4 | 2542 | |
9a799d71 | 2543 | /** |
021230d4 | 2544 | * ixgbe_intr - legacy mode Interrupt Handler |
9a799d71 AK |
2545 | * @irq: interrupt number |
2546 | * @data: pointer to a network interface device structure | |
9a799d71 AK |
2547 | **/ |
2548 | static irqreturn_t ixgbe_intr(int irq, void *data) | |
2549 | { | |
2550 | struct net_device *netdev = data; | |
2551 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
2552 | struct ixgbe_hw *hw = &adapter->hw; | |
7a921c93 | 2553 | struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; |
9a799d71 AK |
2554 | u32 eicr; |
2555 | ||
54037505 | 2556 | /* |
6af3b9eb | 2557 | * Workaround for silicon errata on 82598. Mask the interrupts |
54037505 DS |
2558 | * before the read of EICR. |
2559 | */ | |
2560 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); | |
2561 | ||
021230d4 AV |
2562 | /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read |
2563 | * therefore no explict interrupt disable is necessary */ | |
2564 | eicr = IXGBE_READ_REG(hw, IXGBE_EICR); | |
f47cf66e | 2565 | if (!eicr) { |
6af3b9eb ET |
2566 | /* |
2567 | * shared interrupt alert! | |
f47cf66e | 2568 | * make sure interrupts are enabled because the read will |
6af3b9eb ET |
2569 | * have disabled interrupts due to EIAM |
2570 | * finish the workaround of silicon errata on 82598. Unmask | |
2571 | * the interrupt that we masked before the EICR read. | |
2572 | */ | |
2573 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
2574 | ixgbe_irq_enable(adapter, true, true); | |
9a799d71 | 2575 | return IRQ_NONE; /* Not our interrupt */ |
f47cf66e | 2576 | } |
9a799d71 | 2577 | |
cf8280ee JB |
2578 | if (eicr & IXGBE_EICR_LSC) |
2579 | ixgbe_check_lsc(adapter); | |
021230d4 | 2580 | |
bd508178 AD |
2581 | switch (hw->mac.type) { |
2582 | case ixgbe_mac_82599EB: | |
e8e26350 | 2583 | ixgbe_check_sfp_event(adapter, eicr); |
bd508178 AD |
2584 | if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) && |
2585 | ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) { | |
f0f9778d AD |
2586 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { |
2587 | adapter->interrupt_event = eicr; | |
2588 | adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; | |
2589 | ixgbe_service_event_schedule(adapter); | |
2590 | } | |
bd508178 AD |
2591 | } |
2592 | break; | |
2593 | default: | |
2594 | break; | |
2595 | } | |
e8e26350 | 2596 | |
0befdb3e JB |
2597 | ixgbe_check_fan_failure(adapter, eicr); |
2598 | ||
7a921c93 | 2599 | if (napi_schedule_prep(&(q_vector->napi))) { |
4a0b9ca0 PW |
2600 | adapter->tx_ring[0]->total_packets = 0; |
2601 | adapter->tx_ring[0]->total_bytes = 0; | |
2602 | adapter->rx_ring[0]->total_packets = 0; | |
2603 | adapter->rx_ring[0]->total_bytes = 0; | |
021230d4 | 2604 | /* would disable interrupts here but EIAM disabled it */ |
7a921c93 | 2605 | __napi_schedule(&(q_vector->napi)); |
9a799d71 AK |
2606 | } |
2607 | ||
6af3b9eb ET |
2608 | /* |
2609 | * re-enable link(maybe) and non-queue interrupts, no flush. | |
2610 | * ixgbe_poll will re-enable the queue interrupts | |
2611 | */ | |
2612 | ||
2613 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
2614 | ixgbe_irq_enable(adapter, false, false); | |
2615 | ||
9a799d71 AK |
2616 | return IRQ_HANDLED; |
2617 | } | |
2618 | ||
021230d4 AV |
2619 | static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter) |
2620 | { | |
2621 | int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
2622 | ||
2623 | for (i = 0; i < q_vectors; i++) { | |
7a921c93 | 2624 | struct ixgbe_q_vector *q_vector = adapter->q_vector[i]; |
021230d4 AV |
2625 | bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES); |
2626 | bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES); | |
2627 | q_vector->rxr_count = 0; | |
2628 | q_vector->txr_count = 0; | |
2629 | } | |
2630 | } | |
2631 | ||
9a799d71 AK |
2632 | /** |
2633 | * ixgbe_request_irq - initialize interrupts | |
2634 | * @adapter: board private structure | |
2635 | * | |
2636 | * Attempts to configure interrupts using the best available | |
2637 | * capabilities of the hardware and kernel. | |
2638 | **/ | |
021230d4 | 2639 | static int ixgbe_request_irq(struct ixgbe_adapter *adapter) |
9a799d71 AK |
2640 | { |
2641 | struct net_device *netdev = adapter->netdev; | |
021230d4 | 2642 | int err; |
9a799d71 | 2643 | |
021230d4 AV |
2644 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
2645 | err = ixgbe_request_msix_irqs(adapter); | |
2646 | } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) { | |
a0607fd3 | 2647 | err = request_irq(adapter->pdev->irq, ixgbe_intr, 0, |
e8e9f696 | 2648 | netdev->name, netdev); |
021230d4 | 2649 | } else { |
a0607fd3 | 2650 | err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED, |
e8e9f696 | 2651 | netdev->name, netdev); |
9a799d71 AK |
2652 | } |
2653 | ||
9a799d71 | 2654 | if (err) |
396e799c | 2655 | e_err(probe, "request_irq failed, Error %d\n", err); |
9a799d71 | 2656 | |
9a799d71 AK |
2657 | return err; |
2658 | } | |
2659 | ||
2660 | static void ixgbe_free_irq(struct ixgbe_adapter *adapter) | |
2661 | { | |
2662 | struct net_device *netdev = adapter->netdev; | |
2663 | ||
2664 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
021230d4 | 2665 | int i, q_vectors; |
9a799d71 | 2666 | |
021230d4 AV |
2667 | q_vectors = adapter->num_msix_vectors; |
2668 | ||
2669 | i = q_vectors - 1; | |
9a799d71 | 2670 | free_irq(adapter->msix_entries[i].vector, netdev); |
9a799d71 | 2671 | |
021230d4 AV |
2672 | i--; |
2673 | for (; i >= 0; i--) { | |
894ff7cf AD |
2674 | /* free only the irqs that were actually requested */ |
2675 | if (!adapter->q_vector[i]->rxr_count && | |
2676 | !adapter->q_vector[i]->txr_count) | |
2677 | continue; | |
2678 | ||
021230d4 | 2679 | free_irq(adapter->msix_entries[i].vector, |
e8e9f696 | 2680 | adapter->q_vector[i]); |
021230d4 AV |
2681 | } |
2682 | ||
2683 | ixgbe_reset_q_vectors(adapter); | |
2684 | } else { | |
2685 | free_irq(adapter->pdev->irq, netdev); | |
9a799d71 AK |
2686 | } |
2687 | } | |
2688 | ||
22d5a71b JB |
2689 | /** |
2690 | * ixgbe_irq_disable - Mask off interrupt generation on the NIC | |
2691 | * @adapter: board private structure | |
2692 | **/ | |
2693 | static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) | |
2694 | { | |
bd508178 AD |
2695 | switch (adapter->hw.mac.type) { |
2696 | case ixgbe_mac_82598EB: | |
835462fc | 2697 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); |
bd508178 AD |
2698 | break; |
2699 | case ixgbe_mac_82599EB: | |
b93a2226 | 2700 | case ixgbe_mac_X540: |
835462fc NS |
2701 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000); |
2702 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0); | |
22d5a71b | 2703 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0); |
1cdd1ec8 GR |
2704 | if (adapter->num_vfs > 32) |
2705 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0); | |
bd508178 AD |
2706 | break; |
2707 | default: | |
2708 | break; | |
22d5a71b JB |
2709 | } |
2710 | IXGBE_WRITE_FLUSH(&adapter->hw); | |
2711 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
2712 | int i; | |
2713 | for (i = 0; i < adapter->num_msix_vectors; i++) | |
2714 | synchronize_irq(adapter->msix_entries[i].vector); | |
2715 | } else { | |
2716 | synchronize_irq(adapter->pdev->irq); | |
2717 | } | |
2718 | } | |
2719 | ||
9a799d71 AK |
2720 | /** |
2721 | * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts | |
2722 | * | |
2723 | **/ | |
2724 | static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter) | |
2725 | { | |
9a799d71 AK |
2726 | struct ixgbe_hw *hw = &adapter->hw; |
2727 | ||
021230d4 | 2728 | IXGBE_WRITE_REG(hw, IXGBE_EITR(0), |
e8e9f696 | 2729 | EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param)); |
9a799d71 | 2730 | |
e8e26350 PW |
2731 | ixgbe_set_ivar(adapter, 0, 0, 0); |
2732 | ixgbe_set_ivar(adapter, 1, 0, 0); | |
021230d4 AV |
2733 | |
2734 | map_vector_to_rxq(adapter, 0, 0); | |
2735 | map_vector_to_txq(adapter, 0, 0); | |
2736 | ||
396e799c | 2737 | e_info(hw, "Legacy interrupt IVAR setup done\n"); |
9a799d71 AK |
2738 | } |
2739 | ||
43e69bf0 AD |
2740 | /** |
2741 | * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset | |
2742 | * @adapter: board private structure | |
2743 | * @ring: structure containing ring specific data | |
2744 | * | |
2745 | * Configure the Tx descriptor ring after a reset. | |
2746 | **/ | |
84418e3b AD |
2747 | void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter, |
2748 | struct ixgbe_ring *ring) | |
43e69bf0 AD |
2749 | { |
2750 | struct ixgbe_hw *hw = &adapter->hw; | |
2751 | u64 tdba = ring->dma; | |
2f1860b8 AD |
2752 | int wait_loop = 10; |
2753 | u32 txdctl; | |
bf29ee6c | 2754 | u8 reg_idx = ring->reg_idx; |
43e69bf0 | 2755 | |
2f1860b8 AD |
2756 | /* disable queue to avoid issues while updating state */ |
2757 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); | |
2758 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), | |
2759 | txdctl & ~IXGBE_TXDCTL_ENABLE); | |
2760 | IXGBE_WRITE_FLUSH(hw); | |
2761 | ||
43e69bf0 | 2762 | IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx), |
e8e9f696 | 2763 | (tdba & DMA_BIT_MASK(32))); |
43e69bf0 AD |
2764 | IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32)); |
2765 | IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx), | |
2766 | ring->count * sizeof(union ixgbe_adv_tx_desc)); | |
2767 | IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0); | |
2768 | IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0); | |
84ea2591 | 2769 | ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx); |
43e69bf0 | 2770 | |
2f1860b8 AD |
2771 | /* configure fetching thresholds */ |
2772 | if (adapter->rx_itr_setting == 0) { | |
2773 | /* cannot set wthresh when itr==0 */ | |
2774 | txdctl &= ~0x007F0000; | |
2775 | } else { | |
2776 | /* enable WTHRESH=8 descriptors, to encourage burst writeback */ | |
2777 | txdctl |= (8 << 16); | |
2778 | } | |
2779 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
2780 | /* PThresh workaround for Tx hang with DFP enabled. */ | |
2781 | txdctl |= 32; | |
2782 | } | |
2783 | ||
2784 | /* reinitialize flowdirector state */ | |
ee9e0f0b AD |
2785 | if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) && |
2786 | adapter->atr_sample_rate) { | |
2787 | ring->atr_sample_rate = adapter->atr_sample_rate; | |
2788 | ring->atr_count = 0; | |
2789 | set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state); | |
2790 | } else { | |
2791 | ring->atr_sample_rate = 0; | |
2792 | } | |
2f1860b8 | 2793 | |
c84d324c JF |
2794 | clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state); |
2795 | ||
2f1860b8 AD |
2796 | /* enable queue */ |
2797 | txdctl |= IXGBE_TXDCTL_ENABLE; | |
2798 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl); | |
2799 | ||
2800 | /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */ | |
2801 | if (hw->mac.type == ixgbe_mac_82598EB && | |
2802 | !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) | |
2803 | return; | |
2804 | ||
2805 | /* poll to verify queue is enabled */ | |
2806 | do { | |
032b4325 | 2807 | usleep_range(1000, 2000); |
2f1860b8 AD |
2808 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); |
2809 | } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE)); | |
2810 | if (!wait_loop) | |
2811 | e_err(drv, "Could not enable Tx Queue %d\n", reg_idx); | |
43e69bf0 AD |
2812 | } |
2813 | ||
120ff942 AD |
2814 | static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter) |
2815 | { | |
2816 | struct ixgbe_hw *hw = &adapter->hw; | |
2817 | u32 rttdcs; | |
2818 | u32 mask; | |
72a32f1f | 2819 | u32 reg; |
120ff942 AD |
2820 | |
2821 | if (hw->mac.type == ixgbe_mac_82598EB) | |
2822 | return; | |
2823 | ||
2824 | /* disable the arbiter while setting MTQC */ | |
2825 | rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS); | |
2826 | rttdcs |= IXGBE_RTTDCS_ARBDIS; | |
2827 | IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); | |
2828 | ||
2829 | /* set transmit pool layout */ | |
2830 | mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED); | |
2831 | switch (adapter->flags & mask) { | |
2832 | ||
2833 | case (IXGBE_FLAG_SRIOV_ENABLED): | |
2834 | IXGBE_WRITE_REG(hw, IXGBE_MTQC, | |
2835 | (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF)); | |
2836 | break; | |
2837 | ||
2838 | case (IXGBE_FLAG_DCB_ENABLED): | |
2839 | /* We enable 8 traffic classes, DCB only */ | |
2840 | IXGBE_WRITE_REG(hw, IXGBE_MTQC, | |
2841 | (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ)); | |
72a32f1f JF |
2842 | |
2843 | /* Enable Security TX Buffer IFG for DCB */ | |
2844 | reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); | |
2845 | reg |= IXGBE_SECTX_DCB; | |
2846 | IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg); | |
2847 | ||
120ff942 AD |
2848 | break; |
2849 | ||
2850 | default: | |
2851 | IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB); | |
2852 | break; | |
2853 | } | |
2854 | ||
2855 | /* re-enable the arbiter */ | |
2856 | rttdcs &= ~IXGBE_RTTDCS_ARBDIS; | |
2857 | IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); | |
2858 | } | |
2859 | ||
9a799d71 | 2860 | /** |
3a581073 | 2861 | * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset |
9a799d71 AK |
2862 | * @adapter: board private structure |
2863 | * | |
2864 | * Configure the Tx unit of the MAC after a reset. | |
2865 | **/ | |
2866 | static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) | |
2867 | { | |
2f1860b8 AD |
2868 | struct ixgbe_hw *hw = &adapter->hw; |
2869 | u32 dmatxctl; | |
43e69bf0 | 2870 | u32 i; |
9a799d71 | 2871 | |
2f1860b8 AD |
2872 | ixgbe_setup_mtqc(adapter); |
2873 | ||
2874 | if (hw->mac.type != ixgbe_mac_82598EB) { | |
2875 | /* DMATXCTL.EN must be before Tx queues are enabled */ | |
2876 | dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); | |
2877 | dmatxctl |= IXGBE_DMATXCTL_TE; | |
2878 | IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl); | |
2879 | } | |
2880 | ||
9a799d71 | 2881 | /* Setup the HW Tx Head and Tail descriptor pointers */ |
43e69bf0 AD |
2882 | for (i = 0; i < adapter->num_tx_queues; i++) |
2883 | ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]); | |
9a799d71 AK |
2884 | } |
2885 | ||
e8e26350 | 2886 | #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 |
cc41ac7c | 2887 | |
a6616b42 | 2888 | static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, |
e8e9f696 | 2889 | struct ixgbe_ring *rx_ring) |
cc41ac7c | 2890 | { |
cc41ac7c | 2891 | u32 srrctl; |
bf29ee6c | 2892 | u8 reg_idx = rx_ring->reg_idx; |
3be1adfb | 2893 | |
bd508178 AD |
2894 | switch (adapter->hw.mac.type) { |
2895 | case ixgbe_mac_82598EB: { | |
2896 | struct ixgbe_ring_feature *feature = adapter->ring_feature; | |
2897 | const int mask = feature[RING_F_RSS].mask; | |
bf29ee6c | 2898 | reg_idx = reg_idx & mask; |
cc41ac7c | 2899 | } |
bd508178 AD |
2900 | break; |
2901 | case ixgbe_mac_82599EB: | |
b93a2226 | 2902 | case ixgbe_mac_X540: |
bd508178 AD |
2903 | default: |
2904 | break; | |
2905 | } | |
2906 | ||
bf29ee6c | 2907 | srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx)); |
cc41ac7c JB |
2908 | |
2909 | srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK; | |
2910 | srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK; | |
9e10e045 AD |
2911 | if (adapter->num_vfs) |
2912 | srrctl |= IXGBE_SRRCTL_DROP_EN; | |
cc41ac7c | 2913 | |
afafd5b0 AD |
2914 | srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) & |
2915 | IXGBE_SRRCTL_BSIZEHDR_MASK; | |
2916 | ||
7d637bcc | 2917 | if (ring_is_ps_enabled(rx_ring)) { |
afafd5b0 AD |
2918 | #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER |
2919 | srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
2920 | #else | |
2921 | srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
2922 | #endif | |
cc41ac7c | 2923 | srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS; |
cc41ac7c | 2924 | } else { |
afafd5b0 AD |
2925 | srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >> |
2926 | IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
cc41ac7c | 2927 | srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; |
cc41ac7c | 2928 | } |
e8e26350 | 2929 | |
bf29ee6c | 2930 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl); |
cc41ac7c | 2931 | } |
9a799d71 | 2932 | |
05abb126 | 2933 | static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter) |
0cefafad | 2934 | { |
05abb126 AD |
2935 | struct ixgbe_hw *hw = &adapter->hw; |
2936 | static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D, | |
e8e9f696 JP |
2937 | 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE, |
2938 | 0x6A3E67EA, 0x14364D17, 0x3BED200D}; | |
05abb126 AD |
2939 | u32 mrqc = 0, reta = 0; |
2940 | u32 rxcsum; | |
2941 | int i, j; | |
0cefafad JB |
2942 | int mask; |
2943 | ||
05abb126 AD |
2944 | /* Fill out hash function seeds */ |
2945 | for (i = 0; i < 10; i++) | |
2946 | IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]); | |
2947 | ||
2948 | /* Fill out redirection table */ | |
2949 | for (i = 0, j = 0; i < 128; i++, j++) { | |
2950 | if (j == adapter->ring_feature[RING_F_RSS].indices) | |
2951 | j = 0; | |
2952 | /* reta = 4-byte sliding window of | |
2953 | * 0x00..(indices-1)(indices-1)00..etc. */ | |
2954 | reta = (reta << 8) | (j * 0x11); | |
2955 | if ((i & 3) == 3) | |
2956 | IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); | |
2957 | } | |
0cefafad | 2958 | |
05abb126 AD |
2959 | /* Disable indicating checksum in descriptor, enables RSS hash */ |
2960 | rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); | |
2961 | rxcsum |= IXGBE_RXCSUM_PCSD; | |
2962 | IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); | |
2963 | ||
2964 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) | |
2965 | mask = adapter->flags & IXGBE_FLAG_RSS_ENABLED; | |
2966 | else | |
2967 | mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED | |
0cefafad | 2968 | #ifdef CONFIG_IXGBE_DCB |
05abb126 | 2969 | | IXGBE_FLAG_DCB_ENABLED |
0cefafad | 2970 | #endif |
05abb126 AD |
2971 | | IXGBE_FLAG_SRIOV_ENABLED |
2972 | ); | |
0cefafad JB |
2973 | |
2974 | switch (mask) { | |
8187cd48 JF |
2975 | #ifdef CONFIG_IXGBE_DCB |
2976 | case (IXGBE_FLAG_DCB_ENABLED | IXGBE_FLAG_RSS_ENABLED): | |
2977 | mrqc = IXGBE_MRQC_RTRSS8TCEN; | |
2978 | break; | |
2979 | case (IXGBE_FLAG_DCB_ENABLED): | |
2980 | mrqc = IXGBE_MRQC_RT8TCEN; | |
2981 | break; | |
2982 | #endif /* CONFIG_IXGBE_DCB */ | |
0cefafad JB |
2983 | case (IXGBE_FLAG_RSS_ENABLED): |
2984 | mrqc = IXGBE_MRQC_RSSEN; | |
2985 | break; | |
1cdd1ec8 GR |
2986 | case (IXGBE_FLAG_SRIOV_ENABLED): |
2987 | mrqc = IXGBE_MRQC_VMDQEN; | |
2988 | break; | |
0cefafad JB |
2989 | default: |
2990 | break; | |
2991 | } | |
2992 | ||
05abb126 AD |
2993 | /* Perform hash on these packet types */ |
2994 | mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 | |
2995 | | IXGBE_MRQC_RSS_FIELD_IPV4_TCP | |
2996 | | IXGBE_MRQC_RSS_FIELD_IPV6 | |
2997 | | IXGBE_MRQC_RSS_FIELD_IPV6_TCP; | |
2998 | ||
2999 | IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); | |
0cefafad JB |
3000 | } |
3001 | ||
b93a2226 DS |
3002 | /** |
3003 | * ixgbe_clear_rscctl - disable RSC for the indicated ring | |
3004 | * @adapter: address of board private structure | |
3005 | * @ring: structure containing ring specific data | |
3006 | **/ | |
3007 | void ixgbe_clear_rscctl(struct ixgbe_adapter *adapter, | |
3008 | struct ixgbe_ring *ring) | |
3009 | { | |
3010 | struct ixgbe_hw *hw = &adapter->hw; | |
3011 | u32 rscctrl; | |
3012 | u8 reg_idx = ring->reg_idx; | |
3013 | ||
3014 | rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx)); | |
3015 | rscctrl &= ~IXGBE_RSCCTL_RSCEN; | |
3016 | IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl); | |
3017 | } | |
3018 | ||
bb5a9ad2 NS |
3019 | /** |
3020 | * ixgbe_configure_rscctl - enable RSC for the indicated ring | |
3021 | * @adapter: address of board private structure | |
3022 | * @index: index of ring to set | |
bb5a9ad2 | 3023 | **/ |
b93a2226 | 3024 | void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, |
7367096a | 3025 | struct ixgbe_ring *ring) |
bb5a9ad2 | 3026 | { |
bb5a9ad2 | 3027 | struct ixgbe_hw *hw = &adapter->hw; |
bb5a9ad2 | 3028 | u32 rscctrl; |
edd2ea55 | 3029 | int rx_buf_len; |
bf29ee6c | 3030 | u8 reg_idx = ring->reg_idx; |
7367096a | 3031 | |
7d637bcc | 3032 | if (!ring_is_rsc_enabled(ring)) |
7367096a | 3033 | return; |
bb5a9ad2 | 3034 | |
7367096a AD |
3035 | rx_buf_len = ring->rx_buf_len; |
3036 | rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx)); | |
bb5a9ad2 NS |
3037 | rscctrl |= IXGBE_RSCCTL_RSCEN; |
3038 | /* | |
3039 | * we must limit the number of descriptors so that the | |
3040 | * total size of max desc * buf_len is not greater | |
3041 | * than 65535 | |
3042 | */ | |
7d637bcc | 3043 | if (ring_is_ps_enabled(ring)) { |
bb5a9ad2 NS |
3044 | #if (MAX_SKB_FRAGS > 16) |
3045 | rscctrl |= IXGBE_RSCCTL_MAXDESC_16; | |
3046 | #elif (MAX_SKB_FRAGS > 8) | |
3047 | rscctrl |= IXGBE_RSCCTL_MAXDESC_8; | |
3048 | #elif (MAX_SKB_FRAGS > 4) | |
3049 | rscctrl |= IXGBE_RSCCTL_MAXDESC_4; | |
3050 | #else | |
3051 | rscctrl |= IXGBE_RSCCTL_MAXDESC_1; | |
3052 | #endif | |
3053 | } else { | |
3054 | if (rx_buf_len < IXGBE_RXBUFFER_4096) | |
3055 | rscctrl |= IXGBE_RSCCTL_MAXDESC_16; | |
3056 | else if (rx_buf_len < IXGBE_RXBUFFER_8192) | |
3057 | rscctrl |= IXGBE_RSCCTL_MAXDESC_8; | |
3058 | else | |
3059 | rscctrl |= IXGBE_RSCCTL_MAXDESC_4; | |
3060 | } | |
7367096a | 3061 | IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl); |
bb5a9ad2 NS |
3062 | } |
3063 | ||
9e10e045 AD |
3064 | /** |
3065 | * ixgbe_set_uta - Set unicast filter table address | |
3066 | * @adapter: board private structure | |
3067 | * | |
3068 | * The unicast table address is a register array of 32-bit registers. | |
3069 | * The table is meant to be used in a way similar to how the MTA is used | |
3070 | * however due to certain limitations in the hardware it is necessary to | |
3071 | * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous | |
3072 | * enable bit to allow vlan tag stripping when promiscuous mode is enabled | |
3073 | **/ | |
3074 | static void ixgbe_set_uta(struct ixgbe_adapter *adapter) | |
3075 | { | |
3076 | struct ixgbe_hw *hw = &adapter->hw; | |
3077 | int i; | |
3078 | ||
3079 | /* The UTA table only exists on 82599 hardware and newer */ | |
3080 | if (hw->mac.type < ixgbe_mac_82599EB) | |
3081 | return; | |
3082 | ||
3083 | /* we only need to do this if VMDq is enabled */ | |
3084 | if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) | |
3085 | return; | |
3086 | ||
3087 | for (i = 0; i < 128; i++) | |
3088 | IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0); | |
3089 | } | |
3090 | ||
3091 | #define IXGBE_MAX_RX_DESC_POLL 10 | |
3092 | static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter, | |
3093 | struct ixgbe_ring *ring) | |
3094 | { | |
3095 | struct ixgbe_hw *hw = &adapter->hw; | |
9e10e045 AD |
3096 | int wait_loop = IXGBE_MAX_RX_DESC_POLL; |
3097 | u32 rxdctl; | |
bf29ee6c | 3098 | u8 reg_idx = ring->reg_idx; |
9e10e045 AD |
3099 | |
3100 | /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */ | |
3101 | if (hw->mac.type == ixgbe_mac_82598EB && | |
3102 | !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) | |
3103 | return; | |
3104 | ||
3105 | do { | |
032b4325 | 3106 | usleep_range(1000, 2000); |
9e10e045 AD |
3107 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); |
3108 | } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE)); | |
3109 | ||
3110 | if (!wait_loop) { | |
3111 | e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within " | |
3112 | "the polling period\n", reg_idx); | |
3113 | } | |
3114 | } | |
3115 | ||
2d39d576 YZ |
3116 | void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, |
3117 | struct ixgbe_ring *ring) | |
3118 | { | |
3119 | struct ixgbe_hw *hw = &adapter->hw; | |
3120 | int wait_loop = IXGBE_MAX_RX_DESC_POLL; | |
3121 | u32 rxdctl; | |
3122 | u8 reg_idx = ring->reg_idx; | |
3123 | ||
3124 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); | |
3125 | rxdctl &= ~IXGBE_RXDCTL_ENABLE; | |
3126 | ||
3127 | /* write value back with RXDCTL.ENABLE bit cleared */ | |
3128 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); | |
3129 | ||
3130 | if (hw->mac.type == ixgbe_mac_82598EB && | |
3131 | !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) | |
3132 | return; | |
3133 | ||
3134 | /* the hardware may take up to 100us to really disable the rx queue */ | |
3135 | do { | |
3136 | udelay(10); | |
3137 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); | |
3138 | } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE)); | |
3139 | ||
3140 | if (!wait_loop) { | |
3141 | e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within " | |
3142 | "the polling period\n", reg_idx); | |
3143 | } | |
3144 | } | |
3145 | ||
84418e3b AD |
3146 | void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter, |
3147 | struct ixgbe_ring *ring) | |
acd37177 AD |
3148 | { |
3149 | struct ixgbe_hw *hw = &adapter->hw; | |
3150 | u64 rdba = ring->dma; | |
9e10e045 | 3151 | u32 rxdctl; |
bf29ee6c | 3152 | u8 reg_idx = ring->reg_idx; |
acd37177 | 3153 | |
9e10e045 AD |
3154 | /* disable queue to avoid issues while updating state */ |
3155 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); | |
2d39d576 | 3156 | ixgbe_disable_rx_queue(adapter, ring); |
9e10e045 | 3157 | |
acd37177 AD |
3158 | IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32))); |
3159 | IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32)); | |
3160 | IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx), | |
3161 | ring->count * sizeof(union ixgbe_adv_rx_desc)); | |
3162 | IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0); | |
3163 | IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0); | |
84ea2591 | 3164 | ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx); |
9e10e045 AD |
3165 | |
3166 | ixgbe_configure_srrctl(adapter, ring); | |
3167 | ixgbe_configure_rscctl(adapter, ring); | |
3168 | ||
e9f98072 GR |
3169 | /* If operating in IOV mode set RLPML for X540 */ |
3170 | if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && | |
3171 | hw->mac.type == ixgbe_mac_X540) { | |
3172 | rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK; | |
3173 | rxdctl |= ((ring->netdev->mtu + ETH_HLEN + | |
3174 | ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN); | |
3175 | } | |
3176 | ||
9e10e045 AD |
3177 | if (hw->mac.type == ixgbe_mac_82598EB) { |
3178 | /* | |
3179 | * enable cache line friendly hardware writes: | |
3180 | * PTHRESH=32 descriptors (half the internal cache), | |
3181 | * this also removes ugly rx_no_buffer_count increment | |
3182 | * HTHRESH=4 descriptors (to minimize latency on fetch) | |
3183 | * WTHRESH=8 burst writeback up to two cache lines | |
3184 | */ | |
3185 | rxdctl &= ~0x3FFFFF; | |
3186 | rxdctl |= 0x080420; | |
3187 | } | |
3188 | ||
3189 | /* enable receive descriptor ring */ | |
3190 | rxdctl |= IXGBE_RXDCTL_ENABLE; | |
3191 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); | |
3192 | ||
3193 | ixgbe_rx_desc_queue_enable(adapter, ring); | |
fc77dc3c | 3194 | ixgbe_alloc_rx_buffers(ring, IXGBE_DESC_UNUSED(ring)); |
acd37177 AD |
3195 | } |
3196 | ||
48654521 AD |
3197 | static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter) |
3198 | { | |
3199 | struct ixgbe_hw *hw = &adapter->hw; | |
3200 | int p; | |
3201 | ||
3202 | /* PSRTYPE must be initialized in non 82598 adapters */ | |
3203 | u32 psrtype = IXGBE_PSRTYPE_TCPHDR | | |
e8e9f696 JP |
3204 | IXGBE_PSRTYPE_UDPHDR | |
3205 | IXGBE_PSRTYPE_IPV4HDR | | |
48654521 | 3206 | IXGBE_PSRTYPE_L2HDR | |
e8e9f696 | 3207 | IXGBE_PSRTYPE_IPV6HDR; |
48654521 AD |
3208 | |
3209 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3210 | return; | |
3211 | ||
3212 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) | |
3213 | psrtype |= (adapter->num_rx_queues_per_pool << 29); | |
3214 | ||
3215 | for (p = 0; p < adapter->num_rx_pools; p++) | |
3216 | IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p), | |
3217 | psrtype); | |
3218 | } | |
3219 | ||
f5b4a52e AD |
3220 | static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter) |
3221 | { | |
3222 | struct ixgbe_hw *hw = &adapter->hw; | |
3223 | u32 gcr_ext; | |
3224 | u32 vt_reg_bits; | |
3225 | u32 reg_offset, vf_shift; | |
3226 | u32 vmdctl; | |
3227 | ||
3228 | if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) | |
3229 | return; | |
3230 | ||
3231 | vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); | |
3232 | vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN; | |
3233 | vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT); | |
3234 | IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits); | |
3235 | ||
3236 | vf_shift = adapter->num_vfs % 32; | |
3237 | reg_offset = (adapter->num_vfs > 32) ? 1 : 0; | |
3238 | ||
3239 | /* Enable only the PF's pool for Tx/Rx */ | |
3240 | IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift)); | |
3241 | IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0); | |
3242 | IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift)); | |
3243 | IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0); | |
3244 | IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); | |
3245 | ||
3246 | /* Map PF MAC address in RAR Entry 0 to first pool following VFs */ | |
3247 | hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs); | |
3248 | ||
3249 | /* | |
3250 | * Set up VF register offsets for selected VT Mode, | |
3251 | * i.e. 32 or 64 VFs for SR-IOV | |
3252 | */ | |
3253 | gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); | |
3254 | gcr_ext |= IXGBE_GCR_EXT_MSIX_EN; | |
3255 | gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64; | |
3256 | IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); | |
3257 | ||
3258 | /* enable Tx loopback for VF/PF communication */ | |
3259 | IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); | |
a985b6c3 | 3260 | /* Enable MAC Anti-Spoofing */ |
a1cbb15c GR |
3261 | hw->mac.ops.set_mac_anti_spoofing(hw, |
3262 | (adapter->antispoofing_enabled = | |
3263 | (adapter->num_vfs != 0)), | |
a985b6c3 | 3264 | adapter->num_vfs); |
f5b4a52e AD |
3265 | } |
3266 | ||
477de6ed | 3267 | static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter) |
9a799d71 | 3268 | { |
9a799d71 AK |
3269 | struct ixgbe_hw *hw = &adapter->hw; |
3270 | struct net_device *netdev = adapter->netdev; | |
3271 | int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; | |
7c6e0a43 | 3272 | int rx_buf_len; |
477de6ed AD |
3273 | struct ixgbe_ring *rx_ring; |
3274 | int i; | |
3275 | u32 mhadd, hlreg0; | |
48654521 | 3276 | |
9a799d71 | 3277 | /* Decide whether to use packet split mode or not */ |
a124339a DS |
3278 | /* On by default */ |
3279 | adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED; | |
3280 | ||
1cdd1ec8 | 3281 | /* Do not use packet split if we're in SR-IOV Mode */ |
a124339a DS |
3282 | if (adapter->num_vfs) |
3283 | adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED; | |
3284 | ||
3285 | /* Disable packet split due to 82599 erratum #45 */ | |
3286 | if (hw->mac.type == ixgbe_mac_82599EB) | |
3287 | adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED; | |
9a799d71 AK |
3288 | |
3289 | /* Set the RX buffer length according to the mode */ | |
3290 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { | |
7c6e0a43 | 3291 | rx_buf_len = IXGBE_RX_HDR_SIZE; |
9a799d71 | 3292 | } else { |
0c19d6af | 3293 | if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) && |
f8212f97 | 3294 | (netdev->mtu <= ETH_DATA_LEN)) |
7c6e0a43 | 3295 | rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE; |
9a799d71 | 3296 | else |
477de6ed | 3297 | rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024); |
9a799d71 AK |
3298 | } |
3299 | ||
63f39bd1 | 3300 | #ifdef IXGBE_FCOE |
477de6ed AD |
3301 | /* adjust max frame to be able to do baby jumbo for FCoE */ |
3302 | if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && | |
3303 | (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE)) | |
3304 | max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE; | |
9a799d71 | 3305 | |
477de6ed AD |
3306 | #endif /* IXGBE_FCOE */ |
3307 | mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); | |
3308 | if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) { | |
3309 | mhadd &= ~IXGBE_MHADD_MFS_MASK; | |
3310 | mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT; | |
3311 | ||
3312 | IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); | |
3313 | } | |
3314 | ||
3315 | hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); | |
3316 | /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */ | |
3317 | hlreg0 |= IXGBE_HLREG0_JUMBOEN; | |
3318 | IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); | |
9a799d71 | 3319 | |
0cefafad JB |
3320 | /* |
3321 | * Setup the HW Rx Head and Tail Descriptor Pointers and | |
3322 | * the Base and Length of the Rx Descriptor Ring | |
3323 | */ | |
9a799d71 | 3324 | for (i = 0; i < adapter->num_rx_queues; i++) { |
4a0b9ca0 | 3325 | rx_ring = adapter->rx_ring[i]; |
a6616b42 | 3326 | rx_ring->rx_buf_len = rx_buf_len; |
cc41ac7c | 3327 | |
6e455b89 | 3328 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) |
7d637bcc AD |
3329 | set_ring_ps_enabled(rx_ring); |
3330 | else | |
3331 | clear_ring_ps_enabled(rx_ring); | |
3332 | ||
3333 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) | |
3334 | set_ring_rsc_enabled(rx_ring); | |
1b3ff02e | 3335 | else |
7d637bcc | 3336 | clear_ring_rsc_enabled(rx_ring); |
cc41ac7c | 3337 | |
63f39bd1 | 3338 | #ifdef IXGBE_FCOE |
e8e9f696 | 3339 | if (netdev->features & NETIF_F_FCOE_MTU) { |
63f39bd1 YZ |
3340 | struct ixgbe_ring_feature *f; |
3341 | f = &adapter->ring_feature[RING_F_FCOE]; | |
6e455b89 | 3342 | if ((i >= f->mask) && (i < f->mask + f->indices)) { |
7d637bcc | 3343 | clear_ring_ps_enabled(rx_ring); |
6e455b89 YZ |
3344 | if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE) |
3345 | rx_ring->rx_buf_len = | |
e8e9f696 | 3346 | IXGBE_FCOE_JUMBO_FRAME_SIZE; |
7d637bcc AD |
3347 | } else if (!ring_is_rsc_enabled(rx_ring) && |
3348 | !ring_is_ps_enabled(rx_ring)) { | |
3349 | rx_ring->rx_buf_len = | |
3350 | IXGBE_FCOE_JUMBO_FRAME_SIZE; | |
6e455b89 | 3351 | } |
63f39bd1 | 3352 | } |
63f39bd1 | 3353 | #endif /* IXGBE_FCOE */ |
477de6ed | 3354 | } |
477de6ed AD |
3355 | } |
3356 | ||
7367096a AD |
3357 | static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter) |
3358 | { | |
3359 | struct ixgbe_hw *hw = &adapter->hw; | |
3360 | u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); | |
3361 | ||
3362 | switch (hw->mac.type) { | |
3363 | case ixgbe_mac_82598EB: | |
3364 | /* | |
3365 | * For VMDq support of different descriptor types or | |
3366 | * buffer sizes through the use of multiple SRRCTL | |
3367 | * registers, RDRXCTL.MVMEN must be set to 1 | |
3368 | * | |
3369 | * also, the manual doesn't mention it clearly but DCA hints | |
3370 | * will only use queue 0's tags unless this bit is set. Side | |
3371 | * effects of setting this bit are only that SRRCTL must be | |
3372 | * fully programmed [0..15] | |
3373 | */ | |
3374 | rdrxctl |= IXGBE_RDRXCTL_MVMEN; | |
3375 | break; | |
3376 | case ixgbe_mac_82599EB: | |
b93a2226 | 3377 | case ixgbe_mac_X540: |
7367096a AD |
3378 | /* Disable RSC for ACK packets */ |
3379 | IXGBE_WRITE_REG(hw, IXGBE_RSCDBU, | |
3380 | (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU))); | |
3381 | rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE; | |
3382 | /* hardware requires some bits to be set by default */ | |
3383 | rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX); | |
3384 | rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP; | |
3385 | break; | |
3386 | default: | |
3387 | /* We should do nothing since we don't know this hardware */ | |
3388 | return; | |
3389 | } | |
3390 | ||
3391 | IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); | |
3392 | } | |
3393 | ||
477de6ed AD |
3394 | /** |
3395 | * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset | |
3396 | * @adapter: board private structure | |
3397 | * | |
3398 | * Configure the Rx unit of the MAC after a reset. | |
3399 | **/ | |
3400 | static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) | |
3401 | { | |
3402 | struct ixgbe_hw *hw = &adapter->hw; | |
477de6ed AD |
3403 | int i; |
3404 | u32 rxctrl; | |
477de6ed AD |
3405 | |
3406 | /* disable receives while setting up the descriptors */ | |
3407 | rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); | |
3408 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); | |
3409 | ||
3410 | ixgbe_setup_psrtype(adapter); | |
7367096a | 3411 | ixgbe_setup_rdrxctl(adapter); |
477de6ed | 3412 | |
9e10e045 | 3413 | /* Program registers for the distribution of queues */ |
f5b4a52e | 3414 | ixgbe_setup_mrqc(adapter); |
f5b4a52e | 3415 | |
9e10e045 AD |
3416 | ixgbe_set_uta(adapter); |
3417 | ||
477de6ed AD |
3418 | /* set_rx_buffer_len must be called before ring initialization */ |
3419 | ixgbe_set_rx_buffer_len(adapter); | |
3420 | ||
3421 | /* | |
3422 | * Setup the HW Rx Head and Tail Descriptor Pointers and | |
3423 | * the Base and Length of the Rx Descriptor Ring | |
3424 | */ | |
9e10e045 AD |
3425 | for (i = 0; i < adapter->num_rx_queues; i++) |
3426 | ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]); | |
177db6ff | 3427 | |
9e10e045 AD |
3428 | /* disable drop enable for 82598 parts */ |
3429 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3430 | rxctrl |= IXGBE_RXCTRL_DMBYPS; | |
3431 | ||
3432 | /* enable all receives */ | |
3433 | rxctrl |= IXGBE_RXCTRL_RXEN; | |
3434 | hw->mac.ops.enable_rx_dma(hw, rxctrl); | |
9a799d71 AK |
3435 | } |
3436 | ||
068c89b0 DS |
3437 | static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid) |
3438 | { | |
3439 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3440 | struct ixgbe_hw *hw = &adapter->hw; | |
1ada1b1b | 3441 | int pool_ndx = adapter->num_vfs; |
068c89b0 DS |
3442 | |
3443 | /* add VID to filter table */ | |
1ada1b1b | 3444 | hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true); |
f62bbb5e | 3445 | set_bit(vid, adapter->active_vlans); |
068c89b0 DS |
3446 | } |
3447 | ||
3448 | static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) | |
3449 | { | |
3450 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3451 | struct ixgbe_hw *hw = &adapter->hw; | |
1ada1b1b | 3452 | int pool_ndx = adapter->num_vfs; |
068c89b0 | 3453 | |
068c89b0 | 3454 | /* remove VID from filter table */ |
1ada1b1b | 3455 | hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false); |
f62bbb5e | 3456 | clear_bit(vid, adapter->active_vlans); |
068c89b0 DS |
3457 | } |
3458 | ||
5f6c0181 JB |
3459 | /** |
3460 | * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering | |
3461 | * @adapter: driver data | |
3462 | */ | |
3463 | static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter) | |
3464 | { | |
3465 | struct ixgbe_hw *hw = &adapter->hw; | |
f62bbb5e JG |
3466 | u32 vlnctrl; |
3467 | ||
3468 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); | |
3469 | vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN); | |
3470 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); | |
3471 | } | |
3472 | ||
3473 | /** | |
3474 | * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering | |
3475 | * @adapter: driver data | |
3476 | */ | |
3477 | static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter) | |
3478 | { | |
3479 | struct ixgbe_hw *hw = &adapter->hw; | |
3480 | u32 vlnctrl; | |
3481 | ||
3482 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); | |
3483 | vlnctrl |= IXGBE_VLNCTRL_VFE; | |
3484 | vlnctrl &= ~IXGBE_VLNCTRL_CFIEN; | |
3485 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); | |
3486 | } | |
3487 | ||
3488 | /** | |
3489 | * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping | |
3490 | * @adapter: driver data | |
3491 | */ | |
3492 | static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter) | |
3493 | { | |
3494 | struct ixgbe_hw *hw = &adapter->hw; | |
3495 | u32 vlnctrl; | |
5f6c0181 JB |
3496 | int i, j; |
3497 | ||
3498 | switch (hw->mac.type) { | |
3499 | case ixgbe_mac_82598EB: | |
f62bbb5e JG |
3500 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); |
3501 | vlnctrl &= ~IXGBE_VLNCTRL_VME; | |
5f6c0181 JB |
3502 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); |
3503 | break; | |
3504 | case ixgbe_mac_82599EB: | |
b93a2226 | 3505 | case ixgbe_mac_X540: |
5f6c0181 JB |
3506 | for (i = 0; i < adapter->num_rx_queues; i++) { |
3507 | j = adapter->rx_ring[i]->reg_idx; | |
3508 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); | |
3509 | vlnctrl &= ~IXGBE_RXDCTL_VME; | |
3510 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); | |
3511 | } | |
3512 | break; | |
3513 | default: | |
3514 | break; | |
3515 | } | |
3516 | } | |
3517 | ||
3518 | /** | |
f62bbb5e | 3519 | * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping |
5f6c0181 JB |
3520 | * @adapter: driver data |
3521 | */ | |
f62bbb5e | 3522 | static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter) |
5f6c0181 JB |
3523 | { |
3524 | struct ixgbe_hw *hw = &adapter->hw; | |
f62bbb5e | 3525 | u32 vlnctrl; |
5f6c0181 JB |
3526 | int i, j; |
3527 | ||
3528 | switch (hw->mac.type) { | |
3529 | case ixgbe_mac_82598EB: | |
f62bbb5e JG |
3530 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); |
3531 | vlnctrl |= IXGBE_VLNCTRL_VME; | |
5f6c0181 JB |
3532 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); |
3533 | break; | |
3534 | case ixgbe_mac_82599EB: | |
b93a2226 | 3535 | case ixgbe_mac_X540: |
5f6c0181 JB |
3536 | for (i = 0; i < adapter->num_rx_queues; i++) { |
3537 | j = adapter->rx_ring[i]->reg_idx; | |
3538 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); | |
3539 | vlnctrl |= IXGBE_RXDCTL_VME; | |
3540 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); | |
3541 | } | |
3542 | break; | |
3543 | default: | |
3544 | break; | |
3545 | } | |
3546 | } | |
3547 | ||
9a799d71 AK |
3548 | static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter) |
3549 | { | |
f62bbb5e | 3550 | u16 vid; |
9a799d71 | 3551 | |
f62bbb5e JG |
3552 | ixgbe_vlan_rx_add_vid(adapter->netdev, 0); |
3553 | ||
3554 | for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) | |
3555 | ixgbe_vlan_rx_add_vid(adapter->netdev, vid); | |
9a799d71 AK |
3556 | } |
3557 | ||
2850062a AD |
3558 | /** |
3559 | * ixgbe_write_uc_addr_list - write unicast addresses to RAR table | |
3560 | * @netdev: network interface device structure | |
3561 | * | |
3562 | * Writes unicast address list to the RAR table. | |
3563 | * Returns: -ENOMEM on failure/insufficient address space | |
3564 | * 0 on no addresses written | |
3565 | * X on writing X addresses to the RAR table | |
3566 | **/ | |
3567 | static int ixgbe_write_uc_addr_list(struct net_device *netdev) | |
3568 | { | |
3569 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3570 | struct ixgbe_hw *hw = &adapter->hw; | |
3571 | unsigned int vfn = adapter->num_vfs; | |
a1cbb15c | 3572 | unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS; |
2850062a AD |
3573 | int count = 0; |
3574 | ||
3575 | /* return ENOMEM indicating insufficient memory for addresses */ | |
3576 | if (netdev_uc_count(netdev) > rar_entries) | |
3577 | return -ENOMEM; | |
3578 | ||
3579 | if (!netdev_uc_empty(netdev) && rar_entries) { | |
3580 | struct netdev_hw_addr *ha; | |
3581 | /* return error if we do not support writing to RAR table */ | |
3582 | if (!hw->mac.ops.set_rar) | |
3583 | return -ENOMEM; | |
3584 | ||
3585 | netdev_for_each_uc_addr(ha, netdev) { | |
3586 | if (!rar_entries) | |
3587 | break; | |
3588 | hw->mac.ops.set_rar(hw, rar_entries--, ha->addr, | |
3589 | vfn, IXGBE_RAH_AV); | |
3590 | count++; | |
3591 | } | |
3592 | } | |
3593 | /* write the addresses in reverse order to avoid write combining */ | |
3594 | for (; rar_entries > 0 ; rar_entries--) | |
3595 | hw->mac.ops.clear_rar(hw, rar_entries); | |
3596 | ||
3597 | return count; | |
3598 | } | |
3599 | ||
9a799d71 | 3600 | /** |
2c5645cf | 3601 | * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set |
9a799d71 AK |
3602 | * @netdev: network interface device structure |
3603 | * | |
2c5645cf CL |
3604 | * The set_rx_method entry point is called whenever the unicast/multicast |
3605 | * address list or the network interface flags are updated. This routine is | |
3606 | * responsible for configuring the hardware for proper unicast, multicast and | |
3607 | * promiscuous mode. | |
9a799d71 | 3608 | **/ |
7f870475 | 3609 | void ixgbe_set_rx_mode(struct net_device *netdev) |
9a799d71 AK |
3610 | { |
3611 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3612 | struct ixgbe_hw *hw = &adapter->hw; | |
2850062a AD |
3613 | u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE; |
3614 | int count; | |
9a799d71 AK |
3615 | |
3616 | /* Check for Promiscuous and All Multicast modes */ | |
3617 | ||
3618 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
3619 | ||
f5dc442b AD |
3620 | /* set all bits that we expect to always be set */ |
3621 | fctrl |= IXGBE_FCTRL_BAM; | |
3622 | fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */ | |
3623 | fctrl |= IXGBE_FCTRL_PMCF; | |
3624 | ||
2850062a AD |
3625 | /* clear the bits we are changing the status of */ |
3626 | fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); | |
3627 | ||
9a799d71 | 3628 | if (netdev->flags & IFF_PROMISC) { |
e433ea1f | 3629 | hw->addr_ctrl.user_set_promisc = true; |
9a799d71 | 3630 | fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); |
2850062a | 3631 | vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE); |
5f6c0181 JB |
3632 | /* don't hardware filter vlans in promisc mode */ |
3633 | ixgbe_vlan_filter_disable(adapter); | |
9a799d71 | 3634 | } else { |
746b9f02 PM |
3635 | if (netdev->flags & IFF_ALLMULTI) { |
3636 | fctrl |= IXGBE_FCTRL_MPE; | |
2850062a AD |
3637 | vmolr |= IXGBE_VMOLR_MPE; |
3638 | } else { | |
3639 | /* | |
3640 | * Write addresses to the MTA, if the attempt fails | |
25985edc | 3641 | * then we should just turn on promiscuous mode so |
2850062a AD |
3642 | * that we can at least receive multicast traffic |
3643 | */ | |
3644 | hw->mac.ops.update_mc_addr_list(hw, netdev); | |
3645 | vmolr |= IXGBE_VMOLR_ROMPE; | |
746b9f02 | 3646 | } |
5f6c0181 | 3647 | ixgbe_vlan_filter_enable(adapter); |
e433ea1f | 3648 | hw->addr_ctrl.user_set_promisc = false; |
2850062a AD |
3649 | /* |
3650 | * Write addresses to available RAR registers, if there is not | |
3651 | * sufficient space to store all the addresses then enable | |
25985edc | 3652 | * unicast promiscuous mode |
2850062a AD |
3653 | */ |
3654 | count = ixgbe_write_uc_addr_list(netdev); | |
3655 | if (count < 0) { | |
3656 | fctrl |= IXGBE_FCTRL_UPE; | |
3657 | vmolr |= IXGBE_VMOLR_ROPE; | |
3658 | } | |
9a799d71 AK |
3659 | } |
3660 | ||
2850062a | 3661 | if (adapter->num_vfs) { |
1cdd1ec8 | 3662 | ixgbe_restore_vf_multicasts(adapter); |
2850062a AD |
3663 | vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) & |
3664 | ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE | | |
3665 | IXGBE_VMOLR_ROPE); | |
3666 | IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr); | |
3667 | } | |
3668 | ||
3669 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); | |
f62bbb5e JG |
3670 | |
3671 | if (netdev->features & NETIF_F_HW_VLAN_RX) | |
3672 | ixgbe_vlan_strip_enable(adapter); | |
3673 | else | |
3674 | ixgbe_vlan_strip_disable(adapter); | |
9a799d71 AK |
3675 | } |
3676 | ||
021230d4 AV |
3677 | static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter) |
3678 | { | |
3679 | int q_idx; | |
3680 | struct ixgbe_q_vector *q_vector; | |
3681 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
3682 | ||
3683 | /* legacy and MSI only use one vector */ | |
3684 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
3685 | q_vectors = 1; | |
3686 | ||
3687 | for (q_idx = 0; q_idx < q_vectors; q_idx++) { | |
f0848276 | 3688 | struct napi_struct *napi; |
7a921c93 | 3689 | q_vector = adapter->q_vector[q_idx]; |
f0848276 | 3690 | napi = &q_vector->napi; |
91281fd3 AD |
3691 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
3692 | if (!q_vector->rxr_count || !q_vector->txr_count) { | |
3693 | if (q_vector->txr_count == 1) | |
3694 | napi->poll = &ixgbe_clean_txonly; | |
3695 | else if (q_vector->rxr_count == 1) | |
3696 | napi->poll = &ixgbe_clean_rxonly; | |
3697 | } | |
3698 | } | |
f0848276 JB |
3699 | |
3700 | napi_enable(napi); | |
021230d4 AV |
3701 | } |
3702 | } | |
3703 | ||
3704 | static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter) | |
3705 | { | |
3706 | int q_idx; | |
3707 | struct ixgbe_q_vector *q_vector; | |
3708 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
3709 | ||
3710 | /* legacy and MSI only use one vector */ | |
3711 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
3712 | q_vectors = 1; | |
3713 | ||
3714 | for (q_idx = 0; q_idx < q_vectors; q_idx++) { | |
7a921c93 | 3715 | q_vector = adapter->q_vector[q_idx]; |
021230d4 AV |
3716 | napi_disable(&q_vector->napi); |
3717 | } | |
3718 | } | |
3719 | ||
7a6b6f51 | 3720 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
3721 | /* |
3722 | * ixgbe_configure_dcb - Configure DCB hardware | |
3723 | * @adapter: ixgbe adapter struct | |
3724 | * | |
3725 | * This is called by the driver on open to configure the DCB hardware. | |
3726 | * This is also called by the gennetlink interface when reconfiguring | |
3727 | * the DCB state. | |
3728 | */ | |
3729 | static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter) | |
3730 | { | |
3731 | struct ixgbe_hw *hw = &adapter->hw; | |
9806307a | 3732 | int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN; |
2f90b865 | 3733 | |
67ebd791 AD |
3734 | if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) { |
3735 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3736 | netif_set_gso_max_size(adapter->netdev, 65536); | |
3737 | return; | |
3738 | } | |
3739 | ||
3740 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3741 | netif_set_gso_max_size(adapter->netdev, 32768); | |
3742 | ||
2f90b865 | 3743 | |
2f90b865 | 3744 | /* Enable VLAN tag insert/strip */ |
f62bbb5e | 3745 | adapter->netdev->features |= NETIF_F_HW_VLAN_RX; |
5f6c0181 | 3746 | |
2f90b865 | 3747 | hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true); |
01fa7d90 AD |
3748 | |
3749 | /* reconfigure the hardware */ | |
c27931da JF |
3750 | if (adapter->dcbx_cap & (DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE)) { |
3751 | #ifdef CONFIG_FCOE | |
3752 | if (adapter->netdev->features & NETIF_F_FCOE_MTU) | |
3753 | max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE); | |
3754 | #endif | |
3755 | ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, | |
3756 | DCB_TX_CONFIG); | |
3757 | ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, | |
3758 | DCB_RX_CONFIG); | |
3759 | ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg); | |
3760 | } else { | |
3761 | struct net_device *dev = adapter->netdev; | |
3762 | ||
3763 | if (adapter->ixgbe_ieee_ets) | |
3764 | dev->dcbnl_ops->ieee_setets(dev, | |
3765 | adapter->ixgbe_ieee_ets); | |
3766 | if (adapter->ixgbe_ieee_pfc) | |
3767 | dev->dcbnl_ops->ieee_setpfc(dev, | |
3768 | adapter->ixgbe_ieee_pfc); | |
3769 | } | |
8187cd48 JF |
3770 | |
3771 | /* Enable RSS Hash per TC */ | |
3772 | if (hw->mac.type != ixgbe_mac_82598EB) { | |
3773 | int i; | |
3774 | u32 reg = 0; | |
3775 | ||
3776 | for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { | |
3777 | u8 msb = 0; | |
3778 | u8 cnt = adapter->netdev->tc_to_txq[i].count; | |
3779 | ||
3780 | while (cnt >>= 1) | |
3781 | msb++; | |
3782 | ||
3783 | reg |= msb << IXGBE_RQTC_SHIFT_TC(i); | |
3784 | } | |
3785 | IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg); | |
3786 | } | |
2f90b865 AD |
3787 | } |
3788 | ||
3789 | #endif | |
80605c65 JF |
3790 | |
3791 | static void ixgbe_configure_pb(struct ixgbe_adapter *adapter) | |
3792 | { | |
3793 | int hdrm = 0; | |
3794 | int num_tc = netdev_get_num_tc(adapter->netdev); | |
3795 | struct ixgbe_hw *hw = &adapter->hw; | |
3796 | ||
3797 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || | |
3798 | adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) | |
3799 | hdrm = 64 << adapter->fdir_pballoc; | |
3800 | ||
3801 | hw->mac.ops.set_rxpba(&adapter->hw, num_tc, hdrm, PBA_STRATEGY_EQUAL); | |
3802 | } | |
3803 | ||
9a799d71 AK |
3804 | static void ixgbe_configure(struct ixgbe_adapter *adapter) |
3805 | { | |
3806 | struct net_device *netdev = adapter->netdev; | |
c4cf55e5 | 3807 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 AK |
3808 | int i; |
3809 | ||
80605c65 | 3810 | ixgbe_configure_pb(adapter); |
7a6b6f51 | 3811 | #ifdef CONFIG_IXGBE_DCB |
67ebd791 | 3812 | ixgbe_configure_dcb(adapter); |
2f90b865 | 3813 | #endif |
9a799d71 | 3814 | |
f62bbb5e JG |
3815 | ixgbe_set_rx_mode(netdev); |
3816 | ixgbe_restore_vlan(adapter); | |
3817 | ||
eacd73f7 YZ |
3818 | #ifdef IXGBE_FCOE |
3819 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) | |
3820 | ixgbe_configure_fcoe(adapter); | |
3821 | ||
3822 | #endif /* IXGBE_FCOE */ | |
c4cf55e5 PWJ |
3823 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { |
3824 | for (i = 0; i < adapter->num_tx_queues; i++) | |
4a0b9ca0 | 3825 | adapter->tx_ring[i]->atr_sample_rate = |
e8e9f696 | 3826 | adapter->atr_sample_rate; |
c4cf55e5 PWJ |
3827 | ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc); |
3828 | } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) { | |
3829 | ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc); | |
3830 | } | |
933d41f1 | 3831 | ixgbe_configure_virtualization(adapter); |
c4cf55e5 | 3832 | |
9a799d71 AK |
3833 | ixgbe_configure_tx(adapter); |
3834 | ixgbe_configure_rx(adapter); | |
9a799d71 AK |
3835 | } |
3836 | ||
e8e26350 PW |
3837 | static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw) |
3838 | { | |
3839 | switch (hw->phy.type) { | |
3840 | case ixgbe_phy_sfp_avago: | |
3841 | case ixgbe_phy_sfp_ftl: | |
3842 | case ixgbe_phy_sfp_intel: | |
3843 | case ixgbe_phy_sfp_unknown: | |
ea0a04df DS |
3844 | case ixgbe_phy_sfp_passive_tyco: |
3845 | case ixgbe_phy_sfp_passive_unknown: | |
3846 | case ixgbe_phy_sfp_active_unknown: | |
3847 | case ixgbe_phy_sfp_ftl_active: | |
e8e26350 PW |
3848 | return true; |
3849 | default: | |
3850 | return false; | |
3851 | } | |
3852 | } | |
3853 | ||
0ecc061d | 3854 | /** |
e8e26350 PW |
3855 | * ixgbe_sfp_link_config - set up SFP+ link |
3856 | * @adapter: pointer to private adapter struct | |
3857 | **/ | |
3858 | static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter) | |
3859 | { | |
7086400d AD |
3860 | /* |
3861 | * We are assuming the worst case scenerio here, and that | |
3862 | * is that an SFP was inserted/removed after the reset | |
3863 | * but before SFP detection was enabled. As such the best | |
3864 | * solution is to just start searching as soon as we start | |
3865 | */ | |
3866 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) | |
3867 | adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; | |
e8e26350 | 3868 | |
7086400d | 3869 | adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; |
e8e26350 PW |
3870 | } |
3871 | ||
3872 | /** | |
3873 | * ixgbe_non_sfp_link_config - set up non-SFP+ link | |
0ecc061d PWJ |
3874 | * @hw: pointer to private hardware struct |
3875 | * | |
3876 | * Returns 0 on success, negative on failure | |
3877 | **/ | |
e8e26350 | 3878 | static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw) |
0ecc061d PWJ |
3879 | { |
3880 | u32 autoneg; | |
8620a103 | 3881 | bool negotiation, link_up = false; |
0ecc061d PWJ |
3882 | u32 ret = IXGBE_ERR_LINK_SETUP; |
3883 | ||
3884 | if (hw->mac.ops.check_link) | |
3885 | ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false); | |
3886 | ||
3887 | if (ret) | |
3888 | goto link_cfg_out; | |
3889 | ||
0b0c2b31 ET |
3890 | autoneg = hw->phy.autoneg_advertised; |
3891 | if ((!autoneg) && (hw->mac.ops.get_link_capabilities)) | |
e8e9f696 JP |
3892 | ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, |
3893 | &negotiation); | |
0ecc061d PWJ |
3894 | if (ret) |
3895 | goto link_cfg_out; | |
3896 | ||
8620a103 MC |
3897 | if (hw->mac.ops.setup_link) |
3898 | ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up); | |
0ecc061d PWJ |
3899 | link_cfg_out: |
3900 | return ret; | |
3901 | } | |
3902 | ||
a34bcfff | 3903 | static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter) |
9a799d71 | 3904 | { |
9a799d71 | 3905 | struct ixgbe_hw *hw = &adapter->hw; |
a34bcfff | 3906 | u32 gpie = 0; |
9a799d71 | 3907 | |
9b471446 | 3908 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
a34bcfff AD |
3909 | gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT | |
3910 | IXGBE_GPIE_OCD; | |
3911 | gpie |= IXGBE_GPIE_EIAME; | |
9b471446 JB |
3912 | /* |
3913 | * use EIAM to auto-mask when MSI-X interrupt is asserted | |
3914 | * this saves a register write for every interrupt | |
3915 | */ | |
3916 | switch (hw->mac.type) { | |
3917 | case ixgbe_mac_82598EB: | |
3918 | IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); | |
3919 | break; | |
9b471446 | 3920 | case ixgbe_mac_82599EB: |
b93a2226 DS |
3921 | case ixgbe_mac_X540: |
3922 | default: | |
9b471446 JB |
3923 | IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); |
3924 | IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); | |
3925 | break; | |
3926 | } | |
3927 | } else { | |
021230d4 AV |
3928 | /* legacy interrupts, use EIAM to auto-mask when reading EICR, |
3929 | * specifically only auto mask tx and rx interrupts */ | |
3930 | IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); | |
3931 | } | |
9a799d71 | 3932 | |
a34bcfff AD |
3933 | /* XXX: to interrupt immediately for EICS writes, enable this */ |
3934 | /* gpie |= IXGBE_GPIE_EIMEN; */ | |
3935 | ||
3936 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { | |
3937 | gpie &= ~IXGBE_GPIE_VTMODE_MASK; | |
3938 | gpie |= IXGBE_GPIE_VTMODE_64; | |
119fc60a MC |
3939 | } |
3940 | ||
a34bcfff AD |
3941 | /* Enable fan failure interrupt */ |
3942 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) | |
0befdb3e | 3943 | gpie |= IXGBE_SDP1_GPIEN; |
0befdb3e | 3944 | |
2698b208 | 3945 | if (hw->mac.type == ixgbe_mac_82599EB) { |
e8e26350 PW |
3946 | gpie |= IXGBE_SDP1_GPIEN; |
3947 | gpie |= IXGBE_SDP2_GPIEN; | |
2698b208 | 3948 | } |
a34bcfff AD |
3949 | |
3950 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
3951 | } | |
3952 | ||
3953 | static int ixgbe_up_complete(struct ixgbe_adapter *adapter) | |
3954 | { | |
3955 | struct ixgbe_hw *hw = &adapter->hw; | |
a34bcfff | 3956 | int err; |
a34bcfff AD |
3957 | u32 ctrl_ext; |
3958 | ||
3959 | ixgbe_get_hw_control(adapter); | |
3960 | ixgbe_setup_gpie(adapter); | |
e8e26350 | 3961 | |
9a799d71 AK |
3962 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
3963 | ixgbe_configure_msix(adapter); | |
3964 | else | |
3965 | ixgbe_configure_msi_and_legacy(adapter); | |
3966 | ||
c6ecf39a DS |
3967 | /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */ |
3968 | if (hw->mac.ops.enable_tx_laser && | |
3969 | ((hw->phy.multispeed_fiber) || | |
9f911707 | 3970 | ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) && |
c6ecf39a | 3971 | (hw->mac.type == ixgbe_mac_82599EB)))) |
61fac744 PW |
3972 | hw->mac.ops.enable_tx_laser(hw); |
3973 | ||
9a799d71 | 3974 | clear_bit(__IXGBE_DOWN, &adapter->state); |
021230d4 AV |
3975 | ixgbe_napi_enable_all(adapter); |
3976 | ||
73c4b7cd AD |
3977 | if (ixgbe_is_sfp(hw)) { |
3978 | ixgbe_sfp_link_config(adapter); | |
3979 | } else { | |
3980 | err = ixgbe_non_sfp_link_config(hw); | |
3981 | if (err) | |
3982 | e_err(probe, "link_config FAILED %d\n", err); | |
3983 | } | |
3984 | ||
021230d4 AV |
3985 | /* clear any pending interrupts, may auto mask */ |
3986 | IXGBE_READ_REG(hw, IXGBE_EICR); | |
6af3b9eb | 3987 | ixgbe_irq_enable(adapter, true, true); |
9a799d71 | 3988 | |
bf069c97 DS |
3989 | /* |
3990 | * If this adapter has a fan, check to see if we had a failure | |
3991 | * before we enabled the interrupt. | |
3992 | */ | |
3993 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
3994 | u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); | |
3995 | if (esdp & IXGBE_ESDP_SDP1) | |
396e799c | 3996 | e_crit(drv, "Fan has stopped, replace the adapter\n"); |
bf069c97 DS |
3997 | } |
3998 | ||
1da100bb | 3999 | /* enable transmits */ |
477de6ed | 4000 | netif_tx_start_all_queues(adapter->netdev); |
1da100bb | 4001 | |
9a799d71 AK |
4002 | /* bring the link up in the watchdog, this could race with our first |
4003 | * link up interrupt but shouldn't be a problem */ | |
cf8280ee JB |
4004 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; |
4005 | adapter->link_check_timeout = jiffies; | |
7086400d | 4006 | mod_timer(&adapter->service_timer, jiffies); |
c9205697 GR |
4007 | |
4008 | /* Set PF Reset Done bit so PF/VF Mail Ops can work */ | |
4009 | ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); | |
4010 | ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; | |
4011 | IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); | |
4012 | ||
9a799d71 AK |
4013 | return 0; |
4014 | } | |
4015 | ||
d4f80882 AV |
4016 | void ixgbe_reinit_locked(struct ixgbe_adapter *adapter) |
4017 | { | |
4018 | WARN_ON(in_interrupt()); | |
7086400d AD |
4019 | /* put off any impending NetWatchDogTimeout */ |
4020 | adapter->netdev->trans_start = jiffies; | |
4021 | ||
d4f80882 | 4022 | while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) |
032b4325 | 4023 | usleep_range(1000, 2000); |
d4f80882 | 4024 | ixgbe_down(adapter); |
5809a1ae GR |
4025 | /* |
4026 | * If SR-IOV enabled then wait a bit before bringing the adapter | |
4027 | * back up to give the VFs time to respond to the reset. The | |
4028 | * two second wait is based upon the watchdog timer cycle in | |
4029 | * the VF driver. | |
4030 | */ | |
4031 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) | |
4032 | msleep(2000); | |
d4f80882 AV |
4033 | ixgbe_up(adapter); |
4034 | clear_bit(__IXGBE_RESETTING, &adapter->state); | |
4035 | } | |
4036 | ||
9a799d71 AK |
4037 | int ixgbe_up(struct ixgbe_adapter *adapter) |
4038 | { | |
4039 | /* hardware has been reset, we need to reload some things */ | |
4040 | ixgbe_configure(adapter); | |
4041 | ||
4042 | return ixgbe_up_complete(adapter); | |
4043 | } | |
4044 | ||
4045 | void ixgbe_reset(struct ixgbe_adapter *adapter) | |
4046 | { | |
c44ade9e | 4047 | struct ixgbe_hw *hw = &adapter->hw; |
8ca783ab DS |
4048 | int err; |
4049 | ||
7086400d AD |
4050 | /* lock SFP init bit to prevent race conditions with the watchdog */ |
4051 | while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) | |
4052 | usleep_range(1000, 2000); | |
4053 | ||
4054 | /* clear all SFP and link config related flags while holding SFP_INIT */ | |
4055 | adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP | | |
4056 | IXGBE_FLAG2_SFP_NEEDS_RESET); | |
4057 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; | |
4058 | ||
8ca783ab | 4059 | err = hw->mac.ops.init_hw(hw); |
da4dd0f7 PWJ |
4060 | switch (err) { |
4061 | case 0: | |
4062 | case IXGBE_ERR_SFP_NOT_PRESENT: | |
7086400d | 4063 | case IXGBE_ERR_SFP_NOT_SUPPORTED: |
da4dd0f7 PWJ |
4064 | break; |
4065 | case IXGBE_ERR_MASTER_REQUESTS_PENDING: | |
849c4542 | 4066 | e_dev_err("master disable timed out\n"); |
da4dd0f7 | 4067 | break; |
794caeb2 PWJ |
4068 | case IXGBE_ERR_EEPROM_VERSION: |
4069 | /* We are running on a pre-production device, log a warning */ | |
849c4542 ET |
4070 | e_dev_warn("This device is a pre-production adapter/LOM. " |
4071 | "Please be aware there may be issuesassociated with " | |
4072 | "your hardware. If you are experiencing problems " | |
4073 | "please contact your Intel or hardware " | |
4074 | "representative who provided you with this " | |
4075 | "hardware.\n"); | |
794caeb2 | 4076 | break; |
da4dd0f7 | 4077 | default: |
849c4542 | 4078 | e_dev_err("Hardware Error: %d\n", err); |
da4dd0f7 | 4079 | } |
9a799d71 | 4080 | |
7086400d AD |
4081 | clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); |
4082 | ||
9a799d71 | 4083 | /* reprogram the RAR[0] in case user changed it. */ |
1cdd1ec8 GR |
4084 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs, |
4085 | IXGBE_RAH_AV); | |
9a799d71 AK |
4086 | } |
4087 | ||
9a799d71 AK |
4088 | /** |
4089 | * ixgbe_clean_rx_ring - Free Rx Buffers per Queue | |
9a799d71 AK |
4090 | * @rx_ring: ring to free buffers from |
4091 | **/ | |
b6ec895e | 4092 | static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring) |
9a799d71 | 4093 | { |
b6ec895e | 4094 | struct device *dev = rx_ring->dev; |
9a799d71 | 4095 | unsigned long size; |
b6ec895e | 4096 | u16 i; |
9a799d71 | 4097 | |
84418e3b AD |
4098 | /* ring already cleared, nothing to do */ |
4099 | if (!rx_ring->rx_buffer_info) | |
4100 | return; | |
9a799d71 | 4101 | |
84418e3b | 4102 | /* Free all the Rx ring sk_buffs */ |
9a799d71 AK |
4103 | for (i = 0; i < rx_ring->count; i++) { |
4104 | struct ixgbe_rx_buffer *rx_buffer_info; | |
4105 | ||
4106 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; | |
4107 | if (rx_buffer_info->dma) { | |
b6ec895e | 4108 | dma_unmap_single(rx_ring->dev, rx_buffer_info->dma, |
e8e9f696 | 4109 | rx_ring->rx_buf_len, |
1b507730 | 4110 | DMA_FROM_DEVICE); |
9a799d71 AK |
4111 | rx_buffer_info->dma = 0; |
4112 | } | |
4113 | if (rx_buffer_info->skb) { | |
f8212f97 | 4114 | struct sk_buff *skb = rx_buffer_info->skb; |
9a799d71 | 4115 | rx_buffer_info->skb = NULL; |
f8212f97 AD |
4116 | do { |
4117 | struct sk_buff *this = skb; | |
e8171aaa | 4118 | if (IXGBE_RSC_CB(this)->delay_unmap) { |
b6ec895e | 4119 | dma_unmap_single(dev, |
1b507730 | 4120 | IXGBE_RSC_CB(this)->dma, |
e8e9f696 | 4121 | rx_ring->rx_buf_len, |
1b507730 | 4122 | DMA_FROM_DEVICE); |
fd3686a8 | 4123 | IXGBE_RSC_CB(this)->dma = 0; |
e8171aaa | 4124 | IXGBE_RSC_CB(skb)->delay_unmap = false; |
fd3686a8 | 4125 | } |
f8212f97 AD |
4126 | skb = skb->prev; |
4127 | dev_kfree_skb(this); | |
4128 | } while (skb); | |
9a799d71 AK |
4129 | } |
4130 | if (!rx_buffer_info->page) | |
4131 | continue; | |
4f57ca6e | 4132 | if (rx_buffer_info->page_dma) { |
b6ec895e | 4133 | dma_unmap_page(dev, rx_buffer_info->page_dma, |
1b507730 | 4134 | PAGE_SIZE / 2, DMA_FROM_DEVICE); |
4f57ca6e JB |
4135 | rx_buffer_info->page_dma = 0; |
4136 | } | |
9a799d71 AK |
4137 | put_page(rx_buffer_info->page); |
4138 | rx_buffer_info->page = NULL; | |
762f4c57 | 4139 | rx_buffer_info->page_offset = 0; |
9a799d71 AK |
4140 | } |
4141 | ||
4142 | size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; | |
4143 | memset(rx_ring->rx_buffer_info, 0, size); | |
4144 | ||
4145 | /* Zero out the descriptor ring */ | |
4146 | memset(rx_ring->desc, 0, rx_ring->size); | |
4147 | ||
4148 | rx_ring->next_to_clean = 0; | |
4149 | rx_ring->next_to_use = 0; | |
9a799d71 AK |
4150 | } |
4151 | ||
4152 | /** | |
4153 | * ixgbe_clean_tx_ring - Free Tx Buffers | |
9a799d71 AK |
4154 | * @tx_ring: ring to be cleaned |
4155 | **/ | |
b6ec895e | 4156 | static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring) |
9a799d71 AK |
4157 | { |
4158 | struct ixgbe_tx_buffer *tx_buffer_info; | |
4159 | unsigned long size; | |
b6ec895e | 4160 | u16 i; |
9a799d71 | 4161 | |
84418e3b AD |
4162 | /* ring already cleared, nothing to do */ |
4163 | if (!tx_ring->tx_buffer_info) | |
4164 | return; | |
9a799d71 | 4165 | |
84418e3b | 4166 | /* Free all the Tx ring sk_buffs */ |
9a799d71 AK |
4167 | for (i = 0; i < tx_ring->count; i++) { |
4168 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
b6ec895e | 4169 | ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info); |
9a799d71 AK |
4170 | } |
4171 | ||
4172 | size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; | |
4173 | memset(tx_ring->tx_buffer_info, 0, size); | |
4174 | ||
4175 | /* Zero out the descriptor ring */ | |
4176 | memset(tx_ring->desc, 0, tx_ring->size); | |
4177 | ||
4178 | tx_ring->next_to_use = 0; | |
4179 | tx_ring->next_to_clean = 0; | |
9a799d71 AK |
4180 | } |
4181 | ||
4182 | /** | |
021230d4 | 4183 | * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues |
9a799d71 AK |
4184 | * @adapter: board private structure |
4185 | **/ | |
021230d4 | 4186 | static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter) |
9a799d71 AK |
4187 | { |
4188 | int i; | |
4189 | ||
021230d4 | 4190 | for (i = 0; i < adapter->num_rx_queues; i++) |
b6ec895e | 4191 | ixgbe_clean_rx_ring(adapter->rx_ring[i]); |
9a799d71 AK |
4192 | } |
4193 | ||
4194 | /** | |
021230d4 | 4195 | * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues |
9a799d71 AK |
4196 | * @adapter: board private structure |
4197 | **/ | |
021230d4 | 4198 | static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter) |
9a799d71 AK |
4199 | { |
4200 | int i; | |
4201 | ||
021230d4 | 4202 | for (i = 0; i < adapter->num_tx_queues; i++) |
b6ec895e | 4203 | ixgbe_clean_tx_ring(adapter->tx_ring[i]); |
9a799d71 AK |
4204 | } |
4205 | ||
4206 | void ixgbe_down(struct ixgbe_adapter *adapter) | |
4207 | { | |
4208 | struct net_device *netdev = adapter->netdev; | |
7f821875 | 4209 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 | 4210 | u32 rxctrl; |
bf29ee6c | 4211 | int i; |
b25ebfd2 | 4212 | int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; |
9a799d71 AK |
4213 | |
4214 | /* signal that we are down to the interrupt handler */ | |
4215 | set_bit(__IXGBE_DOWN, &adapter->state); | |
4216 | ||
4217 | /* disable receives */ | |
7f821875 JB |
4218 | rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); |
4219 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); | |
9a799d71 | 4220 | |
2d39d576 YZ |
4221 | /* disable all enabled rx queues */ |
4222 | for (i = 0; i < adapter->num_rx_queues; i++) | |
4223 | /* this call also flushes the previous write */ | |
4224 | ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]); | |
4225 | ||
032b4325 | 4226 | usleep_range(10000, 20000); |
9a799d71 | 4227 | |
7f821875 JB |
4228 | netif_tx_stop_all_queues(netdev); |
4229 | ||
7086400d | 4230 | /* call carrier off first to avoid false dev_watchdog timeouts */ |
c0dfb90e JF |
4231 | netif_carrier_off(netdev); |
4232 | netif_tx_disable(netdev); | |
4233 | ||
4234 | ixgbe_irq_disable(adapter); | |
4235 | ||
4236 | ixgbe_napi_disable_all(adapter); | |
4237 | ||
d034acf1 AD |
4238 | adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT | |
4239 | IXGBE_FLAG2_RESET_REQUESTED); | |
7086400d AD |
4240 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; |
4241 | ||
4242 | del_timer_sync(&adapter->service_timer); | |
4243 | ||
34cecbbf AD |
4244 | /* disable receive for all VFs and wait one second */ |
4245 | if (adapter->num_vfs) { | |
4246 | /* ping all the active vfs to let them know we are going down */ | |
4247 | ixgbe_ping_all_vfs(adapter); | |
4248 | ||
4249 | /* Disable all VFTE/VFRE TX/RX */ | |
4250 | ixgbe_disable_tx_rx(adapter); | |
4251 | ||
4252 | /* Mark all the VFs as inactive */ | |
4253 | for (i = 0 ; i < adapter->num_vfs; i++) | |
4254 | adapter->vfinfo[i].clear_to_send = 0; | |
4255 | } | |
4256 | ||
b25ebfd2 PW |
4257 | /* Cleanup the affinity_hint CPU mask memory and callback */ |
4258 | for (i = 0; i < num_q_vectors; i++) { | |
4259 | struct ixgbe_q_vector *q_vector = adapter->q_vector[i]; | |
4260 | /* clear the affinity_mask in the IRQ descriptor */ | |
4261 | irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL); | |
4262 | /* release the CPU mask memory */ | |
4263 | free_cpumask_var(q_vector->affinity_mask); | |
4264 | } | |
4265 | ||
7f821875 JB |
4266 | /* disable transmits in the hardware now that interrupts are off */ |
4267 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
bf29ee6c | 4268 | u8 reg_idx = adapter->tx_ring[i]->reg_idx; |
34cecbbf | 4269 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); |
7f821875 | 4270 | } |
34cecbbf AD |
4271 | |
4272 | /* Disable the Tx DMA engine on 82599 and X540 */ | |
bd508178 AD |
4273 | switch (hw->mac.type) { |
4274 | case ixgbe_mac_82599EB: | |
b93a2226 | 4275 | case ixgbe_mac_X540: |
88512539 | 4276 | IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, |
e8e9f696 JP |
4277 | (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) & |
4278 | ~IXGBE_DMATXCTL_TE)); | |
bd508178 AD |
4279 | break; |
4280 | default: | |
4281 | break; | |
4282 | } | |
7f821875 | 4283 | |
6f4a0e45 PL |
4284 | if (!pci_channel_offline(adapter->pdev)) |
4285 | ixgbe_reset(adapter); | |
c6ecf39a DS |
4286 | |
4287 | /* power down the optics for multispeed fiber and 82599 SFP+ fiber */ | |
4288 | if (hw->mac.ops.disable_tx_laser && | |
4289 | ((hw->phy.multispeed_fiber) || | |
9f911707 | 4290 | ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) && |
c6ecf39a DS |
4291 | (hw->mac.type == ixgbe_mac_82599EB)))) |
4292 | hw->mac.ops.disable_tx_laser(hw); | |
4293 | ||
9a799d71 AK |
4294 | ixgbe_clean_all_tx_rings(adapter); |
4295 | ixgbe_clean_all_rx_rings(adapter); | |
4296 | ||
5dd2d332 | 4297 | #ifdef CONFIG_IXGBE_DCA |
96b0e0f6 | 4298 | /* since we reset the hardware DCA settings were cleared */ |
e35ec126 | 4299 | ixgbe_setup_dca(adapter); |
96b0e0f6 | 4300 | #endif |
9a799d71 AK |
4301 | } |
4302 | ||
9a799d71 | 4303 | /** |
021230d4 AV |
4304 | * ixgbe_poll - NAPI Rx polling callback |
4305 | * @napi: structure for representing this polling device | |
4306 | * @budget: how many packets driver is allowed to clean | |
4307 | * | |
4308 | * This function is used for legacy and MSI, NAPI mode | |
9a799d71 | 4309 | **/ |
021230d4 | 4310 | static int ixgbe_poll(struct napi_struct *napi, int budget) |
9a799d71 | 4311 | { |
9a1a69ad | 4312 | struct ixgbe_q_vector *q_vector = |
e8e9f696 | 4313 | container_of(napi, struct ixgbe_q_vector, napi); |
021230d4 | 4314 | struct ixgbe_adapter *adapter = q_vector->adapter; |
9a1a69ad | 4315 | int tx_clean_complete, work_done = 0; |
9a799d71 | 4316 | |
5dd2d332 | 4317 | #ifdef CONFIG_IXGBE_DCA |
33cf09c9 AD |
4318 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) |
4319 | ixgbe_update_dca(q_vector); | |
bd0362dd JC |
4320 | #endif |
4321 | ||
4a0b9ca0 PW |
4322 | tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]); |
4323 | ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget); | |
9a799d71 | 4324 | |
9a1a69ad | 4325 | if (!tx_clean_complete) |
d2c7ddd6 DM |
4326 | work_done = budget; |
4327 | ||
53e52c72 DM |
4328 | /* If budget not fully consumed, exit the polling mode */ |
4329 | if (work_done < budget) { | |
288379f0 | 4330 | napi_complete(napi); |
f7554a2b | 4331 | if (adapter->rx_itr_setting & 1) |
f494e8fa | 4332 | ixgbe_set_itr(adapter); |
d4f80882 | 4333 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
835462fc | 4334 | ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE); |
9a799d71 | 4335 | } |
9a799d71 AK |
4336 | return work_done; |
4337 | } | |
4338 | ||
4339 | /** | |
4340 | * ixgbe_tx_timeout - Respond to a Tx Hang | |
4341 | * @netdev: network interface device structure | |
4342 | **/ | |
4343 | static void ixgbe_tx_timeout(struct net_device *netdev) | |
4344 | { | |
4345 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4346 | ||
4347 | /* Do the reset outside of interrupt context */ | |
c83c6cbd | 4348 | ixgbe_tx_timeout_reset(adapter); |
9a799d71 AK |
4349 | } |
4350 | ||
4df10466 JB |
4351 | /** |
4352 | * ixgbe_set_rss_queues: Allocate queues for RSS | |
4353 | * @adapter: board private structure to initialize | |
4354 | * | |
4355 | * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try | |
4356 | * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU. | |
4357 | * | |
4358 | **/ | |
bc97114d PWJ |
4359 | static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter) |
4360 | { | |
4361 | bool ret = false; | |
0cefafad | 4362 | struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS]; |
bc97114d PWJ |
4363 | |
4364 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { | |
0cefafad JB |
4365 | f->mask = 0xF; |
4366 | adapter->num_rx_queues = f->indices; | |
4367 | adapter->num_tx_queues = f->indices; | |
bc97114d PWJ |
4368 | ret = true; |
4369 | } else { | |
bc97114d | 4370 | ret = false; |
b9804972 JB |
4371 | } |
4372 | ||
bc97114d PWJ |
4373 | return ret; |
4374 | } | |
4375 | ||
c4cf55e5 PWJ |
4376 | /** |
4377 | * ixgbe_set_fdir_queues: Allocate queues for Flow Director | |
4378 | * @adapter: board private structure to initialize | |
4379 | * | |
4380 | * Flow Director is an advanced Rx filter, attempting to get Rx flows back | |
4381 | * to the original CPU that initiated the Tx session. This runs in addition | |
4382 | * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the | |
4383 | * Rx load across CPUs using RSS. | |
4384 | * | |
4385 | **/ | |
e8e9f696 | 4386 | static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter) |
c4cf55e5 PWJ |
4387 | { |
4388 | bool ret = false; | |
4389 | struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR]; | |
4390 | ||
4391 | f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices); | |
4392 | f_fdir->mask = 0; | |
4393 | ||
4394 | /* Flow Director must have RSS enabled */ | |
4395 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED && | |
4396 | ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || | |
4397 | (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) { | |
4398 | adapter->num_tx_queues = f_fdir->indices; | |
4399 | adapter->num_rx_queues = f_fdir->indices; | |
4400 | ret = true; | |
4401 | } else { | |
4402 | adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
4403 | adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; | |
4404 | } | |
4405 | return ret; | |
4406 | } | |
4407 | ||
0331a832 YZ |
4408 | #ifdef IXGBE_FCOE |
4409 | /** | |
4410 | * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE) | |
4411 | * @adapter: board private structure to initialize | |
4412 | * | |
4413 | * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges. | |
4414 | * The ring feature mask is not used as a mask for FCoE, as it can take any 8 | |
4415 | * rx queues out of the max number of rx queues, instead, it is used as the | |
4416 | * index of the first rx queue used by FCoE. | |
4417 | * | |
4418 | **/ | |
4419 | static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter) | |
4420 | { | |
0331a832 YZ |
4421 | struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE]; |
4422 | ||
e5b64635 JF |
4423 | if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) |
4424 | return false; | |
4425 | ||
4426 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
0331a832 | 4427 | #ifdef CONFIG_IXGBE_DCB |
e5b64635 JF |
4428 | int tc; |
4429 | struct net_device *dev = adapter->netdev; | |
4430 | ||
4431 | tc = netdev_get_prio_tc_map(dev, adapter->fcoe.up); | |
4432 | f->indices = dev->tc_to_txq[tc].count; | |
4433 | f->mask = dev->tc_to_txq[tc].offset; | |
0331a832 | 4434 | #endif |
e5b64635 JF |
4435 | } else { |
4436 | f->indices = min((int)num_online_cpus(), f->indices); | |
4437 | ||
4438 | adapter->num_rx_queues = 1; | |
4439 | adapter->num_tx_queues = 1; | |
4440 | ||
0331a832 | 4441 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { |
396e799c | 4442 | e_info(probe, "FCoE enabled with RSS\n"); |
8faa2a78 YZ |
4443 | if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) || |
4444 | (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) | |
4445 | ixgbe_set_fdir_queues(adapter); | |
4446 | else | |
4447 | ixgbe_set_rss_queues(adapter); | |
0331a832 YZ |
4448 | } |
4449 | /* adding FCoE rx rings to the end */ | |
4450 | f->mask = adapter->num_rx_queues; | |
4451 | adapter->num_rx_queues += f->indices; | |
8de8b2e6 | 4452 | adapter->num_tx_queues += f->indices; |
e5b64635 | 4453 | } |
0331a832 | 4454 | |
e5b64635 JF |
4455 | return true; |
4456 | } | |
4457 | #endif /* IXGBE_FCOE */ | |
4458 | ||
4459 | #ifdef CONFIG_IXGBE_DCB | |
4460 | static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter) | |
4461 | { | |
4462 | bool ret = false; | |
4463 | struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB]; | |
4464 | int i, q; | |
4465 | ||
4466 | if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) | |
4467 | return ret; | |
4468 | ||
4469 | f->indices = 0; | |
4470 | for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { | |
4471 | q = min((int)num_online_cpus(), MAX_TRAFFIC_CLASS); | |
4472 | f->indices += q; | |
0331a832 YZ |
4473 | } |
4474 | ||
e5b64635 JF |
4475 | f->mask = 0x7 << 3; |
4476 | adapter->num_rx_queues = f->indices; | |
4477 | adapter->num_tx_queues = f->indices; | |
4478 | ret = true; | |
4479 | ||
4480 | #ifdef IXGBE_FCOE | |
4481 | /* FCoE enabled queues require special configuration done through | |
4482 | * configure_fcoe() and others. Here we map FCoE indices onto the | |
4483 | * DCB queue pairs allowing FCoE to own configuration later. | |
4484 | */ | |
4485 | ixgbe_set_fcoe_queues(adapter); | |
4486 | #endif | |
4487 | ||
0331a832 YZ |
4488 | return ret; |
4489 | } | |
e5b64635 | 4490 | #endif |
0331a832 | 4491 | |
1cdd1ec8 GR |
4492 | /** |
4493 | * ixgbe_set_sriov_queues: Allocate queues for IOV use | |
4494 | * @adapter: board private structure to initialize | |
4495 | * | |
4496 | * IOV doesn't actually use anything, so just NAK the | |
4497 | * request for now and let the other queue routines | |
4498 | * figure out what to do. | |
4499 | */ | |
4500 | static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter) | |
4501 | { | |
4502 | return false; | |
4503 | } | |
4504 | ||
4df10466 | 4505 | /* |
25985edc | 4506 | * ixgbe_set_num_queues: Allocate queues for device, feature dependent |
4df10466 JB |
4507 | * @adapter: board private structure to initialize |
4508 | * | |
4509 | * This is the top level queue allocation routine. The order here is very | |
4510 | * important, starting with the "most" number of features turned on at once, | |
4511 | * and ending with the smallest set of features. This way large combinations | |
4512 | * can be allocated if they're turned on, and smaller combinations are the | |
4513 | * fallthrough conditions. | |
4514 | * | |
4515 | **/ | |
847f53ff | 4516 | static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter) |
bc97114d | 4517 | { |
1cdd1ec8 GR |
4518 | /* Start with base case */ |
4519 | adapter->num_rx_queues = 1; | |
4520 | adapter->num_tx_queues = 1; | |
4521 | adapter->num_rx_pools = adapter->num_rx_queues; | |
4522 | adapter->num_rx_queues_per_pool = 1; | |
4523 | ||
4524 | if (ixgbe_set_sriov_queues(adapter)) | |
847f53ff | 4525 | goto done; |
1cdd1ec8 | 4526 | |
bc97114d PWJ |
4527 | #ifdef CONFIG_IXGBE_DCB |
4528 | if (ixgbe_set_dcb_queues(adapter)) | |
af22ab1b | 4529 | goto done; |
bc97114d PWJ |
4530 | |
4531 | #endif | |
e5b64635 JF |
4532 | #ifdef IXGBE_FCOE |
4533 | if (ixgbe_set_fcoe_queues(adapter)) | |
4534 | goto done; | |
4535 | ||
4536 | #endif /* IXGBE_FCOE */ | |
c4cf55e5 PWJ |
4537 | if (ixgbe_set_fdir_queues(adapter)) |
4538 | goto done; | |
4539 | ||
bc97114d | 4540 | if (ixgbe_set_rss_queues(adapter)) |
af22ab1b WF |
4541 | goto done; |
4542 | ||
4543 | /* fallback to base case */ | |
4544 | adapter->num_rx_queues = 1; | |
4545 | adapter->num_tx_queues = 1; | |
4546 | ||
4547 | done: | |
847f53ff | 4548 | /* Notify the stack of the (possibly) reduced queue counts. */ |
f0796d5c | 4549 | netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues); |
847f53ff BH |
4550 | return netif_set_real_num_rx_queues(adapter->netdev, |
4551 | adapter->num_rx_queues); | |
b9804972 JB |
4552 | } |
4553 | ||
021230d4 | 4554 | static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter, |
e8e9f696 | 4555 | int vectors) |
021230d4 AV |
4556 | { |
4557 | int err, vector_threshold; | |
4558 | ||
4559 | /* We'll want at least 3 (vector_threshold): | |
4560 | * 1) TxQ[0] Cleanup | |
4561 | * 2) RxQ[0] Cleanup | |
4562 | * 3) Other (Link Status Change, etc.) | |
4563 | * 4) TCP Timer (optional) | |
4564 | */ | |
4565 | vector_threshold = MIN_MSIX_COUNT; | |
4566 | ||
4567 | /* The more we get, the more we will assign to Tx/Rx Cleanup | |
4568 | * for the separate queues...where Rx Cleanup >= Tx Cleanup. | |
4569 | * Right now, we simply care about how many we'll get; we'll | |
4570 | * set them up later while requesting irq's. | |
4571 | */ | |
4572 | while (vectors >= vector_threshold) { | |
4573 | err = pci_enable_msix(adapter->pdev, adapter->msix_entries, | |
e8e9f696 | 4574 | vectors); |
021230d4 AV |
4575 | if (!err) /* Success in acquiring all requested vectors. */ |
4576 | break; | |
4577 | else if (err < 0) | |
4578 | vectors = 0; /* Nasty failure, quit now */ | |
4579 | else /* err == number of vectors we should try again with */ | |
4580 | vectors = err; | |
4581 | } | |
4582 | ||
4583 | if (vectors < vector_threshold) { | |
4584 | /* Can't allocate enough MSI-X interrupts? Oh well. | |
4585 | * This just means we'll go with either a single MSI | |
4586 | * vector or fall back to legacy interrupts. | |
4587 | */ | |
849c4542 ET |
4588 | netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev, |
4589 | "Unable to allocate MSI-X interrupts\n"); | |
021230d4 AV |
4590 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; |
4591 | kfree(adapter->msix_entries); | |
4592 | adapter->msix_entries = NULL; | |
021230d4 AV |
4593 | } else { |
4594 | adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */ | |
eb7f139c PWJ |
4595 | /* |
4596 | * Adjust for only the vectors we'll use, which is minimum | |
4597 | * of max_msix_q_vectors + NON_Q_VECTORS, or the number of | |
4598 | * vectors we were allocated. | |
4599 | */ | |
4600 | adapter->num_msix_vectors = min(vectors, | |
e8e9f696 | 4601 | adapter->max_msix_q_vectors + NON_Q_VECTORS); |
021230d4 AV |
4602 | } |
4603 | } | |
4604 | ||
021230d4 | 4605 | /** |
bc97114d | 4606 | * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS |
021230d4 AV |
4607 | * @adapter: board private structure to initialize |
4608 | * | |
bc97114d PWJ |
4609 | * Cache the descriptor ring offsets for RSS to the assigned rings. |
4610 | * | |
021230d4 | 4611 | **/ |
bc97114d | 4612 | static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter) |
021230d4 | 4613 | { |
bc97114d | 4614 | int i; |
bc97114d | 4615 | |
9d6b758f AD |
4616 | if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) |
4617 | return false; | |
bc97114d | 4618 | |
9d6b758f AD |
4619 | for (i = 0; i < adapter->num_rx_queues; i++) |
4620 | adapter->rx_ring[i]->reg_idx = i; | |
4621 | for (i = 0; i < adapter->num_tx_queues; i++) | |
4622 | adapter->tx_ring[i]->reg_idx = i; | |
4623 | ||
4624 | return true; | |
bc97114d PWJ |
4625 | } |
4626 | ||
4627 | #ifdef CONFIG_IXGBE_DCB | |
e5b64635 JF |
4628 | |
4629 | /* ixgbe_get_first_reg_idx - Return first register index associated with ring */ | |
b32c8dcc JF |
4630 | static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc, |
4631 | unsigned int *tx, unsigned int *rx) | |
e5b64635 JF |
4632 | { |
4633 | struct net_device *dev = adapter->netdev; | |
4634 | struct ixgbe_hw *hw = &adapter->hw; | |
4635 | u8 num_tcs = netdev_get_num_tc(dev); | |
4636 | ||
4637 | *tx = 0; | |
4638 | *rx = 0; | |
4639 | ||
4640 | switch (hw->mac.type) { | |
4641 | case ixgbe_mac_82598EB: | |
4642 | *tx = tc << 3; | |
4643 | *rx = tc << 2; | |
4644 | break; | |
4645 | case ixgbe_mac_82599EB: | |
4646 | case ixgbe_mac_X540: | |
4647 | if (num_tcs == 8) { | |
4648 | if (tc < 3) { | |
4649 | *tx = tc << 5; | |
4650 | *rx = tc << 4; | |
4651 | } else if (tc < 5) { | |
4652 | *tx = ((tc + 2) << 4); | |
4653 | *rx = tc << 4; | |
4654 | } else if (tc < num_tcs) { | |
4655 | *tx = ((tc + 8) << 3); | |
4656 | *rx = tc << 4; | |
4657 | } | |
4658 | } else if (num_tcs == 4) { | |
4659 | *rx = tc << 5; | |
4660 | switch (tc) { | |
4661 | case 0: | |
4662 | *tx = 0; | |
4663 | break; | |
4664 | case 1: | |
4665 | *tx = 64; | |
4666 | break; | |
4667 | case 2: | |
4668 | *tx = 96; | |
4669 | break; | |
4670 | case 3: | |
4671 | *tx = 112; | |
4672 | break; | |
4673 | default: | |
4674 | break; | |
4675 | } | |
4676 | } | |
4677 | break; | |
4678 | default: | |
4679 | break; | |
4680 | } | |
4681 | } | |
4682 | ||
4683 | #define IXGBE_MAX_Q_PER_TC (IXGBE_MAX_DCB_INDICES / MAX_TRAFFIC_CLASS) | |
4684 | ||
4685 | /* ixgbe_setup_tc - routine to configure net_device for multiple traffic | |
4686 | * classes. | |
4687 | * | |
4688 | * @netdev: net device to configure | |
4689 | * @tc: number of traffic classes to enable | |
4690 | */ | |
4691 | int ixgbe_setup_tc(struct net_device *dev, u8 tc) | |
4692 | { | |
4693 | int i; | |
4694 | unsigned int q, offset = 0; | |
4695 | ||
4696 | if (!tc) { | |
4697 | netdev_reset_tc(dev); | |
4698 | } else { | |
24095aa3 JF |
4699 | struct ixgbe_adapter *adapter = netdev_priv(dev); |
4700 | ||
4701 | /* Hardware supports up to 8 traffic classes */ | |
4702 | if (tc > MAX_TRAFFIC_CLASS || netdev_set_num_tc(dev, tc)) | |
e5b64635 JF |
4703 | return -EINVAL; |
4704 | ||
4705 | /* Partition Tx queues evenly amongst traffic classes */ | |
4706 | for (i = 0; i < tc; i++) { | |
4707 | q = min((int)num_online_cpus(), IXGBE_MAX_Q_PER_TC); | |
4708 | netdev_set_prio_tc_map(dev, i, i); | |
4709 | netdev_set_tc_queue(dev, i, q, offset); | |
4710 | offset += q; | |
4711 | } | |
24095aa3 JF |
4712 | |
4713 | /* This enables multiple traffic class support in the hardware | |
4714 | * which defaults to strict priority transmission by default. | |
4715 | * If traffic classes are already enabled perhaps through DCB | |
4716 | * code path then existing configuration will be used. | |
4717 | */ | |
4718 | if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) && | |
4719 | dev->dcbnl_ops && dev->dcbnl_ops->setdcbx) { | |
4720 | struct ieee_ets ets = { | |
4721 | .prio_tc = {0, 1, 2, 3, 4, 5, 6, 7}, | |
4722 | }; | |
4723 | u8 mode = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_IEEE; | |
4724 | ||
4725 | dev->dcbnl_ops->setdcbx(dev, mode); | |
4726 | dev->dcbnl_ops->ieee_setets(dev, &ets); | |
4727 | } | |
e5b64635 JF |
4728 | } |
4729 | return 0; | |
4730 | } | |
4731 | ||
bc97114d PWJ |
4732 | /** |
4733 | * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB | |
4734 | * @adapter: board private structure to initialize | |
4735 | * | |
4736 | * Cache the descriptor ring offsets for DCB to the assigned rings. | |
4737 | * | |
4738 | **/ | |
4739 | static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter) | |
4740 | { | |
e5b64635 JF |
4741 | struct net_device *dev = adapter->netdev; |
4742 | int i, j, k; | |
4743 | u8 num_tcs = netdev_get_num_tc(dev); | |
bc97114d | 4744 | |
bd508178 AD |
4745 | if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) |
4746 | return false; | |
f92ef202 | 4747 | |
e5b64635 JF |
4748 | for (i = 0, k = 0; i < num_tcs; i++) { |
4749 | unsigned int tx_s, rx_s; | |
4750 | u16 count = dev->tc_to_txq[i].count; | |
4751 | ||
4752 | ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s); | |
4753 | for (j = 0; j < count; j++, k++) { | |
4754 | adapter->tx_ring[k]->reg_idx = tx_s + j; | |
4755 | adapter->rx_ring[k]->reg_idx = rx_s + j; | |
4756 | adapter->tx_ring[k]->dcb_tc = i; | |
4757 | adapter->rx_ring[k]->dcb_tc = i; | |
021230d4 | 4758 | } |
021230d4 | 4759 | } |
e5b64635 JF |
4760 | |
4761 | return true; | |
bc97114d PWJ |
4762 | } |
4763 | #endif | |
4764 | ||
c4cf55e5 PWJ |
4765 | /** |
4766 | * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director | |
4767 | * @adapter: board private structure to initialize | |
4768 | * | |
4769 | * Cache the descriptor ring offsets for Flow Director to the assigned rings. | |
4770 | * | |
4771 | **/ | |
e8e9f696 | 4772 | static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter) |
c4cf55e5 PWJ |
4773 | { |
4774 | int i; | |
4775 | bool ret = false; | |
4776 | ||
4777 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED && | |
4778 | ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) || | |
4779 | (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) { | |
4780 | for (i = 0; i < adapter->num_rx_queues; i++) | |
4a0b9ca0 | 4781 | adapter->rx_ring[i]->reg_idx = i; |
c4cf55e5 | 4782 | for (i = 0; i < adapter->num_tx_queues; i++) |
4a0b9ca0 | 4783 | adapter->tx_ring[i]->reg_idx = i; |
c4cf55e5 PWJ |
4784 | ret = true; |
4785 | } | |
4786 | ||
4787 | return ret; | |
4788 | } | |
4789 | ||
0331a832 YZ |
4790 | #ifdef IXGBE_FCOE |
4791 | /** | |
4792 | * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE | |
4793 | * @adapter: board private structure to initialize | |
4794 | * | |
4795 | * Cache the descriptor ring offsets for FCoE mode to the assigned rings. | |
4796 | * | |
4797 | */ | |
4798 | static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter) | |
4799 | { | |
0331a832 | 4800 | struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE]; |
bf29ee6c AD |
4801 | int i; |
4802 | u8 fcoe_rx_i = 0, fcoe_tx_i = 0; | |
4803 | ||
4804 | if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) | |
4805 | return false; | |
0331a832 | 4806 | |
bf29ee6c AD |
4807 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { |
4808 | if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) || | |
4809 | (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) | |
4810 | ixgbe_cache_ring_fdir(adapter); | |
4811 | else | |
4812 | ixgbe_cache_ring_rss(adapter); | |
8faa2a78 | 4813 | |
bf29ee6c AD |
4814 | fcoe_rx_i = f->mask; |
4815 | fcoe_tx_i = f->mask; | |
0331a832 | 4816 | } |
bf29ee6c AD |
4817 | for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) { |
4818 | adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i; | |
4819 | adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i; | |
4820 | } | |
4821 | return true; | |
0331a832 YZ |
4822 | } |
4823 | ||
4824 | #endif /* IXGBE_FCOE */ | |
1cdd1ec8 GR |
4825 | /** |
4826 | * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov | |
4827 | * @adapter: board private structure to initialize | |
4828 | * | |
4829 | * SR-IOV doesn't use any descriptor rings but changes the default if | |
4830 | * no other mapping is used. | |
4831 | * | |
4832 | */ | |
4833 | static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter) | |
4834 | { | |
4a0b9ca0 PW |
4835 | adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2; |
4836 | adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2; | |
1cdd1ec8 GR |
4837 | if (adapter->num_vfs) |
4838 | return true; | |
4839 | else | |
4840 | return false; | |
4841 | } | |
4842 | ||
bc97114d PWJ |
4843 | /** |
4844 | * ixgbe_cache_ring_register - Descriptor ring to register mapping | |
4845 | * @adapter: board private structure to initialize | |
4846 | * | |
4847 | * Once we know the feature-set enabled for the device, we'll cache | |
4848 | * the register offset the descriptor ring is assigned to. | |
4849 | * | |
4850 | * Note, the order the various feature calls is important. It must start with | |
4851 | * the "most" features enabled at the same time, then trickle down to the | |
4852 | * least amount of features turned on at once. | |
4853 | **/ | |
4854 | static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter) | |
4855 | { | |
4856 | /* start with default case */ | |
4a0b9ca0 PW |
4857 | adapter->rx_ring[0]->reg_idx = 0; |
4858 | adapter->tx_ring[0]->reg_idx = 0; | |
bc97114d | 4859 | |
1cdd1ec8 GR |
4860 | if (ixgbe_cache_ring_sriov(adapter)) |
4861 | return; | |
4862 | ||
e5b64635 JF |
4863 | #ifdef CONFIG_IXGBE_DCB |
4864 | if (ixgbe_cache_ring_dcb(adapter)) | |
4865 | return; | |
4866 | #endif | |
4867 | ||
0331a832 YZ |
4868 | #ifdef IXGBE_FCOE |
4869 | if (ixgbe_cache_ring_fcoe(adapter)) | |
4870 | return; | |
0331a832 | 4871 | #endif /* IXGBE_FCOE */ |
bc97114d | 4872 | |
c4cf55e5 PWJ |
4873 | if (ixgbe_cache_ring_fdir(adapter)) |
4874 | return; | |
4875 | ||
bc97114d PWJ |
4876 | if (ixgbe_cache_ring_rss(adapter)) |
4877 | return; | |
021230d4 AV |
4878 | } |
4879 | ||
9a799d71 AK |
4880 | /** |
4881 | * ixgbe_alloc_queues - Allocate memory for all rings | |
4882 | * @adapter: board private structure to initialize | |
4883 | * | |
4884 | * We allocate one ring per queue at run-time since we don't know the | |
4df10466 JB |
4885 | * number of queues at compile-time. The polling_netdev array is |
4886 | * intended for Multiqueue, but should work fine with a single queue. | |
9a799d71 | 4887 | **/ |
2f90b865 | 4888 | static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter) |
9a799d71 | 4889 | { |
e2ddeba9 | 4890 | int rx = 0, tx = 0, nid = adapter->node; |
9a799d71 | 4891 | |
e2ddeba9 ED |
4892 | if (nid < 0 || !node_online(nid)) |
4893 | nid = first_online_node; | |
4894 | ||
4895 | for (; tx < adapter->num_tx_queues; tx++) { | |
4896 | struct ixgbe_ring *ring; | |
4897 | ||
4898 | ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid); | |
4a0b9ca0 | 4899 | if (!ring) |
e2ddeba9 | 4900 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); |
4a0b9ca0 | 4901 | if (!ring) |
e2ddeba9 | 4902 | goto err_allocation; |
4a0b9ca0 | 4903 | ring->count = adapter->tx_ring_count; |
e2ddeba9 ED |
4904 | ring->queue_index = tx; |
4905 | ring->numa_node = nid; | |
b6ec895e | 4906 | ring->dev = &adapter->pdev->dev; |
fc77dc3c | 4907 | ring->netdev = adapter->netdev; |
4a0b9ca0 | 4908 | |
e2ddeba9 | 4909 | adapter->tx_ring[tx] = ring; |
021230d4 | 4910 | } |
b9804972 | 4911 | |
e2ddeba9 ED |
4912 | for (; rx < adapter->num_rx_queues; rx++) { |
4913 | struct ixgbe_ring *ring; | |
4a0b9ca0 | 4914 | |
e2ddeba9 | 4915 | ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid); |
4a0b9ca0 | 4916 | if (!ring) |
e2ddeba9 | 4917 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); |
4a0b9ca0 | 4918 | if (!ring) |
e2ddeba9 ED |
4919 | goto err_allocation; |
4920 | ring->count = adapter->rx_ring_count; | |
4921 | ring->queue_index = rx; | |
4922 | ring->numa_node = nid; | |
b6ec895e | 4923 | ring->dev = &adapter->pdev->dev; |
fc77dc3c | 4924 | ring->netdev = adapter->netdev; |
4a0b9ca0 | 4925 | |
e2ddeba9 | 4926 | adapter->rx_ring[rx] = ring; |
021230d4 AV |
4927 | } |
4928 | ||
4929 | ixgbe_cache_ring_register(adapter); | |
4930 | ||
4931 | return 0; | |
4932 | ||
e2ddeba9 ED |
4933 | err_allocation: |
4934 | while (tx) | |
4935 | kfree(adapter->tx_ring[--tx]); | |
4936 | ||
4937 | while (rx) | |
4938 | kfree(adapter->rx_ring[--rx]); | |
021230d4 AV |
4939 | return -ENOMEM; |
4940 | } | |
4941 | ||
4942 | /** | |
4943 | * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported | |
4944 | * @adapter: board private structure to initialize | |
4945 | * | |
4946 | * Attempt to configure the interrupts using the best available | |
4947 | * capabilities of the hardware and the kernel. | |
4948 | **/ | |
feea6a57 | 4949 | static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter) |
021230d4 | 4950 | { |
8be0e467 | 4951 | struct ixgbe_hw *hw = &adapter->hw; |
021230d4 AV |
4952 | int err = 0; |
4953 | int vector, v_budget; | |
4954 | ||
4955 | /* | |
4956 | * It's easy to be greedy for MSI-X vectors, but it really | |
4957 | * doesn't do us much good if we have a lot more vectors | |
4958 | * than CPU's. So let's be conservative and only ask for | |
342bde1b | 4959 | * (roughly) the same number of vectors as there are CPU's. |
021230d4 AV |
4960 | */ |
4961 | v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues, | |
e8e9f696 | 4962 | (int)num_online_cpus()) + NON_Q_VECTORS; |
021230d4 AV |
4963 | |
4964 | /* | |
4965 | * At the same time, hardware can only support a maximum of | |
8be0e467 PW |
4966 | * hw.mac->max_msix_vectors vectors. With features |
4967 | * such as RSS and VMDq, we can easily surpass the number of Rx and Tx | |
4968 | * descriptor queues supported by our device. Thus, we cap it off in | |
4969 | * those rare cases where the cpu count also exceeds our vector limit. | |
021230d4 | 4970 | */ |
8be0e467 | 4971 | v_budget = min(v_budget, (int)hw->mac.max_msix_vectors); |
021230d4 AV |
4972 | |
4973 | /* A failure in MSI-X entry allocation isn't fatal, but it does | |
4974 | * mean we disable MSI-X capabilities of the adapter. */ | |
4975 | adapter->msix_entries = kcalloc(v_budget, | |
e8e9f696 | 4976 | sizeof(struct msix_entry), GFP_KERNEL); |
7a921c93 AD |
4977 | if (adapter->msix_entries) { |
4978 | for (vector = 0; vector < v_budget; vector++) | |
4979 | adapter->msix_entries[vector].entry = vector; | |
021230d4 | 4980 | |
7a921c93 | 4981 | ixgbe_acquire_msix_vectors(adapter, v_budget); |
021230d4 | 4982 | |
7a921c93 AD |
4983 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
4984 | goto out; | |
4985 | } | |
26d27844 | 4986 | |
7a921c93 AD |
4987 | adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; |
4988 | adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED; | |
45b9f509 AD |
4989 | if (adapter->flags & (IXGBE_FLAG_FDIR_HASH_CAPABLE | |
4990 | IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) { | |
4991 | e_err(probe, | |
4992 | "Flow Director is not supported while multiple " | |
4993 | "queues are disabled. Disabling Flow Director\n"); | |
4994 | } | |
c4cf55e5 PWJ |
4995 | adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; |
4996 | adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; | |
4997 | adapter->atr_sample_rate = 0; | |
1cdd1ec8 GR |
4998 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) |
4999 | ixgbe_disable_sriov(adapter); | |
5000 | ||
847f53ff BH |
5001 | err = ixgbe_set_num_queues(adapter); |
5002 | if (err) | |
5003 | return err; | |
021230d4 | 5004 | |
021230d4 AV |
5005 | err = pci_enable_msi(adapter->pdev); |
5006 | if (!err) { | |
5007 | adapter->flags |= IXGBE_FLAG_MSI_ENABLED; | |
5008 | } else { | |
849c4542 ET |
5009 | netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev, |
5010 | "Unable to allocate MSI interrupt, " | |
5011 | "falling back to legacy. Error: %d\n", err); | |
021230d4 AV |
5012 | /* reset err */ |
5013 | err = 0; | |
5014 | } | |
5015 | ||
5016 | out: | |
021230d4 AV |
5017 | return err; |
5018 | } | |
5019 | ||
7a921c93 AD |
5020 | /** |
5021 | * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors | |
5022 | * @adapter: board private structure to initialize | |
5023 | * | |
5024 | * We allocate one q_vector per queue interrupt. If allocation fails we | |
5025 | * return -ENOMEM. | |
5026 | **/ | |
5027 | static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter) | |
5028 | { | |
5029 | int q_idx, num_q_vectors; | |
5030 | struct ixgbe_q_vector *q_vector; | |
7a921c93 AD |
5031 | int (*poll)(struct napi_struct *, int); |
5032 | ||
5033 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
5034 | num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
91281fd3 | 5035 | poll = &ixgbe_clean_rxtx_many; |
7a921c93 AD |
5036 | } else { |
5037 | num_q_vectors = 1; | |
7a921c93 AD |
5038 | poll = &ixgbe_poll; |
5039 | } | |
5040 | ||
5041 | for (q_idx = 0; q_idx < num_q_vectors; q_idx++) { | |
1a6c14a2 | 5042 | q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector), |
e8e9f696 | 5043 | GFP_KERNEL, adapter->node); |
1a6c14a2 JB |
5044 | if (!q_vector) |
5045 | q_vector = kzalloc(sizeof(struct ixgbe_q_vector), | |
e8e9f696 | 5046 | GFP_KERNEL); |
7a921c93 AD |
5047 | if (!q_vector) |
5048 | goto err_out; | |
5049 | q_vector->adapter = adapter; | |
f7554a2b NS |
5050 | if (q_vector->txr_count && !q_vector->rxr_count) |
5051 | q_vector->eitr = adapter->tx_eitr_param; | |
5052 | else | |
5053 | q_vector->eitr = adapter->rx_eitr_param; | |
fe49f04a | 5054 | q_vector->v_idx = q_idx; |
91281fd3 | 5055 | netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64); |
7a921c93 AD |
5056 | adapter->q_vector[q_idx] = q_vector; |
5057 | } | |
5058 | ||
5059 | return 0; | |
5060 | ||
5061 | err_out: | |
5062 | while (q_idx) { | |
5063 | q_idx--; | |
5064 | q_vector = adapter->q_vector[q_idx]; | |
5065 | netif_napi_del(&q_vector->napi); | |
5066 | kfree(q_vector); | |
5067 | adapter->q_vector[q_idx] = NULL; | |
5068 | } | |
5069 | return -ENOMEM; | |
5070 | } | |
5071 | ||
5072 | /** | |
5073 | * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors | |
5074 | * @adapter: board private structure to initialize | |
5075 | * | |
5076 | * This function frees the memory allocated to the q_vectors. In addition if | |
5077 | * NAPI is enabled it will delete any references to the NAPI struct prior | |
5078 | * to freeing the q_vector. | |
5079 | **/ | |
5080 | static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter) | |
5081 | { | |
5082 | int q_idx, num_q_vectors; | |
7a921c93 | 5083 | |
91281fd3 | 5084 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
7a921c93 | 5085 | num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; |
91281fd3 | 5086 | else |
7a921c93 | 5087 | num_q_vectors = 1; |
7a921c93 AD |
5088 | |
5089 | for (q_idx = 0; q_idx < num_q_vectors; q_idx++) { | |
5090 | struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx]; | |
7a921c93 | 5091 | adapter->q_vector[q_idx] = NULL; |
91281fd3 | 5092 | netif_napi_del(&q_vector->napi); |
7a921c93 AD |
5093 | kfree(q_vector); |
5094 | } | |
5095 | } | |
5096 | ||
7b25cdba | 5097 | static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter) |
021230d4 AV |
5098 | { |
5099 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
5100 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; | |
5101 | pci_disable_msix(adapter->pdev); | |
5102 | kfree(adapter->msix_entries); | |
5103 | adapter->msix_entries = NULL; | |
5104 | } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) { | |
5105 | adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED; | |
5106 | pci_disable_msi(adapter->pdev); | |
5107 | } | |
021230d4 AV |
5108 | } |
5109 | ||
5110 | /** | |
5111 | * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme | |
5112 | * @adapter: board private structure to initialize | |
5113 | * | |
5114 | * We determine which interrupt scheme to use based on... | |
5115 | * - Kernel support (MSI, MSI-X) | |
5116 | * - which can be user-defined (via MODULE_PARAM) | |
5117 | * - Hardware queue count (num_*_queues) | |
5118 | * - defined by miscellaneous hardware support/features (RSS, etc.) | |
5119 | **/ | |
2f90b865 | 5120 | int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter) |
021230d4 AV |
5121 | { |
5122 | int err; | |
5123 | ||
5124 | /* Number of supported queues */ | |
847f53ff BH |
5125 | err = ixgbe_set_num_queues(adapter); |
5126 | if (err) | |
5127 | return err; | |
021230d4 | 5128 | |
021230d4 AV |
5129 | err = ixgbe_set_interrupt_capability(adapter); |
5130 | if (err) { | |
849c4542 | 5131 | e_dev_err("Unable to setup interrupt capabilities\n"); |
021230d4 | 5132 | goto err_set_interrupt; |
9a799d71 AK |
5133 | } |
5134 | ||
7a921c93 AD |
5135 | err = ixgbe_alloc_q_vectors(adapter); |
5136 | if (err) { | |
849c4542 | 5137 | e_dev_err("Unable to allocate memory for queue vectors\n"); |
7a921c93 AD |
5138 | goto err_alloc_q_vectors; |
5139 | } | |
5140 | ||
5141 | err = ixgbe_alloc_queues(adapter); | |
5142 | if (err) { | |
849c4542 | 5143 | e_dev_err("Unable to allocate memory for queues\n"); |
7a921c93 AD |
5144 | goto err_alloc_queues; |
5145 | } | |
5146 | ||
849c4542 | 5147 | e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n", |
396e799c ET |
5148 | (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled", |
5149 | adapter->num_rx_queues, adapter->num_tx_queues); | |
021230d4 AV |
5150 | |
5151 | set_bit(__IXGBE_DOWN, &adapter->state); | |
5152 | ||
9a799d71 | 5153 | return 0; |
021230d4 | 5154 | |
7a921c93 AD |
5155 | err_alloc_queues: |
5156 | ixgbe_free_q_vectors(adapter); | |
5157 | err_alloc_q_vectors: | |
5158 | ixgbe_reset_interrupt_capability(adapter); | |
021230d4 | 5159 | err_set_interrupt: |
7a921c93 AD |
5160 | return err; |
5161 | } | |
5162 | ||
5163 | /** | |
5164 | * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings | |
5165 | * @adapter: board private structure to clear interrupt scheme on | |
5166 | * | |
5167 | * We go through and clear interrupt specific resources and reset the structure | |
5168 | * to pre-load conditions | |
5169 | **/ | |
5170 | void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter) | |
5171 | { | |
4a0b9ca0 PW |
5172 | int i; |
5173 | ||
5174 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
5175 | kfree(adapter->tx_ring[i]); | |
5176 | adapter->tx_ring[i] = NULL; | |
5177 | } | |
5178 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
1a51502b ED |
5179 | struct ixgbe_ring *ring = adapter->rx_ring[i]; |
5180 | ||
5181 | /* ixgbe_get_stats64() might access this ring, we must wait | |
5182 | * a grace period before freeing it. | |
5183 | */ | |
bcec8b65 | 5184 | kfree_rcu(ring, rcu); |
4a0b9ca0 PW |
5185 | adapter->rx_ring[i] = NULL; |
5186 | } | |
7a921c93 | 5187 | |
b8eb3a10 DS |
5188 | adapter->num_tx_queues = 0; |
5189 | adapter->num_rx_queues = 0; | |
5190 | ||
7a921c93 AD |
5191 | ixgbe_free_q_vectors(adapter); |
5192 | ixgbe_reset_interrupt_capability(adapter); | |
9a799d71 AK |
5193 | } |
5194 | ||
5195 | /** | |
5196 | * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter) | |
5197 | * @adapter: board private structure to initialize | |
5198 | * | |
5199 | * ixgbe_sw_init initializes the Adapter private data structure. | |
5200 | * Fields are initialized based on PCI device information and | |
5201 | * OS network device settings (MTU size). | |
5202 | **/ | |
5203 | static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter) | |
5204 | { | |
5205 | struct ixgbe_hw *hw = &adapter->hw; | |
5206 | struct pci_dev *pdev = adapter->pdev; | |
9a713e7c | 5207 | struct net_device *dev = adapter->netdev; |
021230d4 | 5208 | unsigned int rss; |
7a6b6f51 | 5209 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
5210 | int j; |
5211 | struct tc_configuration *tc; | |
5212 | #endif | |
16b61beb | 5213 | int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN; |
021230d4 | 5214 | |
c44ade9e JB |
5215 | /* PCI config space info */ |
5216 | ||
5217 | hw->vendor_id = pdev->vendor; | |
5218 | hw->device_id = pdev->device; | |
5219 | hw->revision_id = pdev->revision; | |
5220 | hw->subsystem_vendor_id = pdev->subsystem_vendor; | |
5221 | hw->subsystem_device_id = pdev->subsystem_device; | |
5222 | ||
021230d4 AV |
5223 | /* Set capability flags */ |
5224 | rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus()); | |
5225 | adapter->ring_feature[RING_F_RSS].indices = rss; | |
5226 | adapter->flags |= IXGBE_FLAG_RSS_ENABLED; | |
2f90b865 | 5227 | adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES; |
bd508178 AD |
5228 | switch (hw->mac.type) { |
5229 | case ixgbe_mac_82598EB: | |
bf069c97 DS |
5230 | if (hw->device_id == IXGBE_DEV_ID_82598AT) |
5231 | adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE; | |
e8e26350 | 5232 | adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598; |
bd508178 AD |
5233 | break; |
5234 | case ixgbe_mac_82599EB: | |
b93a2226 | 5235 | case ixgbe_mac_X540: |
e8e26350 | 5236 | adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599; |
0c19d6af PWJ |
5237 | adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE; |
5238 | adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; | |
119fc60a MC |
5239 | if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM) |
5240 | adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; | |
45b9f509 AD |
5241 | /* n-tuple support exists, always init our spinlock */ |
5242 | spin_lock_init(&adapter->fdir_perfect_lock); | |
5243 | /* Flow Director hash filters enabled */ | |
5244 | adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
5245 | adapter->atr_sample_rate = 20; | |
c4cf55e5 | 5246 | adapter->ring_feature[RING_F_FDIR].indices = |
e8e9f696 | 5247 | IXGBE_MAX_FDIR_INDICES; |
c4cf55e5 | 5248 | adapter->fdir_pballoc = 0; |
eacd73f7 | 5249 | #ifdef IXGBE_FCOE |
0d551589 YZ |
5250 | adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE; |
5251 | adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; | |
5252 | adapter->ring_feature[RING_F_FCOE].indices = 0; | |
61a0f421 | 5253 | #ifdef CONFIG_IXGBE_DCB |
6ee16520 YZ |
5254 | /* Default traffic class to use for FCoE */ |
5255 | adapter->fcoe.tc = IXGBE_FCOE_DEFTC; | |
56075a98 | 5256 | adapter->fcoe.up = IXGBE_FCOE_DEFTC; |
61a0f421 | 5257 | #endif |
eacd73f7 | 5258 | #endif /* IXGBE_FCOE */ |
bd508178 AD |
5259 | break; |
5260 | default: | |
5261 | break; | |
f8212f97 | 5262 | } |
2f90b865 | 5263 | |
7a6b6f51 | 5264 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
5265 | /* Configure DCB traffic classes */ |
5266 | for (j = 0; j < MAX_TRAFFIC_CLASS; j++) { | |
5267 | tc = &adapter->dcb_cfg.tc_config[j]; | |
5268 | tc->path[DCB_TX_CONFIG].bwg_id = 0; | |
5269 | tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1); | |
5270 | tc->path[DCB_RX_CONFIG].bwg_id = 0; | |
5271 | tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1); | |
5272 | tc->dcb_pfc = pfc_disabled; | |
5273 | } | |
5274 | adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100; | |
5275 | adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100; | |
264857b8 | 5276 | adapter->dcb_cfg.pfc_mode_enable = false; |
2f90b865 | 5277 | adapter->dcb_set_bitmap = 0x00; |
3032309b | 5278 | adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE; |
2f90b865 | 5279 | ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg, |
e5b64635 | 5280 | MAX_TRAFFIC_CLASS); |
2f90b865 AD |
5281 | |
5282 | #endif | |
9a799d71 AK |
5283 | |
5284 | /* default flow control settings */ | |
cd7664f6 | 5285 | hw->fc.requested_mode = ixgbe_fc_full; |
71fd570b | 5286 | hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */ |
264857b8 PWJ |
5287 | #ifdef CONFIG_DCB |
5288 | adapter->last_lfc_mode = hw->fc.current_mode; | |
5289 | #endif | |
16b61beb JF |
5290 | hw->fc.high_water = FC_HIGH_WATER(max_frame); |
5291 | hw->fc.low_water = FC_LOW_WATER(max_frame); | |
2b9ade93 JB |
5292 | hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE; |
5293 | hw->fc.send_xon = true; | |
71fd570b | 5294 | hw->fc.disable_fc_autoneg = false; |
9a799d71 | 5295 | |
30efa5a3 | 5296 | /* enable itr by default in dynamic mode */ |
f7554a2b NS |
5297 | adapter->rx_itr_setting = 1; |
5298 | adapter->rx_eitr_param = 20000; | |
5299 | adapter->tx_itr_setting = 1; | |
5300 | adapter->tx_eitr_param = 10000; | |
30efa5a3 JB |
5301 | |
5302 | /* set defaults for eitr in MegaBytes */ | |
5303 | adapter->eitr_low = 10; | |
5304 | adapter->eitr_high = 20; | |
5305 | ||
5306 | /* set default ring sizes */ | |
5307 | adapter->tx_ring_count = IXGBE_DEFAULT_TXD; | |
5308 | adapter->rx_ring_count = IXGBE_DEFAULT_RXD; | |
5309 | ||
9a799d71 | 5310 | /* initialize eeprom parameters */ |
c44ade9e | 5311 | if (ixgbe_init_eeprom_params_generic(hw)) { |
849c4542 | 5312 | e_dev_err("EEPROM initialization failed\n"); |
9a799d71 AK |
5313 | return -EIO; |
5314 | } | |
5315 | ||
021230d4 | 5316 | /* enable rx csum by default */ |
9a799d71 AK |
5317 | adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED; |
5318 | ||
1a6c14a2 JB |
5319 | /* get assigned NUMA node */ |
5320 | adapter->node = dev_to_node(&pdev->dev); | |
5321 | ||
9a799d71 AK |
5322 | set_bit(__IXGBE_DOWN, &adapter->state); |
5323 | ||
5324 | return 0; | |
5325 | } | |
5326 | ||
5327 | /** | |
5328 | * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors) | |
3a581073 | 5329 | * @tx_ring: tx descriptor ring (for a specific queue) to setup |
9a799d71 AK |
5330 | * |
5331 | * Return 0 on success, negative on failure | |
5332 | **/ | |
b6ec895e | 5333 | int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring) |
9a799d71 | 5334 | { |
b6ec895e | 5335 | struct device *dev = tx_ring->dev; |
9a799d71 AK |
5336 | int size; |
5337 | ||
3a581073 | 5338 | size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; |
89bf67f1 | 5339 | tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node); |
1a6c14a2 | 5340 | if (!tx_ring->tx_buffer_info) |
89bf67f1 | 5341 | tx_ring->tx_buffer_info = vzalloc(size); |
e01c31a5 JB |
5342 | if (!tx_ring->tx_buffer_info) |
5343 | goto err; | |
9a799d71 AK |
5344 | |
5345 | /* round up to nearest 4K */ | |
12207e49 | 5346 | tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc); |
3a581073 | 5347 | tx_ring->size = ALIGN(tx_ring->size, 4096); |
9a799d71 | 5348 | |
b6ec895e | 5349 | tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, |
1b507730 | 5350 | &tx_ring->dma, GFP_KERNEL); |
e01c31a5 JB |
5351 | if (!tx_ring->desc) |
5352 | goto err; | |
9a799d71 | 5353 | |
3a581073 JB |
5354 | tx_ring->next_to_use = 0; |
5355 | tx_ring->next_to_clean = 0; | |
5356 | tx_ring->work_limit = tx_ring->count; | |
9a799d71 | 5357 | return 0; |
e01c31a5 JB |
5358 | |
5359 | err: | |
5360 | vfree(tx_ring->tx_buffer_info); | |
5361 | tx_ring->tx_buffer_info = NULL; | |
b6ec895e | 5362 | dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); |
e01c31a5 | 5363 | return -ENOMEM; |
9a799d71 AK |
5364 | } |
5365 | ||
69888674 AD |
5366 | /** |
5367 | * ixgbe_setup_all_tx_resources - allocate all queues Tx resources | |
5368 | * @adapter: board private structure | |
5369 | * | |
5370 | * If this function returns with an error, then it's possible one or | |
5371 | * more of the rings is populated (while the rest are not). It is the | |
5372 | * callers duty to clean those orphaned rings. | |
5373 | * | |
5374 | * Return 0 on success, negative on failure | |
5375 | **/ | |
5376 | static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter) | |
5377 | { | |
5378 | int i, err = 0; | |
5379 | ||
5380 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
b6ec895e | 5381 | err = ixgbe_setup_tx_resources(adapter->tx_ring[i]); |
69888674 AD |
5382 | if (!err) |
5383 | continue; | |
396e799c | 5384 | e_err(probe, "Allocation for Tx Queue %u failed\n", i); |
69888674 AD |
5385 | break; |
5386 | } | |
5387 | ||
5388 | return err; | |
5389 | } | |
5390 | ||
9a799d71 AK |
5391 | /** |
5392 | * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors) | |
3a581073 | 5393 | * @rx_ring: rx descriptor ring (for a specific queue) to setup |
9a799d71 AK |
5394 | * |
5395 | * Returns 0 on success, negative on failure | |
5396 | **/ | |
b6ec895e | 5397 | int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring) |
9a799d71 | 5398 | { |
b6ec895e | 5399 | struct device *dev = rx_ring->dev; |
021230d4 | 5400 | int size; |
9a799d71 | 5401 | |
3a581073 | 5402 | size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; |
89bf67f1 | 5403 | rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node); |
1a6c14a2 | 5404 | if (!rx_ring->rx_buffer_info) |
89bf67f1 | 5405 | rx_ring->rx_buffer_info = vzalloc(size); |
b6ec895e AD |
5406 | if (!rx_ring->rx_buffer_info) |
5407 | goto err; | |
9a799d71 | 5408 | |
9a799d71 | 5409 | /* Round up to nearest 4K */ |
3a581073 JB |
5410 | rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); |
5411 | rx_ring->size = ALIGN(rx_ring->size, 4096); | |
9a799d71 | 5412 | |
b6ec895e | 5413 | rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, |
1b507730 | 5414 | &rx_ring->dma, GFP_KERNEL); |
9a799d71 | 5415 | |
b6ec895e AD |
5416 | if (!rx_ring->desc) |
5417 | goto err; | |
9a799d71 | 5418 | |
3a581073 JB |
5419 | rx_ring->next_to_clean = 0; |
5420 | rx_ring->next_to_use = 0; | |
9a799d71 AK |
5421 | |
5422 | return 0; | |
b6ec895e AD |
5423 | err: |
5424 | vfree(rx_ring->rx_buffer_info); | |
5425 | rx_ring->rx_buffer_info = NULL; | |
5426 | dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); | |
177db6ff | 5427 | return -ENOMEM; |
9a799d71 AK |
5428 | } |
5429 | ||
69888674 AD |
5430 | /** |
5431 | * ixgbe_setup_all_rx_resources - allocate all queues Rx resources | |
5432 | * @adapter: board private structure | |
5433 | * | |
5434 | * If this function returns with an error, then it's possible one or | |
5435 | * more of the rings is populated (while the rest are not). It is the | |
5436 | * callers duty to clean those orphaned rings. | |
5437 | * | |
5438 | * Return 0 on success, negative on failure | |
5439 | **/ | |
69888674 AD |
5440 | static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter) |
5441 | { | |
5442 | int i, err = 0; | |
5443 | ||
5444 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
b6ec895e | 5445 | err = ixgbe_setup_rx_resources(adapter->rx_ring[i]); |
69888674 AD |
5446 | if (!err) |
5447 | continue; | |
396e799c | 5448 | e_err(probe, "Allocation for Rx Queue %u failed\n", i); |
69888674 AD |
5449 | break; |
5450 | } | |
5451 | ||
5452 | return err; | |
5453 | } | |
5454 | ||
9a799d71 AK |
5455 | /** |
5456 | * ixgbe_free_tx_resources - Free Tx Resources per Queue | |
9a799d71 AK |
5457 | * @tx_ring: Tx descriptor ring for a specific queue |
5458 | * | |
5459 | * Free all transmit software resources | |
5460 | **/ | |
b6ec895e | 5461 | void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring) |
9a799d71 | 5462 | { |
b6ec895e | 5463 | ixgbe_clean_tx_ring(tx_ring); |
9a799d71 AK |
5464 | |
5465 | vfree(tx_ring->tx_buffer_info); | |
5466 | tx_ring->tx_buffer_info = NULL; | |
5467 | ||
b6ec895e AD |
5468 | /* if not set, then don't free */ |
5469 | if (!tx_ring->desc) | |
5470 | return; | |
5471 | ||
5472 | dma_free_coherent(tx_ring->dev, tx_ring->size, | |
5473 | tx_ring->desc, tx_ring->dma); | |
9a799d71 AK |
5474 | |
5475 | tx_ring->desc = NULL; | |
5476 | } | |
5477 | ||
5478 | /** | |
5479 | * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues | |
5480 | * @adapter: board private structure | |
5481 | * | |
5482 | * Free all transmit software resources | |
5483 | **/ | |
5484 | static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter) | |
5485 | { | |
5486 | int i; | |
5487 | ||
5488 | for (i = 0; i < adapter->num_tx_queues; i++) | |
4a0b9ca0 | 5489 | if (adapter->tx_ring[i]->desc) |
b6ec895e | 5490 | ixgbe_free_tx_resources(adapter->tx_ring[i]); |
9a799d71 AK |
5491 | } |
5492 | ||
5493 | /** | |
b4617240 | 5494 | * ixgbe_free_rx_resources - Free Rx Resources |
9a799d71 AK |
5495 | * @rx_ring: ring to clean the resources from |
5496 | * | |
5497 | * Free all receive software resources | |
5498 | **/ | |
b6ec895e | 5499 | void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring) |
9a799d71 | 5500 | { |
b6ec895e | 5501 | ixgbe_clean_rx_ring(rx_ring); |
9a799d71 AK |
5502 | |
5503 | vfree(rx_ring->rx_buffer_info); | |
5504 | rx_ring->rx_buffer_info = NULL; | |
5505 | ||
b6ec895e AD |
5506 | /* if not set, then don't free */ |
5507 | if (!rx_ring->desc) | |
5508 | return; | |
5509 | ||
5510 | dma_free_coherent(rx_ring->dev, rx_ring->size, | |
5511 | rx_ring->desc, rx_ring->dma); | |
9a799d71 AK |
5512 | |
5513 | rx_ring->desc = NULL; | |
5514 | } | |
5515 | ||
5516 | /** | |
5517 | * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues | |
5518 | * @adapter: board private structure | |
5519 | * | |
5520 | * Free all receive software resources | |
5521 | **/ | |
5522 | static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter) | |
5523 | { | |
5524 | int i; | |
5525 | ||
5526 | for (i = 0; i < adapter->num_rx_queues; i++) | |
4a0b9ca0 | 5527 | if (adapter->rx_ring[i]->desc) |
b6ec895e | 5528 | ixgbe_free_rx_resources(adapter->rx_ring[i]); |
9a799d71 AK |
5529 | } |
5530 | ||
9a799d71 AK |
5531 | /** |
5532 | * ixgbe_change_mtu - Change the Maximum Transfer Unit | |
5533 | * @netdev: network interface device structure | |
5534 | * @new_mtu: new value for maximum frame size | |
5535 | * | |
5536 | * Returns 0 on success, negative on failure | |
5537 | **/ | |
5538 | static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu) | |
5539 | { | |
5540 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
16b61beb | 5541 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 AK |
5542 | int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; |
5543 | ||
42c783c5 | 5544 | /* MTU < 68 is an error and causes problems on some kernels */ |
e9f98072 GR |
5545 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED && |
5546 | hw->mac.type != ixgbe_mac_X540) { | |
5547 | if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE)) | |
5548 | return -EINVAL; | |
5549 | } else { | |
5550 | if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE)) | |
5551 | return -EINVAL; | |
5552 | } | |
9a799d71 | 5553 | |
396e799c | 5554 | e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu); |
021230d4 | 5555 | /* must set new MTU before calling down or up */ |
9a799d71 AK |
5556 | netdev->mtu = new_mtu; |
5557 | ||
16b61beb JF |
5558 | hw->fc.high_water = FC_HIGH_WATER(max_frame); |
5559 | hw->fc.low_water = FC_LOW_WATER(max_frame); | |
5560 | ||
d4f80882 AV |
5561 | if (netif_running(netdev)) |
5562 | ixgbe_reinit_locked(adapter); | |
9a799d71 AK |
5563 | |
5564 | return 0; | |
5565 | } | |
5566 | ||
5567 | /** | |
5568 | * ixgbe_open - Called when a network interface is made active | |
5569 | * @netdev: network interface device structure | |
5570 | * | |
5571 | * Returns 0 on success, negative value on failure | |
5572 | * | |
5573 | * The open entry point is called when a network interface is made | |
5574 | * active by the system (IFF_UP). At this point all resources needed | |
5575 | * for transmit and receive operations are allocated, the interrupt | |
5576 | * handler is registered with the OS, the watchdog timer is started, | |
5577 | * and the stack is notified that the interface is ready. | |
5578 | **/ | |
5579 | static int ixgbe_open(struct net_device *netdev) | |
5580 | { | |
5581 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
5582 | int err; | |
4bebfaa5 AK |
5583 | |
5584 | /* disallow open during test */ | |
5585 | if (test_bit(__IXGBE_TESTING, &adapter->state)) | |
5586 | return -EBUSY; | |
9a799d71 | 5587 | |
54386467 JB |
5588 | netif_carrier_off(netdev); |
5589 | ||
9a799d71 AK |
5590 | /* allocate transmit descriptors */ |
5591 | err = ixgbe_setup_all_tx_resources(adapter); | |
5592 | if (err) | |
5593 | goto err_setup_tx; | |
5594 | ||
9a799d71 AK |
5595 | /* allocate receive descriptors */ |
5596 | err = ixgbe_setup_all_rx_resources(adapter); | |
5597 | if (err) | |
5598 | goto err_setup_rx; | |
5599 | ||
5600 | ixgbe_configure(adapter); | |
5601 | ||
021230d4 | 5602 | err = ixgbe_request_irq(adapter); |
9a799d71 AK |
5603 | if (err) |
5604 | goto err_req_irq; | |
5605 | ||
9a799d71 AK |
5606 | err = ixgbe_up_complete(adapter); |
5607 | if (err) | |
5608 | goto err_up; | |
5609 | ||
d55b53ff JK |
5610 | netif_tx_start_all_queues(netdev); |
5611 | ||
9a799d71 AK |
5612 | return 0; |
5613 | ||
5614 | err_up: | |
5eba3699 | 5615 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
5616 | ixgbe_free_irq(adapter); |
5617 | err_req_irq: | |
9a799d71 | 5618 | err_setup_rx: |
a20a1199 | 5619 | ixgbe_free_all_rx_resources(adapter); |
9a799d71 | 5620 | err_setup_tx: |
a20a1199 | 5621 | ixgbe_free_all_tx_resources(adapter); |
9a799d71 AK |
5622 | ixgbe_reset(adapter); |
5623 | ||
5624 | return err; | |
5625 | } | |
5626 | ||
5627 | /** | |
5628 | * ixgbe_close - Disables a network interface | |
5629 | * @netdev: network interface device structure | |
5630 | * | |
5631 | * Returns 0, this is not allowed to fail | |
5632 | * | |
5633 | * The close entry point is called when an interface is de-activated | |
5634 | * by the OS. The hardware is still under the drivers control, but | |
5635 | * needs to be disabled. A global MAC reset is issued to stop the | |
5636 | * hardware, and all transmit and receive resources are freed. | |
5637 | **/ | |
5638 | static int ixgbe_close(struct net_device *netdev) | |
5639 | { | |
5640 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
9a799d71 AK |
5641 | |
5642 | ixgbe_down(adapter); | |
5643 | ixgbe_free_irq(adapter); | |
5644 | ||
5645 | ixgbe_free_all_tx_resources(adapter); | |
5646 | ixgbe_free_all_rx_resources(adapter); | |
5647 | ||
5eba3699 | 5648 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
5649 | |
5650 | return 0; | |
5651 | } | |
5652 | ||
b3c8b4ba AD |
5653 | #ifdef CONFIG_PM |
5654 | static int ixgbe_resume(struct pci_dev *pdev) | |
5655 | { | |
c60fbb00 AD |
5656 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
5657 | struct net_device *netdev = adapter->netdev; | |
b3c8b4ba AD |
5658 | u32 err; |
5659 | ||
5660 | pci_set_power_state(pdev, PCI_D0); | |
5661 | pci_restore_state(pdev); | |
656ab817 DS |
5662 | /* |
5663 | * pci_restore_state clears dev->state_saved so call | |
5664 | * pci_save_state to restore it. | |
5665 | */ | |
5666 | pci_save_state(pdev); | |
9ce77666 | 5667 | |
5668 | err = pci_enable_device_mem(pdev); | |
b3c8b4ba | 5669 | if (err) { |
849c4542 | 5670 | e_dev_err("Cannot enable PCI device from suspend\n"); |
b3c8b4ba AD |
5671 | return err; |
5672 | } | |
5673 | pci_set_master(pdev); | |
5674 | ||
dd4d8ca6 | 5675 | pci_wake_from_d3(pdev, false); |
b3c8b4ba AD |
5676 | |
5677 | err = ixgbe_init_interrupt_scheme(adapter); | |
5678 | if (err) { | |
849c4542 | 5679 | e_dev_err("Cannot initialize interrupts for device\n"); |
b3c8b4ba AD |
5680 | return err; |
5681 | } | |
5682 | ||
b3c8b4ba AD |
5683 | ixgbe_reset(adapter); |
5684 | ||
495dce12 WJP |
5685 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
5686 | ||
b3c8b4ba | 5687 | if (netif_running(netdev)) { |
c60fbb00 | 5688 | err = ixgbe_open(netdev); |
b3c8b4ba AD |
5689 | if (err) |
5690 | return err; | |
5691 | } | |
5692 | ||
5693 | netif_device_attach(netdev); | |
5694 | ||
5695 | return 0; | |
5696 | } | |
b3c8b4ba | 5697 | #endif /* CONFIG_PM */ |
9d8d05ae RW |
5698 | |
5699 | static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake) | |
b3c8b4ba | 5700 | { |
c60fbb00 AD |
5701 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
5702 | struct net_device *netdev = adapter->netdev; | |
e8e26350 PW |
5703 | struct ixgbe_hw *hw = &adapter->hw; |
5704 | u32 ctrl, fctrl; | |
5705 | u32 wufc = adapter->wol; | |
b3c8b4ba AD |
5706 | #ifdef CONFIG_PM |
5707 | int retval = 0; | |
5708 | #endif | |
5709 | ||
5710 | netif_device_detach(netdev); | |
5711 | ||
5712 | if (netif_running(netdev)) { | |
5713 | ixgbe_down(adapter); | |
5714 | ixgbe_free_irq(adapter); | |
5715 | ixgbe_free_all_tx_resources(adapter); | |
5716 | ixgbe_free_all_rx_resources(adapter); | |
5717 | } | |
b3c8b4ba | 5718 | |
5f5ae6fc | 5719 | ixgbe_clear_interrupt_scheme(adapter); |
d033d526 JF |
5720 | #ifdef CONFIG_DCB |
5721 | kfree(adapter->ixgbe_ieee_pfc); | |
5722 | kfree(adapter->ixgbe_ieee_ets); | |
5723 | #endif | |
5f5ae6fc | 5724 | |
b3c8b4ba AD |
5725 | #ifdef CONFIG_PM |
5726 | retval = pci_save_state(pdev); | |
5727 | if (retval) | |
5728 | return retval; | |
4df10466 | 5729 | |
b3c8b4ba | 5730 | #endif |
e8e26350 PW |
5731 | if (wufc) { |
5732 | ixgbe_set_rx_mode(netdev); | |
b3c8b4ba | 5733 | |
e8e26350 PW |
5734 | /* turn on all-multi mode if wake on multicast is enabled */ |
5735 | if (wufc & IXGBE_WUFC_MC) { | |
5736 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
5737 | fctrl |= IXGBE_FCTRL_MPE; | |
5738 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); | |
5739 | } | |
5740 | ||
5741 | ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); | |
5742 | ctrl |= IXGBE_CTRL_GIO_DIS; | |
5743 | IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); | |
5744 | ||
5745 | IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc); | |
5746 | } else { | |
5747 | IXGBE_WRITE_REG(hw, IXGBE_WUC, 0); | |
5748 | IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); | |
5749 | } | |
5750 | ||
bd508178 AD |
5751 | switch (hw->mac.type) { |
5752 | case ixgbe_mac_82598EB: | |
dd4d8ca6 | 5753 | pci_wake_from_d3(pdev, false); |
bd508178 AD |
5754 | break; |
5755 | case ixgbe_mac_82599EB: | |
b93a2226 | 5756 | case ixgbe_mac_X540: |
bd508178 AD |
5757 | pci_wake_from_d3(pdev, !!wufc); |
5758 | break; | |
5759 | default: | |
5760 | break; | |
5761 | } | |
b3c8b4ba | 5762 | |
9d8d05ae RW |
5763 | *enable_wake = !!wufc; |
5764 | ||
b3c8b4ba AD |
5765 | ixgbe_release_hw_control(adapter); |
5766 | ||
5767 | pci_disable_device(pdev); | |
5768 | ||
9d8d05ae RW |
5769 | return 0; |
5770 | } | |
5771 | ||
5772 | #ifdef CONFIG_PM | |
5773 | static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state) | |
5774 | { | |
5775 | int retval; | |
5776 | bool wake; | |
5777 | ||
5778 | retval = __ixgbe_shutdown(pdev, &wake); | |
5779 | if (retval) | |
5780 | return retval; | |
5781 | ||
5782 | if (wake) { | |
5783 | pci_prepare_to_sleep(pdev); | |
5784 | } else { | |
5785 | pci_wake_from_d3(pdev, false); | |
5786 | pci_set_power_state(pdev, PCI_D3hot); | |
5787 | } | |
b3c8b4ba AD |
5788 | |
5789 | return 0; | |
5790 | } | |
9d8d05ae | 5791 | #endif /* CONFIG_PM */ |
b3c8b4ba AD |
5792 | |
5793 | static void ixgbe_shutdown(struct pci_dev *pdev) | |
5794 | { | |
9d8d05ae RW |
5795 | bool wake; |
5796 | ||
5797 | __ixgbe_shutdown(pdev, &wake); | |
5798 | ||
5799 | if (system_state == SYSTEM_POWER_OFF) { | |
5800 | pci_wake_from_d3(pdev, wake); | |
5801 | pci_set_power_state(pdev, PCI_D3hot); | |
5802 | } | |
b3c8b4ba AD |
5803 | } |
5804 | ||
9a799d71 AK |
5805 | /** |
5806 | * ixgbe_update_stats - Update the board statistics counters. | |
5807 | * @adapter: board private structure | |
5808 | **/ | |
5809 | void ixgbe_update_stats(struct ixgbe_adapter *adapter) | |
5810 | { | |
2d86f139 | 5811 | struct net_device *netdev = adapter->netdev; |
9a799d71 | 5812 | struct ixgbe_hw *hw = &adapter->hw; |
5b7da515 | 5813 | struct ixgbe_hw_stats *hwstats = &adapter->stats; |
6f11eef7 AV |
5814 | u64 total_mpc = 0; |
5815 | u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot; | |
5b7da515 AD |
5816 | u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0; |
5817 | u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0; | |
5818 | u64 bytes = 0, packets = 0; | |
9a799d71 | 5819 | |
d08935c2 DS |
5820 | if (test_bit(__IXGBE_DOWN, &adapter->state) || |
5821 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
5822 | return; | |
5823 | ||
94b982b2 | 5824 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { |
f8212f97 | 5825 | u64 rsc_count = 0; |
94b982b2 | 5826 | u64 rsc_flush = 0; |
d51019a4 PW |
5827 | for (i = 0; i < 16; i++) |
5828 | adapter->hw_rx_no_dma_resources += | |
7ca647bd | 5829 | IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); |
94b982b2 | 5830 | for (i = 0; i < adapter->num_rx_queues; i++) { |
5b7da515 AD |
5831 | rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count; |
5832 | rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush; | |
94b982b2 MC |
5833 | } |
5834 | adapter->rsc_total_count = rsc_count; | |
5835 | adapter->rsc_total_flush = rsc_flush; | |
d51019a4 PW |
5836 | } |
5837 | ||
5b7da515 AD |
5838 | for (i = 0; i < adapter->num_rx_queues; i++) { |
5839 | struct ixgbe_ring *rx_ring = adapter->rx_ring[i]; | |
5840 | non_eop_descs += rx_ring->rx_stats.non_eop_descs; | |
5841 | alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed; | |
5842 | alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed; | |
5843 | bytes += rx_ring->stats.bytes; | |
5844 | packets += rx_ring->stats.packets; | |
5845 | } | |
5846 | adapter->non_eop_descs = non_eop_descs; | |
5847 | adapter->alloc_rx_page_failed = alloc_rx_page_failed; | |
5848 | adapter->alloc_rx_buff_failed = alloc_rx_buff_failed; | |
5849 | netdev->stats.rx_bytes = bytes; | |
5850 | netdev->stats.rx_packets = packets; | |
5851 | ||
5852 | bytes = 0; | |
5853 | packets = 0; | |
7ca3bc58 | 5854 | /* gather some stats to the adapter struct that are per queue */ |
5b7da515 AD |
5855 | for (i = 0; i < adapter->num_tx_queues; i++) { |
5856 | struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; | |
5857 | restart_queue += tx_ring->tx_stats.restart_queue; | |
5858 | tx_busy += tx_ring->tx_stats.tx_busy; | |
5859 | bytes += tx_ring->stats.bytes; | |
5860 | packets += tx_ring->stats.packets; | |
5861 | } | |
eb985f09 | 5862 | adapter->restart_queue = restart_queue; |
5b7da515 AD |
5863 | adapter->tx_busy = tx_busy; |
5864 | netdev->stats.tx_bytes = bytes; | |
5865 | netdev->stats.tx_packets = packets; | |
7ca3bc58 | 5866 | |
7ca647bd | 5867 | hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); |
6f11eef7 AV |
5868 | for (i = 0; i < 8; i++) { |
5869 | /* for packet buffers not used, the register should read 0 */ | |
5870 | mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i)); | |
5871 | missed_rx += mpc; | |
7ca647bd JP |
5872 | hwstats->mpc[i] += mpc; |
5873 | total_mpc += hwstats->mpc[i]; | |
e8e26350 | 5874 | if (hw->mac.type == ixgbe_mac_82598EB) |
7ca647bd JP |
5875 | hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); |
5876 | hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); | |
5877 | hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i)); | |
5878 | hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); | |
5879 | hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i)); | |
bd508178 AD |
5880 | switch (hw->mac.type) { |
5881 | case ixgbe_mac_82598EB: | |
7ca647bd JP |
5882 | hwstats->pxonrxc[i] += |
5883 | IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); | |
bd508178 AD |
5884 | break; |
5885 | case ixgbe_mac_82599EB: | |
b93a2226 | 5886 | case ixgbe_mac_X540: |
bd508178 AD |
5887 | hwstats->pxonrxc[i] += |
5888 | IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); | |
bd508178 AD |
5889 | break; |
5890 | default: | |
5891 | break; | |
e8e26350 | 5892 | } |
7ca647bd JP |
5893 | hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); |
5894 | hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); | |
6f11eef7 | 5895 | } |
7ca647bd | 5896 | hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); |
6f11eef7 | 5897 | /* work around hardware counting issue */ |
7ca647bd | 5898 | hwstats->gprc -= missed_rx; |
6f11eef7 | 5899 | |
c84d324c JF |
5900 | ixgbe_update_xoff_received(adapter); |
5901 | ||
6f11eef7 | 5902 | /* 82598 hardware only has a 32 bit counter in the high register */ |
bd508178 AD |
5903 | switch (hw->mac.type) { |
5904 | case ixgbe_mac_82598EB: | |
5905 | hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); | |
bd508178 AD |
5906 | hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); |
5907 | hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); | |
5908 | hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); | |
5909 | break; | |
b93a2226 | 5910 | case ixgbe_mac_X540: |
58f6bcf9 ET |
5911 | /* OS2BMC stats are X540 only*/ |
5912 | hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC); | |
5913 | hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC); | |
5914 | hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC); | |
5915 | hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC); | |
5916 | case ixgbe_mac_82599EB: | |
7ca647bd | 5917 | hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); |
bd508178 | 5918 | IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */ |
7ca647bd | 5919 | hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); |
bd508178 | 5920 | IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */ |
7ca647bd | 5921 | hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL); |
bd508178 | 5922 | IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */ |
7ca647bd | 5923 | hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); |
7ca647bd JP |
5924 | hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); |
5925 | hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); | |
6d45522c | 5926 | #ifdef IXGBE_FCOE |
7ca647bd JP |
5927 | hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); |
5928 | hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); | |
5929 | hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); | |
5930 | hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); | |
5931 | hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); | |
5932 | hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); | |
6d45522c | 5933 | #endif /* IXGBE_FCOE */ |
bd508178 AD |
5934 | break; |
5935 | default: | |
5936 | break; | |
e8e26350 | 5937 | } |
9a799d71 | 5938 | bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); |
7ca647bd JP |
5939 | hwstats->bprc += bprc; |
5940 | hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); | |
e8e26350 | 5941 | if (hw->mac.type == ixgbe_mac_82598EB) |
7ca647bd JP |
5942 | hwstats->mprc -= bprc; |
5943 | hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); | |
5944 | hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); | |
5945 | hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); | |
5946 | hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); | |
5947 | hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); | |
5948 | hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); | |
5949 | hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); | |
5950 | hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); | |
6f11eef7 | 5951 | lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); |
7ca647bd | 5952 | hwstats->lxontxc += lxon; |
6f11eef7 | 5953 | lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); |
7ca647bd JP |
5954 | hwstats->lxofftxc += lxoff; |
5955 | hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); | |
5956 | hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); | |
5957 | hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); | |
6f11eef7 AV |
5958 | /* |
5959 | * 82598 errata - tx of flow control packets is included in tx counters | |
5960 | */ | |
5961 | xon_off_tot = lxon + lxoff; | |
7ca647bd JP |
5962 | hwstats->gptc -= xon_off_tot; |
5963 | hwstats->mptc -= xon_off_tot; | |
5964 | hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN)); | |
5965 | hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); | |
5966 | hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); | |
5967 | hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); | |
5968 | hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); | |
5969 | hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); | |
5970 | hwstats->ptc64 -= xon_off_tot; | |
5971 | hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); | |
5972 | hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); | |
5973 | hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); | |
5974 | hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); | |
5975 | hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); | |
5976 | hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); | |
9a799d71 AK |
5977 | |
5978 | /* Fill out the OS statistics structure */ | |
7ca647bd | 5979 | netdev->stats.multicast = hwstats->mprc; |
9a799d71 AK |
5980 | |
5981 | /* Rx Errors */ | |
7ca647bd | 5982 | netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec; |
2d86f139 | 5983 | netdev->stats.rx_dropped = 0; |
7ca647bd JP |
5984 | netdev->stats.rx_length_errors = hwstats->rlec; |
5985 | netdev->stats.rx_crc_errors = hwstats->crcerrs; | |
2d86f139 | 5986 | netdev->stats.rx_missed_errors = total_mpc; |
9a799d71 AK |
5987 | } |
5988 | ||
5989 | /** | |
d034acf1 AD |
5990 | * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table |
5991 | * @adapter - pointer to the device adapter structure | |
9a799d71 | 5992 | **/ |
d034acf1 | 5993 | static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter) |
9a799d71 | 5994 | { |
cf8280ee | 5995 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a | 5996 | int i; |
cf8280ee | 5997 | |
d034acf1 AD |
5998 | if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) |
5999 | return; | |
6000 | ||
6001 | adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; | |
22d5a71b | 6002 | |
d034acf1 | 6003 | /* if interface is down do nothing */ |
fe49f04a | 6004 | if (test_bit(__IXGBE_DOWN, &adapter->state)) |
d034acf1 AD |
6005 | return; |
6006 | ||
6007 | /* do nothing if we are not using signature filters */ | |
6008 | if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) | |
6009 | return; | |
6010 | ||
6011 | adapter->fdir_overflow++; | |
6012 | ||
93c52dd0 AD |
6013 | if (ixgbe_reinit_fdir_tables_82599(hw) == 0) { |
6014 | for (i = 0; i < adapter->num_tx_queues; i++) | |
6015 | set_bit(__IXGBE_TX_FDIR_INIT_DONE, | |
f0f9778d | 6016 | &(adapter->tx_ring[i]->state)); |
d034acf1 AD |
6017 | /* re-enable flow director interrupts */ |
6018 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR); | |
93c52dd0 AD |
6019 | } else { |
6020 | e_err(probe, "failed to finish FDIR re-initialization, " | |
6021 | "ignored adding FDIR ATR filters\n"); | |
6022 | } | |
93c52dd0 AD |
6023 | } |
6024 | ||
6025 | /** | |
6026 | * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts | |
6027 | * @adapter - pointer to the device adapter structure | |
6028 | * | |
6029 | * This function serves two purposes. First it strobes the interrupt lines | |
6030 | * in order to make certain interrupts are occuring. Secondly it sets the | |
6031 | * bits needed to check for TX hangs. As a result we should immediately | |
6032 | * determine if a hang has occured. | |
6033 | */ | |
6034 | static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter) | |
9a799d71 | 6035 | { |
cf8280ee | 6036 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a AD |
6037 | u64 eics = 0; |
6038 | int i; | |
cf8280ee | 6039 | |
93c52dd0 AD |
6040 | /* If we're down or resetting, just bail */ |
6041 | if (test_bit(__IXGBE_DOWN, &adapter->state) || | |
6042 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
6043 | return; | |
22d5a71b | 6044 | |
93c52dd0 AD |
6045 | /* Force detection of hung controller */ |
6046 | if (netif_carrier_ok(adapter->netdev)) { | |
6047 | for (i = 0; i < adapter->num_tx_queues; i++) | |
6048 | set_check_for_tx_hang(adapter->tx_ring[i]); | |
6049 | } | |
22d5a71b | 6050 | |
fe49f04a AD |
6051 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { |
6052 | /* | |
6053 | * for legacy and MSI interrupts don't set any bits | |
6054 | * that are enabled for EIAM, because this operation | |
6055 | * would set *both* EIMS and EICS for any bit in EIAM | |
6056 | */ | |
6057 | IXGBE_WRITE_REG(hw, IXGBE_EICS, | |
6058 | (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); | |
93c52dd0 AD |
6059 | } else { |
6060 | /* get one bit for every active tx/rx interrupt vector */ | |
6061 | for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) { | |
6062 | struct ixgbe_q_vector *qv = adapter->q_vector[i]; | |
6063 | if (qv->rxr_count || qv->txr_count) | |
6064 | eics |= ((u64)1 << i); | |
6065 | } | |
cf8280ee | 6066 | } |
9a799d71 | 6067 | |
93c52dd0 | 6068 | /* Cause software interrupt to ensure rings are cleaned */ |
fe49f04a AD |
6069 | ixgbe_irq_rearm_queues(adapter, eics); |
6070 | ||
cf8280ee JB |
6071 | } |
6072 | ||
e8e26350 | 6073 | /** |
93c52dd0 AD |
6074 | * ixgbe_watchdog_update_link - update the link status |
6075 | * @adapter - pointer to the device adapter structure | |
6076 | * @link_speed - pointer to a u32 to store the link_speed | |
e8e26350 | 6077 | **/ |
93c52dd0 | 6078 | static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter) |
e8e26350 | 6079 | { |
e8e26350 | 6080 | struct ixgbe_hw *hw = &adapter->hw; |
93c52dd0 AD |
6081 | u32 link_speed = adapter->link_speed; |
6082 | bool link_up = adapter->link_up; | |
c4cf55e5 | 6083 | int i; |
e8e26350 | 6084 | |
93c52dd0 AD |
6085 | if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) |
6086 | return; | |
6087 | ||
6088 | if (hw->mac.ops.check_link) { | |
6089 | hw->mac.ops.check_link(hw, &link_speed, &link_up, false); | |
c4cf55e5 | 6090 | } else { |
93c52dd0 AD |
6091 | /* always assume link is up, if no check link function */ |
6092 | link_speed = IXGBE_LINK_SPEED_10GB_FULL; | |
6093 | link_up = true; | |
c4cf55e5 | 6094 | } |
93c52dd0 AD |
6095 | if (link_up) { |
6096 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
6097 | for (i = 0; i < MAX_TRAFFIC_CLASS; i++) | |
6098 | hw->mac.ops.fc_enable(hw, i); | |
6099 | } else { | |
6100 | hw->mac.ops.fc_enable(hw, 0); | |
6101 | } | |
6102 | } | |
6103 | ||
6104 | if (link_up || | |
6105 | time_after(jiffies, (adapter->link_check_timeout + | |
6106 | IXGBE_TRY_LINK_TIMEOUT))) { | |
6107 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; | |
6108 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC); | |
6109 | IXGBE_WRITE_FLUSH(hw); | |
6110 | } | |
6111 | ||
6112 | adapter->link_up = link_up; | |
6113 | adapter->link_speed = link_speed; | |
e8e26350 PW |
6114 | } |
6115 | ||
6116 | /** | |
93c52dd0 AD |
6117 | * ixgbe_watchdog_link_is_up - update netif_carrier status and |
6118 | * print link up message | |
6119 | * @adapter - pointer to the device adapter structure | |
e8e26350 | 6120 | **/ |
93c52dd0 | 6121 | static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter) |
e8e26350 | 6122 | { |
93c52dd0 | 6123 | struct net_device *netdev = adapter->netdev; |
e8e26350 | 6124 | struct ixgbe_hw *hw = &adapter->hw; |
93c52dd0 AD |
6125 | u32 link_speed = adapter->link_speed; |
6126 | bool flow_rx, flow_tx; | |
e8e26350 | 6127 | |
93c52dd0 AD |
6128 | /* only continue if link was previously down */ |
6129 | if (netif_carrier_ok(netdev)) | |
a985b6c3 | 6130 | return; |
63d6e1d8 | 6131 | |
93c52dd0 | 6132 | adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; |
63d6e1d8 | 6133 | |
93c52dd0 AD |
6134 | switch (hw->mac.type) { |
6135 | case ixgbe_mac_82598EB: { | |
6136 | u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
6137 | u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS); | |
6138 | flow_rx = !!(frctl & IXGBE_FCTRL_RFCE); | |
6139 | flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X); | |
6140 | } | |
6141 | break; | |
6142 | case ixgbe_mac_X540: | |
6143 | case ixgbe_mac_82599EB: { | |
6144 | u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); | |
6145 | u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG); | |
6146 | flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE); | |
6147 | flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X); | |
6148 | } | |
6149 | break; | |
6150 | default: | |
6151 | flow_tx = false; | |
6152 | flow_rx = false; | |
6153 | break; | |
e8e26350 | 6154 | } |
93c52dd0 AD |
6155 | e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", |
6156 | (link_speed == IXGBE_LINK_SPEED_10GB_FULL ? | |
6157 | "10 Gbps" : | |
6158 | (link_speed == IXGBE_LINK_SPEED_1GB_FULL ? | |
6159 | "1 Gbps" : | |
6160 | (link_speed == IXGBE_LINK_SPEED_100_FULL ? | |
6161 | "100 Mbps" : | |
6162 | "unknown speed"))), | |
6163 | ((flow_rx && flow_tx) ? "RX/TX" : | |
6164 | (flow_rx ? "RX" : | |
6165 | (flow_tx ? "TX" : "None")))); | |
e8e26350 | 6166 | |
93c52dd0 AD |
6167 | netif_carrier_on(netdev); |
6168 | #ifdef HAVE_IPLINK_VF_CONFIG | |
6169 | ixgbe_check_vf_rate_limit(adapter); | |
6170 | #endif /* HAVE_IPLINK_VF_CONFIG */ | |
e8e26350 PW |
6171 | } |
6172 | ||
c4cf55e5 | 6173 | /** |
93c52dd0 AD |
6174 | * ixgbe_watchdog_link_is_down - update netif_carrier status and |
6175 | * print link down message | |
6176 | * @adapter - pointer to the adapter structure | |
c4cf55e5 | 6177 | **/ |
93c52dd0 | 6178 | static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter* adapter) |
c4cf55e5 | 6179 | { |
cf8280ee | 6180 | struct net_device *netdev = adapter->netdev; |
c4cf55e5 | 6181 | struct ixgbe_hw *hw = &adapter->hw; |
10eec955 | 6182 | |
93c52dd0 AD |
6183 | adapter->link_up = false; |
6184 | adapter->link_speed = 0; | |
cf8280ee | 6185 | |
93c52dd0 AD |
6186 | /* only continue if link was up previously */ |
6187 | if (!netif_carrier_ok(netdev)) | |
6188 | return; | |
264857b8 | 6189 | |
93c52dd0 AD |
6190 | /* poll for SFP+ cable when link is down */ |
6191 | if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB) | |
6192 | adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; | |
9a799d71 | 6193 | |
93c52dd0 AD |
6194 | e_info(drv, "NIC Link is Down\n"); |
6195 | netif_carrier_off(netdev); | |
6196 | } | |
e8e26350 | 6197 | |
93c52dd0 AD |
6198 | /** |
6199 | * ixgbe_watchdog_flush_tx - flush queues on link down | |
6200 | * @adapter - pointer to the device adapter structure | |
6201 | **/ | |
6202 | static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter) | |
6203 | { | |
c4cf55e5 | 6204 | int i; |
93c52dd0 | 6205 | int some_tx_pending = 0; |
c4cf55e5 | 6206 | |
93c52dd0 | 6207 | if (!netif_carrier_ok(adapter->netdev)) { |
bc59fcda | 6208 | for (i = 0; i < adapter->num_tx_queues; i++) { |
93c52dd0 | 6209 | struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; |
bc59fcda NS |
6210 | if (tx_ring->next_to_use != tx_ring->next_to_clean) { |
6211 | some_tx_pending = 1; | |
6212 | break; | |
6213 | } | |
6214 | } | |
6215 | ||
6216 | if (some_tx_pending) { | |
6217 | /* We've lost link, so the controller stops DMA, | |
6218 | * but we've got queued Tx work that's never going | |
6219 | * to get done, so reset controller to flush Tx. | |
6220 | * (Do the reset outside of interrupt context). | |
6221 | */ | |
c83c6cbd | 6222 | adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED; |
bc59fcda | 6223 | } |
c4cf55e5 | 6224 | } |
c4cf55e5 PWJ |
6225 | } |
6226 | ||
a985b6c3 GR |
6227 | static void ixgbe_spoof_check(struct ixgbe_adapter *adapter) |
6228 | { | |
6229 | u32 ssvpc; | |
6230 | ||
6231 | /* Do not perform spoof check for 82598 */ | |
6232 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) | |
6233 | return; | |
6234 | ||
6235 | ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC); | |
6236 | ||
6237 | /* | |
6238 | * ssvpc register is cleared on read, if zero then no | |
6239 | * spoofed packets in the last interval. | |
6240 | */ | |
6241 | if (!ssvpc) | |
6242 | return; | |
6243 | ||
6244 | e_warn(drv, "%d Spoofed packets detected\n", ssvpc); | |
6245 | } | |
6246 | ||
93c52dd0 AD |
6247 | /** |
6248 | * ixgbe_watchdog_subtask - check and bring link up | |
6249 | * @adapter - pointer to the device adapter structure | |
6250 | **/ | |
6251 | static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter) | |
6252 | { | |
6253 | /* if interface is down do nothing */ | |
6254 | if (test_bit(__IXGBE_DOWN, &adapter->state)) | |
6255 | return; | |
6256 | ||
6257 | ixgbe_watchdog_update_link(adapter); | |
6258 | ||
6259 | if (adapter->link_up) | |
6260 | ixgbe_watchdog_link_is_up(adapter); | |
6261 | else | |
6262 | ixgbe_watchdog_link_is_down(adapter); | |
bc59fcda | 6263 | |
a985b6c3 | 6264 | ixgbe_spoof_check(adapter); |
9a799d71 | 6265 | ixgbe_update_stats(adapter); |
93c52dd0 AD |
6266 | |
6267 | ixgbe_watchdog_flush_tx(adapter); | |
9a799d71 | 6268 | } |
10eec955 | 6269 | |
cf8280ee | 6270 | /** |
7086400d AD |
6271 | * ixgbe_sfp_detection_subtask - poll for SFP+ cable |
6272 | * @adapter - the ixgbe adapter structure | |
cf8280ee | 6273 | **/ |
7086400d | 6274 | static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter) |
cf8280ee | 6275 | { |
cf8280ee | 6276 | struct ixgbe_hw *hw = &adapter->hw; |
7086400d | 6277 | s32 err; |
cf8280ee | 6278 | |
7086400d AD |
6279 | /* not searching for SFP so there is nothing to do here */ |
6280 | if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) && | |
6281 | !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) | |
6282 | return; | |
10eec955 | 6283 | |
7086400d AD |
6284 | /* someone else is in init, wait until next service event */ |
6285 | if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) | |
6286 | return; | |
cf8280ee | 6287 | |
7086400d AD |
6288 | err = hw->phy.ops.identify_sfp(hw); |
6289 | if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) | |
6290 | goto sfp_out; | |
264857b8 | 6291 | |
7086400d AD |
6292 | if (err == IXGBE_ERR_SFP_NOT_PRESENT) { |
6293 | /* If no cable is present, then we need to reset | |
6294 | * the next time we find a good cable. */ | |
6295 | adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; | |
cf8280ee | 6296 | } |
9a799d71 | 6297 | |
7086400d AD |
6298 | /* exit on error */ |
6299 | if (err) | |
6300 | goto sfp_out; | |
e8e26350 | 6301 | |
7086400d AD |
6302 | /* exit if reset not needed */ |
6303 | if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) | |
6304 | goto sfp_out; | |
9a799d71 | 6305 | |
7086400d | 6306 | adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET; |
bc59fcda | 6307 | |
7086400d AD |
6308 | /* |
6309 | * A module may be identified correctly, but the EEPROM may not have | |
6310 | * support for that module. setup_sfp() will fail in that case, so | |
6311 | * we should not allow that module to load. | |
6312 | */ | |
6313 | if (hw->mac.type == ixgbe_mac_82598EB) | |
6314 | err = hw->phy.ops.reset(hw); | |
6315 | else | |
6316 | err = hw->mac.ops.setup_sfp(hw); | |
6317 | ||
6318 | if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) | |
6319 | goto sfp_out; | |
6320 | ||
6321 | adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; | |
6322 | e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type); | |
6323 | ||
6324 | sfp_out: | |
6325 | clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); | |
6326 | ||
6327 | if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) && | |
6328 | (adapter->netdev->reg_state == NETREG_REGISTERED)) { | |
6329 | e_dev_err("failed to initialize because an unsupported " | |
6330 | "SFP+ module type was detected.\n"); | |
6331 | e_dev_err("Reload the driver after installing a " | |
6332 | "supported module.\n"); | |
6333 | unregister_netdev(adapter->netdev); | |
bc59fcda | 6334 | } |
7086400d | 6335 | } |
bc59fcda | 6336 | |
7086400d AD |
6337 | /** |
6338 | * ixgbe_sfp_link_config_subtask - set up link SFP after module install | |
6339 | * @adapter - the ixgbe adapter structure | |
6340 | **/ | |
6341 | static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter) | |
6342 | { | |
6343 | struct ixgbe_hw *hw = &adapter->hw; | |
6344 | u32 autoneg; | |
6345 | bool negotiation; | |
6346 | ||
6347 | if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG)) | |
6348 | return; | |
6349 | ||
6350 | /* someone else is in init, wait until next service event */ | |
6351 | if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) | |
6352 | return; | |
6353 | ||
6354 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; | |
6355 | ||
6356 | autoneg = hw->phy.autoneg_advertised; | |
6357 | if ((!autoneg) && (hw->mac.ops.get_link_capabilities)) | |
6358 | hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation); | |
6359 | hw->mac.autotry_restart = false; | |
6360 | if (hw->mac.ops.setup_link) | |
6361 | hw->mac.ops.setup_link(hw, autoneg, negotiation, true); | |
6362 | ||
6363 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; | |
6364 | adapter->link_check_timeout = jiffies; | |
6365 | clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); | |
6366 | } | |
6367 | ||
6368 | /** | |
6369 | * ixgbe_service_timer - Timer Call-back | |
6370 | * @data: pointer to adapter cast into an unsigned long | |
6371 | **/ | |
6372 | static void ixgbe_service_timer(unsigned long data) | |
6373 | { | |
6374 | struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data; | |
6375 | unsigned long next_event_offset; | |
6376 | ||
6377 | /* poll faster when waiting for link */ | |
6378 | if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) | |
6379 | next_event_offset = HZ / 10; | |
6380 | else | |
6381 | next_event_offset = HZ * 2; | |
6382 | ||
6383 | /* Reset the timer */ | |
6384 | mod_timer(&adapter->service_timer, next_event_offset + jiffies); | |
6385 | ||
6386 | ixgbe_service_event_schedule(adapter); | |
6387 | } | |
6388 | ||
c83c6cbd AD |
6389 | static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter) |
6390 | { | |
6391 | if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED)) | |
6392 | return; | |
6393 | ||
6394 | adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED; | |
6395 | ||
6396 | /* If we're already down or resetting, just bail */ | |
6397 | if (test_bit(__IXGBE_DOWN, &adapter->state) || | |
6398 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
6399 | return; | |
6400 | ||
6401 | ixgbe_dump(adapter); | |
6402 | netdev_err(adapter->netdev, "Reset adapter\n"); | |
6403 | adapter->tx_timeout_count++; | |
6404 | ||
6405 | ixgbe_reinit_locked(adapter); | |
6406 | } | |
6407 | ||
7086400d AD |
6408 | /** |
6409 | * ixgbe_service_task - manages and runs subtasks | |
6410 | * @work: pointer to work_struct containing our data | |
6411 | **/ | |
6412 | static void ixgbe_service_task(struct work_struct *work) | |
6413 | { | |
6414 | struct ixgbe_adapter *adapter = container_of(work, | |
6415 | struct ixgbe_adapter, | |
6416 | service_task); | |
6417 | ||
c83c6cbd | 6418 | ixgbe_reset_subtask(adapter); |
7086400d AD |
6419 | ixgbe_sfp_detection_subtask(adapter); |
6420 | ixgbe_sfp_link_config_subtask(adapter); | |
f0f9778d | 6421 | ixgbe_check_overtemp_subtask(adapter); |
93c52dd0 | 6422 | ixgbe_watchdog_subtask(adapter); |
d034acf1 | 6423 | ixgbe_fdir_reinit_subtask(adapter); |
93c52dd0 | 6424 | ixgbe_check_hang_subtask(adapter); |
7086400d AD |
6425 | |
6426 | ixgbe_service_event_complete(adapter); | |
9a799d71 AK |
6427 | } |
6428 | ||
9a799d71 | 6429 | static int ixgbe_tso(struct ixgbe_adapter *adapter, |
e8e9f696 | 6430 | struct ixgbe_ring *tx_ring, struct sk_buff *skb, |
5e09a105 | 6431 | u32 tx_flags, u8 *hdr_len, __be16 protocol) |
9a799d71 AK |
6432 | { |
6433 | struct ixgbe_adv_tx_context_desc *context_desc; | |
6434 | unsigned int i; | |
6435 | int err; | |
6436 | struct ixgbe_tx_buffer *tx_buffer_info; | |
9f8cdf4f JB |
6437 | u32 vlan_macip_lens = 0, type_tucmd_mlhl; |
6438 | u32 mss_l4len_idx, l4len; | |
9a799d71 AK |
6439 | |
6440 | if (skb_is_gso(skb)) { | |
6441 | if (skb_header_cloned(skb)) { | |
6442 | err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); | |
6443 | if (err) | |
6444 | return err; | |
6445 | } | |
6446 | l4len = tcp_hdrlen(skb); | |
6447 | *hdr_len += l4len; | |
6448 | ||
5e09a105 | 6449 | if (protocol == htons(ETH_P_IP)) { |
9a799d71 AK |
6450 | struct iphdr *iph = ip_hdr(skb); |
6451 | iph->tot_len = 0; | |
6452 | iph->check = 0; | |
6453 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, | |
e8e9f696 JP |
6454 | iph->daddr, 0, |
6455 | IPPROTO_TCP, | |
6456 | 0); | |
8e1e8a47 | 6457 | } else if (skb_is_gso_v6(skb)) { |
9a799d71 AK |
6458 | ipv6_hdr(skb)->payload_len = 0; |
6459 | tcp_hdr(skb)->check = | |
6460 | ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, | |
e8e9f696 JP |
6461 | &ipv6_hdr(skb)->daddr, |
6462 | 0, IPPROTO_TCP, 0); | |
9a799d71 AK |
6463 | } |
6464 | ||
6465 | i = tx_ring->next_to_use; | |
6466 | ||
6467 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
31f05a2d | 6468 | context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i); |
9a799d71 AK |
6469 | |
6470 | /* VLAN MACLEN IPLEN */ | |
6471 | if (tx_flags & IXGBE_TX_FLAGS_VLAN) | |
6472 | vlan_macip_lens |= | |
6473 | (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK); | |
6474 | vlan_macip_lens |= ((skb_network_offset(skb)) << | |
e8e9f696 | 6475 | IXGBE_ADVTXD_MACLEN_SHIFT); |
9a799d71 AK |
6476 | *hdr_len += skb_network_offset(skb); |
6477 | vlan_macip_lens |= | |
6478 | (skb_transport_header(skb) - skb_network_header(skb)); | |
6479 | *hdr_len += | |
6480 | (skb_transport_header(skb) - skb_network_header(skb)); | |
6481 | context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); | |
6482 | context_desc->seqnum_seed = 0; | |
6483 | ||
6484 | /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ | |
9f8cdf4f | 6485 | type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT | |
e8e9f696 | 6486 | IXGBE_ADVTXD_DTYP_CTXT); |
9a799d71 | 6487 | |
5e09a105 | 6488 | if (protocol == htons(ETH_P_IP)) |
9a799d71 AK |
6489 | type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4; |
6490 | type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP; | |
6491 | context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl); | |
6492 | ||
6493 | /* MSS L4LEN IDX */ | |
9f8cdf4f | 6494 | mss_l4len_idx = |
9a799d71 AK |
6495 | (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT); |
6496 | mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT); | |
4eeae6fd PW |
6497 | /* use index 1 for TSO */ |
6498 | mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT); | |
9a799d71 AK |
6499 | context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); |
6500 | ||
6501 | tx_buffer_info->time_stamp = jiffies; | |
6502 | tx_buffer_info->next_to_watch = i; | |
6503 | ||
6504 | i++; | |
6505 | if (i == tx_ring->count) | |
6506 | i = 0; | |
6507 | tx_ring->next_to_use = i; | |
6508 | ||
6509 | return true; | |
6510 | } | |
6511 | return false; | |
6512 | } | |
6513 | ||
5e09a105 HZ |
6514 | static u32 ixgbe_psum(struct ixgbe_adapter *adapter, struct sk_buff *skb, |
6515 | __be16 protocol) | |
7ca647bd JP |
6516 | { |
6517 | u32 rtn = 0; | |
7ca647bd JP |
6518 | |
6519 | switch (protocol) { | |
6520 | case cpu_to_be16(ETH_P_IP): | |
6521 | rtn |= IXGBE_ADVTXD_TUCMD_IPV4; | |
6522 | switch (ip_hdr(skb)->protocol) { | |
6523 | case IPPROTO_TCP: | |
6524 | rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP; | |
6525 | break; | |
6526 | case IPPROTO_SCTP: | |
6527 | rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP; | |
6528 | break; | |
6529 | } | |
6530 | break; | |
6531 | case cpu_to_be16(ETH_P_IPV6): | |
6532 | /* XXX what about other V6 headers?? */ | |
6533 | switch (ipv6_hdr(skb)->nexthdr) { | |
6534 | case IPPROTO_TCP: | |
6535 | rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP; | |
6536 | break; | |
6537 | case IPPROTO_SCTP: | |
6538 | rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP; | |
6539 | break; | |
6540 | } | |
6541 | break; | |
6542 | default: | |
6543 | if (unlikely(net_ratelimit())) | |
6544 | e_warn(probe, "partial checksum but proto=%x!\n", | |
5e09a105 | 6545 | protocol); |
7ca647bd JP |
6546 | break; |
6547 | } | |
6548 | ||
6549 | return rtn; | |
6550 | } | |
6551 | ||
9a799d71 | 6552 | static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter, |
e8e9f696 | 6553 | struct ixgbe_ring *tx_ring, |
5e09a105 HZ |
6554 | struct sk_buff *skb, u32 tx_flags, |
6555 | __be16 protocol) | |
9a799d71 AK |
6556 | { |
6557 | struct ixgbe_adv_tx_context_desc *context_desc; | |
6558 | unsigned int i; | |
6559 | struct ixgbe_tx_buffer *tx_buffer_info; | |
6560 | u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0; | |
6561 | ||
6562 | if (skb->ip_summed == CHECKSUM_PARTIAL || | |
6563 | (tx_flags & IXGBE_TX_FLAGS_VLAN)) { | |
6564 | i = tx_ring->next_to_use; | |
6565 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
31f05a2d | 6566 | context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i); |
9a799d71 AK |
6567 | |
6568 | if (tx_flags & IXGBE_TX_FLAGS_VLAN) | |
6569 | vlan_macip_lens |= | |
6570 | (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK); | |
6571 | vlan_macip_lens |= (skb_network_offset(skb) << | |
e8e9f696 | 6572 | IXGBE_ADVTXD_MACLEN_SHIFT); |
9a799d71 AK |
6573 | if (skb->ip_summed == CHECKSUM_PARTIAL) |
6574 | vlan_macip_lens |= (skb_transport_header(skb) - | |
e8e9f696 | 6575 | skb_network_header(skb)); |
9a799d71 AK |
6576 | |
6577 | context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); | |
6578 | context_desc->seqnum_seed = 0; | |
6579 | ||
6580 | type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT | | |
e8e9f696 | 6581 | IXGBE_ADVTXD_DTYP_CTXT); |
9a799d71 | 6582 | |
7ca647bd | 6583 | if (skb->ip_summed == CHECKSUM_PARTIAL) |
5e09a105 | 6584 | type_tucmd_mlhl |= ixgbe_psum(adapter, skb, protocol); |
9a799d71 AK |
6585 | |
6586 | context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl); | |
4eeae6fd | 6587 | /* use index zero for tx checksum offload */ |
9a799d71 AK |
6588 | context_desc->mss_l4len_idx = 0; |
6589 | ||
6590 | tx_buffer_info->time_stamp = jiffies; | |
6591 | tx_buffer_info->next_to_watch = i; | |
9f8cdf4f | 6592 | |
9a799d71 AK |
6593 | i++; |
6594 | if (i == tx_ring->count) | |
6595 | i = 0; | |
6596 | tx_ring->next_to_use = i; | |
6597 | ||
6598 | return true; | |
6599 | } | |
9f8cdf4f | 6600 | |
9a799d71 AK |
6601 | return false; |
6602 | } | |
6603 | ||
6604 | static int ixgbe_tx_map(struct ixgbe_adapter *adapter, | |
e8e9f696 JP |
6605 | struct ixgbe_ring *tx_ring, |
6606 | struct sk_buff *skb, u32 tx_flags, | |
8ad494b0 | 6607 | unsigned int first, const u8 hdr_len) |
9a799d71 | 6608 | { |
b6ec895e | 6609 | struct device *dev = tx_ring->dev; |
9a799d71 | 6610 | struct ixgbe_tx_buffer *tx_buffer_info; |
eacd73f7 YZ |
6611 | unsigned int len; |
6612 | unsigned int total = skb->len; | |
9a799d71 AK |
6613 | unsigned int offset = 0, size, count = 0, i; |
6614 | unsigned int nr_frags = skb_shinfo(skb)->nr_frags; | |
6615 | unsigned int f; | |
8ad494b0 AD |
6616 | unsigned int bytecount = skb->len; |
6617 | u16 gso_segs = 1; | |
9a799d71 AK |
6618 | |
6619 | i = tx_ring->next_to_use; | |
6620 | ||
eacd73f7 YZ |
6621 | if (tx_flags & IXGBE_TX_FLAGS_FCOE) |
6622 | /* excluding fcoe_crc_eof for FCoE */ | |
6623 | total -= sizeof(struct fcoe_crc_eof); | |
6624 | ||
6625 | len = min(skb_headlen(skb), total); | |
9a799d71 AK |
6626 | while (len) { |
6627 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
6628 | size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD); | |
6629 | ||
6630 | tx_buffer_info->length = size; | |
e5a43549 | 6631 | tx_buffer_info->mapped_as_page = false; |
b6ec895e | 6632 | tx_buffer_info->dma = dma_map_single(dev, |
e5a43549 | 6633 | skb->data + offset, |
1b507730 | 6634 | size, DMA_TO_DEVICE); |
b6ec895e | 6635 | if (dma_mapping_error(dev, tx_buffer_info->dma)) |
e5a43549 | 6636 | goto dma_error; |
9a799d71 AK |
6637 | tx_buffer_info->time_stamp = jiffies; |
6638 | tx_buffer_info->next_to_watch = i; | |
6639 | ||
6640 | len -= size; | |
eacd73f7 | 6641 | total -= size; |
9a799d71 AK |
6642 | offset += size; |
6643 | count++; | |
44df32c5 AD |
6644 | |
6645 | if (len) { | |
6646 | i++; | |
6647 | if (i == tx_ring->count) | |
6648 | i = 0; | |
6649 | } | |
9a799d71 AK |
6650 | } |
6651 | ||
6652 | for (f = 0; f < nr_frags; f++) { | |
6653 | struct skb_frag_struct *frag; | |
6654 | ||
6655 | frag = &skb_shinfo(skb)->frags[f]; | |
eacd73f7 | 6656 | len = min((unsigned int)frag->size, total); |
e5a43549 | 6657 | offset = frag->page_offset; |
9a799d71 AK |
6658 | |
6659 | while (len) { | |
44df32c5 AD |
6660 | i++; |
6661 | if (i == tx_ring->count) | |
6662 | i = 0; | |
6663 | ||
9a799d71 AK |
6664 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; |
6665 | size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD); | |
6666 | ||
6667 | tx_buffer_info->length = size; | |
b6ec895e | 6668 | tx_buffer_info->dma = dma_map_page(dev, |
e5a43549 AD |
6669 | frag->page, |
6670 | offset, size, | |
1b507730 | 6671 | DMA_TO_DEVICE); |
e5a43549 | 6672 | tx_buffer_info->mapped_as_page = true; |
b6ec895e | 6673 | if (dma_mapping_error(dev, tx_buffer_info->dma)) |
e5a43549 | 6674 | goto dma_error; |
9a799d71 AK |
6675 | tx_buffer_info->time_stamp = jiffies; |
6676 | tx_buffer_info->next_to_watch = i; | |
6677 | ||
6678 | len -= size; | |
eacd73f7 | 6679 | total -= size; |
9a799d71 AK |
6680 | offset += size; |
6681 | count++; | |
9a799d71 | 6682 | } |
eacd73f7 YZ |
6683 | if (total == 0) |
6684 | break; | |
9a799d71 | 6685 | } |
44df32c5 | 6686 | |
8ad494b0 AD |
6687 | if (tx_flags & IXGBE_TX_FLAGS_TSO) |
6688 | gso_segs = skb_shinfo(skb)->gso_segs; | |
6689 | #ifdef IXGBE_FCOE | |
6690 | /* adjust for FCoE Sequence Offload */ | |
6691 | else if (tx_flags & IXGBE_TX_FLAGS_FSO) | |
6692 | gso_segs = DIV_ROUND_UP(skb->len - hdr_len, | |
6693 | skb_shinfo(skb)->gso_size); | |
6694 | #endif /* IXGBE_FCOE */ | |
6695 | bytecount += (gso_segs - 1) * hdr_len; | |
6696 | ||
6697 | /* multiply data chunks by size of headers */ | |
6698 | tx_ring->tx_buffer_info[i].bytecount = bytecount; | |
6699 | tx_ring->tx_buffer_info[i].gso_segs = gso_segs; | |
9a799d71 AK |
6700 | tx_ring->tx_buffer_info[i].skb = skb; |
6701 | tx_ring->tx_buffer_info[first].next_to_watch = i; | |
6702 | ||
e5a43549 AD |
6703 | return count; |
6704 | ||
6705 | dma_error: | |
849c4542 | 6706 | e_dev_err("TX DMA map failed\n"); |
e5a43549 AD |
6707 | |
6708 | /* clear timestamp and dma mappings for failed tx_buffer_info map */ | |
6709 | tx_buffer_info->dma = 0; | |
6710 | tx_buffer_info->time_stamp = 0; | |
6711 | tx_buffer_info->next_to_watch = 0; | |
c1fa347f RK |
6712 | if (count) |
6713 | count--; | |
e5a43549 AD |
6714 | |
6715 | /* clear timestamp and dma mappings for remaining portion of packet */ | |
c1fa347f | 6716 | while (count--) { |
e8e9f696 | 6717 | if (i == 0) |
e5a43549 | 6718 | i += tx_ring->count; |
c1fa347f | 6719 | i--; |
e5a43549 | 6720 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; |
b6ec895e | 6721 | ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info); |
e5a43549 AD |
6722 | } |
6723 | ||
e44d38e1 | 6724 | return 0; |
9a799d71 AK |
6725 | } |
6726 | ||
84ea2591 | 6727 | static void ixgbe_tx_queue(struct ixgbe_ring *tx_ring, |
e8e9f696 | 6728 | int tx_flags, int count, u32 paylen, u8 hdr_len) |
9a799d71 AK |
6729 | { |
6730 | union ixgbe_adv_tx_desc *tx_desc = NULL; | |
6731 | struct ixgbe_tx_buffer *tx_buffer_info; | |
6732 | u32 olinfo_status = 0, cmd_type_len = 0; | |
6733 | unsigned int i; | |
6734 | u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS; | |
6735 | ||
6736 | cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA; | |
6737 | ||
6738 | cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT; | |
6739 | ||
6740 | if (tx_flags & IXGBE_TX_FLAGS_VLAN) | |
6741 | cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE; | |
6742 | ||
6743 | if (tx_flags & IXGBE_TX_FLAGS_TSO) { | |
6744 | cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE; | |
6745 | ||
6746 | olinfo_status |= IXGBE_TXD_POPTS_TXSM << | |
e8e9f696 | 6747 | IXGBE_ADVTXD_POPTS_SHIFT; |
9a799d71 | 6748 | |
4eeae6fd PW |
6749 | /* use index 1 context for tso */ |
6750 | olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT); | |
9a799d71 AK |
6751 | if (tx_flags & IXGBE_TX_FLAGS_IPV4) |
6752 | olinfo_status |= IXGBE_TXD_POPTS_IXSM << | |
e8e9f696 | 6753 | IXGBE_ADVTXD_POPTS_SHIFT; |
9a799d71 AK |
6754 | |
6755 | } else if (tx_flags & IXGBE_TX_FLAGS_CSUM) | |
6756 | olinfo_status |= IXGBE_TXD_POPTS_TXSM << | |
e8e9f696 | 6757 | IXGBE_ADVTXD_POPTS_SHIFT; |
9a799d71 | 6758 | |
eacd73f7 YZ |
6759 | if (tx_flags & IXGBE_TX_FLAGS_FCOE) { |
6760 | olinfo_status |= IXGBE_ADVTXD_CC; | |
6761 | olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT); | |
6762 | if (tx_flags & IXGBE_TX_FLAGS_FSO) | |
6763 | cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE; | |
6764 | } | |
6765 | ||
9a799d71 AK |
6766 | olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT); |
6767 | ||
6768 | i = tx_ring->next_to_use; | |
6769 | while (count--) { | |
6770 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
31f05a2d | 6771 | tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i); |
9a799d71 AK |
6772 | tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma); |
6773 | tx_desc->read.cmd_type_len = | |
e8e9f696 | 6774 | cpu_to_le32(cmd_type_len | tx_buffer_info->length); |
9a799d71 | 6775 | tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); |
9a799d71 AK |
6776 | i++; |
6777 | if (i == tx_ring->count) | |
6778 | i = 0; | |
6779 | } | |
6780 | ||
6781 | tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd); | |
6782 | ||
6783 | /* | |
6784 | * Force memory writes to complete before letting h/w | |
6785 | * know there are new descriptors to fetch. (Only | |
6786 | * applicable for weak-ordered memory model archs, | |
6787 | * such as IA-64). | |
6788 | */ | |
6789 | wmb(); | |
6790 | ||
6791 | tx_ring->next_to_use = i; | |
84ea2591 | 6792 | writel(i, tx_ring->tail); |
9a799d71 AK |
6793 | } |
6794 | ||
69830529 AD |
6795 | static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb, |
6796 | u32 tx_flags, __be16 protocol) | |
6797 | { | |
6798 | struct ixgbe_q_vector *q_vector = ring->q_vector; | |
6799 | union ixgbe_atr_hash_dword input = { .dword = 0 }; | |
6800 | union ixgbe_atr_hash_dword common = { .dword = 0 }; | |
6801 | union { | |
6802 | unsigned char *network; | |
6803 | struct iphdr *ipv4; | |
6804 | struct ipv6hdr *ipv6; | |
6805 | } hdr; | |
ee9e0f0b | 6806 | struct tcphdr *th; |
905e4a41 | 6807 | __be16 vlan_id; |
c4cf55e5 | 6808 | |
69830529 AD |
6809 | /* if ring doesn't have a interrupt vector, cannot perform ATR */ |
6810 | if (!q_vector) | |
6811 | return; | |
6812 | ||
6813 | /* do nothing if sampling is disabled */ | |
6814 | if (!ring->atr_sample_rate) | |
d3ead241 | 6815 | return; |
c4cf55e5 | 6816 | |
69830529 | 6817 | ring->atr_count++; |
c4cf55e5 | 6818 | |
69830529 AD |
6819 | /* snag network header to get L4 type and address */ |
6820 | hdr.network = skb_network_header(skb); | |
6821 | ||
6822 | /* Currently only IPv4/IPv6 with TCP is supported */ | |
6823 | if ((protocol != __constant_htons(ETH_P_IPV6) || | |
6824 | hdr.ipv6->nexthdr != IPPROTO_TCP) && | |
6825 | (protocol != __constant_htons(ETH_P_IP) || | |
6826 | hdr.ipv4->protocol != IPPROTO_TCP)) | |
6827 | return; | |
ee9e0f0b AD |
6828 | |
6829 | th = tcp_hdr(skb); | |
c4cf55e5 | 6830 | |
69830529 AD |
6831 | /* skip this packet since the socket is closing */ |
6832 | if (th->fin) | |
6833 | return; | |
6834 | ||
6835 | /* sample on all syn packets or once every atr sample count */ | |
6836 | if (!th->syn && (ring->atr_count < ring->atr_sample_rate)) | |
6837 | return; | |
6838 | ||
6839 | /* reset sample count */ | |
6840 | ring->atr_count = 0; | |
6841 | ||
6842 | vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT); | |
6843 | ||
6844 | /* | |
6845 | * src and dst are inverted, think how the receiver sees them | |
6846 | * | |
6847 | * The input is broken into two sections, a non-compressed section | |
6848 | * containing vm_pool, vlan_id, and flow_type. The rest of the data | |
6849 | * is XORed together and stored in the compressed dword. | |
6850 | */ | |
6851 | input.formatted.vlan_id = vlan_id; | |
6852 | ||
6853 | /* | |
6854 | * since src port and flex bytes occupy the same word XOR them together | |
6855 | * and write the value to source port portion of compressed dword | |
6856 | */ | |
6857 | if (vlan_id) | |
6858 | common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q); | |
6859 | else | |
6860 | common.port.src ^= th->dest ^ protocol; | |
6861 | common.port.dst ^= th->source; | |
6862 | ||
6863 | if (protocol == __constant_htons(ETH_P_IP)) { | |
6864 | input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; | |
6865 | common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr; | |
6866 | } else { | |
6867 | input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6; | |
6868 | common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^ | |
6869 | hdr.ipv6->saddr.s6_addr32[1] ^ | |
6870 | hdr.ipv6->saddr.s6_addr32[2] ^ | |
6871 | hdr.ipv6->saddr.s6_addr32[3] ^ | |
6872 | hdr.ipv6->daddr.s6_addr32[0] ^ | |
6873 | hdr.ipv6->daddr.s6_addr32[1] ^ | |
6874 | hdr.ipv6->daddr.s6_addr32[2] ^ | |
6875 | hdr.ipv6->daddr.s6_addr32[3]; | |
6876 | } | |
c4cf55e5 PWJ |
6877 | |
6878 | /* This assumes the Rx queue and Tx queue are bound to the same CPU */ | |
69830529 AD |
6879 | ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw, |
6880 | input, common, ring->queue_index); | |
c4cf55e5 PWJ |
6881 | } |
6882 | ||
fc77dc3c | 6883 | static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size) |
e092be60 | 6884 | { |
fc77dc3c | 6885 | netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); |
e092be60 AV |
6886 | /* Herbert's original patch had: |
6887 | * smp_mb__after_netif_stop_queue(); | |
6888 | * but since that doesn't exist yet, just open code it. */ | |
6889 | smp_mb(); | |
6890 | ||
6891 | /* We need to check again in a case another CPU has just | |
6892 | * made room available. */ | |
6893 | if (likely(IXGBE_DESC_UNUSED(tx_ring) < size)) | |
6894 | return -EBUSY; | |
6895 | ||
6896 | /* A reprieve! - use start_queue because it doesn't call schedule */ | |
fc77dc3c | 6897 | netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); |
5b7da515 | 6898 | ++tx_ring->tx_stats.restart_queue; |
e092be60 AV |
6899 | return 0; |
6900 | } | |
6901 | ||
fc77dc3c | 6902 | static int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size) |
e092be60 AV |
6903 | { |
6904 | if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size)) | |
6905 | return 0; | |
fc77dc3c | 6906 | return __ixgbe_maybe_stop_tx(tx_ring, size); |
e092be60 AV |
6907 | } |
6908 | ||
09a3b1f8 SH |
6909 | static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb) |
6910 | { | |
6911 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
5f715823 | 6912 | int txq = smp_processor_id(); |
56075a98 | 6913 | #ifdef IXGBE_FCOE |
5e09a105 HZ |
6914 | __be16 protocol; |
6915 | ||
6916 | protocol = vlan_get_protocol(skb); | |
6917 | ||
e5b64635 JF |
6918 | if (((protocol == htons(ETH_P_FCOE)) || |
6919 | (protocol == htons(ETH_P_FIP))) && | |
6920 | (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) { | |
6921 | txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1); | |
6922 | txq += adapter->ring_feature[RING_F_FCOE].mask; | |
6923 | return txq; | |
56075a98 JF |
6924 | } |
6925 | #endif | |
6926 | ||
fdd3d631 KK |
6927 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { |
6928 | while (unlikely(txq >= dev->real_num_tx_queues)) | |
6929 | txq -= dev->real_num_tx_queues; | |
5f715823 | 6930 | return txq; |
fdd3d631 | 6931 | } |
c4cf55e5 | 6932 | |
09a3b1f8 SH |
6933 | return skb_tx_hash(dev, skb); |
6934 | } | |
6935 | ||
fc77dc3c | 6936 | netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, |
84418e3b AD |
6937 | struct ixgbe_adapter *adapter, |
6938 | struct ixgbe_ring *tx_ring) | |
9a799d71 | 6939 | { |
9a799d71 AK |
6940 | unsigned int first; |
6941 | unsigned int tx_flags = 0; | |
30eba97a | 6942 | u8 hdr_len = 0; |
5f715823 | 6943 | int tso; |
9a799d71 AK |
6944 | int count = 0; |
6945 | unsigned int f; | |
5e09a105 HZ |
6946 | __be16 protocol; |
6947 | ||
6948 | protocol = vlan_get_protocol(skb); | |
9f8cdf4f | 6949 | |
eab6d18d | 6950 | if (vlan_tx_tag_present(skb)) { |
9f8cdf4f | 6951 | tx_flags |= vlan_tx_tag_get(skb); |
2f90b865 AD |
6952 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { |
6953 | tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK; | |
e5b64635 | 6954 | tx_flags |= tx_ring->dcb_tc << 13; |
2f90b865 AD |
6955 | } |
6956 | tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT; | |
6957 | tx_flags |= IXGBE_TX_FLAGS_VLAN; | |
33c66bd1 JF |
6958 | } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED && |
6959 | skb->priority != TC_PRIO_CONTROL) { | |
e5b64635 | 6960 | tx_flags |= tx_ring->dcb_tc << 13; |
2ea186ae JF |
6961 | tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT; |
6962 | tx_flags |= IXGBE_TX_FLAGS_VLAN; | |
9a799d71 | 6963 | } |
eacd73f7 | 6964 | |
09ad1cc0 | 6965 | #ifdef IXGBE_FCOE |
56075a98 JF |
6966 | /* for FCoE with DCB, we force the priority to what |
6967 | * was specified by the switch */ | |
6968 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED && | |
e5b64635 JF |
6969 | (protocol == htons(ETH_P_FCOE))) |
6970 | tx_flags |= IXGBE_TX_FLAGS_FCOE; | |
ca77cd59 RL |
6971 | #endif |
6972 | ||
eacd73f7 | 6973 | /* four things can cause us to need a context descriptor */ |
9f8cdf4f JB |
6974 | if (skb_is_gso(skb) || |
6975 | (skb->ip_summed == CHECKSUM_PARTIAL) || | |
eacd73f7 YZ |
6976 | (tx_flags & IXGBE_TX_FLAGS_VLAN) || |
6977 | (tx_flags & IXGBE_TX_FLAGS_FCOE)) | |
9a799d71 AK |
6978 | count++; |
6979 | ||
9f8cdf4f JB |
6980 | count += TXD_USE_COUNT(skb_headlen(skb)); |
6981 | for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) | |
9a799d71 AK |
6982 | count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); |
6983 | ||
fc77dc3c | 6984 | if (ixgbe_maybe_stop_tx(tx_ring, count)) { |
5b7da515 | 6985 | tx_ring->tx_stats.tx_busy++; |
9a799d71 AK |
6986 | return NETDEV_TX_BUSY; |
6987 | } | |
9a799d71 | 6988 | |
9a799d71 | 6989 | first = tx_ring->next_to_use; |
eacd73f7 YZ |
6990 | if (tx_flags & IXGBE_TX_FLAGS_FCOE) { |
6991 | #ifdef IXGBE_FCOE | |
6992 | /* setup tx offload for FCoE */ | |
6993 | tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len); | |
6994 | if (tso < 0) { | |
6995 | dev_kfree_skb_any(skb); | |
6996 | return NETDEV_TX_OK; | |
6997 | } | |
6998 | if (tso) | |
6999 | tx_flags |= IXGBE_TX_FLAGS_FSO; | |
7000 | #endif /* IXGBE_FCOE */ | |
7001 | } else { | |
5e09a105 | 7002 | if (protocol == htons(ETH_P_IP)) |
eacd73f7 | 7003 | tx_flags |= IXGBE_TX_FLAGS_IPV4; |
5e09a105 HZ |
7004 | tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len, |
7005 | protocol); | |
eacd73f7 YZ |
7006 | if (tso < 0) { |
7007 | dev_kfree_skb_any(skb); | |
7008 | return NETDEV_TX_OK; | |
7009 | } | |
9a799d71 | 7010 | |
eacd73f7 YZ |
7011 | if (tso) |
7012 | tx_flags |= IXGBE_TX_FLAGS_TSO; | |
5e09a105 HZ |
7013 | else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags, |
7014 | protocol) && | |
eacd73f7 YZ |
7015 | (skb->ip_summed == CHECKSUM_PARTIAL)) |
7016 | tx_flags |= IXGBE_TX_FLAGS_CSUM; | |
7017 | } | |
9a799d71 | 7018 | |
8ad494b0 | 7019 | count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first, hdr_len); |
44df32c5 | 7020 | if (count) { |
c4cf55e5 | 7021 | /* add the ATR filter if ATR is on */ |
69830529 AD |
7022 | if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state)) |
7023 | ixgbe_atr(tx_ring, skb, tx_flags, protocol); | |
84ea2591 | 7024 | ixgbe_tx_queue(tx_ring, tx_flags, count, skb->len, hdr_len); |
fc77dc3c | 7025 | ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED); |
9a799d71 | 7026 | |
44df32c5 AD |
7027 | } else { |
7028 | dev_kfree_skb_any(skb); | |
7029 | tx_ring->tx_buffer_info[first].time_stamp = 0; | |
7030 | tx_ring->next_to_use = first; | |
7031 | } | |
9a799d71 AK |
7032 | |
7033 | return NETDEV_TX_OK; | |
7034 | } | |
7035 | ||
84418e3b AD |
7036 | static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev) |
7037 | { | |
7038 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
7039 | struct ixgbe_ring *tx_ring; | |
7040 | ||
7041 | tx_ring = adapter->tx_ring[skb->queue_mapping]; | |
fc77dc3c | 7042 | return ixgbe_xmit_frame_ring(skb, adapter, tx_ring); |
84418e3b AD |
7043 | } |
7044 | ||
9a799d71 AK |
7045 | /** |
7046 | * ixgbe_set_mac - Change the Ethernet Address of the NIC | |
7047 | * @netdev: network interface device structure | |
7048 | * @p: pointer to an address structure | |
7049 | * | |
7050 | * Returns 0 on success, negative on failure | |
7051 | **/ | |
7052 | static int ixgbe_set_mac(struct net_device *netdev, void *p) | |
7053 | { | |
7054 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
b4617240 | 7055 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 AK |
7056 | struct sockaddr *addr = p; |
7057 | ||
7058 | if (!is_valid_ether_addr(addr->sa_data)) | |
7059 | return -EADDRNOTAVAIL; | |
7060 | ||
7061 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | |
b4617240 | 7062 | memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); |
9a799d71 | 7063 | |
1cdd1ec8 GR |
7064 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs, |
7065 | IXGBE_RAH_AV); | |
9a799d71 AK |
7066 | |
7067 | return 0; | |
7068 | } | |
7069 | ||
6b73e10d BH |
7070 | static int |
7071 | ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr) | |
7072 | { | |
7073 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
7074 | struct ixgbe_hw *hw = &adapter->hw; | |
7075 | u16 value; | |
7076 | int rc; | |
7077 | ||
7078 | if (prtad != hw->phy.mdio.prtad) | |
7079 | return -EINVAL; | |
7080 | rc = hw->phy.ops.read_reg(hw, addr, devad, &value); | |
7081 | if (!rc) | |
7082 | rc = value; | |
7083 | return rc; | |
7084 | } | |
7085 | ||
7086 | static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad, | |
7087 | u16 addr, u16 value) | |
7088 | { | |
7089 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
7090 | struct ixgbe_hw *hw = &adapter->hw; | |
7091 | ||
7092 | if (prtad != hw->phy.mdio.prtad) | |
7093 | return -EINVAL; | |
7094 | return hw->phy.ops.write_reg(hw, addr, devad, value); | |
7095 | } | |
7096 | ||
7097 | static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) | |
7098 | { | |
7099 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
7100 | ||
7101 | return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd); | |
7102 | } | |
7103 | ||
0365e6e4 PW |
7104 | /** |
7105 | * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding | |
31278e71 | 7106 | * netdev->dev_addrs |
0365e6e4 PW |
7107 | * @netdev: network interface device structure |
7108 | * | |
7109 | * Returns non-zero on failure | |
7110 | **/ | |
7111 | static int ixgbe_add_sanmac_netdev(struct net_device *dev) | |
7112 | { | |
7113 | int err = 0; | |
7114 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
7115 | struct ixgbe_mac_info *mac = &adapter->hw.mac; | |
7116 | ||
7117 | if (is_valid_ether_addr(mac->san_addr)) { | |
7118 | rtnl_lock(); | |
7119 | err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); | |
7120 | rtnl_unlock(); | |
7121 | } | |
7122 | return err; | |
7123 | } | |
7124 | ||
7125 | /** | |
7126 | * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding | |
31278e71 | 7127 | * netdev->dev_addrs |
0365e6e4 PW |
7128 | * @netdev: network interface device structure |
7129 | * | |
7130 | * Returns non-zero on failure | |
7131 | **/ | |
7132 | static int ixgbe_del_sanmac_netdev(struct net_device *dev) | |
7133 | { | |
7134 | int err = 0; | |
7135 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
7136 | struct ixgbe_mac_info *mac = &adapter->hw.mac; | |
7137 | ||
7138 | if (is_valid_ether_addr(mac->san_addr)) { | |
7139 | rtnl_lock(); | |
7140 | err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); | |
7141 | rtnl_unlock(); | |
7142 | } | |
7143 | return err; | |
7144 | } | |
7145 | ||
9a799d71 AK |
7146 | #ifdef CONFIG_NET_POLL_CONTROLLER |
7147 | /* | |
7148 | * Polling 'interrupt' - used by things like netconsole to send skbs | |
7149 | * without having to re-enable interrupts. It's not called while | |
7150 | * the interrupt routine is executing. | |
7151 | */ | |
7152 | static void ixgbe_netpoll(struct net_device *netdev) | |
7153 | { | |
7154 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
8f9a7167 | 7155 | int i; |
9a799d71 | 7156 | |
1a647bd2 AD |
7157 | /* if interface is down do nothing */ |
7158 | if (test_bit(__IXGBE_DOWN, &adapter->state)) | |
7159 | return; | |
7160 | ||
9a799d71 | 7161 | adapter->flags |= IXGBE_FLAG_IN_NETPOLL; |
8f9a7167 PWJ |
7162 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
7163 | int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
7164 | for (i = 0; i < num_q_vectors; i++) { | |
7165 | struct ixgbe_q_vector *q_vector = adapter->q_vector[i]; | |
7166 | ixgbe_msix_clean_many(0, q_vector); | |
7167 | } | |
7168 | } else { | |
7169 | ixgbe_intr(adapter->pdev->irq, netdev); | |
7170 | } | |
9a799d71 | 7171 | adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL; |
9a799d71 AK |
7172 | } |
7173 | #endif | |
7174 | ||
de1036b1 ED |
7175 | static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev, |
7176 | struct rtnl_link_stats64 *stats) | |
7177 | { | |
7178 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
7179 | int i; | |
7180 | ||
1a51502b | 7181 | rcu_read_lock(); |
de1036b1 | 7182 | for (i = 0; i < adapter->num_rx_queues; i++) { |
1a51502b | 7183 | struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]); |
de1036b1 ED |
7184 | u64 bytes, packets; |
7185 | unsigned int start; | |
7186 | ||
1a51502b ED |
7187 | if (ring) { |
7188 | do { | |
7189 | start = u64_stats_fetch_begin_bh(&ring->syncp); | |
7190 | packets = ring->stats.packets; | |
7191 | bytes = ring->stats.bytes; | |
7192 | } while (u64_stats_fetch_retry_bh(&ring->syncp, start)); | |
7193 | stats->rx_packets += packets; | |
7194 | stats->rx_bytes += bytes; | |
7195 | } | |
de1036b1 | 7196 | } |
1ac9ad13 ED |
7197 | |
7198 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
7199 | struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]); | |
7200 | u64 bytes, packets; | |
7201 | unsigned int start; | |
7202 | ||
7203 | if (ring) { | |
7204 | do { | |
7205 | start = u64_stats_fetch_begin_bh(&ring->syncp); | |
7206 | packets = ring->stats.packets; | |
7207 | bytes = ring->stats.bytes; | |
7208 | } while (u64_stats_fetch_retry_bh(&ring->syncp, start)); | |
7209 | stats->tx_packets += packets; | |
7210 | stats->tx_bytes += bytes; | |
7211 | } | |
7212 | } | |
1a51502b | 7213 | rcu_read_unlock(); |
de1036b1 ED |
7214 | /* following stats updated by ixgbe_watchdog_task() */ |
7215 | stats->multicast = netdev->stats.multicast; | |
7216 | stats->rx_errors = netdev->stats.rx_errors; | |
7217 | stats->rx_length_errors = netdev->stats.rx_length_errors; | |
7218 | stats->rx_crc_errors = netdev->stats.rx_crc_errors; | |
7219 | stats->rx_missed_errors = netdev->stats.rx_missed_errors; | |
7220 | return stats; | |
7221 | } | |
7222 | ||
7223 | ||
0edc3527 | 7224 | static const struct net_device_ops ixgbe_netdev_ops = { |
e8e9f696 | 7225 | .ndo_open = ixgbe_open, |
0edc3527 | 7226 | .ndo_stop = ixgbe_close, |
00829823 | 7227 | .ndo_start_xmit = ixgbe_xmit_frame, |
09a3b1f8 | 7228 | .ndo_select_queue = ixgbe_select_queue, |
e90d400c | 7229 | .ndo_set_rx_mode = ixgbe_set_rx_mode, |
0edc3527 SH |
7230 | .ndo_set_multicast_list = ixgbe_set_rx_mode, |
7231 | .ndo_validate_addr = eth_validate_addr, | |
7232 | .ndo_set_mac_address = ixgbe_set_mac, | |
7233 | .ndo_change_mtu = ixgbe_change_mtu, | |
7234 | .ndo_tx_timeout = ixgbe_tx_timeout, | |
0edc3527 SH |
7235 | .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid, |
7236 | .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid, | |
6b73e10d | 7237 | .ndo_do_ioctl = ixgbe_ioctl, |
7f01648a GR |
7238 | .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac, |
7239 | .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan, | |
7240 | .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw, | |
7241 | .ndo_get_vf_config = ixgbe_ndo_get_vf_config, | |
de1036b1 | 7242 | .ndo_get_stats64 = ixgbe_get_stats64, |
24095aa3 JF |
7243 | #ifdef CONFIG_IXGBE_DCB |
7244 | .ndo_setup_tc = ixgbe_setup_tc, | |
7245 | #endif | |
0edc3527 SH |
7246 | #ifdef CONFIG_NET_POLL_CONTROLLER |
7247 | .ndo_poll_controller = ixgbe_netpoll, | |
7248 | #endif | |
332d4a7d YZ |
7249 | #ifdef IXGBE_FCOE |
7250 | .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get, | |
68a683cf | 7251 | .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target, |
332d4a7d | 7252 | .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put, |
8450ff8c YZ |
7253 | .ndo_fcoe_enable = ixgbe_fcoe_enable, |
7254 | .ndo_fcoe_disable = ixgbe_fcoe_disable, | |
61a1fa10 | 7255 | .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn, |
332d4a7d | 7256 | #endif /* IXGBE_FCOE */ |
0edc3527 SH |
7257 | }; |
7258 | ||
1cdd1ec8 GR |
7259 | static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter, |
7260 | const struct ixgbe_info *ii) | |
7261 | { | |
7262 | #ifdef CONFIG_PCI_IOV | |
7263 | struct ixgbe_hw *hw = &adapter->hw; | |
7264 | int err; | |
a1cbb15c GR |
7265 | int num_vf_macvlans, i; |
7266 | struct vf_macvlans *mv_list; | |
1cdd1ec8 | 7267 | |
3377eba7 | 7268 | if (hw->mac.type == ixgbe_mac_82598EB || !max_vfs) |
1cdd1ec8 GR |
7269 | return; |
7270 | ||
7271 | /* The 82599 supports up to 64 VFs per physical function | |
7272 | * but this implementation limits allocation to 63 so that | |
7273 | * basic networking resources are still available to the | |
7274 | * physical function | |
7275 | */ | |
7276 | adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs; | |
7277 | adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED; | |
7278 | err = pci_enable_sriov(adapter->pdev, adapter->num_vfs); | |
7279 | if (err) { | |
396e799c | 7280 | e_err(probe, "Failed to enable PCI sriov: %d\n", err); |
1cdd1ec8 GR |
7281 | goto err_novfs; |
7282 | } | |
a1cbb15c GR |
7283 | |
7284 | num_vf_macvlans = hw->mac.num_rar_entries - | |
7285 | (IXGBE_MAX_PF_MACVLANS + 1 + adapter->num_vfs); | |
7286 | ||
7287 | adapter->mv_list = mv_list = kcalloc(num_vf_macvlans, | |
7288 | sizeof(struct vf_macvlans), | |
7289 | GFP_KERNEL); | |
7290 | if (mv_list) { | |
7291 | /* Initialize list of VF macvlans */ | |
7292 | INIT_LIST_HEAD(&adapter->vf_mvs.l); | |
7293 | for (i = 0; i < num_vf_macvlans; i++) { | |
7294 | mv_list->vf = -1; | |
7295 | mv_list->free = true; | |
7296 | mv_list->rar_entry = hw->mac.num_rar_entries - | |
7297 | (i + adapter->num_vfs + 1); | |
7298 | list_add(&mv_list->l, &adapter->vf_mvs.l); | |
7299 | mv_list++; | |
7300 | } | |
7301 | } | |
7302 | ||
1cdd1ec8 GR |
7303 | /* If call to enable VFs succeeded then allocate memory |
7304 | * for per VF control structures. | |
7305 | */ | |
7306 | adapter->vfinfo = | |
7307 | kcalloc(adapter->num_vfs, | |
7308 | sizeof(struct vf_data_storage), GFP_KERNEL); | |
7309 | if (adapter->vfinfo) { | |
7310 | /* Now that we're sure SR-IOV is enabled | |
7311 | * and memory allocated set up the mailbox parameters | |
7312 | */ | |
7313 | ixgbe_init_mbx_params_pf(hw); | |
7314 | memcpy(&hw->mbx.ops, ii->mbx_ops, | |
7315 | sizeof(hw->mbx.ops)); | |
7316 | ||
7317 | /* Disable RSC when in SR-IOV mode */ | |
7318 | adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE | | |
7319 | IXGBE_FLAG2_RSC_ENABLED); | |
7320 | return; | |
7321 | } | |
7322 | ||
7323 | /* Oh oh */ | |
396e799c ET |
7324 | e_err(probe, "Unable to allocate memory for VF Data Storage - " |
7325 | "SRIOV disabled\n"); | |
1cdd1ec8 GR |
7326 | pci_disable_sriov(adapter->pdev); |
7327 | ||
7328 | err_novfs: | |
7329 | adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED; | |
7330 | adapter->num_vfs = 0; | |
7331 | #endif /* CONFIG_PCI_IOV */ | |
7332 | } | |
7333 | ||
9a799d71 AK |
7334 | /** |
7335 | * ixgbe_probe - Device Initialization Routine | |
7336 | * @pdev: PCI device information struct | |
7337 | * @ent: entry in ixgbe_pci_tbl | |
7338 | * | |
7339 | * Returns 0 on success, negative on failure | |
7340 | * | |
7341 | * ixgbe_probe initializes an adapter identified by a pci_dev structure. | |
7342 | * The OS initialization, configuring of the adapter private structure, | |
7343 | * and a hardware reset occur. | |
7344 | **/ | |
7345 | static int __devinit ixgbe_probe(struct pci_dev *pdev, | |
e8e9f696 | 7346 | const struct pci_device_id *ent) |
9a799d71 AK |
7347 | { |
7348 | struct net_device *netdev; | |
7349 | struct ixgbe_adapter *adapter = NULL; | |
7350 | struct ixgbe_hw *hw; | |
7351 | const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data]; | |
9a799d71 AK |
7352 | static int cards_found; |
7353 | int i, err, pci_using_dac; | |
289700db | 7354 | u8 part_str[IXGBE_PBANUM_LENGTH]; |
c85a2618 | 7355 | unsigned int indices = num_possible_cpus(); |
eacd73f7 YZ |
7356 | #ifdef IXGBE_FCOE |
7357 | u16 device_caps; | |
7358 | #endif | |
289700db | 7359 | u32 eec; |
9a799d71 | 7360 | |
bded64a7 AG |
7361 | /* Catch broken hardware that put the wrong VF device ID in |
7362 | * the PCIe SR-IOV capability. | |
7363 | */ | |
7364 | if (pdev->is_virtfn) { | |
7365 | WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", | |
7366 | pci_name(pdev), pdev->vendor, pdev->device); | |
7367 | return -EINVAL; | |
7368 | } | |
7369 | ||
9ce77666 | 7370 | err = pci_enable_device_mem(pdev); |
9a799d71 AK |
7371 | if (err) |
7372 | return err; | |
7373 | ||
1b507730 NN |
7374 | if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) && |
7375 | !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) { | |
9a799d71 AK |
7376 | pci_using_dac = 1; |
7377 | } else { | |
1b507730 | 7378 | err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); |
9a799d71 | 7379 | if (err) { |
1b507730 NN |
7380 | err = dma_set_coherent_mask(&pdev->dev, |
7381 | DMA_BIT_MASK(32)); | |
9a799d71 | 7382 | if (err) { |
b8bc0421 DC |
7383 | dev_err(&pdev->dev, |
7384 | "No usable DMA configuration, aborting\n"); | |
9a799d71 AK |
7385 | goto err_dma; |
7386 | } | |
7387 | } | |
7388 | pci_using_dac = 0; | |
7389 | } | |
7390 | ||
9ce77666 | 7391 | err = pci_request_selected_regions(pdev, pci_select_bars(pdev, |
e8e9f696 | 7392 | IORESOURCE_MEM), ixgbe_driver_name); |
9a799d71 | 7393 | if (err) { |
b8bc0421 DC |
7394 | dev_err(&pdev->dev, |
7395 | "pci_request_selected_regions failed 0x%x\n", err); | |
9a799d71 AK |
7396 | goto err_pci_reg; |
7397 | } | |
7398 | ||
19d5afd4 | 7399 | pci_enable_pcie_error_reporting(pdev); |
6fabd715 | 7400 | |
9a799d71 | 7401 | pci_set_master(pdev); |
fb3b27bc | 7402 | pci_save_state(pdev); |
9a799d71 | 7403 | |
c85a2618 JF |
7404 | if (ii->mac == ixgbe_mac_82598EB) |
7405 | indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES); | |
7406 | else | |
7407 | indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES); | |
7408 | ||
e5b64635 | 7409 | #if defined(CONFIG_DCB) |
c85a2618 | 7410 | indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES); |
e5b64635 | 7411 | #elif defined(IXGBE_FCOE) |
c85a2618 JF |
7412 | indices += min_t(unsigned int, num_possible_cpus(), |
7413 | IXGBE_MAX_FCOE_INDICES); | |
7414 | #endif | |
c85a2618 | 7415 | netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices); |
9a799d71 AK |
7416 | if (!netdev) { |
7417 | err = -ENOMEM; | |
7418 | goto err_alloc_etherdev; | |
7419 | } | |
7420 | ||
9a799d71 AK |
7421 | SET_NETDEV_DEV(netdev, &pdev->dev); |
7422 | ||
9a799d71 | 7423 | adapter = netdev_priv(netdev); |
c60fbb00 | 7424 | pci_set_drvdata(pdev, adapter); |
9a799d71 AK |
7425 | |
7426 | adapter->netdev = netdev; | |
7427 | adapter->pdev = pdev; | |
7428 | hw = &adapter->hw; | |
7429 | hw->back = adapter; | |
7430 | adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1; | |
7431 | ||
05857980 | 7432 | hw->hw_addr = ioremap(pci_resource_start(pdev, 0), |
e8e9f696 | 7433 | pci_resource_len(pdev, 0)); |
9a799d71 AK |
7434 | if (!hw->hw_addr) { |
7435 | err = -EIO; | |
7436 | goto err_ioremap; | |
7437 | } | |
7438 | ||
7439 | for (i = 1; i <= 5; i++) { | |
7440 | if (pci_resource_len(pdev, i) == 0) | |
7441 | continue; | |
7442 | } | |
7443 | ||
0edc3527 | 7444 | netdev->netdev_ops = &ixgbe_netdev_ops; |
9a799d71 | 7445 | ixgbe_set_ethtool_ops(netdev); |
9a799d71 | 7446 | netdev->watchdog_timeo = 5 * HZ; |
9fe93afd | 7447 | strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); |
9a799d71 | 7448 | |
9a799d71 AK |
7449 | adapter->bd_number = cards_found; |
7450 | ||
9a799d71 AK |
7451 | /* Setup hw api */ |
7452 | memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops)); | |
021230d4 | 7453 | hw->mac.type = ii->mac; |
9a799d71 | 7454 | |
c44ade9e JB |
7455 | /* EEPROM */ |
7456 | memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops)); | |
7457 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); | |
7458 | /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */ | |
7459 | if (!(eec & (1 << 8))) | |
7460 | hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic; | |
7461 | ||
7462 | /* PHY */ | |
7463 | memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops)); | |
c4900be0 | 7464 | hw->phy.sfp_type = ixgbe_sfp_type_unknown; |
6b73e10d BH |
7465 | /* ixgbe_identify_phy_generic will set prtad and mmds properly */ |
7466 | hw->phy.mdio.prtad = MDIO_PRTAD_NONE; | |
7467 | hw->phy.mdio.mmds = 0; | |
7468 | hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; | |
7469 | hw->phy.mdio.dev = netdev; | |
7470 | hw->phy.mdio.mdio_read = ixgbe_mdio_read; | |
7471 | hw->phy.mdio.mdio_write = ixgbe_mdio_write; | |
c4900be0 | 7472 | |
8ca783ab | 7473 | ii->get_invariants(hw); |
9a799d71 AK |
7474 | |
7475 | /* setup the private structure */ | |
7476 | err = ixgbe_sw_init(adapter); | |
7477 | if (err) | |
7478 | goto err_sw_init; | |
7479 | ||
e86bff0e | 7480 | /* Make it possible the adapter to be woken up via WOL */ |
b93a2226 DS |
7481 | switch (adapter->hw.mac.type) { |
7482 | case ixgbe_mac_82599EB: | |
7483 | case ixgbe_mac_X540: | |
e86bff0e | 7484 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
b93a2226 DS |
7485 | break; |
7486 | default: | |
7487 | break; | |
7488 | } | |
e86bff0e | 7489 | |
bf069c97 DS |
7490 | /* |
7491 | * If there is a fan on this device and it has failed log the | |
7492 | * failure. | |
7493 | */ | |
7494 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
7495 | u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); | |
7496 | if (esdp & IXGBE_ESDP_SDP1) | |
396e799c | 7497 | e_crit(probe, "Fan has stopped, replace the adapter\n"); |
bf069c97 DS |
7498 | } |
7499 | ||
c44ade9e | 7500 | /* reset_hw fills in the perm_addr as well */ |
119fc60a | 7501 | hw->phy.reset_if_overtemp = true; |
c44ade9e | 7502 | err = hw->mac.ops.reset_hw(hw); |
119fc60a | 7503 | hw->phy.reset_if_overtemp = false; |
8ca783ab DS |
7504 | if (err == IXGBE_ERR_SFP_NOT_PRESENT && |
7505 | hw->mac.type == ixgbe_mac_82598EB) { | |
8ca783ab DS |
7506 | err = 0; |
7507 | } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
7086400d | 7508 | e_dev_err("failed to load because an unsupported SFP+ " |
849c4542 ET |
7509 | "module type was detected.\n"); |
7510 | e_dev_err("Reload the driver after installing a supported " | |
7511 | "module.\n"); | |
04f165ef PW |
7512 | goto err_sw_init; |
7513 | } else if (err) { | |
849c4542 | 7514 | e_dev_err("HW Init failed: %d\n", err); |
c44ade9e JB |
7515 | goto err_sw_init; |
7516 | } | |
7517 | ||
1cdd1ec8 GR |
7518 | ixgbe_probe_vf(adapter, ii); |
7519 | ||
396e799c | 7520 | netdev->features = NETIF_F_SG | |
e8e9f696 JP |
7521 | NETIF_F_IP_CSUM | |
7522 | NETIF_F_HW_VLAN_TX | | |
7523 | NETIF_F_HW_VLAN_RX | | |
7524 | NETIF_F_HW_VLAN_FILTER; | |
9a799d71 | 7525 | |
e9990a9c | 7526 | netdev->features |= NETIF_F_IPV6_CSUM; |
9a799d71 | 7527 | netdev->features |= NETIF_F_TSO; |
9a799d71 | 7528 | netdev->features |= NETIF_F_TSO6; |
78b6f4ce | 7529 | netdev->features |= NETIF_F_GRO; |
67a74ee2 | 7530 | netdev->features |= NETIF_F_RXHASH; |
ad31c402 | 7531 | |
58be7666 DS |
7532 | switch (adapter->hw.mac.type) { |
7533 | case ixgbe_mac_82599EB: | |
7534 | case ixgbe_mac_X540: | |
45a5ead0 | 7535 | netdev->features |= NETIF_F_SCTP_CSUM; |
58be7666 DS |
7536 | break; |
7537 | default: | |
7538 | break; | |
7539 | } | |
45a5ead0 | 7540 | |
ad31c402 JK |
7541 | netdev->vlan_features |= NETIF_F_TSO; |
7542 | netdev->vlan_features |= NETIF_F_TSO6; | |
22f32b7a | 7543 | netdev->vlan_features |= NETIF_F_IP_CSUM; |
cd1da503 | 7544 | netdev->vlan_features |= NETIF_F_IPV6_CSUM; |
ad31c402 JK |
7545 | netdev->vlan_features |= NETIF_F_SG; |
7546 | ||
1cdd1ec8 GR |
7547 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) |
7548 | adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED | | |
7549 | IXGBE_FLAG_DCB_ENABLED); | |
2f90b865 | 7550 | |
7a6b6f51 | 7551 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
7552 | netdev->dcbnl_ops = &dcbnl_ops; |
7553 | #endif | |
7554 | ||
eacd73f7 | 7555 | #ifdef IXGBE_FCOE |
0d551589 | 7556 | if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) { |
eacd73f7 YZ |
7557 | if (hw->mac.ops.get_device_caps) { |
7558 | hw->mac.ops.get_device_caps(hw, &device_caps); | |
0d551589 YZ |
7559 | if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS) |
7560 | adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; | |
eacd73f7 YZ |
7561 | } |
7562 | } | |
5e09d7f6 YZ |
7563 | if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) { |
7564 | netdev->vlan_features |= NETIF_F_FCOE_CRC; | |
7565 | netdev->vlan_features |= NETIF_F_FSO; | |
7566 | netdev->vlan_features |= NETIF_F_FCOE_MTU; | |
7567 | } | |
eacd73f7 | 7568 | #endif /* IXGBE_FCOE */ |
7b872a55 | 7569 | if (pci_using_dac) { |
9a799d71 | 7570 | netdev->features |= NETIF_F_HIGHDMA; |
7b872a55 YZ |
7571 | netdev->vlan_features |= NETIF_F_HIGHDMA; |
7572 | } | |
9a799d71 | 7573 | |
0c19d6af | 7574 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) |
f8212f97 AD |
7575 | netdev->features |= NETIF_F_LRO; |
7576 | ||
9a799d71 | 7577 | /* make sure the EEPROM is good */ |
c44ade9e | 7578 | if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) { |
849c4542 | 7579 | e_dev_err("The EEPROM Checksum Is Not Valid\n"); |
9a799d71 AK |
7580 | err = -EIO; |
7581 | goto err_eeprom; | |
7582 | } | |
7583 | ||
7584 | memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len); | |
7585 | memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len); | |
7586 | ||
c44ade9e | 7587 | if (ixgbe_validate_mac_addr(netdev->perm_addr)) { |
849c4542 | 7588 | e_dev_err("invalid MAC address\n"); |
9a799d71 AK |
7589 | err = -EIO; |
7590 | goto err_eeprom; | |
7591 | } | |
7592 | ||
c6ecf39a DS |
7593 | /* power down the optics for multispeed fiber and 82599 SFP+ fiber */ |
7594 | if (hw->mac.ops.disable_tx_laser && | |
7595 | ((hw->phy.multispeed_fiber) || | |
9f911707 | 7596 | ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) && |
c6ecf39a | 7597 | (hw->mac.type == ixgbe_mac_82599EB)))) |
61fac744 PW |
7598 | hw->mac.ops.disable_tx_laser(hw); |
7599 | ||
7086400d AD |
7600 | setup_timer(&adapter->service_timer, &ixgbe_service_timer, |
7601 | (unsigned long) adapter); | |
9a799d71 | 7602 | |
7086400d AD |
7603 | INIT_WORK(&adapter->service_task, ixgbe_service_task); |
7604 | clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); | |
9a799d71 | 7605 | |
021230d4 AV |
7606 | err = ixgbe_init_interrupt_scheme(adapter); |
7607 | if (err) | |
7608 | goto err_sw_init; | |
9a799d71 | 7609 | |
67a74ee2 ET |
7610 | if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) |
7611 | netdev->features &= ~NETIF_F_RXHASH; | |
7612 | ||
e8e26350 | 7613 | switch (pdev->device) { |
0b077fea DS |
7614 | case IXGBE_DEV_ID_82599_SFP: |
7615 | /* Only this subdevice supports WOL */ | |
7616 | if (pdev->subsystem_device == IXGBE_SUBDEV_ID_82599_SFP) | |
7617 | adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX | | |
7618 | IXGBE_WUFC_MC | IXGBE_WUFC_BC); | |
7619 | break; | |
50d6c681 AD |
7620 | case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: |
7621 | /* All except this subdevice support WOL */ | |
0b077fea DS |
7622 | if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) |
7623 | adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX | | |
7624 | IXGBE_WUFC_MC | IXGBE_WUFC_BC); | |
7625 | break; | |
e8e26350 | 7626 | case IXGBE_DEV_ID_82599_KX4: |
495dce12 | 7627 | adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX | |
e8e9f696 | 7628 | IXGBE_WUFC_MC | IXGBE_WUFC_BC); |
e8e26350 PW |
7629 | break; |
7630 | default: | |
7631 | adapter->wol = 0; | |
7632 | break; | |
7633 | } | |
e8e26350 PW |
7634 | device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); |
7635 | ||
04f165ef PW |
7636 | /* pick up the PCI bus settings for reporting later */ |
7637 | hw->mac.ops.get_bus_info(hw); | |
7638 | ||
9a799d71 | 7639 | /* print bus type/speed/width info */ |
849c4542 | 7640 | e_dev_info("(PCI Express:%s:%s) %pM\n", |
6716344c DS |
7641 | (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" : |
7642 | hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" : | |
e8e9f696 JP |
7643 | "Unknown"), |
7644 | (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" : | |
7645 | hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" : | |
7646 | hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" : | |
7647 | "Unknown"), | |
7648 | netdev->dev_addr); | |
289700db DS |
7649 | |
7650 | err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH); | |
7651 | if (err) | |
9fe93afd | 7652 | strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH); |
e8e26350 | 7653 | if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) |
289700db | 7654 | e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n", |
849c4542 | 7655 | hw->mac.type, hw->phy.type, hw->phy.sfp_type, |
289700db | 7656 | part_str); |
e8e26350 | 7657 | else |
289700db DS |
7658 | e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n", |
7659 | hw->mac.type, hw->phy.type, part_str); | |
9a799d71 | 7660 | |
e8e26350 | 7661 | if (hw->bus.width <= ixgbe_bus_width_pcie_x4) { |
849c4542 ET |
7662 | e_dev_warn("PCI-Express bandwidth available for this card is " |
7663 | "not sufficient for optimal performance.\n"); | |
7664 | e_dev_warn("For optimal performance a x8 PCI-Express slot " | |
7665 | "is required.\n"); | |
0c254d86 AK |
7666 | } |
7667 | ||
34b0368c PWJ |
7668 | /* save off EEPROM version number */ |
7669 | hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version); | |
7670 | ||
9a799d71 | 7671 | /* reset the hardware with the new settings */ |
794caeb2 | 7672 | err = hw->mac.ops.start_hw(hw); |
c44ade9e | 7673 | |
794caeb2 PWJ |
7674 | if (err == IXGBE_ERR_EEPROM_VERSION) { |
7675 | /* We are running on a pre-production device, log a warning */ | |
849c4542 ET |
7676 | e_dev_warn("This device is a pre-production adapter/LOM. " |
7677 | "Please be aware there may be issues associated " | |
7678 | "with your hardware. If you are experiencing " | |
7679 | "problems please contact your Intel or hardware " | |
7680 | "representative who provided you with this " | |
7681 | "hardware.\n"); | |
794caeb2 | 7682 | } |
9a799d71 AK |
7683 | strcpy(netdev->name, "eth%d"); |
7684 | err = register_netdev(netdev); | |
7685 | if (err) | |
7686 | goto err_register; | |
7687 | ||
54386467 JB |
7688 | /* carrier off reporting is important to ethtool even BEFORE open */ |
7689 | netif_carrier_off(netdev); | |
7690 | ||
5dd2d332 | 7691 | #ifdef CONFIG_IXGBE_DCA |
652f093f | 7692 | if (dca_add_requester(&pdev->dev) == 0) { |
bd0362dd | 7693 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; |
bd0362dd JC |
7694 | ixgbe_setup_dca(adapter); |
7695 | } | |
7696 | #endif | |
1cdd1ec8 | 7697 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { |
396e799c | 7698 | e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs); |
1cdd1ec8 GR |
7699 | for (i = 0; i < adapter->num_vfs; i++) |
7700 | ixgbe_vf_configuration(pdev, (i | 0x10000000)); | |
7701 | } | |
7702 | ||
0365e6e4 PW |
7703 | /* add san mac addr to netdev */ |
7704 | ixgbe_add_sanmac_netdev(netdev); | |
9a799d71 | 7705 | |
849c4542 | 7706 | e_dev_info("Intel(R) 10 Gigabit Network Connection\n"); |
9a799d71 AK |
7707 | cards_found++; |
7708 | return 0; | |
7709 | ||
7710 | err_register: | |
5eba3699 | 7711 | ixgbe_release_hw_control(adapter); |
7a921c93 | 7712 | ixgbe_clear_interrupt_scheme(adapter); |
9a799d71 AK |
7713 | err_sw_init: |
7714 | err_eeprom: | |
1cdd1ec8 GR |
7715 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) |
7716 | ixgbe_disable_sriov(adapter); | |
7086400d | 7717 | adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; |
9a799d71 AK |
7718 | iounmap(hw->hw_addr); |
7719 | err_ioremap: | |
7720 | free_netdev(netdev); | |
7721 | err_alloc_etherdev: | |
e8e9f696 JP |
7722 | pci_release_selected_regions(pdev, |
7723 | pci_select_bars(pdev, IORESOURCE_MEM)); | |
9a799d71 AK |
7724 | err_pci_reg: |
7725 | err_dma: | |
7726 | pci_disable_device(pdev); | |
7727 | return err; | |
7728 | } | |
7729 | ||
7730 | /** | |
7731 | * ixgbe_remove - Device Removal Routine | |
7732 | * @pdev: PCI device information struct | |
7733 | * | |
7734 | * ixgbe_remove is called by the PCI subsystem to alert the driver | |
7735 | * that it should release a PCI device. The could be caused by a | |
7736 | * Hot-Plug event, or because the driver is going to be removed from | |
7737 | * memory. | |
7738 | **/ | |
7739 | static void __devexit ixgbe_remove(struct pci_dev *pdev) | |
7740 | { | |
c60fbb00 AD |
7741 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
7742 | struct net_device *netdev = adapter->netdev; | |
9a799d71 AK |
7743 | |
7744 | set_bit(__IXGBE_DOWN, &adapter->state); | |
7086400d | 7745 | cancel_work_sync(&adapter->service_task); |
9a799d71 | 7746 | |
5dd2d332 | 7747 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
7748 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { |
7749 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
7750 | dca_remove_requester(&pdev->dev); | |
7751 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); | |
7752 | } | |
7753 | ||
7754 | #endif | |
332d4a7d YZ |
7755 | #ifdef IXGBE_FCOE |
7756 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) | |
7757 | ixgbe_cleanup_fcoe(adapter); | |
7758 | ||
7759 | #endif /* IXGBE_FCOE */ | |
0365e6e4 PW |
7760 | |
7761 | /* remove the added san mac */ | |
7762 | ixgbe_del_sanmac_netdev(netdev); | |
7763 | ||
c4900be0 DS |
7764 | if (netdev->reg_state == NETREG_REGISTERED) |
7765 | unregister_netdev(netdev); | |
9a799d71 | 7766 | |
1cdd1ec8 GR |
7767 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) |
7768 | ixgbe_disable_sriov(adapter); | |
7769 | ||
7a921c93 | 7770 | ixgbe_clear_interrupt_scheme(adapter); |
5eba3699 | 7771 | |
021230d4 | 7772 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
7773 | |
7774 | iounmap(adapter->hw.hw_addr); | |
9ce77666 | 7775 | pci_release_selected_regions(pdev, pci_select_bars(pdev, |
e8e9f696 | 7776 | IORESOURCE_MEM)); |
9a799d71 | 7777 | |
849c4542 | 7778 | e_dev_info("complete\n"); |
021230d4 | 7779 | |
9a799d71 AK |
7780 | free_netdev(netdev); |
7781 | ||
19d5afd4 | 7782 | pci_disable_pcie_error_reporting(pdev); |
6fabd715 | 7783 | |
9a799d71 AK |
7784 | pci_disable_device(pdev); |
7785 | } | |
7786 | ||
7787 | /** | |
7788 | * ixgbe_io_error_detected - called when PCI error is detected | |
7789 | * @pdev: Pointer to PCI device | |
7790 | * @state: The current pci connection state | |
7791 | * | |
7792 | * This function is called after a PCI bus error affecting | |
7793 | * this device has been detected. | |
7794 | */ | |
7795 | static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev, | |
e8e9f696 | 7796 | pci_channel_state_t state) |
9a799d71 | 7797 | { |
c60fbb00 AD |
7798 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
7799 | struct net_device *netdev = adapter->netdev; | |
9a799d71 AK |
7800 | |
7801 | netif_device_detach(netdev); | |
7802 | ||
3044b8d1 BL |
7803 | if (state == pci_channel_io_perm_failure) |
7804 | return PCI_ERS_RESULT_DISCONNECT; | |
7805 | ||
9a799d71 AK |
7806 | if (netif_running(netdev)) |
7807 | ixgbe_down(adapter); | |
7808 | pci_disable_device(pdev); | |
7809 | ||
b4617240 | 7810 | /* Request a slot reset. */ |
9a799d71 AK |
7811 | return PCI_ERS_RESULT_NEED_RESET; |
7812 | } | |
7813 | ||
7814 | /** | |
7815 | * ixgbe_io_slot_reset - called after the pci bus has been reset. | |
7816 | * @pdev: Pointer to PCI device | |
7817 | * | |
7818 | * Restart the card from scratch, as if from a cold-boot. | |
7819 | */ | |
7820 | static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev) | |
7821 | { | |
c60fbb00 | 7822 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
6fabd715 PWJ |
7823 | pci_ers_result_t result; |
7824 | int err; | |
9a799d71 | 7825 | |
9ce77666 | 7826 | if (pci_enable_device_mem(pdev)) { |
396e799c | 7827 | e_err(probe, "Cannot re-enable PCI device after reset.\n"); |
6fabd715 PWJ |
7828 | result = PCI_ERS_RESULT_DISCONNECT; |
7829 | } else { | |
7830 | pci_set_master(pdev); | |
7831 | pci_restore_state(pdev); | |
c0e1f68b | 7832 | pci_save_state(pdev); |
9a799d71 | 7833 | |
dd4d8ca6 | 7834 | pci_wake_from_d3(pdev, false); |
9a799d71 | 7835 | |
6fabd715 | 7836 | ixgbe_reset(adapter); |
88512539 | 7837 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
6fabd715 PWJ |
7838 | result = PCI_ERS_RESULT_RECOVERED; |
7839 | } | |
7840 | ||
7841 | err = pci_cleanup_aer_uncorrect_error_status(pdev); | |
7842 | if (err) { | |
849c4542 ET |
7843 | e_dev_err("pci_cleanup_aer_uncorrect_error_status " |
7844 | "failed 0x%0x\n", err); | |
6fabd715 PWJ |
7845 | /* non-fatal, continue */ |
7846 | } | |
9a799d71 | 7847 | |
6fabd715 | 7848 | return result; |
9a799d71 AK |
7849 | } |
7850 | ||
7851 | /** | |
7852 | * ixgbe_io_resume - called when traffic can start flowing again. | |
7853 | * @pdev: Pointer to PCI device | |
7854 | * | |
7855 | * This callback is called when the error recovery driver tells us that | |
7856 | * its OK to resume normal operation. | |
7857 | */ | |
7858 | static void ixgbe_io_resume(struct pci_dev *pdev) | |
7859 | { | |
c60fbb00 AD |
7860 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
7861 | struct net_device *netdev = adapter->netdev; | |
9a799d71 AK |
7862 | |
7863 | if (netif_running(netdev)) { | |
7864 | if (ixgbe_up(adapter)) { | |
396e799c | 7865 | e_info(probe, "ixgbe_up failed after reset\n"); |
9a799d71 AK |
7866 | return; |
7867 | } | |
7868 | } | |
7869 | ||
7870 | netif_device_attach(netdev); | |
9a799d71 AK |
7871 | } |
7872 | ||
7873 | static struct pci_error_handlers ixgbe_err_handler = { | |
7874 | .error_detected = ixgbe_io_error_detected, | |
7875 | .slot_reset = ixgbe_io_slot_reset, | |
7876 | .resume = ixgbe_io_resume, | |
7877 | }; | |
7878 | ||
7879 | static struct pci_driver ixgbe_driver = { | |
7880 | .name = ixgbe_driver_name, | |
7881 | .id_table = ixgbe_pci_tbl, | |
7882 | .probe = ixgbe_probe, | |
7883 | .remove = __devexit_p(ixgbe_remove), | |
7884 | #ifdef CONFIG_PM | |
7885 | .suspend = ixgbe_suspend, | |
7886 | .resume = ixgbe_resume, | |
7887 | #endif | |
7888 | .shutdown = ixgbe_shutdown, | |
7889 | .err_handler = &ixgbe_err_handler | |
7890 | }; | |
7891 | ||
7892 | /** | |
7893 | * ixgbe_init_module - Driver Registration Routine | |
7894 | * | |
7895 | * ixgbe_init_module is the first routine called when the driver is | |
7896 | * loaded. All it does is register with the PCI subsystem. | |
7897 | **/ | |
7898 | static int __init ixgbe_init_module(void) | |
7899 | { | |
7900 | int ret; | |
c7689578 | 7901 | pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version); |
849c4542 | 7902 | pr_info("%s\n", ixgbe_copyright); |
9a799d71 | 7903 | |
5dd2d332 | 7904 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 7905 | dca_register_notify(&dca_notifier); |
bd0362dd | 7906 | #endif |
5dd2d332 | 7907 | |
9a799d71 AK |
7908 | ret = pci_register_driver(&ixgbe_driver); |
7909 | return ret; | |
7910 | } | |
b4617240 | 7911 | |
9a799d71 AK |
7912 | module_init(ixgbe_init_module); |
7913 | ||
7914 | /** | |
7915 | * ixgbe_exit_module - Driver Exit Cleanup Routine | |
7916 | * | |
7917 | * ixgbe_exit_module is called just before the driver is removed | |
7918 | * from memory. | |
7919 | **/ | |
7920 | static void __exit ixgbe_exit_module(void) | |
7921 | { | |
5dd2d332 | 7922 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
7923 | dca_unregister_notify(&dca_notifier); |
7924 | #endif | |
9a799d71 | 7925 | pci_unregister_driver(&ixgbe_driver); |
1a51502b | 7926 | rcu_barrier(); /* Wait for completion of call_rcu()'s */ |
9a799d71 | 7927 | } |
bd0362dd | 7928 | |
5dd2d332 | 7929 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 7930 | static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event, |
e8e9f696 | 7931 | void *p) |
bd0362dd JC |
7932 | { |
7933 | int ret_val; | |
7934 | ||
7935 | ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event, | |
e8e9f696 | 7936 | __ixgbe_notify_dca); |
bd0362dd JC |
7937 | |
7938 | return ret_val ? NOTIFY_BAD : NOTIFY_DONE; | |
7939 | } | |
b453368d | 7940 | |
5dd2d332 | 7941 | #endif /* CONFIG_IXGBE_DCA */ |
849c4542 | 7942 | |
9a799d71 AK |
7943 | module_exit(ixgbe_exit_module); |
7944 | ||
7945 | /* ixgbe_main.c */ |