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ixgbe: performance tweaks
[mirror_ubuntu-zesty-kernel.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
3efac5a0 4 Copyright(c) 1999 - 2009 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
60127865 37#include <linux/pkt_sched.h>
9a799d71
AK		 38#include <linux/ipv6.h>
39#include <net/checksum.h>
40#include <net/ip6_checksum.h>
41#include <linux/ethtool.h>
42#include <linux/if_vlan.h>
eacd73f7 43#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 44
45#include "ixgbe.h"
46#include "ixgbe_common.h"
ee5f784a 47#include "ixgbe_dcb_82599.h"
9a799d71
AK		 48
49char ixgbe_driver_name[] = "ixgbe";
9c8eb720 50static const char ixgbe_driver_string[] =
b4617240 51 "Intel(R) 10 Gigabit PCI Express Network Driver";
9a799d71 52
e0f4daff 53#define DRV_VERSION "2.0.44-k2"
9c8eb720 54const char ixgbe_driver_version[] = DRV_VERSION;
3efac5a0 55static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
9a799d71
AK		 56
57static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 58 [board_82598] = &ixgbe_82598_info,
e8e26350 59 [board_82599] = &ixgbe_82599_info,
9a799d71
AK		 60};
61
62/* ixgbe_pci_tbl - PCI Device ID Table
63 *
64 * Wildcard entries (PCI_ANY_ID) should come last
65 * Last entry must be all 0s
66 *
67 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
68 * Class, Class Mask, private data (not used) }
69 */
70static struct pci_device_id ixgbe_pci_tbl[] = {
1e336d0f
DS		 71 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
72 board_82598 },
9a799d71 73 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 74 board_82598 },
9a799d71 75 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 76 board_82598 },
0befdb3e
JB		 77 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
78 board_82598 },
3845bec0
PWJ		 79 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
80 board_82598 },
9a799d71 81 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 82 board_82598 },
8d792cd9
JB		 83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
84 board_82598 },
c4900be0
DS		 85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
86 board_82598 },
87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
88 board_82598 },
b95f5fcb
JB		 89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
90 board_82598 },
c4900be0
DS		 91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
92 board_82598 },
2f21bdd3
DS		 93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
94 board_82598 },
e8e26350
PW		 95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
96 board_82599 },
1fcf03e6
PWJ		 97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
98 board_82599 },
e8e26350
PW		 99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
100 board_82599 },
38ad1c8e
DS		 101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
102 board_82599 },
dbfec662
DS		 103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
104 board_82599 },
8911184f
PWJ		 105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
106 board_82599 },
312eb931
DS		 107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
108 board_82599 },
9a799d71
AK		 109
110 /* required last entry */
111 {0, }
112};
113MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
114
5dd2d332 115#ifdef CONFIG_IXGBE_DCA
bd0362dd 116static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
b4617240 117 void *p);
bd0362dd
JC		 118static struct notifier_block dca_notifier = {
119 .notifier_call = ixgbe_notify_dca,
120 .next = NULL,
121 .priority = 0
122};
123#endif
124
9a799d71
AK		 125MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
126MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
127MODULE_LICENSE("GPL");
128MODULE_VERSION(DRV_VERSION);
129
130#define DEFAULT_DEBUG_LEVEL_SHIFT 3
131
5eba3699
AV		 132static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
133{
134 u32 ctrl_ext;
135
136 /* Let firmware take over control of h/w */
137 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
138 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 139 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 140}
141
142static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
143{
144 u32 ctrl_ext;
145
146 /* Let firmware know the driver has taken over */
147 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
148 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 149 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 150}
9a799d71 151
e8e26350
PW		 152/*
153 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
154 * @adapter: pointer to adapter struct
155 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
156 * @queue: queue to map the corresponding interrupt to
157 * @msix_vector: the vector to map to the corresponding queue
158 *
159 */
160static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
161 u8 queue, u8 msix_vector)
9a799d71
AK		 162{
163 u32 ivar, index;
e8e26350
PW		 164 struct ixgbe_hw *hw = &adapter->hw;
165 switch (hw->mac.type) {
166 case ixgbe_mac_82598EB:
167 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
168 if (direction == -1)
169 direction = 0;
170 index = (((direction * 64) + queue) >> 2) & 0x1F;
171 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
172 ivar &= ~(0xFF << (8 * (queue & 0x3)));
173 ivar |= (msix_vector << (8 * (queue & 0x3)));
174 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
175 break;
176 case ixgbe_mac_82599EB:
177 if (direction == -1) {
178 /* other causes */
179 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
180 index = ((queue & 1) * 8);
181 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
182 ivar &= ~(0xFF << index);
183 ivar |= (msix_vector << index);
184 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
185 break;
186 } else {
187 /* tx or rx causes */
188 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
189 index = ((16 * (queue & 1)) + (8 * direction));
190 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
191 ivar &= ~(0xFF << index);
192 ivar |= (msix_vector << index);
193 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
194 break;
195 }
196 default:
197 break;
198 }
9a799d71
AK		 199}
200
fe49f04a
AD		 201static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
202 u64 qmask)
203{
204 u32 mask;
205
206 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
207 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
208 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
209 } else {
210 mask = (qmask & 0xFFFFFFFF);
211 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
212 mask = (qmask >> 32);
213 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
214 }
215}
216
9a799d71 217static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
b4617240
PW		 218 struct ixgbe_tx_buffer
219 *tx_buffer_info)
9a799d71 220{
e5a43549
AD		 221 if (tx_buffer_info->dma) {
222 if (tx_buffer_info->mapped_as_page)
223 pci_unmap_page(adapter->pdev,
224 tx_buffer_info->dma,
225 tx_buffer_info->length,
226 PCI_DMA_TODEVICE);
227 else
228 pci_unmap_single(adapter->pdev,
229 tx_buffer_info->dma,
230 tx_buffer_info->length,
231 PCI_DMA_TODEVICE);
232 tx_buffer_info->dma = 0;
233 }
9a799d71
AK		 234 if (tx_buffer_info->skb) {
235 dev_kfree_skb_any(tx_buffer_info->skb);
236 tx_buffer_info->skb = NULL;
237 }
44df32c5 238 tx_buffer_info->time_stamp = 0;
9a799d71
AK		 239 /* tx_buffer_info must be completely set up in the transmit path */
240}
241
26f23d82
YZ		 242/**
243 * ixgbe_tx_is_paused - check if the tx ring is paused
244 * @adapter: the ixgbe adapter
245 * @tx_ring: the corresponding tx_ring
246 *
247 * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
248 * corresponding TC of this tx_ring when checking TFCS.
249 *
250 * Returns : true if paused
251 */
252static inline bool ixgbe_tx_is_paused(struct ixgbe_adapter *adapter,
253 struct ixgbe_ring *tx_ring)
254{
26f23d82
YZ		 255 u32 txoff = IXGBE_TFCS_TXOFF;
256
257#ifdef CONFIG_IXGBE_DCB
258 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
30b76832 259 int tc;
26f23d82
YZ		 260 int reg_idx = tx_ring->reg_idx;
261 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
262
263 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
264 tc = reg_idx >> 2;
265 txoff = IXGBE_TFCS_TXOFF0;
266 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
267 tc = 0;
268 txoff = IXGBE_TFCS_TXOFF;
269 if (dcb_i == 8) {
270 /* TC0, TC1 */
271 tc = reg_idx >> 5;
272 if (tc == 2) /* TC2, TC3 */
273 tc += (reg_idx - 64) >> 4;
274 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
275 tc += 1 + ((reg_idx - 96) >> 3);
276 } else if (dcb_i == 4) {
277 /* TC0, TC1 */
278 tc = reg_idx >> 6;
279 if (tc == 1) {
280 tc += (reg_idx - 64) >> 5;
281 if (tc == 2) /* TC2, TC3 */
282 tc += (reg_idx - 96) >> 4;
283 }
284 }
285 }
286 txoff <<= tc;
287 }
288#endif
289 return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
290}
291
9a799d71 292static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
b4617240
PW		 293 struct ixgbe_ring *tx_ring,
294 unsigned int eop)
9a799d71 295{
e01c31a5 296 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 297
9a799d71 298 /* Detect a transmit hang in hardware, this serializes the
e01c31a5 299 * check with the clearing of time_stamp and movement of eop */
9a799d71 300 adapter->detect_tx_hung = false;
44df32c5 301 if (tx_ring->tx_buffer_info[eop].time_stamp &&
9a799d71 302 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
26f23d82 303 !ixgbe_tx_is_paused(adapter, tx_ring)) {
9a799d71 304 /* detected Tx unit hang */
e01c31a5
JB		 305 union ixgbe_adv_tx_desc *tx_desc;
306 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
9a799d71 307 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
e01c31a5
JB		 308 " Tx Queue <%d>\n"
309 " TDH, TDT <%x>, <%x>\n"
9a799d71
AK		 310 " next_to_use <%x>\n"
311 " next_to_clean <%x>\n"
312 "tx_buffer_info[next_to_clean]\n"
313 " time_stamp <%lx>\n"
e01c31a5
JB		 314 " jiffies <%lx>\n",
315 tx_ring->queue_index,
44df32c5
AD		 316 IXGBE_READ_REG(hw, tx_ring->head),
317 IXGBE_READ_REG(hw, tx_ring->tail),
e01c31a5
JB		 318 tx_ring->next_to_use, eop,
319 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
9a799d71
AK		 320 return true;
321 }
322
323 return false;
324}
325
b4617240
PW		 326#define IXGBE_MAX_TXD_PWR 14
327#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
e092be60
AV		 328
329/* Tx Descriptors needed, worst case */
330#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
331 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
332#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
b4617240 333 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
e092be60 334
e01c31a5
JB		 335static void ixgbe_tx_timeout(struct net_device *netdev);
336
9a799d71
AK		 337/**
338 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 339 * @q_vector: structure containing interrupt and ring information
e01c31a5 340 * @tx_ring: tx ring to clean
9a799d71 341 **/
fe49f04a 342static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e01c31a5 343 struct ixgbe_ring *tx_ring)
9a799d71 344{
fe49f04a 345 struct ixgbe_adapter *adapter = q_vector->adapter;
e01c31a5 346 struct net_device *netdev = adapter->netdev;
12207e49
PWJ		 347 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
348 struct ixgbe_tx_buffer *tx_buffer_info;
349 unsigned int i, eop, count = 0;
e01c31a5 350 unsigned int total_bytes = 0, total_packets = 0;
9a799d71
AK		 351
352 i = tx_ring->next_to_clean;
12207e49
PWJ		 353 eop = tx_ring->tx_buffer_info[i].next_to_watch;
354 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
355
356 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
9a1a69ad 357 (count < tx_ring->work_limit)) {
12207e49
PWJ		 358 bool cleaned = false;
359 for ( ; !cleaned; count++) {
360 struct sk_buff *skb;
9a799d71
AK		 361 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
362 tx_buffer_info = &tx_ring->tx_buffer_info[i];
12207e49 363 cleaned = (i == eop);
e01c31a5 364 skb = tx_buffer_info->skb;
9a799d71 365
12207e49 366 if (cleaned && skb) {
e092be60 367 unsigned int segs, bytecount;
3d8fd385 368 unsigned int hlen = skb_headlen(skb);
e01c31a5
JB		 369
370 /* gso_segs is currently only valid for tcp */
e092be60 371 segs = skb_shinfo(skb)->gso_segs ?: 1;
3d8fd385
YZ		 372#ifdef IXGBE_FCOE
373 /* adjust for FCoE Sequence Offload */
374 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
375 && (skb->protocol == htons(ETH_P_FCOE)) &&
376 skb_is_gso(skb)) {
377 hlen = skb_transport_offset(skb) +
378 sizeof(struct fc_frame_header) +
379 sizeof(struct fcoe_crc_eof);
380 segs = DIV_ROUND_UP(skb->len - hlen,
381 skb_shinfo(skb)->gso_size);
382 }
383#endif /* IXGBE_FCOE */
e092be60 384 /* multiply data chunks by size of headers */
3d8fd385 385 bytecount = ((segs - 1) * hlen) + skb->len;
e01c31a5
JB		 386 total_packets += segs;
387 total_bytes += bytecount;
e092be60 388 }
e01c31a5 389
9a799d71 390 ixgbe_unmap_and_free_tx_resource(adapter,
e01c31a5 391 tx_buffer_info);
9a799d71 392
12207e49
PWJ		 393 tx_desc->wb.status = 0;
394
9a799d71
AK		 395 i++;
396 if (i == tx_ring->count)
397 i = 0;
e01c31a5 398 }
12207e49
PWJ		 399
400 eop = tx_ring->tx_buffer_info[i].next_to_watch;
401 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
402 }
403
9a799d71
AK		 404 tx_ring->next_to_clean = i;
405
e092be60 406#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
e01c31a5
JB		 407 if (unlikely(count && netif_carrier_ok(netdev) &&
408 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 409 /* Make sure that anybody stopping the queue after this
410 * sees the new next_to_clean.
411 */
412 smp_mb();
30eba97a
AV		 413 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
414 !test_bit(__IXGBE_DOWN, &adapter->state)) {
415 netif_wake_subqueue(netdev, tx_ring->queue_index);
7ca3bc58 416 ++tx_ring->restart_queue;
30eba97a 417 }
e092be60 418 }
9a799d71 419
e01c31a5
JB		 420 if (adapter->detect_tx_hung) {
421 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
422 /* schedule immediate reset if we believe we hung */
423 DPRINTK(PROBE, INFO,
424 "tx hang %d detected, resetting adapter\n",
425 adapter->tx_timeout_count + 1);
426 ixgbe_tx_timeout(adapter->netdev);
427 }
428 }
9a799d71 429
e01c31a5 430 /* re-arm the interrupt */
fe49f04a
AD		 431 if (count >= tx_ring->work_limit)
432 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
9a799d71 433
e01c31a5
JB		 434 tx_ring->total_bytes += total_bytes;
435 tx_ring->total_packets += total_packets;
e01c31a5 436 tx_ring->stats.packets += total_packets;
12207e49 437 tx_ring->stats.bytes += total_bytes;
2d86f139
AK		 438 netdev->stats.tx_bytes += total_bytes;
439 netdev->stats.tx_packets += total_packets;
9a1a69ad 440 return (count < tx_ring->work_limit);
9a799d71
AK		 441}
442
5dd2d332 443#ifdef CONFIG_IXGBE_DCA
bd0362dd 444static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
b4617240 445 struct ixgbe_ring *rx_ring)
bd0362dd
JC		 446{
447 u32 rxctrl;
448 int cpu = get_cpu();
3a581073 449 int q = rx_ring - adapter->rx_ring;
bd0362dd 450
3a581073 451 if (rx_ring->cpu != cpu) {
bd0362dd 452 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
e8e26350
PW		 453 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
454 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
455 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
456 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
457 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
458 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
459 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
460 }
bd0362dd
JC		 461 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
462 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
15005a32
DS		 463 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
464 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
e8e26350 465 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
bd0362dd 466 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
3a581073 467 rx_ring->cpu = cpu;
bd0362dd
JC		 468 }
469 put_cpu();
470}
471
472static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
b4617240 473 struct ixgbe_ring *tx_ring)
bd0362dd
JC		 474{
475 u32 txctrl;
476 int cpu = get_cpu();
3a581073 477 int q = tx_ring - adapter->tx_ring;
ee5f784a 478 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 479
3a581073 480 if (tx_ring->cpu != cpu) {
e8e26350 481 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
ee5f784a 482 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q));
e8e26350
PW		 483 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
484 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
ee5f784a
DS		 485 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
486 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl);
e8e26350 487 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
ee5f784a 488 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q));
e8e26350
PW		 489 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
490 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
ee5f784a
DS		 491 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
492 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
493 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl);
e8e26350 494 }
3a581073 495 tx_ring->cpu = cpu;
bd0362dd
JC		 496 }
497 put_cpu();
498}
499
500static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
501{
502 int i;
503
504 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
505 return;
506
e35ec126
AD		 507 /* always use CB2 mode, difference is masked in the CB driver */
508 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
509
bd0362dd
JC		 510 for (i = 0; i < adapter->num_tx_queues; i++) {
511 adapter->tx_ring[i].cpu = -1;
512 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
513 }
514 for (i = 0; i < adapter->num_rx_queues; i++) {
515 adapter->rx_ring[i].cpu = -1;
516 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
517 }
518}
519
520static int __ixgbe_notify_dca(struct device *dev, void *data)
521{
522 struct net_device *netdev = dev_get_drvdata(dev);
523 struct ixgbe_adapter *adapter = netdev_priv(netdev);
524 unsigned long event = *(unsigned long *)data;
525
526 switch (event) {
527 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 528 /* if we're already enabled, don't do it again */
529 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
530 break;
652f093f 531 if (dca_add_requester(dev) == 0) {
96b0e0f6 532 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 533 ixgbe_setup_dca(adapter);
534 break;
535 }
536 /* Fall Through since DCA is disabled. */
537 case DCA_PROVIDER_REMOVE:
538 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
539 dca_remove_requester(dev);
540 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
541 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
542 }
543 break;
544 }
545
652f093f 546 return 0;
bd0362dd
JC		 547}
548
5dd2d332 549#endif /* CONFIG_IXGBE_DCA */
9a799d71
AK		 550/**
551 * ixgbe_receive_skb - Send a completed packet up the stack
552 * @adapter: board private structure
553 * @skb: packet to send up
177db6ff
MC		 554 * @status: hardware indication of status of receive
555 * @rx_ring: rx descriptor ring (for a specific queue) to setup
556 * @rx_desc: rx descriptor
9a799d71 557 **/
78b6f4ce 558static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
b4617240 559 struct sk_buff *skb, u8 status,
fdaff1ce 560 struct ixgbe_ring *ring,
177db6ff 561 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 562{
78b6f4ce
HX		 563 struct ixgbe_adapter *adapter = q_vector->adapter;
564 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 565 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
566 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 567
fdaff1ce 568 skb_record_rx_queue(skb, ring->queue_index);
182ff8df 569 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
8a62babf 570 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
78b6f4ce 571 vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
9a799d71 572 else
78b6f4ce 573 napi_gro_receive(napi, skb);
177db6ff 574 } else {
8a62babf 575 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
182ff8df
AD		 576 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
577 else
578 netif_rx(skb);
9a799d71
AK		 579 }
580}
581
e59bd25d
AV		 582/**
583 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
584 * @adapter: address of board private structure
585 * @status_err: hardware indication of status of receive
586 * @skb: skb currently being received and modified
587 **/
9a799d71 588static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
8bae1b2b
DS		 589 union ixgbe_adv_rx_desc *rx_desc,
590 struct sk_buff *skb)
9a799d71 591{
8bae1b2b
DS		 592 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
593
9a799d71
AK		 594 skb->ip_summed = CHECKSUM_NONE;
595
712744be
JB		 596 /* Rx csum disabled */
597 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 598 return;
e59bd25d
AV		 599
600 /* if IP and error */
601 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
602 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 603 adapter->hw_csum_rx_error++;
604 return;
605 }
e59bd25d
AV		 606
607 if (!(status_err & IXGBE_RXD_STAT_L4CS))
608 return;
609
610 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
8bae1b2b
DS		 611 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
612
613 /*
614 * 82599 errata, UDP frames with a 0 checksum can be marked as
615 * checksum errors.
616 */
617 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
618 (adapter->hw.mac.type == ixgbe_mac_82599EB))
619 return;
620
e59bd25d
AV		 621 adapter->hw_csum_rx_error++;
622 return;
623 }
624
9a799d71 625 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 626 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 627}
628
e8e26350
PW		 629static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
630 struct ixgbe_ring *rx_ring, u32 val)
631{
632 /*
633 * Force memory writes to complete before letting h/w
634 * know there are new descriptors to fetch. (Only
635 * applicable for weak-ordered memory model archs,
636 * such as IA-64).
637 */
638 wmb();
639 IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
640}
641
9a799d71
AK		 642/**
643 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
644 * @adapter: address of board private structure
645 **/
646static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
7c6e0a43
JB		 647 struct ixgbe_ring *rx_ring,
648 int cleaned_count)
9a799d71 649{
9a799d71
AK		 650 struct pci_dev *pdev = adapter->pdev;
651 union ixgbe_adv_rx_desc *rx_desc;
3a581073 652 struct ixgbe_rx_buffer *bi;
9a799d71 653 unsigned int i;
9a799d71
AK		 654
655 i = rx_ring->next_to_use;
3a581073 656 bi = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 657
658 while (cleaned_count--) {
659 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
660
762f4c57 661 if (!bi->page_dma &&
6e455b89 662 (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
3a581073 663 if (!bi->page) {
762f4c57
JB		 664 bi->page = alloc_page(GFP_ATOMIC);
665 if (!bi->page) {
666 adapter->alloc_rx_page_failed++;
667 goto no_buffers;
668 }
669 bi->page_offset = 0;
670 } else {
671 /* use a half page if we're re-using */
672 bi->page_offset ^= (PAGE_SIZE / 2);
9a799d71 673 }
762f4c57
JB		 674
675 bi->page_dma = pci_map_page(pdev, bi->page,
676 bi->page_offset,
677 (PAGE_SIZE / 2),
678 PCI_DMA_FROMDEVICE);
9a799d71
AK		 679 }
680
3a581073 681 if (!bi->skb) {
5ecc3614 682 struct sk_buff *skb;
7ca3bc58
JB		 683 /* netdev_alloc_skb reserves 32 bytes up front!! */
684 uint bufsz = rx_ring->rx_buf_len + SMP_CACHE_BYTES;
685 skb = netdev_alloc_skb(adapter->netdev, bufsz);
9a799d71
AK		 686
687 if (!skb) {
688 adapter->alloc_rx_buff_failed++;
689 goto no_buffers;
690 }
691
7ca3bc58
JB		 692 /* advance the data pointer to the next cache line */
693 skb_reserve(skb, (PTR_ALIGN(skb->data, SMP_CACHE_BYTES)
694 - skb->data));
695
3a581073 696 bi->skb = skb;
4f57ca6e
JB		 697 bi->dma = pci_map_single(pdev, skb->data,
698 rx_ring->rx_buf_len,
3a581073 699 PCI_DMA_FROMDEVICE);
9a799d71
AK		 700 }
701 /* Refresh the desc even if buffer_addrs didn't change because
702 * each write-back erases this info. */
6e455b89 703 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
3a581073
JB		 704 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
705 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 706 } else {
3a581073 707 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
9a799d71
AK		 708 }
709
710 i++;
711 if (i == rx_ring->count)
712 i = 0;
3a581073 713 bi = &rx_ring->rx_buffer_info[i];
9a799d71 714 }
7c6e0a43 715
9a799d71
AK		 716no_buffers:
717 if (rx_ring->next_to_use != i) {
718 rx_ring->next_to_use = i;
719 if (i-- == 0)
720 i = (rx_ring->count - 1);
721
e8e26350 722 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
9a799d71
AK		 723 }
724}
725
7c6e0a43
JB		 726static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
727{
728 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
729}
730
731static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
732{
733 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
734}
735
f8212f97
AD		 736static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
737{
738 return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
739 IXGBE_RXDADV_RSCCNT_MASK) >>
740 IXGBE_RXDADV_RSCCNT_SHIFT;
741}
742
743/**
744 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
745 * @skb: pointer to the last skb in the rsc queue
94b982b2 746 * @count: pointer to number of packets coalesced in this context
f8212f97
AD		 747 *
748 * This function changes a queue full of hw rsc buffers into a completed
749 * packet. It uses the ->prev pointers to find the first packet and then
750 * turns it into the frag list owner.
751 **/
94b982b2
MC		 752static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb,
753 u64 *count)
f8212f97
AD		 754{
755 unsigned int frag_list_size = 0;
756
757 while (skb->prev) {
758 struct sk_buff *prev = skb->prev;
759 frag_list_size += skb->len;
760 skb->prev = NULL;
761 skb = prev;
94b982b2 762 *count += 1;
f8212f97
AD		 763 }
764
765 skb_shinfo(skb)->frag_list = skb->next;
766 skb->next = NULL;
767 skb->len += frag_list_size;
768 skb->data_len += frag_list_size;
769 skb->truesize += frag_list_size;
770 return skb;
771}
772
78b6f4ce 773static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
b4617240
PW		 774 struct ixgbe_ring *rx_ring,
775 int *work_done, int work_to_do)
9a799d71 776{
78b6f4ce 777 struct ixgbe_adapter *adapter = q_vector->adapter;
2d86f139 778 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 779 struct pci_dev *pdev = adapter->pdev;
780 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
781 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
782 struct sk_buff *skb;
f8212f97 783 unsigned int i, rsc_count = 0;
7c6e0a43 784 u32 len, staterr;
177db6ff
MC		 785 u16 hdr_info;
786 bool cleaned = false;
9a799d71 787 int cleaned_count = 0;
d2f4fbe2 788 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3d8fd385
YZ		 789#ifdef IXGBE_FCOE
790 int ddp_bytes = 0;
791#endif /* IXGBE_FCOE */
9a799d71
AK		 792
793 i = rx_ring->next_to_clean;
9a799d71
AK		 794 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
795 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
796 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 797
798 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 799 u32 upper_len = 0;
9a799d71
AK		 800 if (*work_done >= work_to_do)
801 break;
802 (*work_done)++;
803
6e455b89 804 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
7c6e0a43
JB		 805 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
806 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
762f4c57 807 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
9a799d71
AK		 808 if (len > IXGBE_RX_HDR_SIZE)
809 len = IXGBE_RX_HDR_SIZE;
810 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 811 } else {
9a799d71 812 len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 813 }
9a799d71
AK		 814
815 cleaned = true;
816 skb = rx_buffer_info->skb;
7ca3bc58 817 prefetch(skb->data);
9a799d71
AK		 818 rx_buffer_info->skb = NULL;
819
21fa4e66 820 if (rx_buffer_info->dma) {
9a799d71 821 pci_unmap_single(pdev, rx_buffer_info->dma,
5ecc3614 822 rx_ring->rx_buf_len,
b4617240 823 PCI_DMA_FROMDEVICE);
4f57ca6e 824 rx_buffer_info->dma = 0;
9a799d71
AK		 825 skb_put(skb, len);
826 }
827
828 if (upper_len) {
829 pci_unmap_page(pdev, rx_buffer_info->page_dma,
762f4c57 830 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9a799d71
AK		 831 rx_buffer_info->page_dma = 0;
832 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
762f4c57
JB		 833 rx_buffer_info->page,
834 rx_buffer_info->page_offset,
835 upper_len);
836
837 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
838 (page_count(rx_buffer_info->page) != 1))
839 rx_buffer_info->page = NULL;
840 else
841 get_page(rx_buffer_info->page);
9a799d71
AK		 842
843 skb->len += upper_len;
844 skb->data_len += upper_len;
845 skb->truesize += upper_len;
846 }
847
848 i++;
849 if (i == rx_ring->count)
850 i = 0;
9a799d71
AK		 851
852 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
853 prefetch(next_rxd);
9a799d71 854 cleaned_count++;
f8212f97 855
0c19d6af 856 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
f8212f97
AD		 857 rsc_count = ixgbe_get_rsc_count(rx_desc);
858
859 if (rsc_count) {
860 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
861 IXGBE_RXDADV_NEXTP_SHIFT;
862 next_buffer = &rx_ring->rx_buffer_info[nextp];
f8212f97
AD		 863 } else {
864 next_buffer = &rx_ring->rx_buffer_info[i];
865 }
866
9a799d71 867 if (staterr & IXGBE_RXD_STAT_EOP) {
f8212f97 868 if (skb->prev)
94b982b2
MC		 869 skb = ixgbe_transform_rsc_queue(skb, &(rx_ring->rsc_count));
870 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
871 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)
872 rx_ring->rsc_count += skb_shinfo(skb)->nr_frags;
873 else
874 rx_ring->rsc_count++;
875 rx_ring->rsc_flush++;
876 }
9a799d71
AK		 877 rx_ring->stats.packets++;
878 rx_ring->stats.bytes += skb->len;
879 } else {
6e455b89 880 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
f8212f97
AD		 881 rx_buffer_info->skb = next_buffer->skb;
882 rx_buffer_info->dma = next_buffer->dma;
883 next_buffer->skb = skb;
884 next_buffer->dma = 0;
885 } else {
886 skb->next = next_buffer->skb;
887 skb->next->prev = skb;
888 }
7ca3bc58 889 rx_ring->non_eop_descs++;
9a799d71
AK		 890 goto next_desc;
891 }
892
893 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
894 dev_kfree_skb_irq(skb);
895 goto next_desc;
896 }
897
8bae1b2b 898 ixgbe_rx_checksum(adapter, rx_desc, skb);
d2f4fbe2
AV		 899
900 /* probably a little skewed due to removing CRC */
901 total_rx_bytes += skb->len;
902 total_rx_packets++;
903
74ce8dd2 904 skb->protocol = eth_type_trans(skb, adapter->netdev);
332d4a7d
YZ		 905#ifdef IXGBE_FCOE
906 /* if ddp, not passing to ULD unless for FCP_RSP or error */
3d8fd385
YZ		 907 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
908 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
909 if (!ddp_bytes)
332d4a7d 910 goto next_desc;
3d8fd385 911 }
332d4a7d 912#endif /* IXGBE_FCOE */
fdaff1ce 913 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
9a799d71
AK		 914
915next_desc:
916 rx_desc->wb.upper.status_error = 0;
917
918 /* return some buffers to hardware, one at a time is too slow */
919 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
920 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
921 cleaned_count = 0;
922 }
923
924 /* use prefetched values */
925 rx_desc = next_rxd;
f8212f97 926 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 927
928 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 929 }
930
9a799d71
AK		 931 rx_ring->next_to_clean = i;
932 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
933
934 if (cleaned_count)
935 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
936
3d8fd385
YZ		 937#ifdef IXGBE_FCOE
938 /* include DDPed FCoE data */
939 if (ddp_bytes > 0) {
940 unsigned int mss;
941
942 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
943 sizeof(struct fc_frame_header) -
944 sizeof(struct fcoe_crc_eof);
945 if (mss > 512)
946 mss &= ~511;
947 total_rx_bytes += ddp_bytes;
948 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
949 }
950#endif /* IXGBE_FCOE */
951
f494e8fa
AV		 952 rx_ring->total_packets += total_rx_packets;
953 rx_ring->total_bytes += total_rx_bytes;
2d86f139
AK		 954 netdev->stats.rx_bytes += total_rx_bytes;
955 netdev->stats.rx_packets += total_rx_packets;
f494e8fa 956
9a799d71
AK		 957 return cleaned;
958}
959
021230d4 960static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 961/**
962 * ixgbe_configure_msix - Configure MSI-X hardware
963 * @adapter: board private structure
964 *
965 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
966 * interrupts.
967 **/
968static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
969{
021230d4
AV		 970 struct ixgbe_q_vector *q_vector;
971 int i, j, q_vectors, v_idx, r_idx;
972 u32 mask;
9a799d71 973
021230d4 974 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 975
4df10466
JB		 976 /*
977 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 978 * corresponding register.
979 */
980 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
7a921c93 981 q_vector = adapter->q_vector[v_idx];
021230d4
AV		 982 /* XXX for_each_bit(...) */
983 r_idx = find_first_bit(q_vector->rxr_idx,
b4617240 984 adapter->num_rx_queues);
021230d4
AV		 985
986 for (i = 0; i < q_vector->rxr_count; i++) {
987 j = adapter->rx_ring[r_idx].reg_idx;
e8e26350 988 ixgbe_set_ivar(adapter, 0, j, v_idx);
021230d4 989 r_idx = find_next_bit(q_vector->rxr_idx,
b4617240
PW		 990 adapter->num_rx_queues,
991 r_idx + 1);
021230d4
AV		 992 }
993 r_idx = find_first_bit(q_vector->txr_idx,
b4617240 994 adapter->num_tx_queues);
021230d4
AV		 995
996 for (i = 0; i < q_vector->txr_count; i++) {
997 j = adapter->tx_ring[r_idx].reg_idx;
e8e26350 998 ixgbe_set_ivar(adapter, 1, j, v_idx);
021230d4 999 r_idx = find_next_bit(q_vector->txr_idx,
b4617240
PW		 1000 adapter->num_tx_queues,
1001 r_idx + 1);
021230d4
AV		 1002 }
1003
021230d4 1004 if (q_vector->txr_count && !q_vector->rxr_count)
f7554a2b
NS		 1005 /* tx only */
1006 q_vector->eitr = adapter->tx_eitr_param;
509ee935 1007 else if (q_vector->rxr_count)
f7554a2b
NS		 1008 /* rx or mixed */
1009 q_vector->eitr = adapter->rx_eitr_param;
021230d4 1010
fe49f04a 1011 ixgbe_write_eitr(q_vector);
9a799d71
AK		 1012 }
1013
e8e26350
PW		 1014 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1015 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1016 v_idx);
1017 else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1018 ixgbe_set_ivar(adapter, -1, 1, v_idx);
021230d4
AV		 1019 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1020
41fb9248 1021 /* set up to autoclear timer, and the vectors */
021230d4 1022 mask = IXGBE_EIMS_ENABLE_MASK;
41fb9248 1023 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 1024 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1025}
1026
f494e8fa
AV		 1027enum latency_range {
1028 lowest_latency = 0,
1029 low_latency = 1,
1030 bulk_latency = 2,
1031 latency_invalid = 255
1032};
1033
1034/**
1035 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1036 * @adapter: pointer to adapter
1037 * @eitr: eitr setting (ints per sec) to give last timeslice
1038 * @itr_setting: current throttle rate in ints/second
1039 * @packets: the number of packets during this measurement interval
1040 * @bytes: the number of bytes during this measurement interval
1041 *
1042 * Stores a new ITR value based on packets and byte
1043 * counts during the last interrupt. The advantage of per interrupt
1044 * computation is faster updates and more accurate ITR for the current
1045 * traffic pattern. Constants in this function were computed
1046 * based on theoretical maximum wire speed and thresholds were set based
1047 * on testing data as well as attempting to minimize response time
1048 * while increasing bulk throughput.
1049 * this functionality is controlled by the InterruptThrottleRate module
1050 * parameter (see ixgbe_param.c)
1051 **/
1052static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
b4617240
PW		 1053 u32 eitr, u8 itr_setting,
1054 int packets, int bytes)
f494e8fa
AV		 1055{
1056 unsigned int retval = itr_setting;
1057 u32 timepassed_us;
1058 u64 bytes_perint;
1059
1060 if (packets == 0)
1061 goto update_itr_done;
1062
1063
1064 /* simple throttlerate management
1065 * 0-20MB/s lowest (100000 ints/s)
1066 * 20-100MB/s low (20000 ints/s)
1067 * 100-1249MB/s bulk (8000 ints/s)
1068 */
1069 /* what was last interrupt timeslice? */
1070 timepassed_us = 1000000/eitr;
1071 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1072
1073 switch (itr_setting) {
1074 case lowest_latency:
1075 if (bytes_perint > adapter->eitr_low)
1076 retval = low_latency;
1077 break;
1078 case low_latency:
1079 if (bytes_perint > adapter->eitr_high)
1080 retval = bulk_latency;
1081 else if (bytes_perint <= adapter->eitr_low)
1082 retval = lowest_latency;
1083 break;
1084 case bulk_latency:
1085 if (bytes_perint <= adapter->eitr_high)
1086 retval = low_latency;
1087 break;
1088 }
1089
1090update_itr_done:
1091 return retval;
1092}
1093
509ee935
JB		 1094/**
1095 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1096 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1097 *
1098 * This function is made to be called by ethtool and by the driver
1099 * when it needs to update EITR registers at runtime. Hardware
1100 * specific quirks/differences are taken care of here.
1101 */
fe49f04a 1102void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1103{
fe49f04a 1104 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1105 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 1106 int v_idx = q_vector->v_idx;
1107 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1108
509ee935
JB		 1109 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1110 /* must write high and low 16 bits to reset counter */
1111 itr_reg |= (itr_reg << 16);
1112 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1113 /*
1114 * set the WDIS bit to not clear the timer bits and cause an
1115 * immediate assertion of the interrupt
1116 */
1117 itr_reg |= IXGBE_EITR_CNT_WDIS;
1118 }
1119 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1120}
1121
f494e8fa
AV		 1122static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1123{
1124 struct ixgbe_adapter *adapter = q_vector->adapter;
f494e8fa
AV		 1125 u32 new_itr;
1126 u8 current_itr, ret_itr;
fe49f04a 1127 int i, r_idx;
f494e8fa
AV		 1128 struct ixgbe_ring *rx_ring, *tx_ring;
1129
1130 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1131 for (i = 0; i < q_vector->txr_count; i++) {
1132 tx_ring = &(adapter->tx_ring[r_idx]);
1133 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 1134 q_vector->tx_itr,
1135 tx_ring->total_packets,
1136 tx_ring->total_bytes);
f494e8fa
AV		 1137 /* if the result for this queue would decrease interrupt
1138 * rate for this vector then use that result */
30efa5a3 1139 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
b4617240 1140 q_vector->tx_itr - 1 : ret_itr);
f494e8fa 1141 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1142 r_idx + 1);
f494e8fa
AV		 1143 }
1144
1145 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1146 for (i = 0; i < q_vector->rxr_count; i++) {
1147 rx_ring = &(adapter->rx_ring[r_idx]);
1148 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 1149 q_vector->rx_itr,
1150 rx_ring->total_packets,
1151 rx_ring->total_bytes);
f494e8fa
AV		 1152 /* if the result for this queue would decrease interrupt
1153 * rate for this vector then use that result */
30efa5a3 1154 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
b4617240 1155 q_vector->rx_itr - 1 : ret_itr);
f494e8fa 1156 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
b4617240 1157 r_idx + 1);
f494e8fa
AV		 1158 }
1159
30efa5a3 1160 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1161
1162 switch (current_itr) {
1163 /* counts and packets in update_itr are dependent on these numbers */
1164 case lowest_latency:
1165 new_itr = 100000;
1166 break;
1167 case low_latency:
1168 new_itr = 20000; /* aka hwitr = ~200 */
1169 break;
1170 case bulk_latency:
1171 default:
1172 new_itr = 8000;
1173 break;
1174 }
1175
1176 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 1177 /* do an exponential smoothing */
1178 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 1179
1180 /* save the algorithm value here, not the smoothed one */
1181 q_vector->eitr = new_itr;
fe49f04a
AD		 1182
1183 ixgbe_write_eitr(q_vector);
f494e8fa
AV		 1184 }
1185
1186 return;
1187}
1188
0befdb3e
JB		 1189static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1190{
1191 struct ixgbe_hw *hw = &adapter->hw;
1192
1193 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1194 (eicr & IXGBE_EICR_GPI_SDP1)) {
1195 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1196 /* write to clear the interrupt */
1197 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1198 }
1199}
cf8280ee 1200
e8e26350
PW		 1201static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1202{
1203 struct ixgbe_hw *hw = &adapter->hw;
1204
1205 if (eicr & IXGBE_EICR_GPI_SDP1) {
1206 /* Clear the interrupt */
1207 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1208 schedule_work(&adapter->multispeed_fiber_task);
1209 } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1210 /* Clear the interrupt */
1211 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1212 schedule_work(&adapter->sfp_config_module_task);
1213 } else {
1214 /* Interrupt isn't for us... */
1215 return;
1216 }
1217}
1218
cf8280ee
JB		 1219static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1220{
1221 struct ixgbe_hw *hw = &adapter->hw;
1222
1223 adapter->lsc_int++;
1224 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1225 adapter->link_check_timeout = jiffies;
1226 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1227 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 1228 IXGBE_WRITE_FLUSH(hw);
cf8280ee
JB		 1229 schedule_work(&adapter->watchdog_task);
1230 }
1231}
1232
9a799d71
AK		 1233static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1234{
1235 struct net_device *netdev = data;
1236 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1237 struct ixgbe_hw *hw = &adapter->hw;
54037505
DS		 1238 u32 eicr;
1239
1240 /*
1241 * Workaround for Silicon errata. Use clear-by-write instead
1242 * of clear-by-read. Reading with EICS will return the
1243 * interrupt causes without clearing, which later be done
1244 * with the write to EICR.
1245 */
1246 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1247 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
9a799d71 1248
cf8280ee
JB		 1249 if (eicr & IXGBE_EICR_LSC)
1250 ixgbe_check_lsc(adapter);
d4f80882 1251
e8e26350
PW		 1252 if (hw->mac.type == ixgbe_mac_82598EB)
1253 ixgbe_check_fan_failure(adapter, eicr);
0befdb3e 1254
c4cf55e5 1255 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 1256 ixgbe_check_sfp_event(adapter, eicr);
c4cf55e5
PWJ		 1257
1258 /* Handle Flow Director Full threshold interrupt */
1259 if (eicr & IXGBE_EICR_FLOW_DIR) {
1260 int i;
1261 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1262 /* Disable transmits before FDIR Re-initialization */
1263 netif_tx_stop_all_queues(netdev);
1264 for (i = 0; i < adapter->num_tx_queues; i++) {
1265 struct ixgbe_ring *tx_ring =
1266 &adapter->tx_ring[i];
1267 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1268 &tx_ring->reinit_state))
1269 schedule_work(&adapter->fdir_reinit_task);
1270 }
1271 }
1272 }
d4f80882
AV		 1273 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1274 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 1275
1276 return IRQ_HANDLED;
1277}
1278
fe49f04a
AD		 1279static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1280 u64 qmask)
1281{
1282 u32 mask;
1283
1284 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1285 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1286 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1287 } else {
1288 mask = (qmask & 0xFFFFFFFF);
1289 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1290 mask = (qmask >> 32);
1291 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1292 }
1293 /* skip the flush */
1294}
1295
1296static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1297 u64 qmask)
1298{
1299 u32 mask;
1300
1301 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1302 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1303 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1304 } else {
1305 mask = (qmask & 0xFFFFFFFF);
1306 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1307 mask = (qmask >> 32);
1308 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1309 }
1310 /* skip the flush */
1311}
1312
9a799d71
AK		 1313static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1314{
021230d4
AV		 1315 struct ixgbe_q_vector *q_vector = data;
1316 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1317 struct ixgbe_ring *tx_ring;
021230d4
AV		 1318 int i, r_idx;
1319
1320 if (!q_vector->txr_count)
1321 return IRQ_HANDLED;
1322
1323 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1324 for (i = 0; i < q_vector->txr_count; i++) {
3a581073 1325 tx_ring = &(adapter->tx_ring[r_idx]);
3a581073
JB		 1326 tx_ring->total_bytes = 0;
1327 tx_ring->total_packets = 0;
021230d4 1328 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1329 r_idx + 1);
021230d4 1330 }
9a799d71 1331
91281fd3
AD		 1332 /* disable interrupts on this vector only */
1333 ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1334 napi_schedule(&q_vector->napi);
1335
9a799d71
AK		 1336 return IRQ_HANDLED;
1337}
1338
021230d4
AV		 1339/**
1340 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1341 * @irq: unused
1342 * @data: pointer to our q_vector struct for this interrupt vector
1343 **/
9a799d71
AK		 1344static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1345{
021230d4
AV		 1346 struct ixgbe_q_vector *q_vector = data;
1347 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1348 struct ixgbe_ring *rx_ring;
021230d4 1349 int r_idx;
30efa5a3 1350 int i;
021230d4
AV		 1351
1352 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
30efa5a3
JB		 1353 for (i = 0; i < q_vector->rxr_count; i++) {
1354 rx_ring = &(adapter->rx_ring[r_idx]);
1355 rx_ring->total_bytes = 0;
1356 rx_ring->total_packets = 0;
1357 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1358 r_idx + 1);
1359 }
1360
021230d4
AV		 1361 if (!q_vector->rxr_count)
1362 return IRQ_HANDLED;
1363
021230d4 1364 /* disable interrupts on this vector only */
fe49f04a 1365 ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
288379f0 1366 napi_schedule(&q_vector->napi);
021230d4
AV		 1367
1368 return IRQ_HANDLED;
1369}
1370
1371static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1372{
91281fd3
AD		 1373 struct ixgbe_q_vector *q_vector = data;
1374 struct ixgbe_adapter *adapter = q_vector->adapter;
1375 struct ixgbe_ring *ring;
1376 int r_idx;
1377 int i;
1378
1379 if (!q_vector->txr_count && !q_vector->rxr_count)
1380 return IRQ_HANDLED;
1381
1382 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1383 for (i = 0; i < q_vector->txr_count; i++) {
1384 ring = &(adapter->tx_ring[r_idx]);
1385 ring->total_bytes = 0;
1386 ring->total_packets = 0;
1387 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1388 r_idx + 1);
1389 }
1390
1391 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1392 for (i = 0; i < q_vector->rxr_count; i++) {
1393 ring = &(adapter->rx_ring[r_idx]);
1394 ring->total_bytes = 0;
1395 ring->total_packets = 0;
1396 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1397 r_idx + 1);
1398 }
1399
1400 /* disable interrupts on this vector only */
1401 ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1402 napi_schedule(&q_vector->napi);
9a799d71 1403
9a799d71
AK		 1404 return IRQ_HANDLED;
1405}
1406
021230d4
AV		 1407/**
1408 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1409 * @napi: napi struct with our devices info in it
1410 * @budget: amount of work driver is allowed to do this pass, in packets
1411 *
f0848276
JB		 1412 * This function is optimized for cleaning one queue only on a single
1413 * q_vector!!!
021230d4 1414 **/
9a799d71
AK		 1415static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1416{
021230d4 1417 struct ixgbe_q_vector *q_vector =
b4617240 1418 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 1419 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 1420 struct ixgbe_ring *rx_ring = NULL;
9a799d71 1421 int work_done = 0;
021230d4 1422 long r_idx;
9a799d71 1423
021230d4 1424 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
3a581073 1425 rx_ring = &(adapter->rx_ring[r_idx]);
5dd2d332 1426#ifdef CONFIG_IXGBE_DCA
bd0362dd 1427 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1428 ixgbe_update_rx_dca(adapter, rx_ring);
bd0362dd 1429#endif
9a799d71 1430
78b6f4ce 1431 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
9a799d71 1432
021230d4
AV		 1433 /* If all Rx work done, exit the polling mode */
1434 if (work_done < budget) {
288379f0 1435 napi_complete(napi);
f7554a2b 1436 if (adapter->rx_itr_setting & 1)
f494e8fa 1437 ixgbe_set_itr_msix(q_vector);
9a799d71 1438 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a
AD		 1439 ixgbe_irq_enable_queues(adapter,
1440 ((u64)1 << q_vector->v_idx));
9a799d71
AK		 1441 }
1442
1443 return work_done;
1444}
1445
f0848276 1446/**
91281fd3 1447 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
f0848276
JB		 1448 * @napi: napi struct with our devices info in it
1449 * @budget: amount of work driver is allowed to do this pass, in packets
1450 *
1451 * This function will clean more than one rx queue associated with a
1452 * q_vector.
1453 **/
91281fd3 1454static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
f0848276
JB		 1455{
1456 struct ixgbe_q_vector *q_vector =
1457 container_of(napi, struct ixgbe_q_vector, napi);
1458 struct ixgbe_adapter *adapter = q_vector->adapter;
91281fd3 1459 struct ixgbe_ring *ring = NULL;
f0848276
JB		 1460 int work_done = 0, i;
1461 long r_idx;
91281fd3
AD		 1462 bool tx_clean_complete = true;
1463
1464 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1465 for (i = 0; i < q_vector->txr_count; i++) {
1466 ring = &(adapter->tx_ring[r_idx]);
1467#ifdef CONFIG_IXGBE_DCA
1468 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1469 ixgbe_update_tx_dca(adapter, ring);
1470#endif
1471 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1472 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1473 r_idx + 1);
1474 }
f0848276
JB		 1475
1476 /* attempt to distribute budget to each queue fairly, but don't allow
1477 * the budget to go below 1 because we'll exit polling */
1478 budget /= (q_vector->rxr_count ?: 1);
1479 budget = max(budget, 1);
1480 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1481 for (i = 0; i < q_vector->rxr_count; i++) {
91281fd3 1482 ring = &(adapter->rx_ring[r_idx]);
5dd2d332 1483#ifdef CONFIG_IXGBE_DCA
f0848276 1484 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
91281fd3 1485 ixgbe_update_rx_dca(adapter, ring);
f0848276 1486#endif
91281fd3 1487 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
f0848276
JB		 1488 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1489 r_idx + 1);
1490 }
1491
1492 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
91281fd3 1493 ring = &(adapter->rx_ring[r_idx]);
f0848276 1494 /* If all Rx work done, exit the polling mode */
7f821875 1495 if (work_done < budget) {
288379f0 1496 napi_complete(napi);
f7554a2b 1497 if (adapter->rx_itr_setting & 1)
f0848276
JB		 1498 ixgbe_set_itr_msix(q_vector);
1499 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a
AD		 1500 ixgbe_irq_enable_queues(adapter,
1501 ((u64)1 << q_vector->v_idx));
f0848276
JB		 1502 return 0;
1503 }
1504
1505 return work_done;
1506}
91281fd3
AD		 1507
1508/**
1509 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1510 * @napi: napi struct with our devices info in it
1511 * @budget: amount of work driver is allowed to do this pass, in packets
1512 *
1513 * This function is optimized for cleaning one queue only on a single
1514 * q_vector!!!
1515 **/
1516static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1517{
1518 struct ixgbe_q_vector *q_vector =
1519 container_of(napi, struct ixgbe_q_vector, napi);
1520 struct ixgbe_adapter *adapter = q_vector->adapter;
1521 struct ixgbe_ring *tx_ring = NULL;
1522 int work_done = 0;
1523 long r_idx;
1524
1525 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1526 tx_ring = &(adapter->tx_ring[r_idx]);
1527#ifdef CONFIG_IXGBE_DCA
1528 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1529 ixgbe_update_tx_dca(adapter, tx_ring);
1530#endif
1531
1532 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
1533 work_done = budget;
1534
f7554a2b 1535 /* If all Tx work done, exit the polling mode */
91281fd3
AD		 1536 if (work_done < budget) {
1537 napi_complete(napi);
f7554a2b 1538 if (adapter->tx_itr_setting & 1)
91281fd3
AD		 1539 ixgbe_set_itr_msix(q_vector);
1540 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1541 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
1542 }
1543
1544 return work_done;
1545}
1546
021230d4 1547static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
b4617240 1548 int r_idx)
021230d4 1549{
7a921c93
AD		 1550 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1551
1552 set_bit(r_idx, q_vector->rxr_idx);
1553 q_vector->rxr_count++;
021230d4
AV		 1554}
1555
1556static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
7a921c93 1557 int t_idx)
021230d4 1558{
7a921c93
AD		 1559 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1560
1561 set_bit(t_idx, q_vector->txr_idx);
1562 q_vector->txr_count++;
021230d4
AV		 1563}
1564
9a799d71 1565/**
021230d4
AV		 1566 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1567 * @adapter: board private structure to initialize
1568 * @vectors: allotted vector count for descriptor rings
9a799d71 1569 *
021230d4
AV		 1570 * This function maps descriptor rings to the queue-specific vectors
1571 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1572 * one vector per ring/queue, but on a constrained vector budget, we
1573 * group the rings as "efficiently" as possible. You would add new
1574 * mapping configurations in here.
9a799d71 1575 **/
021230d4 1576static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
b4617240 1577 int vectors)
021230d4
AV		 1578{
1579 int v_start = 0;
1580 int rxr_idx = 0, txr_idx = 0;
1581 int rxr_remaining = adapter->num_rx_queues;
1582 int txr_remaining = adapter->num_tx_queues;
1583 int i, j;
1584 int rqpv, tqpv;
1585 int err = 0;
1586
1587 /* No mapping required if MSI-X is disabled. */
1588 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1589 goto out;
9a799d71 1590
021230d4
AV		 1591 /*
1592 * The ideal configuration...
1593 * We have enough vectors to map one per queue.
1594 */
1595 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1596 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1597 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 1598
021230d4
AV		 1599 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1600 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 1601
9a799d71 1602 goto out;
021230d4 1603 }
9a799d71 1604
021230d4
AV		 1605 /*
1606 * If we don't have enough vectors for a 1-to-1
1607 * mapping, we'll have to group them so there are
1608 * multiple queues per vector.
1609 */
1610 /* Re-adjusting *qpv takes care of the remainder. */
1611 for (i = v_start; i < vectors; i++) {
1612 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1613 for (j = 0; j < rqpv; j++) {
1614 map_vector_to_rxq(adapter, i, rxr_idx);
1615 rxr_idx++;
1616 rxr_remaining--;
1617 }
1618 }
1619 for (i = v_start; i < vectors; i++) {
1620 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1621 for (j = 0; j < tqpv; j++) {
1622 map_vector_to_txq(adapter, i, txr_idx);
1623 txr_idx++;
1624 txr_remaining--;
9a799d71 1625 }
9a799d71
AK		 1626 }
1627
021230d4
AV		 1628out:
1629 return err;
1630}
1631
1632/**
1633 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1634 * @adapter: board private structure
1635 *
1636 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1637 * interrupts from the kernel.
1638 **/
1639static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1640{
1641 struct net_device *netdev = adapter->netdev;
1642 irqreturn_t (*handler)(int, void *);
1643 int i, vector, q_vectors, err;
cb13fc20 1644 int ri=0, ti=0;
021230d4
AV		 1645
1646 /* Decrement for Other and TCP Timer vectors */
1647 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1648
1649 /* Map the Tx/Rx rings to the vectors we were allotted. */
1650 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1651 if (err)
1652 goto out;
1653
1654#define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
b4617240
PW		 1655 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1656 &ixgbe_msix_clean_many)
021230d4 1657 for (vector = 0; vector < q_vectors; vector++) {
7a921c93 1658 handler = SET_HANDLER(adapter->q_vector[vector]);
cb13fc20
RO		 1659
1660 if(handler == &ixgbe_msix_clean_rx) {
1661 sprintf(adapter->name[vector], "%s-%s-%d",
1662 netdev->name, "rx", ri++);
1663 }
1664 else if(handler == &ixgbe_msix_clean_tx) {
1665 sprintf(adapter->name[vector], "%s-%s-%d",
1666 netdev->name, "tx", ti++);
1667 }
1668 else
1669 sprintf(adapter->name[vector], "%s-%s-%d",
1670 netdev->name, "TxRx", vector);
1671
021230d4 1672 err = request_irq(adapter->msix_entries[vector].vector,
b4617240 1673 handler, 0, adapter->name[vector],
7a921c93 1674 adapter->q_vector[vector]);
9a799d71
AK		 1675 if (err) {
1676 DPRINTK(PROBE, ERR,
b4617240
PW		 1677 "request_irq failed for MSIX interrupt "
1678 "Error: %d\n", err);
021230d4 1679 goto free_queue_irqs;
9a799d71 1680 }
9a799d71
AK		 1681 }
1682
021230d4
AV		 1683 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1684 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 1685 ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
9a799d71
AK		 1686 if (err) {
1687 DPRINTK(PROBE, ERR,
1688 "request_irq for msix_lsc failed: %d\n", err);
021230d4 1689 goto free_queue_irqs;
9a799d71
AK		 1690 }
1691
9a799d71
AK		 1692 return 0;
1693
021230d4
AV		 1694free_queue_irqs:
1695 for (i = vector - 1; i >= 0; i--)
1696 free_irq(adapter->msix_entries[--vector].vector,
7a921c93 1697 adapter->q_vector[i]);
021230d4
AV		 1698 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1699 pci_disable_msix(adapter->pdev);
9a799d71
AK		 1700 kfree(adapter->msix_entries);
1701 adapter->msix_entries = NULL;
021230d4 1702out:
9a799d71
AK		 1703 return err;
1704}
1705
f494e8fa
AV		 1706static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1707{
7a921c93 1708 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
f494e8fa
AV		 1709 u8 current_itr;
1710 u32 new_itr = q_vector->eitr;
1711 struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1712 struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1713
30efa5a3 1714 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1715 q_vector->tx_itr,
1716 tx_ring->total_packets,
1717 tx_ring->total_bytes);
30efa5a3 1718 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1719 q_vector->rx_itr,
1720 rx_ring->total_packets,
1721 rx_ring->total_bytes);
f494e8fa 1722
30efa5a3 1723 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1724
1725 switch (current_itr) {
1726 /* counts and packets in update_itr are dependent on these numbers */
1727 case lowest_latency:
1728 new_itr = 100000;
1729 break;
1730 case low_latency:
1731 new_itr = 20000; /* aka hwitr = ~200 */
1732 break;
1733 case bulk_latency:
1734 new_itr = 8000;
1735 break;
1736 default:
1737 break;
1738 }
1739
1740 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 1741 /* do an exponential smoothing */
1742 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 1743
1744 /* save the algorithm value here, not the smoothed one */
1745 q_vector->eitr = new_itr;
fe49f04a
AD		 1746
1747 ixgbe_write_eitr(q_vector);
f494e8fa
AV		 1748 }
1749
1750 return;
1751}
1752
79aefa45
AD		 1753/**
1754 * ixgbe_irq_enable - Enable default interrupt generation settings
1755 * @adapter: board private structure
1756 **/
1757static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1758{
1759 u32 mask;
835462fc
NS		 1760
1761 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
6ab33d51
DM		 1762 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1763 mask |= IXGBE_EIMS_GPI_SDP1;
e8e26350 1764 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2a41ff81 1765 mask |= IXGBE_EIMS_ECC;
e8e26350
PW		 1766 mask |= IXGBE_EIMS_GPI_SDP1;
1767 mask |= IXGBE_EIMS_GPI_SDP2;
1768 }
c4cf55e5
PWJ		 1769 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
1770 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
1771 mask |= IXGBE_EIMS_FLOW_DIR;
e8e26350 1772
79aefa45 1773 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
835462fc 1774 ixgbe_irq_enable_queues(adapter, ~0);
79aefa45
AD		 1775 IXGBE_WRITE_FLUSH(&adapter->hw);
1776}
021230d4 1777
9a799d71 1778/**
021230d4 1779 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 1780 * @irq: interrupt number
1781 * @data: pointer to a network interface device structure
9a799d71
AK		 1782 **/
1783static irqreturn_t ixgbe_intr(int irq, void *data)
1784{
1785 struct net_device *netdev = data;
1786 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1787 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 1788 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 1789 u32 eicr;
1790
54037505
DS		 1791 /*
1792 * Workaround for silicon errata. Mask the interrupts
1793 * before the read of EICR.
1794 */
1795 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1796
021230d4
AV		 1797 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1798 * therefore no explict interrupt disable is necessary */
1799 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e
JB		 1800 if (!eicr) {
1801 /* shared interrupt alert!
1802 * make sure interrupts are enabled because the read will
1803 * have disabled interrupts due to EIAM */
1804 ixgbe_irq_enable(adapter);
9a799d71 1805 return IRQ_NONE; /* Not our interrupt */
f47cf66e 1806 }
9a799d71 1807
cf8280ee
JB		 1808 if (eicr & IXGBE_EICR_LSC)
1809 ixgbe_check_lsc(adapter);
021230d4 1810
e8e26350
PW		 1811 if (hw->mac.type == ixgbe_mac_82599EB)
1812 ixgbe_check_sfp_event(adapter, eicr);
1813
0befdb3e
JB		 1814 ixgbe_check_fan_failure(adapter, eicr);
1815
7a921c93 1816 if (napi_schedule_prep(&(q_vector->napi))) {
f494e8fa
AV		 1817 adapter->tx_ring[0].total_packets = 0;
1818 adapter->tx_ring[0].total_bytes = 0;
1819 adapter->rx_ring[0].total_packets = 0;
1820 adapter->rx_ring[0].total_bytes = 0;
021230d4 1821 /* would disable interrupts here but EIAM disabled it */
7a921c93 1822 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 1823 }
1824
1825 return IRQ_HANDLED;
1826}
1827
021230d4
AV		 1828static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1829{
1830 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1831
1832 for (i = 0; i < q_vectors; i++) {
7a921c93 1833 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
021230d4
AV		 1834 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1835 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1836 q_vector->rxr_count = 0;
1837 q_vector->txr_count = 0;
1838 }
1839}
1840
9a799d71
AK		 1841/**
1842 * ixgbe_request_irq - initialize interrupts
1843 * @adapter: board private structure
1844 *
1845 * Attempts to configure interrupts using the best available
1846 * capabilities of the hardware and kernel.
1847 **/
021230d4 1848static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 1849{
1850 struct net_device *netdev = adapter->netdev;
021230d4 1851 int err;
9a799d71 1852
021230d4
AV		 1853 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1854 err = ixgbe_request_msix_irqs(adapter);
1855 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
a0607fd3 1856 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
b4617240 1857 netdev->name, netdev);
021230d4 1858 } else {
a0607fd3 1859 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
b4617240 1860 netdev->name, netdev);
9a799d71
AK		 1861 }
1862
9a799d71
AK		 1863 if (err)
1864 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1865
9a799d71
AK		 1866 return err;
1867}
1868
1869static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1870{
1871 struct net_device *netdev = adapter->netdev;
1872
1873 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 1874 int i, q_vectors;
9a799d71 1875
021230d4
AV		 1876 q_vectors = adapter->num_msix_vectors;
1877
1878 i = q_vectors - 1;
9a799d71 1879 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 1880
021230d4
AV		 1881 i--;
1882 for (; i >= 0; i--) {
1883 free_irq(adapter->msix_entries[i].vector,
7a921c93 1884 adapter->q_vector[i]);
021230d4
AV		 1885 }
1886
1887 ixgbe_reset_q_vectors(adapter);
1888 } else {
1889 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 1890 }
1891}
1892
22d5a71b
JB		 1893/**
1894 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1895 * @adapter: board private structure
1896 **/
1897static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1898{
835462fc
NS		 1899 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1900 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1901 } else {
1902 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
1903 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 1904 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
22d5a71b
JB		 1905 }
1906 IXGBE_WRITE_FLUSH(&adapter->hw);
1907 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1908 int i;
1909 for (i = 0; i < adapter->num_msix_vectors; i++)
1910 synchronize_irq(adapter->msix_entries[i].vector);
1911 } else {
1912 synchronize_irq(adapter->pdev->irq);
1913 }
1914}
1915
9a799d71
AK		 1916/**
1917 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1918 *
1919 **/
1920static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1921{
9a799d71
AK		 1922 struct ixgbe_hw *hw = &adapter->hw;
1923
021230d4 1924 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
f7554a2b 1925 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
9a799d71 1926
e8e26350
PW		 1927 ixgbe_set_ivar(adapter, 0, 0, 0);
1928 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4
AV		 1929
1930 map_vector_to_rxq(adapter, 0, 0);
1931 map_vector_to_txq(adapter, 0, 0);
1932
1933 DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 1934}
1935
1936/**
3a581073 1937 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 1938 * @adapter: board private structure
1939 *
1940 * Configure the Tx unit of the MAC after a reset.
1941 **/
1942static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1943{
12207e49 1944 u64 tdba;
9a799d71 1945 struct ixgbe_hw *hw = &adapter->hw;
021230d4 1946 u32 i, j, tdlen, txctrl;
9a799d71
AK		 1947
1948 /* Setup the HW Tx Head and Tail descriptor pointers */
1949 for (i = 0; i < adapter->num_tx_queues; i++) {
e01c31a5
JB		 1950 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1951 j = ring->reg_idx;
1952 tdba = ring->dma;
1953 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
021230d4 1954 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
284901a9 1955 (tdba & DMA_BIT_MASK(32)));
021230d4
AV		 1956 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1957 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1958 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1959 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1960 adapter->tx_ring[i].head = IXGBE_TDH(j);
1961 adapter->tx_ring[i].tail = IXGBE_TDT(j);
84f62d4b
PWJ		 1962 /*
1963 * Disable Tx Head Writeback RO bit, since this hoses
021230d4
AV		 1964 * bookkeeping if things aren't delivered in order.
1965 */
84f62d4b
PWJ		 1966 switch (hw->mac.type) {
1967 case ixgbe_mac_82598EB:
1968 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
1969 break;
1970 case ixgbe_mac_82599EB:
1971 default:
1972 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(j));
1973 break;
1974 }
021230d4 1975 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
84f62d4b
PWJ		 1976 switch (hw->mac.type) {
1977 case ixgbe_mac_82598EB:
1978 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
1979 break;
1980 case ixgbe_mac_82599EB:
1981 default:
1982 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(j), txctrl);
1983 break;
1984 }
9a799d71 1985 }
ee5f784a 1986
e8e26350 1987 if (hw->mac.type == ixgbe_mac_82599EB) {
ee5f784a
DS		 1988 u32 rttdcs;
1989
1990 /* disable the arbiter while setting MTQC */
1991 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
1992 rttdcs |= IXGBE_RTTDCS_ARBDIS;
1993 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
1994
e8e26350
PW		 1995 /* We enable 8 traffic classes, DCB only */
1996 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
1997 IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA |
1998 IXGBE_MTQC_8TC_8TQ));
ee5f784a
DS		 1999 else
2000 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2001
2002 /* re-eable the arbiter */
2003 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2004 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
e8e26350 2005 }
9a799d71
AK		 2006}
2007
e8e26350 2008#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2009
a6616b42
YZ		 2010static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2011 struct ixgbe_ring *rx_ring)
cc41ac7c 2012{
cc41ac7c 2013 u32 srrctl;
a6616b42 2014 int index;
0cefafad 2015 struct ixgbe_ring_feature *feature = adapter->ring_feature;
3be1adfb 2016
a6616b42
YZ		 2017 index = rx_ring->reg_idx;
2018 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2019 unsigned long mask;
0cefafad 2020 mask = (unsigned long) feature[RING_F_RSS].mask;
3be1adfb 2021 index = index & mask;
cc41ac7c 2022 }
cc41ac7c
JB		 2023 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2024
2025 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2026 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2027
afafd5b0
AD		 2028 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2029 IXGBE_SRRCTL_BSIZEHDR_MASK;
2030
6e455b89 2031 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
afafd5b0
AD		 2032#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2033 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2034#else
2035 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2036#endif
cc41ac7c 2037 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 2038 } else {
afafd5b0
AD		 2039 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2040 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 2041 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 2042 }
e8e26350 2043
cc41ac7c
JB		 2044 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2045}
9a799d71 2046
0cefafad
JB		 2047static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2048{
2049 u32 mrqc = 0;
2050 int mask;
2051
2052 if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
2053 return mrqc;
2054
2055 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2056#ifdef CONFIG_IXGBE_DCB
2057 | IXGBE_FLAG_DCB_ENABLED
2058#endif
2059 );
2060
2061 switch (mask) {
2062 case (IXGBE_FLAG_RSS_ENABLED):
2063 mrqc = IXGBE_MRQC_RSSEN;
2064 break;
2065#ifdef CONFIG_IXGBE_DCB
2066 case (IXGBE_FLAG_DCB_ENABLED):
2067 mrqc = IXGBE_MRQC_RT8TCEN;
2068 break;
2069#endif /* CONFIG_IXGBE_DCB */
2070 default:
2071 break;
2072 }
2073
2074 return mrqc;
2075}
2076
bb5a9ad2
NS		 2077/**
2078 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2079 * @adapter: address of board private structure
2080 * @index: index of ring to set
bb5a9ad2 2081 **/
edd2ea55 2082static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, int index)
bb5a9ad2
NS		 2083{
2084 struct ixgbe_ring *rx_ring;
2085 struct ixgbe_hw *hw = &adapter->hw;
2086 int j;
2087 u32 rscctrl;
edd2ea55 2088 int rx_buf_len;
bb5a9ad2
NS		 2089
2090 rx_ring = &adapter->rx_ring[index];
2091 j = rx_ring->reg_idx;
edd2ea55 2092 rx_buf_len = rx_ring->rx_buf_len;
bb5a9ad2
NS		 2093 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2094 rscctrl |= IXGBE_RSCCTL_RSCEN;
2095 /*
2096 * we must limit the number of descriptors so that the
2097 * total size of max desc * buf_len is not greater
2098 * than 65535
2099 */
2100 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2101#if (MAX_SKB_FRAGS > 16)
2102 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2103#elif (MAX_SKB_FRAGS > 8)
2104 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2105#elif (MAX_SKB_FRAGS > 4)
2106 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2107#else
2108 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2109#endif
2110 } else {
2111 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2112 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2113 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2114 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2115 else
2116 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2117 }
2118 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2119}
2120
9a799d71 2121/**
3a581073 2122 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
9a799d71
AK		 2123 * @adapter: board private structure
2124 *
2125 * Configure the Rx unit of the MAC after a reset.
2126 **/
2127static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2128{
2129 u64 rdba;
2130 struct ixgbe_hw *hw = &adapter->hw;
a6616b42 2131 struct ixgbe_ring *rx_ring;
9a799d71
AK		 2132 struct net_device *netdev = adapter->netdev;
2133 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 2134 int i, j;
9a799d71 2135 u32 rdlen, rxctrl, rxcsum;
7c6e0a43
JB		 2136 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2137 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2138 0x6A3E67EA, 0x14364D17, 0x3BED200D};
9a799d71 2139 u32 fctrl, hlreg0;
509ee935 2140 u32 reta = 0, mrqc = 0;
cc41ac7c 2141 u32 rdrxctl;
7c6e0a43 2142 int rx_buf_len;
9a799d71
AK		 2143
2144 /* Decide whether to use packet split mode or not */
762f4c57 2145 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
9a799d71
AK		 2146
2147 /* Set the RX buffer length according to the mode */
2148 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 2149 rx_buf_len = IXGBE_RX_HDR_SIZE;
e8e26350
PW		 2150 if (hw->mac.type == ixgbe_mac_82599EB) {
2151 /* PSRTYPE must be initialized in 82599 */
2152 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2153 IXGBE_PSRTYPE_UDPHDR |
2154 IXGBE_PSRTYPE_IPV4HDR |
dfa12f05
YZ		 2155 IXGBE_PSRTYPE_IPV6HDR |
2156 IXGBE_PSRTYPE_L2HDR;
e8e26350
PW		 2157 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype);
2158 }
9a799d71 2159 } else {
0c19d6af 2160 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
f8212f97 2161 (netdev->mtu <= ETH_DATA_LEN))
7c6e0a43 2162 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 2163 else
7c6e0a43 2164 rx_buf_len = ALIGN(max_frame, 1024);
9a799d71
AK		 2165 }
2166
2167 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2168 fctrl |= IXGBE_FCTRL_BAM;
021230d4 2169 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
e8e26350 2170 fctrl |= IXGBE_FCTRL_PMCF;
9a799d71
AK		 2171 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
2172
2173 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2174 if (adapter->netdev->mtu <= ETH_DATA_LEN)
2175 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2176 else
2177 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
63f39bd1 2178#ifdef IXGBE_FCOE
f34c5c82 2179 if (netdev->features & NETIF_F_FCOE_MTU)
63f39bd1
YZ		 2180 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2181#endif
9a799d71
AK		 2182 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2183
9a799d71
AK		 2184 rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
2185 /* disable receives while setting up the descriptors */
2186 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2187 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2188
0cefafad
JB		 2189 /*
2190 * Setup the HW Rx Head and Tail Descriptor Pointers and
2191 * the Base and Length of the Rx Descriptor Ring
2192 */
9a799d71 2193 for (i = 0; i < adapter->num_rx_queues; i++) {
a6616b42
YZ		 2194 rx_ring = &adapter->rx_ring[i];
2195 rdba = rx_ring->dma;
2196 j = rx_ring->reg_idx;
284901a9 2197 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
7c6e0a43
JB		 2198 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2199 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2200 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2201 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
a6616b42
YZ		 2202 rx_ring->head = IXGBE_RDH(j);
2203 rx_ring->tail = IXGBE_RDT(j);
2204 rx_ring->rx_buf_len = rx_buf_len;
cc41ac7c 2205
6e455b89
YZ		 2206 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2207 rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
1b3ff02e
PWJ		 2208 else
2209 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
cc41ac7c 2210
63f39bd1 2211#ifdef IXGBE_FCOE
f34c5c82 2212 if (netdev->features & NETIF_F_FCOE_MTU) {
63f39bd1
YZ		 2213 struct ixgbe_ring_feature *f;
2214 f = &adapter->ring_feature[RING_F_FCOE];
6e455b89
YZ		 2215 if ((i >= f->mask) && (i < f->mask + f->indices)) {
2216 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2217 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2218 rx_ring->rx_buf_len =
2219 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2220 }
63f39bd1
YZ		 2221 }
2222
2223#endif /* IXGBE_FCOE */
a6616b42 2224 ixgbe_configure_srrctl(adapter, rx_ring);
9a799d71
AK		 2225 }
2226
e8e26350
PW		 2227 if (hw->mac.type == ixgbe_mac_82598EB) {
2228 /*
2229 * For VMDq support of different descriptor types or
2230 * buffer sizes through the use of multiple SRRCTL
2231 * registers, RDRXCTL.MVMEN must be set to 1
2232 *
2233 * also, the manual doesn't mention it clearly but DCA hints
2234 * will only use queue 0's tags unless this bit is set. Side
2235 * effects of setting this bit are only that SRRCTL must be
2236 * fully programmed [0..15]
2237 */
2a41ff81
JB		 2238 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2239 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2240 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2f90b865 2241 }
177db6ff 2242
e8e26350 2243 /* Program MRQC for the distribution of queues */
0cefafad 2244 mrqc = ixgbe_setup_mrqc(adapter);
e8e26350 2245
021230d4 2246 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
9a799d71 2247 /* Fill out redirection table */
021230d4
AV		 2248 for (i = 0, j = 0; i < 128; i++, j++) {
2249 if (j == adapter->ring_feature[RING_F_RSS].indices)
2250 j = 0;
2251 /* reta = 4-byte sliding window of
2252 * 0x00..(indices-1)(indices-1)00..etc. */
2253 reta = (reta << 8) | (j * 0x11);
2254 if ((i & 3) == 3)
2255 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
9a799d71
AK		 2256 }
2257
2258 /* Fill out hash function seeds */
2259 for (i = 0; i < 10; i++)
7c6e0a43 2260 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
9a799d71 2261
2a41ff81
JB		 2262 if (hw->mac.type == ixgbe_mac_82598EB)
2263 mrqc |= IXGBE_MRQC_RSSEN;
9a799d71 2264 /* Perform hash on these packet types */
2a41ff81
JB		 2265 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2266 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2267 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2268 | IXGBE_MRQC_RSS_FIELD_IPV6
2269 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2270 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
021230d4 2271 }
2a41ff81 2272 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
9a799d71 2273
021230d4
AV		 2274 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2275
2276 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
2277 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
2278 /* Disable indicating checksum in descriptor, enables
2279 * RSS hash */
9a799d71 2280 rxcsum |= IXGBE_RXCSUM_PCSD;
9a799d71 2281 }
021230d4
AV		 2282 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
2283 /* Enable IPv4 payload checksum for UDP fragments
2284 * if PCSD is not set */
2285 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2286 }
2287
2288 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
e8e26350
PW		 2289
2290 if (hw->mac.type == ixgbe_mac_82599EB) {
2291 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2292 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
f8212f97 2293 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
e8e26350
PW		 2294 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2295 }
f8212f97 2296
0c19d6af 2297 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 2298 /* Enable 82599 HW-RSC */
bb5a9ad2 2299 for (i = 0; i < adapter->num_rx_queues; i++)
edd2ea55 2300 ixgbe_configure_rscctl(adapter, i);
bb5a9ad2 2301
f8212f97
AD		 2302 /* Disable RSC for ACK packets */
2303 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2304 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2305 }
9a799d71
AK		 2306}
2307
068c89b0
DS		 2308static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2309{
2310 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2311 struct ixgbe_hw *hw = &adapter->hw;
2312
2313 /* add VID to filter table */
2314 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
2315}
2316
2317static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2318{
2319 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2320 struct ixgbe_hw *hw = &adapter->hw;
2321
2322 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2323 ixgbe_irq_disable(adapter);
2324
2325 vlan_group_set_device(adapter->vlgrp, vid, NULL);
2326
2327 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2328 ixgbe_irq_enable(adapter);
2329
2330 /* remove VID from filter table */
2331 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
2332}
2333
9a799d71 2334static void ixgbe_vlan_rx_register(struct net_device *netdev,
b4617240 2335 struct vlan_group *grp)
9a799d71
AK		 2336{
2337 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2338 u32 ctrl;
e8e26350 2339 int i, j;
9a799d71 2340
d4f80882
AV		 2341 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2342 ixgbe_irq_disable(adapter);
9a799d71
AK		 2343 adapter->vlgrp = grp;
2344
2f90b865
AD		 2345 /*
2346 * For a DCB driver, always enable VLAN tag stripping so we can
2347 * still receive traffic from a DCB-enabled host even if we're
2348 * not in DCB mode.
2349 */
2350 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
dc63d377
AD		 2351
2352 /* Disable CFI check */
2353 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2354
2355 /* enable VLAN tag stripping */
e8e26350 2356 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
dc63d377 2357 ctrl |= IXGBE_VLNCTRL_VME;
e8e26350 2358 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
e8e26350 2359 for (i = 0; i < adapter->num_rx_queues; i++) {
dc63d377 2360 u32 ctrl;
e8e26350
PW		 2361 j = adapter->rx_ring[i].reg_idx;
2362 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
2363 ctrl |= IXGBE_RXDCTL_VME;
2364 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
2365 }
9a799d71 2366 }
dc63d377
AD		 2367
2368 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2369
e8e26350 2370 ixgbe_vlan_rx_add_vid(netdev, 0);
9a799d71 2371
d4f80882
AV		 2372 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2373 ixgbe_irq_enable(adapter);
9a799d71
AK		 2374}
2375
9a799d71
AK		 2376static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2377{
2378 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2379
2380 if (adapter->vlgrp) {
2381 u16 vid;
2382 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2383 if (!vlan_group_get_device(adapter->vlgrp, vid))
2384 continue;
2385 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2386 }
2387 }
2388}
2389
2c5645cf
CL		 2390static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
2391{
2392 struct dev_mc_list *mc_ptr;
2393 u8 *addr = *mc_addr_ptr;
2394 *vmdq = 0;
2395
2396 mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
2397 if (mc_ptr->next)
2398 *mc_addr_ptr = mc_ptr->next->dmi_addr;
2399 else
2400 *mc_addr_ptr = NULL;
2401
2402 return addr;
2403}
2404
9a799d71 2405/**
2c5645cf 2406 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 2407 * @netdev: network interface device structure
2408 *
2c5645cf
CL		 2409 * The set_rx_method entry point is called whenever the unicast/multicast
2410 * address list or the network interface flags are updated. This routine is
2411 * responsible for configuring the hardware for proper unicast, multicast and
2412 * promiscuous mode.
9a799d71 2413 **/
2c5645cf 2414static void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 2415{
2416 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2417 struct ixgbe_hw *hw = &adapter->hw;
3d01625a 2418 u32 fctrl, vlnctrl;
2c5645cf
CL		 2419 u8 *addr_list = NULL;
2420 int addr_count = 0;
9a799d71
AK		 2421
2422 /* Check for Promiscuous and All Multicast modes */
2423
2424 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3d01625a 2425 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
9a799d71
AK		 2426
2427 if (netdev->flags & IFF_PROMISC) {
2c5645cf 2428 hw->addr_ctrl.user_set_promisc = 1;
9a799d71 2429 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3d01625a 2430 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
9a799d71 2431 } else {
746b9f02
PM		 2432 if (netdev->flags & IFF_ALLMULTI) {
2433 fctrl |= IXGBE_FCTRL_MPE;
2434 fctrl &= ~IXGBE_FCTRL_UPE;
2435 } else {
2436 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2437 }
3d01625a 2438 vlnctrl |= IXGBE_VLNCTRL_VFE;
2c5645cf 2439 hw->addr_ctrl.user_set_promisc = 0;
9a799d71
AK		 2440 }
2441
2442 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3d01625a 2443 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
9a799d71 2444
2c5645cf 2445 /* reprogram secondary unicast list */
31278e71 2446 hw->mac.ops.update_uc_addr_list(hw, &netdev->uc.list);
9a799d71 2447
2c5645cf
CL		 2448 /* reprogram multicast list */
2449 addr_count = netdev->mc_count;
2450 if (addr_count)
2451 addr_list = netdev->mc_list->dmi_addr;
c44ade9e
JB		 2452 hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2453 ixgbe_addr_list_itr);
9a799d71
AK		 2454}
2455
021230d4
AV		 2456static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2457{
2458 int q_idx;
2459 struct ixgbe_q_vector *q_vector;
2460 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2461
2462 /* legacy and MSI only use one vector */
2463 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2464 q_vectors = 1;
2465
2466 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 2467 struct napi_struct *napi;
7a921c93 2468 q_vector = adapter->q_vector[q_idx];
f0848276 2469 napi = &q_vector->napi;
91281fd3
AD		 2470 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2471 if (!q_vector->rxr_count || !q_vector->txr_count) {
2472 if (q_vector->txr_count == 1)
2473 napi->poll = &ixgbe_clean_txonly;
2474 else if (q_vector->rxr_count == 1)
2475 napi->poll = &ixgbe_clean_rxonly;
2476 }
2477 }
f0848276
JB		 2478
2479 napi_enable(napi);
021230d4
AV		 2480 }
2481}
2482
2483static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2484{
2485 int q_idx;
2486 struct ixgbe_q_vector *q_vector;
2487 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2488
2489 /* legacy and MSI only use one vector */
2490 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2491 q_vectors = 1;
2492
2493 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 2494 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 2495 napi_disable(&q_vector->napi);
2496 }
2497}
2498
7a6b6f51 2499#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 2500/*
2501 * ixgbe_configure_dcb - Configure DCB hardware
2502 * @adapter: ixgbe adapter struct
2503 *
2504 * This is called by the driver on open to configure the DCB hardware.
2505 * This is also called by the gennetlink interface when reconfiguring
2506 * the DCB state.
2507 */
2508static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2509{
2510 struct ixgbe_hw *hw = &adapter->hw;
2511 u32 txdctl, vlnctrl;
2512 int i, j;
2513
2514 ixgbe_dcb_check_config(&adapter->dcb_cfg);
2515 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2516 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2517
2518 /* reconfigure the hardware */
2519 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2520
2521 for (i = 0; i < adapter->num_tx_queues; i++) {
2522 j = adapter->tx_ring[i].reg_idx;
2523 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2524 /* PThresh workaround for Tx hang with DFP enabled. */
2525 txdctl |= 32;
2526 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2527 }
2528 /* Enable VLAN tag insert/strip */
2529 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
e8e26350
PW		 2530 if (hw->mac.type == ixgbe_mac_82598EB) {
2531 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2532 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2533 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2534 } else if (hw->mac.type == ixgbe_mac_82599EB) {
2535 vlnctrl |= IXGBE_VLNCTRL_VFE;
2536 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2537 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2538 for (i = 0; i < adapter->num_rx_queues; i++) {
2539 j = adapter->rx_ring[i].reg_idx;
2540 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2541 vlnctrl |= IXGBE_RXDCTL_VME;
2542 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2543 }
2544 }
2f90b865
AD		 2545 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2546}
2547
2548#endif
9a799d71
AK		 2549static void ixgbe_configure(struct ixgbe_adapter *adapter)
2550{
2551 struct net_device *netdev = adapter->netdev;
c4cf55e5 2552 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 2553 int i;
2554
2c5645cf 2555 ixgbe_set_rx_mode(netdev);
9a799d71
AK		 2556
2557 ixgbe_restore_vlan(adapter);
7a6b6f51 2558#ifdef CONFIG_IXGBE_DCB
2f90b865 2559 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
b352e40d
YZ		 2560 if (hw->mac.type == ixgbe_mac_82598EB)
2561 netif_set_gso_max_size(netdev, 32768);
2562 else
2563 netif_set_gso_max_size(netdev, 65536);
2f90b865
AD		 2564 ixgbe_configure_dcb(adapter);
2565 } else {
2566 netif_set_gso_max_size(netdev, 65536);
2567 }
2568#else
2569 netif_set_gso_max_size(netdev, 65536);
2570#endif
9a799d71 2571
eacd73f7
YZ		 2572#ifdef IXGBE_FCOE
2573 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2574 ixgbe_configure_fcoe(adapter);
2575
2576#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 2577 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2578 for (i = 0; i < adapter->num_tx_queues; i++)
2579 adapter->tx_ring[i].atr_sample_rate =
2580 adapter->atr_sample_rate;
2581 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
2582 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
2583 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
2584 }
2585
9a799d71
AK		 2586 ixgbe_configure_tx(adapter);
2587 ixgbe_configure_rx(adapter);
2588 for (i = 0; i < adapter->num_rx_queues; i++)
2589 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
b4617240 2590 (adapter->rx_ring[i].count - 1));
9a799d71
AK		 2591}
2592
e8e26350
PW		 2593static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2594{
2595 switch (hw->phy.type) {
2596 case ixgbe_phy_sfp_avago:
2597 case ixgbe_phy_sfp_ftl:
2598 case ixgbe_phy_sfp_intel:
2599 case ixgbe_phy_sfp_unknown:
2600 case ixgbe_phy_tw_tyco:
2601 case ixgbe_phy_tw_unknown:
2602 return true;
2603 default:
2604 return false;
2605 }
2606}
2607
0ecc061d 2608/**
e8e26350
PW		 2609 * ixgbe_sfp_link_config - set up SFP+ link
2610 * @adapter: pointer to private adapter struct
2611 **/
2612static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2613{
2614 struct ixgbe_hw *hw = &adapter->hw;
2615
2616 if (hw->phy.multispeed_fiber) {
2617 /*
2618 * In multispeed fiber setups, the device may not have
2619 * had a physical connection when the driver loaded.
2620 * If that's the case, the initial link configuration
2621 * couldn't get the MAC into 10G or 1G mode, so we'll
2622 * never have a link status change interrupt fire.
2623 * We need to try and force an autonegotiation
2624 * session, then bring up link.
2625 */
2626 hw->mac.ops.setup_sfp(hw);
2627 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2628 schedule_work(&adapter->multispeed_fiber_task);
2629 } else {
2630 /*
2631 * Direct Attach Cu and non-multispeed fiber modules
2632 * still need to be configured properly prior to
2633 * attempting link.
2634 */
2635 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2636 schedule_work(&adapter->sfp_config_module_task);
2637 }
2638}
2639
2640/**
2641 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 2642 * @hw: pointer to private hardware struct
2643 *
2644 * Returns 0 on success, negative on failure
2645 **/
e8e26350 2646static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 2647{
2648 u32 autoneg;
8620a103 2649 bool negotiation, link_up = false;
0ecc061d
PWJ		 2650 u32 ret = IXGBE_ERR_LINK_SETUP;
2651
2652 if (hw->mac.ops.check_link)
2653 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2654
2655 if (ret)
2656 goto link_cfg_out;
2657
2658 if (hw->mac.ops.get_link_capabilities)
8620a103 2659 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
0ecc061d
PWJ		 2660 if (ret)
2661 goto link_cfg_out;
2662
8620a103
MC		 2663 if (hw->mac.ops.setup_link)
2664 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 2665link_cfg_out:
2666 return ret;
2667}
2668
e8e26350
PW		 2669#define IXGBE_MAX_RX_DESC_POLL 10
2670static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2671 int rxr)
2672{
2673 int j = adapter->rx_ring[rxr].reg_idx;
2674 int k;
2675
2676 for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2677 if (IXGBE_READ_REG(&adapter->hw,
2678 IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2679 break;
2680 else
2681 msleep(1);
2682 }
2683 if (k >= IXGBE_MAX_RX_DESC_POLL) {
2684 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2685 "not set within the polling period\n", rxr);
2686 }
2687 ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
2688 (adapter->rx_ring[rxr].count - 1));
2689}
2690
9a799d71
AK		 2691static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2692{
2693 struct net_device *netdev = adapter->netdev;
9a799d71 2694 struct ixgbe_hw *hw = &adapter->hw;
021230d4 2695 int i, j = 0;
e8e26350 2696 int num_rx_rings = adapter->num_rx_queues;
0ecc061d 2697 int err;
9a799d71 2698 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 2699 u32 txdctl, rxdctl, mhadd;
e8e26350 2700 u32 dmatxctl;
021230d4 2701 u32 gpie;
9a799d71 2702
5eba3699
AV		 2703 ixgbe_get_hw_control(adapter);
2704
021230d4
AV		 2705 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2706 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
9a799d71
AK		 2707 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2708 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
b4617240 2709 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
9a799d71
AK		 2710 } else {
2711 /* MSI only */
021230d4 2712 gpie = 0;
9a799d71 2713 }
021230d4
AV		 2714 /* XXX: to interrupt immediately for EICS writes, enable this */
2715 /* gpie |= IXGBE_GPIE_EIMEN; */
2716 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
9a799d71
AK		 2717 }
2718
021230d4
AV		 2719 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2720 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2721 * specifically only auto mask tx and rx interrupts */
2722 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2723 }
9a799d71 2724
0befdb3e
JB		 2725 /* Enable fan failure interrupt if media type is copper */
2726 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2727 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2728 gpie |= IXGBE_SDP1_GPIEN;
2729 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2730 }
2731
e8e26350
PW		 2732 if (hw->mac.type == ixgbe_mac_82599EB) {
2733 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2734 gpie |= IXGBE_SDP1_GPIEN;
2735 gpie |= IXGBE_SDP2_GPIEN;
2736 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2737 }
2738
63f39bd1
YZ		 2739#ifdef IXGBE_FCOE
2740 /* adjust max frame to be able to do baby jumbo for FCoE */
f34c5c82 2741 if ((netdev->features & NETIF_F_FCOE_MTU) &&
63f39bd1
YZ		 2742 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2743 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2744
2745#endif /* IXGBE_FCOE */
021230d4 2746 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
9a799d71
AK		 2747 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2748 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2749 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2750
2751 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2752 }
2753
2754 for (i = 0; i < adapter->num_tx_queues; i++) {
021230d4
AV		 2755 j = adapter->tx_ring[i].reg_idx;
2756 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
e01c31a5
JB		 2757 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2758 txdctl |= (8 << 16);
e8e26350
PW		 2759 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2760 }
2761
2762 if (hw->mac.type == ixgbe_mac_82599EB) {
2763 /* DMATXCTL.EN must be set after all Tx queue config is done */
2764 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2765 dmatxctl |= IXGBE_DMATXCTL_TE;
2766 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2767 }
2768 for (i = 0; i < adapter->num_tx_queues; i++) {
2769 j = adapter->tx_ring[i].reg_idx;
2770 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
9a799d71 2771 txdctl |= IXGBE_TXDCTL_ENABLE;
021230d4 2772 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
9a799d71
AK		 2773 }
2774
e8e26350 2775 for (i = 0; i < num_rx_rings; i++) {
021230d4
AV		 2776 j = adapter->rx_ring[i].reg_idx;
2777 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2778 /* enable PTHRESH=32 descriptors (half the internal cache)
2779 * and HTHRESH=0 descriptors (to minimize latency on fetch),
2780 * this also removes a pesky rx_no_buffer_count increment */
2781 rxdctl |= 0x0020;
9a799d71 2782 rxdctl |= IXGBE_RXDCTL_ENABLE;
021230d4 2783 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
e8e26350
PW		 2784 if (hw->mac.type == ixgbe_mac_82599EB)
2785 ixgbe_rx_desc_queue_enable(adapter, i);
9a799d71
AK		 2786 }
2787 /* enable all receives */
2788 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
e8e26350
PW		 2789 if (hw->mac.type == ixgbe_mac_82598EB)
2790 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2791 else
2792 rxdctl |= IXGBE_RXCTRL_RXEN;
2793 hw->mac.ops.enable_rx_dma(hw, rxdctl);
9a799d71
AK		 2794
2795 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2796 ixgbe_configure_msix(adapter);
2797 else
2798 ixgbe_configure_msi_and_legacy(adapter);
2799
2800 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 2801 ixgbe_napi_enable_all(adapter);
2802
2803 /* clear any pending interrupts, may auto mask */
2804 IXGBE_READ_REG(hw, IXGBE_EICR);
2805
9a799d71
AK		 2806 ixgbe_irq_enable(adapter);
2807
bf069c97
DS		 2808 /*
2809 * If this adapter has a fan, check to see if we had a failure
2810 * before we enabled the interrupt.
2811 */
2812 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2813 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2814 if (esdp & IXGBE_ESDP_SDP1)
2815 DPRINTK(DRV, CRIT,
2816 "Fan has stopped, replace the adapter\n");
2817 }
2818
e8e26350
PW		 2819 /*
2820 * For hot-pluggable SFP+ devices, a new SFP+ module may have
19343de2
DS		 2821 * arrived before interrupts were enabled but after probe. Such
2822 * devices wouldn't have their type identified yet. We need to
2823 * kick off the SFP+ module setup first, then try to bring up link.
e8e26350
PW		 2824 * If we're not hot-pluggable SFP+, we just need to configure link
2825 * and bring it up.
2826 */
19343de2
DS		 2827 if (hw->phy.type == ixgbe_phy_unknown) {
2828 err = hw->phy.ops.identify(hw);
2829 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5da43c1a
DS		 2830 /*
2831 * Take the device down and schedule the sfp tasklet
2832 * which will unregister_netdev and log it.
2833 */
19343de2 2834 ixgbe_down(adapter);
5da43c1a 2835 schedule_work(&adapter->sfp_config_module_task);
19343de2
DS		 2836 return err;
2837 }
e8e26350
PW		 2838 }
2839
2840 if (ixgbe_is_sfp(hw)) {
2841 ixgbe_sfp_link_config(adapter);
2842 } else {
2843 err = ixgbe_non_sfp_link_config(hw);
2844 if (err)
2845 DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
2846 }
0ecc061d 2847
c4cf55e5
PWJ		 2848 for (i = 0; i < adapter->num_tx_queues; i++)
2849 set_bit(__IXGBE_FDIR_INIT_DONE,
2850 &(adapter->tx_ring[i].reinit_state));
2851
1da100bb
PWJ		 2852 /* enable transmits */
2853 netif_tx_start_all_queues(netdev);
2854
9a799d71
AK		 2855 /* bring the link up in the watchdog, this could race with our first
2856 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 2857 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2858 adapter->link_check_timeout = jiffies;
9a799d71
AK		 2859 mod_timer(&adapter->watchdog_timer, jiffies);
2860 return 0;
2861}
2862
d4f80882
AV		 2863void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2864{
2865 WARN_ON(in_interrupt());
2866 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2867 msleep(1);
2868 ixgbe_down(adapter);
2869 ixgbe_up(adapter);
2870 clear_bit(__IXGBE_RESETTING, &adapter->state);
2871}
2872
9a799d71
AK		 2873int ixgbe_up(struct ixgbe_adapter *adapter)
2874{
2875 /* hardware has been reset, we need to reload some things */
2876 ixgbe_configure(adapter);
2877
2878 return ixgbe_up_complete(adapter);
2879}
2880
2881void ixgbe_reset(struct ixgbe_adapter *adapter)
2882{
c44ade9e 2883 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 2884 int err;
2885
2886 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 2887 switch (err) {
2888 case 0:
2889 case IXGBE_ERR_SFP_NOT_PRESENT:
2890 break;
2891 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
2892 dev_err(&adapter->pdev->dev, "master disable timed out\n");
2893 break;
794caeb2
PWJ		 2894 case IXGBE_ERR_EEPROM_VERSION:
2895 /* We are running on a pre-production device, log a warning */
2896 dev_warn(&adapter->pdev->dev, "This device is a pre-production "
2897 "adapter/LOM. Please be aware there may be issues "
2898 "associated with your hardware. If you are "
2899 "experiencing problems please contact your Intel or "
2900 "hardware representative who provided you with this "
2901 "hardware.\n");
2902 break;
da4dd0f7
PWJ		 2903 default:
2904 dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err);
2905 }
9a799d71
AK		 2906
2907 /* reprogram the RAR[0] in case user changed it. */
c44ade9e 2908 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71
AK		 2909}
2910
9a799d71
AK		 2911/**
2912 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2913 * @adapter: board private structure
2914 * @rx_ring: ring to free buffers from
2915 **/
2916static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
b4617240 2917 struct ixgbe_ring *rx_ring)
9a799d71
AK		 2918{
2919 struct pci_dev *pdev = adapter->pdev;
2920 unsigned long size;
2921 unsigned int i;
2922
2923 /* Free all the Rx ring sk_buffs */
2924
2925 for (i = 0; i < rx_ring->count; i++) {
2926 struct ixgbe_rx_buffer *rx_buffer_info;
2927
2928 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2929 if (rx_buffer_info->dma) {
2930 pci_unmap_single(pdev, rx_buffer_info->dma,
b4617240
PW		 2931 rx_ring->rx_buf_len,
2932 PCI_DMA_FROMDEVICE);
9a799d71
AK		 2933 rx_buffer_info->dma = 0;
2934 }
2935 if (rx_buffer_info->skb) {
f8212f97 2936 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 2937 rx_buffer_info->skb = NULL;
f8212f97
AD		 2938 do {
2939 struct sk_buff *this = skb;
2940 skb = skb->prev;
2941 dev_kfree_skb(this);
2942 } while (skb);
9a799d71
AK		 2943 }
2944 if (!rx_buffer_info->page)
2945 continue;
4f57ca6e
JB		 2946 if (rx_buffer_info->page_dma) {
2947 pci_unmap_page(pdev, rx_buffer_info->page_dma,
2948 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
2949 rx_buffer_info->page_dma = 0;
2950 }
9a799d71
AK		 2951 put_page(rx_buffer_info->page);
2952 rx_buffer_info->page = NULL;
762f4c57 2953 rx_buffer_info->page_offset = 0;
9a799d71
AK		 2954 }
2955
2956 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2957 memset(rx_ring->rx_buffer_info, 0, size);
2958
2959 /* Zero out the descriptor ring */
2960 memset(rx_ring->desc, 0, rx_ring->size);
2961
2962 rx_ring->next_to_clean = 0;
2963 rx_ring->next_to_use = 0;
2964
9891ca7c
JB		 2965 if (rx_ring->head)
2966 writel(0, adapter->hw.hw_addr + rx_ring->head);
2967 if (rx_ring->tail)
2968 writel(0, adapter->hw.hw_addr + rx_ring->tail);
9a799d71
AK		 2969}
2970
2971/**
2972 * ixgbe_clean_tx_ring - Free Tx Buffers
2973 * @adapter: board private structure
2974 * @tx_ring: ring to be cleaned
2975 **/
2976static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
b4617240 2977 struct ixgbe_ring *tx_ring)
9a799d71
AK		 2978{
2979 struct ixgbe_tx_buffer *tx_buffer_info;
2980 unsigned long size;
2981 unsigned int i;
2982
2983 /* Free all the Tx ring sk_buffs */
2984
2985 for (i = 0; i < tx_ring->count; i++) {
2986 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2987 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2988 }
2989
2990 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2991 memset(tx_ring->tx_buffer_info, 0, size);
2992
2993 /* Zero out the descriptor ring */
2994 memset(tx_ring->desc, 0, tx_ring->size);
2995
2996 tx_ring->next_to_use = 0;
2997 tx_ring->next_to_clean = 0;
2998
9891ca7c
JB		 2999 if (tx_ring->head)
3000 writel(0, adapter->hw.hw_addr + tx_ring->head);
3001 if (tx_ring->tail)
3002 writel(0, adapter->hw.hw_addr + tx_ring->tail);
9a799d71
AK		 3003}
3004
3005/**
021230d4 3006 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 3007 * @adapter: board private structure
3008 **/
021230d4 3009static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3010{
3011 int i;
3012
021230d4
AV		 3013 for (i = 0; i < adapter->num_rx_queues; i++)
3014 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
9a799d71
AK		 3015}
3016
3017/**
021230d4 3018 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 3019 * @adapter: board private structure
3020 **/
021230d4 3021static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3022{
3023 int i;
3024
021230d4
AV		 3025 for (i = 0; i < adapter->num_tx_queues; i++)
3026 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
9a799d71
AK		 3027}
3028
3029void ixgbe_down(struct ixgbe_adapter *adapter)
3030{
3031 struct net_device *netdev = adapter->netdev;
7f821875 3032 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 3033 u32 rxctrl;
7f821875
JB		 3034 u32 txdctl;
3035 int i, j;
9a799d71
AK		 3036
3037 /* signal that we are down to the interrupt handler */
3038 set_bit(__IXGBE_DOWN, &adapter->state);
3039
3040 /* disable receives */
7f821875
JB		 3041 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3042 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71
AK		 3043
3044 netif_tx_disable(netdev);
3045
7f821875 3046 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 3047 msleep(10);
3048
7f821875
JB		 3049 netif_tx_stop_all_queues(netdev);
3050
9a799d71
AK		 3051 ixgbe_irq_disable(adapter);
3052
021230d4 3053 ixgbe_napi_disable_all(adapter);
7f821875 3054
0a1f87cb
DS		 3055 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3056 del_timer_sync(&adapter->sfp_timer);
9a799d71 3057 del_timer_sync(&adapter->watchdog_timer);
cf8280ee 3058 cancel_work_sync(&adapter->watchdog_task);
9a799d71 3059
c4cf55e5
PWJ		 3060 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3061 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3062 cancel_work_sync(&adapter->fdir_reinit_task);
3063
7f821875
JB		 3064 /* disable transmits in the hardware now that interrupts are off */
3065 for (i = 0; i < adapter->num_tx_queues; i++) {
3066 j = adapter->tx_ring[i].reg_idx;
3067 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3068 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
3069 (txdctl & ~IXGBE_TXDCTL_ENABLE));
3070 }
88512539
PW		 3071 /* Disable the Tx DMA engine on 82599 */
3072 if (hw->mac.type == ixgbe_mac_82599EB)
3073 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3074 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3075 ~IXGBE_DMATXCTL_TE));
7f821875 3076
9a799d71 3077 netif_carrier_off(netdev);
9a799d71 3078
6f4a0e45
PL		 3079 if (!pci_channel_offline(adapter->pdev))
3080 ixgbe_reset(adapter);
9a799d71
AK		 3081 ixgbe_clean_all_tx_rings(adapter);
3082 ixgbe_clean_all_rx_rings(adapter);
3083
5dd2d332 3084#ifdef CONFIG_IXGBE_DCA
96b0e0f6 3085 /* since we reset the hardware DCA settings were cleared */
e35ec126 3086 ixgbe_setup_dca(adapter);
96b0e0f6 3087#endif
9a799d71
AK		 3088}
3089
9a799d71 3090/**
021230d4
AV		 3091 * ixgbe_poll - NAPI Rx polling callback
3092 * @napi: structure for representing this polling device
3093 * @budget: how many packets driver is allowed to clean
3094 *
3095 * This function is used for legacy and MSI, NAPI mode
9a799d71 3096 **/
021230d4 3097static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 3098{
9a1a69ad
JB		 3099 struct ixgbe_q_vector *q_vector =
3100 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 3101 struct ixgbe_adapter *adapter = q_vector->adapter;
9a1a69ad 3102 int tx_clean_complete, work_done = 0;
9a799d71 3103
5dd2d332 3104#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 3105 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
3106 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
3107 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
3108 }
3109#endif
3110
fe49f04a 3111 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring);
78b6f4ce 3112 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
9a799d71 3113
9a1a69ad 3114 if (!tx_clean_complete)
d2c7ddd6
DM		 3115 work_done = budget;
3116
53e52c72
DM		 3117 /* If budget not fully consumed, exit the polling mode */
3118 if (work_done < budget) {
288379f0 3119 napi_complete(napi);
f7554a2b 3120 if (adapter->rx_itr_setting & 1)
f494e8fa 3121 ixgbe_set_itr(adapter);
d4f80882 3122 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 3123 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
9a799d71 3124 }
9a799d71
AK		 3125 return work_done;
3126}
3127
3128/**
3129 * ixgbe_tx_timeout - Respond to a Tx Hang
3130 * @netdev: network interface device structure
3131 **/
3132static void ixgbe_tx_timeout(struct net_device *netdev)
3133{
3134 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3135
3136 /* Do the reset outside of interrupt context */
3137 schedule_work(&adapter->reset_task);
3138}
3139
3140static void ixgbe_reset_task(struct work_struct *work)
3141{
3142 struct ixgbe_adapter *adapter;
3143 adapter = container_of(work, struct ixgbe_adapter, reset_task);
3144
2f90b865
AD		 3145 /* If we're already down or resetting, just bail */
3146 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3147 test_bit(__IXGBE_RESETTING, &adapter->state))
3148 return;
3149
9a799d71
AK		 3150 adapter->tx_timeout_count++;
3151
d4f80882 3152 ixgbe_reinit_locked(adapter);
9a799d71
AK		 3153}
3154
bc97114d
PWJ		 3155#ifdef CONFIG_IXGBE_DCB
3156static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
b9804972 3157{
bc97114d 3158 bool ret = false;
0cefafad 3159 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
b9804972 3160
0cefafad
JB		 3161 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3162 return ret;
3163
3164 f->mask = 0x7 << 3;
3165 adapter->num_rx_queues = f->indices;
3166 adapter->num_tx_queues = f->indices;
3167 ret = true;
2f90b865 3168
bc97114d
PWJ		 3169 return ret;
3170}
3171#endif
3172
4df10466
JB		 3173/**
3174 * ixgbe_set_rss_queues: Allocate queues for RSS
3175 * @adapter: board private structure to initialize
3176 *
3177 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
3178 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3179 *
3180 **/
bc97114d
PWJ		 3181static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3182{
3183 bool ret = false;
0cefafad 3184 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
bc97114d
PWJ		 3185
3186 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
0cefafad
JB		 3187 f->mask = 0xF;
3188 adapter->num_rx_queues = f->indices;
3189 adapter->num_tx_queues = f->indices;
bc97114d
PWJ		 3190 ret = true;
3191 } else {
bc97114d 3192 ret = false;
b9804972
JB		 3193 }
3194
bc97114d
PWJ		 3195 return ret;
3196}
3197
c4cf55e5
PWJ		 3198/**
3199 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3200 * @adapter: board private structure to initialize
3201 *
3202 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3203 * to the original CPU that initiated the Tx session. This runs in addition
3204 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3205 * Rx load across CPUs using RSS.
3206 *
3207 **/
3208static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3209{
3210 bool ret = false;
3211 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3212
3213 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3214 f_fdir->mask = 0;
3215
3216 /* Flow Director must have RSS enabled */
3217 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3218 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3219 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3220 adapter->num_tx_queues = f_fdir->indices;
3221 adapter->num_rx_queues = f_fdir->indices;
3222 ret = true;
3223 } else {
3224 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3225 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3226 }
3227 return ret;
3228}
3229
0331a832
YZ		 3230#ifdef IXGBE_FCOE
3231/**
3232 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3233 * @adapter: board private structure to initialize
3234 *
3235 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3236 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3237 * rx queues out of the max number of rx queues, instead, it is used as the
3238 * index of the first rx queue used by FCoE.
3239 *
3240 **/
3241static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3242{
3243 bool ret = false;
3244 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3245
3246 f->indices = min((int)num_online_cpus(), f->indices);
3247 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
8de8b2e6
YZ		 3248 adapter->num_rx_queues = 1;
3249 adapter->num_tx_queues = 1;
0331a832
YZ		 3250#ifdef CONFIG_IXGBE_DCB
3251 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
8de8b2e6 3252 DPRINTK(PROBE, INFO, "FCoE enabled with DCB \n");
0331a832
YZ		 3253 ixgbe_set_dcb_queues(adapter);
3254 }
3255#endif
3256 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
8de8b2e6 3257 DPRINTK(PROBE, INFO, "FCoE enabled with RSS \n");
8faa2a78
YZ		 3258 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3259 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3260 ixgbe_set_fdir_queues(adapter);
3261 else
3262 ixgbe_set_rss_queues(adapter);
0331a832
YZ		 3263 }
3264 /* adding FCoE rx rings to the end */
3265 f->mask = adapter->num_rx_queues;
3266 adapter->num_rx_queues += f->indices;
8de8b2e6 3267 adapter->num_tx_queues += f->indices;
0331a832
YZ		 3268
3269 ret = true;
3270 }
3271
3272 return ret;
3273}
3274
3275#endif /* IXGBE_FCOE */
4df10466
JB		 3276/*
3277 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
3278 * @adapter: board private structure to initialize
3279 *
3280 * This is the top level queue allocation routine. The order here is very
3281 * important, starting with the "most" number of features turned on at once,
3282 * and ending with the smallest set of features. This way large combinations
3283 * can be allocated if they're turned on, and smaller combinations are the
3284 * fallthrough conditions.
3285 *
3286 **/
bc97114d
PWJ		 3287static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
3288{
0331a832
YZ		 3289#ifdef IXGBE_FCOE
3290 if (ixgbe_set_fcoe_queues(adapter))
3291 goto done;
3292
3293#endif /* IXGBE_FCOE */
bc97114d
PWJ		 3294#ifdef CONFIG_IXGBE_DCB
3295 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 3296 goto done;
bc97114d
PWJ		 3297
3298#endif
c4cf55e5
PWJ		 3299 if (ixgbe_set_fdir_queues(adapter))
3300 goto done;
3301
bc97114d 3302 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 3303 goto done;
3304
3305 /* fallback to base case */
3306 adapter->num_rx_queues = 1;
3307 adapter->num_tx_queues = 1;
3308
3309done:
3310 /* Notify the stack of the (possibly) reduced Tx Queue count. */
3311 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
b9804972
JB		 3312}
3313
021230d4 3314static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
b4617240 3315 int vectors)
021230d4
AV		 3316{
3317 int err, vector_threshold;
3318
3319 /* We'll want at least 3 (vector_threshold):
3320 * 1) TxQ[0] Cleanup
3321 * 2) RxQ[0] Cleanup
3322 * 3) Other (Link Status Change, etc.)
3323 * 4) TCP Timer (optional)
3324 */
3325 vector_threshold = MIN_MSIX_COUNT;
3326
3327 /* The more we get, the more we will assign to Tx/Rx Cleanup
3328 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
3329 * Right now, we simply care about how many we'll get; we'll
3330 * set them up later while requesting irq's.
3331 */
3332 while (vectors >= vector_threshold) {
3333 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
b4617240 3334 vectors);
021230d4
AV		 3335 if (!err) /* Success in acquiring all requested vectors. */
3336 break;
3337 else if (err < 0)
3338 vectors = 0; /* Nasty failure, quit now */
3339 else /* err == number of vectors we should try again with */
3340 vectors = err;
3341 }
3342
3343 if (vectors < vector_threshold) {
3344 /* Can't allocate enough MSI-X interrupts? Oh well.
3345 * This just means we'll go with either a single MSI
3346 * vector or fall back to legacy interrupts.
3347 */
3348 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
3349 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3350 kfree(adapter->msix_entries);
3351 adapter->msix_entries = NULL;
021230d4
AV		 3352 } else {
3353 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 3354 /*
3355 * Adjust for only the vectors we'll use, which is minimum
3356 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3357 * vectors we were allocated.
3358 */
3359 adapter->num_msix_vectors = min(vectors,
3360 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 3361 }
3362}
3363
021230d4 3364/**
bc97114d 3365 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 3366 * @adapter: board private structure to initialize
3367 *
bc97114d
PWJ		 3368 * Cache the descriptor ring offsets for RSS to the assigned rings.
3369 *
021230d4 3370 **/
bc97114d 3371static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 3372{
bc97114d
PWJ		 3373 int i;
3374 bool ret = false;
3375
3376 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3377 for (i = 0; i < adapter->num_rx_queues; i++)
3378 adapter->rx_ring[i].reg_idx = i;
3379 for (i = 0; i < adapter->num_tx_queues; i++)
3380 adapter->tx_ring[i].reg_idx = i;
3381 ret = true;
3382 } else {
3383 ret = false;
3384 }
3385
3386 return ret;
3387}
3388
3389#ifdef CONFIG_IXGBE_DCB
3390/**
3391 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
3392 * @adapter: board private structure to initialize
3393 *
3394 * Cache the descriptor ring offsets for DCB to the assigned rings.
3395 *
3396 **/
3397static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
3398{
3399 int i;
3400 bool ret = false;
3401 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
3402
3403 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3404 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2f90b865
AD		 3405 /* the number of queues is assumed to be symmetric */
3406 for (i = 0; i < dcb_i; i++) {
3407 adapter->rx_ring[i].reg_idx = i << 3;
3408 adapter->tx_ring[i].reg_idx = i << 2;
3409 }
bc97114d 3410 ret = true;
e8e26350 3411 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
f92ef202
PW		 3412 if (dcb_i == 8) {
3413 /*
3414 * Tx TC0 starts at: descriptor queue 0
3415 * Tx TC1 starts at: descriptor queue 32
3416 * Tx TC2 starts at: descriptor queue 64
3417 * Tx TC3 starts at: descriptor queue 80
3418 * Tx TC4 starts at: descriptor queue 96
3419 * Tx TC5 starts at: descriptor queue 104
3420 * Tx TC6 starts at: descriptor queue 112
3421 * Tx TC7 starts at: descriptor queue 120
3422 *
3423 * Rx TC0-TC7 are offset by 16 queues each
3424 */
3425 for (i = 0; i < 3; i++) {
3426 adapter->tx_ring[i].reg_idx = i << 5;
3427 adapter->rx_ring[i].reg_idx = i << 4;
3428 }
3429 for ( ; i < 5; i++) {
3430 adapter->tx_ring[i].reg_idx =
3431 ((i + 2) << 4);
3432 adapter->rx_ring[i].reg_idx = i << 4;
3433 }
3434 for ( ; i < dcb_i; i++) {
3435 adapter->tx_ring[i].reg_idx =
3436 ((i + 8) << 3);
3437 adapter->rx_ring[i].reg_idx = i << 4;
3438 }
3439
3440 ret = true;
3441 } else if (dcb_i == 4) {
3442 /*
3443 * Tx TC0 starts at: descriptor queue 0
3444 * Tx TC1 starts at: descriptor queue 64
3445 * Tx TC2 starts at: descriptor queue 96
3446 * Tx TC3 starts at: descriptor queue 112
3447 *
3448 * Rx TC0-TC3 are offset by 32 queues each
3449 */
3450 adapter->tx_ring[0].reg_idx = 0;
3451 adapter->tx_ring[1].reg_idx = 64;
3452 adapter->tx_ring[2].reg_idx = 96;
3453 adapter->tx_ring[3].reg_idx = 112;
3454 for (i = 0 ; i < dcb_i; i++)
3455 adapter->rx_ring[i].reg_idx = i << 5;
3456
3457 ret = true;
3458 } else {
3459 ret = false;
e8e26350 3460 }
bc97114d
PWJ		 3461 } else {
3462 ret = false;
021230d4 3463 }
bc97114d
PWJ		 3464 } else {
3465 ret = false;
021230d4 3466 }
bc97114d
PWJ		 3467
3468 return ret;
3469}
3470#endif
3471
c4cf55e5
PWJ		 3472/**
3473 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
3474 * @adapter: board private structure to initialize
3475 *
3476 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
3477 *
3478 **/
3479static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
3480{
3481 int i;
3482 bool ret = false;
3483
3484 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3485 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3486 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
3487 for (i = 0; i < adapter->num_rx_queues; i++)
3488 adapter->rx_ring[i].reg_idx = i;
3489 for (i = 0; i < adapter->num_tx_queues; i++)
3490 adapter->tx_ring[i].reg_idx = i;
3491 ret = true;
3492 }
3493
3494 return ret;
3495}
3496
0331a832
YZ		 3497#ifdef IXGBE_FCOE
3498/**
3499 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
3500 * @adapter: board private structure to initialize
3501 *
3502 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
3503 *
3504 */
3505static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
3506{
8de8b2e6 3507 int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
0331a832
YZ		 3508 bool ret = false;
3509 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3510
3511 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3512#ifdef CONFIG_IXGBE_DCB
3513 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
8de8b2e6
YZ		 3514 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
3515
0331a832 3516 ixgbe_cache_ring_dcb(adapter);
8de8b2e6
YZ		 3517 /* find out queues in TC for FCoE */
3518 fcoe_rx_i = adapter->rx_ring[fcoe->tc].reg_idx + 1;
3519 fcoe_tx_i = adapter->tx_ring[fcoe->tc].reg_idx + 1;
3520 /*
3521 * In 82599, the number of Tx queues for each traffic
3522 * class for both 8-TC and 4-TC modes are:
3523 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
3524 * 8 TCs: 32 32 16 16 8 8 8 8
3525 * 4 TCs: 64 64 32 32
3526 * We have max 8 queues for FCoE, where 8 the is
3527 * FCoE redirection table size. If TC for FCoE is
3528 * less than or equal to TC3, we have enough queues
3529 * to add max of 8 queues for FCoE, so we start FCoE
3530 * tx descriptor from the next one, i.e., reg_idx + 1.
3531 * If TC for FCoE is above TC3, implying 8 TC mode,
3532 * and we need 8 for FCoE, we have to take all queues
3533 * in that traffic class for FCoE.
3534 */
3535 if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
3536 fcoe_tx_i--;
0331a832
YZ		 3537 }
3538#endif /* CONFIG_IXGBE_DCB */
3539 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
8faa2a78
YZ		 3540 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3541 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3542 ixgbe_cache_ring_fdir(adapter);
3543 else
3544 ixgbe_cache_ring_rss(adapter);
3545
8de8b2e6
YZ		 3546 fcoe_rx_i = f->mask;
3547 fcoe_tx_i = f->mask;
3548 }
3549 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
3550 adapter->rx_ring[f->mask + i].reg_idx = fcoe_rx_i;
3551 adapter->tx_ring[f->mask + i].reg_idx = fcoe_tx_i;
0331a832 3552 }
0331a832
YZ		 3553 ret = true;
3554 }
3555 return ret;
3556}
3557
3558#endif /* IXGBE_FCOE */
bc97114d
PWJ		 3559/**
3560 * ixgbe_cache_ring_register - Descriptor ring to register mapping
3561 * @adapter: board private structure to initialize
3562 *
3563 * Once we know the feature-set enabled for the device, we'll cache
3564 * the register offset the descriptor ring is assigned to.
3565 *
3566 * Note, the order the various feature calls is important. It must start with
3567 * the "most" features enabled at the same time, then trickle down to the
3568 * least amount of features turned on at once.
3569 **/
3570static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
3571{
3572 /* start with default case */
3573 adapter->rx_ring[0].reg_idx = 0;
3574 adapter->tx_ring[0].reg_idx = 0;
3575
0331a832
YZ		 3576#ifdef IXGBE_FCOE
3577 if (ixgbe_cache_ring_fcoe(adapter))
3578 return;
3579
3580#endif /* IXGBE_FCOE */
bc97114d
PWJ		 3581#ifdef CONFIG_IXGBE_DCB
3582 if (ixgbe_cache_ring_dcb(adapter))
3583 return;
3584
3585#endif
c4cf55e5
PWJ		 3586 if (ixgbe_cache_ring_fdir(adapter))
3587 return;
3588
bc97114d
PWJ		 3589 if (ixgbe_cache_ring_rss(adapter))
3590 return;
021230d4
AV		 3591}
3592
9a799d71
AK		 3593/**
3594 * ixgbe_alloc_queues - Allocate memory for all rings
3595 * @adapter: board private structure to initialize
3596 *
3597 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 3598 * number of queues at compile-time. The polling_netdev array is
3599 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 3600 **/
2f90b865 3601static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71
AK		 3602{
3603 int i;
3604
3605 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
b4617240 3606 sizeof(struct ixgbe_ring), GFP_KERNEL);
9a799d71 3607 if (!adapter->tx_ring)
021230d4 3608 goto err_tx_ring_allocation;
9a799d71
AK		 3609
3610 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
b4617240 3611 sizeof(struct ixgbe_ring), GFP_KERNEL);
021230d4
AV		 3612 if (!adapter->rx_ring)
3613 goto err_rx_ring_allocation;
9a799d71 3614
021230d4 3615 for (i = 0; i < adapter->num_tx_queues; i++) {
b9804972 3616 adapter->tx_ring[i].count = adapter->tx_ring_count;
021230d4
AV		 3617 adapter->tx_ring[i].queue_index = i;
3618 }
b9804972 3619
9a799d71 3620 for (i = 0; i < adapter->num_rx_queues; i++) {
b9804972 3621 adapter->rx_ring[i].count = adapter->rx_ring_count;
021230d4
AV		 3622 adapter->rx_ring[i].queue_index = i;
3623 }
3624
3625 ixgbe_cache_ring_register(adapter);
3626
3627 return 0;
3628
3629err_rx_ring_allocation:
3630 kfree(adapter->tx_ring);
3631err_tx_ring_allocation:
3632 return -ENOMEM;
3633}
3634
3635/**
3636 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3637 * @adapter: board private structure to initialize
3638 *
3639 * Attempt to configure the interrupts using the best available
3640 * capabilities of the hardware and the kernel.
3641 **/
feea6a57 3642static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 3643{
8be0e467 3644 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 3645 int err = 0;
3646 int vector, v_budget;
3647
3648 /*
3649 * It's easy to be greedy for MSI-X vectors, but it really
3650 * doesn't do us much good if we have a lot more vectors
3651 * than CPU's. So let's be conservative and only ask for
342bde1b 3652 * (roughly) the same number of vectors as there are CPU's.
021230d4
AV		 3653 */
3654 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
342bde1b 3655 (int)num_online_cpus()) + NON_Q_VECTORS;
021230d4
AV		 3656
3657 /*
3658 * At the same time, hardware can only support a maximum of
8be0e467
PW		 3659 * hw.mac->max_msix_vectors vectors. With features
3660 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3661 * descriptor queues supported by our device. Thus, we cap it off in
3662 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 3663 */
8be0e467 3664 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 3665
3666 /* A failure in MSI-X entry allocation isn't fatal, but it does
3667 * mean we disable MSI-X capabilities of the adapter. */
3668 adapter->msix_entries = kcalloc(v_budget,
b4617240 3669 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 3670 if (adapter->msix_entries) {
3671 for (vector = 0; vector < v_budget; vector++)
3672 adapter->msix_entries[vector].entry = vector;
021230d4 3673
7a921c93 3674 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 3675
7a921c93
AD		 3676 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3677 goto out;
3678 }
021230d4 3679
7a921c93
AD		 3680 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
3681 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
c4cf55e5
PWJ		 3682 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3683 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3684 adapter->atr_sample_rate = 0;
7a921c93 3685 ixgbe_set_num_queues(adapter);
021230d4 3686
021230d4
AV		 3687 err = pci_enable_msi(adapter->pdev);
3688 if (!err) {
3689 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
3690 } else {
3691 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
b4617240 3692 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 3693 /* reset err */
3694 err = 0;
3695 }
3696
3697out:
021230d4
AV		 3698 return err;
3699}
3700
7a921c93
AD		 3701/**
3702 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
3703 * @adapter: board private structure to initialize
3704 *
3705 * We allocate one q_vector per queue interrupt. If allocation fails we
3706 * return -ENOMEM.
3707 **/
3708static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
3709{
3710 int q_idx, num_q_vectors;
3711 struct ixgbe_q_vector *q_vector;
3712 int napi_vectors;
3713 int (*poll)(struct napi_struct *, int);
3714
3715 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3716 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3717 napi_vectors = adapter->num_rx_queues;
91281fd3 3718 poll = &ixgbe_clean_rxtx_many;
7a921c93
AD		 3719 } else {
3720 num_q_vectors = 1;
3721 napi_vectors = 1;
3722 poll = &ixgbe_poll;
3723 }
3724
3725 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3726 q_vector = kzalloc(sizeof(struct ixgbe_q_vector), GFP_KERNEL);
3727 if (!q_vector)
3728 goto err_out;
3729 q_vector->adapter = adapter;
f7554a2b
NS		 3730 if (q_vector->txr_count && !q_vector->rxr_count)
3731 q_vector->eitr = adapter->tx_eitr_param;
3732 else
3733 q_vector->eitr = adapter->rx_eitr_param;
fe49f04a 3734 q_vector->v_idx = q_idx;
91281fd3 3735 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
7a921c93
AD		 3736 adapter->q_vector[q_idx] = q_vector;
3737 }
3738
3739 return 0;
3740
3741err_out:
3742 while (q_idx) {
3743 q_idx--;
3744 q_vector = adapter->q_vector[q_idx];
3745 netif_napi_del(&q_vector->napi);
3746 kfree(q_vector);
3747 adapter->q_vector[q_idx] = NULL;
3748 }
3749 return -ENOMEM;
3750}
3751
3752/**
3753 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
3754 * @adapter: board private structure to initialize
3755 *
3756 * This function frees the memory allocated to the q_vectors. In addition if
3757 * NAPI is enabled it will delete any references to the NAPI struct prior
3758 * to freeing the q_vector.
3759 **/
3760static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
3761{
3762 int q_idx, num_q_vectors;
7a921c93 3763
91281fd3 3764 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 3765 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 3766 else
7a921c93 3767 num_q_vectors = 1;
7a921c93
AD		 3768
3769 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3770 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
7a921c93 3771 adapter->q_vector[q_idx] = NULL;
91281fd3 3772 netif_napi_del(&q_vector->napi);
7a921c93
AD		 3773 kfree(q_vector);
3774 }
3775}
3776
7b25cdba 3777static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 3778{
3779 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3780 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3781 pci_disable_msix(adapter->pdev);
3782 kfree(adapter->msix_entries);
3783 adapter->msix_entries = NULL;
3784 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
3785 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
3786 pci_disable_msi(adapter->pdev);
3787 }
3788 return;
3789}
3790
3791/**
3792 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
3793 * @adapter: board private structure to initialize
3794 *
3795 * We determine which interrupt scheme to use based on...
3796 * - Kernel support (MSI, MSI-X)
3797 * - which can be user-defined (via MODULE_PARAM)
3798 * - Hardware queue count (num_*_queues)
3799 * - defined by miscellaneous hardware support/features (RSS, etc.)
3800 **/
2f90b865 3801int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 3802{
3803 int err;
3804
3805 /* Number of supported queues */
3806 ixgbe_set_num_queues(adapter);
3807
021230d4
AV		 3808 err = ixgbe_set_interrupt_capability(adapter);
3809 if (err) {
3810 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
3811 goto err_set_interrupt;
9a799d71
AK		 3812 }
3813
7a921c93
AD		 3814 err = ixgbe_alloc_q_vectors(adapter);
3815 if (err) {
3816 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
3817 "vectors\n");
3818 goto err_alloc_q_vectors;
3819 }
3820
3821 err = ixgbe_alloc_queues(adapter);
3822 if (err) {
3823 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
3824 goto err_alloc_queues;
3825 }
3826
021230d4 3827 DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
b4617240
PW		 3828 "Tx Queue count = %u\n",
3829 (adapter->num_rx_queues > 1) ? "Enabled" :
3830 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 3831
3832 set_bit(__IXGBE_DOWN, &adapter->state);
3833
9a799d71 3834 return 0;
021230d4 3835
7a921c93
AD		 3836err_alloc_queues:
3837 ixgbe_free_q_vectors(adapter);
3838err_alloc_q_vectors:
3839 ixgbe_reset_interrupt_capability(adapter);
021230d4 3840err_set_interrupt:
7a921c93
AD		 3841 return err;
3842}
3843
3844/**
3845 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
3846 * @adapter: board private structure to clear interrupt scheme on
3847 *
3848 * We go through and clear interrupt specific resources and reset the structure
3849 * to pre-load conditions
3850 **/
3851void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
3852{
021230d4
AV		 3853 kfree(adapter->tx_ring);
3854 kfree(adapter->rx_ring);
7a921c93
AD		 3855 adapter->tx_ring = NULL;
3856 adapter->rx_ring = NULL;
3857
3858 ixgbe_free_q_vectors(adapter);
3859 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 3860}
3861
c4900be0
DS		 3862/**
3863 * ixgbe_sfp_timer - worker thread to find a missing module
3864 * @data: pointer to our adapter struct
3865 **/
3866static void ixgbe_sfp_timer(unsigned long data)
3867{
3868 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3869
4df10466
JB		 3870 /*
3871 * Do the sfp_timer outside of interrupt context due to the
c4900be0
DS		 3872 * delays that sfp+ detection requires
3873 */
3874 schedule_work(&adapter->sfp_task);
3875}
3876
3877/**
3878 * ixgbe_sfp_task - worker thread to find a missing module
3879 * @work: pointer to work_struct containing our data
3880 **/
3881static void ixgbe_sfp_task(struct work_struct *work)
3882{
3883 struct ixgbe_adapter *adapter = container_of(work,
3884 struct ixgbe_adapter,
3885 sfp_task);
3886 struct ixgbe_hw *hw = &adapter->hw;
3887
3888 if ((hw->phy.type == ixgbe_phy_nl) &&
3889 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
3890 s32 ret = hw->phy.ops.identify_sfp(hw);
63d6e1d8 3891 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
c4900be0
DS		 3892 goto reschedule;
3893 ret = hw->phy.ops.reset(hw);
3894 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
88d2b81f
DS		 3895 dev_err(&adapter->pdev->dev, "failed to initialize "
3896 "because an unsupported SFP+ module type "
3897 "was detected.\n"
3898 "Reload the driver after installing a "
3899 "supported module.\n");
c4900be0
DS		 3900 unregister_netdev(adapter->netdev);
3901 } else {
3902 DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
3903 hw->phy.sfp_type);
3904 }
3905 /* don't need this routine any more */
3906 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3907 }
3908 return;
3909reschedule:
3910 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
3911 mod_timer(&adapter->sfp_timer,
3912 round_jiffies(jiffies + (2 * HZ)));
3913}
3914
9a799d71
AK		 3915/**
3916 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
3917 * @adapter: board private structure to initialize
3918 *
3919 * ixgbe_sw_init initializes the Adapter private data structure.
3920 * Fields are initialized based on PCI device information and
3921 * OS network device settings (MTU size).
3922 **/
3923static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
3924{
3925 struct ixgbe_hw *hw = &adapter->hw;
3926 struct pci_dev *pdev = adapter->pdev;
021230d4 3927 unsigned int rss;
7a6b6f51 3928#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3929 int j;
3930 struct tc_configuration *tc;
3931#endif
021230d4 3932
c44ade9e
JB		 3933 /* PCI config space info */
3934
3935 hw->vendor_id = pdev->vendor;
3936 hw->device_id = pdev->device;
3937 hw->revision_id = pdev->revision;
3938 hw->subsystem_vendor_id = pdev->subsystem_vendor;
3939 hw->subsystem_device_id = pdev->subsystem_device;
3940
021230d4
AV		 3941 /* Set capability flags */
3942 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
3943 adapter->ring_feature[RING_F_RSS].indices = rss;
3944 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
2f90b865 3945 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
bf069c97
DS		 3946 if (hw->mac.type == ixgbe_mac_82598EB) {
3947 if (hw->device_id == IXGBE_DEV_ID_82598AT)
3948 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 3949 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bf069c97 3950 } else if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 3951 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
0c19d6af
PWJ		 3952 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
3953 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
c4cf55e5
PWJ		 3954 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
3955 adapter->ring_feature[RING_F_FDIR].indices =
3956 IXGBE_MAX_FDIR_INDICES;
3957 adapter->atr_sample_rate = 20;
3958 adapter->fdir_pballoc = 0;
eacd73f7 3959#ifdef IXGBE_FCOE
0d551589
YZ		 3960 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
3961 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
3962 adapter->ring_feature[RING_F_FCOE].indices = 0;
61a0f421 3963#ifdef CONFIG_IXGBE_DCB
6ee16520
YZ		 3964 /* Default traffic class to use for FCoE */
3965 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
61a0f421 3966#endif
eacd73f7 3967#endif /* IXGBE_FCOE */
f8212f97 3968 }
2f90b865 3969
7a6b6f51 3970#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3971 /* Configure DCB traffic classes */
3972 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
3973 tc = &adapter->dcb_cfg.tc_config[j];
3974 tc->path[DCB_TX_CONFIG].bwg_id = 0;
3975 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
3976 tc->path[DCB_RX_CONFIG].bwg_id = 0;
3977 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
3978 tc->dcb_pfc = pfc_disabled;
3979 }
3980 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
3981 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
3982 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
264857b8 3983 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865
AD		 3984 adapter->dcb_cfg.round_robin_enable = false;
3985 adapter->dcb_set_bitmap = 0x00;
3986 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
3987 adapter->ring_feature[RING_F_DCB].indices);
3988
3989#endif
9a799d71
AK		 3990
3991 /* default flow control settings */
cd7664f6 3992 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 3993 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 3994#ifdef CONFIG_DCB
3995 adapter->last_lfc_mode = hw->fc.current_mode;
3996#endif
2b9ade93
JB		 3997 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
3998 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
3999 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4000 hw->fc.send_xon = true;
71fd570b 4001 hw->fc.disable_fc_autoneg = false;
9a799d71 4002
30efa5a3 4003 /* enable itr by default in dynamic mode */
f7554a2b
NS		 4004 adapter->rx_itr_setting = 1;
4005 adapter->rx_eitr_param = 20000;
4006 adapter->tx_itr_setting = 1;
4007 adapter->tx_eitr_param = 10000;
30efa5a3
JB		 4008
4009 /* set defaults for eitr in MegaBytes */
4010 adapter->eitr_low = 10;
4011 adapter->eitr_high = 20;
4012
4013 /* set default ring sizes */
4014 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4015 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4016
9a799d71 4017 /* initialize eeprom parameters */
c44ade9e 4018 if (ixgbe_init_eeprom_params_generic(hw)) {
9a799d71
AK		 4019 dev_err(&pdev->dev, "EEPROM initialization failed\n");
4020 return -EIO;
4021 }
4022
021230d4 4023 /* enable rx csum by default */
9a799d71
AK		 4024 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4025
9a799d71
AK		 4026 set_bit(__IXGBE_DOWN, &adapter->state);
4027
4028 return 0;
4029}
4030
4031/**
4032 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4033 * @adapter: board private structure
3a581073 4034 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4035 *
4036 * Return 0 on success, negative on failure
4037 **/
4038int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
e01c31a5 4039 struct ixgbe_ring *tx_ring)
9a799d71
AK		 4040{
4041 struct pci_dev *pdev = adapter->pdev;
4042 int size;
4043
3a581073
JB		 4044 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4045 tx_ring->tx_buffer_info = vmalloc(size);
e01c31a5
JB		 4046 if (!tx_ring->tx_buffer_info)
4047 goto err;
3a581073 4048 memset(tx_ring->tx_buffer_info, 0, size);
9a799d71
AK		 4049
4050 /* round up to nearest 4K */
12207e49 4051 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 4052 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 4053
3a581073
JB		 4054 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
4055 &tx_ring->dma);
e01c31a5
JB		 4056 if (!tx_ring->desc)
4057 goto err;
9a799d71 4058
3a581073
JB		 4059 tx_ring->next_to_use = 0;
4060 tx_ring->next_to_clean = 0;
4061 tx_ring->work_limit = tx_ring->count;
9a799d71 4062 return 0;
e01c31a5
JB		 4063
4064err:
4065 vfree(tx_ring->tx_buffer_info);
4066 tx_ring->tx_buffer_info = NULL;
4067 DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
4068 "descriptor ring\n");
4069 return -ENOMEM;
9a799d71
AK		 4070}
4071
69888674
AD		 4072/**
4073 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4074 * @adapter: board private structure
4075 *
4076 * If this function returns with an error, then it's possible one or
4077 * more of the rings is populated (while the rest are not). It is the
4078 * callers duty to clean those orphaned rings.
4079 *
4080 * Return 0 on success, negative on failure
4081 **/
4082static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4083{
4084 int i, err = 0;
4085
4086 for (i = 0; i < adapter->num_tx_queues; i++) {
4087 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
4088 if (!err)
4089 continue;
4090 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
4091 break;
4092 }
4093
4094 return err;
4095}
4096
9a799d71
AK		 4097/**
4098 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4099 * @adapter: board private structure
3a581073 4100 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4101 *
4102 * Returns 0 on success, negative on failure
4103 **/
4104int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
b4617240 4105 struct ixgbe_ring *rx_ring)
9a799d71
AK		 4106{
4107 struct pci_dev *pdev = adapter->pdev;
021230d4 4108 int size;
9a799d71 4109
3a581073
JB		 4110 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4111 rx_ring->rx_buffer_info = vmalloc(size);
4112 if (!rx_ring->rx_buffer_info) {
9a799d71 4113 DPRINTK(PROBE, ERR,
b4617240 4114 "vmalloc allocation failed for the rx desc ring\n");
177db6ff 4115 goto alloc_failed;
9a799d71 4116 }
3a581073 4117 memset(rx_ring->rx_buffer_info, 0, size);
9a799d71 4118
9a799d71 4119 /* Round up to nearest 4K */
3a581073
JB		 4120 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4121 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 4122
3a581073 4123 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
9a799d71 4124
3a581073 4125 if (!rx_ring->desc) {
9a799d71 4126 DPRINTK(PROBE, ERR,
b4617240 4127 "Memory allocation failed for the rx desc ring\n");
3a581073 4128 vfree(rx_ring->rx_buffer_info);
177db6ff 4129 goto alloc_failed;
9a799d71
AK		 4130 }
4131
3a581073
JB		 4132 rx_ring->next_to_clean = 0;
4133 rx_ring->next_to_use = 0;
9a799d71
AK		 4134
4135 return 0;
177db6ff
MC		 4136
4137alloc_failed:
177db6ff 4138 return -ENOMEM;
9a799d71
AK		 4139}
4140
69888674
AD		 4141/**
4142 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4143 * @adapter: board private structure
4144 *
4145 * If this function returns with an error, then it's possible one or
4146 * more of the rings is populated (while the rest are not). It is the
4147 * callers duty to clean those orphaned rings.
4148 *
4149 * Return 0 on success, negative on failure
4150 **/
4151
4152static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4153{
4154 int i, err = 0;
4155
4156 for (i = 0; i < adapter->num_rx_queues; i++) {
4157 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
4158 if (!err)
4159 continue;
4160 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
4161 break;
4162 }
4163
4164 return err;
4165}
4166
9a799d71
AK		 4167/**
4168 * ixgbe_free_tx_resources - Free Tx Resources per Queue
4169 * @adapter: board private structure
4170 * @tx_ring: Tx descriptor ring for a specific queue
4171 *
4172 * Free all transmit software resources
4173 **/
c431f97e
JB		 4174void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
4175 struct ixgbe_ring *tx_ring)
9a799d71
AK		 4176{
4177 struct pci_dev *pdev = adapter->pdev;
4178
4179 ixgbe_clean_tx_ring(adapter, tx_ring);
4180
4181 vfree(tx_ring->tx_buffer_info);
4182 tx_ring->tx_buffer_info = NULL;
4183
4184 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
4185
4186 tx_ring->desc = NULL;
4187}
4188
4189/**
4190 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4191 * @adapter: board private structure
4192 *
4193 * Free all transmit software resources
4194 **/
4195static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4196{
4197 int i;
4198
4199 for (i = 0; i < adapter->num_tx_queues; i++)
9891ca7c
JB		 4200 if (adapter->tx_ring[i].desc)
4201 ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
9a799d71
AK		 4202}
4203
4204/**
b4617240 4205 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 4206 * @adapter: board private structure
4207 * @rx_ring: ring to clean the resources from
4208 *
4209 * Free all receive software resources
4210 **/
c431f97e
JB		 4211void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
4212 struct ixgbe_ring *rx_ring)
9a799d71
AK		 4213{
4214 struct pci_dev *pdev = adapter->pdev;
4215
4216 ixgbe_clean_rx_ring(adapter, rx_ring);
4217
4218 vfree(rx_ring->rx_buffer_info);
4219 rx_ring->rx_buffer_info = NULL;
4220
4221 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
4222
4223 rx_ring->desc = NULL;
4224}
4225
4226/**
4227 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4228 * @adapter: board private structure
4229 *
4230 * Free all receive software resources
4231 **/
4232static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4233{
4234 int i;
4235
4236 for (i = 0; i < adapter->num_rx_queues; i++)
9891ca7c
JB		 4237 if (adapter->rx_ring[i].desc)
4238 ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
9a799d71
AK		 4239}
4240
9a799d71
AK		 4241/**
4242 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4243 * @netdev: network interface device structure
4244 * @new_mtu: new value for maximum frame size
4245 *
4246 * Returns 0 on success, negative on failure
4247 **/
4248static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4249{
4250 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4251 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4252
42c783c5
JB		 4253 /* MTU < 68 is an error and causes problems on some kernels */
4254 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
9a799d71
AK		 4255 return -EINVAL;
4256
021230d4 4257 DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
b4617240 4258 netdev->mtu, new_mtu);
021230d4 4259 /* must set new MTU before calling down or up */
9a799d71
AK		 4260 netdev->mtu = new_mtu;
4261
d4f80882
AV		 4262 if (netif_running(netdev))
4263 ixgbe_reinit_locked(adapter);
9a799d71
AK		 4264
4265 return 0;
4266}
4267
4268/**
4269 * ixgbe_open - Called when a network interface is made active
4270 * @netdev: network interface device structure
4271 *
4272 * Returns 0 on success, negative value on failure
4273 *
4274 * The open entry point is called when a network interface is made
4275 * active by the system (IFF_UP). At this point all resources needed
4276 * for transmit and receive operations are allocated, the interrupt
4277 * handler is registered with the OS, the watchdog timer is started,
4278 * and the stack is notified that the interface is ready.
4279 **/
4280static int ixgbe_open(struct net_device *netdev)
4281{
4282 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4283 int err;
4bebfaa5
AK		 4284
4285 /* disallow open during test */
4286 if (test_bit(__IXGBE_TESTING, &adapter->state))
4287 return -EBUSY;
9a799d71 4288
54386467
JB		 4289 netif_carrier_off(netdev);
4290
9a799d71
AK		 4291 /* allocate transmit descriptors */
4292 err = ixgbe_setup_all_tx_resources(adapter);
4293 if (err)
4294 goto err_setup_tx;
4295
9a799d71
AK		 4296 /* allocate receive descriptors */
4297 err = ixgbe_setup_all_rx_resources(adapter);
4298 if (err)
4299 goto err_setup_rx;
4300
4301 ixgbe_configure(adapter);
4302
021230d4 4303 err = ixgbe_request_irq(adapter);
9a799d71
AK		 4304 if (err)
4305 goto err_req_irq;
4306
9a799d71
AK		 4307 err = ixgbe_up_complete(adapter);
4308 if (err)
4309 goto err_up;
4310
d55b53ff
JK		 4311 netif_tx_start_all_queues(netdev);
4312
9a799d71
AK		 4313 return 0;
4314
4315err_up:
5eba3699 4316 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4317 ixgbe_free_irq(adapter);
4318err_req_irq:
9a799d71 4319err_setup_rx:
a20a1199 4320 ixgbe_free_all_rx_resources(adapter);
9a799d71 4321err_setup_tx:
a20a1199 4322 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 4323 ixgbe_reset(adapter);
4324
4325 return err;
4326}
4327
4328/**
4329 * ixgbe_close - Disables a network interface
4330 * @netdev: network interface device structure
4331 *
4332 * Returns 0, this is not allowed to fail
4333 *
4334 * The close entry point is called when an interface is de-activated
4335 * by the OS. The hardware is still under the drivers control, but
4336 * needs to be disabled. A global MAC reset is issued to stop the
4337 * hardware, and all transmit and receive resources are freed.
4338 **/
4339static int ixgbe_close(struct net_device *netdev)
4340{
4341 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 4342
4343 ixgbe_down(adapter);
4344 ixgbe_free_irq(adapter);
4345
4346 ixgbe_free_all_tx_resources(adapter);
4347 ixgbe_free_all_rx_resources(adapter);
4348
5eba3699 4349 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4350
4351 return 0;
4352}
4353
b3c8b4ba
AD		 4354#ifdef CONFIG_PM
4355static int ixgbe_resume(struct pci_dev *pdev)
4356{
4357 struct net_device *netdev = pci_get_drvdata(pdev);
4358 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4359 u32 err;
4360
4361 pci_set_power_state(pdev, PCI_D0);
4362 pci_restore_state(pdev);
9ce77666 4363
4364 err = pci_enable_device_mem(pdev);
b3c8b4ba 4365 if (err) {
69888674 4366 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
b3c8b4ba
AD		 4367 "suspend\n");
4368 return err;
4369 }
4370 pci_set_master(pdev);
4371
dd4d8ca6 4372 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 4373
4374 err = ixgbe_init_interrupt_scheme(adapter);
4375 if (err) {
4376 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
4377 "device\n");
4378 return err;
4379 }
4380
b3c8b4ba
AD		 4381 ixgbe_reset(adapter);
4382
495dce12
WJP		 4383 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4384
b3c8b4ba
AD		 4385 if (netif_running(netdev)) {
4386 err = ixgbe_open(adapter->netdev);
4387 if (err)
4388 return err;
4389 }
4390
4391 netif_device_attach(netdev);
4392
4393 return 0;
4394}
b3c8b4ba 4395#endif /* CONFIG_PM */
9d8d05ae
RW		 4396
4397static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba
AD		 4398{
4399 struct net_device *netdev = pci_get_drvdata(pdev);
4400 struct ixgbe_adapter *adapter = netdev_priv(netdev);
e8e26350
PW		 4401 struct ixgbe_hw *hw = &adapter->hw;
4402 u32 ctrl, fctrl;
4403 u32 wufc = adapter->wol;
b3c8b4ba
AD		 4404#ifdef CONFIG_PM
4405 int retval = 0;
4406#endif
4407
4408 netif_device_detach(netdev);
4409
4410 if (netif_running(netdev)) {
4411 ixgbe_down(adapter);
4412 ixgbe_free_irq(adapter);
4413 ixgbe_free_all_tx_resources(adapter);
4414 ixgbe_free_all_rx_resources(adapter);
4415 }
7a921c93 4416 ixgbe_clear_interrupt_scheme(adapter);
b3c8b4ba
AD		 4417
4418#ifdef CONFIG_PM
4419 retval = pci_save_state(pdev);
4420 if (retval)
4421 return retval;
4df10466 4422
b3c8b4ba 4423#endif
e8e26350
PW		 4424 if (wufc) {
4425 ixgbe_set_rx_mode(netdev);
b3c8b4ba 4426
e8e26350
PW		 4427 /* turn on all-multi mode if wake on multicast is enabled */
4428 if (wufc & IXGBE_WUFC_MC) {
4429 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4430 fctrl |= IXGBE_FCTRL_MPE;
4431 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4432 }
4433
4434 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4435 ctrl |= IXGBE_CTRL_GIO_DIS;
4436 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4437
4438 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4439 } else {
4440 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4441 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4442 }
4443
dd4d8ca6
DS		 4444 if (wufc && hw->mac.type == ixgbe_mac_82599EB)
4445 pci_wake_from_d3(pdev, true);
4446 else
4447 pci_wake_from_d3(pdev, false);
b3c8b4ba 4448
9d8d05ae
RW		 4449 *enable_wake = !!wufc;
4450
b3c8b4ba
AD		 4451 ixgbe_release_hw_control(adapter);
4452
4453 pci_disable_device(pdev);
4454
9d8d05ae
RW		 4455 return 0;
4456}
4457
4458#ifdef CONFIG_PM
4459static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4460{
4461 int retval;
4462 bool wake;
4463
4464 retval = __ixgbe_shutdown(pdev, &wake);
4465 if (retval)
4466 return retval;
4467
4468 if (wake) {
4469 pci_prepare_to_sleep(pdev);
4470 } else {
4471 pci_wake_from_d3(pdev, false);
4472 pci_set_power_state(pdev, PCI_D3hot);
4473 }
b3c8b4ba
AD		 4474
4475 return 0;
4476}
9d8d05ae 4477#endif /* CONFIG_PM */
b3c8b4ba
AD		 4478
4479static void ixgbe_shutdown(struct pci_dev *pdev)
4480{
9d8d05ae
RW		 4481 bool wake;
4482
4483 __ixgbe_shutdown(pdev, &wake);
4484
4485 if (system_state == SYSTEM_POWER_OFF) {
4486 pci_wake_from_d3(pdev, wake);
4487 pci_set_power_state(pdev, PCI_D3hot);
4488 }
b3c8b4ba
AD		 4489}
4490
9a799d71
AK		 4491/**
4492 * ixgbe_update_stats - Update the board statistics counters.
4493 * @adapter: board private structure
4494 **/
4495void ixgbe_update_stats(struct ixgbe_adapter *adapter)
4496{
2d86f139 4497 struct net_device *netdev = adapter->netdev;
9a799d71 4498 struct ixgbe_hw *hw = &adapter->hw;
6f11eef7
AV		 4499 u64 total_mpc = 0;
4500 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
9a799d71 4501
94b982b2 4502 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 4503 u64 rsc_count = 0;
94b982b2 4504 u64 rsc_flush = 0;
d51019a4
PW		 4505 for (i = 0; i < 16; i++)
4506 adapter->hw_rx_no_dma_resources +=
4507 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
94b982b2 4508 for (i = 0; i < adapter->num_rx_queues; i++) {
f8212f97 4509 rsc_count += adapter->rx_ring[i].rsc_count;
94b982b2
MC		 4510 rsc_flush += adapter->rx_ring[i].rsc_flush;
4511 }
4512 adapter->rsc_total_count = rsc_count;
4513 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 4514 }
4515
7ca3bc58
JB		 4516 /* gather some stats to the adapter struct that are per queue */
4517 for (i = 0; i < adapter->num_tx_queues; i++)
4518 adapter->restart_queue += adapter->tx_ring[i].restart_queue;
4519
4520 for (i = 0; i < adapter->num_rx_queues; i++)
4521 adapter->non_eop_descs += adapter->tx_ring[i].non_eop_descs;
4522
9a799d71 4523 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 4524 for (i = 0; i < 8; i++) {
4525 /* for packet buffers not used, the register should read 0 */
4526 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
4527 missed_rx += mpc;
4528 adapter->stats.mpc[i] += mpc;
4529 total_mpc += adapter->stats.mpc[i];
e8e26350
PW		 4530 if (hw->mac.type == ixgbe_mac_82598EB)
4531 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2f90b865
AD		 4532 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
4533 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
4534 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
4535 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
e8e26350
PW		 4536 if (hw->mac.type == ixgbe_mac_82599EB) {
4537 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4538 IXGBE_PXONRXCNT(i));
4539 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4540 IXGBE_PXOFFRXCNT(i));
4541 adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
e8e26350
PW		 4542 } else {
4543 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4544 IXGBE_PXONRXC(i));
4545 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4546 IXGBE_PXOFFRXC(i));
4547 }
2f90b865
AD		 4548 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
4549 IXGBE_PXONTXC(i));
2f90b865 4550 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
e8e26350 4551 IXGBE_PXOFFTXC(i));
6f11eef7
AV		 4552 }
4553 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
4554 /* work around hardware counting issue */
4555 adapter->stats.gprc -= missed_rx;
4556
4557 /* 82598 hardware only has a 32 bit counter in the high register */
e8e26350 4558 if (hw->mac.type == ixgbe_mac_82599EB) {
aad71918 4559 u64 tmp;
e8e26350 4560 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
aad71918
BG		 4561 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF; /* 4 high bits of GORC */
4562 adapter->stats.gorc += (tmp << 32);
e8e26350 4563 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
aad71918
BG		 4564 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF; /* 4 high bits of GOTC */
4565 adapter->stats.gotc += (tmp << 32);
e8e26350
PW		 4566 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
4567 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
4568 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
4569 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
c4cf55e5
PWJ		 4570 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
4571 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c
YZ		 4572#ifdef IXGBE_FCOE
4573 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
4574 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
4575 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
4576 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
4577 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
4578 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
4579#endif /* IXGBE_FCOE */
e8e26350
PW		 4580 } else {
4581 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
4582 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
4583 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
4584 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
4585 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
4586 }
9a799d71
AK		 4587 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
4588 adapter->stats.bprc += bprc;
4589 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350
PW		 4590 if (hw->mac.type == ixgbe_mac_82598EB)
4591 adapter->stats.mprc -= bprc;
9a799d71
AK		 4592 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
4593 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
4594 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
4595 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
4596 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
4597 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
4598 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
9a799d71 4599 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7
AV		 4600 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
4601 adapter->stats.lxontxc += lxon;
4602 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
4603 adapter->stats.lxofftxc += lxoff;
9a799d71
AK		 4604 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4605 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6f11eef7
AV		 4606 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
4607 /*
4608 * 82598 errata - tx of flow control packets is included in tx counters
4609 */
4610 xon_off_tot = lxon + lxoff;
4611 adapter->stats.gptc -= xon_off_tot;
4612 adapter->stats.mptc -= xon_off_tot;
4613 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
9a799d71
AK		 4614 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4615 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
4616 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
9a799d71
AK		 4617 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
4618 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6f11eef7 4619 adapter->stats.ptc64 -= xon_off_tot;
9a799d71
AK		 4620 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
4621 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
4622 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
4623 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
4624 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
9a799d71
AK		 4625 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
4626
4627 /* Fill out the OS statistics structure */
2d86f139 4628 netdev->stats.multicast = adapter->stats.mprc;
9a799d71
AK		 4629
4630 /* Rx Errors */
2d86f139 4631 netdev->stats.rx_errors = adapter->stats.crcerrs +
b4617240 4632 adapter->stats.rlec;
2d86f139
AK		 4633 netdev->stats.rx_dropped = 0;
4634 netdev->stats.rx_length_errors = adapter->stats.rlec;
4635 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
4636 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 4637}
4638
4639/**
4640 * ixgbe_watchdog - Timer Call-back
4641 * @data: pointer to adapter cast into an unsigned long
4642 **/
4643static void ixgbe_watchdog(unsigned long data)
4644{
4645 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
cf8280ee 4646 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 4647 u64 eics = 0;
4648 int i;
cf8280ee 4649
fe49f04a
AD		 4650 /*
4651 * Do the watchdog outside of interrupt context due to the lovely
4652 * delays that some of the newer hardware requires
4653 */
22d5a71b 4654
fe49f04a
AD		 4655 if (test_bit(__IXGBE_DOWN, &adapter->state))
4656 goto watchdog_short_circuit;
22d5a71b 4657
fe49f04a
AD		 4658 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
4659 /*
4660 * for legacy and MSI interrupts don't set any bits
4661 * that are enabled for EIAM, because this operation
4662 * would set *both* EIMS and EICS for any bit in EIAM
4663 */
4664 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4665 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4666 goto watchdog_reschedule;
4667 }
4668
4669 /* get one bit for every active tx/rx interrupt vector */
4670 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
4671 struct ixgbe_q_vector *qv = adapter->q_vector[i];
4672 if (qv->rxr_count || qv->txr_count)
4673 eics |= ((u64)1 << i);
cf8280ee 4674 }
9a799d71 4675
fe49f04a
AD		 4676 /* Cause software interrupt to ensure rx rings are cleaned */
4677 ixgbe_irq_rearm_queues(adapter, eics);
4678
4679watchdog_reschedule:
4680 /* Reset the timer */
4681 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
4682
4683watchdog_short_circuit:
cf8280ee
JB		 4684 schedule_work(&adapter->watchdog_task);
4685}
4686
e8e26350
PW		 4687/**
4688 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
4689 * @work: pointer to work_struct containing our data
4690 **/
4691static void ixgbe_multispeed_fiber_task(struct work_struct *work)
4692{
4693 struct ixgbe_adapter *adapter = container_of(work,
4694 struct ixgbe_adapter,
4695 multispeed_fiber_task);
4696 struct ixgbe_hw *hw = &adapter->hw;
4697 u32 autoneg;
8620a103 4698 bool negotiation;
e8e26350
PW		 4699
4700 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
a1f25324
MC		 4701 autoneg = hw->phy.autoneg_advertised;
4702 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
8620a103
MC		 4703 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
4704 if (hw->mac.ops.setup_link)
4705 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
e8e26350
PW		 4706 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4707 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
4708}
4709
4710/**
4711 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
4712 * @work: pointer to work_struct containing our data
4713 **/
4714static void ixgbe_sfp_config_module_task(struct work_struct *work)
4715{
4716 struct ixgbe_adapter *adapter = container_of(work,
4717 struct ixgbe_adapter,
4718 sfp_config_module_task);
4719 struct ixgbe_hw *hw = &adapter->hw;
4720 u32 err;
4721
4722 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
63d6e1d8
DS		 4723
4724 /* Time for electrical oscillations to settle down */
4725 msleep(100);
e8e26350 4726 err = hw->phy.ops.identify_sfp(hw);
63d6e1d8 4727
e8e26350 4728 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
88d2b81f
DS		 4729 dev_err(&adapter->pdev->dev, "failed to initialize because "
4730 "an unsupported SFP+ module type was detected.\n"
4731 "Reload the driver after installing a supported "
4732 "module.\n");
63d6e1d8 4733 unregister_netdev(adapter->netdev);
e8e26350
PW		 4734 return;
4735 }
4736 hw->mac.ops.setup_sfp(hw);
4737
8d1c3c07 4738 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
e8e26350
PW		 4739 /* This will also work for DA Twinax connections */
4740 schedule_work(&adapter->multispeed_fiber_task);
4741 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
4742}
4743
c4cf55e5
PWJ		 4744/**
4745 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
4746 * @work: pointer to work_struct containing our data
4747 **/
4748static void ixgbe_fdir_reinit_task(struct work_struct *work)
4749{
4750 struct ixgbe_adapter *adapter = container_of(work,
4751 struct ixgbe_adapter,
4752 fdir_reinit_task);
4753 struct ixgbe_hw *hw = &adapter->hw;
4754 int i;
4755
4756 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
4757 for (i = 0; i < adapter->num_tx_queues; i++)
4758 set_bit(__IXGBE_FDIR_INIT_DONE,
4759 &(adapter->tx_ring[i].reinit_state));
4760 } else {
4761 DPRINTK(PROBE, ERR, "failed to finish FDIR re-initialization, "
4762 "ignored adding FDIR ATR filters \n");
4763 }
4764 /* Done FDIR Re-initialization, enable transmits */
4765 netif_tx_start_all_queues(adapter->netdev);
4766}
4767
cf8280ee 4768/**
69888674
AD		 4769 * ixgbe_watchdog_task - worker thread to bring link up
4770 * @work: pointer to work_struct containing our data
cf8280ee
JB		 4771 **/
4772static void ixgbe_watchdog_task(struct work_struct *work)
4773{
4774 struct ixgbe_adapter *adapter = container_of(work,
4775 struct ixgbe_adapter,
4776 watchdog_task);
4777 struct net_device *netdev = adapter->netdev;
4778 struct ixgbe_hw *hw = &adapter->hw;
4779 u32 link_speed = adapter->link_speed;
4780 bool link_up = adapter->link_up;
bc59fcda
NS		 4781 int i;
4782 struct ixgbe_ring *tx_ring;
4783 int some_tx_pending = 0;
cf8280ee
JB		 4784
4785 adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
4786
4787 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4788 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
264857b8
PWJ		 4789 if (link_up) {
4790#ifdef CONFIG_DCB
4791 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4792 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
620fa036 4793 hw->mac.ops.fc_enable(hw, i);
264857b8 4794 } else {
620fa036 4795 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 4796 }
4797#else
620fa036 4798 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 4799#endif
4800 }
4801
cf8280ee
JB		 4802 if (link_up ||
4803 time_after(jiffies, (adapter->link_check_timeout +
4804 IXGBE_TRY_LINK_TIMEOUT))) {
cf8280ee 4805 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
264857b8 4806 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
cf8280ee
JB		 4807 }
4808 adapter->link_up = link_up;
4809 adapter->link_speed = link_speed;
4810 }
9a799d71
AK		 4811
4812 if (link_up) {
4813 if (!netif_carrier_ok(netdev)) {
e8e26350
PW		 4814 bool flow_rx, flow_tx;
4815
4816 if (hw->mac.type == ixgbe_mac_82599EB) {
4817 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4818 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
078788b6
PWJ		 4819 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
4820 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
e8e26350
PW		 4821 } else {
4822 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4823 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
078788b6
PWJ		 4824 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
4825 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
e8e26350
PW		 4826 }
4827
a46e534b
JK		 4828 printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
4829 "Flow Control: %s\n",
4830 netdev->name,
4831 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
4832 "10 Gbps" :
4833 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
4834 "1 Gbps" : "unknown speed")),
e8e26350
PW		 4835 ((flow_rx && flow_tx) ? "RX/TX" :
4836 (flow_rx ? "RX" :
4837 (flow_tx ? "TX" : "None"))));
9a799d71
AK		 4838
4839 netif_carrier_on(netdev);
9a799d71
AK		 4840 } else {
4841 /* Force detection of hung controller */
4842 adapter->detect_tx_hung = true;
4843 }
4844 } else {
cf8280ee
JB		 4845 adapter->link_up = false;
4846 adapter->link_speed = 0;
9a799d71 4847 if (netif_carrier_ok(netdev)) {
a46e534b
JK		 4848 printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
4849 netdev->name);
9a799d71 4850 netif_carrier_off(netdev);
9a799d71
AK		 4851 }
4852 }
4853
bc59fcda
NS		 4854 if (!netif_carrier_ok(netdev)) {
4855 for (i = 0; i < adapter->num_tx_queues; i++) {
4856 tx_ring = &adapter->tx_ring[i];
4857 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
4858 some_tx_pending = 1;
4859 break;
4860 }
4861 }
4862
4863 if (some_tx_pending) {
4864 /* We've lost link, so the controller stops DMA,
4865 * but we've got queued Tx work that's never going
4866 * to get done, so reset controller to flush Tx.
4867 * (Do the reset outside of interrupt context).
4868 */
4869 schedule_work(&adapter->reset_task);
4870 }
4871 }
4872
9a799d71 4873 ixgbe_update_stats(adapter);
cf8280ee 4874 adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
9a799d71
AK		 4875}
4876
9a799d71 4877static int ixgbe_tso(struct ixgbe_adapter *adapter,
b4617240
PW		 4878 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
4879 u32 tx_flags, u8 *hdr_len)
9a799d71
AK		 4880{
4881 struct ixgbe_adv_tx_context_desc *context_desc;
4882 unsigned int i;
4883 int err;
4884 struct ixgbe_tx_buffer *tx_buffer_info;
9f8cdf4f
JB		 4885 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
4886 u32 mss_l4len_idx, l4len;
9a799d71
AK		 4887
4888 if (skb_is_gso(skb)) {
4889 if (skb_header_cloned(skb)) {
4890 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4891 if (err)
4892 return err;
4893 }
4894 l4len = tcp_hdrlen(skb);
4895 *hdr_len += l4len;
4896
8327d000 4897 if (skb->protocol == htons(ETH_P_IP)) {
9a799d71
AK		 4898 struct iphdr *iph = ip_hdr(skb);
4899 iph->tot_len = 0;
4900 iph->check = 0;
4901 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b4617240
PW		 4902 iph->daddr, 0,
4903 IPPROTO_TCP,
4904 0);
9a799d71
AK		 4905 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
4906 ipv6_hdr(skb)->payload_len = 0;
4907 tcp_hdr(skb)->check =
4908 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
b4617240
PW		 4909 &ipv6_hdr(skb)->daddr,
4910 0, IPPROTO_TCP, 0);
9a799d71
AK		 4911 }
4912
4913 i = tx_ring->next_to_use;
4914
4915 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4916 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4917
4918 /* VLAN MACLEN IPLEN */
4919 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4920 vlan_macip_lens |=
4921 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4922 vlan_macip_lens |= ((skb_network_offset(skb)) <<
b4617240 4923 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 4924 *hdr_len += skb_network_offset(skb);
4925 vlan_macip_lens |=
4926 (skb_transport_header(skb) - skb_network_header(skb));
4927 *hdr_len +=
4928 (skb_transport_header(skb) - skb_network_header(skb));
4929 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4930 context_desc->seqnum_seed = 0;
4931
4932 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
9f8cdf4f 4933 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
b4617240 4934 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 4935
8327d000 4936 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 4937 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4938 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
4939 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4940
4941 /* MSS L4LEN IDX */
9f8cdf4f 4942 mss_l4len_idx =
9a799d71
AK		 4943 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
4944 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4eeae6fd
PW		 4945 /* use index 1 for TSO */
4946 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 4947 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4948
4949 tx_buffer_info->time_stamp = jiffies;
4950 tx_buffer_info->next_to_watch = i;
4951
4952 i++;
4953 if (i == tx_ring->count)
4954 i = 0;
4955 tx_ring->next_to_use = i;
4956
4957 return true;
4958 }
4959 return false;
4960}
4961
4962static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
b4617240
PW		 4963 struct ixgbe_ring *tx_ring,
4964 struct sk_buff *skb, u32 tx_flags)
9a799d71
AK		 4965{
4966 struct ixgbe_adv_tx_context_desc *context_desc;
4967 unsigned int i;
4968 struct ixgbe_tx_buffer *tx_buffer_info;
4969 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
4970
4971 if (skb->ip_summed == CHECKSUM_PARTIAL ||
4972 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
4973 i = tx_ring->next_to_use;
4974 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4975 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4976
4977 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4978 vlan_macip_lens |=
4979 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4980 vlan_macip_lens |= (skb_network_offset(skb) <<
b4617240 4981 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 4982 if (skb->ip_summed == CHECKSUM_PARTIAL)
4983 vlan_macip_lens |= (skb_transport_header(skb) -
b4617240 4984 skb_network_header(skb));
9a799d71
AK		 4985
4986 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4987 context_desc->seqnum_seed = 0;
4988
4989 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
b4617240 4990 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71
AK		 4991
4992 if (skb->ip_summed == CHECKSUM_PARTIAL) {
41825d71 4993 switch (skb->protocol) {
09640e63 4994 case cpu_to_be16(ETH_P_IP):
9a799d71 4995 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
41825d71
AK		 4996 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4997 type_tucmd_mlhl |=
b4617240 4998 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 4999 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
5000 type_tucmd_mlhl |=
5001 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 5002 break;
09640e63 5003 case cpu_to_be16(ETH_P_IPV6):
41825d71
AK		 5004 /* XXX what about other V6 headers?? */
5005 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5006 type_tucmd_mlhl |=
b4617240 5007 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 5008 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
5009 type_tucmd_mlhl |=
5010 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 5011 break;
41825d71
AK		 5012 default:
5013 if (unlikely(net_ratelimit())) {
5014 DPRINTK(PROBE, WARNING,
5015 "partial checksum but proto=%x!\n",
5016 skb->protocol);
5017 }
5018 break;
5019 }
9a799d71
AK		 5020 }
5021
5022 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4eeae6fd 5023 /* use index zero for tx checksum offload */
9a799d71
AK		 5024 context_desc->mss_l4len_idx = 0;
5025
5026 tx_buffer_info->time_stamp = jiffies;
5027 tx_buffer_info->next_to_watch = i;
9f8cdf4f 5028
9a799d71
AK		 5029 i++;
5030 if (i == tx_ring->count)
5031 i = 0;
5032 tx_ring->next_to_use = i;
5033
5034 return true;
5035 }
9f8cdf4f 5036
9a799d71
AK		 5037 return false;
5038}
5039
5040static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
b4617240 5041 struct ixgbe_ring *tx_ring,
eacd73f7
YZ		 5042 struct sk_buff *skb, u32 tx_flags,
5043 unsigned int first)
9a799d71 5044{
e5a43549 5045 struct pci_dev *pdev = adapter->pdev;
9a799d71 5046 struct ixgbe_tx_buffer *tx_buffer_info;
eacd73f7
YZ		 5047 unsigned int len;
5048 unsigned int total = skb->len;
9a799d71
AK		 5049 unsigned int offset = 0, size, count = 0, i;
5050 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
5051 unsigned int f;
9a799d71
AK		 5052
5053 i = tx_ring->next_to_use;
5054
eacd73f7
YZ		 5055 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
5056 /* excluding fcoe_crc_eof for FCoE */
5057 total -= sizeof(struct fcoe_crc_eof);
5058
5059 len = min(skb_headlen(skb), total);
9a799d71
AK		 5060 while (len) {
5061 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5062 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5063
5064 tx_buffer_info->length = size;
e5a43549
AD		 5065 tx_buffer_info->mapped_as_page = false;
5066 tx_buffer_info->dma = pci_map_single(pdev,
5067 skb->data + offset,
5068 size, PCI_DMA_TODEVICE);
5069 if (pci_dma_mapping_error(pdev, tx_buffer_info->dma))
5070 goto dma_error;
9a799d71
AK		 5071 tx_buffer_info->time_stamp = jiffies;
5072 tx_buffer_info->next_to_watch = i;
5073
5074 len -= size;
eacd73f7 5075 total -= size;
9a799d71
AK		 5076 offset += size;
5077 count++;
44df32c5
AD		 5078
5079 if (len) {
5080 i++;
5081 if (i == tx_ring->count)
5082 i = 0;
5083 }
9a799d71
AK		 5084 }
5085
5086 for (f = 0; f < nr_frags; f++) {
5087 struct skb_frag_struct *frag;
5088
5089 frag = &skb_shinfo(skb)->frags[f];
eacd73f7 5090 len = min((unsigned int)frag->size, total);
e5a43549 5091 offset = frag->page_offset;
9a799d71
AK		 5092
5093 while (len) {
44df32c5
AD		 5094 i++;
5095 if (i == tx_ring->count)
5096 i = 0;
5097
9a799d71
AK		 5098 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5099 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5100
5101 tx_buffer_info->length = size;
e5a43549
AD		 5102 tx_buffer_info->dma = pci_map_page(adapter->pdev,
5103 frag->page,
5104 offset, size,
5105 PCI_DMA_TODEVICE);
5106 tx_buffer_info->mapped_as_page = true;
5107 if (pci_dma_mapping_error(pdev, tx_buffer_info->dma))
5108 goto dma_error;
9a799d71
AK		 5109 tx_buffer_info->time_stamp = jiffies;
5110 tx_buffer_info->next_to_watch = i;
5111
5112 len -= size;
eacd73f7 5113 total -= size;
9a799d71
AK		 5114 offset += size;
5115 count++;
9a799d71 5116 }
eacd73f7
YZ		 5117 if (total == 0)
5118 break;
9a799d71 5119 }
44df32c5 5120
9a799d71
AK		 5121 tx_ring->tx_buffer_info[i].skb = skb;
5122 tx_ring->tx_buffer_info[first].next_to_watch = i;
5123
e5a43549
AD		 5124 return count;
5125
5126dma_error:
5127 dev_err(&pdev->dev, "TX DMA map failed\n");
5128
5129 /* clear timestamp and dma mappings for failed tx_buffer_info map */
5130 tx_buffer_info->dma = 0;
5131 tx_buffer_info->time_stamp = 0;
5132 tx_buffer_info->next_to_watch = 0;
5133 count--;
5134
5135 /* clear timestamp and dma mappings for remaining portion of packet */
5136 while (count >= 0) {
5137 count--;
5138 i--;
5139 if (i < 0)
5140 i += tx_ring->count;
5141 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5142 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
5143 }
5144
9a799d71
AK		 5145 return count;
5146}
5147
5148static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
b4617240
PW		 5149 struct ixgbe_ring *tx_ring,
5150 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 5151{
5152 union ixgbe_adv_tx_desc *tx_desc = NULL;
5153 struct ixgbe_tx_buffer *tx_buffer_info;
5154 u32 olinfo_status = 0, cmd_type_len = 0;
5155 unsigned int i;
5156 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
5157
5158 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
5159
5160 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
5161
5162 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5163 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
5164
5165 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
5166 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5167
5168 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 5169 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 5170
4eeae6fd
PW		 5171 /* use index 1 context for tso */
5172 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 5173 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
5174 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
b4617240 5175 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 5176
5177 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
5178 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 5179 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 5180
eacd73f7
YZ		 5181 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5182 olinfo_status |= IXGBE_ADVTXD_CC;
5183 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5184 if (tx_flags & IXGBE_TX_FLAGS_FSO)
5185 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5186 }
5187
9a799d71
AK		 5188 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
5189
5190 i = tx_ring->next_to_use;
5191 while (count--) {
5192 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5193 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
5194 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
5195 tx_desc->read.cmd_type_len =
b4617240 5196 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71 5197 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
9a799d71
AK		 5198 i++;
5199 if (i == tx_ring->count)
5200 i = 0;
5201 }
5202
5203 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
5204
5205 /*
5206 * Force memory writes to complete before letting h/w
5207 * know there are new descriptors to fetch. (Only
5208 * applicable for weak-ordered memory model archs,
5209 * such as IA-64).
5210 */
5211 wmb();
5212
5213 tx_ring->next_to_use = i;
5214 writel(i, adapter->hw.hw_addr + tx_ring->tail);
5215}
5216
c4cf55e5
PWJ		 5217static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5218 int queue, u32 tx_flags)
5219{
5220 /* Right now, we support IPv4 only */
5221 struct ixgbe_atr_input atr_input;
5222 struct tcphdr *th;
c4cf55e5
PWJ		 5223 struct iphdr *iph = ip_hdr(skb);
5224 struct ethhdr *eth = (struct ethhdr *)skb->data;
5225 u16 vlan_id, src_port, dst_port, flex_bytes;
5226 u32 src_ipv4_addr, dst_ipv4_addr;
5227 u8 l4type = 0;
5228
5229 /* check if we're UDP or TCP */
5230 if (iph->protocol == IPPROTO_TCP) {
5231 th = tcp_hdr(skb);
5232 src_port = th->source;
5233 dst_port = th->dest;
5234 l4type |= IXGBE_ATR_L4TYPE_TCP;
5235 /* l4type IPv4 type is 0, no need to assign */
c4cf55e5
PWJ		 5236 } else {
5237 /* Unsupported L4 header, just bail here */
5238 return;
5239 }
5240
5241 memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
5242
5243 vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
5244 IXGBE_TX_FLAGS_VLAN_SHIFT;
5245 src_ipv4_addr = iph->saddr;
5246 dst_ipv4_addr = iph->daddr;
5247 flex_bytes = eth->h_proto;
5248
5249 ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
5250 ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
5251 ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
5252 ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
5253 ixgbe_atr_set_l4type_82599(&atr_input, l4type);
5254 /* src and dst are inverted, think how the receiver sees them */
5255 ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
5256 ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
5257
5258 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
5259 ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
5260}
5261
e092be60 5262static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 5263 struct ixgbe_ring *tx_ring, int size)
e092be60 5264{
30eba97a 5265 netif_stop_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 5266 /* Herbert's original patch had:
5267 * smp_mb__after_netif_stop_queue();
5268 * but since that doesn't exist yet, just open code it. */
5269 smp_mb();
5270
5271 /* We need to check again in a case another CPU has just
5272 * made room available. */
5273 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
5274 return -EBUSY;
5275
5276 /* A reprieve! - use start_queue because it doesn't call schedule */
af72166f 5277 netif_start_subqueue(netdev, tx_ring->queue_index);
7ca3bc58 5278 ++tx_ring->restart_queue;
e092be60
AV		 5279 return 0;
5280}
5281
5282static int ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 5283 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 5284{
5285 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
5286 return 0;
5287 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
5288}
5289
09a3b1f8
SH		 5290static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
5291{
5292 struct ixgbe_adapter *adapter = netdev_priv(dev);
5f715823 5293 int txq = smp_processor_id();
09a3b1f8 5294
c4cf55e5 5295 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
5f715823 5296 return txq;
c4cf55e5 5297
5f715823
YZ		 5298#ifdef IXGBE_FCOE
5299 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
5300 (skb->protocol == htons(ETH_P_FCOE))) {
5301 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
5302 txq += adapter->ring_feature[RING_F_FCOE].mask;
5303 return txq;
5304 }
5305#endif
09a3b1f8 5306 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
36e89d73 5307 return (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK) >> 13;
09a3b1f8
SH		 5308
5309 return skb_tx_hash(dev, skb);
5310}
5311
3b29a56d
SH		 5312static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
5313 struct net_device *netdev)
9a799d71
AK		 5314{
5315 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5316 struct ixgbe_ring *tx_ring;
9a799d71
AK		 5317 unsigned int first;
5318 unsigned int tx_flags = 0;
30eba97a 5319 u8 hdr_len = 0;
5f715823 5320 int tso;
9a799d71
AK		 5321 int count = 0;
5322 unsigned int f;
9f8cdf4f 5323
9f8cdf4f
JB		 5324 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
5325 tx_flags |= vlan_tx_tag_get(skb);
2f90b865
AD		 5326 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5327 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5f715823 5328 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
2f90b865
AD		 5329 }
5330 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5331 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5332 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
60127865 5333 if (skb->priority != TC_PRIO_CONTROL) {
5f715823 5334 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
60127865
LL		 5335 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5336 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5337 } else {
5338 skb->queue_mapping =
5339 adapter->ring_feature[RING_F_DCB].indices-1;
5340 }
9a799d71 5341 }
eacd73f7 5342
5f715823 5343 tx_ring = &adapter->tx_ring[skb->queue_mapping];
60127865 5344
eacd73f7 5345 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
09ad1cc0 5346 (skb->protocol == htons(ETH_P_FCOE))) {
eacd73f7 5347 tx_flags |= IXGBE_TX_FLAGS_FCOE;
09ad1cc0 5348#ifdef IXGBE_FCOE
61a0f421
YZ		 5349#ifdef CONFIG_IXGBE_DCB
5350 tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
5351 << IXGBE_TX_FLAGS_VLAN_SHIFT);
5352 tx_flags |= ((adapter->fcoe.up << 13)
5353 << IXGBE_TX_FLAGS_VLAN_SHIFT);
5354#endif
09ad1cc0
YZ		 5355#endif
5356 }
eacd73f7 5357 /* four things can cause us to need a context descriptor */
9f8cdf4f
JB		 5358 if (skb_is_gso(skb) ||
5359 (skb->ip_summed == CHECKSUM_PARTIAL) ||
eacd73f7
YZ		 5360 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
5361 (tx_flags & IXGBE_TX_FLAGS_FCOE))
9a799d71
AK		 5362 count++;
5363
9f8cdf4f
JB		 5364 count += TXD_USE_COUNT(skb_headlen(skb));
5365 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
9a799d71
AK		 5366 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5367
e092be60 5368 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
9a799d71 5369 adapter->tx_busy++;
9a799d71
AK		 5370 return NETDEV_TX_BUSY;
5371 }
9a799d71 5372
9a799d71 5373 first = tx_ring->next_to_use;
eacd73f7
YZ		 5374 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5375#ifdef IXGBE_FCOE
5376 /* setup tx offload for FCoE */
5377 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5378 if (tso < 0) {
5379 dev_kfree_skb_any(skb);
5380 return NETDEV_TX_OK;
5381 }
5382 if (tso)
5383 tx_flags |= IXGBE_TX_FLAGS_FSO;
5384#endif /* IXGBE_FCOE */
5385 } else {
5386 if (skb->protocol == htons(ETH_P_IP))
5387 tx_flags |= IXGBE_TX_FLAGS_IPV4;
5388 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5389 if (tso < 0) {
5390 dev_kfree_skb_any(skb);
5391 return NETDEV_TX_OK;
5392 }
9a799d71 5393
eacd73f7
YZ		 5394 if (tso)
5395 tx_flags |= IXGBE_TX_FLAGS_TSO;
5396 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
5397 (skb->ip_summed == CHECKSUM_PARTIAL))
5398 tx_flags |= IXGBE_TX_FLAGS_CSUM;
5399 }
9a799d71 5400
eacd73f7 5401 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
44df32c5 5402 if (count) {
c4cf55e5
PWJ		 5403 /* add the ATR filter if ATR is on */
5404 if (tx_ring->atr_sample_rate) {
5405 ++tx_ring->atr_count;
5406 if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
5407 test_bit(__IXGBE_FDIR_INIT_DONE,
5408 &tx_ring->reinit_state)) {
5409 ixgbe_atr(adapter, skb, tx_ring->queue_index,
5410 tx_flags);
5411 tx_ring->atr_count = 0;
5412 }
5413 }
44df32c5
AD		 5414 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
5415 hdr_len);
44df32c5 5416 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
9a799d71 5417
44df32c5
AD		 5418 } else {
5419 dev_kfree_skb_any(skb);
5420 tx_ring->tx_buffer_info[first].time_stamp = 0;
5421 tx_ring->next_to_use = first;
5422 }
9a799d71
AK		 5423
5424 return NETDEV_TX_OK;
5425}
5426
5427/**
5428 * ixgbe_get_stats - Get System Network Statistics
5429 * @netdev: network interface device structure
5430 *
5431 * Returns the address of the device statistics structure.
5432 * The statistics are actually updated from the timer callback.
5433 **/
5434static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
5435{
9a799d71 5436 /* only return the current stats */
2d86f139 5437 return &netdev->stats;
9a799d71
AK		 5438}
5439
5440/**
5441 * ixgbe_set_mac - Change the Ethernet Address of the NIC
5442 * @netdev: network interface device structure
5443 * @p: pointer to an address structure
5444 *
5445 * Returns 0 on success, negative on failure
5446 **/
5447static int ixgbe_set_mac(struct net_device *netdev, void *p)
5448{
5449 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 5450 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 5451 struct sockaddr *addr = p;
5452
5453 if (!is_valid_ether_addr(addr->sa_data))
5454 return -EADDRNOTAVAIL;
5455
5456 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 5457 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 5458
b4617240 5459 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71
AK		 5460
5461 return 0;
5462}
5463
6b73e10d
BH		 5464static int
5465ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
5466{
5467 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5468 struct ixgbe_hw *hw = &adapter->hw;
5469 u16 value;
5470 int rc;
5471
5472 if (prtad != hw->phy.mdio.prtad)
5473 return -EINVAL;
5474 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
5475 if (!rc)
5476 rc = value;
5477 return rc;
5478}
5479
5480static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
5481 u16 addr, u16 value)
5482{
5483 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5484 struct ixgbe_hw *hw = &adapter->hw;
5485
5486 if (prtad != hw->phy.mdio.prtad)
5487 return -EINVAL;
5488 return hw->phy.ops.write_reg(hw, addr, devad, value);
5489}
5490
5491static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
5492{
5493 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5494
5495 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
5496}
5497
0365e6e4
PW		 5498/**
5499 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 5500 * netdev->dev_addrs
0365e6e4
PW		 5501 * @netdev: network interface device structure
5502 *
5503 * Returns non-zero on failure
5504 **/
5505static int ixgbe_add_sanmac_netdev(struct net_device *dev)
5506{
5507 int err = 0;
5508 struct ixgbe_adapter *adapter = netdev_priv(dev);
5509 struct ixgbe_mac_info *mac = &adapter->hw.mac;
5510
5511 if (is_valid_ether_addr(mac->san_addr)) {
5512 rtnl_lock();
5513 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5514 rtnl_unlock();
5515 }
5516 return err;
5517}
5518
5519/**
5520 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 5521 * netdev->dev_addrs
0365e6e4
PW		 5522 * @netdev: network interface device structure
5523 *
5524 * Returns non-zero on failure
5525 **/
5526static int ixgbe_del_sanmac_netdev(struct net_device *dev)
5527{
5528 int err = 0;
5529 struct ixgbe_adapter *adapter = netdev_priv(dev);
5530 struct ixgbe_mac_info *mac = &adapter->hw.mac;
5531
5532 if (is_valid_ether_addr(mac->san_addr)) {
5533 rtnl_lock();
5534 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5535 rtnl_unlock();
5536 }
5537 return err;
5538}
5539
9a799d71
AK		 5540#ifdef CONFIG_NET_POLL_CONTROLLER
5541/*
5542 * Polling 'interrupt' - used by things like netconsole to send skbs
5543 * without having to re-enable interrupts. It's not called while
5544 * the interrupt routine is executing.
5545 */
5546static void ixgbe_netpoll(struct net_device *netdev)
5547{
5548 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 5549 int i;
9a799d71 5550
9a799d71 5551 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167
PWJ		 5552 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5553 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
5554 for (i = 0; i < num_q_vectors; i++) {
5555 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
5556 ixgbe_msix_clean_many(0, q_vector);
5557 }
5558 } else {
5559 ixgbe_intr(adapter->pdev->irq, netdev);
5560 }
9a799d71 5561 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71
AK		 5562}
5563#endif
5564
0edc3527
SH		 5565static const struct net_device_ops ixgbe_netdev_ops = {
5566 .ndo_open = ixgbe_open,
5567 .ndo_stop = ixgbe_close,
00829823 5568 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 5569 .ndo_select_queue = ixgbe_select_queue,
0edc3527 5570 .ndo_get_stats = ixgbe_get_stats,
e90d400c 5571 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 5572 .ndo_set_multicast_list = ixgbe_set_rx_mode,
5573 .ndo_validate_addr = eth_validate_addr,
5574 .ndo_set_mac_address = ixgbe_set_mac,
5575 .ndo_change_mtu = ixgbe_change_mtu,
5576 .ndo_tx_timeout = ixgbe_tx_timeout,
5577 .ndo_vlan_rx_register = ixgbe_vlan_rx_register,
5578 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
5579 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 5580 .ndo_do_ioctl = ixgbe_ioctl,
0edc3527
SH		 5581#ifdef CONFIG_NET_POLL_CONTROLLER
5582 .ndo_poll_controller = ixgbe_netpoll,
5583#endif
332d4a7d
YZ		 5584#ifdef IXGBE_FCOE
5585 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
5586 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 5587 .ndo_fcoe_enable = ixgbe_fcoe_enable,
5588 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 5589 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
332d4a7d 5590#endif /* IXGBE_FCOE */
0edc3527
SH		 5591};
5592
9a799d71
AK		 5593/**
5594 * ixgbe_probe - Device Initialization Routine
5595 * @pdev: PCI device information struct
5596 * @ent: entry in ixgbe_pci_tbl
5597 *
5598 * Returns 0 on success, negative on failure
5599 *
5600 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
5601 * The OS initialization, configuring of the adapter private structure,
5602 * and a hardware reset occur.
5603 **/
5604static int __devinit ixgbe_probe(struct pci_dev *pdev,
b4617240 5605 const struct pci_device_id *ent)
9a799d71
AK		 5606{
5607 struct net_device *netdev;
5608 struct ixgbe_adapter *adapter = NULL;
5609 struct ixgbe_hw *hw;
5610 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 5611 static int cards_found;
5612 int i, err, pci_using_dac;
eacd73f7
YZ		 5613#ifdef IXGBE_FCOE
5614 u16 device_caps;
5615#endif
c44ade9e 5616 u32 part_num, eec;
9a799d71 5617
9ce77666 5618 err = pci_enable_device_mem(pdev);
9a799d71
AK		 5619 if (err)
5620 return err;
5621
6a35528a
YH		 5622 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
5623 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
9a799d71
AK		 5624 pci_using_dac = 1;
5625 } else {
284901a9 5626 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
9a799d71 5627 if (err) {
284901a9 5628 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
9a799d71 5629 if (err) {
b4617240
PW		 5630 dev_err(&pdev->dev, "No usable DMA "
5631 "configuration, aborting\n");
9a799d71
AK		 5632 goto err_dma;
5633 }
5634 }
5635 pci_using_dac = 0;
5636 }
5637
9ce77666 5638 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
5639 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 5640 if (err) {
9ce77666 5641 dev_err(&pdev->dev,
5642 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 5643 goto err_pci_reg;
5644 }
5645
19d5afd4 5646 pci_enable_pcie_error_reporting(pdev);
6fabd715 5647
9a799d71 5648 pci_set_master(pdev);
fb3b27bc 5649 pci_save_state(pdev);
9a799d71 5650
30eba97a 5651 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
9a799d71
AK		 5652 if (!netdev) {
5653 err = -ENOMEM;
5654 goto err_alloc_etherdev;
5655 }
5656
9a799d71
AK		 5657 SET_NETDEV_DEV(netdev, &pdev->dev);
5658
5659 pci_set_drvdata(pdev, netdev);
5660 adapter = netdev_priv(netdev);
5661
5662 adapter->netdev = netdev;
5663 adapter->pdev = pdev;
5664 hw = &adapter->hw;
5665 hw->back = adapter;
5666 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
5667
05857980
JK		 5668 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
5669 pci_resource_len(pdev, 0));
9a799d71
AK		 5670 if (!hw->hw_addr) {
5671 err = -EIO;
5672 goto err_ioremap;
5673 }
5674
5675 for (i = 1; i <= 5; i++) {
5676 if (pci_resource_len(pdev, i) == 0)
5677 continue;
5678 }
5679
0edc3527 5680 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 5681 ixgbe_set_ethtool_ops(netdev);
9a799d71 5682 netdev->watchdog_timeo = 5 * HZ;
9a799d71
AK		 5683 strcpy(netdev->name, pci_name(pdev));
5684
9a799d71
AK		 5685 adapter->bd_number = cards_found;
5686
9a799d71
AK		 5687 /* Setup hw api */
5688 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 5689 hw->mac.type = ii->mac;
9a799d71 5690
c44ade9e
JB		 5691 /* EEPROM */
5692 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
5693 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
5694 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
5695 if (!(eec & (1 << 8)))
5696 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
5697
5698 /* PHY */
5699 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 5700 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 5701 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
5702 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
5703 hw->phy.mdio.mmds = 0;
5704 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
5705 hw->phy.mdio.dev = netdev;
5706 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
5707 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0
DS		 5708
5709 /* set up this timer and work struct before calling get_invariants
5710 * which might start the timer
5711 */
5712 init_timer(&adapter->sfp_timer);
5713 adapter->sfp_timer.function = &ixgbe_sfp_timer;
5714 adapter->sfp_timer.data = (unsigned long) adapter;
5715
5716 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
c44ade9e 5717
e8e26350
PW		 5718 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
5719 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
5720
5721 /* a new SFP+ module arrival, called from GPI SDP2 context */
5722 INIT_WORK(&adapter->sfp_config_module_task,
5723 ixgbe_sfp_config_module_task);
5724
8ca783ab 5725 ii->get_invariants(hw);
9a799d71
AK		 5726
5727 /* setup the private structure */
5728 err = ixgbe_sw_init(adapter);
5729 if (err)
5730 goto err_sw_init;
5731
bf069c97
DS		 5732 /*
5733 * If there is a fan on this device and it has failed log the
5734 * failure.
5735 */
5736 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
5737 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5738 if (esdp & IXGBE_ESDP_SDP1)
5739 DPRINTK(PROBE, CRIT,
5740 "Fan has stopped, replace the adapter\n");
5741 }
5742
c44ade9e
JB		 5743 /* reset_hw fills in the perm_addr as well */
5744 err = hw->mac.ops.reset_hw(hw);
8ca783ab
DS		 5745 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
5746 hw->mac.type == ixgbe_mac_82598EB) {
5747 /*
5748 * Start a kernel thread to watch for a module to arrive.
5749 * Only do this for 82598, since 82599 will generate
5750 * interrupts on module arrival.
5751 */
5752 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5753 mod_timer(&adapter->sfp_timer,
5754 round_jiffies(jiffies + (2 * HZ)));
5755 err = 0;
5756 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
88d2b81f
DS		 5757 dev_err(&adapter->pdev->dev, "failed to initialize because "
5758 "an unsupported SFP+ module type was detected.\n"
5759 "Reload the driver after installing a supported "
5760 "module.\n");
04f165ef
PW		 5761 goto err_sw_init;
5762 } else if (err) {
c44ade9e
JB		 5763 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
5764 goto err_sw_init;
5765 }
5766
9a799d71 5767 netdev->features = NETIF_F_SG |
b4617240
PW		 5768 NETIF_F_IP_CSUM |
5769 NETIF_F_HW_VLAN_TX |
5770 NETIF_F_HW_VLAN_RX |
5771 NETIF_F_HW_VLAN_FILTER;
9a799d71 5772
e9990a9c 5773 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 5774 netdev->features |= NETIF_F_TSO;
9a799d71 5775 netdev->features |= NETIF_F_TSO6;
78b6f4ce 5776 netdev->features |= NETIF_F_GRO;
ad31c402 5777
45a5ead0
JB		 5778 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
5779 netdev->features |= NETIF_F_SCTP_CSUM;
5780
ad31c402
JK		 5781 netdev->vlan_features |= NETIF_F_TSO;
5782 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 5783 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 5784 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 5785 netdev->vlan_features |= NETIF_F_SG;
5786
2f90b865
AD		 5787 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5788 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
5789
7a6b6f51 5790#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5791 netdev->dcbnl_ops = &dcbnl_ops;
5792#endif
5793
eacd73f7 5794#ifdef IXGBE_FCOE
0d551589 5795 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 5796 if (hw->mac.ops.get_device_caps) {
5797 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 5798 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
5799 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7
YZ		 5800 }
5801 }
5802#endif /* IXGBE_FCOE */
9a799d71
AK		 5803 if (pci_using_dac)
5804 netdev->features |= NETIF_F_HIGHDMA;
5805
0c19d6af 5806 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 5807 netdev->features |= NETIF_F_LRO;
5808
9a799d71 5809 /* make sure the EEPROM is good */
c44ade9e 5810 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
9a799d71
AK		 5811 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
5812 err = -EIO;
5813 goto err_eeprom;
5814 }
5815
5816 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
5817 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
5818
c44ade9e
JB		 5819 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
5820 dev_err(&pdev->dev, "invalid MAC address\n");
9a799d71
AK		 5821 err = -EIO;
5822 goto err_eeprom;
5823 }
5824
5825 init_timer(&adapter->watchdog_timer);
5826 adapter->watchdog_timer.function = &ixgbe_watchdog;
5827 adapter->watchdog_timer.data = (unsigned long)adapter;
5828
5829 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
cf8280ee 5830 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
9a799d71 5831
021230d4
AV		 5832 err = ixgbe_init_interrupt_scheme(adapter);
5833 if (err)
5834 goto err_sw_init;
9a799d71 5835
e8e26350
PW		 5836 switch (pdev->device) {
5837 case IXGBE_DEV_ID_82599_KX4:
495dce12
WJP		 5838 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
5839 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
bdf0a550
PWJ		 5840 /* Enable ACPI wakeup in GRC */
5841 IXGBE_WRITE_REG(hw, IXGBE_GRC,
5842 (IXGBE_READ_REG(hw, IXGBE_GRC) & ~IXGBE_GRC_APME));
e8e26350
PW		 5843 break;
5844 default:
5845 adapter->wol = 0;
5846 break;
5847 }
e8e26350
PW		 5848 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
5849
04f165ef
PW		 5850 /* pick up the PCI bus settings for reporting later */
5851 hw->mac.ops.get_bus_info(hw);
5852
9a799d71 5853 /* print bus type/speed/width info */
7c510e4b 5854 dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
e8e26350
PW		 5855 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
5856 (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
5857 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
5858 (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
5859 (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
b4617240 5860 "Unknown"),
7c510e4b 5861 netdev->dev_addr);
c44ade9e 5862 ixgbe_read_pba_num_generic(hw, &part_num);
e8e26350
PW		 5863 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
5864 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
5865 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
5866 (part_num >> 8), (part_num & 0xff));
5867 else
5868 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
5869 hw->mac.type, hw->phy.type,
5870 (part_num >> 8), (part_num & 0xff));
9a799d71 5871
e8e26350 5872 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
0c254d86 5873 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
b4617240
PW		 5874 "this card is not sufficient for optimal "
5875 "performance.\n");
0c254d86 5876 dev_warn(&pdev->dev, "For optimal performance a x8 "
b4617240 5877 "PCI-Express slot is required.\n");
0c254d86
AK		 5878 }
5879
34b0368c
PWJ		 5880 /* save off EEPROM version number */
5881 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
5882
9a799d71 5883 /* reset the hardware with the new settings */
794caeb2 5884 err = hw->mac.ops.start_hw(hw);
c44ade9e 5885
794caeb2
PWJ		 5886 if (err == IXGBE_ERR_EEPROM_VERSION) {
5887 /* We are running on a pre-production device, log a warning */
5888 dev_warn(&pdev->dev, "This device is a pre-production "
5889 "adapter/LOM. Please be aware there may be issues "
5890 "associated with your hardware. If you are "
5891 "experiencing problems please contact your Intel or "
5892 "hardware representative who provided you with this "
5893 "hardware.\n");
5894 }
9a799d71
AK		 5895 strcpy(netdev->name, "eth%d");
5896 err = register_netdev(netdev);
5897 if (err)
5898 goto err_register;
5899
54386467
JB		 5900 /* carrier off reporting is important to ethtool even BEFORE open */
5901 netif_carrier_off(netdev);
5902
c4cf55e5
PWJ		 5903 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5904 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5905 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
5906
5dd2d332 5907#ifdef CONFIG_IXGBE_DCA
652f093f 5908 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 5909 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 5910 ixgbe_setup_dca(adapter);
5911 }
5912#endif
0365e6e4
PW		 5913 /* add san mac addr to netdev */
5914 ixgbe_add_sanmac_netdev(netdev);
9a799d71
AK		 5915
5916 dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
5917 cards_found++;
5918 return 0;
5919
5920err_register:
5eba3699 5921 ixgbe_release_hw_control(adapter);
7a921c93 5922 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 5923err_sw_init:
5924err_eeprom:
c4900be0
DS		 5925 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5926 del_timer_sync(&adapter->sfp_timer);
5927 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 5928 cancel_work_sync(&adapter->multispeed_fiber_task);
5929 cancel_work_sync(&adapter->sfp_config_module_task);
9a799d71
AK		 5930 iounmap(hw->hw_addr);
5931err_ioremap:
5932 free_netdev(netdev);
5933err_alloc_etherdev:
9ce77666 5934 pci_release_selected_regions(pdev, pci_select_bars(pdev,
5935 IORESOURCE_MEM));
9a799d71
AK		 5936err_pci_reg:
5937err_dma:
5938 pci_disable_device(pdev);
5939 return err;
5940}
5941
5942/**
5943 * ixgbe_remove - Device Removal Routine
5944 * @pdev: PCI device information struct
5945 *
5946 * ixgbe_remove is called by the PCI subsystem to alert the driver
5947 * that it should release a PCI device. The could be caused by a
5948 * Hot-Plug event, or because the driver is going to be removed from
5949 * memory.
5950 **/
5951static void __devexit ixgbe_remove(struct pci_dev *pdev)
5952{
5953 struct net_device *netdev = pci_get_drvdata(pdev);
5954 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5955
5956 set_bit(__IXGBE_DOWN, &adapter->state);
c4900be0
DS		 5957 /* clear the module not found bit to make sure the worker won't
5958 * reschedule
5959 */
5960 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
9a799d71
AK		 5961 del_timer_sync(&adapter->watchdog_timer);
5962
c4900be0
DS		 5963 del_timer_sync(&adapter->sfp_timer);
5964 cancel_work_sync(&adapter->watchdog_task);
5965 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 5966 cancel_work_sync(&adapter->multispeed_fiber_task);
5967 cancel_work_sync(&adapter->sfp_config_module_task);
c4cf55e5
PWJ		 5968 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5969 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5970 cancel_work_sync(&adapter->fdir_reinit_task);
9a799d71
AK		 5971 flush_scheduled_work();
5972
5dd2d332 5973#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 5974 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
5975 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
5976 dca_remove_requester(&pdev->dev);
5977 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
5978 }
5979
5980#endif
332d4a7d
YZ		 5981#ifdef IXGBE_FCOE
5982 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
5983 ixgbe_cleanup_fcoe(adapter);
5984
5985#endif /* IXGBE_FCOE */
0365e6e4
PW		 5986
5987 /* remove the added san mac */
5988 ixgbe_del_sanmac_netdev(netdev);
5989
c4900be0
DS		 5990 if (netdev->reg_state == NETREG_REGISTERED)
5991 unregister_netdev(netdev);
9a799d71 5992
7a921c93 5993 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 5994
021230d4 5995 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5996
5997 iounmap(adapter->hw.hw_addr);
9ce77666 5998 pci_release_selected_regions(pdev, pci_select_bars(pdev,
5999 IORESOURCE_MEM));
9a799d71 6000
021230d4 6001 DPRINTK(PROBE, INFO, "complete\n");
021230d4 6002
9a799d71
AK		 6003 free_netdev(netdev);
6004
19d5afd4 6005 pci_disable_pcie_error_reporting(pdev);
6fabd715 6006
9a799d71
AK		 6007 pci_disable_device(pdev);
6008}
6009
6010/**
6011 * ixgbe_io_error_detected - called when PCI error is detected
6012 * @pdev: Pointer to PCI device
6013 * @state: The current pci connection state
6014 *
6015 * This function is called after a PCI bus error affecting
6016 * this device has been detected.
6017 */
6018static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
b4617240 6019 pci_channel_state_t state)
9a799d71
AK		 6020{
6021 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 6022 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 6023
6024 netif_device_detach(netdev);
6025
3044b8d1
BL		 6026 if (state == pci_channel_io_perm_failure)
6027 return PCI_ERS_RESULT_DISCONNECT;
6028
9a799d71
AK		 6029 if (netif_running(netdev))
6030 ixgbe_down(adapter);
6031 pci_disable_device(pdev);
6032
b4617240 6033 /* Request a slot reset. */
9a799d71
AK		 6034 return PCI_ERS_RESULT_NEED_RESET;
6035}
6036
6037/**
6038 * ixgbe_io_slot_reset - called after the pci bus has been reset.
6039 * @pdev: Pointer to PCI device
6040 *
6041 * Restart the card from scratch, as if from a cold-boot.
6042 */
6043static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
6044{
6045 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 6046 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715
PWJ		 6047 pci_ers_result_t result;
6048 int err;
9a799d71 6049
9ce77666 6050 if (pci_enable_device_mem(pdev)) {
9a799d71 6051 DPRINTK(PROBE, ERR,
b4617240 6052 "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 6053 result = PCI_ERS_RESULT_DISCONNECT;
6054 } else {
6055 pci_set_master(pdev);
6056 pci_restore_state(pdev);
c0e1f68b 6057 pci_save_state(pdev);
9a799d71 6058
dd4d8ca6 6059 pci_wake_from_d3(pdev, false);
9a799d71 6060
6fabd715 6061 ixgbe_reset(adapter);
88512539 6062 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 6063 result = PCI_ERS_RESULT_RECOVERED;
6064 }
6065
6066 err = pci_cleanup_aer_uncorrect_error_status(pdev);
6067 if (err) {
6068 dev_err(&pdev->dev,
6069 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
6070 /* non-fatal, continue */
6071 }
9a799d71 6072
6fabd715 6073 return result;
9a799d71
AK		 6074}
6075
6076/**
6077 * ixgbe_io_resume - called when traffic can start flowing again.
6078 * @pdev: Pointer to PCI device
6079 *
6080 * This callback is called when the error recovery driver tells us that
6081 * its OK to resume normal operation.
6082 */
6083static void ixgbe_io_resume(struct pci_dev *pdev)
6084{
6085 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 6086 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 6087
6088 if (netif_running(netdev)) {
6089 if (ixgbe_up(adapter)) {
6090 DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
6091 return;
6092 }
6093 }
6094
6095 netif_device_attach(netdev);
9a799d71
AK		 6096}
6097
6098static struct pci_error_handlers ixgbe_err_handler = {
6099 .error_detected = ixgbe_io_error_detected,
6100 .slot_reset = ixgbe_io_slot_reset,
6101 .resume = ixgbe_io_resume,
6102};
6103
6104static struct pci_driver ixgbe_driver = {
6105 .name = ixgbe_driver_name,
6106 .id_table = ixgbe_pci_tbl,
6107 .probe = ixgbe_probe,
6108 .remove = __devexit_p(ixgbe_remove),
6109#ifdef CONFIG_PM
6110 .suspend = ixgbe_suspend,
6111 .resume = ixgbe_resume,
6112#endif
6113 .shutdown = ixgbe_shutdown,
6114 .err_handler = &ixgbe_err_handler
6115};
6116
6117/**
6118 * ixgbe_init_module - Driver Registration Routine
6119 *
6120 * ixgbe_init_module is the first routine called when the driver is
6121 * loaded. All it does is register with the PCI subsystem.
6122 **/
6123static int __init ixgbe_init_module(void)
6124{
6125 int ret;
6126 printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
6127 ixgbe_driver_string, ixgbe_driver_version);
6128
6129 printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
6130
5dd2d332 6131#ifdef CONFIG_IXGBE_DCA
bd0362dd 6132 dca_register_notify(&dca_notifier);
bd0362dd 6133#endif
5dd2d332 6134
9a799d71
AK		 6135 ret = pci_register_driver(&ixgbe_driver);
6136 return ret;
6137}
b4617240 6138
9a799d71
AK		 6139module_init(ixgbe_init_module);
6140
6141/**
6142 * ixgbe_exit_module - Driver Exit Cleanup Routine
6143 *
6144 * ixgbe_exit_module is called just before the driver is removed
6145 * from memory.
6146 **/
6147static void __exit ixgbe_exit_module(void)
6148{
5dd2d332 6149#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 6150 dca_unregister_notify(&dca_notifier);
6151#endif
9a799d71
AK		 6152 pci_unregister_driver(&ixgbe_driver);
6153}
bd0362dd 6154
5dd2d332 6155#ifdef CONFIG_IXGBE_DCA
bd0362dd 6156static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
b4617240 6157 void *p)
bd0362dd
JC		 6158{
6159 int ret_val;
6160
6161 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
b4617240 6162 __ixgbe_notify_dca);
bd0362dd
JC		 6163
6164 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
6165}
b453368d 6166
5dd2d332 6167#endif /* CONFIG_IXGBE_DCA */
b453368d
AD		 6168#ifdef DEBUG
6169/**
6170 * ixgbe_get_hw_dev_name - return device name string
6171 * used by hardware layer to print debugging information
6172 **/
6173char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
6174{
6175 struct ixgbe_adapter *adapter = hw->back;
6176 return adapter->netdev->name;
6177}
bd0362dd 6178
b453368d 6179#endif
9a799d71
AK		 6180module_exit(ixgbe_exit_module);
6181
6182/* ixgbe_main.c */
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