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ixgbe: Whitespace, copyright update and version number change patch
[mirror_ubuntu-zesty-kernel.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
b4617240 4 Copyright(c) 1999 - 2008 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
37#include <linux/ipv6.h>
38#include <net/checksum.h>
39#include <net/ip6_checksum.h>
40#include <linux/ethtool.h>
41#include <linux/if_vlan.h>
42
43#include "ixgbe.h"
44#include "ixgbe_common.h"
45
46char ixgbe_driver_name[] = "ixgbe";
9c8eb720 47static const char ixgbe_driver_string[] =
b4617240 48 "Intel(R) 10 Gigabit PCI Express Network Driver";
9a799d71 49
51ac6445 50#define DRV_VERSION "1.3.30-k2"
9c8eb720 51const char ixgbe_driver_version[] = DRV_VERSION;
b4617240 52static char ixgbe_copyright[] = "Copyright (c) 1999-2007 Intel Corporation.";
9a799d71
AK		 53
54static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 55 [board_82598] = &ixgbe_82598_info,
9a799d71
AK		 56};
57
58/* ixgbe_pci_tbl - PCI Device ID Table
59 *
60 * Wildcard entries (PCI_ANY_ID) should come last
61 * Last entry must be all 0s
62 *
63 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
64 * Class, Class Mask, private data (not used) }
65 */
66static struct pci_device_id ixgbe_pci_tbl[] = {
67 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 68 board_82598 },
9a799d71 69 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 70 board_82598 },
9a799d71 71 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 72 board_82598 },
8d792cd9
JB		 73 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
74 board_82598 },
b95f5fcb
JB		 75 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
76 board_82598 },
9a799d71
AK		 77
78 /* required last entry */
79 {0, }
80};
81MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
82
a1f96ee7 83#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
bd0362dd 84static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
b4617240 85 void *p);
bd0362dd
JC		 86static struct notifier_block dca_notifier = {
87 .notifier_call = ixgbe_notify_dca,
88 .next = NULL,
89 .priority = 0
90};
91#endif
92
9a799d71
AK		 93MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
94MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
95MODULE_LICENSE("GPL");
96MODULE_VERSION(DRV_VERSION);
97
98#define DEFAULT_DEBUG_LEVEL_SHIFT 3
99
5eba3699
AV		 100static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
101{
102 u32 ctrl_ext;
103
104 /* Let firmware take over control of h/w */
105 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
106 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 107 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 108}
109
110static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
111{
112 u32 ctrl_ext;
113
114 /* Let firmware know the driver has taken over */
115 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
116 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 117 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 118}
9a799d71
AK		 119
120#ifdef DEBUG
121/**
122 * ixgbe_get_hw_dev_name - return device name string
123 * used by hardware layer to print debugging information
124 **/
125char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
126{
127 struct ixgbe_adapter *adapter = hw->back;
128 struct net_device *netdev = adapter->netdev;
129 return netdev->name;
130}
131#endif
132
133static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, u16 int_alloc_entry,
b4617240 134 u8 msix_vector)
9a799d71
AK		 135{
136 u32 ivar, index;
137
138 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
139 index = (int_alloc_entry >> 2) & 0x1F;
140 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR(index));
141 ivar &= ~(0xFF << (8 * (int_alloc_entry & 0x3)));
142 ivar |= (msix_vector << (8 * (int_alloc_entry & 0x3)));
143 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR(index), ivar);
144}
145
146static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
b4617240
PW		 147 struct ixgbe_tx_buffer
148 *tx_buffer_info)
9a799d71
AK		 149{
150 if (tx_buffer_info->dma) {
e01c31a5 151 pci_unmap_page(adapter->pdev, tx_buffer_info->dma,
b4617240 152 tx_buffer_info->length, PCI_DMA_TODEVICE);
9a799d71
AK		 153 tx_buffer_info->dma = 0;
154 }
155 if (tx_buffer_info->skb) {
156 dev_kfree_skb_any(tx_buffer_info->skb);
157 tx_buffer_info->skb = NULL;
158 }
159 /* tx_buffer_info must be completely set up in the transmit path */
160}
161
162static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
b4617240
PW		 163 struct ixgbe_ring *tx_ring,
164 unsigned int eop)
9a799d71 165{
e01c31a5
JB		 166 struct ixgbe_hw *hw = &adapter->hw;
167 u32 head, tail;
168
9a799d71 169 /* Detect a transmit hang in hardware, this serializes the
e01c31a5
JB		 170 * check with the clearing of time_stamp and movement of eop */
171 head = IXGBE_READ_REG(hw, tx_ring->head);
172 tail = IXGBE_READ_REG(hw, tx_ring->tail);
9a799d71 173 adapter->detect_tx_hung = false;
e01c31a5
JB		 174 if ((head != tail) &&
175 tx_ring->tx_buffer_info[eop].time_stamp &&
9a799d71
AK		 176 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
177 !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
178 /* detected Tx unit hang */
e01c31a5
JB		 179 union ixgbe_adv_tx_desc *tx_desc;
180 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
9a799d71 181 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
e01c31a5
JB		 182 " Tx Queue <%d>\n"
183 " TDH, TDT <%x>, <%x>\n"
9a799d71
AK		 184 " next_to_use <%x>\n"
185 " next_to_clean <%x>\n"
186 "tx_buffer_info[next_to_clean]\n"
187 " time_stamp <%lx>\n"
e01c31a5
JB		 188 " jiffies <%lx>\n",
189 tx_ring->queue_index,
190 head, tail,
191 tx_ring->next_to_use, eop,
192 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
9a799d71
AK		 193 return true;
194 }
195
196 return false;
197}
198
b4617240
PW		 199#define IXGBE_MAX_TXD_PWR 14
200#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
e092be60
AV		 201
202/* Tx Descriptors needed, worst case */
203#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
204 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
205#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
b4617240 206 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
e092be60 207
e01c31a5
JB		 208#define GET_TX_HEAD_FROM_RING(ring) (\
209 *(volatile u32 *) \
210 ((union ixgbe_adv_tx_desc *)(ring)->desc + (ring)->count))
211static void ixgbe_tx_timeout(struct net_device *netdev);
212
9a799d71
AK		 213/**
214 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
215 * @adapter: board private structure
e01c31a5 216 * @tx_ring: tx ring to clean
9a799d71
AK		 217 **/
218static bool ixgbe_clean_tx_irq(struct ixgbe_adapter *adapter,
e01c31a5 219 struct ixgbe_ring *tx_ring)
9a799d71 220{
e01c31a5 221 union ixgbe_adv_tx_desc *tx_desc;
9a799d71 222 struct ixgbe_tx_buffer *tx_buffer_info;
e01c31a5
JB		 223 struct net_device *netdev = adapter->netdev;
224 struct sk_buff *skb;
225 unsigned int i;
226 u32 head, oldhead;
227 unsigned int count = 0;
228 unsigned int total_bytes = 0, total_packets = 0;
9a799d71 229
e01c31a5
JB		 230 rmb();
231 head = GET_TX_HEAD_FROM_RING(tx_ring);
232 head = le32_to_cpu(head);
9a799d71 233 i = tx_ring->next_to_clean;
e01c31a5
JB		 234 while (1) {
235 while (i != head) {
9a799d71
AK		 236 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
237 tx_buffer_info = &tx_ring->tx_buffer_info[i];
e01c31a5 238 skb = tx_buffer_info->skb;
9a799d71 239
e01c31a5 240 if (skb) {
e092be60 241 unsigned int segs, bytecount;
e01c31a5
JB		 242
243 /* gso_segs is currently only valid for tcp */
e092be60
AV		 244 segs = skb_shinfo(skb)->gso_segs ?: 1;
245 /* multiply data chunks by size of headers */
246 bytecount = ((segs - 1) * skb_headlen(skb)) +
e01c31a5
JB		 247 skb->len;
248 total_packets += segs;
249 total_bytes += bytecount;
e092be60 250 }
e01c31a5 251
9a799d71 252 ixgbe_unmap_and_free_tx_resource(adapter,
e01c31a5 253 tx_buffer_info);
9a799d71
AK		 254
255 i++;
256 if (i == tx_ring->count)
257 i = 0;
9a799d71 258
e01c31a5
JB		 259 count++;
260 if (count == tx_ring->count)
261 goto done_cleaning;
262 }
263 oldhead = head;
264 rmb();
265 head = GET_TX_HEAD_FROM_RING(tx_ring);
266 head = le32_to_cpu(head);
267 if (head == oldhead)
268 goto done_cleaning;
269 } /* while (1) */
270
271done_cleaning:
9a799d71
AK		 272 tx_ring->next_to_clean = i;
273
e092be60 274#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
e01c31a5
JB		 275 if (unlikely(count && netif_carrier_ok(netdev) &&
276 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 277 /* Make sure that anybody stopping the queue after this
278 * sees the new next_to_clean.
279 */
280 smp_mb();
30eba97a
AV		 281 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
282 !test_bit(__IXGBE_DOWN, &adapter->state)) {
283 netif_wake_subqueue(netdev, tx_ring->queue_index);
e01c31a5 284 ++adapter->restart_queue;
30eba97a 285 }
e092be60 286 }
9a799d71 287
e01c31a5
JB		 288 if (adapter->detect_tx_hung) {
289 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
290 /* schedule immediate reset if we believe we hung */
291 DPRINTK(PROBE, INFO,
292 "tx hang %d detected, resetting adapter\n",
293 adapter->tx_timeout_count + 1);
294 ixgbe_tx_timeout(adapter->netdev);
295 }
296 }
9a799d71 297
e01c31a5
JB		 298 /* re-arm the interrupt */
299 if ((total_packets >= tx_ring->work_limit) ||
300 (count == tx_ring->count))
301 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, tx_ring->v_idx);
9a799d71 302
e01c31a5
JB		 303 tx_ring->total_bytes += total_bytes;
304 tx_ring->total_packets += total_packets;
305 tx_ring->stats.bytes += total_bytes;
306 tx_ring->stats.packets += total_packets;
307 adapter->net_stats.tx_bytes += total_bytes;
308 adapter->net_stats.tx_packets += total_packets;
309 return (total_packets ? true : false);
9a799d71
AK		 310}
311
a1f96ee7 312#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
bd0362dd 313static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
b4617240 314 struct ixgbe_ring *rx_ring)
bd0362dd
JC		 315{
316 u32 rxctrl;
317 int cpu = get_cpu();
3a581073 318 int q = rx_ring - adapter->rx_ring;
bd0362dd 319
3a581073 320 if (rx_ring->cpu != cpu) {
bd0362dd
JC		 321 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
322 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
96b0e0f6 323 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
bd0362dd
JC		 324 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
325 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
326 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
3a581073 327 rx_ring->cpu = cpu;
bd0362dd
JC		 328 }
329 put_cpu();
330}
331
332static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
b4617240 333 struct ixgbe_ring *tx_ring)
bd0362dd
JC		 334{
335 u32 txctrl;
336 int cpu = get_cpu();
3a581073 337 int q = tx_ring - adapter->tx_ring;
bd0362dd 338
3a581073 339 if (tx_ring->cpu != cpu) {
bd0362dd
JC		 340 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
341 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
96b0e0f6 342 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
bd0362dd
JC		 343 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
344 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
3a581073 345 tx_ring->cpu = cpu;
bd0362dd
JC		 346 }
347 put_cpu();
348}
349
350static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
351{
352 int i;
353
354 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
355 return;
356
357 for (i = 0; i < adapter->num_tx_queues; i++) {
358 adapter->tx_ring[i].cpu = -1;
359 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
360 }
361 for (i = 0; i < adapter->num_rx_queues; i++) {
362 adapter->rx_ring[i].cpu = -1;
363 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
364 }
365}
366
367static int __ixgbe_notify_dca(struct device *dev, void *data)
368{
369 struct net_device *netdev = dev_get_drvdata(dev);
370 struct ixgbe_adapter *adapter = netdev_priv(netdev);
371 unsigned long event = *(unsigned long *)data;
372
373 switch (event) {
374 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 375 /* if we're already enabled, don't do it again */
376 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
377 break;
bd0362dd
JC		 378 /* Always use CB2 mode, difference is masked
379 * in the CB driver. */
380 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
652f093f 381 if (dca_add_requester(dev) == 0) {
96b0e0f6 382 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 383 ixgbe_setup_dca(adapter);
384 break;
385 }
386 /* Fall Through since DCA is disabled. */
387 case DCA_PROVIDER_REMOVE:
388 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
389 dca_remove_requester(dev);
390 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
391 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
392 }
393 break;
394 }
395
652f093f 396 return 0;
bd0362dd
JC		 397}
398
96b0e0f6 399#endif /* CONFIG_DCA or CONFIG_DCA_MODULE */
9a799d71
AK		 400/**
401 * ixgbe_receive_skb - Send a completed packet up the stack
402 * @adapter: board private structure
403 * @skb: packet to send up
177db6ff
MC		 404 * @status: hardware indication of status of receive
405 * @rx_ring: rx descriptor ring (for a specific queue) to setup
406 * @rx_desc: rx descriptor
9a799d71
AK		 407 **/
408static void ixgbe_receive_skb(struct ixgbe_adapter *adapter,
b4617240
PW		 409 struct sk_buff *skb, u8 status,
410 struct ixgbe_ring *ring,
177db6ff 411 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 412{
177db6ff
MC		 413 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
414 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 415
177db6ff
MC		 416 if (adapter->netdev->features & NETIF_F_LRO &&
417 skb->ip_summed == CHECKSUM_UNNECESSARY) {
9a799d71 418 if (adapter->vlgrp && is_vlan)
177db6ff
MC		 419 lro_vlan_hwaccel_receive_skb(&ring->lro_mgr, skb,
420 adapter->vlgrp, tag,
421 rx_desc);
9a799d71 422 else
177db6ff
MC		 423 lro_receive_skb(&ring->lro_mgr, skb, rx_desc);
424 ring->lro_used = true;
425 } else {
426 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
427 if (adapter->vlgrp && is_vlan)
428 vlan_hwaccel_receive_skb(skb, adapter->vlgrp, tag);
429 else
430 netif_receive_skb(skb);
431 } else {
432 if (adapter->vlgrp && is_vlan)
433 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
434 else
435 netif_rx(skb);
436 }
9a799d71
AK		 437 }
438}
439
e59bd25d
AV		 440/**
441 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
442 * @adapter: address of board private structure
443 * @status_err: hardware indication of status of receive
444 * @skb: skb currently being received and modified
445 **/
9a799d71 446static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
712744be 447 u32 status_err, struct sk_buff *skb)
9a799d71
AK		 448{
449 skb->ip_summed = CHECKSUM_NONE;
450
712744be
JB		 451 /* Rx csum disabled */
452 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 453 return;
e59bd25d
AV		 454
455 /* if IP and error */
456 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
457 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 458 adapter->hw_csum_rx_error++;
459 return;
460 }
e59bd25d
AV		 461
462 if (!(status_err & IXGBE_RXD_STAT_L4CS))
463 return;
464
465 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
466 adapter->hw_csum_rx_error++;
467 return;
468 }
469
9a799d71 470 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 471 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 472 adapter->hw_csum_rx_good++;
473}
474
475/**
476 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
477 * @adapter: address of board private structure
478 **/
479static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
7c6e0a43
JB		 480 struct ixgbe_ring *rx_ring,
481 int cleaned_count)
9a799d71 482{
9a799d71
AK		 483 struct pci_dev *pdev = adapter->pdev;
484 union ixgbe_adv_rx_desc *rx_desc;
3a581073 485 struct ixgbe_rx_buffer *bi;
9a799d71 486 unsigned int i;
7c6e0a43 487 unsigned int bufsz = rx_ring->rx_buf_len + NET_IP_ALIGN;
9a799d71
AK		 488
489 i = rx_ring->next_to_use;
3a581073 490 bi = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 491
492 while (cleaned_count--) {
493 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
494
762f4c57 495 if (!bi->page_dma &&
3a581073 496 (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) {
3a581073 497 if (!bi->page) {
762f4c57
JB		 498 bi->page = alloc_page(GFP_ATOMIC);
499 if (!bi->page) {
500 adapter->alloc_rx_page_failed++;
501 goto no_buffers;
502 }
503 bi->page_offset = 0;
504 } else {
505 /* use a half page if we're re-using */
506 bi->page_offset ^= (PAGE_SIZE / 2);
9a799d71 507 }
762f4c57
JB		 508
509 bi->page_dma = pci_map_page(pdev, bi->page,
510 bi->page_offset,
511 (PAGE_SIZE / 2),
512 PCI_DMA_FROMDEVICE);
9a799d71
AK		 513 }
514
3a581073 515 if (!bi->skb) {
74ce8dd2
JB		 516 struct sk_buff *skb = netdev_alloc_skb(adapter->netdev,
517 bufsz);
9a799d71
AK		 518
519 if (!skb) {
520 adapter->alloc_rx_buff_failed++;
521 goto no_buffers;
522 }
523
524 /*
525 * Make buffer alignment 2 beyond a 16 byte boundary
526 * this will result in a 16 byte aligned IP header after
527 * the 14 byte MAC header is removed
528 */
529 skb_reserve(skb, NET_IP_ALIGN);
530
3a581073
JB		 531 bi->skb = skb;
532 bi->dma = pci_map_single(pdev, skb->data, bufsz,
533 PCI_DMA_FROMDEVICE);
9a799d71
AK		 534 }
535 /* Refresh the desc even if buffer_addrs didn't change because
536 * each write-back erases this info. */
537 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
3a581073
JB		 538 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
539 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 540 } else {
3a581073 541 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
9a799d71
AK		 542 }
543
544 i++;
545 if (i == rx_ring->count)
546 i = 0;
3a581073 547 bi = &rx_ring->rx_buffer_info[i];
9a799d71 548 }
7c6e0a43 549
9a799d71
AK		 550no_buffers:
551 if (rx_ring->next_to_use != i) {
552 rx_ring->next_to_use = i;
553 if (i-- == 0)
554 i = (rx_ring->count - 1);
555
556 /*
557 * Force memory writes to complete before letting h/w
558 * know there are new descriptors to fetch. (Only
559 * applicable for weak-ordered memory model archs,
560 * such as IA-64).
561 */
562 wmb();
563 writel(i, adapter->hw.hw_addr + rx_ring->tail);
564 }
565}
566
7c6e0a43
JB		 567static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
568{
569 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
570}
571
572static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
573{
574 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
575}
576
9a799d71 577static bool ixgbe_clean_rx_irq(struct ixgbe_adapter *adapter,
b4617240
PW		 578 struct ixgbe_ring *rx_ring,
579 int *work_done, int work_to_do)
9a799d71 580{
9a799d71
AK		 581 struct pci_dev *pdev = adapter->pdev;
582 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
583 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
584 struct sk_buff *skb;
585 unsigned int i;
7c6e0a43 586 u32 len, staterr;
177db6ff
MC		 587 u16 hdr_info;
588 bool cleaned = false;
9a799d71 589 int cleaned_count = 0;
d2f4fbe2 590 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
9a799d71
AK		 591
592 i = rx_ring->next_to_clean;
9a799d71
AK		 593 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
594 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
595 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 596
597 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 598 u32 upper_len = 0;
9a799d71
AK		 599 if (*work_done >= work_to_do)
600 break;
601 (*work_done)++;
602
603 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43
JB		 604 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
605 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
762f4c57 606 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
9a799d71
AK		 607 if (hdr_info & IXGBE_RXDADV_SPH)
608 adapter->rx_hdr_split++;
609 if (len > IXGBE_RX_HDR_SIZE)
610 len = IXGBE_RX_HDR_SIZE;
611 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 612 } else {
9a799d71 613 len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 614 }
9a799d71
AK		 615
616 cleaned = true;
617 skb = rx_buffer_info->skb;
618 prefetch(skb->data - NET_IP_ALIGN);
619 rx_buffer_info->skb = NULL;
620
621 if (len && !skb_shinfo(skb)->nr_frags) {
622 pci_unmap_single(pdev, rx_buffer_info->dma,
b4617240
PW		 623 rx_ring->rx_buf_len + NET_IP_ALIGN,
624 PCI_DMA_FROMDEVICE);
9a799d71
AK		 625 skb_put(skb, len);
626 }
627
628 if (upper_len) {
629 pci_unmap_page(pdev, rx_buffer_info->page_dma,
762f4c57 630 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9a799d71
AK		 631 rx_buffer_info->page_dma = 0;
632 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
762f4c57
JB		 633 rx_buffer_info->page,
634 rx_buffer_info->page_offset,
635 upper_len);
636
637 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
638 (page_count(rx_buffer_info->page) != 1))
639 rx_buffer_info->page = NULL;
640 else
641 get_page(rx_buffer_info->page);
9a799d71
AK		 642
643 skb->len += upper_len;
644 skb->data_len += upper_len;
645 skb->truesize += upper_len;
646 }
647
648 i++;
649 if (i == rx_ring->count)
650 i = 0;
651 next_buffer = &rx_ring->rx_buffer_info[i];
652
653 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
654 prefetch(next_rxd);
655
656 cleaned_count++;
657 if (staterr & IXGBE_RXD_STAT_EOP) {
658 rx_ring->stats.packets++;
659 rx_ring->stats.bytes += skb->len;
660 } else {
661 rx_buffer_info->skb = next_buffer->skb;
662 rx_buffer_info->dma = next_buffer->dma;
663 next_buffer->skb = skb;
762f4c57 664 next_buffer->dma = 0;
9a799d71
AK		 665 adapter->non_eop_descs++;
666 goto next_desc;
667 }
668
669 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
670 dev_kfree_skb_irq(skb);
671 goto next_desc;
672 }
673
674 ixgbe_rx_checksum(adapter, staterr, skb);
d2f4fbe2
AV		 675
676 /* probably a little skewed due to removing CRC */
677 total_rx_bytes += skb->len;
678 total_rx_packets++;
679
74ce8dd2 680 skb->protocol = eth_type_trans(skb, adapter->netdev);
177db6ff 681 ixgbe_receive_skb(adapter, skb, staterr, rx_ring, rx_desc);
74ce8dd2 682 adapter->netdev->last_rx = jiffies;
9a799d71
AK		 683
684next_desc:
685 rx_desc->wb.upper.status_error = 0;
686
687 /* return some buffers to hardware, one at a time is too slow */
688 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
689 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
690 cleaned_count = 0;
691 }
692
693 /* use prefetched values */
694 rx_desc = next_rxd;
695 rx_buffer_info = next_buffer;
696
697 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 698 }
699
700 if (rx_ring->lro_used) {
701 lro_flush_all(&rx_ring->lro_mgr);
702 rx_ring->lro_used = false;
9a799d71
AK		 703 }
704
705 rx_ring->next_to_clean = i;
706 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
707
708 if (cleaned_count)
709 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
710
f494e8fa
AV		 711 rx_ring->total_packets += total_rx_packets;
712 rx_ring->total_bytes += total_rx_bytes;
713 adapter->net_stats.rx_bytes += total_rx_bytes;
714 adapter->net_stats.rx_packets += total_rx_packets;
715
9a799d71
AK		 716 return cleaned;
717}
718
021230d4 719static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 720/**
721 * ixgbe_configure_msix - Configure MSI-X hardware
722 * @adapter: board private structure
723 *
724 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
725 * interrupts.
726 **/
727static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
728{
021230d4
AV		 729 struct ixgbe_q_vector *q_vector;
730 int i, j, q_vectors, v_idx, r_idx;
731 u32 mask;
9a799d71 732
021230d4 733 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 734
021230d4
AV		 735 /* Populate the IVAR table and set the ITR values to the
736 * corresponding register.
737 */
738 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
739 q_vector = &adapter->q_vector[v_idx];
740 /* XXX for_each_bit(...) */
741 r_idx = find_first_bit(q_vector->rxr_idx,
b4617240 742 adapter->num_rx_queues);
021230d4
AV		 743
744 for (i = 0; i < q_vector->rxr_count; i++) {
745 j = adapter->rx_ring[r_idx].reg_idx;
746 ixgbe_set_ivar(adapter, IXGBE_IVAR_RX_QUEUE(j), v_idx);
747 r_idx = find_next_bit(q_vector->rxr_idx,
b4617240
PW		 748 adapter->num_rx_queues,
749 r_idx + 1);
021230d4
AV		 750 }
751 r_idx = find_first_bit(q_vector->txr_idx,
b4617240 752 adapter->num_tx_queues);
021230d4
AV		 753
754 for (i = 0; i < q_vector->txr_count; i++) {
755 j = adapter->tx_ring[r_idx].reg_idx;
756 ixgbe_set_ivar(adapter, IXGBE_IVAR_TX_QUEUE(j), v_idx);
757 r_idx = find_next_bit(q_vector->txr_idx,
b4617240
PW		 758 adapter->num_tx_queues,
759 r_idx + 1);
021230d4
AV		 760 }
761
30efa5a3 762 /* if this is a tx only vector halve the interrupt rate */
021230d4 763 if (q_vector->txr_count && !q_vector->rxr_count)
30efa5a3 764 q_vector->eitr = (adapter->eitr_param >> 1);
021230d4 765 else
30efa5a3
JB		 766 /* rx only */
767 q_vector->eitr = adapter->eitr_param;
021230d4
AV		 768
769 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx),
b4617240 770 EITR_INTS_PER_SEC_TO_REG(q_vector->eitr));
9a799d71
AK		 771 }
772
021230d4
AV		 773 ixgbe_set_ivar(adapter, IXGBE_IVAR_OTHER_CAUSES_INDEX, v_idx);
774 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
775
41fb9248 776 /* set up to autoclear timer, and the vectors */
021230d4 777 mask = IXGBE_EIMS_ENABLE_MASK;
41fb9248 778 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 779 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 780}
781
f494e8fa
AV		 782enum latency_range {
783 lowest_latency = 0,
784 low_latency = 1,
785 bulk_latency = 2,
786 latency_invalid = 255
787};
788
789/**
790 * ixgbe_update_itr - update the dynamic ITR value based on statistics
791 * @adapter: pointer to adapter
792 * @eitr: eitr setting (ints per sec) to give last timeslice
793 * @itr_setting: current throttle rate in ints/second
794 * @packets: the number of packets during this measurement interval
795 * @bytes: the number of bytes during this measurement interval
796 *
797 * Stores a new ITR value based on packets and byte
798 * counts during the last interrupt. The advantage of per interrupt
799 * computation is faster updates and more accurate ITR for the current
800 * traffic pattern. Constants in this function were computed
801 * based on theoretical maximum wire speed and thresholds were set based
802 * on testing data as well as attempting to minimize response time
803 * while increasing bulk throughput.
804 * this functionality is controlled by the InterruptThrottleRate module
805 * parameter (see ixgbe_param.c)
806 **/
807static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
b4617240
PW		 808 u32 eitr, u8 itr_setting,
809 int packets, int bytes)
f494e8fa
AV		 810{
811 unsigned int retval = itr_setting;
812 u32 timepassed_us;
813 u64 bytes_perint;
814
815 if (packets == 0)
816 goto update_itr_done;
817
818
819 /* simple throttlerate management
820 * 0-20MB/s lowest (100000 ints/s)
821 * 20-100MB/s low (20000 ints/s)
822 * 100-1249MB/s bulk (8000 ints/s)
823 */
824 /* what was last interrupt timeslice? */
825 timepassed_us = 1000000/eitr;
826 bytes_perint = bytes / timepassed_us; /* bytes/usec */
827
828 switch (itr_setting) {
829 case lowest_latency:
830 if (bytes_perint > adapter->eitr_low)
831 retval = low_latency;
832 break;
833 case low_latency:
834 if (bytes_perint > adapter->eitr_high)
835 retval = bulk_latency;
836 else if (bytes_perint <= adapter->eitr_low)
837 retval = lowest_latency;
838 break;
839 case bulk_latency:
840 if (bytes_perint <= adapter->eitr_high)
841 retval = low_latency;
842 break;
843 }
844
845update_itr_done:
846 return retval;
847}
848
849static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
850{
851 struct ixgbe_adapter *adapter = q_vector->adapter;
852 struct ixgbe_hw *hw = &adapter->hw;
853 u32 new_itr;
854 u8 current_itr, ret_itr;
855 int i, r_idx, v_idx = ((void *)q_vector - (void *)(adapter->q_vector)) /
b4617240 856 sizeof(struct ixgbe_q_vector);
f494e8fa
AV		 857 struct ixgbe_ring *rx_ring, *tx_ring;
858
859 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
860 for (i = 0; i < q_vector->txr_count; i++) {
861 tx_ring = &(adapter->tx_ring[r_idx]);
862 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 863 q_vector->tx_itr,
864 tx_ring->total_packets,
865 tx_ring->total_bytes);
f494e8fa
AV		 866 /* if the result for this queue would decrease interrupt
867 * rate for this vector then use that result */
30efa5a3 868 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
b4617240 869 q_vector->tx_itr - 1 : ret_itr);
f494e8fa 870 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 871 r_idx + 1);
f494e8fa
AV		 872 }
873
874 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
875 for (i = 0; i < q_vector->rxr_count; i++) {
876 rx_ring = &(adapter->rx_ring[r_idx]);
877 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 878 q_vector->rx_itr,
879 rx_ring->total_packets,
880 rx_ring->total_bytes);
f494e8fa
AV		 881 /* if the result for this queue would decrease interrupt
882 * rate for this vector then use that result */
30efa5a3 883 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
b4617240 884 q_vector->rx_itr - 1 : ret_itr);
f494e8fa 885 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
b4617240 886 r_idx + 1);
f494e8fa
AV		 887 }
888
30efa5a3 889 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 890
891 switch (current_itr) {
892 /* counts and packets in update_itr are dependent on these numbers */
893 case lowest_latency:
894 new_itr = 100000;
895 break;
896 case low_latency:
897 new_itr = 20000; /* aka hwitr = ~200 */
898 break;
899 case bulk_latency:
900 default:
901 new_itr = 8000;
902 break;
903 }
904
905 if (new_itr != q_vector->eitr) {
906 u32 itr_reg;
907 /* do an exponential smoothing */
908 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
909 q_vector->eitr = new_itr;
910 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
911 /* must write high and low 16 bits to reset counter */
912 DPRINTK(TX_ERR, DEBUG, "writing eitr(%d): %08X\n", v_idx,
b4617240 913 itr_reg);
f494e8fa
AV		 914 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg | (itr_reg)<<16);
915 }
916
917 return;
918}
919
cf8280ee
JB		 920
921static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
922{
923 struct ixgbe_hw *hw = &adapter->hw;
924
925 adapter->lsc_int++;
926 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
927 adapter->link_check_timeout = jiffies;
928 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
929 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
930 schedule_work(&adapter->watchdog_task);
931 }
932}
933
9a799d71
AK		 934static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
935{
936 struct net_device *netdev = data;
937 struct ixgbe_adapter *adapter = netdev_priv(netdev);
938 struct ixgbe_hw *hw = &adapter->hw;
939 u32 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
940
cf8280ee
JB		 941 if (eicr & IXGBE_EICR_LSC)
942 ixgbe_check_lsc(adapter);
d4f80882
AV		 943
944 if (!test_bit(__IXGBE_DOWN, &adapter->state))
945 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 946
947 return IRQ_HANDLED;
948}
949
950static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
951{
021230d4
AV		 952 struct ixgbe_q_vector *q_vector = data;
953 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 954 struct ixgbe_ring *tx_ring;
021230d4
AV		 955 int i, r_idx;
956
957 if (!q_vector->txr_count)
958 return IRQ_HANDLED;
959
960 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
961 for (i = 0; i < q_vector->txr_count; i++) {
3a581073 962 tx_ring = &(adapter->tx_ring[r_idx]);
a1f96ee7 963#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
bd0362dd 964 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 965 ixgbe_update_tx_dca(adapter, tx_ring);
bd0362dd 966#endif
3a581073
JB		 967 tx_ring->total_bytes = 0;
968 tx_ring->total_packets = 0;
969 ixgbe_clean_tx_irq(adapter, tx_ring);
021230d4 970 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 971 r_idx + 1);
021230d4 972 }
9a799d71 973
9a799d71
AK		 974 return IRQ_HANDLED;
975}
976
021230d4
AV		 977/**
978 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
979 * @irq: unused
980 * @data: pointer to our q_vector struct for this interrupt vector
981 **/
9a799d71
AK		 982static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
983{
021230d4
AV		 984 struct ixgbe_q_vector *q_vector = data;
985 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 986 struct ixgbe_ring *rx_ring;
021230d4 987 int r_idx;
30efa5a3 988 int i;
021230d4
AV		 989
990 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
30efa5a3
JB		 991 for (i = 0; i < q_vector->rxr_count; i++) {
992 rx_ring = &(adapter->rx_ring[r_idx]);
993 rx_ring->total_bytes = 0;
994 rx_ring->total_packets = 0;
995 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
996 r_idx + 1);
997 }
998
021230d4
AV		 999 if (!q_vector->rxr_count)
1000 return IRQ_HANDLED;
1001
30efa5a3 1002 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
3a581073 1003 rx_ring = &(adapter->rx_ring[r_idx]);
021230d4 1004 /* disable interrupts on this vector only */
3a581073 1005 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, rx_ring->v_idx);
021230d4
AV		 1006 netif_rx_schedule(adapter->netdev, &q_vector->napi);
1007
1008 return IRQ_HANDLED;
1009}
1010
1011static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1012{
1013 ixgbe_msix_clean_rx(irq, data);
1014 ixgbe_msix_clean_tx(irq, data);
9a799d71 1015
9a799d71
AK		 1016 return IRQ_HANDLED;
1017}
1018
021230d4
AV		 1019/**
1020 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1021 * @napi: napi struct with our devices info in it
1022 * @budget: amount of work driver is allowed to do this pass, in packets
1023 *
f0848276
JB		 1024 * This function is optimized for cleaning one queue only on a single
1025 * q_vector!!!
021230d4 1026 **/
9a799d71
AK		 1027static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1028{
021230d4 1029 struct ixgbe_q_vector *q_vector =
b4617240 1030 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 1031 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 1032 struct ixgbe_ring *rx_ring = NULL;
9a799d71 1033 int work_done = 0;
021230d4 1034 long r_idx;
9a799d71 1035
021230d4 1036 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
3a581073 1037 rx_ring = &(adapter->rx_ring[r_idx]);
a1f96ee7 1038#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
bd0362dd 1039 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1040 ixgbe_update_rx_dca(adapter, rx_ring);
bd0362dd 1041#endif
9a799d71 1042
3a581073 1043 ixgbe_clean_rx_irq(adapter, rx_ring, &work_done, budget);
9a799d71 1044
021230d4
AV		 1045 /* If all Rx work done, exit the polling mode */
1046 if (work_done < budget) {
1047 netif_rx_complete(adapter->netdev, napi);
30efa5a3 1048 if (adapter->itr_setting & 3)
f494e8fa 1049 ixgbe_set_itr_msix(q_vector);
9a799d71 1050 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3a581073 1051 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, rx_ring->v_idx);
9a799d71
AK		 1052 }
1053
1054 return work_done;
1055}
1056
f0848276
JB		 1057/**
1058 * ixgbe_clean_rxonly_many - msix (aka one shot) rx clean routine
1059 * @napi: napi struct with our devices info in it
1060 * @budget: amount of work driver is allowed to do this pass, in packets
1061 *
1062 * This function will clean more than one rx queue associated with a
1063 * q_vector.
1064 **/
1065static int ixgbe_clean_rxonly_many(struct napi_struct *napi, int budget)
1066{
1067 struct ixgbe_q_vector *q_vector =
1068 container_of(napi, struct ixgbe_q_vector, napi);
1069 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276
JB		 1070 struct ixgbe_ring *rx_ring = NULL;
1071 int work_done = 0, i;
1072 long r_idx;
1073 u16 enable_mask = 0;
1074
1075 /* attempt to distribute budget to each queue fairly, but don't allow
1076 * the budget to go below 1 because we'll exit polling */
1077 budget /= (q_vector->rxr_count ?: 1);
1078 budget = max(budget, 1);
1079 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1080 for (i = 0; i < q_vector->rxr_count; i++) {
1081 rx_ring = &(adapter->rx_ring[r_idx]);
1082#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
1083 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1084 ixgbe_update_rx_dca(adapter, rx_ring);
1085#endif
1086 ixgbe_clean_rx_irq(adapter, rx_ring, &work_done, budget);
1087 enable_mask |= rx_ring->v_idx;
1088 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1089 r_idx + 1);
1090 }
1091
1092 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1093 rx_ring = &(adapter->rx_ring[r_idx]);
1094 /* If all Rx work done, exit the polling mode */
7f821875 1095 if (work_done < budget) {
74ce8dd2 1096 netif_rx_complete(adapter->netdev, napi);
f0848276
JB		 1097 if (adapter->itr_setting & 3)
1098 ixgbe_set_itr_msix(q_vector);
1099 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1100 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, enable_mask);
1101 return 0;
1102 }
1103
1104 return work_done;
1105}
021230d4 1106static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
b4617240 1107 int r_idx)
021230d4
AV		 1108{
1109 a->q_vector[v_idx].adapter = a;
1110 set_bit(r_idx, a->q_vector[v_idx].rxr_idx);
1111 a->q_vector[v_idx].rxr_count++;
1112 a->rx_ring[r_idx].v_idx = 1 << v_idx;
1113}
1114
1115static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
b4617240 1116 int r_idx)
021230d4
AV		 1117{
1118 a->q_vector[v_idx].adapter = a;
1119 set_bit(r_idx, a->q_vector[v_idx].txr_idx);
1120 a->q_vector[v_idx].txr_count++;
1121 a->tx_ring[r_idx].v_idx = 1 << v_idx;
1122}
1123
9a799d71 1124/**
021230d4
AV		 1125 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1126 * @adapter: board private structure to initialize
1127 * @vectors: allotted vector count for descriptor rings
9a799d71 1128 *
021230d4
AV		 1129 * This function maps descriptor rings to the queue-specific vectors
1130 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1131 * one vector per ring/queue, but on a constrained vector budget, we
1132 * group the rings as "efficiently" as possible. You would add new
1133 * mapping configurations in here.
9a799d71 1134 **/
021230d4 1135static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
b4617240 1136 int vectors)
021230d4
AV		 1137{
1138 int v_start = 0;
1139 int rxr_idx = 0, txr_idx = 0;
1140 int rxr_remaining = adapter->num_rx_queues;
1141 int txr_remaining = adapter->num_tx_queues;
1142 int i, j;
1143 int rqpv, tqpv;
1144 int err = 0;
1145
1146 /* No mapping required if MSI-X is disabled. */
1147 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1148 goto out;
9a799d71 1149
021230d4
AV		 1150 /*
1151 * The ideal configuration...
1152 * We have enough vectors to map one per queue.
1153 */
1154 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1155 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1156 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 1157
021230d4
AV		 1158 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1159 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 1160
9a799d71 1161 goto out;
021230d4 1162 }
9a799d71 1163
021230d4
AV		 1164 /*
1165 * If we don't have enough vectors for a 1-to-1
1166 * mapping, we'll have to group them so there are
1167 * multiple queues per vector.
1168 */
1169 /* Re-adjusting *qpv takes care of the remainder. */
1170 for (i = v_start; i < vectors; i++) {
1171 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1172 for (j = 0; j < rqpv; j++) {
1173 map_vector_to_rxq(adapter, i, rxr_idx);
1174 rxr_idx++;
1175 rxr_remaining--;
1176 }
1177 }
1178 for (i = v_start; i < vectors; i++) {
1179 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1180 for (j = 0; j < tqpv; j++) {
1181 map_vector_to_txq(adapter, i, txr_idx);
1182 txr_idx++;
1183 txr_remaining--;
9a799d71 1184 }
9a799d71
AK		 1185 }
1186
021230d4
AV		 1187out:
1188 return err;
1189}
1190
1191/**
1192 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1193 * @adapter: board private structure
1194 *
1195 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1196 * interrupts from the kernel.
1197 **/
1198static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1199{
1200 struct net_device *netdev = adapter->netdev;
1201 irqreturn_t (*handler)(int, void *);
1202 int i, vector, q_vectors, err;
1203
1204 /* Decrement for Other and TCP Timer vectors */
1205 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1206
1207 /* Map the Tx/Rx rings to the vectors we were allotted. */
1208 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1209 if (err)
1210 goto out;
1211
1212#define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
b4617240
PW		 1213 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1214 &ixgbe_msix_clean_many)
021230d4
AV		 1215 for (vector = 0; vector < q_vectors; vector++) {
1216 handler = SET_HANDLER(&adapter->q_vector[vector]);
1217 sprintf(adapter->name[vector], "%s:v%d-%s",
b4617240
PW		 1218 netdev->name, vector,
1219 (handler == &ixgbe_msix_clean_rx) ? "Rx" :
1220 ((handler == &ixgbe_msix_clean_tx) ? "Tx" : "TxRx"));
021230d4 1221 err = request_irq(adapter->msix_entries[vector].vector,
b4617240
PW		 1222 handler, 0, adapter->name[vector],
1223 &(adapter->q_vector[vector]));
9a799d71
AK		 1224 if (err) {
1225 DPRINTK(PROBE, ERR,
b4617240
PW		 1226 "request_irq failed for MSIX interrupt "
1227 "Error: %d\n", err);
021230d4 1228 goto free_queue_irqs;
9a799d71 1229 }
9a799d71
AK		 1230 }
1231
021230d4
AV		 1232 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1233 err = request_irq(adapter->msix_entries[vector].vector,
b4617240 1234 &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
9a799d71
AK		 1235 if (err) {
1236 DPRINTK(PROBE, ERR,
1237 "request_irq for msix_lsc failed: %d\n", err);
021230d4 1238 goto free_queue_irqs;
9a799d71
AK		 1239 }
1240
9a799d71
AK		 1241 return 0;
1242
021230d4
AV		 1243free_queue_irqs:
1244 for (i = vector - 1; i >= 0; i--)
1245 free_irq(adapter->msix_entries[--vector].vector,
b4617240 1246 &(adapter->q_vector[i]));
021230d4
AV		 1247 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1248 pci_disable_msix(adapter->pdev);
9a799d71
AK		 1249 kfree(adapter->msix_entries);
1250 adapter->msix_entries = NULL;
021230d4 1251out:
9a799d71
AK		 1252 return err;
1253}
1254
f494e8fa
AV		 1255static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1256{
1257 struct ixgbe_hw *hw = &adapter->hw;
1258 struct ixgbe_q_vector *q_vector = adapter->q_vector;
1259 u8 current_itr;
1260 u32 new_itr = q_vector->eitr;
1261 struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1262 struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1263
30efa5a3 1264 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1265 q_vector->tx_itr,
1266 tx_ring->total_packets,
1267 tx_ring->total_bytes);
30efa5a3 1268 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1269 q_vector->rx_itr,
1270 rx_ring->total_packets,
1271 rx_ring->total_bytes);
f494e8fa 1272
30efa5a3 1273 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1274
1275 switch (current_itr) {
1276 /* counts and packets in update_itr are dependent on these numbers */
1277 case lowest_latency:
1278 new_itr = 100000;
1279 break;
1280 case low_latency:
1281 new_itr = 20000; /* aka hwitr = ~200 */
1282 break;
1283 case bulk_latency:
1284 new_itr = 8000;
1285 break;
1286 default:
1287 break;
1288 }
1289
1290 if (new_itr != q_vector->eitr) {
1291 u32 itr_reg;
1292 /* do an exponential smoothing */
1293 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1294 q_vector->eitr = new_itr;
1295 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
1296 /* must write high and low 16 bits to reset counter */
1297 IXGBE_WRITE_REG(hw, IXGBE_EITR(0), itr_reg | (itr_reg)<<16);
1298 }
1299
1300 return;
1301}
1302
021230d4
AV		 1303static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter);
1304
9a799d71 1305/**
021230d4 1306 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 1307 * @irq: interrupt number
1308 * @data: pointer to a network interface device structure
1309 * @pt_regs: CPU registers structure
1310 **/
1311static irqreturn_t ixgbe_intr(int irq, void *data)
1312{
1313 struct net_device *netdev = data;
1314 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1315 struct ixgbe_hw *hw = &adapter->hw;
1316 u32 eicr;
1317
9a799d71 1318
021230d4
AV		 1319 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1320 * therefore no explict interrupt disable is necessary */
1321 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e
JB		 1322 if (!eicr) {
1323 /* shared interrupt alert!
1324 * make sure interrupts are enabled because the read will
1325 * have disabled interrupts due to EIAM */
1326 ixgbe_irq_enable(adapter);
9a799d71 1327 return IRQ_NONE; /* Not our interrupt */
f47cf66e 1328 }
9a799d71 1329
cf8280ee
JB		 1330 if (eicr & IXGBE_EICR_LSC)
1331 ixgbe_check_lsc(adapter);
021230d4
AV		 1332
1333 if (netif_rx_schedule_prep(netdev, &adapter->q_vector[0].napi)) {
f494e8fa
AV		 1334 adapter->tx_ring[0].total_packets = 0;
1335 adapter->tx_ring[0].total_bytes = 0;
1336 adapter->rx_ring[0].total_packets = 0;
1337 adapter->rx_ring[0].total_bytes = 0;
021230d4
AV		 1338 /* would disable interrupts here but EIAM disabled it */
1339 __netif_rx_schedule(netdev, &adapter->q_vector[0].napi);
9a799d71
AK		 1340 }
1341
1342 return IRQ_HANDLED;
1343}
1344
021230d4
AV		 1345static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1346{
1347 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1348
1349 for (i = 0; i < q_vectors; i++) {
1350 struct ixgbe_q_vector *q_vector = &adapter->q_vector[i];
1351 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1352 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1353 q_vector->rxr_count = 0;
1354 q_vector->txr_count = 0;
1355 }
1356}
1357
9a799d71
AK		 1358/**
1359 * ixgbe_request_irq - initialize interrupts
1360 * @adapter: board private structure
1361 *
1362 * Attempts to configure interrupts using the best available
1363 * capabilities of the hardware and kernel.
1364 **/
021230d4 1365static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 1366{
1367 struct net_device *netdev = adapter->netdev;
021230d4 1368 int err;
9a799d71 1369
021230d4
AV		 1370 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1371 err = ixgbe_request_msix_irqs(adapter);
1372 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1373 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
b4617240 1374 netdev->name, netdev);
021230d4
AV		 1375 } else {
1376 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
b4617240 1377 netdev->name, netdev);
9a799d71
AK		 1378 }
1379
9a799d71
AK		 1380 if (err)
1381 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1382
9a799d71
AK		 1383 return err;
1384}
1385
1386static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1387{
1388 struct net_device *netdev = adapter->netdev;
1389
1390 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 1391 int i, q_vectors;
9a799d71 1392
021230d4
AV		 1393 q_vectors = adapter->num_msix_vectors;
1394
1395 i = q_vectors - 1;
9a799d71 1396 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 1397
021230d4
AV		 1398 i--;
1399 for (; i >= 0; i--) {
1400 free_irq(adapter->msix_entries[i].vector,
b4617240 1401 &(adapter->q_vector[i]));
021230d4
AV		 1402 }
1403
1404 ixgbe_reset_q_vectors(adapter);
1405 } else {
1406 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 1407 }
1408}
1409
1410/**
1411 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1412 * @adapter: board private structure
1413 **/
1414static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1415{
9a799d71
AK		 1416 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1417 IXGBE_WRITE_FLUSH(&adapter->hw);
021230d4
AV		 1418 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1419 int i;
1420 for (i = 0; i < adapter->num_msix_vectors; i++)
1421 synchronize_irq(adapter->msix_entries[i].vector);
1422 } else {
1423 synchronize_irq(adapter->pdev->irq);
1424 }
9a799d71
AK		 1425}
1426
1427/**
1428 * ixgbe_irq_enable - Enable default interrupt generation settings
1429 * @adapter: board private structure
1430 **/
1431static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1432{
021230d4
AV		 1433 u32 mask;
1434 mask = IXGBE_EIMS_ENABLE_MASK;
1435 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
d4f80882 1436 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 1437}
1438
1439/**
1440 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1441 *
1442 **/
1443static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1444{
9a799d71
AK		 1445 struct ixgbe_hw *hw = &adapter->hw;
1446
021230d4 1447 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
30efa5a3 1448 EITR_INTS_PER_SEC_TO_REG(adapter->eitr_param));
9a799d71
AK		 1449
1450 ixgbe_set_ivar(adapter, IXGBE_IVAR_RX_QUEUE(0), 0);
021230d4
AV		 1451 ixgbe_set_ivar(adapter, IXGBE_IVAR_TX_QUEUE(0), 0);
1452
1453 map_vector_to_rxq(adapter, 0, 0);
1454 map_vector_to_txq(adapter, 0, 0);
1455
1456 DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 1457}
1458
1459/**
3a581073 1460 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 1461 * @adapter: board private structure
1462 *
1463 * Configure the Tx unit of the MAC after a reset.
1464 **/
1465static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1466{
e01c31a5 1467 u64 tdba, tdwba;
9a799d71 1468 struct ixgbe_hw *hw = &adapter->hw;
021230d4 1469 u32 i, j, tdlen, txctrl;
9a799d71
AK		 1470
1471 /* Setup the HW Tx Head and Tail descriptor pointers */
1472 for (i = 0; i < adapter->num_tx_queues; i++) {
e01c31a5
JB		 1473 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1474 j = ring->reg_idx;
1475 tdba = ring->dma;
1476 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
021230d4 1477 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
e01c31a5 1478 (tdba & DMA_32BIT_MASK));
021230d4 1479 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
e01c31a5
JB		 1480 tdwba = ring->dma +
1481 (ring->count * sizeof(union ixgbe_adv_tx_desc));
1482 tdwba |= IXGBE_TDWBAL_HEAD_WB_ENABLE;
1483 IXGBE_WRITE_REG(hw, IXGBE_TDWBAL(j), tdwba & DMA_32BIT_MASK);
1484 IXGBE_WRITE_REG(hw, IXGBE_TDWBAH(j), (tdwba >> 32));
021230d4
AV		 1485 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1486 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1487 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1488 adapter->tx_ring[i].head = IXGBE_TDH(j);
1489 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1490 /* Disable Tx Head Writeback RO bit, since this hoses
1491 * bookkeeping if things aren't delivered in order.
1492 */
e01c31a5 1493 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
021230d4 1494 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
e01c31a5 1495 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
9a799d71 1496 }
9a799d71
AK		 1497}
1498
cc41ac7c
JB		 1499#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
1500
1501static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, int index)
1502{
1503 struct ixgbe_ring *rx_ring;
1504 u32 srrctl;
1505 int queue0;
3be1adfb
AD		 1506 unsigned long mask;
1507
1508 /* program one srrctl register per VMDq index */
1509 if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) {
1510 long shift, len;
1511 mask = (unsigned long) adapter->ring_feature[RING_F_RSS].mask;
1512 len = sizeof(adapter->ring_feature[RING_F_VMDQ].mask) * 8;
1513 shift = find_first_bit(&mask, len);
1514 queue0 = index & mask;
1515 index = (index & mask) >> shift;
1516 /* program one srrctl per RSS queue since RDRXCTL.MVMEN is enabled */
cc41ac7c 1517 } else {
3be1adfb
AD		 1518 mask = (unsigned long) adapter->ring_feature[RING_F_RSS].mask;
1519 queue0 = index & mask;
1520 index = index & mask;
cc41ac7c 1521 }
3be1adfb 1522
cc41ac7c
JB		 1523 rx_ring = &adapter->rx_ring[queue0];
1524
1525 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
1526
1527 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1528 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1529
1530 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1531 srrctl |= IXGBE_RXBUFFER_2048 >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1532 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1533 srrctl |= ((IXGBE_RX_HDR_SIZE <<
b4617240
PW		 1534 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1535 IXGBE_SRRCTL_BSIZEHDR_MASK);
cc41ac7c
JB		 1536 } else {
1537 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
1538
1539 if (rx_ring->rx_buf_len == MAXIMUM_ETHERNET_VLAN_SIZE)
1540 srrctl |= IXGBE_RXBUFFER_2048 >>
1541 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1542 else
1543 srrctl |= rx_ring->rx_buf_len >>
1544 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1545 }
1546 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
1547}
9a799d71 1548
177db6ff
MC		 1549/**
1550 * ixgbe_get_skb_hdr - helper function for LRO header processing
1551 * @skb: pointer to sk_buff to be added to LRO packet
b4617240 1552 * @iphdr: pointer to ip header structure
177db6ff
MC		 1553 * @tcph: pointer to tcp header structure
1554 * @hdr_flags: pointer to header flags
1555 * @priv: private data
1556 **/
1557static int ixgbe_get_skb_hdr(struct sk_buff *skb, void **iphdr, void **tcph,
1558 u64 *hdr_flags, void *priv)
1559{
1560 union ixgbe_adv_rx_desc *rx_desc = priv;
1561
1562 /* Verify that this is a valid IPv4 TCP packet */
e9990a9c
JB		 1563 if (!((ixgbe_get_pkt_info(rx_desc) & IXGBE_RXDADV_PKTTYPE_IPV4) &&
1564 (ixgbe_get_pkt_info(rx_desc) & IXGBE_RXDADV_PKTTYPE_TCP)))
177db6ff
MC		 1565 return -1;
1566
1567 /* Set network headers */
1568 skb_reset_network_header(skb);
1569 skb_set_transport_header(skb, ip_hdrlen(skb));
1570 *iphdr = ip_hdr(skb);
1571 *tcph = tcp_hdr(skb);
1572 *hdr_flags = LRO_IPV4 | LRO_TCP;
1573 return 0;
1574}
1575
cc41ac7c 1576#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
b4617240 1577 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
cc41ac7c 1578
9a799d71 1579/**
3a581073 1580 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
9a799d71
AK		 1581 * @adapter: board private structure
1582 *
1583 * Configure the Rx unit of the MAC after a reset.
1584 **/
1585static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
1586{
1587 u64 rdba;
1588 struct ixgbe_hw *hw = &adapter->hw;
1589 struct net_device *netdev = adapter->netdev;
1590 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 1591 int i, j;
9a799d71 1592 u32 rdlen, rxctrl, rxcsum;
7c6e0a43
JB		 1593 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
1594 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
1595 0x6A3E67EA, 0x14364D17, 0x3BED200D};
9a799d71 1596 u32 fctrl, hlreg0;
9a799d71 1597 u32 pages;
cc41ac7c
JB		 1598 u32 reta = 0, mrqc;
1599 u32 rdrxctl;
7c6e0a43 1600 int rx_buf_len;
9a799d71
AK		 1601
1602 /* Decide whether to use packet split mode or not */
762f4c57 1603 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
9a799d71
AK		 1604
1605 /* Set the RX buffer length according to the mode */
1606 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 1607 rx_buf_len = IXGBE_RX_HDR_SIZE;
9a799d71
AK		 1608 } else {
1609 if (netdev->mtu <= ETH_DATA_LEN)
7c6e0a43 1610 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 1611 else
7c6e0a43 1612 rx_buf_len = ALIGN(max_frame, 1024);
9a799d71
AK		 1613 }
1614
1615 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1616 fctrl |= IXGBE_FCTRL_BAM;
021230d4 1617 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
9a799d71
AK		 1618 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
1619
1620 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1621 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1622 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
1623 else
1624 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
1625 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1626
1627 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
1628
9a799d71
AK		 1629 rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
1630 /* disable receives while setting up the descriptors */
1631 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1632 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
1633
1634 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1635 * the Base and Length of the Rx Descriptor Ring */
1636 for (i = 0; i < adapter->num_rx_queues; i++) {
1637 rdba = adapter->rx_ring[i].dma;
7c6e0a43
JB		 1638 j = adapter->rx_ring[i].reg_idx;
1639 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_32BIT_MASK));
1640 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
1641 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
1642 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
1643 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
1644 adapter->rx_ring[i].head = IXGBE_RDH(j);
1645 adapter->rx_ring[i].tail = IXGBE_RDT(j);
1646 adapter->rx_ring[i].rx_buf_len = rx_buf_len;
e9990a9c
JB		 1647 /* Intitial LRO Settings */
1648 adapter->rx_ring[i].lro_mgr.max_aggr = IXGBE_MAX_LRO_AGGREGATE;
1649 adapter->rx_ring[i].lro_mgr.max_desc = IXGBE_MAX_LRO_DESCRIPTORS;
1650 adapter->rx_ring[i].lro_mgr.get_skb_header = ixgbe_get_skb_hdr;
1651 adapter->rx_ring[i].lro_mgr.features = LRO_F_EXTRACT_VLAN_ID;
1652 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1653 adapter->rx_ring[i].lro_mgr.features |= LRO_F_NAPI;
1654 adapter->rx_ring[i].lro_mgr.dev = adapter->netdev;
1655 adapter->rx_ring[i].lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
1656 adapter->rx_ring[i].lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
cc41ac7c
JB		 1657
1658 ixgbe_configure_srrctl(adapter, j);
9a799d71
AK		 1659 }
1660
cc41ac7c
JB		 1661 /*
1662 * For VMDq support of different descriptor types or
1663 * buffer sizes through the use of multiple SRRCTL
1664 * registers, RDRXCTL.MVMEN must be set to 1
1665 *
1666 * also, the manual doesn't mention it clearly but DCA hints
1667 * will only use queue 0's tags unless this bit is set. Side
1668 * effects of setting this bit are only that SRRCTL must be
1669 * fully programmed [0..15]
1670 */
1671 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1672 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
1673 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
1674
177db6ff 1675
021230d4 1676 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
9a799d71 1677 /* Fill out redirection table */
021230d4
AV		 1678 for (i = 0, j = 0; i < 128; i++, j++) {
1679 if (j == adapter->ring_feature[RING_F_RSS].indices)
1680 j = 0;
1681 /* reta = 4-byte sliding window of
1682 * 0x00..(indices-1)(indices-1)00..etc. */
1683 reta = (reta << 8) | (j * 0x11);
1684 if ((i & 3) == 3)
1685 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
9a799d71
AK		 1686 }
1687
1688 /* Fill out hash function seeds */
1689 for (i = 0; i < 10; i++)
7c6e0a43 1690 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
9a799d71
AK		 1691
1692 mrqc = IXGBE_MRQC_RSSEN
1693 /* Perform hash on these packet types */
7c6e0a43
JB		 1694 | IXGBE_MRQC_RSS_FIELD_IPV4
1695 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
1696 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
1697 | IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP
1698 | IXGBE_MRQC_RSS_FIELD_IPV6_EX
1699 | IXGBE_MRQC_RSS_FIELD_IPV6
1700 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
1701 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP
1702 | IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
9a799d71 1703 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
021230d4 1704 }
9a799d71 1705
021230d4
AV		 1706 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
1707
1708 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
1709 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
1710 /* Disable indicating checksum in descriptor, enables
1711 * RSS hash */
9a799d71 1712 rxcsum |= IXGBE_RXCSUM_PCSD;
9a799d71 1713 }
021230d4
AV		 1714 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
1715 /* Enable IPv4 payload checksum for UDP fragments
1716 * if PCSD is not set */
1717 rxcsum |= IXGBE_RXCSUM_IPPCSE;
1718 }
1719
1720 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
9a799d71
AK		 1721}
1722
1723static void ixgbe_vlan_rx_register(struct net_device *netdev,
b4617240 1724 struct vlan_group *grp)
9a799d71
AK		 1725{
1726 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1727 u32 ctrl;
1728
d4f80882
AV		 1729 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1730 ixgbe_irq_disable(adapter);
9a799d71
AK		 1731 adapter->vlgrp = grp;
1732
1733 if (grp) {
1734 /* enable VLAN tag insert/strip */
1735 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
746b9f02 1736 ctrl |= IXGBE_VLNCTRL_VME;
9a799d71
AK		 1737 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
1738 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
1739 }
1740
d4f80882
AV		 1741 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1742 ixgbe_irq_enable(adapter);
9a799d71
AK		 1743}
1744
1745static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
1746{
1747 struct ixgbe_adapter *adapter = netdev_priv(netdev);
c44ade9e 1748 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 1749
1750 /* add VID to filter table */
c44ade9e 1751 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
9a799d71
AK		 1752}
1753
1754static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
1755{
1756 struct ixgbe_adapter *adapter = netdev_priv(netdev);
c44ade9e 1757 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 1758
d4f80882
AV		 1759 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1760 ixgbe_irq_disable(adapter);
1761
9a799d71 1762 vlan_group_set_device(adapter->vlgrp, vid, NULL);
d4f80882
AV		 1763
1764 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1765 ixgbe_irq_enable(adapter);
9a799d71
AK		 1766
1767 /* remove VID from filter table */
c44ade9e 1768 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
9a799d71
AK		 1769}
1770
1771static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
1772{
1773 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
1774
1775 if (adapter->vlgrp) {
1776 u16 vid;
1777 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
1778 if (!vlan_group_get_device(adapter->vlgrp, vid))
1779 continue;
1780 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
1781 }
1782 }
1783}
1784
2c5645cf
CL		 1785static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
1786{
1787 struct dev_mc_list *mc_ptr;
1788 u8 *addr = *mc_addr_ptr;
1789 *vmdq = 0;
1790
1791 mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
1792 if (mc_ptr->next)
1793 *mc_addr_ptr = mc_ptr->next->dmi_addr;
1794 else
1795 *mc_addr_ptr = NULL;
1796
1797 return addr;
1798}
1799
9a799d71 1800/**
2c5645cf 1801 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 1802 * @netdev: network interface device structure
1803 *
2c5645cf
CL		 1804 * The set_rx_method entry point is called whenever the unicast/multicast
1805 * address list or the network interface flags are updated. This routine is
1806 * responsible for configuring the hardware for proper unicast, multicast and
1807 * promiscuous mode.
9a799d71 1808 **/
2c5645cf 1809static void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 1810{
1811 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1812 struct ixgbe_hw *hw = &adapter->hw;
3d01625a 1813 u32 fctrl, vlnctrl;
2c5645cf
CL		 1814 u8 *addr_list = NULL;
1815 int addr_count = 0;
9a799d71
AK		 1816
1817 /* Check for Promiscuous and All Multicast modes */
1818
1819 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3d01625a 1820 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
9a799d71
AK		 1821
1822 if (netdev->flags & IFF_PROMISC) {
2c5645cf 1823 hw->addr_ctrl.user_set_promisc = 1;
9a799d71 1824 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3d01625a 1825 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
9a799d71 1826 } else {
746b9f02
PM		 1827 if (netdev->flags & IFF_ALLMULTI) {
1828 fctrl |= IXGBE_FCTRL_MPE;
1829 fctrl &= ~IXGBE_FCTRL_UPE;
1830 } else {
1831 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
1832 }
3d01625a 1833 vlnctrl |= IXGBE_VLNCTRL_VFE;
2c5645cf 1834 hw->addr_ctrl.user_set_promisc = 0;
9a799d71
AK		 1835 }
1836
1837 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3d01625a 1838 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
9a799d71 1839
2c5645cf
CL		 1840 /* reprogram secondary unicast list */
1841 addr_count = netdev->uc_count;
1842 if (addr_count)
1843 addr_list = netdev->uc_list->dmi_addr;
c44ade9e
JB		 1844 hw->mac.ops.update_uc_addr_list(hw, addr_list, addr_count,
1845 ixgbe_addr_list_itr);
9a799d71 1846
2c5645cf
CL		 1847 /* reprogram multicast list */
1848 addr_count = netdev->mc_count;
1849 if (addr_count)
1850 addr_list = netdev->mc_list->dmi_addr;
c44ade9e
JB		 1851 hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
1852 ixgbe_addr_list_itr);
9a799d71
AK		 1853}
1854
021230d4
AV		 1855static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
1856{
1857 int q_idx;
1858 struct ixgbe_q_vector *q_vector;
1859 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1860
1861 /* legacy and MSI only use one vector */
1862 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1863 q_vectors = 1;
1864
1865 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 1866 struct napi_struct *napi;
021230d4
AV		 1867 q_vector = &adapter->q_vector[q_idx];
1868 if (!q_vector->rxr_count)
1869 continue;
f0848276
JB		 1870 napi = &q_vector->napi;
1871 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) &&
1872 (q_vector->rxr_count > 1))
1873 napi->poll = &ixgbe_clean_rxonly_many;
1874
1875 napi_enable(napi);
021230d4
AV		 1876 }
1877}
1878
1879static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
1880{
1881 int q_idx;
1882 struct ixgbe_q_vector *q_vector;
1883 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1884
1885 /* legacy and MSI only use one vector */
1886 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1887 q_vectors = 1;
1888
1889 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
1890 q_vector = &adapter->q_vector[q_idx];
1891 if (!q_vector->rxr_count)
1892 continue;
1893 napi_disable(&q_vector->napi);
1894 }
1895}
1896
9a799d71
AK		 1897static void ixgbe_configure(struct ixgbe_adapter *adapter)
1898{
1899 struct net_device *netdev = adapter->netdev;
1900 int i;
1901
2c5645cf 1902 ixgbe_set_rx_mode(netdev);
9a799d71
AK		 1903
1904 ixgbe_restore_vlan(adapter);
1905
1906 ixgbe_configure_tx(adapter);
1907 ixgbe_configure_rx(adapter);
1908 for (i = 0; i < adapter->num_rx_queues; i++)
1909 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
b4617240 1910 (adapter->rx_ring[i].count - 1));
9a799d71
AK		 1911}
1912
1913static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
1914{
1915 struct net_device *netdev = adapter->netdev;
9a799d71 1916 struct ixgbe_hw *hw = &adapter->hw;
021230d4 1917 int i, j = 0;
9a799d71 1918 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4
AV		 1919 u32 txdctl, rxdctl, mhadd;
1920 u32 gpie;
9a799d71 1921
5eba3699
AV		 1922 ixgbe_get_hw_control(adapter);
1923
021230d4
AV		 1924 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
1925 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
9a799d71
AK		 1926 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1927 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
b4617240 1928 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
9a799d71
AK		 1929 } else {
1930 /* MSI only */
021230d4 1931 gpie = 0;
9a799d71 1932 }
021230d4
AV		 1933 /* XXX: to interrupt immediately for EICS writes, enable this */
1934 /* gpie |= IXGBE_GPIE_EIMEN; */
1935 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
9a799d71
AK		 1936 }
1937
021230d4
AV		 1938 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
1939 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
1940 * specifically only auto mask tx and rx interrupts */
1941 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
1942 }
9a799d71 1943
021230d4 1944 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
9a799d71
AK		 1945 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
1946 mhadd &= ~IXGBE_MHADD_MFS_MASK;
1947 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
1948
1949 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
1950 }
1951
1952 for (i = 0; i < adapter->num_tx_queues; i++) {
021230d4
AV		 1953 j = adapter->tx_ring[i].reg_idx;
1954 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
e01c31a5
JB		 1955 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
1956 txdctl |= (8 << 16);
9a799d71 1957 txdctl |= IXGBE_TXDCTL_ENABLE;
021230d4 1958 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
9a799d71
AK		 1959 }
1960
1961 for (i = 0; i < adapter->num_rx_queues; i++) {
021230d4
AV		 1962 j = adapter->rx_ring[i].reg_idx;
1963 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
1964 /* enable PTHRESH=32 descriptors (half the internal cache)
1965 * and HTHRESH=0 descriptors (to minimize latency on fetch),
1966 * this also removes a pesky rx_no_buffer_count increment */
1967 rxdctl |= 0x0020;
9a799d71 1968 rxdctl |= IXGBE_RXDCTL_ENABLE;
021230d4 1969 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
9a799d71
AK		 1970 }
1971 /* enable all receives */
1972 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1973 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
1974 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxdctl);
1975
1976 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
1977 ixgbe_configure_msix(adapter);
1978 else
1979 ixgbe_configure_msi_and_legacy(adapter);
1980
1981 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 1982 ixgbe_napi_enable_all(adapter);
1983
1984 /* clear any pending interrupts, may auto mask */
1985 IXGBE_READ_REG(hw, IXGBE_EICR);
1986
9a799d71
AK		 1987 ixgbe_irq_enable(adapter);
1988
1989 /* bring the link up in the watchdog, this could race with our first
1990 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 1991 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1992 adapter->link_check_timeout = jiffies;
9a799d71
AK		 1993 mod_timer(&adapter->watchdog_timer, jiffies);
1994 return 0;
1995}
1996
d4f80882
AV		 1997void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
1998{
1999 WARN_ON(in_interrupt());
2000 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2001 msleep(1);
2002 ixgbe_down(adapter);
2003 ixgbe_up(adapter);
2004 clear_bit(__IXGBE_RESETTING, &adapter->state);
2005}
2006
9a799d71
AK		 2007int ixgbe_up(struct ixgbe_adapter *adapter)
2008{
2009 /* hardware has been reset, we need to reload some things */
2010 ixgbe_configure(adapter);
2011
2012 return ixgbe_up_complete(adapter);
2013}
2014
2015void ixgbe_reset(struct ixgbe_adapter *adapter)
2016{
c44ade9e
JB		 2017 struct ixgbe_hw *hw = &adapter->hw;
2018 if (hw->mac.ops.init_hw(hw))
2019 dev_err(&adapter->pdev->dev, "Hardware Error\n");
9a799d71
AK		 2020
2021 /* reprogram the RAR[0] in case user changed it. */
c44ade9e 2022 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71
AK		 2023
2024}
2025
2026#ifdef CONFIG_PM
2027static int ixgbe_resume(struct pci_dev *pdev)
2028{
2029 struct net_device *netdev = pci_get_drvdata(pdev);
2030 struct ixgbe_adapter *adapter = netdev_priv(netdev);
021230d4 2031 u32 err;
9a799d71
AK		 2032
2033 pci_set_power_state(pdev, PCI_D0);
2034 pci_restore_state(pdev);
2035 err = pci_enable_device(pdev);
2036 if (err) {
2037 printk(KERN_ERR "ixgbe: Cannot enable PCI device from " \
b4617240 2038 "suspend\n");
9a799d71
AK		 2039 return err;
2040 }
2041 pci_set_master(pdev);
2042
2043 pci_enable_wake(pdev, PCI_D3hot, 0);
2044 pci_enable_wake(pdev, PCI_D3cold, 0);
2045
2046 if (netif_running(netdev)) {
021230d4 2047 err = ixgbe_request_irq(adapter);
9a799d71
AK		 2048 if (err)
2049 return err;
2050 }
2051
2052 ixgbe_reset(adapter);
2053
2054 if (netif_running(netdev))
2055 ixgbe_up(adapter);
2056
2057 netif_device_attach(netdev);
2058
2059 return 0;
2060}
2061#endif
2062
2063/**
2064 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2065 * @adapter: board private structure
2066 * @rx_ring: ring to free buffers from
2067 **/
2068static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
b4617240 2069 struct ixgbe_ring *rx_ring)
9a799d71
AK		 2070{
2071 struct pci_dev *pdev = adapter->pdev;
2072 unsigned long size;
2073 unsigned int i;
2074
2075 /* Free all the Rx ring sk_buffs */
2076
2077 for (i = 0; i < rx_ring->count; i++) {
2078 struct ixgbe_rx_buffer *rx_buffer_info;
2079
2080 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2081 if (rx_buffer_info->dma) {
2082 pci_unmap_single(pdev, rx_buffer_info->dma,
b4617240
PW		 2083 rx_ring->rx_buf_len,
2084 PCI_DMA_FROMDEVICE);
9a799d71
AK		 2085 rx_buffer_info->dma = 0;
2086 }
2087 if (rx_buffer_info->skb) {
2088 dev_kfree_skb(rx_buffer_info->skb);
2089 rx_buffer_info->skb = NULL;
2090 }
2091 if (!rx_buffer_info->page)
2092 continue;
762f4c57
JB		 2093 pci_unmap_page(pdev, rx_buffer_info->page_dma, PAGE_SIZE / 2,
2094 PCI_DMA_FROMDEVICE);
9a799d71 2095 rx_buffer_info->page_dma = 0;
9a799d71
AK		 2096 put_page(rx_buffer_info->page);
2097 rx_buffer_info->page = NULL;
762f4c57 2098 rx_buffer_info->page_offset = 0;
9a799d71
AK		 2099 }
2100
2101 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2102 memset(rx_ring->rx_buffer_info, 0, size);
2103
2104 /* Zero out the descriptor ring */
2105 memset(rx_ring->desc, 0, rx_ring->size);
2106
2107 rx_ring->next_to_clean = 0;
2108 rx_ring->next_to_use = 0;
2109
2110 writel(0, adapter->hw.hw_addr + rx_ring->head);
2111 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2112}
2113
2114/**
2115 * ixgbe_clean_tx_ring - Free Tx Buffers
2116 * @adapter: board private structure
2117 * @tx_ring: ring to be cleaned
2118 **/
2119static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
b4617240 2120 struct ixgbe_ring *tx_ring)
9a799d71
AK		 2121{
2122 struct ixgbe_tx_buffer *tx_buffer_info;
2123 unsigned long size;
2124 unsigned int i;
2125
2126 /* Free all the Tx ring sk_buffs */
2127
2128 for (i = 0; i < tx_ring->count; i++) {
2129 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2130 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2131 }
2132
2133 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2134 memset(tx_ring->tx_buffer_info, 0, size);
2135
2136 /* Zero out the descriptor ring */
2137 memset(tx_ring->desc, 0, tx_ring->size);
2138
2139 tx_ring->next_to_use = 0;
2140 tx_ring->next_to_clean = 0;
2141
2142 writel(0, adapter->hw.hw_addr + tx_ring->head);
2143 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2144}
2145
2146/**
021230d4 2147 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 2148 * @adapter: board private structure
2149 **/
021230d4 2150static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 2151{
2152 int i;
2153
021230d4
AV		 2154 for (i = 0; i < adapter->num_rx_queues; i++)
2155 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
9a799d71
AK		 2156}
2157
2158/**
021230d4 2159 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 2160 * @adapter: board private structure
2161 **/
021230d4 2162static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 2163{
2164 int i;
2165
021230d4
AV		 2166 for (i = 0; i < adapter->num_tx_queues; i++)
2167 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
9a799d71
AK		 2168}
2169
2170void ixgbe_down(struct ixgbe_adapter *adapter)
2171{
2172 struct net_device *netdev = adapter->netdev;
7f821875 2173 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 2174 u32 rxctrl;
7f821875
JB		 2175 u32 txdctl;
2176 int i, j;
9a799d71
AK		 2177
2178 /* signal that we are down to the interrupt handler */
2179 set_bit(__IXGBE_DOWN, &adapter->state);
2180
2181 /* disable receives */
7f821875
JB		 2182 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2183 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71
AK		 2184
2185 netif_tx_disable(netdev);
2186
7f821875 2187 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 2188 msleep(10);
2189
7f821875
JB		 2190 netif_tx_stop_all_queues(netdev);
2191
9a799d71
AK		 2192 ixgbe_irq_disable(adapter);
2193
021230d4 2194 ixgbe_napi_disable_all(adapter);
7f821875 2195
9a799d71 2196 del_timer_sync(&adapter->watchdog_timer);
cf8280ee 2197 cancel_work_sync(&adapter->watchdog_task);
9a799d71 2198
7f821875
JB		 2199 /* disable transmits in the hardware now that interrupts are off */
2200 for (i = 0; i < adapter->num_tx_queues; i++) {
2201 j = adapter->tx_ring[i].reg_idx;
2202 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2203 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
2204 (txdctl & ~IXGBE_TXDCTL_ENABLE));
2205 }
2206
9a799d71 2207 netif_carrier_off(netdev);
9a799d71 2208
a1f96ee7 2209#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
96b0e0f6
JB		 2210 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2211 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
2212 dca_remove_requester(&adapter->pdev->dev);
2213 }
2214
2215#endif
6f4a0e45
PL		 2216 if (!pci_channel_offline(adapter->pdev))
2217 ixgbe_reset(adapter);
9a799d71
AK		 2218 ixgbe_clean_all_tx_rings(adapter);
2219 ixgbe_clean_all_rx_rings(adapter);
2220
a1f96ee7 2221#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
96b0e0f6
JB		 2222 /* since we reset the hardware DCA settings were cleared */
2223 if (dca_add_requester(&adapter->pdev->dev) == 0) {
2224 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
2225 /* always use CB2 mode, difference is masked
2226 * in the CB driver */
b4617240 2227 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
96b0e0f6
JB		 2228 ixgbe_setup_dca(adapter);
2229 }
2230#endif
9a799d71
AK		 2231}
2232
2233static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
2234{
2235 struct net_device *netdev = pci_get_drvdata(pdev);
2236 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2237#ifdef CONFIG_PM
2238 int retval = 0;
2239#endif
2240
2241 netif_device_detach(netdev);
2242
2243 if (netif_running(netdev)) {
2244 ixgbe_down(adapter);
2245 ixgbe_free_irq(adapter);
2246 }
2247
2248#ifdef CONFIG_PM
2249 retval = pci_save_state(pdev);
2250 if (retval)
2251 return retval;
2252#endif
2253
2254 pci_enable_wake(pdev, PCI_D3hot, 0);
2255 pci_enable_wake(pdev, PCI_D3cold, 0);
2256
5eba3699
AV		 2257 ixgbe_release_hw_control(adapter);
2258
9a799d71
AK		 2259 pci_disable_device(pdev);
2260
2261 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2262
2263 return 0;
2264}
2265
2266static void ixgbe_shutdown(struct pci_dev *pdev)
2267{
2268 ixgbe_suspend(pdev, PMSG_SUSPEND);
2269}
2270
2271/**
021230d4
AV		 2272 * ixgbe_poll - NAPI Rx polling callback
2273 * @napi: structure for representing this polling device
2274 * @budget: how many packets driver is allowed to clean
2275 *
2276 * This function is used for legacy and MSI, NAPI mode
9a799d71 2277 **/
021230d4 2278static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 2279{
021230d4 2280 struct ixgbe_q_vector *q_vector = container_of(napi,
b4617240 2281 struct ixgbe_q_vector, napi);
021230d4 2282 struct ixgbe_adapter *adapter = q_vector->adapter;
74ce8dd2 2283 int tx_cleaned, work_done = 0;
9a799d71 2284
a1f96ee7 2285#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
bd0362dd
JC		 2286 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2287 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
2288 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
2289 }
2290#endif
2291
d2c7ddd6 2292 tx_cleaned = ixgbe_clean_tx_irq(adapter, adapter->tx_ring);
021230d4 2293 ixgbe_clean_rx_irq(adapter, adapter->rx_ring, &work_done, budget);
9a799d71 2294
d2c7ddd6
DM		 2295 if (tx_cleaned)
2296 work_done = budget;
2297
53e52c72
DM		 2298 /* If budget not fully consumed, exit the polling mode */
2299 if (work_done < budget) {
021230d4 2300 netif_rx_complete(adapter->netdev, napi);
30efa5a3 2301 if (adapter->itr_setting & 3)
f494e8fa 2302 ixgbe_set_itr(adapter);
d4f80882
AV		 2303 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2304 ixgbe_irq_enable(adapter);
9a799d71 2305 }
9a799d71
AK		 2306 return work_done;
2307}
2308
2309/**
2310 * ixgbe_tx_timeout - Respond to a Tx Hang
2311 * @netdev: network interface device structure
2312 **/
2313static void ixgbe_tx_timeout(struct net_device *netdev)
2314{
2315 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2316
2317 /* Do the reset outside of interrupt context */
2318 schedule_work(&adapter->reset_task);
2319}
2320
2321static void ixgbe_reset_task(struct work_struct *work)
2322{
2323 struct ixgbe_adapter *adapter;
2324 adapter = container_of(work, struct ixgbe_adapter, reset_task);
2325
2326 adapter->tx_timeout_count++;
2327
d4f80882 2328 ixgbe_reinit_locked(adapter);
9a799d71
AK		 2329}
2330
b9804972
JB		 2331static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
2332{
2333 int nrq = 1, ntq = 1;
2334 int feature_mask = 0, rss_i, rss_m;
2335
2336 /* Number of supported queues */
2337 switch (adapter->hw.mac.type) {
2338 case ixgbe_mac_82598EB:
2339 rss_i = adapter->ring_feature[RING_F_RSS].indices;
2340 rss_m = 0;
2341 feature_mask |= IXGBE_FLAG_RSS_ENABLED;
2342
2343 switch (adapter->flags & feature_mask) {
2344 case (IXGBE_FLAG_RSS_ENABLED):
2345 rss_m = 0xF;
2346 nrq = rss_i;
2347 ntq = rss_i;
2348 break;
2349 case 0:
2350 default:
2351 rss_i = 0;
2352 rss_m = 0;
2353 nrq = 1;
2354 ntq = 1;
2355 break;
2356 }
2357
2358 adapter->ring_feature[RING_F_RSS].indices = rss_i;
2359 adapter->ring_feature[RING_F_RSS].mask = rss_m;
2360 break;
2361 default:
2362 nrq = 1;
2363 ntq = 1;
2364 break;
2365 }
2366
2367 adapter->num_rx_queues = nrq;
2368 adapter->num_tx_queues = ntq;
2369}
2370
021230d4 2371static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
b4617240 2372 int vectors)
021230d4
AV		 2373{
2374 int err, vector_threshold;
2375
2376 /* We'll want at least 3 (vector_threshold):
2377 * 1) TxQ[0] Cleanup
2378 * 2) RxQ[0] Cleanup
2379 * 3) Other (Link Status Change, etc.)
2380 * 4) TCP Timer (optional)
2381 */
2382 vector_threshold = MIN_MSIX_COUNT;
2383
2384 /* The more we get, the more we will assign to Tx/Rx Cleanup
2385 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
2386 * Right now, we simply care about how many we'll get; we'll
2387 * set them up later while requesting irq's.
2388 */
2389 while (vectors >= vector_threshold) {
2390 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
b4617240 2391 vectors);
021230d4
AV		 2392 if (!err) /* Success in acquiring all requested vectors. */
2393 break;
2394 else if (err < 0)
2395 vectors = 0; /* Nasty failure, quit now */
2396 else /* err == number of vectors we should try again with */
2397 vectors = err;
2398 }
2399
2400 if (vectors < vector_threshold) {
2401 /* Can't allocate enough MSI-X interrupts? Oh well.
2402 * This just means we'll go with either a single MSI
2403 * vector or fall back to legacy interrupts.
2404 */
2405 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
2406 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2407 kfree(adapter->msix_entries);
2408 adapter->msix_entries = NULL;
2409 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
b9804972 2410 ixgbe_set_num_queues(adapter);
021230d4
AV		 2411 } else {
2412 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
2413 adapter->num_msix_vectors = vectors;
2414 }
2415}
2416
021230d4
AV		 2417/**
2418 * ixgbe_cache_ring_register - Descriptor ring to register mapping
2419 * @adapter: board private structure to initialize
2420 *
2421 * Once we know the feature-set enabled for the device, we'll cache
2422 * the register offset the descriptor ring is assigned to.
2423 **/
2424static void __devinit ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
2425{
021230d4
AV		 2426 int feature_mask = 0, rss_i;
2427 int i, txr_idx, rxr_idx;
2428
2429 /* Number of supported queues */
2430 switch (adapter->hw.mac.type) {
2431 case ixgbe_mac_82598EB:
2432 rss_i = adapter->ring_feature[RING_F_RSS].indices;
2433 txr_idx = 0;
2434 rxr_idx = 0;
2435 feature_mask |= IXGBE_FLAG_RSS_ENABLED;
2436 switch (adapter->flags & feature_mask) {
2437 case (IXGBE_FLAG_RSS_ENABLED):
2438 for (i = 0; i < adapter->num_rx_queues; i++)
2439 adapter->rx_ring[i].reg_idx = i;
2440 for (i = 0; i < adapter->num_tx_queues; i++)
2441 adapter->tx_ring[i].reg_idx = i;
2442 break;
2443 case 0:
2444 default:
2445 break;
2446 }
2447 break;
2448 default:
2449 break;
2450 }
2451}
2452
9a799d71
AK		 2453/**
2454 * ixgbe_alloc_queues - Allocate memory for all rings
2455 * @adapter: board private structure to initialize
2456 *
2457 * We allocate one ring per queue at run-time since we don't know the
2458 * number of queues at compile-time. The polling_netdev array is
2459 * intended for Multiqueue, but should work fine with a single queue.
2460 **/
2461static int __devinit ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
2462{
2463 int i;
2464
2465 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
b4617240 2466 sizeof(struct ixgbe_ring), GFP_KERNEL);
9a799d71 2467 if (!adapter->tx_ring)
021230d4 2468 goto err_tx_ring_allocation;
9a799d71
AK		 2469
2470 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
b4617240 2471 sizeof(struct ixgbe_ring), GFP_KERNEL);
021230d4
AV		 2472 if (!adapter->rx_ring)
2473 goto err_rx_ring_allocation;
9a799d71 2474
021230d4 2475 for (i = 0; i < adapter->num_tx_queues; i++) {
b9804972 2476 adapter->tx_ring[i].count = adapter->tx_ring_count;
021230d4
AV		 2477 adapter->tx_ring[i].queue_index = i;
2478 }
b9804972 2479
9a799d71 2480 for (i = 0; i < adapter->num_rx_queues; i++) {
b9804972 2481 adapter->rx_ring[i].count = adapter->rx_ring_count;
021230d4
AV		 2482 adapter->rx_ring[i].queue_index = i;
2483 }
2484
2485 ixgbe_cache_ring_register(adapter);
2486
2487 return 0;
2488
2489err_rx_ring_allocation:
2490 kfree(adapter->tx_ring);
2491err_tx_ring_allocation:
2492 return -ENOMEM;
2493}
2494
2495/**
2496 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
2497 * @adapter: board private structure to initialize
2498 *
2499 * Attempt to configure the interrupts using the best available
2500 * capabilities of the hardware and the kernel.
2501 **/
2502static int __devinit ixgbe_set_interrupt_capability(struct ixgbe_adapter
b4617240 2503 *adapter)
021230d4
AV		 2504{
2505 int err = 0;
2506 int vector, v_budget;
2507
2508 /*
2509 * It's easy to be greedy for MSI-X vectors, but it really
2510 * doesn't do us much good if we have a lot more vectors
2511 * than CPU's. So let's be conservative and only ask for
2512 * (roughly) twice the number of vectors as there are CPU's.
2513 */
2514 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
b4617240 2515 (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
021230d4
AV		 2516
2517 /*
2518 * At the same time, hardware can only support a maximum of
2519 * MAX_MSIX_COUNT vectors. With features such as RSS and VMDq,
2520 * we can easily reach upwards of 64 Rx descriptor queues and
2521 * 32 Tx queues. Thus, we cap it off in those rare cases where
2522 * the cpu count also exceeds our vector limit.
2523 */
2524 v_budget = min(v_budget, MAX_MSIX_COUNT);
2525
2526 /* A failure in MSI-X entry allocation isn't fatal, but it does
2527 * mean we disable MSI-X capabilities of the adapter. */
2528 adapter->msix_entries = kcalloc(v_budget,
b4617240 2529 sizeof(struct msix_entry), GFP_KERNEL);
021230d4
AV		 2530 if (!adapter->msix_entries) {
2531 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
2532 ixgbe_set_num_queues(adapter);
2533 kfree(adapter->tx_ring);
2534 kfree(adapter->rx_ring);
2535 err = ixgbe_alloc_queues(adapter);
2536 if (err) {
2537 DPRINTK(PROBE, ERR, "Unable to allocate memory "
b4617240 2538 "for queues\n");
021230d4
AV		 2539 goto out;
2540 }
2541
2542 goto try_msi;
2543 }
2544
2545 for (vector = 0; vector < v_budget; vector++)
2546 adapter->msix_entries[vector].entry = vector;
2547
2548 ixgbe_acquire_msix_vectors(adapter, v_budget);
2549
2550 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2551 goto out;
2552
2553try_msi:
2554 err = pci_enable_msi(adapter->pdev);
2555 if (!err) {
2556 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
2557 } else {
2558 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
b4617240 2559 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 2560 /* reset err */
2561 err = 0;
2562 }
2563
2564out:
30eba97a 2565 /* Notify the stack of the (possibly) reduced Tx Queue count. */
fd2ea0a7 2566 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
021230d4
AV		 2567
2568 return err;
2569}
2570
2571static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
2572{
2573 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2574 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2575 pci_disable_msix(adapter->pdev);
2576 kfree(adapter->msix_entries);
2577 adapter->msix_entries = NULL;
2578 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2579 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
2580 pci_disable_msi(adapter->pdev);
2581 }
2582 return;
2583}
2584
2585/**
2586 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
2587 * @adapter: board private structure to initialize
2588 *
2589 * We determine which interrupt scheme to use based on...
2590 * - Kernel support (MSI, MSI-X)
2591 * - which can be user-defined (via MODULE_PARAM)
2592 * - Hardware queue count (num_*_queues)
2593 * - defined by miscellaneous hardware support/features (RSS, etc.)
2594 **/
2595static int __devinit ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
2596{
2597 int err;
2598
2599 /* Number of supported queues */
2600 ixgbe_set_num_queues(adapter);
2601
2602 err = ixgbe_alloc_queues(adapter);
2603 if (err) {
2604 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
2605 goto err_alloc_queues;
2606 }
2607
2608 err = ixgbe_set_interrupt_capability(adapter);
2609 if (err) {
2610 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
2611 goto err_set_interrupt;
9a799d71
AK		 2612 }
2613
021230d4 2614 DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
b4617240
PW		 2615 "Tx Queue count = %u\n",
2616 (adapter->num_rx_queues > 1) ? "Enabled" :
2617 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 2618
2619 set_bit(__IXGBE_DOWN, &adapter->state);
2620
9a799d71 2621 return 0;
021230d4
AV		 2622
2623err_set_interrupt:
2624 kfree(adapter->tx_ring);
2625 kfree(adapter->rx_ring);
2626err_alloc_queues:
2627 return err;
9a799d71
AK		 2628}
2629
2630/**
2631 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
2632 * @adapter: board private structure to initialize
2633 *
2634 * ixgbe_sw_init initializes the Adapter private data structure.
2635 * Fields are initialized based on PCI device information and
2636 * OS network device settings (MTU size).
2637 **/
2638static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
2639{
2640 struct ixgbe_hw *hw = &adapter->hw;
2641 struct pci_dev *pdev = adapter->pdev;
021230d4
AV		 2642 unsigned int rss;
2643
c44ade9e
JB		 2644 /* PCI config space info */
2645
2646 hw->vendor_id = pdev->vendor;
2647 hw->device_id = pdev->device;
2648 hw->revision_id = pdev->revision;
2649 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2650 hw->subsystem_device_id = pdev->subsystem_device;
2651
021230d4
AV		 2652 /* Set capability flags */
2653 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
2654 adapter->ring_feature[RING_F_RSS].indices = rss;
2655 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
9a799d71
AK		 2656
2657 /* default flow control settings */
2b9ade93
JB		 2658 hw->fc.original_type = ixgbe_fc_none;
2659 hw->fc.type = ixgbe_fc_none;
2660 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
2661 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
2662 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
2663 hw->fc.send_xon = true;
9a799d71 2664
021230d4 2665 /* select 10G link by default */
9a799d71 2666 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_10G_LINK_NO_AN;
9a799d71 2667
30efa5a3
JB		 2668 /* enable itr by default in dynamic mode */
2669 adapter->itr_setting = 1;
2670 adapter->eitr_param = 20000;
2671
2672 /* set defaults for eitr in MegaBytes */
2673 adapter->eitr_low = 10;
2674 adapter->eitr_high = 20;
2675
2676 /* set default ring sizes */
2677 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
2678 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
2679
9a799d71 2680 /* initialize eeprom parameters */
c44ade9e 2681 if (ixgbe_init_eeprom_params_generic(hw)) {
9a799d71
AK		 2682 dev_err(&pdev->dev, "EEPROM initialization failed\n");
2683 return -EIO;
2684 }
2685
021230d4 2686 /* enable rx csum by default */
9a799d71
AK		 2687 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
2688
9a799d71
AK		 2689 set_bit(__IXGBE_DOWN, &adapter->state);
2690
2691 return 0;
2692}
2693
2694/**
2695 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
2696 * @adapter: board private structure
3a581073 2697 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 2698 *
2699 * Return 0 on success, negative on failure
2700 **/
2701int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
e01c31a5 2702 struct ixgbe_ring *tx_ring)
9a799d71
AK		 2703{
2704 struct pci_dev *pdev = adapter->pdev;
2705 int size;
2706
3a581073
JB		 2707 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2708 tx_ring->tx_buffer_info = vmalloc(size);
e01c31a5
JB		 2709 if (!tx_ring->tx_buffer_info)
2710 goto err;
3a581073 2711 memset(tx_ring->tx_buffer_info, 0, size);
9a799d71
AK		 2712
2713 /* round up to nearest 4K */
e01c31a5
JB		 2714 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc) +
2715 sizeof(u32);
3a581073 2716 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 2717
3a581073
JB		 2718 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
2719 &tx_ring->dma);
e01c31a5
JB		 2720 if (!tx_ring->desc)
2721 goto err;
9a799d71 2722
3a581073
JB		 2723 tx_ring->next_to_use = 0;
2724 tx_ring->next_to_clean = 0;
2725 tx_ring->work_limit = tx_ring->count;
9a799d71 2726 return 0;
e01c31a5
JB		 2727
2728err:
2729 vfree(tx_ring->tx_buffer_info);
2730 tx_ring->tx_buffer_info = NULL;
2731 DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
2732 "descriptor ring\n");
2733 return -ENOMEM;
9a799d71
AK		 2734}
2735
2736/**
2737 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
2738 * @adapter: board private structure
3a581073 2739 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 2740 *
2741 * Returns 0 on success, negative on failure
2742 **/
2743int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
b4617240 2744 struct ixgbe_ring *rx_ring)
9a799d71
AK		 2745{
2746 struct pci_dev *pdev = adapter->pdev;
021230d4 2747 int size;
9a799d71 2748
177db6ff 2749 size = sizeof(struct net_lro_desc) * IXGBE_MAX_LRO_DESCRIPTORS;
3a581073
JB		 2750 rx_ring->lro_mgr.lro_arr = vmalloc(size);
2751 if (!rx_ring->lro_mgr.lro_arr)
177db6ff 2752 return -ENOMEM;
3a581073 2753 memset(rx_ring->lro_mgr.lro_arr, 0, size);
177db6ff 2754
3a581073
JB		 2755 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2756 rx_ring->rx_buffer_info = vmalloc(size);
2757 if (!rx_ring->rx_buffer_info) {
9a799d71 2758 DPRINTK(PROBE, ERR,
b4617240 2759 "vmalloc allocation failed for the rx desc ring\n");
177db6ff 2760 goto alloc_failed;
9a799d71 2761 }
3a581073 2762 memset(rx_ring->rx_buffer_info, 0, size);
9a799d71 2763
9a799d71 2764 /* Round up to nearest 4K */
3a581073
JB		 2765 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
2766 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 2767
3a581073 2768 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
9a799d71 2769
3a581073 2770 if (!rx_ring->desc) {
9a799d71 2771 DPRINTK(PROBE, ERR,
b4617240 2772 "Memory allocation failed for the rx desc ring\n");
3a581073 2773 vfree(rx_ring->rx_buffer_info);
177db6ff 2774 goto alloc_failed;
9a799d71
AK		 2775 }
2776
3a581073
JB		 2777 rx_ring->next_to_clean = 0;
2778 rx_ring->next_to_use = 0;
9a799d71
AK		 2779
2780 return 0;
177db6ff
MC		 2781
2782alloc_failed:
3a581073
JB		 2783 vfree(rx_ring->lro_mgr.lro_arr);
2784 rx_ring->lro_mgr.lro_arr = NULL;
177db6ff 2785 return -ENOMEM;
9a799d71
AK		 2786}
2787
2788/**
2789 * ixgbe_free_tx_resources - Free Tx Resources per Queue
2790 * @adapter: board private structure
2791 * @tx_ring: Tx descriptor ring for a specific queue
2792 *
2793 * Free all transmit software resources
2794 **/
c431f97e
JB		 2795void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
2796 struct ixgbe_ring *tx_ring)
9a799d71
AK		 2797{
2798 struct pci_dev *pdev = adapter->pdev;
2799
2800 ixgbe_clean_tx_ring(adapter, tx_ring);
2801
2802 vfree(tx_ring->tx_buffer_info);
2803 tx_ring->tx_buffer_info = NULL;
2804
2805 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
2806
2807 tx_ring->desc = NULL;
2808}
2809
2810/**
2811 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
2812 * @adapter: board private structure
2813 *
2814 * Free all transmit software resources
2815 **/
2816static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
2817{
2818 int i;
2819
2820 for (i = 0; i < adapter->num_tx_queues; i++)
2821 ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
2822}
2823
2824/**
b4617240 2825 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 2826 * @adapter: board private structure
2827 * @rx_ring: ring to clean the resources from
2828 *
2829 * Free all receive software resources
2830 **/
c431f97e
JB		 2831void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
2832 struct ixgbe_ring *rx_ring)
9a799d71
AK		 2833{
2834 struct pci_dev *pdev = adapter->pdev;
2835
177db6ff
MC		 2836 vfree(rx_ring->lro_mgr.lro_arr);
2837 rx_ring->lro_mgr.lro_arr = NULL;
2838
9a799d71
AK		 2839 ixgbe_clean_rx_ring(adapter, rx_ring);
2840
2841 vfree(rx_ring->rx_buffer_info);
2842 rx_ring->rx_buffer_info = NULL;
2843
2844 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2845
2846 rx_ring->desc = NULL;
2847}
2848
2849/**
2850 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
2851 * @adapter: board private structure
2852 *
2853 * Free all receive software resources
2854 **/
2855static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
2856{
2857 int i;
2858
2859 for (i = 0; i < adapter->num_rx_queues; i++)
2860 ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
2861}
2862
2863/**
021230d4 2864 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
9a799d71
AK		 2865 * @adapter: board private structure
2866 *
2867 * If this function returns with an error, then it's possible one or
2868 * more of the rings is populated (while the rest are not). It is the
2869 * callers duty to clean those orphaned rings.
2870 *
2871 * Return 0 on success, negative on failure
2872 **/
2873static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
2874{
2875 int i, err = 0;
2876
2877 for (i = 0; i < adapter->num_tx_queues; i++) {
2878 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
b4617240
PW		 2879 if (!err)
2880 continue;
2881 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
2882 break;
9a799d71
AK		 2883 }
2884
2885 return err;
2886}
2887
2888/**
021230d4 2889 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
9a799d71
AK		 2890 * @adapter: board private structure
2891 *
2892 * If this function returns with an error, then it's possible one or
2893 * more of the rings is populated (while the rest are not). It is the
2894 * callers duty to clean those orphaned rings.
2895 *
2896 * Return 0 on success, negative on failure
2897 **/
2898
2899static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
2900{
2901 int i, err = 0;
2902
2903 for (i = 0; i < adapter->num_rx_queues; i++) {
2904 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
b4617240
PW		 2905 if (!err)
2906 continue;
2907 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
2908 break;
9a799d71
AK		 2909 }
2910
2911 return err;
2912}
2913
2914/**
2915 * ixgbe_change_mtu - Change the Maximum Transfer Unit
2916 * @netdev: network interface device structure
2917 * @new_mtu: new value for maximum frame size
2918 *
2919 * Returns 0 on success, negative on failure
2920 **/
2921static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
2922{
2923 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2924 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
2925
42c783c5
JB		 2926 /* MTU < 68 is an error and causes problems on some kernels */
2927 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
9a799d71
AK		 2928 return -EINVAL;
2929
021230d4 2930 DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
b4617240 2931 netdev->mtu, new_mtu);
021230d4 2932 /* must set new MTU before calling down or up */
9a799d71
AK		 2933 netdev->mtu = new_mtu;
2934
d4f80882
AV		 2935 if (netif_running(netdev))
2936 ixgbe_reinit_locked(adapter);
9a799d71
AK		 2937
2938 return 0;
2939}
2940
2941/**
2942 * ixgbe_open - Called when a network interface is made active
2943 * @netdev: network interface device structure
2944 *
2945 * Returns 0 on success, negative value on failure
2946 *
2947 * The open entry point is called when a network interface is made
2948 * active by the system (IFF_UP). At this point all resources needed
2949 * for transmit and receive operations are allocated, the interrupt
2950 * handler is registered with the OS, the watchdog timer is started,
2951 * and the stack is notified that the interface is ready.
2952 **/
2953static int ixgbe_open(struct net_device *netdev)
2954{
2955 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2956 int err;
4bebfaa5
AK		 2957
2958 /* disallow open during test */
2959 if (test_bit(__IXGBE_TESTING, &adapter->state))
2960 return -EBUSY;
9a799d71 2961
9a799d71
AK		 2962 /* allocate transmit descriptors */
2963 err = ixgbe_setup_all_tx_resources(adapter);
2964 if (err)
2965 goto err_setup_tx;
2966
9a799d71
AK		 2967 /* allocate receive descriptors */
2968 err = ixgbe_setup_all_rx_resources(adapter);
2969 if (err)
2970 goto err_setup_rx;
2971
2972 ixgbe_configure(adapter);
2973
021230d4 2974 err = ixgbe_request_irq(adapter);
9a799d71
AK		 2975 if (err)
2976 goto err_req_irq;
2977
9a799d71
AK		 2978 err = ixgbe_up_complete(adapter);
2979 if (err)
2980 goto err_up;
2981
d55b53ff
JK		 2982 netif_tx_start_all_queues(netdev);
2983
9a799d71
AK		 2984 return 0;
2985
2986err_up:
5eba3699 2987 ixgbe_release_hw_control(adapter);
9a799d71
AK		 2988 ixgbe_free_irq(adapter);
2989err_req_irq:
2990 ixgbe_free_all_rx_resources(adapter);
2991err_setup_rx:
2992 ixgbe_free_all_tx_resources(adapter);
2993err_setup_tx:
2994 ixgbe_reset(adapter);
2995
2996 return err;
2997}
2998
2999/**
3000 * ixgbe_close - Disables a network interface
3001 * @netdev: network interface device structure
3002 *
3003 * Returns 0, this is not allowed to fail
3004 *
3005 * The close entry point is called when an interface is de-activated
3006 * by the OS. The hardware is still under the drivers control, but
3007 * needs to be disabled. A global MAC reset is issued to stop the
3008 * hardware, and all transmit and receive resources are freed.
3009 **/
3010static int ixgbe_close(struct net_device *netdev)
3011{
3012 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 3013
3014 ixgbe_down(adapter);
3015 ixgbe_free_irq(adapter);
3016
3017 ixgbe_free_all_tx_resources(adapter);
3018 ixgbe_free_all_rx_resources(adapter);
3019
5eba3699 3020 ixgbe_release_hw_control(adapter);
9a799d71
AK		 3021
3022 return 0;
3023}
3024
3025/**
3026 * ixgbe_update_stats - Update the board statistics counters.
3027 * @adapter: board private structure
3028 **/
3029void ixgbe_update_stats(struct ixgbe_adapter *adapter)
3030{
3031 struct ixgbe_hw *hw = &adapter->hw;
6f11eef7
AV		 3032 u64 total_mpc = 0;
3033 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
9a799d71
AK		 3034
3035 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 3036 for (i = 0; i < 8; i++) {
3037 /* for packet buffers not used, the register should read 0 */
3038 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3039 missed_rx += mpc;
3040 adapter->stats.mpc[i] += mpc;
3041 total_mpc += adapter->stats.mpc[i];
3042 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3043 }
3044 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
3045 /* work around hardware counting issue */
3046 adapter->stats.gprc -= missed_rx;
3047
3048 /* 82598 hardware only has a 32 bit counter in the high register */
9a799d71 3049 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
6f11eef7
AV		 3050 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3051 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
9a799d71
AK		 3052 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3053 adapter->stats.bprc += bprc;
3054 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3055 adapter->stats.mprc -= bprc;
3056 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3057 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3058 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3059 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3060 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3061 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3062 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
9a799d71
AK		 3063 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3064 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
9a799d71 3065 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
6f11eef7
AV		 3066 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3067 adapter->stats.lxontxc += lxon;
3068 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3069 adapter->stats.lxofftxc += lxoff;
9a799d71
AK		 3070 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3071 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6f11eef7
AV		 3072 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3073 /*
3074 * 82598 errata - tx of flow control packets is included in tx counters
3075 */
3076 xon_off_tot = lxon + lxoff;
3077 adapter->stats.gptc -= xon_off_tot;
3078 adapter->stats.mptc -= xon_off_tot;
3079 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
9a799d71
AK		 3080 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3081 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3082 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
9a799d71
AK		 3083 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3084 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6f11eef7 3085 adapter->stats.ptc64 -= xon_off_tot;
9a799d71
AK		 3086 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3087 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3088 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3089 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3090 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
9a799d71
AK		 3091 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3092
3093 /* Fill out the OS statistics structure */
9a799d71
AK		 3094 adapter->net_stats.multicast = adapter->stats.mprc;
3095
3096 /* Rx Errors */
3097 adapter->net_stats.rx_errors = adapter->stats.crcerrs +
b4617240 3098 adapter->stats.rlec;
9a799d71
AK		 3099 adapter->net_stats.rx_dropped = 0;
3100 adapter->net_stats.rx_length_errors = adapter->stats.rlec;
3101 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
6f11eef7 3102 adapter->net_stats.rx_missed_errors = total_mpc;
9a799d71
AK		 3103}
3104
3105/**
3106 * ixgbe_watchdog - Timer Call-back
3107 * @data: pointer to adapter cast into an unsigned long
3108 **/
3109static void ixgbe_watchdog(unsigned long data)
3110{
3111 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
cf8280ee
JB		 3112 struct ixgbe_hw *hw = &adapter->hw;
3113
3114 /* Do the watchdog outside of interrupt context due to the lovely
3115 * delays that some of the newer hardware requires */
3116 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
3117 /* Cause software interrupt to ensure rx rings are cleaned */
3118 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3119 u32 eics =
3120 (1 << (adapter->num_msix_vectors - NON_Q_VECTORS)) - 1;
3121 IXGBE_WRITE_REG(hw, IXGBE_EICS, eics);
3122 } else {
3123 /* For legacy and MSI interrupts don't set any bits that
3124 * are enabled for EIAM, because this operation would
3125 * set *both* EIMS and EICS for any bit in EIAM */
3126 IXGBE_WRITE_REG(hw, IXGBE_EICS,
3127 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
3128 }
3129 /* Reset the timer */
3130 mod_timer(&adapter->watchdog_timer,
3131 round_jiffies(jiffies + 2 * HZ));
3132 }
9a799d71 3133
cf8280ee
JB		 3134 schedule_work(&adapter->watchdog_task);
3135}
3136
3137/**
3138 * ixgbe_watchdog_task - worker thread to bring link up
3139 * @work: pointer to work_struct containing our data
3140 **/
3141static void ixgbe_watchdog_task(struct work_struct *work)
3142{
3143 struct ixgbe_adapter *adapter = container_of(work,
3144 struct ixgbe_adapter,
3145 watchdog_task);
3146 struct net_device *netdev = adapter->netdev;
3147 struct ixgbe_hw *hw = &adapter->hw;
3148 u32 link_speed = adapter->link_speed;
3149 bool link_up = adapter->link_up;
3150
3151 adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
3152
3153 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3154 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
3155 if (link_up ||
3156 time_after(jiffies, (adapter->link_check_timeout +
3157 IXGBE_TRY_LINK_TIMEOUT))) {
3158 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
3159 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3160 }
3161 adapter->link_up = link_up;
3162 adapter->link_speed = link_speed;
3163 }
9a799d71
AK		 3164
3165 if (link_up) {
3166 if (!netif_carrier_ok(netdev)) {
cf8280ee
JB		 3167 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3168 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
9a799d71
AK		 3169#define FLOW_RX (frctl & IXGBE_FCTRL_RFCE)
3170#define FLOW_TX (rmcs & IXGBE_RMCS_TFCE_802_3X)
3171 DPRINTK(LINK, INFO, "NIC Link is Up %s, "
cf8280ee
JB		 3172 "Flow Control: %s\n",
3173 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
3174 "10 Gbps" :
3175 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
3176 "1 Gbps" : "unknown speed")),
3177 ((FLOW_RX && FLOW_TX) ? "RX/TX" :
3178 (FLOW_RX ? "RX" :
3179 (FLOW_TX ? "TX" : "None"))));
9a799d71
AK		 3180
3181 netif_carrier_on(netdev);
fd2ea0a7 3182 netif_tx_wake_all_queues(netdev);
9a799d71
AK		 3183 } else {
3184 /* Force detection of hung controller */
3185 adapter->detect_tx_hung = true;
3186 }
3187 } else {
cf8280ee
JB		 3188 adapter->link_up = false;
3189 adapter->link_speed = 0;
9a799d71
AK		 3190 if (netif_carrier_ok(netdev)) {
3191 DPRINTK(LINK, INFO, "NIC Link is Down\n");
3192 netif_carrier_off(netdev);
fd2ea0a7 3193 netif_tx_stop_all_queues(netdev);
9a799d71
AK		 3194 }
3195 }
3196
3197 ixgbe_update_stats(adapter);
cf8280ee 3198 adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
9a799d71
AK		 3199}
3200
9a799d71 3201static int ixgbe_tso(struct ixgbe_adapter *adapter,
b4617240
PW		 3202 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
3203 u32 tx_flags, u8 *hdr_len)
9a799d71
AK		 3204{
3205 struct ixgbe_adv_tx_context_desc *context_desc;
3206 unsigned int i;
3207 int err;
3208 struct ixgbe_tx_buffer *tx_buffer_info;
9f8cdf4f
JB		 3209 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
3210 u32 mss_l4len_idx, l4len;
9a799d71
AK		 3211
3212 if (skb_is_gso(skb)) {
3213 if (skb_header_cloned(skb)) {
3214 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
3215 if (err)
3216 return err;
3217 }
3218 l4len = tcp_hdrlen(skb);
3219 *hdr_len += l4len;
3220
8327d000 3221 if (skb->protocol == htons(ETH_P_IP)) {
9a799d71
AK		 3222 struct iphdr *iph = ip_hdr(skb);
3223 iph->tot_len = 0;
3224 iph->check = 0;
3225 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b4617240
PW		 3226 iph->daddr, 0,
3227 IPPROTO_TCP,
3228 0);
9a799d71
AK		 3229 adapter->hw_tso_ctxt++;
3230 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
3231 ipv6_hdr(skb)->payload_len = 0;
3232 tcp_hdr(skb)->check =
3233 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
b4617240
PW		 3234 &ipv6_hdr(skb)->daddr,
3235 0, IPPROTO_TCP, 0);
9a799d71
AK		 3236 adapter->hw_tso6_ctxt++;
3237 }
3238
3239 i = tx_ring->next_to_use;
3240
3241 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3242 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
3243
3244 /* VLAN MACLEN IPLEN */
3245 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
3246 vlan_macip_lens |=
3247 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
3248 vlan_macip_lens |= ((skb_network_offset(skb)) <<
b4617240 3249 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 3250 *hdr_len += skb_network_offset(skb);
3251 vlan_macip_lens |=
3252 (skb_transport_header(skb) - skb_network_header(skb));
3253 *hdr_len +=
3254 (skb_transport_header(skb) - skb_network_header(skb));
3255 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
3256 context_desc->seqnum_seed = 0;
3257
3258 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
9f8cdf4f 3259 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
b4617240 3260 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 3261
8327d000 3262 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 3263 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
3264 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
3265 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
3266
3267 /* MSS L4LEN IDX */
9f8cdf4f 3268 mss_l4len_idx =
9a799d71
AK		 3269 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
3270 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4eeae6fd
PW		 3271 /* use index 1 for TSO */
3272 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 3273 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
3274
3275 tx_buffer_info->time_stamp = jiffies;
3276 tx_buffer_info->next_to_watch = i;
3277
3278 i++;
3279 if (i == tx_ring->count)
3280 i = 0;
3281 tx_ring->next_to_use = i;
3282
3283 return true;
3284 }
3285 return false;
3286}
3287
3288static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
b4617240
PW		 3289 struct ixgbe_ring *tx_ring,
3290 struct sk_buff *skb, u32 tx_flags)
9a799d71
AK		 3291{
3292 struct ixgbe_adv_tx_context_desc *context_desc;
3293 unsigned int i;
3294 struct ixgbe_tx_buffer *tx_buffer_info;
3295 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
3296
3297 if (skb->ip_summed == CHECKSUM_PARTIAL ||
3298 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
3299 i = tx_ring->next_to_use;
3300 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3301 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
3302
3303 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
3304 vlan_macip_lens |=
3305 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
3306 vlan_macip_lens |= (skb_network_offset(skb) <<
b4617240 3307 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 3308 if (skb->ip_summed == CHECKSUM_PARTIAL)
3309 vlan_macip_lens |= (skb_transport_header(skb) -
b4617240 3310 skb_network_header(skb));
9a799d71
AK		 3311
3312 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
3313 context_desc->seqnum_seed = 0;
3314
3315 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
b4617240 3316 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71
AK		 3317
3318 if (skb->ip_summed == CHECKSUM_PARTIAL) {
41825d71
AK		 3319 switch (skb->protocol) {
3320 case __constant_htons(ETH_P_IP):
9a799d71 3321 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
41825d71
AK		 3322 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
3323 type_tucmd_mlhl |=
b4617240 3324 IXGBE_ADVTXD_TUCMD_L4T_TCP;
41825d71 3325 break;
41825d71
AK		 3326 case __constant_htons(ETH_P_IPV6):
3327 /* XXX what about other V6 headers?? */
3328 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
3329 type_tucmd_mlhl |=
b4617240 3330 IXGBE_ADVTXD_TUCMD_L4T_TCP;
41825d71 3331 break;
41825d71
AK		 3332 default:
3333 if (unlikely(net_ratelimit())) {
3334 DPRINTK(PROBE, WARNING,
3335 "partial checksum but proto=%x!\n",
3336 skb->protocol);
3337 }
3338 break;
3339 }
9a799d71
AK		 3340 }
3341
3342 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4eeae6fd 3343 /* use index zero for tx checksum offload */
9a799d71
AK		 3344 context_desc->mss_l4len_idx = 0;
3345
3346 tx_buffer_info->time_stamp = jiffies;
3347 tx_buffer_info->next_to_watch = i;
9f8cdf4f 3348
9a799d71
AK		 3349 adapter->hw_csum_tx_good++;
3350 i++;
3351 if (i == tx_ring->count)
3352 i = 0;
3353 tx_ring->next_to_use = i;
3354
3355 return true;
3356 }
9f8cdf4f 3357
9a799d71
AK		 3358 return false;
3359}
3360
3361static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
b4617240
PW		 3362 struct ixgbe_ring *tx_ring,
3363 struct sk_buff *skb, unsigned int first)
9a799d71
AK		 3364{
3365 struct ixgbe_tx_buffer *tx_buffer_info;
3366 unsigned int len = skb->len;
3367 unsigned int offset = 0, size, count = 0, i;
3368 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
3369 unsigned int f;
3370
3371 len -= skb->data_len;
3372
3373 i = tx_ring->next_to_use;
3374
3375 while (len) {
3376 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3377 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
3378
3379 tx_buffer_info->length = size;
3380 tx_buffer_info->dma = pci_map_single(adapter->pdev,
b4617240
PW		 3381 skb->data + offset,
3382 size, PCI_DMA_TODEVICE);
9a799d71
AK		 3383 tx_buffer_info->time_stamp = jiffies;
3384 tx_buffer_info->next_to_watch = i;
3385
3386 len -= size;
3387 offset += size;
3388 count++;
3389 i++;
3390 if (i == tx_ring->count)
3391 i = 0;
3392 }
3393
3394 for (f = 0; f < nr_frags; f++) {
3395 struct skb_frag_struct *frag;
3396
3397 frag = &skb_shinfo(skb)->frags[f];
3398 len = frag->size;
3399 offset = frag->page_offset;
3400
3401 while (len) {
3402 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3403 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
3404
3405 tx_buffer_info->length = size;
3406 tx_buffer_info->dma = pci_map_page(adapter->pdev,
b4617240
PW		 3407 frag->page,
3408 offset,
3409 size,
3410 PCI_DMA_TODEVICE);
9a799d71
AK		 3411 tx_buffer_info->time_stamp = jiffies;
3412 tx_buffer_info->next_to_watch = i;
3413
3414 len -= size;
3415 offset += size;
3416 count++;
3417 i++;
3418 if (i == tx_ring->count)
3419 i = 0;
3420 }
3421 }
3422 if (i == 0)
3423 i = tx_ring->count - 1;
3424 else
3425 i = i - 1;
3426 tx_ring->tx_buffer_info[i].skb = skb;
3427 tx_ring->tx_buffer_info[first].next_to_watch = i;
3428
3429 return count;
3430}
3431
3432static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
b4617240
PW		 3433 struct ixgbe_ring *tx_ring,
3434 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 3435{
3436 union ixgbe_adv_tx_desc *tx_desc = NULL;
3437 struct ixgbe_tx_buffer *tx_buffer_info;
3438 u32 olinfo_status = 0, cmd_type_len = 0;
3439 unsigned int i;
3440 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
3441
3442 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
3443
3444 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
3445
3446 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
3447 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
3448
3449 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
3450 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
3451
3452 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 3453 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 3454
4eeae6fd
PW		 3455 /* use index 1 context for tso */
3456 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 3457 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
3458 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
b4617240 3459 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 3460
3461 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
3462 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 3463 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 3464
3465 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
3466
3467 i = tx_ring->next_to_use;
3468 while (count--) {
3469 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3470 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
3471 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
3472 tx_desc->read.cmd_type_len =
b4617240 3473 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71
AK		 3474 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
3475
3476 i++;
3477 if (i == tx_ring->count)
3478 i = 0;
3479 }
3480
3481 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
3482
3483 /*
3484 * Force memory writes to complete before letting h/w
3485 * know there are new descriptors to fetch. (Only
3486 * applicable for weak-ordered memory model archs,
3487 * such as IA-64).
3488 */
3489 wmb();
3490
3491 tx_ring->next_to_use = i;
3492 writel(i, adapter->hw.hw_addr + tx_ring->tail);
3493}
3494
e092be60 3495static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 3496 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 3497{
3498 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3499
30eba97a 3500 netif_stop_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 3501 /* Herbert's original patch had:
3502 * smp_mb__after_netif_stop_queue();
3503 * but since that doesn't exist yet, just open code it. */
3504 smp_mb();
3505
3506 /* We need to check again in a case another CPU has just
3507 * made room available. */
3508 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
3509 return -EBUSY;
3510
3511 /* A reprieve! - use start_queue because it doesn't call schedule */
af72166f 3512 netif_start_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 3513 ++adapter->restart_queue;
3514 return 0;
3515}
3516
3517static int ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 3518 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 3519{
3520 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
3521 return 0;
3522 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
3523}
3524
3525
9a799d71
AK		 3526static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
3527{
3528 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3529 struct ixgbe_ring *tx_ring;
9a799d71
AK		 3530 unsigned int first;
3531 unsigned int tx_flags = 0;
30eba97a
AV		 3532 u8 hdr_len = 0;
3533 int r_idx = 0, tso;
9a799d71
AK		 3534 int count = 0;
3535 unsigned int f;
9f8cdf4f 3536
30eba97a 3537 r_idx = (adapter->num_tx_queues - 1) & skb->queue_mapping;
30eba97a 3538 tx_ring = &adapter->tx_ring[r_idx];
9a799d71 3539
9f8cdf4f
JB		 3540 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
3541 tx_flags |= vlan_tx_tag_get(skb);
3542 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
3543 tx_flags |= IXGBE_TX_FLAGS_VLAN;
9a799d71 3544 }
9f8cdf4f
JB		 3545 /* three things can cause us to need a context descriptor */
3546 if (skb_is_gso(skb) ||
3547 (skb->ip_summed == CHECKSUM_PARTIAL) ||
3548 (tx_flags & IXGBE_TX_FLAGS_VLAN))
9a799d71
AK		 3549 count++;
3550
9f8cdf4f
JB		 3551 count += TXD_USE_COUNT(skb_headlen(skb));
3552 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
9a799d71
AK		 3553 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
3554
e092be60 3555 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
9a799d71 3556 adapter->tx_busy++;
9a799d71
AK		 3557 return NETDEV_TX_BUSY;
3558 }
9a799d71 3559
8327d000 3560 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 3561 tx_flags |= IXGBE_TX_FLAGS_IPV4;
3562 first = tx_ring->next_to_use;
3563 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
3564 if (tso < 0) {
3565 dev_kfree_skb_any(skb);
3566 return NETDEV_TX_OK;
3567 }
3568
3569 if (tso)
3570 tx_flags |= IXGBE_TX_FLAGS_TSO;
3571 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
b4617240 3572 (skb->ip_summed == CHECKSUM_PARTIAL))
9a799d71
AK		 3573 tx_flags |= IXGBE_TX_FLAGS_CSUM;
3574
3575 ixgbe_tx_queue(adapter, tx_ring, tx_flags,
b4617240
PW		 3576 ixgbe_tx_map(adapter, tx_ring, skb, first),
3577 skb->len, hdr_len);
9a799d71
AK		 3578
3579 netdev->trans_start = jiffies;
3580
e092be60 3581 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
9a799d71
AK		 3582
3583 return NETDEV_TX_OK;
3584}
3585
3586/**
3587 * ixgbe_get_stats - Get System Network Statistics
3588 * @netdev: network interface device structure
3589 *
3590 * Returns the address of the device statistics structure.
3591 * The statistics are actually updated from the timer callback.
3592 **/
3593static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
3594{
3595 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3596
3597 /* only return the current stats */
3598 return &adapter->net_stats;
3599}
3600
3601/**
3602 * ixgbe_set_mac - Change the Ethernet Address of the NIC
3603 * @netdev: network interface device structure
3604 * @p: pointer to an address structure
3605 *
3606 * Returns 0 on success, negative on failure
3607 **/
3608static int ixgbe_set_mac(struct net_device *netdev, void *p)
3609{
3610 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 3611 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 3612 struct sockaddr *addr = p;
3613
3614 if (!is_valid_ether_addr(addr->sa_data))
3615 return -EADDRNOTAVAIL;
3616
3617 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 3618 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 3619
b4617240 3620 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71
AK		 3621
3622 return 0;
3623}
3624
3625#ifdef CONFIG_NET_POLL_CONTROLLER
3626/*
3627 * Polling 'interrupt' - used by things like netconsole to send skbs
3628 * without having to re-enable interrupts. It's not called while
3629 * the interrupt routine is executing.
3630 */
3631static void ixgbe_netpoll(struct net_device *netdev)
3632{
3633 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3634
3635 disable_irq(adapter->pdev->irq);
3636 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
3637 ixgbe_intr(adapter->pdev->irq, netdev);
3638 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
3639 enable_irq(adapter->pdev->irq);
3640}
3641#endif
3642
c44ade9e
JB		 3643/**
3644 * ixgbe_link_config - set up initial link with default speed and duplex
3645 * @hw: pointer to private hardware struct
3646 *
3647 * Returns 0 on success, negative on failure
3648 **/
3649static int ixgbe_link_config(struct ixgbe_hw *hw)
3650{
3651 u32 autoneg = IXGBE_LINK_SPEED_10GB_FULL;
3652
3653 /* must always autoneg for both 1G and 10G link */
3654 hw->mac.autoneg = true;
3655
3656 return hw->mac.ops.setup_link_speed(hw, autoneg, true, true);
3657}
3658
021230d4
AV		 3659/**
3660 * ixgbe_napi_add_all - prep napi structs for use
3661 * @adapter: private struct
3662 * helper function to napi_add each possible q_vector->napi
3663 */
3664static void ixgbe_napi_add_all(struct ixgbe_adapter *adapter)
3665{
3666 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3667 int (*poll)(struct napi_struct *, int);
3668
3669 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3670 poll = &ixgbe_clean_rxonly;
3671 } else {
3672 poll = &ixgbe_poll;
3673 /* only one q_vector for legacy modes */
3674 q_vectors = 1;
3675 }
3676
3677 for (i = 0; i < q_vectors; i++) {
3678 struct ixgbe_q_vector *q_vector = &adapter->q_vector[i];
3679 netif_napi_add(adapter->netdev, &q_vector->napi,
b4617240 3680 (*poll), 64);
021230d4
AV		 3681 }
3682}
3683
9a799d71
AK		 3684/**
3685 * ixgbe_probe - Device Initialization Routine
3686 * @pdev: PCI device information struct
3687 * @ent: entry in ixgbe_pci_tbl
3688 *
3689 * Returns 0 on success, negative on failure
3690 *
3691 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
3692 * The OS initialization, configuring of the adapter private structure,
3693 * and a hardware reset occur.
3694 **/
3695static int __devinit ixgbe_probe(struct pci_dev *pdev,
b4617240 3696 const struct pci_device_id *ent)
9a799d71
AK		 3697{
3698 struct net_device *netdev;
3699 struct ixgbe_adapter *adapter = NULL;
3700 struct ixgbe_hw *hw;
3701 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 3702 static int cards_found;
3703 int i, err, pci_using_dac;
3704 u16 link_status, link_speed, link_width;
c44ade9e 3705 u32 part_num, eec;
9a799d71
AK		 3706
3707 err = pci_enable_device(pdev);
3708 if (err)
3709 return err;
3710
3711 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK) &&
3712 !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK)) {
3713 pci_using_dac = 1;
3714 } else {
3715 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3716 if (err) {
3717 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3718 if (err) {
b4617240
PW		 3719 dev_err(&pdev->dev, "No usable DMA "
3720 "configuration, aborting\n");
9a799d71
AK		 3721 goto err_dma;
3722 }
3723 }
3724 pci_using_dac = 0;
3725 }
3726
3727 err = pci_request_regions(pdev, ixgbe_driver_name);
3728 if (err) {
3729 dev_err(&pdev->dev, "pci_request_regions failed 0x%x\n", err);
3730 goto err_pci_reg;
3731 }
3732
3733 pci_set_master(pdev);
fb3b27bc 3734 pci_save_state(pdev);
9a799d71 3735
30eba97a 3736 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
9a799d71
AK		 3737 if (!netdev) {
3738 err = -ENOMEM;
3739 goto err_alloc_etherdev;
3740 }
3741
9a799d71
AK		 3742 SET_NETDEV_DEV(netdev, &pdev->dev);
3743
3744 pci_set_drvdata(pdev, netdev);
3745 adapter = netdev_priv(netdev);
3746
3747 adapter->netdev = netdev;
3748 adapter->pdev = pdev;
3749 hw = &adapter->hw;
3750 hw->back = adapter;
3751 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
3752
05857980
JK		 3753 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
3754 pci_resource_len(pdev, 0));
9a799d71
AK		 3755 if (!hw->hw_addr) {
3756 err = -EIO;
3757 goto err_ioremap;
3758 }
3759
3760 for (i = 1; i <= 5; i++) {
3761 if (pci_resource_len(pdev, i) == 0)
3762 continue;
3763 }
3764
3765 netdev->open = &ixgbe_open;
3766 netdev->stop = &ixgbe_close;
3767 netdev->hard_start_xmit = &ixgbe_xmit_frame;
3768 netdev->get_stats = &ixgbe_get_stats;
2c5645cf
CL		 3769 netdev->set_rx_mode = &ixgbe_set_rx_mode;
3770 netdev->set_multicast_list = &ixgbe_set_rx_mode;
9a799d71
AK		 3771 netdev->set_mac_address = &ixgbe_set_mac;
3772 netdev->change_mtu = &ixgbe_change_mtu;
3773 ixgbe_set_ethtool_ops(netdev);
3774 netdev->tx_timeout = &ixgbe_tx_timeout;
3775 netdev->watchdog_timeo = 5 * HZ;
9a799d71
AK		 3776 netdev->vlan_rx_register = ixgbe_vlan_rx_register;
3777 netdev->vlan_rx_add_vid = ixgbe_vlan_rx_add_vid;
3778 netdev->vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid;
3779#ifdef CONFIG_NET_POLL_CONTROLLER
3780 netdev->poll_controller = ixgbe_netpoll;
3781#endif
3782 strcpy(netdev->name, pci_name(pdev));
3783
9a799d71
AK		 3784 adapter->bd_number = cards_found;
3785
9a799d71
AK		 3786 /* Setup hw api */
3787 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 3788 hw->mac.type = ii->mac;
9a799d71 3789
c44ade9e
JB		 3790 /* EEPROM */
3791 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
3792 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
3793 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
3794 if (!(eec & (1 << 8)))
3795 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
3796
3797 /* PHY */
3798 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
3799 /* phy->sfp_type = ixgbe_sfp_type_unknown; */
3800
9a799d71
AK		 3801 err = ii->get_invariants(hw);
3802 if (err)
3803 goto err_hw_init;
3804
3805 /* setup the private structure */
3806 err = ixgbe_sw_init(adapter);
3807 if (err)
3808 goto err_sw_init;
3809
c44ade9e
JB		 3810 /* reset_hw fills in the perm_addr as well */
3811 err = hw->mac.ops.reset_hw(hw);
3812 if (err) {
3813 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
3814 goto err_sw_init;
3815 }
3816
9a799d71 3817 netdev->features = NETIF_F_SG |
b4617240
PW		 3818 NETIF_F_IP_CSUM |
3819 NETIF_F_HW_VLAN_TX |
3820 NETIF_F_HW_VLAN_RX |
3821 NETIF_F_HW_VLAN_FILTER;
9a799d71 3822
e9990a9c 3823 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 3824 netdev->features |= NETIF_F_TSO;
9a799d71 3825 netdev->features |= NETIF_F_TSO6;
e9990a9c 3826 netdev->features |= NETIF_F_LRO;
ad31c402
JK		 3827
3828 netdev->vlan_features |= NETIF_F_TSO;
3829 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 3830 netdev->vlan_features |= NETIF_F_IP_CSUM;
ad31c402
JK		 3831 netdev->vlan_features |= NETIF_F_SG;
3832
9a799d71
AK		 3833 if (pci_using_dac)
3834 netdev->features |= NETIF_F_HIGHDMA;
3835
9a799d71 3836 /* make sure the EEPROM is good */
c44ade9e 3837 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
9a799d71
AK		 3838 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
3839 err = -EIO;
3840 goto err_eeprom;
3841 }
3842
3843 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
3844 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
3845
c44ade9e
JB		 3846 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
3847 dev_err(&pdev->dev, "invalid MAC address\n");
9a799d71
AK		 3848 err = -EIO;
3849 goto err_eeprom;
3850 }
3851
3852 init_timer(&adapter->watchdog_timer);
3853 adapter->watchdog_timer.function = &ixgbe_watchdog;
3854 adapter->watchdog_timer.data = (unsigned long)adapter;
3855
3856 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
cf8280ee 3857 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
9a799d71 3858
021230d4
AV		 3859 err = ixgbe_init_interrupt_scheme(adapter);
3860 if (err)
3861 goto err_sw_init;
9a799d71
AK		 3862
3863 /* print bus type/speed/width info */
3864 pci_read_config_word(pdev, IXGBE_PCI_LINK_STATUS, &link_status);
3865 link_speed = link_status & IXGBE_PCI_LINK_SPEED;
3866 link_width = link_status & IXGBE_PCI_LINK_WIDTH;
3867 dev_info(&pdev->dev, "(PCI Express:%s:%s) "
b4617240
PW		 3868 "%02x:%02x:%02x:%02x:%02x:%02x\n",
3869 ((link_speed == IXGBE_PCI_LINK_SPEED_5000) ? "5.0Gb/s" :
3870 (link_speed == IXGBE_PCI_LINK_SPEED_2500) ? "2.5Gb/s" :
3871 "Unknown"),
3872 ((link_width == IXGBE_PCI_LINK_WIDTH_8) ? "Width x8" :
3873 (link_width == IXGBE_PCI_LINK_WIDTH_4) ? "Width x4" :
3874 (link_width == IXGBE_PCI_LINK_WIDTH_2) ? "Width x2" :
3875 (link_width == IXGBE_PCI_LINK_WIDTH_1) ? "Width x1" :
3876 "Unknown"),
3877 netdev->dev_addr[0], netdev->dev_addr[1], netdev->dev_addr[2],
3878 netdev->dev_addr[3], netdev->dev_addr[4], netdev->dev_addr[5]);
c44ade9e 3879 ixgbe_read_pba_num_generic(hw, &part_num);
9a799d71 3880 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
b4617240
PW		 3881 hw->mac.type, hw->phy.type,
3882 (part_num >> 8), (part_num & 0xff));
9a799d71 3883
0c254d86
AK		 3884 if (link_width <= IXGBE_PCI_LINK_WIDTH_4) {
3885 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
b4617240
PW		 3886 "this card is not sufficient for optimal "
3887 "performance.\n");
0c254d86 3888 dev_warn(&pdev->dev, "For optimal performance a x8 "
b4617240 3889 "PCI-Express slot is required.\n");
0c254d86
AK		 3890 }
3891
9a799d71 3892 /* reset the hardware with the new settings */
c44ade9e
JB		 3893 hw->mac.ops.start_hw(hw);
3894
3895 /* link_config depends on start_hw being called at least once */
3896 err = ixgbe_link_config(hw);
3897 if (err) {
3898 dev_err(&pdev->dev, "setup_link_speed FAILED %d\n", err);
3899 goto err_register;
3900 }
9a799d71
AK		 3901
3902 netif_carrier_off(netdev);
fd2ea0a7 3903 netif_tx_stop_all_queues(netdev);
9a799d71 3904
021230d4
AV		 3905 ixgbe_napi_add_all(adapter);
3906
9a799d71
AK		 3907 strcpy(netdev->name, "eth%d");
3908 err = register_netdev(netdev);
3909 if (err)
3910 goto err_register;
3911
a1f96ee7 3912#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
652f093f 3913 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd
JC		 3914 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
3915 /* always use CB2 mode, difference is masked
3916 * in the CB driver */
3917 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
3918 ixgbe_setup_dca(adapter);
3919 }
3920#endif
9a799d71
AK		 3921
3922 dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
3923 cards_found++;
3924 return 0;
3925
3926err_register:
5eba3699 3927 ixgbe_release_hw_control(adapter);
9a799d71
AK		 3928err_hw_init:
3929err_sw_init:
021230d4 3930 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 3931err_eeprom:
3932 iounmap(hw->hw_addr);
3933err_ioremap:
3934 free_netdev(netdev);
3935err_alloc_etherdev:
3936 pci_release_regions(pdev);
3937err_pci_reg:
3938err_dma:
3939 pci_disable_device(pdev);
3940 return err;
3941}
3942
3943/**
3944 * ixgbe_remove - Device Removal Routine
3945 * @pdev: PCI device information struct
3946 *
3947 * ixgbe_remove is called by the PCI subsystem to alert the driver
3948 * that it should release a PCI device. The could be caused by a
3949 * Hot-Plug event, or because the driver is going to be removed from
3950 * memory.
3951 **/
3952static void __devexit ixgbe_remove(struct pci_dev *pdev)
3953{
3954 struct net_device *netdev = pci_get_drvdata(pdev);
3955 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3956
3957 set_bit(__IXGBE_DOWN, &adapter->state);
3958 del_timer_sync(&adapter->watchdog_timer);
3959
3960 flush_scheduled_work();
3961
a1f96ee7 3962#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
bd0362dd
JC		 3963 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
3964 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
3965 dca_remove_requester(&pdev->dev);
3966 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
3967 }
3968
3969#endif
9a799d71
AK		 3970 unregister_netdev(netdev);
3971
021230d4 3972 ixgbe_reset_interrupt_capability(adapter);
5eba3699 3973
021230d4 3974 ixgbe_release_hw_control(adapter);
9a799d71
AK		 3975
3976 iounmap(adapter->hw.hw_addr);
3977 pci_release_regions(pdev);
3978
021230d4
AV		 3979 DPRINTK(PROBE, INFO, "complete\n");
3980 kfree(adapter->tx_ring);
3981 kfree(adapter->rx_ring);
3982
9a799d71
AK		 3983 free_netdev(netdev);
3984
3985 pci_disable_device(pdev);
3986}
3987
3988/**
3989 * ixgbe_io_error_detected - called when PCI error is detected
3990 * @pdev: Pointer to PCI device
3991 * @state: The current pci connection state
3992 *
3993 * This function is called after a PCI bus error affecting
3994 * this device has been detected.
3995 */
3996static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
b4617240 3997 pci_channel_state_t state)
9a799d71
AK		 3998{
3999 struct net_device *netdev = pci_get_drvdata(pdev);
4000 struct ixgbe_adapter *adapter = netdev->priv;
4001
4002 netif_device_detach(netdev);
4003
4004 if (netif_running(netdev))
4005 ixgbe_down(adapter);
4006 pci_disable_device(pdev);
4007
b4617240 4008 /* Request a slot reset. */
9a799d71
AK		 4009 return PCI_ERS_RESULT_NEED_RESET;
4010}
4011
4012/**
4013 * ixgbe_io_slot_reset - called after the pci bus has been reset.
4014 * @pdev: Pointer to PCI device
4015 *
4016 * Restart the card from scratch, as if from a cold-boot.
4017 */
4018static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
4019{
4020 struct net_device *netdev = pci_get_drvdata(pdev);
4021 struct ixgbe_adapter *adapter = netdev->priv;
4022
4023 if (pci_enable_device(pdev)) {
4024 DPRINTK(PROBE, ERR,
b4617240 4025 "Cannot re-enable PCI device after reset.\n");
9a799d71
AK		 4026 return PCI_ERS_RESULT_DISCONNECT;
4027 }
4028 pci_set_master(pdev);
fb3b27bc 4029 pci_restore_state(pdev);
9a799d71
AK		 4030
4031 pci_enable_wake(pdev, PCI_D3hot, 0);
4032 pci_enable_wake(pdev, PCI_D3cold, 0);
4033
4034 ixgbe_reset(adapter);
4035
4036 return PCI_ERS_RESULT_RECOVERED;
4037}
4038
4039/**
4040 * ixgbe_io_resume - called when traffic can start flowing again.
4041 * @pdev: Pointer to PCI device
4042 *
4043 * This callback is called when the error recovery driver tells us that
4044 * its OK to resume normal operation.
4045 */
4046static void ixgbe_io_resume(struct pci_dev *pdev)
4047{
4048 struct net_device *netdev = pci_get_drvdata(pdev);
4049 struct ixgbe_adapter *adapter = netdev->priv;
4050
4051 if (netif_running(netdev)) {
4052 if (ixgbe_up(adapter)) {
4053 DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
4054 return;
4055 }
4056 }
4057
4058 netif_device_attach(netdev);
4059
4060}
4061
4062static struct pci_error_handlers ixgbe_err_handler = {
4063 .error_detected = ixgbe_io_error_detected,
4064 .slot_reset = ixgbe_io_slot_reset,
4065 .resume = ixgbe_io_resume,
4066};
4067
4068static struct pci_driver ixgbe_driver = {
4069 .name = ixgbe_driver_name,
4070 .id_table = ixgbe_pci_tbl,
4071 .probe = ixgbe_probe,
4072 .remove = __devexit_p(ixgbe_remove),
4073#ifdef CONFIG_PM
4074 .suspend = ixgbe_suspend,
4075 .resume = ixgbe_resume,
4076#endif
4077 .shutdown = ixgbe_shutdown,
4078 .err_handler = &ixgbe_err_handler
4079};
4080
4081/**
4082 * ixgbe_init_module - Driver Registration Routine
4083 *
4084 * ixgbe_init_module is the first routine called when the driver is
4085 * loaded. All it does is register with the PCI subsystem.
4086 **/
4087static int __init ixgbe_init_module(void)
4088{
4089 int ret;
4090 printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
4091 ixgbe_driver_string, ixgbe_driver_version);
4092
4093 printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
4094
a1f96ee7 4095#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
bd0362dd
JC		 4096 dca_register_notify(&dca_notifier);
4097
4098#endif
9a799d71
AK		 4099 ret = pci_register_driver(&ixgbe_driver);
4100 return ret;
4101}
b4617240 4102
9a799d71
AK		 4103module_init(ixgbe_init_module);
4104
4105/**
4106 * ixgbe_exit_module - Driver Exit Cleanup Routine
4107 *
4108 * ixgbe_exit_module is called just before the driver is removed
4109 * from memory.
4110 **/
4111static void __exit ixgbe_exit_module(void)
4112{
a1f96ee7 4113#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
bd0362dd
JC		 4114 dca_unregister_notify(&dca_notifier);
4115#endif
9a799d71
AK		 4116 pci_unregister_driver(&ixgbe_driver);
4117}
bd0362dd 4118
a1f96ee7 4119#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
bd0362dd 4120static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
b4617240 4121 void *p)
bd0362dd
JC		 4122{
4123 int ret_val;
4124
4125 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
b4617240 4126 __ixgbe_notify_dca);
bd0362dd
JC		 4127
4128 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
4129}
96b0e0f6 4130#endif /* CONFIG_DCA or CONFIG_DCA_MODULE */
bd0362dd 4131
9a799d71
AK		 4132module_exit(ixgbe_exit_module);
4133
4134/* ixgbe_main.c */
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