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9a799d71 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
3efac5a0 | 4 | Copyright(c) 1999 - 2009 Intel Corporation. |
9a799d71 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
9a799d71 AK |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #include <linux/types.h> | |
29 | #include <linux/module.h> | |
30 | #include <linux/pci.h> | |
31 | #include <linux/netdevice.h> | |
32 | #include <linux/vmalloc.h> | |
33 | #include <linux/string.h> | |
34 | #include <linux/in.h> | |
35 | #include <linux/ip.h> | |
36 | #include <linux/tcp.h> | |
37 | #include <linux/ipv6.h> | |
38 | #include <net/checksum.h> | |
39 | #include <net/ip6_checksum.h> | |
40 | #include <linux/ethtool.h> | |
41 | #include <linux/if_vlan.h> | |
eacd73f7 | 42 | #include <scsi/fc/fc_fcoe.h> |
9a799d71 AK |
43 | |
44 | #include "ixgbe.h" | |
45 | #include "ixgbe_common.h" | |
46 | ||
47 | char ixgbe_driver_name[] = "ixgbe"; | |
9c8eb720 | 48 | static const char ixgbe_driver_string[] = |
b4617240 | 49 | "Intel(R) 10 Gigabit PCI Express Network Driver"; |
9a799d71 | 50 | |
04193058 | 51 | #define DRV_VERSION "2.0.16-k2" |
9c8eb720 | 52 | const char ixgbe_driver_version[] = DRV_VERSION; |
3efac5a0 | 53 | static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation."; |
9a799d71 AK |
54 | |
55 | static const struct ixgbe_info *ixgbe_info_tbl[] = { | |
b4617240 | 56 | [board_82598] = &ixgbe_82598_info, |
e8e26350 | 57 | [board_82599] = &ixgbe_82599_info, |
9a799d71 AK |
58 | }; |
59 | ||
60 | /* ixgbe_pci_tbl - PCI Device ID Table | |
61 | * | |
62 | * Wildcard entries (PCI_ANY_ID) should come last | |
63 | * Last entry must be all 0s | |
64 | * | |
65 | * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, | |
66 | * Class, Class Mask, private data (not used) } | |
67 | */ | |
68 | static struct pci_device_id ixgbe_pci_tbl[] = { | |
1e336d0f DS |
69 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), |
70 | board_82598 }, | |
9a799d71 | 71 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), |
3957d63d | 72 | board_82598 }, |
9a799d71 | 73 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), |
3957d63d | 74 | board_82598 }, |
0befdb3e JB |
75 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), |
76 | board_82598 }, | |
9a799d71 | 77 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), |
3957d63d | 78 | board_82598 }, |
8d792cd9 JB |
79 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), |
80 | board_82598 }, | |
c4900be0 DS |
81 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), |
82 | board_82598 }, | |
83 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), | |
84 | board_82598 }, | |
b95f5fcb JB |
85 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), |
86 | board_82598 }, | |
c4900be0 DS |
87 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), |
88 | board_82598 }, | |
2f21bdd3 DS |
89 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), |
90 | board_82598 }, | |
e8e26350 PW |
91 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), |
92 | board_82599 }, | |
93 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), | |
94 | board_82599 }, | |
9a799d71 AK |
95 | |
96 | /* required last entry */ | |
97 | {0, } | |
98 | }; | |
99 | MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl); | |
100 | ||
5dd2d332 | 101 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 102 | static int ixgbe_notify_dca(struct notifier_block *, unsigned long event, |
b4617240 | 103 | void *p); |
bd0362dd JC |
104 | static struct notifier_block dca_notifier = { |
105 | .notifier_call = ixgbe_notify_dca, | |
106 | .next = NULL, | |
107 | .priority = 0 | |
108 | }; | |
109 | #endif | |
110 | ||
9a799d71 AK |
111 | MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); |
112 | MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver"); | |
113 | MODULE_LICENSE("GPL"); | |
114 | MODULE_VERSION(DRV_VERSION); | |
115 | ||
116 | #define DEFAULT_DEBUG_LEVEL_SHIFT 3 | |
117 | ||
5eba3699 AV |
118 | static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter) |
119 | { | |
120 | u32 ctrl_ext; | |
121 | ||
122 | /* Let firmware take over control of h/w */ | |
123 | ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); | |
124 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, | |
b4617240 | 125 | ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD); |
5eba3699 AV |
126 | } |
127 | ||
128 | static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter) | |
129 | { | |
130 | u32 ctrl_ext; | |
131 | ||
132 | /* Let firmware know the driver has taken over */ | |
133 | ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); | |
134 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, | |
b4617240 | 135 | ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD); |
5eba3699 | 136 | } |
9a799d71 | 137 | |
e8e26350 PW |
138 | /* |
139 | * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors | |
140 | * @adapter: pointer to adapter struct | |
141 | * @direction: 0 for Rx, 1 for Tx, -1 for other causes | |
142 | * @queue: queue to map the corresponding interrupt to | |
143 | * @msix_vector: the vector to map to the corresponding queue | |
144 | * | |
145 | */ | |
146 | static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction, | |
147 | u8 queue, u8 msix_vector) | |
9a799d71 AK |
148 | { |
149 | u32 ivar, index; | |
e8e26350 PW |
150 | struct ixgbe_hw *hw = &adapter->hw; |
151 | switch (hw->mac.type) { | |
152 | case ixgbe_mac_82598EB: | |
153 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
154 | if (direction == -1) | |
155 | direction = 0; | |
156 | index = (((direction * 64) + queue) >> 2) & 0x1F; | |
157 | ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); | |
158 | ivar &= ~(0xFF << (8 * (queue & 0x3))); | |
159 | ivar |= (msix_vector << (8 * (queue & 0x3))); | |
160 | IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar); | |
161 | break; | |
162 | case ixgbe_mac_82599EB: | |
163 | if (direction == -1) { | |
164 | /* other causes */ | |
165 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
166 | index = ((queue & 1) * 8); | |
167 | ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC); | |
168 | ivar &= ~(0xFF << index); | |
169 | ivar |= (msix_vector << index); | |
170 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar); | |
171 | break; | |
172 | } else { | |
173 | /* tx or rx causes */ | |
174 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
175 | index = ((16 * (queue & 1)) + (8 * direction)); | |
176 | ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); | |
177 | ivar &= ~(0xFF << index); | |
178 | ivar |= (msix_vector << index); | |
179 | IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar); | |
180 | break; | |
181 | } | |
182 | default: | |
183 | break; | |
184 | } | |
9a799d71 AK |
185 | } |
186 | ||
187 | static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter, | |
b4617240 PW |
188 | struct ixgbe_tx_buffer |
189 | *tx_buffer_info) | |
9a799d71 | 190 | { |
44df32c5 | 191 | tx_buffer_info->dma = 0; |
9a799d71 | 192 | if (tx_buffer_info->skb) { |
44df32c5 AD |
193 | skb_dma_unmap(&adapter->pdev->dev, tx_buffer_info->skb, |
194 | DMA_TO_DEVICE); | |
9a799d71 AK |
195 | dev_kfree_skb_any(tx_buffer_info->skb); |
196 | tx_buffer_info->skb = NULL; | |
197 | } | |
44df32c5 | 198 | tx_buffer_info->time_stamp = 0; |
9a799d71 AK |
199 | /* tx_buffer_info must be completely set up in the transmit path */ |
200 | } | |
201 | ||
202 | static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter, | |
b4617240 PW |
203 | struct ixgbe_ring *tx_ring, |
204 | unsigned int eop) | |
9a799d71 | 205 | { |
e01c31a5 | 206 | struct ixgbe_hw *hw = &adapter->hw; |
e01c31a5 | 207 | |
9a799d71 | 208 | /* Detect a transmit hang in hardware, this serializes the |
e01c31a5 | 209 | * check with the clearing of time_stamp and movement of eop */ |
9a799d71 | 210 | adapter->detect_tx_hung = false; |
44df32c5 | 211 | if (tx_ring->tx_buffer_info[eop].time_stamp && |
9a799d71 AK |
212 | time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) && |
213 | !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) { | |
214 | /* detected Tx unit hang */ | |
e01c31a5 JB |
215 | union ixgbe_adv_tx_desc *tx_desc; |
216 | tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop); | |
9a799d71 | 217 | DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n" |
e01c31a5 JB |
218 | " Tx Queue <%d>\n" |
219 | " TDH, TDT <%x>, <%x>\n" | |
9a799d71 AK |
220 | " next_to_use <%x>\n" |
221 | " next_to_clean <%x>\n" | |
222 | "tx_buffer_info[next_to_clean]\n" | |
223 | " time_stamp <%lx>\n" | |
e01c31a5 JB |
224 | " jiffies <%lx>\n", |
225 | tx_ring->queue_index, | |
44df32c5 AD |
226 | IXGBE_READ_REG(hw, tx_ring->head), |
227 | IXGBE_READ_REG(hw, tx_ring->tail), | |
e01c31a5 JB |
228 | tx_ring->next_to_use, eop, |
229 | tx_ring->tx_buffer_info[eop].time_stamp, jiffies); | |
9a799d71 AK |
230 | return true; |
231 | } | |
232 | ||
233 | return false; | |
234 | } | |
235 | ||
b4617240 PW |
236 | #define IXGBE_MAX_TXD_PWR 14 |
237 | #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR) | |
e092be60 AV |
238 | |
239 | /* Tx Descriptors needed, worst case */ | |
240 | #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \ | |
241 | (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0)) | |
242 | #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \ | |
b4617240 | 243 | MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */ |
e092be60 | 244 | |
e01c31a5 JB |
245 | static void ixgbe_tx_timeout(struct net_device *netdev); |
246 | ||
9a799d71 AK |
247 | /** |
248 | * ixgbe_clean_tx_irq - Reclaim resources after transmit completes | |
249 | * @adapter: board private structure | |
e01c31a5 | 250 | * @tx_ring: tx ring to clean |
9a1a69ad JB |
251 | * |
252 | * returns true if transmit work is done | |
9a799d71 AK |
253 | **/ |
254 | static bool ixgbe_clean_tx_irq(struct ixgbe_adapter *adapter, | |
e01c31a5 | 255 | struct ixgbe_ring *tx_ring) |
9a799d71 | 256 | { |
e01c31a5 | 257 | struct net_device *netdev = adapter->netdev; |
12207e49 PWJ |
258 | union ixgbe_adv_tx_desc *tx_desc, *eop_desc; |
259 | struct ixgbe_tx_buffer *tx_buffer_info; | |
260 | unsigned int i, eop, count = 0; | |
e01c31a5 | 261 | unsigned int total_bytes = 0, total_packets = 0; |
9a799d71 AK |
262 | |
263 | i = tx_ring->next_to_clean; | |
12207e49 PWJ |
264 | eop = tx_ring->tx_buffer_info[i].next_to_watch; |
265 | eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop); | |
266 | ||
267 | while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) && | |
9a1a69ad | 268 | (count < tx_ring->work_limit)) { |
12207e49 PWJ |
269 | bool cleaned = false; |
270 | for ( ; !cleaned; count++) { | |
271 | struct sk_buff *skb; | |
9a799d71 AK |
272 | tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i); |
273 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
12207e49 | 274 | cleaned = (i == eop); |
e01c31a5 | 275 | skb = tx_buffer_info->skb; |
9a799d71 | 276 | |
12207e49 | 277 | if (cleaned && skb) { |
e092be60 | 278 | unsigned int segs, bytecount; |
e01c31a5 JB |
279 | |
280 | /* gso_segs is currently only valid for tcp */ | |
e092be60 AV |
281 | segs = skb_shinfo(skb)->gso_segs ?: 1; |
282 | /* multiply data chunks by size of headers */ | |
283 | bytecount = ((segs - 1) * skb_headlen(skb)) + | |
e01c31a5 JB |
284 | skb->len; |
285 | total_packets += segs; | |
286 | total_bytes += bytecount; | |
e092be60 | 287 | } |
e01c31a5 | 288 | |
9a799d71 | 289 | ixgbe_unmap_and_free_tx_resource(adapter, |
e01c31a5 | 290 | tx_buffer_info); |
9a799d71 | 291 | |
12207e49 PWJ |
292 | tx_desc->wb.status = 0; |
293 | ||
9a799d71 AK |
294 | i++; |
295 | if (i == tx_ring->count) | |
296 | i = 0; | |
e01c31a5 | 297 | } |
12207e49 PWJ |
298 | |
299 | eop = tx_ring->tx_buffer_info[i].next_to_watch; | |
300 | eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop); | |
301 | } | |
302 | ||
9a799d71 AK |
303 | tx_ring->next_to_clean = i; |
304 | ||
e092be60 | 305 | #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) |
e01c31a5 JB |
306 | if (unlikely(count && netif_carrier_ok(netdev) && |
307 | (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) { | |
e092be60 AV |
308 | /* Make sure that anybody stopping the queue after this |
309 | * sees the new next_to_clean. | |
310 | */ | |
311 | smp_mb(); | |
30eba97a AV |
312 | if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) && |
313 | !test_bit(__IXGBE_DOWN, &adapter->state)) { | |
314 | netif_wake_subqueue(netdev, tx_ring->queue_index); | |
e01c31a5 | 315 | ++adapter->restart_queue; |
30eba97a | 316 | } |
e092be60 | 317 | } |
9a799d71 | 318 | |
e01c31a5 JB |
319 | if (adapter->detect_tx_hung) { |
320 | if (ixgbe_check_tx_hang(adapter, tx_ring, i)) { | |
321 | /* schedule immediate reset if we believe we hung */ | |
322 | DPRINTK(PROBE, INFO, | |
323 | "tx hang %d detected, resetting adapter\n", | |
324 | adapter->tx_timeout_count + 1); | |
325 | ixgbe_tx_timeout(adapter->netdev); | |
326 | } | |
327 | } | |
9a799d71 | 328 | |
e01c31a5 | 329 | /* re-arm the interrupt */ |
835462fc NS |
330 | if (count >= tx_ring->work_limit) { |
331 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) | |
332 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, | |
333 | tx_ring->v_idx); | |
334 | else if (tx_ring->v_idx & 0xFFFFFFFF) | |
335 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), | |
336 | tx_ring->v_idx); | |
337 | else | |
338 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), | |
339 | (tx_ring->v_idx >> 32)); | |
340 | } | |
341 | ||
9a799d71 | 342 | |
e01c31a5 JB |
343 | tx_ring->total_bytes += total_bytes; |
344 | tx_ring->total_packets += total_packets; | |
e01c31a5 | 345 | tx_ring->stats.packets += total_packets; |
12207e49 | 346 | tx_ring->stats.bytes += total_bytes; |
e01c31a5 JB |
347 | adapter->net_stats.tx_bytes += total_bytes; |
348 | adapter->net_stats.tx_packets += total_packets; | |
9a1a69ad | 349 | return (count < tx_ring->work_limit); |
9a799d71 AK |
350 | } |
351 | ||
5dd2d332 | 352 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 353 | static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter, |
b4617240 | 354 | struct ixgbe_ring *rx_ring) |
bd0362dd JC |
355 | { |
356 | u32 rxctrl; | |
357 | int cpu = get_cpu(); | |
3a581073 | 358 | int q = rx_ring - adapter->rx_ring; |
bd0362dd | 359 | |
3a581073 | 360 | if (rx_ring->cpu != cpu) { |
bd0362dd | 361 | rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q)); |
e8e26350 PW |
362 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
363 | rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK; | |
364 | rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu); | |
365 | } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { | |
366 | rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599; | |
367 | rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) << | |
368 | IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599); | |
369 | } | |
bd0362dd JC |
370 | rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN; |
371 | rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN; | |
15005a32 DS |
372 | rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN); |
373 | rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN | | |
e8e26350 | 374 | IXGBE_DCA_RXCTRL_DESC_HSRO_EN); |
bd0362dd | 375 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl); |
3a581073 | 376 | rx_ring->cpu = cpu; |
bd0362dd JC |
377 | } |
378 | put_cpu(); | |
379 | } | |
380 | ||
381 | static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter, | |
b4617240 | 382 | struct ixgbe_ring *tx_ring) |
bd0362dd JC |
383 | { |
384 | u32 txctrl; | |
385 | int cpu = get_cpu(); | |
3a581073 | 386 | int q = tx_ring - adapter->tx_ring; |
bd0362dd | 387 | |
3a581073 | 388 | if (tx_ring->cpu != cpu) { |
bd0362dd | 389 | txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q)); |
e8e26350 PW |
390 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
391 | txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK; | |
392 | txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu); | |
393 | } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { | |
394 | txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599; | |
395 | txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) << | |
396 | IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599); | |
397 | } | |
bd0362dd JC |
398 | txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN; |
399 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl); | |
3a581073 | 400 | tx_ring->cpu = cpu; |
bd0362dd JC |
401 | } |
402 | put_cpu(); | |
403 | } | |
404 | ||
405 | static void ixgbe_setup_dca(struct ixgbe_adapter *adapter) | |
406 | { | |
407 | int i; | |
408 | ||
409 | if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED)) | |
410 | return; | |
411 | ||
412 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
413 | adapter->tx_ring[i].cpu = -1; | |
414 | ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]); | |
415 | } | |
416 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
417 | adapter->rx_ring[i].cpu = -1; | |
418 | ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]); | |
419 | } | |
420 | } | |
421 | ||
422 | static int __ixgbe_notify_dca(struct device *dev, void *data) | |
423 | { | |
424 | struct net_device *netdev = dev_get_drvdata(dev); | |
425 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
426 | unsigned long event = *(unsigned long *)data; | |
427 | ||
428 | switch (event) { | |
429 | case DCA_PROVIDER_ADD: | |
96b0e0f6 JB |
430 | /* if we're already enabled, don't do it again */ |
431 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
432 | break; | |
bd0362dd JC |
433 | /* Always use CB2 mode, difference is masked |
434 | * in the CB driver. */ | |
435 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2); | |
652f093f | 436 | if (dca_add_requester(dev) == 0) { |
96b0e0f6 | 437 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; |
bd0362dd JC |
438 | ixgbe_setup_dca(adapter); |
439 | break; | |
440 | } | |
441 | /* Fall Through since DCA is disabled. */ | |
442 | case DCA_PROVIDER_REMOVE: | |
443 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { | |
444 | dca_remove_requester(dev); | |
445 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
446 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); | |
447 | } | |
448 | break; | |
449 | } | |
450 | ||
652f093f | 451 | return 0; |
bd0362dd JC |
452 | } |
453 | ||
5dd2d332 | 454 | #endif /* CONFIG_IXGBE_DCA */ |
9a799d71 AK |
455 | /** |
456 | * ixgbe_receive_skb - Send a completed packet up the stack | |
457 | * @adapter: board private structure | |
458 | * @skb: packet to send up | |
177db6ff MC |
459 | * @status: hardware indication of status of receive |
460 | * @rx_ring: rx descriptor ring (for a specific queue) to setup | |
461 | * @rx_desc: rx descriptor | |
9a799d71 | 462 | **/ |
78b6f4ce | 463 | static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector, |
b4617240 | 464 | struct sk_buff *skb, u8 status, |
fdaff1ce | 465 | struct ixgbe_ring *ring, |
177db6ff | 466 | union ixgbe_adv_rx_desc *rx_desc) |
9a799d71 | 467 | { |
78b6f4ce HX |
468 | struct ixgbe_adapter *adapter = q_vector->adapter; |
469 | struct napi_struct *napi = &q_vector->napi; | |
177db6ff MC |
470 | bool is_vlan = (status & IXGBE_RXD_STAT_VP); |
471 | u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan); | |
9a799d71 | 472 | |
fdaff1ce | 473 | skb_record_rx_queue(skb, ring->queue_index); |
182ff8df | 474 | if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) { |
2f90b865 | 475 | if (adapter->vlgrp && is_vlan && (tag != 0)) |
78b6f4ce | 476 | vlan_gro_receive(napi, adapter->vlgrp, tag, skb); |
9a799d71 | 477 | else |
78b6f4ce | 478 | napi_gro_receive(napi, skb); |
177db6ff | 479 | } else { |
182ff8df AD |
480 | if (adapter->vlgrp && is_vlan && (tag != 0)) |
481 | vlan_hwaccel_rx(skb, adapter->vlgrp, tag); | |
482 | else | |
483 | netif_rx(skb); | |
9a799d71 AK |
484 | } |
485 | } | |
486 | ||
e59bd25d AV |
487 | /** |
488 | * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum | |
489 | * @adapter: address of board private structure | |
490 | * @status_err: hardware indication of status of receive | |
491 | * @skb: skb currently being received and modified | |
492 | **/ | |
9a799d71 | 493 | static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter, |
712744be | 494 | u32 status_err, struct sk_buff *skb) |
9a799d71 AK |
495 | { |
496 | skb->ip_summed = CHECKSUM_NONE; | |
497 | ||
712744be JB |
498 | /* Rx csum disabled */ |
499 | if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED)) | |
9a799d71 | 500 | return; |
e59bd25d AV |
501 | |
502 | /* if IP and error */ | |
503 | if ((status_err & IXGBE_RXD_STAT_IPCS) && | |
504 | (status_err & IXGBE_RXDADV_ERR_IPE)) { | |
9a799d71 AK |
505 | adapter->hw_csum_rx_error++; |
506 | return; | |
507 | } | |
e59bd25d AV |
508 | |
509 | if (!(status_err & IXGBE_RXD_STAT_L4CS)) | |
510 | return; | |
511 | ||
512 | if (status_err & IXGBE_RXDADV_ERR_TCPE) { | |
513 | adapter->hw_csum_rx_error++; | |
514 | return; | |
515 | } | |
516 | ||
9a799d71 | 517 | /* It must be a TCP or UDP packet with a valid checksum */ |
e59bd25d | 518 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
9a799d71 AK |
519 | adapter->hw_csum_rx_good++; |
520 | } | |
521 | ||
e8e26350 PW |
522 | static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw, |
523 | struct ixgbe_ring *rx_ring, u32 val) | |
524 | { | |
525 | /* | |
526 | * Force memory writes to complete before letting h/w | |
527 | * know there are new descriptors to fetch. (Only | |
528 | * applicable for weak-ordered memory model archs, | |
529 | * such as IA-64). | |
530 | */ | |
531 | wmb(); | |
532 | IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val); | |
533 | } | |
534 | ||
9a799d71 AK |
535 | /** |
536 | * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split | |
537 | * @adapter: address of board private structure | |
538 | **/ | |
539 | static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter, | |
7c6e0a43 JB |
540 | struct ixgbe_ring *rx_ring, |
541 | int cleaned_count) | |
9a799d71 | 542 | { |
9a799d71 AK |
543 | struct pci_dev *pdev = adapter->pdev; |
544 | union ixgbe_adv_rx_desc *rx_desc; | |
3a581073 | 545 | struct ixgbe_rx_buffer *bi; |
9a799d71 | 546 | unsigned int i; |
e8e26350 | 547 | unsigned int bufsz = rx_ring->rx_buf_len + NET_IP_ALIGN; |
9a799d71 AK |
548 | |
549 | i = rx_ring->next_to_use; | |
3a581073 | 550 | bi = &rx_ring->rx_buffer_info[i]; |
9a799d71 AK |
551 | |
552 | while (cleaned_count--) { | |
553 | rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i); | |
554 | ||
762f4c57 | 555 | if (!bi->page_dma && |
3a581073 | 556 | (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) { |
3a581073 | 557 | if (!bi->page) { |
762f4c57 JB |
558 | bi->page = alloc_page(GFP_ATOMIC); |
559 | if (!bi->page) { | |
560 | adapter->alloc_rx_page_failed++; | |
561 | goto no_buffers; | |
562 | } | |
563 | bi->page_offset = 0; | |
564 | } else { | |
565 | /* use a half page if we're re-using */ | |
566 | bi->page_offset ^= (PAGE_SIZE / 2); | |
9a799d71 | 567 | } |
762f4c57 JB |
568 | |
569 | bi->page_dma = pci_map_page(pdev, bi->page, | |
570 | bi->page_offset, | |
571 | (PAGE_SIZE / 2), | |
572 | PCI_DMA_FROMDEVICE); | |
9a799d71 AK |
573 | } |
574 | ||
3a581073 | 575 | if (!bi->skb) { |
5ecc3614 | 576 | struct sk_buff *skb; |
e8e26350 | 577 | skb = netdev_alloc_skb(adapter->netdev, bufsz); |
9a799d71 AK |
578 | |
579 | if (!skb) { | |
580 | adapter->alloc_rx_buff_failed++; | |
581 | goto no_buffers; | |
582 | } | |
583 | ||
584 | /* | |
585 | * Make buffer alignment 2 beyond a 16 byte boundary | |
586 | * this will result in a 16 byte aligned IP header after | |
587 | * the 14 byte MAC header is removed | |
588 | */ | |
589 | skb_reserve(skb, NET_IP_ALIGN); | |
590 | ||
3a581073 | 591 | bi->skb = skb; |
e8e26350 | 592 | bi->dma = pci_map_single(pdev, skb->data, bufsz, |
3a581073 | 593 | PCI_DMA_FROMDEVICE); |
9a799d71 AK |
594 | } |
595 | /* Refresh the desc even if buffer_addrs didn't change because | |
596 | * each write-back erases this info. */ | |
597 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { | |
3a581073 JB |
598 | rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma); |
599 | rx_desc->read.hdr_addr = cpu_to_le64(bi->dma); | |
9a799d71 | 600 | } else { |
3a581073 | 601 | rx_desc->read.pkt_addr = cpu_to_le64(bi->dma); |
9a799d71 AK |
602 | } |
603 | ||
604 | i++; | |
605 | if (i == rx_ring->count) | |
606 | i = 0; | |
3a581073 | 607 | bi = &rx_ring->rx_buffer_info[i]; |
9a799d71 | 608 | } |
7c6e0a43 | 609 | |
9a799d71 AK |
610 | no_buffers: |
611 | if (rx_ring->next_to_use != i) { | |
612 | rx_ring->next_to_use = i; | |
613 | if (i-- == 0) | |
614 | i = (rx_ring->count - 1); | |
615 | ||
e8e26350 | 616 | ixgbe_release_rx_desc(&adapter->hw, rx_ring, i); |
9a799d71 AK |
617 | } |
618 | } | |
619 | ||
7c6e0a43 JB |
620 | static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc) |
621 | { | |
622 | return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info; | |
623 | } | |
624 | ||
625 | static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc) | |
626 | { | |
627 | return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; | |
628 | } | |
629 | ||
f8212f97 AD |
630 | static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc) |
631 | { | |
632 | return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) & | |
633 | IXGBE_RXDADV_RSCCNT_MASK) >> | |
634 | IXGBE_RXDADV_RSCCNT_SHIFT; | |
635 | } | |
636 | ||
637 | /** | |
638 | * ixgbe_transform_rsc_queue - change rsc queue into a full packet | |
639 | * @skb: pointer to the last skb in the rsc queue | |
640 | * | |
641 | * This function changes a queue full of hw rsc buffers into a completed | |
642 | * packet. It uses the ->prev pointers to find the first packet and then | |
643 | * turns it into the frag list owner. | |
644 | **/ | |
645 | static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb) | |
646 | { | |
647 | unsigned int frag_list_size = 0; | |
648 | ||
649 | while (skb->prev) { | |
650 | struct sk_buff *prev = skb->prev; | |
651 | frag_list_size += skb->len; | |
652 | skb->prev = NULL; | |
653 | skb = prev; | |
654 | } | |
655 | ||
656 | skb_shinfo(skb)->frag_list = skb->next; | |
657 | skb->next = NULL; | |
658 | skb->len += frag_list_size; | |
659 | skb->data_len += frag_list_size; | |
660 | skb->truesize += frag_list_size; | |
661 | return skb; | |
662 | } | |
663 | ||
78b6f4ce | 664 | static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, |
b4617240 PW |
665 | struct ixgbe_ring *rx_ring, |
666 | int *work_done, int work_to_do) | |
9a799d71 | 667 | { |
78b6f4ce | 668 | struct ixgbe_adapter *adapter = q_vector->adapter; |
9a799d71 AK |
669 | struct pci_dev *pdev = adapter->pdev; |
670 | union ixgbe_adv_rx_desc *rx_desc, *next_rxd; | |
671 | struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer; | |
672 | struct sk_buff *skb; | |
f8212f97 | 673 | unsigned int i, rsc_count = 0; |
7c6e0a43 | 674 | u32 len, staterr; |
177db6ff MC |
675 | u16 hdr_info; |
676 | bool cleaned = false; | |
9a799d71 | 677 | int cleaned_count = 0; |
d2f4fbe2 | 678 | unsigned int total_rx_bytes = 0, total_rx_packets = 0; |
9a799d71 AK |
679 | |
680 | i = rx_ring->next_to_clean; | |
9a799d71 AK |
681 | rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i); |
682 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
683 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; | |
9a799d71 AK |
684 | |
685 | while (staterr & IXGBE_RXD_STAT_DD) { | |
7c6e0a43 | 686 | u32 upper_len = 0; |
9a799d71 AK |
687 | if (*work_done >= work_to_do) |
688 | break; | |
689 | (*work_done)++; | |
690 | ||
691 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { | |
7c6e0a43 JB |
692 | hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc)); |
693 | len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >> | |
762f4c57 | 694 | IXGBE_RXDADV_HDRBUFLEN_SHIFT; |
9a799d71 AK |
695 | if (hdr_info & IXGBE_RXDADV_SPH) |
696 | adapter->rx_hdr_split++; | |
697 | if (len > IXGBE_RX_HDR_SIZE) | |
698 | len = IXGBE_RX_HDR_SIZE; | |
699 | upper_len = le16_to_cpu(rx_desc->wb.upper.length); | |
7c6e0a43 | 700 | } else { |
9a799d71 | 701 | len = le16_to_cpu(rx_desc->wb.upper.length); |
7c6e0a43 | 702 | } |
9a799d71 AK |
703 | |
704 | cleaned = true; | |
705 | skb = rx_buffer_info->skb; | |
706 | prefetch(skb->data - NET_IP_ALIGN); | |
707 | rx_buffer_info->skb = NULL; | |
708 | ||
709 | if (len && !skb_shinfo(skb)->nr_frags) { | |
710 | pci_unmap_single(pdev, rx_buffer_info->dma, | |
5ecc3614 | 711 | rx_ring->rx_buf_len, |
b4617240 | 712 | PCI_DMA_FROMDEVICE); |
9a799d71 AK |
713 | skb_put(skb, len); |
714 | } | |
715 | ||
716 | if (upper_len) { | |
717 | pci_unmap_page(pdev, rx_buffer_info->page_dma, | |
762f4c57 | 718 | PAGE_SIZE / 2, PCI_DMA_FROMDEVICE); |
9a799d71 AK |
719 | rx_buffer_info->page_dma = 0; |
720 | skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, | |
762f4c57 JB |
721 | rx_buffer_info->page, |
722 | rx_buffer_info->page_offset, | |
723 | upper_len); | |
724 | ||
725 | if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) || | |
726 | (page_count(rx_buffer_info->page) != 1)) | |
727 | rx_buffer_info->page = NULL; | |
728 | else | |
729 | get_page(rx_buffer_info->page); | |
9a799d71 AK |
730 | |
731 | skb->len += upper_len; | |
732 | skb->data_len += upper_len; | |
733 | skb->truesize += upper_len; | |
734 | } | |
735 | ||
736 | i++; | |
737 | if (i == rx_ring->count) | |
738 | i = 0; | |
9a799d71 AK |
739 | |
740 | next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i); | |
741 | prefetch(next_rxd); | |
9a799d71 | 742 | cleaned_count++; |
f8212f97 AD |
743 | |
744 | if (adapter->flags & IXGBE_FLAG_RSC_CAPABLE) | |
745 | rsc_count = ixgbe_get_rsc_count(rx_desc); | |
746 | ||
747 | if (rsc_count) { | |
748 | u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >> | |
749 | IXGBE_RXDADV_NEXTP_SHIFT; | |
750 | next_buffer = &rx_ring->rx_buffer_info[nextp]; | |
751 | rx_ring->rsc_count += (rsc_count - 1); | |
752 | } else { | |
753 | next_buffer = &rx_ring->rx_buffer_info[i]; | |
754 | } | |
755 | ||
9a799d71 | 756 | if (staterr & IXGBE_RXD_STAT_EOP) { |
f8212f97 AD |
757 | if (skb->prev) |
758 | skb = ixgbe_transform_rsc_queue(skb); | |
9a799d71 AK |
759 | rx_ring->stats.packets++; |
760 | rx_ring->stats.bytes += skb->len; | |
761 | } else { | |
f8212f97 AD |
762 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { |
763 | rx_buffer_info->skb = next_buffer->skb; | |
764 | rx_buffer_info->dma = next_buffer->dma; | |
765 | next_buffer->skb = skb; | |
766 | next_buffer->dma = 0; | |
767 | } else { | |
768 | skb->next = next_buffer->skb; | |
769 | skb->next->prev = skb; | |
770 | } | |
9a799d71 AK |
771 | adapter->non_eop_descs++; |
772 | goto next_desc; | |
773 | } | |
774 | ||
775 | if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) { | |
776 | dev_kfree_skb_irq(skb); | |
777 | goto next_desc; | |
778 | } | |
779 | ||
780 | ixgbe_rx_checksum(adapter, staterr, skb); | |
d2f4fbe2 AV |
781 | |
782 | /* probably a little skewed due to removing CRC */ | |
783 | total_rx_bytes += skb->len; | |
784 | total_rx_packets++; | |
785 | ||
74ce8dd2 | 786 | skb->protocol = eth_type_trans(skb, adapter->netdev); |
332d4a7d YZ |
787 | #ifdef IXGBE_FCOE |
788 | /* if ddp, not passing to ULD unless for FCP_RSP or error */ | |
789 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) | |
790 | if (!ixgbe_fcoe_ddp(adapter, rx_desc, skb)) | |
791 | goto next_desc; | |
792 | #endif /* IXGBE_FCOE */ | |
fdaff1ce | 793 | ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc); |
9a799d71 AK |
794 | |
795 | next_desc: | |
796 | rx_desc->wb.upper.status_error = 0; | |
797 | ||
798 | /* return some buffers to hardware, one at a time is too slow */ | |
799 | if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) { | |
800 | ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count); | |
801 | cleaned_count = 0; | |
802 | } | |
803 | ||
804 | /* use prefetched values */ | |
805 | rx_desc = next_rxd; | |
f8212f97 | 806 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; |
9a799d71 AK |
807 | |
808 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
177db6ff MC |
809 | } |
810 | ||
9a799d71 AK |
811 | rx_ring->next_to_clean = i; |
812 | cleaned_count = IXGBE_DESC_UNUSED(rx_ring); | |
813 | ||
814 | if (cleaned_count) | |
815 | ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count); | |
816 | ||
f494e8fa AV |
817 | rx_ring->total_packets += total_rx_packets; |
818 | rx_ring->total_bytes += total_rx_bytes; | |
819 | adapter->net_stats.rx_bytes += total_rx_bytes; | |
820 | adapter->net_stats.rx_packets += total_rx_packets; | |
821 | ||
9a799d71 AK |
822 | return cleaned; |
823 | } | |
824 | ||
021230d4 | 825 | static int ixgbe_clean_rxonly(struct napi_struct *, int); |
9a799d71 AK |
826 | /** |
827 | * ixgbe_configure_msix - Configure MSI-X hardware | |
828 | * @adapter: board private structure | |
829 | * | |
830 | * ixgbe_configure_msix sets up the hardware to properly generate MSI-X | |
831 | * interrupts. | |
832 | **/ | |
833 | static void ixgbe_configure_msix(struct ixgbe_adapter *adapter) | |
834 | { | |
021230d4 AV |
835 | struct ixgbe_q_vector *q_vector; |
836 | int i, j, q_vectors, v_idx, r_idx; | |
837 | u32 mask; | |
9a799d71 | 838 | |
021230d4 | 839 | q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; |
9a799d71 | 840 | |
4df10466 JB |
841 | /* |
842 | * Populate the IVAR table and set the ITR values to the | |
021230d4 AV |
843 | * corresponding register. |
844 | */ | |
845 | for (v_idx = 0; v_idx < q_vectors; v_idx++) { | |
7a921c93 | 846 | q_vector = adapter->q_vector[v_idx]; |
021230d4 AV |
847 | /* XXX for_each_bit(...) */ |
848 | r_idx = find_first_bit(q_vector->rxr_idx, | |
b4617240 | 849 | adapter->num_rx_queues); |
021230d4 AV |
850 | |
851 | for (i = 0; i < q_vector->rxr_count; i++) { | |
852 | j = adapter->rx_ring[r_idx].reg_idx; | |
e8e26350 | 853 | ixgbe_set_ivar(adapter, 0, j, v_idx); |
021230d4 | 854 | r_idx = find_next_bit(q_vector->rxr_idx, |
b4617240 PW |
855 | adapter->num_rx_queues, |
856 | r_idx + 1); | |
021230d4 AV |
857 | } |
858 | r_idx = find_first_bit(q_vector->txr_idx, | |
b4617240 | 859 | adapter->num_tx_queues); |
021230d4 AV |
860 | |
861 | for (i = 0; i < q_vector->txr_count; i++) { | |
862 | j = adapter->tx_ring[r_idx].reg_idx; | |
e8e26350 | 863 | ixgbe_set_ivar(adapter, 1, j, v_idx); |
021230d4 | 864 | r_idx = find_next_bit(q_vector->txr_idx, |
b4617240 PW |
865 | adapter->num_tx_queues, |
866 | r_idx + 1); | |
021230d4 AV |
867 | } |
868 | ||
30efa5a3 | 869 | /* if this is a tx only vector halve the interrupt rate */ |
021230d4 | 870 | if (q_vector->txr_count && !q_vector->rxr_count) |
30efa5a3 | 871 | q_vector->eitr = (adapter->eitr_param >> 1); |
509ee935 | 872 | else if (q_vector->rxr_count) |
30efa5a3 JB |
873 | /* rx only */ |
874 | q_vector->eitr = adapter->eitr_param; | |
021230d4 | 875 | |
509ee935 | 876 | /* |
4df10466 | 877 | * since this is initial set up don't need to call |
509ee935 JB |
878 | * ixgbe_write_eitr helper |
879 | */ | |
021230d4 | 880 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), |
b4617240 | 881 | EITR_INTS_PER_SEC_TO_REG(q_vector->eitr)); |
9a799d71 AK |
882 | } |
883 | ||
e8e26350 PW |
884 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) |
885 | ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX, | |
886 | v_idx); | |
887 | else if (adapter->hw.mac.type == ixgbe_mac_82599EB) | |
888 | ixgbe_set_ivar(adapter, -1, 1, v_idx); | |
021230d4 AV |
889 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950); |
890 | ||
41fb9248 | 891 | /* set up to autoclear timer, and the vectors */ |
021230d4 | 892 | mask = IXGBE_EIMS_ENABLE_MASK; |
41fb9248 | 893 | mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC); |
021230d4 | 894 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask); |
9a799d71 AK |
895 | } |
896 | ||
f494e8fa AV |
897 | enum latency_range { |
898 | lowest_latency = 0, | |
899 | low_latency = 1, | |
900 | bulk_latency = 2, | |
901 | latency_invalid = 255 | |
902 | }; | |
903 | ||
904 | /** | |
905 | * ixgbe_update_itr - update the dynamic ITR value based on statistics | |
906 | * @adapter: pointer to adapter | |
907 | * @eitr: eitr setting (ints per sec) to give last timeslice | |
908 | * @itr_setting: current throttle rate in ints/second | |
909 | * @packets: the number of packets during this measurement interval | |
910 | * @bytes: the number of bytes during this measurement interval | |
911 | * | |
912 | * Stores a new ITR value based on packets and byte | |
913 | * counts during the last interrupt. The advantage of per interrupt | |
914 | * computation is faster updates and more accurate ITR for the current | |
915 | * traffic pattern. Constants in this function were computed | |
916 | * based on theoretical maximum wire speed and thresholds were set based | |
917 | * on testing data as well as attempting to minimize response time | |
918 | * while increasing bulk throughput. | |
919 | * this functionality is controlled by the InterruptThrottleRate module | |
920 | * parameter (see ixgbe_param.c) | |
921 | **/ | |
922 | static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter, | |
b4617240 PW |
923 | u32 eitr, u8 itr_setting, |
924 | int packets, int bytes) | |
f494e8fa AV |
925 | { |
926 | unsigned int retval = itr_setting; | |
927 | u32 timepassed_us; | |
928 | u64 bytes_perint; | |
929 | ||
930 | if (packets == 0) | |
931 | goto update_itr_done; | |
932 | ||
933 | ||
934 | /* simple throttlerate management | |
935 | * 0-20MB/s lowest (100000 ints/s) | |
936 | * 20-100MB/s low (20000 ints/s) | |
937 | * 100-1249MB/s bulk (8000 ints/s) | |
938 | */ | |
939 | /* what was last interrupt timeslice? */ | |
940 | timepassed_us = 1000000/eitr; | |
941 | bytes_perint = bytes / timepassed_us; /* bytes/usec */ | |
942 | ||
943 | switch (itr_setting) { | |
944 | case lowest_latency: | |
945 | if (bytes_perint > adapter->eitr_low) | |
946 | retval = low_latency; | |
947 | break; | |
948 | case low_latency: | |
949 | if (bytes_perint > adapter->eitr_high) | |
950 | retval = bulk_latency; | |
951 | else if (bytes_perint <= adapter->eitr_low) | |
952 | retval = lowest_latency; | |
953 | break; | |
954 | case bulk_latency: | |
955 | if (bytes_perint <= adapter->eitr_high) | |
956 | retval = low_latency; | |
957 | break; | |
958 | } | |
959 | ||
960 | update_itr_done: | |
961 | return retval; | |
962 | } | |
963 | ||
509ee935 JB |
964 | /** |
965 | * ixgbe_write_eitr - write EITR register in hardware specific way | |
966 | * @adapter: pointer to adapter struct | |
967 | * @v_idx: vector index into q_vector array | |
968 | * @itr_reg: new value to be written in *register* format, not ints/s | |
969 | * | |
970 | * This function is made to be called by ethtool and by the driver | |
971 | * when it needs to update EITR registers at runtime. Hardware | |
972 | * specific quirks/differences are taken care of here. | |
973 | */ | |
974 | void ixgbe_write_eitr(struct ixgbe_adapter *adapter, int v_idx, u32 itr_reg) | |
975 | { | |
976 | struct ixgbe_hw *hw = &adapter->hw; | |
977 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { | |
978 | /* must write high and low 16 bits to reset counter */ | |
979 | itr_reg |= (itr_reg << 16); | |
980 | } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { | |
981 | /* | |
982 | * set the WDIS bit to not clear the timer bits and cause an | |
983 | * immediate assertion of the interrupt | |
984 | */ | |
985 | itr_reg |= IXGBE_EITR_CNT_WDIS; | |
986 | } | |
987 | IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg); | |
988 | } | |
989 | ||
f494e8fa AV |
990 | static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector) |
991 | { | |
992 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
f494e8fa AV |
993 | u32 new_itr; |
994 | u8 current_itr, ret_itr; | |
7a921c93 | 995 | int i, r_idx, v_idx = q_vector->v_idx; |
f494e8fa AV |
996 | struct ixgbe_ring *rx_ring, *tx_ring; |
997 | ||
998 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
999 | for (i = 0; i < q_vector->txr_count; i++) { | |
1000 | tx_ring = &(adapter->tx_ring[r_idx]); | |
1001 | ret_itr = ixgbe_update_itr(adapter, q_vector->eitr, | |
b4617240 PW |
1002 | q_vector->tx_itr, |
1003 | tx_ring->total_packets, | |
1004 | tx_ring->total_bytes); | |
f494e8fa AV |
1005 | /* if the result for this queue would decrease interrupt |
1006 | * rate for this vector then use that result */ | |
30efa5a3 | 1007 | q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ? |
b4617240 | 1008 | q_vector->tx_itr - 1 : ret_itr); |
f494e8fa | 1009 | r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, |
b4617240 | 1010 | r_idx + 1); |
f494e8fa AV |
1011 | } |
1012 | ||
1013 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
1014 | for (i = 0; i < q_vector->rxr_count; i++) { | |
1015 | rx_ring = &(adapter->rx_ring[r_idx]); | |
1016 | ret_itr = ixgbe_update_itr(adapter, q_vector->eitr, | |
b4617240 PW |
1017 | q_vector->rx_itr, |
1018 | rx_ring->total_packets, | |
1019 | rx_ring->total_bytes); | |
f494e8fa AV |
1020 | /* if the result for this queue would decrease interrupt |
1021 | * rate for this vector then use that result */ | |
30efa5a3 | 1022 | q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ? |
b4617240 | 1023 | q_vector->rx_itr - 1 : ret_itr); |
f494e8fa | 1024 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, |
b4617240 | 1025 | r_idx + 1); |
f494e8fa AV |
1026 | } |
1027 | ||
30efa5a3 | 1028 | current_itr = max(q_vector->rx_itr, q_vector->tx_itr); |
f494e8fa AV |
1029 | |
1030 | switch (current_itr) { | |
1031 | /* counts and packets in update_itr are dependent on these numbers */ | |
1032 | case lowest_latency: | |
1033 | new_itr = 100000; | |
1034 | break; | |
1035 | case low_latency: | |
1036 | new_itr = 20000; /* aka hwitr = ~200 */ | |
1037 | break; | |
1038 | case bulk_latency: | |
1039 | default: | |
1040 | new_itr = 8000; | |
1041 | break; | |
1042 | } | |
1043 | ||
1044 | if (new_itr != q_vector->eitr) { | |
1045 | u32 itr_reg; | |
509ee935 JB |
1046 | |
1047 | /* save the algorithm value here, not the smoothed one */ | |
1048 | q_vector->eitr = new_itr; | |
f494e8fa AV |
1049 | /* do an exponential smoothing */ |
1050 | new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100); | |
f494e8fa | 1051 | itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr); |
509ee935 | 1052 | ixgbe_write_eitr(adapter, v_idx, itr_reg); |
f494e8fa AV |
1053 | } |
1054 | ||
1055 | return; | |
1056 | } | |
1057 | ||
0befdb3e JB |
1058 | static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr) |
1059 | { | |
1060 | struct ixgbe_hw *hw = &adapter->hw; | |
1061 | ||
1062 | if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) && | |
1063 | (eicr & IXGBE_EICR_GPI_SDP1)) { | |
1064 | DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n"); | |
1065 | /* write to clear the interrupt */ | |
1066 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); | |
1067 | } | |
1068 | } | |
cf8280ee | 1069 | |
e8e26350 PW |
1070 | static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr) |
1071 | { | |
1072 | struct ixgbe_hw *hw = &adapter->hw; | |
1073 | ||
1074 | if (eicr & IXGBE_EICR_GPI_SDP1) { | |
1075 | /* Clear the interrupt */ | |
1076 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); | |
1077 | schedule_work(&adapter->multispeed_fiber_task); | |
1078 | } else if (eicr & IXGBE_EICR_GPI_SDP2) { | |
1079 | /* Clear the interrupt */ | |
1080 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2); | |
1081 | schedule_work(&adapter->sfp_config_module_task); | |
1082 | } else { | |
1083 | /* Interrupt isn't for us... */ | |
1084 | return; | |
1085 | } | |
1086 | } | |
1087 | ||
cf8280ee JB |
1088 | static void ixgbe_check_lsc(struct ixgbe_adapter *adapter) |
1089 | { | |
1090 | struct ixgbe_hw *hw = &adapter->hw; | |
1091 | ||
1092 | adapter->lsc_int++; | |
1093 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; | |
1094 | adapter->link_check_timeout = jiffies; | |
1095 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { | |
1096 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); | |
1097 | schedule_work(&adapter->watchdog_task); | |
1098 | } | |
1099 | } | |
1100 | ||
9a799d71 AK |
1101 | static irqreturn_t ixgbe_msix_lsc(int irq, void *data) |
1102 | { | |
1103 | struct net_device *netdev = data; | |
1104 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
1105 | struct ixgbe_hw *hw = &adapter->hw; | |
54037505 DS |
1106 | u32 eicr; |
1107 | ||
1108 | /* | |
1109 | * Workaround for Silicon errata. Use clear-by-write instead | |
1110 | * of clear-by-read. Reading with EICS will return the | |
1111 | * interrupt causes without clearing, which later be done | |
1112 | * with the write to EICR. | |
1113 | */ | |
1114 | eicr = IXGBE_READ_REG(hw, IXGBE_EICS); | |
1115 | IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); | |
9a799d71 | 1116 | |
cf8280ee JB |
1117 | if (eicr & IXGBE_EICR_LSC) |
1118 | ixgbe_check_lsc(adapter); | |
d4f80882 | 1119 | |
e8e26350 PW |
1120 | if (hw->mac.type == ixgbe_mac_82598EB) |
1121 | ixgbe_check_fan_failure(adapter, eicr); | |
0befdb3e | 1122 | |
e8e26350 PW |
1123 | if (hw->mac.type == ixgbe_mac_82599EB) |
1124 | ixgbe_check_sfp_event(adapter, eicr); | |
d4f80882 AV |
1125 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
1126 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER); | |
9a799d71 AK |
1127 | |
1128 | return IRQ_HANDLED; | |
1129 | } | |
1130 | ||
1131 | static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data) | |
1132 | { | |
021230d4 AV |
1133 | struct ixgbe_q_vector *q_vector = data; |
1134 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
3a581073 | 1135 | struct ixgbe_ring *tx_ring; |
021230d4 AV |
1136 | int i, r_idx; |
1137 | ||
1138 | if (!q_vector->txr_count) | |
1139 | return IRQ_HANDLED; | |
1140 | ||
1141 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
1142 | for (i = 0; i < q_vector->txr_count; i++) { | |
3a581073 | 1143 | tx_ring = &(adapter->tx_ring[r_idx]); |
5dd2d332 | 1144 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 1145 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) |
3a581073 | 1146 | ixgbe_update_tx_dca(adapter, tx_ring); |
bd0362dd | 1147 | #endif |
3a581073 JB |
1148 | tx_ring->total_bytes = 0; |
1149 | tx_ring->total_packets = 0; | |
1150 | ixgbe_clean_tx_irq(adapter, tx_ring); | |
021230d4 | 1151 | r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, |
b4617240 | 1152 | r_idx + 1); |
021230d4 | 1153 | } |
9a799d71 | 1154 | |
9a799d71 AK |
1155 | return IRQ_HANDLED; |
1156 | } | |
1157 | ||
021230d4 AV |
1158 | /** |
1159 | * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues) | |
1160 | * @irq: unused | |
1161 | * @data: pointer to our q_vector struct for this interrupt vector | |
1162 | **/ | |
9a799d71 AK |
1163 | static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data) |
1164 | { | |
021230d4 AV |
1165 | struct ixgbe_q_vector *q_vector = data; |
1166 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
3a581073 | 1167 | struct ixgbe_ring *rx_ring; |
021230d4 | 1168 | int r_idx; |
30efa5a3 | 1169 | int i; |
021230d4 AV |
1170 | |
1171 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
30efa5a3 JB |
1172 | for (i = 0; i < q_vector->rxr_count; i++) { |
1173 | rx_ring = &(adapter->rx_ring[r_idx]); | |
1174 | rx_ring->total_bytes = 0; | |
1175 | rx_ring->total_packets = 0; | |
1176 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, | |
1177 | r_idx + 1); | |
1178 | } | |
1179 | ||
021230d4 AV |
1180 | if (!q_vector->rxr_count) |
1181 | return IRQ_HANDLED; | |
1182 | ||
30efa5a3 | 1183 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); |
3a581073 | 1184 | rx_ring = &(adapter->rx_ring[r_idx]); |
021230d4 | 1185 | /* disable interrupts on this vector only */ |
835462fc NS |
1186 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) |
1187 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, rx_ring->v_idx); | |
1188 | else if (rx_ring->v_idx & 0xFFFFFFFF) | |
1189 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), rx_ring->v_idx); | |
1190 | else | |
1191 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), | |
1192 | (rx_ring->v_idx >> 32)); | |
288379f0 | 1193 | napi_schedule(&q_vector->napi); |
021230d4 AV |
1194 | |
1195 | return IRQ_HANDLED; | |
1196 | } | |
1197 | ||
1198 | static irqreturn_t ixgbe_msix_clean_many(int irq, void *data) | |
1199 | { | |
1200 | ixgbe_msix_clean_rx(irq, data); | |
1201 | ixgbe_msix_clean_tx(irq, data); | |
9a799d71 | 1202 | |
9a799d71 AK |
1203 | return IRQ_HANDLED; |
1204 | } | |
1205 | ||
835462fc NS |
1206 | static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter, |
1207 | u64 qmask) | |
1208 | { | |
1209 | u32 mask; | |
1210 | ||
1211 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { | |
1212 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); | |
1213 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); | |
1214 | } else { | |
1215 | mask = (qmask & 0xFFFFFFFF); | |
1216 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask); | |
1217 | mask = (qmask >> 32); | |
1218 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask); | |
1219 | } | |
1220 | /* skip the flush */ | |
1221 | } | |
1222 | ||
021230d4 AV |
1223 | /** |
1224 | * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine | |
1225 | * @napi: napi struct with our devices info in it | |
1226 | * @budget: amount of work driver is allowed to do this pass, in packets | |
1227 | * | |
f0848276 JB |
1228 | * This function is optimized for cleaning one queue only on a single |
1229 | * q_vector!!! | |
021230d4 | 1230 | **/ |
9a799d71 AK |
1231 | static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget) |
1232 | { | |
021230d4 | 1233 | struct ixgbe_q_vector *q_vector = |
b4617240 | 1234 | container_of(napi, struct ixgbe_q_vector, napi); |
021230d4 | 1235 | struct ixgbe_adapter *adapter = q_vector->adapter; |
f0848276 | 1236 | struct ixgbe_ring *rx_ring = NULL; |
9a799d71 | 1237 | int work_done = 0; |
021230d4 | 1238 | long r_idx; |
9a799d71 | 1239 | |
021230d4 | 1240 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); |
3a581073 | 1241 | rx_ring = &(adapter->rx_ring[r_idx]); |
5dd2d332 | 1242 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 1243 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) |
3a581073 | 1244 | ixgbe_update_rx_dca(adapter, rx_ring); |
bd0362dd | 1245 | #endif |
9a799d71 | 1246 | |
78b6f4ce | 1247 | ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget); |
9a799d71 | 1248 | |
021230d4 AV |
1249 | /* If all Rx work done, exit the polling mode */ |
1250 | if (work_done < budget) { | |
288379f0 | 1251 | napi_complete(napi); |
509ee935 | 1252 | if (adapter->itr_setting & 1) |
f494e8fa | 1253 | ixgbe_set_itr_msix(q_vector); |
9a799d71 | 1254 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
835462fc | 1255 | ixgbe_irq_enable_queues(adapter, rx_ring->v_idx); |
9a799d71 AK |
1256 | } |
1257 | ||
1258 | return work_done; | |
1259 | } | |
1260 | ||
f0848276 JB |
1261 | /** |
1262 | * ixgbe_clean_rxonly_many - msix (aka one shot) rx clean routine | |
1263 | * @napi: napi struct with our devices info in it | |
1264 | * @budget: amount of work driver is allowed to do this pass, in packets | |
1265 | * | |
1266 | * This function will clean more than one rx queue associated with a | |
1267 | * q_vector. | |
1268 | **/ | |
1269 | static int ixgbe_clean_rxonly_many(struct napi_struct *napi, int budget) | |
1270 | { | |
1271 | struct ixgbe_q_vector *q_vector = | |
1272 | container_of(napi, struct ixgbe_q_vector, napi); | |
1273 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
f0848276 JB |
1274 | struct ixgbe_ring *rx_ring = NULL; |
1275 | int work_done = 0, i; | |
1276 | long r_idx; | |
835462fc | 1277 | u64 enable_mask = 0; |
f0848276 JB |
1278 | |
1279 | /* attempt to distribute budget to each queue fairly, but don't allow | |
1280 | * the budget to go below 1 because we'll exit polling */ | |
1281 | budget /= (q_vector->rxr_count ?: 1); | |
1282 | budget = max(budget, 1); | |
1283 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
1284 | for (i = 0; i < q_vector->rxr_count; i++) { | |
1285 | rx_ring = &(adapter->rx_ring[r_idx]); | |
5dd2d332 | 1286 | #ifdef CONFIG_IXGBE_DCA |
f0848276 JB |
1287 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) |
1288 | ixgbe_update_rx_dca(adapter, rx_ring); | |
1289 | #endif | |
78b6f4ce | 1290 | ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget); |
f0848276 JB |
1291 | enable_mask |= rx_ring->v_idx; |
1292 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, | |
1293 | r_idx + 1); | |
1294 | } | |
1295 | ||
1296 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
1297 | rx_ring = &(adapter->rx_ring[r_idx]); | |
1298 | /* If all Rx work done, exit the polling mode */ | |
7f821875 | 1299 | if (work_done < budget) { |
288379f0 | 1300 | napi_complete(napi); |
509ee935 | 1301 | if (adapter->itr_setting & 1) |
f0848276 JB |
1302 | ixgbe_set_itr_msix(q_vector); |
1303 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
835462fc | 1304 | ixgbe_irq_enable_queues(adapter, enable_mask); |
f0848276 JB |
1305 | return 0; |
1306 | } | |
1307 | ||
1308 | return work_done; | |
1309 | } | |
021230d4 | 1310 | static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx, |
b4617240 | 1311 | int r_idx) |
021230d4 | 1312 | { |
7a921c93 AD |
1313 | struct ixgbe_q_vector *q_vector = a->q_vector[v_idx]; |
1314 | ||
1315 | set_bit(r_idx, q_vector->rxr_idx); | |
1316 | q_vector->rxr_count++; | |
c9c7d2e5 | 1317 | a->rx_ring[r_idx].v_idx = (u64)1 << v_idx; |
021230d4 AV |
1318 | } |
1319 | ||
1320 | static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx, | |
7a921c93 | 1321 | int t_idx) |
021230d4 | 1322 | { |
7a921c93 AD |
1323 | struct ixgbe_q_vector *q_vector = a->q_vector[v_idx]; |
1324 | ||
1325 | set_bit(t_idx, q_vector->txr_idx); | |
1326 | q_vector->txr_count++; | |
c9c7d2e5 | 1327 | a->tx_ring[t_idx].v_idx = (u64)1 << v_idx; |
021230d4 AV |
1328 | } |
1329 | ||
9a799d71 | 1330 | /** |
021230d4 AV |
1331 | * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors |
1332 | * @adapter: board private structure to initialize | |
1333 | * @vectors: allotted vector count for descriptor rings | |
9a799d71 | 1334 | * |
021230d4 AV |
1335 | * This function maps descriptor rings to the queue-specific vectors |
1336 | * we were allotted through the MSI-X enabling code. Ideally, we'd have | |
1337 | * one vector per ring/queue, but on a constrained vector budget, we | |
1338 | * group the rings as "efficiently" as possible. You would add new | |
1339 | * mapping configurations in here. | |
9a799d71 | 1340 | **/ |
021230d4 | 1341 | static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter, |
b4617240 | 1342 | int vectors) |
021230d4 AV |
1343 | { |
1344 | int v_start = 0; | |
1345 | int rxr_idx = 0, txr_idx = 0; | |
1346 | int rxr_remaining = adapter->num_rx_queues; | |
1347 | int txr_remaining = adapter->num_tx_queues; | |
1348 | int i, j; | |
1349 | int rqpv, tqpv; | |
1350 | int err = 0; | |
1351 | ||
1352 | /* No mapping required if MSI-X is disabled. */ | |
1353 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
1354 | goto out; | |
9a799d71 | 1355 | |
021230d4 AV |
1356 | /* |
1357 | * The ideal configuration... | |
1358 | * We have enough vectors to map one per queue. | |
1359 | */ | |
1360 | if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) { | |
1361 | for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++) | |
1362 | map_vector_to_rxq(adapter, v_start, rxr_idx); | |
9a799d71 | 1363 | |
021230d4 AV |
1364 | for (; txr_idx < txr_remaining; v_start++, txr_idx++) |
1365 | map_vector_to_txq(adapter, v_start, txr_idx); | |
9a799d71 | 1366 | |
9a799d71 | 1367 | goto out; |
021230d4 | 1368 | } |
9a799d71 | 1369 | |
021230d4 AV |
1370 | /* |
1371 | * If we don't have enough vectors for a 1-to-1 | |
1372 | * mapping, we'll have to group them so there are | |
1373 | * multiple queues per vector. | |
1374 | */ | |
1375 | /* Re-adjusting *qpv takes care of the remainder. */ | |
1376 | for (i = v_start; i < vectors; i++) { | |
1377 | rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i); | |
1378 | for (j = 0; j < rqpv; j++) { | |
1379 | map_vector_to_rxq(adapter, i, rxr_idx); | |
1380 | rxr_idx++; | |
1381 | rxr_remaining--; | |
1382 | } | |
1383 | } | |
1384 | for (i = v_start; i < vectors; i++) { | |
1385 | tqpv = DIV_ROUND_UP(txr_remaining, vectors - i); | |
1386 | for (j = 0; j < tqpv; j++) { | |
1387 | map_vector_to_txq(adapter, i, txr_idx); | |
1388 | txr_idx++; | |
1389 | txr_remaining--; | |
9a799d71 | 1390 | } |
9a799d71 AK |
1391 | } |
1392 | ||
021230d4 AV |
1393 | out: |
1394 | return err; | |
1395 | } | |
1396 | ||
1397 | /** | |
1398 | * ixgbe_request_msix_irqs - Initialize MSI-X interrupts | |
1399 | * @adapter: board private structure | |
1400 | * | |
1401 | * ixgbe_request_msix_irqs allocates MSI-X vectors and requests | |
1402 | * interrupts from the kernel. | |
1403 | **/ | |
1404 | static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter) | |
1405 | { | |
1406 | struct net_device *netdev = adapter->netdev; | |
1407 | irqreturn_t (*handler)(int, void *); | |
1408 | int i, vector, q_vectors, err; | |
cb13fc20 | 1409 | int ri=0, ti=0; |
021230d4 AV |
1410 | |
1411 | /* Decrement for Other and TCP Timer vectors */ | |
1412 | q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
1413 | ||
1414 | /* Map the Tx/Rx rings to the vectors we were allotted. */ | |
1415 | err = ixgbe_map_rings_to_vectors(adapter, q_vectors); | |
1416 | if (err) | |
1417 | goto out; | |
1418 | ||
1419 | #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \ | |
b4617240 PW |
1420 | (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \ |
1421 | &ixgbe_msix_clean_many) | |
021230d4 | 1422 | for (vector = 0; vector < q_vectors; vector++) { |
7a921c93 | 1423 | handler = SET_HANDLER(adapter->q_vector[vector]); |
cb13fc20 RO |
1424 | |
1425 | if(handler == &ixgbe_msix_clean_rx) { | |
1426 | sprintf(adapter->name[vector], "%s-%s-%d", | |
1427 | netdev->name, "rx", ri++); | |
1428 | } | |
1429 | else if(handler == &ixgbe_msix_clean_tx) { | |
1430 | sprintf(adapter->name[vector], "%s-%s-%d", | |
1431 | netdev->name, "tx", ti++); | |
1432 | } | |
1433 | else | |
1434 | sprintf(adapter->name[vector], "%s-%s-%d", | |
1435 | netdev->name, "TxRx", vector); | |
1436 | ||
021230d4 | 1437 | err = request_irq(adapter->msix_entries[vector].vector, |
b4617240 | 1438 | handler, 0, adapter->name[vector], |
7a921c93 | 1439 | adapter->q_vector[vector]); |
9a799d71 AK |
1440 | if (err) { |
1441 | DPRINTK(PROBE, ERR, | |
b4617240 PW |
1442 | "request_irq failed for MSIX interrupt " |
1443 | "Error: %d\n", err); | |
021230d4 | 1444 | goto free_queue_irqs; |
9a799d71 | 1445 | } |
9a799d71 AK |
1446 | } |
1447 | ||
021230d4 AV |
1448 | sprintf(adapter->name[vector], "%s:lsc", netdev->name); |
1449 | err = request_irq(adapter->msix_entries[vector].vector, | |
b4617240 | 1450 | &ixgbe_msix_lsc, 0, adapter->name[vector], netdev); |
9a799d71 AK |
1451 | if (err) { |
1452 | DPRINTK(PROBE, ERR, | |
1453 | "request_irq for msix_lsc failed: %d\n", err); | |
021230d4 | 1454 | goto free_queue_irqs; |
9a799d71 AK |
1455 | } |
1456 | ||
9a799d71 AK |
1457 | return 0; |
1458 | ||
021230d4 AV |
1459 | free_queue_irqs: |
1460 | for (i = vector - 1; i >= 0; i--) | |
1461 | free_irq(adapter->msix_entries[--vector].vector, | |
7a921c93 | 1462 | adapter->q_vector[i]); |
021230d4 AV |
1463 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; |
1464 | pci_disable_msix(adapter->pdev); | |
9a799d71 AK |
1465 | kfree(adapter->msix_entries); |
1466 | adapter->msix_entries = NULL; | |
021230d4 | 1467 | out: |
9a799d71 AK |
1468 | return err; |
1469 | } | |
1470 | ||
f494e8fa AV |
1471 | static void ixgbe_set_itr(struct ixgbe_adapter *adapter) |
1472 | { | |
7a921c93 | 1473 | struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; |
f494e8fa AV |
1474 | u8 current_itr; |
1475 | u32 new_itr = q_vector->eitr; | |
1476 | struct ixgbe_ring *rx_ring = &adapter->rx_ring[0]; | |
1477 | struct ixgbe_ring *tx_ring = &adapter->tx_ring[0]; | |
1478 | ||
30efa5a3 | 1479 | q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr, |
b4617240 PW |
1480 | q_vector->tx_itr, |
1481 | tx_ring->total_packets, | |
1482 | tx_ring->total_bytes); | |
30efa5a3 | 1483 | q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr, |
b4617240 PW |
1484 | q_vector->rx_itr, |
1485 | rx_ring->total_packets, | |
1486 | rx_ring->total_bytes); | |
f494e8fa | 1487 | |
30efa5a3 | 1488 | current_itr = max(q_vector->rx_itr, q_vector->tx_itr); |
f494e8fa AV |
1489 | |
1490 | switch (current_itr) { | |
1491 | /* counts and packets in update_itr are dependent on these numbers */ | |
1492 | case lowest_latency: | |
1493 | new_itr = 100000; | |
1494 | break; | |
1495 | case low_latency: | |
1496 | new_itr = 20000; /* aka hwitr = ~200 */ | |
1497 | break; | |
1498 | case bulk_latency: | |
1499 | new_itr = 8000; | |
1500 | break; | |
1501 | default: | |
1502 | break; | |
1503 | } | |
1504 | ||
1505 | if (new_itr != q_vector->eitr) { | |
1506 | u32 itr_reg; | |
509ee935 JB |
1507 | |
1508 | /* save the algorithm value here, not the smoothed one */ | |
1509 | q_vector->eitr = new_itr; | |
f494e8fa AV |
1510 | /* do an exponential smoothing */ |
1511 | new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100); | |
f494e8fa | 1512 | itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr); |
509ee935 | 1513 | ixgbe_write_eitr(adapter, 0, itr_reg); |
f494e8fa AV |
1514 | } |
1515 | ||
1516 | return; | |
1517 | } | |
1518 | ||
79aefa45 AD |
1519 | /** |
1520 | * ixgbe_irq_enable - Enable default interrupt generation settings | |
1521 | * @adapter: board private structure | |
1522 | **/ | |
1523 | static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter) | |
1524 | { | |
1525 | u32 mask; | |
835462fc NS |
1526 | |
1527 | mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE); | |
6ab33d51 DM |
1528 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) |
1529 | mask |= IXGBE_EIMS_GPI_SDP1; | |
e8e26350 | 1530 | if (adapter->hw.mac.type == ixgbe_mac_82599EB) { |
2a41ff81 | 1531 | mask |= IXGBE_EIMS_ECC; |
e8e26350 PW |
1532 | mask |= IXGBE_EIMS_GPI_SDP1; |
1533 | mask |= IXGBE_EIMS_GPI_SDP2; | |
1534 | } | |
1535 | ||
79aefa45 | 1536 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); |
835462fc | 1537 | ixgbe_irq_enable_queues(adapter, ~0); |
79aefa45 AD |
1538 | IXGBE_WRITE_FLUSH(&adapter->hw); |
1539 | } | |
021230d4 | 1540 | |
9a799d71 | 1541 | /** |
021230d4 | 1542 | * ixgbe_intr - legacy mode Interrupt Handler |
9a799d71 AK |
1543 | * @irq: interrupt number |
1544 | * @data: pointer to a network interface device structure | |
9a799d71 AK |
1545 | **/ |
1546 | static irqreturn_t ixgbe_intr(int irq, void *data) | |
1547 | { | |
1548 | struct net_device *netdev = data; | |
1549 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
1550 | struct ixgbe_hw *hw = &adapter->hw; | |
7a921c93 | 1551 | struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; |
9a799d71 AK |
1552 | u32 eicr; |
1553 | ||
54037505 DS |
1554 | /* |
1555 | * Workaround for silicon errata. Mask the interrupts | |
1556 | * before the read of EICR. | |
1557 | */ | |
1558 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); | |
1559 | ||
021230d4 AV |
1560 | /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read |
1561 | * therefore no explict interrupt disable is necessary */ | |
1562 | eicr = IXGBE_READ_REG(hw, IXGBE_EICR); | |
f47cf66e JB |
1563 | if (!eicr) { |
1564 | /* shared interrupt alert! | |
1565 | * make sure interrupts are enabled because the read will | |
1566 | * have disabled interrupts due to EIAM */ | |
1567 | ixgbe_irq_enable(adapter); | |
9a799d71 | 1568 | return IRQ_NONE; /* Not our interrupt */ |
f47cf66e | 1569 | } |
9a799d71 | 1570 | |
cf8280ee JB |
1571 | if (eicr & IXGBE_EICR_LSC) |
1572 | ixgbe_check_lsc(adapter); | |
021230d4 | 1573 | |
e8e26350 PW |
1574 | if (hw->mac.type == ixgbe_mac_82599EB) |
1575 | ixgbe_check_sfp_event(adapter, eicr); | |
1576 | ||
0befdb3e JB |
1577 | ixgbe_check_fan_failure(adapter, eicr); |
1578 | ||
7a921c93 | 1579 | if (napi_schedule_prep(&(q_vector->napi))) { |
f494e8fa AV |
1580 | adapter->tx_ring[0].total_packets = 0; |
1581 | adapter->tx_ring[0].total_bytes = 0; | |
1582 | adapter->rx_ring[0].total_packets = 0; | |
1583 | adapter->rx_ring[0].total_bytes = 0; | |
021230d4 | 1584 | /* would disable interrupts here but EIAM disabled it */ |
7a921c93 | 1585 | __napi_schedule(&(q_vector->napi)); |
9a799d71 AK |
1586 | } |
1587 | ||
1588 | return IRQ_HANDLED; | |
1589 | } | |
1590 | ||
021230d4 AV |
1591 | static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter) |
1592 | { | |
1593 | int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
1594 | ||
1595 | for (i = 0; i < q_vectors; i++) { | |
7a921c93 | 1596 | struct ixgbe_q_vector *q_vector = adapter->q_vector[i]; |
021230d4 AV |
1597 | bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES); |
1598 | bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES); | |
1599 | q_vector->rxr_count = 0; | |
1600 | q_vector->txr_count = 0; | |
1601 | } | |
1602 | } | |
1603 | ||
9a799d71 AK |
1604 | /** |
1605 | * ixgbe_request_irq - initialize interrupts | |
1606 | * @adapter: board private structure | |
1607 | * | |
1608 | * Attempts to configure interrupts using the best available | |
1609 | * capabilities of the hardware and kernel. | |
1610 | **/ | |
021230d4 | 1611 | static int ixgbe_request_irq(struct ixgbe_adapter *adapter) |
9a799d71 AK |
1612 | { |
1613 | struct net_device *netdev = adapter->netdev; | |
021230d4 | 1614 | int err; |
9a799d71 | 1615 | |
021230d4 AV |
1616 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
1617 | err = ixgbe_request_msix_irqs(adapter); | |
1618 | } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) { | |
1619 | err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0, | |
b4617240 | 1620 | netdev->name, netdev); |
021230d4 AV |
1621 | } else { |
1622 | err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED, | |
b4617240 | 1623 | netdev->name, netdev); |
9a799d71 AK |
1624 | } |
1625 | ||
9a799d71 AK |
1626 | if (err) |
1627 | DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err); | |
1628 | ||
9a799d71 AK |
1629 | return err; |
1630 | } | |
1631 | ||
1632 | static void ixgbe_free_irq(struct ixgbe_adapter *adapter) | |
1633 | { | |
1634 | struct net_device *netdev = adapter->netdev; | |
1635 | ||
1636 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
021230d4 | 1637 | int i, q_vectors; |
9a799d71 | 1638 | |
021230d4 AV |
1639 | q_vectors = adapter->num_msix_vectors; |
1640 | ||
1641 | i = q_vectors - 1; | |
9a799d71 | 1642 | free_irq(adapter->msix_entries[i].vector, netdev); |
9a799d71 | 1643 | |
021230d4 AV |
1644 | i--; |
1645 | for (; i >= 0; i--) { | |
1646 | free_irq(adapter->msix_entries[i].vector, | |
7a921c93 | 1647 | adapter->q_vector[i]); |
021230d4 AV |
1648 | } |
1649 | ||
1650 | ixgbe_reset_q_vectors(adapter); | |
1651 | } else { | |
1652 | free_irq(adapter->pdev->irq, netdev); | |
9a799d71 AK |
1653 | } |
1654 | } | |
1655 | ||
22d5a71b JB |
1656 | /** |
1657 | * ixgbe_irq_disable - Mask off interrupt generation on the NIC | |
1658 | * @adapter: board private structure | |
1659 | **/ | |
1660 | static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) | |
1661 | { | |
835462fc NS |
1662 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
1663 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); | |
1664 | } else { | |
1665 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000); | |
1666 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0); | |
22d5a71b | 1667 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0); |
22d5a71b JB |
1668 | } |
1669 | IXGBE_WRITE_FLUSH(&adapter->hw); | |
1670 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
1671 | int i; | |
1672 | for (i = 0; i < adapter->num_msix_vectors; i++) | |
1673 | synchronize_irq(adapter->msix_entries[i].vector); | |
1674 | } else { | |
1675 | synchronize_irq(adapter->pdev->irq); | |
1676 | } | |
1677 | } | |
1678 | ||
9a799d71 AK |
1679 | /** |
1680 | * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts | |
1681 | * | |
1682 | **/ | |
1683 | static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter) | |
1684 | { | |
9a799d71 AK |
1685 | struct ixgbe_hw *hw = &adapter->hw; |
1686 | ||
021230d4 | 1687 | IXGBE_WRITE_REG(hw, IXGBE_EITR(0), |
30efa5a3 | 1688 | EITR_INTS_PER_SEC_TO_REG(adapter->eitr_param)); |
9a799d71 | 1689 | |
e8e26350 PW |
1690 | ixgbe_set_ivar(adapter, 0, 0, 0); |
1691 | ixgbe_set_ivar(adapter, 1, 0, 0); | |
021230d4 AV |
1692 | |
1693 | map_vector_to_rxq(adapter, 0, 0); | |
1694 | map_vector_to_txq(adapter, 0, 0); | |
1695 | ||
1696 | DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n"); | |
9a799d71 AK |
1697 | } |
1698 | ||
1699 | /** | |
3a581073 | 1700 | * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset |
9a799d71 AK |
1701 | * @adapter: board private structure |
1702 | * | |
1703 | * Configure the Tx unit of the MAC after a reset. | |
1704 | **/ | |
1705 | static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) | |
1706 | { | |
12207e49 | 1707 | u64 tdba; |
9a799d71 | 1708 | struct ixgbe_hw *hw = &adapter->hw; |
021230d4 | 1709 | u32 i, j, tdlen, txctrl; |
9a799d71 AK |
1710 | |
1711 | /* Setup the HW Tx Head and Tail descriptor pointers */ | |
1712 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
e01c31a5 JB |
1713 | struct ixgbe_ring *ring = &adapter->tx_ring[i]; |
1714 | j = ring->reg_idx; | |
1715 | tdba = ring->dma; | |
1716 | tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc); | |
021230d4 | 1717 | IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j), |
284901a9 | 1718 | (tdba & DMA_BIT_MASK(32))); |
021230d4 AV |
1719 | IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32)); |
1720 | IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen); | |
1721 | IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0); | |
1722 | IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0); | |
1723 | adapter->tx_ring[i].head = IXGBE_TDH(j); | |
1724 | adapter->tx_ring[i].tail = IXGBE_TDT(j); | |
1725 | /* Disable Tx Head Writeback RO bit, since this hoses | |
1726 | * bookkeeping if things aren't delivered in order. | |
1727 | */ | |
e01c31a5 | 1728 | txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j)); |
021230d4 | 1729 | txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN; |
e01c31a5 | 1730 | IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl); |
9a799d71 | 1731 | } |
e8e26350 PW |
1732 | if (hw->mac.type == ixgbe_mac_82599EB) { |
1733 | /* We enable 8 traffic classes, DCB only */ | |
1734 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) | |
1735 | IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA | | |
1736 | IXGBE_MTQC_8TC_8TQ)); | |
1737 | } | |
9a799d71 AK |
1738 | } |
1739 | ||
e8e26350 | 1740 | #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 |
cc41ac7c JB |
1741 | |
1742 | static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, int index) | |
1743 | { | |
1744 | struct ixgbe_ring *rx_ring; | |
1745 | u32 srrctl; | |
e8e26350 | 1746 | int queue0 = 0; |
3be1adfb AD |
1747 | unsigned long mask; |
1748 | ||
e8e26350 | 1749 | if (adapter->hw.mac.type == ixgbe_mac_82599EB) { |
163de42e AD |
1750 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { |
1751 | int dcb_i = adapter->ring_feature[RING_F_DCB].indices; | |
1752 | if (dcb_i == 8) | |
1753 | queue0 = index >> 4; | |
1754 | else if (dcb_i == 4) | |
1755 | queue0 = index >> 5; | |
1756 | else | |
1757 | dev_err(&adapter->pdev->dev, "Invalid DCB " | |
1758 | "configuration\n"); | |
1759 | } else { | |
1760 | queue0 = index; | |
1761 | } | |
cc41ac7c | 1762 | } else { |
3be1adfb AD |
1763 | mask = (unsigned long) adapter->ring_feature[RING_F_RSS].mask; |
1764 | queue0 = index & mask; | |
1765 | index = index & mask; | |
cc41ac7c | 1766 | } |
3be1adfb | 1767 | |
cc41ac7c JB |
1768 | rx_ring = &adapter->rx_ring[queue0]; |
1769 | ||
1770 | srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index)); | |
1771 | ||
1772 | srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK; | |
1773 | srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK; | |
1774 | ||
afafd5b0 AD |
1775 | srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) & |
1776 | IXGBE_SRRCTL_BSIZEHDR_MASK; | |
1777 | ||
cc41ac7c | 1778 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { |
afafd5b0 AD |
1779 | #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER |
1780 | srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
1781 | #else | |
1782 | srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
1783 | #endif | |
cc41ac7c | 1784 | srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS; |
cc41ac7c | 1785 | } else { |
afafd5b0 AD |
1786 | srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >> |
1787 | IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
cc41ac7c | 1788 | srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; |
cc41ac7c | 1789 | } |
e8e26350 | 1790 | |
cc41ac7c JB |
1791 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl); |
1792 | } | |
9a799d71 | 1793 | |
9a799d71 | 1794 | /** |
3a581073 | 1795 | * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset |
9a799d71 AK |
1796 | * @adapter: board private structure |
1797 | * | |
1798 | * Configure the Rx unit of the MAC after a reset. | |
1799 | **/ | |
1800 | static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) | |
1801 | { | |
1802 | u64 rdba; | |
1803 | struct ixgbe_hw *hw = &adapter->hw; | |
1804 | struct net_device *netdev = adapter->netdev; | |
1805 | int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; | |
021230d4 | 1806 | int i, j; |
9a799d71 | 1807 | u32 rdlen, rxctrl, rxcsum; |
7c6e0a43 JB |
1808 | static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D, |
1809 | 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE, | |
1810 | 0x6A3E67EA, 0x14364D17, 0x3BED200D}; | |
9a799d71 | 1811 | u32 fctrl, hlreg0; |
509ee935 | 1812 | u32 reta = 0, mrqc = 0; |
cc41ac7c | 1813 | u32 rdrxctl; |
f8212f97 | 1814 | u32 rscctrl; |
7c6e0a43 | 1815 | int rx_buf_len; |
9a799d71 AK |
1816 | |
1817 | /* Decide whether to use packet split mode or not */ | |
762f4c57 | 1818 | adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED; |
9a799d71 | 1819 | |
eacd73f7 YZ |
1820 | #ifdef IXGBE_FCOE |
1821 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) | |
1822 | adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED; | |
1823 | #endif /* IXGBE_FCOE */ | |
1824 | ||
9a799d71 AK |
1825 | /* Set the RX buffer length according to the mode */ |
1826 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { | |
7c6e0a43 | 1827 | rx_buf_len = IXGBE_RX_HDR_SIZE; |
e8e26350 PW |
1828 | if (hw->mac.type == ixgbe_mac_82599EB) { |
1829 | /* PSRTYPE must be initialized in 82599 */ | |
1830 | u32 psrtype = IXGBE_PSRTYPE_TCPHDR | | |
1831 | IXGBE_PSRTYPE_UDPHDR | | |
1832 | IXGBE_PSRTYPE_IPV4HDR | | |
dfa12f05 YZ |
1833 | IXGBE_PSRTYPE_IPV6HDR | |
1834 | IXGBE_PSRTYPE_L2HDR; | |
e8e26350 PW |
1835 | IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype); |
1836 | } | |
9a799d71 | 1837 | } else { |
f8212f97 AD |
1838 | if (!(adapter->flags & IXGBE_FLAG_RSC_ENABLED) && |
1839 | (netdev->mtu <= ETH_DATA_LEN)) | |
7c6e0a43 | 1840 | rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE; |
9a799d71 | 1841 | else |
7c6e0a43 | 1842 | rx_buf_len = ALIGN(max_frame, 1024); |
9a799d71 AK |
1843 | } |
1844 | ||
1845 | fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL); | |
1846 | fctrl |= IXGBE_FCTRL_BAM; | |
021230d4 | 1847 | fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */ |
e8e26350 | 1848 | fctrl |= IXGBE_FCTRL_PMCF; |
9a799d71 AK |
1849 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl); |
1850 | ||
1851 | hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); | |
1852 | if (adapter->netdev->mtu <= ETH_DATA_LEN) | |
1853 | hlreg0 &= ~IXGBE_HLREG0_JUMBOEN; | |
1854 | else | |
1855 | hlreg0 |= IXGBE_HLREG0_JUMBOEN; | |
1856 | IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); | |
1857 | ||
9a799d71 AK |
1858 | rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc); |
1859 | /* disable receives while setting up the descriptors */ | |
1860 | rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); | |
1861 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); | |
1862 | ||
1863 | /* Setup the HW Rx Head and Tail Descriptor Pointers and | |
1864 | * the Base and Length of the Rx Descriptor Ring */ | |
1865 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
1866 | rdba = adapter->rx_ring[i].dma; | |
7c6e0a43 | 1867 | j = adapter->rx_ring[i].reg_idx; |
284901a9 | 1868 | IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32))); |
7c6e0a43 JB |
1869 | IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32)); |
1870 | IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen); | |
1871 | IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0); | |
1872 | IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0); | |
1873 | adapter->rx_ring[i].head = IXGBE_RDH(j); | |
1874 | adapter->rx_ring[i].tail = IXGBE_RDT(j); | |
1875 | adapter->rx_ring[i].rx_buf_len = rx_buf_len; | |
cc41ac7c JB |
1876 | |
1877 | ixgbe_configure_srrctl(adapter, j); | |
9a799d71 AK |
1878 | } |
1879 | ||
e8e26350 PW |
1880 | if (hw->mac.type == ixgbe_mac_82598EB) { |
1881 | /* | |
1882 | * For VMDq support of different descriptor types or | |
1883 | * buffer sizes through the use of multiple SRRCTL | |
1884 | * registers, RDRXCTL.MVMEN must be set to 1 | |
1885 | * | |
1886 | * also, the manual doesn't mention it clearly but DCA hints | |
1887 | * will only use queue 0's tags unless this bit is set. Side | |
1888 | * effects of setting this bit are only that SRRCTL must be | |
1889 | * fully programmed [0..15] | |
1890 | */ | |
2a41ff81 JB |
1891 | rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); |
1892 | rdrxctl |= IXGBE_RDRXCTL_MVMEN; | |
1893 | IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); | |
2f90b865 | 1894 | } |
177db6ff | 1895 | |
e8e26350 PW |
1896 | /* Program MRQC for the distribution of queues */ |
1897 | if (hw->mac.type == ixgbe_mac_82599EB) { | |
1898 | int mask = adapter->flags & ( | |
1899 | IXGBE_FLAG_RSS_ENABLED | |
1900 | | IXGBE_FLAG_DCB_ENABLED | |
1901 | ); | |
1902 | ||
1903 | switch (mask) { | |
1904 | case (IXGBE_FLAG_RSS_ENABLED): | |
1905 | mrqc = IXGBE_MRQC_RSSEN; | |
1906 | break; | |
1907 | case (IXGBE_FLAG_DCB_ENABLED): | |
1908 | mrqc = IXGBE_MRQC_RT8TCEN; | |
1909 | break; | |
1910 | default: | |
1911 | break; | |
1912 | } | |
1913 | } | |
021230d4 | 1914 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { |
9a799d71 | 1915 | /* Fill out redirection table */ |
021230d4 AV |
1916 | for (i = 0, j = 0; i < 128; i++, j++) { |
1917 | if (j == adapter->ring_feature[RING_F_RSS].indices) | |
1918 | j = 0; | |
1919 | /* reta = 4-byte sliding window of | |
1920 | * 0x00..(indices-1)(indices-1)00..etc. */ | |
1921 | reta = (reta << 8) | (j * 0x11); | |
1922 | if ((i & 3) == 3) | |
1923 | IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); | |
9a799d71 AK |
1924 | } |
1925 | ||
1926 | /* Fill out hash function seeds */ | |
1927 | for (i = 0; i < 10; i++) | |
7c6e0a43 | 1928 | IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]); |
9a799d71 | 1929 | |
2a41ff81 JB |
1930 | if (hw->mac.type == ixgbe_mac_82598EB) |
1931 | mrqc |= IXGBE_MRQC_RSSEN; | |
9a799d71 | 1932 | /* Perform hash on these packet types */ |
2a41ff81 JB |
1933 | mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 |
1934 | | IXGBE_MRQC_RSS_FIELD_IPV4_TCP | |
1935 | | IXGBE_MRQC_RSS_FIELD_IPV4_UDP | |
1936 | | IXGBE_MRQC_RSS_FIELD_IPV6 | |
1937 | | IXGBE_MRQC_RSS_FIELD_IPV6_TCP | |
1938 | | IXGBE_MRQC_RSS_FIELD_IPV6_UDP; | |
021230d4 | 1939 | } |
2a41ff81 | 1940 | IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); |
9a799d71 | 1941 | |
021230d4 AV |
1942 | rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); |
1943 | ||
1944 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED || | |
1945 | adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) { | |
1946 | /* Disable indicating checksum in descriptor, enables | |
1947 | * RSS hash */ | |
9a799d71 | 1948 | rxcsum |= IXGBE_RXCSUM_PCSD; |
9a799d71 | 1949 | } |
021230d4 AV |
1950 | if (!(rxcsum & IXGBE_RXCSUM_PCSD)) { |
1951 | /* Enable IPv4 payload checksum for UDP fragments | |
1952 | * if PCSD is not set */ | |
1953 | rxcsum |= IXGBE_RXCSUM_IPPCSE; | |
1954 | } | |
1955 | ||
1956 | IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); | |
e8e26350 PW |
1957 | |
1958 | if (hw->mac.type == ixgbe_mac_82599EB) { | |
1959 | rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); | |
1960 | rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP; | |
f8212f97 | 1961 | rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE; |
e8e26350 PW |
1962 | IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); |
1963 | } | |
f8212f97 AD |
1964 | |
1965 | if (adapter->flags & IXGBE_FLAG_RSC_ENABLED) { | |
1966 | /* Enable 82599 HW-RSC */ | |
1967 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
1968 | j = adapter->rx_ring[i].reg_idx; | |
1969 | rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j)); | |
1970 | rscctrl |= IXGBE_RSCCTL_RSCEN; | |
1971 | /* | |
1972 | * if packet split is enabled we can only support up | |
1973 | * to max frags + 1 descriptors. | |
1974 | */ | |
1975 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) | |
1976 | #if (MAX_SKB_FRAGS < 3) | |
1977 | rscctrl |= IXGBE_RSCCTL_MAXDESC_1; | |
1978 | #elif (MAX_SKB_FRAGS < 7) | |
1979 | rscctrl |= IXGBE_RSCCTL_MAXDESC_4; | |
1980 | #elif (MAX_SKB_FRAGS < 15) | |
1981 | rscctrl |= IXGBE_RSCCTL_MAXDESC_8; | |
1982 | #else | |
1983 | rscctrl |= IXGBE_RSCCTL_MAXDESC_16; | |
1984 | #endif | |
1985 | else | |
1986 | rscctrl |= IXGBE_RSCCTL_MAXDESC_16; | |
1987 | IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl); | |
1988 | } | |
1989 | /* Disable RSC for ACK packets */ | |
1990 | IXGBE_WRITE_REG(hw, IXGBE_RSCDBU, | |
1991 | (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU))); | |
1992 | } | |
9a799d71 AK |
1993 | } |
1994 | ||
068c89b0 DS |
1995 | static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid) |
1996 | { | |
1997 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
1998 | struct ixgbe_hw *hw = &adapter->hw; | |
1999 | ||
2000 | /* add VID to filter table */ | |
2001 | hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true); | |
2002 | } | |
2003 | ||
2004 | static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) | |
2005 | { | |
2006 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
2007 | struct ixgbe_hw *hw = &adapter->hw; | |
2008 | ||
2009 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
2010 | ixgbe_irq_disable(adapter); | |
2011 | ||
2012 | vlan_group_set_device(adapter->vlgrp, vid, NULL); | |
2013 | ||
2014 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
2015 | ixgbe_irq_enable(adapter); | |
2016 | ||
2017 | /* remove VID from filter table */ | |
2018 | hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false); | |
2019 | } | |
2020 | ||
9a799d71 | 2021 | static void ixgbe_vlan_rx_register(struct net_device *netdev, |
b4617240 | 2022 | struct vlan_group *grp) |
9a799d71 AK |
2023 | { |
2024 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
2025 | u32 ctrl; | |
e8e26350 | 2026 | int i, j; |
9a799d71 | 2027 | |
d4f80882 AV |
2028 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
2029 | ixgbe_irq_disable(adapter); | |
9a799d71 AK |
2030 | adapter->vlgrp = grp; |
2031 | ||
2f90b865 AD |
2032 | /* |
2033 | * For a DCB driver, always enable VLAN tag stripping so we can | |
2034 | * still receive traffic from a DCB-enabled host even if we're | |
2035 | * not in DCB mode. | |
2036 | */ | |
2037 | ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL); | |
e8e26350 PW |
2038 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
2039 | ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE; | |
2040 | ctrl &= ~IXGBE_VLNCTRL_CFIEN; | |
2041 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl); | |
2042 | } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { | |
2043 | ctrl |= IXGBE_VLNCTRL_VFE; | |
9a799d71 AK |
2044 | /* enable VLAN tag insert/strip */ |
2045 | ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL); | |
9a799d71 AK |
2046 | ctrl &= ~IXGBE_VLNCTRL_CFIEN; |
2047 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl); | |
e8e26350 PW |
2048 | for (i = 0; i < adapter->num_rx_queues; i++) { |
2049 | j = adapter->rx_ring[i].reg_idx; | |
2050 | ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j)); | |
2051 | ctrl |= IXGBE_RXDCTL_VME; | |
2052 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl); | |
2053 | } | |
9a799d71 | 2054 | } |
e8e26350 | 2055 | ixgbe_vlan_rx_add_vid(netdev, 0); |
9a799d71 | 2056 | |
d4f80882 AV |
2057 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
2058 | ixgbe_irq_enable(adapter); | |
9a799d71 AK |
2059 | } |
2060 | ||
9a799d71 AK |
2061 | static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter) |
2062 | { | |
2063 | ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp); | |
2064 | ||
2065 | if (adapter->vlgrp) { | |
2066 | u16 vid; | |
2067 | for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) { | |
2068 | if (!vlan_group_get_device(adapter->vlgrp, vid)) | |
2069 | continue; | |
2070 | ixgbe_vlan_rx_add_vid(adapter->netdev, vid); | |
2071 | } | |
2072 | } | |
2073 | } | |
2074 | ||
2c5645cf CL |
2075 | static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq) |
2076 | { | |
2077 | struct dev_mc_list *mc_ptr; | |
2078 | u8 *addr = *mc_addr_ptr; | |
2079 | *vmdq = 0; | |
2080 | ||
2081 | mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]); | |
2082 | if (mc_ptr->next) | |
2083 | *mc_addr_ptr = mc_ptr->next->dmi_addr; | |
2084 | else | |
2085 | *mc_addr_ptr = NULL; | |
2086 | ||
2087 | return addr; | |
2088 | } | |
2089 | ||
9a799d71 | 2090 | /** |
2c5645cf | 2091 | * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set |
9a799d71 AK |
2092 | * @netdev: network interface device structure |
2093 | * | |
2c5645cf CL |
2094 | * The set_rx_method entry point is called whenever the unicast/multicast |
2095 | * address list or the network interface flags are updated. This routine is | |
2096 | * responsible for configuring the hardware for proper unicast, multicast and | |
2097 | * promiscuous mode. | |
9a799d71 | 2098 | **/ |
2c5645cf | 2099 | static void ixgbe_set_rx_mode(struct net_device *netdev) |
9a799d71 AK |
2100 | { |
2101 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
2102 | struct ixgbe_hw *hw = &adapter->hw; | |
3d01625a | 2103 | u32 fctrl, vlnctrl; |
2c5645cf CL |
2104 | u8 *addr_list = NULL; |
2105 | int addr_count = 0; | |
9a799d71 AK |
2106 | |
2107 | /* Check for Promiscuous and All Multicast modes */ | |
2108 | ||
2109 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
3d01625a | 2110 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); |
9a799d71 AK |
2111 | |
2112 | if (netdev->flags & IFF_PROMISC) { | |
2c5645cf | 2113 | hw->addr_ctrl.user_set_promisc = 1; |
9a799d71 | 2114 | fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); |
3d01625a | 2115 | vlnctrl &= ~IXGBE_VLNCTRL_VFE; |
9a799d71 | 2116 | } else { |
746b9f02 PM |
2117 | if (netdev->flags & IFF_ALLMULTI) { |
2118 | fctrl |= IXGBE_FCTRL_MPE; | |
2119 | fctrl &= ~IXGBE_FCTRL_UPE; | |
2120 | } else { | |
2121 | fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); | |
2122 | } | |
3d01625a | 2123 | vlnctrl |= IXGBE_VLNCTRL_VFE; |
2c5645cf | 2124 | hw->addr_ctrl.user_set_promisc = 0; |
9a799d71 AK |
2125 | } |
2126 | ||
2127 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); | |
3d01625a | 2128 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); |
9a799d71 | 2129 | |
2c5645cf CL |
2130 | /* reprogram secondary unicast list */ |
2131 | addr_count = netdev->uc_count; | |
2132 | if (addr_count) | |
2133 | addr_list = netdev->uc_list->dmi_addr; | |
c44ade9e JB |
2134 | hw->mac.ops.update_uc_addr_list(hw, addr_list, addr_count, |
2135 | ixgbe_addr_list_itr); | |
9a799d71 | 2136 | |
2c5645cf CL |
2137 | /* reprogram multicast list */ |
2138 | addr_count = netdev->mc_count; | |
2139 | if (addr_count) | |
2140 | addr_list = netdev->mc_list->dmi_addr; | |
c44ade9e JB |
2141 | hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count, |
2142 | ixgbe_addr_list_itr); | |
9a799d71 AK |
2143 | } |
2144 | ||
021230d4 AV |
2145 | static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter) |
2146 | { | |
2147 | int q_idx; | |
2148 | struct ixgbe_q_vector *q_vector; | |
2149 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
2150 | ||
2151 | /* legacy and MSI only use one vector */ | |
2152 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
2153 | q_vectors = 1; | |
2154 | ||
2155 | for (q_idx = 0; q_idx < q_vectors; q_idx++) { | |
f0848276 | 2156 | struct napi_struct *napi; |
7a921c93 | 2157 | q_vector = adapter->q_vector[q_idx]; |
021230d4 AV |
2158 | if (!q_vector->rxr_count) |
2159 | continue; | |
f0848276 JB |
2160 | napi = &q_vector->napi; |
2161 | if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) && | |
2162 | (q_vector->rxr_count > 1)) | |
2163 | napi->poll = &ixgbe_clean_rxonly_many; | |
2164 | ||
2165 | napi_enable(napi); | |
021230d4 AV |
2166 | } |
2167 | } | |
2168 | ||
2169 | static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter) | |
2170 | { | |
2171 | int q_idx; | |
2172 | struct ixgbe_q_vector *q_vector; | |
2173 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
2174 | ||
2175 | /* legacy and MSI only use one vector */ | |
2176 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
2177 | q_vectors = 1; | |
2178 | ||
2179 | for (q_idx = 0; q_idx < q_vectors; q_idx++) { | |
7a921c93 | 2180 | q_vector = adapter->q_vector[q_idx]; |
021230d4 AV |
2181 | if (!q_vector->rxr_count) |
2182 | continue; | |
2183 | napi_disable(&q_vector->napi); | |
2184 | } | |
2185 | } | |
2186 | ||
7a6b6f51 | 2187 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
2188 | /* |
2189 | * ixgbe_configure_dcb - Configure DCB hardware | |
2190 | * @adapter: ixgbe adapter struct | |
2191 | * | |
2192 | * This is called by the driver on open to configure the DCB hardware. | |
2193 | * This is also called by the gennetlink interface when reconfiguring | |
2194 | * the DCB state. | |
2195 | */ | |
2196 | static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter) | |
2197 | { | |
2198 | struct ixgbe_hw *hw = &adapter->hw; | |
2199 | u32 txdctl, vlnctrl; | |
2200 | int i, j; | |
2201 | ||
2202 | ixgbe_dcb_check_config(&adapter->dcb_cfg); | |
2203 | ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG); | |
2204 | ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG); | |
2205 | ||
2206 | /* reconfigure the hardware */ | |
2207 | ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg); | |
2208 | ||
2209 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
2210 | j = adapter->tx_ring[i].reg_idx; | |
2211 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)); | |
2212 | /* PThresh workaround for Tx hang with DFP enabled. */ | |
2213 | txdctl |= 32; | |
2214 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl); | |
2215 | } | |
2216 | /* Enable VLAN tag insert/strip */ | |
2217 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); | |
e8e26350 PW |
2218 | if (hw->mac.type == ixgbe_mac_82598EB) { |
2219 | vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE; | |
2220 | vlnctrl &= ~IXGBE_VLNCTRL_CFIEN; | |
2221 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); | |
2222 | } else if (hw->mac.type == ixgbe_mac_82599EB) { | |
2223 | vlnctrl |= IXGBE_VLNCTRL_VFE; | |
2224 | vlnctrl &= ~IXGBE_VLNCTRL_CFIEN; | |
2225 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); | |
2226 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
2227 | j = adapter->rx_ring[i].reg_idx; | |
2228 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); | |
2229 | vlnctrl |= IXGBE_RXDCTL_VME; | |
2230 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); | |
2231 | } | |
2232 | } | |
2f90b865 AD |
2233 | hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true); |
2234 | } | |
2235 | ||
2236 | #endif | |
9a799d71 AK |
2237 | static void ixgbe_configure(struct ixgbe_adapter *adapter) |
2238 | { | |
2239 | struct net_device *netdev = adapter->netdev; | |
2240 | int i; | |
2241 | ||
2c5645cf | 2242 | ixgbe_set_rx_mode(netdev); |
9a799d71 AK |
2243 | |
2244 | ixgbe_restore_vlan(adapter); | |
7a6b6f51 | 2245 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
2246 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { |
2247 | netif_set_gso_max_size(netdev, 32768); | |
2248 | ixgbe_configure_dcb(adapter); | |
2249 | } else { | |
2250 | netif_set_gso_max_size(netdev, 65536); | |
2251 | } | |
2252 | #else | |
2253 | netif_set_gso_max_size(netdev, 65536); | |
2254 | #endif | |
9a799d71 | 2255 | |
eacd73f7 YZ |
2256 | #ifdef IXGBE_FCOE |
2257 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) | |
2258 | ixgbe_configure_fcoe(adapter); | |
2259 | ||
2260 | #endif /* IXGBE_FCOE */ | |
9a799d71 AK |
2261 | ixgbe_configure_tx(adapter); |
2262 | ixgbe_configure_rx(adapter); | |
2263 | for (i = 0; i < adapter->num_rx_queues; i++) | |
2264 | ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i], | |
b4617240 | 2265 | (adapter->rx_ring[i].count - 1)); |
9a799d71 AK |
2266 | } |
2267 | ||
e8e26350 PW |
2268 | static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw) |
2269 | { | |
2270 | switch (hw->phy.type) { | |
2271 | case ixgbe_phy_sfp_avago: | |
2272 | case ixgbe_phy_sfp_ftl: | |
2273 | case ixgbe_phy_sfp_intel: | |
2274 | case ixgbe_phy_sfp_unknown: | |
2275 | case ixgbe_phy_tw_tyco: | |
2276 | case ixgbe_phy_tw_unknown: | |
2277 | return true; | |
2278 | default: | |
2279 | return false; | |
2280 | } | |
2281 | } | |
2282 | ||
0ecc061d | 2283 | /** |
e8e26350 PW |
2284 | * ixgbe_sfp_link_config - set up SFP+ link |
2285 | * @adapter: pointer to private adapter struct | |
2286 | **/ | |
2287 | static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter) | |
2288 | { | |
2289 | struct ixgbe_hw *hw = &adapter->hw; | |
2290 | ||
2291 | if (hw->phy.multispeed_fiber) { | |
2292 | /* | |
2293 | * In multispeed fiber setups, the device may not have | |
2294 | * had a physical connection when the driver loaded. | |
2295 | * If that's the case, the initial link configuration | |
2296 | * couldn't get the MAC into 10G or 1G mode, so we'll | |
2297 | * never have a link status change interrupt fire. | |
2298 | * We need to try and force an autonegotiation | |
2299 | * session, then bring up link. | |
2300 | */ | |
2301 | hw->mac.ops.setup_sfp(hw); | |
2302 | if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK)) | |
2303 | schedule_work(&adapter->multispeed_fiber_task); | |
2304 | } else { | |
2305 | /* | |
2306 | * Direct Attach Cu and non-multispeed fiber modules | |
2307 | * still need to be configured properly prior to | |
2308 | * attempting link. | |
2309 | */ | |
2310 | if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK)) | |
2311 | schedule_work(&adapter->sfp_config_module_task); | |
2312 | } | |
2313 | } | |
2314 | ||
2315 | /** | |
2316 | * ixgbe_non_sfp_link_config - set up non-SFP+ link | |
0ecc061d PWJ |
2317 | * @hw: pointer to private hardware struct |
2318 | * | |
2319 | * Returns 0 on success, negative on failure | |
2320 | **/ | |
e8e26350 | 2321 | static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw) |
0ecc061d PWJ |
2322 | { |
2323 | u32 autoneg; | |
2324 | bool link_up = false; | |
2325 | u32 ret = IXGBE_ERR_LINK_SETUP; | |
2326 | ||
2327 | if (hw->mac.ops.check_link) | |
2328 | ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false); | |
2329 | ||
2330 | if (ret) | |
2331 | goto link_cfg_out; | |
2332 | ||
2333 | if (hw->mac.ops.get_link_capabilities) | |
2334 | ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, | |
2335 | &hw->mac.autoneg); | |
2336 | if (ret) | |
2337 | goto link_cfg_out; | |
2338 | ||
2339 | if (hw->mac.ops.setup_link_speed) | |
2340 | ret = hw->mac.ops.setup_link_speed(hw, autoneg, true, link_up); | |
0ecc061d PWJ |
2341 | link_cfg_out: |
2342 | return ret; | |
2343 | } | |
2344 | ||
e8e26350 PW |
2345 | #define IXGBE_MAX_RX_DESC_POLL 10 |
2346 | static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter, | |
2347 | int rxr) | |
2348 | { | |
2349 | int j = adapter->rx_ring[rxr].reg_idx; | |
2350 | int k; | |
2351 | ||
2352 | for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) { | |
2353 | if (IXGBE_READ_REG(&adapter->hw, | |
2354 | IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE) | |
2355 | break; | |
2356 | else | |
2357 | msleep(1); | |
2358 | } | |
2359 | if (k >= IXGBE_MAX_RX_DESC_POLL) { | |
2360 | DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d " | |
2361 | "not set within the polling period\n", rxr); | |
2362 | } | |
2363 | ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr], | |
2364 | (adapter->rx_ring[rxr].count - 1)); | |
2365 | } | |
2366 | ||
9a799d71 AK |
2367 | static int ixgbe_up_complete(struct ixgbe_adapter *adapter) |
2368 | { | |
2369 | struct net_device *netdev = adapter->netdev; | |
9a799d71 | 2370 | struct ixgbe_hw *hw = &adapter->hw; |
021230d4 | 2371 | int i, j = 0; |
e8e26350 | 2372 | int num_rx_rings = adapter->num_rx_queues; |
0ecc061d | 2373 | int err; |
9a799d71 | 2374 | int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; |
021230d4 | 2375 | u32 txdctl, rxdctl, mhadd; |
e8e26350 | 2376 | u32 dmatxctl; |
021230d4 | 2377 | u32 gpie; |
9a799d71 | 2378 | |
5eba3699 AV |
2379 | ixgbe_get_hw_control(adapter); |
2380 | ||
021230d4 AV |
2381 | if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) || |
2382 | (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) { | |
9a799d71 AK |
2383 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
2384 | gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME | | |
b4617240 | 2385 | IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD); |
9a799d71 AK |
2386 | } else { |
2387 | /* MSI only */ | |
021230d4 | 2388 | gpie = 0; |
9a799d71 | 2389 | } |
021230d4 AV |
2390 | /* XXX: to interrupt immediately for EICS writes, enable this */ |
2391 | /* gpie |= IXGBE_GPIE_EIMEN; */ | |
2392 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
9a799d71 AK |
2393 | } |
2394 | ||
021230d4 AV |
2395 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { |
2396 | /* legacy interrupts, use EIAM to auto-mask when reading EICR, | |
2397 | * specifically only auto mask tx and rx interrupts */ | |
2398 | IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); | |
2399 | } | |
9a799d71 | 2400 | |
0befdb3e JB |
2401 | /* Enable fan failure interrupt if media type is copper */ |
2402 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
2403 | gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); | |
2404 | gpie |= IXGBE_SDP1_GPIEN; | |
2405 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
2406 | } | |
2407 | ||
e8e26350 PW |
2408 | if (hw->mac.type == ixgbe_mac_82599EB) { |
2409 | gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); | |
2410 | gpie |= IXGBE_SDP1_GPIEN; | |
2411 | gpie |= IXGBE_SDP2_GPIEN; | |
2412 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
2413 | } | |
2414 | ||
021230d4 | 2415 | mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); |
9a799d71 AK |
2416 | if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) { |
2417 | mhadd &= ~IXGBE_MHADD_MFS_MASK; | |
2418 | mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT; | |
2419 | ||
2420 | IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); | |
2421 | } | |
2422 | ||
2423 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
021230d4 AV |
2424 | j = adapter->tx_ring[i].reg_idx; |
2425 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)); | |
e01c31a5 JB |
2426 | /* enable WTHRESH=8 descriptors, to encourage burst writeback */ |
2427 | txdctl |= (8 << 16); | |
e8e26350 PW |
2428 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl); |
2429 | } | |
2430 | ||
2431 | if (hw->mac.type == ixgbe_mac_82599EB) { | |
2432 | /* DMATXCTL.EN must be set after all Tx queue config is done */ | |
2433 | dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); | |
2434 | dmatxctl |= IXGBE_DMATXCTL_TE; | |
2435 | IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl); | |
2436 | } | |
2437 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
2438 | j = adapter->tx_ring[i].reg_idx; | |
2439 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)); | |
9a799d71 | 2440 | txdctl |= IXGBE_TXDCTL_ENABLE; |
021230d4 | 2441 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl); |
9a799d71 AK |
2442 | } |
2443 | ||
e8e26350 | 2444 | for (i = 0; i < num_rx_rings; i++) { |
021230d4 AV |
2445 | j = adapter->rx_ring[i].reg_idx; |
2446 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); | |
2447 | /* enable PTHRESH=32 descriptors (half the internal cache) | |
2448 | * and HTHRESH=0 descriptors (to minimize latency on fetch), | |
2449 | * this also removes a pesky rx_no_buffer_count increment */ | |
2450 | rxdctl |= 0x0020; | |
9a799d71 | 2451 | rxdctl |= IXGBE_RXDCTL_ENABLE; |
021230d4 | 2452 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl); |
e8e26350 PW |
2453 | if (hw->mac.type == ixgbe_mac_82599EB) |
2454 | ixgbe_rx_desc_queue_enable(adapter, i); | |
9a799d71 AK |
2455 | } |
2456 | /* enable all receives */ | |
2457 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); | |
e8e26350 PW |
2458 | if (hw->mac.type == ixgbe_mac_82598EB) |
2459 | rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN); | |
2460 | else | |
2461 | rxdctl |= IXGBE_RXCTRL_RXEN; | |
2462 | hw->mac.ops.enable_rx_dma(hw, rxdctl); | |
9a799d71 AK |
2463 | |
2464 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) | |
2465 | ixgbe_configure_msix(adapter); | |
2466 | else | |
2467 | ixgbe_configure_msi_and_legacy(adapter); | |
2468 | ||
2469 | clear_bit(__IXGBE_DOWN, &adapter->state); | |
021230d4 AV |
2470 | ixgbe_napi_enable_all(adapter); |
2471 | ||
2472 | /* clear any pending interrupts, may auto mask */ | |
2473 | IXGBE_READ_REG(hw, IXGBE_EICR); | |
2474 | ||
9a799d71 AK |
2475 | ixgbe_irq_enable(adapter); |
2476 | ||
bf069c97 DS |
2477 | /* |
2478 | * If this adapter has a fan, check to see if we had a failure | |
2479 | * before we enabled the interrupt. | |
2480 | */ | |
2481 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
2482 | u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); | |
2483 | if (esdp & IXGBE_ESDP_SDP1) | |
2484 | DPRINTK(DRV, CRIT, | |
2485 | "Fan has stopped, replace the adapter\n"); | |
2486 | } | |
2487 | ||
e8e26350 PW |
2488 | /* |
2489 | * For hot-pluggable SFP+ devices, a new SFP+ module may have | |
2490 | * arrived before interrupts were enabled. We need to kick off | |
2491 | * the SFP+ module setup first, then try to bring up link. | |
2492 | * If we're not hot-pluggable SFP+, we just need to configure link | |
2493 | * and bring it up. | |
2494 | */ | |
2495 | err = hw->phy.ops.identify(hw); | |
2496 | if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
2497 | DPRINTK(PROBE, ERR, "PHY not supported on this NIC %d\n", err); | |
2498 | ixgbe_down(adapter); | |
2499 | return err; | |
2500 | } | |
2501 | ||
2502 | if (ixgbe_is_sfp(hw)) { | |
2503 | ixgbe_sfp_link_config(adapter); | |
2504 | } else { | |
2505 | err = ixgbe_non_sfp_link_config(hw); | |
2506 | if (err) | |
2507 | DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err); | |
2508 | } | |
0ecc061d | 2509 | |
1da100bb PWJ |
2510 | /* enable transmits */ |
2511 | netif_tx_start_all_queues(netdev); | |
2512 | ||
9a799d71 AK |
2513 | /* bring the link up in the watchdog, this could race with our first |
2514 | * link up interrupt but shouldn't be a problem */ | |
cf8280ee JB |
2515 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; |
2516 | adapter->link_check_timeout = jiffies; | |
9a799d71 AK |
2517 | mod_timer(&adapter->watchdog_timer, jiffies); |
2518 | return 0; | |
2519 | } | |
2520 | ||
d4f80882 AV |
2521 | void ixgbe_reinit_locked(struct ixgbe_adapter *adapter) |
2522 | { | |
2523 | WARN_ON(in_interrupt()); | |
2524 | while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) | |
2525 | msleep(1); | |
2526 | ixgbe_down(adapter); | |
2527 | ixgbe_up(adapter); | |
2528 | clear_bit(__IXGBE_RESETTING, &adapter->state); | |
2529 | } | |
2530 | ||
9a799d71 AK |
2531 | int ixgbe_up(struct ixgbe_adapter *adapter) |
2532 | { | |
2533 | /* hardware has been reset, we need to reload some things */ | |
2534 | ixgbe_configure(adapter); | |
2535 | ||
2536 | return ixgbe_up_complete(adapter); | |
2537 | } | |
2538 | ||
2539 | void ixgbe_reset(struct ixgbe_adapter *adapter) | |
2540 | { | |
c44ade9e JB |
2541 | struct ixgbe_hw *hw = &adapter->hw; |
2542 | if (hw->mac.ops.init_hw(hw)) | |
2543 | dev_err(&adapter->pdev->dev, "Hardware Error\n"); | |
9a799d71 AK |
2544 | |
2545 | /* reprogram the RAR[0] in case user changed it. */ | |
c44ade9e | 2546 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); |
9a799d71 AK |
2547 | |
2548 | } | |
2549 | ||
9a799d71 AK |
2550 | /** |
2551 | * ixgbe_clean_rx_ring - Free Rx Buffers per Queue | |
2552 | * @adapter: board private structure | |
2553 | * @rx_ring: ring to free buffers from | |
2554 | **/ | |
2555 | static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter, | |
b4617240 | 2556 | struct ixgbe_ring *rx_ring) |
9a799d71 AK |
2557 | { |
2558 | struct pci_dev *pdev = adapter->pdev; | |
2559 | unsigned long size; | |
2560 | unsigned int i; | |
2561 | ||
2562 | /* Free all the Rx ring sk_buffs */ | |
2563 | ||
2564 | for (i = 0; i < rx_ring->count; i++) { | |
2565 | struct ixgbe_rx_buffer *rx_buffer_info; | |
2566 | ||
2567 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; | |
2568 | if (rx_buffer_info->dma) { | |
2569 | pci_unmap_single(pdev, rx_buffer_info->dma, | |
b4617240 PW |
2570 | rx_ring->rx_buf_len, |
2571 | PCI_DMA_FROMDEVICE); | |
9a799d71 AK |
2572 | rx_buffer_info->dma = 0; |
2573 | } | |
2574 | if (rx_buffer_info->skb) { | |
f8212f97 | 2575 | struct sk_buff *skb = rx_buffer_info->skb; |
9a799d71 | 2576 | rx_buffer_info->skb = NULL; |
f8212f97 AD |
2577 | do { |
2578 | struct sk_buff *this = skb; | |
2579 | skb = skb->prev; | |
2580 | dev_kfree_skb(this); | |
2581 | } while (skb); | |
9a799d71 AK |
2582 | } |
2583 | if (!rx_buffer_info->page) | |
2584 | continue; | |
762f4c57 JB |
2585 | pci_unmap_page(pdev, rx_buffer_info->page_dma, PAGE_SIZE / 2, |
2586 | PCI_DMA_FROMDEVICE); | |
9a799d71 | 2587 | rx_buffer_info->page_dma = 0; |
9a799d71 AK |
2588 | put_page(rx_buffer_info->page); |
2589 | rx_buffer_info->page = NULL; | |
762f4c57 | 2590 | rx_buffer_info->page_offset = 0; |
9a799d71 AK |
2591 | } |
2592 | ||
2593 | size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; | |
2594 | memset(rx_ring->rx_buffer_info, 0, size); | |
2595 | ||
2596 | /* Zero out the descriptor ring */ | |
2597 | memset(rx_ring->desc, 0, rx_ring->size); | |
2598 | ||
2599 | rx_ring->next_to_clean = 0; | |
2600 | rx_ring->next_to_use = 0; | |
2601 | ||
9891ca7c JB |
2602 | if (rx_ring->head) |
2603 | writel(0, adapter->hw.hw_addr + rx_ring->head); | |
2604 | if (rx_ring->tail) | |
2605 | writel(0, adapter->hw.hw_addr + rx_ring->tail); | |
9a799d71 AK |
2606 | } |
2607 | ||
2608 | /** | |
2609 | * ixgbe_clean_tx_ring - Free Tx Buffers | |
2610 | * @adapter: board private structure | |
2611 | * @tx_ring: ring to be cleaned | |
2612 | **/ | |
2613 | static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter, | |
b4617240 | 2614 | struct ixgbe_ring *tx_ring) |
9a799d71 AK |
2615 | { |
2616 | struct ixgbe_tx_buffer *tx_buffer_info; | |
2617 | unsigned long size; | |
2618 | unsigned int i; | |
2619 | ||
2620 | /* Free all the Tx ring sk_buffs */ | |
2621 | ||
2622 | for (i = 0; i < tx_ring->count; i++) { | |
2623 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
2624 | ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info); | |
2625 | } | |
2626 | ||
2627 | size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; | |
2628 | memset(tx_ring->tx_buffer_info, 0, size); | |
2629 | ||
2630 | /* Zero out the descriptor ring */ | |
2631 | memset(tx_ring->desc, 0, tx_ring->size); | |
2632 | ||
2633 | tx_ring->next_to_use = 0; | |
2634 | tx_ring->next_to_clean = 0; | |
2635 | ||
9891ca7c JB |
2636 | if (tx_ring->head) |
2637 | writel(0, adapter->hw.hw_addr + tx_ring->head); | |
2638 | if (tx_ring->tail) | |
2639 | writel(0, adapter->hw.hw_addr + tx_ring->tail); | |
9a799d71 AK |
2640 | } |
2641 | ||
2642 | /** | |
021230d4 | 2643 | * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues |
9a799d71 AK |
2644 | * @adapter: board private structure |
2645 | **/ | |
021230d4 | 2646 | static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter) |
9a799d71 AK |
2647 | { |
2648 | int i; | |
2649 | ||
021230d4 AV |
2650 | for (i = 0; i < adapter->num_rx_queues; i++) |
2651 | ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]); | |
9a799d71 AK |
2652 | } |
2653 | ||
2654 | /** | |
021230d4 | 2655 | * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues |
9a799d71 AK |
2656 | * @adapter: board private structure |
2657 | **/ | |
021230d4 | 2658 | static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter) |
9a799d71 AK |
2659 | { |
2660 | int i; | |
2661 | ||
021230d4 AV |
2662 | for (i = 0; i < adapter->num_tx_queues; i++) |
2663 | ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]); | |
9a799d71 AK |
2664 | } |
2665 | ||
2666 | void ixgbe_down(struct ixgbe_adapter *adapter) | |
2667 | { | |
2668 | struct net_device *netdev = adapter->netdev; | |
7f821875 | 2669 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 | 2670 | u32 rxctrl; |
7f821875 JB |
2671 | u32 txdctl; |
2672 | int i, j; | |
9a799d71 AK |
2673 | |
2674 | /* signal that we are down to the interrupt handler */ | |
2675 | set_bit(__IXGBE_DOWN, &adapter->state); | |
2676 | ||
2677 | /* disable receives */ | |
7f821875 JB |
2678 | rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); |
2679 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); | |
9a799d71 AK |
2680 | |
2681 | netif_tx_disable(netdev); | |
2682 | ||
7f821875 | 2683 | IXGBE_WRITE_FLUSH(hw); |
9a799d71 AK |
2684 | msleep(10); |
2685 | ||
7f821875 JB |
2686 | netif_tx_stop_all_queues(netdev); |
2687 | ||
9a799d71 AK |
2688 | ixgbe_irq_disable(adapter); |
2689 | ||
021230d4 | 2690 | ixgbe_napi_disable_all(adapter); |
7f821875 | 2691 | |
9a799d71 | 2692 | del_timer_sync(&adapter->watchdog_timer); |
cf8280ee | 2693 | cancel_work_sync(&adapter->watchdog_task); |
9a799d71 | 2694 | |
7f821875 JB |
2695 | /* disable transmits in the hardware now that interrupts are off */ |
2696 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
2697 | j = adapter->tx_ring[i].reg_idx; | |
2698 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)); | |
2699 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), | |
2700 | (txdctl & ~IXGBE_TXDCTL_ENABLE)); | |
2701 | } | |
88512539 PW |
2702 | /* Disable the Tx DMA engine on 82599 */ |
2703 | if (hw->mac.type == ixgbe_mac_82599EB) | |
2704 | IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, | |
2705 | (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) & | |
2706 | ~IXGBE_DMATXCTL_TE)); | |
7f821875 | 2707 | |
9a799d71 | 2708 | netif_carrier_off(netdev); |
9a799d71 | 2709 | |
5dd2d332 | 2710 | #ifdef CONFIG_IXGBE_DCA |
96b0e0f6 JB |
2711 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { |
2712 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
2713 | dca_remove_requester(&adapter->pdev->dev); | |
2714 | } | |
2715 | ||
2716 | #endif | |
6f4a0e45 PL |
2717 | if (!pci_channel_offline(adapter->pdev)) |
2718 | ixgbe_reset(adapter); | |
9a799d71 AK |
2719 | ixgbe_clean_all_tx_rings(adapter); |
2720 | ixgbe_clean_all_rx_rings(adapter); | |
2721 | ||
5dd2d332 | 2722 | #ifdef CONFIG_IXGBE_DCA |
96b0e0f6 JB |
2723 | /* since we reset the hardware DCA settings were cleared */ |
2724 | if (dca_add_requester(&adapter->pdev->dev) == 0) { | |
2725 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; | |
2726 | /* always use CB2 mode, difference is masked | |
2727 | * in the CB driver */ | |
b4617240 | 2728 | IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2); |
96b0e0f6 JB |
2729 | ixgbe_setup_dca(adapter); |
2730 | } | |
2731 | #endif | |
9a799d71 AK |
2732 | } |
2733 | ||
9a799d71 | 2734 | /** |
021230d4 AV |
2735 | * ixgbe_poll - NAPI Rx polling callback |
2736 | * @napi: structure for representing this polling device | |
2737 | * @budget: how many packets driver is allowed to clean | |
2738 | * | |
2739 | * This function is used for legacy and MSI, NAPI mode | |
9a799d71 | 2740 | **/ |
021230d4 | 2741 | static int ixgbe_poll(struct napi_struct *napi, int budget) |
9a799d71 | 2742 | { |
9a1a69ad JB |
2743 | struct ixgbe_q_vector *q_vector = |
2744 | container_of(napi, struct ixgbe_q_vector, napi); | |
021230d4 | 2745 | struct ixgbe_adapter *adapter = q_vector->adapter; |
9a1a69ad | 2746 | int tx_clean_complete, work_done = 0; |
9a799d71 | 2747 | |
5dd2d332 | 2748 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
2749 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { |
2750 | ixgbe_update_tx_dca(adapter, adapter->tx_ring); | |
2751 | ixgbe_update_rx_dca(adapter, adapter->rx_ring); | |
2752 | } | |
2753 | #endif | |
2754 | ||
9a1a69ad | 2755 | tx_clean_complete = ixgbe_clean_tx_irq(adapter, adapter->tx_ring); |
78b6f4ce | 2756 | ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget); |
9a799d71 | 2757 | |
9a1a69ad | 2758 | if (!tx_clean_complete) |
d2c7ddd6 DM |
2759 | work_done = budget; |
2760 | ||
53e52c72 DM |
2761 | /* If budget not fully consumed, exit the polling mode */ |
2762 | if (work_done < budget) { | |
288379f0 | 2763 | napi_complete(napi); |
509ee935 | 2764 | if (adapter->itr_setting & 1) |
f494e8fa | 2765 | ixgbe_set_itr(adapter); |
d4f80882 | 2766 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
835462fc | 2767 | ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE); |
9a799d71 | 2768 | } |
9a799d71 AK |
2769 | return work_done; |
2770 | } | |
2771 | ||
2772 | /** | |
2773 | * ixgbe_tx_timeout - Respond to a Tx Hang | |
2774 | * @netdev: network interface device structure | |
2775 | **/ | |
2776 | static void ixgbe_tx_timeout(struct net_device *netdev) | |
2777 | { | |
2778 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
2779 | ||
2780 | /* Do the reset outside of interrupt context */ | |
2781 | schedule_work(&adapter->reset_task); | |
2782 | } | |
2783 | ||
2784 | static void ixgbe_reset_task(struct work_struct *work) | |
2785 | { | |
2786 | struct ixgbe_adapter *adapter; | |
2787 | adapter = container_of(work, struct ixgbe_adapter, reset_task); | |
2788 | ||
2f90b865 AD |
2789 | /* If we're already down or resetting, just bail */ |
2790 | if (test_bit(__IXGBE_DOWN, &adapter->state) || | |
2791 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
2792 | return; | |
2793 | ||
9a799d71 AK |
2794 | adapter->tx_timeout_count++; |
2795 | ||
d4f80882 | 2796 | ixgbe_reinit_locked(adapter); |
9a799d71 AK |
2797 | } |
2798 | ||
bc97114d PWJ |
2799 | #ifdef CONFIG_IXGBE_DCB |
2800 | static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter) | |
b9804972 | 2801 | { |
bc97114d | 2802 | bool ret = false; |
b9804972 | 2803 | |
bc97114d PWJ |
2804 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { |
2805 | adapter->ring_feature[RING_F_DCB].mask = 0x7 << 3; | |
2806 | adapter->num_rx_queues = | |
2807 | adapter->ring_feature[RING_F_DCB].indices; | |
2808 | adapter->num_tx_queues = | |
2809 | adapter->ring_feature[RING_F_DCB].indices; | |
2810 | ret = true; | |
2811 | } else { | |
bc97114d PWJ |
2812 | ret = false; |
2813 | } | |
2f90b865 | 2814 | |
bc97114d PWJ |
2815 | return ret; |
2816 | } | |
2817 | #endif | |
2818 | ||
4df10466 JB |
2819 | /** |
2820 | * ixgbe_set_rss_queues: Allocate queues for RSS | |
2821 | * @adapter: board private structure to initialize | |
2822 | * | |
2823 | * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try | |
2824 | * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU. | |
2825 | * | |
2826 | **/ | |
bc97114d PWJ |
2827 | static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter) |
2828 | { | |
2829 | bool ret = false; | |
2830 | ||
2831 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { | |
2832 | adapter->ring_feature[RING_F_RSS].mask = 0xF; | |
2833 | adapter->num_rx_queues = | |
2834 | adapter->ring_feature[RING_F_RSS].indices; | |
2835 | adapter->num_tx_queues = | |
2836 | adapter->ring_feature[RING_F_RSS].indices; | |
2837 | ret = true; | |
2838 | } else { | |
bc97114d | 2839 | ret = false; |
b9804972 JB |
2840 | } |
2841 | ||
bc97114d PWJ |
2842 | return ret; |
2843 | } | |
2844 | ||
4df10466 JB |
2845 | /* |
2846 | * ixgbe_set_num_queues: Allocate queues for device, feature dependant | |
2847 | * @adapter: board private structure to initialize | |
2848 | * | |
2849 | * This is the top level queue allocation routine. The order here is very | |
2850 | * important, starting with the "most" number of features turned on at once, | |
2851 | * and ending with the smallest set of features. This way large combinations | |
2852 | * can be allocated if they're turned on, and smaller combinations are the | |
2853 | * fallthrough conditions. | |
2854 | * | |
2855 | **/ | |
bc97114d PWJ |
2856 | static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter) |
2857 | { | |
bc97114d PWJ |
2858 | #ifdef CONFIG_IXGBE_DCB |
2859 | if (ixgbe_set_dcb_queues(adapter)) | |
af22ab1b | 2860 | goto done; |
bc97114d PWJ |
2861 | |
2862 | #endif | |
2863 | if (ixgbe_set_rss_queues(adapter)) | |
af22ab1b WF |
2864 | goto done; |
2865 | ||
2866 | /* fallback to base case */ | |
2867 | adapter->num_rx_queues = 1; | |
2868 | adapter->num_tx_queues = 1; | |
2869 | ||
2870 | done: | |
2871 | /* Notify the stack of the (possibly) reduced Tx Queue count. */ | |
2872 | adapter->netdev->real_num_tx_queues = adapter->num_tx_queues; | |
b9804972 JB |
2873 | } |
2874 | ||
021230d4 | 2875 | static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter, |
b4617240 | 2876 | int vectors) |
021230d4 AV |
2877 | { |
2878 | int err, vector_threshold; | |
2879 | ||
2880 | /* We'll want at least 3 (vector_threshold): | |
2881 | * 1) TxQ[0] Cleanup | |
2882 | * 2) RxQ[0] Cleanup | |
2883 | * 3) Other (Link Status Change, etc.) | |
2884 | * 4) TCP Timer (optional) | |
2885 | */ | |
2886 | vector_threshold = MIN_MSIX_COUNT; | |
2887 | ||
2888 | /* The more we get, the more we will assign to Tx/Rx Cleanup | |
2889 | * for the separate queues...where Rx Cleanup >= Tx Cleanup. | |
2890 | * Right now, we simply care about how many we'll get; we'll | |
2891 | * set them up later while requesting irq's. | |
2892 | */ | |
2893 | while (vectors >= vector_threshold) { | |
2894 | err = pci_enable_msix(adapter->pdev, adapter->msix_entries, | |
b4617240 | 2895 | vectors); |
021230d4 AV |
2896 | if (!err) /* Success in acquiring all requested vectors. */ |
2897 | break; | |
2898 | else if (err < 0) | |
2899 | vectors = 0; /* Nasty failure, quit now */ | |
2900 | else /* err == number of vectors we should try again with */ | |
2901 | vectors = err; | |
2902 | } | |
2903 | ||
2904 | if (vectors < vector_threshold) { | |
2905 | /* Can't allocate enough MSI-X interrupts? Oh well. | |
2906 | * This just means we'll go with either a single MSI | |
2907 | * vector or fall back to legacy interrupts. | |
2908 | */ | |
2909 | DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n"); | |
2910 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; | |
2911 | kfree(adapter->msix_entries); | |
2912 | adapter->msix_entries = NULL; | |
021230d4 AV |
2913 | } else { |
2914 | adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */ | |
eb7f139c PWJ |
2915 | /* |
2916 | * Adjust for only the vectors we'll use, which is minimum | |
2917 | * of max_msix_q_vectors + NON_Q_VECTORS, or the number of | |
2918 | * vectors we were allocated. | |
2919 | */ | |
2920 | adapter->num_msix_vectors = min(vectors, | |
2921 | adapter->max_msix_q_vectors + NON_Q_VECTORS); | |
021230d4 AV |
2922 | } |
2923 | } | |
2924 | ||
021230d4 | 2925 | /** |
bc97114d | 2926 | * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS |
021230d4 AV |
2927 | * @adapter: board private structure to initialize |
2928 | * | |
bc97114d PWJ |
2929 | * Cache the descriptor ring offsets for RSS to the assigned rings. |
2930 | * | |
021230d4 | 2931 | **/ |
bc97114d | 2932 | static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter) |
021230d4 | 2933 | { |
bc97114d PWJ |
2934 | int i; |
2935 | bool ret = false; | |
2936 | ||
2937 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { | |
2938 | for (i = 0; i < adapter->num_rx_queues; i++) | |
2939 | adapter->rx_ring[i].reg_idx = i; | |
2940 | for (i = 0; i < adapter->num_tx_queues; i++) | |
2941 | adapter->tx_ring[i].reg_idx = i; | |
2942 | ret = true; | |
2943 | } else { | |
2944 | ret = false; | |
2945 | } | |
2946 | ||
2947 | return ret; | |
2948 | } | |
2949 | ||
2950 | #ifdef CONFIG_IXGBE_DCB | |
2951 | /** | |
2952 | * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB | |
2953 | * @adapter: board private structure to initialize | |
2954 | * | |
2955 | * Cache the descriptor ring offsets for DCB to the assigned rings. | |
2956 | * | |
2957 | **/ | |
2958 | static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter) | |
2959 | { | |
2960 | int i; | |
2961 | bool ret = false; | |
2962 | int dcb_i = adapter->ring_feature[RING_F_DCB].indices; | |
2963 | ||
2964 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
2965 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { | |
2f90b865 AD |
2966 | /* the number of queues is assumed to be symmetric */ |
2967 | for (i = 0; i < dcb_i; i++) { | |
2968 | adapter->rx_ring[i].reg_idx = i << 3; | |
2969 | adapter->tx_ring[i].reg_idx = i << 2; | |
2970 | } | |
bc97114d | 2971 | ret = true; |
e8e26350 | 2972 | } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { |
f92ef202 PW |
2973 | if (dcb_i == 8) { |
2974 | /* | |
2975 | * Tx TC0 starts at: descriptor queue 0 | |
2976 | * Tx TC1 starts at: descriptor queue 32 | |
2977 | * Tx TC2 starts at: descriptor queue 64 | |
2978 | * Tx TC3 starts at: descriptor queue 80 | |
2979 | * Tx TC4 starts at: descriptor queue 96 | |
2980 | * Tx TC5 starts at: descriptor queue 104 | |
2981 | * Tx TC6 starts at: descriptor queue 112 | |
2982 | * Tx TC7 starts at: descriptor queue 120 | |
2983 | * | |
2984 | * Rx TC0-TC7 are offset by 16 queues each | |
2985 | */ | |
2986 | for (i = 0; i < 3; i++) { | |
2987 | adapter->tx_ring[i].reg_idx = i << 5; | |
2988 | adapter->rx_ring[i].reg_idx = i << 4; | |
2989 | } | |
2990 | for ( ; i < 5; i++) { | |
2991 | adapter->tx_ring[i].reg_idx = | |
2992 | ((i + 2) << 4); | |
2993 | adapter->rx_ring[i].reg_idx = i << 4; | |
2994 | } | |
2995 | for ( ; i < dcb_i; i++) { | |
2996 | adapter->tx_ring[i].reg_idx = | |
2997 | ((i + 8) << 3); | |
2998 | adapter->rx_ring[i].reg_idx = i << 4; | |
2999 | } | |
3000 | ||
3001 | ret = true; | |
3002 | } else if (dcb_i == 4) { | |
3003 | /* | |
3004 | * Tx TC0 starts at: descriptor queue 0 | |
3005 | * Tx TC1 starts at: descriptor queue 64 | |
3006 | * Tx TC2 starts at: descriptor queue 96 | |
3007 | * Tx TC3 starts at: descriptor queue 112 | |
3008 | * | |
3009 | * Rx TC0-TC3 are offset by 32 queues each | |
3010 | */ | |
3011 | adapter->tx_ring[0].reg_idx = 0; | |
3012 | adapter->tx_ring[1].reg_idx = 64; | |
3013 | adapter->tx_ring[2].reg_idx = 96; | |
3014 | adapter->tx_ring[3].reg_idx = 112; | |
3015 | for (i = 0 ; i < dcb_i; i++) | |
3016 | adapter->rx_ring[i].reg_idx = i << 5; | |
3017 | ||
3018 | ret = true; | |
3019 | } else { | |
3020 | ret = false; | |
e8e26350 | 3021 | } |
bc97114d PWJ |
3022 | } else { |
3023 | ret = false; | |
021230d4 | 3024 | } |
bc97114d PWJ |
3025 | } else { |
3026 | ret = false; | |
021230d4 | 3027 | } |
bc97114d PWJ |
3028 | |
3029 | return ret; | |
3030 | } | |
3031 | #endif | |
3032 | ||
3033 | /** | |
3034 | * ixgbe_cache_ring_register - Descriptor ring to register mapping | |
3035 | * @adapter: board private structure to initialize | |
3036 | * | |
3037 | * Once we know the feature-set enabled for the device, we'll cache | |
3038 | * the register offset the descriptor ring is assigned to. | |
3039 | * | |
3040 | * Note, the order the various feature calls is important. It must start with | |
3041 | * the "most" features enabled at the same time, then trickle down to the | |
3042 | * least amount of features turned on at once. | |
3043 | **/ | |
3044 | static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter) | |
3045 | { | |
3046 | /* start with default case */ | |
3047 | adapter->rx_ring[0].reg_idx = 0; | |
3048 | adapter->tx_ring[0].reg_idx = 0; | |
3049 | ||
3050 | #ifdef CONFIG_IXGBE_DCB | |
3051 | if (ixgbe_cache_ring_dcb(adapter)) | |
3052 | return; | |
3053 | ||
3054 | #endif | |
3055 | if (ixgbe_cache_ring_rss(adapter)) | |
3056 | return; | |
021230d4 AV |
3057 | } |
3058 | ||
9a799d71 AK |
3059 | /** |
3060 | * ixgbe_alloc_queues - Allocate memory for all rings | |
3061 | * @adapter: board private structure to initialize | |
3062 | * | |
3063 | * We allocate one ring per queue at run-time since we don't know the | |
4df10466 JB |
3064 | * number of queues at compile-time. The polling_netdev array is |
3065 | * intended for Multiqueue, but should work fine with a single queue. | |
9a799d71 | 3066 | **/ |
2f90b865 | 3067 | static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter) |
9a799d71 AK |
3068 | { |
3069 | int i; | |
3070 | ||
3071 | adapter->tx_ring = kcalloc(adapter->num_tx_queues, | |
b4617240 | 3072 | sizeof(struct ixgbe_ring), GFP_KERNEL); |
9a799d71 | 3073 | if (!adapter->tx_ring) |
021230d4 | 3074 | goto err_tx_ring_allocation; |
9a799d71 AK |
3075 | |
3076 | adapter->rx_ring = kcalloc(adapter->num_rx_queues, | |
b4617240 | 3077 | sizeof(struct ixgbe_ring), GFP_KERNEL); |
021230d4 AV |
3078 | if (!adapter->rx_ring) |
3079 | goto err_rx_ring_allocation; | |
9a799d71 | 3080 | |
021230d4 | 3081 | for (i = 0; i < adapter->num_tx_queues; i++) { |
b9804972 | 3082 | adapter->tx_ring[i].count = adapter->tx_ring_count; |
021230d4 AV |
3083 | adapter->tx_ring[i].queue_index = i; |
3084 | } | |
b9804972 | 3085 | |
9a799d71 | 3086 | for (i = 0; i < adapter->num_rx_queues; i++) { |
b9804972 | 3087 | adapter->rx_ring[i].count = adapter->rx_ring_count; |
021230d4 AV |
3088 | adapter->rx_ring[i].queue_index = i; |
3089 | } | |
3090 | ||
3091 | ixgbe_cache_ring_register(adapter); | |
3092 | ||
3093 | return 0; | |
3094 | ||
3095 | err_rx_ring_allocation: | |
3096 | kfree(adapter->tx_ring); | |
3097 | err_tx_ring_allocation: | |
3098 | return -ENOMEM; | |
3099 | } | |
3100 | ||
3101 | /** | |
3102 | * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported | |
3103 | * @adapter: board private structure to initialize | |
3104 | * | |
3105 | * Attempt to configure the interrupts using the best available | |
3106 | * capabilities of the hardware and the kernel. | |
3107 | **/ | |
feea6a57 | 3108 | static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter) |
021230d4 | 3109 | { |
8be0e467 | 3110 | struct ixgbe_hw *hw = &adapter->hw; |
021230d4 AV |
3111 | int err = 0; |
3112 | int vector, v_budget; | |
3113 | ||
3114 | /* | |
3115 | * It's easy to be greedy for MSI-X vectors, but it really | |
3116 | * doesn't do us much good if we have a lot more vectors | |
3117 | * than CPU's. So let's be conservative and only ask for | |
3118 | * (roughly) twice the number of vectors as there are CPU's. | |
3119 | */ | |
3120 | v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues, | |
b4617240 | 3121 | (int)(num_online_cpus() * 2)) + NON_Q_VECTORS; |
021230d4 AV |
3122 | |
3123 | /* | |
3124 | * At the same time, hardware can only support a maximum of | |
8be0e467 PW |
3125 | * hw.mac->max_msix_vectors vectors. With features |
3126 | * such as RSS and VMDq, we can easily surpass the number of Rx and Tx | |
3127 | * descriptor queues supported by our device. Thus, we cap it off in | |
3128 | * those rare cases where the cpu count also exceeds our vector limit. | |
021230d4 | 3129 | */ |
8be0e467 | 3130 | v_budget = min(v_budget, (int)hw->mac.max_msix_vectors); |
021230d4 AV |
3131 | |
3132 | /* A failure in MSI-X entry allocation isn't fatal, but it does | |
3133 | * mean we disable MSI-X capabilities of the adapter. */ | |
3134 | adapter->msix_entries = kcalloc(v_budget, | |
b4617240 | 3135 | sizeof(struct msix_entry), GFP_KERNEL); |
7a921c93 AD |
3136 | if (adapter->msix_entries) { |
3137 | for (vector = 0; vector < v_budget; vector++) | |
3138 | adapter->msix_entries[vector].entry = vector; | |
021230d4 | 3139 | |
7a921c93 | 3140 | ixgbe_acquire_msix_vectors(adapter, v_budget); |
021230d4 | 3141 | |
7a921c93 AD |
3142 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
3143 | goto out; | |
3144 | } | |
021230d4 | 3145 | |
7a921c93 AD |
3146 | adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; |
3147 | adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED; | |
3148 | ixgbe_set_num_queues(adapter); | |
021230d4 | 3149 | |
021230d4 AV |
3150 | err = pci_enable_msi(adapter->pdev); |
3151 | if (!err) { | |
3152 | adapter->flags |= IXGBE_FLAG_MSI_ENABLED; | |
3153 | } else { | |
3154 | DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, " | |
b4617240 | 3155 | "falling back to legacy. Error: %d\n", err); |
021230d4 AV |
3156 | /* reset err */ |
3157 | err = 0; | |
3158 | } | |
3159 | ||
3160 | out: | |
021230d4 AV |
3161 | return err; |
3162 | } | |
3163 | ||
7a921c93 AD |
3164 | /** |
3165 | * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors | |
3166 | * @adapter: board private structure to initialize | |
3167 | * | |
3168 | * We allocate one q_vector per queue interrupt. If allocation fails we | |
3169 | * return -ENOMEM. | |
3170 | **/ | |
3171 | static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter) | |
3172 | { | |
3173 | int q_idx, num_q_vectors; | |
3174 | struct ixgbe_q_vector *q_vector; | |
3175 | int napi_vectors; | |
3176 | int (*poll)(struct napi_struct *, int); | |
3177 | ||
3178 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
3179 | num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
3180 | napi_vectors = adapter->num_rx_queues; | |
3181 | poll = &ixgbe_clean_rxonly; | |
3182 | } else { | |
3183 | num_q_vectors = 1; | |
3184 | napi_vectors = 1; | |
3185 | poll = &ixgbe_poll; | |
3186 | } | |
3187 | ||
3188 | for (q_idx = 0; q_idx < num_q_vectors; q_idx++) { | |
3189 | q_vector = kzalloc(sizeof(struct ixgbe_q_vector), GFP_KERNEL); | |
3190 | if (!q_vector) | |
3191 | goto err_out; | |
3192 | q_vector->adapter = adapter; | |
3193 | q_vector->v_idx = q_idx; | |
3194 | q_vector->eitr = adapter->eitr_param; | |
3195 | if (q_idx < napi_vectors) | |
3196 | netif_napi_add(adapter->netdev, &q_vector->napi, | |
3197 | (*poll), 64); | |
3198 | adapter->q_vector[q_idx] = q_vector; | |
3199 | } | |
3200 | ||
3201 | return 0; | |
3202 | ||
3203 | err_out: | |
3204 | while (q_idx) { | |
3205 | q_idx--; | |
3206 | q_vector = adapter->q_vector[q_idx]; | |
3207 | netif_napi_del(&q_vector->napi); | |
3208 | kfree(q_vector); | |
3209 | adapter->q_vector[q_idx] = NULL; | |
3210 | } | |
3211 | return -ENOMEM; | |
3212 | } | |
3213 | ||
3214 | /** | |
3215 | * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors | |
3216 | * @adapter: board private structure to initialize | |
3217 | * | |
3218 | * This function frees the memory allocated to the q_vectors. In addition if | |
3219 | * NAPI is enabled it will delete any references to the NAPI struct prior | |
3220 | * to freeing the q_vector. | |
3221 | **/ | |
3222 | static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter) | |
3223 | { | |
3224 | int q_idx, num_q_vectors; | |
3225 | int napi_vectors; | |
3226 | ||
3227 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
3228 | num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
3229 | napi_vectors = adapter->num_rx_queues; | |
3230 | } else { | |
3231 | num_q_vectors = 1; | |
3232 | napi_vectors = 1; | |
3233 | } | |
3234 | ||
3235 | for (q_idx = 0; q_idx < num_q_vectors; q_idx++) { | |
3236 | struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx]; | |
3237 | ||
3238 | adapter->q_vector[q_idx] = NULL; | |
3239 | if (q_idx < napi_vectors) | |
3240 | netif_napi_del(&q_vector->napi); | |
3241 | kfree(q_vector); | |
3242 | } | |
3243 | } | |
3244 | ||
2f90b865 | 3245 | void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter) |
021230d4 AV |
3246 | { |
3247 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
3248 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; | |
3249 | pci_disable_msix(adapter->pdev); | |
3250 | kfree(adapter->msix_entries); | |
3251 | adapter->msix_entries = NULL; | |
3252 | } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) { | |
3253 | adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED; | |
3254 | pci_disable_msi(adapter->pdev); | |
3255 | } | |
3256 | return; | |
3257 | } | |
3258 | ||
3259 | /** | |
3260 | * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme | |
3261 | * @adapter: board private structure to initialize | |
3262 | * | |
3263 | * We determine which interrupt scheme to use based on... | |
3264 | * - Kernel support (MSI, MSI-X) | |
3265 | * - which can be user-defined (via MODULE_PARAM) | |
3266 | * - Hardware queue count (num_*_queues) | |
3267 | * - defined by miscellaneous hardware support/features (RSS, etc.) | |
3268 | **/ | |
2f90b865 | 3269 | int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter) |
021230d4 AV |
3270 | { |
3271 | int err; | |
3272 | ||
3273 | /* Number of supported queues */ | |
3274 | ixgbe_set_num_queues(adapter); | |
3275 | ||
021230d4 AV |
3276 | err = ixgbe_set_interrupt_capability(adapter); |
3277 | if (err) { | |
3278 | DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n"); | |
3279 | goto err_set_interrupt; | |
9a799d71 AK |
3280 | } |
3281 | ||
7a921c93 AD |
3282 | err = ixgbe_alloc_q_vectors(adapter); |
3283 | if (err) { | |
3284 | DPRINTK(PROBE, ERR, "Unable to allocate memory for queue " | |
3285 | "vectors\n"); | |
3286 | goto err_alloc_q_vectors; | |
3287 | } | |
3288 | ||
3289 | err = ixgbe_alloc_queues(adapter); | |
3290 | if (err) { | |
3291 | DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n"); | |
3292 | goto err_alloc_queues; | |
3293 | } | |
3294 | ||
021230d4 | 3295 | DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, " |
b4617240 PW |
3296 | "Tx Queue count = %u\n", |
3297 | (adapter->num_rx_queues > 1) ? "Enabled" : | |
3298 | "Disabled", adapter->num_rx_queues, adapter->num_tx_queues); | |
021230d4 AV |
3299 | |
3300 | set_bit(__IXGBE_DOWN, &adapter->state); | |
3301 | ||
9a799d71 | 3302 | return 0; |
021230d4 | 3303 | |
7a921c93 AD |
3304 | err_alloc_queues: |
3305 | ixgbe_free_q_vectors(adapter); | |
3306 | err_alloc_q_vectors: | |
3307 | ixgbe_reset_interrupt_capability(adapter); | |
021230d4 | 3308 | err_set_interrupt: |
7a921c93 AD |
3309 | return err; |
3310 | } | |
3311 | ||
3312 | /** | |
3313 | * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings | |
3314 | * @adapter: board private structure to clear interrupt scheme on | |
3315 | * | |
3316 | * We go through and clear interrupt specific resources and reset the structure | |
3317 | * to pre-load conditions | |
3318 | **/ | |
3319 | void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter) | |
3320 | { | |
021230d4 AV |
3321 | kfree(adapter->tx_ring); |
3322 | kfree(adapter->rx_ring); | |
7a921c93 AD |
3323 | adapter->tx_ring = NULL; |
3324 | adapter->rx_ring = NULL; | |
3325 | ||
3326 | ixgbe_free_q_vectors(adapter); | |
3327 | ixgbe_reset_interrupt_capability(adapter); | |
9a799d71 AK |
3328 | } |
3329 | ||
c4900be0 DS |
3330 | /** |
3331 | * ixgbe_sfp_timer - worker thread to find a missing module | |
3332 | * @data: pointer to our adapter struct | |
3333 | **/ | |
3334 | static void ixgbe_sfp_timer(unsigned long data) | |
3335 | { | |
3336 | struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data; | |
3337 | ||
4df10466 JB |
3338 | /* |
3339 | * Do the sfp_timer outside of interrupt context due to the | |
c4900be0 DS |
3340 | * delays that sfp+ detection requires |
3341 | */ | |
3342 | schedule_work(&adapter->sfp_task); | |
3343 | } | |
3344 | ||
3345 | /** | |
3346 | * ixgbe_sfp_task - worker thread to find a missing module | |
3347 | * @work: pointer to work_struct containing our data | |
3348 | **/ | |
3349 | static void ixgbe_sfp_task(struct work_struct *work) | |
3350 | { | |
3351 | struct ixgbe_adapter *adapter = container_of(work, | |
3352 | struct ixgbe_adapter, | |
3353 | sfp_task); | |
3354 | struct ixgbe_hw *hw = &adapter->hw; | |
3355 | ||
3356 | if ((hw->phy.type == ixgbe_phy_nl) && | |
3357 | (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) { | |
3358 | s32 ret = hw->phy.ops.identify_sfp(hw); | |
3359 | if (ret) | |
3360 | goto reschedule; | |
3361 | ret = hw->phy.ops.reset(hw); | |
3362 | if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
3363 | DPRINTK(PROBE, ERR, "failed to initialize because an " | |
3364 | "unsupported SFP+ module type was detected.\n" | |
3365 | "Reload the driver after installing a " | |
3366 | "supported module.\n"); | |
3367 | unregister_netdev(adapter->netdev); | |
3368 | } else { | |
3369 | DPRINTK(PROBE, INFO, "detected SFP+: %d\n", | |
3370 | hw->phy.sfp_type); | |
3371 | } | |
3372 | /* don't need this routine any more */ | |
3373 | clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); | |
3374 | } | |
3375 | return; | |
3376 | reschedule: | |
3377 | if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state)) | |
3378 | mod_timer(&adapter->sfp_timer, | |
3379 | round_jiffies(jiffies + (2 * HZ))); | |
3380 | } | |
3381 | ||
9a799d71 AK |
3382 | /** |
3383 | * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter) | |
3384 | * @adapter: board private structure to initialize | |
3385 | * | |
3386 | * ixgbe_sw_init initializes the Adapter private data structure. | |
3387 | * Fields are initialized based on PCI device information and | |
3388 | * OS network device settings (MTU size). | |
3389 | **/ | |
3390 | static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter) | |
3391 | { | |
3392 | struct ixgbe_hw *hw = &adapter->hw; | |
3393 | struct pci_dev *pdev = adapter->pdev; | |
021230d4 | 3394 | unsigned int rss; |
7a6b6f51 | 3395 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
3396 | int j; |
3397 | struct tc_configuration *tc; | |
3398 | #endif | |
021230d4 | 3399 | |
c44ade9e JB |
3400 | /* PCI config space info */ |
3401 | ||
3402 | hw->vendor_id = pdev->vendor; | |
3403 | hw->device_id = pdev->device; | |
3404 | hw->revision_id = pdev->revision; | |
3405 | hw->subsystem_vendor_id = pdev->subsystem_vendor; | |
3406 | hw->subsystem_device_id = pdev->subsystem_device; | |
3407 | ||
021230d4 AV |
3408 | /* Set capability flags */ |
3409 | rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus()); | |
3410 | adapter->ring_feature[RING_F_RSS].indices = rss; | |
3411 | adapter->flags |= IXGBE_FLAG_RSS_ENABLED; | |
2f90b865 | 3412 | adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES; |
bf069c97 DS |
3413 | if (hw->mac.type == ixgbe_mac_82598EB) { |
3414 | if (hw->device_id == IXGBE_DEV_ID_82598AT) | |
3415 | adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE; | |
e8e26350 | 3416 | adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598; |
bf069c97 | 3417 | } else if (hw->mac.type == ixgbe_mac_82599EB) { |
e8e26350 | 3418 | adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599; |
f8212f97 AD |
3419 | adapter->flags |= IXGBE_FLAG_RSC_CAPABLE; |
3420 | adapter->flags |= IXGBE_FLAG_RSC_ENABLED; | |
eacd73f7 YZ |
3421 | #ifdef IXGBE_FCOE |
3422 | adapter->flags |= IXGBE_FLAG_FCOE_ENABLED; | |
3423 | #endif /* IXGBE_FCOE */ | |
f8212f97 | 3424 | } |
2f90b865 | 3425 | |
7a6b6f51 | 3426 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
3427 | /* Configure DCB traffic classes */ |
3428 | for (j = 0; j < MAX_TRAFFIC_CLASS; j++) { | |
3429 | tc = &adapter->dcb_cfg.tc_config[j]; | |
3430 | tc->path[DCB_TX_CONFIG].bwg_id = 0; | |
3431 | tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1); | |
3432 | tc->path[DCB_RX_CONFIG].bwg_id = 0; | |
3433 | tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1); | |
3434 | tc->dcb_pfc = pfc_disabled; | |
3435 | } | |
3436 | adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100; | |
3437 | adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100; | |
3438 | adapter->dcb_cfg.rx_pba_cfg = pba_equal; | |
3439 | adapter->dcb_cfg.round_robin_enable = false; | |
3440 | adapter->dcb_set_bitmap = 0x00; | |
3441 | ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg, | |
3442 | adapter->ring_feature[RING_F_DCB].indices); | |
3443 | ||
3444 | #endif | |
9a799d71 AK |
3445 | |
3446 | /* default flow control settings */ | |
cd7664f6 | 3447 | hw->fc.requested_mode = ixgbe_fc_full; |
71fd570b | 3448 | hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */ |
2b9ade93 JB |
3449 | hw->fc.high_water = IXGBE_DEFAULT_FCRTH; |
3450 | hw->fc.low_water = IXGBE_DEFAULT_FCRTL; | |
3451 | hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE; | |
3452 | hw->fc.send_xon = true; | |
71fd570b | 3453 | hw->fc.disable_fc_autoneg = false; |
9a799d71 | 3454 | |
30efa5a3 JB |
3455 | /* enable itr by default in dynamic mode */ |
3456 | adapter->itr_setting = 1; | |
3457 | adapter->eitr_param = 20000; | |
3458 | ||
3459 | /* set defaults for eitr in MegaBytes */ | |
3460 | adapter->eitr_low = 10; | |
3461 | adapter->eitr_high = 20; | |
3462 | ||
3463 | /* set default ring sizes */ | |
3464 | adapter->tx_ring_count = IXGBE_DEFAULT_TXD; | |
3465 | adapter->rx_ring_count = IXGBE_DEFAULT_RXD; | |
3466 | ||
9a799d71 | 3467 | /* initialize eeprom parameters */ |
c44ade9e | 3468 | if (ixgbe_init_eeprom_params_generic(hw)) { |
9a799d71 AK |
3469 | dev_err(&pdev->dev, "EEPROM initialization failed\n"); |
3470 | return -EIO; | |
3471 | } | |
3472 | ||
021230d4 | 3473 | /* enable rx csum by default */ |
9a799d71 AK |
3474 | adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED; |
3475 | ||
9a799d71 AK |
3476 | set_bit(__IXGBE_DOWN, &adapter->state); |
3477 | ||
3478 | return 0; | |
3479 | } | |
3480 | ||
3481 | /** | |
3482 | * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors) | |
3483 | * @adapter: board private structure | |
3a581073 | 3484 | * @tx_ring: tx descriptor ring (for a specific queue) to setup |
9a799d71 AK |
3485 | * |
3486 | * Return 0 on success, negative on failure | |
3487 | **/ | |
3488 | int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter, | |
e01c31a5 | 3489 | struct ixgbe_ring *tx_ring) |
9a799d71 AK |
3490 | { |
3491 | struct pci_dev *pdev = adapter->pdev; | |
3492 | int size; | |
3493 | ||
3a581073 JB |
3494 | size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; |
3495 | tx_ring->tx_buffer_info = vmalloc(size); | |
e01c31a5 JB |
3496 | if (!tx_ring->tx_buffer_info) |
3497 | goto err; | |
3a581073 | 3498 | memset(tx_ring->tx_buffer_info, 0, size); |
9a799d71 AK |
3499 | |
3500 | /* round up to nearest 4K */ | |
12207e49 | 3501 | tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc); |
3a581073 | 3502 | tx_ring->size = ALIGN(tx_ring->size, 4096); |
9a799d71 | 3503 | |
3a581073 JB |
3504 | tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size, |
3505 | &tx_ring->dma); | |
e01c31a5 JB |
3506 | if (!tx_ring->desc) |
3507 | goto err; | |
9a799d71 | 3508 | |
3a581073 JB |
3509 | tx_ring->next_to_use = 0; |
3510 | tx_ring->next_to_clean = 0; | |
3511 | tx_ring->work_limit = tx_ring->count; | |
9a799d71 | 3512 | return 0; |
e01c31a5 JB |
3513 | |
3514 | err: | |
3515 | vfree(tx_ring->tx_buffer_info); | |
3516 | tx_ring->tx_buffer_info = NULL; | |
3517 | DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit " | |
3518 | "descriptor ring\n"); | |
3519 | return -ENOMEM; | |
9a799d71 AK |
3520 | } |
3521 | ||
69888674 AD |
3522 | /** |
3523 | * ixgbe_setup_all_tx_resources - allocate all queues Tx resources | |
3524 | * @adapter: board private structure | |
3525 | * | |
3526 | * If this function returns with an error, then it's possible one or | |
3527 | * more of the rings is populated (while the rest are not). It is the | |
3528 | * callers duty to clean those orphaned rings. | |
3529 | * | |
3530 | * Return 0 on success, negative on failure | |
3531 | **/ | |
3532 | static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter) | |
3533 | { | |
3534 | int i, err = 0; | |
3535 | ||
3536 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
3537 | err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]); | |
3538 | if (!err) | |
3539 | continue; | |
3540 | DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i); | |
3541 | break; | |
3542 | } | |
3543 | ||
3544 | return err; | |
3545 | } | |
3546 | ||
9a799d71 AK |
3547 | /** |
3548 | * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors) | |
3549 | * @adapter: board private structure | |
3a581073 | 3550 | * @rx_ring: rx descriptor ring (for a specific queue) to setup |
9a799d71 AK |
3551 | * |
3552 | * Returns 0 on success, negative on failure | |
3553 | **/ | |
3554 | int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter, | |
b4617240 | 3555 | struct ixgbe_ring *rx_ring) |
9a799d71 AK |
3556 | { |
3557 | struct pci_dev *pdev = adapter->pdev; | |
021230d4 | 3558 | int size; |
9a799d71 | 3559 | |
3a581073 JB |
3560 | size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; |
3561 | rx_ring->rx_buffer_info = vmalloc(size); | |
3562 | if (!rx_ring->rx_buffer_info) { | |
9a799d71 | 3563 | DPRINTK(PROBE, ERR, |
b4617240 | 3564 | "vmalloc allocation failed for the rx desc ring\n"); |
177db6ff | 3565 | goto alloc_failed; |
9a799d71 | 3566 | } |
3a581073 | 3567 | memset(rx_ring->rx_buffer_info, 0, size); |
9a799d71 | 3568 | |
9a799d71 | 3569 | /* Round up to nearest 4K */ |
3a581073 JB |
3570 | rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); |
3571 | rx_ring->size = ALIGN(rx_ring->size, 4096); | |
9a799d71 | 3572 | |
3a581073 | 3573 | rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma); |
9a799d71 | 3574 | |
3a581073 | 3575 | if (!rx_ring->desc) { |
9a799d71 | 3576 | DPRINTK(PROBE, ERR, |
b4617240 | 3577 | "Memory allocation failed for the rx desc ring\n"); |
3a581073 | 3578 | vfree(rx_ring->rx_buffer_info); |
177db6ff | 3579 | goto alloc_failed; |
9a799d71 AK |
3580 | } |
3581 | ||
3a581073 JB |
3582 | rx_ring->next_to_clean = 0; |
3583 | rx_ring->next_to_use = 0; | |
9a799d71 AK |
3584 | |
3585 | return 0; | |
177db6ff MC |
3586 | |
3587 | alloc_failed: | |
177db6ff | 3588 | return -ENOMEM; |
9a799d71 AK |
3589 | } |
3590 | ||
69888674 AD |
3591 | /** |
3592 | * ixgbe_setup_all_rx_resources - allocate all queues Rx resources | |
3593 | * @adapter: board private structure | |
3594 | * | |
3595 | * If this function returns with an error, then it's possible one or | |
3596 | * more of the rings is populated (while the rest are not). It is the | |
3597 | * callers duty to clean those orphaned rings. | |
3598 | * | |
3599 | * Return 0 on success, negative on failure | |
3600 | **/ | |
3601 | ||
3602 | static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter) | |
3603 | { | |
3604 | int i, err = 0; | |
3605 | ||
3606 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
3607 | err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]); | |
3608 | if (!err) | |
3609 | continue; | |
3610 | DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i); | |
3611 | break; | |
3612 | } | |
3613 | ||
3614 | return err; | |
3615 | } | |
3616 | ||
9a799d71 AK |
3617 | /** |
3618 | * ixgbe_free_tx_resources - Free Tx Resources per Queue | |
3619 | * @adapter: board private structure | |
3620 | * @tx_ring: Tx descriptor ring for a specific queue | |
3621 | * | |
3622 | * Free all transmit software resources | |
3623 | **/ | |
c431f97e JB |
3624 | void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter, |
3625 | struct ixgbe_ring *tx_ring) | |
9a799d71 AK |
3626 | { |
3627 | struct pci_dev *pdev = adapter->pdev; | |
3628 | ||
3629 | ixgbe_clean_tx_ring(adapter, tx_ring); | |
3630 | ||
3631 | vfree(tx_ring->tx_buffer_info); | |
3632 | tx_ring->tx_buffer_info = NULL; | |
3633 | ||
3634 | pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma); | |
3635 | ||
3636 | tx_ring->desc = NULL; | |
3637 | } | |
3638 | ||
3639 | /** | |
3640 | * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues | |
3641 | * @adapter: board private structure | |
3642 | * | |
3643 | * Free all transmit software resources | |
3644 | **/ | |
3645 | static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter) | |
3646 | { | |
3647 | int i; | |
3648 | ||
3649 | for (i = 0; i < adapter->num_tx_queues; i++) | |
9891ca7c JB |
3650 | if (adapter->tx_ring[i].desc) |
3651 | ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]); | |
9a799d71 AK |
3652 | } |
3653 | ||
3654 | /** | |
b4617240 | 3655 | * ixgbe_free_rx_resources - Free Rx Resources |
9a799d71 AK |
3656 | * @adapter: board private structure |
3657 | * @rx_ring: ring to clean the resources from | |
3658 | * | |
3659 | * Free all receive software resources | |
3660 | **/ | |
c431f97e JB |
3661 | void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter, |
3662 | struct ixgbe_ring *rx_ring) | |
9a799d71 AK |
3663 | { |
3664 | struct pci_dev *pdev = adapter->pdev; | |
3665 | ||
3666 | ixgbe_clean_rx_ring(adapter, rx_ring); | |
3667 | ||
3668 | vfree(rx_ring->rx_buffer_info); | |
3669 | rx_ring->rx_buffer_info = NULL; | |
3670 | ||
3671 | pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma); | |
3672 | ||
3673 | rx_ring->desc = NULL; | |
3674 | } | |
3675 | ||
3676 | /** | |
3677 | * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues | |
3678 | * @adapter: board private structure | |
3679 | * | |
3680 | * Free all receive software resources | |
3681 | **/ | |
3682 | static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter) | |
3683 | { | |
3684 | int i; | |
3685 | ||
3686 | for (i = 0; i < adapter->num_rx_queues; i++) | |
9891ca7c JB |
3687 | if (adapter->rx_ring[i].desc) |
3688 | ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]); | |
9a799d71 AK |
3689 | } |
3690 | ||
9a799d71 AK |
3691 | /** |
3692 | * ixgbe_change_mtu - Change the Maximum Transfer Unit | |
3693 | * @netdev: network interface device structure | |
3694 | * @new_mtu: new value for maximum frame size | |
3695 | * | |
3696 | * Returns 0 on success, negative on failure | |
3697 | **/ | |
3698 | static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu) | |
3699 | { | |
3700 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3701 | int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; | |
3702 | ||
42c783c5 JB |
3703 | /* MTU < 68 is an error and causes problems on some kernels */ |
3704 | if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE)) | |
9a799d71 AK |
3705 | return -EINVAL; |
3706 | ||
021230d4 | 3707 | DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n", |
b4617240 | 3708 | netdev->mtu, new_mtu); |
021230d4 | 3709 | /* must set new MTU before calling down or up */ |
9a799d71 AK |
3710 | netdev->mtu = new_mtu; |
3711 | ||
d4f80882 AV |
3712 | if (netif_running(netdev)) |
3713 | ixgbe_reinit_locked(adapter); | |
9a799d71 AK |
3714 | |
3715 | return 0; | |
3716 | } | |
3717 | ||
3718 | /** | |
3719 | * ixgbe_open - Called when a network interface is made active | |
3720 | * @netdev: network interface device structure | |
3721 | * | |
3722 | * Returns 0 on success, negative value on failure | |
3723 | * | |
3724 | * The open entry point is called when a network interface is made | |
3725 | * active by the system (IFF_UP). At this point all resources needed | |
3726 | * for transmit and receive operations are allocated, the interrupt | |
3727 | * handler is registered with the OS, the watchdog timer is started, | |
3728 | * and the stack is notified that the interface is ready. | |
3729 | **/ | |
3730 | static int ixgbe_open(struct net_device *netdev) | |
3731 | { | |
3732 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3733 | int err; | |
4bebfaa5 AK |
3734 | |
3735 | /* disallow open during test */ | |
3736 | if (test_bit(__IXGBE_TESTING, &adapter->state)) | |
3737 | return -EBUSY; | |
9a799d71 | 3738 | |
54386467 JB |
3739 | netif_carrier_off(netdev); |
3740 | ||
9a799d71 AK |
3741 | /* allocate transmit descriptors */ |
3742 | err = ixgbe_setup_all_tx_resources(adapter); | |
3743 | if (err) | |
3744 | goto err_setup_tx; | |
3745 | ||
9a799d71 AK |
3746 | /* allocate receive descriptors */ |
3747 | err = ixgbe_setup_all_rx_resources(adapter); | |
3748 | if (err) | |
3749 | goto err_setup_rx; | |
3750 | ||
3751 | ixgbe_configure(adapter); | |
3752 | ||
021230d4 | 3753 | err = ixgbe_request_irq(adapter); |
9a799d71 AK |
3754 | if (err) |
3755 | goto err_req_irq; | |
3756 | ||
9a799d71 AK |
3757 | err = ixgbe_up_complete(adapter); |
3758 | if (err) | |
3759 | goto err_up; | |
3760 | ||
d55b53ff JK |
3761 | netif_tx_start_all_queues(netdev); |
3762 | ||
9a799d71 AK |
3763 | return 0; |
3764 | ||
3765 | err_up: | |
5eba3699 | 3766 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
3767 | ixgbe_free_irq(adapter); |
3768 | err_req_irq: | |
9a799d71 | 3769 | err_setup_rx: |
a20a1199 | 3770 | ixgbe_free_all_rx_resources(adapter); |
9a799d71 | 3771 | err_setup_tx: |
a20a1199 | 3772 | ixgbe_free_all_tx_resources(adapter); |
9a799d71 AK |
3773 | ixgbe_reset(adapter); |
3774 | ||
3775 | return err; | |
3776 | } | |
3777 | ||
3778 | /** | |
3779 | * ixgbe_close - Disables a network interface | |
3780 | * @netdev: network interface device structure | |
3781 | * | |
3782 | * Returns 0, this is not allowed to fail | |
3783 | * | |
3784 | * The close entry point is called when an interface is de-activated | |
3785 | * by the OS. The hardware is still under the drivers control, but | |
3786 | * needs to be disabled. A global MAC reset is issued to stop the | |
3787 | * hardware, and all transmit and receive resources are freed. | |
3788 | **/ | |
3789 | static int ixgbe_close(struct net_device *netdev) | |
3790 | { | |
3791 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
9a799d71 AK |
3792 | |
3793 | ixgbe_down(adapter); | |
3794 | ixgbe_free_irq(adapter); | |
3795 | ||
3796 | ixgbe_free_all_tx_resources(adapter); | |
3797 | ixgbe_free_all_rx_resources(adapter); | |
3798 | ||
5eba3699 | 3799 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
3800 | |
3801 | return 0; | |
3802 | } | |
3803 | ||
b3c8b4ba AD |
3804 | #ifdef CONFIG_PM |
3805 | static int ixgbe_resume(struct pci_dev *pdev) | |
3806 | { | |
3807 | struct net_device *netdev = pci_get_drvdata(pdev); | |
3808 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3809 | u32 err; | |
3810 | ||
3811 | pci_set_power_state(pdev, PCI_D0); | |
3812 | pci_restore_state(pdev); | |
9ce77666 | 3813 | |
3814 | err = pci_enable_device_mem(pdev); | |
b3c8b4ba | 3815 | if (err) { |
69888674 | 3816 | printk(KERN_ERR "ixgbe: Cannot enable PCI device from " |
b3c8b4ba AD |
3817 | "suspend\n"); |
3818 | return err; | |
3819 | } | |
3820 | pci_set_master(pdev); | |
3821 | ||
dd4d8ca6 | 3822 | pci_wake_from_d3(pdev, false); |
b3c8b4ba AD |
3823 | |
3824 | err = ixgbe_init_interrupt_scheme(adapter); | |
3825 | if (err) { | |
3826 | printk(KERN_ERR "ixgbe: Cannot initialize interrupts for " | |
3827 | "device\n"); | |
3828 | return err; | |
3829 | } | |
3830 | ||
b3c8b4ba AD |
3831 | ixgbe_reset(adapter); |
3832 | ||
495dce12 WJP |
3833 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
3834 | ||
b3c8b4ba AD |
3835 | if (netif_running(netdev)) { |
3836 | err = ixgbe_open(adapter->netdev); | |
3837 | if (err) | |
3838 | return err; | |
3839 | } | |
3840 | ||
3841 | netif_device_attach(netdev); | |
3842 | ||
3843 | return 0; | |
3844 | } | |
b3c8b4ba | 3845 | #endif /* CONFIG_PM */ |
9d8d05ae RW |
3846 | |
3847 | static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake) | |
b3c8b4ba AD |
3848 | { |
3849 | struct net_device *netdev = pci_get_drvdata(pdev); | |
3850 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
e8e26350 PW |
3851 | struct ixgbe_hw *hw = &adapter->hw; |
3852 | u32 ctrl, fctrl; | |
3853 | u32 wufc = adapter->wol; | |
b3c8b4ba AD |
3854 | #ifdef CONFIG_PM |
3855 | int retval = 0; | |
3856 | #endif | |
3857 | ||
3858 | netif_device_detach(netdev); | |
3859 | ||
3860 | if (netif_running(netdev)) { | |
3861 | ixgbe_down(adapter); | |
3862 | ixgbe_free_irq(adapter); | |
3863 | ixgbe_free_all_tx_resources(adapter); | |
3864 | ixgbe_free_all_rx_resources(adapter); | |
3865 | } | |
7a921c93 | 3866 | ixgbe_clear_interrupt_scheme(adapter); |
b3c8b4ba AD |
3867 | |
3868 | #ifdef CONFIG_PM | |
3869 | retval = pci_save_state(pdev); | |
3870 | if (retval) | |
3871 | return retval; | |
4df10466 | 3872 | |
b3c8b4ba | 3873 | #endif |
e8e26350 PW |
3874 | if (wufc) { |
3875 | ixgbe_set_rx_mode(netdev); | |
b3c8b4ba | 3876 | |
e8e26350 PW |
3877 | /* turn on all-multi mode if wake on multicast is enabled */ |
3878 | if (wufc & IXGBE_WUFC_MC) { | |
3879 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
3880 | fctrl |= IXGBE_FCTRL_MPE; | |
3881 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); | |
3882 | } | |
3883 | ||
3884 | ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); | |
3885 | ctrl |= IXGBE_CTRL_GIO_DIS; | |
3886 | IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); | |
3887 | ||
3888 | IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc); | |
3889 | } else { | |
3890 | IXGBE_WRITE_REG(hw, IXGBE_WUC, 0); | |
3891 | IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); | |
3892 | } | |
3893 | ||
dd4d8ca6 DS |
3894 | if (wufc && hw->mac.type == ixgbe_mac_82599EB) |
3895 | pci_wake_from_d3(pdev, true); | |
3896 | else | |
3897 | pci_wake_from_d3(pdev, false); | |
b3c8b4ba | 3898 | |
9d8d05ae RW |
3899 | *enable_wake = !!wufc; |
3900 | ||
b3c8b4ba AD |
3901 | ixgbe_release_hw_control(adapter); |
3902 | ||
3903 | pci_disable_device(pdev); | |
3904 | ||
9d8d05ae RW |
3905 | return 0; |
3906 | } | |
3907 | ||
3908 | #ifdef CONFIG_PM | |
3909 | static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state) | |
3910 | { | |
3911 | int retval; | |
3912 | bool wake; | |
3913 | ||
3914 | retval = __ixgbe_shutdown(pdev, &wake); | |
3915 | if (retval) | |
3916 | return retval; | |
3917 | ||
3918 | if (wake) { | |
3919 | pci_prepare_to_sleep(pdev); | |
3920 | } else { | |
3921 | pci_wake_from_d3(pdev, false); | |
3922 | pci_set_power_state(pdev, PCI_D3hot); | |
3923 | } | |
b3c8b4ba AD |
3924 | |
3925 | return 0; | |
3926 | } | |
9d8d05ae | 3927 | #endif /* CONFIG_PM */ |
b3c8b4ba AD |
3928 | |
3929 | static void ixgbe_shutdown(struct pci_dev *pdev) | |
3930 | { | |
9d8d05ae RW |
3931 | bool wake; |
3932 | ||
3933 | __ixgbe_shutdown(pdev, &wake); | |
3934 | ||
3935 | if (system_state == SYSTEM_POWER_OFF) { | |
3936 | pci_wake_from_d3(pdev, wake); | |
3937 | pci_set_power_state(pdev, PCI_D3hot); | |
3938 | } | |
b3c8b4ba AD |
3939 | } |
3940 | ||
9a799d71 AK |
3941 | /** |
3942 | * ixgbe_update_stats - Update the board statistics counters. | |
3943 | * @adapter: board private structure | |
3944 | **/ | |
3945 | void ixgbe_update_stats(struct ixgbe_adapter *adapter) | |
3946 | { | |
3947 | struct ixgbe_hw *hw = &adapter->hw; | |
6f11eef7 AV |
3948 | u64 total_mpc = 0; |
3949 | u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot; | |
9a799d71 | 3950 | |
d51019a4 | 3951 | if (hw->mac.type == ixgbe_mac_82599EB) { |
f8212f97 | 3952 | u64 rsc_count = 0; |
d51019a4 PW |
3953 | for (i = 0; i < 16; i++) |
3954 | adapter->hw_rx_no_dma_resources += | |
3955 | IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); | |
f8212f97 AD |
3956 | for (i = 0; i < adapter->num_rx_queues; i++) |
3957 | rsc_count += adapter->rx_ring[i].rsc_count; | |
3958 | adapter->rsc_count = rsc_count; | |
d51019a4 PW |
3959 | } |
3960 | ||
9a799d71 | 3961 | adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); |
6f11eef7 AV |
3962 | for (i = 0; i < 8; i++) { |
3963 | /* for packet buffers not used, the register should read 0 */ | |
3964 | mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i)); | |
3965 | missed_rx += mpc; | |
3966 | adapter->stats.mpc[i] += mpc; | |
3967 | total_mpc += adapter->stats.mpc[i]; | |
e8e26350 PW |
3968 | if (hw->mac.type == ixgbe_mac_82598EB) |
3969 | adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); | |
2f90b865 AD |
3970 | adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); |
3971 | adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i)); | |
3972 | adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); | |
3973 | adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i)); | |
e8e26350 PW |
3974 | if (hw->mac.type == ixgbe_mac_82599EB) { |
3975 | adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw, | |
3976 | IXGBE_PXONRXCNT(i)); | |
3977 | adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw, | |
3978 | IXGBE_PXOFFRXCNT(i)); | |
3979 | adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); | |
e8e26350 PW |
3980 | } else { |
3981 | adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw, | |
3982 | IXGBE_PXONRXC(i)); | |
3983 | adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw, | |
3984 | IXGBE_PXOFFRXC(i)); | |
3985 | } | |
2f90b865 AD |
3986 | adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw, |
3987 | IXGBE_PXONTXC(i)); | |
2f90b865 | 3988 | adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw, |
e8e26350 | 3989 | IXGBE_PXOFFTXC(i)); |
6f11eef7 AV |
3990 | } |
3991 | adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); | |
3992 | /* work around hardware counting issue */ | |
3993 | adapter->stats.gprc -= missed_rx; | |
3994 | ||
3995 | /* 82598 hardware only has a 32 bit counter in the high register */ | |
e8e26350 PW |
3996 | if (hw->mac.type == ixgbe_mac_82599EB) { |
3997 | adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); | |
3998 | IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */ | |
3999 | adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); | |
4000 | IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */ | |
4001 | adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL); | |
4002 | IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */ | |
4003 | adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); | |
4004 | adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); | |
6d45522c YZ |
4005 | #ifdef IXGBE_FCOE |
4006 | adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); | |
4007 | adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); | |
4008 | adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); | |
4009 | adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); | |
4010 | adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); | |
4011 | adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); | |
4012 | #endif /* IXGBE_FCOE */ | |
e8e26350 PW |
4013 | } else { |
4014 | adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); | |
4015 | adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); | |
4016 | adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); | |
4017 | adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); | |
4018 | adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH); | |
4019 | } | |
9a799d71 AK |
4020 | bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); |
4021 | adapter->stats.bprc += bprc; | |
4022 | adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); | |
e8e26350 PW |
4023 | if (hw->mac.type == ixgbe_mac_82598EB) |
4024 | adapter->stats.mprc -= bprc; | |
9a799d71 AK |
4025 | adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC); |
4026 | adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); | |
4027 | adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); | |
4028 | adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); | |
4029 | adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); | |
4030 | adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); | |
4031 | adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); | |
9a799d71 | 4032 | adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); |
6f11eef7 AV |
4033 | lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); |
4034 | adapter->stats.lxontxc += lxon; | |
4035 | lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); | |
4036 | adapter->stats.lxofftxc += lxoff; | |
9a799d71 AK |
4037 | adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC); |
4038 | adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); | |
6f11eef7 AV |
4039 | adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); |
4040 | /* | |
4041 | * 82598 errata - tx of flow control packets is included in tx counters | |
4042 | */ | |
4043 | xon_off_tot = lxon + lxoff; | |
4044 | adapter->stats.gptc -= xon_off_tot; | |
4045 | adapter->stats.mptc -= xon_off_tot; | |
4046 | adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN)); | |
9a799d71 AK |
4047 | adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC); |
4048 | adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC); | |
4049 | adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC); | |
9a799d71 AK |
4050 | adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR); |
4051 | adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); | |
6f11eef7 | 4052 | adapter->stats.ptc64 -= xon_off_tot; |
9a799d71 AK |
4053 | adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); |
4054 | adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); | |
4055 | adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); | |
4056 | adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); | |
4057 | adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); | |
9a799d71 AK |
4058 | adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); |
4059 | ||
4060 | /* Fill out the OS statistics structure */ | |
9a799d71 AK |
4061 | adapter->net_stats.multicast = adapter->stats.mprc; |
4062 | ||
4063 | /* Rx Errors */ | |
4064 | adapter->net_stats.rx_errors = adapter->stats.crcerrs + | |
b4617240 | 4065 | adapter->stats.rlec; |
9a799d71 AK |
4066 | adapter->net_stats.rx_dropped = 0; |
4067 | adapter->net_stats.rx_length_errors = adapter->stats.rlec; | |
4068 | adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs; | |
6f11eef7 | 4069 | adapter->net_stats.rx_missed_errors = total_mpc; |
9a799d71 AK |
4070 | } |
4071 | ||
4072 | /** | |
4073 | * ixgbe_watchdog - Timer Call-back | |
4074 | * @data: pointer to adapter cast into an unsigned long | |
4075 | **/ | |
4076 | static void ixgbe_watchdog(unsigned long data) | |
4077 | { | |
4078 | struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data; | |
cf8280ee JB |
4079 | struct ixgbe_hw *hw = &adapter->hw; |
4080 | ||
4081 | /* Do the watchdog outside of interrupt context due to the lovely | |
4082 | * delays that some of the newer hardware requires */ | |
4083 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { | |
22d5a71b JB |
4084 | u64 eics = 0; |
4085 | int i; | |
4086 | ||
4087 | for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) | |
c9c7d2e5 | 4088 | eics |= ((u64)1 << i); |
22d5a71b | 4089 | |
cf8280ee | 4090 | /* Cause software interrupt to ensure rx rings are cleaned */ |
22d5a71b JB |
4091 | switch (hw->mac.type) { |
4092 | case ixgbe_mac_82598EB: | |
4093 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
4094 | IXGBE_WRITE_REG(hw, IXGBE_EICS, (u32)eics); | |
4095 | } else { | |
4096 | /* | |
4097 | * for legacy and MSI interrupts don't set any | |
4098 | * bits that are enabled for EIAM, because this | |
4099 | * operation would set *both* EIMS and EICS for | |
4100 | * any bit in EIAM | |
4101 | */ | |
4102 | IXGBE_WRITE_REG(hw, IXGBE_EICS, | |
4103 | (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); | |
4104 | } | |
4105 | break; | |
4106 | case ixgbe_mac_82599EB: | |
4107 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
835462fc NS |
4108 | IXGBE_WRITE_REG(hw, IXGBE_EICS_EX(0), |
4109 | (u32)(eics & 0xFFFFFFFF)); | |
22d5a71b | 4110 | IXGBE_WRITE_REG(hw, IXGBE_EICS_EX(1), |
22d5a71b JB |
4111 | (u32)(eics >> 32)); |
4112 | } else { | |
4113 | /* | |
4114 | * for legacy and MSI interrupts don't set any | |
4115 | * bits that are enabled for EIAM, because this | |
4116 | * operation would set *both* EIMS and EICS for | |
4117 | * any bit in EIAM | |
4118 | */ | |
4119 | IXGBE_WRITE_REG(hw, IXGBE_EICS, | |
4120 | (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); | |
4121 | } | |
4122 | break; | |
4123 | default: | |
4124 | break; | |
cf8280ee JB |
4125 | } |
4126 | /* Reset the timer */ | |
4127 | mod_timer(&adapter->watchdog_timer, | |
4128 | round_jiffies(jiffies + 2 * HZ)); | |
4129 | } | |
9a799d71 | 4130 | |
cf8280ee JB |
4131 | schedule_work(&adapter->watchdog_task); |
4132 | } | |
4133 | ||
e8e26350 PW |
4134 | /** |
4135 | * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber | |
4136 | * @work: pointer to work_struct containing our data | |
4137 | **/ | |
4138 | static void ixgbe_multispeed_fiber_task(struct work_struct *work) | |
4139 | { | |
4140 | struct ixgbe_adapter *adapter = container_of(work, | |
4141 | struct ixgbe_adapter, | |
4142 | multispeed_fiber_task); | |
4143 | struct ixgbe_hw *hw = &adapter->hw; | |
4144 | u32 autoneg; | |
4145 | ||
4146 | adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK; | |
4147 | if (hw->mac.ops.get_link_capabilities) | |
4148 | hw->mac.ops.get_link_capabilities(hw, &autoneg, | |
4149 | &hw->mac.autoneg); | |
4150 | if (hw->mac.ops.setup_link_speed) | |
4151 | hw->mac.ops.setup_link_speed(hw, autoneg, true, true); | |
4152 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; | |
4153 | adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK; | |
4154 | } | |
4155 | ||
4156 | /** | |
4157 | * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module | |
4158 | * @work: pointer to work_struct containing our data | |
4159 | **/ | |
4160 | static void ixgbe_sfp_config_module_task(struct work_struct *work) | |
4161 | { | |
4162 | struct ixgbe_adapter *adapter = container_of(work, | |
4163 | struct ixgbe_adapter, | |
4164 | sfp_config_module_task); | |
4165 | struct ixgbe_hw *hw = &adapter->hw; | |
4166 | u32 err; | |
4167 | ||
4168 | adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK; | |
4169 | err = hw->phy.ops.identify_sfp(hw); | |
4170 | if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
4171 | DPRINTK(PROBE, ERR, "PHY not supported on this NIC %d\n", err); | |
4172 | ixgbe_down(adapter); | |
4173 | return; | |
4174 | } | |
4175 | hw->mac.ops.setup_sfp(hw); | |
4176 | ||
8d1c3c07 | 4177 | if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK)) |
e8e26350 PW |
4178 | /* This will also work for DA Twinax connections */ |
4179 | schedule_work(&adapter->multispeed_fiber_task); | |
4180 | adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK; | |
4181 | } | |
4182 | ||
cf8280ee | 4183 | /** |
69888674 AD |
4184 | * ixgbe_watchdog_task - worker thread to bring link up |
4185 | * @work: pointer to work_struct containing our data | |
cf8280ee JB |
4186 | **/ |
4187 | static void ixgbe_watchdog_task(struct work_struct *work) | |
4188 | { | |
4189 | struct ixgbe_adapter *adapter = container_of(work, | |
4190 | struct ixgbe_adapter, | |
4191 | watchdog_task); | |
4192 | struct net_device *netdev = adapter->netdev; | |
4193 | struct ixgbe_hw *hw = &adapter->hw; | |
4194 | u32 link_speed = adapter->link_speed; | |
4195 | bool link_up = adapter->link_up; | |
bc59fcda NS |
4196 | int i; |
4197 | struct ixgbe_ring *tx_ring; | |
4198 | int some_tx_pending = 0; | |
cf8280ee JB |
4199 | |
4200 | adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK; | |
4201 | ||
4202 | if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) { | |
4203 | hw->mac.ops.check_link(hw, &link_speed, &link_up, false); | |
4204 | if (link_up || | |
4205 | time_after(jiffies, (adapter->link_check_timeout + | |
4206 | IXGBE_TRY_LINK_TIMEOUT))) { | |
4207 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC); | |
4208 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; | |
4209 | } | |
4210 | adapter->link_up = link_up; | |
4211 | adapter->link_speed = link_speed; | |
4212 | } | |
9a799d71 AK |
4213 | |
4214 | if (link_up) { | |
4215 | if (!netif_carrier_ok(netdev)) { | |
e8e26350 PW |
4216 | bool flow_rx, flow_tx; |
4217 | ||
4218 | if (hw->mac.type == ixgbe_mac_82599EB) { | |
4219 | u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); | |
4220 | u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG); | |
4221 | flow_rx = (mflcn & IXGBE_MFLCN_RFCE); | |
4222 | flow_tx = (fccfg & IXGBE_FCCFG_TFCE_802_3X); | |
4223 | } else { | |
4224 | u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
4225 | u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS); | |
4226 | flow_rx = (frctl & IXGBE_FCTRL_RFCE); | |
4227 | flow_tx = (rmcs & IXGBE_RMCS_TFCE_802_3X); | |
4228 | } | |
4229 | ||
a46e534b JK |
4230 | printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, " |
4231 | "Flow Control: %s\n", | |
4232 | netdev->name, | |
4233 | (link_speed == IXGBE_LINK_SPEED_10GB_FULL ? | |
4234 | "10 Gbps" : | |
4235 | (link_speed == IXGBE_LINK_SPEED_1GB_FULL ? | |
4236 | "1 Gbps" : "unknown speed")), | |
e8e26350 PW |
4237 | ((flow_rx && flow_tx) ? "RX/TX" : |
4238 | (flow_rx ? "RX" : | |
4239 | (flow_tx ? "TX" : "None")))); | |
9a799d71 AK |
4240 | |
4241 | netif_carrier_on(netdev); | |
9a799d71 AK |
4242 | } else { |
4243 | /* Force detection of hung controller */ | |
4244 | adapter->detect_tx_hung = true; | |
4245 | } | |
4246 | } else { | |
cf8280ee JB |
4247 | adapter->link_up = false; |
4248 | adapter->link_speed = 0; | |
9a799d71 | 4249 | if (netif_carrier_ok(netdev)) { |
a46e534b JK |
4250 | printk(KERN_INFO "ixgbe: %s NIC Link is Down\n", |
4251 | netdev->name); | |
9a799d71 | 4252 | netif_carrier_off(netdev); |
9a799d71 AK |
4253 | } |
4254 | } | |
4255 | ||
bc59fcda NS |
4256 | if (!netif_carrier_ok(netdev)) { |
4257 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
4258 | tx_ring = &adapter->tx_ring[i]; | |
4259 | if (tx_ring->next_to_use != tx_ring->next_to_clean) { | |
4260 | some_tx_pending = 1; | |
4261 | break; | |
4262 | } | |
4263 | } | |
4264 | ||
4265 | if (some_tx_pending) { | |
4266 | /* We've lost link, so the controller stops DMA, | |
4267 | * but we've got queued Tx work that's never going | |
4268 | * to get done, so reset controller to flush Tx. | |
4269 | * (Do the reset outside of interrupt context). | |
4270 | */ | |
4271 | schedule_work(&adapter->reset_task); | |
4272 | } | |
4273 | } | |
4274 | ||
9a799d71 | 4275 | ixgbe_update_stats(adapter); |
cf8280ee | 4276 | adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK; |
9a799d71 AK |
4277 | } |
4278 | ||
9a799d71 | 4279 | static int ixgbe_tso(struct ixgbe_adapter *adapter, |
b4617240 PW |
4280 | struct ixgbe_ring *tx_ring, struct sk_buff *skb, |
4281 | u32 tx_flags, u8 *hdr_len) | |
9a799d71 AK |
4282 | { |
4283 | struct ixgbe_adv_tx_context_desc *context_desc; | |
4284 | unsigned int i; | |
4285 | int err; | |
4286 | struct ixgbe_tx_buffer *tx_buffer_info; | |
9f8cdf4f JB |
4287 | u32 vlan_macip_lens = 0, type_tucmd_mlhl; |
4288 | u32 mss_l4len_idx, l4len; | |
9a799d71 AK |
4289 | |
4290 | if (skb_is_gso(skb)) { | |
4291 | if (skb_header_cloned(skb)) { | |
4292 | err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); | |
4293 | if (err) | |
4294 | return err; | |
4295 | } | |
4296 | l4len = tcp_hdrlen(skb); | |
4297 | *hdr_len += l4len; | |
4298 | ||
8327d000 | 4299 | if (skb->protocol == htons(ETH_P_IP)) { |
9a799d71 AK |
4300 | struct iphdr *iph = ip_hdr(skb); |
4301 | iph->tot_len = 0; | |
4302 | iph->check = 0; | |
4303 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, | |
b4617240 PW |
4304 | iph->daddr, 0, |
4305 | IPPROTO_TCP, | |
4306 | 0); | |
9a799d71 AK |
4307 | adapter->hw_tso_ctxt++; |
4308 | } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) { | |
4309 | ipv6_hdr(skb)->payload_len = 0; | |
4310 | tcp_hdr(skb)->check = | |
4311 | ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, | |
b4617240 PW |
4312 | &ipv6_hdr(skb)->daddr, |
4313 | 0, IPPROTO_TCP, 0); | |
9a799d71 AK |
4314 | adapter->hw_tso6_ctxt++; |
4315 | } | |
4316 | ||
4317 | i = tx_ring->next_to_use; | |
4318 | ||
4319 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
4320 | context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i); | |
4321 | ||
4322 | /* VLAN MACLEN IPLEN */ | |
4323 | if (tx_flags & IXGBE_TX_FLAGS_VLAN) | |
4324 | vlan_macip_lens |= | |
4325 | (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK); | |
4326 | vlan_macip_lens |= ((skb_network_offset(skb)) << | |
b4617240 | 4327 | IXGBE_ADVTXD_MACLEN_SHIFT); |
9a799d71 AK |
4328 | *hdr_len += skb_network_offset(skb); |
4329 | vlan_macip_lens |= | |
4330 | (skb_transport_header(skb) - skb_network_header(skb)); | |
4331 | *hdr_len += | |
4332 | (skb_transport_header(skb) - skb_network_header(skb)); | |
4333 | context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); | |
4334 | context_desc->seqnum_seed = 0; | |
4335 | ||
4336 | /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ | |
9f8cdf4f | 4337 | type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT | |
b4617240 | 4338 | IXGBE_ADVTXD_DTYP_CTXT); |
9a799d71 | 4339 | |
8327d000 | 4340 | if (skb->protocol == htons(ETH_P_IP)) |
9a799d71 AK |
4341 | type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4; |
4342 | type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP; | |
4343 | context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl); | |
4344 | ||
4345 | /* MSS L4LEN IDX */ | |
9f8cdf4f | 4346 | mss_l4len_idx = |
9a799d71 AK |
4347 | (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT); |
4348 | mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT); | |
4eeae6fd PW |
4349 | /* use index 1 for TSO */ |
4350 | mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT); | |
9a799d71 AK |
4351 | context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); |
4352 | ||
4353 | tx_buffer_info->time_stamp = jiffies; | |
4354 | tx_buffer_info->next_to_watch = i; | |
4355 | ||
4356 | i++; | |
4357 | if (i == tx_ring->count) | |
4358 | i = 0; | |
4359 | tx_ring->next_to_use = i; | |
4360 | ||
4361 | return true; | |
4362 | } | |
4363 | return false; | |
4364 | } | |
4365 | ||
4366 | static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter, | |
b4617240 PW |
4367 | struct ixgbe_ring *tx_ring, |
4368 | struct sk_buff *skb, u32 tx_flags) | |
9a799d71 AK |
4369 | { |
4370 | struct ixgbe_adv_tx_context_desc *context_desc; | |
4371 | unsigned int i; | |
4372 | struct ixgbe_tx_buffer *tx_buffer_info; | |
4373 | u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0; | |
4374 | ||
4375 | if (skb->ip_summed == CHECKSUM_PARTIAL || | |
4376 | (tx_flags & IXGBE_TX_FLAGS_VLAN)) { | |
4377 | i = tx_ring->next_to_use; | |
4378 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
4379 | context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i); | |
4380 | ||
4381 | if (tx_flags & IXGBE_TX_FLAGS_VLAN) | |
4382 | vlan_macip_lens |= | |
4383 | (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK); | |
4384 | vlan_macip_lens |= (skb_network_offset(skb) << | |
b4617240 | 4385 | IXGBE_ADVTXD_MACLEN_SHIFT); |
9a799d71 AK |
4386 | if (skb->ip_summed == CHECKSUM_PARTIAL) |
4387 | vlan_macip_lens |= (skb_transport_header(skb) - | |
b4617240 | 4388 | skb_network_header(skb)); |
9a799d71 AK |
4389 | |
4390 | context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); | |
4391 | context_desc->seqnum_seed = 0; | |
4392 | ||
4393 | type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT | | |
b4617240 | 4394 | IXGBE_ADVTXD_DTYP_CTXT); |
9a799d71 AK |
4395 | |
4396 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
41825d71 | 4397 | switch (skb->protocol) { |
09640e63 | 4398 | case cpu_to_be16(ETH_P_IP): |
9a799d71 | 4399 | type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4; |
41825d71 AK |
4400 | if (ip_hdr(skb)->protocol == IPPROTO_TCP) |
4401 | type_tucmd_mlhl |= | |
b4617240 | 4402 | IXGBE_ADVTXD_TUCMD_L4T_TCP; |
45a5ead0 JB |
4403 | else if (ip_hdr(skb)->protocol == IPPROTO_SCTP) |
4404 | type_tucmd_mlhl |= | |
4405 | IXGBE_ADVTXD_TUCMD_L4T_SCTP; | |
41825d71 | 4406 | break; |
09640e63 | 4407 | case cpu_to_be16(ETH_P_IPV6): |
41825d71 AK |
4408 | /* XXX what about other V6 headers?? */ |
4409 | if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP) | |
4410 | type_tucmd_mlhl |= | |
b4617240 | 4411 | IXGBE_ADVTXD_TUCMD_L4T_TCP; |
45a5ead0 JB |
4412 | else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP) |
4413 | type_tucmd_mlhl |= | |
4414 | IXGBE_ADVTXD_TUCMD_L4T_SCTP; | |
41825d71 | 4415 | break; |
41825d71 AK |
4416 | default: |
4417 | if (unlikely(net_ratelimit())) { | |
4418 | DPRINTK(PROBE, WARNING, | |
4419 | "partial checksum but proto=%x!\n", | |
4420 | skb->protocol); | |
4421 | } | |
4422 | break; | |
4423 | } | |
9a799d71 AK |
4424 | } |
4425 | ||
4426 | context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl); | |
4eeae6fd | 4427 | /* use index zero for tx checksum offload */ |
9a799d71 AK |
4428 | context_desc->mss_l4len_idx = 0; |
4429 | ||
4430 | tx_buffer_info->time_stamp = jiffies; | |
4431 | tx_buffer_info->next_to_watch = i; | |
9f8cdf4f | 4432 | |
9a799d71 AK |
4433 | adapter->hw_csum_tx_good++; |
4434 | i++; | |
4435 | if (i == tx_ring->count) | |
4436 | i = 0; | |
4437 | tx_ring->next_to_use = i; | |
4438 | ||
4439 | return true; | |
4440 | } | |
9f8cdf4f | 4441 | |
9a799d71 AK |
4442 | return false; |
4443 | } | |
4444 | ||
4445 | static int ixgbe_tx_map(struct ixgbe_adapter *adapter, | |
b4617240 | 4446 | struct ixgbe_ring *tx_ring, |
eacd73f7 YZ |
4447 | struct sk_buff *skb, u32 tx_flags, |
4448 | unsigned int first) | |
9a799d71 AK |
4449 | { |
4450 | struct ixgbe_tx_buffer *tx_buffer_info; | |
eacd73f7 YZ |
4451 | unsigned int len; |
4452 | unsigned int total = skb->len; | |
9a799d71 AK |
4453 | unsigned int offset = 0, size, count = 0, i; |
4454 | unsigned int nr_frags = skb_shinfo(skb)->nr_frags; | |
4455 | unsigned int f; | |
44df32c5 | 4456 | dma_addr_t *map; |
9a799d71 AK |
4457 | |
4458 | i = tx_ring->next_to_use; | |
4459 | ||
44df32c5 AD |
4460 | if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) { |
4461 | dev_err(&adapter->pdev->dev, "TX DMA map failed\n"); | |
4462 | return 0; | |
4463 | } | |
4464 | ||
4465 | map = skb_shinfo(skb)->dma_maps; | |
4466 | ||
eacd73f7 YZ |
4467 | if (tx_flags & IXGBE_TX_FLAGS_FCOE) |
4468 | /* excluding fcoe_crc_eof for FCoE */ | |
4469 | total -= sizeof(struct fcoe_crc_eof); | |
4470 | ||
4471 | len = min(skb_headlen(skb), total); | |
9a799d71 AK |
4472 | while (len) { |
4473 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
4474 | size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD); | |
4475 | ||
4476 | tx_buffer_info->length = size; | |
44df32c5 | 4477 | tx_buffer_info->dma = map[0] + offset; |
9a799d71 AK |
4478 | tx_buffer_info->time_stamp = jiffies; |
4479 | tx_buffer_info->next_to_watch = i; | |
4480 | ||
4481 | len -= size; | |
eacd73f7 | 4482 | total -= size; |
9a799d71 AK |
4483 | offset += size; |
4484 | count++; | |
44df32c5 AD |
4485 | |
4486 | if (len) { | |
4487 | i++; | |
4488 | if (i == tx_ring->count) | |
4489 | i = 0; | |
4490 | } | |
9a799d71 AK |
4491 | } |
4492 | ||
4493 | for (f = 0; f < nr_frags; f++) { | |
4494 | struct skb_frag_struct *frag; | |
4495 | ||
4496 | frag = &skb_shinfo(skb)->frags[f]; | |
eacd73f7 | 4497 | len = min((unsigned int)frag->size, total); |
44df32c5 | 4498 | offset = 0; |
9a799d71 AK |
4499 | |
4500 | while (len) { | |
44df32c5 AD |
4501 | i++; |
4502 | if (i == tx_ring->count) | |
4503 | i = 0; | |
4504 | ||
9a799d71 AK |
4505 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; |
4506 | size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD); | |
4507 | ||
4508 | tx_buffer_info->length = size; | |
44df32c5 | 4509 | tx_buffer_info->dma = map[f + 1] + offset; |
9a799d71 AK |
4510 | tx_buffer_info->time_stamp = jiffies; |
4511 | tx_buffer_info->next_to_watch = i; | |
4512 | ||
4513 | len -= size; | |
eacd73f7 | 4514 | total -= size; |
9a799d71 AK |
4515 | offset += size; |
4516 | count++; | |
9a799d71 | 4517 | } |
eacd73f7 YZ |
4518 | if (total == 0) |
4519 | break; | |
9a799d71 | 4520 | } |
44df32c5 | 4521 | |
9a799d71 AK |
4522 | tx_ring->tx_buffer_info[i].skb = skb; |
4523 | tx_ring->tx_buffer_info[first].next_to_watch = i; | |
4524 | ||
4525 | return count; | |
4526 | } | |
4527 | ||
4528 | static void ixgbe_tx_queue(struct ixgbe_adapter *adapter, | |
b4617240 PW |
4529 | struct ixgbe_ring *tx_ring, |
4530 | int tx_flags, int count, u32 paylen, u8 hdr_len) | |
9a799d71 AK |
4531 | { |
4532 | union ixgbe_adv_tx_desc *tx_desc = NULL; | |
4533 | struct ixgbe_tx_buffer *tx_buffer_info; | |
4534 | u32 olinfo_status = 0, cmd_type_len = 0; | |
4535 | unsigned int i; | |
4536 | u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS; | |
4537 | ||
4538 | cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA; | |
4539 | ||
4540 | cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT; | |
4541 | ||
4542 | if (tx_flags & IXGBE_TX_FLAGS_VLAN) | |
4543 | cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE; | |
4544 | ||
4545 | if (tx_flags & IXGBE_TX_FLAGS_TSO) { | |
4546 | cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE; | |
4547 | ||
4548 | olinfo_status |= IXGBE_TXD_POPTS_TXSM << | |
b4617240 | 4549 | IXGBE_ADVTXD_POPTS_SHIFT; |
9a799d71 | 4550 | |
4eeae6fd PW |
4551 | /* use index 1 context for tso */ |
4552 | olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT); | |
9a799d71 AK |
4553 | if (tx_flags & IXGBE_TX_FLAGS_IPV4) |
4554 | olinfo_status |= IXGBE_TXD_POPTS_IXSM << | |
b4617240 | 4555 | IXGBE_ADVTXD_POPTS_SHIFT; |
9a799d71 AK |
4556 | |
4557 | } else if (tx_flags & IXGBE_TX_FLAGS_CSUM) | |
4558 | olinfo_status |= IXGBE_TXD_POPTS_TXSM << | |
b4617240 | 4559 | IXGBE_ADVTXD_POPTS_SHIFT; |
9a799d71 | 4560 | |
eacd73f7 YZ |
4561 | if (tx_flags & IXGBE_TX_FLAGS_FCOE) { |
4562 | olinfo_status |= IXGBE_ADVTXD_CC; | |
4563 | olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT); | |
4564 | if (tx_flags & IXGBE_TX_FLAGS_FSO) | |
4565 | cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE; | |
4566 | } | |
4567 | ||
9a799d71 AK |
4568 | olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT); |
4569 | ||
4570 | i = tx_ring->next_to_use; | |
4571 | while (count--) { | |
4572 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
4573 | tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i); | |
4574 | tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma); | |
4575 | tx_desc->read.cmd_type_len = | |
b4617240 | 4576 | cpu_to_le32(cmd_type_len | tx_buffer_info->length); |
9a799d71 | 4577 | tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); |
9a799d71 AK |
4578 | i++; |
4579 | if (i == tx_ring->count) | |
4580 | i = 0; | |
4581 | } | |
4582 | ||
4583 | tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd); | |
4584 | ||
4585 | /* | |
4586 | * Force memory writes to complete before letting h/w | |
4587 | * know there are new descriptors to fetch. (Only | |
4588 | * applicable for weak-ordered memory model archs, | |
4589 | * such as IA-64). | |
4590 | */ | |
4591 | wmb(); | |
4592 | ||
4593 | tx_ring->next_to_use = i; | |
4594 | writel(i, adapter->hw.hw_addr + tx_ring->tail); | |
4595 | } | |
4596 | ||
e092be60 | 4597 | static int __ixgbe_maybe_stop_tx(struct net_device *netdev, |
b4617240 | 4598 | struct ixgbe_ring *tx_ring, int size) |
e092be60 AV |
4599 | { |
4600 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4601 | ||
30eba97a | 4602 | netif_stop_subqueue(netdev, tx_ring->queue_index); |
e092be60 AV |
4603 | /* Herbert's original patch had: |
4604 | * smp_mb__after_netif_stop_queue(); | |
4605 | * but since that doesn't exist yet, just open code it. */ | |
4606 | smp_mb(); | |
4607 | ||
4608 | /* We need to check again in a case another CPU has just | |
4609 | * made room available. */ | |
4610 | if (likely(IXGBE_DESC_UNUSED(tx_ring) < size)) | |
4611 | return -EBUSY; | |
4612 | ||
4613 | /* A reprieve! - use start_queue because it doesn't call schedule */ | |
af72166f | 4614 | netif_start_subqueue(netdev, tx_ring->queue_index); |
e092be60 AV |
4615 | ++adapter->restart_queue; |
4616 | return 0; | |
4617 | } | |
4618 | ||
4619 | static int ixgbe_maybe_stop_tx(struct net_device *netdev, | |
b4617240 | 4620 | struct ixgbe_ring *tx_ring, int size) |
e092be60 AV |
4621 | { |
4622 | if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size)) | |
4623 | return 0; | |
4624 | return __ixgbe_maybe_stop_tx(netdev, tx_ring, size); | |
4625 | } | |
4626 | ||
09a3b1f8 SH |
4627 | static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb) |
4628 | { | |
4629 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
4630 | ||
4631 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) | |
4632 | return 0; /* All traffic should default to class 0 */ | |
4633 | ||
4634 | return skb_tx_hash(dev, skb); | |
4635 | } | |
4636 | ||
9a799d71 AK |
4637 | static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev) |
4638 | { | |
4639 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4640 | struct ixgbe_ring *tx_ring; | |
9a799d71 AK |
4641 | unsigned int first; |
4642 | unsigned int tx_flags = 0; | |
30eba97a AV |
4643 | u8 hdr_len = 0; |
4644 | int r_idx = 0, tso; | |
9a799d71 AK |
4645 | int count = 0; |
4646 | unsigned int f; | |
9f8cdf4f | 4647 | |
95615d90 | 4648 | r_idx = skb->queue_mapping; |
30eba97a | 4649 | tx_ring = &adapter->tx_ring[r_idx]; |
9a799d71 | 4650 | |
9f8cdf4f JB |
4651 | if (adapter->vlgrp && vlan_tx_tag_present(skb)) { |
4652 | tx_flags |= vlan_tx_tag_get(skb); | |
2f90b865 AD |
4653 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { |
4654 | tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK; | |
4655 | tx_flags |= (skb->queue_mapping << 13); | |
4656 | } | |
4657 | tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT; | |
4658 | tx_flags |= IXGBE_TX_FLAGS_VLAN; | |
4659 | } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
4660 | tx_flags |= (skb->queue_mapping << 13); | |
9f8cdf4f JB |
4661 | tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT; |
4662 | tx_flags |= IXGBE_TX_FLAGS_VLAN; | |
9a799d71 | 4663 | } |
eacd73f7 YZ |
4664 | |
4665 | if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && | |
4666 | (skb->protocol == htons(ETH_P_FCOE))) | |
4667 | tx_flags |= IXGBE_TX_FLAGS_FCOE; | |
4668 | ||
4669 | /* four things can cause us to need a context descriptor */ | |
9f8cdf4f JB |
4670 | if (skb_is_gso(skb) || |
4671 | (skb->ip_summed == CHECKSUM_PARTIAL) || | |
eacd73f7 YZ |
4672 | (tx_flags & IXGBE_TX_FLAGS_VLAN) || |
4673 | (tx_flags & IXGBE_TX_FLAGS_FCOE)) | |
9a799d71 AK |
4674 | count++; |
4675 | ||
9f8cdf4f JB |
4676 | count += TXD_USE_COUNT(skb_headlen(skb)); |
4677 | for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) | |
9a799d71 AK |
4678 | count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); |
4679 | ||
e092be60 | 4680 | if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) { |
9a799d71 | 4681 | adapter->tx_busy++; |
9a799d71 AK |
4682 | return NETDEV_TX_BUSY; |
4683 | } | |
9a799d71 | 4684 | |
9a799d71 | 4685 | first = tx_ring->next_to_use; |
eacd73f7 YZ |
4686 | if (tx_flags & IXGBE_TX_FLAGS_FCOE) { |
4687 | #ifdef IXGBE_FCOE | |
4688 | /* setup tx offload for FCoE */ | |
4689 | tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len); | |
4690 | if (tso < 0) { | |
4691 | dev_kfree_skb_any(skb); | |
4692 | return NETDEV_TX_OK; | |
4693 | } | |
4694 | if (tso) | |
4695 | tx_flags |= IXGBE_TX_FLAGS_FSO; | |
4696 | #endif /* IXGBE_FCOE */ | |
4697 | } else { | |
4698 | if (skb->protocol == htons(ETH_P_IP)) | |
4699 | tx_flags |= IXGBE_TX_FLAGS_IPV4; | |
4700 | tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len); | |
4701 | if (tso < 0) { | |
4702 | dev_kfree_skb_any(skb); | |
4703 | return NETDEV_TX_OK; | |
4704 | } | |
9a799d71 | 4705 | |
eacd73f7 YZ |
4706 | if (tso) |
4707 | tx_flags |= IXGBE_TX_FLAGS_TSO; | |
4708 | else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) && | |
4709 | (skb->ip_summed == CHECKSUM_PARTIAL)) | |
4710 | tx_flags |= IXGBE_TX_FLAGS_CSUM; | |
4711 | } | |
9a799d71 | 4712 | |
eacd73f7 | 4713 | count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first); |
44df32c5 AD |
4714 | if (count) { |
4715 | ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len, | |
4716 | hdr_len); | |
4717 | netdev->trans_start = jiffies; | |
4718 | ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED); | |
9a799d71 | 4719 | |
44df32c5 AD |
4720 | } else { |
4721 | dev_kfree_skb_any(skb); | |
4722 | tx_ring->tx_buffer_info[first].time_stamp = 0; | |
4723 | tx_ring->next_to_use = first; | |
4724 | } | |
9a799d71 AK |
4725 | |
4726 | return NETDEV_TX_OK; | |
4727 | } | |
4728 | ||
4729 | /** | |
4730 | * ixgbe_get_stats - Get System Network Statistics | |
4731 | * @netdev: network interface device structure | |
4732 | * | |
4733 | * Returns the address of the device statistics structure. | |
4734 | * The statistics are actually updated from the timer callback. | |
4735 | **/ | |
4736 | static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev) | |
4737 | { | |
4738 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4739 | ||
4740 | /* only return the current stats */ | |
4741 | return &adapter->net_stats; | |
4742 | } | |
4743 | ||
4744 | /** | |
4745 | * ixgbe_set_mac - Change the Ethernet Address of the NIC | |
4746 | * @netdev: network interface device structure | |
4747 | * @p: pointer to an address structure | |
4748 | * | |
4749 | * Returns 0 on success, negative on failure | |
4750 | **/ | |
4751 | static int ixgbe_set_mac(struct net_device *netdev, void *p) | |
4752 | { | |
4753 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
b4617240 | 4754 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 AK |
4755 | struct sockaddr *addr = p; |
4756 | ||
4757 | if (!is_valid_ether_addr(addr->sa_data)) | |
4758 | return -EADDRNOTAVAIL; | |
4759 | ||
4760 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | |
b4617240 | 4761 | memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); |
9a799d71 | 4762 | |
b4617240 | 4763 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); |
9a799d71 AK |
4764 | |
4765 | return 0; | |
4766 | } | |
4767 | ||
6b73e10d BH |
4768 | static int |
4769 | ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr) | |
4770 | { | |
4771 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4772 | struct ixgbe_hw *hw = &adapter->hw; | |
4773 | u16 value; | |
4774 | int rc; | |
4775 | ||
4776 | if (prtad != hw->phy.mdio.prtad) | |
4777 | return -EINVAL; | |
4778 | rc = hw->phy.ops.read_reg(hw, addr, devad, &value); | |
4779 | if (!rc) | |
4780 | rc = value; | |
4781 | return rc; | |
4782 | } | |
4783 | ||
4784 | static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad, | |
4785 | u16 addr, u16 value) | |
4786 | { | |
4787 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4788 | struct ixgbe_hw *hw = &adapter->hw; | |
4789 | ||
4790 | if (prtad != hw->phy.mdio.prtad) | |
4791 | return -EINVAL; | |
4792 | return hw->phy.ops.write_reg(hw, addr, devad, value); | |
4793 | } | |
4794 | ||
4795 | static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) | |
4796 | { | |
4797 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4798 | ||
4799 | return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd); | |
4800 | } | |
4801 | ||
9a799d71 AK |
4802 | #ifdef CONFIG_NET_POLL_CONTROLLER |
4803 | /* | |
4804 | * Polling 'interrupt' - used by things like netconsole to send skbs | |
4805 | * without having to re-enable interrupts. It's not called while | |
4806 | * the interrupt routine is executing. | |
4807 | */ | |
4808 | static void ixgbe_netpoll(struct net_device *netdev) | |
4809 | { | |
4810 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4811 | ||
4812 | disable_irq(adapter->pdev->irq); | |
4813 | adapter->flags |= IXGBE_FLAG_IN_NETPOLL; | |
4814 | ixgbe_intr(adapter->pdev->irq, netdev); | |
4815 | adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL; | |
4816 | enable_irq(adapter->pdev->irq); | |
4817 | } | |
4818 | #endif | |
4819 | ||
0edc3527 SH |
4820 | static const struct net_device_ops ixgbe_netdev_ops = { |
4821 | .ndo_open = ixgbe_open, | |
4822 | .ndo_stop = ixgbe_close, | |
00829823 | 4823 | .ndo_start_xmit = ixgbe_xmit_frame, |
09a3b1f8 | 4824 | .ndo_select_queue = ixgbe_select_queue, |
0edc3527 | 4825 | .ndo_get_stats = ixgbe_get_stats, |
e90d400c | 4826 | .ndo_set_rx_mode = ixgbe_set_rx_mode, |
0edc3527 SH |
4827 | .ndo_set_multicast_list = ixgbe_set_rx_mode, |
4828 | .ndo_validate_addr = eth_validate_addr, | |
4829 | .ndo_set_mac_address = ixgbe_set_mac, | |
4830 | .ndo_change_mtu = ixgbe_change_mtu, | |
4831 | .ndo_tx_timeout = ixgbe_tx_timeout, | |
4832 | .ndo_vlan_rx_register = ixgbe_vlan_rx_register, | |
4833 | .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid, | |
4834 | .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid, | |
6b73e10d | 4835 | .ndo_do_ioctl = ixgbe_ioctl, |
0edc3527 SH |
4836 | #ifdef CONFIG_NET_POLL_CONTROLLER |
4837 | .ndo_poll_controller = ixgbe_netpoll, | |
4838 | #endif | |
332d4a7d YZ |
4839 | #ifdef IXGBE_FCOE |
4840 | .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get, | |
4841 | .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put, | |
4842 | #endif /* IXGBE_FCOE */ | |
0edc3527 SH |
4843 | }; |
4844 | ||
9a799d71 AK |
4845 | /** |
4846 | * ixgbe_probe - Device Initialization Routine | |
4847 | * @pdev: PCI device information struct | |
4848 | * @ent: entry in ixgbe_pci_tbl | |
4849 | * | |
4850 | * Returns 0 on success, negative on failure | |
4851 | * | |
4852 | * ixgbe_probe initializes an adapter identified by a pci_dev structure. | |
4853 | * The OS initialization, configuring of the adapter private structure, | |
4854 | * and a hardware reset occur. | |
4855 | **/ | |
4856 | static int __devinit ixgbe_probe(struct pci_dev *pdev, | |
b4617240 | 4857 | const struct pci_device_id *ent) |
9a799d71 AK |
4858 | { |
4859 | struct net_device *netdev; | |
4860 | struct ixgbe_adapter *adapter = NULL; | |
4861 | struct ixgbe_hw *hw; | |
4862 | const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data]; | |
9a799d71 AK |
4863 | static int cards_found; |
4864 | int i, err, pci_using_dac; | |
eacd73f7 YZ |
4865 | #ifdef IXGBE_FCOE |
4866 | u16 device_caps; | |
4867 | #endif | |
c44ade9e | 4868 | u32 part_num, eec; |
9a799d71 | 4869 | |
9ce77666 | 4870 | err = pci_enable_device_mem(pdev); |
9a799d71 AK |
4871 | if (err) |
4872 | return err; | |
4873 | ||
6a35528a YH |
4874 | if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && |
4875 | !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) { | |
9a799d71 AK |
4876 | pci_using_dac = 1; |
4877 | } else { | |
284901a9 | 4878 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
9a799d71 | 4879 | if (err) { |
284901a9 | 4880 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
9a799d71 | 4881 | if (err) { |
b4617240 PW |
4882 | dev_err(&pdev->dev, "No usable DMA " |
4883 | "configuration, aborting\n"); | |
9a799d71 AK |
4884 | goto err_dma; |
4885 | } | |
4886 | } | |
4887 | pci_using_dac = 0; | |
4888 | } | |
4889 | ||
9ce77666 | 4890 | err = pci_request_selected_regions(pdev, pci_select_bars(pdev, |
4891 | IORESOURCE_MEM), ixgbe_driver_name); | |
9a799d71 | 4892 | if (err) { |
9ce77666 | 4893 | dev_err(&pdev->dev, |
4894 | "pci_request_selected_regions failed 0x%x\n", err); | |
9a799d71 AK |
4895 | goto err_pci_reg; |
4896 | } | |
4897 | ||
6fabd715 PWJ |
4898 | err = pci_enable_pcie_error_reporting(pdev); |
4899 | if (err) { | |
4900 | dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed " | |
4901 | "0x%x\n", err); | |
4902 | /* non-fatal, continue */ | |
4903 | } | |
4904 | ||
9a799d71 | 4905 | pci_set_master(pdev); |
fb3b27bc | 4906 | pci_save_state(pdev); |
9a799d71 | 4907 | |
30eba97a | 4908 | netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES); |
9a799d71 AK |
4909 | if (!netdev) { |
4910 | err = -ENOMEM; | |
4911 | goto err_alloc_etherdev; | |
4912 | } | |
4913 | ||
9a799d71 AK |
4914 | SET_NETDEV_DEV(netdev, &pdev->dev); |
4915 | ||
4916 | pci_set_drvdata(pdev, netdev); | |
4917 | adapter = netdev_priv(netdev); | |
4918 | ||
4919 | adapter->netdev = netdev; | |
4920 | adapter->pdev = pdev; | |
4921 | hw = &adapter->hw; | |
4922 | hw->back = adapter; | |
4923 | adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1; | |
4924 | ||
05857980 JK |
4925 | hw->hw_addr = ioremap(pci_resource_start(pdev, 0), |
4926 | pci_resource_len(pdev, 0)); | |
9a799d71 AK |
4927 | if (!hw->hw_addr) { |
4928 | err = -EIO; | |
4929 | goto err_ioremap; | |
4930 | } | |
4931 | ||
4932 | for (i = 1; i <= 5; i++) { | |
4933 | if (pci_resource_len(pdev, i) == 0) | |
4934 | continue; | |
4935 | } | |
4936 | ||
0edc3527 | 4937 | netdev->netdev_ops = &ixgbe_netdev_ops; |
9a799d71 | 4938 | ixgbe_set_ethtool_ops(netdev); |
9a799d71 | 4939 | netdev->watchdog_timeo = 5 * HZ; |
9a799d71 AK |
4940 | strcpy(netdev->name, pci_name(pdev)); |
4941 | ||
9a799d71 AK |
4942 | adapter->bd_number = cards_found; |
4943 | ||
9a799d71 AK |
4944 | /* Setup hw api */ |
4945 | memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops)); | |
021230d4 | 4946 | hw->mac.type = ii->mac; |
9a799d71 | 4947 | |
c44ade9e JB |
4948 | /* EEPROM */ |
4949 | memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops)); | |
4950 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); | |
4951 | /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */ | |
4952 | if (!(eec & (1 << 8))) | |
4953 | hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic; | |
4954 | ||
4955 | /* PHY */ | |
4956 | memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops)); | |
c4900be0 | 4957 | hw->phy.sfp_type = ixgbe_sfp_type_unknown; |
6b73e10d BH |
4958 | /* ixgbe_identify_phy_generic will set prtad and mmds properly */ |
4959 | hw->phy.mdio.prtad = MDIO_PRTAD_NONE; | |
4960 | hw->phy.mdio.mmds = 0; | |
4961 | hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; | |
4962 | hw->phy.mdio.dev = netdev; | |
4963 | hw->phy.mdio.mdio_read = ixgbe_mdio_read; | |
4964 | hw->phy.mdio.mdio_write = ixgbe_mdio_write; | |
c4900be0 DS |
4965 | |
4966 | /* set up this timer and work struct before calling get_invariants | |
4967 | * which might start the timer | |
4968 | */ | |
4969 | init_timer(&adapter->sfp_timer); | |
4970 | adapter->sfp_timer.function = &ixgbe_sfp_timer; | |
4971 | adapter->sfp_timer.data = (unsigned long) adapter; | |
4972 | ||
4973 | INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task); | |
c44ade9e | 4974 | |
e8e26350 PW |
4975 | /* multispeed fiber has its own tasklet, called from GPI SDP1 context */ |
4976 | INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task); | |
4977 | ||
4978 | /* a new SFP+ module arrival, called from GPI SDP2 context */ | |
4979 | INIT_WORK(&adapter->sfp_config_module_task, | |
4980 | ixgbe_sfp_config_module_task); | |
4981 | ||
9a799d71 | 4982 | err = ii->get_invariants(hw); |
c4900be0 DS |
4983 | if (err == IXGBE_ERR_SFP_NOT_PRESENT) { |
4984 | /* start a kernel thread to watch for a module to arrive */ | |
4985 | set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); | |
4986 | mod_timer(&adapter->sfp_timer, | |
4987 | round_jiffies(jiffies + (2 * HZ))); | |
4988 | err = 0; | |
4989 | } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
4990 | DPRINTK(PROBE, ERR, "failed to load because an " | |
4991 | "unsupported SFP+ module type was detected.\n"); | |
9a799d71 | 4992 | goto err_hw_init; |
c4900be0 DS |
4993 | } else if (err) { |
4994 | goto err_hw_init; | |
4995 | } | |
9a799d71 AK |
4996 | |
4997 | /* setup the private structure */ | |
4998 | err = ixgbe_sw_init(adapter); | |
4999 | if (err) | |
5000 | goto err_sw_init; | |
5001 | ||
bf069c97 DS |
5002 | /* |
5003 | * If there is a fan on this device and it has failed log the | |
5004 | * failure. | |
5005 | */ | |
5006 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
5007 | u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); | |
5008 | if (esdp & IXGBE_ESDP_SDP1) | |
5009 | DPRINTK(PROBE, CRIT, | |
5010 | "Fan has stopped, replace the adapter\n"); | |
5011 | } | |
5012 | ||
c44ade9e JB |
5013 | /* reset_hw fills in the perm_addr as well */ |
5014 | err = hw->mac.ops.reset_hw(hw); | |
04f165ef PW |
5015 | if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { |
5016 | dev_err(&adapter->pdev->dev, "failed to load because an " | |
5017 | "unsupported SFP+ module type was detected.\n"); | |
5018 | goto err_sw_init; | |
5019 | } else if (err) { | |
c44ade9e JB |
5020 | dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err); |
5021 | goto err_sw_init; | |
5022 | } | |
5023 | ||
9a799d71 | 5024 | netdev->features = NETIF_F_SG | |
b4617240 PW |
5025 | NETIF_F_IP_CSUM | |
5026 | NETIF_F_HW_VLAN_TX | | |
5027 | NETIF_F_HW_VLAN_RX | | |
5028 | NETIF_F_HW_VLAN_FILTER; | |
9a799d71 | 5029 | |
e9990a9c | 5030 | netdev->features |= NETIF_F_IPV6_CSUM; |
9a799d71 | 5031 | netdev->features |= NETIF_F_TSO; |
9a799d71 | 5032 | netdev->features |= NETIF_F_TSO6; |
78b6f4ce | 5033 | netdev->features |= NETIF_F_GRO; |
ad31c402 | 5034 | |
45a5ead0 JB |
5035 | if (adapter->hw.mac.type == ixgbe_mac_82599EB) |
5036 | netdev->features |= NETIF_F_SCTP_CSUM; | |
5037 | ||
ad31c402 JK |
5038 | netdev->vlan_features |= NETIF_F_TSO; |
5039 | netdev->vlan_features |= NETIF_F_TSO6; | |
22f32b7a | 5040 | netdev->vlan_features |= NETIF_F_IP_CSUM; |
ad31c402 JK |
5041 | netdev->vlan_features |= NETIF_F_SG; |
5042 | ||
2f90b865 AD |
5043 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) |
5044 | adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED; | |
5045 | ||
7a6b6f51 | 5046 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
5047 | netdev->dcbnl_ops = &dcbnl_ops; |
5048 | #endif | |
5049 | ||
eacd73f7 YZ |
5050 | #ifdef IXGBE_FCOE |
5051 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { | |
5052 | if (hw->mac.ops.get_device_caps) { | |
5053 | hw->mac.ops.get_device_caps(hw, &device_caps); | |
5054 | if (!(device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)) { | |
5055 | netdev->features |= NETIF_F_FCOE_CRC; | |
5056 | netdev->features |= NETIF_F_FSO; | |
332d4a7d | 5057 | netdev->fcoe_ddp_xid = IXGBE_FCOE_DDP_MAX - 1; |
eacd73f7 YZ |
5058 | } else { |
5059 | adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; | |
5060 | } | |
5061 | } | |
5062 | } | |
5063 | #endif /* IXGBE_FCOE */ | |
9a799d71 AK |
5064 | if (pci_using_dac) |
5065 | netdev->features |= NETIF_F_HIGHDMA; | |
5066 | ||
f8212f97 AD |
5067 | if (adapter->flags & IXGBE_FLAG_RSC_ENABLED) |
5068 | netdev->features |= NETIF_F_LRO; | |
5069 | ||
9a799d71 | 5070 | /* make sure the EEPROM is good */ |
c44ade9e | 5071 | if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) { |
9a799d71 AK |
5072 | dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n"); |
5073 | err = -EIO; | |
5074 | goto err_eeprom; | |
5075 | } | |
5076 | ||
5077 | memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len); | |
5078 | memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len); | |
5079 | ||
c44ade9e JB |
5080 | if (ixgbe_validate_mac_addr(netdev->perm_addr)) { |
5081 | dev_err(&pdev->dev, "invalid MAC address\n"); | |
9a799d71 AK |
5082 | err = -EIO; |
5083 | goto err_eeprom; | |
5084 | } | |
5085 | ||
5086 | init_timer(&adapter->watchdog_timer); | |
5087 | adapter->watchdog_timer.function = &ixgbe_watchdog; | |
5088 | adapter->watchdog_timer.data = (unsigned long)adapter; | |
5089 | ||
5090 | INIT_WORK(&adapter->reset_task, ixgbe_reset_task); | |
cf8280ee | 5091 | INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task); |
9a799d71 | 5092 | |
021230d4 AV |
5093 | err = ixgbe_init_interrupt_scheme(adapter); |
5094 | if (err) | |
5095 | goto err_sw_init; | |
9a799d71 | 5096 | |
e8e26350 PW |
5097 | switch (pdev->device) { |
5098 | case IXGBE_DEV_ID_82599_KX4: | |
495dce12 WJP |
5099 | adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX | |
5100 | IXGBE_WUFC_MC | IXGBE_WUFC_BC); | |
e8e26350 PW |
5101 | break; |
5102 | default: | |
5103 | adapter->wol = 0; | |
5104 | break; | |
5105 | } | |
5106 | device_init_wakeup(&adapter->pdev->dev, true); | |
5107 | device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); | |
5108 | ||
04f165ef PW |
5109 | /* pick up the PCI bus settings for reporting later */ |
5110 | hw->mac.ops.get_bus_info(hw); | |
5111 | ||
9a799d71 | 5112 | /* print bus type/speed/width info */ |
7c510e4b | 5113 | dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n", |
e8e26350 PW |
5114 | ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s": |
5115 | (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"), | |
5116 | ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" : | |
5117 | (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" : | |
5118 | (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" : | |
b4617240 | 5119 | "Unknown"), |
7c510e4b | 5120 | netdev->dev_addr); |
c44ade9e | 5121 | ixgbe_read_pba_num_generic(hw, &part_num); |
e8e26350 PW |
5122 | if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) |
5123 | dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n", | |
5124 | hw->mac.type, hw->phy.type, hw->phy.sfp_type, | |
5125 | (part_num >> 8), (part_num & 0xff)); | |
5126 | else | |
5127 | dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n", | |
5128 | hw->mac.type, hw->phy.type, | |
5129 | (part_num >> 8), (part_num & 0xff)); | |
9a799d71 | 5130 | |
e8e26350 | 5131 | if (hw->bus.width <= ixgbe_bus_width_pcie_x4) { |
0c254d86 | 5132 | dev_warn(&pdev->dev, "PCI-Express bandwidth available for " |
b4617240 PW |
5133 | "this card is not sufficient for optimal " |
5134 | "performance.\n"); | |
0c254d86 | 5135 | dev_warn(&pdev->dev, "For optimal performance a x8 " |
b4617240 | 5136 | "PCI-Express slot is required.\n"); |
0c254d86 AK |
5137 | } |
5138 | ||
34b0368c PWJ |
5139 | /* save off EEPROM version number */ |
5140 | hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version); | |
5141 | ||
9a799d71 | 5142 | /* reset the hardware with the new settings */ |
c44ade9e JB |
5143 | hw->mac.ops.start_hw(hw); |
5144 | ||
9a799d71 AK |
5145 | strcpy(netdev->name, "eth%d"); |
5146 | err = register_netdev(netdev); | |
5147 | if (err) | |
5148 | goto err_register; | |
5149 | ||
54386467 JB |
5150 | /* carrier off reporting is important to ethtool even BEFORE open */ |
5151 | netif_carrier_off(netdev); | |
5152 | ||
5dd2d332 | 5153 | #ifdef CONFIG_IXGBE_DCA |
652f093f | 5154 | if (dca_add_requester(&pdev->dev) == 0) { |
bd0362dd JC |
5155 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; |
5156 | /* always use CB2 mode, difference is masked | |
5157 | * in the CB driver */ | |
5158 | IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2); | |
5159 | ixgbe_setup_dca(adapter); | |
5160 | } | |
5161 | #endif | |
9a799d71 AK |
5162 | |
5163 | dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n"); | |
5164 | cards_found++; | |
5165 | return 0; | |
5166 | ||
5167 | err_register: | |
5eba3699 | 5168 | ixgbe_release_hw_control(adapter); |
9a799d71 | 5169 | err_hw_init: |
7a921c93 | 5170 | ixgbe_clear_interrupt_scheme(adapter); |
9a799d71 AK |
5171 | err_sw_init: |
5172 | err_eeprom: | |
c4900be0 DS |
5173 | clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); |
5174 | del_timer_sync(&adapter->sfp_timer); | |
5175 | cancel_work_sync(&adapter->sfp_task); | |
e8e26350 PW |
5176 | cancel_work_sync(&adapter->multispeed_fiber_task); |
5177 | cancel_work_sync(&adapter->sfp_config_module_task); | |
9a799d71 AK |
5178 | iounmap(hw->hw_addr); |
5179 | err_ioremap: | |
5180 | free_netdev(netdev); | |
5181 | err_alloc_etherdev: | |
9ce77666 | 5182 | pci_release_selected_regions(pdev, pci_select_bars(pdev, |
5183 | IORESOURCE_MEM)); | |
9a799d71 AK |
5184 | err_pci_reg: |
5185 | err_dma: | |
5186 | pci_disable_device(pdev); | |
5187 | return err; | |
5188 | } | |
5189 | ||
5190 | /** | |
5191 | * ixgbe_remove - Device Removal Routine | |
5192 | * @pdev: PCI device information struct | |
5193 | * | |
5194 | * ixgbe_remove is called by the PCI subsystem to alert the driver | |
5195 | * that it should release a PCI device. The could be caused by a | |
5196 | * Hot-Plug event, or because the driver is going to be removed from | |
5197 | * memory. | |
5198 | **/ | |
5199 | static void __devexit ixgbe_remove(struct pci_dev *pdev) | |
5200 | { | |
5201 | struct net_device *netdev = pci_get_drvdata(pdev); | |
5202 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6fabd715 | 5203 | int err; |
9a799d71 AK |
5204 | |
5205 | set_bit(__IXGBE_DOWN, &adapter->state); | |
c4900be0 DS |
5206 | /* clear the module not found bit to make sure the worker won't |
5207 | * reschedule | |
5208 | */ | |
5209 | clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); | |
9a799d71 AK |
5210 | del_timer_sync(&adapter->watchdog_timer); |
5211 | ||
c4900be0 DS |
5212 | del_timer_sync(&adapter->sfp_timer); |
5213 | cancel_work_sync(&adapter->watchdog_task); | |
5214 | cancel_work_sync(&adapter->sfp_task); | |
e8e26350 PW |
5215 | cancel_work_sync(&adapter->multispeed_fiber_task); |
5216 | cancel_work_sync(&adapter->sfp_config_module_task); | |
9a799d71 AK |
5217 | flush_scheduled_work(); |
5218 | ||
5dd2d332 | 5219 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
5220 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { |
5221 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
5222 | dca_remove_requester(&pdev->dev); | |
5223 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); | |
5224 | } | |
5225 | ||
5226 | #endif | |
332d4a7d YZ |
5227 | #ifdef IXGBE_FCOE |
5228 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) | |
5229 | ixgbe_cleanup_fcoe(adapter); | |
5230 | ||
5231 | #endif /* IXGBE_FCOE */ | |
c4900be0 DS |
5232 | if (netdev->reg_state == NETREG_REGISTERED) |
5233 | unregister_netdev(netdev); | |
9a799d71 | 5234 | |
7a921c93 | 5235 | ixgbe_clear_interrupt_scheme(adapter); |
5eba3699 | 5236 | |
021230d4 | 5237 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
5238 | |
5239 | iounmap(adapter->hw.hw_addr); | |
9ce77666 | 5240 | pci_release_selected_regions(pdev, pci_select_bars(pdev, |
5241 | IORESOURCE_MEM)); | |
9a799d71 | 5242 | |
021230d4 | 5243 | DPRINTK(PROBE, INFO, "complete\n"); |
021230d4 | 5244 | |
9a799d71 AK |
5245 | free_netdev(netdev); |
5246 | ||
6fabd715 PWJ |
5247 | err = pci_disable_pcie_error_reporting(pdev); |
5248 | if (err) | |
5249 | dev_err(&pdev->dev, | |
5250 | "pci_disable_pcie_error_reporting failed 0x%x\n", err); | |
5251 | ||
9a799d71 AK |
5252 | pci_disable_device(pdev); |
5253 | } | |
5254 | ||
5255 | /** | |
5256 | * ixgbe_io_error_detected - called when PCI error is detected | |
5257 | * @pdev: Pointer to PCI device | |
5258 | * @state: The current pci connection state | |
5259 | * | |
5260 | * This function is called after a PCI bus error affecting | |
5261 | * this device has been detected. | |
5262 | */ | |
5263 | static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev, | |
b4617240 | 5264 | pci_channel_state_t state) |
9a799d71 AK |
5265 | { |
5266 | struct net_device *netdev = pci_get_drvdata(pdev); | |
454d7c9b | 5267 | struct ixgbe_adapter *adapter = netdev_priv(netdev); |
9a799d71 AK |
5268 | |
5269 | netif_device_detach(netdev); | |
5270 | ||
3044b8d1 BL |
5271 | if (state == pci_channel_io_perm_failure) |
5272 | return PCI_ERS_RESULT_DISCONNECT; | |
5273 | ||
9a799d71 AK |
5274 | if (netif_running(netdev)) |
5275 | ixgbe_down(adapter); | |
5276 | pci_disable_device(pdev); | |
5277 | ||
b4617240 | 5278 | /* Request a slot reset. */ |
9a799d71 AK |
5279 | return PCI_ERS_RESULT_NEED_RESET; |
5280 | } | |
5281 | ||
5282 | /** | |
5283 | * ixgbe_io_slot_reset - called after the pci bus has been reset. | |
5284 | * @pdev: Pointer to PCI device | |
5285 | * | |
5286 | * Restart the card from scratch, as if from a cold-boot. | |
5287 | */ | |
5288 | static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev) | |
5289 | { | |
5290 | struct net_device *netdev = pci_get_drvdata(pdev); | |
454d7c9b | 5291 | struct ixgbe_adapter *adapter = netdev_priv(netdev); |
6fabd715 PWJ |
5292 | pci_ers_result_t result; |
5293 | int err; | |
9a799d71 | 5294 | |
9ce77666 | 5295 | if (pci_enable_device_mem(pdev)) { |
9a799d71 | 5296 | DPRINTK(PROBE, ERR, |
b4617240 | 5297 | "Cannot re-enable PCI device after reset.\n"); |
6fabd715 PWJ |
5298 | result = PCI_ERS_RESULT_DISCONNECT; |
5299 | } else { | |
5300 | pci_set_master(pdev); | |
5301 | pci_restore_state(pdev); | |
9a799d71 | 5302 | |
dd4d8ca6 | 5303 | pci_wake_from_d3(pdev, false); |
9a799d71 | 5304 | |
6fabd715 | 5305 | ixgbe_reset(adapter); |
88512539 | 5306 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
6fabd715 PWJ |
5307 | result = PCI_ERS_RESULT_RECOVERED; |
5308 | } | |
5309 | ||
5310 | err = pci_cleanup_aer_uncorrect_error_status(pdev); | |
5311 | if (err) { | |
5312 | dev_err(&pdev->dev, | |
5313 | "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err); | |
5314 | /* non-fatal, continue */ | |
5315 | } | |
9a799d71 | 5316 | |
6fabd715 | 5317 | return result; |
9a799d71 AK |
5318 | } |
5319 | ||
5320 | /** | |
5321 | * ixgbe_io_resume - called when traffic can start flowing again. | |
5322 | * @pdev: Pointer to PCI device | |
5323 | * | |
5324 | * This callback is called when the error recovery driver tells us that | |
5325 | * its OK to resume normal operation. | |
5326 | */ | |
5327 | static void ixgbe_io_resume(struct pci_dev *pdev) | |
5328 | { | |
5329 | struct net_device *netdev = pci_get_drvdata(pdev); | |
454d7c9b | 5330 | struct ixgbe_adapter *adapter = netdev_priv(netdev); |
9a799d71 AK |
5331 | |
5332 | if (netif_running(netdev)) { | |
5333 | if (ixgbe_up(adapter)) { | |
5334 | DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n"); | |
5335 | return; | |
5336 | } | |
5337 | } | |
5338 | ||
5339 | netif_device_attach(netdev); | |
9a799d71 AK |
5340 | } |
5341 | ||
5342 | static struct pci_error_handlers ixgbe_err_handler = { | |
5343 | .error_detected = ixgbe_io_error_detected, | |
5344 | .slot_reset = ixgbe_io_slot_reset, | |
5345 | .resume = ixgbe_io_resume, | |
5346 | }; | |
5347 | ||
5348 | static struct pci_driver ixgbe_driver = { | |
5349 | .name = ixgbe_driver_name, | |
5350 | .id_table = ixgbe_pci_tbl, | |
5351 | .probe = ixgbe_probe, | |
5352 | .remove = __devexit_p(ixgbe_remove), | |
5353 | #ifdef CONFIG_PM | |
5354 | .suspend = ixgbe_suspend, | |
5355 | .resume = ixgbe_resume, | |
5356 | #endif | |
5357 | .shutdown = ixgbe_shutdown, | |
5358 | .err_handler = &ixgbe_err_handler | |
5359 | }; | |
5360 | ||
5361 | /** | |
5362 | * ixgbe_init_module - Driver Registration Routine | |
5363 | * | |
5364 | * ixgbe_init_module is the first routine called when the driver is | |
5365 | * loaded. All it does is register with the PCI subsystem. | |
5366 | **/ | |
5367 | static int __init ixgbe_init_module(void) | |
5368 | { | |
5369 | int ret; | |
5370 | printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name, | |
5371 | ixgbe_driver_string, ixgbe_driver_version); | |
5372 | ||
5373 | printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright); | |
5374 | ||
5dd2d332 | 5375 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 5376 | dca_register_notify(&dca_notifier); |
bd0362dd | 5377 | #endif |
5dd2d332 | 5378 | |
9a799d71 AK |
5379 | ret = pci_register_driver(&ixgbe_driver); |
5380 | return ret; | |
5381 | } | |
b4617240 | 5382 | |
9a799d71 AK |
5383 | module_init(ixgbe_init_module); |
5384 | ||
5385 | /** | |
5386 | * ixgbe_exit_module - Driver Exit Cleanup Routine | |
5387 | * | |
5388 | * ixgbe_exit_module is called just before the driver is removed | |
5389 | * from memory. | |
5390 | **/ | |
5391 | static void __exit ixgbe_exit_module(void) | |
5392 | { | |
5dd2d332 | 5393 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
5394 | dca_unregister_notify(&dca_notifier); |
5395 | #endif | |
9a799d71 AK |
5396 | pci_unregister_driver(&ixgbe_driver); |
5397 | } | |
bd0362dd | 5398 | |
5dd2d332 | 5399 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 5400 | static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event, |
b4617240 | 5401 | void *p) |
bd0362dd JC |
5402 | { |
5403 | int ret_val; | |
5404 | ||
5405 | ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event, | |
b4617240 | 5406 | __ixgbe_notify_dca); |
bd0362dd JC |
5407 | |
5408 | return ret_val ? NOTIFY_BAD : NOTIFY_DONE; | |
5409 | } | |
b453368d | 5410 | |
5dd2d332 | 5411 | #endif /* CONFIG_IXGBE_DCA */ |
b453368d AD |
5412 | #ifdef DEBUG |
5413 | /** | |
5414 | * ixgbe_get_hw_dev_name - return device name string | |
5415 | * used by hardware layer to print debugging information | |
5416 | **/ | |
5417 | char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw) | |
5418 | { | |
5419 | struct ixgbe_adapter *adapter = hw->back; | |
5420 | return adapter->netdev->name; | |
5421 | } | |
bd0362dd | 5422 | |
b453368d | 5423 | #endif |
9a799d71 AK |
5424 | module_exit(ixgbe_exit_module); |
5425 | ||
5426 | /* ixgbe_main.c */ |