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ixgbe: Introduce adaptive interrupt moderation
[mirror_ubuntu-zesty-kernel.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2007 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include <linux/types.h>
30#include <linux/module.h>
31#include <linux/pci.h>
32#include <linux/netdevice.h>
33#include <linux/vmalloc.h>
34#include <linux/string.h>
35#include <linux/in.h>
36#include <linux/ip.h>
37#include <linux/tcp.h>
38#include <linux/ipv6.h>
39#include <net/checksum.h>
40#include <net/ip6_checksum.h>
41#include <linux/ethtool.h>
42#include <linux/if_vlan.h>
43
44#include "ixgbe.h"
45#include "ixgbe_common.h"
46
47char ixgbe_driver_name[] = "ixgbe";
9c8eb720
SH		 48static const char ixgbe_driver_string[] =
49 "Intel(R) 10 Gigabit PCI Express Network Driver";
9a799d71
AK		 50
51#define DRV_VERSION "1.1.18"
9c8eb720
SH		 52const char ixgbe_driver_version[] = DRV_VERSION;
53static const char ixgbe_copyright[] =
54 "Copyright (c) 1999-2007 Intel Corporation.";
9a799d71
AK		 55
56static const struct ixgbe_info *ixgbe_info_tbl[] = {
3957d63d 57 [board_82598] = &ixgbe_82598_info,
9a799d71
AK		 58};
59
60/* ixgbe_pci_tbl - PCI Device ID Table
61 *
62 * Wildcard entries (PCI_ANY_ID) should come last
63 * Last entry must be all 0s
64 *
65 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
66 * Class, Class Mask, private data (not used) }
67 */
68static struct pci_device_id ixgbe_pci_tbl[] = {
69 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 70 board_82598 },
9a799d71 71 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 72 board_82598 },
9a799d71 73 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT_DUAL_PORT),
3957d63d 74 board_82598 },
9a799d71 75 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 76 board_82598 },
9a799d71
AK		 77
78 /* required last entry */
79 {0, }
80};
81MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
82
83MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
84MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
85MODULE_LICENSE("GPL");
86MODULE_VERSION(DRV_VERSION);
87
88#define DEFAULT_DEBUG_LEVEL_SHIFT 3
89
5eba3699
AV		 90static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
91{
92 u32 ctrl_ext;
93
94 /* Let firmware take over control of h/w */
95 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
96 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
97 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
98}
99
100static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
101{
102 u32 ctrl_ext;
103
104 /* Let firmware know the driver has taken over */
105 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
106 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
107 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
108}
9a799d71
AK		 109
110#ifdef DEBUG
111/**
112 * ixgbe_get_hw_dev_name - return device name string
113 * used by hardware layer to print debugging information
114 **/
115char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
116{
117 struct ixgbe_adapter *adapter = hw->back;
118 struct net_device *netdev = adapter->netdev;
119 return netdev->name;
120}
121#endif
122
123static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, u16 int_alloc_entry,
124 u8 msix_vector)
125{
126 u32 ivar, index;
127
128 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
129 index = (int_alloc_entry >> 2) & 0x1F;
130 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR(index));
131 ivar &= ~(0xFF << (8 * (int_alloc_entry & 0x3)));
132 ivar |= (msix_vector << (8 * (int_alloc_entry & 0x3)));
133 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR(index), ivar);
134}
135
136static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
137 struct ixgbe_tx_buffer
138 *tx_buffer_info)
139{
140 if (tx_buffer_info->dma) {
141 pci_unmap_page(adapter->pdev,
142 tx_buffer_info->dma,
143 tx_buffer_info->length, PCI_DMA_TODEVICE);
144 tx_buffer_info->dma = 0;
145 }
146 if (tx_buffer_info->skb) {
147 dev_kfree_skb_any(tx_buffer_info->skb);
148 tx_buffer_info->skb = NULL;
149 }
150 /* tx_buffer_info must be completely set up in the transmit path */
151}
152
153static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
154 struct ixgbe_ring *tx_ring,
155 unsigned int eop,
156 union ixgbe_adv_tx_desc *eop_desc)
157{
158 /* Detect a transmit hang in hardware, this serializes the
159 * check with the clearing of time_stamp and movement of i */
160 adapter->detect_tx_hung = false;
161 if (tx_ring->tx_buffer_info[eop].dma &&
162 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
163 !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
164 /* detected Tx unit hang */
165 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
166 " TDH <%x>\n"
167 " TDT <%x>\n"
168 " next_to_use <%x>\n"
169 " next_to_clean <%x>\n"
170 "tx_buffer_info[next_to_clean]\n"
171 " time_stamp <%lx>\n"
172 " next_to_watch <%x>\n"
173 " jiffies <%lx>\n"
174 " next_to_watch.status <%x>\n",
175 readl(adapter->hw.hw_addr + tx_ring->head),
176 readl(adapter->hw.hw_addr + tx_ring->tail),
177 tx_ring->next_to_use,
178 tx_ring->next_to_clean,
179 tx_ring->tx_buffer_info[eop].time_stamp,
180 eop, jiffies, eop_desc->wb.status);
181 return true;
182 }
183
184 return false;
185}
186
e092be60
AV		 187#define IXGBE_MAX_TXD_PWR 14
188#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
189
190/* Tx Descriptors needed, worst case */
191#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
192 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
193#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
194 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
195
9a799d71
AK		 196/**
197 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
198 * @adapter: board private structure
199 **/
200static bool ixgbe_clean_tx_irq(struct ixgbe_adapter *adapter,
201 struct ixgbe_ring *tx_ring)
202{
203 struct net_device *netdev = adapter->netdev;
204 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
205 struct ixgbe_tx_buffer *tx_buffer_info;
206 unsigned int i, eop;
207 bool cleaned = false;
e092be60 208 unsigned int total_tx_bytes = 0, total_tx_packets = 0;
9a799d71
AK		 209
210 i = tx_ring->next_to_clean;
211 eop = tx_ring->tx_buffer_info[i].next_to_watch;
212 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
213 while (eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) {
e092be60
AV		 214 cleaned = false;
215 while (!cleaned) {
9a799d71
AK		 216 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
217 tx_buffer_info = &tx_ring->tx_buffer_info[i];
218 cleaned = (i == eop);
219
220 tx_ring->stats.bytes += tx_buffer_info->length;
e092be60
AV		 221 if (cleaned) {
222 struct sk_buff *skb = tx_buffer_info->skb;
e092be60
AV		 223 unsigned int segs, bytecount;
224 segs = skb_shinfo(skb)->gso_segs ?: 1;
225 /* multiply data chunks by size of headers */
226 bytecount = ((segs - 1) * skb_headlen(skb)) +
227 skb->len;
228 total_tx_packets += segs;
229 total_tx_bytes += bytecount;
e092be60 230 }
9a799d71
AK		 231 ixgbe_unmap_and_free_tx_resource(adapter,
232 tx_buffer_info);
233 tx_desc->wb.status = 0;
234
235 i++;
236 if (i == tx_ring->count)
237 i = 0;
238 }
239
240 tx_ring->stats.packets++;
241
242 eop = tx_ring->tx_buffer_info[i].next_to_watch;
243 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
244
245 /* weight of a sort for tx, avoid endless transmit cleanup */
e092be60 246 if (total_tx_packets >= tx_ring->work_limit)
9a799d71
AK		 247 break;
248 }
249
250 tx_ring->next_to_clean = i;
251
e092be60
AV		 252#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
253 if (total_tx_packets && netif_carrier_ok(netdev) &&
254 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD)) {
255 /* Make sure that anybody stopping the queue after this
256 * sees the new next_to_clean.
257 */
258 smp_mb();
30eba97a
AV		 259#ifdef CONFIG_NETDEVICES_MULTIQUEUE
260 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
261 !test_bit(__IXGBE_DOWN, &adapter->state)) {
262 netif_wake_subqueue(netdev, tx_ring->queue_index);
263 adapter->restart_queue++;
264 }
265#else
e092be60
AV		 266 if (netif_queue_stopped(netdev) &&
267 !test_bit(__IXGBE_DOWN, &adapter->state)) {
268 netif_wake_queue(netdev);
269 adapter->restart_queue++;
270 }
30eba97a 271#endif
e092be60 272 }
9a799d71
AK		 273
274 if (adapter->detect_tx_hung)
275 if (ixgbe_check_tx_hang(adapter, tx_ring, eop, eop_desc))
30eba97a
AV		 276#ifdef CONFIG_NETDEVICES_MULTIQUEUE
277 netif_stop_subqueue(netdev, tx_ring->queue_index);
278#else
9a799d71 279 netif_stop_queue(netdev);
30eba97a 280#endif
9a799d71 281
e092be60 282 if (total_tx_packets >= tx_ring->work_limit)
9a799d71
AK		 283 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, tx_ring->eims_value);
284
f494e8fa
AV		 285 tx_ring->total_bytes += total_tx_bytes;
286 tx_ring->total_packets += total_tx_packets;
d2f4fbe2
AV		 287 adapter->net_stats.tx_bytes += total_tx_bytes;
288 adapter->net_stats.tx_packets += total_tx_packets;
e092be60 289 cleaned = total_tx_packets ? true : false;
9a799d71
AK		 290 return cleaned;
291}
292
293/**
294 * ixgbe_receive_skb - Send a completed packet up the stack
295 * @adapter: board private structure
296 * @skb: packet to send up
297 * @is_vlan: packet has a VLAN tag
298 * @tag: VLAN tag from descriptor
299 **/
300static void ixgbe_receive_skb(struct ixgbe_adapter *adapter,
301 struct sk_buff *skb, bool is_vlan,
302 u16 tag)
303{
304 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
305 if (adapter->vlgrp && is_vlan)
306 vlan_hwaccel_receive_skb(skb, adapter->vlgrp, tag);
307 else
308 netif_receive_skb(skb);
309 } else {
310
311 if (adapter->vlgrp && is_vlan)
312 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
313 else
314 netif_rx(skb);
315 }
316}
317
e59bd25d
AV		 318/**
319 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
320 * @adapter: address of board private structure
321 * @status_err: hardware indication of status of receive
322 * @skb: skb currently being received and modified
323 **/
9a799d71
AK		 324static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
325 u32 status_err,
326 struct sk_buff *skb)
327{
328 skb->ip_summed = CHECKSUM_NONE;
329
e59bd25d 330 /* Ignore Checksum bit is set, or rx csum disabled */
9a799d71 331 if ((status_err & IXGBE_RXD_STAT_IXSM) ||
e59bd25d 332 !(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 333 return;
e59bd25d
AV		 334
335 /* if IP and error */
336 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
337 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 338 adapter->hw_csum_rx_error++;
339 return;
340 }
e59bd25d
AV		 341
342 if (!(status_err & IXGBE_RXD_STAT_L4CS))
343 return;
344
345 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
346 adapter->hw_csum_rx_error++;
347 return;
348 }
349
9a799d71 350 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 351 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 352 adapter->hw_csum_rx_good++;
353}
354
355/**
356 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
357 * @adapter: address of board private structure
358 **/
359static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
360 struct ixgbe_ring *rx_ring,
361 int cleaned_count)
362{
363 struct net_device *netdev = adapter->netdev;
364 struct pci_dev *pdev = adapter->pdev;
365 union ixgbe_adv_rx_desc *rx_desc;
366 struct ixgbe_rx_buffer *rx_buffer_info;
367 struct sk_buff *skb;
368 unsigned int i;
369 unsigned int bufsz = adapter->rx_buf_len + NET_IP_ALIGN;
370
371 i = rx_ring->next_to_use;
372 rx_buffer_info = &rx_ring->rx_buffer_info[i];
373
374 while (cleaned_count--) {
375 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
376
377 if (!rx_buffer_info->page &&
378 (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) {
379 rx_buffer_info->page = alloc_page(GFP_ATOMIC);
380 if (!rx_buffer_info->page) {
381 adapter->alloc_rx_page_failed++;
382 goto no_buffers;
383 }
384 rx_buffer_info->page_dma =
385 pci_map_page(pdev, rx_buffer_info->page,
386 0, PAGE_SIZE, PCI_DMA_FROMDEVICE);
387 }
388
389 if (!rx_buffer_info->skb) {
390 skb = netdev_alloc_skb(netdev, bufsz);
391
392 if (!skb) {
393 adapter->alloc_rx_buff_failed++;
394 goto no_buffers;
395 }
396
397 /*
398 * Make buffer alignment 2 beyond a 16 byte boundary
399 * this will result in a 16 byte aligned IP header after
400 * the 14 byte MAC header is removed
401 */
402 skb_reserve(skb, NET_IP_ALIGN);
403
404 rx_buffer_info->skb = skb;
405 rx_buffer_info->dma = pci_map_single(pdev, skb->data,
406 bufsz,
407 PCI_DMA_FROMDEVICE);
408 }
409 /* Refresh the desc even if buffer_addrs didn't change because
410 * each write-back erases this info. */
411 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
412 rx_desc->read.pkt_addr =
413 cpu_to_le64(rx_buffer_info->page_dma);
414 rx_desc->read.hdr_addr =
415 cpu_to_le64(rx_buffer_info->dma);
416 } else {
417 rx_desc->read.pkt_addr =
418 cpu_to_le64(rx_buffer_info->dma);
419 }
420
421 i++;
422 if (i == rx_ring->count)
423 i = 0;
424 rx_buffer_info = &rx_ring->rx_buffer_info[i];
425 }
426no_buffers:
427 if (rx_ring->next_to_use != i) {
428 rx_ring->next_to_use = i;
429 if (i-- == 0)
430 i = (rx_ring->count - 1);
431
432 /*
433 * Force memory writes to complete before letting h/w
434 * know there are new descriptors to fetch. (Only
435 * applicable for weak-ordered memory model archs,
436 * such as IA-64).
437 */
438 wmb();
439 writel(i, adapter->hw.hw_addr + rx_ring->tail);
440 }
441}
442
443static bool ixgbe_clean_rx_irq(struct ixgbe_adapter *adapter,
444 struct ixgbe_ring *rx_ring,
445 int *work_done, int work_to_do)
446{
447 struct net_device *netdev = adapter->netdev;
448 struct pci_dev *pdev = adapter->pdev;
449 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
450 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
451 struct sk_buff *skb;
452 unsigned int i;
453 u32 upper_len, len, staterr;
454 u16 hdr_info, vlan_tag;
455 bool is_vlan, cleaned = false;
456 int cleaned_count = 0;
d2f4fbe2 457 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
9a799d71
AK		 458
459 i = rx_ring->next_to_clean;
460 upper_len = 0;
461 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
462 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
463 rx_buffer_info = &rx_ring->rx_buffer_info[i];
464 is_vlan = (staterr & IXGBE_RXD_STAT_VP);
465 vlan_tag = le16_to_cpu(rx_desc->wb.upper.vlan);
466
467 while (staterr & IXGBE_RXD_STAT_DD) {
468 if (*work_done >= work_to_do)
469 break;
470 (*work_done)++;
471
472 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
473 hdr_info =
474 le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info);
475 len =
476 ((hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
477 IXGBE_RXDADV_HDRBUFLEN_SHIFT);
478 if (hdr_info & IXGBE_RXDADV_SPH)
479 adapter->rx_hdr_split++;
480 if (len > IXGBE_RX_HDR_SIZE)
481 len = IXGBE_RX_HDR_SIZE;
482 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
483 } else
484 len = le16_to_cpu(rx_desc->wb.upper.length);
485
486 cleaned = true;
487 skb = rx_buffer_info->skb;
488 prefetch(skb->data - NET_IP_ALIGN);
489 rx_buffer_info->skb = NULL;
490
491 if (len && !skb_shinfo(skb)->nr_frags) {
492 pci_unmap_single(pdev, rx_buffer_info->dma,
493 adapter->rx_buf_len + NET_IP_ALIGN,
494 PCI_DMA_FROMDEVICE);
495 skb_put(skb, len);
496 }
497
498 if (upper_len) {
499 pci_unmap_page(pdev, rx_buffer_info->page_dma,
500 PAGE_SIZE, PCI_DMA_FROMDEVICE);
501 rx_buffer_info->page_dma = 0;
502 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
503 rx_buffer_info->page, 0, upper_len);
504 rx_buffer_info->page = NULL;
505
506 skb->len += upper_len;
507 skb->data_len += upper_len;
508 skb->truesize += upper_len;
509 }
510
511 i++;
512 if (i == rx_ring->count)
513 i = 0;
514 next_buffer = &rx_ring->rx_buffer_info[i];
515
516 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
517 prefetch(next_rxd);
518
519 cleaned_count++;
520 if (staterr & IXGBE_RXD_STAT_EOP) {
521 rx_ring->stats.packets++;
522 rx_ring->stats.bytes += skb->len;
523 } else {
524 rx_buffer_info->skb = next_buffer->skb;
525 rx_buffer_info->dma = next_buffer->dma;
526 next_buffer->skb = skb;
527 adapter->non_eop_descs++;
528 goto next_desc;
529 }
530
531 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
532 dev_kfree_skb_irq(skb);
533 goto next_desc;
534 }
535
536 ixgbe_rx_checksum(adapter, staterr, skb);
d2f4fbe2
AV		 537
538 /* probably a little skewed due to removing CRC */
539 total_rx_bytes += skb->len;
540 total_rx_packets++;
541
9a799d71
AK		 542 skb->protocol = eth_type_trans(skb, netdev);
543 ixgbe_receive_skb(adapter, skb, is_vlan, vlan_tag);
544 netdev->last_rx = jiffies;
545
546next_desc:
547 rx_desc->wb.upper.status_error = 0;
548
549 /* return some buffers to hardware, one at a time is too slow */
550 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
551 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
552 cleaned_count = 0;
553 }
554
555 /* use prefetched values */
556 rx_desc = next_rxd;
557 rx_buffer_info = next_buffer;
558
559 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
560 is_vlan = (staterr & IXGBE_RXD_STAT_VP);
561 vlan_tag = le16_to_cpu(rx_desc->wb.upper.vlan);
562 }
563
564 rx_ring->next_to_clean = i;
565 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
566
567 if (cleaned_count)
568 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
569
d2f4fbe2
AV		 570 adapter->net_stats.rx_bytes += total_rx_bytes;
571 adapter->net_stats.rx_packets += total_rx_packets;
572
f494e8fa
AV		 573 rx_ring->total_packets += total_rx_packets;
574 rx_ring->total_bytes += total_rx_bytes;
575 adapter->net_stats.rx_bytes += total_rx_bytes;
576 adapter->net_stats.rx_packets += total_rx_packets;
577
9a799d71
AK		 578 return cleaned;
579}
580
021230d4 581static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 582/**
583 * ixgbe_configure_msix - Configure MSI-X hardware
584 * @adapter: board private structure
585 *
586 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
587 * interrupts.
588 **/
589static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
590{
021230d4
AV		 591 struct ixgbe_q_vector *q_vector;
592 int i, j, q_vectors, v_idx, r_idx;
593 u32 mask;
9a799d71 594
021230d4 595 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 596
021230d4
AV		 597 /* Populate the IVAR table and set the ITR values to the
598 * corresponding register.
599 */
600 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
601 q_vector = &adapter->q_vector[v_idx];
602 /* XXX for_each_bit(...) */
603 r_idx = find_first_bit(q_vector->rxr_idx,
604 adapter->num_rx_queues);
605
606 for (i = 0; i < q_vector->rxr_count; i++) {
607 j = adapter->rx_ring[r_idx].reg_idx;
608 ixgbe_set_ivar(adapter, IXGBE_IVAR_RX_QUEUE(j), v_idx);
609 r_idx = find_next_bit(q_vector->rxr_idx,
610 adapter->num_rx_queues,
611 r_idx + 1);
612 }
613 r_idx = find_first_bit(q_vector->txr_idx,
614 adapter->num_tx_queues);
615
616 for (i = 0; i < q_vector->txr_count; i++) {
617 j = adapter->tx_ring[r_idx].reg_idx;
618 ixgbe_set_ivar(adapter, IXGBE_IVAR_TX_QUEUE(j), v_idx);
619 r_idx = find_next_bit(q_vector->txr_idx,
620 adapter->num_tx_queues,
621 r_idx + 1);
622 }
623
624 /* if this is a tx only vector use half the irq (tx) rate */
625 if (q_vector->txr_count && !q_vector->rxr_count)
626 q_vector->eitr = adapter->tx_eitr;
627 else
628 /* rx only or mixed */
629 q_vector->eitr = adapter->rx_eitr;
630
631 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx),
632 EITR_INTS_PER_SEC_TO_REG(q_vector->eitr));
9a799d71
AK		 633 }
634
021230d4
AV		 635 ixgbe_set_ivar(adapter, IXGBE_IVAR_OTHER_CAUSES_INDEX, v_idx);
636 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
637
638 /* set up to autoclear timer, lsc, and the vectors */
639 mask = IXGBE_EIMS_ENABLE_MASK;
640 mask &= ~IXGBE_EIMS_OTHER;
641 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 642}
643
f494e8fa
AV		 644enum latency_range {
645 lowest_latency = 0,
646 low_latency = 1,
647 bulk_latency = 2,
648 latency_invalid = 255
649};
650
651/**
652 * ixgbe_update_itr - update the dynamic ITR value based on statistics
653 * @adapter: pointer to adapter
654 * @eitr: eitr setting (ints per sec) to give last timeslice
655 * @itr_setting: current throttle rate in ints/second
656 * @packets: the number of packets during this measurement interval
657 * @bytes: the number of bytes during this measurement interval
658 *
659 * Stores a new ITR value based on packets and byte
660 * counts during the last interrupt. The advantage of per interrupt
661 * computation is faster updates and more accurate ITR for the current
662 * traffic pattern. Constants in this function were computed
663 * based on theoretical maximum wire speed and thresholds were set based
664 * on testing data as well as attempting to minimize response time
665 * while increasing bulk throughput.
666 * this functionality is controlled by the InterruptThrottleRate module
667 * parameter (see ixgbe_param.c)
668 **/
669static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
670 u32 eitr, u8 itr_setting,
671 int packets, int bytes)
672{
673 unsigned int retval = itr_setting;
674 u32 timepassed_us;
675 u64 bytes_perint;
676
677 if (packets == 0)
678 goto update_itr_done;
679
680
681 /* simple throttlerate management
682 * 0-20MB/s lowest (100000 ints/s)
683 * 20-100MB/s low (20000 ints/s)
684 * 100-1249MB/s bulk (8000 ints/s)
685 */
686 /* what was last interrupt timeslice? */
687 timepassed_us = 1000000/eitr;
688 bytes_perint = bytes / timepassed_us; /* bytes/usec */
689
690 switch (itr_setting) {
691 case lowest_latency:
692 if (bytes_perint > adapter->eitr_low)
693 retval = low_latency;
694 break;
695 case low_latency:
696 if (bytes_perint > adapter->eitr_high)
697 retval = bulk_latency;
698 else if (bytes_perint <= adapter->eitr_low)
699 retval = lowest_latency;
700 break;
701 case bulk_latency:
702 if (bytes_perint <= adapter->eitr_high)
703 retval = low_latency;
704 break;
705 }
706
707update_itr_done:
708 return retval;
709}
710
711static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
712{
713 struct ixgbe_adapter *adapter = q_vector->adapter;
714 struct ixgbe_hw *hw = &adapter->hw;
715 u32 new_itr;
716 u8 current_itr, ret_itr;
717 int i, r_idx, v_idx = ((void *)q_vector - (void *)(adapter->q_vector)) /
718 sizeof(struct ixgbe_q_vector);
719 struct ixgbe_ring *rx_ring, *tx_ring;
720
721 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
722 for (i = 0; i < q_vector->txr_count; i++) {
723 tx_ring = &(adapter->tx_ring[r_idx]);
724 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
725 q_vector->tx_eitr,
726 tx_ring->total_packets,
727 tx_ring->total_bytes);
728 /* if the result for this queue would decrease interrupt
729 * rate for this vector then use that result */
730 q_vector->tx_eitr = ((q_vector->tx_eitr > ret_itr) ?
731 q_vector->tx_eitr - 1 : ret_itr);
732 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
733 r_idx + 1);
734 }
735
736 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
737 for (i = 0; i < q_vector->rxr_count; i++) {
738 rx_ring = &(adapter->rx_ring[r_idx]);
739 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
740 q_vector->rx_eitr,
741 rx_ring->total_packets,
742 rx_ring->total_bytes);
743 /* if the result for this queue would decrease interrupt
744 * rate for this vector then use that result */
745 q_vector->rx_eitr = ((q_vector->rx_eitr > ret_itr) ?
746 q_vector->rx_eitr - 1 : ret_itr);
747 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
748 r_idx + 1);
749 }
750
751 current_itr = max(q_vector->rx_eitr, q_vector->tx_eitr);
752
753 switch (current_itr) {
754 /* counts and packets in update_itr are dependent on these numbers */
755 case lowest_latency:
756 new_itr = 100000;
757 break;
758 case low_latency:
759 new_itr = 20000; /* aka hwitr = ~200 */
760 break;
761 case bulk_latency:
762 default:
763 new_itr = 8000;
764 break;
765 }
766
767 if (new_itr != q_vector->eitr) {
768 u32 itr_reg;
769 /* do an exponential smoothing */
770 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
771 q_vector->eitr = new_itr;
772 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
773 /* must write high and low 16 bits to reset counter */
774 DPRINTK(TX_ERR, DEBUG, "writing eitr(%d): %08X\n", v_idx,
775 itr_reg);
776 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg | (itr_reg)<<16);
777 }
778
779 return;
780}
781
9a799d71
AK		 782static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
783{
784 struct net_device *netdev = data;
785 struct ixgbe_adapter *adapter = netdev_priv(netdev);
786 struct ixgbe_hw *hw = &adapter->hw;
787 u32 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
788
789 if (eicr & IXGBE_EICR_LSC) {
790 adapter->lsc_int++;
791 if (!test_bit(__IXGBE_DOWN, &adapter->state))
792 mod_timer(&adapter->watchdog_timer, jiffies);
793 }
d4f80882
AV		 794
795 if (!test_bit(__IXGBE_DOWN, &adapter->state))
796 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 797
798 return IRQ_HANDLED;
799}
800
801static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
802{
021230d4
AV		 803 struct ixgbe_q_vector *q_vector = data;
804 struct ixgbe_adapter *adapter = q_vector->adapter;
805 struct ixgbe_ring *txr;
806 int i, r_idx;
807
808 if (!q_vector->txr_count)
809 return IRQ_HANDLED;
810
811 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
812 for (i = 0; i < q_vector->txr_count; i++) {
813 txr = &(adapter->tx_ring[r_idx]);
f494e8fa
AV		 814 txr->total_bytes = 0;
815 txr->total_packets = 0;
021230d4
AV		 816 ixgbe_clean_tx_irq(adapter, txr);
817 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
818 r_idx + 1);
819 }
9a799d71 820
9a799d71
AK		 821 return IRQ_HANDLED;
822}
823
021230d4
AV		 824/**
825 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
826 * @irq: unused
827 * @data: pointer to our q_vector struct for this interrupt vector
828 **/
9a799d71
AK		 829static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
830{
021230d4
AV		 831 struct ixgbe_q_vector *q_vector = data;
832 struct ixgbe_adapter *adapter = q_vector->adapter;
833 struct ixgbe_ring *rxr;
834 int r_idx;
835
836 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
837 if (!q_vector->rxr_count)
838 return IRQ_HANDLED;
839
840 rxr = &(adapter->rx_ring[r_idx]);
841 /* disable interrupts on this vector only */
842 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, rxr->v_idx);
f494e8fa
AV		 843 rxr->total_bytes = 0;
844 rxr->total_packets = 0;
021230d4
AV		 845 netif_rx_schedule(adapter->netdev, &q_vector->napi);
846
847 return IRQ_HANDLED;
848}
849
850static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
851{
852 ixgbe_msix_clean_rx(irq, data);
853 ixgbe_msix_clean_tx(irq, data);
9a799d71 854
9a799d71
AK		 855 return IRQ_HANDLED;
856}
857
021230d4
AV		 858/**
859 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
860 * @napi: napi struct with our devices info in it
861 * @budget: amount of work driver is allowed to do this pass, in packets
862 *
863 **/
9a799d71
AK		 864static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
865{
021230d4
AV		 866 struct ixgbe_q_vector *q_vector =
867 container_of(napi, struct ixgbe_q_vector, napi);
868 struct ixgbe_adapter *adapter = q_vector->adapter;
869 struct ixgbe_ring *rxr;
9a799d71 870 int work_done = 0;
021230d4 871 long r_idx;
9a799d71 872
021230d4
AV		 873 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
874 rxr = &(adapter->rx_ring[r_idx]);
9a799d71
AK		 875
876 ixgbe_clean_rx_irq(adapter, rxr, &work_done, budget);
877
021230d4
AV		 878 /* If all Rx work done, exit the polling mode */
879 if (work_done < budget) {
880 netif_rx_complete(adapter->netdev, napi);
f494e8fa
AV		 881 if (adapter->rx_eitr < IXGBE_MIN_ITR_USECS)
882 ixgbe_set_itr_msix(q_vector);
9a799d71 883 if (!test_bit(__IXGBE_DOWN, &adapter->state))
021230d4 884 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, rxr->v_idx);
9a799d71
AK		 885 }
886
887 return work_done;
888}
889
021230d4
AV		 890static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
891 int r_idx)
892{
893 a->q_vector[v_idx].adapter = a;
894 set_bit(r_idx, a->q_vector[v_idx].rxr_idx);
895 a->q_vector[v_idx].rxr_count++;
896 a->rx_ring[r_idx].v_idx = 1 << v_idx;
897}
898
899static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
900 int r_idx)
901{
902 a->q_vector[v_idx].adapter = a;
903 set_bit(r_idx, a->q_vector[v_idx].txr_idx);
904 a->q_vector[v_idx].txr_count++;
905 a->tx_ring[r_idx].v_idx = 1 << v_idx;
906}
907
9a799d71 908/**
021230d4
AV		 909 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
910 * @adapter: board private structure to initialize
911 * @vectors: allotted vector count for descriptor rings
9a799d71 912 *
021230d4
AV		 913 * This function maps descriptor rings to the queue-specific vectors
914 * we were allotted through the MSI-X enabling code. Ideally, we'd have
915 * one vector per ring/queue, but on a constrained vector budget, we
916 * group the rings as "efficiently" as possible. You would add new
917 * mapping configurations in here.
9a799d71 918 **/
021230d4
AV		 919static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
920 int vectors)
921{
922 int v_start = 0;
923 int rxr_idx = 0, txr_idx = 0;
924 int rxr_remaining = adapter->num_rx_queues;
925 int txr_remaining = adapter->num_tx_queues;
926 int i, j;
927 int rqpv, tqpv;
928 int err = 0;
929
930 /* No mapping required if MSI-X is disabled. */
931 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
932 goto out;
9a799d71 933
021230d4
AV		 934 /*
935 * The ideal configuration...
936 * We have enough vectors to map one per queue.
937 */
938 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
939 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
940 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 941
021230d4
AV		 942 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
943 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 944
9a799d71 945 goto out;
021230d4 946 }
9a799d71 947
021230d4
AV		 948 /*
949 * If we don't have enough vectors for a 1-to-1
950 * mapping, we'll have to group them so there are
951 * multiple queues per vector.
952 */
953 /* Re-adjusting *qpv takes care of the remainder. */
954 for (i = v_start; i < vectors; i++) {
955 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
956 for (j = 0; j < rqpv; j++) {
957 map_vector_to_rxq(adapter, i, rxr_idx);
958 rxr_idx++;
959 rxr_remaining--;
960 }
961 }
962 for (i = v_start; i < vectors; i++) {
963 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
964 for (j = 0; j < tqpv; j++) {
965 map_vector_to_txq(adapter, i, txr_idx);
966 txr_idx++;
967 txr_remaining--;
9a799d71 968 }
9a799d71
AK		 969 }
970
021230d4
AV		 971out:
972 return err;
973}
974
975/**
976 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
977 * @adapter: board private structure
978 *
979 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
980 * interrupts from the kernel.
981 **/
982static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
983{
984 struct net_device *netdev = adapter->netdev;
985 irqreturn_t (*handler)(int, void *);
986 int i, vector, q_vectors, err;
987
988 /* Decrement for Other and TCP Timer vectors */
989 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
990
991 /* Map the Tx/Rx rings to the vectors we were allotted. */
992 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
993 if (err)
994 goto out;
995
996#define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
997 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
998 &ixgbe_msix_clean_many)
999 for (vector = 0; vector < q_vectors; vector++) {
1000 handler = SET_HANDLER(&adapter->q_vector[vector]);
1001 sprintf(adapter->name[vector], "%s:v%d-%s",
1002 netdev->name, vector,
1003 (handler == &ixgbe_msix_clean_rx) ? "Rx" :
1004 ((handler == &ixgbe_msix_clean_tx) ? "Tx" : "TxRx"));
1005 err = request_irq(adapter->msix_entries[vector].vector,
1006 handler, 0, adapter->name[vector],
1007 &(adapter->q_vector[vector]));
9a799d71
AK		 1008 if (err) {
1009 DPRINTK(PROBE, ERR,
1010 "request_irq failed for MSIX interrupt "
1011 "Error: %d\n", err);
021230d4 1012 goto free_queue_irqs;
9a799d71 1013 }
9a799d71
AK		 1014 }
1015
021230d4
AV		 1016 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1017 err = request_irq(adapter->msix_entries[vector].vector,
1018 &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
9a799d71
AK		 1019 if (err) {
1020 DPRINTK(PROBE, ERR,
1021 "request_irq for msix_lsc failed: %d\n", err);
021230d4 1022 goto free_queue_irqs;
9a799d71
AK		 1023 }
1024
9a799d71
AK		 1025 return 0;
1026
021230d4
AV		 1027free_queue_irqs:
1028 for (i = vector - 1; i >= 0; i--)
1029 free_irq(adapter->msix_entries[--vector].vector,
1030 &(adapter->q_vector[i]));
1031 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1032 pci_disable_msix(adapter->pdev);
9a799d71
AK		 1033 kfree(adapter->msix_entries);
1034 adapter->msix_entries = NULL;
021230d4 1035out:
9a799d71
AK		 1036 return err;
1037}
1038
f494e8fa
AV		 1039static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1040{
1041 struct ixgbe_hw *hw = &adapter->hw;
1042 struct ixgbe_q_vector *q_vector = adapter->q_vector;
1043 u8 current_itr;
1044 u32 new_itr = q_vector->eitr;
1045 struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1046 struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1047
1048 q_vector->tx_eitr = ixgbe_update_itr(adapter, new_itr,
1049 q_vector->tx_eitr,
1050 tx_ring->total_packets,
1051 tx_ring->total_bytes);
1052 q_vector->rx_eitr = ixgbe_update_itr(adapter, new_itr,
1053 q_vector->rx_eitr,
1054 rx_ring->total_packets,
1055 rx_ring->total_bytes);
1056
1057 current_itr = max(q_vector->rx_eitr, q_vector->tx_eitr);
1058
1059 switch (current_itr) {
1060 /* counts and packets in update_itr are dependent on these numbers */
1061 case lowest_latency:
1062 new_itr = 100000;
1063 break;
1064 case low_latency:
1065 new_itr = 20000; /* aka hwitr = ~200 */
1066 break;
1067 case bulk_latency:
1068 new_itr = 8000;
1069 break;
1070 default:
1071 break;
1072 }
1073
1074 if (new_itr != q_vector->eitr) {
1075 u32 itr_reg;
1076 /* do an exponential smoothing */
1077 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1078 q_vector->eitr = new_itr;
1079 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
1080 /* must write high and low 16 bits to reset counter */
1081 IXGBE_WRITE_REG(hw, IXGBE_EITR(0), itr_reg | (itr_reg)<<16);
1082 }
1083
1084 return;
1085}
1086
021230d4
AV		 1087static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter);
1088
9a799d71 1089/**
021230d4 1090 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 1091 * @irq: interrupt number
1092 * @data: pointer to a network interface device structure
1093 * @pt_regs: CPU registers structure
1094 **/
1095static irqreturn_t ixgbe_intr(int irq, void *data)
1096{
1097 struct net_device *netdev = data;
1098 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1099 struct ixgbe_hw *hw = &adapter->hw;
1100 u32 eicr;
1101
9a799d71 1102
021230d4
AV		 1103 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1104 * therefore no explict interrupt disable is necessary */
1105 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
9a799d71
AK		 1106 if (!eicr)
1107 return IRQ_NONE; /* Not our interrupt */
1108
1109 if (eicr & IXGBE_EICR_LSC) {
1110 adapter->lsc_int++;
1111 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1112 mod_timer(&adapter->watchdog_timer, jiffies);
1113 }
021230d4
AV		 1114
1115
1116 if (netif_rx_schedule_prep(netdev, &adapter->q_vector[0].napi)) {
f494e8fa
AV		 1117 adapter->tx_ring[0].total_packets = 0;
1118 adapter->tx_ring[0].total_bytes = 0;
1119 adapter->rx_ring[0].total_packets = 0;
1120 adapter->rx_ring[0].total_bytes = 0;
021230d4
AV		 1121 /* would disable interrupts here but EIAM disabled it */
1122 __netif_rx_schedule(netdev, &adapter->q_vector[0].napi);
9a799d71
AK		 1123 }
1124
1125 return IRQ_HANDLED;
1126}
1127
021230d4
AV		 1128static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1129{
1130 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1131
1132 for (i = 0; i < q_vectors; i++) {
1133 struct ixgbe_q_vector *q_vector = &adapter->q_vector[i];
1134 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1135 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1136 q_vector->rxr_count = 0;
1137 q_vector->txr_count = 0;
1138 }
1139}
1140
9a799d71
AK		 1141/**
1142 * ixgbe_request_irq - initialize interrupts
1143 * @adapter: board private structure
1144 *
1145 * Attempts to configure interrupts using the best available
1146 * capabilities of the hardware and kernel.
1147 **/
021230d4 1148static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 1149{
1150 struct net_device *netdev = adapter->netdev;
021230d4 1151 int err;
9a799d71 1152
021230d4
AV		 1153 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1154 err = ixgbe_request_msix_irqs(adapter);
1155 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1156 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
1157 netdev->name, netdev);
1158 } else {
1159 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
1160 netdev->name, netdev);
9a799d71
AK		 1161 }
1162
9a799d71
AK		 1163 if (err)
1164 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1165
9a799d71
AK		 1166 return err;
1167}
1168
1169static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1170{
1171 struct net_device *netdev = adapter->netdev;
1172
1173 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 1174 int i, q_vectors;
9a799d71 1175
021230d4
AV		 1176 q_vectors = adapter->num_msix_vectors;
1177
1178 i = q_vectors - 1;
9a799d71 1179 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 1180
021230d4
AV		 1181 i--;
1182 for (; i >= 0; i--) {
1183 free_irq(adapter->msix_entries[i].vector,
1184 &(adapter->q_vector[i]));
1185 }
1186
1187 ixgbe_reset_q_vectors(adapter);
1188 } else {
1189 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 1190 }
1191}
1192
1193/**
1194 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1195 * @adapter: board private structure
1196 **/
1197static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1198{
9a799d71
AK		 1199 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1200 IXGBE_WRITE_FLUSH(&adapter->hw);
021230d4
AV		 1201 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1202 int i;
1203 for (i = 0; i < adapter->num_msix_vectors; i++)
1204 synchronize_irq(adapter->msix_entries[i].vector);
1205 } else {
1206 synchronize_irq(adapter->pdev->irq);
1207 }
9a799d71
AK		 1208}
1209
1210/**
1211 * ixgbe_irq_enable - Enable default interrupt generation settings
1212 * @adapter: board private structure
1213 **/
1214static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1215{
021230d4
AV		 1216 u32 mask;
1217 mask = IXGBE_EIMS_ENABLE_MASK;
1218 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
d4f80882 1219 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 1220}
1221
1222/**
1223 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1224 *
1225 **/
1226static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1227{
9a799d71
AK		 1228 struct ixgbe_hw *hw = &adapter->hw;
1229
021230d4
AV		 1230 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
1231 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr));
9a799d71
AK		 1232
1233 ixgbe_set_ivar(adapter, IXGBE_IVAR_RX_QUEUE(0), 0);
021230d4
AV		 1234 ixgbe_set_ivar(adapter, IXGBE_IVAR_TX_QUEUE(0), 0);
1235
1236 map_vector_to_rxq(adapter, 0, 0);
1237 map_vector_to_txq(adapter, 0, 0);
1238
1239 DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 1240}
1241
1242/**
1243 * ixgbe_configure_tx - Configure 8254x Transmit Unit after Reset
1244 * @adapter: board private structure
1245 *
1246 * Configure the Tx unit of the MAC after a reset.
1247 **/
1248static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1249{
1250 u64 tdba;
1251 struct ixgbe_hw *hw = &adapter->hw;
021230d4 1252 u32 i, j, tdlen, txctrl;
9a799d71
AK		 1253
1254 /* Setup the HW Tx Head and Tail descriptor pointers */
1255 for (i = 0; i < adapter->num_tx_queues; i++) {
021230d4 1256 j = adapter->tx_ring[i].reg_idx;
9a799d71
AK		 1257 tdba = adapter->tx_ring[i].dma;
1258 tdlen = adapter->tx_ring[i].count *
021230d4
AV		 1259 sizeof(union ixgbe_adv_tx_desc);
1260 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
1261 (tdba & DMA_32BIT_MASK));
1262 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1263 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1264 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1265 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1266 adapter->tx_ring[i].head = IXGBE_TDH(j);
1267 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1268 /* Disable Tx Head Writeback RO bit, since this hoses
1269 * bookkeeping if things aren't delivered in order.
1270 */
1271 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
1272 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
1273 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), txctrl);
9a799d71 1274 }
9a799d71
AK		 1275}
1276
1277#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
1278 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
1279
1280#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
1281/**
1282 * ixgbe_configure_rx - Configure 8254x Receive Unit after Reset
1283 * @adapter: board private structure
1284 *
1285 * Configure the Rx unit of the MAC after a reset.
1286 **/
1287static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
1288{
1289 u64 rdba;
1290 struct ixgbe_hw *hw = &adapter->hw;
1291 struct net_device *netdev = adapter->netdev;
1292 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 1293 int i, j;
9a799d71
AK		 1294 u32 rdlen, rxctrl, rxcsum;
1295 u32 random[10];
9a799d71 1296 u32 fctrl, hlreg0;
9a799d71 1297 u32 pages;
021230d4 1298 u32 reta = 0, mrqc, srrctl;
9a799d71
AK		 1299
1300 /* Decide whether to use packet split mode or not */
1301 if (netdev->mtu > ETH_DATA_LEN)
1302 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
1303 else
1304 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
1305
1306 /* Set the RX buffer length according to the mode */
1307 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1308 adapter->rx_buf_len = IXGBE_RX_HDR_SIZE;
1309 } else {
1310 if (netdev->mtu <= ETH_DATA_LEN)
1311 adapter->rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1312 else
1313 adapter->rx_buf_len = ALIGN(max_frame, 1024);
1314 }
1315
1316 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1317 fctrl |= IXGBE_FCTRL_BAM;
021230d4 1318 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
9a799d71
AK		 1319 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
1320
1321 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1322 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1323 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
1324 else
1325 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
1326 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1327
1328 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
1329
1330 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(0));
1331 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1332 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1333
1334 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1335 srrctl |= PAGE_SIZE >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1336 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1337 srrctl |= ((IXGBE_RX_HDR_SIZE <<
1338 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1339 IXGBE_SRRCTL_BSIZEHDR_MASK);
1340 } else {
1341 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
1342
1343 if (adapter->rx_buf_len == MAXIMUM_ETHERNET_VLAN_SIZE)
1344 srrctl |=
1345 IXGBE_RXBUFFER_2048 >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1346 else
1347 srrctl |=
1348 adapter->rx_buf_len >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1349 }
1350 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(0), srrctl);
1351
1352 rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
1353 /* disable receives while setting up the descriptors */
1354 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1355 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
1356
1357 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1358 * the Base and Length of the Rx Descriptor Ring */
1359 for (i = 0; i < adapter->num_rx_queues; i++) {
1360 rdba = adapter->rx_ring[i].dma;
1361 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(i), (rdba & DMA_32BIT_MASK));
1362 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(i), (rdba >> 32));
1363 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(i), rdlen);
1364 IXGBE_WRITE_REG(hw, IXGBE_RDH(i), 0);
1365 IXGBE_WRITE_REG(hw, IXGBE_RDT(i), 0);
1366 adapter->rx_ring[i].head = IXGBE_RDH(i);
1367 adapter->rx_ring[i].tail = IXGBE_RDT(i);
1368 }
1369
021230d4 1370 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
9a799d71 1371 /* Fill out redirection table */
021230d4
AV		 1372 for (i = 0, j = 0; i < 128; i++, j++) {
1373 if (j == adapter->ring_feature[RING_F_RSS].indices)
1374 j = 0;
1375 /* reta = 4-byte sliding window of
1376 * 0x00..(indices-1)(indices-1)00..etc. */
1377 reta = (reta << 8) | (j * 0x11);
1378 if ((i & 3) == 3)
1379 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
9a799d71
AK		 1380 }
1381
1382 /* Fill out hash function seeds */
021230d4
AV		 1383 /* XXX use a random constant here to glue certain flows */
1384 get_random_bytes(&random[0], 40);
9a799d71 1385 for (i = 0; i < 10; i++)
021230d4 1386 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), random[i]);
9a799d71
AK		 1387
1388 mrqc = IXGBE_MRQC_RSSEN
1389 /* Perform hash on these packet types */
1390 | IXGBE_MRQC_RSS_FIELD_IPV4
1391 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
1392 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
1393 | IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP
1394 | IXGBE_MRQC_RSS_FIELD_IPV6_EX
1395 | IXGBE_MRQC_RSS_FIELD_IPV6
1396 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
1397 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP
1398 | IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
1399 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
021230d4 1400 }
9a799d71 1401
021230d4
AV		 1402 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
1403
1404 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
1405 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
1406 /* Disable indicating checksum in descriptor, enables
1407 * RSS hash */
9a799d71 1408 rxcsum |= IXGBE_RXCSUM_PCSD;
9a799d71 1409 }
021230d4
AV		 1410 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
1411 /* Enable IPv4 payload checksum for UDP fragments
1412 * if PCSD is not set */
1413 rxcsum |= IXGBE_RXCSUM_IPPCSE;
1414 }
1415
1416 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
9a799d71
AK		 1417}
1418
1419static void ixgbe_vlan_rx_register(struct net_device *netdev,
1420 struct vlan_group *grp)
1421{
1422 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1423 u32 ctrl;
1424
d4f80882
AV		 1425 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1426 ixgbe_irq_disable(adapter);
9a799d71
AK		 1427 adapter->vlgrp = grp;
1428
1429 if (grp) {
1430 /* enable VLAN tag insert/strip */
1431 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
1432 ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
1433 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
1434 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
1435 }
1436
d4f80882
AV		 1437 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1438 ixgbe_irq_enable(adapter);
9a799d71
AK		 1439}
1440
1441static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
1442{
1443 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1444
1445 /* add VID to filter table */
1446 ixgbe_set_vfta(&adapter->hw, vid, 0, true);
1447}
1448
1449static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
1450{
1451 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1452
d4f80882
AV		 1453 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1454 ixgbe_irq_disable(adapter);
1455
9a799d71 1456 vlan_group_set_device(adapter->vlgrp, vid, NULL);
d4f80882
AV		 1457
1458 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1459 ixgbe_irq_enable(adapter);
9a799d71
AK		 1460
1461 /* remove VID from filter table */
1462 ixgbe_set_vfta(&adapter->hw, vid, 0, false);
1463}
1464
1465static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
1466{
1467 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
1468
1469 if (adapter->vlgrp) {
1470 u16 vid;
1471 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
1472 if (!vlan_group_get_device(adapter->vlgrp, vid))
1473 continue;
1474 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
1475 }
1476 }
1477}
1478
1479/**
1480 * ixgbe_set_multi - Multicast and Promiscuous mode set
1481 * @netdev: network interface device structure
1482 *
1483 * The set_multi entry point is called whenever the multicast address
1484 * list or the network interface flags are updated. This routine is
1485 * responsible for configuring the hardware for proper multicast,
1486 * promiscuous mode, and all-multi behavior.
1487 **/
1488static void ixgbe_set_multi(struct net_device *netdev)
1489{
1490 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1491 struct ixgbe_hw *hw = &adapter->hw;
1492 struct dev_mc_list *mc_ptr;
1493 u8 *mta_list;
1494 u32 fctrl;
1495 int i;
1496
1497 /* Check for Promiscuous and All Multicast modes */
1498
1499 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1500
1501 if (netdev->flags & IFF_PROMISC) {
1502 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
1503 } else if (netdev->flags & IFF_ALLMULTI) {
1504 fctrl |= IXGBE_FCTRL_MPE;
1505 fctrl &= ~IXGBE_FCTRL_UPE;
1506 } else {
1507 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
1508 }
1509
1510 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1511
1512 if (netdev->mc_count) {
1513 mta_list = kcalloc(netdev->mc_count, ETH_ALEN, GFP_ATOMIC);
1514 if (!mta_list)
1515 return;
1516
1517 /* Shared function expects packed array of only addresses. */
1518 mc_ptr = netdev->mc_list;
1519
1520 for (i = 0; i < netdev->mc_count; i++) {
1521 if (!mc_ptr)
1522 break;
1523 memcpy(mta_list + (i * ETH_ALEN), mc_ptr->dmi_addr,
1524 ETH_ALEN);
1525 mc_ptr = mc_ptr->next;
1526 }
1527
1528 ixgbe_update_mc_addr_list(hw, mta_list, i, 0);
1529 kfree(mta_list);
1530 } else {
1531 ixgbe_update_mc_addr_list(hw, NULL, 0, 0);
1532 }
1533
1534}
1535
021230d4
AV		 1536static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
1537{
1538 int q_idx;
1539 struct ixgbe_q_vector *q_vector;
1540 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1541
1542 /* legacy and MSI only use one vector */
1543 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1544 q_vectors = 1;
1545
1546 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
1547 q_vector = &adapter->q_vector[q_idx];
1548 if (!q_vector->rxr_count)
1549 continue;
1550 napi_enable(&q_vector->napi);
1551 }
1552}
1553
1554static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
1555{
1556 int q_idx;
1557 struct ixgbe_q_vector *q_vector;
1558 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1559
1560 /* legacy and MSI only use one vector */
1561 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1562 q_vectors = 1;
1563
1564 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
1565 q_vector = &adapter->q_vector[q_idx];
1566 if (!q_vector->rxr_count)
1567 continue;
1568 napi_disable(&q_vector->napi);
1569 }
1570}
1571
9a799d71
AK		 1572static void ixgbe_configure(struct ixgbe_adapter *adapter)
1573{
1574 struct net_device *netdev = adapter->netdev;
1575 int i;
1576
1577 ixgbe_set_multi(netdev);
1578
1579 ixgbe_restore_vlan(adapter);
1580
1581 ixgbe_configure_tx(adapter);
1582 ixgbe_configure_rx(adapter);
1583 for (i = 0; i < adapter->num_rx_queues; i++)
1584 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
1585 (adapter->rx_ring[i].count - 1));
1586}
1587
1588static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
1589{
1590 struct net_device *netdev = adapter->netdev;
9a799d71 1591 struct ixgbe_hw *hw = &adapter->hw;
021230d4 1592 int i, j = 0;
9a799d71 1593 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4
AV		 1594 u32 txdctl, rxdctl, mhadd;
1595 u32 gpie;
9a799d71 1596
5eba3699
AV		 1597 ixgbe_get_hw_control(adapter);
1598
021230d4
AV		 1599 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
1600 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
9a799d71
AK		 1601 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1602 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
1603 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
1604 } else {
1605 /* MSI only */
021230d4 1606 gpie = 0;
9a799d71 1607 }
021230d4
AV		 1608 /* XXX: to interrupt immediately for EICS writes, enable this */
1609 /* gpie |= IXGBE_GPIE_EIMEN; */
1610 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
9a799d71
AK		 1611 }
1612
021230d4
AV		 1613 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
1614 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
1615 * specifically only auto mask tx and rx interrupts */
1616 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
1617 }
9a799d71 1618
021230d4 1619 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
9a799d71
AK		 1620 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
1621 mhadd &= ~IXGBE_MHADD_MFS_MASK;
1622 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
1623
1624 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
1625 }
1626
1627 for (i = 0; i < adapter->num_tx_queues; i++) {
021230d4
AV		 1628 j = adapter->tx_ring[i].reg_idx;
1629 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
9a799d71 1630 txdctl |= IXGBE_TXDCTL_ENABLE;
021230d4 1631 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
9a799d71
AK		 1632 }
1633
1634 for (i = 0; i < adapter->num_rx_queues; i++) {
021230d4
AV		 1635 j = adapter->rx_ring[i].reg_idx;
1636 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
1637 /* enable PTHRESH=32 descriptors (half the internal cache)
1638 * and HTHRESH=0 descriptors (to minimize latency on fetch),
1639 * this also removes a pesky rx_no_buffer_count increment */
1640 rxdctl |= 0x0020;
9a799d71 1641 rxdctl |= IXGBE_RXDCTL_ENABLE;
021230d4 1642 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
9a799d71
AK		 1643 }
1644 /* enable all receives */
1645 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1646 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
1647 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxdctl);
1648
1649 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
1650 ixgbe_configure_msix(adapter);
1651 else
1652 ixgbe_configure_msi_and_legacy(adapter);
1653
1654 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 1655 ixgbe_napi_enable_all(adapter);
1656
1657 /* clear any pending interrupts, may auto mask */
1658 IXGBE_READ_REG(hw, IXGBE_EICR);
1659
9a799d71
AK		 1660 ixgbe_irq_enable(adapter);
1661
1662 /* bring the link up in the watchdog, this could race with our first
1663 * link up interrupt but shouldn't be a problem */
1664 mod_timer(&adapter->watchdog_timer, jiffies);
1665 return 0;
1666}
1667
d4f80882
AV		 1668void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
1669{
1670 WARN_ON(in_interrupt());
1671 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
1672 msleep(1);
1673 ixgbe_down(adapter);
1674 ixgbe_up(adapter);
1675 clear_bit(__IXGBE_RESETTING, &adapter->state);
1676}
1677
9a799d71
AK		 1678int ixgbe_up(struct ixgbe_adapter *adapter)
1679{
1680 /* hardware has been reset, we need to reload some things */
1681 ixgbe_configure(adapter);
1682
1683 return ixgbe_up_complete(adapter);
1684}
1685
1686void ixgbe_reset(struct ixgbe_adapter *adapter)
1687{
1688 if (ixgbe_init_hw(&adapter->hw))
1689 DPRINTK(PROBE, ERR, "Hardware Error\n");
1690
1691 /* reprogram the RAR[0] in case user changed it. */
1692 ixgbe_set_rar(&adapter->hw, 0, adapter->hw.mac.addr, 0, IXGBE_RAH_AV);
1693
1694}
1695
1696#ifdef CONFIG_PM
1697static int ixgbe_resume(struct pci_dev *pdev)
1698{
1699 struct net_device *netdev = pci_get_drvdata(pdev);
1700 struct ixgbe_adapter *adapter = netdev_priv(netdev);
021230d4 1701 u32 err;
9a799d71
AK		 1702
1703 pci_set_power_state(pdev, PCI_D0);
1704 pci_restore_state(pdev);
1705 err = pci_enable_device(pdev);
1706 if (err) {
1707 printk(KERN_ERR "ixgbe: Cannot enable PCI device from " \
1708 "suspend\n");
1709 return err;
1710 }
1711 pci_set_master(pdev);
1712
1713 pci_enable_wake(pdev, PCI_D3hot, 0);
1714 pci_enable_wake(pdev, PCI_D3cold, 0);
1715
1716 if (netif_running(netdev)) {
021230d4 1717 err = ixgbe_request_irq(adapter);
9a799d71
AK		 1718 if (err)
1719 return err;
1720 }
1721
1722 ixgbe_reset(adapter);
1723
1724 if (netif_running(netdev))
1725 ixgbe_up(adapter);
1726
1727 netif_device_attach(netdev);
1728
1729 return 0;
1730}
1731#endif
1732
1733/**
1734 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
1735 * @adapter: board private structure
1736 * @rx_ring: ring to free buffers from
1737 **/
1738static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
1739 struct ixgbe_ring *rx_ring)
1740{
1741 struct pci_dev *pdev = adapter->pdev;
1742 unsigned long size;
1743 unsigned int i;
1744
1745 /* Free all the Rx ring sk_buffs */
1746
1747 for (i = 0; i < rx_ring->count; i++) {
1748 struct ixgbe_rx_buffer *rx_buffer_info;
1749
1750 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1751 if (rx_buffer_info->dma) {
1752 pci_unmap_single(pdev, rx_buffer_info->dma,
1753 adapter->rx_buf_len,
1754 PCI_DMA_FROMDEVICE);
1755 rx_buffer_info->dma = 0;
1756 }
1757 if (rx_buffer_info->skb) {
1758 dev_kfree_skb(rx_buffer_info->skb);
1759 rx_buffer_info->skb = NULL;
1760 }
1761 if (!rx_buffer_info->page)
1762 continue;
1763 pci_unmap_page(pdev, rx_buffer_info->page_dma, PAGE_SIZE,
1764 PCI_DMA_FROMDEVICE);
1765 rx_buffer_info->page_dma = 0;
1766
1767 put_page(rx_buffer_info->page);
1768 rx_buffer_info->page = NULL;
1769 }
1770
1771 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
1772 memset(rx_ring->rx_buffer_info, 0, size);
1773
1774 /* Zero out the descriptor ring */
1775 memset(rx_ring->desc, 0, rx_ring->size);
1776
1777 rx_ring->next_to_clean = 0;
1778 rx_ring->next_to_use = 0;
1779
1780 writel(0, adapter->hw.hw_addr + rx_ring->head);
1781 writel(0, adapter->hw.hw_addr + rx_ring->tail);
1782}
1783
1784/**
1785 * ixgbe_clean_tx_ring - Free Tx Buffers
1786 * @adapter: board private structure
1787 * @tx_ring: ring to be cleaned
1788 **/
1789static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
1790 struct ixgbe_ring *tx_ring)
1791{
1792 struct ixgbe_tx_buffer *tx_buffer_info;
1793 unsigned long size;
1794 unsigned int i;
1795
1796 /* Free all the Tx ring sk_buffs */
1797
1798 for (i = 0; i < tx_ring->count; i++) {
1799 tx_buffer_info = &tx_ring->tx_buffer_info[i];
1800 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
1801 }
1802
1803 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
1804 memset(tx_ring->tx_buffer_info, 0, size);
1805
1806 /* Zero out the descriptor ring */
1807 memset(tx_ring->desc, 0, tx_ring->size);
1808
1809 tx_ring->next_to_use = 0;
1810 tx_ring->next_to_clean = 0;
1811
1812 writel(0, adapter->hw.hw_addr + tx_ring->head);
1813 writel(0, adapter->hw.hw_addr + tx_ring->tail);
1814}
1815
1816/**
021230d4 1817 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 1818 * @adapter: board private structure
1819 **/
021230d4 1820static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 1821{
1822 int i;
1823
021230d4
AV		 1824 for (i = 0; i < adapter->num_rx_queues; i++)
1825 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
9a799d71
AK		 1826}
1827
1828/**
021230d4 1829 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 1830 * @adapter: board private structure
1831 **/
021230d4 1832static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 1833{
1834 int i;
1835
021230d4
AV		 1836 for (i = 0; i < adapter->num_tx_queues; i++)
1837 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
9a799d71
AK		 1838}
1839
1840void ixgbe_down(struct ixgbe_adapter *adapter)
1841{
1842 struct net_device *netdev = adapter->netdev;
1843 u32 rxctrl;
1844
1845 /* signal that we are down to the interrupt handler */
1846 set_bit(__IXGBE_DOWN, &adapter->state);
1847
1848 /* disable receives */
1849 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL);
1850 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL,
1851 rxctrl & ~IXGBE_RXCTRL_RXEN);
1852
1853 netif_tx_disable(netdev);
1854
1855 /* disable transmits in the hardware */
1856
1857 /* flush both disables */
1858 IXGBE_WRITE_FLUSH(&adapter->hw);
1859 msleep(10);
1860
1861 ixgbe_irq_disable(adapter);
1862
021230d4 1863 ixgbe_napi_disable_all(adapter);
9a799d71
AK		 1864 del_timer_sync(&adapter->watchdog_timer);
1865
1866 netif_carrier_off(netdev);
1867 netif_stop_queue(netdev);
1868
1869 ixgbe_reset(adapter);
1870 ixgbe_clean_all_tx_rings(adapter);
1871 ixgbe_clean_all_rx_rings(adapter);
1872
1873}
1874
1875static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
1876{
1877 struct net_device *netdev = pci_get_drvdata(pdev);
1878 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1879#ifdef CONFIG_PM
1880 int retval = 0;
1881#endif
1882
1883 netif_device_detach(netdev);
1884
1885 if (netif_running(netdev)) {
1886 ixgbe_down(adapter);
1887 ixgbe_free_irq(adapter);
1888 }
1889
1890#ifdef CONFIG_PM
1891 retval = pci_save_state(pdev);
1892 if (retval)
1893 return retval;
1894#endif
1895
1896 pci_enable_wake(pdev, PCI_D3hot, 0);
1897 pci_enable_wake(pdev, PCI_D3cold, 0);
1898
5eba3699
AV		 1899 ixgbe_release_hw_control(adapter);
1900
9a799d71
AK		 1901 pci_disable_device(pdev);
1902
1903 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1904
1905 return 0;
1906}
1907
1908static void ixgbe_shutdown(struct pci_dev *pdev)
1909{
1910 ixgbe_suspend(pdev, PMSG_SUSPEND);
1911}
1912
1913/**
021230d4
AV		 1914 * ixgbe_poll - NAPI Rx polling callback
1915 * @napi: structure for representing this polling device
1916 * @budget: how many packets driver is allowed to clean
1917 *
1918 * This function is used for legacy and MSI, NAPI mode
9a799d71 1919 **/
021230d4 1920static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 1921{
021230d4
AV		 1922 struct ixgbe_q_vector *q_vector = container_of(napi,
1923 struct ixgbe_q_vector, napi);
1924 struct ixgbe_adapter *adapter = q_vector->adapter;
d2c7ddd6 1925 int tx_cleaned = 0, work_done = 0;
9a799d71 1926
d2c7ddd6 1927 tx_cleaned = ixgbe_clean_tx_irq(adapter, adapter->tx_ring);
021230d4 1928 ixgbe_clean_rx_irq(adapter, adapter->rx_ring, &work_done, budget);
9a799d71 1929
d2c7ddd6
DM		 1930 if (tx_cleaned)
1931 work_done = budget;
1932
53e52c72
DM		 1933 /* If budget not fully consumed, exit the polling mode */
1934 if (work_done < budget) {
021230d4 1935 netif_rx_complete(adapter->netdev, napi);
f494e8fa
AV		 1936 if (adapter->rx_eitr < IXGBE_MIN_ITR_USECS)
1937 ixgbe_set_itr(adapter);
d4f80882
AV		 1938 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1939 ixgbe_irq_enable(adapter);
9a799d71
AK		 1940 }
1941
1942 return work_done;
1943}
1944
1945/**
1946 * ixgbe_tx_timeout - Respond to a Tx Hang
1947 * @netdev: network interface device structure
1948 **/
1949static void ixgbe_tx_timeout(struct net_device *netdev)
1950{
1951 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1952
1953 /* Do the reset outside of interrupt context */
1954 schedule_work(&adapter->reset_task);
1955}
1956
1957static void ixgbe_reset_task(struct work_struct *work)
1958{
1959 struct ixgbe_adapter *adapter;
1960 adapter = container_of(work, struct ixgbe_adapter, reset_task);
1961
1962 adapter->tx_timeout_count++;
1963
d4f80882 1964 ixgbe_reinit_locked(adapter);
9a799d71
AK		 1965}
1966
021230d4
AV		 1967static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
1968 int vectors)
1969{
1970 int err, vector_threshold;
1971
1972 /* We'll want at least 3 (vector_threshold):
1973 * 1) TxQ[0] Cleanup
1974 * 2) RxQ[0] Cleanup
1975 * 3) Other (Link Status Change, etc.)
1976 * 4) TCP Timer (optional)
1977 */
1978 vector_threshold = MIN_MSIX_COUNT;
1979
1980 /* The more we get, the more we will assign to Tx/Rx Cleanup
1981 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
1982 * Right now, we simply care about how many we'll get; we'll
1983 * set them up later while requesting irq's.
1984 */
1985 while (vectors >= vector_threshold) {
1986 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
1987 vectors);
1988 if (!err) /* Success in acquiring all requested vectors. */
1989 break;
1990 else if (err < 0)
1991 vectors = 0; /* Nasty failure, quit now */
1992 else /* err == number of vectors we should try again with */
1993 vectors = err;
1994 }
1995
1996 if (vectors < vector_threshold) {
1997 /* Can't allocate enough MSI-X interrupts? Oh well.
1998 * This just means we'll go with either a single MSI
1999 * vector or fall back to legacy interrupts.
2000 */
2001 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
2002 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2003 kfree(adapter->msix_entries);
2004 adapter->msix_entries = NULL;
2005 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
2006 adapter->num_tx_queues = 1;
2007 adapter->num_rx_queues = 1;
2008 } else {
2009 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
2010 adapter->num_msix_vectors = vectors;
2011 }
2012}
2013
2014static void __devinit ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
2015{
2016 int nrq, ntq;
2017 int feature_mask = 0, rss_i, rss_m;
2018
2019 /* Number of supported queues */
2020 switch (adapter->hw.mac.type) {
2021 case ixgbe_mac_82598EB:
2022 rss_i = adapter->ring_feature[RING_F_RSS].indices;
2023 rss_m = 0;
2024 feature_mask |= IXGBE_FLAG_RSS_ENABLED;
2025
2026 switch (adapter->flags & feature_mask) {
2027 case (IXGBE_FLAG_RSS_ENABLED):
2028 rss_m = 0xF;
2029 nrq = rss_i;
30eba97a
AV		 2030#ifdef CONFIG_NETDEVICES_MULTIQUEUE
2031 ntq = rss_i;
2032#else
021230d4 2033 ntq = 1;
30eba97a 2034#endif
021230d4
AV		 2035 break;
2036 case 0:
2037 default:
2038 rss_i = 0;
2039 rss_m = 0;
2040 nrq = 1;
2041 ntq = 1;
2042 break;
2043 }
2044
2045 adapter->ring_feature[RING_F_RSS].indices = rss_i;
2046 adapter->ring_feature[RING_F_RSS].mask = rss_m;
2047 break;
2048 default:
2049 nrq = 1;
2050 ntq = 1;
2051 break;
2052 }
2053
2054 adapter->num_rx_queues = nrq;
2055 adapter->num_tx_queues = ntq;
2056}
2057
2058/**
2059 * ixgbe_cache_ring_register - Descriptor ring to register mapping
2060 * @adapter: board private structure to initialize
2061 *
2062 * Once we know the feature-set enabled for the device, we'll cache
2063 * the register offset the descriptor ring is assigned to.
2064 **/
2065static void __devinit ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
2066{
2067 /* TODO: Remove all uses of the indices in the cases where multiple
2068 * features are OR'd together, if the feature set makes sense.
2069 */
2070 int feature_mask = 0, rss_i;
2071 int i, txr_idx, rxr_idx;
2072
2073 /* Number of supported queues */
2074 switch (adapter->hw.mac.type) {
2075 case ixgbe_mac_82598EB:
2076 rss_i = adapter->ring_feature[RING_F_RSS].indices;
2077 txr_idx = 0;
2078 rxr_idx = 0;
2079 feature_mask |= IXGBE_FLAG_RSS_ENABLED;
2080 switch (adapter->flags & feature_mask) {
2081 case (IXGBE_FLAG_RSS_ENABLED):
2082 for (i = 0; i < adapter->num_rx_queues; i++)
2083 adapter->rx_ring[i].reg_idx = i;
2084 for (i = 0; i < adapter->num_tx_queues; i++)
2085 adapter->tx_ring[i].reg_idx = i;
2086 break;
2087 case 0:
2088 default:
2089 break;
2090 }
2091 break;
2092 default:
2093 break;
2094 }
2095}
2096
9a799d71
AK		 2097/**
2098 * ixgbe_alloc_queues - Allocate memory for all rings
2099 * @adapter: board private structure to initialize
2100 *
2101 * We allocate one ring per queue at run-time since we don't know the
2102 * number of queues at compile-time. The polling_netdev array is
2103 * intended for Multiqueue, but should work fine with a single queue.
2104 **/
2105static int __devinit ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
2106{
2107 int i;
2108
2109 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
2110 sizeof(struct ixgbe_ring), GFP_KERNEL);
2111 if (!adapter->tx_ring)
021230d4 2112 goto err_tx_ring_allocation;
9a799d71
AK		 2113
2114 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
2115 sizeof(struct ixgbe_ring), GFP_KERNEL);
021230d4
AV		 2116 if (!adapter->rx_ring)
2117 goto err_rx_ring_allocation;
9a799d71 2118
021230d4
AV		 2119 for (i = 0; i < adapter->num_tx_queues; i++) {
2120 adapter->tx_ring[i].count = IXGBE_DEFAULT_TXD;
2121 adapter->tx_ring[i].queue_index = i;
2122 }
9a799d71 2123 for (i = 0; i < adapter->num_rx_queues; i++) {
9a799d71 2124 adapter->rx_ring[i].count = IXGBE_DEFAULT_RXD;
021230d4
AV		 2125 adapter->rx_ring[i].queue_index = i;
2126 }
2127
2128 ixgbe_cache_ring_register(adapter);
2129
2130 return 0;
2131
2132err_rx_ring_allocation:
2133 kfree(adapter->tx_ring);
2134err_tx_ring_allocation:
2135 return -ENOMEM;
2136}
2137
2138/**
2139 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
2140 * @adapter: board private structure to initialize
2141 *
2142 * Attempt to configure the interrupts using the best available
2143 * capabilities of the hardware and the kernel.
2144 **/
2145static int __devinit ixgbe_set_interrupt_capability(struct ixgbe_adapter
2146 *adapter)
2147{
2148 int err = 0;
2149 int vector, v_budget;
2150
2151 /*
2152 * It's easy to be greedy for MSI-X vectors, but it really
2153 * doesn't do us much good if we have a lot more vectors
2154 * than CPU's. So let's be conservative and only ask for
2155 * (roughly) twice the number of vectors as there are CPU's.
2156 */
2157 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
2158 (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
2159
2160 /*
2161 * At the same time, hardware can only support a maximum of
2162 * MAX_MSIX_COUNT vectors. With features such as RSS and VMDq,
2163 * we can easily reach upwards of 64 Rx descriptor queues and
2164 * 32 Tx queues. Thus, we cap it off in those rare cases where
2165 * the cpu count also exceeds our vector limit.
2166 */
2167 v_budget = min(v_budget, MAX_MSIX_COUNT);
2168
2169 /* A failure in MSI-X entry allocation isn't fatal, but it does
2170 * mean we disable MSI-X capabilities of the adapter. */
2171 adapter->msix_entries = kcalloc(v_budget,
2172 sizeof(struct msix_entry), GFP_KERNEL);
2173 if (!adapter->msix_entries) {
2174 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
2175 ixgbe_set_num_queues(adapter);
2176 kfree(adapter->tx_ring);
2177 kfree(adapter->rx_ring);
2178 err = ixgbe_alloc_queues(adapter);
2179 if (err) {
2180 DPRINTK(PROBE, ERR, "Unable to allocate memory "
2181 "for queues\n");
2182 goto out;
2183 }
2184
2185 goto try_msi;
2186 }
2187
2188 for (vector = 0; vector < v_budget; vector++)
2189 adapter->msix_entries[vector].entry = vector;
2190
2191 ixgbe_acquire_msix_vectors(adapter, v_budget);
2192
2193 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2194 goto out;
2195
2196try_msi:
2197 err = pci_enable_msi(adapter->pdev);
2198 if (!err) {
2199 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
2200 } else {
2201 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
2202 "falling back to legacy. Error: %d\n", err);
2203 /* reset err */
2204 err = 0;
2205 }
2206
2207out:
30eba97a
AV		 2208#ifdef CONFIG_NETDEVICES_MULTIQUEUE
2209 /* Notify the stack of the (possibly) reduced Tx Queue count. */
2210 adapter->netdev->egress_subqueue_count = adapter->num_tx_queues;
2211#endif
021230d4
AV		 2212
2213 return err;
2214}
2215
2216static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
2217{
2218 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2219 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2220 pci_disable_msix(adapter->pdev);
2221 kfree(adapter->msix_entries);
2222 adapter->msix_entries = NULL;
2223 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2224 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
2225 pci_disable_msi(adapter->pdev);
2226 }
2227 return;
2228}
2229
2230/**
2231 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
2232 * @adapter: board private structure to initialize
2233 *
2234 * We determine which interrupt scheme to use based on...
2235 * - Kernel support (MSI, MSI-X)
2236 * - which can be user-defined (via MODULE_PARAM)
2237 * - Hardware queue count (num_*_queues)
2238 * - defined by miscellaneous hardware support/features (RSS, etc.)
2239 **/
2240static int __devinit ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
2241{
2242 int err;
2243
2244 /* Number of supported queues */
2245 ixgbe_set_num_queues(adapter);
2246
2247 err = ixgbe_alloc_queues(adapter);
2248 if (err) {
2249 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
2250 goto err_alloc_queues;
2251 }
2252
2253 err = ixgbe_set_interrupt_capability(adapter);
2254 if (err) {
2255 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
2256 goto err_set_interrupt;
9a799d71
AK		 2257 }
2258
021230d4
AV		 2259 DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
2260 "Tx Queue count = %u\n",
2261 (adapter->num_rx_queues > 1) ? "Enabled" :
2262 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
2263
2264 set_bit(__IXGBE_DOWN, &adapter->state);
2265
9a799d71 2266 return 0;
021230d4
AV		 2267
2268err_set_interrupt:
2269 kfree(adapter->tx_ring);
2270 kfree(adapter->rx_ring);
2271err_alloc_queues:
2272 return err;
9a799d71
AK		 2273}
2274
2275/**
2276 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
2277 * @adapter: board private structure to initialize
2278 *
2279 * ixgbe_sw_init initializes the Adapter private data structure.
2280 * Fields are initialized based on PCI device information and
2281 * OS network device settings (MTU size).
2282 **/
2283static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
2284{
2285 struct ixgbe_hw *hw = &adapter->hw;
2286 struct pci_dev *pdev = adapter->pdev;
021230d4
AV		 2287 unsigned int rss;
2288
2289 /* Set capability flags */
2290 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
2291 adapter->ring_feature[RING_F_RSS].indices = rss;
2292 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
9a799d71 2293
f494e8fa
AV		 2294 /* Enable Dynamic interrupt throttling by default */
2295 adapter->rx_eitr = 1;
2296 adapter->tx_eitr = 1;
2297
9a799d71
AK		 2298 /* default flow control settings */
2299 hw->fc.original_type = ixgbe_fc_full;
2300 hw->fc.type = ixgbe_fc_full;
2301
021230d4 2302 /* select 10G link by default */
9a799d71
AK		 2303 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_10G_LINK_NO_AN;
2304 if (hw->mac.ops.reset(hw)) {
2305 dev_err(&pdev->dev, "HW Init failed\n");
2306 return -EIO;
2307 }
3957d63d
AK		 2308 if (hw->mac.ops.setup_link_speed(hw, IXGBE_LINK_SPEED_10GB_FULL, true,
2309 false)) {
9a799d71
AK		 2310 dev_err(&pdev->dev, "Link Speed setup failed\n");
2311 return -EIO;
2312 }
2313
2314 /* initialize eeprom parameters */
2315 if (ixgbe_init_eeprom(hw)) {
2316 dev_err(&pdev->dev, "EEPROM initialization failed\n");
2317 return -EIO;
2318 }
2319
021230d4 2320 /* enable rx csum by default */
9a799d71
AK		 2321 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
2322
9a799d71
AK		 2323 set_bit(__IXGBE_DOWN, &adapter->state);
2324
2325 return 0;
2326}
2327
2328/**
2329 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
2330 * @adapter: board private structure
2331 * @txdr: tx descriptor ring (for a specific queue) to setup
2332 *
2333 * Return 0 on success, negative on failure
2334 **/
2335int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
2336 struct ixgbe_ring *txdr)
2337{
2338 struct pci_dev *pdev = adapter->pdev;
2339 int size;
2340
2341 size = sizeof(struct ixgbe_tx_buffer) * txdr->count;
2342 txdr->tx_buffer_info = vmalloc(size);
2343 if (!txdr->tx_buffer_info) {
2344 DPRINTK(PROBE, ERR,
2345 "Unable to allocate memory for the transmit descriptor ring\n");
2346 return -ENOMEM;
2347 }
2348 memset(txdr->tx_buffer_info, 0, size);
2349
2350 /* round up to nearest 4K */
2351 txdr->size = txdr->count * sizeof(union ixgbe_adv_tx_desc);
2352 txdr->size = ALIGN(txdr->size, 4096);
2353
2354 txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma);
2355 if (!txdr->desc) {
2356 vfree(txdr->tx_buffer_info);
2357 DPRINTK(PROBE, ERR,
2358 "Memory allocation failed for the tx desc ring\n");
2359 return -ENOMEM;
2360 }
2361
9a799d71
AK		 2362 txdr->next_to_use = 0;
2363 txdr->next_to_clean = 0;
2364 txdr->work_limit = txdr->count;
9a799d71
AK		 2365
2366 return 0;
2367}
2368
2369/**
2370 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
2371 * @adapter: board private structure
2372 * @rxdr: rx descriptor ring (for a specific queue) to setup
2373 *
2374 * Returns 0 on success, negative on failure
2375 **/
2376int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
2377 struct ixgbe_ring *rxdr)
2378{
2379 struct pci_dev *pdev = adapter->pdev;
021230d4 2380 int size;
9a799d71
AK		 2381
2382 size = sizeof(struct ixgbe_rx_buffer) * rxdr->count;
2383 rxdr->rx_buffer_info = vmalloc(size);
2384 if (!rxdr->rx_buffer_info) {
2385 DPRINTK(PROBE, ERR,
2386 "vmalloc allocation failed for the rx desc ring\n");
2387 return -ENOMEM;
2388 }
2389 memset(rxdr->rx_buffer_info, 0, size);
2390
9a799d71 2391 /* Round up to nearest 4K */
021230d4 2392 rxdr->size = rxdr->count * sizeof(union ixgbe_adv_rx_desc);
9a799d71
AK		 2393 rxdr->size = ALIGN(rxdr->size, 4096);
2394
2395 rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma);
2396
2397 if (!rxdr->desc) {
2398 DPRINTK(PROBE, ERR,
2399 "Memory allocation failed for the rx desc ring\n");
2400 vfree(rxdr->rx_buffer_info);
2401 return -ENOMEM;
2402 }
2403
2404 rxdr->next_to_clean = 0;
2405 rxdr->next_to_use = 0;
9a799d71
AK		 2406
2407 return 0;
2408}
2409
2410/**
2411 * ixgbe_free_tx_resources - Free Tx Resources per Queue
2412 * @adapter: board private structure
2413 * @tx_ring: Tx descriptor ring for a specific queue
2414 *
2415 * Free all transmit software resources
2416 **/
2417static void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
2418 struct ixgbe_ring *tx_ring)
2419{
2420 struct pci_dev *pdev = adapter->pdev;
2421
2422 ixgbe_clean_tx_ring(adapter, tx_ring);
2423
2424 vfree(tx_ring->tx_buffer_info);
2425 tx_ring->tx_buffer_info = NULL;
2426
2427 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
2428
2429 tx_ring->desc = NULL;
2430}
2431
2432/**
2433 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
2434 * @adapter: board private structure
2435 *
2436 * Free all transmit software resources
2437 **/
2438static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
2439{
2440 int i;
2441
2442 for (i = 0; i < adapter->num_tx_queues; i++)
2443 ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
2444}
2445
2446/**
2447 * ixgbe_free_rx_resources - Free Rx Resources
2448 * @adapter: board private structure
2449 * @rx_ring: ring to clean the resources from
2450 *
2451 * Free all receive software resources
2452 **/
2453static void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
2454 struct ixgbe_ring *rx_ring)
2455{
2456 struct pci_dev *pdev = adapter->pdev;
2457
2458 ixgbe_clean_rx_ring(adapter, rx_ring);
2459
2460 vfree(rx_ring->rx_buffer_info);
2461 rx_ring->rx_buffer_info = NULL;
2462
2463 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2464
2465 rx_ring->desc = NULL;
2466}
2467
2468/**
2469 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
2470 * @adapter: board private structure
2471 *
2472 * Free all receive software resources
2473 **/
2474static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
2475{
2476 int i;
2477
2478 for (i = 0; i < adapter->num_rx_queues; i++)
2479 ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
2480}
2481
2482/**
021230d4 2483 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
9a799d71
AK		 2484 * @adapter: board private structure
2485 *
2486 * If this function returns with an error, then it's possible one or
2487 * more of the rings is populated (while the rest are not). It is the
2488 * callers duty to clean those orphaned rings.
2489 *
2490 * Return 0 on success, negative on failure
2491 **/
2492static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
2493{
2494 int i, err = 0;
2495
2496 for (i = 0; i < adapter->num_tx_queues; i++) {
2497 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
2498 if (err) {
2499 DPRINTK(PROBE, ERR,
2500 "Allocation for Tx Queue %u failed\n", i);
2501 break;
2502 }
2503 }
2504
2505 return err;
2506}
2507
2508/**
021230d4 2509 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
9a799d71
AK		 2510 * @adapter: board private structure
2511 *
2512 * If this function returns with an error, then it's possible one or
2513 * more of the rings is populated (while the rest are not). It is the
2514 * callers duty to clean those orphaned rings.
2515 *
2516 * Return 0 on success, negative on failure
2517 **/
2518
2519static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
2520{
2521 int i, err = 0;
2522
2523 for (i = 0; i < adapter->num_rx_queues; i++) {
2524 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
2525 if (err) {
2526 DPRINTK(PROBE, ERR,
2527 "Allocation for Rx Queue %u failed\n", i);
2528 break;
2529 }
2530 }
2531
2532 return err;
2533}
2534
2535/**
2536 * ixgbe_change_mtu - Change the Maximum Transfer Unit
2537 * @netdev: network interface device structure
2538 * @new_mtu: new value for maximum frame size
2539 *
2540 * Returns 0 on success, negative on failure
2541 **/
2542static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
2543{
2544 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2545 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
2546
2547 if ((max_frame < (ETH_ZLEN + ETH_FCS_LEN)) ||
2548 (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
2549 return -EINVAL;
2550
021230d4
AV		 2551 DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
2552 netdev->mtu, new_mtu);
2553 /* must set new MTU before calling down or up */
9a799d71
AK		 2554 netdev->mtu = new_mtu;
2555
d4f80882
AV		 2556 if (netif_running(netdev))
2557 ixgbe_reinit_locked(adapter);
9a799d71
AK		 2558
2559 return 0;
2560}
2561
2562/**
2563 * ixgbe_open - Called when a network interface is made active
2564 * @netdev: network interface device structure
2565 *
2566 * Returns 0 on success, negative value on failure
2567 *
2568 * The open entry point is called when a network interface is made
2569 * active by the system (IFF_UP). At this point all resources needed
2570 * for transmit and receive operations are allocated, the interrupt
2571 * handler is registered with the OS, the watchdog timer is started,
2572 * and the stack is notified that the interface is ready.
2573 **/
2574static int ixgbe_open(struct net_device *netdev)
2575{
2576 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2577 int err;
4bebfaa5
AK		 2578
2579 /* disallow open during test */
2580 if (test_bit(__IXGBE_TESTING, &adapter->state))
2581 return -EBUSY;
9a799d71 2582
9a799d71
AK		 2583 /* allocate transmit descriptors */
2584 err = ixgbe_setup_all_tx_resources(adapter);
2585 if (err)
2586 goto err_setup_tx;
2587
9a799d71
AK		 2588 /* allocate receive descriptors */
2589 err = ixgbe_setup_all_rx_resources(adapter);
2590 if (err)
2591 goto err_setup_rx;
2592
2593 ixgbe_configure(adapter);
2594
021230d4 2595 err = ixgbe_request_irq(adapter);
9a799d71
AK		 2596 if (err)
2597 goto err_req_irq;
2598
9a799d71
AK		 2599 err = ixgbe_up_complete(adapter);
2600 if (err)
2601 goto err_up;
2602
2603 return 0;
2604
2605err_up:
5eba3699 2606 ixgbe_release_hw_control(adapter);
9a799d71
AK		 2607 ixgbe_free_irq(adapter);
2608err_req_irq:
2609 ixgbe_free_all_rx_resources(adapter);
2610err_setup_rx:
2611 ixgbe_free_all_tx_resources(adapter);
2612err_setup_tx:
2613 ixgbe_reset(adapter);
2614
2615 return err;
2616}
2617
2618/**
2619 * ixgbe_close - Disables a network interface
2620 * @netdev: network interface device structure
2621 *
2622 * Returns 0, this is not allowed to fail
2623 *
2624 * The close entry point is called when an interface is de-activated
2625 * by the OS. The hardware is still under the drivers control, but
2626 * needs to be disabled. A global MAC reset is issued to stop the
2627 * hardware, and all transmit and receive resources are freed.
2628 **/
2629static int ixgbe_close(struct net_device *netdev)
2630{
2631 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 2632
2633 ixgbe_down(adapter);
2634 ixgbe_free_irq(adapter);
2635
2636 ixgbe_free_all_tx_resources(adapter);
2637 ixgbe_free_all_rx_resources(adapter);
2638
5eba3699 2639 ixgbe_release_hw_control(adapter);
9a799d71
AK		 2640
2641 return 0;
2642}
2643
2644/**
2645 * ixgbe_update_stats - Update the board statistics counters.
2646 * @adapter: board private structure
2647 **/
2648void ixgbe_update_stats(struct ixgbe_adapter *adapter)
2649{
2650 struct ixgbe_hw *hw = &adapter->hw;
6f11eef7
AV		 2651 u64 total_mpc = 0;
2652 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
9a799d71
AK		 2653
2654 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 2655 for (i = 0; i < 8; i++) {
2656 /* for packet buffers not used, the register should read 0 */
2657 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2658 missed_rx += mpc;
2659 adapter->stats.mpc[i] += mpc;
2660 total_mpc += adapter->stats.mpc[i];
2661 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2662 }
2663 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
2664 /* work around hardware counting issue */
2665 adapter->stats.gprc -= missed_rx;
2666
2667 /* 82598 hardware only has a 32 bit counter in the high register */
9a799d71 2668 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
6f11eef7
AV		 2669 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2670 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
9a799d71
AK		 2671 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2672 adapter->stats.bprc += bprc;
2673 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2674 adapter->stats.mprc -= bprc;
2675 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2676 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2677 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2678 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2679 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2680 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2681 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
9a799d71
AK		 2682 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2683 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
9a799d71 2684 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
6f11eef7
AV		 2685 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2686 adapter->stats.lxontxc += lxon;
2687 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2688 adapter->stats.lxofftxc += lxoff;
9a799d71
AK		 2689 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2690 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6f11eef7
AV		 2691 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2692 /*
2693 * 82598 errata - tx of flow control packets is included in tx counters
2694 */
2695 xon_off_tot = lxon + lxoff;
2696 adapter->stats.gptc -= xon_off_tot;
2697 adapter->stats.mptc -= xon_off_tot;
2698 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
9a799d71
AK		 2699 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2700 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2701 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
9a799d71
AK		 2702 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2703 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6f11eef7 2704 adapter->stats.ptc64 -= xon_off_tot;
9a799d71
AK		 2705 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2706 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2707 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2708 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2709 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
9a799d71
AK		 2710 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2711
2712 /* Fill out the OS statistics structure */
9a799d71
AK		 2713 adapter->net_stats.multicast = adapter->stats.mprc;
2714
2715 /* Rx Errors */
2716 adapter->net_stats.rx_errors = adapter->stats.crcerrs +
2717 adapter->stats.rlec;
2718 adapter->net_stats.rx_dropped = 0;
2719 adapter->net_stats.rx_length_errors = adapter->stats.rlec;
2720 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
6f11eef7 2721 adapter->net_stats.rx_missed_errors = total_mpc;
9a799d71
AK		 2722}
2723
2724/**
2725 * ixgbe_watchdog - Timer Call-back
2726 * @data: pointer to adapter cast into an unsigned long
2727 **/
2728static void ixgbe_watchdog(unsigned long data)
2729{
2730 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
2731 struct net_device *netdev = adapter->netdev;
2732 bool link_up;
2733 u32 link_speed = 0;
30eba97a
AV		 2734#ifdef CONFIG_NETDEVICES_MULTIQUEUE
2735 int i;
2736#endif
9a799d71 2737
3957d63d 2738 adapter->hw.mac.ops.check_link(&adapter->hw, &(link_speed), &link_up);
9a799d71
AK		 2739
2740 if (link_up) {
2741 if (!netif_carrier_ok(netdev)) {
2742 u32 frctl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2743 u32 rmcs = IXGBE_READ_REG(&adapter->hw, IXGBE_RMCS);
2744#define FLOW_RX (frctl & IXGBE_FCTRL_RFCE)
2745#define FLOW_TX (rmcs & IXGBE_RMCS_TFCE_802_3X)
2746 DPRINTK(LINK, INFO, "NIC Link is Up %s, "
2747 "Flow Control: %s\n",
2748 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
2749 "10 Gbps" :
2750 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5a059e9d 2751 "1 Gbps" : "unknown speed")),
9a799d71
AK		 2752 ((FLOW_RX && FLOW_TX) ? "RX/TX" :
2753 (FLOW_RX ? "RX" :
2754 (FLOW_TX ? "TX" : "None"))));
2755
2756 netif_carrier_on(netdev);
2757 netif_wake_queue(netdev);
30eba97a
AV		 2758#ifdef CONFIG_NETDEVICES_MULTIQUEUE
2759 for (i = 0; i < adapter->num_tx_queues; i++)
2760 netif_wake_subqueue(netdev, i);
2761#endif
9a799d71
AK		 2762 } else {
2763 /* Force detection of hung controller */
2764 adapter->detect_tx_hung = true;
2765 }
2766 } else {
2767 if (netif_carrier_ok(netdev)) {
2768 DPRINTK(LINK, INFO, "NIC Link is Down\n");
2769 netif_carrier_off(netdev);
2770 netif_stop_queue(netdev);
2771 }
2772 }
2773
2774 ixgbe_update_stats(adapter);
2775
021230d4
AV		 2776 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2777 /* Cause software interrupt to ensure rx rings are cleaned */
2778 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2779 u32 eics =
2780 (1 << (adapter->num_msix_vectors - NON_Q_VECTORS)) - 1;
2781 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, eics);
2782 } else {
2783 /* for legacy and MSI interrupts don't set any bits that
2784 * are enabled for EIAM, because this operation would
2785 * set *both* EIMS and EICS for any bit in EIAM */
2786 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
2787 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
2788 }
2789 /* Reset the timer */
9a799d71
AK		 2790 mod_timer(&adapter->watchdog_timer,
2791 round_jiffies(jiffies + 2 * HZ));
021230d4 2792 }
9a799d71
AK		 2793}
2794
9a799d71
AK		 2795static int ixgbe_tso(struct ixgbe_adapter *adapter,
2796 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
2797 u32 tx_flags, u8 *hdr_len)
2798{
2799 struct ixgbe_adv_tx_context_desc *context_desc;
2800 unsigned int i;
2801 int err;
2802 struct ixgbe_tx_buffer *tx_buffer_info;
2803 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
2804 u32 mss_l4len_idx = 0, l4len;
9a799d71
AK		 2805
2806 if (skb_is_gso(skb)) {
2807 if (skb_header_cloned(skb)) {
2808 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2809 if (err)
2810 return err;
2811 }
2812 l4len = tcp_hdrlen(skb);
2813 *hdr_len += l4len;
2814
8327d000 2815 if (skb->protocol == htons(ETH_P_IP)) {
9a799d71
AK		 2816 struct iphdr *iph = ip_hdr(skb);
2817 iph->tot_len = 0;
2818 iph->check = 0;
2819 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2820 iph->daddr, 0,
2821 IPPROTO_TCP,
2822 0);
2823 adapter->hw_tso_ctxt++;
2824 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
2825 ipv6_hdr(skb)->payload_len = 0;
2826 tcp_hdr(skb)->check =
2827 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2828 &ipv6_hdr(skb)->daddr,
2829 0, IPPROTO_TCP, 0);
2830 adapter->hw_tso6_ctxt++;
2831 }
2832
2833 i = tx_ring->next_to_use;
2834
2835 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2836 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
2837
2838 /* VLAN MACLEN IPLEN */
2839 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
2840 vlan_macip_lens |=
2841 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
2842 vlan_macip_lens |= ((skb_network_offset(skb)) <<
2843 IXGBE_ADVTXD_MACLEN_SHIFT);
2844 *hdr_len += skb_network_offset(skb);
2845 vlan_macip_lens |=
2846 (skb_transport_header(skb) - skb_network_header(skb));
2847 *hdr_len +=
2848 (skb_transport_header(skb) - skb_network_header(skb));
2849 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
2850 context_desc->seqnum_seed = 0;
2851
2852 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
2853 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
2854 IXGBE_ADVTXD_DTYP_CTXT);
2855
8327d000 2856 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 2857 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
2858 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
2859 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
2860
2861 /* MSS L4LEN IDX */
2862 mss_l4len_idx |=
2863 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
2864 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
2865 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
2866
2867 tx_buffer_info->time_stamp = jiffies;
2868 tx_buffer_info->next_to_watch = i;
2869
2870 i++;
2871 if (i == tx_ring->count)
2872 i = 0;
2873 tx_ring->next_to_use = i;
2874
2875 return true;
2876 }
2877 return false;
2878}
2879
2880static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
2881 struct ixgbe_ring *tx_ring,
2882 struct sk_buff *skb, u32 tx_flags)
2883{
2884 struct ixgbe_adv_tx_context_desc *context_desc;
2885 unsigned int i;
2886 struct ixgbe_tx_buffer *tx_buffer_info;
2887 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
2888
2889 if (skb->ip_summed == CHECKSUM_PARTIAL ||
2890 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
2891 i = tx_ring->next_to_use;
2892 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2893 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
2894
2895 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
2896 vlan_macip_lens |=
2897 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
2898 vlan_macip_lens |= (skb_network_offset(skb) <<
2899 IXGBE_ADVTXD_MACLEN_SHIFT);
2900 if (skb->ip_summed == CHECKSUM_PARTIAL)
2901 vlan_macip_lens |= (skb_transport_header(skb) -
2902 skb_network_header(skb));
2903
2904 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
2905 context_desc->seqnum_seed = 0;
2906
2907 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
2908 IXGBE_ADVTXD_DTYP_CTXT);
2909
2910 if (skb->ip_summed == CHECKSUM_PARTIAL) {
41825d71
AK		 2911 switch (skb->protocol) {
2912 case __constant_htons(ETH_P_IP):
9a799d71 2913 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
41825d71
AK		 2914 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
2915 type_tucmd_mlhl |=
2916 IXGBE_ADVTXD_TUCMD_L4T_TCP;
2917 break;
2918
2919 case __constant_htons(ETH_P_IPV6):
2920 /* XXX what about other V6 headers?? */
2921 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
2922 type_tucmd_mlhl |=
2923 IXGBE_ADVTXD_TUCMD_L4T_TCP;
2924 break;
9a799d71 2925
41825d71
AK		 2926 default:
2927 if (unlikely(net_ratelimit())) {
2928 DPRINTK(PROBE, WARNING,
2929 "partial checksum but proto=%x!\n",
2930 skb->protocol);
2931 }
2932 break;
2933 }
9a799d71
AK		 2934 }
2935
2936 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
2937 context_desc->mss_l4len_idx = 0;
2938
2939 tx_buffer_info->time_stamp = jiffies;
2940 tx_buffer_info->next_to_watch = i;
2941 adapter->hw_csum_tx_good++;
2942 i++;
2943 if (i == tx_ring->count)
2944 i = 0;
2945 tx_ring->next_to_use = i;
2946
2947 return true;
2948 }
2949 return false;
2950}
2951
2952static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
2953 struct ixgbe_ring *tx_ring,
2954 struct sk_buff *skb, unsigned int first)
2955{
2956 struct ixgbe_tx_buffer *tx_buffer_info;
2957 unsigned int len = skb->len;
2958 unsigned int offset = 0, size, count = 0, i;
2959 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
2960 unsigned int f;
2961
2962 len -= skb->data_len;
2963
2964 i = tx_ring->next_to_use;
2965
2966 while (len) {
2967 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2968 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
2969
2970 tx_buffer_info->length = size;
2971 tx_buffer_info->dma = pci_map_single(adapter->pdev,
2972 skb->data + offset,
2973 size, PCI_DMA_TODEVICE);
2974 tx_buffer_info->time_stamp = jiffies;
2975 tx_buffer_info->next_to_watch = i;
2976
2977 len -= size;
2978 offset += size;
2979 count++;
2980 i++;
2981 if (i == tx_ring->count)
2982 i = 0;
2983 }
2984
2985 for (f = 0; f < nr_frags; f++) {
2986 struct skb_frag_struct *frag;
2987
2988 frag = &skb_shinfo(skb)->frags[f];
2989 len = frag->size;
2990 offset = frag->page_offset;
2991
2992 while (len) {
2993 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2994 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
2995
2996 tx_buffer_info->length = size;
2997 tx_buffer_info->dma = pci_map_page(adapter->pdev,
2998 frag->page,
2999 offset,
3000 size, PCI_DMA_TODEVICE);
3001 tx_buffer_info->time_stamp = jiffies;
3002 tx_buffer_info->next_to_watch = i;
3003
3004 len -= size;
3005 offset += size;
3006 count++;
3007 i++;
3008 if (i == tx_ring->count)
3009 i = 0;
3010 }
3011 }
3012 if (i == 0)
3013 i = tx_ring->count - 1;
3014 else
3015 i = i - 1;
3016 tx_ring->tx_buffer_info[i].skb = skb;
3017 tx_ring->tx_buffer_info[first].next_to_watch = i;
3018
3019 return count;
3020}
3021
3022static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
3023 struct ixgbe_ring *tx_ring,
3024 int tx_flags, int count, u32 paylen, u8 hdr_len)
3025{
3026 union ixgbe_adv_tx_desc *tx_desc = NULL;
3027 struct ixgbe_tx_buffer *tx_buffer_info;
3028 u32 olinfo_status = 0, cmd_type_len = 0;
3029 unsigned int i;
3030 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
3031
3032 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
3033
3034 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
3035
3036 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
3037 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
3038
3039 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
3040 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
3041
3042 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
3043 IXGBE_ADVTXD_POPTS_SHIFT;
3044
3045 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
3046 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
3047 IXGBE_ADVTXD_POPTS_SHIFT;
3048
3049 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
3050 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
3051 IXGBE_ADVTXD_POPTS_SHIFT;
3052
3053 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
3054
3055 i = tx_ring->next_to_use;
3056 while (count--) {
3057 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3058 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
3059 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
3060 tx_desc->read.cmd_type_len =
3061 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
3062 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
3063
3064 i++;
3065 if (i == tx_ring->count)
3066 i = 0;
3067 }
3068
3069 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
3070
3071 /*
3072 * Force memory writes to complete before letting h/w
3073 * know there are new descriptors to fetch. (Only
3074 * applicable for weak-ordered memory model archs,
3075 * such as IA-64).
3076 */
3077 wmb();
3078
3079 tx_ring->next_to_use = i;
3080 writel(i, adapter->hw.hw_addr + tx_ring->tail);
3081}
3082
e092be60
AV		 3083static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
3084 struct ixgbe_ring *tx_ring, int size)
3085{
3086 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3087
30eba97a
AV		 3088#ifdef CONFIG_NETDEVICES_MULTIQUEUE
3089 netif_stop_subqueue(netdev, tx_ring->queue_index);
3090#else
e092be60 3091 netif_stop_queue(netdev);
30eba97a 3092#endif
e092be60
AV		 3093 /* Herbert's original patch had:
3094 * smp_mb__after_netif_stop_queue();
3095 * but since that doesn't exist yet, just open code it. */
3096 smp_mb();
3097
3098 /* We need to check again in a case another CPU has just
3099 * made room available. */
3100 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
3101 return -EBUSY;
3102
3103 /* A reprieve! - use start_queue because it doesn't call schedule */
30eba97a
AV		 3104#ifdef CONFIG_NETDEVICES_MULTIQUEUE
3105 netif_wake_subqueue(netdev, tx_ring->queue_index);
3106#else
e092be60 3107 netif_wake_queue(netdev);
30eba97a 3108#endif
e092be60
AV		 3109 ++adapter->restart_queue;
3110 return 0;
3111}
3112
3113static int ixgbe_maybe_stop_tx(struct net_device *netdev,
3114 struct ixgbe_ring *tx_ring, int size)
3115{
3116 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
3117 return 0;
3118 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
3119}
3120
3121
9a799d71
AK		 3122static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
3123{
3124 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3125 struct ixgbe_ring *tx_ring;
3126 unsigned int len = skb->len;
3127 unsigned int first;
3128 unsigned int tx_flags = 0;
30eba97a
AV		 3129 u8 hdr_len = 0;
3130 int r_idx = 0, tso;
9a799d71
AK		 3131 unsigned int mss = 0;
3132 int count = 0;
3133 unsigned int f;
3134 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
3135 len -= skb->data_len;
30eba97a
AV		 3136#ifdef CONFIG_NETDEVICES_MULTIQUEUE
3137 r_idx = (adapter->num_tx_queues - 1) & skb->queue_mapping;
3138#endif
3139 tx_ring = &adapter->tx_ring[r_idx];
9a799d71 3140
9a799d71
AK		 3141
3142 if (skb->len <= 0) {
3143 dev_kfree_skb(skb);
3144 return NETDEV_TX_OK;
3145 }
3146 mss = skb_shinfo(skb)->gso_size;
3147
3148 if (mss)
3149 count++;
3150 else if (skb->ip_summed == CHECKSUM_PARTIAL)
3151 count++;
3152
3153 count += TXD_USE_COUNT(len);
3154 for (f = 0; f < nr_frags; f++)
3155 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
3156
e092be60 3157 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
9a799d71 3158 adapter->tx_busy++;
9a799d71
AK		 3159 return NETDEV_TX_BUSY;
3160 }
9a799d71
AK		 3161 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
3162 tx_flags |= IXGBE_TX_FLAGS_VLAN;
3163 tx_flags |= (vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT);
3164 }
3165
8327d000 3166 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 3167 tx_flags |= IXGBE_TX_FLAGS_IPV4;
3168 first = tx_ring->next_to_use;
3169 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
3170 if (tso < 0) {
3171 dev_kfree_skb_any(skb);
3172 return NETDEV_TX_OK;
3173 }
3174
3175 if (tso)
3176 tx_flags |= IXGBE_TX_FLAGS_TSO;
3177 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
3178 (skb->ip_summed == CHECKSUM_PARTIAL))
3179 tx_flags |= IXGBE_TX_FLAGS_CSUM;
3180
3181 ixgbe_tx_queue(adapter, tx_ring, tx_flags,
3182 ixgbe_tx_map(adapter, tx_ring, skb, first),
3183 skb->len, hdr_len);
3184
3185 netdev->trans_start = jiffies;
3186
e092be60 3187 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
9a799d71
AK		 3188
3189 return NETDEV_TX_OK;
3190}
3191
3192/**
3193 * ixgbe_get_stats - Get System Network Statistics
3194 * @netdev: network interface device structure
3195 *
3196 * Returns the address of the device statistics structure.
3197 * The statistics are actually updated from the timer callback.
3198 **/
3199static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
3200{
3201 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3202
3203 /* only return the current stats */
3204 return &adapter->net_stats;
3205}
3206
3207/**
3208 * ixgbe_set_mac - Change the Ethernet Address of the NIC
3209 * @netdev: network interface device structure
3210 * @p: pointer to an address structure
3211 *
3212 * Returns 0 on success, negative on failure
3213 **/
3214static int ixgbe_set_mac(struct net_device *netdev, void *p)
3215{
3216 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3217 struct sockaddr *addr = p;
3218
3219 if (!is_valid_ether_addr(addr->sa_data))
3220 return -EADDRNOTAVAIL;
3221
3222 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
3223 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
3224
3225 ixgbe_set_rar(&adapter->hw, 0, adapter->hw.mac.addr, 0, IXGBE_RAH_AV);
3226
3227 return 0;
3228}
3229
3230#ifdef CONFIG_NET_POLL_CONTROLLER
3231/*
3232 * Polling 'interrupt' - used by things like netconsole to send skbs
3233 * without having to re-enable interrupts. It's not called while
3234 * the interrupt routine is executing.
3235 */
3236static void ixgbe_netpoll(struct net_device *netdev)
3237{
3238 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3239
3240 disable_irq(adapter->pdev->irq);
3241 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
3242 ixgbe_intr(adapter->pdev->irq, netdev);
3243 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
3244 enable_irq(adapter->pdev->irq);
3245}
3246#endif
3247
021230d4
AV		 3248/**
3249 * ixgbe_napi_add_all - prep napi structs for use
3250 * @adapter: private struct
3251 * helper function to napi_add each possible q_vector->napi
3252 */
3253static void ixgbe_napi_add_all(struct ixgbe_adapter *adapter)
3254{
3255 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3256 int (*poll)(struct napi_struct *, int);
3257
3258 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3259 poll = &ixgbe_clean_rxonly;
3260 } else {
3261 poll = &ixgbe_poll;
3262 /* only one q_vector for legacy modes */
3263 q_vectors = 1;
3264 }
3265
3266 for (i = 0; i < q_vectors; i++) {
3267 struct ixgbe_q_vector *q_vector = &adapter->q_vector[i];
3268 netif_napi_add(adapter->netdev, &q_vector->napi,
3269 (*poll), 64);
3270 }
3271}
3272
9a799d71
AK		 3273/**
3274 * ixgbe_probe - Device Initialization Routine
3275 * @pdev: PCI device information struct
3276 * @ent: entry in ixgbe_pci_tbl
3277 *
3278 * Returns 0 on success, negative on failure
3279 *
3280 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
3281 * The OS initialization, configuring of the adapter private structure,
3282 * and a hardware reset occur.
3283 **/
3284static int __devinit ixgbe_probe(struct pci_dev *pdev,
3285 const struct pci_device_id *ent)
3286{
3287 struct net_device *netdev;
3288 struct ixgbe_adapter *adapter = NULL;
3289 struct ixgbe_hw *hw;
3290 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
3291 unsigned long mmio_start, mmio_len;
3292 static int cards_found;
3293 int i, err, pci_using_dac;
3294 u16 link_status, link_speed, link_width;
3295 u32 part_num;
3296
3297 err = pci_enable_device(pdev);
3298 if (err)
3299 return err;
3300
3301 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK) &&
3302 !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK)) {
3303 pci_using_dac = 1;
3304 } else {
3305 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3306 if (err) {
3307 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3308 if (err) {
3309 dev_err(&pdev->dev, "No usable DMA "
3310 "configuration, aborting\n");
3311 goto err_dma;
3312 }
3313 }
3314 pci_using_dac = 0;
3315 }
3316
3317 err = pci_request_regions(pdev, ixgbe_driver_name);
3318 if (err) {
3319 dev_err(&pdev->dev, "pci_request_regions failed 0x%x\n", err);
3320 goto err_pci_reg;
3321 }
3322
3323 pci_set_master(pdev);
3324
30eba97a
AV		 3325#ifdef CONFIG_NETDEVICES_MULTIQUEUE
3326 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
3327#else
9a799d71 3328 netdev = alloc_etherdev(sizeof(struct ixgbe_adapter));
30eba97a 3329#endif
9a799d71
AK		 3330 if (!netdev) {
3331 err = -ENOMEM;
3332 goto err_alloc_etherdev;
3333 }
3334
9a799d71
AK		 3335 SET_NETDEV_DEV(netdev, &pdev->dev);
3336
3337 pci_set_drvdata(pdev, netdev);
3338 adapter = netdev_priv(netdev);
3339
3340 adapter->netdev = netdev;
3341 adapter->pdev = pdev;
3342 hw = &adapter->hw;
3343 hw->back = adapter;
3344 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
3345
3346 mmio_start = pci_resource_start(pdev, 0);
3347 mmio_len = pci_resource_len(pdev, 0);
3348
3349 hw->hw_addr = ioremap(mmio_start, mmio_len);
3350 if (!hw->hw_addr) {
3351 err = -EIO;
3352 goto err_ioremap;
3353 }
3354
3355 for (i = 1; i <= 5; i++) {
3356 if (pci_resource_len(pdev, i) == 0)
3357 continue;
3358 }
3359
3360 netdev->open = &ixgbe_open;
3361 netdev->stop = &ixgbe_close;
3362 netdev->hard_start_xmit = &ixgbe_xmit_frame;
3363 netdev->get_stats = &ixgbe_get_stats;
3364 netdev->set_multicast_list = &ixgbe_set_multi;
3365 netdev->set_mac_address = &ixgbe_set_mac;
3366 netdev->change_mtu = &ixgbe_change_mtu;
3367 ixgbe_set_ethtool_ops(netdev);
3368 netdev->tx_timeout = &ixgbe_tx_timeout;
3369 netdev->watchdog_timeo = 5 * HZ;
9a799d71
AK		 3370 netdev->vlan_rx_register = ixgbe_vlan_rx_register;
3371 netdev->vlan_rx_add_vid = ixgbe_vlan_rx_add_vid;
3372 netdev->vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid;
3373#ifdef CONFIG_NET_POLL_CONTROLLER
3374 netdev->poll_controller = ixgbe_netpoll;
3375#endif
3376 strcpy(netdev->name, pci_name(pdev));
3377
3378 netdev->mem_start = mmio_start;
3379 netdev->mem_end = mmio_start + mmio_len;
3380
3381 adapter->bd_number = cards_found;
3382
3383 /* PCI config space info */
3384 hw->vendor_id = pdev->vendor;
3385 hw->device_id = pdev->device;
3386 hw->revision_id = pdev->revision;
3387 hw->subsystem_vendor_id = pdev->subsystem_vendor;
3388 hw->subsystem_device_id = pdev->subsystem_device;
3389
3390 /* Setup hw api */
3391 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 3392 hw->mac.type = ii->mac;
9a799d71
AK		 3393
3394 err = ii->get_invariants(hw);
3395 if (err)
3396 goto err_hw_init;
3397
3398 /* setup the private structure */
3399 err = ixgbe_sw_init(adapter);
3400 if (err)
3401 goto err_sw_init;
3402
3403 netdev->features = NETIF_F_SG |
3404 NETIF_F_HW_CSUM |
3405 NETIF_F_HW_VLAN_TX |
3406 NETIF_F_HW_VLAN_RX |
3407 NETIF_F_HW_VLAN_FILTER;
3408
3409 netdev->features |= NETIF_F_TSO;
3410
3411 netdev->features |= NETIF_F_TSO6;
3412 if (pci_using_dac)
3413 netdev->features |= NETIF_F_HIGHDMA;
3414
30eba97a
AV		 3415#ifdef CONFIG_NETDEVICES_MULTIQUEUE
3416 netdev->features |= NETIF_F_MULTI_QUEUE;
3417#endif
9a799d71
AK		 3418
3419 /* make sure the EEPROM is good */
3420 if (ixgbe_validate_eeprom_checksum(hw, NULL) < 0) {
3421 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
3422 err = -EIO;
3423 goto err_eeprom;
3424 }
3425
3426 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
3427 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
3428
3429 if (ixgbe_validate_mac_addr(netdev->dev_addr)) {
3430 err = -EIO;
3431 goto err_eeprom;
3432 }
3433
3434 init_timer(&adapter->watchdog_timer);
3435 adapter->watchdog_timer.function = &ixgbe_watchdog;
3436 adapter->watchdog_timer.data = (unsigned long)adapter;
3437
3438 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
3439
3440 /* initialize default flow control settings */
3441 hw->fc.original_type = ixgbe_fc_full;
3442 hw->fc.type = ixgbe_fc_full;
3443 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
3444 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
3445 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
3446
021230d4
AV		 3447 err = ixgbe_init_interrupt_scheme(adapter);
3448 if (err)
3449 goto err_sw_init;
9a799d71
AK		 3450
3451 /* print bus type/speed/width info */
3452 pci_read_config_word(pdev, IXGBE_PCI_LINK_STATUS, &link_status);
3453 link_speed = link_status & IXGBE_PCI_LINK_SPEED;
3454 link_width = link_status & IXGBE_PCI_LINK_WIDTH;
3455 dev_info(&pdev->dev, "(PCI Express:%s:%s) "
3456 "%02x:%02x:%02x:%02x:%02x:%02x\n",
3457 ((link_speed == IXGBE_PCI_LINK_SPEED_5000) ? "5.0Gb/s" :
3458 (link_speed == IXGBE_PCI_LINK_SPEED_2500) ? "2.5Gb/s" :
3459 "Unknown"),
3460 ((link_width == IXGBE_PCI_LINK_WIDTH_8) ? "Width x8" :
3461 (link_width == IXGBE_PCI_LINK_WIDTH_4) ? "Width x4" :
3462 (link_width == IXGBE_PCI_LINK_WIDTH_2) ? "Width x2" :
3463 (link_width == IXGBE_PCI_LINK_WIDTH_1) ? "Width x1" :
3464 "Unknown"),
3465 netdev->dev_addr[0], netdev->dev_addr[1], netdev->dev_addr[2],
3466 netdev->dev_addr[3], netdev->dev_addr[4], netdev->dev_addr[5]);
3467 ixgbe_read_part_num(hw, &part_num);
3468 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
3469 hw->mac.type, hw->phy.type,
3470 (part_num >> 8), (part_num & 0xff));
3471
0c254d86
AK		 3472 if (link_width <= IXGBE_PCI_LINK_WIDTH_4) {
3473 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
3474 "this card is not sufficient for optimal "
3475 "performance.\n");
3476 dev_warn(&pdev->dev, "For optimal performance a x8 "
3477 "PCI-Express slot is required.\n");
3478 }
3479
9a799d71
AK		 3480 /* reset the hardware with the new settings */
3481 ixgbe_start_hw(hw);
3482
3483 netif_carrier_off(netdev);
3484 netif_stop_queue(netdev);
30eba97a
AV		 3485#ifdef CONFIG_NETDEVICES_MULTIQUEUE
3486 for (i = 0; i < adapter->num_tx_queues; i++)
3487 netif_stop_subqueue(netdev, i);
3488#endif
9a799d71 3489
021230d4
AV		 3490 ixgbe_napi_add_all(adapter);
3491
9a799d71
AK		 3492 strcpy(netdev->name, "eth%d");
3493 err = register_netdev(netdev);
3494 if (err)
3495 goto err_register;
3496
3497
3498 dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
3499 cards_found++;
3500 return 0;
3501
3502err_register:
5eba3699 3503 ixgbe_release_hw_control(adapter);
9a799d71
AK		 3504err_hw_init:
3505err_sw_init:
021230d4 3506 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 3507err_eeprom:
3508 iounmap(hw->hw_addr);
3509err_ioremap:
3510 free_netdev(netdev);
3511err_alloc_etherdev:
3512 pci_release_regions(pdev);
3513err_pci_reg:
3514err_dma:
3515 pci_disable_device(pdev);
3516 return err;
3517}
3518
3519/**
3520 * ixgbe_remove - Device Removal Routine
3521 * @pdev: PCI device information struct
3522 *
3523 * ixgbe_remove is called by the PCI subsystem to alert the driver
3524 * that it should release a PCI device. The could be caused by a
3525 * Hot-Plug event, or because the driver is going to be removed from
3526 * memory.
3527 **/
3528static void __devexit ixgbe_remove(struct pci_dev *pdev)
3529{
3530 struct net_device *netdev = pci_get_drvdata(pdev);
3531 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3532
3533 set_bit(__IXGBE_DOWN, &adapter->state);
3534 del_timer_sync(&adapter->watchdog_timer);
3535
3536 flush_scheduled_work();
3537
3538 unregister_netdev(netdev);
3539
021230d4 3540 ixgbe_reset_interrupt_capability(adapter);
5eba3699 3541
021230d4 3542 ixgbe_release_hw_control(adapter);
9a799d71
AK		 3543
3544 iounmap(adapter->hw.hw_addr);
3545 pci_release_regions(pdev);
3546
021230d4
AV		 3547 DPRINTK(PROBE, INFO, "complete\n");
3548 kfree(adapter->tx_ring);
3549 kfree(adapter->rx_ring);
3550
9a799d71
AK		 3551 free_netdev(netdev);
3552
3553 pci_disable_device(pdev);
3554}
3555
3556/**
3557 * ixgbe_io_error_detected - called when PCI error is detected
3558 * @pdev: Pointer to PCI device
3559 * @state: The current pci connection state
3560 *
3561 * This function is called after a PCI bus error affecting
3562 * this device has been detected.
3563 */
3564static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
3565 pci_channel_state_t state)
3566{
3567 struct net_device *netdev = pci_get_drvdata(pdev);
3568 struct ixgbe_adapter *adapter = netdev->priv;
3569
3570 netif_device_detach(netdev);
3571
3572 if (netif_running(netdev))
3573 ixgbe_down(adapter);
3574 pci_disable_device(pdev);
3575
3576 /* Request a slot slot reset. */
3577 return PCI_ERS_RESULT_NEED_RESET;
3578}
3579
3580/**
3581 * ixgbe_io_slot_reset - called after the pci bus has been reset.
3582 * @pdev: Pointer to PCI device
3583 *
3584 * Restart the card from scratch, as if from a cold-boot.
3585 */
3586static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
3587{
3588 struct net_device *netdev = pci_get_drvdata(pdev);
3589 struct ixgbe_adapter *adapter = netdev->priv;
3590
3591 if (pci_enable_device(pdev)) {
3592 DPRINTK(PROBE, ERR,
3593 "Cannot re-enable PCI device after reset.\n");
3594 return PCI_ERS_RESULT_DISCONNECT;
3595 }
3596 pci_set_master(pdev);
3597
3598 pci_enable_wake(pdev, PCI_D3hot, 0);
3599 pci_enable_wake(pdev, PCI_D3cold, 0);
3600
3601 ixgbe_reset(adapter);
3602
3603 return PCI_ERS_RESULT_RECOVERED;
3604}
3605
3606/**
3607 * ixgbe_io_resume - called when traffic can start flowing again.
3608 * @pdev: Pointer to PCI device
3609 *
3610 * This callback is called when the error recovery driver tells us that
3611 * its OK to resume normal operation.
3612 */
3613static void ixgbe_io_resume(struct pci_dev *pdev)
3614{
3615 struct net_device *netdev = pci_get_drvdata(pdev);
3616 struct ixgbe_adapter *adapter = netdev->priv;
3617
3618 if (netif_running(netdev)) {
3619 if (ixgbe_up(adapter)) {
3620 DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
3621 return;
3622 }
3623 }
3624
3625 netif_device_attach(netdev);
3626
3627}
3628
3629static struct pci_error_handlers ixgbe_err_handler = {
3630 .error_detected = ixgbe_io_error_detected,
3631 .slot_reset = ixgbe_io_slot_reset,
3632 .resume = ixgbe_io_resume,
3633};
3634
3635static struct pci_driver ixgbe_driver = {
3636 .name = ixgbe_driver_name,
3637 .id_table = ixgbe_pci_tbl,
3638 .probe = ixgbe_probe,
3639 .remove = __devexit_p(ixgbe_remove),
3640#ifdef CONFIG_PM
3641 .suspend = ixgbe_suspend,
3642 .resume = ixgbe_resume,
3643#endif
3644 .shutdown = ixgbe_shutdown,
3645 .err_handler = &ixgbe_err_handler
3646};
3647
3648/**
3649 * ixgbe_init_module - Driver Registration Routine
3650 *
3651 * ixgbe_init_module is the first routine called when the driver is
3652 * loaded. All it does is register with the PCI subsystem.
3653 **/
3654static int __init ixgbe_init_module(void)
3655{
3656 int ret;
3657 printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
3658 ixgbe_driver_string, ixgbe_driver_version);
3659
3660 printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
3661
3662 ret = pci_register_driver(&ixgbe_driver);
3663 return ret;
3664}
3665module_init(ixgbe_init_module);
3666
3667/**
3668 * ixgbe_exit_module - Driver Exit Cleanup Routine
3669 *
3670 * ixgbe_exit_module is called just before the driver is removed
3671 * from memory.
3672 **/
3673static void __exit ixgbe_exit_module(void)
3674{
3675 pci_unregister_driver(&ixgbe_driver);
3676}
3677module_exit(ixgbe_exit_module);
3678
3679/* ixgbe_main.c */
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