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92744989 GL |
1 | /* |
2 | * Driver for Xilinx TEMAC Ethernet device | |
3 | * | |
4 | * Copyright (c) 2008 Nissin Systems Co., Ltd., Yoshio Kashiwagi | |
5 | * Copyright (c) 2005-2008 DLA Systems, David H. Lynch Jr. <dhlii@dlasys.net> | |
6 | * Copyright (c) 2008-2009 Secret Lab Technologies Ltd. | |
7 | * | |
8 | * This is a driver for the Xilinx ll_temac ipcore which is often used | |
9 | * in the Virtex and Spartan series of chips. | |
10 | * | |
11 | * Notes: | |
12 | * - The ll_temac hardware uses indirect access for many of the TEMAC | |
13 | * registers, include the MDIO bus. However, indirect access to MDIO | |
14 | * registers take considerably more clock cycles than to TEMAC registers. | |
15 | * MDIO accesses are long, so threads doing them should probably sleep | |
16 | * rather than busywait. However, since only one indirect access can be | |
17 | * in progress at any given time, that means that *all* indirect accesses | |
18 | * could end up sleeping (to wait for an MDIO access to complete). | |
19 | * Fortunately none of the indirect accesses are on the 'hot' path for tx | |
20 | * or rx, so this should be okay. | |
21 | * | |
22 | * TODO: | |
92744989 GL |
23 | * - Factor out locallink DMA code into separate driver |
24 | * - Fix multicast assignment. | |
25 | * - Fix support for hardware checksumming. | |
26 | * - Testing. Lots and lots of testing. | |
27 | * | |
28 | */ | |
29 | ||
30 | #include <linux/delay.h> | |
31 | #include <linux/etherdevice.h> | |
32 | #include <linux/init.h> | |
33 | #include <linux/mii.h> | |
34 | #include <linux/module.h> | |
35 | #include <linux/mutex.h> | |
36 | #include <linux/netdevice.h> | |
37 | #include <linux/of.h> | |
38 | #include <linux/of_device.h> | |
39 | #include <linux/of_mdio.h> | |
40 | #include <linux/of_platform.h> | |
41 | #include <linux/skbuff.h> | |
42 | #include <linux/spinlock.h> | |
43 | #include <linux/tcp.h> /* needed for sizeof(tcphdr) */ | |
44 | #include <linux/udp.h> /* needed for sizeof(udphdr) */ | |
45 | #include <linux/phy.h> | |
46 | #include <linux/in.h> | |
47 | #include <linux/io.h> | |
48 | #include <linux/ip.h> | |
5a0e3ad6 | 49 | #include <linux/slab.h> |
92744989 GL |
50 | |
51 | #include "ll_temac.h" | |
52 | ||
53 | #define TX_BD_NUM 64 | |
54 | #define RX_BD_NUM 128 | |
55 | ||
56 | /* --------------------------------------------------------------------- | |
57 | * Low level register access functions | |
58 | */ | |
59 | ||
60 | u32 temac_ior(struct temac_local *lp, int offset) | |
61 | { | |
62 | return in_be32((u32 *)(lp->regs + offset)); | |
63 | } | |
64 | ||
65 | void temac_iow(struct temac_local *lp, int offset, u32 value) | |
66 | { | |
67 | out_be32((u32 *) (lp->regs + offset), value); | |
68 | } | |
69 | ||
70 | int temac_indirect_busywait(struct temac_local *lp) | |
71 | { | |
72 | long end = jiffies + 2; | |
73 | ||
74 | while (!(temac_ior(lp, XTE_RDY0_OFFSET) & XTE_RDY0_HARD_ACS_RDY_MASK)) { | |
75 | if (end - jiffies <= 0) { | |
76 | WARN_ON(1); | |
77 | return -ETIMEDOUT; | |
78 | } | |
79 | msleep(1); | |
80 | } | |
81 | return 0; | |
82 | } | |
83 | ||
84 | /** | |
85 | * temac_indirect_in32 | |
86 | * | |
87 | * lp->indirect_mutex must be held when calling this function | |
88 | */ | |
89 | u32 temac_indirect_in32(struct temac_local *lp, int reg) | |
90 | { | |
91 | u32 val; | |
92 | ||
93 | if (temac_indirect_busywait(lp)) | |
94 | return -ETIMEDOUT; | |
95 | temac_iow(lp, XTE_CTL0_OFFSET, reg); | |
96 | if (temac_indirect_busywait(lp)) | |
97 | return -ETIMEDOUT; | |
98 | val = temac_ior(lp, XTE_LSW0_OFFSET); | |
99 | ||
100 | return val; | |
101 | } | |
102 | ||
103 | /** | |
104 | * temac_indirect_out32 | |
105 | * | |
106 | * lp->indirect_mutex must be held when calling this function | |
107 | */ | |
108 | void temac_indirect_out32(struct temac_local *lp, int reg, u32 value) | |
109 | { | |
110 | if (temac_indirect_busywait(lp)) | |
111 | return; | |
112 | temac_iow(lp, XTE_LSW0_OFFSET, value); | |
113 | temac_iow(lp, XTE_CTL0_OFFSET, CNTLREG_WRITE_ENABLE_MASK | reg); | |
114 | } | |
115 | ||
e44171f1 JL |
116 | /** |
117 | * temac_dma_in32 - Memory mapped DMA read, this function expects a | |
118 | * register input that is based on DCR word addresses which | |
119 | * are then converted to memory mapped byte addresses | |
120 | */ | |
92744989 GL |
121 | static u32 temac_dma_in32(struct temac_local *lp, int reg) |
122 | { | |
e44171f1 | 123 | return in_be32((u32 *)(lp->sdma_regs + (reg << 2))); |
92744989 GL |
124 | } |
125 | ||
e44171f1 JL |
126 | /** |
127 | * temac_dma_out32 - Memory mapped DMA read, this function expects a | |
128 | * register input that is based on DCR word addresses which | |
129 | * are then converted to memory mapped byte addresses | |
130 | */ | |
92744989 | 131 | static void temac_dma_out32(struct temac_local *lp, int reg, u32 value) |
e44171f1 JL |
132 | { |
133 | out_be32((u32 *)(lp->sdma_regs + (reg << 2)), value); | |
134 | } | |
135 | ||
136 | /* DMA register access functions can be DCR based or memory mapped. | |
137 | * The PowerPC 440 is DCR based, the PowerPC 405 and MicroBlaze are both | |
138 | * memory mapped. | |
139 | */ | |
140 | #ifdef CONFIG_PPC_DCR | |
141 | ||
142 | /** | |
143 | * temac_dma_dcr_in32 - DCR based DMA read | |
144 | */ | |
145 | static u32 temac_dma_dcr_in(struct temac_local *lp, int reg) | |
146 | { | |
147 | return dcr_read(lp->sdma_dcrs, reg); | |
148 | } | |
149 | ||
150 | /** | |
151 | * temac_dma_dcr_out32 - DCR based DMA write | |
152 | */ | |
153 | static void temac_dma_dcr_out(struct temac_local *lp, int reg, u32 value) | |
92744989 GL |
154 | { |
155 | dcr_write(lp->sdma_dcrs, reg, value); | |
156 | } | |
157 | ||
e44171f1 JL |
158 | /** |
159 | * temac_dcr_setup - If the DMA is DCR based, then setup the address and | |
160 | * I/O functions | |
161 | */ | |
162 | static int temac_dcr_setup(struct temac_local *lp, struct of_device *op, | |
163 | struct device_node *np) | |
164 | { | |
165 | unsigned int dcrs; | |
166 | ||
167 | /* setup the dcr address mapping if it's in the device tree */ | |
168 | ||
169 | dcrs = dcr_resource_start(np, 0); | |
170 | if (dcrs != 0) { | |
171 | lp->sdma_dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0)); | |
172 | lp->dma_in = temac_dma_dcr_in; | |
173 | lp->dma_out = temac_dma_dcr_out; | |
174 | dev_dbg(&op->dev, "DCR base: %x\n", dcrs); | |
175 | return 0; | |
176 | } | |
177 | /* no DCR in the device tree, indicate a failure */ | |
178 | return -1; | |
179 | } | |
180 | ||
181 | #else | |
182 | ||
183 | /* | |
184 | * temac_dcr_setup - This is a stub for when DCR is not supported, | |
185 | * such as with MicroBlaze | |
186 | */ | |
187 | static int temac_dcr_setup(struct temac_local *lp, struct of_device *op, | |
188 | struct device_node *np) | |
189 | { | |
190 | return -1; | |
191 | } | |
192 | ||
193 | #endif | |
194 | ||
92744989 GL |
195 | /** |
196 | * temac_dma_bd_init - Setup buffer descriptor rings | |
197 | */ | |
198 | static int temac_dma_bd_init(struct net_device *ndev) | |
199 | { | |
200 | struct temac_local *lp = netdev_priv(ndev); | |
201 | struct sk_buff *skb; | |
202 | int i; | |
203 | ||
5d66fe92 | 204 | lp->rx_skb = kzalloc(sizeof(*lp->rx_skb) * RX_BD_NUM, GFP_KERNEL); |
92744989 GL |
205 | /* allocate the tx and rx ring buffer descriptors. */ |
206 | /* returns a virtual addres and a physical address. */ | |
207 | lp->tx_bd_v = dma_alloc_coherent(ndev->dev.parent, | |
208 | sizeof(*lp->tx_bd_v) * TX_BD_NUM, | |
209 | &lp->tx_bd_p, GFP_KERNEL); | |
210 | lp->rx_bd_v = dma_alloc_coherent(ndev->dev.parent, | |
211 | sizeof(*lp->rx_bd_v) * RX_BD_NUM, | |
212 | &lp->rx_bd_p, GFP_KERNEL); | |
213 | ||
214 | memset(lp->tx_bd_v, 0, sizeof(*lp->tx_bd_v) * TX_BD_NUM); | |
215 | for (i = 0; i < TX_BD_NUM; i++) { | |
216 | lp->tx_bd_v[i].next = lp->tx_bd_p + | |
217 | sizeof(*lp->tx_bd_v) * ((i + 1) % TX_BD_NUM); | |
218 | } | |
219 | ||
220 | memset(lp->rx_bd_v, 0, sizeof(*lp->rx_bd_v) * RX_BD_NUM); | |
221 | for (i = 0; i < RX_BD_NUM; i++) { | |
222 | lp->rx_bd_v[i].next = lp->rx_bd_p + | |
223 | sizeof(*lp->rx_bd_v) * ((i + 1) % RX_BD_NUM); | |
224 | ||
e44171f1 JL |
225 | skb = netdev_alloc_skb_ip_align(ndev, |
226 | XTE_MAX_JUMBO_FRAME_SIZE); | |
227 | ||
92744989 GL |
228 | if (skb == 0) { |
229 | dev_err(&ndev->dev, "alloc_skb error %d\n", i); | |
230 | return -1; | |
231 | } | |
232 | lp->rx_skb[i] = skb; | |
92744989 GL |
233 | /* returns physical address of skb->data */ |
234 | lp->rx_bd_v[i].phys = dma_map_single(ndev->dev.parent, | |
235 | skb->data, | |
236 | XTE_MAX_JUMBO_FRAME_SIZE, | |
237 | DMA_FROM_DEVICE); | |
238 | lp->rx_bd_v[i].len = XTE_MAX_JUMBO_FRAME_SIZE; | |
239 | lp->rx_bd_v[i].app0 = STS_CTRL_APP0_IRQONEND; | |
240 | } | |
241 | ||
e44171f1 | 242 | lp->dma_out(lp, TX_CHNL_CTRL, 0x10220400 | |
92744989 GL |
243 | CHNL_CTRL_IRQ_EN | |
244 | CHNL_CTRL_IRQ_DLY_EN | | |
245 | CHNL_CTRL_IRQ_COAL_EN); | |
246 | /* 0x10220483 */ | |
247 | /* 0x00100483 */ | |
23ecc4bd | 248 | lp->dma_out(lp, RX_CHNL_CTRL, 0xff070000 | |
92744989 GL |
249 | CHNL_CTRL_IRQ_EN | |
250 | CHNL_CTRL_IRQ_DLY_EN | | |
251 | CHNL_CTRL_IRQ_COAL_EN | | |
252 | CHNL_CTRL_IRQ_IOE); | |
253 | /* 0xff010283 */ | |
254 | ||
e44171f1 JL |
255 | lp->dma_out(lp, RX_CURDESC_PTR, lp->rx_bd_p); |
256 | lp->dma_out(lp, RX_TAILDESC_PTR, | |
92744989 | 257 | lp->rx_bd_p + (sizeof(*lp->rx_bd_v) * (RX_BD_NUM - 1))); |
e44171f1 | 258 | lp->dma_out(lp, TX_CURDESC_PTR, lp->tx_bd_p); |
92744989 GL |
259 | |
260 | return 0; | |
261 | } | |
262 | ||
263 | /* --------------------------------------------------------------------- | |
264 | * net_device_ops | |
265 | */ | |
266 | ||
267 | static int temac_set_mac_address(struct net_device *ndev, void *address) | |
268 | { | |
269 | struct temac_local *lp = netdev_priv(ndev); | |
270 | ||
271 | if (address) | |
272 | memcpy(ndev->dev_addr, address, ETH_ALEN); | |
273 | ||
274 | if (!is_valid_ether_addr(ndev->dev_addr)) | |
275 | random_ether_addr(ndev->dev_addr); | |
276 | ||
277 | /* set up unicast MAC address filter set its mac address */ | |
278 | mutex_lock(&lp->indirect_mutex); | |
279 | temac_indirect_out32(lp, XTE_UAW0_OFFSET, | |
280 | (ndev->dev_addr[0]) | | |
281 | (ndev->dev_addr[1] << 8) | | |
282 | (ndev->dev_addr[2] << 16) | | |
283 | (ndev->dev_addr[3] << 24)); | |
284 | /* There are reserved bits in EUAW1 | |
285 | * so don't affect them Set MAC bits [47:32] in EUAW1 */ | |
286 | temac_indirect_out32(lp, XTE_UAW1_OFFSET, | |
287 | (ndev->dev_addr[4] & 0x000000ff) | | |
288 | (ndev->dev_addr[5] << 8)); | |
289 | mutex_unlock(&lp->indirect_mutex); | |
290 | ||
291 | return 0; | |
292 | } | |
293 | ||
8ea7a37c SM |
294 | static int netdev_set_mac_address(struct net_device *ndev, void *p) |
295 | { | |
296 | struct sockaddr *addr = p; | |
297 | ||
298 | return temac_set_mac_address(ndev, addr->sa_data); | |
299 | } | |
300 | ||
92744989 GL |
301 | static void temac_set_multicast_list(struct net_device *ndev) |
302 | { | |
303 | struct temac_local *lp = netdev_priv(ndev); | |
304 | u32 multi_addr_msw, multi_addr_lsw, val; | |
305 | int i; | |
306 | ||
307 | mutex_lock(&lp->indirect_mutex); | |
8e95a202 | 308 | if (ndev->flags & (IFF_ALLMULTI | IFF_PROMISC) || |
4cd24eaf | 309 | netdev_mc_count(ndev) > MULTICAST_CAM_TABLE_NUM) { |
92744989 GL |
310 | /* |
311 | * We must make the kernel realise we had to move | |
312 | * into promisc mode or we start all out war on | |
313 | * the cable. If it was a promisc request the | |
314 | * flag is already set. If not we assert it. | |
315 | */ | |
316 | ndev->flags |= IFF_PROMISC; | |
317 | temac_indirect_out32(lp, XTE_AFM_OFFSET, XTE_AFM_EPPRM_MASK); | |
318 | dev_info(&ndev->dev, "Promiscuous mode enabled.\n"); | |
4cd24eaf | 319 | } else if (!netdev_mc_empty(ndev)) { |
22bedad3 | 320 | struct netdev_hw_addr *ha; |
92744989 | 321 | |
f9dcbcc9 | 322 | i = 0; |
22bedad3 | 323 | netdev_for_each_mc_addr(ha, ndev) { |
92744989 GL |
324 | if (i >= MULTICAST_CAM_TABLE_NUM) |
325 | break; | |
22bedad3 JP |
326 | multi_addr_msw = ((ha->addr[3] << 24) | |
327 | (ha->addr[2] << 16) | | |
328 | (ha->addr[1] << 8) | | |
329 | (ha->addr[0])); | |
92744989 GL |
330 | temac_indirect_out32(lp, XTE_MAW0_OFFSET, |
331 | multi_addr_msw); | |
22bedad3 JP |
332 | multi_addr_lsw = ((ha->addr[5] << 8) | |
333 | (ha->addr[4]) | (i << 16)); | |
92744989 GL |
334 | temac_indirect_out32(lp, XTE_MAW1_OFFSET, |
335 | multi_addr_lsw); | |
f9dcbcc9 | 336 | i++; |
92744989 GL |
337 | } |
338 | } else { | |
339 | val = temac_indirect_in32(lp, XTE_AFM_OFFSET); | |
340 | temac_indirect_out32(lp, XTE_AFM_OFFSET, | |
341 | val & ~XTE_AFM_EPPRM_MASK); | |
342 | temac_indirect_out32(lp, XTE_MAW0_OFFSET, 0); | |
343 | temac_indirect_out32(lp, XTE_MAW1_OFFSET, 0); | |
344 | dev_info(&ndev->dev, "Promiscuous mode disabled.\n"); | |
345 | } | |
346 | mutex_unlock(&lp->indirect_mutex); | |
347 | } | |
348 | ||
349 | struct temac_option { | |
350 | int flg; | |
351 | u32 opt; | |
352 | u32 reg; | |
353 | u32 m_or; | |
354 | u32 m_and; | |
355 | } temac_options[] = { | |
356 | /* Turn on jumbo packet support for both Rx and Tx */ | |
357 | { | |
358 | .opt = XTE_OPTION_JUMBO, | |
359 | .reg = XTE_TXC_OFFSET, | |
360 | .m_or = XTE_TXC_TXJMBO_MASK, | |
361 | }, | |
362 | { | |
363 | .opt = XTE_OPTION_JUMBO, | |
364 | .reg = XTE_RXC1_OFFSET, | |
365 | .m_or =XTE_RXC1_RXJMBO_MASK, | |
366 | }, | |
367 | /* Turn on VLAN packet support for both Rx and Tx */ | |
368 | { | |
369 | .opt = XTE_OPTION_VLAN, | |
370 | .reg = XTE_TXC_OFFSET, | |
371 | .m_or =XTE_TXC_TXVLAN_MASK, | |
372 | }, | |
373 | { | |
374 | .opt = XTE_OPTION_VLAN, | |
375 | .reg = XTE_RXC1_OFFSET, | |
376 | .m_or =XTE_RXC1_RXVLAN_MASK, | |
377 | }, | |
378 | /* Turn on FCS stripping on receive packets */ | |
379 | { | |
380 | .opt = XTE_OPTION_FCS_STRIP, | |
381 | .reg = XTE_RXC1_OFFSET, | |
382 | .m_or =XTE_RXC1_RXFCS_MASK, | |
383 | }, | |
384 | /* Turn on FCS insertion on transmit packets */ | |
385 | { | |
386 | .opt = XTE_OPTION_FCS_INSERT, | |
387 | .reg = XTE_TXC_OFFSET, | |
388 | .m_or =XTE_TXC_TXFCS_MASK, | |
389 | }, | |
390 | /* Turn on length/type field checking on receive packets */ | |
391 | { | |
392 | .opt = XTE_OPTION_LENTYPE_ERR, | |
393 | .reg = XTE_RXC1_OFFSET, | |
394 | .m_or =XTE_RXC1_RXLT_MASK, | |
395 | }, | |
396 | /* Turn on flow control */ | |
397 | { | |
398 | .opt = XTE_OPTION_FLOW_CONTROL, | |
399 | .reg = XTE_FCC_OFFSET, | |
400 | .m_or =XTE_FCC_RXFLO_MASK, | |
401 | }, | |
402 | /* Turn on flow control */ | |
403 | { | |
404 | .opt = XTE_OPTION_FLOW_CONTROL, | |
405 | .reg = XTE_FCC_OFFSET, | |
406 | .m_or =XTE_FCC_TXFLO_MASK, | |
407 | }, | |
408 | /* Turn on promiscuous frame filtering (all frames are received ) */ | |
409 | { | |
410 | .opt = XTE_OPTION_PROMISC, | |
411 | .reg = XTE_AFM_OFFSET, | |
412 | .m_or =XTE_AFM_EPPRM_MASK, | |
413 | }, | |
414 | /* Enable transmitter if not already enabled */ | |
415 | { | |
416 | .opt = XTE_OPTION_TXEN, | |
417 | .reg = XTE_TXC_OFFSET, | |
418 | .m_or =XTE_TXC_TXEN_MASK, | |
419 | }, | |
420 | /* Enable receiver? */ | |
421 | { | |
422 | .opt = XTE_OPTION_RXEN, | |
423 | .reg = XTE_RXC1_OFFSET, | |
424 | .m_or =XTE_RXC1_RXEN_MASK, | |
425 | }, | |
426 | {} | |
427 | }; | |
428 | ||
429 | /** | |
430 | * temac_setoptions | |
431 | */ | |
432 | static u32 temac_setoptions(struct net_device *ndev, u32 options) | |
433 | { | |
434 | struct temac_local *lp = netdev_priv(ndev); | |
435 | struct temac_option *tp = &temac_options[0]; | |
436 | int reg; | |
437 | ||
438 | mutex_lock(&lp->indirect_mutex); | |
439 | while (tp->opt) { | |
440 | reg = temac_indirect_in32(lp, tp->reg) & ~tp->m_or; | |
441 | if (options & tp->opt) | |
442 | reg |= tp->m_or; | |
443 | temac_indirect_out32(lp, tp->reg, reg); | |
444 | tp++; | |
445 | } | |
446 | lp->options |= options; | |
447 | mutex_unlock(&lp->indirect_mutex); | |
448 | ||
449 | return (0); | |
450 | } | |
451 | ||
452 | /* Initilize temac */ | |
453 | static void temac_device_reset(struct net_device *ndev) | |
454 | { | |
455 | struct temac_local *lp = netdev_priv(ndev); | |
456 | u32 timeout; | |
457 | u32 val; | |
458 | ||
459 | /* Perform a software reset */ | |
460 | ||
461 | /* 0x300 host enable bit ? */ | |
462 | /* reset PHY through control register ?:1 */ | |
463 | ||
464 | dev_dbg(&ndev->dev, "%s()\n", __func__); | |
465 | ||
466 | mutex_lock(&lp->indirect_mutex); | |
467 | /* Reset the receiver and wait for it to finish reset */ | |
468 | temac_indirect_out32(lp, XTE_RXC1_OFFSET, XTE_RXC1_RXRST_MASK); | |
469 | timeout = 1000; | |
470 | while (temac_indirect_in32(lp, XTE_RXC1_OFFSET) & XTE_RXC1_RXRST_MASK) { | |
471 | udelay(1); | |
472 | if (--timeout == 0) { | |
473 | dev_err(&ndev->dev, | |
474 | "temac_device_reset RX reset timeout!!\n"); | |
475 | break; | |
476 | } | |
477 | } | |
478 | ||
479 | /* Reset the transmitter and wait for it to finish reset */ | |
480 | temac_indirect_out32(lp, XTE_TXC_OFFSET, XTE_TXC_TXRST_MASK); | |
481 | timeout = 1000; | |
482 | while (temac_indirect_in32(lp, XTE_TXC_OFFSET) & XTE_TXC_TXRST_MASK) { | |
483 | udelay(1); | |
484 | if (--timeout == 0) { | |
485 | dev_err(&ndev->dev, | |
486 | "temac_device_reset TX reset timeout!!\n"); | |
487 | break; | |
488 | } | |
489 | } | |
490 | ||
491 | /* Disable the receiver */ | |
492 | val = temac_indirect_in32(lp, XTE_RXC1_OFFSET); | |
493 | temac_indirect_out32(lp, XTE_RXC1_OFFSET, val & ~XTE_RXC1_RXEN_MASK); | |
494 | ||
495 | /* Reset Local Link (DMA) */ | |
e44171f1 | 496 | lp->dma_out(lp, DMA_CONTROL_REG, DMA_CONTROL_RST); |
92744989 | 497 | timeout = 1000; |
e44171f1 | 498 | while (lp->dma_in(lp, DMA_CONTROL_REG) & DMA_CONTROL_RST) { |
92744989 GL |
499 | udelay(1); |
500 | if (--timeout == 0) { | |
501 | dev_err(&ndev->dev, | |
502 | "temac_device_reset DMA reset timeout!!\n"); | |
503 | break; | |
504 | } | |
505 | } | |
e44171f1 | 506 | lp->dma_out(lp, DMA_CONTROL_REG, DMA_TAIL_ENABLE); |
92744989 GL |
507 | |
508 | temac_dma_bd_init(ndev); | |
509 | ||
510 | temac_indirect_out32(lp, XTE_RXC0_OFFSET, 0); | |
511 | temac_indirect_out32(lp, XTE_RXC1_OFFSET, 0); | |
512 | temac_indirect_out32(lp, XTE_TXC_OFFSET, 0); | |
513 | temac_indirect_out32(lp, XTE_FCC_OFFSET, XTE_FCC_RXFLO_MASK); | |
514 | ||
515 | mutex_unlock(&lp->indirect_mutex); | |
516 | ||
517 | /* Sync default options with HW | |
518 | * but leave receiver and transmitter disabled. */ | |
519 | temac_setoptions(ndev, | |
520 | lp->options & ~(XTE_OPTION_TXEN | XTE_OPTION_RXEN)); | |
521 | ||
522 | temac_set_mac_address(ndev, NULL); | |
523 | ||
524 | /* Set address filter table */ | |
525 | temac_set_multicast_list(ndev); | |
526 | if (temac_setoptions(ndev, lp->options)) | |
527 | dev_err(&ndev->dev, "Error setting TEMAC options\n"); | |
528 | ||
529 | /* Init Driver variable */ | |
1ae5dc34 | 530 | ndev->trans_start = jiffies; /* prevent tx timeout */ |
92744989 GL |
531 | } |
532 | ||
533 | void temac_adjust_link(struct net_device *ndev) | |
534 | { | |
535 | struct temac_local *lp = netdev_priv(ndev); | |
536 | struct phy_device *phy = lp->phy_dev; | |
537 | u32 mii_speed; | |
538 | int link_state; | |
539 | ||
540 | /* hash together the state values to decide if something has changed */ | |
541 | link_state = phy->speed | (phy->duplex << 1) | phy->link; | |
542 | ||
543 | mutex_lock(&lp->indirect_mutex); | |
544 | if (lp->last_link != link_state) { | |
545 | mii_speed = temac_indirect_in32(lp, XTE_EMCFG_OFFSET); | |
546 | mii_speed &= ~XTE_EMCFG_LINKSPD_MASK; | |
547 | ||
548 | switch (phy->speed) { | |
549 | case SPEED_1000: mii_speed |= XTE_EMCFG_LINKSPD_1000; break; | |
550 | case SPEED_100: mii_speed |= XTE_EMCFG_LINKSPD_100; break; | |
551 | case SPEED_10: mii_speed |= XTE_EMCFG_LINKSPD_10; break; | |
552 | } | |
553 | ||
554 | /* Write new speed setting out to TEMAC */ | |
555 | temac_indirect_out32(lp, XTE_EMCFG_OFFSET, mii_speed); | |
556 | lp->last_link = link_state; | |
557 | phy_print_status(phy); | |
558 | } | |
559 | mutex_unlock(&lp->indirect_mutex); | |
560 | } | |
561 | ||
562 | static void temac_start_xmit_done(struct net_device *ndev) | |
563 | { | |
564 | struct temac_local *lp = netdev_priv(ndev); | |
565 | struct cdmac_bd *cur_p; | |
566 | unsigned int stat = 0; | |
567 | ||
568 | cur_p = &lp->tx_bd_v[lp->tx_bd_ci]; | |
569 | stat = cur_p->app0; | |
570 | ||
571 | while (stat & STS_CTRL_APP0_CMPLT) { | |
572 | dma_unmap_single(ndev->dev.parent, cur_p->phys, cur_p->len, | |
573 | DMA_TO_DEVICE); | |
574 | if (cur_p->app4) | |
575 | dev_kfree_skb_irq((struct sk_buff *)cur_p->app4); | |
576 | cur_p->app0 = 0; | |
23ecc4bd BH |
577 | cur_p->app1 = 0; |
578 | cur_p->app2 = 0; | |
579 | cur_p->app3 = 0; | |
580 | cur_p->app4 = 0; | |
92744989 GL |
581 | |
582 | ndev->stats.tx_packets++; | |
583 | ndev->stats.tx_bytes += cur_p->len; | |
584 | ||
585 | lp->tx_bd_ci++; | |
586 | if (lp->tx_bd_ci >= TX_BD_NUM) | |
587 | lp->tx_bd_ci = 0; | |
588 | ||
589 | cur_p = &lp->tx_bd_v[lp->tx_bd_ci]; | |
590 | stat = cur_p->app0; | |
591 | } | |
592 | ||
593 | netif_wake_queue(ndev); | |
594 | } | |
595 | ||
23ecc4bd BH |
596 | static inline int temac_check_tx_bd_space(struct temac_local *lp, int num_frag) |
597 | { | |
598 | struct cdmac_bd *cur_p; | |
599 | int tail; | |
600 | ||
601 | tail = lp->tx_bd_tail; | |
602 | cur_p = &lp->tx_bd_v[tail]; | |
603 | ||
604 | do { | |
605 | if (cur_p->app0) | |
606 | return NETDEV_TX_BUSY; | |
607 | ||
608 | tail++; | |
609 | if (tail >= TX_BD_NUM) | |
610 | tail = 0; | |
611 | ||
612 | cur_p = &lp->tx_bd_v[tail]; | |
613 | num_frag--; | |
614 | } while (num_frag >= 0); | |
615 | ||
616 | return 0; | |
617 | } | |
618 | ||
92744989 GL |
619 | static int temac_start_xmit(struct sk_buff *skb, struct net_device *ndev) |
620 | { | |
621 | struct temac_local *lp = netdev_priv(ndev); | |
622 | struct cdmac_bd *cur_p; | |
623 | dma_addr_t start_p, tail_p; | |
624 | int ii; | |
625 | unsigned long num_frag; | |
626 | skb_frag_t *frag; | |
627 | ||
628 | num_frag = skb_shinfo(skb)->nr_frags; | |
629 | frag = &skb_shinfo(skb)->frags[0]; | |
630 | start_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail; | |
631 | cur_p = &lp->tx_bd_v[lp->tx_bd_tail]; | |
632 | ||
23ecc4bd | 633 | if (temac_check_tx_bd_space(lp, num_frag)) { |
92744989 GL |
634 | if (!netif_queue_stopped(ndev)) { |
635 | netif_stop_queue(ndev); | |
636 | return NETDEV_TX_BUSY; | |
637 | } | |
638 | return NETDEV_TX_BUSY; | |
639 | } | |
640 | ||
641 | cur_p->app0 = 0; | |
642 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
23ecc4bd BH |
643 | unsigned int csum_start_off = skb_transport_offset(skb); |
644 | unsigned int csum_index_off = csum_start_off + skb->csum_offset; | |
645 | ||
646 | cur_p->app0 |= 1; /* TX Checksum Enabled */ | |
647 | cur_p->app1 = (csum_start_off << 16) | csum_index_off; | |
648 | cur_p->app2 = 0; /* initial checksum seed */ | |
92744989 | 649 | } |
23ecc4bd | 650 | |
92744989 GL |
651 | cur_p->app0 |= STS_CTRL_APP0_SOP; |
652 | cur_p->len = skb_headlen(skb); | |
653 | cur_p->phys = dma_map_single(ndev->dev.parent, skb->data, skb->len, | |
654 | DMA_TO_DEVICE); | |
655 | cur_p->app4 = (unsigned long)skb; | |
656 | ||
657 | for (ii = 0; ii < num_frag; ii++) { | |
658 | lp->tx_bd_tail++; | |
659 | if (lp->tx_bd_tail >= TX_BD_NUM) | |
660 | lp->tx_bd_tail = 0; | |
661 | ||
662 | cur_p = &lp->tx_bd_v[lp->tx_bd_tail]; | |
663 | cur_p->phys = dma_map_single(ndev->dev.parent, | |
664 | (void *)page_address(frag->page) + | |
665 | frag->page_offset, | |
666 | frag->size, DMA_TO_DEVICE); | |
667 | cur_p->len = frag->size; | |
668 | cur_p->app0 = 0; | |
669 | frag++; | |
670 | } | |
671 | cur_p->app0 |= STS_CTRL_APP0_EOP; | |
672 | ||
673 | tail_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail; | |
674 | lp->tx_bd_tail++; | |
675 | if (lp->tx_bd_tail >= TX_BD_NUM) | |
676 | lp->tx_bd_tail = 0; | |
677 | ||
678 | /* Kick off the transfer */ | |
e44171f1 | 679 | lp->dma_out(lp, TX_TAILDESC_PTR, tail_p); /* DMA start */ |
92744989 | 680 | |
6ed10654 | 681 | return NETDEV_TX_OK; |
92744989 GL |
682 | } |
683 | ||
684 | ||
685 | static void ll_temac_recv(struct net_device *ndev) | |
686 | { | |
687 | struct temac_local *lp = netdev_priv(ndev); | |
688 | struct sk_buff *skb, *new_skb; | |
689 | unsigned int bdstat; | |
690 | struct cdmac_bd *cur_p; | |
691 | dma_addr_t tail_p; | |
692 | int length; | |
92744989 GL |
693 | unsigned long flags; |
694 | ||
695 | spin_lock_irqsave(&lp->rx_lock, flags); | |
696 | ||
697 | tail_p = lp->rx_bd_p + sizeof(*lp->rx_bd_v) * lp->rx_bd_ci; | |
698 | cur_p = &lp->rx_bd_v[lp->rx_bd_ci]; | |
699 | ||
700 | bdstat = cur_p->app0; | |
701 | while ((bdstat & STS_CTRL_APP0_CMPLT)) { | |
702 | ||
703 | skb = lp->rx_skb[lp->rx_bd_ci]; | |
c3b7c12c | 704 | length = cur_p->app4 & 0x3FFF; |
92744989 | 705 | |
33646d7f | 706 | dma_unmap_single(ndev->dev.parent, cur_p->phys, length, |
92744989 GL |
707 | DMA_FROM_DEVICE); |
708 | ||
709 | skb_put(skb, length); | |
710 | skb->dev = ndev; | |
711 | skb->protocol = eth_type_trans(skb, ndev); | |
712 | skb->ip_summed = CHECKSUM_NONE; | |
713 | ||
23ecc4bd BH |
714 | /* if we're doing rx csum offload, set it up */ |
715 | if (((lp->temac_features & TEMAC_FEATURE_RX_CSUM) != 0) && | |
716 | (skb->protocol == __constant_htons(ETH_P_IP)) && | |
717 | (skb->len > 64)) { | |
718 | ||
719 | skb->csum = cur_p->app3 & 0xFFFF; | |
720 | skb->ip_summed = CHECKSUM_COMPLETE; | |
721 | } | |
722 | ||
92744989 GL |
723 | netif_rx(skb); |
724 | ||
725 | ndev->stats.rx_packets++; | |
726 | ndev->stats.rx_bytes += length; | |
727 | ||
e44171f1 JL |
728 | new_skb = netdev_alloc_skb_ip_align(ndev, |
729 | XTE_MAX_JUMBO_FRAME_SIZE); | |
730 | ||
92744989 GL |
731 | if (new_skb == 0) { |
732 | dev_err(&ndev->dev, "no memory for new sk_buff\n"); | |
733 | spin_unlock_irqrestore(&lp->rx_lock, flags); | |
734 | return; | |
735 | } | |
736 | ||
92744989 GL |
737 | cur_p->app0 = STS_CTRL_APP0_IRQONEND; |
738 | cur_p->phys = dma_map_single(ndev->dev.parent, new_skb->data, | |
739 | XTE_MAX_JUMBO_FRAME_SIZE, | |
740 | DMA_FROM_DEVICE); | |
741 | cur_p->len = XTE_MAX_JUMBO_FRAME_SIZE; | |
742 | lp->rx_skb[lp->rx_bd_ci] = new_skb; | |
743 | ||
744 | lp->rx_bd_ci++; | |
745 | if (lp->rx_bd_ci >= RX_BD_NUM) | |
746 | lp->rx_bd_ci = 0; | |
747 | ||
748 | cur_p = &lp->rx_bd_v[lp->rx_bd_ci]; | |
749 | bdstat = cur_p->app0; | |
750 | } | |
e44171f1 | 751 | lp->dma_out(lp, RX_TAILDESC_PTR, tail_p); |
92744989 GL |
752 | |
753 | spin_unlock_irqrestore(&lp->rx_lock, flags); | |
754 | } | |
755 | ||
756 | static irqreturn_t ll_temac_tx_irq(int irq, void *_ndev) | |
757 | { | |
758 | struct net_device *ndev = _ndev; | |
759 | struct temac_local *lp = netdev_priv(ndev); | |
760 | unsigned int status; | |
761 | ||
e44171f1 JL |
762 | status = lp->dma_in(lp, TX_IRQ_REG); |
763 | lp->dma_out(lp, TX_IRQ_REG, status); | |
92744989 GL |
764 | |
765 | if (status & (IRQ_COAL | IRQ_DLY)) | |
766 | temac_start_xmit_done(lp->ndev); | |
767 | if (status & 0x080) | |
768 | dev_err(&ndev->dev, "DMA error 0x%x\n", status); | |
769 | ||
770 | return IRQ_HANDLED; | |
771 | } | |
772 | ||
773 | static irqreturn_t ll_temac_rx_irq(int irq, void *_ndev) | |
774 | { | |
775 | struct net_device *ndev = _ndev; | |
776 | struct temac_local *lp = netdev_priv(ndev); | |
777 | unsigned int status; | |
778 | ||
779 | /* Read and clear the status registers */ | |
e44171f1 JL |
780 | status = lp->dma_in(lp, RX_IRQ_REG); |
781 | lp->dma_out(lp, RX_IRQ_REG, status); | |
92744989 GL |
782 | |
783 | if (status & (IRQ_COAL | IRQ_DLY)) | |
784 | ll_temac_recv(lp->ndev); | |
785 | ||
786 | return IRQ_HANDLED; | |
787 | } | |
788 | ||
789 | static int temac_open(struct net_device *ndev) | |
790 | { | |
791 | struct temac_local *lp = netdev_priv(ndev); | |
792 | int rc; | |
793 | ||
794 | dev_dbg(&ndev->dev, "temac_open()\n"); | |
795 | ||
796 | if (lp->phy_node) { | |
797 | lp->phy_dev = of_phy_connect(lp->ndev, lp->phy_node, | |
798 | temac_adjust_link, 0, 0); | |
799 | if (!lp->phy_dev) { | |
800 | dev_err(lp->dev, "of_phy_connect() failed\n"); | |
801 | return -ENODEV; | |
802 | } | |
803 | ||
804 | phy_start(lp->phy_dev); | |
805 | } | |
806 | ||
807 | rc = request_irq(lp->tx_irq, ll_temac_tx_irq, 0, ndev->name, ndev); | |
808 | if (rc) | |
809 | goto err_tx_irq; | |
810 | rc = request_irq(lp->rx_irq, ll_temac_rx_irq, 0, ndev->name, ndev); | |
811 | if (rc) | |
812 | goto err_rx_irq; | |
813 | ||
814 | temac_device_reset(ndev); | |
815 | return 0; | |
816 | ||
817 | err_rx_irq: | |
818 | free_irq(lp->tx_irq, ndev); | |
819 | err_tx_irq: | |
820 | if (lp->phy_dev) | |
821 | phy_disconnect(lp->phy_dev); | |
822 | lp->phy_dev = NULL; | |
823 | dev_err(lp->dev, "request_irq() failed\n"); | |
824 | return rc; | |
825 | } | |
826 | ||
827 | static int temac_stop(struct net_device *ndev) | |
828 | { | |
829 | struct temac_local *lp = netdev_priv(ndev); | |
830 | ||
831 | dev_dbg(&ndev->dev, "temac_close()\n"); | |
832 | ||
833 | free_irq(lp->tx_irq, ndev); | |
834 | free_irq(lp->rx_irq, ndev); | |
835 | ||
836 | if (lp->phy_dev) | |
837 | phy_disconnect(lp->phy_dev); | |
838 | lp->phy_dev = NULL; | |
839 | ||
840 | return 0; | |
841 | } | |
842 | ||
843 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
844 | static void | |
845 | temac_poll_controller(struct net_device *ndev) | |
846 | { | |
847 | struct temac_local *lp = netdev_priv(ndev); | |
848 | ||
849 | disable_irq(lp->tx_irq); | |
850 | disable_irq(lp->rx_irq); | |
851 | ||
852 | ll_temac_rx_irq(lp->tx_irq, lp); | |
853 | ll_temac_tx_irq(lp->rx_irq, lp); | |
854 | ||
855 | enable_irq(lp->tx_irq); | |
856 | enable_irq(lp->rx_irq); | |
857 | } | |
858 | #endif | |
859 | ||
860 | static const struct net_device_ops temac_netdev_ops = { | |
861 | .ndo_open = temac_open, | |
862 | .ndo_stop = temac_stop, | |
863 | .ndo_start_xmit = temac_start_xmit, | |
8ea7a37c | 864 | .ndo_set_mac_address = netdev_set_mac_address, |
92744989 GL |
865 | //.ndo_set_multicast_list = temac_set_multicast_list, |
866 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
867 | .ndo_poll_controller = temac_poll_controller, | |
868 | #endif | |
869 | }; | |
870 | ||
871 | /* --------------------------------------------------------------------- | |
872 | * SYSFS device attributes | |
873 | */ | |
874 | static ssize_t temac_show_llink_regs(struct device *dev, | |
875 | struct device_attribute *attr, char *buf) | |
876 | { | |
877 | struct net_device *ndev = dev_get_drvdata(dev); | |
878 | struct temac_local *lp = netdev_priv(ndev); | |
879 | int i, len = 0; | |
880 | ||
881 | for (i = 0; i < 0x11; i++) | |
e44171f1 | 882 | len += sprintf(buf + len, "%.8x%s", lp->dma_in(lp, i), |
92744989 GL |
883 | (i % 8) == 7 ? "\n" : " "); |
884 | len += sprintf(buf + len, "\n"); | |
885 | ||
886 | return len; | |
887 | } | |
888 | ||
889 | static DEVICE_ATTR(llink_regs, 0440, temac_show_llink_regs, NULL); | |
890 | ||
891 | static struct attribute *temac_device_attrs[] = { | |
892 | &dev_attr_llink_regs.attr, | |
893 | NULL, | |
894 | }; | |
895 | ||
896 | static const struct attribute_group temac_attr_group = { | |
897 | .attrs = temac_device_attrs, | |
898 | }; | |
899 | ||
900 | static int __init | |
901 | temac_of_probe(struct of_device *op, const struct of_device_id *match) | |
902 | { | |
903 | struct device_node *np; | |
904 | struct temac_local *lp; | |
905 | struct net_device *ndev; | |
906 | const void *addr; | |
23ecc4bd | 907 | __be32 *p; |
92744989 | 908 | int size, rc = 0; |
92744989 GL |
909 | |
910 | /* Init network device structure */ | |
911 | ndev = alloc_etherdev(sizeof(*lp)); | |
912 | if (!ndev) { | |
913 | dev_err(&op->dev, "could not allocate device.\n"); | |
914 | return -ENOMEM; | |
915 | } | |
916 | ether_setup(ndev); | |
917 | dev_set_drvdata(&op->dev, ndev); | |
918 | SET_NETDEV_DEV(ndev, &op->dev); | |
919 | ndev->flags &= ~IFF_MULTICAST; /* clear multicast */ | |
920 | ndev->features = NETIF_F_SG | NETIF_F_FRAGLIST; | |
921 | ndev->netdev_ops = &temac_netdev_ops; | |
922 | #if 0 | |
923 | ndev->features |= NETIF_F_IP_CSUM; /* Can checksum TCP/UDP over IPv4. */ | |
924 | ndev->features |= NETIF_F_HW_CSUM; /* Can checksum all the packets. */ | |
925 | ndev->features |= NETIF_F_IPV6_CSUM; /* Can checksum IPV6 TCP/UDP */ | |
926 | ndev->features |= NETIF_F_HIGHDMA; /* Can DMA to high memory. */ | |
927 | ndev->features |= NETIF_F_HW_VLAN_TX; /* Transmit VLAN hw accel */ | |
928 | ndev->features |= NETIF_F_HW_VLAN_RX; /* Receive VLAN hw acceleration */ | |
929 | ndev->features |= NETIF_F_HW_VLAN_FILTER; /* Receive VLAN filtering */ | |
930 | ndev->features |= NETIF_F_VLAN_CHALLENGED; /* cannot handle VLAN pkts */ | |
931 | ndev->features |= NETIF_F_GSO; /* Enable software GSO. */ | |
932 | ndev->features |= NETIF_F_MULTI_QUEUE; /* Has multiple TX/RX queues */ | |
933 | ndev->features |= NETIF_F_LRO; /* large receive offload */ | |
934 | #endif | |
935 | ||
936 | /* setup temac private info structure */ | |
937 | lp = netdev_priv(ndev); | |
938 | lp->ndev = ndev; | |
939 | lp->dev = &op->dev; | |
940 | lp->options = XTE_OPTION_DEFAULTS; | |
941 | spin_lock_init(&lp->rx_lock); | |
942 | mutex_init(&lp->indirect_mutex); | |
943 | ||
944 | /* map device registers */ | |
61c7a080 | 945 | lp->regs = of_iomap(op->dev.of_node, 0); |
92744989 GL |
946 | if (!lp->regs) { |
947 | dev_err(&op->dev, "could not map temac regs.\n"); | |
948 | goto nodev; | |
949 | } | |
950 | ||
23ecc4bd BH |
951 | /* Setup checksum offload, but default to off if not specified */ |
952 | lp->temac_features = 0; | |
953 | p = (__be32 *)of_get_property(op->dev.of_node, "xlnx,txcsum", NULL); | |
954 | if (p && be32_to_cpu(*p)) { | |
955 | lp->temac_features |= TEMAC_FEATURE_TX_CSUM; | |
956 | /* Can checksum TCP/UDP over IPv4. */ | |
957 | ndev->features |= NETIF_F_IP_CSUM; | |
958 | } | |
959 | p = (__be32 *)of_get_property(op->dev.of_node, "xlnx,rxcsum", NULL); | |
960 | if (p && be32_to_cpu(*p)) | |
961 | lp->temac_features |= TEMAC_FEATURE_RX_CSUM; | |
962 | ||
92744989 | 963 | /* Find the DMA node, map the DMA registers, and decode the DMA IRQs */ |
61c7a080 | 964 | np = of_parse_phandle(op->dev.of_node, "llink-connected", 0); |
92744989 GL |
965 | if (!np) { |
966 | dev_err(&op->dev, "could not find DMA node\n"); | |
967 | goto nodev; | |
968 | } | |
969 | ||
e44171f1 JL |
970 | /* Setup the DMA register accesses, could be DCR or memory mapped */ |
971 | if (temac_dcr_setup(lp, op, np)) { | |
972 | ||
973 | /* no DCR in the device tree, try non-DCR */ | |
974 | lp->sdma_regs = of_iomap(np, 0); | |
975 | if (lp->sdma_regs) { | |
976 | lp->dma_in = temac_dma_in32; | |
977 | lp->dma_out = temac_dma_out32; | |
978 | dev_dbg(&op->dev, "MEM base: %p\n", lp->sdma_regs); | |
979 | } else { | |
980 | dev_err(&op->dev, "unable to map DMA registers\n"); | |
981 | goto nodev; | |
982 | } | |
92744989 | 983 | } |
92744989 GL |
984 | |
985 | lp->rx_irq = irq_of_parse_and_map(np, 0); | |
986 | lp->tx_irq = irq_of_parse_and_map(np, 1); | |
755fae0a | 987 | if ((lp->rx_irq == NO_IRQ) || (lp->tx_irq == NO_IRQ)) { |
92744989 GL |
988 | dev_err(&op->dev, "could not determine irqs\n"); |
989 | rc = -ENOMEM; | |
990 | goto nodev; | |
991 | } | |
992 | ||
993 | of_node_put(np); /* Finished with the DMA node; drop the reference */ | |
994 | ||
995 | /* Retrieve the MAC address */ | |
61c7a080 | 996 | addr = of_get_property(op->dev.of_node, "local-mac-address", &size); |
92744989 GL |
997 | if ((!addr) || (size != 6)) { |
998 | dev_err(&op->dev, "could not find MAC address\n"); | |
999 | rc = -ENODEV; | |
1000 | goto nodev; | |
1001 | } | |
1002 | temac_set_mac_address(ndev, (void *)addr); | |
1003 | ||
61c7a080 | 1004 | rc = temac_mdio_setup(lp, op->dev.of_node); |
92744989 GL |
1005 | if (rc) |
1006 | dev_warn(&op->dev, "error registering MDIO bus\n"); | |
1007 | ||
61c7a080 | 1008 | lp->phy_node = of_parse_phandle(op->dev.of_node, "phy-handle", 0); |
92744989 GL |
1009 | if (lp->phy_node) |
1010 | dev_dbg(lp->dev, "using PHY node %s (%p)\n", np->full_name, np); | |
1011 | ||
1012 | /* Add the device attributes */ | |
1013 | rc = sysfs_create_group(&lp->dev->kobj, &temac_attr_group); | |
1014 | if (rc) { | |
1015 | dev_err(lp->dev, "Error creating sysfs files\n"); | |
1016 | goto nodev; | |
1017 | } | |
1018 | ||
1019 | rc = register_netdev(lp->ndev); | |
1020 | if (rc) { | |
1021 | dev_err(lp->dev, "register_netdev() error (%i)\n", rc); | |
1022 | goto err_register_ndev; | |
1023 | } | |
1024 | ||
1025 | return 0; | |
1026 | ||
1027 | err_register_ndev: | |
1028 | sysfs_remove_group(&lp->dev->kobj, &temac_attr_group); | |
1029 | nodev: | |
1030 | free_netdev(ndev); | |
1031 | ndev = NULL; | |
1032 | return rc; | |
1033 | } | |
1034 | ||
1035 | static int __devexit temac_of_remove(struct of_device *op) | |
1036 | { | |
1037 | struct net_device *ndev = dev_get_drvdata(&op->dev); | |
1038 | struct temac_local *lp = netdev_priv(ndev); | |
1039 | ||
1040 | temac_mdio_teardown(lp); | |
1041 | unregister_netdev(ndev); | |
1042 | sysfs_remove_group(&lp->dev->kobj, &temac_attr_group); | |
1043 | if (lp->phy_node) | |
1044 | of_node_put(lp->phy_node); | |
1045 | lp->phy_node = NULL; | |
1046 | dev_set_drvdata(&op->dev, NULL); | |
1047 | free_netdev(ndev); | |
1048 | return 0; | |
1049 | } | |
1050 | ||
1051 | static struct of_device_id temac_of_match[] __devinitdata = { | |
1052 | { .compatible = "xlnx,xps-ll-temac-1.01.b", }, | |
c3b7c12c SM |
1053 | { .compatible = "xlnx,xps-ll-temac-2.00.a", }, |
1054 | { .compatible = "xlnx,xps-ll-temac-2.02.a", }, | |
1055 | { .compatible = "xlnx,xps-ll-temac-2.03.a", }, | |
92744989 GL |
1056 | {}, |
1057 | }; | |
1058 | MODULE_DEVICE_TABLE(of, temac_of_match); | |
1059 | ||
1060 | static struct of_platform_driver temac_of_driver = { | |
92744989 GL |
1061 | .probe = temac_of_probe, |
1062 | .remove = __devexit_p(temac_of_remove), | |
1063 | .driver = { | |
1064 | .owner = THIS_MODULE, | |
1065 | .name = "xilinx_temac", | |
4018294b | 1066 | .of_match_table = temac_of_match, |
92744989 GL |
1067 | }, |
1068 | }; | |
1069 | ||
1070 | static int __init temac_init(void) | |
1071 | { | |
1072 | return of_register_platform_driver(&temac_of_driver); | |
1073 | } | |
1074 | module_init(temac_init); | |
1075 | ||
1076 | static void __exit temac_exit(void) | |
1077 | { | |
1078 | of_unregister_platform_driver(&temac_of_driver); | |
1079 | } | |
1080 | module_exit(temac_exit); | |
1081 | ||
1082 | MODULE_DESCRIPTION("Xilinx LL_TEMAC Ethernet driver"); | |
1083 | MODULE_AUTHOR("Yoshio Kashiwagi"); | |
1084 | MODULE_LICENSE("GPL"); |