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92744989
GL		 1/*
2 * Driver for Xilinx TEMAC Ethernet device
3 *
4 * Copyright (c) 2008 Nissin Systems Co., Ltd., Yoshio Kashiwagi
5 * Copyright (c) 2005-2008 DLA Systems, David H. Lynch Jr. <dhlii@dlasys.net>
6 * Copyright (c) 2008-2009 Secret Lab Technologies Ltd.
7 *
8 * This is a driver for the Xilinx ll_temac ipcore which is often used
9 * in the Virtex and Spartan series of chips.
10 *
11 * Notes:
12 * - The ll_temac hardware uses indirect access for many of the TEMAC
13 * registers, include the MDIO bus. However, indirect access to MDIO
14 * registers take considerably more clock cycles than to TEMAC registers.
15 * MDIO accesses are long, so threads doing them should probably sleep
16 * rather than busywait. However, since only one indirect access can be
17 * in progress at any given time, that means that *all* indirect accesses
18 * could end up sleeping (to wait for an MDIO access to complete).
19 * Fortunately none of the indirect accesses are on the 'hot' path for tx
20 * or rx, so this should be okay.
21 *
22 * TODO:
92744989
GL		 23 * - Factor out locallink DMA code into separate driver
24 * - Fix multicast assignment.
25 * - Fix support for hardware checksumming.
26 * - Testing. Lots and lots of testing.
27 *
28 */
29
30#include <linux/delay.h>
31#include <linux/etherdevice.h>
32#include <linux/init.h>
33#include <linux/mii.h>
34#include <linux/module.h>
35#include <linux/mutex.h>
36#include <linux/netdevice.h>
37#include <linux/of.h>
38#include <linux/of_device.h>
39#include <linux/of_mdio.h>
40#include <linux/of_platform.h>
9f1a1fca 41#include <linux/of_address.h>
92744989
GL		 42#include <linux/skbuff.h>
43#include <linux/spinlock.h>
44#include <linux/tcp.h> /* needed for sizeof(tcphdr) */
45#include <linux/udp.h> /* needed for sizeof(udphdr) */
46#include <linux/phy.h>
47#include <linux/in.h>
48#include <linux/io.h>
49#include <linux/ip.h>
5a0e3ad6 50#include <linux/slab.h>
ffbc03bc 51#include <linux/interrupt.h>
92744989
GL		 52
53#include "ll_temac.h"
54
55#define TX_BD_NUM 64
56#define RX_BD_NUM 128
57
58/* ---------------------------------------------------------------------
59 * Low level register access functions
60 */
61
62u32 temac_ior(struct temac_local *lp, int offset)
63{
64 return in_be32((u32 *)(lp->regs + offset));
65}
66
67void temac_iow(struct temac_local *lp, int offset, u32 value)
68{
69 out_be32((u32 *) (lp->regs + offset), value);
70}
71
72int temac_indirect_busywait(struct temac_local *lp)
73{
74 long end = jiffies + 2;
75
76 while (!(temac_ior(lp, XTE_RDY0_OFFSET) & XTE_RDY0_HARD_ACS_RDY_MASK)) {
77 if (end - jiffies <= 0) {
78 WARN_ON(1);
79 return -ETIMEDOUT;
80 }
81 msleep(1);
82 }
83 return 0;
84}
85
86/**
87 * temac_indirect_in32
88 *
89 * lp->indirect_mutex must be held when calling this function
90 */
91u32 temac_indirect_in32(struct temac_local *lp, int reg)
92{
93 u32 val;
94
95 if (temac_indirect_busywait(lp))
96 return -ETIMEDOUT;
97 temac_iow(lp, XTE_CTL0_OFFSET, reg);
98 if (temac_indirect_busywait(lp))
99 return -ETIMEDOUT;
100 val = temac_ior(lp, XTE_LSW0_OFFSET);
101
102 return val;
103}
104
105/**
106 * temac_indirect_out32
107 *
108 * lp->indirect_mutex must be held when calling this function
109 */
110void temac_indirect_out32(struct temac_local *lp, int reg, u32 value)
111{
112 if (temac_indirect_busywait(lp))
113 return;
114 temac_iow(lp, XTE_LSW0_OFFSET, value);
115 temac_iow(lp, XTE_CTL0_OFFSET, CNTLREG_WRITE_ENABLE_MASK | reg);
116}
117
e44171f1
JL		 118/**
119 * temac_dma_in32 - Memory mapped DMA read, this function expects a
120 * register input that is based on DCR word addresses which
121 * are then converted to memory mapped byte addresses
122 */
92744989
GL		 123static u32 temac_dma_in32(struct temac_local *lp, int reg)
124{
e44171f1 125 return in_be32((u32 *)(lp->sdma_regs + (reg << 2)));
92744989
GL		 126}
127
e44171f1
JL		 128/**
129 * temac_dma_out32 - Memory mapped DMA read, this function expects a
130 * register input that is based on DCR word addresses which
131 * are then converted to memory mapped byte addresses
132 */
92744989 133static void temac_dma_out32(struct temac_local *lp, int reg, u32 value)
e44171f1
JL		 134{
135 out_be32((u32 *)(lp->sdma_regs + (reg << 2)), value);
136}
137
138/* DMA register access functions can be DCR based or memory mapped.
139 * The PowerPC 440 is DCR based, the PowerPC 405 and MicroBlaze are both
140 * memory mapped.
141 */
142#ifdef CONFIG_PPC_DCR
143
144/**
145 * temac_dma_dcr_in32 - DCR based DMA read
146 */
147static u32 temac_dma_dcr_in(struct temac_local *lp, int reg)
148{
149 return dcr_read(lp->sdma_dcrs, reg);
150}
151
152/**
153 * temac_dma_dcr_out32 - DCR based DMA write
154 */
155static void temac_dma_dcr_out(struct temac_local *lp, int reg, u32 value)
92744989
GL		 156{
157 dcr_write(lp->sdma_dcrs, reg, value);
158}
159
e44171f1
JL		 160/**
161 * temac_dcr_setup - If the DMA is DCR based, then setup the address and
162 * I/O functions
163 */
2dc11581 164static int temac_dcr_setup(struct temac_local *lp, struct platform_device *op,
e44171f1
JL		 165 struct device_node *np)
166{
167 unsigned int dcrs;
168
169 /* setup the dcr address mapping if it's in the device tree */
170
171 dcrs = dcr_resource_start(np, 0);
172 if (dcrs != 0) {
173 lp->sdma_dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0));
174 lp->dma_in = temac_dma_dcr_in;
175 lp->dma_out = temac_dma_dcr_out;
176 dev_dbg(&op->dev, "DCR base: %x\n", dcrs);
177 return 0;
178 }
179 /* no DCR in the device tree, indicate a failure */
180 return -1;
181}
182
183#else
184
185/*
186 * temac_dcr_setup - This is a stub for when DCR is not supported,
187 * such as with MicroBlaze
188 */
2dc11581 189static int temac_dcr_setup(struct temac_local *lp, struct platform_device *op,
e44171f1
JL		 190 struct device_node *np)
191{
192 return -1;
193}
194
195#endif
196
301e9d96
DK		 197/**
198 * * temac_dma_bd_release - Release buffer descriptor rings
199 */
200static void temac_dma_bd_release(struct net_device *ndev)
201{
202 struct temac_local *lp = netdev_priv(ndev);
203 int i;
204
205 for (i = 0; i < RX_BD_NUM; i++) {
206 if (!lp->rx_skb[i])
207 break;
208 else {
209 dma_unmap_single(ndev->dev.parent, lp->rx_bd_v[i].phys,
210 XTE_MAX_JUMBO_FRAME_SIZE, DMA_FROM_DEVICE);
211 dev_kfree_skb(lp->rx_skb[i]);
212 }
213 }
214 if (lp->rx_bd_v)
215 dma_free_coherent(ndev->dev.parent,
216 sizeof(*lp->rx_bd_v) * RX_BD_NUM,
217 lp->rx_bd_v, lp->rx_bd_p);
218 if (lp->tx_bd_v)
219 dma_free_coherent(ndev->dev.parent,
220 sizeof(*lp->tx_bd_v) * TX_BD_NUM,
221 lp->tx_bd_v, lp->tx_bd_p);
222 if (lp->rx_skb)
223 kfree(lp->rx_skb);
224}
225
92744989
GL		 226/**
227 * temac_dma_bd_init - Setup buffer descriptor rings
228 */
229static int temac_dma_bd_init(struct net_device *ndev)
230{
231 struct temac_local *lp = netdev_priv(ndev);
232 struct sk_buff *skb;
233 int i;
234
5d66fe92 235 lp->rx_skb = kzalloc(sizeof(*lp->rx_skb) * RX_BD_NUM, GFP_KERNEL);
fe62c298
DK		 236 if (!lp->rx_skb) {
237 dev_err(&ndev->dev,
238 "can't allocate memory for DMA RX buffer\n");
239 goto out;
240 }
92744989 241 /* allocate the tx and rx ring buffer descriptors. */
b595076a 242 /* returns a virtual address and a physical address. */
92744989
GL		 243 lp->tx_bd_v = dma_alloc_coherent(ndev->dev.parent,
244 sizeof(*lp->tx_bd_v) * TX_BD_NUM,
245 &lp->tx_bd_p, GFP_KERNEL);
fe62c298
DK		 246 if (!lp->tx_bd_v) {
247 dev_err(&ndev->dev,
248 "unable to allocate DMA TX buffer descriptors");
249 goto out;
250 }
92744989
GL		 251 lp->rx_bd_v = dma_alloc_coherent(ndev->dev.parent,
252 sizeof(*lp->rx_bd_v) * RX_BD_NUM,
253 &lp->rx_bd_p, GFP_KERNEL);
fe62c298
DK		 254 if (!lp->rx_bd_v) {
255 dev_err(&ndev->dev,
256 "unable to allocate DMA RX buffer descriptors");
257 goto out;
258 }
92744989
GL		 259
260 memset(lp->tx_bd_v, 0, sizeof(*lp->tx_bd_v) * TX_BD_NUM);
261 for (i = 0; i < TX_BD_NUM; i++) {
262 lp->tx_bd_v[i].next = lp->tx_bd_p +
263 sizeof(*lp->tx_bd_v) * ((i + 1) % TX_BD_NUM);
264 }
265
266 memset(lp->rx_bd_v, 0, sizeof(*lp->rx_bd_v) * RX_BD_NUM);
267 for (i = 0; i < RX_BD_NUM; i++) {
268 lp->rx_bd_v[i].next = lp->rx_bd_p +
269 sizeof(*lp->rx_bd_v) * ((i + 1) % RX_BD_NUM);
270
e44171f1
JL		 271 skb = netdev_alloc_skb_ip_align(ndev,
272 XTE_MAX_JUMBO_FRAME_SIZE);
273
92744989
GL		 274 if (skb == 0) {
275 dev_err(&ndev->dev, "alloc_skb error %d\n", i);
fe62c298 276 goto out;
92744989
GL		 277 }
278 lp->rx_skb[i] = skb;
92744989
GL		 279 /* returns physical address of skb->data */
280 lp->rx_bd_v[i].phys = dma_map_single(ndev->dev.parent,
281 skb->data,
282 XTE_MAX_JUMBO_FRAME_SIZE,
283 DMA_FROM_DEVICE);
284 lp->rx_bd_v[i].len = XTE_MAX_JUMBO_FRAME_SIZE;
285 lp->rx_bd_v[i].app0 = STS_CTRL_APP0_IRQONEND;
286 }
287
e44171f1 288 lp->dma_out(lp, TX_CHNL_CTRL, 0x10220400 |
92744989
GL		 289 CHNL_CTRL_IRQ_EN |
290 CHNL_CTRL_IRQ_DLY_EN |
291 CHNL_CTRL_IRQ_COAL_EN);
292 /* 0x10220483 */
293 /* 0x00100483 */
23ecc4bd 294 lp->dma_out(lp, RX_CHNL_CTRL, 0xff070000 |
92744989
GL		 295 CHNL_CTRL_IRQ_EN |
296 CHNL_CTRL_IRQ_DLY_EN |
297 CHNL_CTRL_IRQ_COAL_EN |
298 CHNL_CTRL_IRQ_IOE);
299 /* 0xff010283 */
300
e44171f1
JL		 301 lp->dma_out(lp, RX_CURDESC_PTR, lp->rx_bd_p);
302 lp->dma_out(lp, RX_TAILDESC_PTR,
92744989 303 lp->rx_bd_p + (sizeof(*lp->rx_bd_v) * (RX_BD_NUM - 1)));
e44171f1 304 lp->dma_out(lp, TX_CURDESC_PTR, lp->tx_bd_p);
92744989
GL		 305
306 return 0;
fe62c298
DK		 307
308out:
301e9d96 309 temac_dma_bd_release(ndev);
fe62c298 310 return -ENOMEM;
92744989
GL		 311}
312
313/* ---------------------------------------------------------------------
314 * net_device_ops
315 */
316
317static int temac_set_mac_address(struct net_device *ndev, void *address)
318{
319 struct temac_local *lp = netdev_priv(ndev);
320
321 if (address)
322 memcpy(ndev->dev_addr, address, ETH_ALEN);
323
324 if (!is_valid_ether_addr(ndev->dev_addr))
325 random_ether_addr(ndev->dev_addr);
326
327 /* set up unicast MAC address filter set its mac address */
328 mutex_lock(&lp->indirect_mutex);
329 temac_indirect_out32(lp, XTE_UAW0_OFFSET,
330 (ndev->dev_addr[0]) |
331 (ndev->dev_addr[1] << 8) |
332 (ndev->dev_addr[2] << 16) |
333 (ndev->dev_addr[3] << 24));
334 /* There are reserved bits in EUAW1
335 * so don't affect them Set MAC bits [47:32] in EUAW1 */
336 temac_indirect_out32(lp, XTE_UAW1_OFFSET,
337 (ndev->dev_addr[4] & 0x000000ff) |
338 (ndev->dev_addr[5] << 8));
339 mutex_unlock(&lp->indirect_mutex);
340
341 return 0;
342}
343
8ea7a37c
SM		 344static int netdev_set_mac_address(struct net_device *ndev, void *p)
345{
346 struct sockaddr *addr = p;
347
348 return temac_set_mac_address(ndev, addr->sa_data);
349}
350
92744989
GL		 351static void temac_set_multicast_list(struct net_device *ndev)
352{
353 struct temac_local *lp = netdev_priv(ndev);
354 u32 multi_addr_msw, multi_addr_lsw, val;
355 int i;
356
357 mutex_lock(&lp->indirect_mutex);
8e95a202 358 if (ndev->flags & (IFF_ALLMULTI | IFF_PROMISC) ||
4cd24eaf 359 netdev_mc_count(ndev) > MULTICAST_CAM_TABLE_NUM) {
92744989
GL		 360 /*
361 * We must make the kernel realise we had to move
362 * into promisc mode or we start all out war on
363 * the cable. If it was a promisc request the
364 * flag is already set. If not we assert it.
365 */
366 ndev->flags |= IFF_PROMISC;
367 temac_indirect_out32(lp, XTE_AFM_OFFSET, XTE_AFM_EPPRM_MASK);
368 dev_info(&ndev->dev, "Promiscuous mode enabled.\n");
4cd24eaf 369 } else if (!netdev_mc_empty(ndev)) {
22bedad3 370 struct netdev_hw_addr *ha;
92744989 371
f9dcbcc9 372 i = 0;
22bedad3 373 netdev_for_each_mc_addr(ha, ndev) {
92744989
GL		 374 if (i >= MULTICAST_CAM_TABLE_NUM)
375 break;
22bedad3
JP		 376 multi_addr_msw = ((ha->addr[3] << 24) |
377 (ha->addr[2] << 16) |
378 (ha->addr[1] << 8) |
379 (ha->addr[0]));
92744989
GL		 380 temac_indirect_out32(lp, XTE_MAW0_OFFSET,
381 multi_addr_msw);
22bedad3
JP		 382 multi_addr_lsw = ((ha->addr[5] << 8) |
383 (ha->addr[4]) | (i << 16));
92744989
GL		 384 temac_indirect_out32(lp, XTE_MAW1_OFFSET,
385 multi_addr_lsw);
f9dcbcc9 386 i++;
92744989
GL		 387 }
388 } else {
389 val = temac_indirect_in32(lp, XTE_AFM_OFFSET);
390 temac_indirect_out32(lp, XTE_AFM_OFFSET,
391 val & ~XTE_AFM_EPPRM_MASK);
392 temac_indirect_out32(lp, XTE_MAW0_OFFSET, 0);
393 temac_indirect_out32(lp, XTE_MAW1_OFFSET, 0);
394 dev_info(&ndev->dev, "Promiscuous mode disabled.\n");
395 }
396 mutex_unlock(&lp->indirect_mutex);
397}
398
399struct temac_option {
400 int flg;
401 u32 opt;
402 u32 reg;
403 u32 m_or;
404 u32 m_and;
405} temac_options[] = {
406 /* Turn on jumbo packet support for both Rx and Tx */
407 {
408 .opt = XTE_OPTION_JUMBO,
409 .reg = XTE_TXC_OFFSET,
410 .m_or = XTE_TXC_TXJMBO_MASK,
411 },
412 {
413 .opt = XTE_OPTION_JUMBO,
414 .reg = XTE_RXC1_OFFSET,
415 .m_or =XTE_RXC1_RXJMBO_MASK,
416 },
417 /* Turn on VLAN packet support for both Rx and Tx */
418 {
419 .opt = XTE_OPTION_VLAN,
420 .reg = XTE_TXC_OFFSET,
421 .m_or =XTE_TXC_TXVLAN_MASK,
422 },
423 {
424 .opt = XTE_OPTION_VLAN,
425 .reg = XTE_RXC1_OFFSET,
426 .m_or =XTE_RXC1_RXVLAN_MASK,
427 },
428 /* Turn on FCS stripping on receive packets */
429 {
430 .opt = XTE_OPTION_FCS_STRIP,
431 .reg = XTE_RXC1_OFFSET,
432 .m_or =XTE_RXC1_RXFCS_MASK,
433 },
434 /* Turn on FCS insertion on transmit packets */
435 {
436 .opt = XTE_OPTION_FCS_INSERT,
437 .reg = XTE_TXC_OFFSET,
438 .m_or =XTE_TXC_TXFCS_MASK,
439 },
440 /* Turn on length/type field checking on receive packets */
441 {
442 .opt = XTE_OPTION_LENTYPE_ERR,
443 .reg = XTE_RXC1_OFFSET,
444 .m_or =XTE_RXC1_RXLT_MASK,
445 },
446 /* Turn on flow control */
447 {
448 .opt = XTE_OPTION_FLOW_CONTROL,
449 .reg = XTE_FCC_OFFSET,
450 .m_or =XTE_FCC_RXFLO_MASK,
451 },
452 /* Turn on flow control */
453 {
454 .opt = XTE_OPTION_FLOW_CONTROL,
455 .reg = XTE_FCC_OFFSET,
456 .m_or =XTE_FCC_TXFLO_MASK,
457 },
458 /* Turn on promiscuous frame filtering (all frames are received ) */
459 {
460 .opt = XTE_OPTION_PROMISC,
461 .reg = XTE_AFM_OFFSET,
462 .m_or =XTE_AFM_EPPRM_MASK,
463 },
464 /* Enable transmitter if not already enabled */
465 {
466 .opt = XTE_OPTION_TXEN,
467 .reg = XTE_TXC_OFFSET,
468 .m_or =XTE_TXC_TXEN_MASK,
469 },
470 /* Enable receiver? */
471 {
472 .opt = XTE_OPTION_RXEN,
473 .reg = XTE_RXC1_OFFSET,
474 .m_or =XTE_RXC1_RXEN_MASK,
475 },
476 {}
477};
478
479/**
480 * temac_setoptions
481 */
482static u32 temac_setoptions(struct net_device *ndev, u32 options)
483{
484 struct temac_local *lp = netdev_priv(ndev);
485 struct temac_option *tp = &temac_options[0];
486 int reg;
487
488 mutex_lock(&lp->indirect_mutex);
489 while (tp->opt) {
490 reg = temac_indirect_in32(lp, tp->reg) & ~tp->m_or;
491 if (options & tp->opt)
492 reg |= tp->m_or;
493 temac_indirect_out32(lp, tp->reg, reg);
494 tp++;
495 }
496 lp->options |= options;
497 mutex_unlock(&lp->indirect_mutex);
498
807540ba 499 return 0;
92744989
GL		 500}
501
421f91d2 502/* Initialize temac */
92744989
GL		 503static void temac_device_reset(struct net_device *ndev)
504{
505 struct temac_local *lp = netdev_priv(ndev);
506 u32 timeout;
507 u32 val;
508
509 /* Perform a software reset */
510
511 /* 0x300 host enable bit ? */
512 /* reset PHY through control register ?:1 */
513
514 dev_dbg(&ndev->dev, "%s()\n", __func__);
515
516 mutex_lock(&lp->indirect_mutex);
517 /* Reset the receiver and wait for it to finish reset */
518 temac_indirect_out32(lp, XTE_RXC1_OFFSET, XTE_RXC1_RXRST_MASK);
519 timeout = 1000;
520 while (temac_indirect_in32(lp, XTE_RXC1_OFFSET) & XTE_RXC1_RXRST_MASK) {
521 udelay(1);
522 if (--timeout == 0) {
523 dev_err(&ndev->dev,
524 "temac_device_reset RX reset timeout!!\n");
525 break;
526 }
527 }
528
529 /* Reset the transmitter and wait for it to finish reset */
530 temac_indirect_out32(lp, XTE_TXC_OFFSET, XTE_TXC_TXRST_MASK);
531 timeout = 1000;
532 while (temac_indirect_in32(lp, XTE_TXC_OFFSET) & XTE_TXC_TXRST_MASK) {
533 udelay(1);
534 if (--timeout == 0) {
535 dev_err(&ndev->dev,
536 "temac_device_reset TX reset timeout!!\n");
537 break;
538 }
539 }
540
541 /* Disable the receiver */
542 val = temac_indirect_in32(lp, XTE_RXC1_OFFSET);
543 temac_indirect_out32(lp, XTE_RXC1_OFFSET, val & ~XTE_RXC1_RXEN_MASK);
544
545 /* Reset Local Link (DMA) */
e44171f1 546 lp->dma_out(lp, DMA_CONTROL_REG, DMA_CONTROL_RST);
92744989 547 timeout = 1000;
e44171f1 548 while (lp->dma_in(lp, DMA_CONTROL_REG) & DMA_CONTROL_RST) {
92744989
GL		 549 udelay(1);
550 if (--timeout == 0) {
551 dev_err(&ndev->dev,
552 "temac_device_reset DMA reset timeout!!\n");
553 break;
554 }
555 }
e44171f1 556 lp->dma_out(lp, DMA_CONTROL_REG, DMA_TAIL_ENABLE);
92744989 557
fe62c298
DK		 558 if (temac_dma_bd_init(ndev)) {
559 dev_err(&ndev->dev,
560 "temac_device_reset descriptor allocation failed\n");
561 }
92744989
GL		 562
563 temac_indirect_out32(lp, XTE_RXC0_OFFSET, 0);
564 temac_indirect_out32(lp, XTE_RXC1_OFFSET, 0);
565 temac_indirect_out32(lp, XTE_TXC_OFFSET, 0);
566 temac_indirect_out32(lp, XTE_FCC_OFFSET, XTE_FCC_RXFLO_MASK);
567
568 mutex_unlock(&lp->indirect_mutex);
569
570 /* Sync default options with HW
571 * but leave receiver and transmitter disabled. */
572 temac_setoptions(ndev,
573 lp->options & ~(XTE_OPTION_TXEN | XTE_OPTION_RXEN));
574
575 temac_set_mac_address(ndev, NULL);
576
577 /* Set address filter table */
578 temac_set_multicast_list(ndev);
579 if (temac_setoptions(ndev, lp->options))
580 dev_err(&ndev->dev, "Error setting TEMAC options\n");
581
582 /* Init Driver variable */
1ae5dc34 583 ndev->trans_start = jiffies; /* prevent tx timeout */
92744989
GL		 584}
585
586void temac_adjust_link(struct net_device *ndev)
587{
588 struct temac_local *lp = netdev_priv(ndev);
589 struct phy_device *phy = lp->phy_dev;
590 u32 mii_speed;
591 int link_state;
592
593 /* hash together the state values to decide if something has changed */
594 link_state = phy->speed | (phy->duplex << 1) | phy->link;
595
596 mutex_lock(&lp->indirect_mutex);
597 if (lp->last_link != link_state) {
598 mii_speed = temac_indirect_in32(lp, XTE_EMCFG_OFFSET);
599 mii_speed &= ~XTE_EMCFG_LINKSPD_MASK;
600
601 switch (phy->speed) {
602 case SPEED_1000: mii_speed |= XTE_EMCFG_LINKSPD_1000; break;
603 case SPEED_100: mii_speed |= XTE_EMCFG_LINKSPD_100; break;
604 case SPEED_10: mii_speed |= XTE_EMCFG_LINKSPD_10; break;
605 }
606
607 /* Write new speed setting out to TEMAC */
608 temac_indirect_out32(lp, XTE_EMCFG_OFFSET, mii_speed);
609 lp->last_link = link_state;
610 phy_print_status(phy);
611 }
612 mutex_unlock(&lp->indirect_mutex);
613}
614
615static void temac_start_xmit_done(struct net_device *ndev)
616{
617 struct temac_local *lp = netdev_priv(ndev);
618 struct cdmac_bd *cur_p;
619 unsigned int stat = 0;
620
621 cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
622 stat = cur_p->app0;
623
624 while (stat & STS_CTRL_APP0_CMPLT) {
625 dma_unmap_single(ndev->dev.parent, cur_p->phys, cur_p->len,
626 DMA_TO_DEVICE);
627 if (cur_p->app4)
628 dev_kfree_skb_irq((struct sk_buff *)cur_p->app4);
629 cur_p->app0 = 0;
23ecc4bd
BH		 630 cur_p->app1 = 0;
631 cur_p->app2 = 0;
632 cur_p->app3 = 0;
633 cur_p->app4 = 0;
92744989
GL		 634
635 ndev->stats.tx_packets++;
636 ndev->stats.tx_bytes += cur_p->len;
637
638 lp->tx_bd_ci++;
639 if (lp->tx_bd_ci >= TX_BD_NUM)
640 lp->tx_bd_ci = 0;
641
642 cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
643 stat = cur_p->app0;
644 }
645
646 netif_wake_queue(ndev);
647}
648
23ecc4bd
BH		 649static inline int temac_check_tx_bd_space(struct temac_local *lp, int num_frag)
650{
651 struct cdmac_bd *cur_p;
652 int tail;
653
654 tail = lp->tx_bd_tail;
655 cur_p = &lp->tx_bd_v[tail];
656
657 do {
658 if (cur_p->app0)
659 return NETDEV_TX_BUSY;
660
661 tail++;
662 if (tail >= TX_BD_NUM)
663 tail = 0;
664
665 cur_p = &lp->tx_bd_v[tail];
666 num_frag--;
667 } while (num_frag >= 0);
668
669 return 0;
670}
671
92744989
GL		 672static int temac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
673{
674 struct temac_local *lp = netdev_priv(ndev);
675 struct cdmac_bd *cur_p;
676 dma_addr_t start_p, tail_p;
677 int ii;
678 unsigned long num_frag;
679 skb_frag_t *frag;
680
681 num_frag = skb_shinfo(skb)->nr_frags;
682 frag = &skb_shinfo(skb)->frags[0];
683 start_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail;
684 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
685
23ecc4bd 686 if (temac_check_tx_bd_space(lp, num_frag)) {
92744989
GL		 687 if (!netif_queue_stopped(ndev)) {
688 netif_stop_queue(ndev);
689 return NETDEV_TX_BUSY;
690 }
691 return NETDEV_TX_BUSY;
692 }
693
694 cur_p->app0 = 0;
695 if (skb->ip_summed == CHECKSUM_PARTIAL) {
0d0b1672 696 unsigned int csum_start_off = skb_checksum_start_offset(skb);
23ecc4bd
BH		 697 unsigned int csum_index_off = csum_start_off + skb->csum_offset;
698
699 cur_p->app0 |= 1; /* TX Checksum Enabled */
700 cur_p->app1 = (csum_start_off << 16) | csum_index_off;
701 cur_p->app2 = 0; /* initial checksum seed */
92744989 702 }
23ecc4bd 703
92744989
GL		 704 cur_p->app0 |= STS_CTRL_APP0_SOP;
705 cur_p->len = skb_headlen(skb);
706 cur_p->phys = dma_map_single(ndev->dev.parent, skb->data, skb->len,
707 DMA_TO_DEVICE);
708 cur_p->app4 = (unsigned long)skb;
709
710 for (ii = 0; ii < num_frag; ii++) {
711 lp->tx_bd_tail++;
712 if (lp->tx_bd_tail >= TX_BD_NUM)
713 lp->tx_bd_tail = 0;
714
715 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
716 cur_p->phys = dma_map_single(ndev->dev.parent,
717 (void *)page_address(frag->page) +
718 frag->page_offset,
719 frag->size, DMA_TO_DEVICE);
720 cur_p->len = frag->size;
721 cur_p->app0 = 0;
722 frag++;
723 }
724 cur_p->app0 |= STS_CTRL_APP0_EOP;
725
726 tail_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail;
727 lp->tx_bd_tail++;
728 if (lp->tx_bd_tail >= TX_BD_NUM)
729 lp->tx_bd_tail = 0;
730
731 /* Kick off the transfer */
e44171f1 732 lp->dma_out(lp, TX_TAILDESC_PTR, tail_p); /* DMA start */
92744989 733
6ed10654 734 return NETDEV_TX_OK;
92744989
GL		 735}
736
737
738static void ll_temac_recv(struct net_device *ndev)
739{
740 struct temac_local *lp = netdev_priv(ndev);
741 struct sk_buff *skb, *new_skb;
742 unsigned int bdstat;
743 struct cdmac_bd *cur_p;
744 dma_addr_t tail_p;
745 int length;
92744989
GL		 746 unsigned long flags;
747
748 spin_lock_irqsave(&lp->rx_lock, flags);
749
750 tail_p = lp->rx_bd_p + sizeof(*lp->rx_bd_v) * lp->rx_bd_ci;
751 cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
752
753 bdstat = cur_p->app0;
754 while ((bdstat & STS_CTRL_APP0_CMPLT)) {
755
756 skb = lp->rx_skb[lp->rx_bd_ci];
c3b7c12c 757 length = cur_p->app4 & 0x3FFF;
92744989 758
33646d7f 759 dma_unmap_single(ndev->dev.parent, cur_p->phys, length,
92744989
GL		 760 DMA_FROM_DEVICE);
761
762 skb_put(skb, length);
763 skb->dev = ndev;
764 skb->protocol = eth_type_trans(skb, ndev);
bc8acf2c 765 skb_checksum_none_assert(skb);
92744989 766
23ecc4bd
BH		 767 /* if we're doing rx csum offload, set it up */
768 if (((lp->temac_features & TEMAC_FEATURE_RX_CSUM) != 0) &&
769 (skb->protocol == __constant_htons(ETH_P_IP)) &&
770 (skb->len > 64)) {
771
772 skb->csum = cur_p->app3 & 0xFFFF;
773 skb->ip_summed = CHECKSUM_COMPLETE;
774 }
775
92744989
GL		 776 netif_rx(skb);
777
778 ndev->stats.rx_packets++;
779 ndev->stats.rx_bytes += length;
780
e44171f1
JL		 781 new_skb = netdev_alloc_skb_ip_align(ndev,
782 XTE_MAX_JUMBO_FRAME_SIZE);
783
92744989
GL		 784 if (new_skb == 0) {
785 dev_err(&ndev->dev, "no memory for new sk_buff\n");
786 spin_unlock_irqrestore(&lp->rx_lock, flags);
787 return;
788 }
789
92744989
GL		 790 cur_p->app0 = STS_CTRL_APP0_IRQONEND;
791 cur_p->phys = dma_map_single(ndev->dev.parent, new_skb->data,
792 XTE_MAX_JUMBO_FRAME_SIZE,
793 DMA_FROM_DEVICE);
794 cur_p->len = XTE_MAX_JUMBO_FRAME_SIZE;
795 lp->rx_skb[lp->rx_bd_ci] = new_skb;
796
797 lp->rx_bd_ci++;
798 if (lp->rx_bd_ci >= RX_BD_NUM)
799 lp->rx_bd_ci = 0;
800
801 cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
802 bdstat = cur_p->app0;
803 }
e44171f1 804 lp->dma_out(lp, RX_TAILDESC_PTR, tail_p);
92744989
GL		 805
806 spin_unlock_irqrestore(&lp->rx_lock, flags);
807}
808
809static irqreturn_t ll_temac_tx_irq(int irq, void *_ndev)
810{
811 struct net_device *ndev = _ndev;
812 struct temac_local *lp = netdev_priv(ndev);
813 unsigned int status;
814
e44171f1
JL		 815 status = lp->dma_in(lp, TX_IRQ_REG);
816 lp->dma_out(lp, TX_IRQ_REG, status);
92744989
GL		 817
818 if (status & (IRQ_COAL | IRQ_DLY))
819 temac_start_xmit_done(lp->ndev);
820 if (status & 0x080)
821 dev_err(&ndev->dev, "DMA error 0x%x\n", status);
822
823 return IRQ_HANDLED;
824}
825
826static irqreturn_t ll_temac_rx_irq(int irq, void *_ndev)
827{
828 struct net_device *ndev = _ndev;
829 struct temac_local *lp = netdev_priv(ndev);
830 unsigned int status;
831
832 /* Read and clear the status registers */
e44171f1
JL		 833 status = lp->dma_in(lp, RX_IRQ_REG);
834 lp->dma_out(lp, RX_IRQ_REG, status);
92744989
GL		 835
836 if (status & (IRQ_COAL | IRQ_DLY))
837 ll_temac_recv(lp->ndev);
838
839 return IRQ_HANDLED;
840}
841
842static int temac_open(struct net_device *ndev)
843{
844 struct temac_local *lp = netdev_priv(ndev);
845 int rc;
846
847 dev_dbg(&ndev->dev, "temac_open()\n");
848
849 if (lp->phy_node) {
850 lp->phy_dev = of_phy_connect(lp->ndev, lp->phy_node,
851 temac_adjust_link, 0, 0);
852 if (!lp->phy_dev) {
853 dev_err(lp->dev, "of_phy_connect() failed\n");
854 return -ENODEV;
855 }
856
857 phy_start(lp->phy_dev);
858 }
859
860 rc = request_irq(lp->tx_irq, ll_temac_tx_irq, 0, ndev->name, ndev);
861 if (rc)
862 goto err_tx_irq;
863 rc = request_irq(lp->rx_irq, ll_temac_rx_irq, 0, ndev->name, ndev);
864 if (rc)
865 goto err_rx_irq;
866
867 temac_device_reset(ndev);
868 return 0;
869
870 err_rx_irq:
871 free_irq(lp->tx_irq, ndev);
872 err_tx_irq:
873 if (lp->phy_dev)
874 phy_disconnect(lp->phy_dev);
875 lp->phy_dev = NULL;
876 dev_err(lp->dev, "request_irq() failed\n");
877 return rc;
878}
879
880static int temac_stop(struct net_device *ndev)
881{
882 struct temac_local *lp = netdev_priv(ndev);
883
884 dev_dbg(&ndev->dev, "temac_close()\n");
885
886 free_irq(lp->tx_irq, ndev);
887 free_irq(lp->rx_irq, ndev);
888
889 if (lp->phy_dev)
890 phy_disconnect(lp->phy_dev);
891 lp->phy_dev = NULL;
892
301e9d96
DK		 893 temac_dma_bd_release(ndev);
894
92744989
GL		 895 return 0;
896}
897
898#ifdef CONFIG_NET_POLL_CONTROLLER
899static void
900temac_poll_controller(struct net_device *ndev)
901{
902 struct temac_local *lp = netdev_priv(ndev);
903
904 disable_irq(lp->tx_irq);
905 disable_irq(lp->rx_irq);
906
8539992f
MS		 907 ll_temac_rx_irq(lp->tx_irq, ndev);
908 ll_temac_tx_irq(lp->rx_irq, ndev);
92744989
GL		 909
910 enable_irq(lp->tx_irq);
911 enable_irq(lp->rx_irq);
912}
913#endif
914
915static const struct net_device_ops temac_netdev_ops = {
916 .ndo_open = temac_open,
917 .ndo_stop = temac_stop,
918 .ndo_start_xmit = temac_start_xmit,
8ea7a37c 919 .ndo_set_mac_address = netdev_set_mac_address,
60eb5fd1 920 .ndo_validate_addr = eth_validate_addr,
92744989
GL		 921 //.ndo_set_multicast_list = temac_set_multicast_list,
922#ifdef CONFIG_NET_POLL_CONTROLLER
923 .ndo_poll_controller = temac_poll_controller,
924#endif
925};
926
927/* ---------------------------------------------------------------------
928 * SYSFS device attributes
929 */
930static ssize_t temac_show_llink_regs(struct device *dev,
931 struct device_attribute *attr, char *buf)
932{
933 struct net_device *ndev = dev_get_drvdata(dev);
934 struct temac_local *lp = netdev_priv(ndev);
935 int i, len = 0;
936
937 for (i = 0; i < 0x11; i++)
e44171f1 938 len += sprintf(buf + len, "%.8x%s", lp->dma_in(lp, i),
92744989
GL		 939 (i % 8) == 7 ? "\n" : " ");
940 len += sprintf(buf + len, "\n");
941
942 return len;
943}
944
945static DEVICE_ATTR(llink_regs, 0440, temac_show_llink_regs, NULL);
946
947static struct attribute *temac_device_attrs[] = {
948 &dev_attr_llink_regs.attr,
949 NULL,
950};
951
952static const struct attribute_group temac_attr_group = {
953 .attrs = temac_device_attrs,
954};
955
74888760 956static int __devinit temac_of_probe(struct platform_device *op)
92744989
GL		 957{
958 struct device_node *np;
959 struct temac_local *lp;
960 struct net_device *ndev;
961 const void *addr;
23ecc4bd 962 __be32 *p;
92744989 963 int size, rc = 0;
92744989
GL		 964
965 /* Init network device structure */
966 ndev = alloc_etherdev(sizeof(*lp));
967 if (!ndev) {
968 dev_err(&op->dev, "could not allocate device.\n");
969 return -ENOMEM;
970 }
971 ether_setup(ndev);
972 dev_set_drvdata(&op->dev, ndev);
973 SET_NETDEV_DEV(ndev, &op->dev);
974 ndev->flags &= ~IFF_MULTICAST; /* clear multicast */
975 ndev->features = NETIF_F_SG | NETIF_F_FRAGLIST;
976 ndev->netdev_ops = &temac_netdev_ops;
977#if 0
978 ndev->features |= NETIF_F_IP_CSUM; /* Can checksum TCP/UDP over IPv4. */
979 ndev->features |= NETIF_F_HW_CSUM; /* Can checksum all the packets. */
980 ndev->features |= NETIF_F_IPV6_CSUM; /* Can checksum IPV6 TCP/UDP */
981 ndev->features |= NETIF_F_HIGHDMA; /* Can DMA to high memory. */
982 ndev->features |= NETIF_F_HW_VLAN_TX; /* Transmit VLAN hw accel */
983 ndev->features |= NETIF_F_HW_VLAN_RX; /* Receive VLAN hw acceleration */
984 ndev->features |= NETIF_F_HW_VLAN_FILTER; /* Receive VLAN filtering */
985 ndev->features |= NETIF_F_VLAN_CHALLENGED; /* cannot handle VLAN pkts */
986 ndev->features |= NETIF_F_GSO; /* Enable software GSO. */
987 ndev->features |= NETIF_F_MULTI_QUEUE; /* Has multiple TX/RX queues */
988 ndev->features |= NETIF_F_LRO; /* large receive offload */
989#endif
990
991 /* setup temac private info structure */
992 lp = netdev_priv(ndev);
993 lp->ndev = ndev;
994 lp->dev = &op->dev;
995 lp->options = XTE_OPTION_DEFAULTS;
996 spin_lock_init(&lp->rx_lock);
997 mutex_init(&lp->indirect_mutex);
998
999 /* map device registers */
61c7a080 1000 lp->regs = of_iomap(op->dev.of_node, 0);
92744989
GL		 1001 if (!lp->regs) {
1002 dev_err(&op->dev, "could not map temac regs.\n");
1003 goto nodev;
1004 }
1005
23ecc4bd
BH		 1006 /* Setup checksum offload, but default to off if not specified */
1007 lp->temac_features = 0;
1008 p = (__be32 *)of_get_property(op->dev.of_node, "xlnx,txcsum", NULL);
1009 if (p && be32_to_cpu(*p)) {
1010 lp->temac_features |= TEMAC_FEATURE_TX_CSUM;
1011 /* Can checksum TCP/UDP over IPv4. */
1012 ndev->features |= NETIF_F_IP_CSUM;
1013 }
1014 p = (__be32 *)of_get_property(op->dev.of_node, "xlnx,rxcsum", NULL);
1015 if (p && be32_to_cpu(*p))
1016 lp->temac_features |= TEMAC_FEATURE_RX_CSUM;
1017
92744989 1018 /* Find the DMA node, map the DMA registers, and decode the DMA IRQs */
61c7a080 1019 np = of_parse_phandle(op->dev.of_node, "llink-connected", 0);
92744989
GL		 1020 if (!np) {
1021 dev_err(&op->dev, "could not find DMA node\n");
dfe1e8ed 1022 goto err_iounmap;
92744989
GL		 1023 }
1024
e44171f1
JL		 1025 /* Setup the DMA register accesses, could be DCR or memory mapped */
1026 if (temac_dcr_setup(lp, op, np)) {
1027
1028 /* no DCR in the device tree, try non-DCR */
1029 lp->sdma_regs = of_iomap(np, 0);
1030 if (lp->sdma_regs) {
1031 lp->dma_in = temac_dma_in32;
1032 lp->dma_out = temac_dma_out32;
1033 dev_dbg(&op->dev, "MEM base: %p\n", lp->sdma_regs);
1034 } else {
1035 dev_err(&op->dev, "unable to map DMA registers\n");
7cc36f6f 1036 of_node_put(np);
dfe1e8ed 1037 goto err_iounmap;
e44171f1 1038 }
92744989 1039 }
92744989
GL		 1040
1041 lp->rx_irq = irq_of_parse_and_map(np, 0);
1042 lp->tx_irq = irq_of_parse_and_map(np, 1);
7cc36f6f
KV		 1043
1044 of_node_put(np); /* Finished with the DMA node; drop the reference */
1045
755fae0a 1046 if ((lp->rx_irq == NO_IRQ) || (lp->tx_irq == NO_IRQ)) {
92744989
GL		 1047 dev_err(&op->dev, "could not determine irqs\n");
1048 rc = -ENOMEM;
dfe1e8ed 1049 goto err_iounmap_2;
92744989
GL		 1050 }
1051
92744989
GL		 1052
1053 /* Retrieve the MAC address */
61c7a080 1054 addr = of_get_property(op->dev.of_node, "local-mac-address", &size);
92744989
GL		 1055 if ((!addr) || (size != 6)) {
1056 dev_err(&op->dev, "could not find MAC address\n");
1057 rc = -ENODEV;
dfe1e8ed 1058 goto err_iounmap_2;
92744989
GL		 1059 }
1060 temac_set_mac_address(ndev, (void *)addr);
1061
61c7a080 1062 rc = temac_mdio_setup(lp, op->dev.of_node);
92744989
GL		 1063 if (rc)
1064 dev_warn(&op->dev, "error registering MDIO bus\n");
1065
61c7a080 1066 lp->phy_node = of_parse_phandle(op->dev.of_node, "phy-handle", 0);
92744989
GL		 1067 if (lp->phy_node)
1068 dev_dbg(lp->dev, "using PHY node %s (%p)\n", np->full_name, np);
1069
1070 /* Add the device attributes */
1071 rc = sysfs_create_group(&lp->dev->kobj, &temac_attr_group);
1072 if (rc) {
1073 dev_err(lp->dev, "Error creating sysfs files\n");
dfe1e8ed 1074 goto err_iounmap_2;
92744989
GL		 1075 }
1076
1077 rc = register_netdev(lp->ndev);
1078 if (rc) {
1079 dev_err(lp->dev, "register_netdev() error (%i)\n", rc);
1080 goto err_register_ndev;
1081 }
1082
1083 return 0;
1084
1085 err_register_ndev:
1086 sysfs_remove_group(&lp->dev->kobj, &temac_attr_group);
dfe1e8ed
DK		 1087 err_iounmap_2:
1088 if (lp->sdma_regs)
1089 iounmap(lp->sdma_regs);
1090 err_iounmap:
1091 iounmap(lp->regs);
92744989
GL		 1092 nodev:
1093 free_netdev(ndev);
1094 ndev = NULL;
1095 return rc;
1096}
1097
2dc11581 1098static int __devexit temac_of_remove(struct platform_device *op)
92744989
GL		 1099{
1100 struct net_device *ndev = dev_get_drvdata(&op->dev);
1101 struct temac_local *lp = netdev_priv(ndev);
1102
1103 temac_mdio_teardown(lp);
1104 unregister_netdev(ndev);
1105 sysfs_remove_group(&lp->dev->kobj, &temac_attr_group);
1106 if (lp->phy_node)
1107 of_node_put(lp->phy_node);
1108 lp->phy_node = NULL;
1109 dev_set_drvdata(&op->dev, NULL);
dfe1e8ed
DK		 1110 iounmap(lp->regs);
1111 if (lp->sdma_regs)
1112 iounmap(lp->sdma_regs);
92744989
GL		 1113 free_netdev(ndev);
1114 return 0;
1115}
1116
1117static struct of_device_id temac_of_match[] __devinitdata = {
1118 { .compatible = "xlnx,xps-ll-temac-1.01.b", },
c3b7c12c
SM		 1119 { .compatible = "xlnx,xps-ll-temac-2.00.a", },
1120 { .compatible = "xlnx,xps-ll-temac-2.02.a", },
1121 { .compatible = "xlnx,xps-ll-temac-2.03.a", },
92744989
GL		 1122 {},
1123};
1124MODULE_DEVICE_TABLE(of, temac_of_match);
1125
74888760 1126static struct platform_driver temac_of_driver = {
92744989
GL		 1127 .probe = temac_of_probe,
1128 .remove = __devexit_p(temac_of_remove),
1129 .driver = {
1130 .owner = THIS_MODULE,
1131 .name = "xilinx_temac",
4018294b 1132 .of_match_table = temac_of_match,
92744989
GL		 1133 },
1134};
1135
1136static int __init temac_init(void)
1137{
74888760 1138 return platform_driver_register(&temac_of_driver);
92744989
GL		 1139}
1140module_init(temac_init);
1141
1142static void __exit temac_exit(void)
1143{
74888760 1144 platform_driver_unregister(&temac_of_driver);
92744989
GL		 1145}
1146module_exit(temac_exit);
1147
1148MODULE_DESCRIPTION("Xilinx LL_TEMAC Ethernet driver");
1149MODULE_AUTHOR("Yoshio Kashiwagi");
1150MODULE_LICENSE("GPL");
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