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Commit | Line | Data |
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89e5785f HS |
1 | /* |
2 | * Atmel MACB Ethernet Controller driver | |
3 | * | |
4 | * Copyright (C) 2004-2006 Atmel Corporation | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/clk.h> | |
12 | #include <linux/module.h> | |
13 | #include <linux/moduleparam.h> | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/types.h> | |
16 | #include <linux/slab.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/netdevice.h> | |
19 | #include <linux/etherdevice.h> | |
89e5785f | 20 | #include <linux/dma-mapping.h> |
89e5785f | 21 | #include <linux/platform_device.h> |
6c36a707 | 22 | #include <linux/phy.h> |
89e5785f HS |
23 | |
24 | #include <asm/arch/board.h> | |
6c36a707 | 25 | #include <asm/arch/cpu.h> |
89e5785f HS |
26 | |
27 | #include "macb.h" | |
28 | ||
89e5785f HS |
29 | #define RX_BUFFER_SIZE 128 |
30 | #define RX_RING_SIZE 512 | |
31 | #define RX_RING_BYTES (sizeof(struct dma_desc) * RX_RING_SIZE) | |
32 | ||
33 | /* Make the IP header word-aligned (the ethernet header is 14 bytes) */ | |
34 | #define RX_OFFSET 2 | |
35 | ||
36 | #define TX_RING_SIZE 128 | |
37 | #define DEF_TX_RING_PENDING (TX_RING_SIZE - 1) | |
38 | #define TX_RING_BYTES (sizeof(struct dma_desc) * TX_RING_SIZE) | |
39 | ||
40 | #define TX_RING_GAP(bp) \ | |
41 | (TX_RING_SIZE - (bp)->tx_pending) | |
42 | #define TX_BUFFS_AVAIL(bp) \ | |
43 | (((bp)->tx_tail <= (bp)->tx_head) ? \ | |
44 | (bp)->tx_tail + (bp)->tx_pending - (bp)->tx_head : \ | |
45 | (bp)->tx_tail - (bp)->tx_head - TX_RING_GAP(bp)) | |
46 | #define NEXT_TX(n) (((n) + 1) & (TX_RING_SIZE - 1)) | |
47 | ||
48 | #define NEXT_RX(n) (((n) + 1) & (RX_RING_SIZE - 1)) | |
49 | ||
50 | /* minimum number of free TX descriptors before waking up TX process */ | |
51 | #define MACB_TX_WAKEUP_THRESH (TX_RING_SIZE / 4) | |
52 | ||
53 | #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \ | |
54 | | MACB_BIT(ISR_ROVR)) | |
55 | ||
56 | static void __macb_set_hwaddr(struct macb *bp) | |
57 | { | |
58 | u32 bottom; | |
59 | u16 top; | |
60 | ||
61 | bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr)); | |
62 | macb_writel(bp, SA1B, bottom); | |
63 | top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4))); | |
64 | macb_writel(bp, SA1T, top); | |
65 | } | |
66 | ||
67 | static void __init macb_get_hwaddr(struct macb *bp) | |
68 | { | |
69 | u32 bottom; | |
70 | u16 top; | |
71 | u8 addr[6]; | |
72 | ||
73 | bottom = macb_readl(bp, SA1B); | |
74 | top = macb_readl(bp, SA1T); | |
75 | ||
76 | addr[0] = bottom & 0xff; | |
77 | addr[1] = (bottom >> 8) & 0xff; | |
78 | addr[2] = (bottom >> 16) & 0xff; | |
79 | addr[3] = (bottom >> 24) & 0xff; | |
80 | addr[4] = top & 0xff; | |
81 | addr[5] = (top >> 8) & 0xff; | |
82 | ||
83 | if (is_valid_ether_addr(addr)) | |
84 | memcpy(bp->dev->dev_addr, addr, sizeof(addr)); | |
85 | } | |
86 | ||
6c36a707 | 87 | static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum) |
89e5785f | 88 | { |
6c36a707 | 89 | struct macb *bp = bus->priv; |
89e5785f HS |
90 | int value; |
91 | ||
89e5785f HS |
92 | macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF) |
93 | | MACB_BF(RW, MACB_MAN_READ) | |
6c36a707 R |
94 | | MACB_BF(PHYA, mii_id) |
95 | | MACB_BF(REGA, regnum) | |
89e5785f HS |
96 | | MACB_BF(CODE, MACB_MAN_CODE))); |
97 | ||
6c36a707 R |
98 | /* wait for end of transfer */ |
99 | while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR))) | |
100 | cpu_relax(); | |
89e5785f HS |
101 | |
102 | value = MACB_BFEXT(DATA, macb_readl(bp, MAN)); | |
89e5785f HS |
103 | |
104 | return value; | |
105 | } | |
106 | ||
6c36a707 R |
107 | static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum, |
108 | u16 value) | |
89e5785f | 109 | { |
6c36a707 | 110 | struct macb *bp = bus->priv; |
89e5785f HS |
111 | |
112 | macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF) | |
113 | | MACB_BF(RW, MACB_MAN_WRITE) | |
6c36a707 R |
114 | | MACB_BF(PHYA, mii_id) |
115 | | MACB_BF(REGA, regnum) | |
89e5785f | 116 | | MACB_BF(CODE, MACB_MAN_CODE) |
6c36a707 | 117 | | MACB_BF(DATA, value))); |
89e5785f | 118 | |
6c36a707 R |
119 | /* wait for end of transfer */ |
120 | while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR))) | |
121 | cpu_relax(); | |
122 | ||
123 | return 0; | |
124 | } | |
89e5785f | 125 | |
6c36a707 R |
126 | static int macb_mdio_reset(struct mii_bus *bus) |
127 | { | |
128 | return 0; | |
89e5785f HS |
129 | } |
130 | ||
6c36a707 | 131 | static void macb_handle_link_change(struct net_device *dev) |
89e5785f | 132 | { |
6c36a707 R |
133 | struct macb *bp = netdev_priv(dev); |
134 | struct phy_device *phydev = bp->phy_dev; | |
135 | unsigned long flags; | |
89e5785f | 136 | |
6c36a707 | 137 | int status_change = 0; |
89e5785f | 138 | |
6c36a707 R |
139 | spin_lock_irqsave(&bp->lock, flags); |
140 | ||
141 | if (phydev->link) { | |
142 | if ((bp->speed != phydev->speed) || | |
143 | (bp->duplex != phydev->duplex)) { | |
144 | u32 reg; | |
145 | ||
146 | reg = macb_readl(bp, NCFGR); | |
147 | reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD)); | |
148 | ||
149 | if (phydev->duplex) | |
150 | reg |= MACB_BIT(FD); | |
151 | if (phydev->speed) | |
152 | reg |= MACB_BIT(SPD); | |
153 | ||
154 | macb_writel(bp, NCFGR, reg); | |
155 | ||
156 | bp->speed = phydev->speed; | |
157 | bp->duplex = phydev->duplex; | |
158 | status_change = 1; | |
159 | } | |
89e5785f HS |
160 | } |
161 | ||
6c36a707 R |
162 | if (phydev->link != bp->link) { |
163 | if (phydev->link) | |
164 | netif_schedule(dev); | |
165 | else { | |
166 | bp->speed = 0; | |
167 | bp->duplex = -1; | |
168 | } | |
169 | bp->link = phydev->link; | |
89e5785f | 170 | |
6c36a707 R |
171 | status_change = 1; |
172 | } | |
89e5785f | 173 | |
6c36a707 R |
174 | spin_unlock_irqrestore(&bp->lock, flags); |
175 | ||
176 | if (status_change) { | |
177 | if (phydev->link) | |
178 | printk(KERN_INFO "%s: link up (%d/%s)\n", | |
179 | dev->name, phydev->speed, | |
180 | DUPLEX_FULL == phydev->duplex ? "Full":"Half"); | |
181 | else | |
182 | printk(KERN_INFO "%s: link down\n", dev->name); | |
183 | } | |
89e5785f HS |
184 | } |
185 | ||
6c36a707 R |
186 | /* based on au1000_eth. c*/ |
187 | static int macb_mii_probe(struct net_device *dev) | |
89e5785f | 188 | { |
6c36a707 R |
189 | struct macb *bp = netdev_priv(dev); |
190 | struct phy_device *phydev = NULL; | |
191 | struct eth_platform_data *pdata; | |
192 | int phy_addr; | |
89e5785f | 193 | |
6c36a707 R |
194 | /* find the first phy */ |
195 | for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { | |
196 | if (bp->mii_bus.phy_map[phy_addr]) { | |
197 | phydev = bp->mii_bus.phy_map[phy_addr]; | |
198 | break; | |
199 | } | |
200 | } | |
201 | ||
202 | if (!phydev) { | |
203 | printk (KERN_ERR "%s: no PHY found\n", dev->name); | |
204 | return -1; | |
205 | } | |
206 | ||
207 | pdata = bp->pdev->dev.platform_data; | |
208 | /* TODO : add pin_irq */ | |
209 | ||
210 | /* attach the mac to the phy */ | |
211 | if (pdata && pdata->is_rmii) { | |
212 | phydev = phy_connect(dev, phydev->dev.bus_id, | |
213 | &macb_handle_link_change, 0, PHY_INTERFACE_MODE_RMII); | |
214 | } else { | |
215 | phydev = phy_connect(dev, phydev->dev.bus_id, | |
216 | &macb_handle_link_change, 0, PHY_INTERFACE_MODE_MII); | |
217 | } | |
218 | ||
219 | if (IS_ERR(phydev)) { | |
220 | printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name); | |
221 | return PTR_ERR(phydev); | |
222 | } | |
223 | ||
224 | /* mask with MAC supported features */ | |
225 | phydev->supported &= PHY_BASIC_FEATURES; | |
226 | ||
227 | phydev->advertising = phydev->supported; | |
228 | ||
229 | bp->link = 0; | |
230 | bp->speed = 0; | |
231 | bp->duplex = -1; | |
232 | bp->phy_dev = phydev; | |
233 | ||
234 | return 0; | |
89e5785f HS |
235 | } |
236 | ||
6c36a707 | 237 | static int macb_mii_init(struct macb *bp) |
89e5785f | 238 | { |
6c36a707 R |
239 | struct eth_platform_data *pdata; |
240 | int err = -ENXIO, i; | |
89e5785f | 241 | |
6c36a707 R |
242 | /* Enable managment port */ |
243 | macb_writel(bp, NCR, MACB_BIT(MPE)); | |
89e5785f | 244 | |
6c36a707 R |
245 | bp->mii_bus.name = "MACB_mii_bus", |
246 | bp->mii_bus.read = &macb_mdio_read, | |
247 | bp->mii_bus.write = &macb_mdio_write, | |
248 | bp->mii_bus.reset = &macb_mdio_reset, | |
249 | bp->mii_bus.id = bp->pdev->id, | |
250 | bp->mii_bus.priv = bp, | |
251 | bp->mii_bus.dev = &bp->dev->dev; | |
252 | pdata = bp->pdev->dev.platform_data; | |
89e5785f | 253 | |
6c36a707 R |
254 | if (pdata) |
255 | bp->mii_bus.phy_mask = pdata->phy_mask; | |
89e5785f | 256 | |
6c36a707 R |
257 | bp->mii_bus.irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL); |
258 | if (!bp->mii_bus.irq) { | |
259 | err = -ENOMEM; | |
260 | goto err_out; | |
89e5785f HS |
261 | } |
262 | ||
6c36a707 R |
263 | for (i = 0; i < PHY_MAX_ADDR; i++) |
264 | bp->mii_bus.irq[i] = PHY_POLL; | |
89e5785f | 265 | |
6c36a707 | 266 | platform_set_drvdata(bp->dev, &bp->mii_bus); |
89e5785f | 267 | |
6c36a707 R |
268 | if (mdiobus_register(&bp->mii_bus)) |
269 | goto err_out_free_mdio_irq; | |
89e5785f | 270 | |
6c36a707 R |
271 | if (macb_mii_probe(bp->dev) != 0) { |
272 | goto err_out_unregister_bus; | |
273 | } | |
89e5785f | 274 | |
6c36a707 | 275 | return 0; |
89e5785f | 276 | |
6c36a707 R |
277 | err_out_unregister_bus: |
278 | mdiobus_unregister(&bp->mii_bus); | |
279 | err_out_free_mdio_irq: | |
280 | kfree(bp->mii_bus.irq); | |
281 | err_out: | |
282 | return err; | |
89e5785f HS |
283 | } |
284 | ||
285 | static void macb_update_stats(struct macb *bp) | |
286 | { | |
287 | u32 __iomem *reg = bp->regs + MACB_PFR; | |
288 | u32 *p = &bp->hw_stats.rx_pause_frames; | |
289 | u32 *end = &bp->hw_stats.tx_pause_frames + 1; | |
290 | ||
291 | WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4); | |
292 | ||
293 | for(; p < end; p++, reg++) | |
0f0d84e5 | 294 | *p += __raw_readl(reg); |
89e5785f HS |
295 | } |
296 | ||
89e5785f HS |
297 | static void macb_tx(struct macb *bp) |
298 | { | |
299 | unsigned int tail; | |
300 | unsigned int head; | |
301 | u32 status; | |
302 | ||
303 | status = macb_readl(bp, TSR); | |
304 | macb_writel(bp, TSR, status); | |
305 | ||
306 | dev_dbg(&bp->pdev->dev, "macb_tx status = %02lx\n", | |
307 | (unsigned long)status); | |
308 | ||
309 | if (status & MACB_BIT(UND)) { | |
310 | printk(KERN_ERR "%s: TX underrun, resetting buffers\n", | |
311 | bp->dev->name); | |
312 | bp->tx_head = bp->tx_tail = 0; | |
313 | } | |
314 | ||
315 | if (!(status & MACB_BIT(COMP))) | |
316 | /* | |
317 | * This may happen when a buffer becomes complete | |
318 | * between reading the ISR and scanning the | |
319 | * descriptors. Nothing to worry about. | |
320 | */ | |
321 | return; | |
322 | ||
323 | head = bp->tx_head; | |
324 | for (tail = bp->tx_tail; tail != head; tail = NEXT_TX(tail)) { | |
325 | struct ring_info *rp = &bp->tx_skb[tail]; | |
326 | struct sk_buff *skb = rp->skb; | |
327 | u32 bufstat; | |
328 | ||
329 | BUG_ON(skb == NULL); | |
330 | ||
331 | rmb(); | |
332 | bufstat = bp->tx_ring[tail].ctrl; | |
333 | ||
334 | if (!(bufstat & MACB_BIT(TX_USED))) | |
335 | break; | |
336 | ||
337 | dev_dbg(&bp->pdev->dev, "skb %u (data %p) TX complete\n", | |
338 | tail, skb->data); | |
339 | dma_unmap_single(&bp->pdev->dev, rp->mapping, skb->len, | |
340 | DMA_TO_DEVICE); | |
341 | bp->stats.tx_packets++; | |
342 | bp->stats.tx_bytes += skb->len; | |
343 | rp->skb = NULL; | |
344 | dev_kfree_skb_irq(skb); | |
345 | } | |
346 | ||
347 | bp->tx_tail = tail; | |
348 | if (netif_queue_stopped(bp->dev) && | |
349 | TX_BUFFS_AVAIL(bp) > MACB_TX_WAKEUP_THRESH) | |
350 | netif_wake_queue(bp->dev); | |
351 | } | |
352 | ||
353 | static int macb_rx_frame(struct macb *bp, unsigned int first_frag, | |
354 | unsigned int last_frag) | |
355 | { | |
356 | unsigned int len; | |
357 | unsigned int frag; | |
358 | unsigned int offset = 0; | |
359 | struct sk_buff *skb; | |
360 | ||
361 | len = MACB_BFEXT(RX_FRMLEN, bp->rx_ring[last_frag].ctrl); | |
362 | ||
363 | dev_dbg(&bp->pdev->dev, "macb_rx_frame frags %u - %u (len %u)\n", | |
364 | first_frag, last_frag, len); | |
365 | ||
366 | skb = dev_alloc_skb(len + RX_OFFSET); | |
367 | if (!skb) { | |
368 | bp->stats.rx_dropped++; | |
369 | for (frag = first_frag; ; frag = NEXT_RX(frag)) { | |
370 | bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED); | |
371 | if (frag == last_frag) | |
372 | break; | |
373 | } | |
374 | wmb(); | |
375 | return 1; | |
376 | } | |
377 | ||
378 | skb_reserve(skb, RX_OFFSET); | |
89e5785f HS |
379 | skb->ip_summed = CHECKSUM_NONE; |
380 | skb_put(skb, len); | |
381 | ||
382 | for (frag = first_frag; ; frag = NEXT_RX(frag)) { | |
383 | unsigned int frag_len = RX_BUFFER_SIZE; | |
384 | ||
385 | if (offset + frag_len > len) { | |
386 | BUG_ON(frag != last_frag); | |
387 | frag_len = len - offset; | |
388 | } | |
27d7ff46 ACM |
389 | skb_copy_to_linear_data_offset(skb, offset, |
390 | (bp->rx_buffers + | |
391 | (RX_BUFFER_SIZE * frag)), | |
392 | frag_len); | |
89e5785f HS |
393 | offset += RX_BUFFER_SIZE; |
394 | bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED); | |
395 | wmb(); | |
396 | ||
397 | if (frag == last_frag) | |
398 | break; | |
399 | } | |
400 | ||
401 | skb->protocol = eth_type_trans(skb, bp->dev); | |
402 | ||
403 | bp->stats.rx_packets++; | |
404 | bp->stats.rx_bytes += len; | |
405 | bp->dev->last_rx = jiffies; | |
406 | dev_dbg(&bp->pdev->dev, "received skb of length %u, csum: %08x\n", | |
407 | skb->len, skb->csum); | |
408 | netif_receive_skb(skb); | |
409 | ||
410 | return 0; | |
411 | } | |
412 | ||
413 | /* Mark DMA descriptors from begin up to and not including end as unused */ | |
414 | static void discard_partial_frame(struct macb *bp, unsigned int begin, | |
415 | unsigned int end) | |
416 | { | |
417 | unsigned int frag; | |
418 | ||
419 | for (frag = begin; frag != end; frag = NEXT_RX(frag)) | |
420 | bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED); | |
421 | wmb(); | |
422 | ||
423 | /* | |
424 | * When this happens, the hardware stats registers for | |
425 | * whatever caused this is updated, so we don't have to record | |
426 | * anything. | |
427 | */ | |
428 | } | |
429 | ||
430 | static int macb_rx(struct macb *bp, int budget) | |
431 | { | |
432 | int received = 0; | |
433 | unsigned int tail = bp->rx_tail; | |
434 | int first_frag = -1; | |
435 | ||
436 | for (; budget > 0; tail = NEXT_RX(tail)) { | |
437 | u32 addr, ctrl; | |
438 | ||
439 | rmb(); | |
440 | addr = bp->rx_ring[tail].addr; | |
441 | ctrl = bp->rx_ring[tail].ctrl; | |
442 | ||
443 | if (!(addr & MACB_BIT(RX_USED))) | |
444 | break; | |
445 | ||
446 | if (ctrl & MACB_BIT(RX_SOF)) { | |
447 | if (first_frag != -1) | |
448 | discard_partial_frame(bp, first_frag, tail); | |
449 | first_frag = tail; | |
450 | } | |
451 | ||
452 | if (ctrl & MACB_BIT(RX_EOF)) { | |
453 | int dropped; | |
454 | BUG_ON(first_frag == -1); | |
455 | ||
456 | dropped = macb_rx_frame(bp, first_frag, tail); | |
457 | first_frag = -1; | |
458 | if (!dropped) { | |
459 | received++; | |
460 | budget--; | |
461 | } | |
462 | } | |
463 | } | |
464 | ||
465 | if (first_frag != -1) | |
466 | bp->rx_tail = first_frag; | |
467 | else | |
468 | bp->rx_tail = tail; | |
469 | ||
470 | return received; | |
471 | } | |
472 | ||
bea3348e | 473 | static int macb_poll(struct napi_struct *napi, int budget) |
89e5785f | 474 | { |
bea3348e SH |
475 | struct macb *bp = container_of(napi, struct macb, napi); |
476 | struct net_device *dev = bp->dev; | |
477 | int work_done; | |
89e5785f HS |
478 | u32 status; |
479 | ||
480 | status = macb_readl(bp, RSR); | |
481 | macb_writel(bp, RSR, status); | |
482 | ||
bea3348e | 483 | work_done = 0; |
89e5785f HS |
484 | if (!status) { |
485 | /* | |
486 | * This may happen if an interrupt was pending before | |
487 | * this function was called last time, and no packets | |
488 | * have been received since. | |
489 | */ | |
bea3348e | 490 | netif_rx_complete(dev, napi); |
89e5785f HS |
491 | goto out; |
492 | } | |
493 | ||
494 | dev_dbg(&bp->pdev->dev, "poll: status = %08lx, budget = %d\n", | |
bea3348e | 495 | (unsigned long)status, budget); |
89e5785f HS |
496 | |
497 | if (!(status & MACB_BIT(REC))) { | |
498 | dev_warn(&bp->pdev->dev, | |
499 | "No RX buffers complete, status = %02lx\n", | |
500 | (unsigned long)status); | |
bea3348e | 501 | netif_rx_complete(dev, napi); |
89e5785f HS |
502 | goto out; |
503 | } | |
504 | ||
bea3348e SH |
505 | work_done = macb_rx(bp, budget); |
506 | if (work_done < budget) | |
507 | netif_rx_complete(dev, napi); | |
89e5785f HS |
508 | |
509 | /* | |
510 | * We've done what we can to clean the buffers. Make sure we | |
511 | * get notified when new packets arrive. | |
512 | */ | |
513 | out: | |
514 | macb_writel(bp, IER, MACB_RX_INT_FLAGS); | |
515 | ||
516 | /* TODO: Handle errors */ | |
517 | ||
bea3348e | 518 | return work_done; |
89e5785f HS |
519 | } |
520 | ||
521 | static irqreturn_t macb_interrupt(int irq, void *dev_id) | |
522 | { | |
523 | struct net_device *dev = dev_id; | |
524 | struct macb *bp = netdev_priv(dev); | |
525 | u32 status; | |
526 | ||
527 | status = macb_readl(bp, ISR); | |
528 | ||
529 | if (unlikely(!status)) | |
530 | return IRQ_NONE; | |
531 | ||
532 | spin_lock(&bp->lock); | |
533 | ||
534 | while (status) { | |
89e5785f HS |
535 | /* close possible race with dev_close */ |
536 | if (unlikely(!netif_running(dev))) { | |
537 | macb_writel(bp, IDR, ~0UL); | |
538 | break; | |
539 | } | |
540 | ||
541 | if (status & MACB_RX_INT_FLAGS) { | |
bea3348e | 542 | if (netif_rx_schedule_prep(dev, &bp->napi)) { |
89e5785f HS |
543 | /* |
544 | * There's no point taking any more interrupts | |
545 | * until we have processed the buffers | |
546 | */ | |
547 | macb_writel(bp, IDR, MACB_RX_INT_FLAGS); | |
6c36a707 R |
548 | dev_dbg(&bp->pdev->dev, |
549 | "scheduling RX softirq\n"); | |
bea3348e | 550 | __netif_rx_schedule(dev, &bp->napi); |
89e5785f HS |
551 | } |
552 | } | |
553 | ||
554 | if (status & (MACB_BIT(TCOMP) | MACB_BIT(ISR_TUND))) | |
555 | macb_tx(bp); | |
556 | ||
557 | /* | |
558 | * Link change detection isn't possible with RMII, so we'll | |
559 | * add that if/when we get our hands on a full-blown MII PHY. | |
560 | */ | |
561 | ||
562 | if (status & MACB_BIT(HRESP)) { | |
563 | /* | |
564 | * TODO: Reset the hardware, and maybe move the printk | |
565 | * to a lower-priority context as well (work queue?) | |
566 | */ | |
567 | printk(KERN_ERR "%s: DMA bus error: HRESP not OK\n", | |
568 | dev->name); | |
569 | } | |
570 | ||
571 | status = macb_readl(bp, ISR); | |
572 | } | |
573 | ||
574 | spin_unlock(&bp->lock); | |
575 | ||
576 | return IRQ_HANDLED; | |
577 | } | |
578 | ||
579 | static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
580 | { | |
581 | struct macb *bp = netdev_priv(dev); | |
582 | dma_addr_t mapping; | |
583 | unsigned int len, entry; | |
584 | u32 ctrl; | |
585 | ||
586 | #ifdef DEBUG | |
587 | int i; | |
588 | dev_dbg(&bp->pdev->dev, | |
589 | "start_xmit: len %u head %p data %p tail %p end %p\n", | |
27a884dc | 590 | skb->len, skb->head, skb->data, |
4305b541 | 591 | skb_tail_pointer(skb), skb_end_pointer(skb)); |
89e5785f HS |
592 | dev_dbg(&bp->pdev->dev, |
593 | "data:"); | |
594 | for (i = 0; i < 16; i++) | |
595 | printk(" %02x", (unsigned int)skb->data[i]); | |
596 | printk("\n"); | |
597 | #endif | |
598 | ||
599 | len = skb->len; | |
600 | spin_lock_irq(&bp->lock); | |
601 | ||
602 | /* This is a hard error, log it. */ | |
603 | if (TX_BUFFS_AVAIL(bp) < 1) { | |
604 | netif_stop_queue(dev); | |
605 | spin_unlock_irq(&bp->lock); | |
606 | dev_err(&bp->pdev->dev, | |
607 | "BUG! Tx Ring full when queue awake!\n"); | |
608 | dev_dbg(&bp->pdev->dev, "tx_head = %u, tx_tail = %u\n", | |
609 | bp->tx_head, bp->tx_tail); | |
610 | return 1; | |
611 | } | |
612 | ||
613 | entry = bp->tx_head; | |
614 | dev_dbg(&bp->pdev->dev, "Allocated ring entry %u\n", entry); | |
615 | mapping = dma_map_single(&bp->pdev->dev, skb->data, | |
616 | len, DMA_TO_DEVICE); | |
617 | bp->tx_skb[entry].skb = skb; | |
618 | bp->tx_skb[entry].mapping = mapping; | |
619 | dev_dbg(&bp->pdev->dev, "Mapped skb data %p to DMA addr %08lx\n", | |
620 | skb->data, (unsigned long)mapping); | |
621 | ||
622 | ctrl = MACB_BF(TX_FRMLEN, len); | |
623 | ctrl |= MACB_BIT(TX_LAST); | |
624 | if (entry == (TX_RING_SIZE - 1)) | |
625 | ctrl |= MACB_BIT(TX_WRAP); | |
626 | ||
627 | bp->tx_ring[entry].addr = mapping; | |
628 | bp->tx_ring[entry].ctrl = ctrl; | |
629 | wmb(); | |
630 | ||
631 | entry = NEXT_TX(entry); | |
632 | bp->tx_head = entry; | |
633 | ||
634 | macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART)); | |
635 | ||
636 | if (TX_BUFFS_AVAIL(bp) < 1) | |
637 | netif_stop_queue(dev); | |
638 | ||
639 | spin_unlock_irq(&bp->lock); | |
640 | ||
641 | dev->trans_start = jiffies; | |
642 | ||
643 | return 0; | |
644 | } | |
645 | ||
646 | static void macb_free_consistent(struct macb *bp) | |
647 | { | |
648 | if (bp->tx_skb) { | |
649 | kfree(bp->tx_skb); | |
650 | bp->tx_skb = NULL; | |
651 | } | |
652 | if (bp->rx_ring) { | |
653 | dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES, | |
654 | bp->rx_ring, bp->rx_ring_dma); | |
655 | bp->rx_ring = NULL; | |
656 | } | |
657 | if (bp->tx_ring) { | |
658 | dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES, | |
659 | bp->tx_ring, bp->tx_ring_dma); | |
660 | bp->tx_ring = NULL; | |
661 | } | |
662 | if (bp->rx_buffers) { | |
663 | dma_free_coherent(&bp->pdev->dev, | |
664 | RX_RING_SIZE * RX_BUFFER_SIZE, | |
665 | bp->rx_buffers, bp->rx_buffers_dma); | |
666 | bp->rx_buffers = NULL; | |
667 | } | |
668 | } | |
669 | ||
670 | static int macb_alloc_consistent(struct macb *bp) | |
671 | { | |
672 | int size; | |
673 | ||
674 | size = TX_RING_SIZE * sizeof(struct ring_info); | |
675 | bp->tx_skb = kmalloc(size, GFP_KERNEL); | |
676 | if (!bp->tx_skb) | |
677 | goto out_err; | |
678 | ||
679 | size = RX_RING_BYTES; | |
680 | bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size, | |
681 | &bp->rx_ring_dma, GFP_KERNEL); | |
682 | if (!bp->rx_ring) | |
683 | goto out_err; | |
684 | dev_dbg(&bp->pdev->dev, | |
685 | "Allocated RX ring of %d bytes at %08lx (mapped %p)\n", | |
686 | size, (unsigned long)bp->rx_ring_dma, bp->rx_ring); | |
687 | ||
688 | size = TX_RING_BYTES; | |
689 | bp->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size, | |
690 | &bp->tx_ring_dma, GFP_KERNEL); | |
691 | if (!bp->tx_ring) | |
692 | goto out_err; | |
693 | dev_dbg(&bp->pdev->dev, | |
694 | "Allocated TX ring of %d bytes at %08lx (mapped %p)\n", | |
695 | size, (unsigned long)bp->tx_ring_dma, bp->tx_ring); | |
696 | ||
697 | size = RX_RING_SIZE * RX_BUFFER_SIZE; | |
698 | bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size, | |
699 | &bp->rx_buffers_dma, GFP_KERNEL); | |
700 | if (!bp->rx_buffers) | |
701 | goto out_err; | |
702 | dev_dbg(&bp->pdev->dev, | |
703 | "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n", | |
704 | size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers); | |
705 | ||
706 | return 0; | |
707 | ||
708 | out_err: | |
709 | macb_free_consistent(bp); | |
710 | return -ENOMEM; | |
711 | } | |
712 | ||
713 | static void macb_init_rings(struct macb *bp) | |
714 | { | |
715 | int i; | |
716 | dma_addr_t addr; | |
717 | ||
718 | addr = bp->rx_buffers_dma; | |
719 | for (i = 0; i < RX_RING_SIZE; i++) { | |
720 | bp->rx_ring[i].addr = addr; | |
721 | bp->rx_ring[i].ctrl = 0; | |
722 | addr += RX_BUFFER_SIZE; | |
723 | } | |
724 | bp->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP); | |
725 | ||
726 | for (i = 0; i < TX_RING_SIZE; i++) { | |
727 | bp->tx_ring[i].addr = 0; | |
728 | bp->tx_ring[i].ctrl = MACB_BIT(TX_USED); | |
729 | } | |
730 | bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP); | |
731 | ||
732 | bp->rx_tail = bp->tx_head = bp->tx_tail = 0; | |
733 | } | |
734 | ||
735 | static void macb_reset_hw(struct macb *bp) | |
736 | { | |
737 | /* Make sure we have the write buffer for ourselves */ | |
738 | wmb(); | |
739 | ||
740 | /* | |
741 | * Disable RX and TX (XXX: Should we halt the transmission | |
742 | * more gracefully?) | |
743 | */ | |
744 | macb_writel(bp, NCR, 0); | |
745 | ||
746 | /* Clear the stats registers (XXX: Update stats first?) */ | |
747 | macb_writel(bp, NCR, MACB_BIT(CLRSTAT)); | |
748 | ||
749 | /* Clear all status flags */ | |
750 | macb_writel(bp, TSR, ~0UL); | |
751 | macb_writel(bp, RSR, ~0UL); | |
752 | ||
753 | /* Disable all interrupts */ | |
754 | macb_writel(bp, IDR, ~0UL); | |
755 | macb_readl(bp, ISR); | |
756 | } | |
757 | ||
758 | static void macb_init_hw(struct macb *bp) | |
759 | { | |
760 | u32 config; | |
761 | ||
762 | macb_reset_hw(bp); | |
763 | __macb_set_hwaddr(bp); | |
764 | ||
765 | config = macb_readl(bp, NCFGR) & MACB_BF(CLK, -1L); | |
766 | config |= MACB_BIT(PAE); /* PAuse Enable */ | |
767 | config |= MACB_BIT(DRFCS); /* Discard Rx FCS */ | |
768 | if (bp->dev->flags & IFF_PROMISC) | |
769 | config |= MACB_BIT(CAF); /* Copy All Frames */ | |
770 | if (!(bp->dev->flags & IFF_BROADCAST)) | |
771 | config |= MACB_BIT(NBC); /* No BroadCast */ | |
772 | macb_writel(bp, NCFGR, config); | |
773 | ||
774 | /* Initialize TX and RX buffers */ | |
775 | macb_writel(bp, RBQP, bp->rx_ring_dma); | |
776 | macb_writel(bp, TBQP, bp->tx_ring_dma); | |
777 | ||
778 | /* Enable TX and RX */ | |
6c36a707 | 779 | macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE)); |
89e5785f HS |
780 | |
781 | /* Enable interrupts */ | |
782 | macb_writel(bp, IER, (MACB_BIT(RCOMP) | |
783 | | MACB_BIT(RXUBR) | |
784 | | MACB_BIT(ISR_TUND) | |
785 | | MACB_BIT(ISR_RLE) | |
786 | | MACB_BIT(TXERR) | |
787 | | MACB_BIT(TCOMP) | |
788 | | MACB_BIT(ISR_ROVR) | |
789 | | MACB_BIT(HRESP))); | |
89e5785f | 790 | |
89e5785f HS |
791 | } |
792 | ||
446ebd01 PV |
793 | /* |
794 | * The hash address register is 64 bits long and takes up two | |
795 | * locations in the memory map. The least significant bits are stored | |
796 | * in EMAC_HSL and the most significant bits in EMAC_HSH. | |
797 | * | |
798 | * The unicast hash enable and the multicast hash enable bits in the | |
799 | * network configuration register enable the reception of hash matched | |
800 | * frames. The destination address is reduced to a 6 bit index into | |
801 | * the 64 bit hash register using the following hash function. The | |
802 | * hash function is an exclusive or of every sixth bit of the | |
803 | * destination address. | |
804 | * | |
805 | * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47] | |
806 | * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46] | |
807 | * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45] | |
808 | * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44] | |
809 | * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43] | |
810 | * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42] | |
811 | * | |
812 | * da[0] represents the least significant bit of the first byte | |
813 | * received, that is, the multicast/unicast indicator, and da[47] | |
814 | * represents the most significant bit of the last byte received. If | |
815 | * the hash index, hi[n], points to a bit that is set in the hash | |
816 | * register then the frame will be matched according to whether the | |
817 | * frame is multicast or unicast. A multicast match will be signalled | |
818 | * if the multicast hash enable bit is set, da[0] is 1 and the hash | |
819 | * index points to a bit set in the hash register. A unicast match | |
820 | * will be signalled if the unicast hash enable bit is set, da[0] is 0 | |
821 | * and the hash index points to a bit set in the hash register. To | |
822 | * receive all multicast frames, the hash register should be set with | |
823 | * all ones and the multicast hash enable bit should be set in the | |
824 | * network configuration register. | |
825 | */ | |
826 | ||
827 | static inline int hash_bit_value(int bitnr, __u8 *addr) | |
828 | { | |
829 | if (addr[bitnr / 8] & (1 << (bitnr % 8))) | |
830 | return 1; | |
831 | return 0; | |
832 | } | |
833 | ||
834 | /* | |
835 | * Return the hash index value for the specified address. | |
836 | */ | |
837 | static int hash_get_index(__u8 *addr) | |
838 | { | |
839 | int i, j, bitval; | |
840 | int hash_index = 0; | |
841 | ||
842 | for (j = 0; j < 6; j++) { | |
843 | for (i = 0, bitval = 0; i < 8; i++) | |
844 | bitval ^= hash_bit_value(i*6 + j, addr); | |
845 | ||
846 | hash_index |= (bitval << j); | |
847 | } | |
848 | ||
849 | return hash_index; | |
850 | } | |
851 | ||
852 | /* | |
853 | * Add multicast addresses to the internal multicast-hash table. | |
854 | */ | |
855 | static void macb_sethashtable(struct net_device *dev) | |
856 | { | |
857 | struct dev_mc_list *curr; | |
858 | unsigned long mc_filter[2]; | |
859 | unsigned int i, bitnr; | |
860 | struct macb *bp = netdev_priv(dev); | |
861 | ||
862 | mc_filter[0] = mc_filter[1] = 0; | |
863 | ||
864 | curr = dev->mc_list; | |
865 | for (i = 0; i < dev->mc_count; i++, curr = curr->next) { | |
866 | if (!curr) break; /* unexpected end of list */ | |
867 | ||
868 | bitnr = hash_get_index(curr->dmi_addr); | |
869 | mc_filter[bitnr >> 5] |= 1 << (bitnr & 31); | |
870 | } | |
871 | ||
872 | macb_writel(bp, HRB, mc_filter[0]); | |
873 | macb_writel(bp, HRT, mc_filter[1]); | |
874 | } | |
875 | ||
876 | /* | |
877 | * Enable/Disable promiscuous and multicast modes. | |
878 | */ | |
879 | static void macb_set_rx_mode(struct net_device *dev) | |
880 | { | |
881 | unsigned long cfg; | |
882 | struct macb *bp = netdev_priv(dev); | |
883 | ||
884 | cfg = macb_readl(bp, NCFGR); | |
885 | ||
886 | if (dev->flags & IFF_PROMISC) | |
887 | /* Enable promiscuous mode */ | |
888 | cfg |= MACB_BIT(CAF); | |
889 | else if (dev->flags & (~IFF_PROMISC)) | |
890 | /* Disable promiscuous mode */ | |
891 | cfg &= ~MACB_BIT(CAF); | |
892 | ||
893 | if (dev->flags & IFF_ALLMULTI) { | |
894 | /* Enable all multicast mode */ | |
895 | macb_writel(bp, HRB, -1); | |
896 | macb_writel(bp, HRT, -1); | |
897 | cfg |= MACB_BIT(NCFGR_MTI); | |
898 | } else if (dev->mc_count > 0) { | |
899 | /* Enable specific multicasts */ | |
900 | macb_sethashtable(dev); | |
901 | cfg |= MACB_BIT(NCFGR_MTI); | |
902 | } else if (dev->flags & (~IFF_ALLMULTI)) { | |
903 | /* Disable all multicast mode */ | |
904 | macb_writel(bp, HRB, 0); | |
905 | macb_writel(bp, HRT, 0); | |
906 | cfg &= ~MACB_BIT(NCFGR_MTI); | |
907 | } | |
908 | ||
909 | macb_writel(bp, NCFGR, cfg); | |
910 | } | |
911 | ||
89e5785f HS |
912 | static int macb_open(struct net_device *dev) |
913 | { | |
914 | struct macb *bp = netdev_priv(dev); | |
915 | int err; | |
916 | ||
917 | dev_dbg(&bp->pdev->dev, "open\n"); | |
918 | ||
6c36a707 R |
919 | /* if the phy is not yet register, retry later*/ |
920 | if (!bp->phy_dev) | |
921 | return -EAGAIN; | |
922 | ||
89e5785f HS |
923 | if (!is_valid_ether_addr(dev->dev_addr)) |
924 | return -EADDRNOTAVAIL; | |
925 | ||
926 | err = macb_alloc_consistent(bp); | |
927 | if (err) { | |
928 | printk(KERN_ERR | |
929 | "%s: Unable to allocate DMA memory (error %d)\n", | |
930 | dev->name, err); | |
931 | return err; | |
932 | } | |
933 | ||
bea3348e SH |
934 | napi_enable(&bp->napi); |
935 | ||
89e5785f HS |
936 | macb_init_rings(bp); |
937 | macb_init_hw(bp); | |
89e5785f | 938 | |
6c36a707 R |
939 | /* schedule a link state check */ |
940 | phy_start(bp->phy_dev); | |
89e5785f | 941 | |
6c36a707 | 942 | netif_start_queue(dev); |
89e5785f HS |
943 | |
944 | return 0; | |
945 | } | |
946 | ||
947 | static int macb_close(struct net_device *dev) | |
948 | { | |
949 | struct macb *bp = netdev_priv(dev); | |
950 | unsigned long flags; | |
951 | ||
89e5785f | 952 | netif_stop_queue(dev); |
bea3348e | 953 | napi_disable(&bp->napi); |
89e5785f | 954 | |
6c36a707 R |
955 | if (bp->phy_dev) |
956 | phy_stop(bp->phy_dev); | |
957 | ||
89e5785f HS |
958 | spin_lock_irqsave(&bp->lock, flags); |
959 | macb_reset_hw(bp); | |
960 | netif_carrier_off(dev); | |
961 | spin_unlock_irqrestore(&bp->lock, flags); | |
962 | ||
963 | macb_free_consistent(bp); | |
964 | ||
965 | return 0; | |
966 | } | |
967 | ||
968 | static struct net_device_stats *macb_get_stats(struct net_device *dev) | |
969 | { | |
970 | struct macb *bp = netdev_priv(dev); | |
971 | struct net_device_stats *nstat = &bp->stats; | |
972 | struct macb_stats *hwstat = &bp->hw_stats; | |
973 | ||
6c36a707 R |
974 | /* read stats from hardware */ |
975 | macb_update_stats(bp); | |
976 | ||
89e5785f HS |
977 | /* Convert HW stats into netdevice stats */ |
978 | nstat->rx_errors = (hwstat->rx_fcs_errors + | |
979 | hwstat->rx_align_errors + | |
980 | hwstat->rx_resource_errors + | |
981 | hwstat->rx_overruns + | |
982 | hwstat->rx_oversize_pkts + | |
983 | hwstat->rx_jabbers + | |
984 | hwstat->rx_undersize_pkts + | |
985 | hwstat->sqe_test_errors + | |
986 | hwstat->rx_length_mismatch); | |
987 | nstat->tx_errors = (hwstat->tx_late_cols + | |
988 | hwstat->tx_excessive_cols + | |
989 | hwstat->tx_underruns + | |
990 | hwstat->tx_carrier_errors); | |
991 | nstat->collisions = (hwstat->tx_single_cols + | |
992 | hwstat->tx_multiple_cols + | |
993 | hwstat->tx_excessive_cols); | |
994 | nstat->rx_length_errors = (hwstat->rx_oversize_pkts + | |
995 | hwstat->rx_jabbers + | |
996 | hwstat->rx_undersize_pkts + | |
997 | hwstat->rx_length_mismatch); | |
998 | nstat->rx_over_errors = hwstat->rx_resource_errors; | |
999 | nstat->rx_crc_errors = hwstat->rx_fcs_errors; | |
1000 | nstat->rx_frame_errors = hwstat->rx_align_errors; | |
1001 | nstat->rx_fifo_errors = hwstat->rx_overruns; | |
1002 | /* XXX: What does "missed" mean? */ | |
1003 | nstat->tx_aborted_errors = hwstat->tx_excessive_cols; | |
1004 | nstat->tx_carrier_errors = hwstat->tx_carrier_errors; | |
1005 | nstat->tx_fifo_errors = hwstat->tx_underruns; | |
1006 | /* Don't know about heartbeat or window errors... */ | |
1007 | ||
1008 | return nstat; | |
1009 | } | |
1010 | ||
1011 | static int macb_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1012 | { | |
1013 | struct macb *bp = netdev_priv(dev); | |
6c36a707 R |
1014 | struct phy_device *phydev = bp->phy_dev; |
1015 | ||
1016 | if (!phydev) | |
1017 | return -ENODEV; | |
89e5785f | 1018 | |
6c36a707 | 1019 | return phy_ethtool_gset(phydev, cmd); |
89e5785f HS |
1020 | } |
1021 | ||
1022 | static int macb_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1023 | { | |
1024 | struct macb *bp = netdev_priv(dev); | |
6c36a707 | 1025 | struct phy_device *phydev = bp->phy_dev; |
89e5785f | 1026 | |
6c36a707 R |
1027 | if (!phydev) |
1028 | return -ENODEV; | |
1029 | ||
1030 | return phy_ethtool_sset(phydev, cmd); | |
89e5785f HS |
1031 | } |
1032 | ||
6c36a707 R |
1033 | static void macb_get_drvinfo(struct net_device *dev, |
1034 | struct ethtool_drvinfo *info) | |
89e5785f HS |
1035 | { |
1036 | struct macb *bp = netdev_priv(dev); | |
1037 | ||
1038 | strcpy(info->driver, bp->pdev->dev.driver->name); | |
1039 | strcpy(info->version, "$Revision: 1.14 $"); | |
1040 | strcpy(info->bus_info, bp->pdev->dev.bus_id); | |
1041 | } | |
1042 | ||
89e5785f HS |
1043 | static struct ethtool_ops macb_ethtool_ops = { |
1044 | .get_settings = macb_get_settings, | |
1045 | .set_settings = macb_set_settings, | |
1046 | .get_drvinfo = macb_get_drvinfo, | |
89e5785f HS |
1047 | .get_link = ethtool_op_get_link, |
1048 | }; | |
1049 | ||
1050 | static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
1051 | { | |
1052 | struct macb *bp = netdev_priv(dev); | |
6c36a707 | 1053 | struct phy_device *phydev = bp->phy_dev; |
89e5785f HS |
1054 | |
1055 | if (!netif_running(dev)) | |
1056 | return -EINVAL; | |
1057 | ||
6c36a707 R |
1058 | if (!phydev) |
1059 | return -ENODEV; | |
89e5785f | 1060 | |
6c36a707 | 1061 | return phy_mii_ioctl(phydev, if_mii(rq), cmd); |
89e5785f HS |
1062 | } |
1063 | ||
89e5785f HS |
1064 | static int __devinit macb_probe(struct platform_device *pdev) |
1065 | { | |
1066 | struct eth_platform_data *pdata; | |
1067 | struct resource *regs; | |
1068 | struct net_device *dev; | |
1069 | struct macb *bp; | |
6c36a707 | 1070 | struct phy_device *phydev; |
89e5785f HS |
1071 | unsigned long pclk_hz; |
1072 | u32 config; | |
1073 | int err = -ENXIO; | |
1074 | ||
1075 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1076 | if (!regs) { | |
1077 | dev_err(&pdev->dev, "no mmio resource defined\n"); | |
1078 | goto err_out; | |
1079 | } | |
1080 | ||
1081 | err = -ENOMEM; | |
1082 | dev = alloc_etherdev(sizeof(*bp)); | |
1083 | if (!dev) { | |
1084 | dev_err(&pdev->dev, "etherdev alloc failed, aborting.\n"); | |
1085 | goto err_out; | |
1086 | } | |
1087 | ||
1088 | SET_MODULE_OWNER(dev); | |
1089 | SET_NETDEV_DEV(dev, &pdev->dev); | |
1090 | ||
1091 | /* TODO: Actually, we have some interesting features... */ | |
1092 | dev->features |= 0; | |
1093 | ||
1094 | bp = netdev_priv(dev); | |
1095 | bp->pdev = pdev; | |
1096 | bp->dev = dev; | |
1097 | ||
1098 | spin_lock_init(&bp->lock); | |
1099 | ||
0cc8674f AV |
1100 | #if defined(CONFIG_ARCH_AT91) |
1101 | bp->pclk = clk_get(&pdev->dev, "macb_clk"); | |
1102 | if (IS_ERR(bp->pclk)) { | |
1103 | dev_err(&pdev->dev, "failed to get macb_clk\n"); | |
1104 | goto err_out_free_dev; | |
1105 | } | |
1106 | clk_enable(bp->pclk); | |
1107 | #else | |
89e5785f HS |
1108 | bp->pclk = clk_get(&pdev->dev, "pclk"); |
1109 | if (IS_ERR(bp->pclk)) { | |
1110 | dev_err(&pdev->dev, "failed to get pclk\n"); | |
1111 | goto err_out_free_dev; | |
1112 | } | |
1113 | bp->hclk = clk_get(&pdev->dev, "hclk"); | |
1114 | if (IS_ERR(bp->hclk)) { | |
1115 | dev_err(&pdev->dev, "failed to get hclk\n"); | |
1116 | goto err_out_put_pclk; | |
1117 | } | |
1118 | ||
1119 | clk_enable(bp->pclk); | |
1120 | clk_enable(bp->hclk); | |
0cc8674f | 1121 | #endif |
89e5785f HS |
1122 | |
1123 | bp->regs = ioremap(regs->start, regs->end - regs->start + 1); | |
1124 | if (!bp->regs) { | |
1125 | dev_err(&pdev->dev, "failed to map registers, aborting.\n"); | |
1126 | err = -ENOMEM; | |
1127 | goto err_out_disable_clocks; | |
1128 | } | |
1129 | ||
1130 | dev->irq = platform_get_irq(pdev, 0); | |
38515e90 | 1131 | err = request_irq(dev->irq, macb_interrupt, IRQF_SAMPLE_RANDOM, |
89e5785f HS |
1132 | dev->name, dev); |
1133 | if (err) { | |
1134 | printk(KERN_ERR | |
1135 | "%s: Unable to request IRQ %d (error %d)\n", | |
1136 | dev->name, dev->irq, err); | |
1137 | goto err_out_iounmap; | |
1138 | } | |
1139 | ||
1140 | dev->open = macb_open; | |
1141 | dev->stop = macb_close; | |
1142 | dev->hard_start_xmit = macb_start_xmit; | |
1143 | dev->get_stats = macb_get_stats; | |
446ebd01 | 1144 | dev->set_multicast_list = macb_set_rx_mode; |
89e5785f | 1145 | dev->do_ioctl = macb_ioctl; |
bea3348e | 1146 | netif_napi_add(dev, &bp->napi, macb_poll, 64); |
89e5785f HS |
1147 | dev->ethtool_ops = &macb_ethtool_ops; |
1148 | ||
1149 | dev->base_addr = regs->start; | |
1150 | ||
89e5785f HS |
1151 | /* Set MII management clock divider */ |
1152 | pclk_hz = clk_get_rate(bp->pclk); | |
1153 | if (pclk_hz <= 20000000) | |
1154 | config = MACB_BF(CLK, MACB_CLK_DIV8); | |
1155 | else if (pclk_hz <= 40000000) | |
1156 | config = MACB_BF(CLK, MACB_CLK_DIV16); | |
1157 | else if (pclk_hz <= 80000000) | |
1158 | config = MACB_BF(CLK, MACB_CLK_DIV32); | |
1159 | else | |
1160 | config = MACB_BF(CLK, MACB_CLK_DIV64); | |
1161 | macb_writel(bp, NCFGR, config); | |
1162 | ||
89e5785f | 1163 | macb_get_hwaddr(bp); |
89e5785f | 1164 | pdata = pdev->dev.platform_data; |
6c36a707 | 1165 | |
89e5785f | 1166 | if (pdata && pdata->is_rmii) |
0cc8674f AV |
1167 | #if defined(CONFIG_ARCH_AT91) |
1168 | macb_writel(bp, USRIO, (MACB_BIT(RMII) | MACB_BIT(CLKEN)) ); | |
1169 | #else | |
89e5785f | 1170 | macb_writel(bp, USRIO, 0); |
0cc8674f | 1171 | #endif |
89e5785f | 1172 | else |
0cc8674f AV |
1173 | #if defined(CONFIG_ARCH_AT91) |
1174 | macb_writel(bp, USRIO, MACB_BIT(CLKEN)); | |
1175 | #else | |
89e5785f | 1176 | macb_writel(bp, USRIO, MACB_BIT(MII)); |
0cc8674f | 1177 | #endif |
89e5785f HS |
1178 | |
1179 | bp->tx_pending = DEF_TX_RING_PENDING; | |
1180 | ||
1181 | err = register_netdev(dev); | |
1182 | if (err) { | |
1183 | dev_err(&pdev->dev, "Cannot register net device, aborting.\n"); | |
1184 | goto err_out_free_irq; | |
1185 | } | |
1186 | ||
6c36a707 R |
1187 | if (macb_mii_init(bp) != 0) { |
1188 | goto err_out_unregister_netdev; | |
1189 | } | |
89e5785f | 1190 | |
6c36a707 | 1191 | platform_set_drvdata(pdev, dev); |
89e5785f HS |
1192 | |
1193 | printk(KERN_INFO "%s: Atmel MACB at 0x%08lx irq %d " | |
1194 | "(%02x:%02x:%02x:%02x:%02x:%02x)\n", | |
1195 | dev->name, dev->base_addr, dev->irq, | |
1196 | dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2], | |
1197 | dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]); | |
1198 | ||
6c36a707 R |
1199 | phydev = bp->phy_dev; |
1200 | printk(KERN_INFO "%s: attached PHY driver [%s] " | |
1201 | "(mii_bus:phy_addr=%s, irq=%d)\n", | |
1202 | dev->name, phydev->drv->name, phydev->dev.bus_id, phydev->irq); | |
1203 | ||
89e5785f HS |
1204 | return 0; |
1205 | ||
6c36a707 R |
1206 | err_out_unregister_netdev: |
1207 | unregister_netdev(dev); | |
89e5785f HS |
1208 | err_out_free_irq: |
1209 | free_irq(dev->irq, dev); | |
1210 | err_out_iounmap: | |
1211 | iounmap(bp->regs); | |
1212 | err_out_disable_clocks: | |
0cc8674f | 1213 | #ifndef CONFIG_ARCH_AT91 |
89e5785f | 1214 | clk_disable(bp->hclk); |
89e5785f | 1215 | clk_put(bp->hclk); |
0cc8674f AV |
1216 | #endif |
1217 | clk_disable(bp->pclk); | |
6c36a707 | 1218 | #ifndef CONFIG_ARCH_AT91 |
89e5785f | 1219 | err_out_put_pclk: |
6c36a707 | 1220 | #endif |
89e5785f HS |
1221 | clk_put(bp->pclk); |
1222 | err_out_free_dev: | |
1223 | free_netdev(dev); | |
1224 | err_out: | |
1225 | platform_set_drvdata(pdev, NULL); | |
1226 | return err; | |
1227 | } | |
1228 | ||
1229 | static int __devexit macb_remove(struct platform_device *pdev) | |
1230 | { | |
1231 | struct net_device *dev; | |
1232 | struct macb *bp; | |
1233 | ||
1234 | dev = platform_get_drvdata(pdev); | |
1235 | ||
1236 | if (dev) { | |
1237 | bp = netdev_priv(dev); | |
6c36a707 R |
1238 | mdiobus_unregister(&bp->mii_bus); |
1239 | kfree(bp->mii_bus.irq); | |
89e5785f HS |
1240 | unregister_netdev(dev); |
1241 | free_irq(dev->irq, dev); | |
1242 | iounmap(bp->regs); | |
0cc8674f | 1243 | #ifndef CONFIG_ARCH_AT91 |
89e5785f | 1244 | clk_disable(bp->hclk); |
89e5785f | 1245 | clk_put(bp->hclk); |
0cc8674f AV |
1246 | #endif |
1247 | clk_disable(bp->pclk); | |
89e5785f HS |
1248 | clk_put(bp->pclk); |
1249 | free_netdev(dev); | |
1250 | platform_set_drvdata(pdev, NULL); | |
1251 | } | |
1252 | ||
1253 | return 0; | |
1254 | } | |
1255 | ||
1256 | static struct platform_driver macb_driver = { | |
1257 | .probe = macb_probe, | |
1258 | .remove = __devexit_p(macb_remove), | |
1259 | .driver = { | |
1260 | .name = "macb", | |
1261 | }, | |
1262 | }; | |
1263 | ||
1264 | static int __init macb_init(void) | |
1265 | { | |
1266 | return platform_driver_register(&macb_driver); | |
1267 | } | |
1268 | ||
1269 | static void __exit macb_exit(void) | |
1270 | { | |
1271 | platform_driver_unregister(&macb_driver); | |
1272 | } | |
1273 | ||
1274 | module_init(macb_init); | |
1275 | module_exit(macb_exit); | |
1276 | ||
1277 | MODULE_LICENSE("GPL"); | |
1278 | MODULE_DESCRIPTION("Atmel MACB Ethernet driver"); | |
1279 | MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>"); |