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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Driver for the Macintosh 68K onboard MACE controller with PSC | |
3 | * driven DMA. The MACE driver code is derived from mace.c. The | |
4 | * Mac68k theory of operation is courtesy of the MacBSD wizards. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * Copyright (C) 1996 Paul Mackerras. | |
12 | * Copyright (C) 1998 Alan Cox <alan@redhat.com> | |
13 | * | |
14 | * Modified heavily by Joshua M. Thompson based on Dave Huang's NetBSD driver | |
8b6aaab8 FT |
15 | * |
16 | * Copyright (C) 2007 Finn Thain | |
17 | * | |
18 | * Converted to DMA API, converted to unified driver model, | |
19 | * sync'd some routines with mace.c and fixed various bugs. | |
1da177e4 LT |
20 | */ |
21 | ||
22 | ||
23 | #include <linux/kernel.h> | |
24 | #include <linux/module.h> | |
25 | #include <linux/netdevice.h> | |
26 | #include <linux/etherdevice.h> | |
27 | #include <linux/delay.h> | |
28 | #include <linux/string.h> | |
29 | #include <linux/crc32.h> | |
bc63eb9c | 30 | #include <linux/bitrev.h> |
8b6aaab8 FT |
31 | #include <linux/dma-mapping.h> |
32 | #include <linux/platform_device.h> | |
1da177e4 | 33 | #include <asm/io.h> |
1da177e4 LT |
34 | #include <asm/irq.h> |
35 | #include <asm/macintosh.h> | |
36 | #include <asm/macints.h> | |
37 | #include <asm/mac_psc.h> | |
38 | #include <asm/page.h> | |
39 | #include "mace.h" | |
40 | ||
8b6aaab8 FT |
41 | static char mac_mace_string[] = "macmace"; |
42 | static struct platform_device *mac_mace_device; | |
43 | ||
44 | #define N_TX_BUFF_ORDER 0 | |
45 | #define N_TX_RING (1 << N_TX_BUFF_ORDER) | |
46 | #define N_RX_BUFF_ORDER 3 | |
47 | #define N_RX_RING (1 << N_RX_BUFF_ORDER) | |
48 | ||
1da177e4 LT |
49 | #define TX_TIMEOUT HZ |
50 | ||
8b6aaab8 FT |
51 | #define MACE_BUFF_SIZE 0x800 |
52 | ||
53 | /* Chip rev needs workaround on HW & multicast addr change */ | |
54 | #define BROKEN_ADDRCHG_REV 0x0941 | |
1da177e4 LT |
55 | |
56 | /* The MACE is simply wired down on a Mac68K box */ | |
57 | ||
58 | #define MACE_BASE (void *)(0x50F1C000) | |
59 | #define MACE_PROM (void *)(0x50F08001) | |
60 | ||
61 | struct mace_data { | |
62 | volatile struct mace *mace; | |
8b6aaab8 FT |
63 | unsigned char *tx_ring; |
64 | dma_addr_t tx_ring_phys; | |
65 | unsigned char *rx_ring; | |
66 | dma_addr_t rx_ring_phys; | |
1da177e4 LT |
67 | int dma_intr; |
68 | struct net_device_stats stats; | |
69 | int rx_slot, rx_tail; | |
70 | int tx_slot, tx_sloti, tx_count; | |
8b6aaab8 FT |
71 | int chipid; |
72 | struct device *device; | |
1da177e4 LT |
73 | }; |
74 | ||
75 | struct mace_frame { | |
8b6aaab8 FT |
76 | u8 rcvcnt; |
77 | u8 pad1; | |
78 | u8 rcvsts; | |
79 | u8 pad2; | |
80 | u8 rntpc; | |
81 | u8 pad3; | |
82 | u8 rcvcc; | |
83 | u8 pad4; | |
84 | u32 pad5; | |
85 | u32 pad6; | |
6aa20a22 | 86 | u8 data[1]; |
1da177e4 LT |
87 | /* And frame continues.. */ |
88 | }; | |
89 | ||
90 | #define PRIV_BYTES sizeof(struct mace_data) | |
91 | ||
1da177e4 LT |
92 | static int mace_open(struct net_device *dev); |
93 | static int mace_close(struct net_device *dev); | |
94 | static int mace_xmit_start(struct sk_buff *skb, struct net_device *dev); | |
95 | static struct net_device_stats *mace_stats(struct net_device *dev); | |
96 | static void mace_set_multicast(struct net_device *dev); | |
97 | static int mace_set_address(struct net_device *dev, void *addr); | |
8b6aaab8 | 98 | static void mace_reset(struct net_device *dev); |
7d12e780 DH |
99 | static irqreturn_t mace_interrupt(int irq, void *dev_id); |
100 | static irqreturn_t mace_dma_intr(int irq, void *dev_id); | |
1da177e4 | 101 | static void mace_tx_timeout(struct net_device *dev); |
8b6aaab8 | 102 | static void __mace_set_address(struct net_device *dev, void *addr); |
1da177e4 | 103 | |
1da177e4 LT |
104 | /* |
105 | * Load a receive DMA channel with a base address and ring length | |
106 | */ | |
107 | ||
108 | static void mace_load_rxdma_base(struct net_device *dev, int set) | |
109 | { | |
8b6aaab8 | 110 | struct mace_data *mp = netdev_priv(dev); |
1da177e4 LT |
111 | |
112 | psc_write_word(PSC_ENETRD_CMD + set, 0x0100); | |
113 | psc_write_long(PSC_ENETRD_ADDR + set, (u32) mp->rx_ring_phys); | |
114 | psc_write_long(PSC_ENETRD_LEN + set, N_RX_RING); | |
115 | psc_write_word(PSC_ENETRD_CMD + set, 0x9800); | |
116 | mp->rx_tail = 0; | |
117 | } | |
118 | ||
119 | /* | |
120 | * Reset the receive DMA subsystem | |
121 | */ | |
122 | ||
123 | static void mace_rxdma_reset(struct net_device *dev) | |
124 | { | |
8b6aaab8 | 125 | struct mace_data *mp = netdev_priv(dev); |
1da177e4 LT |
126 | volatile struct mace *mace = mp->mace; |
127 | u8 maccc = mace->maccc; | |
6aa20a22 | 128 | |
1da177e4 | 129 | mace->maccc = maccc & ~ENRCV; |
6aa20a22 | 130 | |
1da177e4 LT |
131 | psc_write_word(PSC_ENETRD_CTL, 0x8800); |
132 | mace_load_rxdma_base(dev, 0x00); | |
133 | psc_write_word(PSC_ENETRD_CTL, 0x0400); | |
6aa20a22 | 134 | |
1da177e4 LT |
135 | psc_write_word(PSC_ENETRD_CTL, 0x8800); |
136 | mace_load_rxdma_base(dev, 0x10); | |
137 | psc_write_word(PSC_ENETRD_CTL, 0x0400); | |
6aa20a22 | 138 | |
1da177e4 LT |
139 | mace->maccc = maccc; |
140 | mp->rx_slot = 0; | |
141 | ||
142 | psc_write_word(PSC_ENETRD_CMD + PSC_SET0, 0x9800); | |
143 | psc_write_word(PSC_ENETRD_CMD + PSC_SET1, 0x9800); | |
144 | } | |
145 | ||
146 | /* | |
147 | * Reset the transmit DMA subsystem | |
148 | */ | |
6aa20a22 | 149 | |
1da177e4 LT |
150 | static void mace_txdma_reset(struct net_device *dev) |
151 | { | |
8b6aaab8 | 152 | struct mace_data *mp = netdev_priv(dev); |
1da177e4 LT |
153 | volatile struct mace *mace = mp->mace; |
154 | u8 maccc; | |
155 | ||
156 | psc_write_word(PSC_ENETWR_CTL, 0x8800); | |
157 | ||
158 | maccc = mace->maccc; | |
159 | mace->maccc = maccc & ~ENXMT; | |
160 | ||
161 | mp->tx_slot = mp->tx_sloti = 0; | |
162 | mp->tx_count = N_TX_RING; | |
163 | ||
164 | psc_write_word(PSC_ENETWR_CTL, 0x0400); | |
165 | mace->maccc = maccc; | |
166 | } | |
167 | ||
168 | /* | |
169 | * Disable DMA | |
170 | */ | |
6aa20a22 | 171 | |
1da177e4 LT |
172 | static void mace_dma_off(struct net_device *dev) |
173 | { | |
174 | psc_write_word(PSC_ENETRD_CTL, 0x8800); | |
175 | psc_write_word(PSC_ENETRD_CTL, 0x1000); | |
176 | psc_write_word(PSC_ENETRD_CMD + PSC_SET0, 0x1100); | |
177 | psc_write_word(PSC_ENETRD_CMD + PSC_SET1, 0x1100); | |
178 | ||
179 | psc_write_word(PSC_ENETWR_CTL, 0x8800); | |
180 | psc_write_word(PSC_ENETWR_CTL, 0x1000); | |
181 | psc_write_word(PSC_ENETWR_CMD + PSC_SET0, 0x1100); | |
182 | psc_write_word(PSC_ENETWR_CMD + PSC_SET1, 0x1100); | |
183 | } | |
184 | ||
185 | /* | |
186 | * Not really much of a probe. The hardware table tells us if this | |
187 | * model of Macintrash has a MACE (AV macintoshes) | |
188 | */ | |
6aa20a22 | 189 | |
8b6aaab8 | 190 | static int __devinit mace_probe(struct platform_device *pdev) |
1da177e4 LT |
191 | { |
192 | int j; | |
193 | struct mace_data *mp; | |
194 | unsigned char *addr; | |
195 | struct net_device *dev; | |
196 | unsigned char checksum = 0; | |
197 | static int found = 0; | |
198 | int err; | |
6aa20a22 | 199 | |
1da177e4 | 200 | if (found || macintosh_config->ether_type != MAC_ETHER_MACE) |
8b6aaab8 | 201 | return -ENODEV; |
1da177e4 LT |
202 | |
203 | found = 1; /* prevent 'finding' one on every device probe */ | |
204 | ||
205 | dev = alloc_etherdev(PRIV_BYTES); | |
206 | if (!dev) | |
8b6aaab8 | 207 | return -ENOMEM; |
1da177e4 | 208 | |
8b6aaab8 FT |
209 | mp = netdev_priv(dev); |
210 | ||
211 | mp->device = &pdev->dev; | |
212 | SET_NETDEV_DEV(dev, &pdev->dev); | |
213 | SET_MODULE_OWNER(dev); | |
1da177e4 | 214 | |
1da177e4 LT |
215 | dev->base_addr = (u32)MACE_BASE; |
216 | mp->mace = (volatile struct mace *) MACE_BASE; | |
6aa20a22 | 217 | |
1da177e4 LT |
218 | dev->irq = IRQ_MAC_MACE; |
219 | mp->dma_intr = IRQ_MAC_MACE_DMA; | |
220 | ||
8b6aaab8 FT |
221 | mp->chipid = mp->mace->chipid_hi << 8 | mp->mace->chipid_lo; |
222 | ||
1da177e4 LT |
223 | /* |
224 | * The PROM contains 8 bytes which total 0xFF when XOR'd | |
225 | * together. Due to the usual peculiar apple brain damage | |
226 | * the bytes are spaced out in a strange boundary and the | |
227 | * bits are reversed. | |
228 | */ | |
229 | ||
230 | addr = (void *)MACE_PROM; | |
6aa20a22 | 231 | |
1da177e4 | 232 | for (j = 0; j < 6; ++j) { |
bc63eb9c | 233 | u8 v = bitrev8(addr[j<<4]); |
1da177e4 LT |
234 | checksum ^= v; |
235 | dev->dev_addr[j] = v; | |
236 | } | |
237 | for (; j < 8; ++j) { | |
bc63eb9c | 238 | checksum ^= bitrev8(addr[j<<4]); |
1da177e4 | 239 | } |
6aa20a22 | 240 | |
1da177e4 LT |
241 | if (checksum != 0xFF) { |
242 | free_netdev(dev); | |
8b6aaab8 | 243 | return -ENODEV; |
1da177e4 LT |
244 | } |
245 | ||
246 | memset(&mp->stats, 0, sizeof(mp->stats)); | |
247 | ||
248 | dev->open = mace_open; | |
249 | dev->stop = mace_close; | |
250 | dev->hard_start_xmit = mace_xmit_start; | |
251 | dev->tx_timeout = mace_tx_timeout; | |
252 | dev->watchdog_timeo = TX_TIMEOUT; | |
253 | dev->get_stats = mace_stats; | |
254 | dev->set_multicast_list = mace_set_multicast; | |
255 | dev->set_mac_address = mace_set_address; | |
256 | ||
257 | printk(KERN_INFO "%s: 68K MACE, hardware address %.2X", dev->name, dev->dev_addr[0]); | |
258 | for (j = 1 ; j < 6 ; j++) printk(":%.2X", dev->dev_addr[j]); | |
259 | printk("\n"); | |
260 | ||
261 | err = register_netdev(dev); | |
262 | if (!err) | |
8b6aaab8 | 263 | return 0; |
1da177e4 LT |
264 | |
265 | free_netdev(dev); | |
8b6aaab8 FT |
266 | return err; |
267 | } | |
268 | ||
269 | /* | |
270 | * Reset the chip. | |
271 | */ | |
272 | ||
273 | static void mace_reset(struct net_device *dev) | |
274 | { | |
275 | struct mace_data *mp = netdev_priv(dev); | |
276 | volatile struct mace *mb = mp->mace; | |
277 | int i; | |
278 | ||
279 | /* soft-reset the chip */ | |
280 | i = 200; | |
281 | while (--i) { | |
282 | mb->biucc = SWRST; | |
283 | if (mb->biucc & SWRST) { | |
284 | udelay(10); | |
285 | continue; | |
286 | } | |
287 | break; | |
288 | } | |
289 | if (!i) { | |
290 | printk(KERN_ERR "macmace: cannot reset chip!\n"); | |
291 | return; | |
292 | } | |
293 | ||
294 | mb->maccc = 0; /* turn off tx, rx */ | |
295 | mb->imr = 0xFF; /* disable all intrs for now */ | |
296 | i = mb->ir; | |
297 | ||
298 | mb->biucc = XMTSP_64; | |
299 | mb->utr = RTRD; | |
300 | mb->fifocc = XMTFW_8 | RCVFW_64 | XMTFWU | RCVFWU; | |
301 | ||
302 | mb->xmtfc = AUTO_PAD_XMIT; /* auto-pad short frames */ | |
303 | mb->rcvfc = 0; | |
304 | ||
305 | /* load up the hardware address */ | |
306 | __mace_set_address(dev, dev->dev_addr); | |
307 | ||
308 | /* clear the multicast filter */ | |
309 | if (mp->chipid == BROKEN_ADDRCHG_REV) | |
310 | mb->iac = LOGADDR; | |
311 | else { | |
312 | mb->iac = ADDRCHG | LOGADDR; | |
313 | while ((mb->iac & ADDRCHG) != 0) | |
314 | ; | |
315 | } | |
316 | for (i = 0; i < 8; ++i) | |
317 | mb->ladrf = 0; | |
318 | ||
319 | /* done changing address */ | |
320 | if (mp->chipid != BROKEN_ADDRCHG_REV) | |
321 | mb->iac = 0; | |
322 | ||
323 | mb->plscc = PORTSEL_AUI; | |
1da177e4 LT |
324 | } |
325 | ||
326 | /* | |
327 | * Load the address on a mace controller. | |
328 | */ | |
329 | ||
8b6aaab8 | 330 | static void __mace_set_address(struct net_device *dev, void *addr) |
1da177e4 | 331 | { |
8b6aaab8 | 332 | struct mace_data *mp = netdev_priv(dev); |
1da177e4 | 333 | volatile struct mace *mb = mp->mace; |
8b6aaab8 | 334 | unsigned char *p = addr; |
1da177e4 | 335 | int i; |
8b6aaab8 FT |
336 | |
337 | /* load up the hardware address */ | |
338 | if (mp->chipid == BROKEN_ADDRCHG_REV) | |
339 | mb->iac = PHYADDR; | |
340 | else { | |
341 | mb->iac = ADDRCHG | PHYADDR; | |
342 | while ((mb->iac & ADDRCHG) != 0) | |
343 | ; | |
344 | } | |
345 | for (i = 0; i < 6; ++i) | |
346 | mb->padr = dev->dev_addr[i] = p[i]; | |
347 | if (mp->chipid != BROKEN_ADDRCHG_REV) | |
348 | mb->iac = 0; | |
349 | } | |
350 | ||
351 | static int mace_set_address(struct net_device *dev, void *addr) | |
352 | { | |
353 | struct mace_data *mp = netdev_priv(dev); | |
354 | volatile struct mace *mb = mp->mace; | |
1da177e4 LT |
355 | unsigned long flags; |
356 | u8 maccc; | |
357 | ||
358 | local_irq_save(flags); | |
359 | ||
360 | maccc = mb->maccc; | |
361 | ||
8b6aaab8 | 362 | __mace_set_address(dev, addr); |
1da177e4 LT |
363 | |
364 | mb->maccc = maccc; | |
8b6aaab8 | 365 | |
1da177e4 LT |
366 | local_irq_restore(flags); |
367 | ||
368 | return 0; | |
369 | } | |
370 | ||
371 | /* | |
372 | * Open the Macintosh MACE. Most of this is playing with the DMA | |
373 | * engine. The ethernet chip is quite friendly. | |
374 | */ | |
6aa20a22 | 375 | |
1da177e4 LT |
376 | static int mace_open(struct net_device *dev) |
377 | { | |
8b6aaab8 | 378 | struct mace_data *mp = netdev_priv(dev); |
1da177e4 | 379 | volatile struct mace *mb = mp->mace; |
1da177e4 | 380 | |
8b6aaab8 FT |
381 | /* reset the chip */ |
382 | mace_reset(dev); | |
1da177e4 LT |
383 | |
384 | if (request_irq(dev->irq, mace_interrupt, 0, dev->name, dev)) { | |
385 | printk(KERN_ERR "%s: can't get irq %d\n", dev->name, dev->irq); | |
386 | return -EAGAIN; | |
387 | } | |
388 | if (request_irq(mp->dma_intr, mace_dma_intr, 0, dev->name, dev)) { | |
389 | printk(KERN_ERR "%s: can't get irq %d\n", dev->name, mp->dma_intr); | |
390 | free_irq(dev->irq, dev); | |
391 | return -EAGAIN; | |
392 | } | |
393 | ||
394 | /* Allocate the DMA ring buffers */ | |
395 | ||
8b6aaab8 FT |
396 | mp->tx_ring = dma_alloc_coherent(mp->device, |
397 | N_TX_RING * MACE_BUFF_SIZE, | |
398 | &mp->tx_ring_phys, GFP_KERNEL); | |
399 | if (mp->tx_ring == NULL) { | |
400 | printk(KERN_ERR "%s: unable to allocate DMA tx buffers\n", dev->name); | |
401 | goto out1; | |
1da177e4 LT |
402 | } |
403 | ||
8b6aaab8 FT |
404 | mp->rx_ring = dma_alloc_coherent(mp->device, |
405 | N_RX_RING * MACE_BUFF_SIZE, | |
406 | &mp->rx_ring_phys, GFP_KERNEL); | |
407 | if (mp->rx_ring == NULL) { | |
408 | printk(KERN_ERR "%s: unable to allocate DMA rx buffers\n", dev->name); | |
409 | goto out2; | |
410 | } | |
1da177e4 LT |
411 | |
412 | mace_dma_off(dev); | |
413 | ||
414 | /* Not sure what these do */ | |
415 | ||
416 | psc_write_word(PSC_ENETWR_CTL, 0x9000); | |
417 | psc_write_word(PSC_ENETRD_CTL, 0x9000); | |
418 | psc_write_word(PSC_ENETWR_CTL, 0x0400); | |
419 | psc_write_word(PSC_ENETRD_CTL, 0x0400); | |
420 | ||
1da177e4 LT |
421 | mace_rxdma_reset(dev); |
422 | mace_txdma_reset(dev); | |
6aa20a22 | 423 | |
8b6aaab8 FT |
424 | /* turn it on! */ |
425 | mb->maccc = ENXMT | ENRCV; | |
426 | /* enable all interrupts except receive interrupts */ | |
427 | mb->imr = RCVINT; | |
1da177e4 | 428 | return 0; |
8b6aaab8 FT |
429 | |
430 | out2: | |
431 | dma_free_coherent(mp->device, N_TX_RING * MACE_BUFF_SIZE, | |
432 | mp->tx_ring, mp->tx_ring_phys); | |
433 | out1: | |
434 | free_irq(dev->irq, dev); | |
435 | free_irq(mp->dma_intr, dev); | |
436 | return -ENOMEM; | |
1da177e4 LT |
437 | } |
438 | ||
439 | /* | |
440 | * Shut down the mace and its interrupt channel | |
441 | */ | |
6aa20a22 | 442 | |
1da177e4 LT |
443 | static int mace_close(struct net_device *dev) |
444 | { | |
8b6aaab8 | 445 | struct mace_data *mp = netdev_priv(dev); |
1da177e4 LT |
446 | volatile struct mace *mb = mp->mace; |
447 | ||
448 | mb->maccc = 0; /* disable rx and tx */ | |
449 | mb->imr = 0xFF; /* disable all irqs */ | |
450 | mace_dma_off(dev); /* disable rx and tx dma */ | |
451 | ||
1da177e4 LT |
452 | return 0; |
453 | } | |
454 | ||
455 | /* | |
456 | * Transmit a frame | |
457 | */ | |
6aa20a22 | 458 | |
1da177e4 LT |
459 | static int mace_xmit_start(struct sk_buff *skb, struct net_device *dev) |
460 | { | |
8b6aaab8 FT |
461 | struct mace_data *mp = netdev_priv(dev); |
462 | unsigned long flags; | |
1da177e4 | 463 | |
8b6aaab8 | 464 | /* Stop the queue since there's only the one buffer */ |
1da177e4 | 465 | |
8b6aaab8 FT |
466 | local_irq_save(flags); |
467 | netif_stop_queue(dev); | |
1da177e4 | 468 | if (!mp->tx_count) { |
8b6aaab8 FT |
469 | printk(KERN_ERR "macmace: tx queue running but no free buffers.\n"); |
470 | local_irq_restore(flags); | |
471 | return NETDEV_TX_BUSY; | |
1da177e4 LT |
472 | } |
473 | mp->tx_count--; | |
8b6aaab8 | 474 | local_irq_restore(flags); |
6aa20a22 | 475 | |
1da177e4 LT |
476 | mp->stats.tx_packets++; |
477 | mp->stats.tx_bytes += skb->len; | |
478 | ||
479 | /* We need to copy into our xmit buffer to take care of alignment and caching issues */ | |
d626f62b | 480 | skb_copy_from_linear_data(skb, mp->tx_ring, skb->len); |
1da177e4 LT |
481 | |
482 | /* load the Tx DMA and fire it off */ | |
483 | ||
484 | psc_write_long(PSC_ENETWR_ADDR + mp->tx_slot, (u32) mp->tx_ring_phys); | |
485 | psc_write_long(PSC_ENETWR_LEN + mp->tx_slot, skb->len); | |
486 | psc_write_word(PSC_ENETWR_CMD + mp->tx_slot, 0x9800); | |
487 | ||
488 | mp->tx_slot ^= 0x10; | |
489 | ||
490 | dev_kfree_skb(skb); | |
491 | ||
8b6aaab8 FT |
492 | dev->trans_start = jiffies; |
493 | return NETDEV_TX_OK; | |
1da177e4 LT |
494 | } |
495 | ||
496 | static struct net_device_stats *mace_stats(struct net_device *dev) | |
497 | { | |
8b6aaab8 FT |
498 | struct mace_data *mp = netdev_priv(dev); |
499 | return &mp->stats; | |
1da177e4 LT |
500 | } |
501 | ||
502 | static void mace_set_multicast(struct net_device *dev) | |
503 | { | |
8b6aaab8 | 504 | struct mace_data *mp = netdev_priv(dev); |
1da177e4 LT |
505 | volatile struct mace *mb = mp->mace; |
506 | int i, j; | |
507 | u32 crc; | |
508 | u8 maccc; | |
8b6aaab8 | 509 | unsigned long flags; |
1da177e4 | 510 | |
8b6aaab8 | 511 | local_irq_save(flags); |
1da177e4 LT |
512 | maccc = mb->maccc; |
513 | mb->maccc &= ~PROM; | |
514 | ||
515 | if (dev->flags & IFF_PROMISC) { | |
516 | mb->maccc |= PROM; | |
517 | } else { | |
518 | unsigned char multicast_filter[8]; | |
519 | struct dev_mc_list *dmi = dev->mc_list; | |
520 | ||
521 | if (dev->flags & IFF_ALLMULTI) { | |
522 | for (i = 0; i < 8; i++) { | |
523 | multicast_filter[i] = 0xFF; | |
524 | } | |
525 | } else { | |
526 | for (i = 0; i < 8; i++) | |
527 | multicast_filter[i] = 0; | |
528 | for (i = 0; i < dev->mc_count; i++) { | |
529 | crc = ether_crc_le(6, dmi->dmi_addr); | |
530 | j = crc >> 26; /* bit number in multicast_filter */ | |
531 | multicast_filter[j >> 3] |= 1 << (j & 7); | |
532 | dmi = dmi->next; | |
533 | } | |
534 | } | |
535 | ||
8b6aaab8 FT |
536 | if (mp->chipid == BROKEN_ADDRCHG_REV) |
537 | mb->iac = LOGADDR; | |
538 | else { | |
539 | mb->iac = ADDRCHG | LOGADDR; | |
540 | while ((mb->iac & ADDRCHG) != 0) | |
541 | ; | |
1da177e4 | 542 | } |
8b6aaab8 FT |
543 | for (i = 0; i < 8; ++i) |
544 | mb->ladrf = multicast_filter[i]; | |
545 | if (mp->chipid != BROKEN_ADDRCHG_REV) | |
546 | mb->iac = 0; | |
1da177e4 LT |
547 | } |
548 | ||
549 | mb->maccc = maccc; | |
8b6aaab8 | 550 | local_irq_restore(flags); |
1da177e4 LT |
551 | } |
552 | ||
1da177e4 LT |
553 | static void mace_handle_misc_intrs(struct mace_data *mp, int intr) |
554 | { | |
555 | volatile struct mace *mb = mp->mace; | |
556 | static int mace_babbles, mace_jabbers; | |
557 | ||
8b6aaab8 | 558 | if (intr & MPCO) |
1da177e4 | 559 | mp->stats.rx_missed_errors += 256; |
8b6aaab8 FT |
560 | mp->stats.rx_missed_errors += mb->mpc; /* reading clears it */ |
561 | if (intr & RNTPCO) | |
1da177e4 | 562 | mp->stats.rx_length_errors += 256; |
8b6aaab8 FT |
563 | mp->stats.rx_length_errors += mb->rntpc; /* reading clears it */ |
564 | if (intr & CERR) | |
1da177e4 | 565 | ++mp->stats.tx_heartbeat_errors; |
8b6aaab8 FT |
566 | if (intr & BABBLE) |
567 | if (mace_babbles++ < 4) | |
568 | printk(KERN_DEBUG "macmace: babbling transmitter\n"); | |
569 | if (intr & JABBER) | |
570 | if (mace_jabbers++ < 4) | |
571 | printk(KERN_DEBUG "macmace: jabbering transceiver\n"); | |
1da177e4 LT |
572 | } |
573 | ||
8b6aaab8 | 574 | static irqreturn_t mace_interrupt(int irq, void *dev_id) |
1da177e4 | 575 | { |
8b6aaab8 FT |
576 | struct net_device *dev = (struct net_device *) dev_id; |
577 | struct mace_data *mp = netdev_priv(dev); | |
1da177e4 | 578 | volatile struct mace *mb = mp->mace; |
8b6aaab8 | 579 | int intr, fs; |
099575b6 | 580 | unsigned long flags; |
6aa20a22 | 581 | |
8b6aaab8 FT |
582 | /* don't want the dma interrupt handler to fire */ |
583 | local_irq_save(flags); | |
6aa20a22 | 584 | |
8b6aaab8 FT |
585 | intr = mb->ir; /* read interrupt register */ |
586 | mace_handle_misc_intrs(mp, intr); | |
587 | ||
588 | if (intr & XMTINT) { | |
589 | fs = mb->xmtfs; | |
590 | if ((fs & XMTSV) == 0) { | |
591 | printk(KERN_ERR "macmace: xmtfs not valid! (fs=%x)\n", fs); | |
592 | mace_reset(dev); | |
593 | /* | |
594 | * XXX mace likes to hang the machine after a xmtfs error. | |
595 | * This is hard to reproduce, reseting *may* help | |
596 | */ | |
1da177e4 | 597 | } |
8b6aaab8 FT |
598 | /* dma should have finished */ |
599 | if (!mp->tx_count) { | |
600 | printk(KERN_DEBUG "macmace: tx ring ran out? (fs=%x)\n", fs); | |
601 | } | |
602 | /* Update stats */ | |
603 | if (fs & (UFLO|LCOL|LCAR|RTRY)) { | |
604 | ++mp->stats.tx_errors; | |
605 | if (fs & LCAR) | |
606 | ++mp->stats.tx_carrier_errors; | |
607 | else if (fs & (UFLO|LCOL|RTRY)) { | |
608 | ++mp->stats.tx_aborted_errors; | |
609 | if (mb->xmtfs & UFLO) { | |
610 | printk(KERN_ERR "%s: DMA underrun.\n", dev->name); | |
611 | mp->stats.tx_fifo_errors++; | |
612 | mace_txdma_reset(dev); | |
613 | } | |
614 | } | |
1da177e4 | 615 | } |
6aa20a22 | 616 | } |
1da177e4 | 617 | |
8b6aaab8 FT |
618 | if (mp->tx_count) |
619 | netif_wake_queue(dev); | |
6aa20a22 | 620 | |
8b6aaab8 | 621 | local_irq_restore(flags); |
1da177e4 | 622 | |
8b6aaab8 FT |
623 | return IRQ_HANDLED; |
624 | } | |
6aa20a22 | 625 | |
8b6aaab8 | 626 | static void mace_tx_timeout(struct net_device *dev) |
1da177e4 | 627 | { |
8b6aaab8 | 628 | struct mace_data *mp = netdev_priv(dev); |
1da177e4 | 629 | volatile struct mace *mb = mp->mace; |
8b6aaab8 | 630 | unsigned long flags; |
6aa20a22 | 631 | |
8b6aaab8 | 632 | local_irq_save(flags); |
6aa20a22 | 633 | |
8b6aaab8 FT |
634 | /* turn off both tx and rx and reset the chip */ |
635 | mb->maccc = 0; | |
636 | printk(KERN_ERR "macmace: transmit timeout - resetting\n"); | |
637 | mace_txdma_reset(dev); | |
638 | mace_reset(dev); | |
1da177e4 | 639 | |
8b6aaab8 FT |
640 | /* restart rx dma */ |
641 | mace_rxdma_reset(dev); | |
642 | ||
643 | mp->tx_count = N_TX_RING; | |
644 | netif_wake_queue(dev); | |
645 | ||
646 | /* turn it on! */ | |
647 | mb->maccc = ENXMT | ENRCV; | |
648 | /* enable all interrupts except receive interrupts */ | |
649 | mb->imr = RCVINT; | |
650 | ||
651 | local_irq_restore(flags); | |
1da177e4 LT |
652 | } |
653 | ||
654 | /* | |
655 | * Handle a newly arrived frame | |
656 | */ | |
6aa20a22 | 657 | |
1da177e4 LT |
658 | static void mace_dma_rx_frame(struct net_device *dev, struct mace_frame *mf) |
659 | { | |
8b6aaab8 | 660 | struct mace_data *mp = netdev_priv(dev); |
1da177e4 | 661 | struct sk_buff *skb; |
8b6aaab8 | 662 | unsigned int frame_status = mf->rcvsts; |
1da177e4 | 663 | |
8b6aaab8 | 664 | if (frame_status & (RS_OFLO | RS_CLSN | RS_FRAMERR | RS_FCSERR)) { |
1da177e4 | 665 | mp->stats.rx_errors++; |
8b6aaab8 FT |
666 | if (frame_status & RS_OFLO) { |
667 | printk(KERN_DEBUG "%s: fifo overflow.\n", dev->name); | |
668 | mp->stats.rx_fifo_errors++; | |
669 | } | |
670 | if (frame_status & RS_CLSN) | |
671 | mp->stats.collisions++; | |
672 | if (frame_status & RS_FRAMERR) | |
673 | mp->stats.rx_frame_errors++; | |
674 | if (frame_status & RS_FCSERR) | |
675 | mp->stats.rx_crc_errors++; | |
676 | } else { | |
677 | unsigned int frame_length = mf->rcvcnt + ((frame_status & 0x0F) << 8 ); | |
6aa20a22 | 678 | |
8b6aaab8 FT |
679 | skb = dev_alloc_skb(frame_length + 2); |
680 | if (!skb) { | |
681 | mp->stats.rx_dropped++; | |
682 | return; | |
683 | } | |
684 | skb_reserve(skb, 2); | |
685 | memcpy(skb_put(skb, frame_length), mf->data, frame_length); | |
686 | ||
687 | skb->protocol = eth_type_trans(skb, dev); | |
688 | netif_rx(skb); | |
689 | dev->last_rx = jiffies; | |
690 | mp->stats.rx_packets++; | |
691 | mp->stats.rx_bytes += frame_length; | |
1da177e4 | 692 | } |
1da177e4 LT |
693 | } |
694 | ||
695 | /* | |
696 | * The PSC has passed us a DMA interrupt event. | |
697 | */ | |
6aa20a22 | 698 | |
7d12e780 | 699 | static irqreturn_t mace_dma_intr(int irq, void *dev_id) |
1da177e4 LT |
700 | { |
701 | struct net_device *dev = (struct net_device *) dev_id; | |
8b6aaab8 | 702 | struct mace_data *mp = netdev_priv(dev); |
1da177e4 LT |
703 | int left, head; |
704 | u16 status; | |
705 | u32 baka; | |
706 | ||
707 | /* Not sure what this does */ | |
708 | ||
709 | while ((baka = psc_read_long(PSC_MYSTERY)) != psc_read_long(PSC_MYSTERY)); | |
710 | if (!(baka & 0x60000000)) return IRQ_NONE; | |
711 | ||
712 | /* | |
713 | * Process the read queue | |
714 | */ | |
6aa20a22 | 715 | |
1da177e4 | 716 | status = psc_read_word(PSC_ENETRD_CTL); |
6aa20a22 | 717 | |
1da177e4 LT |
718 | if (status & 0x2000) { |
719 | mace_rxdma_reset(dev); | |
720 | } else if (status & 0x0100) { | |
721 | psc_write_word(PSC_ENETRD_CMD + mp->rx_slot, 0x1100); | |
722 | ||
723 | left = psc_read_long(PSC_ENETRD_LEN + mp->rx_slot); | |
724 | head = N_RX_RING - left; | |
725 | ||
726 | /* Loop through the ring buffer and process new packages */ | |
727 | ||
728 | while (mp->rx_tail < head) { | |
8b6aaab8 FT |
729 | mace_dma_rx_frame(dev, (struct mace_frame*) (mp->rx_ring |
730 | + (mp->rx_tail * MACE_BUFF_SIZE))); | |
1da177e4 LT |
731 | mp->rx_tail++; |
732 | } | |
6aa20a22 | 733 | |
1da177e4 LT |
734 | /* If we're out of buffers in this ring then switch to */ |
735 | /* the other set, otherwise just reactivate this one. */ | |
736 | ||
737 | if (!left) { | |
738 | mace_load_rxdma_base(dev, mp->rx_slot); | |
739 | mp->rx_slot ^= 0x10; | |
740 | } else { | |
741 | psc_write_word(PSC_ENETRD_CMD + mp->rx_slot, 0x9800); | |
742 | } | |
743 | } | |
6aa20a22 | 744 | |
1da177e4 LT |
745 | /* |
746 | * Process the write queue | |
747 | */ | |
748 | ||
749 | status = psc_read_word(PSC_ENETWR_CTL); | |
750 | ||
751 | if (status & 0x2000) { | |
752 | mace_txdma_reset(dev); | |
753 | } else if (status & 0x0100) { | |
754 | psc_write_word(PSC_ENETWR_CMD + mp->tx_sloti, 0x0100); | |
755 | mp->tx_sloti ^= 0x10; | |
756 | mp->tx_count++; | |
1da177e4 LT |
757 | } |
758 | return IRQ_HANDLED; | |
759 | } | |
760 | ||
761 | MODULE_LICENSE("GPL"); | |
8b6aaab8 FT |
762 | MODULE_DESCRIPTION("Macintosh MACE ethernet driver"); |
763 | ||
764 | static int __devexit mac_mace_device_remove (struct platform_device *pdev) | |
765 | { | |
766 | struct net_device *dev = platform_get_drvdata(pdev); | |
767 | struct mace_data *mp = netdev_priv(dev); | |
768 | ||
769 | unregister_netdev(dev); | |
770 | ||
771 | free_irq(dev->irq, dev); | |
772 | free_irq(IRQ_MAC_MACE_DMA, dev); | |
773 | ||
774 | dma_free_coherent(mp->device, N_RX_RING * MACE_BUFF_SIZE, | |
775 | mp->rx_ring, mp->rx_ring_phys); | |
776 | dma_free_coherent(mp->device, N_TX_RING * MACE_BUFF_SIZE, | |
777 | mp->tx_ring, mp->tx_ring_phys); | |
778 | ||
779 | free_netdev(dev); | |
780 | ||
781 | return 0; | |
782 | } | |
783 | ||
784 | static struct platform_driver mac_mace_driver = { | |
785 | .probe = mace_probe, | |
786 | .remove = __devexit_p(mac_mace_device_remove), | |
787 | .driver = { | |
788 | .name = mac_mace_string, | |
789 | }, | |
790 | }; | |
791 | ||
792 | static int __init mac_mace_init_module(void) | |
793 | { | |
794 | int err; | |
795 | ||
796 | if ((err = platform_driver_register(&mac_mace_driver))) { | |
797 | printk(KERN_ERR "Driver registration failed\n"); | |
798 | return err; | |
799 | } | |
800 | ||
801 | mac_mace_device = platform_device_alloc(mac_mace_string, 0); | |
802 | if (!mac_mace_device) | |
803 | goto out_unregister; | |
804 | ||
805 | if (platform_device_add(mac_mace_device)) { | |
806 | platform_device_put(mac_mace_device); | |
807 | mac_mace_device = NULL; | |
808 | } | |
809 | ||
810 | return 0; | |
811 | ||
812 | out_unregister: | |
813 | platform_driver_unregister(&mac_mace_driver); | |
814 | ||
815 | return -ENOMEM; | |
816 | } | |
817 | ||
818 | static void __exit mac_mace_cleanup_module(void) | |
819 | { | |
820 | platform_driver_unregister(&mac_mace_driver); | |
821 | ||
822 | if (mac_mace_device) { | |
823 | platform_device_unregister(mac_mace_device); | |
824 | mac_mace_device = NULL; | |
825 | } | |
826 | } | |
827 | ||
828 | module_init(mac_mace_init_module); | |
829 | module_exit(mac_mace_cleanup_module); |