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c27a02cd YP |
1 | /* |
2 | * Copyright (c) 2007 Mellanox Technologies. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | * | |
32 | */ | |
33 | ||
34 | #include <linux/mlx4/cq.h> | |
35 | #include <linux/mlx4/qp.h> | |
36 | #include <linux/skbuff.h> | |
37 | #include <linux/if_ether.h> | |
38 | #include <linux/if_vlan.h> | |
39 | #include <linux/vmalloc.h> | |
40 | ||
41 | #include "mlx4_en.h" | |
42 | ||
c27a02cd YP |
43 | |
44 | static int mlx4_en_get_frag_header(struct skb_frag_struct *frags, void **mac_hdr, | |
45 | void **ip_hdr, void **tcpudp_hdr, | |
46 | u64 *hdr_flags, void *priv) | |
47 | { | |
48 | *mac_hdr = page_address(frags->page) + frags->page_offset; | |
49 | *ip_hdr = *mac_hdr + ETH_HLEN; | |
50 | *tcpudp_hdr = (struct tcphdr *)(*ip_hdr + sizeof(struct iphdr)); | |
51 | *hdr_flags = LRO_IPV4 | LRO_TCP; | |
52 | ||
53 | return 0; | |
54 | } | |
55 | ||
56 | static int mlx4_en_alloc_frag(struct mlx4_en_priv *priv, | |
57 | struct mlx4_en_rx_desc *rx_desc, | |
58 | struct skb_frag_struct *skb_frags, | |
59 | struct mlx4_en_rx_alloc *ring_alloc, | |
60 | int i) | |
61 | { | |
62 | struct mlx4_en_dev *mdev = priv->mdev; | |
63 | struct mlx4_en_frag_info *frag_info = &priv->frag_info[i]; | |
64 | struct mlx4_en_rx_alloc *page_alloc = &ring_alloc[i]; | |
65 | struct page *page; | |
66 | dma_addr_t dma; | |
67 | ||
68 | if (page_alloc->offset == frag_info->last_offset) { | |
69 | /* Allocate new page */ | |
70 | page = alloc_pages(GFP_ATOMIC | __GFP_COMP, MLX4_EN_ALLOC_ORDER); | |
71 | if (!page) | |
72 | return -ENOMEM; | |
73 | ||
74 | skb_frags[i].page = page_alloc->page; | |
75 | skb_frags[i].page_offset = page_alloc->offset; | |
76 | page_alloc->page = page; | |
77 | page_alloc->offset = frag_info->frag_align; | |
78 | } else { | |
79 | page = page_alloc->page; | |
80 | get_page(page); | |
81 | ||
82 | skb_frags[i].page = page; | |
83 | skb_frags[i].page_offset = page_alloc->offset; | |
84 | page_alloc->offset += frag_info->frag_stride; | |
85 | } | |
86 | dma = pci_map_single(mdev->pdev, page_address(skb_frags[i].page) + | |
87 | skb_frags[i].page_offset, frag_info->frag_size, | |
88 | PCI_DMA_FROMDEVICE); | |
89 | rx_desc->data[i].addr = cpu_to_be64(dma); | |
90 | return 0; | |
91 | } | |
92 | ||
93 | static int mlx4_en_init_allocator(struct mlx4_en_priv *priv, | |
94 | struct mlx4_en_rx_ring *ring) | |
95 | { | |
96 | struct mlx4_en_rx_alloc *page_alloc; | |
97 | int i; | |
98 | ||
99 | for (i = 0; i < priv->num_frags; i++) { | |
100 | page_alloc = &ring->page_alloc[i]; | |
101 | page_alloc->page = alloc_pages(GFP_ATOMIC | __GFP_COMP, | |
102 | MLX4_EN_ALLOC_ORDER); | |
103 | if (!page_alloc->page) | |
104 | goto out; | |
105 | ||
106 | page_alloc->offset = priv->frag_info[i].frag_align; | |
453a6082 YP |
107 | en_dbg(DRV, priv, "Initialized allocator:%d with page:%p\n", |
108 | i, page_alloc->page); | |
c27a02cd YP |
109 | } |
110 | return 0; | |
111 | ||
112 | out: | |
113 | while (i--) { | |
114 | page_alloc = &ring->page_alloc[i]; | |
115 | put_page(page_alloc->page); | |
116 | page_alloc->page = NULL; | |
117 | } | |
118 | return -ENOMEM; | |
119 | } | |
120 | ||
121 | static void mlx4_en_destroy_allocator(struct mlx4_en_priv *priv, | |
122 | struct mlx4_en_rx_ring *ring) | |
123 | { | |
124 | struct mlx4_en_rx_alloc *page_alloc; | |
125 | int i; | |
126 | ||
127 | for (i = 0; i < priv->num_frags; i++) { | |
128 | page_alloc = &ring->page_alloc[i]; | |
453a6082 YP |
129 | en_dbg(DRV, priv, "Freeing allocator:%d count:%d\n", |
130 | i, page_count(page_alloc->page)); | |
c27a02cd YP |
131 | |
132 | put_page(page_alloc->page); | |
133 | page_alloc->page = NULL; | |
134 | } | |
135 | } | |
136 | ||
137 | ||
138 | static void mlx4_en_init_rx_desc(struct mlx4_en_priv *priv, | |
139 | struct mlx4_en_rx_ring *ring, int index) | |
140 | { | |
141 | struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index; | |
142 | struct skb_frag_struct *skb_frags = ring->rx_info + | |
143 | (index << priv->log_rx_info); | |
144 | int possible_frags; | |
145 | int i; | |
146 | ||
c27a02cd YP |
147 | /* Set size and memtype fields */ |
148 | for (i = 0; i < priv->num_frags; i++) { | |
149 | skb_frags[i].size = priv->frag_info[i].frag_size; | |
150 | rx_desc->data[i].byte_count = | |
151 | cpu_to_be32(priv->frag_info[i].frag_size); | |
152 | rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key); | |
153 | } | |
154 | ||
155 | /* If the number of used fragments does not fill up the ring stride, | |
156 | * remaining (unused) fragments must be padded with null address/size | |
157 | * and a special memory key */ | |
158 | possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE; | |
159 | for (i = priv->num_frags; i < possible_frags; i++) { | |
160 | rx_desc->data[i].byte_count = 0; | |
161 | rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD); | |
162 | rx_desc->data[i].addr = 0; | |
163 | } | |
164 | } | |
165 | ||
166 | ||
167 | static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv, | |
168 | struct mlx4_en_rx_ring *ring, int index) | |
169 | { | |
170 | struct mlx4_en_rx_desc *rx_desc = ring->buf + (index * ring->stride); | |
171 | struct skb_frag_struct *skb_frags = ring->rx_info + | |
172 | (index << priv->log_rx_info); | |
173 | int i; | |
174 | ||
175 | for (i = 0; i < priv->num_frags; i++) | |
176 | if (mlx4_en_alloc_frag(priv, rx_desc, skb_frags, ring->page_alloc, i)) | |
177 | goto err; | |
178 | ||
179 | return 0; | |
180 | ||
181 | err: | |
182 | while (i--) | |
183 | put_page(skb_frags[i].page); | |
184 | return -ENOMEM; | |
185 | } | |
186 | ||
187 | static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring) | |
188 | { | |
189 | *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff); | |
190 | } | |
191 | ||
38aab07c YP |
192 | static void mlx4_en_free_rx_desc(struct mlx4_en_priv *priv, |
193 | struct mlx4_en_rx_ring *ring, | |
194 | int index) | |
195 | { | |
196 | struct mlx4_en_dev *mdev = priv->mdev; | |
197 | struct skb_frag_struct *skb_frags; | |
198 | struct mlx4_en_rx_desc *rx_desc = ring->buf + (index << ring->log_stride); | |
199 | dma_addr_t dma; | |
200 | int nr; | |
201 | ||
202 | skb_frags = ring->rx_info + (index << priv->log_rx_info); | |
203 | for (nr = 0; nr < priv->num_frags; nr++) { | |
453a6082 | 204 | en_dbg(DRV, priv, "Freeing fragment:%d\n", nr); |
38aab07c YP |
205 | dma = be64_to_cpu(rx_desc->data[nr].addr); |
206 | ||
af901ca1 | 207 | en_dbg(DRV, priv, "Unmapping buffer at dma:0x%llx\n", (u64) dma); |
38aab07c YP |
208 | pci_unmap_single(mdev->pdev, dma, skb_frags[nr].size, |
209 | PCI_DMA_FROMDEVICE); | |
210 | put_page(skb_frags[nr].page); | |
211 | } | |
212 | } | |
213 | ||
c27a02cd YP |
214 | static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv) |
215 | { | |
c27a02cd YP |
216 | struct mlx4_en_rx_ring *ring; |
217 | int ring_ind; | |
218 | int buf_ind; | |
38aab07c | 219 | int new_size; |
c27a02cd YP |
220 | |
221 | for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) { | |
222 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { | |
223 | ring = &priv->rx_ring[ring_ind]; | |
224 | ||
225 | if (mlx4_en_prepare_rx_desc(priv, ring, | |
226 | ring->actual_size)) { | |
227 | if (ring->actual_size < MLX4_EN_MIN_RX_SIZE) { | |
453a6082 YP |
228 | en_err(priv, "Failed to allocate " |
229 | "enough rx buffers\n"); | |
c27a02cd YP |
230 | return -ENOMEM; |
231 | } else { | |
38aab07c | 232 | new_size = rounddown_pow_of_two(ring->actual_size); |
453a6082 YP |
233 | en_warn(priv, "Only %d buffers allocated " |
234 | "reducing ring size to %d", | |
235 | ring->actual_size, new_size); | |
38aab07c | 236 | goto reduce_rings; |
c27a02cd YP |
237 | } |
238 | } | |
239 | ring->actual_size++; | |
240 | ring->prod++; | |
241 | } | |
242 | } | |
38aab07c YP |
243 | return 0; |
244 | ||
245 | reduce_rings: | |
246 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { | |
247 | ring = &priv->rx_ring[ring_ind]; | |
248 | while (ring->actual_size > new_size) { | |
249 | ring->actual_size--; | |
250 | ring->prod--; | |
251 | mlx4_en_free_rx_desc(priv, ring, ring->actual_size); | |
252 | } | |
253 | ring->size_mask = ring->actual_size - 1; | |
254 | } | |
255 | ||
c27a02cd YP |
256 | return 0; |
257 | } | |
258 | ||
c27a02cd YP |
259 | static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv, |
260 | struct mlx4_en_rx_ring *ring) | |
261 | { | |
c27a02cd | 262 | int index; |
c27a02cd | 263 | |
453a6082 YP |
264 | en_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n", |
265 | ring->cons, ring->prod); | |
c27a02cd YP |
266 | |
267 | /* Unmap and free Rx buffers */ | |
38aab07c | 268 | BUG_ON((u32) (ring->prod - ring->cons) > ring->actual_size); |
c27a02cd YP |
269 | while (ring->cons != ring->prod) { |
270 | index = ring->cons & ring->size_mask; | |
453a6082 | 271 | en_dbg(DRV, priv, "Processing descriptor:%d\n", index); |
38aab07c | 272 | mlx4_en_free_rx_desc(priv, ring, index); |
c27a02cd YP |
273 | ++ring->cons; |
274 | } | |
275 | } | |
276 | ||
c27a02cd YP |
277 | int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv, |
278 | struct mlx4_en_rx_ring *ring, u32 size, u16 stride) | |
279 | { | |
280 | struct mlx4_en_dev *mdev = priv->mdev; | |
281 | int err; | |
282 | int tmp; | |
283 | ||
c27a02cd YP |
284 | |
285 | ring->prod = 0; | |
286 | ring->cons = 0; | |
287 | ring->size = size; | |
288 | ring->size_mask = size - 1; | |
289 | ring->stride = stride; | |
290 | ring->log_stride = ffs(ring->stride) - 1; | |
9f519f68 | 291 | ring->buf_size = ring->size * ring->stride + TXBB_SIZE; |
c27a02cd YP |
292 | |
293 | tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS * | |
294 | sizeof(struct skb_frag_struct)); | |
295 | ring->rx_info = vmalloc(tmp); | |
296 | if (!ring->rx_info) { | |
453a6082 | 297 | en_err(priv, "Failed allocating rx_info ring\n"); |
c27a02cd YP |
298 | return -ENOMEM; |
299 | } | |
453a6082 | 300 | en_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n", |
c27a02cd YP |
301 | ring->rx_info, tmp); |
302 | ||
303 | err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, | |
304 | ring->buf_size, 2 * PAGE_SIZE); | |
305 | if (err) | |
306 | goto err_ring; | |
307 | ||
308 | err = mlx4_en_map_buffer(&ring->wqres.buf); | |
309 | if (err) { | |
453a6082 | 310 | en_err(priv, "Failed to map RX buffer\n"); |
c27a02cd YP |
311 | goto err_hwq; |
312 | } | |
313 | ring->buf = ring->wqres.buf.direct.buf; | |
314 | ||
315 | /* Configure lro mngr */ | |
316 | memset(&ring->lro, 0, sizeof(struct net_lro_mgr)); | |
317 | ring->lro.dev = priv->dev; | |
318 | ring->lro.features = LRO_F_NAPI; | |
319 | ring->lro.frag_align_pad = NET_IP_ALIGN; | |
320 | ring->lro.ip_summed = CHECKSUM_UNNECESSARY; | |
321 | ring->lro.ip_summed_aggr = CHECKSUM_UNNECESSARY; | |
322 | ring->lro.max_desc = mdev->profile.num_lro; | |
323 | ring->lro.max_aggr = MAX_SKB_FRAGS; | |
324 | ring->lro.lro_arr = kzalloc(mdev->profile.num_lro * | |
325 | sizeof(struct net_lro_desc), | |
326 | GFP_KERNEL); | |
327 | if (!ring->lro.lro_arr) { | |
453a6082 | 328 | en_err(priv, "Failed to allocate lro array\n"); |
c27a02cd YP |
329 | goto err_map; |
330 | } | |
331 | ring->lro.get_frag_header = mlx4_en_get_frag_header; | |
332 | ||
333 | return 0; | |
334 | ||
335 | err_map: | |
336 | mlx4_en_unmap_buffer(&ring->wqres.buf); | |
337 | err_hwq: | |
338 | mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); | |
339 | err_ring: | |
340 | vfree(ring->rx_info); | |
341 | ring->rx_info = NULL; | |
342 | return err; | |
343 | } | |
344 | ||
345 | int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv) | |
346 | { | |
c27a02cd YP |
347 | struct mlx4_en_rx_ring *ring; |
348 | int i; | |
349 | int ring_ind; | |
350 | int err; | |
351 | int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) + | |
352 | DS_SIZE * priv->num_frags); | |
c27a02cd YP |
353 | |
354 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { | |
355 | ring = &priv->rx_ring[ring_ind]; | |
356 | ||
357 | ring->prod = 0; | |
358 | ring->cons = 0; | |
359 | ring->actual_size = 0; | |
360 | ring->cqn = priv->rx_cq[ring_ind].mcq.cqn; | |
361 | ||
362 | ring->stride = stride; | |
9f519f68 YP |
363 | if (ring->stride <= TXBB_SIZE) |
364 | ring->buf += TXBB_SIZE; | |
365 | ||
c27a02cd YP |
366 | ring->log_stride = ffs(ring->stride) - 1; |
367 | ring->buf_size = ring->size * ring->stride; | |
368 | ||
369 | memset(ring->buf, 0, ring->buf_size); | |
370 | mlx4_en_update_rx_prod_db(ring); | |
371 | ||
372 | /* Initailize all descriptors */ | |
373 | for (i = 0; i < ring->size; i++) | |
374 | mlx4_en_init_rx_desc(priv, ring, i); | |
375 | ||
376 | /* Initialize page allocators */ | |
377 | err = mlx4_en_init_allocator(priv, ring); | |
378 | if (err) { | |
453a6082 | 379 | en_err(priv, "Failed initializing ring allocator\n"); |
9a4f92a6 YP |
380 | ring_ind--; |
381 | goto err_allocator; | |
c27a02cd | 382 | } |
c27a02cd | 383 | } |
b58515be IM |
384 | err = mlx4_en_fill_rx_buffers(priv); |
385 | if (err) | |
c27a02cd YP |
386 | goto err_buffers; |
387 | ||
388 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { | |
389 | ring = &priv->rx_ring[ring_ind]; | |
390 | ||
391 | mlx4_en_update_rx_prod_db(ring); | |
c27a02cd YP |
392 | } |
393 | ||
394 | return 0; | |
395 | ||
c27a02cd YP |
396 | err_buffers: |
397 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) | |
398 | mlx4_en_free_rx_buf(priv, &priv->rx_ring[ring_ind]); | |
399 | ||
400 | ring_ind = priv->rx_ring_num - 1; | |
401 | err_allocator: | |
402 | while (ring_ind >= 0) { | |
403 | mlx4_en_destroy_allocator(priv, &priv->rx_ring[ring_ind]); | |
404 | ring_ind--; | |
405 | } | |
406 | return err; | |
407 | } | |
408 | ||
409 | void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv, | |
410 | struct mlx4_en_rx_ring *ring) | |
411 | { | |
412 | struct mlx4_en_dev *mdev = priv->mdev; | |
413 | ||
414 | kfree(ring->lro.lro_arr); | |
415 | mlx4_en_unmap_buffer(&ring->wqres.buf); | |
9f519f68 | 416 | mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size + TXBB_SIZE); |
c27a02cd YP |
417 | vfree(ring->rx_info); |
418 | ring->rx_info = NULL; | |
419 | } | |
420 | ||
421 | void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv, | |
422 | struct mlx4_en_rx_ring *ring) | |
423 | { | |
c27a02cd | 424 | mlx4_en_free_rx_buf(priv, ring); |
9f519f68 YP |
425 | if (ring->stride <= TXBB_SIZE) |
426 | ring->buf -= TXBB_SIZE; | |
c27a02cd YP |
427 | mlx4_en_destroy_allocator(priv, ring); |
428 | } | |
429 | ||
430 | ||
431 | /* Unmap a completed descriptor and free unused pages */ | |
432 | static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv, | |
433 | struct mlx4_en_rx_desc *rx_desc, | |
434 | struct skb_frag_struct *skb_frags, | |
435 | struct skb_frag_struct *skb_frags_rx, | |
436 | struct mlx4_en_rx_alloc *page_alloc, | |
437 | int length) | |
438 | { | |
439 | struct mlx4_en_dev *mdev = priv->mdev; | |
440 | struct mlx4_en_frag_info *frag_info; | |
441 | int nr; | |
442 | dma_addr_t dma; | |
443 | ||
444 | /* Collect used fragments while replacing them in the HW descirptors */ | |
445 | for (nr = 0; nr < priv->num_frags; nr++) { | |
446 | frag_info = &priv->frag_info[nr]; | |
447 | if (length <= frag_info->frag_prefix_size) | |
448 | break; | |
449 | ||
450 | /* Save page reference in skb */ | |
451 | skb_frags_rx[nr].page = skb_frags[nr].page; | |
452 | skb_frags_rx[nr].size = skb_frags[nr].size; | |
453 | skb_frags_rx[nr].page_offset = skb_frags[nr].page_offset; | |
454 | dma = be64_to_cpu(rx_desc->data[nr].addr); | |
455 | ||
456 | /* Allocate a replacement page */ | |
457 | if (mlx4_en_alloc_frag(priv, rx_desc, skb_frags, page_alloc, nr)) | |
458 | goto fail; | |
459 | ||
460 | /* Unmap buffer */ | |
461 | pci_unmap_single(mdev->pdev, dma, skb_frags[nr].size, | |
462 | PCI_DMA_FROMDEVICE); | |
463 | } | |
464 | /* Adjust size of last fragment to match actual length */ | |
973507cb | 465 | if (nr > 0) |
466 | skb_frags_rx[nr - 1].size = length - | |
467 | priv->frag_info[nr - 1].frag_prefix_size; | |
c27a02cd YP |
468 | return nr; |
469 | ||
470 | fail: | |
471 | /* Drop all accumulated fragments (which have already been replaced in | |
472 | * the descriptor) of this packet; remaining fragments are reused... */ | |
473 | while (nr > 0) { | |
474 | nr--; | |
475 | put_page(skb_frags_rx[nr].page); | |
476 | } | |
477 | return 0; | |
478 | } | |
479 | ||
480 | ||
481 | static struct sk_buff *mlx4_en_rx_skb(struct mlx4_en_priv *priv, | |
482 | struct mlx4_en_rx_desc *rx_desc, | |
483 | struct skb_frag_struct *skb_frags, | |
484 | struct mlx4_en_rx_alloc *page_alloc, | |
485 | unsigned int length) | |
486 | { | |
487 | struct mlx4_en_dev *mdev = priv->mdev; | |
488 | struct sk_buff *skb; | |
489 | void *va; | |
490 | int used_frags; | |
491 | dma_addr_t dma; | |
492 | ||
493 | skb = dev_alloc_skb(SMALL_PACKET_SIZE + NET_IP_ALIGN); | |
494 | if (!skb) { | |
453a6082 | 495 | en_dbg(RX_ERR, priv, "Failed allocating skb\n"); |
c27a02cd YP |
496 | return NULL; |
497 | } | |
498 | skb->dev = priv->dev; | |
499 | skb_reserve(skb, NET_IP_ALIGN); | |
500 | skb->len = length; | |
501 | skb->truesize = length + sizeof(struct sk_buff); | |
502 | ||
503 | /* Get pointer to first fragment so we could copy the headers into the | |
504 | * (linear part of the) skb */ | |
505 | va = page_address(skb_frags[0].page) + skb_frags[0].page_offset; | |
506 | ||
507 | if (length <= SMALL_PACKET_SIZE) { | |
508 | /* We are copying all relevant data to the skb - temporarily | |
509 | * synch buffers for the copy */ | |
510 | dma = be64_to_cpu(rx_desc->data[0].addr); | |
511 | dma_sync_single_range_for_cpu(&mdev->pdev->dev, dma, 0, | |
512 | length, DMA_FROM_DEVICE); | |
513 | skb_copy_to_linear_data(skb, va, length); | |
514 | dma_sync_single_range_for_device(&mdev->pdev->dev, dma, 0, | |
515 | length, DMA_FROM_DEVICE); | |
516 | skb->tail += length; | |
517 | } else { | |
518 | ||
519 | /* Move relevant fragments to skb */ | |
520 | used_frags = mlx4_en_complete_rx_desc(priv, rx_desc, skb_frags, | |
521 | skb_shinfo(skb)->frags, | |
522 | page_alloc, length); | |
785a0982 YP |
523 | if (unlikely(!used_frags)) { |
524 | kfree_skb(skb); | |
525 | return NULL; | |
526 | } | |
c27a02cd YP |
527 | skb_shinfo(skb)->nr_frags = used_frags; |
528 | ||
529 | /* Copy headers into the skb linear buffer */ | |
530 | memcpy(skb->data, va, HEADER_COPY_SIZE); | |
531 | skb->tail += HEADER_COPY_SIZE; | |
532 | ||
533 | /* Skip headers in first fragment */ | |
534 | skb_shinfo(skb)->frags[0].page_offset += HEADER_COPY_SIZE; | |
535 | ||
536 | /* Adjust size of first fragment */ | |
537 | skb_shinfo(skb)->frags[0].size -= HEADER_COPY_SIZE; | |
538 | skb->data_len = length - HEADER_COPY_SIZE; | |
539 | } | |
540 | return skb; | |
541 | } | |
542 | ||
c27a02cd YP |
543 | |
544 | int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget) | |
545 | { | |
546 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
c27a02cd YP |
547 | struct mlx4_cqe *cqe; |
548 | struct mlx4_en_rx_ring *ring = &priv->rx_ring[cq->ring]; | |
549 | struct skb_frag_struct *skb_frags; | |
550 | struct skb_frag_struct lro_frags[MLX4_EN_MAX_RX_FRAGS]; | |
551 | struct mlx4_en_rx_desc *rx_desc; | |
552 | struct sk_buff *skb; | |
553 | int index; | |
554 | int nr; | |
555 | unsigned int length; | |
556 | int polled = 0; | |
557 | int ip_summed; | |
558 | ||
559 | if (!priv->port_up) | |
560 | return 0; | |
561 | ||
562 | /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx | |
563 | * descriptor offset can be deduced from the CQE index instead of | |
564 | * reading 'cqe->index' */ | |
565 | index = cq->mcq.cons_index & ring->size_mask; | |
566 | cqe = &cq->buf[index]; | |
567 | ||
568 | /* Process all completed CQEs */ | |
569 | while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK, | |
570 | cq->mcq.cons_index & cq->size)) { | |
571 | ||
572 | skb_frags = ring->rx_info + (index << priv->log_rx_info); | |
573 | rx_desc = ring->buf + (index << ring->log_stride); | |
574 | ||
575 | /* | |
576 | * make sure we read the CQE after we read the ownership bit | |
577 | */ | |
578 | rmb(); | |
579 | ||
580 | /* Drop packet on bad receive or bad checksum */ | |
581 | if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == | |
582 | MLX4_CQE_OPCODE_ERROR)) { | |
453a6082 | 583 | en_err(priv, "CQE completed in error - vendor " |
c27a02cd YP |
584 | "syndrom:%d syndrom:%d\n", |
585 | ((struct mlx4_err_cqe *) cqe)->vendor_err_syndrome, | |
586 | ((struct mlx4_err_cqe *) cqe)->syndrome); | |
587 | goto next; | |
588 | } | |
589 | if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) { | |
453a6082 | 590 | en_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n"); |
c27a02cd YP |
591 | goto next; |
592 | } | |
593 | ||
594 | /* | |
595 | * Packet is OK - process it. | |
596 | */ | |
597 | length = be32_to_cpu(cqe->byte_cnt); | |
598 | ring->bytes += length; | |
599 | ring->packets++; | |
600 | ||
601 | if (likely(priv->rx_csum)) { | |
602 | if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) && | |
603 | (cqe->checksum == cpu_to_be16(0xffff))) { | |
604 | priv->port_stats.rx_chksum_good++; | |
605 | /* This packet is eligible for LRO if it is: | |
606 | * - DIX Ethernet (type interpretation) | |
607 | * - TCP/IP (v4) | |
608 | * - without IP options | |
609 | * - not an IP fragment */ | |
610 | if (mlx4_en_can_lro(cqe->status) && | |
611 | dev->features & NETIF_F_LRO) { | |
612 | ||
613 | nr = mlx4_en_complete_rx_desc( | |
614 | priv, rx_desc, | |
615 | skb_frags, lro_frags, | |
616 | ring->page_alloc, length); | |
617 | if (!nr) | |
618 | goto next; | |
619 | ||
620 | if (priv->vlgrp && (cqe->vlan_my_qpn & | |
621 | cpu_to_be32(MLX4_CQE_VLAN_PRESENT_MASK))) { | |
622 | lro_vlan_hwaccel_receive_frags( | |
623 | &ring->lro, lro_frags, | |
624 | length, length, | |
625 | priv->vlgrp, | |
626 | be16_to_cpu(cqe->sl_vid), | |
627 | NULL, 0); | |
628 | } else | |
629 | lro_receive_frags(&ring->lro, | |
630 | lro_frags, | |
631 | length, | |
632 | length, | |
633 | NULL, 0); | |
634 | ||
635 | goto next; | |
636 | } | |
637 | ||
638 | /* LRO not possible, complete processing here */ | |
639 | ip_summed = CHECKSUM_UNNECESSARY; | |
640 | INC_PERF_COUNTER(priv->pstats.lro_misses); | |
641 | } else { | |
642 | ip_summed = CHECKSUM_NONE; | |
643 | priv->port_stats.rx_chksum_none++; | |
644 | } | |
645 | } else { | |
646 | ip_summed = CHECKSUM_NONE; | |
647 | priv->port_stats.rx_chksum_none++; | |
648 | } | |
649 | ||
650 | skb = mlx4_en_rx_skb(priv, rx_desc, skb_frags, | |
651 | ring->page_alloc, length); | |
652 | if (!skb) { | |
653 | priv->stats.rx_dropped++; | |
654 | goto next; | |
655 | } | |
656 | ||
657 | skb->ip_summed = ip_summed; | |
658 | skb->protocol = eth_type_trans(skb, dev); | |
0c8dfc83 | 659 | skb_record_rx_queue(skb, cq->ring); |
c27a02cd YP |
660 | |
661 | /* Push it up the stack */ | |
662 | if (priv->vlgrp && (be32_to_cpu(cqe->vlan_my_qpn) & | |
663 | MLX4_CQE_VLAN_PRESENT_MASK)) { | |
664 | vlan_hwaccel_receive_skb(skb, priv->vlgrp, | |
665 | be16_to_cpu(cqe->sl_vid)); | |
666 | } else | |
667 | netif_receive_skb(skb); | |
668 | ||
c27a02cd YP |
669 | next: |
670 | ++cq->mcq.cons_index; | |
671 | index = (cq->mcq.cons_index) & ring->size_mask; | |
672 | cqe = &cq->buf[index]; | |
673 | if (++polled == budget) { | |
674 | /* We are here because we reached the NAPI budget - | |
675 | * flush only pending LRO sessions */ | |
676 | lro_flush_all(&ring->lro); | |
677 | goto out; | |
678 | } | |
679 | } | |
680 | ||
681 | /* If CQ is empty flush all LRO sessions unconditionally */ | |
682 | lro_flush_all(&ring->lro); | |
683 | ||
684 | out: | |
685 | AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled); | |
686 | mlx4_cq_set_ci(&cq->mcq); | |
687 | wmb(); /* ensure HW sees CQ consumer before we post new buffers */ | |
688 | ring->cons = cq->mcq.cons_index; | |
689 | ring->prod += polled; /* Polled descriptors were realocated in place */ | |
c27a02cd YP |
690 | mlx4_en_update_rx_prod_db(ring); |
691 | return polled; | |
692 | } | |
693 | ||
694 | ||
695 | void mlx4_en_rx_irq(struct mlx4_cq *mcq) | |
696 | { | |
697 | struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq); | |
698 | struct mlx4_en_priv *priv = netdev_priv(cq->dev); | |
699 | ||
700 | if (priv->port_up) | |
288379f0 | 701 | napi_schedule(&cq->napi); |
c27a02cd YP |
702 | else |
703 | mlx4_en_arm_cq(priv, cq); | |
704 | } | |
705 | ||
706 | /* Rx CQ polling - called by NAPI */ | |
707 | int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget) | |
708 | { | |
709 | struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi); | |
710 | struct net_device *dev = cq->dev; | |
711 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
712 | int done; | |
713 | ||
714 | done = mlx4_en_process_rx_cq(dev, cq, budget); | |
715 | ||
716 | /* If we used up all the quota - we're probably not done yet... */ | |
717 | if (done == budget) | |
718 | INC_PERF_COUNTER(priv->pstats.napi_quota); | |
719 | else { | |
720 | /* Done for now */ | |
288379f0 | 721 | napi_complete(napi); |
c27a02cd YP |
722 | mlx4_en_arm_cq(priv, cq); |
723 | } | |
724 | return done; | |
725 | } | |
726 | ||
727 | ||
728 | /* Calculate the last offset position that accomodates a full fragment | |
729 | * (assuming fagment size = stride-align) */ | |
730 | static int mlx4_en_last_alloc_offset(struct mlx4_en_priv *priv, u16 stride, u16 align) | |
731 | { | |
732 | u16 res = MLX4_EN_ALLOC_SIZE % stride; | |
733 | u16 offset = MLX4_EN_ALLOC_SIZE - stride - res + align; | |
734 | ||
453a6082 | 735 | en_dbg(DRV, priv, "Calculated last offset for stride:%d align:%d " |
c27a02cd YP |
736 | "res:%d offset:%d\n", stride, align, res, offset); |
737 | return offset; | |
738 | } | |
739 | ||
740 | ||
741 | static int frag_sizes[] = { | |
742 | FRAG_SZ0, | |
743 | FRAG_SZ1, | |
744 | FRAG_SZ2, | |
745 | FRAG_SZ3 | |
746 | }; | |
747 | ||
748 | void mlx4_en_calc_rx_buf(struct net_device *dev) | |
749 | { | |
750 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
751 | int eff_mtu = dev->mtu + ETH_HLEN + VLAN_HLEN + ETH_LLC_SNAP_SIZE; | |
752 | int buf_size = 0; | |
753 | int i = 0; | |
754 | ||
755 | while (buf_size < eff_mtu) { | |
756 | priv->frag_info[i].frag_size = | |
757 | (eff_mtu > buf_size + frag_sizes[i]) ? | |
758 | frag_sizes[i] : eff_mtu - buf_size; | |
759 | priv->frag_info[i].frag_prefix_size = buf_size; | |
760 | if (!i) { | |
761 | priv->frag_info[i].frag_align = NET_IP_ALIGN; | |
762 | priv->frag_info[i].frag_stride = | |
763 | ALIGN(frag_sizes[i] + NET_IP_ALIGN, SMP_CACHE_BYTES); | |
764 | } else { | |
765 | priv->frag_info[i].frag_align = 0; | |
766 | priv->frag_info[i].frag_stride = | |
767 | ALIGN(frag_sizes[i], SMP_CACHE_BYTES); | |
768 | } | |
769 | priv->frag_info[i].last_offset = mlx4_en_last_alloc_offset( | |
770 | priv, priv->frag_info[i].frag_stride, | |
771 | priv->frag_info[i].frag_align); | |
772 | buf_size += priv->frag_info[i].frag_size; | |
773 | i++; | |
774 | } | |
775 | ||
776 | priv->num_frags = i; | |
777 | priv->rx_skb_size = eff_mtu; | |
778 | priv->log_rx_info = ROUNDUP_LOG2(i * sizeof(struct skb_frag_struct)); | |
779 | ||
453a6082 | 780 | en_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d " |
c27a02cd YP |
781 | "num_frags:%d):\n", eff_mtu, priv->num_frags); |
782 | for (i = 0; i < priv->num_frags; i++) { | |
453a6082 | 783 | en_dbg(DRV, priv, " frag:%d - size:%d prefix:%d align:%d " |
c27a02cd YP |
784 | "stride:%d last_offset:%d\n", i, |
785 | priv->frag_info[i].frag_size, | |
786 | priv->frag_info[i].frag_prefix_size, | |
787 | priv->frag_info[i].frag_align, | |
788 | priv->frag_info[i].frag_stride, | |
789 | priv->frag_info[i].last_offset); | |
790 | } | |
791 | } | |
792 | ||
793 | /* RSS related functions */ | |
794 | ||
9f519f68 YP |
795 | static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv, int qpn, |
796 | struct mlx4_en_rx_ring *ring, | |
c27a02cd YP |
797 | enum mlx4_qp_state *state, |
798 | struct mlx4_qp *qp) | |
799 | { | |
800 | struct mlx4_en_dev *mdev = priv->mdev; | |
801 | struct mlx4_qp_context *context; | |
802 | int err = 0; | |
803 | ||
804 | context = kmalloc(sizeof *context , GFP_KERNEL); | |
805 | if (!context) { | |
453a6082 | 806 | en_err(priv, "Failed to allocate qp context\n"); |
c27a02cd YP |
807 | return -ENOMEM; |
808 | } | |
809 | ||
810 | err = mlx4_qp_alloc(mdev->dev, qpn, qp); | |
811 | if (err) { | |
453a6082 | 812 | en_err(priv, "Failed to allocate qp #%x\n", qpn); |
c27a02cd | 813 | goto out; |
c27a02cd YP |
814 | } |
815 | qp->event = mlx4_en_sqp_event; | |
816 | ||
817 | memset(context, 0, sizeof *context); | |
9f519f68 YP |
818 | mlx4_en_fill_qp_context(priv, ring->size, ring->stride, 0, 0, |
819 | qpn, ring->cqn, context); | |
820 | context->db_rec_addr = cpu_to_be64(ring->wqres.db.dma); | |
c27a02cd | 821 | |
9f519f68 | 822 | err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, context, qp, state); |
c27a02cd YP |
823 | if (err) { |
824 | mlx4_qp_remove(mdev->dev, qp); | |
825 | mlx4_qp_free(mdev->dev, qp); | |
826 | } | |
9f519f68 | 827 | mlx4_en_update_rx_prod_db(ring); |
c27a02cd YP |
828 | out: |
829 | kfree(context); | |
830 | return err; | |
831 | } | |
832 | ||
833 | /* Allocate rx qp's and configure them according to rss map */ | |
834 | int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv) | |
835 | { | |
836 | struct mlx4_en_dev *mdev = priv->mdev; | |
837 | struct mlx4_en_rss_map *rss_map = &priv->rss_map; | |
838 | struct mlx4_qp_context context; | |
839 | struct mlx4_en_rss_context *rss_context; | |
840 | void *ptr; | |
841 | int rss_xor = mdev->profile.rss_xor; | |
842 | u8 rss_mask = mdev->profile.rss_mask; | |
9f519f68 | 843 | int i, qpn; |
c27a02cd YP |
844 | int err = 0; |
845 | int good_qps = 0; | |
846 | ||
453a6082 | 847 | en_dbg(DRV, priv, "Configuring rss steering\n"); |
b6b912e0 YP |
848 | err = mlx4_qp_reserve_range(mdev->dev, priv->rx_ring_num, |
849 | priv->rx_ring_num, | |
850 | &rss_map->base_qpn); | |
c27a02cd | 851 | if (err) { |
b6b912e0 | 852 | en_err(priv, "Failed reserving %d qps\n", priv->rx_ring_num); |
c27a02cd YP |
853 | return err; |
854 | } | |
855 | ||
b6b912e0 | 856 | for (i = 0; i < priv->rx_ring_num; i++) { |
c27a02cd | 857 | qpn = rss_map->base_qpn + i; |
9f519f68 | 858 | err = mlx4_en_config_rss_qp(priv, qpn, &priv->rx_ring[i], |
c27a02cd YP |
859 | &rss_map->state[i], |
860 | &rss_map->qps[i]); | |
861 | if (err) | |
862 | goto rss_err; | |
863 | ||
864 | ++good_qps; | |
865 | } | |
866 | ||
867 | /* Configure RSS indirection qp */ | |
868 | err = mlx4_qp_reserve_range(mdev->dev, 1, 1, &priv->base_qpn); | |
869 | if (err) { | |
453a6082 YP |
870 | en_err(priv, "Failed to reserve range for RSS " |
871 | "indirection qp\n"); | |
c27a02cd YP |
872 | goto rss_err; |
873 | } | |
874 | err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, &rss_map->indir_qp); | |
875 | if (err) { | |
453a6082 | 876 | en_err(priv, "Failed to allocate RSS indirection QP\n"); |
c27a02cd YP |
877 | goto reserve_err; |
878 | } | |
879 | rss_map->indir_qp.event = mlx4_en_sqp_event; | |
880 | mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn, | |
9f519f68 | 881 | priv->rx_ring[0].cqn, &context); |
c27a02cd YP |
882 | |
883 | ptr = ((void *) &context) + 0x3c; | |
884 | rss_context = (struct mlx4_en_rss_context *) ptr; | |
b6b912e0 | 885 | rss_context->base_qpn = cpu_to_be32(ilog2(priv->rx_ring_num) << 24 | |
c27a02cd YP |
886 | (rss_map->base_qpn)); |
887 | rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn); | |
888 | rss_context->hash_fn = rss_xor & 0x3; | |
889 | rss_context->flags = rss_mask << 2; | |
890 | ||
891 | err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context, | |
892 | &rss_map->indir_qp, &rss_map->indir_state); | |
893 | if (err) | |
894 | goto indir_err; | |
895 | ||
896 | return 0; | |
897 | ||
898 | indir_err: | |
899 | mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state, | |
900 | MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp); | |
901 | mlx4_qp_remove(mdev->dev, &rss_map->indir_qp); | |
902 | mlx4_qp_free(mdev->dev, &rss_map->indir_qp); | |
903 | reserve_err: | |
904 | mlx4_qp_release_range(mdev->dev, priv->base_qpn, 1); | |
905 | rss_err: | |
906 | for (i = 0; i < good_qps; i++) { | |
907 | mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i], | |
908 | MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]); | |
909 | mlx4_qp_remove(mdev->dev, &rss_map->qps[i]); | |
910 | mlx4_qp_free(mdev->dev, &rss_map->qps[i]); | |
911 | } | |
b6b912e0 | 912 | mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num); |
c27a02cd YP |
913 | return err; |
914 | } | |
915 | ||
916 | void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv) | |
917 | { | |
918 | struct mlx4_en_dev *mdev = priv->mdev; | |
919 | struct mlx4_en_rss_map *rss_map = &priv->rss_map; | |
920 | int i; | |
921 | ||
922 | mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state, | |
923 | MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp); | |
924 | mlx4_qp_remove(mdev->dev, &rss_map->indir_qp); | |
925 | mlx4_qp_free(mdev->dev, &rss_map->indir_qp); | |
926 | mlx4_qp_release_range(mdev->dev, priv->base_qpn, 1); | |
927 | ||
b6b912e0 | 928 | for (i = 0; i < priv->rx_ring_num; i++) { |
c27a02cd YP |
929 | mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i], |
930 | MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]); | |
931 | mlx4_qp_remove(mdev->dev, &rss_map->qps[i]); | |
932 | mlx4_qp_free(mdev->dev, &rss_map->qps[i]); | |
933 | } | |
b6b912e0 | 934 | mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num); |
c27a02cd YP |
935 | } |
936 | ||
937 | ||
938 | ||
939 | ||
940 |