[mirror_ubuntu-zesty-kernel.git] / drivers / net / mlx4 / eq.c

/*
 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *	- Redistributions of source code must retain the above
 *	  copyright notice, this list of conditions and the following
 *	  disclaimer.
 *
 *	- Redistributions in binary form must reproduce the above
 *	  copyright notice, this list of conditions and the following
 *	  disclaimer in the documentation and/or other materials
 *	  provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#include <linux/interrupt.h>
#include <linux/mm.h>
#include <linux/dma-mapping.h>

#include <linux/mlx4/cmd.h>

#include "mlx4.h"
#include "fw.h"

enum {
	MLX4_NUM_ASYNC_EQE	= 0x100,
	MLX4_NUM_SPARE_EQE	= 0x80,
	MLX4_EQ_ENTRY_SIZE	= 0x20
};

/*
 * Must be packed because start is 64 bits but only aligned to 32 bits.
 */
struct mlx4_eq_context {
	__be32			flags;
	u16			reserved1[3];
	__be16			page_offset;
	u8			log_eq_size;
	u8			reserved2[4];
	u8			eq_period;
	u8			reserved3;
	u8			eq_max_count;
	u8			reserved4[3];
	u8			intr;
	u8			log_page_size;
	u8			reserved5[2];
	u8			mtt_base_addr_h;
	__be32			mtt_base_addr_l;
	u32			reserved6[2];
	__be32			consumer_index;
	__be32			producer_index;
	u32			reserved7[4];
};

#define MLX4_EQ_STATUS_OK	   ( 0 << 28)
#define MLX4_EQ_STATUS_WRITE_FAIL  (10 << 28)
#define MLX4_EQ_OWNER_SW	   ( 0 << 24)
#define MLX4_EQ_OWNER_HW	   ( 1 << 24)
#define MLX4_EQ_FLAG_EC		   ( 1 << 18)
#define MLX4_EQ_FLAG_OI		   ( 1 << 17)
#define MLX4_EQ_STATE_ARMED	   ( 9 <<  8)
#define MLX4_EQ_STATE_FIRED	   (10 <<  8)
#define MLX4_EQ_STATE_ALWAYS_ARMED (11 <<  8)

#define MLX4_ASYNC_EVENT_MASK ((1ull << MLX4_EVENT_TYPE_PATH_MIG)	    | \
			       (1ull << MLX4_EVENT_TYPE_COMM_EST)	    | \
			       (1ull << MLX4_EVENT_TYPE_SQ_DRAINED)	    | \
			       (1ull << MLX4_EVENT_TYPE_CQ_ERROR)	    | \
			       (1ull << MLX4_EVENT_TYPE_WQ_CATAS_ERROR)	    | \
			       (1ull << MLX4_EVENT_TYPE_EEC_CATAS_ERROR)    | \
			       (1ull << MLX4_EVENT_TYPE_PATH_MIG_FAILED)    | \
			       (1ull << MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \
			       (1ull << MLX4_EVENT_TYPE_WQ_ACCESS_ERROR)    | \
			       (1ull << MLX4_EVENT_TYPE_PORT_CHANGE)	    | \
			       (1ull << MLX4_EVENT_TYPE_ECC_DETECT)	    | \
			       (1ull << MLX4_EVENT_TYPE_SRQ_CATAS_ERROR)    | \
			       (1ull << MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE)    | \
			       (1ull << MLX4_EVENT_TYPE_SRQ_LIMIT)	    | \
			       (1ull << MLX4_EVENT_TYPE_CMD))

struct mlx4_eqe {
	u8			reserved1;
	u8			type;
	u8			reserved2;
	u8			subtype;
	union {
		u32		raw[6];
		struct {
			__be32	cqn;
		} __attribute__((packed)) comp;
		struct {
			u16	reserved1;
			__be16	token;
			u32	reserved2;
			u8	reserved3[3];
			u8	status;
			__be64	out_param;
		} __attribute__((packed)) cmd;
		struct {
			__be32	qpn;
		} __attribute__((packed)) qp;
		struct {
			__be32	srqn;
		} __attribute__((packed)) srq;
		struct {
			__be32	cqn;
			u32	reserved1;
			u8	reserved2[3];
			u8	syndrome;
		} __attribute__((packed)) cq_err;
		struct {
			u32	reserved1[2];
			__be32	port;
		} __attribute__((packed)) port_change;
	}			event;
	u8			reserved3[3];
	u8			owner;
} __attribute__((packed));

static void eq_set_ci(struct mlx4_eq *eq, int req_not)
{
	__raw_writel((__force u32) cpu_to_be32((eq->cons_index & 0xffffff) |
					       req_not << 31),
		     eq->doorbell);
	/* We still want ordering, just not swabbing, so add a barrier */
	mb();
}

static struct mlx4_eqe *get_eqe(struct mlx4_eq *eq, u32 entry)
{
	unsigned long off = (entry & (eq->nent - 1)) * MLX4_EQ_ENTRY_SIZE;
	return eq->page_list[off / PAGE_SIZE].buf + off % PAGE_SIZE;
}

static struct mlx4_eqe *next_eqe_sw(struct mlx4_eq *eq)
{
	struct mlx4_eqe *eqe = get_eqe(eq, eq->cons_index);
	return !!(eqe->owner & 0x80) ^ !!(eq->cons_index & eq->nent) ? NULL : eqe;
}

static int mlx4_eq_int(struct mlx4_dev *dev, struct mlx4_eq *eq)
{
	struct mlx4_eqe *eqe;
	int cqn;
	int eqes_found = 0;
	int set_ci = 0;
	int port;

	while ((eqe = next_eqe_sw(eq))) {
		/*
		 * Make sure we read EQ entry contents after we've
		 * checked the ownership bit.
		 */
		rmb();

		switch (eqe->type) {
		case MLX4_EVENT_TYPE_COMP:
			cqn = be32_to_cpu(eqe->event.comp.cqn) & 0xffffff;
			mlx4_cq_completion(dev, cqn);
			break;

		case MLX4_EVENT_TYPE_PATH_MIG:
		case MLX4_EVENT_TYPE_COMM_EST:
		case MLX4_EVENT_TYPE_SQ_DRAINED:
		case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
		case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
		case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
		case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
		case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
			mlx4_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,
				      eqe->type);
			break;

		case MLX4_EVENT_TYPE_SRQ_LIMIT:
		case MLX4_EVENT_TYPE_SRQ_CATAS_ERROR:
			mlx4_srq_event(dev, be32_to_cpu(eqe->event.srq.srqn) & 0xffffff,
				      eqe->type);
			break;

		case MLX4_EVENT_TYPE_CMD:
			mlx4_cmd_event(dev,
				       be16_to_cpu(eqe->event.cmd.token),
				       eqe->event.cmd.status,
				       be64_to_cpu(eqe->event.cmd.out_param));
			break;

		case MLX4_EVENT_TYPE_PORT_CHANGE:
			port = be32_to_cpu(eqe->event.port_change.port) >> 28;
			if (eqe->subtype == MLX4_PORT_CHANGE_SUBTYPE_DOWN) {
				mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_DOWN,
						    port);
				mlx4_priv(dev)->sense.do_sense_port[port] = 1;
			} else {
				mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_UP,
						    port);
				mlx4_priv(dev)->sense.do_sense_port[port] = 0;
			}
			break;

		case MLX4_EVENT_TYPE_CQ_ERROR:
			mlx4_warn(dev, "CQ %s on CQN %06x\n",
				  eqe->event.cq_err.syndrome == 1 ?
				  "overrun" : "access violation",
				  be32_to_cpu(eqe->event.cq_err.cqn) & 0xffffff);
			mlx4_cq_event(dev, be32_to_cpu(eqe->event.cq_err.cqn),
				      eqe->type);
			break;

		case MLX4_EVENT_TYPE_EQ_OVERFLOW:
			mlx4_warn(dev, "EQ overrun on EQN %d\n", eq->eqn);
			break;

		case MLX4_EVENT_TYPE_EEC_CATAS_ERROR:
		case MLX4_EVENT_TYPE_ECC_DETECT:
		default:
			mlx4_warn(dev, "Unhandled event %02x(%02x) on EQ %d at index %u\n",
				  eqe->type, eqe->subtype, eq->eqn, eq->cons_index);
			break;
		};

		++eq->cons_index;
		eqes_found = 1;
		++set_ci;

		/*
		 * The HCA will think the queue has overflowed if we
		 * don't tell it we've been processing events.  We
		 * create our EQs with MLX4_NUM_SPARE_EQE extra
		 * entries, so we must update our consumer index at
		 * least that often.
		 */
		if (unlikely(set_ci >= MLX4_NUM_SPARE_EQE)) {
			eq_set_ci(eq, 0);
			set_ci = 0;
		}
	}

	eq_set_ci(eq, 1);

	return eqes_found;
}

static irqreturn_t mlx4_interrupt(int irq, void *dev_ptr)
{
	struct mlx4_dev *dev = dev_ptr;
	struct mlx4_priv *priv = mlx4_priv(dev);
	int work = 0;
	int i;

	writel(priv->eq_table.clr_mask, priv->eq_table.clr_int);

	for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
		work |= mlx4_eq_int(dev, &priv->eq_table.eq[i]);

	return IRQ_RETVAL(work);
}

static irqreturn_t mlx4_msi_x_interrupt(int irq, void *eq_ptr)
{
	struct mlx4_eq  *eq  = eq_ptr;
	struct mlx4_dev *dev = eq->dev;

	mlx4_eq_int(dev, eq);

	/* MSI-X vectors always belong to us */
	return IRQ_HANDLED;
}

static int mlx4_MAP_EQ(struct mlx4_dev *dev, u64 event_mask, int unmap,
			int eq_num)
{
	return mlx4_cmd(dev, event_mask, (unmap << 31) | eq_num,
			0, MLX4_CMD_MAP_EQ, MLX4_CMD_TIME_CLASS_B);
}

static int mlx4_SW2HW_EQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
			 int eq_num)
{
	return mlx4_cmd(dev, mailbox->dma, eq_num, 0, MLX4_CMD_SW2HW_EQ,
			MLX4_CMD_TIME_CLASS_A);
}

static int mlx4_HW2SW_EQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
			 int eq_num)
{
	return mlx4_cmd_box(dev, 0, mailbox->dma, eq_num, 0, MLX4_CMD_HW2SW_EQ,
			    MLX4_CMD_TIME_CLASS_A);
}

static int mlx4_num_eq_uar(struct mlx4_dev *dev)
{
	/*
	 * Each UAR holds 4 EQ doorbells.  To figure out how many UARs
	 * we need to map, take the difference of highest index and
	 * the lowest index we'll use and add 1.
	 */
	return (dev->caps.num_comp_vectors + 1 + dev->caps.reserved_eqs) / 4 -
		dev->caps.reserved_eqs / 4 + 1;
}

static void __iomem *mlx4_get_eq_uar(struct mlx4_dev *dev, struct mlx4_eq *eq)
{
	struct mlx4_priv *priv = mlx4_priv(dev);
	int index;

	index = eq->eqn / 4 - dev->caps.reserved_eqs / 4;

	if (!priv->eq_table.uar_map[index]) {
		priv->eq_table.uar_map[index] =
			ioremap(pci_resource_start(dev->pdev, 2) +
				((eq->eqn / 4) << PAGE_SHIFT),
				PAGE_SIZE);
		if (!priv->eq_table.uar_map[index]) {
			mlx4_err(dev, "Couldn't map EQ doorbell for EQN 0x%06x\n",
				 eq->eqn);
			return NULL;
		}
	}

	return priv->eq_table.uar_map[index] + 0x800 + 8 * (eq->eqn % 4);
}

static int mlx4_create_eq(struct mlx4_dev *dev, int nent,
			  u8 intr, struct mlx4_eq *eq)
{
	struct mlx4_priv *priv = mlx4_priv(dev);
	struct mlx4_cmd_mailbox *mailbox;
	struct mlx4_eq_context *eq_context;
	int npages;
	u64 *dma_list = NULL;
	dma_addr_t t;
	u64 mtt_addr;
	int err = -ENOMEM;
	int i;

	eq->dev   = dev;
	eq->nent  = roundup_pow_of_two(max(nent, 2));
	npages = PAGE_ALIGN(eq->nent * MLX4_EQ_ENTRY_SIZE) / PAGE_SIZE;

	eq->page_list = kmalloc(npages * sizeof *eq->page_list,
				GFP_KERNEL);
	if (!eq->page_list)
		goto err_out;

	for (i = 0; i < npages; ++i)
		eq->page_list[i].buf = NULL;

	dma_list = kmalloc(npages * sizeof *dma_list, GFP_KERNEL);
	if (!dma_list)
		goto err_out_free;

	mailbox = mlx4_alloc_cmd_mailbox(dev);
	if (IS_ERR(mailbox))
		goto err_out_free;
	eq_context = mailbox->buf;

	for (i = 0; i < npages; ++i) {
		eq->page_list[i].buf = dma_alloc_coherent(&dev->pdev->dev,
							  PAGE_SIZE, &t, GFP_KERNEL);
		if (!eq->page_list[i].buf)
			goto err_out_free_pages;

		dma_list[i] = t;
		eq->page_list[i].map = t;

		memset(eq->page_list[i].buf, 0, PAGE_SIZE);
	}

	eq->eqn = mlx4_bitmap_alloc(&priv->eq_table.bitmap);
	if (eq->eqn == -1)
		goto err_out_free_pages;

	eq->doorbell = mlx4_get_eq_uar(dev, eq);
	if (!eq->doorbell) {
		err = -ENOMEM;
		goto err_out_free_eq;
	}

	err = mlx4_mtt_init(dev, npages, PAGE_SHIFT, &eq->mtt);
	if (err)
		goto err_out_free_eq;

	err = mlx4_write_mtt(dev, &eq->mtt, 0, npages, dma_list);
	if (err)
		goto err_out_free_mtt;

	memset(eq_context, 0, sizeof *eq_context);
	eq_context->flags	  = cpu_to_be32(MLX4_EQ_STATUS_OK   |
						MLX4_EQ_STATE_ARMED);
	eq_context->log_eq_size	  = ilog2(eq->nent);
	eq_context->intr	  = intr;
	eq_context->log_page_size = PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT;

	mtt_addr = mlx4_mtt_addr(dev, &eq->mtt);
	eq_context->mtt_base_addr_h = mtt_addr >> 32;
	eq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);

	err = mlx4_SW2HW_EQ(dev, mailbox, eq->eqn);
	if (err) {
		mlx4_warn(dev, "SW2HW_EQ failed (%d)\n", err);
		goto err_out_free_mtt;
	}

	kfree(dma_list);
	mlx4_free_cmd_mailbox(dev, mailbox);

	eq->cons_index = 0;

	return err;

err_out_free_mtt:
	mlx4_mtt_cleanup(dev, &eq->mtt);

err_out_free_eq:
	mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn);

err_out_free_pages:
	for (i = 0; i < npages; ++i)
		if (eq->page_list[i].buf)
			dma_free_coherent(&dev->pdev->dev, PAGE_SIZE,
					  eq->page_list[i].buf,
					  eq->page_list[i].map);

	mlx4_free_cmd_mailbox(dev, mailbox);

err_out_free:
	kfree(eq->page_list);
	kfree(dma_list);

err_out:
	return err;
}

static void mlx4_free_eq(struct mlx4_dev *dev,
			 struct mlx4_eq *eq)
{
	struct mlx4_priv *priv = mlx4_priv(dev);
	struct mlx4_cmd_mailbox *mailbox;
	int err;
	int npages = PAGE_ALIGN(MLX4_EQ_ENTRY_SIZE * eq->nent) / PAGE_SIZE;
	int i;

	mailbox = mlx4_alloc_cmd_mailbox(dev);
	if (IS_ERR(mailbox))
		return;

	err = mlx4_HW2SW_EQ(dev, mailbox, eq->eqn);
	if (err)
		mlx4_warn(dev, "HW2SW_EQ failed (%d)\n", err);

	if (0) {
		mlx4_dbg(dev, "Dumping EQ context %02x:\n", eq->eqn);
		for (i = 0; i < sizeof (struct mlx4_eq_context) / 4; ++i) {
			if (i % 4 == 0)
				printk("[%02x] ", i * 4);
			printk(" %08x", be32_to_cpup(mailbox->buf + i * 4));
			if ((i + 1) % 4 == 0)
				printk("\n");
		}
	}

	mlx4_mtt_cleanup(dev, &eq->mtt);
	for (i = 0; i < npages; ++i)
		pci_free_consistent(dev->pdev, PAGE_SIZE,
				    eq->page_list[i].buf,
				    eq->page_list[i].map);

	kfree(eq->page_list);
	mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn);
	mlx4_free_cmd_mailbox(dev, mailbox);
}

static void mlx4_free_irqs(struct mlx4_dev *dev)
{
	struct mlx4_eq_table *eq_table = &mlx4_priv(dev)->eq_table;
	int i;

	if (eq_table->have_irq)
		free_irq(dev->pdev->irq, dev);
	for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
		if (eq_table->eq[i].have_irq) {
			free_irq(eq_table->eq[i].irq, eq_table->eq + i);
			eq_table->eq[i].have_irq = 0;
		}

	kfree(eq_table->irq_names);
}

static int mlx4_map_clr_int(struct mlx4_dev *dev)
{
	struct mlx4_priv *priv = mlx4_priv(dev);

	priv->clr_base = ioremap(pci_resource_start(dev->pdev, priv->fw.clr_int_bar) +
				 priv->fw.clr_int_base, MLX4_CLR_INT_SIZE);
	if (!priv->clr_base) {
		mlx4_err(dev, "Couldn't map interrupt clear register, aborting.\n");
		return -ENOMEM;
	}

	return 0;
}

static void mlx4_unmap_clr_int(struct mlx4_dev *dev)
{
	struct mlx4_priv *priv = mlx4_priv(dev);

	iounmap(priv->clr_base);
}

int mlx4_alloc_eq_table(struct mlx4_dev *dev)
{
	struct mlx4_priv *priv = mlx4_priv(dev);

	priv->eq_table.eq = kcalloc(dev->caps.num_eqs - dev->caps.reserved_eqs,
				    sizeof *priv->eq_table.eq, GFP_KERNEL);
	if (!priv->eq_table.eq)
		return -ENOMEM;

	return 0;
}

void mlx4_free_eq_table(struct mlx4_dev *dev)
{
	kfree(mlx4_priv(dev)->eq_table.eq);
}

int mlx4_init_eq_table(struct mlx4_dev *dev)
{
	struct mlx4_priv *priv = mlx4_priv(dev);
	int err;
	int i;

	priv->eq_table.uar_map = kcalloc(sizeof *priv->eq_table.uar_map,
					 mlx4_num_eq_uar(dev), GFP_KERNEL);
	if (!priv->eq_table.uar_map) {
		err = -ENOMEM;
		goto err_out_free;
	}

	err = mlx4_bitmap_init(&priv->eq_table.bitmap, dev->caps.num_eqs,
			       dev->caps.num_eqs - 1, dev->caps.reserved_eqs, 0);
	if (err)
		goto err_out_free;

	for (i = 0; i < mlx4_num_eq_uar(dev); ++i)
		priv->eq_table.uar_map[i] = NULL;

	err = mlx4_map_clr_int(dev);
	if (err)
		goto err_out_bitmap;

	priv->eq_table.clr_mask =
		swab32(1 << (priv->eq_table.inta_pin & 31));
	priv->eq_table.clr_int  = priv->clr_base +
		(priv->eq_table.inta_pin < 32 ? 4 : 0);

	priv->eq_table.irq_names = kmalloc(16 * dev->caps.num_comp_vectors, GFP_KERNEL);
	if (!priv->eq_table.irq_names) {
		err = -ENOMEM;
		goto err_out_bitmap;
	}

	for (i = 0; i < dev->caps.num_comp_vectors; ++i) {
		err = mlx4_create_eq(dev, dev->caps.num_cqs + MLX4_NUM_SPARE_EQE,
				     (dev->flags & MLX4_FLAG_MSI_X) ? i : 0,
				     &priv->eq_table.eq[i]);
		if (err) {
			--i;
			goto err_out_unmap;
		}
	}

	err = mlx4_create_eq(dev, MLX4_NUM_ASYNC_EQE + MLX4_NUM_SPARE_EQE,
			     (dev->flags & MLX4_FLAG_MSI_X) ? dev->caps.num_comp_vectors : 0,
			     &priv->eq_table.eq[dev->caps.num_comp_vectors]);
	if (err)
		goto err_out_comp;

	if (dev->flags & MLX4_FLAG_MSI_X) {
		static const char async_eq_name[] = "mlx4-async";
		const char *eq_name;

		for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) {
			if (i < dev->caps.num_comp_vectors) {
				snprintf(priv->eq_table.irq_names + i * 16, 16,
					 "mlx4-comp-%d", i);
				eq_name = priv->eq_table.irq_names + i * 16;
			} else
				eq_name = async_eq_name;

			err = request_irq(priv->eq_table.eq[i].irq,
					  mlx4_msi_x_interrupt, 0, eq_name,
					  priv->eq_table.eq + i);
			if (err)
				goto err_out_async;

			priv->eq_table.eq[i].have_irq = 1;
		}
	} else {
		err = request_irq(dev->pdev->irq, mlx4_interrupt,
				  IRQF_SHARED, DRV_NAME, dev);
		if (err)
			goto err_out_async;

		priv->eq_table.have_irq = 1;
	}

	err = mlx4_MAP_EQ(dev, MLX4_ASYNC_EVENT_MASK, 0,
			  priv->eq_table.eq[dev->caps.num_comp_vectors].eqn);
	if (err)
		mlx4_warn(dev, "MAP_EQ for async EQ %d failed (%d)\n",
			   priv->eq_table.eq[dev->caps.num_comp_vectors].eqn, err);

	for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
		eq_set_ci(&priv->eq_table.eq[i], 1);

	return 0;

err_out_async:
	mlx4_free_eq(dev, &priv->eq_table.eq[dev->caps.num_comp_vectors]);

err_out_comp:
	i = dev->caps.num_comp_vectors - 1;

err_out_unmap:
	while (i >= 0) {
		mlx4_free_eq(dev, &priv->eq_table.eq[i]);
		--i;
	}
	mlx4_unmap_clr_int(dev);
	mlx4_free_irqs(dev);

err_out_bitmap:
	mlx4_bitmap_cleanup(&priv->eq_table.bitmap);

err_out_free:
	kfree(priv->eq_table.uar_map);

	return err;
}

void mlx4_cleanup_eq_table(struct mlx4_dev *dev)
{
	struct mlx4_priv *priv = mlx4_priv(dev);
	int i;

	mlx4_MAP_EQ(dev, MLX4_ASYNC_EVENT_MASK, 1,
		    priv->eq_table.eq[dev->caps.num_comp_vectors].eqn);

	mlx4_free_irqs(dev);

	for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
		mlx4_free_eq(dev, &priv->eq_table.eq[i]);

	mlx4_unmap_clr_int(dev);

	for (i = 0; i < mlx4_num_eq_uar(dev); ++i)
		if (priv->eq_table.uar_map[i])
			iounmap(priv->eq_table.uar_map[i]);

	mlx4_bitmap_cleanup(&priv->eq_table.bitmap);

	kfree(priv->eq_table.uar_map);
}
Commit	Line	Data
225c7b1f	1	/*
51a379d0	2	* Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f RD	3	* Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
	4	*
	5	* This software is available to you under a choice of one of two
	6	* licenses. You may choose to be licensed under the terms of the GNU
	7	* General Public License (GPL) Version 2, available from the file
	8	* COPYING in the main directory of this source tree, or the
	9	* OpenIB.org BSD license below:
	10	*
	11	* Redistribution and use in source and binary forms, with or
	12	* without modification, are permitted provided that the following
	13	* conditions are met:
	14	*
	15	* - Redistributions of source code must retain the above
	16	* copyright notice, this list of conditions and the following
	17	* disclaimer.
	18	*
	19	* - Redistributions in binary form must reproduce the above
	20	* copyright notice, this list of conditions and the following
	21	* disclaimer in the documentation and/or other materials
	22	* provided with the distribution.
	23	*
	24	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	25	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	26	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	27	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	28	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	29	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	30	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	31	* SOFTWARE.
	32	*/
	33
225c7b1f	34	#include <linux/interrupt.h>
27ac792c	35	#include <linux/mm.h>
9cbe05c7	36	#include <linux/dma-mapping.h>
225c7b1f RD	37
	38	#include <linux/mlx4/cmd.h>
	39
	40	#include "mlx4.h"
	41	#include "fw.h"
	42
	43	enum {
	44	MLX4_NUM_ASYNC_EQE = 0x100,
	45	MLX4_NUM_SPARE_EQE = 0x80,
	46	MLX4_EQ_ENTRY_SIZE = 0x20
	47	};
	48
	49	/*
	50	* Must be packed because start is 64 bits but only aligned to 32 bits.
	51	*/
	52	struct mlx4_eq_context {
	53	__be32 flags;
	54	u16 reserved1[3];
	55	__be16 page_offset;
	56	u8 log_eq_size;
	57	u8 reserved2[4];
	58	u8 eq_period;
	59	u8 reserved3;
	60	u8 eq_max_count;
	61	u8 reserved4[3];
	62	u8 intr;
	63	u8 log_page_size;
	64	u8 reserved5[2];
	65	u8 mtt_base_addr_h;
	66	__be32 mtt_base_addr_l;
	67	u32 reserved6[2];
	68	__be32 consumer_index;
	69	__be32 producer_index;
	70	u32 reserved7[4];
	71	};
	72
	73	#define MLX4_EQ_STATUS_OK ( 0 << 28)
	74	#define MLX4_EQ_STATUS_WRITE_FAIL (10 << 28)
	75	#define MLX4_EQ_OWNER_SW ( 0 << 24)
	76	#define MLX4_EQ_OWNER_HW ( 1 << 24)
	77	#define MLX4_EQ_FLAG_EC ( 1 << 18)
	78	#define MLX4_EQ_FLAG_OI ( 1 << 17)
	79	#define MLX4_EQ_STATE_ARMED ( 9 << 8)
	80	#define MLX4_EQ_STATE_FIRED (10 << 8)
	81	#define MLX4_EQ_STATE_ALWAYS_ARMED (11 << 8)
	82
	83	#define MLX4_ASYNC_EVENT_MASK ((1ull << MLX4_EVENT_TYPE_PATH_MIG) \| \
	84	(1ull << MLX4_EVENT_TYPE_COMM_EST) \| \
	85	(1ull << MLX4_EVENT_TYPE_SQ_DRAINED) \| \
	86	(1ull << MLX4_EVENT_TYPE_CQ_ERROR) \| \
	87	(1ull << MLX4_EVENT_TYPE_WQ_CATAS_ERROR) \| \
	88	(1ull << MLX4_EVENT_TYPE_EEC_CATAS_ERROR) \| \
	89	(1ull << MLX4_EVENT_TYPE_PATH_MIG_FAILED) \| \
	90	(1ull << MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR) \| \
	91	(1ull << MLX4_EVENT_TYPE_WQ_ACCESS_ERROR) \| \
225c7b1f RD	92	(1ull << MLX4_EVENT_TYPE_PORT_CHANGE) \| \
	93	(1ull << MLX4_EVENT_TYPE_ECC_DETECT) \| \
	94	(1ull << MLX4_EVENT_TYPE_SRQ_CATAS_ERROR) \| \
	95	(1ull << MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE) \| \
	96	(1ull << MLX4_EVENT_TYPE_SRQ_LIMIT) \| \
	97	(1ull << MLX4_EVENT_TYPE_CMD))
225c7b1f RD	98
	99	struct mlx4_eqe {
	100	u8 reserved1;
	101	u8 type;
	102	u8 reserved2;
	103	u8 subtype;
	104	union {
	105	u32 raw[6];
	106	struct {
	107	__be32 cqn;
	108	} __attribute__((packed)) comp;
	109	struct {
	110	u16 reserved1;
	111	__be16 token;
	112	u32 reserved2;
	113	u8 reserved3[3];
	114	u8 status;
	115	__be64 out_param;
	116	} __attribute__((packed)) cmd;
	117	struct {
	118	__be32 qpn;
	119	} __attribute__((packed)) qp;
	120	struct {
	121	__be32 srqn;
	122	} __attribute__((packed)) srq;
	123	struct {
	124	__be32 cqn;
	125	u32 reserved1;
	126	u8 reserved2[3];
	127	u8 syndrome;
	128	} __attribute__((packed)) cq_err;
	129	struct {
	130	u32 reserved1[2];
	131	__be32 port;
	132	} __attribute__((packed)) port_change;
	133	} event;
	134	u8 reserved3[3];
	135	u8 owner;
	136	} __attribute__((packed));
	137
	138	static void eq_set_ci(struct mlx4_eq *eq, int req_not)
	139	{
	140	__raw_writel((__force u32) cpu_to_be32((eq->cons_index & 0xffffff) \|
	141	req_not << 31),
	142	eq->doorbell);
	143	/* We still want ordering, just not swabbing, so add a barrier */
	144	mb();
	145	}
	146
	147	static struct mlx4_eqe get_eqe(struct mlx4_eq eq, u32 entry)
	148	{
	149	unsigned long off = (entry & (eq->nent - 1)) * MLX4_EQ_ENTRY_SIZE;
	150	return eq->page_list[off / PAGE_SIZE].buf + off % PAGE_SIZE;
	151	}
	152
	153	static struct mlx4_eqe next_eqe_sw(struct mlx4_eq eq)
	154	{
	155	struct mlx4_eqe *eqe = get_eqe(eq, eq->cons_index);
	156	return !!(eqe->owner & 0x80) ^ !!(eq->cons_index & eq->nent) ? NULL : eqe;
	157	}
	158
	159	static int mlx4_eq_int(struct mlx4_dev dev, struct mlx4_eq eq)
	160	{
	161	struct mlx4_eqe *eqe;
162	int cqn;
163	int eqes_found = 0;
164	int set_ci = 0;
27bf91d6	165	int port;
225c7b1f RD	166
	167	while ((eqe = next_eqe_sw(eq))) {
	168	/*
	169	* Make sure we read EQ entry contents after we've
	170	* checked the ownership bit.
	171	*/
	172	rmb();
	173
	174	switch (eqe->type) {
	175	case MLX4_EVENT_TYPE_COMP:
	176	cqn = be32_to_cpu(eqe->event.comp.cqn) & 0xffffff;
	177	mlx4_cq_completion(dev, cqn);
	178	break;
	179
	180	case MLX4_EVENT_TYPE_PATH_MIG:
	181	case MLX4_EVENT_TYPE_COMM_EST:
	182	case MLX4_EVENT_TYPE_SQ_DRAINED:
	183	case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
	184	case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
	185	case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
	186	case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
	187	case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
	188	mlx4_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,
	189	eqe->type);
	190	break;
	191
	192	case MLX4_EVENT_TYPE_SRQ_LIMIT:
	193	case MLX4_EVENT_TYPE_SRQ_CATAS_ERROR:
	194	mlx4_srq_event(dev, be32_to_cpu(eqe->event.srq.srqn) & 0xffffff,
	195	eqe->type);
	196	break;
	197
	198	case MLX4_EVENT_TYPE_CMD:
	199	mlx4_cmd_event(dev,
	200	be16_to_cpu(eqe->event.cmd.token),
	201	eqe->event.cmd.status,
	202	be64_to_cpu(eqe->event.cmd.out_param));
	203	break;
	204
	205	case MLX4_EVENT_TYPE_PORT_CHANGE:
27bf91d6 YP	206	port = be32_to_cpu(eqe->event.port_change.port) >> 28;
	207	if (eqe->subtype == MLX4_PORT_CHANGE_SUBTYPE_DOWN) {
	208	mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_DOWN,
	209	port);
	210	mlx4_priv(dev)->sense.do_sense_port[port] = 1;
	211	} else {
	212	mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_UP,
	213	port);
	214	mlx4_priv(dev)->sense.do_sense_port[port] = 0;
	215	}
225c7b1f RD	216	break;
	217
	218	case MLX4_EVENT_TYPE_CQ_ERROR:
	219	mlx4_warn(dev, "CQ %s on CQN %06x\n",
	220	eqe->event.cq_err.syndrome == 1 ?
	221	"overrun" : "access violation",
	222	be32_to_cpu(eqe->event.cq_err.cqn) & 0xffffff);
	223	mlx4_cq_event(dev, be32_to_cpu(eqe->event.cq_err.cqn),
	224	eqe->type);
	225	break;
	226
	227	case MLX4_EVENT_TYPE_EQ_OVERFLOW:
	228	mlx4_warn(dev, "EQ overrun on EQN %d\n", eq->eqn);
	229	break;
	230
	231	case MLX4_EVENT_TYPE_EEC_CATAS_ERROR:
	232	case MLX4_EVENT_TYPE_ECC_DETECT:
	233	default:
	234	mlx4_warn(dev, "Unhandled event %02x(%02x) on EQ %d at index %u\n",
	235	eqe->type, eqe->subtype, eq->eqn, eq->cons_index);
	236	break;
	237	};
	238
	239	++eq->cons_index;
	240	eqes_found = 1;
	241	++set_ci;
	242
	243	/*
	244	* The HCA will think the queue has overflowed if we
	245	* don't tell it we've been processing events. We
	246	* create our EQs with MLX4_NUM_SPARE_EQE extra
	247	* entries, so we must update our consumer index at
	248	* least that often.
	249	*/
	250	if (unlikely(set_ci >= MLX4_NUM_SPARE_EQE)) {
225c7b1f RD	251	eq_set_ci(eq, 0);
	252	set_ci = 0;
	253	}
	254	}
	255
	256	eq_set_ci(eq, 1);
	257
	258	return eqes_found;
	259	}
	260
	261	static irqreturn_t mlx4_interrupt(int irq, void *dev_ptr)
	262	{
	263	struct mlx4_dev *dev = dev_ptr;
	264	struct mlx4_priv *priv = mlx4_priv(dev);
	265	int work = 0;
	266	int i;
	267
	268	writel(priv->eq_table.clr_mask, priv->eq_table.clr_int);
	269
b8dd786f	270	for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
225c7b1f RD	271	work \|= mlx4_eq_int(dev, &priv->eq_table.eq[i]);
	272
	273	return IRQ_RETVAL(work);
	274	}
	275
	276	static irqreturn_t mlx4_msi_x_interrupt(int irq, void *eq_ptr)
	277	{
	278	struct mlx4_eq *eq = eq_ptr;
	279	struct mlx4_dev *dev = eq->dev;
	280
	281	mlx4_eq_int(dev, eq);
	282
	283	/* MSI-X vectors always belong to us */
	284	return IRQ_HANDLED;
	285	}
	286
225c7b1f RD	287	static int mlx4_MAP_EQ(struct mlx4_dev *dev, u64 event_mask, int unmap,
	288	int eq_num)
	289	{
	290	return mlx4_cmd(dev, event_mask, (unmap << 31) \| eq_num,
	291	0, MLX4_CMD_MAP_EQ, MLX4_CMD_TIME_CLASS_B);
	292	}
	293
	294	static int mlx4_SW2HW_EQ(struct mlx4_dev dev, struct mlx4_cmd_mailbox mailbox,
	295	int eq_num)
	296	{
	297	return mlx4_cmd(dev, mailbox->dma, eq_num, 0, MLX4_CMD_SW2HW_EQ,
	298	MLX4_CMD_TIME_CLASS_A);
	299	}
	300
	301	static int mlx4_HW2SW_EQ(struct mlx4_dev dev, struct mlx4_cmd_mailbox mailbox,
	302	int eq_num)
	303	{
	304	return mlx4_cmd_box(dev, 0, mailbox->dma, eq_num, 0, MLX4_CMD_HW2SW_EQ,
	305	MLX4_CMD_TIME_CLASS_A);
	306	}
	307
b8dd786f YP	308	static int mlx4_num_eq_uar(struct mlx4_dev *dev)
	309	{
	310	/*
	311	* Each UAR holds 4 EQ doorbells. To figure out how many UARs
	312	* we need to map, take the difference of highest index and
	313	* the lowest index we'll use and add 1.
	314	*/
	315	return (dev->caps.num_comp_vectors + 1 + dev->caps.reserved_eqs) / 4 -
	316	dev->caps.reserved_eqs / 4 + 1;
	317	}
	318
3d73c288	319	static void __iomem mlx4_get_eq_uar(struct mlx4_dev dev, struct mlx4_eq *eq)
225c7b1f RD	320	{
	321	struct mlx4_priv *priv = mlx4_priv(dev);
	322	int index;
	323
	324	index = eq->eqn / 4 - dev->caps.reserved_eqs / 4;
	325
	326	if (!priv->eq_table.uar_map[index]) {
	327	priv->eq_table.uar_map[index] =
	328	ioremap(pci_resource_start(dev->pdev, 2) +
	329	((eq->eqn / 4) << PAGE_SHIFT),
	330	PAGE_SIZE);
	331	if (!priv->eq_table.uar_map[index]) {
	332	mlx4_err(dev, "Couldn't map EQ doorbell for EQN 0x%06x\n",
	333	eq->eqn);
	334	return NULL;
	335	}
	336	}
	337
	338	return priv->eq_table.uar_map[index] + 0x800 + 8 * (eq->eqn % 4);
	339	}
	340
3d73c288 RD	341	static int mlx4_create_eq(struct mlx4_dev *dev, int nent,
3d73c288 RD	342	u8 intr, struct mlx4_eq *eq)
225c7b1f RD	343	{
	344	struct mlx4_priv *priv = mlx4_priv(dev);
	345	struct mlx4_cmd_mailbox *mailbox;
	346	struct mlx4_eq_context *eq_context;
	347	int npages;
	348	u64 *dma_list = NULL;
	349	dma_addr_t t;
	350	u64 mtt_addr;
	351	int err = -ENOMEM;
	352	int i;
	353
	354	eq->dev = dev;
	355	eq->nent = roundup_pow_of_two(max(nent, 2));
	356	npages = PAGE_ALIGN(eq->nent * MLX4_EQ_ENTRY_SIZE) / PAGE_SIZE;
	357
	358	eq->page_list = kmalloc(npages * sizeof *eq->page_list,
	359	GFP_KERNEL);
	360	if (!eq->page_list)
	361	goto err_out;
	362
	363	for (i = 0; i < npages; ++i)
	364	eq->page_list[i].buf = NULL;
	365
	366	dma_list = kmalloc(npages * sizeof *dma_list, GFP_KERNEL);
	367	if (!dma_list)
	368	goto err_out_free;
	369
	370	mailbox = mlx4_alloc_cmd_mailbox(dev);
	371	if (IS_ERR(mailbox))
	372	goto err_out_free;
	373	eq_context = mailbox->buf;
	374
	375	for (i = 0; i < npages; ++i) {
	376	eq->page_list[i].buf = dma_alloc_coherent(&dev->pdev->dev,
	377	PAGE_SIZE, &t, GFP_KERNEL);
	378	if (!eq->page_list[i].buf)
	379	goto err_out_free_pages;
	380
	381	dma_list[i] = t;
	382	eq->page_list[i].map = t;
	383
	384	memset(eq->page_list[i].buf, 0, PAGE_SIZE);
	385	}
	386
	387	eq->eqn = mlx4_bitmap_alloc(&priv->eq_table.bitmap);
	388	if (eq->eqn == -1)
	389	goto err_out_free_pages;
	390
	391	eq->doorbell = mlx4_get_eq_uar(dev, eq);
	392	if (!eq->doorbell) {
	393	err = -ENOMEM;
	394	goto err_out_free_eq;
	395	}
	396
	397	err = mlx4_mtt_init(dev, npages, PAGE_SHIFT, &eq->mtt);
	398	if (err)
	399	goto err_out_free_eq;
	400
	401	err = mlx4_write_mtt(dev, &eq->mtt, 0, npages, dma_list);
	402	if (err)
	403	goto err_out_free_mtt;
	404
	405	memset(eq_context, 0, sizeof *eq_context);
	406	eq_context->flags = cpu_to_be32(MLX4_EQ_STATUS_OK \|
407	MLX4_EQ_STATE_ARMED);
408	eq_context->log_eq_size = ilog2(eq->nent);
409	eq_context->intr = intr;
410	eq_context->log_page_size = PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT;
411
412	mtt_addr = mlx4_mtt_addr(dev, &eq->mtt);
413	eq_context->mtt_base_addr_h = mtt_addr >> 32;
414	eq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);
415
416	err = mlx4_SW2HW_EQ(dev, mailbox, eq->eqn);
417	if (err) {
418	mlx4_warn(dev, "SW2HW_EQ failed (%d)\n", err);
419	goto err_out_free_mtt;
420	}
421
422	kfree(dma_list);
423	mlx4_free_cmd_mailbox(dev, mailbox);
424
425	eq->cons_index = 0;
426
427	return err;
428
429	err_out_free_mtt:
430	mlx4_mtt_cleanup(dev, &eq->mtt);
431
432	err_out_free_eq:
433	mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn);
434
435	err_out_free_pages:
436	for (i = 0; i < npages; ++i)
437	if (eq->page_list[i].buf)
438	dma_free_coherent(&dev->pdev->dev, PAGE_SIZE,
439	eq->page_list[i].buf,
440	eq->page_list[i].map);
441
442	mlx4_free_cmd_mailbox(dev, mailbox);
443
444	err_out_free:
445	kfree(eq->page_list);
446	kfree(dma_list);
447
448	err_out:
449	return err;
450	}
451
452	static void mlx4_free_eq(struct mlx4_dev *dev,
453	struct mlx4_eq *eq)
454	{
455	struct mlx4_priv *priv = mlx4_priv(dev);
456	struct mlx4_cmd_mailbox *mailbox;
457	int err;
458	int npages = PAGE_ALIGN(MLX4_EQ_ENTRY_SIZE * eq->nent) / PAGE_SIZE;
459	int i;
460
461	mailbox = mlx4_alloc_cmd_mailbox(dev);
462	if (IS_ERR(mailbox))
463	return;
464
465	err = mlx4_HW2SW_EQ(dev, mailbox, eq->eqn);
466	if (err)
467	mlx4_warn(dev, "HW2SW_EQ failed (%d)\n", err);
468
469	if (0) {
470	mlx4_dbg(dev, "Dumping EQ context %02x:\n", eq->eqn);
471	for (i = 0; i < sizeof (struct mlx4_eq_context) / 4; ++i) {
472	if (i % 4 == 0)
473	printk("[%02x] ", i * 4);
474	printk(" %08x", be32_to_cpup(mailbox->buf + i * 4));
475	if ((i + 1) % 4 == 0)
476	printk("\n");
477	}
478	}
479
480	mlx4_mtt_cleanup(dev, &eq->mtt);
481	for (i = 0; i < npages; ++i)
482	pci_free_consistent(dev->pdev, PAGE_SIZE,
483	eq->page_list[i].buf,
484	eq->page_list[i].map);
485
486	kfree(eq->page_list);
487	mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn);
488	mlx4_free_cmd_mailbox(dev, mailbox);
489	}
490
491	static void mlx4_free_irqs(struct mlx4_dev *dev)
492	{
493	struct mlx4_eq_table *eq_table = &mlx4_priv(dev)->eq_table;
494	int i;
495
496	if (eq_table->have_irq)
497	free_irq(dev->pdev->irq, dev);
b8dd786f	498	for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
d1fdf24b	499	if (eq_table->eq[i].have_irq) {
225c7b1f	500	free_irq(eq_table->eq[i].irq, eq_table->eq + i);
d1fdf24b RD	501	eq_table->eq[i].have_irq = 0;
d1fdf24b RD	502	}
b8dd786f YP	503
b8dd786f YP	504	kfree(eq_table->irq_names);
225c7b1f RD	505	}
225c7b1f RD	506
3d73c288	507	static int mlx4_map_clr_int(struct mlx4_dev *dev)
225c7b1f RD	508	{
	509	struct mlx4_priv *priv = mlx4_priv(dev);
	510
	511	priv->clr_base = ioremap(pci_resource_start(dev->pdev, priv->fw.clr_int_bar) +
	512	priv->fw.clr_int_base, MLX4_CLR_INT_SIZE);
	513	if (!priv->clr_base) {
	514	mlx4_err(dev, "Couldn't map interrupt clear register, aborting.\n");
	515	return -ENOMEM;
	516	}
	517
	518	return 0;
	519	}
	520
	521	static void mlx4_unmap_clr_int(struct mlx4_dev *dev)
	522	{
	523	struct mlx4_priv *priv = mlx4_priv(dev);
	524
	525	iounmap(priv->clr_base);
	526	}
	527
b8dd786f YP	528	int mlx4_alloc_eq_table(struct mlx4_dev *dev)
	529	{
	530	struct mlx4_priv *priv = mlx4_priv(dev);
	531
	532	priv->eq_table.eq = kcalloc(dev->caps.num_eqs - dev->caps.reserved_eqs,
	533	sizeof *priv->eq_table.eq, GFP_KERNEL);
	534	if (!priv->eq_table.eq)
	535	return -ENOMEM;
	536
	537	return 0;
	538	}
	539
	540	void mlx4_free_eq_table(struct mlx4_dev *dev)
	541	{
	542	kfree(mlx4_priv(dev)->eq_table.eq);
	543	}
	544
3d73c288	545	int mlx4_init_eq_table(struct mlx4_dev *dev)
225c7b1f RD	546	{
	547	struct mlx4_priv *priv = mlx4_priv(dev);
	548	int err;
	549	int i;
	550
b8dd786f YP	551	priv->eq_table.uar_map = kcalloc(sizeof *priv->eq_table.uar_map,
	552	mlx4_num_eq_uar(dev), GFP_KERNEL);
	553	if (!priv->eq_table.uar_map) {
	554	err = -ENOMEM;
	555	goto err_out_free;
	556	}
	557
225c7b1f	558	err = mlx4_bitmap_init(&priv->eq_table.bitmap, dev->caps.num_eqs,
93fc9e1b	559	dev->caps.num_eqs - 1, dev->caps.reserved_eqs, 0);
225c7b1f	560	if (err)
b8dd786f	561	goto err_out_free;
225c7b1f	562
b8dd786f	563	for (i = 0; i < mlx4_num_eq_uar(dev); ++i)
225c7b1f RD	564	priv->eq_table.uar_map[i] = NULL;
	565
	566	err = mlx4_map_clr_int(dev);
	567	if (err)
b8dd786f	568	goto err_out_bitmap;
225c7b1f RD	569
	570	priv->eq_table.clr_mask =
	571	swab32(1 << (priv->eq_table.inta_pin & 31));
	572	priv->eq_table.clr_int = priv->clr_base +
	573	(priv->eq_table.inta_pin < 32 ? 4 : 0);
	574
b8dd786f YP	575	priv->eq_table.irq_names = kmalloc(16 * dev->caps.num_comp_vectors, GFP_KERNEL);
	576	if (!priv->eq_table.irq_names) {
	577	err = -ENOMEM;
	578	goto err_out_bitmap;
	579	}
	580
	581	for (i = 0; i < dev->caps.num_comp_vectors; ++i) {
	582	err = mlx4_create_eq(dev, dev->caps.num_cqs + MLX4_NUM_SPARE_EQE,
	583	(dev->flags & MLX4_FLAG_MSI_X) ? i : 0,
	584	&priv->eq_table.eq[i]);
a5b19b63 YP	585	if (err) {
a5b19b63 YP	586	--i;
b8dd786f	587	goto err_out_unmap;
a5b19b63	588	}
b8dd786f	589	}
225c7b1f RD	590
225c7b1f RD	591	err = mlx4_create_eq(dev, MLX4_NUM_ASYNC_EQE + MLX4_NUM_SPARE_EQE,
b8dd786f YP	592	(dev->flags & MLX4_FLAG_MSI_X) ? dev->caps.num_comp_vectors : 0,
b8dd786f YP	593	&priv->eq_table.eq[dev->caps.num_comp_vectors]);
225c7b1f RD	594	if (err)
	595	goto err_out_comp;
	596
	597	if (dev->flags & MLX4_FLAG_MSI_X) {
b8dd786f YP	598	static const char async_eq_name[] = "mlx4-async";
	599	const char *eq_name;
	600
	601	for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) {
	602	if (i < dev->caps.num_comp_vectors) {
	603	snprintf(priv->eq_table.irq_names + i * 16, 16,
	604	"mlx4-comp-%d", i);
	605	eq_name = priv->eq_table.irq_names + i * 16;
	606	} else
	607	eq_name = async_eq_name;
225c7b1f	608
225c7b1f	609	err = request_irq(priv->eq_table.eq[i].irq,
b8dd786f YP	610	mlx4_msi_x_interrupt, 0, eq_name,
b8dd786f YP	611	priv->eq_table.eq + i);
225c7b1f	612	if (err)
ee49bd93	613	goto err_out_async;
225c7b1f RD	614
	615	priv->eq_table.eq[i].have_irq = 1;
	616	}
225c7b1f RD	617	} else {
225c7b1f RD	618	err = request_irq(dev->pdev->irq, mlx4_interrupt,
4093785d	619	IRQF_SHARED, DRV_NAME, dev);
225c7b1f RD	620	if (err)
	621	goto err_out_async;
	622
	623	priv->eq_table.have_irq = 1;
	624	}
	625
	626	err = mlx4_MAP_EQ(dev, MLX4_ASYNC_EVENT_MASK, 0,
b8dd786f	627	priv->eq_table.eq[dev->caps.num_comp_vectors].eqn);
225c7b1f RD	628	if (err)
225c7b1f RD	629	mlx4_warn(dev, "MAP_EQ for async EQ %d failed (%d)\n",
b8dd786f	630	priv->eq_table.eq[dev->caps.num_comp_vectors].eqn, err);
225c7b1f	631
b8dd786f	632	for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
225c7b1f RD	633	eq_set_ci(&priv->eq_table.eq[i], 1);
225c7b1f RD	634
225c7b1f RD	635	return 0;
225c7b1f RD	636
225c7b1f	637	err_out_async:
b8dd786f	638	mlx4_free_eq(dev, &priv->eq_table.eq[dev->caps.num_comp_vectors]);
225c7b1f RD	639
225c7b1f RD	640	err_out_comp:
b8dd786f	641	i = dev->caps.num_comp_vectors - 1;
225c7b1f RD	642
225c7b1f RD	643	err_out_unmap:
b8dd786f YP	644	while (i >= 0) {
	645	mlx4_free_eq(dev, &priv->eq_table.eq[i]);
	646	--i;
	647	}
225c7b1f RD	648	mlx4_unmap_clr_int(dev);
	649	mlx4_free_irqs(dev);
	650
b8dd786f	651	err_out_bitmap:
225c7b1f	652	mlx4_bitmap_cleanup(&priv->eq_table.bitmap);
b8dd786f YP	653
	654	err_out_free:
	655	kfree(priv->eq_table.uar_map);
	656
225c7b1f RD	657	return err;
	658	}
	659
	660	void mlx4_cleanup_eq_table(struct mlx4_dev *dev)
	661	{
	662	struct mlx4_priv *priv = mlx4_priv(dev);
	663	int i;
	664
225c7b1f	665	mlx4_MAP_EQ(dev, MLX4_ASYNC_EVENT_MASK, 1,
b8dd786f	666	priv->eq_table.eq[dev->caps.num_comp_vectors].eqn);
225c7b1f RD	667
	668	mlx4_free_irqs(dev);
	669
b8dd786f	670	for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
225c7b1f	671	mlx4_free_eq(dev, &priv->eq_table.eq[i]);
225c7b1f RD	672
	673	mlx4_unmap_clr_int(dev);
	674
b8dd786f	675	for (i = 0; i < mlx4_num_eq_uar(dev); ++i)
225c7b1f RD	676	if (priv->eq_table.uar_map[i])
	677	iounmap(priv->eq_table.uar_map[i]);
	678
	679	mlx4_bitmap_cleanup(&priv->eq_table.bitmap);
b8dd786f YP	680
b8dd786f YP	681	kfree(priv->eq_table.uar_map);
225c7b1f	682	}